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[yosys.git] / frontends / verilog / verilog_frontend.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * The Verilog frontend.
21 *
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
26 *
27 */
28
29 #include "verilog_frontend.h"
30 #include "kernel/yosys.h"
31 #include "libs/sha1/sha1.h"
32 #include <stdarg.h>
33
34 YOSYS_NAMESPACE_BEGIN
35 using namespace VERILOG_FRONTEND;
36
37 // use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL
38
39 static std::vector<std::string> verilog_defaults;
40 static std::list<std::vector<std::string>> verilog_defaults_stack;
41
42 static void error_on_dpi_function(AST::AstNode *node)
43 {
44 if (node->type == AST::AST_DPI_FUNCTION)
45 log_file_error(node->filename, node->linenum, "Found DPI function %s.\n", node->str.c_str());
46 for (auto child : node->children)
47 error_on_dpi_function(child);
48 }
49
50 struct VerilogFrontend : public Frontend {
51 VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
52 void help() YS_OVERRIDE
53 {
54 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
55 log("\n");
56 log(" read_verilog [options] [filename]\n");
57 log("\n");
58 log("Load modules from a Verilog file to the current design. A large subset of\n");
59 log("Verilog-2005 is supported.\n");
60 log("\n");
61 log(" -sv\n");
62 log(" enable support for SystemVerilog features. (only a small subset\n");
63 log(" of SystemVerilog is supported)\n");
64 log("\n");
65 log(" -formal\n");
66 log(" enable support for SystemVerilog assertions and some Yosys extensions\n");
67 log(" replace the implicit -D SYNTHESIS with -D FORMAL\n");
68 log("\n");
69 log(" -noassert\n");
70 log(" ignore assert() statements\n");
71 log("\n");
72 log(" -noassume\n");
73 log(" ignore assume() statements\n");
74 log("\n");
75 log(" -norestrict\n");
76 log(" ignore restrict() statements\n");
77 log("\n");
78 log(" -assume-asserts\n");
79 log(" treat all assert() statements like assume() statements\n");
80 log("\n");
81 log(" -assert-assumes\n");
82 log(" treat all assume() statements like assert() statements\n");
83 log("\n");
84 log(" -debug\n");
85 log(" alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug\n");
86 log("\n");
87 log(" -dump_ast1\n");
88 log(" dump abstract syntax tree (before simplification)\n");
89 log("\n");
90 log(" -dump_ast2\n");
91 log(" dump abstract syntax tree (after simplification)\n");
92 log("\n");
93 log(" -no_dump_ptr\n");
94 log(" do not include hex memory addresses in dump (easier to diff dumps)\n");
95 log("\n");
96 log(" -dump_vlog1\n");
97 log(" dump ast as Verilog code (before simplification)\n");
98 log("\n");
99 log(" -dump_vlog2\n");
100 log(" dump ast as Verilog code (after simplification)\n");
101 log("\n");
102 log(" -dump_rtlil\n");
103 log(" dump generated RTLIL netlist\n");
104 log("\n");
105 log(" -yydebug\n");
106 log(" enable parser debug output\n");
107 log("\n");
108 log(" -nolatches\n");
109 log(" usually latches are synthesized into logic loops\n");
110 log(" this option prohibits this and sets the output to 'x'\n");
111 log(" in what would be the latches hold condition\n");
112 log("\n");
113 log(" this behavior can also be achieved by setting the\n");
114 log(" 'nolatches' attribute on the respective module or\n");
115 log(" always block.\n");
116 log("\n");
117 log(" -nomem2reg\n");
118 log(" under certain conditions memories are converted to registers\n");
119 log(" early during simplification to ensure correct handling of\n");
120 log(" complex corner cases. this option disables this behavior.\n");
121 log("\n");
122 log(" this can also be achieved by setting the 'nomem2reg'\n");
123 log(" attribute on the respective module or register.\n");
124 log("\n");
125 log(" This is potentially dangerous. Usually the front-end has good\n");
126 log(" reasons for converting an array to a list of registers.\n");
127 log(" Prohibiting this step will likely result in incorrect synthesis\n");
128 log(" results.\n");
129 log("\n");
130 log(" -mem2reg\n");
131 log(" always convert memories to registers. this can also be\n");
132 log(" achieved by setting the 'mem2reg' attribute on the respective\n");
133 log(" module or register.\n");
134 log("\n");
135 log(" -nomeminit\n");
136 log(" do not infer $meminit cells and instead convert initialized\n");
137 log(" memories to registers directly in the front-end.\n");
138 log("\n");
139 log(" -ppdump\n");
140 log(" dump Verilog code after pre-processor\n");
141 log("\n");
142 log(" -nopp\n");
143 log(" do not run the pre-processor\n");
144 log("\n");
145 log(" -nodpi\n");
146 log(" disable DPI-C support\n");
147 log("\n");
148 log(" -noblackbox\n");
149 log(" do not automatically add a (* blackbox *) attribute to an\n");
150 log(" empty module.\n");
151 log("\n");
152 log(" -lib\n");
153 log(" only create empty blackbox modules. This implies -DBLACKBOX.\n");
154 log(" modules with the (* whitebox *) attribute will be preserved.\n");
155 log(" (* lib_whitebox *) will be treated like (* whitebox *).\n");
156 log("\n");
157 log(" -nowb\n");
158 log(" delete (* whitebox *) and (* lib_whitebox *) attributes from\n");
159 log(" all modules.\n");
160 log("\n");
161 log(" -specify\n");
162 log(" parse and import specify blocks\n");
163 log("\n");
164 log(" -noopt\n");
165 log(" don't perform basic optimizations (such as const folding) in the\n");
166 log(" high-level front-end.\n");
167 log("\n");
168 log(" -icells\n");
169 log(" interpret cell types starting with '$' as internal cell types\n");
170 log("\n");
171 log(" -nooverwrite\n");
172 log(" ignore re-definitions of modules. (the default behavior is to\n");
173 log(" create an error message if the existing module is not a black box\n");
174 log(" module, and overwrite the existing module otherwise.)\n");
175 log("\n");
176 log(" -overwrite\n");
177 log(" overwrite existing modules with the same name\n");
178 log("\n");
179 log(" -defer\n");
180 log(" only read the abstract syntax tree and defer actual compilation\n");
181 log(" to a later 'hierarchy' command. Useful in cases where the default\n");
182 log(" parameters of modules yield invalid or not synthesizable code.\n");
183 log("\n");
184 log(" -noautowire\n");
185 log(" make the default of `default_nettype be \"none\" instead of \"wire\".\n");
186 log("\n");
187 log(" -setattr <attribute_name>\n");
188 log(" set the specified attribute (to the value 1) on all loaded modules\n");
189 log("\n");
190 log(" -Dname[=definition]\n");
191 log(" define the preprocessor symbol 'name' and set its optional value\n");
192 log(" 'definition'\n");
193 log("\n");
194 log(" -Idir\n");
195 log(" add 'dir' to the directories which are used when searching include\n");
196 log(" files\n");
197 log("\n");
198 log("The command 'verilog_defaults' can be used to register default options for\n");
199 log("subsequent calls to 'read_verilog'.\n");
200 log("\n");
201 log("Note that the Verilog frontend does a pretty good job of processing valid\n");
202 log("verilog input, but has not very good error reporting. It generally is\n");
203 log("recommended to use a simulator (for example Icarus Verilog) for checking\n");
204 log("the syntax of the code, rather than to rely on read_verilog for that.\n");
205 log("\n");
206 log("Depending on if read_verilog is run in -formal mode, either the macro\n");
207 log("SYNTHESIS or FORMAL is defined automatically. In addition, read_verilog\n");
208 log("always defines the macro YOSYS.\n");
209 log("\n");
210 log("See the Yosys README file for a list of non-standard Verilog features\n");
211 log("supported by the Yosys Verilog front-end.\n");
212 log("\n");
213 }
214 void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
215 {
216 bool flag_dump_ast1 = false;
217 bool flag_dump_ast2 = false;
218 bool flag_no_dump_ptr = false;
219 bool flag_dump_vlog1 = false;
220 bool flag_dump_vlog2 = false;
221 bool flag_dump_rtlil = false;
222 bool flag_nolatches = false;
223 bool flag_nomeminit = false;
224 bool flag_nomem2reg = false;
225 bool flag_mem2reg = false;
226 bool flag_ppdump = false;
227 bool flag_nopp = false;
228 bool flag_nodpi = false;
229 bool flag_noopt = false;
230 bool flag_icells = false;
231 bool flag_nooverwrite = false;
232 bool flag_overwrite = false;
233 bool flag_defer = false;
234 bool flag_noblackbox = false;
235 bool flag_nowb = false;
236 std::map<std::string, std::string> defines_map;
237 std::list<std::string> include_dirs;
238 std::list<std::string> attributes;
239
240 frontend_verilog_yydebug = false;
241 sv_mode = false;
242 formal_mode = false;
243 norestrict_mode = false;
244 assume_asserts_mode = false;
245 lib_mode = false;
246 specify_mode = false;
247 default_nettype_wire = true;
248
249 args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());
250
251 size_t argidx;
252 for (argidx = 1; argidx < args.size(); argidx++) {
253 std::string arg = args[argidx];
254 if (arg == "-sv") {
255 sv_mode = true;
256 continue;
257 }
258 if (arg == "-formal") {
259 formal_mode = true;
260 continue;
261 }
262 if (arg == "-noassert") {
263 noassert_mode = true;
264 continue;
265 }
266 if (arg == "-noassume") {
267 noassume_mode = true;
268 continue;
269 }
270 if (arg == "-norestrict") {
271 norestrict_mode = true;
272 continue;
273 }
274 if (arg == "-assume-asserts") {
275 assume_asserts_mode = true;
276 continue;
277 }
278 if (arg == "-assert-assumes") {
279 assert_assumes_mode = true;
280 continue;
281 }
282 if (arg == "-debug") {
283 flag_dump_ast1 = true;
284 flag_dump_ast2 = true;
285 flag_dump_vlog1 = true;
286 flag_dump_vlog2 = true;
287 frontend_verilog_yydebug = true;
288 continue;
289 }
290 if (arg == "-dump_ast1") {
291 flag_dump_ast1 = true;
292 continue;
293 }
294 if (arg == "-dump_ast2") {
295 flag_dump_ast2 = true;
296 continue;
297 }
298 if (arg == "-no_dump_ptr") {
299 flag_no_dump_ptr = true;
300 continue;
301 }
302 if (arg == "-dump_vlog1") {
303 flag_dump_vlog1 = true;
304 continue;
305 }
306 if (arg == "-dump_vlog2") {
307 flag_dump_vlog2 = true;
308 continue;
309 }
310 if (arg == "-dump_rtlil") {
311 flag_dump_rtlil = true;
312 continue;
313 }
314 if (arg == "-yydebug") {
315 frontend_verilog_yydebug = true;
316 continue;
317 }
318 if (arg == "-nolatches") {
319 flag_nolatches = true;
320 continue;
321 }
322 if (arg == "-nomeminit") {
323 flag_nomeminit = true;
324 continue;
325 }
326 if (arg == "-nomem2reg") {
327 flag_nomem2reg = true;
328 continue;
329 }
330 if (arg == "-mem2reg") {
331 flag_mem2reg = true;
332 continue;
333 }
334 if (arg == "-ppdump") {
335 flag_ppdump = true;
336 continue;
337 }
338 if (arg == "-nopp") {
339 flag_nopp = true;
340 continue;
341 }
342 if (arg == "-nodpi") {
343 flag_nodpi = true;
344 continue;
345 }
346 if (arg == "-noblackbox") {
347 flag_noblackbox = true;
348 continue;
349 }
350 if (arg == "-lib") {
351 lib_mode = true;
352 defines_map["BLACKBOX"] = string();
353 continue;
354 }
355 if (arg == "-nowb") {
356 flag_nowb = true;
357 continue;
358 }
359 if (arg == "-specify") {
360 specify_mode = true;
361 continue;
362 }
363 if (arg == "-noopt") {
364 flag_noopt = true;
365 continue;
366 }
367 if (arg == "-icells") {
368 flag_icells = true;
369 continue;
370 }
371 if (arg == "-ignore_redef" || arg == "-nooverwrite") {
372 flag_nooverwrite = true;
373 flag_overwrite = false;
374 continue;
375 }
376 if (arg == "-overwrite") {
377 flag_nooverwrite = false;
378 flag_overwrite = true;
379 continue;
380 }
381 if (arg == "-defer") {
382 flag_defer = true;
383 continue;
384 }
385 if (arg == "-noautowire") {
386 default_nettype_wire = false;
387 continue;
388 }
389 if (arg == "-setattr" && argidx+1 < args.size()) {
390 attributes.push_back(RTLIL::escape_id(args[++argidx]));
391 continue;
392 }
393 if (arg == "-D" && argidx+1 < args.size()) {
394 std::string name = args[++argidx], value;
395 size_t equal = name.find('=');
396 if (equal != std::string::npos) {
397 value = name.substr(equal+1);
398 name = name.substr(0, equal);
399 }
400 defines_map[name] = value;
401 continue;
402 }
403 if (arg.compare(0, 2, "-D") == 0) {
404 size_t equal = arg.find('=', 2);
405 std::string name = arg.substr(2, equal-2);
406 std::string value;
407 if (equal != std::string::npos)
408 value = arg.substr(equal+1);
409 defines_map[name] = value;
410 continue;
411 }
412 if (arg == "-I" && argidx+1 < args.size()) {
413 include_dirs.push_back(args[++argidx]);
414 continue;
415 }
416 if (arg.compare(0, 2, "-I") == 0) {
417 include_dirs.push_back(arg.substr(2));
418 continue;
419 }
420 break;
421 }
422 extra_args(f, filename, args, argidx);
423
424 log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str());
425
426 log("Parsing %s%s input from `%s' to AST representation.\n",
427 formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str());
428
429 AST::current_filename = filename;
430 AST::set_line_num = &frontend_verilog_yyset_lineno;
431 AST::get_line_num = &frontend_verilog_yyget_lineno;
432
433 current_ast = new AST::AstNode(AST::AST_DESIGN);
434
435 lexin = f;
436 std::string code_after_preproc;
437
438 if (!flag_nopp) {
439 code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, design->verilog_defines, include_dirs);
440 if (flag_ppdump)
441 log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
442 lexin = new std::istringstream(code_after_preproc);
443 }
444
445 frontend_verilog_yyset_lineno(1);
446 frontend_verilog_yyrestart(NULL);
447 frontend_verilog_yyparse();
448 frontend_verilog_yylex_destroy();
449
450 for (auto &child : current_ast->children) {
451 if (child->type == AST::AST_MODULE)
452 for (auto &attr : attributes)
453 if (child->attributes.count(attr) == 0)
454 child->attributes[attr] = AST::AstNode::mkconst_int(1, false);
455 }
456
457 if (flag_nodpi)
458 error_on_dpi_function(current_ast);
459
460 AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
461 flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
462
463 if (!flag_nopp)
464 delete lexin;
465
466 delete current_ast;
467 current_ast = NULL;
468
469 log("Successfully finished Verilog frontend.\n");
470 }
471 } VerilogFrontend;
472
473 struct VerilogDefaults : public Pass {
474 VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
475 void help() YS_OVERRIDE
476 {
477 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
478 log("\n");
479 log(" verilog_defaults -add [options]\n");
480 log("\n");
481 log("Add the specified options to the list of default options to read_verilog.\n");
482 log("\n");
483 log("\n");
484 log(" verilog_defaults -clear\n");
485 log("\n");
486 log("Clear the list of Verilog default options.\n");
487 log("\n");
488 log("\n");
489 log(" verilog_defaults -push\n");
490 log(" verilog_defaults -pop\n");
491 log("\n");
492 log("Push or pop the list of default options to a stack. Note that -push does\n");
493 log("not imply -clear.\n");
494 log("\n");
495 }
496 void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
497 {
498 if (args.size() < 2)
499 cmd_error(args, 1, "Missing argument.");
500
501 if (args[1] == "-add") {
502 verilog_defaults.insert(verilog_defaults.end(), args.begin()+2, args.end());
503 return;
504 }
505
506 if (args.size() != 2)
507 cmd_error(args, 2, "Extra argument.");
508
509 if (args[1] == "-clear") {
510 verilog_defaults.clear();
511 return;
512 }
513
514 if (args[1] == "-push") {
515 verilog_defaults_stack.push_back(verilog_defaults);
516 return;
517 }
518
519 if (args[1] == "-pop") {
520 if (verilog_defaults_stack.empty()) {
521 verilog_defaults.clear();
522 } else {
523 verilog_defaults.swap(verilog_defaults_stack.back());
524 verilog_defaults_stack.pop_back();
525 }
526 return;
527 }
528 }
529 } VerilogDefaults;
530
531 struct VerilogDefines : public Pass {
532 VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { }
533 void help() YS_OVERRIDE
534 {
535 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
536 log("\n");
537 log(" verilog_defines [options]\n");
538 log("\n");
539 log("Define and undefine verilog preprocessor macros.\n");
540 log("\n");
541 log(" -Dname[=definition]\n");
542 log(" define the preprocessor symbol 'name' and set its optional value\n");
543 log(" 'definition'\n");
544 log("\n");
545 log(" -Uname[=definition]\n");
546 log(" undefine the preprocessor symbol 'name'\n");
547 log("\n");
548 }
549 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
550 {
551 size_t argidx;
552 for (argidx = 1; argidx < args.size(); argidx++) {
553 std::string arg = args[argidx];
554 if (arg == "-D" && argidx+1 < args.size()) {
555 std::string name = args[++argidx], value;
556 size_t equal = name.find('=');
557 if (equal != std::string::npos) {
558 value = name.substr(equal+1);
559 name = name.substr(0, equal);
560 }
561 design->verilog_defines[name] = std::pair<std::string, bool>(value, false);
562 continue;
563 }
564 if (arg.compare(0, 2, "-D") == 0) {
565 size_t equal = arg.find('=', 2);
566 std::string name = arg.substr(2, equal-2);
567 std::string value;
568 if (equal != std::string::npos)
569 value = arg.substr(equal+1);
570 design->verilog_defines[name] = std::pair<std::string, bool>(value, false);
571 continue;
572 }
573 if (arg == "-U" && argidx+1 < args.size()) {
574 std::string name = args[++argidx];
575 design->verilog_defines.erase(name);
576 continue;
577 }
578 if (arg.compare(0, 2, "-U") == 0) {
579 std::string name = arg.substr(2);
580 design->verilog_defines.erase(name);
581 continue;
582 }
583 break;
584 }
585
586 if (args.size() != argidx)
587 cmd_error(args, argidx, "Extra argument.");
588 }
589 } VerilogDefines;
590
591 YOSYS_NAMESPACE_END
592
593 // the yyerror function used by bison to report parser errors
594 void frontend_verilog_yyerror(char const *fmt, ...)
595 {
596 va_list ap;
597 char buffer[1024];
598 char *p = buffer;
599 va_start(ap, fmt);
600 p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
601 va_end(ap);
602 p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
603 YOSYS_NAMESPACE_PREFIX log_file_error(YOSYS_NAMESPACE_PREFIX AST::current_filename, frontend_verilog_yyget_lineno(),
604 "%s", buffer);
605 exit(1);
606 }