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verilog: Fix write to deleted object
[yosys.git] / frontends / verilog / verilog_frontend.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * The Verilog frontend.
21 *
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
26 *
27 */
28
29 #include "verilog_frontend.h"
30 #include "preproc.h"
31 #include "kernel/yosys.h"
32 #include "libs/sha1/sha1.h"
33 #include <stdarg.h>
34
35 YOSYS_NAMESPACE_BEGIN
36 using namespace VERILOG_FRONTEND;
37
38 // use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL
39
40 static std::vector<std::string> verilog_defaults;
41 static std::list<std::vector<std::string>> verilog_defaults_stack;
42
43 static void error_on_dpi_function(AST::AstNode *node)
44 {
45 if (node->type == AST::AST_DPI_FUNCTION)
46 log_file_error(node->filename, node->location.first_line, "Found DPI function %s.\n", node->str.c_str());
47 for (auto child : node->children)
48 error_on_dpi_function(child);
49 }
50
51 static void add_package_types(std::map<std::string, AST::AstNode *> &user_types, std::vector<AST::AstNode *> &package_list)
52 {
53 // prime the parser's user type lookup table with the package qualified names
54 // of typedefed names in the packages seen so far.
55 for (const auto &pkg : package_list) {
56 log_assert(pkg->type==AST::AST_PACKAGE);
57 for (const auto &node: pkg->children) {
58 if (node->type == AST::AST_TYPEDEF) {
59 std::string s = pkg->str + "::" + node->str.substr(1);
60 user_types[s] = node;
61 }
62 }
63 }
64 user_type_stack.clear();
65 user_type_stack.push_back(new UserTypeMap());
66 }
67
68 struct VerilogFrontend : public Frontend {
69 VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
70 void help() YS_OVERRIDE
71 {
72 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
73 log("\n");
74 log(" read_verilog [options] [filename]\n");
75 log("\n");
76 log("Load modules from a Verilog file to the current design. A large subset of\n");
77 log("Verilog-2005 is supported.\n");
78 log("\n");
79 log(" -sv\n");
80 log(" enable support for SystemVerilog features. (only a small subset\n");
81 log(" of SystemVerilog is supported)\n");
82 log("\n");
83 log(" -formal\n");
84 log(" enable support for SystemVerilog assertions and some Yosys extensions\n");
85 log(" replace the implicit -D SYNTHESIS with -D FORMAL\n");
86 log("\n");
87 log(" -noassert\n");
88 log(" ignore assert() statements\n");
89 log("\n");
90 log(" -noassume\n");
91 log(" ignore assume() statements\n");
92 log("\n");
93 log(" -norestrict\n");
94 log(" ignore restrict() statements\n");
95 log("\n");
96 log(" -assume-asserts\n");
97 log(" treat all assert() statements like assume() statements\n");
98 log("\n");
99 log(" -assert-assumes\n");
100 log(" treat all assume() statements like assert() statements\n");
101 log("\n");
102 log(" -debug\n");
103 log(" alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug\n");
104 log("\n");
105 log(" -dump_ast1\n");
106 log(" dump abstract syntax tree (before simplification)\n");
107 log("\n");
108 log(" -dump_ast2\n");
109 log(" dump abstract syntax tree (after simplification)\n");
110 log("\n");
111 log(" -no_dump_ptr\n");
112 log(" do not include hex memory addresses in dump (easier to diff dumps)\n");
113 log("\n");
114 log(" -dump_vlog1\n");
115 log(" dump ast as Verilog code (before simplification)\n");
116 log("\n");
117 log(" -dump_vlog2\n");
118 log(" dump ast as Verilog code (after simplification)\n");
119 log("\n");
120 log(" -dump_rtlil\n");
121 log(" dump generated RTLIL netlist\n");
122 log("\n");
123 log(" -yydebug\n");
124 log(" enable parser debug output\n");
125 log("\n");
126 log(" -nolatches\n");
127 log(" usually latches are synthesized into logic loops\n");
128 log(" this option prohibits this and sets the output to 'x'\n");
129 log(" in what would be the latches hold condition\n");
130 log("\n");
131 log(" this behavior can also be achieved by setting the\n");
132 log(" 'nolatches' attribute on the respective module or\n");
133 log(" always block.\n");
134 log("\n");
135 log(" -nomem2reg\n");
136 log(" under certain conditions memories are converted to registers\n");
137 log(" early during simplification to ensure correct handling of\n");
138 log(" complex corner cases. this option disables this behavior.\n");
139 log("\n");
140 log(" this can also be achieved by setting the 'nomem2reg'\n");
141 log(" attribute on the respective module or register.\n");
142 log("\n");
143 log(" This is potentially dangerous. Usually the front-end has good\n");
144 log(" reasons for converting an array to a list of registers.\n");
145 log(" Prohibiting this step will likely result in incorrect synthesis\n");
146 log(" results.\n");
147 log("\n");
148 log(" -mem2reg\n");
149 log(" always convert memories to registers. this can also be\n");
150 log(" achieved by setting the 'mem2reg' attribute on the respective\n");
151 log(" module or register.\n");
152 log("\n");
153 log(" -nomeminit\n");
154 log(" do not infer $meminit cells and instead convert initialized\n");
155 log(" memories to registers directly in the front-end.\n");
156 log("\n");
157 log(" -ppdump\n");
158 log(" dump Verilog code after pre-processor\n");
159 log("\n");
160 log(" -nopp\n");
161 log(" do not run the pre-processor\n");
162 log("\n");
163 log(" -nodpi\n");
164 log(" disable DPI-C support\n");
165 log("\n");
166 log(" -noblackbox\n");
167 log(" do not automatically add a (* blackbox *) attribute to an\n");
168 log(" empty module.\n");
169 log("\n");
170 log(" -lib\n");
171 log(" only create empty blackbox modules. This implies -DBLACKBOX.\n");
172 log(" modules with the (* whitebox *) attribute will be preserved.\n");
173 log(" (* lib_whitebox *) will be treated like (* whitebox *).\n");
174 log("\n");
175 log(" -nowb\n");
176 log(" delete (* whitebox *) and (* lib_whitebox *) attributes from\n");
177 log(" all modules.\n");
178 log("\n");
179 log(" -specify\n");
180 log(" parse and import specify blocks\n");
181 log("\n");
182 log(" -noopt\n");
183 log(" don't perform basic optimizations (such as const folding) in the\n");
184 log(" high-level front-end.\n");
185 log("\n");
186 log(" -icells\n");
187 log(" interpret cell types starting with '$' as internal cell types\n");
188 log("\n");
189 log(" -pwires\n");
190 log(" add a wire for each module parameter\n");
191 log("\n");
192 log(" -nooverwrite\n");
193 log(" ignore re-definitions of modules. (the default behavior is to\n");
194 log(" create an error message if the existing module is not a black box\n");
195 log(" module, and overwrite the existing module otherwise.)\n");
196 log("\n");
197 log(" -overwrite\n");
198 log(" overwrite existing modules with the same name\n");
199 log("\n");
200 log(" -defer\n");
201 log(" only read the abstract syntax tree and defer actual compilation\n");
202 log(" to a later 'hierarchy' command. Useful in cases where the default\n");
203 log(" parameters of modules yield invalid or not synthesizable code.\n");
204 log("\n");
205 log(" -noautowire\n");
206 log(" make the default of `default_nettype be \"none\" instead of \"wire\".\n");
207 log("\n");
208 log(" -setattr <attribute_name>\n");
209 log(" set the specified attribute (to the value 1) on all loaded modules\n");
210 log("\n");
211 log(" -Dname[=definition]\n");
212 log(" define the preprocessor symbol 'name' and set its optional value\n");
213 log(" 'definition'\n");
214 log("\n");
215 log(" -Idir\n");
216 log(" add 'dir' to the directories which are used when searching include\n");
217 log(" files\n");
218 log("\n");
219 log("The command 'verilog_defaults' can be used to register default options for\n");
220 log("subsequent calls to 'read_verilog'.\n");
221 log("\n");
222 log("Note that the Verilog frontend does a pretty good job of processing valid\n");
223 log("verilog input, but has not very good error reporting. It generally is\n");
224 log("recommended to use a simulator (for example Icarus Verilog) for checking\n");
225 log("the syntax of the code, rather than to rely on read_verilog for that.\n");
226 log("\n");
227 log("Depending on if read_verilog is run in -formal mode, either the macro\n");
228 log("SYNTHESIS or FORMAL is defined automatically. In addition, read_verilog\n");
229 log("always defines the macro YOSYS.\n");
230 log("\n");
231 log("See the Yosys README file for a list of non-standard Verilog features\n");
232 log("supported by the Yosys Verilog front-end.\n");
233 log("\n");
234 }
235 void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
236 {
237 bool flag_dump_ast1 = false;
238 bool flag_dump_ast2 = false;
239 bool flag_no_dump_ptr = false;
240 bool flag_dump_vlog1 = false;
241 bool flag_dump_vlog2 = false;
242 bool flag_dump_rtlil = false;
243 bool flag_nolatches = false;
244 bool flag_nomeminit = false;
245 bool flag_nomem2reg = false;
246 bool flag_mem2reg = false;
247 bool flag_ppdump = false;
248 bool flag_nopp = false;
249 bool flag_nodpi = false;
250 bool flag_noopt = false;
251 bool flag_icells = false;
252 bool flag_pwires = false;
253 bool flag_nooverwrite = false;
254 bool flag_overwrite = false;
255 bool flag_defer = false;
256 bool flag_noblackbox = false;
257 bool flag_nowb = false;
258 define_map_t defines_map;
259
260 std::list<std::string> include_dirs;
261 std::list<std::string> attributes;
262
263 frontend_verilog_yydebug = false;
264 sv_mode = false;
265 formal_mode = false;
266 norestrict_mode = false;
267 assume_asserts_mode = false;
268 lib_mode = false;
269 specify_mode = false;
270 default_nettype_wire = true;
271
272 args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());
273
274 size_t argidx;
275 for (argidx = 1; argidx < args.size(); argidx++) {
276 std::string arg = args[argidx];
277 if (arg == "-sv") {
278 sv_mode = true;
279 continue;
280 }
281 if (arg == "-formal") {
282 formal_mode = true;
283 continue;
284 }
285 if (arg == "-noassert") {
286 noassert_mode = true;
287 continue;
288 }
289 if (arg == "-noassume") {
290 noassume_mode = true;
291 continue;
292 }
293 if (arg == "-norestrict") {
294 norestrict_mode = true;
295 continue;
296 }
297 if (arg == "-assume-asserts") {
298 assume_asserts_mode = true;
299 continue;
300 }
301 if (arg == "-assert-assumes") {
302 assert_assumes_mode = true;
303 continue;
304 }
305 if (arg == "-debug") {
306 flag_dump_ast1 = true;
307 flag_dump_ast2 = true;
308 flag_dump_vlog1 = true;
309 flag_dump_vlog2 = true;
310 frontend_verilog_yydebug = true;
311 continue;
312 }
313 if (arg == "-dump_ast1") {
314 flag_dump_ast1 = true;
315 continue;
316 }
317 if (arg == "-dump_ast2") {
318 flag_dump_ast2 = true;
319 continue;
320 }
321 if (arg == "-no_dump_ptr") {
322 flag_no_dump_ptr = true;
323 continue;
324 }
325 if (arg == "-dump_vlog1") {
326 flag_dump_vlog1 = true;
327 continue;
328 }
329 if (arg == "-dump_vlog2") {
330 flag_dump_vlog2 = true;
331 continue;
332 }
333 if (arg == "-dump_rtlil") {
334 flag_dump_rtlil = true;
335 continue;
336 }
337 if (arg == "-yydebug") {
338 frontend_verilog_yydebug = true;
339 continue;
340 }
341 if (arg == "-nolatches") {
342 flag_nolatches = true;
343 continue;
344 }
345 if (arg == "-nomeminit") {
346 flag_nomeminit = true;
347 continue;
348 }
349 if (arg == "-nomem2reg") {
350 flag_nomem2reg = true;
351 continue;
352 }
353 if (arg == "-mem2reg") {
354 flag_mem2reg = true;
355 continue;
356 }
357 if (arg == "-ppdump") {
358 flag_ppdump = true;
359 continue;
360 }
361 if (arg == "-nopp") {
362 flag_nopp = true;
363 continue;
364 }
365 if (arg == "-nodpi") {
366 flag_nodpi = true;
367 continue;
368 }
369 if (arg == "-noblackbox") {
370 flag_noblackbox = true;
371 continue;
372 }
373 if (arg == "-lib") {
374 lib_mode = true;
375 defines_map.add("BLACKBOX", "");
376 continue;
377 }
378 if (arg == "-nowb") {
379 flag_nowb = true;
380 continue;
381 }
382 if (arg == "-specify") {
383 specify_mode = true;
384 continue;
385 }
386 if (arg == "-noopt") {
387 flag_noopt = true;
388 continue;
389 }
390 if (arg == "-icells") {
391 flag_icells = true;
392 continue;
393 }
394 if (arg == "-pwires") {
395 flag_pwires = true;
396 continue;
397 }
398 if (arg == "-ignore_redef" || arg == "-nooverwrite") {
399 flag_nooverwrite = true;
400 flag_overwrite = false;
401 continue;
402 }
403 if (arg == "-overwrite") {
404 flag_nooverwrite = false;
405 flag_overwrite = true;
406 continue;
407 }
408 if (arg == "-defer") {
409 flag_defer = true;
410 continue;
411 }
412 if (arg == "-noautowire") {
413 default_nettype_wire = false;
414 continue;
415 }
416 if (arg == "-setattr" && argidx+1 < args.size()) {
417 attributes.push_back(RTLIL::escape_id(args[++argidx]));
418 continue;
419 }
420 if (arg == "-D" && argidx+1 < args.size()) {
421 std::string name = args[++argidx], value;
422 size_t equal = name.find('=');
423 if (equal != std::string::npos) {
424 value = name.substr(equal+1);
425 name = name.substr(0, equal);
426 }
427 defines_map.add(name, value);
428 continue;
429 }
430 if (arg.compare(0, 2, "-D") == 0) {
431 size_t equal = arg.find('=', 2);
432 std::string name = arg.substr(2, equal-2);
433 std::string value;
434 if (equal != std::string::npos)
435 value = arg.substr(equal+1);
436 defines_map.add(name, value);
437 continue;
438 }
439 if (arg == "-I" && argidx+1 < args.size()) {
440 include_dirs.push_back(args[++argidx]);
441 continue;
442 }
443 if (arg.compare(0, 2, "-I") == 0) {
444 include_dirs.push_back(arg.substr(2));
445 continue;
446 }
447 break;
448 }
449 extra_args(f, filename, args, argidx);
450
451 log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str());
452
453 log("Parsing %s%s input from `%s' to AST representation.\n",
454 formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str());
455
456 AST::current_filename = filename;
457 AST::set_line_num = &frontend_verilog_yyset_lineno;
458 AST::get_line_num = &frontend_verilog_yyget_lineno;
459
460 current_ast = new AST::AstNode(AST::AST_DESIGN);
461
462 lexin = f;
463 std::string code_after_preproc;
464
465 if (!flag_nopp) {
466 code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs);
467 if (flag_ppdump)
468 log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
469 lexin = new std::istringstream(code_after_preproc);
470 }
471
472 // make package typedefs available to parser
473 add_package_types(pkg_user_types, design->verilog_packages);
474
475 frontend_verilog_yyset_lineno(1);
476 frontend_verilog_yyrestart(NULL);
477 frontend_verilog_yyparse();
478 frontend_verilog_yylex_destroy();
479
480 for (auto &child : current_ast->children) {
481 if (child->type == AST::AST_MODULE)
482 for (auto &attr : attributes)
483 if (child->attributes.count(attr) == 0)
484 child->attributes[attr] = AST::AstNode::mkconst_int(1, false);
485 }
486
487 if (flag_nodpi)
488 error_on_dpi_function(current_ast);
489
490 AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
491 flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
492
493
494 if (!flag_nopp)
495 delete lexin;
496
497 delete current_ast;
498 current_ast = NULL;
499
500 log("Successfully finished Verilog frontend.\n");
501 }
502 } VerilogFrontend;
503
504 struct VerilogDefaults : public Pass {
505 VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
506 void help() YS_OVERRIDE
507 {
508 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
509 log("\n");
510 log(" verilog_defaults -add [options]\n");
511 log("\n");
512 log("Add the specified options to the list of default options to read_verilog.\n");
513 log("\n");
514 log("\n");
515 log(" verilog_defaults -clear\n");
516 log("\n");
517 log("Clear the list of Verilog default options.\n");
518 log("\n");
519 log("\n");
520 log(" verilog_defaults -push\n");
521 log(" verilog_defaults -pop\n");
522 log("\n");
523 log("Push or pop the list of default options to a stack. Note that -push does\n");
524 log("not imply -clear.\n");
525 log("\n");
526 }
527 void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
528 {
529 if (args.size() < 2)
530 cmd_error(args, 1, "Missing argument.");
531
532 if (args[1] == "-add") {
533 verilog_defaults.insert(verilog_defaults.end(), args.begin()+2, args.end());
534 return;
535 }
536
537 if (args.size() != 2)
538 cmd_error(args, 2, "Extra argument.");
539
540 if (args[1] == "-clear") {
541 verilog_defaults.clear();
542 return;
543 }
544
545 if (args[1] == "-push") {
546 verilog_defaults_stack.push_back(verilog_defaults);
547 return;
548 }
549
550 if (args[1] == "-pop") {
551 if (verilog_defaults_stack.empty()) {
552 verilog_defaults.clear();
553 } else {
554 verilog_defaults.swap(verilog_defaults_stack.back());
555 verilog_defaults_stack.pop_back();
556 }
557 return;
558 }
559 }
560 } VerilogDefaults;
561
562 struct VerilogDefines : public Pass {
563 VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { }
564 void help() YS_OVERRIDE
565 {
566 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
567 log("\n");
568 log(" verilog_defines [options]\n");
569 log("\n");
570 log("Define and undefine verilog preprocessor macros.\n");
571 log("\n");
572 log(" -Dname[=definition]\n");
573 log(" define the preprocessor symbol 'name' and set its optional value\n");
574 log(" 'definition'\n");
575 log("\n");
576 log(" -Uname[=definition]\n");
577 log(" undefine the preprocessor symbol 'name'\n");
578 log("\n");
579 log(" -reset\n");
580 log(" clear list of defined preprocessor symbols\n");
581 log("\n");
582 log(" -list\n");
583 log(" list currently defined preprocessor symbols\n");
584 log("\n");
585 }
586 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
587 {
588 size_t argidx;
589 for (argidx = 1; argidx < args.size(); argidx++) {
590 std::string arg = args[argidx];
591 if (arg == "-D" && argidx+1 < args.size()) {
592 std::string name = args[++argidx], value;
593 size_t equal = name.find('=');
594 if (equal != std::string::npos) {
595 value = name.substr(equal+1);
596 name = name.substr(0, equal);
597 }
598 design->verilog_defines->add(name, value);
599 continue;
600 }
601 if (arg.compare(0, 2, "-D") == 0) {
602 size_t equal = arg.find('=', 2);
603 std::string name = arg.substr(2, equal-2);
604 std::string value;
605 if (equal != std::string::npos)
606 value = arg.substr(equal+1);
607 design->verilog_defines->add(name, value);
608 continue;
609 }
610 if (arg == "-U" && argidx+1 < args.size()) {
611 std::string name = args[++argidx];
612 design->verilog_defines->erase(name);
613 continue;
614 }
615 if (arg.compare(0, 2, "-U") == 0) {
616 std::string name = arg.substr(2);
617 design->verilog_defines->erase(name);
618 continue;
619 }
620 if (arg == "-reset") {
621 design->verilog_defines->clear();
622 continue;
623 }
624 if (arg == "-list") {
625 design->verilog_defines->log();
626 continue;
627 }
628 break;
629 }
630
631 if (args.size() != argidx)
632 cmd_error(args, argidx, "Extra argument.");
633 }
634 } VerilogDefines;
635
636 YOSYS_NAMESPACE_END
637
638 // the yyerror function used by bison to report parser errors
639 void frontend_verilog_yyerror(char const *fmt, ...)
640 {
641 va_list ap;
642 char buffer[1024];
643 char *p = buffer;
644 va_start(ap, fmt);
645 p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
646 va_end(ap);
647 p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
648 YOSYS_NAMESPACE_PREFIX log_file_error(YOSYS_NAMESPACE_PREFIX AST::current_filename, frontend_verilog_yyget_lineno(),
649 "%s", buffer);
650 exit(1);
651 }