frontends/verilog/verilog_frontend.h

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The Verilog frontend.
  21  *
  22  *  This frontend is using the AST frontend library (see frontends/ast/).
  23  *  Thus this frontend does not generate RTLIL code directly but creates an
  24  *  AST directly from the Verilog parse tree and then passes this AST to
  25  *  the AST frontend library.
  26  *
  27  */
  28
  29 #ifndef VERILOG_FRONTEND_H
  30 #define VERILOG_FRONTEND_H
  31
  32 #include "kernel/yosys.h"
  33 #include "frontends/ast/ast.h"
  34 #include <stdio.h>
  35 #include <stdint.h>
  36 #include <list>
  37
  38 YOSYS_NAMESPACE_BEGIN
  39
  40 namespace VERILOG_FRONTEND
  41 {
  42         // this variable is set to a new AST_DESIGN node and then filled with the AST by the bison parser
  43         extern struct AST::AstNode *current_ast;
  44
  45         // this function converts a Verilog constant to an AST_CONSTANT node
  46         AST::AstNode *const2ast(std::string code, char case_type = 0, bool warn_z = false);
  47
  48         // state of `default_nettype
  49         extern bool default_nettype_wire;
  50
  51         // running in SystemVerilog mode
  52         extern bool sv_mode;
  53
  54         // running in -formal mode
  55         extern bool formal_mode;
  56
  57         // running in -norestrict mode
  58         extern bool norestrict_mode;
  59
  60         // running in -assume-asserts mode
  61         extern bool assume_asserts_mode;
  62
  63         // running in -lib mode
  64         extern bool lib_mode;
  65
  66         // lexer input stream
  67         extern std::istream *lexin;
  68 }
  69
  70 // the pre-processor
  71 std::string frontend_verilog_preproc(std::istream &f, std::string filename, const std::map<std::string, std::string> &pre_defines_map,
  72                 dict<std::string, std::pair<std::string, bool>> &global_defines_cache, const std::list<std::string> &include_dirs);
  73
  74 YOSYS_NAMESPACE_END
  75
  76 // the usual bison/flex stuff
  77 extern int frontend_verilog_yydebug;
  78 int frontend_verilog_yylex(void);
  79 void frontend_verilog_yyerror(char const *fmt, ...);
  80 void frontend_verilog_yyrestart(FILE *f);
  81 int frontend_verilog_yyparse(void);
  82 int frontend_verilog_yylex_destroy(void);
  83 int frontend_verilog_yyget_lineno(void);
  84 void frontend_verilog_yyset_lineno (int);
  85
  86 #endif