2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The Verilog frontend.
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
29 #ifndef VERILOG_FRONTEND_H
30 #define VERILOG_FRONTEND_H
32 #include "kernel/yosys.h"
33 #include "frontends/ast/ast.h"
40 namespace VERILOG_FRONTEND
42 // this variable is set to a new AST_DESIGN node and then filled with the AST by the bison parser
43 extern struct AST::AstNode
*current_ast
;
45 // this function converts a Verilog constant to an AST_CONSTANT node
46 AST::AstNode
*const2ast(std::string code
, char case_type
= 0, bool warn_z
= false);
48 // state of `default_nettype
49 extern bool default_nettype_wire
;
51 // running in SystemVerilog mode
54 // running in -formal mode
55 extern bool formal_mode
;
57 // running in -noassert mode
58 extern bool noassert_mode
;
60 // running in -noassume mode
61 extern bool noassume_mode
;
63 // running in -norestrict mode
64 extern bool norestrict_mode
;
66 // running in -assume-asserts mode
67 extern bool assume_asserts_mode
;
69 // running in -assert-assumes mode
70 extern bool assert_assumes_mode
;
72 // running in -lib mode
75 // running in -specify mode
76 extern bool specify_mode
;
79 extern std::istream
*lexin
;
83 std::string
frontend_verilog_preproc(std::istream
&f
, std::string filename
, const std::map
<std::string
, std::string
> &pre_defines_map
,
84 dict
<std::string
, std::pair
<std::string
, bool>> &global_defines_cache
, const std::list
<std::string
> &include_dirs
);
88 // the usual bison/flex stuff
89 extern int frontend_verilog_yydebug
;
90 int frontend_verilog_yylex(void);
91 void frontend_verilog_yyerror(char const *fmt
, ...);
92 void frontend_verilog_yyrestart(FILE *f
);
93 int frontend_verilog_yyparse(void);
94 int frontend_verilog_yylex_destroy(void);
95 int frontend_verilog_yyget_lineno(void);
96 void frontend_verilog_yyset_lineno (int);