2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The Verilog frontend.
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
29 * A simple lexer for Verilog code. Non-preprocessor compiler directives are
30 * handled here. The preprocessor stuff is handled in preproc.cc. Everything
31 * else is left to the bison parser (see verilog_parser.y).
38 // bison generates code using the 'register' storage class specifier
39 #pragma clang diagnostic ignored "-Wdeprecated-register"
42 #include "kernel/log.h"
43 #include "frontends/verilog/verilog_frontend.h"
44 #include "frontends/ast/ast.h"
45 #include "verilog_parser.tab.hh"
49 using namespace VERILOG_FRONTEND;
52 namespace VERILOG_FRONTEND {
53 std::vector<std::string> fn_stack;
54 std::vector<int> ln_stack;
58 #define YYSTYPE FRONTEND_VERILOG_YYSTYPE
59 #define YYLTYPE FRONTEND_VERILOG_YYLTYPE
61 #define SV_KEYWORD(_tok) \
62 if (sv_mode) return _tok; \
63 log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\
64 "recognized unless read_verilog is called with -sv!\n", yytext, \
65 AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); \
66 yylval->string = new std::string(std::string("\\") + yytext); \
69 #define NON_KEYWORD() \
70 yylval->string = new std::string(std::string("\\") + yytext); \
73 #define YY_INPUT(buf,result,max_size) \
74 result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
76 YYLTYPE real_location;
79 #define YY_USER_ACTION \
80 old_location = real_location; \
81 real_location.first_line = real_location.last_line; \
82 real_location.first_column = real_location.last_column; \
83 for(int i = 0; yytext[i] != '\0'; ++i){ \
84 if(yytext[i] == '\n') { \
85 real_location.last_line++; \
86 real_location.last_column = 1; \
89 real_location.last_column++; \
92 (*yylloc) = real_location;
95 (*yylloc) = old_location; \
99 #define YY_BUF_SIZE 65536
101 extern int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
107 %option bison-locations
109 %option prefix="frontend_verilog_yy"
113 %x SYNOPSYS_TRANSLATE_OFF
119 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_push "[^\n]* {
120 fn_stack.push_back(current_filename);
121 ln_stack.push_back(frontend_verilog_yyget_lineno());
122 current_filename = yytext+11;
123 if (!current_filename.empty() && current_filename.front() == '"')
124 current_filename = current_filename.substr(1);
125 if (!current_filename.empty() && current_filename.back() == '"')
126 current_filename = current_filename.substr(0, current_filename.size()-1);
127 frontend_verilog_yyset_lineno(0);
128 yylloc->first_line = yylloc->last_line = 0;
129 real_location.first_line = real_location.last_line = 0;
132 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_pop"[^\n]*\n {
133 current_filename = fn_stack.back();
135 frontend_verilog_yyset_lineno(ln_stack.back());
136 yylloc->first_line = yylloc->last_line = ln_stack.back();
137 real_location.first_line = real_location.last_line = ln_stack.back();
141 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`line"[ \t]+[^ \t\r\n]+[ \t]+\"[^ \r\n]+\"[^\r\n]*\n {
142 char *p = yytext + 5;
143 while (*p == ' ' || *p == '\t') p++;
144 frontend_verilog_yyset_lineno(atoi(p));
145 yylloc->first_line = yylloc->last_line = atoi(p);
146 real_location.first_line = real_location.last_line = atoi(p);
147 while (*p && *p != ' ' && *p != '\t') p++;
148 while (*p == ' ' || *p == '\t') p++;
149 char *q = *p ? p + 1 : p;
150 while (*q && *q != '"') q++;
151 current_filename = std::string(p).substr(1, q-p-1);
154 "`file_notfound "[^\n]* {
155 log_error("Can't open include file `%s'!\n", yytext + 15);
158 "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
160 "`celldefine"[^\n]* /* ignore `celldefine */
161 "`endcelldefine"[^\n]* /* ignore `endcelldefine */
163 "`default_nettype"[ \t]+[^ \t\r\n/]+ {
165 while (*p != 0 && *p != ' ' && *p != '\t') p++;
166 while (*p == ' ' || *p == '\t') p++;
167 if (!strcmp(p, "none"))
168 VERILOG_FRONTEND::default_nettype_wire = false;
169 else if (!strcmp(p, "wire"))
170 VERILOG_FRONTEND::default_nettype_wire = true;
172 frontend_verilog_yyerror("Unsupported default nettype: %s", p);
175 "`protect"[^\n]* /* ignore `protect*/
176 "`endprotect"[^\n]* /* ignore `endprotect*/
178 "`"[a-zA-Z_$][a-zA-Z0-9_$]* {
179 frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
182 "module" { return TOK_MODULE; }
183 "endmodule" { return TOK_ENDMODULE; }
184 "function" { return TOK_FUNCTION; }
185 "endfunction" { return TOK_ENDFUNCTION; }
186 "task" { return TOK_TASK; }
187 "endtask" { return TOK_ENDTASK; }
188 "specify" { return specify_mode ? TOK_SPECIFY : TOK_IGNORED_SPECIFY; }
189 "endspecify" { return TOK_ENDSPECIFY; }
190 "specparam" { return TOK_SPECPARAM; }
191 "package" { SV_KEYWORD(TOK_PACKAGE); }
192 "endpackage" { SV_KEYWORD(TOK_ENDPACKAGE); }
193 "interface" { SV_KEYWORD(TOK_INTERFACE); }
194 "endinterface" { SV_KEYWORD(TOK_ENDINTERFACE); }
195 "modport" { SV_KEYWORD(TOK_MODPORT); }
196 "parameter" { return TOK_PARAMETER; }
197 "localparam" { return TOK_LOCALPARAM; }
198 "defparam" { return TOK_DEFPARAM; }
199 "assign" { return TOK_ASSIGN; }
200 "always" { return TOK_ALWAYS; }
201 "initial" { return TOK_INITIAL; }
202 "begin" { return TOK_BEGIN; }
203 "end" { return TOK_END; }
204 "if" { return TOK_IF; }
205 "else" { return TOK_ELSE; }
206 "for" { return TOK_FOR; }
207 "posedge" { return TOK_POSEDGE; }
208 "negedge" { return TOK_NEGEDGE; }
209 "or" { return TOK_OR; }
210 "case" { return TOK_CASE; }
211 "casex" { return TOK_CASEX; }
212 "casez" { return TOK_CASEZ; }
213 "endcase" { return TOK_ENDCASE; }
214 "default" { return TOK_DEFAULT; }
215 "generate" { return TOK_GENERATE; }
216 "endgenerate" { return TOK_ENDGENERATE; }
217 "while" { return TOK_WHILE; }
218 "repeat" { return TOK_REPEAT; }
219 "automatic" { return TOK_AUTOMATIC; }
221 "unique" { SV_KEYWORD(TOK_UNIQUE); }
222 "unique0" { SV_KEYWORD(TOK_UNIQUE); }
223 "priority" { SV_KEYWORD(TOK_PRIORITY); }
225 "always_comb" { SV_KEYWORD(TOK_ALWAYS_COMB); }
226 "always_ff" { SV_KEYWORD(TOK_ALWAYS_FF); }
227 "always_latch" { SV_KEYWORD(TOK_ALWAYS_LATCH); }
229 /* use special token for labels on assert, assume, cover, and restrict because it's insanley complex
230 to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some
231 global state.. its a mess) */
232 [a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] {
233 if (!strcmp(yytext, "default"))
235 yylval->string = new std::string(std::string("\\") + yytext);
236 return TOK_SVA_LABEL;
239 "assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
240 "assume" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
241 "cover" { if (formal_mode) return TOK_COVER; SV_KEYWORD(TOK_COVER); }
242 "restrict" { if (formal_mode) return TOK_RESTRICT; SV_KEYWORD(TOK_RESTRICT); }
243 "property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
244 "rand" { if (formal_mode) return TOK_RAND; SV_KEYWORD(TOK_RAND); }
245 "const" { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }
246 "checker" { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); }
247 "endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }
248 "final" { SV_KEYWORD(TOK_FINAL); }
249 "logic" { SV_KEYWORD(TOK_LOGIC); }
250 "var" { SV_KEYWORD(TOK_VAR); }
251 "bit" { SV_KEYWORD(TOK_REG); }
253 "eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
254 "s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
256 "input" { return TOK_INPUT; }
257 "output" { return TOK_OUTPUT; }
258 "inout" { return TOK_INOUT; }
259 "wire" { return TOK_WIRE; }
260 "wor" { return TOK_WOR; }
261 "wand" { return TOK_WAND; }
262 "reg" { return TOK_REG; }
263 "integer" { return TOK_INTEGER; }
264 "signed" { return TOK_SIGNED; }
265 "genvar" { return TOK_GENVAR; }
266 "real" { return TOK_REAL; }
268 "enum" { SV_KEYWORD(TOK_ENUM); }
269 "typedef" { SV_KEYWORD(TOK_TYPEDEF); }
272 yylval->string = new std::string(yytext);
276 [0-9]*[ \t]*\'[sS]?[bodhBODH]?[ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
277 yylval->string = new std::string(yytext);
281 [0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? {
282 yylval->string = new std::string(yytext);
286 [0-9][0-9_]*[eE][-+]?[0-9_]+ {
287 yylval->string = new std::string(yytext);
291 \" { BEGIN(STRING); }
292 <STRING>\\. { yymore(); real_location = old_location; }
295 char *yystr = strdup(yytext);
296 yystr[strlen(yytext) - 1] = 0;
299 if (yystr[i] == '\\' && yystr[i + 1]) {
303 else if (yystr[i] == 'f')
305 else if (yystr[i] == 'n')
307 else if (yystr[i] == 'r')
309 else if (yystr[i] == 't')
311 else if (yystr[i] == 'v')
313 else if ('0' <= yystr[i] && yystr[i] <= '7') {
314 yystr[i] = yystr[i] - '0';
315 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
316 yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
319 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
320 yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
325 yystr[j++] = yystr[i++];
328 yylval->string = new std::string(yystr, j);
332 <STRING>. { yymore(); real_location = old_location; }
334 and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 {
335 yylval->string = new std::string(yytext);
336 return TOK_PRIMITIVE;
339 supply0 { return TOK_SUPPLY0; }
340 supply1 { return TOK_SUPPLY1; }
342 "$"(display|write|strobe|monitor|time|stop|finish|dumpfile|dumpvars|dumpon|dumpoff|dumpall) {
343 yylval->string = new std::string(yytext);
347 "$"(setup|hold|setuphold|removal|recovery|recrem|skew|timeskew|fullskew|nochange) {
348 if (!specify_mode) REJECT;
349 yylval->string = new std::string(yytext);
353 "$"(info|warning|error|fatal) {
354 yylval->string = new std::string(yytext);
355 return TOK_MSG_TASKS;
358 "$signed" { return TOK_TO_SIGNED; }
359 "$unsigned" { return TOK_TO_UNSIGNED; }
361 [a-zA-Z_$][a-zA-Z0-9_$]* {
362 yylval->string = new std::string(std::string("\\") + yytext);
366 [a-zA-Z_$][a-zA-Z0-9_$\.]* {
367 yylval->string = new std::string(std::string("\\") + yytext);
371 "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {
372 static bool printed_warning = false;
373 if (!printed_warning) {
374 log_warning("Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"
375 "Yosys does support them but it is recommended to use `ifdef constructs instead!\n");
376 printed_warning = true;
378 BEGIN(SYNOPSYS_TRANSLATE_OFF);
380 <SYNOPSYS_TRANSLATE_OFF>. /* ignore synopsys translate_off body */
381 <SYNOPSYS_TRANSLATE_OFF>\n /* ignore synopsys translate_off body */
382 <SYNOPSYS_TRANSLATE_OFF>"/*"[ \t]*(synopsys|synthesis)[ \t]*"translate_on"[ \t]*"*/" { BEGIN(0); }
384 "/*"[ \t]*(synopsys|synthesis)[ \t]+ {
385 BEGIN(SYNOPSYS_FLAGS);
387 <SYNOPSYS_FLAGS>full_case {
388 static bool printed_warning = false;
389 if (!printed_warning) {
390 log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"
391 "Yosys does support them but it is recommended to use Verilog `full_case' attributes instead!\n");
392 printed_warning = true;
394 return TOK_SYNOPSYS_FULL_CASE;
396 <SYNOPSYS_FLAGS>parallel_case {
397 static bool printed_warning = false;
398 if (!printed_warning) {
399 log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"
400 "Yosys does support them but it is recommended to use Verilog `parallel_case' attributes instead!\n");
401 printed_warning = true;
403 return TOK_SYNOPSYS_PARALLEL_CASE;
405 <SYNOPSYS_FLAGS>. /* ignore everything else */
406 <SYNOPSYS_FLAGS>"*/" { BEGIN(0); }
408 import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
410 return TOK_DPI_FUNCTION;
413 <IMPORT_DPI>[a-zA-Z_$][a-zA-Z0-9_$]* {
414 yylval->string = new std::string(std::string("\\") + yytext);
418 <IMPORT_DPI>[ \t\r\n] /* ignore whitespaces */
430 yylval->string = new std::string(yytext);
434 "(*" { return ATTR_BEGIN; }
435 "*)" { return ATTR_END; }
437 "{*" { return DEFATTR_BEGIN; }
438 "*}" { return DEFATTR_END; }
440 "**" { return OP_POW; }
441 "||" { return OP_LOR; }
442 "&&" { return OP_LAND; }
443 "==" { return OP_EQ; }
444 "!=" { return OP_NE; }
445 "<=" { return OP_LE; }
446 ">=" { return OP_GE; }
448 "===" { return OP_EQX; }
449 "!==" { return OP_NEX; }
451 "~&" { return OP_NAND; }
452 "~|" { return OP_NOR; }
453 "~^" { return OP_XNOR; }
454 "^~" { return OP_XNOR; }
456 "<<" { return OP_SHL; }
457 ">>" { return OP_SHR; }
458 "<<<" { return OP_SSHL; }
459 ">>>" { return OP_SSHR; }
461 "::" { return TOK_PACKAGESEP; }
462 "++" { return TOK_INCREMENT; }
463 "--" { return TOK_DECREMENT; }
465 "+:" { return TOK_POS_INDEXED; }
466 "-:" { return TOK_NEG_INDEXED; }
468 ".*" { return TOK_WILDCARD_CONNECT; }
471 if (!specify_mode) REJECT;
472 yylval->string = new std::string(yytext);
473 return TOK_SPECIFY_OPER;
477 if (!specify_mode) return TOK_IGNORED_SPECIFY_AND;
478 return TOK_SPECIFY_AND;
481 "/*" { BEGIN(COMMENT); }
482 <COMMENT>. /* ignore comment body */
483 <COMMENT>\n /* ignore comment body */
484 <COMMENT>"*/" { BEGIN(0); }
486 [ \t\r\n] /* ignore whitespaces */
487 \\[\r\n] /* ignore continuation sequence */
488 "//"[^\r\n]* /* ignore one-line comments */
490 . { return *yytext; }
494 // this is a hack to avoid the 'yyinput defined but not used' error msgs
495 void *frontend_verilog_avoid_input_warnings() {
496 return (void*)&yyinput;