frontends/verilog/verilog_lexer.l

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The Verilog frontend.
  21  *
  22  *  This frontend is using the AST frontend library (see frontends/ast/).
  23  *  Thus this frontend does not generate RTLIL code directly but creates an
  24  *  AST directly from the Verilog parse tree and then passes this AST to
  25  *  the AST frontend library.
  26  *
  27  *  ---
  28  *
  29  *  A simple lexer for Verilog code. Non-preprocessor compiler directives are
  30  *  handled here. The preprocessor stuff is handled in preproc.cc. Everything
  31  *  else is left to the bison parser (see parser.y).
  32  *
  33  */
  34
  35 %{
  36
  37 #ifdef __clang__
  38 // bison generates code using the 'register' storage class specifier
  39 #pragma clang diagnostic ignored "-Wdeprecated-register"
  40 #endif
  41
  42 #include "kernel/log.h"
  43 #include "frontends/verilog/verilog_frontend.h"
  44 #include "frontends/ast/ast.h"
  45 #include "verilog_parser.tab.hh"
  46
  47 USING_YOSYS_NAMESPACE
  48 using namespace AST;
  49 using namespace VERILOG_FRONTEND;
  50
  51 YOSYS_NAMESPACE_BEGIN
  52 namespace VERILOG_FRONTEND {
  53         std::vector<std::string> fn_stack;
  54         std::vector<int> ln_stack;
  55 }
  56 YOSYS_NAMESPACE_END
  57
  58 #define SV_KEYWORD(_tok) \
  59         if (sv_mode) return _tok; \
  60         log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\
  61                         "recognized unless read_verilog is called with -sv!\n", yytext, \
  62                         AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); \
  63         frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
  64         return TOK_ID;
  65
  66 #define NON_KEYWORD() \
  67         frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
  68         return TOK_ID;
  69
  70 #define YY_INPUT(buf,result,max_size) \
  71         result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
  72
  73 %}
  74
  75 %option yylineno
  76 %option noyywrap
  77 %option nounput
  78 %option prefix="frontend_verilog_yy"
  79
  80 %x COMMENT
  81 %x STRING
  82 %x SYNOPSYS_TRANSLATE_OFF
  83 %x SYNOPSYS_FLAGS
  84 %x IMPORT_DPI
  85
  86 %%
  87
  88 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_push "[^\n]* {
  89         fn_stack.push_back(current_filename);
  90         ln_stack.push_back(frontend_verilog_yyget_lineno());
  91         current_filename = yytext+11;
  92         if (!current_filename.empty() && current_filename.front() == '"')
  93                 current_filename = current_filename.substr(1);
  94         if (!current_filename.empty() && current_filename.back() == '"')
  95                 current_filename = current_filename.substr(0, current_filename.size()-1);
  96         frontend_verilog_yyset_lineno(0);
  97 }
  98
  99 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_pop"[^\n]*\n {
 100         current_filename = fn_stack.back();
 101         fn_stack.pop_back();
 102         frontend_verilog_yyset_lineno(ln_stack.back());
 103         ln_stack.pop_back();
 104 }
 105
 106 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`line"[ \t]+[^ \t\r\n]+[ \t]+\"[^ \r\n]+\"[^\r\n]*\n {
 107         char *p = yytext + 5;
 108         while (*p == ' ' || *p == '\t') p++;
 109         frontend_verilog_yyset_lineno(atoi(p));
 110         while (*p && *p != ' ' && *p != '\t') p++;
 111         while (*p == ' ' || *p == '\t') p++;
 112         char *q = *p ? p + 1 : p;
 113         while (*q && *q != '"') q++;
 114         current_filename = std::string(p).substr(1, q-p-1);
 115 }
 116
 117 "`file_notfound "[^\n]* {
 118         log_error("Can't open include file `%s'!\n", yytext + 15);
 119 }
 120
 121 "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
 122
 123 "`celldefine"[^\n]* /* ignore `celldefine */
 124 "`endcelldefine"[^\n]* /* ignore `endcelldefine */
 125
 126 "`default_nettype"[ \t]+[^ \t\r\n/]+ {
 127         char *p = yytext;
 128         while (*p != 0 && *p != ' ' && *p != '\t') p++;
 129         while (*p == ' ' || *p == '\t') p++;
 130         if (!strcmp(p, "none"))
 131                 VERILOG_FRONTEND::default_nettype_wire = false;
 132         else if (!strcmp(p, "wire"))
 133                 VERILOG_FRONTEND::default_nettype_wire = true;
 134         else
 135                 frontend_verilog_yyerror("Unsupported default nettype: %s", p);
 136 }
 137
 138 "`protect"[^\n]* /* ignore `protect*/
 139 "`endprotect"[^\n]* /* ignore `endprotect*/
 140
 141 "`"[a-zA-Z_$][a-zA-Z0-9_$]* {
 142         frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
 143 }
 144
 145 "module"       { return TOK_MODULE; }
 146 "endmodule"    { return TOK_ENDMODULE; }
 147 "function"     { return TOK_FUNCTION; }
 148 "endfunction"  { return TOK_ENDFUNCTION; }
 149 "task"         { return TOK_TASK; }
 150 "endtask"      { return TOK_ENDTASK; }
 151 "specify"      { return specify_mode ? TOK_SPECIFY : TOK_IGNORED_SPECIFY; }
 152 "endspecify"   { return TOK_ENDSPECIFY; }
 153 "specparam"    { return TOK_SPECPARAM; }
 154 "package"      { SV_KEYWORD(TOK_PACKAGE); }
 155 "endpackage"   { SV_KEYWORD(TOK_ENDPACKAGE); }
 156 "interface"    { SV_KEYWORD(TOK_INTERFACE); }
 157 "endinterface" { SV_KEYWORD(TOK_ENDINTERFACE); }
 158 "modport"      { SV_KEYWORD(TOK_MODPORT); }
 159 "parameter"    { return TOK_PARAMETER; }
 160 "localparam"   { return TOK_LOCALPARAM; }
 161 "defparam"     { return TOK_DEFPARAM; }
 162 "assign"       { return TOK_ASSIGN; }
 163 "always"       { return TOK_ALWAYS; }
 164 "initial"      { return TOK_INITIAL; }
 165 "begin"        { return TOK_BEGIN; }
 166 "end"          { return TOK_END; }
 167 "if"           { return TOK_IF; }
 168 "else"         { return TOK_ELSE; }
 169 "for"          { return TOK_FOR; }
 170 "posedge"      { return TOK_POSEDGE; }
 171 "negedge"      { return TOK_NEGEDGE; }
 172 "or"           { return TOK_OR; }
 173 "case"         { return TOK_CASE; }
 174 "casex"        { return TOK_CASEX; }
 175 "casez"        { return TOK_CASEZ; }
 176 "endcase"      { return TOK_ENDCASE; }
 177 "default"      { return TOK_DEFAULT; }
 178 "generate"     { return TOK_GENERATE; }
 179 "endgenerate"  { return TOK_ENDGENERATE; }
 180 "while"        { return TOK_WHILE; }
 181 "repeat"       { return TOK_REPEAT; }
 182 "automatic"    { return TOK_AUTOMATIC; }
 183
 184 "unique"       { SV_KEYWORD(TOK_UNIQUE); }
 185 "unique0"      { SV_KEYWORD(TOK_UNIQUE); }
 186 "priority"     { SV_KEYWORD(TOK_PRIORITY); }
 187
 188 "always_comb"  { SV_KEYWORD(TOK_ALWAYS); }
 189 "always_ff"    { SV_KEYWORD(TOK_ALWAYS); }
 190 "always_latch" { SV_KEYWORD(TOK_ALWAYS); }
 191
 192  /* use special token for labels on assert, assume, cover, and restrict because it's insanley complex
 193     to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some
 194     global state.. its a mess) */
 195 [a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] {
 196         frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
 197         return TOK_SVA_LABEL;
 198 }
 199
 200 "assert"     { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
 201 "assume"     { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
 202 "cover"      { if (formal_mode) return TOK_COVER; SV_KEYWORD(TOK_COVER); }
 203 "restrict"   { if (formal_mode) return TOK_RESTRICT; SV_KEYWORD(TOK_RESTRICT); }
 204 "property"   { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
 205 "rand"       { if (formal_mode) return TOK_RAND; SV_KEYWORD(TOK_RAND); }
 206 "const"      { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }
 207 "checker"    { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); }
 208 "endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }
 209 "final"      { SV_KEYWORD(TOK_FINAL); }
 210 "logic"      { SV_KEYWORD(TOK_LOGIC); }
 211 "var"        { SV_KEYWORD(TOK_VAR); }
 212 "bit"        { SV_KEYWORD(TOK_REG); }
 213
 214 "eventually"   { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
 215 "s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
 216
 217 "input"   { return TOK_INPUT; }
 218 "output"  { return TOK_OUTPUT; }
 219 "inout"   { return TOK_INOUT; }
 220 "wire"    { return TOK_WIRE; }
 221 "wor"     { return TOK_WOR; }
 222 "wand"    { return TOK_WAND; }
 223 "reg"     { return TOK_REG; }
 224 "integer" { return TOK_INTEGER; }
 225 "signed"  { return TOK_SIGNED; }
 226 "genvar"  { return TOK_GENVAR; }
 227 "real"    { return TOK_REAL; }
 228
 229 "enum"    { SV_KEYWORD(TOK_ENUM); }
 230 "typedef" { SV_KEYWORD(TOK_TYPEDEF); }
 231
 232 [0-9][0-9_]* {
 233         frontend_verilog_yylval.string = new std::string(yytext);
 234         return TOK_CONSTVAL;
 235 }
 236
 237 [0-9]*[ \t]*\'s?[bodhBODH]*[ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
 238         frontend_verilog_yylval.string = new std::string(yytext);
 239         return TOK_CONSTVAL;
 240 }
 241
 242 [0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? {
 243         frontend_verilog_yylval.string = new std::string(yytext);
 244         return TOK_REALVAL;
 245 }
 246
 247 [0-9][0-9_]*[eE][-+]?[0-9_]+ {
 248         frontend_verilog_yylval.string = new std::string(yytext);
 249         return TOK_REALVAL;
 250 }
 251
 252 \"              { BEGIN(STRING); }
 253 <STRING>\\.     { yymore(); }
 254 <STRING>\"      {
 255         BEGIN(0);
 256         char *yystr = strdup(yytext);
 257         yystr[strlen(yytext) - 1] = 0;
 258         int i = 0, j = 0;
 259         while (yystr[i]) {
 260                 if (yystr[i] == '\\' && yystr[i + 1]) {
 261                         i++;
 262                         if (yystr[i] == 'a')
 263                                 yystr[i] = '\a';
 264                         else if (yystr[i] == 'f')
 265                                 yystr[i] = '\f';
 266                         else if (yystr[i] == 'n')
 267                                 yystr[i] = '\n';
 268                         else if (yystr[i] == 'r')
 269                                 yystr[i] = '\r';
 270                         else if (yystr[i] == 't')
 271                                 yystr[i] = '\t';
 272                         else if (yystr[i] == 'v')
 273                                 yystr[i] = '\v';
 274                         else if ('0' <= yystr[i] && yystr[i] <= '7') {
 275                                 yystr[i] = yystr[i] - '0';
 276                                 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
 277                                         yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
 278                                         i++;
 279                                 }
 280                                 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
 281                                         yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
 282                                         i++;
 283                                 }
 284                         }
 285                 }
 286                 yystr[j++] = yystr[i++];
 287         }
 288         yystr[j] = 0;
 289         frontend_verilog_yylval.string = new std::string(yystr, j);
 290         free(yystr);
 291         return TOK_STRING;
 292 }
 293 <STRING>.       { yymore(); }
 294
 295 and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 {
 296         frontend_verilog_yylval.string = new std::string(yytext);
 297         return TOK_PRIMITIVE;
 298 }
 299
 300 supply0 { return TOK_SUPPLY0; }
 301 supply1 { return TOK_SUPPLY1; }
 302
 303 "$"(display|write|strobe|monitor|time|stop|finish|dumpfile|dumpvars|dumpon|dumpoff|dumpall) {
 304         frontend_verilog_yylval.string = new std::string(yytext);
 305         return TOK_ID;
 306 }
 307
 308 "$"(setup|hold|setuphold|removal|recovery|recrem|skew|timeskew|fullskew|nochange) {
 309         if (!specify_mode) REJECT;
 310         frontend_verilog_yylval.string = new std::string(yytext);
 311         return TOK_ID;
 312 }
 313
 314 "$"(info|warning|error|fatal) {
 315         frontend_verilog_yylval.string = new std::string(yytext);
 316         return TOK_ELAB_TASK;
 317 }
 318
 319 "$signed"   { return TOK_TO_SIGNED; }
 320 "$unsigned" { return TOK_TO_UNSIGNED; }
 321
 322 [a-zA-Z_$][a-zA-Z0-9_$]* {
 323         frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
 324         return TOK_ID;
 325 }
 326
 327 [a-zA-Z_$][a-zA-Z0-9_$\.]* {
 328         frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
 329         return TOK_ID;
 330 }
 331
 332 "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {
 333         static bool printed_warning = false;
 334         if (!printed_warning) {
 335                 log_warning("Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"
 336                                 "Yosys does support them but it is recommended to use `ifdef constructs instead!\n");
 337                 printed_warning = true;
 338         }
 339         BEGIN(SYNOPSYS_TRANSLATE_OFF);
 340 }
 341 <SYNOPSYS_TRANSLATE_OFF>.    /* ignore synopsys translate_off body */
 342 <SYNOPSYS_TRANSLATE_OFF>\n   /* ignore synopsys translate_off body */
 343 <SYNOPSYS_TRANSLATE_OFF>"/*"[ \t]*(synopsys|synthesis)[ \t]*"translate_on"[ \t]*"*/" { BEGIN(0); }
 344
 345 "/*"[ \t]*(synopsys|synthesis)[ \t]+ {
 346         BEGIN(SYNOPSYS_FLAGS);
 347 }
 348 <SYNOPSYS_FLAGS>full_case {
 349         static bool printed_warning = false;
 350         if (!printed_warning) {
 351                 log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"
 352                                 "Yosys does support them but it is recommended to use Verilog `full_case' attributes instead!\n");
 353                 printed_warning = true;
 354         }
 355         return TOK_SYNOPSYS_FULL_CASE;
 356 }
 357 <SYNOPSYS_FLAGS>parallel_case {
 358         static bool printed_warning = false;
 359         if (!printed_warning) {
 360                 log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"
 361                                 "Yosys does support them but it is recommended to use Verilog `parallel_case' attributes instead!\n");
 362                 printed_warning = true;
 363         }
 364         return TOK_SYNOPSYS_PARALLEL_CASE;
 365 }
 366 <SYNOPSYS_FLAGS>. /* ignore everything else */
 367 <SYNOPSYS_FLAGS>"*/" { BEGIN(0); }
 368
 369 import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 370         BEGIN(IMPORT_DPI);
 371         return TOK_DPI_FUNCTION;
 372 }
 373
 374 <IMPORT_DPI>[a-zA-Z_$][a-zA-Z0-9_$]* {
 375         frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
 376         return TOK_ID;
 377 }
 378
 379 <IMPORT_DPI>[ \t\r\n] /* ignore whitespaces */
 380
 381 <IMPORT_DPI>";" {
 382         BEGIN(0);
 383         return *yytext;
 384 }
 385
 386 <IMPORT_DPI>. {
 387         return *yytext;
 388 }
 389
 390 "\\"[^ \t\r\n]+ {
 391         frontend_verilog_yylval.string = new std::string(yytext);
 392         return TOK_ID;
 393 }
 394
 395 "(*" { return ATTR_BEGIN; }
 396 "*)" { return ATTR_END; }
 397
 398 "{*"  { return DEFATTR_BEGIN; }
 399 "*}"  { return DEFATTR_END; }
 400
 401 "**" { return OP_POW; }
 402 "||" { return OP_LOR; }
 403 "&&" { return OP_LAND; }
 404 "==" { return OP_EQ; }
 405 "!=" { return OP_NE; }
 406 "<=" { return OP_LE; }
 407 ">=" { return OP_GE; }
 408
 409 "===" { return OP_EQX; }
 410 "!==" { return OP_NEX; }
 411
 412 "~&" { return OP_NAND; }
 413 "~|" { return OP_NOR;  }
 414 "~^" { return OP_XNOR; }
 415 "^~" { return OP_XNOR; }
 416
 417 "<<"  { return OP_SHL; }
 418 ">>"  { return OP_SHR; }
 419 "<<<" { return OP_SSHL; }
 420 ">>>" { return OP_SSHR; }
 421
 422 "::"  { return TOK_PACKAGESEP; }
 423 "++"  { return TOK_INCREMENT; }
 424 "--"  { return TOK_DECREMENT; }
 425
 426 "+:" { return TOK_POS_INDEXED; }
 427 "-:" { return TOK_NEG_INDEXED; }
 428
 429 [-+]?[=*]> {
 430         if (!specify_mode) REJECT;
 431         frontend_verilog_yylval.string = new std::string(yytext);
 432         return TOK_SPECIFY_OPER;
 433 }
 434
 435 "&&&" {
 436         if (!specify_mode) REJECT;
 437         return TOK_SPECIFY_AND;
 438 }
 439
 440 "/*" { BEGIN(COMMENT); }
 441 <COMMENT>.    /* ignore comment body */
 442 <COMMENT>\n   /* ignore comment body */
 443 <COMMENT>"*/" { BEGIN(0); }
 444
 445 [ \t\r\n]               /* ignore whitespaces */
 446 \\[\r\n]                /* ignore continuation sequence */
 447 "//"[^\r\n]*            /* ignore one-line comments */
 448
 449 . { return *yytext; }
 450
 451 %%
 452
 453 // this is a hack to avoid the 'yyinput defined but not used' error msgs
 454 void *frontend_verilog_avoid_input_warnings() {
 455         return (void*)&yyinput;
 456 }
 457