2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The Verilog frontend.
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
29 * A simple lexer for Verilog code. Non-preprocessor compiler directives are
30 * handled here. The preprocessor stuff is handled in preproc.cc. Everything
31 * else is left to the bison parser (see parser.y).
38 // bison generates code using the 'register' storage class specifier
39 #pragma clang diagnostic ignored "-Wdeprecated-register"
42 #include "kernel/log.h"
43 #include "frontends/verilog/verilog_frontend.h"
44 #include "frontends/ast/ast.h"
45 #include "verilog_parser.tab.h"
49 using namespace VERILOG_FRONTEND;
52 namespace VERILOG_FRONTEND {
53 std::vector<std::string> fn_stack;
54 std::vector<int> ln_stack;
58 #define SV_KEYWORD(_tok) \
59 if (sv_mode) return _tok; \
60 log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\
61 "recognized unless read_verilog is called with -sv!\n", yytext, \
62 AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); \
63 frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
66 #define NON_KEYWORD() \
67 frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
70 #define YY_INPUT(buf,result,max_size) \
71 result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
78 %option prefix="frontend_verilog_yy"
82 %x SYNOPSYS_TRANSLATE_OFF
88 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_push "[^\n]* {
89 fn_stack.push_back(current_filename);
90 ln_stack.push_back(frontend_verilog_yyget_lineno());
91 current_filename = yytext+11;
92 if (!current_filename.empty() && current_filename.front() == '"')
93 current_filename = current_filename.substr(1);
94 if (!current_filename.empty() && current_filename.back() == '"')
95 current_filename = current_filename.substr(0, current_filename.size()-1);
96 frontend_verilog_yyset_lineno(0);
99 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_pop"[^\n]*\n {
100 current_filename = fn_stack.back();
102 frontend_verilog_yyset_lineno(ln_stack.back());
106 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`line"[ \t]+[^ \t\r\n]+[ \t]+\"[^ \r\n]+\"[^\r\n]*\n {
107 char *p = yytext + 5;
108 while (*p == ' ' || *p == '\t') p++;
109 frontend_verilog_yyset_lineno(atoi(p));
110 while (*p && *p != ' ' && *p != '\t') p++;
111 while (*p == ' ' || *p == '\t') p++;
112 char *q = *p ? p + 1 : p;
113 while (*q && *q != '"') q++;
114 current_filename = std::string(p).substr(1, q-p-1);
117 "`file_notfound "[^\n]* {
118 log_error("Can't open include file `%s'!\n", yytext + 15);
121 "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
123 "`celldefine"[^\n]* /* ignore `celldefine */
124 "`endcelldefine"[^\n]* /* ignore `endcelldefine */
126 "`default_nettype"[ \t]+[^ \t\r\n/]+ {
128 while (*p != 0 && *p != ' ' && *p != '\t') p++;
129 while (*p == ' ' || *p == '\t') p++;
130 if (!strcmp(p, "none"))
131 VERILOG_FRONTEND::default_nettype_wire = false;
132 else if (!strcmp(p, "wire"))
133 VERILOG_FRONTEND::default_nettype_wire = true;
135 frontend_verilog_yyerror("Unsupported default nettype: %s", p);
138 "`"[a-zA-Z_$][a-zA-Z0-9_$]* {
139 frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
142 "module" { return TOK_MODULE; }
143 "endmodule" { return TOK_ENDMODULE; }
144 "function" { return TOK_FUNCTION; }
145 "endfunction" { return TOK_ENDFUNCTION; }
146 "task" { return TOK_TASK; }
147 "endtask" { return TOK_ENDTASK; }
148 "specify" { return TOK_SPECIFY; }
149 "endspecify" { return TOK_ENDSPECIFY; }
150 "specparam" { return TOK_SPECPARAM; }
151 "package" { SV_KEYWORD(TOK_PACKAGE); }
152 "endpackage" { SV_KEYWORD(TOK_ENDPACKAGE); }
153 "parameter" { return TOK_PARAMETER; }
154 "localparam" { return TOK_LOCALPARAM; }
155 "defparam" { return TOK_DEFPARAM; }
156 "assign" { return TOK_ASSIGN; }
157 "always" { return TOK_ALWAYS; }
158 "initial" { return TOK_INITIAL; }
159 "begin" { return TOK_BEGIN; }
160 "end" { return TOK_END; }
161 "if" { return TOK_IF; }
162 "else" { return TOK_ELSE; }
163 "for" { return TOK_FOR; }
164 "posedge" { return TOK_POSEDGE; }
165 "negedge" { return TOK_NEGEDGE; }
166 "or" { return TOK_OR; }
167 "case" { return TOK_CASE; }
168 "casex" { return TOK_CASEX; }
169 "casez" { return TOK_CASEZ; }
170 "endcase" { return TOK_ENDCASE; }
171 "default" { return TOK_DEFAULT; }
172 "generate" { return TOK_GENERATE; }
173 "endgenerate" { return TOK_ENDGENERATE; }
174 "while" { return TOK_WHILE; }
175 "repeat" { return TOK_REPEAT; }
176 "automatic" { return TOK_AUTOMATIC; }
178 "unique" { SV_KEYWORD(TOK_UNIQUE); }
179 "unique0" { SV_KEYWORD(TOK_UNIQUE); }
180 "priority" { SV_KEYWORD(TOK_PRIORITY); }
182 "always_comb" { SV_KEYWORD(TOK_ALWAYS); }
183 "always_ff" { SV_KEYWORD(TOK_ALWAYS); }
184 "always_latch" { SV_KEYWORD(TOK_ALWAYS); }
186 "assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
187 "assume" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
188 "cover" { if (formal_mode) return TOK_COVER; SV_KEYWORD(TOK_COVER); }
189 "restrict" { if (formal_mode) return TOK_RESTRICT; SV_KEYWORD(TOK_RESTRICT); }
190 "property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
191 "rand" { if (formal_mode) return TOK_RAND; SV_KEYWORD(TOK_RAND); }
192 "const" { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }
193 "checker" { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); }
194 "endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }
195 "logic" { SV_KEYWORD(TOK_REG); }
196 "bit" { SV_KEYWORD(TOK_REG); }
198 "eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
199 "s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
201 "input" { return TOK_INPUT; }
202 "output" { return TOK_OUTPUT; }
203 "inout" { return TOK_INOUT; }
204 "wire" { return TOK_WIRE; }
205 "reg" { return TOK_REG; }
206 "integer" { return TOK_INTEGER; }
207 "signed" { return TOK_SIGNED; }
208 "genvar" { return TOK_GENVAR; }
209 "real" { return TOK_REAL; }
211 "enum" { SV_KEYWORD(TOK_ENUM); }
212 "typedef" { SV_KEYWORD(TOK_TYPEDEF); }
215 frontend_verilog_yylval.string = new std::string(yytext);
219 [0-9]*[ \t]*\'s?[bodhBODH][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
220 frontend_verilog_yylval.string = new std::string(yytext);
224 [0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? {
225 frontend_verilog_yylval.string = new std::string(yytext);
229 [0-9][0-9_]*[eE][-+]?[0-9_]+ {
230 frontend_verilog_yylval.string = new std::string(yytext);
234 \" { BEGIN(STRING); }
235 <STRING>\\. { yymore(); }
238 char *yystr = strdup(yytext);
239 yystr[strlen(yytext) - 1] = 0;
242 if (yystr[i] == '\\' && yystr[i + 1]) {
246 else if (yystr[i] == 't')
248 else if ('0' <= yystr[i] && yystr[i] <= '7') {
249 yystr[i] = yystr[i] - '0';
250 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
251 yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
254 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
255 yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
260 yystr[j++] = yystr[i++];
263 frontend_verilog_yylval.string = new std::string(yystr);
267 <STRING>. { yymore(); }
269 and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 {
270 frontend_verilog_yylval.string = new std::string(yytext);
271 return TOK_PRIMITIVE;
274 supply0 { return TOK_SUPPLY0; }
275 supply1 { return TOK_SUPPLY1; }
277 "$"(display|write|strobe|monitor|time|stop|finish|dumpfile|dumpvars|dumpon|dumpoff|dumpall) {
278 frontend_verilog_yylval.string = new std::string(yytext);
282 "$signed" { return TOK_TO_SIGNED; }
283 "$unsigned" { return TOK_TO_UNSIGNED; }
285 [a-zA-Z_$][a-zA-Z0-9_$]* {
286 frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
290 "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {
291 static bool printed_warning = false;
292 if (!printed_warning) {
293 log_warning("Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"
294 "Yosys does support them but it is recommended to use `ifdef constructs instead!\n");
295 printed_warning = true;
297 BEGIN(SYNOPSYS_TRANSLATE_OFF);
299 <SYNOPSYS_TRANSLATE_OFF>. /* ignore synopsys translate_off body */
300 <SYNOPSYS_TRANSLATE_OFF>\n /* ignore synopsys translate_off body */
301 <SYNOPSYS_TRANSLATE_OFF>"/*"[ \t]*(synopsys|synthesis)[ \t]*"translate_on"[ \t]*"*/" { BEGIN(0); }
303 "/*"[ \t]*(synopsys|synthesis)[ \t]+ {
304 BEGIN(SYNOPSYS_FLAGS);
306 <SYNOPSYS_FLAGS>full_case {
307 static bool printed_warning = false;
308 if (!printed_warning) {
309 log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"
310 "Yosys does support them but it is recommended to use Verilog `full_case' attributes instead!\n");
311 printed_warning = true;
313 return TOK_SYNOPSYS_FULL_CASE;
315 <SYNOPSYS_FLAGS>parallel_case {
316 static bool printed_warning = false;
317 if (!printed_warning) {
318 log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"
319 "Yosys does support them but it is recommended to use Verilog `parallel_case' attributes instead!\n");
320 printed_warning = true;
322 return TOK_SYNOPSYS_PARALLEL_CASE;
324 <SYNOPSYS_FLAGS>. /* ignore everything else */
325 <SYNOPSYS_FLAGS>"*/" { BEGIN(0); }
327 import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
329 return TOK_DPI_FUNCTION;
332 <IMPORT_DPI>[a-zA-Z_$][a-zA-Z0-9_$]* {
333 frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
337 <IMPORT_DPI>[ \t\r\n] /* ignore whitespaces */
349 frontend_verilog_yylval.string = new std::string(yytext);
353 "(*" { return ATTR_BEGIN; }
354 "*)" { return ATTR_END; }
356 "{*" { return DEFATTR_BEGIN; }
357 "*}" { return DEFATTR_END; }
359 "**" { return OP_POW; }
360 "||" { return OP_LOR; }
361 "&&" { return OP_LAND; }
362 "==" { return OP_EQ; }
363 "!=" { return OP_NE; }
364 "<=" { return OP_LE; }
365 ">=" { return OP_GE; }
367 "===" { return OP_EQX; }
368 "!==" { return OP_NEX; }
370 "~&" { return OP_NAND; }
371 "~|" { return OP_NOR; }
372 "~^" { return OP_XNOR; }
373 "^~" { return OP_XNOR; }
375 "<<" { return OP_SHL; }
376 ">>" { return OP_SHR; }
377 "<<<" { return OP_SSHL; }
378 ">>>" { return OP_SSHR; }
380 "::" { return TOK_PACKAGESEP; }
381 "++" { return TOK_INCREMENT; }
382 "--" { return TOK_DECREMENT; }
384 "+:" { return TOK_POS_INDEXED; }
385 "-:" { return TOK_NEG_INDEXED; }
387 "/*" { BEGIN(COMMENT); }
388 <COMMENT>. /* ignore comment body */
389 <COMMENT>\n /* ignore comment body */
390 <COMMENT>"*/" { BEGIN(0); }
392 [ \t\r\n] /* ignore whitespaces */
393 \\[\r\n] /* ignore continuation sequence */
394 "//"[^\r\n]* /* ignore one-line comments */
396 . { return *yytext; }
400 // this is a hack to avoid the 'yyinput defined but not used' error msgs
401 void *frontend_verilog_avoid_input_warnings() {
402 return (void*)&yyinput;