2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The Verilog frontend.
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
29 * A simple lexer for Verilog code. Non-preprocessor compiler directives are
30 * handled here. The preprocessor stuff is handled in preproc.cc. Everything
31 * else is left to the bison parser (see parser.y).
38 // bison generates code using the 'register' storage class specifier
39 #pragma clang diagnostic ignored "-Wdeprecated-register"
42 #include "kernel/log.h"
43 #include "frontends/verilog/verilog_frontend.h"
44 #include "frontends/ast/ast.h"
45 #include "verilog_parser.tab.h"
49 using namespace VERILOG_FRONTEND;
52 namespace VERILOG_FRONTEND {
53 std::vector<std::string> fn_stack;
54 std::vector<int> ln_stack;
58 #define SV_KEYWORD(_tok) \
59 if (sv_mode) return _tok; \
60 log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\
61 "recognized unless read_verilog is called with -sv!\n", yytext, \
62 AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); \
63 frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
66 #define YY_INPUT(buf,result,max_size) \
67 result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
74 %option prefix="frontend_verilog_yy"
78 %x SYNOPSYS_TRANSLATE_OFF
84 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_push "[^\n]* {
85 fn_stack.push_back(current_filename);
86 ln_stack.push_back(frontend_verilog_yyget_lineno());
87 current_filename = yytext+11;
88 if (!current_filename.empty() && current_filename.front() == '"')
89 current_filename = current_filename.substr(1);
90 if (!current_filename.empty() && current_filename.back() == '"')
91 current_filename = current_filename.substr(0, current_filename.size()-1);
92 frontend_verilog_yyset_lineno(0);
95 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_pop"[^\n]*\n {
96 current_filename = fn_stack.back();
98 frontend_verilog_yyset_lineno(ln_stack.back());
102 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`line"[ \t]+[^ \t\r\n]+[ \t]+\"[^ \r\n]+\"[^\r\n]*\n {
103 char *p = yytext + 5;
104 while (*p == ' ' || *p == '\t') p++;
105 frontend_verilog_yyset_lineno(atoi(p));
106 while (*p && *p != ' ' && *p != '\t') p++;
107 while (*p == ' ' || *p == '\t') p++;
108 char *q = *p ? p + 1 : p;
109 while (*q && *q != '"') q++;
110 current_filename = std::string(p).substr(1, q-p-1);
113 "`file_notfound "[^\n]* {
114 log_error("Can't open include file `%s'!\n", yytext + 15);
117 "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
119 "`celldefine"[^\n]* /* ignore `celldefine */
120 "`endcelldefine"[^\n]* /* ignore `endcelldefine */
122 "`default_nettype"[ \t]+[^ \t\r\n/]+ {
124 while (*p != 0 && *p != ' ' && *p != '\t') p++;
125 while (*p == ' ' || *p == '\t') p++;
126 if (!strcmp(p, "none"))
127 VERILOG_FRONTEND::default_nettype_wire = false;
128 else if (!strcmp(p, "wire"))
129 VERILOG_FRONTEND::default_nettype_wire = true;
131 frontend_verilog_yyerror("Unsupported default nettype: %s", p);
134 "`"[a-zA-Z_$][a-zA-Z0-9_$]* {
135 frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
138 "module" { return TOK_MODULE; }
139 "endmodule" { return TOK_ENDMODULE; }
140 "function" { return TOK_FUNCTION; }
141 "endfunction" { return TOK_ENDFUNCTION; }
142 "task" { return TOK_TASK; }
143 "endtask" { return TOK_ENDTASK; }
144 "parameter" { return TOK_PARAMETER; }
145 "localparam" { return TOK_LOCALPARAM; }
146 "defparam" { return TOK_DEFPARAM; }
147 "assign" { return TOK_ASSIGN; }
148 "always" { return TOK_ALWAYS; }
149 "initial" { return TOK_INITIAL; }
150 "begin" { return TOK_BEGIN; }
151 "end" { return TOK_END; }
152 "if" { return TOK_IF; }
153 "else" { return TOK_ELSE; }
154 "for" { return TOK_FOR; }
155 "posedge" { return TOK_POSEDGE; }
156 "negedge" { return TOK_NEGEDGE; }
157 "or" { return TOK_OR; }
158 "case" { return TOK_CASE; }
159 "casex" { return TOK_CASEX; }
160 "casez" { return TOK_CASEZ; }
161 "endcase" { return TOK_ENDCASE; }
162 "default" { return TOK_DEFAULT; }
163 "generate" { return TOK_GENERATE; }
164 "endgenerate" { return TOK_ENDGENERATE; }
165 "while" { return TOK_WHILE; }
166 "repeat" { return TOK_REPEAT; }
168 "always_comb" { SV_KEYWORD(TOK_ALWAYS); }
169 "always_ff" { SV_KEYWORD(TOK_ALWAYS); }
170 "always_latch" { SV_KEYWORD(TOK_ALWAYS); }
172 "assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
173 "assume" { if (formal_mode) return TOK_ASSUME; return TOK_ID; }
174 "property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
175 "logic" { SV_KEYWORD(TOK_REG); }
176 "bit" { SV_KEYWORD(TOK_REG); }
178 "input" { return TOK_INPUT; }
179 "output" { return TOK_OUTPUT; }
180 "inout" { return TOK_INOUT; }
181 "wire" { return TOK_WIRE; }
182 "reg" { return TOK_REG; }
183 "integer" { return TOK_INTEGER; }
184 "signed" { return TOK_SIGNED; }
185 "genvar" { return TOK_GENVAR; }
186 "real" { return TOK_REAL; }
189 frontend_verilog_yylval.string = new std::string(yytext);
193 [0-9]*[ \t]*\'s?[bodhBODH][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
194 frontend_verilog_yylval.string = new std::string(yytext);
198 [0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? {
199 frontend_verilog_yylval.string = new std::string(yytext);
203 [0-9][0-9_]*[eE][-+]?[0-9_]+ {
204 frontend_verilog_yylval.string = new std::string(yytext);
208 \" { BEGIN(STRING); }
209 <STRING>\\. { yymore(); }
212 char *yystr = strdup(yytext);
213 yystr[strlen(yytext) - 1] = 0;
216 if (yystr[i] == '\\' && yystr[i + 1]) {
220 else if (yystr[i] == 't')
222 else if ('0' <= yystr[i] && yystr[i] <= '7') {
223 yystr[i] = yystr[i] - '0';
224 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
225 yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
228 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
229 yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
234 yystr[j++] = yystr[i++];
237 frontend_verilog_yylval.string = new std::string(yystr);
241 <STRING>. { yymore(); }
243 and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 {
244 frontend_verilog_yylval.string = new std::string(yytext);
245 return TOK_PRIMITIVE;
248 supply0 { return TOK_SUPPLY0; }
249 supply1 { return TOK_SUPPLY1; }
251 "$"(display|strobe|monitor|time|stop|finish|dumpfile|dumpvars|dumpon|dumpoff|dumpall) {
252 frontend_verilog_yylval.string = new std::string(yytext);
256 "$signed" { return TOK_TO_SIGNED; }
257 "$unsigned" { return TOK_TO_UNSIGNED; }
259 [a-zA-Z_$][a-zA-Z0-9_$]* {
260 frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
264 "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {
265 static bool printed_warning = false;
266 if (!printed_warning) {
267 log_warning("Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"
268 "Yosys does support them but it is recommended to use `ifdef constructs instead!\n");
269 printed_warning = true;
271 BEGIN(SYNOPSYS_TRANSLATE_OFF);
273 <SYNOPSYS_TRANSLATE_OFF>. /* ignore synopsys translate_off body */
274 <SYNOPSYS_TRANSLATE_OFF>\n /* ignore synopsys translate_off body */
275 <SYNOPSYS_TRANSLATE_OFF>"/*"[ \t]*(synopsys|synthesis)[ \t]*"translate_on"[ \t]*"*/" { BEGIN(0); }
277 "/*"[ \t]*(synopsys|synthesis)[ \t]+ {
278 BEGIN(SYNOPSYS_FLAGS);
280 <SYNOPSYS_FLAGS>full_case {
281 static bool printed_warning = false;
282 if (!printed_warning) {
283 log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"
284 "Yosys does support them but it is recommended to use Verilog `full_case' attributes instead!\n");
285 printed_warning = true;
287 return TOK_SYNOPSYS_FULL_CASE;
289 <SYNOPSYS_FLAGS>parallel_case {
290 static bool printed_warning = false;
291 if (!printed_warning) {
292 log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"
293 "Yosys does support them but it is recommended to use Verilog `parallel_case' attributes instead!\n");
294 printed_warning = true;
296 return TOK_SYNOPSYS_PARALLEL_CASE;
298 <SYNOPSYS_FLAGS>. /* ignore everything else */
299 <SYNOPSYS_FLAGS>"*/" { BEGIN(0); }
301 import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
303 return TOK_DPI_FUNCTION;
306 <IMPORT_DPI>[a-zA-Z_$][a-zA-Z0-9_$]* {
307 frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
311 <IMPORT_DPI>[ \t\r\n] /* ignore whitespaces */
323 frontend_verilog_yylval.string = new std::string(yytext);
327 "(*" { return ATTR_BEGIN; }
328 "*)" { return ATTR_END; }
330 "{*" { return DEFATTR_BEGIN; }
331 "*}" { return DEFATTR_END; }
333 "**" { return OP_POW; }
334 "||" { return OP_LOR; }
335 "&&" { return OP_LAND; }
336 "==" { return OP_EQ; }
337 "!=" { return OP_NE; }
338 "<=" { return OP_LE; }
339 ">=" { return OP_GE; }
341 "===" { return OP_EQX; }
342 "!==" { return OP_NEX; }
344 "~&" { return OP_NAND; }
345 "~|" { return OP_NOR; }
346 "~^" { return OP_XNOR; }
347 "^~" { return OP_XNOR; }
349 "<<" { return OP_SHL; }
350 ">>" { return OP_SHR; }
351 "<<<" { return OP_SSHL; }
352 ">>>" { return OP_SSHR; }
354 "+:" { return TOK_POS_INDEXED; }
355 "-:" { return TOK_NEG_INDEXED; }
357 "/*" { BEGIN(COMMENT); }
358 <COMMENT>. /* ignore comment body */
359 <COMMENT>\n /* ignore comment body */
360 <COMMENT>"*/" { BEGIN(0); }
362 [ \t\r\n] /* ignore whitespaces */
363 \\[\r\n] /* ignore continuation sequence */
364 "//"[^\r\n]* /* ignore one-line comments */
366 "#"\ *[0-9][0-9_]* /* ignore simulation timings */
367 "#"\ *[0-9][0-9_]*\.[0-9][0-9_]* /* ignore simulation timings */
368 "#"\ *[$a-zA-Z_\.][$a-zA-Z_0-9\.]* /* ignore simulation timings */
370 . { return *yytext; }
374 // this is a hack to avoid the 'yyinput defined but not used' error msgs
375 void *frontend_verilog_avoid_input_warnings() {
376 return (void*)&yyinput;