2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The Verilog frontend.
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
29 * A simple lexer for Verilog code. Non-preprocessor compiler directives are
30 * handled here. The preprocessor stuff is handled in preproc.cc. Everything
31 * else is left to the bison parser (see parser.y).
38 // bison generates code using the 'register' storage class specifier
39 #pragma clang diagnostic ignored "-Wdeprecated-register"
42 #include "kernel/log.h"
43 #include "frontends/verilog/verilog_frontend.h"
44 #include "frontends/ast/ast.h"
45 #include "verilog_parser.tab.h"
49 using namespace VERILOG_FRONTEND;
52 namespace VERILOG_FRONTEND {
53 std::vector<std::string> fn_stack;
54 std::vector<int> ln_stack;
58 #define SV_KEYWORD(_tok) \
59 if (sv_mode) return _tok; \
60 log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\
61 "recognized unless read_verilog is called with -sv!\n", yytext, \
62 AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); \
63 frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
66 #define NON_KEYWORD() \
67 frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
70 #define YY_INPUT(buf,result,max_size) \
71 result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
78 %option prefix="frontend_verilog_yy"
82 %x SYNOPSYS_TRANSLATE_OFF
88 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_push "[^\n]* {
89 fn_stack.push_back(current_filename);
90 ln_stack.push_back(frontend_verilog_yyget_lineno());
91 current_filename = yytext+11;
92 if (!current_filename.empty() && current_filename.front() == '"')
93 current_filename = current_filename.substr(1);
94 if (!current_filename.empty() && current_filename.back() == '"')
95 current_filename = current_filename.substr(0, current_filename.size()-1);
96 frontend_verilog_yyset_lineno(0);
99 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_pop"[^\n]*\n {
100 current_filename = fn_stack.back();
102 frontend_verilog_yyset_lineno(ln_stack.back());
106 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`line"[ \t]+[^ \t\r\n]+[ \t]+\"[^ \r\n]+\"[^\r\n]*\n {
107 char *p = yytext + 5;
108 while (*p == ' ' || *p == '\t') p++;
109 frontend_verilog_yyset_lineno(atoi(p));
110 while (*p && *p != ' ' && *p != '\t') p++;
111 while (*p == ' ' || *p == '\t') p++;
112 char *q = *p ? p + 1 : p;
113 while (*q && *q != '"') q++;
114 current_filename = std::string(p).substr(1, q-p-1);
117 "`file_notfound "[^\n]* {
118 log_error("Can't open include file `%s'!\n", yytext + 15);
121 "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
123 "`celldefine"[^\n]* /* ignore `celldefine */
124 "`endcelldefine"[^\n]* /* ignore `endcelldefine */
126 "`default_nettype"[ \t]+[^ \t\r\n/]+ {
128 while (*p != 0 && *p != ' ' && *p != '\t') p++;
129 while (*p == ' ' || *p == '\t') p++;
130 if (!strcmp(p, "none"))
131 VERILOG_FRONTEND::default_nettype_wire = false;
132 else if (!strcmp(p, "wire"))
133 VERILOG_FRONTEND::default_nettype_wire = true;
135 frontend_verilog_yyerror("Unsupported default nettype: %s", p);
138 "`"[a-zA-Z_$][a-zA-Z0-9_$]* {
139 frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
142 "module" { return TOK_MODULE; }
143 "endmodule" { return TOK_ENDMODULE; }
144 "function" { return TOK_FUNCTION; }
145 "endfunction" { return TOK_ENDFUNCTION; }
146 "task" { return TOK_TASK; }
147 "endtask" { return TOK_ENDTASK; }
148 "package" { SV_KEYWORD(TOK_PACKAGE); }
149 "endpackage" { SV_KEYWORD(TOK_ENDPACKAGE); }
150 "parameter" { return TOK_PARAMETER; }
151 "localparam" { return TOK_LOCALPARAM; }
152 "defparam" { return TOK_DEFPARAM; }
153 "assign" { return TOK_ASSIGN; }
154 "always" { return TOK_ALWAYS; }
155 "initial" { return TOK_INITIAL; }
156 "begin" { return TOK_BEGIN; }
157 "end" { return TOK_END; }
158 "if" { return TOK_IF; }
159 "else" { return TOK_ELSE; }
160 "for" { return TOK_FOR; }
161 "posedge" { return TOK_POSEDGE; }
162 "negedge" { return TOK_NEGEDGE; }
163 "or" { return TOK_OR; }
164 "case" { return TOK_CASE; }
165 "casex" { return TOK_CASEX; }
166 "casez" { return TOK_CASEZ; }
167 "endcase" { return TOK_ENDCASE; }
168 "default" { return TOK_DEFAULT; }
169 "generate" { return TOK_GENERATE; }
170 "endgenerate" { return TOK_ENDGENERATE; }
171 "while" { return TOK_WHILE; }
172 "repeat" { return TOK_REPEAT; }
174 "always_comb" { SV_KEYWORD(TOK_ALWAYS); }
175 "always_ff" { SV_KEYWORD(TOK_ALWAYS); }
176 "always_latch" { SV_KEYWORD(TOK_ALWAYS); }
178 "assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
179 "assume" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
180 "cover" { if (formal_mode) return TOK_COVER; SV_KEYWORD(TOK_COVER); }
181 "restrict" { if (formal_mode) return TOK_RESTRICT; SV_KEYWORD(TOK_RESTRICT); }
182 "property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
183 "rand" { if (formal_mode) return TOK_RAND; SV_KEYWORD(TOK_RAND); }
184 "const" { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }
185 "checker" { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); }
186 "endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }
187 "logic" { SV_KEYWORD(TOK_REG); }
188 "bit" { SV_KEYWORD(TOK_REG); }
190 "input" { return TOK_INPUT; }
191 "output" { return TOK_OUTPUT; }
192 "inout" { return TOK_INOUT; }
193 "wire" { return TOK_WIRE; }
194 "reg" { return TOK_REG; }
195 "integer" { return TOK_INTEGER; }
196 "signed" { return TOK_SIGNED; }
197 "genvar" { return TOK_GENVAR; }
198 "real" { return TOK_REAL; }
200 "enum" { SV_KEYWORD(TOK_ENUM); }
201 "typedef" { SV_KEYWORD(TOK_TYPEDEF); }
204 frontend_verilog_yylval.string = new std::string(yytext);
208 [0-9]*[ \t]*\'s?[bodhBODH][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
209 frontend_verilog_yylval.string = new std::string(yytext);
213 [0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? {
214 frontend_verilog_yylval.string = new std::string(yytext);
218 [0-9][0-9_]*[eE][-+]?[0-9_]+ {
219 frontend_verilog_yylval.string = new std::string(yytext);
223 \" { BEGIN(STRING); }
224 <STRING>\\. { yymore(); }
227 char *yystr = strdup(yytext);
228 yystr[strlen(yytext) - 1] = 0;
231 if (yystr[i] == '\\' && yystr[i + 1]) {
235 else if (yystr[i] == 't')
237 else if ('0' <= yystr[i] && yystr[i] <= '7') {
238 yystr[i] = yystr[i] - '0';
239 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
240 yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
243 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
244 yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
249 yystr[j++] = yystr[i++];
252 frontend_verilog_yylval.string = new std::string(yystr);
256 <STRING>. { yymore(); }
258 and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 {
259 frontend_verilog_yylval.string = new std::string(yytext);
260 return TOK_PRIMITIVE;
263 supply0 { return TOK_SUPPLY0; }
264 supply1 { return TOK_SUPPLY1; }
266 "$"(display|write|strobe|monitor|time|stop|finish|dumpfile|dumpvars|dumpon|dumpoff|dumpall) {
267 frontend_verilog_yylval.string = new std::string(yytext);
271 "$signed" { return TOK_TO_SIGNED; }
272 "$unsigned" { return TOK_TO_UNSIGNED; }
274 [a-zA-Z_$][a-zA-Z0-9_$]* {
275 frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
279 "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {
280 static bool printed_warning = false;
281 if (!printed_warning) {
282 log_warning("Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"
283 "Yosys does support them but it is recommended to use `ifdef constructs instead!\n");
284 printed_warning = true;
286 BEGIN(SYNOPSYS_TRANSLATE_OFF);
288 <SYNOPSYS_TRANSLATE_OFF>. /* ignore synopsys translate_off body */
289 <SYNOPSYS_TRANSLATE_OFF>\n /* ignore synopsys translate_off body */
290 <SYNOPSYS_TRANSLATE_OFF>"/*"[ \t]*(synopsys|synthesis)[ \t]*"translate_on"[ \t]*"*/" { BEGIN(0); }
292 "/*"[ \t]*(synopsys|synthesis)[ \t]+ {
293 BEGIN(SYNOPSYS_FLAGS);
295 <SYNOPSYS_FLAGS>full_case {
296 static bool printed_warning = false;
297 if (!printed_warning) {
298 log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"
299 "Yosys does support them but it is recommended to use Verilog `full_case' attributes instead!\n");
300 printed_warning = true;
302 return TOK_SYNOPSYS_FULL_CASE;
304 <SYNOPSYS_FLAGS>parallel_case {
305 static bool printed_warning = false;
306 if (!printed_warning) {
307 log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"
308 "Yosys does support them but it is recommended to use Verilog `parallel_case' attributes instead!\n");
309 printed_warning = true;
311 return TOK_SYNOPSYS_PARALLEL_CASE;
313 <SYNOPSYS_FLAGS>. /* ignore everything else */
314 <SYNOPSYS_FLAGS>"*/" { BEGIN(0); }
316 import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
318 return TOK_DPI_FUNCTION;
321 <IMPORT_DPI>[a-zA-Z_$][a-zA-Z0-9_$]* {
322 frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
326 <IMPORT_DPI>[ \t\r\n] /* ignore whitespaces */
338 frontend_verilog_yylval.string = new std::string(yytext);
342 "(*" { return ATTR_BEGIN; }
343 "*)" { return ATTR_END; }
345 "{*" { return DEFATTR_BEGIN; }
346 "*}" { return DEFATTR_END; }
348 "**" { return OP_POW; }
349 "||" { return OP_LOR; }
350 "&&" { return OP_LAND; }
351 "==" { return OP_EQ; }
352 "!=" { return OP_NE; }
353 "<=" { return OP_LE; }
354 ">=" { return OP_GE; }
356 "===" { return OP_EQX; }
357 "!==" { return OP_NEX; }
359 "~&" { return OP_NAND; }
360 "~|" { return OP_NOR; }
361 "~^" { return OP_XNOR; }
362 "^~" { return OP_XNOR; }
364 "<<" { return OP_SHL; }
365 ">>" { return OP_SHR; }
366 "<<<" { return OP_SSHL; }
367 ">>>" { return OP_SSHR; }
369 "::" { SV_KEYWORD(TOK_PACKAGESEP); }
371 "+:" { return TOK_POS_INDEXED; }
372 "-:" { return TOK_NEG_INDEXED; }
374 "/*" { BEGIN(COMMENT); }
375 <COMMENT>. /* ignore comment body */
376 <COMMENT>\n /* ignore comment body */
377 <COMMENT>"*/" { BEGIN(0); }
379 [ \t\r\n] /* ignore whitespaces */
380 \\[\r\n] /* ignore continuation sequence */
381 "//"[^\r\n]* /* ignore one-line comments */
383 "#"\ *[0-9][0-9_]* /* ignore simulation timings */
384 "#"\ *[0-9][0-9_]*\.[0-9][0-9_]* /* ignore simulation timings */
385 "#"\ *[$a-zA-Z_\.][$a-zA-Z_0-9\.]* /* ignore simulation timings */
387 . { return *yytext; }
391 // this is a hack to avoid the 'yyinput defined but not used' error msgs
392 void *frontend_verilog_avoid_input_warnings() {
393 return (void*)&yyinput;