frontends/verilog/verilog_lexer.l

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The Verilog frontend.
  21  *
  22  *  This frontend is using the AST frontend library (see frontends/ast/).
  23  *  Thus this frontend does not generate RTLIL code directly but creates an
  24  *  AST directly from the Verilog parse tree and then passes this AST to
  25  *  the AST frontend library.
  26  *
  27  *  ---
  28  *
  29  *  A simple lexer for Verilog code. Non-preprocessor compiler directives are
  30  *  handled here. The preprocessor stuff is handled in preproc.cc. Everything
  31  *  else is left to the bison parser (see parser.y).
  32  *
  33  */
  34
  35 %{
  36
  37 #ifdef __clang__
  38 // bison generates code using the 'register' storage class specifier
  39 #pragma clang diagnostic ignored "-Wdeprecated-register"
  40 #endif
  41
  42 #include "kernel/log.h"
  43 #include "verilog_frontend.h"
  44 #include "frontends/ast/ast.h"
  45 #include "verilog_parser.tab.h"
  46
  47 USING_YOSYS_NAMESPACE
  48 using namespace AST;
  49 using namespace VERILOG_FRONTEND;
  50
  51 YOSYS_NAMESPACE_BEGIN
  52 namespace VERILOG_FRONTEND {
  53         std::vector<std::string> fn_stack;
  54         std::vector<int> ln_stack;
  55 }
  56 YOSYS_NAMESPACE_END
  57
  58 #define SV_KEYWORD(_tok) \
  59         if (sv_mode) return _tok; \
  60         log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\
  61                         "recognized unless read_verilog is called with -sv!\n", yytext, \
  62                         AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); \
  63         frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
  64         return TOK_ID;
  65
  66 #define YY_INPUT(buf,result,max_size) \
  67         result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
  68
  69 %}
  70
  71 %option yylineno
  72 %option noyywrap
  73 %option nounput
  74 %option prefix="frontend_verilog_yy"
  75
  76 %x COMMENT
  77 %x STRING
  78 %x SYNOPSYS_TRANSLATE_OFF
  79 %x SYNOPSYS_FLAGS
  80 %x IMPORT_DPI
  81
  82 %%
  83
  84 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_push "[^\n]* {
  85         fn_stack.push_back(current_filename);
  86         ln_stack.push_back(frontend_verilog_yyget_lineno());
  87         current_filename = yytext+11;
  88         frontend_verilog_yyset_lineno(0);
  89 }
  90
  91 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_pop"[^\n]*\n {
  92         current_filename = fn_stack.back();
  93         fn_stack.pop_back();
  94         frontend_verilog_yyset_lineno(ln_stack.back());
  95         ln_stack.pop_back();
  96 }
  97
  98 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`line"[ \t]+[^ \t\r\n]+[ \t]+\"[^ \r\n]+\"[^\r\n]*\n {
  99         char *p = yytext + 5;
 100         while (*p == ' ' || *p == '\t') p++;
 101         frontend_verilog_yyset_lineno(atoi(p));
 102         while (*p && *p != ' ' && *p != '\t') p++;
 103         while (*p == ' ' || *p == '\t') p++;
 104         char *q = *p ? p + 1 : p;
 105         while (*q && *q != '"') q++;
 106         current_filename = std::string(p).substr(1, q-p-1);
 107 }
 108
 109 "`file_notfound "[^\n]* {
 110         log_error("Can't open include file `%s'!\n", yytext + 15);
 111 }
 112
 113 "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
 114
 115 "`default_nettype"[ \t]+[^ \t\r\n/]+ {
 116         char *p = yytext;
 117         while (*p != 0 && *p != ' ' && *p != '\t') p++;
 118         while (*p == ' ' || *p == '\t') p++;
 119         if (!strcmp(p, "none"))
 120                 VERILOG_FRONTEND::default_nettype_wire = false;
 121         else if (!strcmp(p, "wire"))
 122                 VERILOG_FRONTEND::default_nettype_wire = true;
 123         else
 124                 frontend_verilog_yyerror("Unsupported default nettype: %s", p);
 125 }
 126
 127 "`"[a-zA-Z_$][a-zA-Z0-9_$]* {
 128         frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
 129 }
 130
 131 "module"       { return TOK_MODULE; }
 132 "endmodule"    { return TOK_ENDMODULE; }
 133 "function"     { return TOK_FUNCTION; }
 134 "endfunction"  { return TOK_ENDFUNCTION; }
 135 "task"         { return TOK_TASK; }
 136 "endtask"      { return TOK_ENDTASK; }
 137 "parameter"    { return TOK_PARAMETER; }
 138 "localparam"   { return TOK_LOCALPARAM; }
 139 "defparam"     { return TOK_DEFPARAM; }
 140 "assign"       { return TOK_ASSIGN; }
 141 "always"       { return TOK_ALWAYS; }
 142 "initial"      { return TOK_INITIAL; }
 143 "begin"        { return TOK_BEGIN; }
 144 "end"          { return TOK_END; }
 145 "if"           { return TOK_IF; }
 146 "else"         { return TOK_ELSE; }
 147 "for"          { return TOK_FOR; }
 148 "posedge"      { return TOK_POSEDGE; }
 149 "negedge"      { return TOK_NEGEDGE; }
 150 "or"           { return TOK_OR; }
 151 "case"         { return TOK_CASE; }
 152 "casex"        { return TOK_CASEX; }
 153 "casez"        { return TOK_CASEZ; }
 154 "endcase"      { return TOK_ENDCASE; }
 155 "default"      { return TOK_DEFAULT; }
 156 "generate"     { return TOK_GENERATE; }
 157 "endgenerate"  { return TOK_ENDGENERATE; }
 158 "while"        { return TOK_WHILE; }
 159 "repeat"       { return TOK_REPEAT; }
 160
 161 "always_comb"  { SV_KEYWORD(TOK_ALWAYS); }
 162 "always_ff"    { SV_KEYWORD(TOK_ALWAYS); }
 163 "always_latch" { SV_KEYWORD(TOK_ALWAYS); }
 164
 165 "assert"   { SV_KEYWORD(TOK_ASSERT); }
 166 "property" { SV_KEYWORD(TOK_PROPERTY); }
 167 "logic"    { SV_KEYWORD(TOK_REG); }
 168 "bit"      { SV_KEYWORD(TOK_REG); }
 169
 170 "input"   { return TOK_INPUT; }
 171 "output"  { return TOK_OUTPUT; }
 172 "inout"   { return TOK_INOUT; }
 173 "wire"    { return TOK_WIRE; }
 174 "reg"     { return TOK_REG; }
 175 "integer" { return TOK_INTEGER; }
 176 "signed"  { return TOK_SIGNED; }
 177 "genvar"  { return TOK_GENVAR; }
 178 "real"    { return TOK_REAL; }
 179
 180 [0-9]+ {
 181         frontend_verilog_yylval.string = new std::string(yytext);
 182         return TOK_CONST;
 183 }
 184
 185 [0-9]*[ \t]*\'s?[bodh][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
 186         frontend_verilog_yylval.string = new std::string(yytext);
 187         return TOK_CONST;
 188 }
 189
 190 [0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? {
 191         frontend_verilog_yylval.string = new std::string(yytext);
 192         return TOK_REALVAL;
 193 }
 194
 195 [0-9][0-9_]*[eE][-+]?[0-9_]+ {
 196         frontend_verilog_yylval.string = new std::string(yytext);
 197         return TOK_REALVAL;
 198 }
 199
 200 \"              { BEGIN(STRING); }
 201 <STRING>\\.     { yymore(); }
 202 <STRING>\"      {
 203         BEGIN(0);
 204         char *yystr = strdup(yytext);
 205         yystr[strlen(yytext) - 1] = 0;
 206         int i = 0, j = 0;
 207         while (yystr[i]) {
 208                 if (yystr[i] == '\\' && yystr[i + 1]) {
 209                         i++;
 210                         if (yystr[i] == 'n')
 211                                 yystr[i] = '\n';
 212                         else if (yystr[i] == 't')
 213                                 yystr[i] = '\t';
 214                         else if ('0' <= yystr[i] && yystr[i] <= '7') {
 215                                 yystr[i] = yystr[i] - '0';
 216                                 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
 217                                         yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
 218                                         i++;
 219                                 }
 220                                 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
 221                                         yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
 222                                         i++;
 223                                 }
 224                         }
 225                 }
 226                 yystr[j++] = yystr[i++];
 227         }
 228         yystr[j] = 0;
 229         frontend_verilog_yylval.string = new std::string(yystr);
 230         free(yystr);
 231         return TOK_STRING;
 232 }
 233 <STRING>.       { yymore(); }
 234
 235 and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 {
 236         frontend_verilog_yylval.string = new std::string(yytext);
 237         return TOK_PRIMITIVE;
 238 }
 239
 240 supply0 { return TOK_SUPPLY0; }
 241 supply1 { return TOK_SUPPLY1; }
 242
 243 "$"(display|time|stop|finish) {
 244         frontend_verilog_yylval.string = new std::string(yytext);
 245         return TOK_ID;
 246 }
 247
 248 "$signed"   { return TOK_TO_SIGNED; }
 249 "$unsigned" { return TOK_TO_UNSIGNED; }
 250
 251 [a-zA-Z_$][a-zA-Z0-9_$]* {
 252         frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
 253         return TOK_ID;
 254 }
 255
 256 "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {
 257         log("Warning: Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n");
 258         log("It is strongly suggested to use `ifdef constructs instead!\n");
 259         BEGIN(SYNOPSYS_TRANSLATE_OFF);
 260 }
 261 <SYNOPSYS_TRANSLATE_OFF>.    /* ignore synopsys translate_off body */
 262 <SYNOPSYS_TRANSLATE_OFF>\n   /* ignore synopsys translate_off body */
 263 <SYNOPSYS_TRANSLATE_OFF>"/*"[ \t]*(synopsys|synthesis)[ \t]*"translate_on"[ \t]*"*/" { BEGIN(0); }
 264
 265 "/*"[ \t]*(synopsys|synthesis)[ \t]+ {
 266         BEGIN(SYNOPSYS_FLAGS);
 267 }
 268 <SYNOPSYS_FLAGS>full_case {
 269         log("Warning: Found one of those horrible `(synopsys|synthesis) full_case' comments.\n");
 270         log("It is strongly suggested to use verilog x-values and default branches instead!\n");
 271         return TOK_SYNOPSYS_FULL_CASE;
 272 }
 273 <SYNOPSYS_FLAGS>parallel_case {
 274         log("Warning: Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n");
 275         log("It is strongly suggested to use verilog `parallel_case' attributes instead!\n");
 276         return TOK_SYNOPSYS_PARALLEL_CASE;
 277 }
 278 <SYNOPSYS_FLAGS>. /* ignore everything else */
 279 <SYNOPSYS_FLAGS>"*/" { BEGIN(0); }
 280
 281 import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 282         BEGIN(IMPORT_DPI);
 283         return TOK_DPI_FUNCTION;
 284 }
 285
 286 <IMPORT_DPI>[a-zA-Z_$][a-zA-Z0-9_$]* {
 287         frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
 288         return TOK_ID;
 289 }
 290
 291 <IMPORT_DPI>[ \t\r\n] /* ignore whitespaces */
 292
 293 <IMPORT_DPI>";" {
 294         BEGIN(0);
 295         return *yytext;
 296 }
 297
 298 <IMPORT_DPI>. {
 299         return *yytext;
 300 }
 301
 302 "\\"[^ \t\r\n]+ {
 303         frontend_verilog_yylval.string = new std::string(yytext);
 304         return TOK_ID;
 305 }
 306
 307 "(*" { return ATTR_BEGIN; }
 308 "*)" { return ATTR_END; }
 309
 310 "{*"  { return DEFATTR_BEGIN; }
 311 "*}"  { return DEFATTR_END; }
 312
 313 "**" { return OP_POW; }
 314 "||" { return OP_LOR; }
 315 "&&" { return OP_LAND; }
 316 "==" { return OP_EQ; }
 317 "!=" { return OP_NE; }
 318 "<=" { return OP_LE; }
 319 ">=" { return OP_GE; }
 320
 321 "===" { return OP_EQX; }
 322 "!==" { return OP_NEX; }
 323
 324 "~&" { return OP_NAND; }
 325 "~|" { return OP_NOR;  }
 326 "~^" { return OP_XNOR; }
 327 "^~" { return OP_XNOR; }
 328
 329 "<<"  { return OP_SHL; }
 330 ">>"  { return OP_SHR; }
 331 "<<<" { return OP_SSHL; }
 332 ">>>" { return OP_SSHR; }
 333
 334 "+:" { return TOK_POS_INDEXED; }
 335 "-:" { return TOK_NEG_INDEXED; }
 336
 337 "/*" { BEGIN(COMMENT); }
 338 <COMMENT>.    /* ignore comment body */
 339 <COMMENT>\n   /* ignore comment body */
 340 <COMMENT>"*/" { BEGIN(0); }
 341
 342 [ \t\r\n]               /* ignore whitespaces */
 343 \\[\r\n]                /* ignore continuation sequence */
 344 "//"[^\r\n]*            /* ignore one-line comments */
 345 "#"[$a-zA-Z_0-9\.]+     /* ignore simulation timings */
 346
 347 . { return *yytext; }
 348
 349 %%
 350
 351 // this is a hack to avoid the 'yyinput defined but not used' error msgs
 352 void *frontend_verilog_avoid_input_warnings() {
 353         return (void*)&yyinput;
 354 }
 355