frontends/verilog/verilog_lexer.l

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The Verilog frontend.
  21  *
  22  *  This frontend is using the AST frontend library (see frontends/ast/).
  23  *  Thus this frontend does not generate RTLIL code directly but creates an
  24  *  AST directly from the Verilog parse tree and then passes this AST to
  25  *  the AST frontend library.
  26  *
  27  *  ---
  28  *
  29  *  A simple lexer for Verilog code. Non-preprocessor compiler directives are
  30  *  handled here. The preprocessor stuff is handled in preproc.cc. Everything
  31  *  else is left to the bison parser (see parser.y).
  32  *
  33  */
  34
  35 %{
  36
  37 #ifdef __clang__
  38 // bison generates code using the 'register' storage class specifier
  39 #pragma clang diagnostic ignored "-Wdeprecated-register"
  40 #endif
  41
  42 #include "kernel/log.h"
  43 #include "frontends/verilog/verilog_frontend.h"
  44 #include "frontends/ast/ast.h"
  45 #include "verilog_parser.tab.h"
  46
  47 USING_YOSYS_NAMESPACE
  48 using namespace AST;
  49 using namespace VERILOG_FRONTEND;
  50
  51 YOSYS_NAMESPACE_BEGIN
  52 namespace VERILOG_FRONTEND {
  53         std::vector<std::string> fn_stack;
  54         std::vector<int> ln_stack;
  55 }
  56 YOSYS_NAMESPACE_END
  57
  58 #define SV_KEYWORD(_tok) \
  59         if (sv_mode) return _tok; \
  60         log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\
  61                         "recognized unless read_verilog is called with -sv!\n", yytext, \
  62                         AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); \
  63         frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
  64         return TOK_ID;
  65
  66 #define NON_KEYWORD() \
  67         frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
  68         return TOK_ID;
  69
  70 #define YY_INPUT(buf,result,max_size) \
  71         result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
  72
  73 %}
  74
  75 %option yylineno
  76 %option noyywrap
  77 %option nounput
  78 %option prefix="frontend_verilog_yy"
  79
  80 %x COMMENT
  81 %x STRING
  82 %x SYNOPSYS_TRANSLATE_OFF
  83 %x SYNOPSYS_FLAGS
  84 %x IMPORT_DPI
  85
  86 %%
  87
  88 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_push "[^\n]* {
  89         fn_stack.push_back(current_filename);
  90         ln_stack.push_back(frontend_verilog_yyget_lineno());
  91         current_filename = yytext+11;
  92         if (!current_filename.empty() && current_filename.front() == '"')
  93                 current_filename = current_filename.substr(1);
  94         if (!current_filename.empty() && current_filename.back() == '"')
  95                 current_filename = current_filename.substr(0, current_filename.size()-1);
  96         frontend_verilog_yyset_lineno(0);
  97 }
  98
  99 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_pop"[^\n]*\n {
 100         current_filename = fn_stack.back();
 101         fn_stack.pop_back();
 102         frontend_verilog_yyset_lineno(ln_stack.back());
 103         ln_stack.pop_back();
 104 }
 105
 106 <INITIAL,SYNOPSYS_TRANSLATE_OFF>"`line"[ \t]+[^ \t\r\n]+[ \t]+\"[^ \r\n]+\"[^\r\n]*\n {
 107         char *p = yytext + 5;
 108         while (*p == ' ' || *p == '\t') p++;
 109         frontend_verilog_yyset_lineno(atoi(p));
 110         while (*p && *p != ' ' && *p != '\t') p++;
 111         while (*p == ' ' || *p == '\t') p++;
 112         char *q = *p ? p + 1 : p;
 113         while (*q && *q != '"') q++;
 114         current_filename = std::string(p).substr(1, q-p-1);
 115 }
 116
 117 "`file_notfound "[^\n]* {
 118         log_error("Can't open include file `%s'!\n", yytext + 15);
 119 }
 120
 121 "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
 122
 123 "`celldefine"[^\n]* /* ignore `celldefine */
 124 "`endcelldefine"[^\n]* /* ignore `endcelldefine */
 125
 126 "`default_nettype"[ \t]+[^ \t\r\n/]+ {
 127         char *p = yytext;
 128         while (*p != 0 && *p != ' ' && *p != '\t') p++;
 129         while (*p == ' ' || *p == '\t') p++;
 130         if (!strcmp(p, "none"))
 131                 VERILOG_FRONTEND::default_nettype_wire = false;
 132         else if (!strcmp(p, "wire"))
 133                 VERILOG_FRONTEND::default_nettype_wire = true;
 134         else
 135                 frontend_verilog_yyerror("Unsupported default nettype: %s", p);
 136 }
 137
 138 "`"[a-zA-Z_$][a-zA-Z0-9_$]* {
 139         frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
 140 }
 141
 142 "module"       { return TOK_MODULE; }
 143 "endmodule"    { return TOK_ENDMODULE; }
 144 "function"     { return TOK_FUNCTION; }
 145 "endfunction"  { return TOK_ENDFUNCTION; }
 146 "task"         { return TOK_TASK; }
 147 "endtask"      { return TOK_ENDTASK; }
 148 "package"      { SV_KEYWORD(TOK_PACKAGE); }
 149 "endpackage"   { SV_KEYWORD(TOK_ENDPACKAGE); }
 150 "parameter"    { return TOK_PARAMETER; }
 151 "localparam"   { return TOK_LOCALPARAM; }
 152 "defparam"     { return TOK_DEFPARAM; }
 153 "assign"       { return TOK_ASSIGN; }
 154 "always"       { return TOK_ALWAYS; }
 155 "initial"      { return TOK_INITIAL; }
 156 "begin"        { return TOK_BEGIN; }
 157 "end"          { return TOK_END; }
 158 "if"           { return TOK_IF; }
 159 "else"         { return TOK_ELSE; }
 160 "for"          { return TOK_FOR; }
 161 "posedge"      { return TOK_POSEDGE; }
 162 "negedge"      { return TOK_NEGEDGE; }
 163 "or"           { return TOK_OR; }
 164 "case"         { return TOK_CASE; }
 165 "casex"        { return TOK_CASEX; }
 166 "casez"        { return TOK_CASEZ; }
 167 "endcase"      { return TOK_ENDCASE; }
 168 "default"      { return TOK_DEFAULT; }
 169 "generate"     { return TOK_GENERATE; }
 170 "endgenerate"  { return TOK_ENDGENERATE; }
 171 "while"        { return TOK_WHILE; }
 172 "repeat"       { return TOK_REPEAT; }
 173
 174 "always_comb"  { SV_KEYWORD(TOK_ALWAYS); }
 175 "always_ff"    { SV_KEYWORD(TOK_ALWAYS); }
 176 "always_latch" { SV_KEYWORD(TOK_ALWAYS); }
 177
 178 "assert"   { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
 179 "assume"   { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
 180 "restrict" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
 181 "predict"  { if (formal_mode) return TOK_PREDICT; NON_KEYWORD(); }
 182 "property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
 183 "logic"    { SV_KEYWORD(TOK_REG); }
 184 "bit"      { SV_KEYWORD(TOK_REG); }
 185
 186 "input"   { return TOK_INPUT; }
 187 "output"  { return TOK_OUTPUT; }
 188 "inout"   { return TOK_INOUT; }
 189 "wire"    { return TOK_WIRE; }
 190 "reg"     { return TOK_REG; }
 191 "integer" { return TOK_INTEGER; }
 192 "signed"  { return TOK_SIGNED; }
 193 "genvar"  { return TOK_GENVAR; }
 194 "real"    { return TOK_REAL; }
 195
 196 [0-9][0-9_]* {
 197         frontend_verilog_yylval.string = new std::string(yytext);
 198         return TOK_CONST;
 199 }
 200
 201 [0-9]*[ \t]*\'s?[bodhBODH][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
 202         frontend_verilog_yylval.string = new std::string(yytext);
 203         return TOK_CONST;
 204 }
 205
 206 [0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? {
 207         frontend_verilog_yylval.string = new std::string(yytext);
 208         return TOK_REALVAL;
 209 }
 210
 211 [0-9][0-9_]*[eE][-+]?[0-9_]+ {
 212         frontend_verilog_yylval.string = new std::string(yytext);
 213         return TOK_REALVAL;
 214 }
 215
 216 \"              { BEGIN(STRING); }
 217 <STRING>\\.     { yymore(); }
 218 <STRING>\"      {
 219         BEGIN(0);
 220         char *yystr = strdup(yytext);
 221         yystr[strlen(yytext) - 1] = 0;
 222         int i = 0, j = 0;
 223         while (yystr[i]) {
 224                 if (yystr[i] == '\\' && yystr[i + 1]) {
 225                         i++;
 226                         if (yystr[i] == 'n')
 227                                 yystr[i] = '\n';
 228                         else if (yystr[i] == 't')
 229                                 yystr[i] = '\t';
 230                         else if ('0' <= yystr[i] && yystr[i] <= '7') {
 231                                 yystr[i] = yystr[i] - '0';
 232                                 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
 233                                         yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
 234                                         i++;
 235                                 }
 236                                 if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
 237                                         yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
 238                                         i++;
 239                                 }
 240                         }
 241                 }
 242                 yystr[j++] = yystr[i++];
 243         }
 244         yystr[j] = 0;
 245         frontend_verilog_yylval.string = new std::string(yystr);
 246         free(yystr);
 247         return TOK_STRING;
 248 }
 249 <STRING>.       { yymore(); }
 250
 251 and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 {
 252         frontend_verilog_yylval.string = new std::string(yytext);
 253         return TOK_PRIMITIVE;
 254 }
 255
 256 supply0 { return TOK_SUPPLY0; }
 257 supply1 { return TOK_SUPPLY1; }
 258
 259 "$"(display|write|strobe|monitor|time|stop|finish|dumpfile|dumpvars|dumpon|dumpoff|dumpall) {
 260         frontend_verilog_yylval.string = new std::string(yytext);
 261         return TOK_ID;
 262 }
 263
 264 "$signed"   { return TOK_TO_SIGNED; }
 265 "$unsigned" { return TOK_TO_UNSIGNED; }
 266
 267 [a-zA-Z_$][a-zA-Z0-9_$]* {
 268         frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
 269         return TOK_ID;
 270 }
 271
 272 "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {
 273         static bool printed_warning = false;
 274         if (!printed_warning) {
 275                 log_warning("Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"
 276                                 "Yosys does support them but it is recommended to use `ifdef constructs instead!\n");
 277                 printed_warning = true;
 278         }
 279         BEGIN(SYNOPSYS_TRANSLATE_OFF);
 280 }
 281 <SYNOPSYS_TRANSLATE_OFF>.    /* ignore synopsys translate_off body */
 282 <SYNOPSYS_TRANSLATE_OFF>\n   /* ignore synopsys translate_off body */
 283 <SYNOPSYS_TRANSLATE_OFF>"/*"[ \t]*(synopsys|synthesis)[ \t]*"translate_on"[ \t]*"*/" { BEGIN(0); }
 284
 285 "/*"[ \t]*(synopsys|synthesis)[ \t]+ {
 286         BEGIN(SYNOPSYS_FLAGS);
 287 }
 288 <SYNOPSYS_FLAGS>full_case {
 289         static bool printed_warning = false;
 290         if (!printed_warning) {
 291                 log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"
 292                                 "Yosys does support them but it is recommended to use Verilog `full_case' attributes instead!\n");
 293                 printed_warning = true;
 294         }
 295         return TOK_SYNOPSYS_FULL_CASE;
 296 }
 297 <SYNOPSYS_FLAGS>parallel_case {
 298         static bool printed_warning = false;
 299         if (!printed_warning) {
 300                 log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"
 301                                 "Yosys does support them but it is recommended to use Verilog `parallel_case' attributes instead!\n");
 302                 printed_warning = true;
 303         }
 304         return TOK_SYNOPSYS_PARALLEL_CASE;
 305 }
 306 <SYNOPSYS_FLAGS>. /* ignore everything else */
 307 <SYNOPSYS_FLAGS>"*/" { BEGIN(0); }
 308
 309 import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 310         BEGIN(IMPORT_DPI);
 311         return TOK_DPI_FUNCTION;
 312 }
 313
 314 <IMPORT_DPI>[a-zA-Z_$][a-zA-Z0-9_$]* {
 315         frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
 316         return TOK_ID;
 317 }
 318
 319 <IMPORT_DPI>[ \t\r\n] /* ignore whitespaces */
 320
 321 <IMPORT_DPI>";" {
 322         BEGIN(0);
 323         return *yytext;
 324 }
 325
 326 <IMPORT_DPI>. {
 327         return *yytext;
 328 }
 329
 330 "\\"[^ \t\r\n]+ {
 331         frontend_verilog_yylval.string = new std::string(yytext);
 332         return TOK_ID;
 333 }
 334
 335 "(*" { return ATTR_BEGIN; }
 336 "*)" { return ATTR_END; }
 337
 338 "{*"  { return DEFATTR_BEGIN; }
 339 "*}"  { return DEFATTR_END; }
 340
 341 "**" { return OP_POW; }
 342 "||" { return OP_LOR; }
 343 "&&" { return OP_LAND; }
 344 "==" { return OP_EQ; }
 345 "!=" { return OP_NE; }
 346 "<=" { return OP_LE; }
 347 ">=" { return OP_GE; }
 348
 349 "===" { return OP_EQX; }
 350 "!==" { return OP_NEX; }
 351
 352 "~&" { return OP_NAND; }
 353 "~|" { return OP_NOR;  }
 354 "~^" { return OP_XNOR; }
 355 "^~" { return OP_XNOR; }
 356
 357 "<<"  { return OP_SHL; }
 358 ">>"  { return OP_SHR; }
 359 "<<<" { return OP_SSHL; }
 360 ">>>" { return OP_SSHR; }
 361
 362 "::"  { SV_KEYWORD(TOK_PACKAGESEP); }
 363
 364 "+:" { return TOK_POS_INDEXED; }
 365 "-:" { return TOK_NEG_INDEXED; }
 366
 367 "/*" { BEGIN(COMMENT); }
 368 <COMMENT>.    /* ignore comment body */
 369 <COMMENT>\n   /* ignore comment body */
 370 <COMMENT>"*/" { BEGIN(0); }
 371
 372 [ \t\r\n]               /* ignore whitespaces */
 373 \\[\r\n]                /* ignore continuation sequence */
 374 "//"[^\r\n]*            /* ignore one-line comments */
 375
 376 "#"\ *[0-9][0-9_]*                      /* ignore simulation timings */
 377 "#"\ *[0-9][0-9_]*\.[0-9][0-9_]*        /* ignore simulation timings */
 378 "#"\ *[$a-zA-Z_\.][$a-zA-Z_0-9\.]*      /* ignore simulation timings */
 379
 380 . { return *yytext; }
 381
 382 %%
 383
 384 // this is a hack to avoid the 'yyinput defined but not used' error msgs
 385 void *frontend_verilog_avoid_input_warnings() {
 386         return (void*)&yyinput;
 387 }
 388