390ef07e9e196d1a0a16527badb855b8d0949448
[yosys.git] / frontends / verilog / verilog_parser.y
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * The Verilog frontend.
21 *
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
26 *
27 * ---
28 *
29 * This is the actual bison parser for Verilog code. The AST ist created directly
30 * from the bison reduce functions here. Note that this code uses a few global
31 * variables to hold the state of the AST generator and therefore this parser is
32 * not reentrant.
33 *
34 */
35
36 %{
37 #include <list>
38 #include <stack>
39 #include <string.h>
40 #include "frontends/verilog/verilog_frontend.h"
41 #include "frontends/verilog/verilog_parser.tab.hh"
42 #include "kernel/log.h"
43
44 #define YYLEX_PARAM &yylval, &yylloc
45
46 USING_YOSYS_NAMESPACE
47 using namespace AST;
48 using namespace VERILOG_FRONTEND;
49
50 YOSYS_NAMESPACE_BEGIN
51 namespace VERILOG_FRONTEND {
52 int port_counter;
53 dict<std::string, int> port_stubs;
54 dict<IdString, AstNode*> *attr_list, default_attr_list;
55 std::stack<dict<IdString, AstNode*> *> attr_list_stack;
56 dict<IdString, AstNode*> *albuf;
57 std::vector<UserTypeMap*> user_type_stack;
58 dict<std::string, AstNode*> pkg_user_types;
59 std::vector<AstNode*> ast_stack;
60 struct AstNode *astbuf1, *astbuf2, *astbuf3;
61 struct AstNode *current_function_or_task;
62 struct AstNode *current_ast, *current_ast_mod;
63 int current_function_or_task_port_id;
64 std::vector<char> case_type_stack;
65 bool do_not_require_port_stubs;
66 bool default_nettype_wire;
67 bool sv_mode, formal_mode, lib_mode, specify_mode;
68 bool noassert_mode, noassume_mode, norestrict_mode;
69 bool assume_asserts_mode, assert_assumes_mode;
70 bool current_wire_rand, current_wire_const;
71 bool current_modport_input, current_modport_output;
72 std::istream *lexin;
73 }
74 YOSYS_NAMESPACE_END
75
76 #define SET_AST_NODE_LOC(WHICH, BEGIN, END) \
77 do { (WHICH)->location.first_line = (BEGIN).first_line; \
78 (WHICH)->location.first_column = (BEGIN).first_column; \
79 (WHICH)->location.last_line = (END).last_line; \
80 (WHICH)->location.last_column = (END).last_column; } while(0)
81
82 #define SET_RULE_LOC(LHS, BEGIN, END) \
83 do { (LHS).first_line = (BEGIN).first_line; \
84 (LHS).first_column = (BEGIN).first_column; \
85 (LHS).last_line = (END).last_line; \
86 (LHS).last_column = (END).last_column; } while(0)
87
88 int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
89
90 static void append_attr(AstNode *ast, dict<IdString, AstNode*> *al)
91 {
92 for (auto &it : *al) {
93 if (ast->attributes.count(it.first) > 0)
94 delete ast->attributes[it.first];
95 ast->attributes[it.first] = it.second;
96 }
97 delete al;
98 }
99
100 static void append_attr_clone(AstNode *ast, dict<IdString, AstNode*> *al)
101 {
102 for (auto &it : *al) {
103 if (ast->attributes.count(it.first) > 0)
104 delete ast->attributes[it.first];
105 ast->attributes[it.first] = it.second->clone();
106 }
107 }
108
109 static void free_attr(dict<IdString, AstNode*> *al)
110 {
111 for (auto &it : *al)
112 delete it.second;
113 delete al;
114 }
115
116 struct specify_target {
117 char polarity_op;
118 AstNode *dst, *dat;
119 };
120
121 struct specify_triple {
122 AstNode *t_min, *t_avg, *t_max;
123 };
124
125 struct specify_rise_fall {
126 specify_triple rise;
127 specify_triple fall;
128 };
129
130 static void addTypedefNode(std::string *name, AstNode *node)
131 {
132 log_assert(node);
133 auto *tnode = new AstNode(AST_TYPEDEF, node);
134 tnode->str = *name;
135 auto user_types = user_type_stack.back();
136 (*user_types)[*name] = tnode;
137 if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {
138 // typedef inside a package so we need the qualified name
139 auto qname = current_ast_mod->str + "::" + (*name).substr(1);
140 pkg_user_types[qname] = tnode;
141 }
142 delete name;
143 ast_stack.back()->children.push_back(tnode);
144 }
145
146 static void enterTypeScope()
147 {
148 auto user_types = new UserTypeMap();
149 user_type_stack.push_back(user_types);
150 }
151
152 static void exitTypeScope()
153 {
154 user_type_stack.pop_back();
155 }
156
157 static bool isInLocalScope(const std::string *name)
158 {
159 // tests if a name was declared in the current block scope
160 auto user_types = user_type_stack.back();
161 return (user_types->count(*name) > 0);
162 }
163
164 static AstNode *getTypeDefinitionNode(std::string type_name)
165 {
166 // return the definition nodes from the typedef statement
167 auto user_types = user_type_stack.back();
168 log_assert(user_types->count(type_name) > 0);
169 auto typedef_node = (*user_types)[type_name];
170 log_assert(typedef_node->type == AST_TYPEDEF);
171 return typedef_node->children[0];
172 }
173
174 static AstNode *copyTypeDefinition(std::string type_name)
175 {
176 // return a copy of the template from a typedef definition
177 auto typedef_node = getTypeDefinitionNode(type_name);
178 return typedef_node->clone();
179 }
180
181 static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
182 {
183 auto range = new AstNode(AST_RANGE);
184 range->children.push_back(AstNode::mkconst_int(msb, true));
185 range->children.push_back(AstNode::mkconst_int(lsb, true));
186 range->is_signed = isSigned;
187 return range;
188 }
189
190 static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned = true)
191 {
192 auto range = makeRange(msb, lsb, isSigned);
193 parent->children.push_back(range);
194 }
195
196 static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
197 {
198 if (type_node->range_left >= 0 && type_node->range_right >= 0) {
199 // type already restricts the range
200 if (range_node) {
201 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
202 }
203 else {
204 range_node = makeRange(type_node->range_left, type_node->range_right, false);
205 }
206 }
207 if (range_node && range_node->children.size() != 2) {
208 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
209 }
210 return range_node;
211 }
212
213 static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
214 {
215 node->type = AST_MEMORY;
216 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
217 // SV array size [n], rewrite as [n-1:0]
218 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
219 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
220 }
221 node->children.push_back(rangeNode);
222 }
223
224 %}
225
226 %define api.prefix {frontend_verilog_yy}
227 %define api.pure
228
229 /* The union is defined in the header, so we need to provide all the
230 * includes it requires
231 */
232 %code requires {
233 #include <map>
234 #include <string>
235 #include "frontends/verilog/verilog_frontend.h"
236 }
237
238 %union {
239 std::string *string;
240 struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
241 YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
242 struct specify_target *specify_target_ptr;
243 struct specify_triple *specify_triple_ptr;
244 struct specify_rise_fall *specify_rise_fall_ptr;
245 bool boolean;
246 char ch;
247 }
248
249 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
250 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
251 %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL
252 %token <string> TOK_USER_TYPE TOK_PKG_USER_TYPE
253 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
254 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
255 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
256 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
257 %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
258 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
259 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_PLUS_ASSIGN TOK_ALWAYS TOK_INITIAL
260 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
261 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
262 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
263 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
264 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
265 %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
266 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
267 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
268 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
269 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
270 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
271 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
272 %token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_UNION
273 %token TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AND_ASSIGN TOK_SUB_ASSIGN
274
275 %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
276 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
277 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
278 %type <string> type_name
279 %type <ast> opt_enum_init enum_type struct_type non_wire_data_type
280 %type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
281 %type <al> attr case_attr
282 %type <ast> struct_union
283
284 %type <specify_target_ptr> specify_target
285 %type <specify_triple_ptr> specify_triple specify_opt_triple
286 %type <specify_rise_fall_ptr> specify_rise_fall
287 %type <ast> specify_if specify_condition
288 %type <ch> specify_edge
289
290 // operator precedence from low to high
291 %left OP_LOR
292 %left OP_LAND
293 %left '|' OP_NOR
294 %left '^' OP_XNOR
295 %left '&' OP_NAND
296 %left OP_EQ OP_NE OP_EQX OP_NEX
297 %left '<' OP_LE OP_GE '>'
298 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
299 %left '+' '-'
300 %left '*' '/' '%'
301 %left OP_POW
302 %left OP_CAST
303 %right UNARY_OPS
304
305 %define parse.error verbose
306 %define parse.lac full
307
308 %nonassoc FAKE_THEN
309 %nonassoc TOK_ELSE
310
311 %debug
312 %locations
313
314 %%
315
316 input: {
317 ast_stack.clear();
318 ast_stack.push_back(current_ast);
319 } design {
320 ast_stack.pop_back();
321 log_assert(GetSize(ast_stack) == 0);
322 for (auto &it : default_attr_list)
323 delete it.second;
324 default_attr_list.clear();
325 };
326
327 design:
328 module design |
329 defattr design |
330 task_func_decl design |
331 param_decl design |
332 localparam_decl design |
333 typedef_decl design |
334 package design |
335 interface design |
336 %empty;
337
338 attr:
339 {
340 if (attr_list != nullptr)
341 attr_list_stack.push(attr_list);
342 attr_list = new dict<IdString, AstNode*>;
343 for (auto &it : default_attr_list)
344 (*attr_list)[it.first] = it.second->clone();
345 } attr_opt {
346 $$ = attr_list;
347 if (!attr_list_stack.empty()) {
348 attr_list = attr_list_stack.top();
349 attr_list_stack.pop();
350 } else
351 attr_list = nullptr;
352 };
353
354 attr_opt:
355 attr_opt ATTR_BEGIN opt_attr_list ATTR_END {
356 SET_RULE_LOC(@$, @2, @$);
357 }|
358 %empty;
359
360 defattr:
361 DEFATTR_BEGIN {
362 if (attr_list != nullptr)
363 attr_list_stack.push(attr_list);
364 attr_list = new dict<IdString, AstNode*>;
365 for (auto &it : default_attr_list)
366 delete it.second;
367 default_attr_list.clear();
368 } opt_attr_list {
369 attr_list->swap(default_attr_list);
370 delete attr_list;
371 if (!attr_list_stack.empty()) {
372 attr_list = attr_list_stack.top();
373 attr_list_stack.pop();
374 } else
375 attr_list = nullptr;
376 } DEFATTR_END;
377
378 opt_attr_list:
379 attr_list | %empty;
380
381 attr_list:
382 attr_assign |
383 attr_list ',' attr_assign;
384
385 attr_assign:
386 hierarchical_id {
387 if (attr_list->count(*$1) != 0)
388 delete (*attr_list)[*$1];
389 (*attr_list)[*$1] = AstNode::mkconst_int(1, false);
390 delete $1;
391 } |
392 hierarchical_id '=' expr {
393 if (attr_list->count(*$1) != 0)
394 delete (*attr_list)[*$1];
395 (*attr_list)[*$1] = $3;
396 delete $1;
397 };
398
399 hierarchical_id:
400 TOK_ID {
401 $$ = $1;
402 } |
403 hierarchical_id TOK_PACKAGESEP TOK_ID {
404 if ($3->compare(0, 1, "\\") == 0)
405 *$1 += "::" + $3->substr(1);
406 else
407 *$1 += "::" + *$3;
408 delete $3;
409 $$ = $1;
410 } |
411 hierarchical_id '.' TOK_ID {
412 if ($3->compare(0, 1, "\\") == 0)
413 *$1 += "." + $3->substr(1);
414 else
415 *$1 += "." + *$3;
416 delete $3;
417 $$ = $1;
418 };
419
420 hierarchical_type_id:
421 TOK_USER_TYPE
422 | TOK_PKG_USER_TYPE // package qualified type name
423 | '(' TOK_USER_TYPE ')' { $$ = $2; } // non-standard grammar
424 ;
425
426 module:
427 attr TOK_MODULE {
428 enterTypeScope();
429 } TOK_ID {
430 do_not_require_port_stubs = false;
431 AstNode *mod = new AstNode(AST_MODULE);
432 ast_stack.back()->children.push_back(mod);
433 ast_stack.push_back(mod);
434 current_ast_mod = mod;
435 port_stubs.clear();
436 port_counter = 0;
437 mod->str = *$4;
438 append_attr(mod, $1);
439 delete $4;
440 } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE opt_label {
441 if (port_stubs.size() != 0)
442 frontend_verilog_yyerror("Missing details for module port `%s'.",
443 port_stubs.begin()->first.c_str());
444 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
445 ast_stack.pop_back();
446 log_assert(ast_stack.size() == 1);
447 current_ast_mod = NULL;
448 exitTypeScope();
449 };
450
451 module_para_opt:
452 '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | %empty;
453
454 module_para_list:
455 single_module_para | module_para_list ',' single_module_para;
456
457 single_module_para:
458 %empty |
459 attr TOK_PARAMETER {
460 if (astbuf1) delete astbuf1;
461 astbuf1 = new AstNode(AST_PARAMETER);
462 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
463 append_attr(astbuf1, $1);
464 } param_type single_param_decl |
465 attr TOK_LOCALPARAM {
466 if (astbuf1) delete astbuf1;
467 astbuf1 = new AstNode(AST_LOCALPARAM);
468 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
469 append_attr(astbuf1, $1);
470 } param_type single_param_decl |
471 single_param_decl;
472
473 module_args_opt:
474 '(' ')' | %empty | '(' module_args optional_comma ')';
475
476 module_args:
477 module_arg | module_args ',' module_arg;
478
479 optional_comma:
480 ',' | %empty;
481
482 module_arg_opt_assignment:
483 '=' expr {
484 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
485 AstNode *wire = new AstNode(AST_IDENTIFIER);
486 wire->str = ast_stack.back()->children.back()->str;
487 if (ast_stack.back()->children.back()->is_input) {
488 AstNode *n = ast_stack.back()->children.back();
489 if (n->attributes.count(ID::defaultvalue))
490 delete n->attributes.at(ID::defaultvalue);
491 n->attributes[ID::defaultvalue] = $2;
492 } else
493 if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
494 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
495 else
496 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
497 } else
498 frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
499 } |
500 %empty;
501
502 module_arg:
503 TOK_ID {
504 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
505 AstNode *node = ast_stack.back()->children.back()->clone();
506 node->str = *$1;
507 node->port_id = ++port_counter;
508 ast_stack.back()->children.push_back(node);
509 SET_AST_NODE_LOC(node, @1, @1);
510 } else {
511 if (port_stubs.count(*$1) != 0)
512 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
513 port_stubs[*$1] = ++port_counter;
514 }
515 delete $1;
516 } module_arg_opt_assignment |
517 TOK_ID {
518 astbuf1 = new AstNode(AST_INTERFACEPORT);
519 astbuf1->children.push_back(new AstNode(AST_INTERFACEPORTTYPE));
520 astbuf1->children[0]->str = *$1;
521 delete $1;
522 } TOK_ID { /* SV interfaces */
523 if (!sv_mode)
524 frontend_verilog_yyerror("Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
525 astbuf2 = astbuf1->clone(); // really only needed if multiple instances of same type.
526 astbuf2->str = *$3;
527 delete $3;
528 astbuf2->port_id = ++port_counter;
529 ast_stack.back()->children.push_back(astbuf2);
530 delete astbuf1; // really only needed if multiple instances of same type.
531 } module_arg_opt_assignment |
532 attr wire_type range TOK_ID {
533 AstNode *node = $2;
534 node->str = *$4;
535 SET_AST_NODE_LOC(node, @4, @4);
536 node->port_id = ++port_counter;
537 if ($3 != NULL)
538 node->children.push_back($3);
539 if (!node->is_input && !node->is_output)
540 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
541 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
542 frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
543 ast_stack.back()->children.push_back(node);
544 append_attr(node, $1);
545 delete $4;
546 } module_arg_opt_assignment |
547 '.' '.' '.' {
548 do_not_require_port_stubs = true;
549 };
550
551 package:
552 attr TOK_PACKAGE {
553 enterTypeScope();
554 } TOK_ID {
555 AstNode *mod = new AstNode(AST_PACKAGE);
556 ast_stack.back()->children.push_back(mod);
557 ast_stack.push_back(mod);
558 current_ast_mod = mod;
559 mod->str = *$4;
560 append_attr(mod, $1);
561 } ';' package_body TOK_ENDPACKAGE opt_label {
562 ast_stack.pop_back();
563 current_ast_mod = NULL;
564 exitTypeScope();
565 };
566
567 package_body:
568 package_body package_body_stmt | %empty;
569
570 package_body_stmt:
571 typedef_decl | localparam_decl | param_decl;
572
573 interface:
574 TOK_INTERFACE {
575 enterTypeScope();
576 } TOK_ID {
577 do_not_require_port_stubs = false;
578 AstNode *intf = new AstNode(AST_INTERFACE);
579 ast_stack.back()->children.push_back(intf);
580 ast_stack.push_back(intf);
581 current_ast_mod = intf;
582 port_stubs.clear();
583 port_counter = 0;
584 intf->str = *$3;
585 delete $3;
586 } module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
587 if (port_stubs.size() != 0)
588 frontend_verilog_yyerror("Missing details for module port `%s'.",
589 port_stubs.begin()->first.c_str());
590 ast_stack.pop_back();
591 log_assert(ast_stack.size() == 1);
592 current_ast_mod = NULL;
593 exitTypeScope();
594 };
595
596 interface_body:
597 interface_body interface_body_stmt | %empty;
598
599 interface_body_stmt:
600 param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
601 modport_stmt;
602
603 non_opt_delay:
604 '#' TOK_ID { delete $2; } |
605 '#' TOK_CONSTVAL { delete $2; } |
606 '#' TOK_REALVAL { delete $2; } |
607 '#' '(' expr ')' { delete $3; } |
608 '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
609
610 delay:
611 non_opt_delay | %empty;
612
613 wire_type:
614 {
615 astbuf3 = new AstNode(AST_WIRE);
616 current_wire_rand = false;
617 current_wire_const = false;
618 } wire_type_token_list {
619 $$ = astbuf3;
620 SET_RULE_LOC(@$, @2, @$);
621 };
622
623 wire_type_token_list:
624 wire_type_token |
625 wire_type_token_list wire_type_token |
626 wire_type_token_io |
627 hierarchical_type_id {
628 astbuf3->is_custom_type = true;
629 astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
630 astbuf3->children.back()->str = *$1;
631 delete $1;
632 };
633
634 wire_type_token_io:
635 TOK_INPUT {
636 astbuf3->is_input = true;
637 } |
638 TOK_OUTPUT {
639 astbuf3->is_output = true;
640 } |
641 TOK_INOUT {
642 astbuf3->is_input = true;
643 astbuf3->is_output = true;
644 };
645
646 wire_type_token:
647 TOK_WIRE {
648 } |
649 TOK_WOR {
650 astbuf3->is_wor = true;
651 } |
652 TOK_WAND {
653 astbuf3->is_wand = true;
654 } |
655 TOK_REG {
656 astbuf3->is_reg = true;
657 } |
658 TOK_LOGIC {
659 astbuf3->is_logic = true;
660 } |
661 TOK_VAR {
662 astbuf3->is_logic = true;
663 } |
664 TOK_INTEGER {
665 astbuf3->is_reg = true;
666 astbuf3->range_left = 31;
667 astbuf3->range_right = 0;
668 astbuf3->is_signed = true;
669 } |
670 TOK_GENVAR {
671 astbuf3->type = AST_GENVAR;
672 astbuf3->is_reg = true;
673 astbuf3->is_signed = true;
674 astbuf3->range_left = 31;
675 astbuf3->range_right = 0;
676 } |
677 TOK_SIGNED {
678 astbuf3->is_signed = true;
679 } |
680 TOK_RAND {
681 current_wire_rand = true;
682 } |
683 TOK_CONST {
684 current_wire_const = true;
685 };
686
687 non_opt_range:
688 '[' expr ':' expr ']' {
689 $$ = new AstNode(AST_RANGE);
690 $$->children.push_back($2);
691 $$->children.push_back($4);
692 } |
693 '[' expr TOK_POS_INDEXED expr ']' {
694 $$ = new AstNode(AST_RANGE);
695 AstNode *expr = new AstNode(AST_SELFSZ, $2);
696 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
697 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
698 } |
699 '[' expr TOK_NEG_INDEXED expr ']' {
700 $$ = new AstNode(AST_RANGE);
701 AstNode *expr = new AstNode(AST_SELFSZ, $2);
702 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
703 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
704 } |
705 '[' expr ']' {
706 $$ = new AstNode(AST_RANGE);
707 $$->children.push_back($2);
708 };
709
710 non_opt_multirange:
711 non_opt_range non_opt_range {
712 $$ = new AstNode(AST_MULTIRANGE, $1, $2);
713 } |
714 non_opt_multirange non_opt_range {
715 $$ = $1;
716 $$->children.push_back($2);
717 };
718
719 range:
720 non_opt_range {
721 $$ = $1;
722 } |
723 %empty {
724 $$ = NULL;
725 };
726
727 range_or_multirange:
728 range { $$ = $1; } |
729 non_opt_multirange { $$ = $1; };
730
731 range_or_signed_int:
732 range { $$ = $1; }
733 | TOK_INTEGER { $$ = makeRange(); }
734 ;
735
736 module_body:
737 module_body module_body_stmt |
738 /* the following line makes the generate..endgenrate keywords optional */
739 module_body gen_stmt |
740 module_body ';' |
741 %empty;
742
743 module_body_stmt:
744 task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
745 enum_decl | struct_decl |
746 always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
747
748 checker_decl:
749 TOK_CHECKER TOK_ID ';' {
750 AstNode *node = new AstNode(AST_GENBLOCK);
751 node->str = *$2;
752 ast_stack.back()->children.push_back(node);
753 ast_stack.push_back(node);
754 } module_body TOK_ENDCHECKER {
755 delete $2;
756 ast_stack.pop_back();
757 };
758
759 task_func_decl:
760 attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
761 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
762 current_function_or_task->str = *$4;
763 append_attr(current_function_or_task, $1);
764 ast_stack.back()->children.push_back(current_function_or_task);
765 delete $3;
766 delete $4;
767 } opt_dpi_function_args ';' {
768 current_function_or_task = NULL;
769 } |
770 attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
771 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
772 current_function_or_task->str = *$6;
773 append_attr(current_function_or_task, $1);
774 ast_stack.back()->children.push_back(current_function_or_task);
775 delete $3;
776 delete $5;
777 delete $6;
778 } opt_dpi_function_args ';' {
779 current_function_or_task = NULL;
780 } |
781 attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
782 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
783 current_function_or_task->str = *$8;
784 append_attr(current_function_or_task, $1);
785 ast_stack.back()->children.push_back(current_function_or_task);
786 delete $3;
787 delete $5;
788 delete $7;
789 delete $8;
790 } opt_dpi_function_args ';' {
791 current_function_or_task = NULL;
792 } |
793 attr TOK_TASK opt_automatic TOK_ID {
794 current_function_or_task = new AstNode(AST_TASK);
795 current_function_or_task->str = *$4;
796 append_attr(current_function_or_task, $1);
797 ast_stack.back()->children.push_back(current_function_or_task);
798 ast_stack.push_back(current_function_or_task);
799 current_function_or_task_port_id = 1;
800 delete $4;
801 } task_func_args_opt ';' task_func_body TOK_ENDTASK {
802 current_function_or_task = NULL;
803 ast_stack.pop_back();
804 } |
805 attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID {
806 current_function_or_task = new AstNode(AST_FUNCTION);
807 current_function_or_task->str = *$6;
808 append_attr(current_function_or_task, $1);
809 ast_stack.back()->children.push_back(current_function_or_task);
810 ast_stack.push_back(current_function_or_task);
811 AstNode *outreg = new AstNode(AST_WIRE);
812 outreg->str = *$6;
813 outreg->is_signed = $4;
814 outreg->is_reg = true;
815 if ($5 != NULL) {
816 outreg->children.push_back($5);
817 outreg->is_signed = $4 || $5->is_signed;
818 $5->is_signed = false;
819 }
820 current_function_or_task->children.push_back(outreg);
821 current_function_or_task_port_id = 1;
822 delete $6;
823 } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
824 current_function_or_task = NULL;
825 ast_stack.pop_back();
826 };
827
828 dpi_function_arg:
829 TOK_ID TOK_ID {
830 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
831 delete $1;
832 delete $2;
833 } |
834 TOK_ID {
835 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
836 delete $1;
837 };
838
839 opt_dpi_function_args:
840 '(' dpi_function_args ')' |
841 %empty;
842
843 dpi_function_args:
844 dpi_function_args ',' dpi_function_arg |
845 dpi_function_args ',' |
846 dpi_function_arg |
847 %empty;
848
849 opt_automatic:
850 TOK_AUTOMATIC |
851 %empty;
852
853 opt_signed:
854 TOK_SIGNED {
855 $$ = true;
856 } |
857 %empty {
858 $$ = false;
859 };
860
861 task_func_args_opt:
862 '(' ')' | %empty | '(' {
863 albuf = nullptr;
864 astbuf1 = nullptr;
865 astbuf2 = nullptr;
866 } task_func_args optional_comma {
867 delete astbuf1;
868 if (astbuf2 != NULL)
869 delete astbuf2;
870 free_attr(albuf);
871 } ')';
872
873 task_func_args:
874 task_func_port | task_func_args ',' task_func_port;
875
876 task_func_port:
877 attr wire_type range {
878 if (albuf) {
879 delete astbuf1;
880 if (astbuf2 != NULL)
881 delete astbuf2;
882 free_attr(albuf);
883 }
884 albuf = $1;
885 astbuf1 = $2;
886 astbuf2 = checkRange(astbuf1, $3);
887 } wire_name |
888 {
889 if (!astbuf1) {
890 if (!sv_mode)
891 frontend_verilog_yyerror("task/function argument direction missing");
892 albuf = new dict<IdString, AstNode*>;
893 astbuf1 = new AstNode(AST_WIRE);
894 current_wire_rand = false;
895 current_wire_const = false;
896 astbuf1->is_input = true;
897 astbuf2 = NULL;
898 }
899 } wire_name;
900
901 task_func_body:
902 task_func_body behavioral_stmt |
903 %empty;
904
905 /*************************** specify parser ***************************/
906
907 specify_block:
908 TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
909
910 specify_item_list:
911 specify_item specify_item_list |
912 %empty;
913
914 specify_item:
915 specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
916 AstNode *en_expr = $1;
917 char specify_edge = $3;
918 AstNode *src_expr = $4;
919 string *oper = $5;
920 specify_target *target = $6;
921 specify_rise_fall *timing = $9;
922
923 if (specify_edge != 0 && target->dat == nullptr)
924 frontend_verilog_yyerror("Found specify edge but no data spec.\n");
925
926 AstNode *cell = new AstNode(AST_CELL);
927 ast_stack.back()->children.push_back(cell);
928 cell->str = stringf("$specify$%d", autoidx++);
929 cell->children.push_back(new AstNode(AST_CELLTYPE));
930 cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
931 SET_AST_NODE_LOC(cell, en_expr ? @1 : @2, @10);
932
933 char oper_polarity = 0;
934 char oper_type = oper->at(0);
935
936 if (oper->size() == 3) {
937 oper_polarity = oper->at(0);
938 oper_type = oper->at(1);
939 }
940
941 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
942 cell->children.back()->str = "\\FULL";
943
944 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
945 cell->children.back()->str = "\\SRC_DST_PEN";
946
947 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
948 cell->children.back()->str = "\\SRC_DST_POL";
949
950 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
951 cell->children.back()->str = "\\T_RISE_MIN";
952
953 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
954 cell->children.back()->str = "\\T_RISE_TYP";
955
956 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
957 cell->children.back()->str = "\\T_RISE_MAX";
958
959 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
960 cell->children.back()->str = "\\T_FALL_MIN";
961
962 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
963 cell->children.back()->str = "\\T_FALL_TYP";
964
965 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
966 cell->children.back()->str = "\\T_FALL_MAX";
967
968 cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
969 cell->children.back()->str = "\\EN";
970
971 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
972 cell->children.back()->str = "\\SRC";
973
974 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
975 cell->children.back()->str = "\\DST";
976
977 if (target->dat)
978 {
979 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
980 cell->children.back()->str = "\\EDGE_EN";
981
982 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
983 cell->children.back()->str = "\\EDGE_POL";
984
985 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
986 cell->children.back()->str = "\\DAT_DST_PEN";
987
988 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
989 cell->children.back()->str = "\\DAT_DST_POL";
990
991 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
992 cell->children.back()->str = "\\DAT";
993 }
994
995 delete oper;
996 delete target;
997 delete timing;
998 } |
999 TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' specify_triple specify_opt_triple ')' ';' {
1000 if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
1001 *$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
1002 frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
1003
1004 AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
1005 AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
1006 AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
1007
1008 AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
1009 AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
1010 AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
1011
1012 specify_triple *limit = $11;
1013 specify_triple *limit2 = $12;
1014
1015 AstNode *cell = new AstNode(AST_CELL);
1016 ast_stack.back()->children.push_back(cell);
1017 cell->str = stringf("$specify$%d", autoidx++);
1018 cell->children.push_back(new AstNode(AST_CELLTYPE));
1019 cell->children.back()->str = "$specrule";
1020 SET_AST_NODE_LOC(cell, @1, @14);
1021
1022 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
1023 cell->children.back()->str = "\\TYPE";
1024
1025 cell->children.push_back(new AstNode(AST_PARASET, limit->t_min));
1026 cell->children.back()->str = "\\T_LIMIT_MIN";
1027
1028 cell->children.push_back(new AstNode(AST_PARASET, limit->t_avg));
1029 cell->children.back()->str = "\\T_LIMIT_TYP";
1030
1031 cell->children.push_back(new AstNode(AST_PARASET, limit->t_max));
1032 cell->children.back()->str = "\\T_LIMIT_MAX";
1033
1034 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_min : AstNode::mkconst_int(0, true)));
1035 cell->children.back()->str = "\\T_LIMIT2_MIN";
1036
1037 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_avg : AstNode::mkconst_int(0, true)));
1038 cell->children.back()->str = "\\T_LIMIT2_TYP";
1039
1040 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_max : AstNode::mkconst_int(0, true)));
1041 cell->children.back()->str = "\\T_LIMIT2_MAX";
1042
1043 cell->children.push_back(new AstNode(AST_PARASET, src_pen));
1044 cell->children.back()->str = "\\SRC_PEN";
1045
1046 cell->children.push_back(new AstNode(AST_PARASET, src_pol));
1047 cell->children.back()->str = "\\SRC_POL";
1048
1049 cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
1050 cell->children.back()->str = "\\DST_PEN";
1051
1052 cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
1053 cell->children.back()->str = "\\DST_POL";
1054
1055 cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
1056 cell->children.back()->str = "\\SRC_EN";
1057
1058 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
1059 cell->children.back()->str = "\\SRC";
1060
1061 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
1062 cell->children.back()->str = "\\DST_EN";
1063
1064 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
1065 cell->children.back()->str = "\\DST";
1066
1067 delete $1;
1068 };
1069
1070 specify_opt_triple:
1071 ',' specify_triple {
1072 $$ = $2;
1073 } |
1074 %empty {
1075 $$ = nullptr;
1076 };
1077
1078 specify_if:
1079 TOK_IF '(' expr ')' {
1080 $$ = $3;
1081 } |
1082 %empty {
1083 $$ = nullptr;
1084 };
1085
1086 specify_condition:
1087 TOK_SPECIFY_AND expr {
1088 $$ = $2;
1089 } |
1090 %empty {
1091 $$ = nullptr;
1092 };
1093
1094 specify_target:
1095 expr {
1096 $$ = new specify_target;
1097 $$->polarity_op = 0;
1098 $$->dst = $1;
1099 $$->dat = nullptr;
1100 } |
1101 '(' expr ':' expr ')'{
1102 $$ = new specify_target;
1103 $$->polarity_op = 0;
1104 $$->dst = $2;
1105 $$->dat = $4;
1106 } |
1107 '(' expr TOK_NEG_INDEXED expr ')'{
1108 $$ = new specify_target;
1109 $$->polarity_op = '-';
1110 $$->dst = $2;
1111 $$->dat = $4;
1112 } |
1113 '(' expr TOK_POS_INDEXED expr ')'{
1114 $$ = new specify_target;
1115 $$->polarity_op = '+';
1116 $$->dst = $2;
1117 $$->dat = $4;
1118 };
1119
1120 specify_edge:
1121 TOK_POSEDGE { $$ = 'p'; } |
1122 TOK_NEGEDGE { $$ = 'n'; } |
1123 %empty { $$ = 0; };
1124
1125 specify_rise_fall:
1126 specify_triple {
1127 $$ = new specify_rise_fall;
1128 $$->rise = *$1;
1129 $$->fall.t_min = $1->t_min->clone();
1130 $$->fall.t_avg = $1->t_avg->clone();
1131 $$->fall.t_max = $1->t_max->clone();
1132 delete $1;
1133 } |
1134 '(' specify_triple ',' specify_triple ')' {
1135 $$ = new specify_rise_fall;
1136 $$->rise = *$2;
1137 $$->fall = *$4;
1138 delete $2;
1139 delete $4;
1140 } |
1141 '(' specify_triple ',' specify_triple ',' specify_triple ')' {
1142 $$ = new specify_rise_fall;
1143 $$->rise = *$2;
1144 $$->fall = *$4;
1145 delete $2;
1146 delete $4;
1147 delete $6;
1148 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1149 } |
1150 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1151 $$ = new specify_rise_fall;
1152 $$->rise = *$2;
1153 $$->fall = *$4;
1154 delete $2;
1155 delete $4;
1156 delete $6;
1157 delete $8;
1158 delete $10;
1159 delete $12;
1160 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1161 } |
1162 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1163 $$ = new specify_rise_fall;
1164 $$->rise = *$2;
1165 $$->fall = *$4;
1166 delete $2;
1167 delete $4;
1168 delete $6;
1169 delete $8;
1170 delete $10;
1171 delete $12;
1172 delete $14;
1173 delete $16;
1174 delete $18;
1175 delete $20;
1176 delete $22;
1177 delete $24;
1178 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1179 }
1180
1181 specify_triple:
1182 expr {
1183 $$ = new specify_triple;
1184 $$->t_min = $1;
1185 $$->t_avg = $1->clone();
1186 $$->t_max = $1->clone();
1187 } |
1188 expr ':' expr ':' expr {
1189 $$ = new specify_triple;
1190 $$->t_min = $1;
1191 $$->t_avg = $3;
1192 $$->t_max = $5;
1193 };
1194
1195 /******************** ignored specify parser **************************/
1196
1197 ignored_specify_block:
1198 TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
1199 TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
1200
1201 ignored_specify_item_opt:
1202 ignored_specify_item_opt ignored_specify_item |
1203 ignored_specify_item ;
1204
1205 ignored_specify_item:
1206 specparam_declaration
1207 // | pulsestyle_declaration
1208 // | showcancelled_declaration
1209 | path_declaration
1210 | system_timing_declaration
1211 ;
1212
1213 specparam_declaration:
1214 TOK_SPECPARAM list_of_specparam_assignments ';' |
1215 TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ;
1216
1217 // IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match
1218 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
1219 // exxxxtending this for SV specparam would change this anyhow
1220 specparam_range:
1221 '[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
1222
1223 list_of_specparam_assignments:
1224 specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
1225
1226 specparam_assignment:
1227 ignspec_id '=' ignspec_expr ;
1228
1229 ignspec_opt_cond:
1230 TOK_IF '(' ignspec_expr ')' | %empty;
1231
1232 path_declaration :
1233 simple_path_declaration ';'
1234 // | edge_sensitive_path_declaration
1235 // | state_dependent_path_declaration
1236 ;
1237
1238 simple_path_declaration :
1239 ignspec_opt_cond parallel_path_description '=' path_delay_value |
1240 ignspec_opt_cond full_path_description '=' path_delay_value
1241 ;
1242
1243 path_delay_value :
1244 '(' ignspec_expr list_of_path_delay_extra_expressions ')'
1245 | ignspec_expr
1246 | ignspec_expr list_of_path_delay_extra_expressions
1247 ;
1248
1249 list_of_path_delay_extra_expressions :
1250 ',' ignspec_expr
1251 | ',' ignspec_expr list_of_path_delay_extra_expressions
1252 ;
1253
1254 specify_edge_identifier :
1255 TOK_POSEDGE | TOK_NEGEDGE ;
1256
1257 parallel_path_description :
1258 '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
1259 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
1260 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
1261
1262 full_path_description :
1263 '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
1264 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
1265 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
1266
1267 // This was broken into 2 rules to solve shift/reduce conflicts
1268 list_of_path_inputs :
1269 specify_input_terminal_descriptor opt_polarity_operator |
1270 specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
1271
1272 more_path_inputs :
1273 ',' specify_input_terminal_descriptor |
1274 more_path_inputs ',' specify_input_terminal_descriptor ;
1275
1276 list_of_path_outputs :
1277 specify_output_terminal_descriptor |
1278 list_of_path_outputs ',' specify_output_terminal_descriptor ;
1279
1280 opt_polarity_operator :
1281 '+' | '-' | %empty;
1282
1283 // Good enough for the time being
1284 specify_input_terminal_descriptor :
1285 ignspec_id ;
1286
1287 // Good enough for the time being
1288 specify_output_terminal_descriptor :
1289 ignspec_id ;
1290
1291 system_timing_declaration :
1292 ignspec_id '(' system_timing_args ')' ';' ;
1293
1294 system_timing_arg :
1295 TOK_POSEDGE ignspec_id |
1296 TOK_NEGEDGE ignspec_id |
1297 ignspec_expr ;
1298
1299 system_timing_args :
1300 system_timing_arg |
1301 system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
1302 system_timing_args ',' system_timing_arg ;
1303
1304 // for the time being this is OK, but we may write our own expr here.
1305 // as I'm not sure it is legal to use a full expr here (probably not)
1306 // On the other hand, other rules requiring constant expressions also use 'expr'
1307 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
1308 ignspec_constant_expression:
1309 expr { delete $1; };
1310
1311 ignspec_expr:
1312 expr { delete $1; } |
1313 expr ':' expr ':' expr {
1314 delete $1;
1315 delete $3;
1316 delete $5;
1317 };
1318
1319 ignspec_id:
1320 TOK_ID { delete $1; }
1321 range_or_multirange { delete $3; };
1322
1323 /**********************************************************************/
1324
1325 param_signed:
1326 TOK_SIGNED {
1327 astbuf1->is_signed = true;
1328 } | TOK_UNSIGNED {
1329 astbuf1->is_signed = false;
1330 } | %empty;
1331
1332 param_integer:
1333 TOK_INTEGER {
1334 astbuf1->children.push_back(new AstNode(AST_RANGE));
1335 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
1336 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
1337 astbuf1->is_signed = true;
1338 };
1339
1340 param_real:
1341 TOK_REAL {
1342 astbuf1->children.push_back(new AstNode(AST_REALVALUE));
1343 };
1344
1345 param_range:
1346 range {
1347 if ($1 != NULL) {
1348 astbuf1->children.push_back($1);
1349 }
1350 };
1351
1352 param_integer_type: param_integer param_signed;
1353 param_range_type: type_vec param_signed param_range;
1354 param_implicit_type: param_signed param_range;
1355
1356 param_type:
1357 param_integer_type | param_real | param_range_type | param_implicit_type |
1358 hierarchical_type_id {
1359 astbuf1->is_custom_type = true;
1360 astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
1361 astbuf1->children.back()->str = *$1;
1362 };
1363
1364 param_decl:
1365 attr TOK_PARAMETER {
1366 astbuf1 = new AstNode(AST_PARAMETER);
1367 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1368 append_attr(astbuf1, $1);
1369 } param_type param_decl_list ';' {
1370 delete astbuf1;
1371 };
1372
1373 localparam_decl:
1374 attr TOK_LOCALPARAM {
1375 astbuf1 = new AstNode(AST_LOCALPARAM);
1376 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1377 append_attr(astbuf1, $1);
1378 } param_type param_decl_list ';' {
1379 delete astbuf1;
1380 };
1381
1382 param_decl_list:
1383 single_param_decl | param_decl_list ',' single_param_decl;
1384
1385 single_param_decl:
1386 TOK_ID '=' expr {
1387 AstNode *node;
1388 if (astbuf1 == nullptr) {
1389 if (!sv_mode)
1390 frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword");
1391 node = new AstNode(AST_PARAMETER);
1392 node->children.push_back(AstNode::mkconst_int(0, true));
1393 } else {
1394 node = astbuf1->clone();
1395 }
1396 node->str = *$1;
1397 delete node->children[0];
1398 node->children[0] = $3;
1399 ast_stack.back()->children.push_back(node);
1400 delete $1;
1401 };
1402
1403 defparam_decl:
1404 TOK_DEFPARAM defparam_decl_list ';';
1405
1406 defparam_decl_list:
1407 single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
1408
1409 single_defparam_decl:
1410 range rvalue '=' expr {
1411 AstNode *node = new AstNode(AST_DEFPARAM);
1412 node->children.push_back($2);
1413 node->children.push_back($4);
1414 if ($1 != NULL)
1415 node->children.push_back($1);
1416 ast_stack.back()->children.push_back(node);
1417 };
1418
1419 /////////
1420 // enum
1421 /////////
1422
1423 enum_type: TOK_ENUM {
1424 static int enum_count;
1425 // create parent node for the enum
1426 astbuf2 = new AstNode(AST_ENUM);
1427 ast_stack.back()->children.push_back(astbuf2);
1428 astbuf2->str = std::string("$enum");
1429 astbuf2->str += std::to_string(enum_count++);
1430 // create the template for the names
1431 astbuf1 = new AstNode(AST_ENUM_ITEM);
1432 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1433 } enum_base_type '{' enum_name_list '}' { // create template for the enum vars
1434 auto tnode = astbuf1->clone();
1435 delete astbuf1;
1436 astbuf1 = tnode;
1437 tnode->type = AST_WIRE;
1438 tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
1439 // drop constant but keep any range
1440 delete tnode->children[0];
1441 tnode->children.erase(tnode->children.begin());
1442 $$ = astbuf1; }
1443 ;
1444
1445 enum_base_type: type_atom type_signing
1446 | type_vec type_signing range { if ($3) astbuf1->children.push_back($3); }
1447 | %empty { astbuf1->is_reg = true; addRange(astbuf1); }
1448 ;
1449
1450 type_atom: TOK_INTEGER { astbuf1->is_reg = true; addRange(astbuf1); } // 4-state signed
1451 | TOK_INT { astbuf1->is_reg = true; addRange(astbuf1); } // 2-state signed
1452 | TOK_SHORTINT { astbuf1->is_reg = true; addRange(astbuf1, 15, 0); } // 2-state signed
1453 | TOK_BYTE { astbuf1->is_reg = true; addRange(astbuf1, 7, 0); } // 2-state signed
1454 ;
1455
1456 type_vec: TOK_REG { astbuf1->is_reg = true; } // unsigned
1457 | TOK_LOGIC { astbuf1->is_logic = true; } // unsigned
1458 ;
1459
1460 type_signing:
1461 TOK_SIGNED { astbuf1->is_signed = true; }
1462 | TOK_UNSIGNED { astbuf1->is_signed = false; }
1463 | %empty
1464 ;
1465
1466 enum_name_list: enum_name_decl
1467 | enum_name_list ',' enum_name_decl
1468 ;
1469
1470 enum_name_decl:
1471 TOK_ID opt_enum_init {
1472 // put in fn
1473 log_assert(astbuf1);
1474 log_assert(astbuf2);
1475 auto node = astbuf1->clone();
1476 node->str = *$1;
1477 delete $1;
1478 SET_AST_NODE_LOC(node, @1, @1);
1479 delete node->children[0];
1480 node->children[0] = $2 ? $2 : new AstNode(AST_NONE);
1481 astbuf2->children.push_back(node);
1482 }
1483 ;
1484
1485 opt_enum_init:
1486 '=' basic_expr { $$ = $2; } // TODO: restrict this
1487 | %empty { $$ = NULL; }
1488 ;
1489
1490 enum_var_list:
1491 enum_var
1492 | enum_var_list ',' enum_var
1493 ;
1494
1495 enum_var: TOK_ID {
1496 log_assert(astbuf1);
1497 log_assert(astbuf2);
1498 auto node = astbuf1->clone();
1499 ast_stack.back()->children.push_back(node);
1500 node->str = *$1;
1501 delete $1;
1502 SET_AST_NODE_LOC(node, @1, @1);
1503 node->is_enum = true;
1504 }
1505 ;
1506
1507 enum_decl: enum_type enum_var_list ';' { delete $1; }
1508 ;
1509
1510 //////////////////
1511 // struct or union
1512 //////////////////
1513
1514 struct_decl: struct_type struct_var_list ';' { delete astbuf2; }
1515 ;
1516
1517 struct_type: struct_union { astbuf2 = $1; } struct_body { $$ = astbuf2; }
1518 ;
1519
1520 struct_union:
1521 TOK_STRUCT { $$ = new AstNode(AST_STRUCT); }
1522 | TOK_UNION { $$ = new AstNode(AST_UNION); }
1523 ;
1524
1525 struct_body: opt_packed '{' struct_member_list '}'
1526 ;
1527
1528 opt_packed:
1529 TOK_PACKED opt_signed_struct |
1530 %empty { frontend_verilog_yyerror("Only PACKED supported at this time"); };
1531
1532 opt_signed_struct:
1533 TOK_SIGNED { astbuf2->is_signed = true; }
1534 | TOK_UNSIGNED { astbuf2->is_signed = false; }
1535 | %empty // default is unsigned
1536 ;
1537
1538 struct_member_list: struct_member
1539 | struct_member_list struct_member
1540 ;
1541
1542 struct_member: struct_member_type member_name_list ';' { delete astbuf1; }
1543 ;
1544
1545 member_name_list:
1546 member_name
1547 | member_name_list ',' member_name
1548 ;
1549
1550 member_name: TOK_ID {
1551 astbuf1->str = $1->substr(1);
1552 delete $1;
1553 astbuf3 = astbuf1->clone();
1554 SET_AST_NODE_LOC(astbuf3, @1, @1);
1555 astbuf2->children.push_back(astbuf3);
1556 } range { if ($3) astbuf3->children.push_back($3); }
1557 ;
1558
1559 struct_member_type: { astbuf1 = new AstNode(AST_STRUCT_ITEM); } member_type_token
1560 ;
1561
1562 member_type_token:
1563 member_type
1564 | hierarchical_type_id {
1565 // use a clone of the typedef definition nodes
1566 auto template_node = copyTypeDefinition(*$1);
1567 delete $1;
1568 switch (template_node->type) {
1569 case AST_WIRE:
1570 template_node->type = AST_STRUCT_ITEM;
1571 break;
1572 case AST_STRUCT:
1573 case AST_UNION:
1574 break;
1575 default:
1576 frontend_verilog_yyerror("Invalid type for struct member: %s", type2str(template_node->type).c_str());
1577 }
1578 delete astbuf1;
1579 astbuf1 = template_node;
1580 }
1581 | struct_union {
1582 // stash state on ast_stack
1583 ast_stack.push_back(astbuf2);
1584 astbuf2 = $1;
1585 } struct_body {
1586 astbuf1 = astbuf2;
1587 // recover state
1588 astbuf2 = ast_stack.back();
1589 ast_stack.pop_back();
1590 }
1591 ;
1592
1593 member_type: type_atom type_signing
1594 | type_vec type_signing range_or_multirange { if ($3) astbuf1->children.push_back($3); }
1595 ;
1596
1597 struct_var_list: struct_var
1598 | struct_var_list ',' struct_var
1599 ;
1600
1601 struct_var: TOK_ID { auto *var_node = astbuf2->clone();
1602 var_node->str = *$1;
1603 delete $1;
1604 SET_AST_NODE_LOC(var_node, @1, @1);
1605 ast_stack.back()->children.push_back(var_node);
1606 }
1607 ;
1608
1609 /////////
1610 // wire
1611 /////////
1612
1613 wire_decl:
1614 attr wire_type range {
1615 albuf = $1;
1616 astbuf1 = $2;
1617 astbuf2 = checkRange(astbuf1, $3);
1618 } delay wire_name_list {
1619 delete astbuf1;
1620 if (astbuf2 != NULL)
1621 delete astbuf2;
1622 free_attr(albuf);
1623 } ';' |
1624 attr TOK_SUPPLY0 TOK_ID {
1625 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1626 ast_stack.back()->children.back()->str = *$3;
1627 append_attr(ast_stack.back()->children.back(), $1);
1628 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
1629 ast_stack.back()->children.back()->children[0]->str = *$3;
1630 delete $3;
1631 } opt_supply_wires ';' |
1632 attr TOK_SUPPLY1 TOK_ID {
1633 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1634 ast_stack.back()->children.back()->str = *$3;
1635 append_attr(ast_stack.back()->children.back(), $1);
1636 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
1637 ast_stack.back()->children.back()->children[0]->str = *$3;
1638 delete $3;
1639 } opt_supply_wires ';';
1640
1641 opt_supply_wires:
1642 %empty |
1643 opt_supply_wires ',' TOK_ID {
1644 AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
1645 AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
1646 wire_node->str = *$3;
1647 assign_node->children[0]->str = *$3;
1648 ast_stack.back()->children.push_back(wire_node);
1649 ast_stack.back()->children.push_back(assign_node);
1650 delete $3;
1651 };
1652
1653 wire_name_list:
1654 wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
1655
1656 wire_name_and_opt_assign:
1657 wire_name {
1658 bool attr_anyconst = false;
1659 bool attr_anyseq = false;
1660 bool attr_allconst = false;
1661 bool attr_allseq = false;
1662 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
1663 delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
1664 ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
1665 attr_anyconst = true;
1666 }
1667 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
1668 delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
1669 ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
1670 attr_anyseq = true;
1671 }
1672 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
1673 delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
1674 ast_stack.back()->children.back()->attributes.erase(ID::allconst);
1675 attr_allconst = true;
1676 }
1677 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
1678 delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
1679 ast_stack.back()->children.back()->attributes.erase(ID::allseq);
1680 attr_allseq = true;
1681 }
1682 if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
1683 AstNode *wire = new AstNode(AST_IDENTIFIER);
1684 AstNode *fcall = new AstNode(AST_FCALL);
1685 wire->str = ast_stack.back()->children.back()->str;
1686 fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
1687 if (attr_anyconst)
1688 fcall->str = "\\$anyconst";
1689 if (attr_anyseq)
1690 fcall->str = "\\$anyseq";
1691 if (attr_allconst)
1692 fcall->str = "\\$allconst";
1693 if (attr_allseq)
1694 fcall->str = "\\$allseq";
1695 fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
1696 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
1697 }
1698 } |
1699 wire_name '=' expr {
1700 AstNode *wire = new AstNode(AST_IDENTIFIER);
1701 wire->str = ast_stack.back()->children.back()->str;
1702 if (astbuf1->is_input) {
1703 if (astbuf1->attributes.count(ID::defaultvalue))
1704 delete astbuf1->attributes.at(ID::defaultvalue);
1705 astbuf1->attributes[ID::defaultvalue] = $3;
1706 }
1707 else if (astbuf1->is_reg || astbuf1->is_logic){
1708 AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
1709 AstNode *block = new AstNode(AST_BLOCK, assign);
1710 AstNode *init = new AstNode(AST_INITIAL, block);
1711
1712 SET_AST_NODE_LOC(assign, @1, @3);
1713 SET_AST_NODE_LOC(block, @1, @3);
1714 SET_AST_NODE_LOC(init, @1, @3);
1715
1716 ast_stack.back()->children.push_back(init);
1717 }
1718 else {
1719 AstNode *assign = new AstNode(AST_ASSIGN, wire, $3);
1720 SET_AST_NODE_LOC(assign, @1, @3);
1721 ast_stack.back()->children.push_back(assign);
1722 }
1723
1724 };
1725
1726 wire_name:
1727 TOK_ID range_or_multirange {
1728 if (astbuf1 == nullptr)
1729 frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node.");
1730 AstNode *node = astbuf1->clone();
1731 node->str = *$1;
1732 append_attr_clone(node, albuf);
1733 if (astbuf2 != NULL)
1734 node->children.push_back(astbuf2->clone());
1735 if ($2 != NULL) {
1736 if (node->is_input || node->is_output)
1737 frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
1738 if (!astbuf2 && !node->is_custom_type) {
1739 addRange(node, 0, 0, false);
1740 }
1741 rewriteAsMemoryNode(node, $2);
1742 }
1743 if (current_function_or_task == NULL) {
1744 if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
1745 port_stubs[*$1] = ++port_counter;
1746 }
1747 if (port_stubs.count(*$1) != 0) {
1748 if (!node->is_input && !node->is_output)
1749 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
1750 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
1751 frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
1752 node->port_id = port_stubs[*$1];
1753 port_stubs.erase(*$1);
1754 } else {
1755 if (node->is_input || node->is_output)
1756 frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
1757 }
1758 } else {
1759 if (node->is_input || node->is_output)
1760 node->port_id = current_function_or_task_port_id++;
1761 }
1762 //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
1763 SET_AST_NODE_LOC(node, @1, @1);
1764 ast_stack.back()->children.push_back(node);
1765
1766 delete $1;
1767 };
1768
1769 assign_stmt:
1770 TOK_ASSIGN delay assign_expr_list ';';
1771
1772 assign_expr_list:
1773 assign_expr | assign_expr_list ',' assign_expr;
1774
1775 assign_expr:
1776 lvalue '=' expr {
1777 AstNode *node = new AstNode(AST_ASSIGN, $1, $3);
1778 SET_AST_NODE_LOC(node, @$, @$);
1779 ast_stack.back()->children.push_back(node);
1780 };
1781
1782 type_name: TOK_ID // first time seen
1783 | TOK_USER_TYPE { if (isInLocalScope($1)) frontend_verilog_yyerror("Duplicate declaration of TYPEDEF '%s'", $1->c_str()+1); }
1784 ;
1785
1786 typedef_decl:
1787 TOK_TYPEDEF wire_type range type_name range_or_multirange ';' {
1788 astbuf1 = $2;
1789 astbuf2 = checkRange(astbuf1, $3);
1790 if (astbuf2)
1791 astbuf1->children.push_back(astbuf2);
1792
1793 if ($5 != NULL) {
1794 if (!astbuf2) {
1795 addRange(astbuf1, 0, 0, false);
1796 }
1797 rewriteAsMemoryNode(astbuf1, $5);
1798 }
1799 addTypedefNode($4, astbuf1); }
1800 | TOK_TYPEDEF non_wire_data_type type_name ';' { addTypedefNode($3, $2); }
1801 ;
1802
1803 non_wire_data_type:
1804 enum_type
1805 | struct_type
1806 ;
1807
1808 cell_stmt:
1809 attr TOK_ID {
1810 astbuf1 = new AstNode(AST_CELL);
1811 append_attr(astbuf1, $1);
1812 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
1813 astbuf1->children[0]->str = *$2;
1814 delete $2;
1815 } cell_parameter_list_opt cell_list ';' {
1816 delete astbuf1;
1817 } |
1818 attr tok_prim_wrapper delay {
1819 astbuf1 = new AstNode(AST_PRIMITIVE);
1820 astbuf1->str = *$2;
1821 append_attr(astbuf1, $1);
1822 delete $2;
1823 } prim_list ';' {
1824 delete astbuf1;
1825 };
1826
1827 tok_prim_wrapper:
1828 TOK_PRIMITIVE {
1829 $$ = $1;
1830 } |
1831 TOK_OR {
1832 $$ = new std::string("or");
1833 };
1834
1835 cell_list:
1836 single_cell |
1837 cell_list ',' single_cell;
1838
1839 single_cell:
1840 TOK_ID {
1841 astbuf2 = astbuf1->clone();
1842 if (astbuf2->type != AST_PRIMITIVE)
1843 astbuf2->str = *$1;
1844 delete $1;
1845 ast_stack.back()->children.push_back(astbuf2);
1846 } '(' cell_port_list ')' {
1847 SET_AST_NODE_LOC(astbuf2, @1, @$);
1848 } |
1849 TOK_ID non_opt_range {
1850 astbuf2 = astbuf1->clone();
1851 if (astbuf2->type != AST_PRIMITIVE)
1852 astbuf2->str = *$1;
1853 delete $1;
1854 ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
1855 } '(' cell_port_list ')'{
1856 SET_AST_NODE_LOC(astbuf2, @1, @$);
1857 };
1858
1859 prim_list:
1860 single_prim |
1861 prim_list ',' single_prim;
1862
1863 single_prim:
1864 single_cell |
1865 /* no name */ {
1866 astbuf2 = astbuf1->clone();
1867 ast_stack.back()->children.push_back(astbuf2);
1868 } '(' cell_port_list ')' {
1869 SET_AST_NODE_LOC(astbuf2, @1, @$);
1870 }
1871
1872 cell_parameter_list_opt:
1873 '#' '(' cell_parameter_list ')' | %empty;
1874
1875 cell_parameter_list:
1876 cell_parameter | cell_parameter_list ',' cell_parameter;
1877
1878 cell_parameter:
1879 %empty |
1880 expr {
1881 AstNode *node = new AstNode(AST_PARASET);
1882 astbuf1->children.push_back(node);
1883 node->children.push_back($1);
1884 } |
1885 '.' TOK_ID '(' expr ')' {
1886 AstNode *node = new AstNode(AST_PARASET);
1887 node->str = *$2;
1888 astbuf1->children.push_back(node);
1889 node->children.push_back($4);
1890 delete $2;
1891 };
1892
1893 cell_port_list:
1894 cell_port_list_rules {
1895 // remove empty args from end of list
1896 while (!astbuf2->children.empty()) {
1897 AstNode *node = astbuf2->children.back();
1898 if (node->type != AST_ARGUMENT) break;
1899 if (!node->children.empty()) break;
1900 if (!node->str.empty()) break;
1901 astbuf2->children.pop_back();
1902 delete node;
1903 }
1904
1905 // check port types
1906 bool has_positional_args = false;
1907 bool has_named_args = false;
1908 for (auto node : astbuf2->children) {
1909 if (node->type != AST_ARGUMENT) continue;
1910 if (node->str.empty())
1911 has_positional_args = true;
1912 else
1913 has_named_args = true;
1914 }
1915
1916 if (has_positional_args && has_named_args)
1917 frontend_verilog_yyerror("Mix of positional and named cell ports.");
1918 };
1919
1920 cell_port_list_rules:
1921 cell_port | cell_port_list_rules ',' cell_port;
1922
1923 cell_port:
1924 attr {
1925 AstNode *node = new AstNode(AST_ARGUMENT);
1926 astbuf2->children.push_back(node);
1927 free_attr($1);
1928 } |
1929 attr expr {
1930 AstNode *node = new AstNode(AST_ARGUMENT);
1931 astbuf2->children.push_back(node);
1932 node->children.push_back($2);
1933 free_attr($1);
1934 } |
1935 attr '.' TOK_ID '(' expr ')' {
1936 AstNode *node = new AstNode(AST_ARGUMENT);
1937 node->str = *$3;
1938 astbuf2->children.push_back(node);
1939 node->children.push_back($5);
1940 delete $3;
1941 free_attr($1);
1942 } |
1943 attr '.' TOK_ID '(' ')' {
1944 AstNode *node = new AstNode(AST_ARGUMENT);
1945 node->str = *$3;
1946 astbuf2->children.push_back(node);
1947 delete $3;
1948 free_attr($1);
1949 } |
1950 attr '.' TOK_ID {
1951 AstNode *node = new AstNode(AST_ARGUMENT);
1952 node->str = *$3;
1953 astbuf2->children.push_back(node);
1954 node->children.push_back(new AstNode(AST_IDENTIFIER));
1955 node->children.back()->str = *$3;
1956 delete $3;
1957 free_attr($1);
1958 } |
1959 attr TOK_WILDCARD_CONNECT {
1960 if (!sv_mode)
1961 frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
1962 astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
1963 };
1964
1965 always_comb_or_latch:
1966 TOK_ALWAYS_COMB {
1967 $$ = false;
1968 } |
1969 TOK_ALWAYS_LATCH {
1970 $$ = true;
1971 };
1972
1973 always_or_always_ff:
1974 TOK_ALWAYS {
1975 $$ = false;
1976 } |
1977 TOK_ALWAYS_FF {
1978 $$ = true;
1979 };
1980
1981 always_stmt:
1982 attr always_or_always_ff {
1983 AstNode *node = new AstNode(AST_ALWAYS);
1984 append_attr(node, $1);
1985 if ($2)
1986 node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
1987 ast_stack.back()->children.push_back(node);
1988 ast_stack.push_back(node);
1989 } always_cond {
1990 AstNode *block = new AstNode(AST_BLOCK);
1991 ast_stack.back()->children.push_back(block);
1992 ast_stack.push_back(block);
1993 } behavioral_stmt {
1994 SET_AST_NODE_LOC(ast_stack.back(), @6, @6);
1995 ast_stack.pop_back();
1996
1997 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
1998 ast_stack.pop_back();
1999
2000 SET_RULE_LOC(@$, @2, @$);
2001 } |
2002 attr always_comb_or_latch {
2003 AstNode *node = new AstNode(AST_ALWAYS);
2004 append_attr(node, $1);
2005 if ($2)
2006 node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
2007 else
2008 node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
2009 ast_stack.back()->children.push_back(node);
2010 ast_stack.push_back(node);
2011 AstNode *block = new AstNode(AST_BLOCK);
2012 ast_stack.back()->children.push_back(block);
2013 ast_stack.push_back(block);
2014 } behavioral_stmt {
2015 ast_stack.pop_back();
2016 ast_stack.pop_back();
2017 } |
2018 attr TOK_INITIAL {
2019 AstNode *node = new AstNode(AST_INITIAL);
2020 append_attr(node, $1);
2021 ast_stack.back()->children.push_back(node);
2022 ast_stack.push_back(node);
2023 AstNode *block = new AstNode(AST_BLOCK);
2024 ast_stack.back()->children.push_back(block);
2025 ast_stack.push_back(block);
2026 } behavioral_stmt {
2027 ast_stack.pop_back();
2028 ast_stack.pop_back();
2029 };
2030
2031 always_cond:
2032 '@' '(' always_events ')' |
2033 '@' '(' '*' ')' |
2034 '@' ATTR_BEGIN ')' |
2035 '@' '(' ATTR_END |
2036 '@' '*' |
2037 %empty;
2038
2039 always_events:
2040 always_event |
2041 always_events TOK_OR always_event |
2042 always_events ',' always_event;
2043
2044 always_event:
2045 TOK_POSEDGE expr {
2046 AstNode *node = new AstNode(AST_POSEDGE);
2047 SET_AST_NODE_LOC(node, @1, @1);
2048 ast_stack.back()->children.push_back(node);
2049 node->children.push_back($2);
2050 } |
2051 TOK_NEGEDGE expr {
2052 AstNode *node = new AstNode(AST_NEGEDGE);
2053 SET_AST_NODE_LOC(node, @1, @1);
2054 ast_stack.back()->children.push_back(node);
2055 node->children.push_back($2);
2056 } |
2057 expr {
2058 AstNode *node = new AstNode(AST_EDGE);
2059 ast_stack.back()->children.push_back(node);
2060 node->children.push_back($1);
2061 };
2062
2063 opt_label:
2064 ':' TOK_ID {
2065 $$ = $2;
2066 } |
2067 %empty {
2068 $$ = NULL;
2069 };
2070
2071 opt_sva_label:
2072 TOK_SVA_LABEL ':' {
2073 $$ = $1;
2074 } |
2075 %empty {
2076 $$ = NULL;
2077 };
2078
2079 opt_property:
2080 TOK_PROPERTY {
2081 $$ = true;
2082 } |
2083 TOK_FINAL {
2084 $$ = false;
2085 } |
2086 %empty {
2087 $$ = false;
2088 };
2089
2090 modport_stmt:
2091 TOK_MODPORT TOK_ID {
2092 AstNode *modport = new AstNode(AST_MODPORT);
2093 ast_stack.back()->children.push_back(modport);
2094 ast_stack.push_back(modport);
2095 modport->str = *$2;
2096 delete $2;
2097 } modport_args_opt {
2098 ast_stack.pop_back();
2099 log_assert(ast_stack.size() == 2);
2100 } ';'
2101
2102 modport_args_opt:
2103 '(' ')' | '(' modport_args optional_comma ')';
2104
2105 modport_args:
2106 modport_arg | modport_args ',' modport_arg;
2107
2108 modport_arg:
2109 modport_type_token modport_member |
2110 modport_member
2111
2112 modport_member:
2113 TOK_ID {
2114 AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
2115 ast_stack.back()->children.push_back(modport_member);
2116 modport_member->str = *$1;
2117 modport_member->is_input = current_modport_input;
2118 modport_member->is_output = current_modport_output;
2119 delete $1;
2120 }
2121
2122 modport_type_token:
2123 TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
2124
2125 assert:
2126 opt_sva_label TOK_ASSERT opt_property '(' expr ')' ';' {
2127 if (noassert_mode) {
2128 delete $5;
2129 } else {
2130 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2131 SET_AST_NODE_LOC(node, @1, @6);
2132 if ($1 != nullptr)
2133 node->str = *$1;
2134 ast_stack.back()->children.push_back(node);
2135 }
2136 if ($1 != nullptr)
2137 delete $1;
2138 } |
2139 opt_sva_label TOK_ASSUME opt_property '(' expr ')' ';' {
2140 if (noassume_mode) {
2141 delete $5;
2142 } else {
2143 AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
2144 SET_AST_NODE_LOC(node, @1, @6);
2145 if ($1 != nullptr)
2146 node->str = *$1;
2147 ast_stack.back()->children.push_back(node);
2148 }
2149 if ($1 != nullptr)
2150 delete $1;
2151 } |
2152 opt_sva_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2153 if (noassert_mode) {
2154 delete $6;
2155 } else {
2156 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2157 SET_AST_NODE_LOC(node, @1, @7);
2158 if ($1 != nullptr)
2159 node->str = *$1;
2160 ast_stack.back()->children.push_back(node);
2161 }
2162 if ($1 != nullptr)
2163 delete $1;
2164 } |
2165 opt_sva_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2166 if (noassume_mode) {
2167 delete $6;
2168 } else {
2169 AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
2170 SET_AST_NODE_LOC(node, @1, @7);
2171 if ($1 != nullptr)
2172 node->str = *$1;
2173 ast_stack.back()->children.push_back(node);
2174 }
2175 if ($1 != nullptr)
2176 delete $1;
2177 } |
2178 opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
2179 AstNode *node = new AstNode(AST_COVER, $5);
2180 SET_AST_NODE_LOC(node, @1, @6);
2181 if ($1 != nullptr) {
2182 node->str = *$1;
2183 delete $1;
2184 }
2185 ast_stack.back()->children.push_back(node);
2186 } |
2187 opt_sva_label TOK_COVER opt_property '(' ')' ';' {
2188 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2189 SET_AST_NODE_LOC(node, @1, @5);
2190 if ($1 != nullptr) {
2191 node->str = *$1;
2192 delete $1;
2193 }
2194 ast_stack.back()->children.push_back(node);
2195 } |
2196 opt_sva_label TOK_COVER ';' {
2197 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2198 SET_AST_NODE_LOC(node, @1, @2);
2199 if ($1 != nullptr) {
2200 node->str = *$1;
2201 delete $1;
2202 }
2203 ast_stack.back()->children.push_back(node);
2204 } |
2205 opt_sva_label TOK_RESTRICT opt_property '(' expr ')' ';' {
2206 if (norestrict_mode) {
2207 delete $5;
2208 } else {
2209 AstNode *node = new AstNode(AST_ASSUME, $5);
2210 SET_AST_NODE_LOC(node, @1, @6);
2211 if ($1 != nullptr)
2212 node->str = *$1;
2213 ast_stack.back()->children.push_back(node);
2214 }
2215 if (!$3)
2216 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2217 if ($1 != nullptr)
2218 delete $1;
2219 } |
2220 opt_sva_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2221 if (norestrict_mode) {
2222 delete $6;
2223 } else {
2224 AstNode *node = new AstNode(AST_FAIR, $6);
2225 SET_AST_NODE_LOC(node, @1, @7);
2226 if ($1 != nullptr)
2227 node->str = *$1;
2228 ast_stack.back()->children.push_back(node);
2229 }
2230 if (!$3)
2231 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2232 if ($1 != nullptr)
2233 delete $1;
2234 };
2235
2236 assert_property:
2237 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
2238 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2239 SET_AST_NODE_LOC(node, @1, @6);
2240 ast_stack.back()->children.push_back(node);
2241 if ($1 != nullptr) {
2242 ast_stack.back()->children.back()->str = *$1;
2243 delete $1;
2244 }
2245 } |
2246 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
2247 AstNode *node = new AstNode(AST_ASSUME, $5);
2248 SET_AST_NODE_LOC(node, @1, @6);
2249 ast_stack.back()->children.push_back(node);
2250 if ($1 != nullptr) {
2251 ast_stack.back()->children.back()->str = *$1;
2252 delete $1;
2253 }
2254 } |
2255 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2256 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2257 SET_AST_NODE_LOC(node, @1, @7);
2258 ast_stack.back()->children.push_back(node);
2259 if ($1 != nullptr) {
2260 ast_stack.back()->children.back()->str = *$1;
2261 delete $1;
2262 }
2263 } |
2264 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2265 AstNode *node = new AstNode(AST_FAIR, $6);
2266 SET_AST_NODE_LOC(node, @1, @7);
2267 ast_stack.back()->children.push_back(node);
2268 if ($1 != nullptr) {
2269 ast_stack.back()->children.back()->str = *$1;
2270 delete $1;
2271 }
2272 } |
2273 opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
2274 AstNode *node = new AstNode(AST_COVER, $5);
2275 SET_AST_NODE_LOC(node, @1, @6);
2276 ast_stack.back()->children.push_back(node);
2277 if ($1 != nullptr) {
2278 ast_stack.back()->children.back()->str = *$1;
2279 delete $1;
2280 }
2281 } |
2282 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
2283 if (norestrict_mode) {
2284 delete $5;
2285 } else {
2286 AstNode *node = new AstNode(AST_ASSUME, $5);
2287 SET_AST_NODE_LOC(node, @1, @6);
2288 ast_stack.back()->children.push_back(node);
2289 if ($1 != nullptr) {
2290 ast_stack.back()->children.back()->str = *$1;
2291 delete $1;
2292 }
2293 }
2294 } |
2295 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2296 if (norestrict_mode) {
2297 delete $6;
2298 } else {
2299 AstNode *node = new AstNode(AST_FAIR, $6);
2300 SET_AST_NODE_LOC(node, @1, @7);
2301 ast_stack.back()->children.push_back(node);
2302 if ($1 != nullptr) {
2303 ast_stack.back()->children.back()->str = *$1;
2304 delete $1;
2305 }
2306 }
2307 };
2308
2309 simple_behavioral_stmt:
2310 attr lvalue '=' delay expr {
2311 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $5);
2312 ast_stack.back()->children.push_back(node);
2313 SET_AST_NODE_LOC(node, @2, @5);
2314 append_attr(node, $1);
2315 } |
2316 attr lvalue TOK_INCREMENT {
2317 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)));
2318 ast_stack.back()->children.push_back(node);
2319 SET_AST_NODE_LOC(node, @2, @3);
2320 append_attr(node, $1);
2321 } |
2322 attr lvalue TOK_DECREMENT {
2323 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_SUB, $2->clone(), AstNode::mkconst_int(1, true)));
2324 ast_stack.back()->children.push_back(node);
2325 SET_AST_NODE_LOC(node, @2, @3);
2326 append_attr(node, $1);
2327 } |
2328 attr lvalue OP_LE delay expr {
2329 AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5);
2330 ast_stack.back()->children.push_back(node);
2331 SET_AST_NODE_LOC(node, @2, @5);
2332 append_attr(node, $1);
2333 } |
2334 attr lvalue TOK_XOR_ASSIGN delay expr {
2335 AstNode *xor_node = new AstNode(AST_BIT_XOR, $2->clone(), $5);
2336 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, xor_node);
2337 SET_AST_NODE_LOC(xor_node, @2, @5);
2338 SET_AST_NODE_LOC(node, @2, @5);
2339 ast_stack.back()->children.push_back(node);
2340 append_attr(node, $1);
2341 } |
2342 attr lvalue TOK_OR_ASSIGN delay expr {
2343 AstNode *or_node = new AstNode(AST_BIT_OR, $2->clone(), $5);
2344 SET_AST_NODE_LOC(or_node, @2, @5);
2345 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, or_node);
2346 SET_AST_NODE_LOC(node, @2, @5);
2347 ast_stack.back()->children.push_back(node);
2348 append_attr(node, $1);
2349 } |
2350 attr lvalue TOK_PLUS_ASSIGN delay expr {
2351 AstNode *add_node = new AstNode(AST_ADD, $2->clone(), $5);
2352 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, add_node);
2353 SET_AST_NODE_LOC(node, @2, @5);
2354 SET_AST_NODE_LOC(add_node, @2, @5);
2355 ast_stack.back()->children.push_back(node);
2356 append_attr(node, $1);
2357 } |
2358 attr lvalue TOK_SUB_ASSIGN delay expr {
2359 AstNode *sub_node = new AstNode(AST_SUB, $2->clone(), $5);
2360 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, sub_node);
2361 SET_AST_NODE_LOC(node, @2, @5);
2362 SET_AST_NODE_LOC(sub_node, @2, @5);
2363 ast_stack.back()->children.push_back(node);
2364 append_attr(node, $1);
2365 } |
2366 attr lvalue TOK_AND_ASSIGN delay expr {
2367 AstNode *and_node = new AstNode(AST_BIT_AND, $2->clone(), $5);
2368 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, and_node);
2369 SET_AST_NODE_LOC(node, @2, @5);
2370 SET_AST_NODE_LOC(and_node, @2, @5);
2371 ast_stack.back()->children.push_back(node);
2372 append_attr(node, $1);
2373 };
2374
2375 // this production creates the obligatory if-else shift/reduce conflict
2376 behavioral_stmt:
2377 defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
2378 non_opt_delay behavioral_stmt |
2379 simple_behavioral_stmt ';' |
2380 attr ';' {
2381 free_attr($1);
2382 } |
2383 attr hierarchical_id {
2384 AstNode *node = new AstNode(AST_TCALL);
2385 node->str = *$2;
2386 delete $2;
2387 ast_stack.back()->children.push_back(node);
2388 ast_stack.push_back(node);
2389 append_attr(node, $1);
2390 } opt_arg_list ';'{
2391 ast_stack.pop_back();
2392 } |
2393 attr TOK_MSG_TASKS {
2394 AstNode *node = new AstNode(AST_TCALL);
2395 node->str = *$2;
2396 delete $2;
2397 ast_stack.back()->children.push_back(node);
2398 ast_stack.push_back(node);
2399 append_attr(node, $1);
2400 } opt_arg_list ';'{
2401 ast_stack.pop_back();
2402 } |
2403 attr TOK_BEGIN {
2404 enterTypeScope();
2405 } opt_label {
2406 AstNode *node = new AstNode(AST_BLOCK);
2407 ast_stack.back()->children.push_back(node);
2408 ast_stack.push_back(node);
2409 append_attr(node, $1);
2410 if ($4 != NULL)
2411 node->str = *$4;
2412 } behavioral_stmt_list TOK_END opt_label {
2413 exitTypeScope();
2414 if ($4 != NULL && $8 != NULL && *$4 != *$8)
2415 frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
2416 SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
2417 delete $4;
2418 delete $8;
2419 ast_stack.pop_back();
2420 } |
2421 attr TOK_FOR '(' {
2422 AstNode *node = new AstNode(AST_FOR);
2423 ast_stack.back()->children.push_back(node);
2424 ast_stack.push_back(node);
2425 append_attr(node, $1);
2426 } simple_behavioral_stmt ';' expr {
2427 ast_stack.back()->children.push_back($7);
2428 } ';' simple_behavioral_stmt ')' {
2429 AstNode *block = new AstNode(AST_BLOCK);
2430 ast_stack.back()->children.push_back(block);
2431 ast_stack.push_back(block);
2432 } behavioral_stmt {
2433 SET_AST_NODE_LOC(ast_stack.back(), @13, @13);
2434 ast_stack.pop_back();
2435 SET_AST_NODE_LOC(ast_stack.back(), @2, @13);
2436 ast_stack.pop_back();
2437 } |
2438 attr TOK_WHILE '(' expr ')' {
2439 AstNode *node = new AstNode(AST_WHILE);
2440 ast_stack.back()->children.push_back(node);
2441 ast_stack.push_back(node);
2442 append_attr(node, $1);
2443 AstNode *block = new AstNode(AST_BLOCK);
2444 ast_stack.back()->children.push_back($4);
2445 ast_stack.back()->children.push_back(block);
2446 ast_stack.push_back(block);
2447 } behavioral_stmt {
2448 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2449 ast_stack.pop_back();
2450 ast_stack.pop_back();
2451 } |
2452 attr TOK_REPEAT '(' expr ')' {
2453 AstNode *node = new AstNode(AST_REPEAT);
2454 ast_stack.back()->children.push_back(node);
2455 ast_stack.push_back(node);
2456 append_attr(node, $1);
2457 AstNode *block = new AstNode(AST_BLOCK);
2458 ast_stack.back()->children.push_back($4);
2459 ast_stack.back()->children.push_back(block);
2460 ast_stack.push_back(block);
2461 } behavioral_stmt {
2462 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2463 ast_stack.pop_back();
2464 ast_stack.pop_back();
2465 } |
2466 attr TOK_IF '(' expr ')' {
2467 AstNode *node = new AstNode(AST_CASE);
2468 AstNode *block = new AstNode(AST_BLOCK);
2469 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
2470 SET_AST_NODE_LOC(cond, @4, @4);
2471 ast_stack.back()->children.push_back(node);
2472 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
2473 node->children.push_back(cond);
2474 ast_stack.push_back(node);
2475 ast_stack.push_back(block);
2476 append_attr(node, $1);
2477 } behavioral_stmt {
2478 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2479 } optional_else {
2480 ast_stack.pop_back();
2481 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2482 ast_stack.pop_back();
2483 } |
2484 case_attr case_type '(' expr ')' {
2485 AstNode *node = new AstNode(AST_CASE, $4);
2486 ast_stack.back()->children.push_back(node);
2487 ast_stack.push_back(node);
2488 append_attr(node, $1);
2489 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2490 } opt_synopsys_attr case_body TOK_ENDCASE {
2491 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2492 case_type_stack.pop_back();
2493 ast_stack.pop_back();
2494 };
2495
2496 unique_case_attr:
2497 %empty {
2498 $$ = false;
2499 } |
2500 TOK_PRIORITY case_attr {
2501 $$ = $2;
2502 } |
2503 TOK_UNIQUE case_attr {
2504 $$ = true;
2505 };
2506
2507 case_attr:
2508 attr unique_case_attr {
2509 if ($2) (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false);
2510 $$ = $1;
2511 };
2512
2513 case_type:
2514 TOK_CASE {
2515 case_type_stack.push_back(0);
2516 } |
2517 TOK_CASEX {
2518 case_type_stack.push_back('x');
2519 } |
2520 TOK_CASEZ {
2521 case_type_stack.push_back('z');
2522 };
2523
2524 opt_synopsys_attr:
2525 opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
2526 if (ast_stack.back()->attributes.count(ID::full_case) == 0)
2527 ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
2528 } |
2529 opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
2530 if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
2531 ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
2532 } |
2533 %empty;
2534
2535 behavioral_stmt_list:
2536 behavioral_stmt_list behavioral_stmt |
2537 %empty;
2538
2539 optional_else:
2540 TOK_ELSE {
2541 AstNode *block = new AstNode(AST_BLOCK);
2542 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
2543 SET_AST_NODE_LOC(cond, @1, @1);
2544
2545 ast_stack.pop_back();
2546 ast_stack.back()->children.push_back(cond);
2547 ast_stack.push_back(block);
2548 } behavioral_stmt {
2549 SET_AST_NODE_LOC(ast_stack.back(), @3, @3);
2550 } |
2551 %empty %prec FAKE_THEN;
2552
2553 case_body:
2554 case_body case_item |
2555 %empty;
2556
2557 case_item:
2558 {
2559 AstNode *node = new AstNode(
2560 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2561 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2562 ast_stack.back()->children.push_back(node);
2563 ast_stack.push_back(node);
2564 } case_select {
2565 AstNode *block = new AstNode(AST_BLOCK);
2566 ast_stack.back()->children.push_back(block);
2567 ast_stack.push_back(block);
2568 case_type_stack.push_back(0);
2569 } behavioral_stmt {
2570 case_type_stack.pop_back();
2571 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2572 ast_stack.pop_back();
2573 ast_stack.pop_back();
2574 };
2575
2576 gen_case_body:
2577 gen_case_body gen_case_item |
2578 %empty;
2579
2580 gen_case_item:
2581 {
2582 AstNode *node = new AstNode(
2583 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2584 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2585 ast_stack.back()->children.push_back(node);
2586 ast_stack.push_back(node);
2587 } case_select {
2588 case_type_stack.push_back(0);
2589 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2590 } gen_stmt_block {
2591 case_type_stack.pop_back();
2592 ast_stack.pop_back();
2593 };
2594
2595 case_select:
2596 case_expr_list ':' |
2597 TOK_DEFAULT;
2598
2599 case_expr_list:
2600 TOK_DEFAULT {
2601 AstNode *node = new AstNode(AST_DEFAULT);
2602 SET_AST_NODE_LOC(node, @1, @1);
2603 ast_stack.back()->children.push_back(node);
2604 } |
2605 TOK_SVA_LABEL {
2606 AstNode *node = new AstNode(AST_IDENTIFIER);
2607 SET_AST_NODE_LOC(node, @1, @1);
2608 ast_stack.back()->children.push_back(node);
2609 ast_stack.back()->children.back()->str = *$1;
2610 delete $1;
2611 } |
2612 expr {
2613 ast_stack.back()->children.push_back($1);
2614 } |
2615 case_expr_list ',' expr {
2616 ast_stack.back()->children.push_back($3);
2617 };
2618
2619 rvalue:
2620 hierarchical_id '[' expr ']' '.' rvalue {
2621 $$ = new AstNode(AST_PREFIX, $3, $6);
2622 $$->str = *$1;
2623 delete $1;
2624 } |
2625 hierarchical_id range {
2626 $$ = new AstNode(AST_IDENTIFIER, $2);
2627 $$->str = *$1;
2628 SET_AST_NODE_LOC($$, @1, @1);
2629 delete $1;
2630 if ($2 == nullptr && ($$->str == "\\$initstate" ||
2631 $$->str == "\\$anyconst" || $$->str == "\\$anyseq" ||
2632 $$->str == "\\$allconst" || $$->str == "\\$allseq"))
2633 $$->type = AST_FCALL;
2634 } |
2635 hierarchical_id non_opt_multirange {
2636 $$ = new AstNode(AST_IDENTIFIER, $2);
2637 $$->str = *$1;
2638 SET_AST_NODE_LOC($$, @1, @1);
2639 delete $1;
2640 };
2641
2642 lvalue:
2643 rvalue {
2644 $$ = $1;
2645 } |
2646 '{' lvalue_concat_list '}' {
2647 $$ = $2;
2648 };
2649
2650 lvalue_concat_list:
2651 expr {
2652 $$ = new AstNode(AST_CONCAT);
2653 $$->children.push_back($1);
2654 } |
2655 expr ',' lvalue_concat_list {
2656 $$ = $3;
2657 $$->children.push_back($1);
2658 };
2659
2660 opt_arg_list:
2661 '(' arg_list optional_comma ')' |
2662 %empty;
2663
2664 arg_list:
2665 arg_list2 |
2666 %empty;
2667
2668 arg_list2:
2669 single_arg |
2670 arg_list ',' single_arg;
2671
2672 single_arg:
2673 expr {
2674 ast_stack.back()->children.push_back($1);
2675 };
2676
2677 module_gen_body:
2678 module_gen_body gen_stmt_or_module_body_stmt |
2679 %empty;
2680
2681 gen_stmt_or_module_body_stmt:
2682 gen_stmt | module_body_stmt |
2683 attr ';' {
2684 free_attr($1);
2685 };
2686
2687 // this production creates the obligatory if-else shift/reduce conflict
2688 gen_stmt:
2689 TOK_FOR '(' {
2690 AstNode *node = new AstNode(AST_GENFOR);
2691 ast_stack.back()->children.push_back(node);
2692 ast_stack.push_back(node);
2693 } simple_behavioral_stmt ';' expr {
2694 ast_stack.back()->children.push_back($6);
2695 } ';' simple_behavioral_stmt ')' gen_stmt_block {
2696 SET_AST_NODE_LOC(ast_stack.back(), @1, @11);
2697 ast_stack.pop_back();
2698 } |
2699 TOK_IF '(' expr ')' {
2700 AstNode *node = new AstNode(AST_GENIF);
2701 ast_stack.back()->children.push_back(node);
2702 ast_stack.push_back(node);
2703 ast_stack.back()->children.push_back($3);
2704 AstNode *block = new AstNode(AST_GENBLOCK);
2705 ast_stack.back()->children.push_back(block);
2706 ast_stack.push_back(block);
2707 } gen_stmt_block {
2708 ast_stack.pop_back();
2709 } opt_gen_else {
2710 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2711 ast_stack.pop_back();
2712 } |
2713 case_type '(' expr ')' {
2714 AstNode *node = new AstNode(AST_GENCASE, $3);
2715 ast_stack.back()->children.push_back(node);
2716 ast_stack.push_back(node);
2717 } gen_case_body TOK_ENDCASE {
2718 case_type_stack.pop_back();
2719 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2720 ast_stack.pop_back();
2721 } |
2722 TOK_BEGIN {
2723 enterTypeScope();
2724 } opt_label {
2725 AstNode *node = new AstNode(AST_GENBLOCK);
2726 node->str = $3 ? *$3 : std::string();
2727 ast_stack.back()->children.push_back(node);
2728 ast_stack.push_back(node);
2729 } module_gen_body TOK_END opt_label {
2730 exitTypeScope();
2731 delete $3;
2732 delete $7;
2733 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2734 ast_stack.pop_back();
2735 } |
2736 TOK_MSG_TASKS {
2737 AstNode *node = new AstNode(AST_TECALL);
2738 node->str = *$1;
2739 delete $1;
2740 ast_stack.back()->children.push_back(node);
2741 ast_stack.push_back(node);
2742 } opt_arg_list ';'{
2743 SET_AST_NODE_LOC(ast_stack.back(), @1, @3);
2744 ast_stack.pop_back();
2745 };
2746
2747 gen_stmt_block:
2748 {
2749 AstNode *node = new AstNode(AST_GENBLOCK);
2750 ast_stack.back()->children.push_back(node);
2751 ast_stack.push_back(node);
2752 } gen_stmt_or_module_body_stmt {
2753 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2754 ast_stack.pop_back();
2755 };
2756
2757 opt_gen_else:
2758 TOK_ELSE gen_stmt_block | %empty %prec FAKE_THEN;
2759
2760 expr:
2761 basic_expr {
2762 $$ = $1;
2763 } |
2764 basic_expr '?' attr expr ':' expr {
2765 $$ = new AstNode(AST_TERNARY);
2766 $$->children.push_back($1);
2767 $$->children.push_back($4);
2768 $$->children.push_back($6);
2769 SET_AST_NODE_LOC($$, @1, @$);
2770 append_attr($$, $3);
2771 };
2772
2773 basic_expr:
2774 rvalue {
2775 $$ = $1;
2776 } |
2777 '(' expr ')' integral_number {
2778 if ($4->compare(0, 1, "'") != 0)
2779 frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
2780 AstNode *bits = $2;
2781 AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2782 if (val == NULL)
2783 log_error("Value conversion failed: `%s'\n", $4->c_str());
2784 $$ = new AstNode(AST_TO_BITS, bits, val);
2785 delete $4;
2786 } |
2787 hierarchical_id integral_number {
2788 if ($2->compare(0, 1, "'") != 0)
2789 frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
2790 AstNode *bits = new AstNode(AST_IDENTIFIER);
2791 bits->str = *$1;
2792 SET_AST_NODE_LOC(bits, @1, @1);
2793 AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2794 SET_AST_NODE_LOC(val, @2, @2);
2795 if (val == NULL)
2796 log_error("Value conversion failed: `%s'\n", $2->c_str());
2797 $$ = new AstNode(AST_TO_BITS, bits, val);
2798 delete $1;
2799 delete $2;
2800 } |
2801 integral_number {
2802 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2803 SET_AST_NODE_LOC($$, @1, @1);
2804 if ($$ == NULL)
2805 log_error("Value conversion failed: `%s'\n", $1->c_str());
2806 delete $1;
2807 } |
2808 TOK_REALVAL {
2809 $$ = new AstNode(AST_REALVALUE);
2810 char *p = (char*)malloc(GetSize(*$1) + 1), *q;
2811 for (int i = 0, j = 0; j < GetSize(*$1); j++)
2812 if ((*$1)[j] != '_')
2813 p[i++] = (*$1)[j], p[i] = 0;
2814 $$->realvalue = strtod(p, &q);
2815 SET_AST_NODE_LOC($$, @1, @1);
2816 log_assert(*q == 0);
2817 delete $1;
2818 free(p);
2819 } |
2820 TOK_STRING {
2821 $$ = AstNode::mkconst_str(*$1);
2822 SET_AST_NODE_LOC($$, @1, @1);
2823 delete $1;
2824 } |
2825 hierarchical_id attr {
2826 AstNode *node = new AstNode(AST_FCALL);
2827 node->str = *$1;
2828 delete $1;
2829 ast_stack.push_back(node);
2830 SET_AST_NODE_LOC(node, @1, @1);
2831 append_attr(node, $2);
2832 } '(' arg_list optional_comma ')' {
2833 $$ = ast_stack.back();
2834 ast_stack.pop_back();
2835 } |
2836 TOK_TO_SIGNED attr '(' expr ')' {
2837 $$ = new AstNode(AST_TO_SIGNED, $4);
2838 append_attr($$, $2);
2839 } |
2840 TOK_TO_UNSIGNED attr '(' expr ')' {
2841 $$ = new AstNode(AST_TO_UNSIGNED, $4);
2842 append_attr($$, $2);
2843 } |
2844 '(' expr ')' {
2845 $$ = $2;
2846 } |
2847 '(' expr ':' expr ':' expr ')' {
2848 delete $2;
2849 $$ = $4;
2850 delete $6;
2851 } |
2852 '{' concat_list '}' {
2853 $$ = $2;
2854 } |
2855 '{' expr '{' concat_list '}' '}' {
2856 $$ = new AstNode(AST_REPLICATE, $2, $4);
2857 } |
2858 '~' attr basic_expr %prec UNARY_OPS {
2859 $$ = new AstNode(AST_BIT_NOT, $3);
2860 SET_AST_NODE_LOC($$, @1, @3);
2861 append_attr($$, $2);
2862 } |
2863 basic_expr '&' attr basic_expr {
2864 $$ = new AstNode(AST_BIT_AND, $1, $4);
2865 SET_AST_NODE_LOC($$, @1, @4);
2866 append_attr($$, $3);
2867 } |
2868 basic_expr OP_NAND attr basic_expr {
2869 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
2870 SET_AST_NODE_LOC($$, @1, @4);
2871 append_attr($$, $3);
2872 } |
2873 basic_expr '|' attr basic_expr {
2874 $$ = new AstNode(AST_BIT_OR, $1, $4);
2875 SET_AST_NODE_LOC($$, @1, @4);
2876 append_attr($$, $3);
2877 } |
2878 basic_expr OP_NOR attr basic_expr {
2879 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
2880 SET_AST_NODE_LOC($$, @1, @4);
2881 append_attr($$, $3);
2882 } |
2883 basic_expr '^' attr basic_expr {
2884 $$ = new AstNode(AST_BIT_XOR, $1, $4);
2885 SET_AST_NODE_LOC($$, @1, @4);
2886 append_attr($$, $3);
2887 } |
2888 basic_expr OP_XNOR attr basic_expr {
2889 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
2890 SET_AST_NODE_LOC($$, @1, @4);
2891 append_attr($$, $3);
2892 } |
2893 '&' attr basic_expr %prec UNARY_OPS {
2894 $$ = new AstNode(AST_REDUCE_AND, $3);
2895 SET_AST_NODE_LOC($$, @1, @3);
2896 append_attr($$, $2);
2897 } |
2898 OP_NAND attr basic_expr %prec UNARY_OPS {
2899 $$ = new AstNode(AST_REDUCE_AND, $3);
2900 SET_AST_NODE_LOC($$, @1, @3);
2901 append_attr($$, $2);
2902 $$ = new AstNode(AST_LOGIC_NOT, $$);
2903 } |
2904 '|' attr basic_expr %prec UNARY_OPS {
2905 $$ = new AstNode(AST_REDUCE_OR, $3);
2906 SET_AST_NODE_LOC($$, @1, @3);
2907 append_attr($$, $2);
2908 } |
2909 OP_NOR attr basic_expr %prec UNARY_OPS {
2910 $$ = new AstNode(AST_REDUCE_OR, $3);
2911 SET_AST_NODE_LOC($$, @1, @3);
2912 append_attr($$, $2);
2913 $$ = new AstNode(AST_LOGIC_NOT, $$);
2914 SET_AST_NODE_LOC($$, @1, @3);
2915 } |
2916 '^' attr basic_expr %prec UNARY_OPS {
2917 $$ = new AstNode(AST_REDUCE_XOR, $3);
2918 SET_AST_NODE_LOC($$, @1, @3);
2919 append_attr($$, $2);
2920 } |
2921 OP_XNOR attr basic_expr %prec UNARY_OPS {
2922 $$ = new AstNode(AST_REDUCE_XNOR, $3);
2923 SET_AST_NODE_LOC($$, @1, @3);
2924 append_attr($$, $2);
2925 } |
2926 basic_expr OP_SHL attr basic_expr {
2927 $$ = new AstNode(AST_SHIFT_LEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2928 SET_AST_NODE_LOC($$, @1, @4);
2929 append_attr($$, $3);
2930 } |
2931 basic_expr OP_SHR attr basic_expr {
2932 $$ = new AstNode(AST_SHIFT_RIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2933 SET_AST_NODE_LOC($$, @1, @4);
2934 append_attr($$, $3);
2935 } |
2936 basic_expr OP_SSHL attr basic_expr {
2937 $$ = new AstNode(AST_SHIFT_SLEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2938 SET_AST_NODE_LOC($$, @1, @4);
2939 append_attr($$, $3);
2940 } |
2941 basic_expr OP_SSHR attr basic_expr {
2942 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2943 SET_AST_NODE_LOC($$, @1, @4);
2944 append_attr($$, $3);
2945 } |
2946 basic_expr '<' attr basic_expr {
2947 $$ = new AstNode(AST_LT, $1, $4);
2948 SET_AST_NODE_LOC($$, @1, @4);
2949 append_attr($$, $3);
2950 } |
2951 basic_expr OP_LE attr basic_expr {
2952 $$ = new AstNode(AST_LE, $1, $4);
2953 SET_AST_NODE_LOC($$, @1, @4);
2954 append_attr($$, $3);
2955 } |
2956 basic_expr OP_EQ attr basic_expr {
2957 $$ = new AstNode(AST_EQ, $1, $4);
2958 SET_AST_NODE_LOC($$, @1, @4);
2959 append_attr($$, $3);
2960 } |
2961 basic_expr OP_NE attr basic_expr {
2962 $$ = new AstNode(AST_NE, $1, $4);
2963 SET_AST_NODE_LOC($$, @1, @4);
2964 append_attr($$, $3);
2965 } |
2966 basic_expr OP_EQX attr basic_expr {
2967 $$ = new AstNode(AST_EQX, $1, $4);
2968 SET_AST_NODE_LOC($$, @1, @4);
2969 append_attr($$, $3);
2970 } |
2971 basic_expr OP_NEX attr basic_expr {
2972 $$ = new AstNode(AST_NEX, $1, $4);
2973 SET_AST_NODE_LOC($$, @1, @4);
2974 append_attr($$, $3);
2975 } |
2976 basic_expr OP_GE attr basic_expr {
2977 $$ = new AstNode(AST_GE, $1, $4);
2978 SET_AST_NODE_LOC($$, @1, @4);
2979 append_attr($$, $3);
2980 } |
2981 basic_expr '>' attr basic_expr {
2982 $$ = new AstNode(AST_GT, $1, $4);
2983 SET_AST_NODE_LOC($$, @1, @4);
2984 append_attr($$, $3);
2985 } |
2986 basic_expr '+' attr basic_expr {
2987 $$ = new AstNode(AST_ADD, $1, $4);
2988 SET_AST_NODE_LOC($$, @1, @4);
2989 append_attr($$, $3);
2990 } |
2991 basic_expr '-' attr basic_expr {
2992 $$ = new AstNode(AST_SUB, $1, $4);
2993 SET_AST_NODE_LOC($$, @1, @4);
2994 append_attr($$, $3);
2995 } |
2996 basic_expr '*' attr basic_expr {
2997 $$ = new AstNode(AST_MUL, $1, $4);
2998 SET_AST_NODE_LOC($$, @1, @4);
2999 append_attr($$, $3);
3000 } |
3001 basic_expr '/' attr basic_expr {
3002 $$ = new AstNode(AST_DIV, $1, $4);
3003 SET_AST_NODE_LOC($$, @1, @4);
3004 append_attr($$, $3);
3005 } |
3006 basic_expr '%' attr basic_expr {
3007 $$ = new AstNode(AST_MOD, $1, $4);
3008 SET_AST_NODE_LOC($$, @1, @4);
3009 append_attr($$, $3);
3010 } |
3011 basic_expr OP_POW attr basic_expr {
3012 $$ = new AstNode(AST_POW, $1, $4);
3013 SET_AST_NODE_LOC($$, @1, @4);
3014 append_attr($$, $3);
3015 } |
3016 '+' attr basic_expr %prec UNARY_OPS {
3017 $$ = new AstNode(AST_POS, $3);
3018 SET_AST_NODE_LOC($$, @1, @3);
3019 append_attr($$, $2);
3020 } |
3021 '-' attr basic_expr %prec UNARY_OPS {
3022 $$ = new AstNode(AST_NEG, $3);
3023 SET_AST_NODE_LOC($$, @1, @3);
3024 append_attr($$, $2);
3025 } |
3026 basic_expr OP_LAND attr basic_expr {
3027 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
3028 SET_AST_NODE_LOC($$, @1, @4);
3029 append_attr($$, $3);
3030 } |
3031 basic_expr OP_LOR attr basic_expr {
3032 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
3033 SET_AST_NODE_LOC($$, @1, @4);
3034 append_attr($$, $3);
3035 } |
3036 '!' attr basic_expr %prec UNARY_OPS {
3037 $$ = new AstNode(AST_LOGIC_NOT, $3);
3038 SET_AST_NODE_LOC($$, @1, @3);
3039 append_attr($$, $2);
3040 } |
3041 TOK_SIGNED OP_CAST '(' expr ')' {
3042 if (!sv_mode)
3043 frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
3044 $$ = new AstNode(AST_TO_SIGNED, $4);
3045 SET_AST_NODE_LOC($$, @1, @4);
3046 } |
3047 TOK_UNSIGNED OP_CAST '(' expr ')' {
3048 if (!sv_mode)
3049 frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
3050 $$ = new AstNode(AST_TO_UNSIGNED, $4);
3051 SET_AST_NODE_LOC($$, @1, @4);
3052 } |
3053 basic_expr OP_CAST '(' expr ')' {
3054 if (!sv_mode)
3055 frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
3056 $$ = new AstNode(AST_CAST_SIZE, $1, $4);
3057 SET_AST_NODE_LOC($$, @1, @4);
3058 };
3059
3060 concat_list:
3061 expr {
3062 $$ = new AstNode(AST_CONCAT, $1);
3063 } |
3064 expr ',' concat_list {
3065 $$ = $3;
3066 $$->children.push_back($1);
3067 };
3068
3069 integral_number:
3070 TOK_CONSTVAL { $$ = $1; } |
3071 TOK_UNBASED_UNSIZED_CONSTVAL { $$ = $1; } |
3072 TOK_BASE TOK_BASED_CONSTVAL {
3073 $1->append(*$2);
3074 $$ = $1;
3075 delete $2;
3076 } |
3077 TOK_CONSTVAL TOK_BASE TOK_BASED_CONSTVAL {
3078 $1->append(*$2).append(*$3);
3079 $$ = $1;
3080 delete $2;
3081 delete $3;
3082 };