2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The Verilog frontend.
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
29 * This is the actual bison parser for Verilog code. The AST ist created directly
30 * from the bison reduce functions here. Note that this code uses a few global
31 * variables to hold the state of the AST generator and therefore this parser is
40 #include "frontends/verilog/verilog_frontend.h"
41 #include "frontends/verilog/verilog_parser.tab.hh"
42 #include "kernel/log.h"
44 #define YYLEX_PARAM &yylval, &yylloc
48 using namespace VERILOG_FRONTEND;
51 namespace VERILOG_FRONTEND {
53 dict<std::string, int> port_stubs;
54 dict<IdString, AstNode*> *attr_list, default_attr_list;
55 std::stack<dict<IdString, AstNode*> *> attr_list_stack;
56 dict<IdString, AstNode*> *albuf;
57 std::vector<UserTypeMap*> user_type_stack;
58 dict<std::string, AstNode*> pkg_user_types;
59 std::vector<AstNode*> ast_stack;
60 struct AstNode *astbuf1, *astbuf2, *astbuf3;
61 struct AstNode *current_function_or_task;
62 struct AstNode *current_ast, *current_ast_mod;
63 int current_function_or_task_port_id;
64 std::vector<char> case_type_stack;
65 bool do_not_require_port_stubs;
66 bool default_nettype_wire;
67 bool sv_mode, formal_mode, lib_mode, specify_mode;
68 bool noassert_mode, noassume_mode, norestrict_mode;
69 bool assume_asserts_mode, assert_assumes_mode;
70 bool current_wire_rand, current_wire_const;
71 bool current_modport_input, current_modport_output;
76 #define SET_AST_NODE_LOC(WHICH, BEGIN, END) \
77 do { (WHICH)->location.first_line = (BEGIN).first_line; \
78 (WHICH)->location.first_column = (BEGIN).first_column; \
79 (WHICH)->location.last_line = (END).last_line; \
80 (WHICH)->location.last_column = (END).last_column; } while(0)
82 #define SET_RULE_LOC(LHS, BEGIN, END) \
83 do { (LHS).first_line = (BEGIN).first_line; \
84 (LHS).first_column = (BEGIN).first_column; \
85 (LHS).last_line = (END).last_line; \
86 (LHS).last_column = (END).last_column; } while(0)
88 int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
90 static void append_attr(AstNode *ast, dict<IdString, AstNode*> *al)
92 for (auto &it : *al) {
93 if (ast->attributes.count(it.first) > 0)
94 delete ast->attributes[it.first];
95 ast->attributes[it.first] = it.second;
100 static void append_attr_clone(AstNode *ast, dict<IdString, AstNode*> *al)
102 for (auto &it : *al) {
103 if (ast->attributes.count(it.first) > 0)
104 delete ast->attributes[it.first];
105 ast->attributes[it.first] = it.second->clone();
109 static void free_attr(dict<IdString, AstNode*> *al)
116 struct specify_target {
121 struct specify_triple {
122 AstNode *t_min, *t_avg, *t_max;
125 struct specify_rise_fall {
130 static void addTypedefNode(std::string *name, AstNode *node)
133 auto *tnode = new AstNode(AST_TYPEDEF, node);
135 auto user_types = user_type_stack.back();
136 (*user_types)[*name] = tnode;
137 if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {
138 // typedef inside a package so we need the qualified name
139 auto qname = current_ast_mod->str + "::" + (*name).substr(1);
140 pkg_user_types[qname] = tnode;
143 ast_stack.back()->children.push_back(tnode);
146 static void enterTypeScope()
148 auto user_types = new UserTypeMap();
149 user_type_stack.push_back(user_types);
152 static void exitTypeScope()
154 user_type_stack.pop_back();
157 static bool isInLocalScope(const std::string *name)
159 // tests if a name was declared in the current block scope
160 auto user_types = user_type_stack.back();
161 return (user_types->count(*name) > 0);
164 static AstNode *getTypeDefinitionNode(std::string type_name)
166 // return the definition nodes from the typedef statement
167 auto user_types = user_type_stack.back();
168 log_assert(user_types->count(type_name) > 0);
169 auto typedef_node = (*user_types)[type_name];
170 log_assert(typedef_node->type == AST_TYPEDEF);
171 return typedef_node->children[0];
174 static AstNode *copyTypeDefinition(std::string type_name)
176 // return a copy of the template from a typedef definition
177 auto typedef_node = getTypeDefinitionNode(type_name);
178 return typedef_node->clone();
181 static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
183 auto range = new AstNode(AST_RANGE);
184 range->children.push_back(AstNode::mkconst_int(msb, true));
185 range->children.push_back(AstNode::mkconst_int(lsb, true));
186 range->is_signed = isSigned;
190 static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned = true)
192 auto range = makeRange(msb, lsb, isSigned);
193 parent->children.push_back(range);
196 static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
198 if (type_node->range_left >= 0 && type_node->range_right >= 0) {
199 // type already restricts the range
201 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
204 range_node = makeRange(type_node->range_left, type_node->range_right, false);
207 if (range_node && range_node->children.size() != 2) {
208 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
213 static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
215 node->type = AST_MEMORY;
216 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
217 // SV array size [n], rewrite as [n-1:0]
218 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
219 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
221 node->children.push_back(rangeNode);
226 %define api.prefix {frontend_verilog_yy}
229 /* The union is defined in the header, so we need to provide all the
230 * includes it requires
235 #include "frontends/verilog/verilog_frontend.h"
240 struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
241 YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
242 struct specify_target *specify_target_ptr;
243 struct specify_triple *specify_triple_ptr;
244 struct specify_rise_fall *specify_rise_fall_ptr;
249 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
250 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
251 %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL
252 %token <string> TOK_USER_TYPE TOK_PKG_USER_TYPE
253 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
254 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
255 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
256 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
257 %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
258 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
259 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_PLUS_ASSIGN TOK_ALWAYS TOK_INITIAL
260 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
261 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
262 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
263 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
264 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
265 %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
266 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
267 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
268 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
269 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
270 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
271 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
272 %token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_UNION
273 %token TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AND_ASSIGN TOK_SUB_ASSIGN
275 %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
276 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
277 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
278 %type <string> type_name
279 %type <ast> opt_enum_init enum_type struct_type non_wire_data_type
280 %type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
281 %type <al> attr case_attr
282 %type <ast> struct_union
284 %type <specify_target_ptr> specify_target
285 %type <specify_triple_ptr> specify_triple specify_opt_triple
286 %type <specify_rise_fall_ptr> specify_rise_fall
287 %type <ast> specify_if specify_condition
288 %type <ch> specify_edge
290 // operator precedence from low to high
296 %left OP_EQ OP_NE OP_EQX OP_NEX
297 %left '<' OP_LE OP_GE '>'
298 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
305 %define parse.error verbose
306 %define parse.lac full
318 ast_stack.push_back(current_ast);
320 ast_stack.pop_back();
321 log_assert(GetSize(ast_stack) == 0);
322 for (auto &it : default_attr_list)
324 default_attr_list.clear();
330 task_func_decl design |
332 localparam_decl design |
333 typedef_decl design |
340 if (attr_list != nullptr)
341 attr_list_stack.push(attr_list);
342 attr_list = new dict<IdString, AstNode*>;
343 for (auto &it : default_attr_list)
344 (*attr_list)[it.first] = it.second->clone();
347 if (!attr_list_stack.empty()) {
348 attr_list = attr_list_stack.top();
349 attr_list_stack.pop();
355 attr_opt ATTR_BEGIN opt_attr_list ATTR_END {
356 SET_RULE_LOC(@$, @2, @$);
362 if (attr_list != nullptr)
363 attr_list_stack.push(attr_list);
364 attr_list = new dict<IdString, AstNode*>;
365 for (auto &it : default_attr_list)
367 default_attr_list.clear();
369 attr_list->swap(default_attr_list);
371 if (!attr_list_stack.empty()) {
372 attr_list = attr_list_stack.top();
373 attr_list_stack.pop();
383 attr_list ',' attr_assign;
387 if (attr_list->count(*$1) != 0)
388 delete (*attr_list)[*$1];
389 (*attr_list)[*$1] = AstNode::mkconst_int(1, false);
392 hierarchical_id '=' expr {
393 if (attr_list->count(*$1) != 0)
394 delete (*attr_list)[*$1];
395 (*attr_list)[*$1] = $3;
403 hierarchical_id TOK_PACKAGESEP TOK_ID {
404 if ($3->compare(0, 1, "\\") == 0)
405 *$1 += "::" + $3->substr(1);
411 hierarchical_id '.' TOK_ID {
412 if ($3->compare(0, 1, "\\") == 0)
413 *$1 += "." + $3->substr(1);
420 hierarchical_type_id:
422 | TOK_PKG_USER_TYPE // package qualified type name
423 | '(' TOK_USER_TYPE ')' { $$ = $2; } // non-standard grammar
430 do_not_require_port_stubs = false;
431 AstNode *mod = new AstNode(AST_MODULE);
432 ast_stack.back()->children.push_back(mod);
433 ast_stack.push_back(mod);
434 current_ast_mod = mod;
438 append_attr(mod, $1);
440 } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE opt_label {
441 if (port_stubs.size() != 0)
442 frontend_verilog_yyerror("Missing details for module port `%s'.",
443 port_stubs.begin()->first.c_str());
444 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
445 ast_stack.pop_back();
446 log_assert(ast_stack.size() == 1);
447 current_ast_mod = NULL;
452 '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | %empty;
455 single_module_para | module_para_list ',' single_module_para;
460 if (astbuf1) delete astbuf1;
461 astbuf1 = new AstNode(AST_PARAMETER);
462 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
463 append_attr(astbuf1, $1);
464 } param_type single_param_decl |
465 attr TOK_LOCALPARAM {
466 if (astbuf1) delete astbuf1;
467 astbuf1 = new AstNode(AST_LOCALPARAM);
468 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
469 append_attr(astbuf1, $1);
470 } param_type single_param_decl |
474 '(' ')' | %empty | '(' module_args optional_comma ')';
477 module_arg | module_args ',' module_arg;
482 module_arg_opt_assignment:
484 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
485 AstNode *wire = new AstNode(AST_IDENTIFIER);
486 wire->str = ast_stack.back()->children.back()->str;
487 if (ast_stack.back()->children.back()->is_input) {
488 AstNode *n = ast_stack.back()->children.back();
489 if (n->attributes.count(ID::defaultvalue))
490 delete n->attributes.at(ID::defaultvalue);
491 n->attributes[ID::defaultvalue] = $2;
493 if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
494 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
496 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
498 frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
504 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
505 AstNode *node = ast_stack.back()->children.back()->clone();
507 node->port_id = ++port_counter;
508 ast_stack.back()->children.push_back(node);
509 SET_AST_NODE_LOC(node, @1, @1);
511 if (port_stubs.count(*$1) != 0)
512 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
513 port_stubs[*$1] = ++port_counter;
516 } module_arg_opt_assignment |
518 astbuf1 = new AstNode(AST_INTERFACEPORT);
519 astbuf1->children.push_back(new AstNode(AST_INTERFACEPORTTYPE));
520 astbuf1->children[0]->str = *$1;
522 } TOK_ID { /* SV interfaces */
524 frontend_verilog_yyerror("Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
525 astbuf2 = astbuf1->clone(); // really only needed if multiple instances of same type.
528 astbuf2->port_id = ++port_counter;
529 ast_stack.back()->children.push_back(astbuf2);
530 delete astbuf1; // really only needed if multiple instances of same type.
531 } module_arg_opt_assignment |
532 attr wire_type range TOK_ID {
535 SET_AST_NODE_LOC(node, @4, @4);
536 node->port_id = ++port_counter;
538 node->children.push_back($3);
539 if (!node->is_input && !node->is_output)
540 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
541 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
542 frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
543 ast_stack.back()->children.push_back(node);
544 append_attr(node, $1);
546 } module_arg_opt_assignment |
548 do_not_require_port_stubs = true;
555 AstNode *mod = new AstNode(AST_PACKAGE);
556 ast_stack.back()->children.push_back(mod);
557 ast_stack.push_back(mod);
558 current_ast_mod = mod;
560 append_attr(mod, $1);
561 } ';' package_body TOK_ENDPACKAGE opt_label {
562 ast_stack.pop_back();
563 current_ast_mod = NULL;
568 package_body package_body_stmt | %empty;
571 typedef_decl | localparam_decl | param_decl;
577 do_not_require_port_stubs = false;
578 AstNode *intf = new AstNode(AST_INTERFACE);
579 ast_stack.back()->children.push_back(intf);
580 ast_stack.push_back(intf);
581 current_ast_mod = intf;
586 } module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
587 if (port_stubs.size() != 0)
588 frontend_verilog_yyerror("Missing details for module port `%s'.",
589 port_stubs.begin()->first.c_str());
590 ast_stack.pop_back();
591 log_assert(ast_stack.size() == 1);
592 current_ast_mod = NULL;
597 interface_body interface_body_stmt | %empty;
600 param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
604 '#' TOK_ID { delete $2; } |
605 '#' TOK_CONSTVAL { delete $2; } |
606 '#' TOK_REALVAL { delete $2; } |
607 '#' '(' expr ')' { delete $3; } |
608 '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
611 non_opt_delay | %empty;
615 astbuf3 = new AstNode(AST_WIRE);
616 current_wire_rand = false;
617 current_wire_const = false;
618 } wire_type_token_list {
620 SET_RULE_LOC(@$, @2, @$);
623 wire_type_token_list:
625 wire_type_token_list wire_type_token |
627 hierarchical_type_id {
628 astbuf3->is_custom_type = true;
629 astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
630 astbuf3->children.back()->str = *$1;
636 astbuf3->is_input = true;
639 astbuf3->is_output = true;
642 astbuf3->is_input = true;
643 astbuf3->is_output = true;
650 astbuf3->is_wor = true;
653 astbuf3->is_wand = true;
656 astbuf3->is_reg = true;
659 astbuf3->is_logic = true;
662 astbuf3->is_logic = true;
665 astbuf3->is_reg = true;
666 astbuf3->range_left = 31;
667 astbuf3->range_right = 0;
668 astbuf3->is_signed = true;
671 astbuf3->type = AST_GENVAR;
672 astbuf3->is_reg = true;
673 astbuf3->is_signed = true;
674 astbuf3->range_left = 31;
675 astbuf3->range_right = 0;
678 astbuf3->is_signed = true;
681 current_wire_rand = true;
684 current_wire_const = true;
688 '[' expr ':' expr ']' {
689 $$ = new AstNode(AST_RANGE);
690 $$->children.push_back($2);
691 $$->children.push_back($4);
693 '[' expr TOK_POS_INDEXED expr ']' {
694 $$ = new AstNode(AST_RANGE);
695 AstNode *expr = new AstNode(AST_SELFSZ, $2);
696 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
697 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
699 '[' expr TOK_NEG_INDEXED expr ']' {
700 $$ = new AstNode(AST_RANGE);
701 AstNode *expr = new AstNode(AST_SELFSZ, $2);
702 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
703 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
706 $$ = new AstNode(AST_RANGE);
707 $$->children.push_back($2);
711 non_opt_range non_opt_range {
712 $$ = new AstNode(AST_MULTIRANGE, $1, $2);
714 non_opt_multirange non_opt_range {
716 $$->children.push_back($2);
729 non_opt_multirange { $$ = $1; };
733 | TOK_INTEGER { $$ = makeRange(); }
737 module_body module_body_stmt |
738 /* the following line makes the generate..endgenrate keywords optional */
739 module_body gen_stmt |
744 task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
745 enum_decl | struct_decl |
746 always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
749 TOK_CHECKER TOK_ID ';' {
750 AstNode *node = new AstNode(AST_GENBLOCK);
752 ast_stack.back()->children.push_back(node);
753 ast_stack.push_back(node);
754 } module_body TOK_ENDCHECKER {
756 ast_stack.pop_back();
760 attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
761 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
762 current_function_or_task->str = *$4;
763 append_attr(current_function_or_task, $1);
764 ast_stack.back()->children.push_back(current_function_or_task);
767 } opt_dpi_function_args ';' {
768 current_function_or_task = NULL;
770 attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
771 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
772 current_function_or_task->str = *$6;
773 append_attr(current_function_or_task, $1);
774 ast_stack.back()->children.push_back(current_function_or_task);
778 } opt_dpi_function_args ';' {
779 current_function_or_task = NULL;
781 attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
782 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
783 current_function_or_task->str = *$8;
784 append_attr(current_function_or_task, $1);
785 ast_stack.back()->children.push_back(current_function_or_task);
790 } opt_dpi_function_args ';' {
791 current_function_or_task = NULL;
793 attr TOK_TASK opt_automatic TOK_ID {
794 current_function_or_task = new AstNode(AST_TASK);
795 current_function_or_task->str = *$4;
796 append_attr(current_function_or_task, $1);
797 ast_stack.back()->children.push_back(current_function_or_task);
798 ast_stack.push_back(current_function_or_task);
799 current_function_or_task_port_id = 1;
801 } task_func_args_opt ';' task_func_body TOK_ENDTASK {
802 current_function_or_task = NULL;
803 ast_stack.pop_back();
805 attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID {
806 current_function_or_task = new AstNode(AST_FUNCTION);
807 current_function_or_task->str = *$6;
808 append_attr(current_function_or_task, $1);
809 ast_stack.back()->children.push_back(current_function_or_task);
810 ast_stack.push_back(current_function_or_task);
811 AstNode *outreg = new AstNode(AST_WIRE);
813 outreg->is_signed = $4;
814 outreg->is_reg = true;
816 outreg->children.push_back($5);
817 outreg->is_signed = $4 || $5->is_signed;
818 $5->is_signed = false;
820 current_function_or_task->children.push_back(outreg);
821 current_function_or_task_port_id = 1;
823 } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
824 current_function_or_task = NULL;
825 ast_stack.pop_back();
830 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
835 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
839 opt_dpi_function_args:
840 '(' dpi_function_args ')' |
844 dpi_function_args ',' dpi_function_arg |
845 dpi_function_args ',' |
862 '(' ')' | %empty | '(' {
866 } task_func_args optional_comma {
874 task_func_port | task_func_args ',' task_func_port;
877 attr wire_type range {
886 astbuf2 = checkRange(astbuf1, $3);
891 frontend_verilog_yyerror("task/function argument direction missing");
892 albuf = new dict<IdString, AstNode*>;
893 astbuf1 = new AstNode(AST_WIRE);
894 current_wire_rand = false;
895 current_wire_const = false;
896 astbuf1->is_input = true;
902 task_func_body behavioral_stmt |
905 /*************************** specify parser ***************************/
908 TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
911 specify_item specify_item_list |
915 specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
916 AstNode *en_expr = $1;
917 char specify_edge = $3;
918 AstNode *src_expr = $4;
920 specify_target *target = $6;
921 specify_rise_fall *timing = $9;
923 if (specify_edge != 0 && target->dat == nullptr)
924 frontend_verilog_yyerror("Found specify edge but no data spec.\n");
926 AstNode *cell = new AstNode(AST_CELL);
927 ast_stack.back()->children.push_back(cell);
928 cell->str = stringf("$specify$%d", autoidx++);
929 cell->children.push_back(new AstNode(AST_CELLTYPE));
930 cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
931 SET_AST_NODE_LOC(cell, en_expr ? @1 : @2, @10);
933 char oper_polarity = 0;
934 char oper_type = oper->at(0);
936 if (oper->size() == 3) {
937 oper_polarity = oper->at(0);
938 oper_type = oper->at(1);
941 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
942 cell->children.back()->str = "\\FULL";
944 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
945 cell->children.back()->str = "\\SRC_DST_PEN";
947 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
948 cell->children.back()->str = "\\SRC_DST_POL";
950 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
951 cell->children.back()->str = "\\T_RISE_MIN";
953 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
954 cell->children.back()->str = "\\T_RISE_TYP";
956 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
957 cell->children.back()->str = "\\T_RISE_MAX";
959 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
960 cell->children.back()->str = "\\T_FALL_MIN";
962 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
963 cell->children.back()->str = "\\T_FALL_TYP";
965 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
966 cell->children.back()->str = "\\T_FALL_MAX";
968 cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
969 cell->children.back()->str = "\\EN";
971 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
972 cell->children.back()->str = "\\SRC";
974 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
975 cell->children.back()->str = "\\DST";
979 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
980 cell->children.back()->str = "\\EDGE_EN";
982 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
983 cell->children.back()->str = "\\EDGE_POL";
985 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
986 cell->children.back()->str = "\\DAT_DST_PEN";
988 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
989 cell->children.back()->str = "\\DAT_DST_POL";
991 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
992 cell->children.back()->str = "\\DAT";
999 TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' specify_triple specify_opt_triple ')' ';' {
1000 if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
1001 *$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
1002 frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
1004 AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
1005 AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
1006 AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
1008 AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
1009 AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
1010 AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
1012 specify_triple *limit = $11;
1013 specify_triple *limit2 = $12;
1015 AstNode *cell = new AstNode(AST_CELL);
1016 ast_stack.back()->children.push_back(cell);
1017 cell->str = stringf("$specify$%d", autoidx++);
1018 cell->children.push_back(new AstNode(AST_CELLTYPE));
1019 cell->children.back()->str = "$specrule";
1020 SET_AST_NODE_LOC(cell, @1, @14);
1022 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
1023 cell->children.back()->str = "\\TYPE";
1025 cell->children.push_back(new AstNode(AST_PARASET, limit->t_min));
1026 cell->children.back()->str = "\\T_LIMIT_MIN";
1028 cell->children.push_back(new AstNode(AST_PARASET, limit->t_avg));
1029 cell->children.back()->str = "\\T_LIMIT_TYP";
1031 cell->children.push_back(new AstNode(AST_PARASET, limit->t_max));
1032 cell->children.back()->str = "\\T_LIMIT_MAX";
1034 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_min : AstNode::mkconst_int(0, true)));
1035 cell->children.back()->str = "\\T_LIMIT2_MIN";
1037 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_avg : AstNode::mkconst_int(0, true)));
1038 cell->children.back()->str = "\\T_LIMIT2_TYP";
1040 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_max : AstNode::mkconst_int(0, true)));
1041 cell->children.back()->str = "\\T_LIMIT2_MAX";
1043 cell->children.push_back(new AstNode(AST_PARASET, src_pen));
1044 cell->children.back()->str = "\\SRC_PEN";
1046 cell->children.push_back(new AstNode(AST_PARASET, src_pol));
1047 cell->children.back()->str = "\\SRC_POL";
1049 cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
1050 cell->children.back()->str = "\\DST_PEN";
1052 cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
1053 cell->children.back()->str = "\\DST_POL";
1055 cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
1056 cell->children.back()->str = "\\SRC_EN";
1058 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
1059 cell->children.back()->str = "\\SRC";
1061 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
1062 cell->children.back()->str = "\\DST_EN";
1064 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
1065 cell->children.back()->str = "\\DST";
1071 ',' specify_triple {
1079 TOK_IF '(' expr ')' {
1087 TOK_SPECIFY_AND expr {
1096 $$ = new specify_target;
1097 $$->polarity_op = 0;
1101 '(' expr ':' expr ')'{
1102 $$ = new specify_target;
1103 $$->polarity_op = 0;
1107 '(' expr TOK_NEG_INDEXED expr ')'{
1108 $$ = new specify_target;
1109 $$->polarity_op = '-';
1113 '(' expr TOK_POS_INDEXED expr ')'{
1114 $$ = new specify_target;
1115 $$->polarity_op = '+';
1121 TOK_POSEDGE { $$ = 'p'; } |
1122 TOK_NEGEDGE { $$ = 'n'; } |
1127 $$ = new specify_rise_fall;
1129 $$->fall.t_min = $1->t_min->clone();
1130 $$->fall.t_avg = $1->t_avg->clone();
1131 $$->fall.t_max = $1->t_max->clone();
1134 '(' specify_triple ',' specify_triple ')' {
1135 $$ = new specify_rise_fall;
1141 '(' specify_triple ',' specify_triple ',' specify_triple ')' {
1142 $$ = new specify_rise_fall;
1148 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1150 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1151 $$ = new specify_rise_fall;
1160 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1162 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1163 $$ = new specify_rise_fall;
1178 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1183 $$ = new specify_triple;
1185 $$->t_avg = $1->clone();
1186 $$->t_max = $1->clone();
1188 expr ':' expr ':' expr {
1189 $$ = new specify_triple;
1195 /******************** ignored specify parser **************************/
1197 ignored_specify_block:
1198 TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
1199 TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
1201 ignored_specify_item_opt:
1202 ignored_specify_item_opt ignored_specify_item |
1203 ignored_specify_item ;
1205 ignored_specify_item:
1206 specparam_declaration
1207 // | pulsestyle_declaration
1208 // | showcancelled_declaration
1210 | system_timing_declaration
1213 specparam_declaration:
1214 TOK_SPECPARAM list_of_specparam_assignments ';' |
1215 TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ;
1217 // IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match
1218 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
1219 // exxxxtending this for SV specparam would change this anyhow
1221 '[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
1223 list_of_specparam_assignments:
1224 specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
1226 specparam_assignment:
1227 ignspec_id '=' ignspec_expr ;
1230 TOK_IF '(' ignspec_expr ')' | %empty;
1233 simple_path_declaration ';'
1234 // | edge_sensitive_path_declaration
1235 // | state_dependent_path_declaration
1238 simple_path_declaration :
1239 ignspec_opt_cond parallel_path_description '=' path_delay_value |
1240 ignspec_opt_cond full_path_description '=' path_delay_value
1244 '(' ignspec_expr list_of_path_delay_extra_expressions ')'
1246 | ignspec_expr list_of_path_delay_extra_expressions
1249 list_of_path_delay_extra_expressions :
1251 | ',' ignspec_expr list_of_path_delay_extra_expressions
1254 specify_edge_identifier :
1255 TOK_POSEDGE | TOK_NEGEDGE ;
1257 parallel_path_description :
1258 '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
1259 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
1260 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
1262 full_path_description :
1263 '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
1264 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
1265 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
1267 // This was broken into 2 rules to solve shift/reduce conflicts
1268 list_of_path_inputs :
1269 specify_input_terminal_descriptor opt_polarity_operator |
1270 specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
1273 ',' specify_input_terminal_descriptor |
1274 more_path_inputs ',' specify_input_terminal_descriptor ;
1276 list_of_path_outputs :
1277 specify_output_terminal_descriptor |
1278 list_of_path_outputs ',' specify_output_terminal_descriptor ;
1280 opt_polarity_operator :
1283 // Good enough for the time being
1284 specify_input_terminal_descriptor :
1287 // Good enough for the time being
1288 specify_output_terminal_descriptor :
1291 system_timing_declaration :
1292 ignspec_id '(' system_timing_args ')' ';' ;
1295 TOK_POSEDGE ignspec_id |
1296 TOK_NEGEDGE ignspec_id |
1299 system_timing_args :
1301 system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
1302 system_timing_args ',' system_timing_arg ;
1304 // for the time being this is OK, but we may write our own expr here.
1305 // as I'm not sure it is legal to use a full expr here (probably not)
1306 // On the other hand, other rules requiring constant expressions also use 'expr'
1307 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
1308 ignspec_constant_expression:
1309 expr { delete $1; };
1312 expr { delete $1; } |
1313 expr ':' expr ':' expr {
1320 TOK_ID { delete $1; }
1321 range_or_multirange { delete $3; };
1323 /**********************************************************************/
1327 astbuf1->is_signed = true;
1329 astbuf1->is_signed = false;
1334 astbuf1->children.push_back(new AstNode(AST_RANGE));
1335 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
1336 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
1337 astbuf1->is_signed = true;
1342 astbuf1->children.push_back(new AstNode(AST_REALVALUE));
1348 astbuf1->children.push_back($1);
1352 param_integer_type: param_integer param_signed;
1353 param_range_type: type_vec param_signed param_range;
1354 param_implicit_type: param_signed param_range;
1357 param_integer_type | param_real | param_range_type | param_implicit_type |
1358 hierarchical_type_id {
1359 astbuf1->is_custom_type = true;
1360 astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
1361 astbuf1->children.back()->str = *$1;
1365 attr TOK_PARAMETER {
1366 astbuf1 = new AstNode(AST_PARAMETER);
1367 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1368 append_attr(astbuf1, $1);
1369 } param_type param_decl_list ';' {
1374 attr TOK_LOCALPARAM {
1375 astbuf1 = new AstNode(AST_LOCALPARAM);
1376 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1377 append_attr(astbuf1, $1);
1378 } param_type param_decl_list ';' {
1383 single_param_decl | param_decl_list ',' single_param_decl;
1388 if (astbuf1 == nullptr) {
1390 frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword");
1391 node = new AstNode(AST_PARAMETER);
1392 node->children.push_back(AstNode::mkconst_int(0, true));
1394 node = astbuf1->clone();
1397 delete node->children[0];
1398 node->children[0] = $3;
1399 ast_stack.back()->children.push_back(node);
1404 TOK_DEFPARAM defparam_decl_list ';';
1407 single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
1409 single_defparam_decl:
1410 range rvalue '=' expr {
1411 AstNode *node = new AstNode(AST_DEFPARAM);
1412 node->children.push_back($2);
1413 node->children.push_back($4);
1415 node->children.push_back($1);
1416 ast_stack.back()->children.push_back(node);
1423 enum_type: TOK_ENUM {
1424 static int enum_count;
1425 // create parent node for the enum
1426 astbuf2 = new AstNode(AST_ENUM);
1427 ast_stack.back()->children.push_back(astbuf2);
1428 astbuf2->str = std::string("$enum");
1429 astbuf2->str += std::to_string(enum_count++);
1430 // create the template for the names
1431 astbuf1 = new AstNode(AST_ENUM_ITEM);
1432 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1433 } enum_base_type '{' enum_name_list '}' { // create template for the enum vars
1434 auto tnode = astbuf1->clone();
1437 tnode->type = AST_WIRE;
1438 tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
1439 // drop constant but keep any range
1440 delete tnode->children[0];
1441 tnode->children.erase(tnode->children.begin());
1445 enum_base_type: type_atom type_signing
1446 | type_vec type_signing range { if ($3) astbuf1->children.push_back($3); }
1447 | %empty { astbuf1->is_reg = true; addRange(astbuf1); }
1450 type_atom: TOK_INTEGER { astbuf1->is_reg = true; addRange(astbuf1); } // 4-state signed
1451 | TOK_INT { astbuf1->is_reg = true; addRange(astbuf1); } // 2-state signed
1452 | TOK_SHORTINT { astbuf1->is_reg = true; addRange(astbuf1, 15, 0); } // 2-state signed
1453 | TOK_BYTE { astbuf1->is_reg = true; addRange(astbuf1, 7, 0); } // 2-state signed
1456 type_vec: TOK_REG { astbuf1->is_reg = true; } // unsigned
1457 | TOK_LOGIC { astbuf1->is_logic = true; } // unsigned
1461 TOK_SIGNED { astbuf1->is_signed = true; }
1462 | TOK_UNSIGNED { astbuf1->is_signed = false; }
1466 enum_name_list: enum_name_decl
1467 | enum_name_list ',' enum_name_decl
1471 TOK_ID opt_enum_init {
1473 log_assert(astbuf1);
1474 log_assert(astbuf2);
1475 auto node = astbuf1->clone();
1478 SET_AST_NODE_LOC(node, @1, @1);
1479 delete node->children[0];
1480 node->children[0] = $2 ? $2 : new AstNode(AST_NONE);
1481 astbuf2->children.push_back(node);
1486 '=' basic_expr { $$ = $2; } // TODO: restrict this
1487 | %empty { $$ = NULL; }
1492 | enum_var_list ',' enum_var
1496 log_assert(astbuf1);
1497 log_assert(astbuf2);
1498 auto node = astbuf1->clone();
1499 ast_stack.back()->children.push_back(node);
1502 SET_AST_NODE_LOC(node, @1, @1);
1503 node->is_enum = true;
1507 enum_decl: enum_type enum_var_list ';' { delete $1; }
1514 struct_decl: struct_type struct_var_list ';' { delete astbuf2; }
1517 struct_type: struct_union { astbuf2 = $1; } struct_body { $$ = astbuf2; }
1521 TOK_STRUCT { $$ = new AstNode(AST_STRUCT); }
1522 | TOK_UNION { $$ = new AstNode(AST_UNION); }
1525 struct_body: opt_packed '{' struct_member_list '}'
1529 TOK_PACKED opt_signed_struct |
1530 %empty { frontend_verilog_yyerror("Only PACKED supported at this time"); };
1533 TOK_SIGNED { astbuf2->is_signed = true; }
1534 | TOK_UNSIGNED { astbuf2->is_signed = false; }
1535 | %empty // default is unsigned
1538 struct_member_list: struct_member
1539 | struct_member_list struct_member
1542 struct_member: struct_member_type member_name_list ';' { delete astbuf1; }
1547 | member_name_list ',' member_name
1550 member_name: TOK_ID {
1551 astbuf1->str = $1->substr(1);
1553 astbuf3 = astbuf1->clone();
1554 SET_AST_NODE_LOC(astbuf3, @1, @1);
1555 astbuf2->children.push_back(astbuf3);
1556 } range { if ($3) astbuf3->children.push_back($3); }
1559 struct_member_type: { astbuf1 = new AstNode(AST_STRUCT_ITEM); } member_type_token
1564 | hierarchical_type_id {
1565 // use a clone of the typedef definition nodes
1566 auto template_node = copyTypeDefinition(*$1);
1568 switch (template_node->type) {
1570 template_node->type = AST_STRUCT_ITEM;
1576 frontend_verilog_yyerror("Invalid type for struct member: %s", type2str(template_node->type).c_str());
1579 astbuf1 = template_node;
1582 // stash state on ast_stack
1583 ast_stack.push_back(astbuf2);
1588 astbuf2 = ast_stack.back();
1589 ast_stack.pop_back();
1593 member_type: type_atom type_signing
1594 | type_vec type_signing range_or_multirange { if ($3) astbuf1->children.push_back($3); }
1597 struct_var_list: struct_var
1598 | struct_var_list ',' struct_var
1601 struct_var: TOK_ID { auto *var_node = astbuf2->clone();
1602 var_node->str = *$1;
1604 SET_AST_NODE_LOC(var_node, @1, @1);
1605 ast_stack.back()->children.push_back(var_node);
1614 attr wire_type range {
1617 astbuf2 = checkRange(astbuf1, $3);
1618 } delay wire_name_list {
1620 if (astbuf2 != NULL)
1624 attr TOK_SUPPLY0 TOK_ID {
1625 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1626 ast_stack.back()->children.back()->str = *$3;
1627 append_attr(ast_stack.back()->children.back(), $1);
1628 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
1629 ast_stack.back()->children.back()->children[0]->str = *$3;
1631 } opt_supply_wires ';' |
1632 attr TOK_SUPPLY1 TOK_ID {
1633 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1634 ast_stack.back()->children.back()->str = *$3;
1635 append_attr(ast_stack.back()->children.back(), $1);
1636 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
1637 ast_stack.back()->children.back()->children[0]->str = *$3;
1639 } opt_supply_wires ';';
1643 opt_supply_wires ',' TOK_ID {
1644 AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
1645 AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
1646 wire_node->str = *$3;
1647 assign_node->children[0]->str = *$3;
1648 ast_stack.back()->children.push_back(wire_node);
1649 ast_stack.back()->children.push_back(assign_node);
1654 wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
1656 wire_name_and_opt_assign:
1658 bool attr_anyconst = false;
1659 bool attr_anyseq = false;
1660 bool attr_allconst = false;
1661 bool attr_allseq = false;
1662 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
1663 delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
1664 ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
1665 attr_anyconst = true;
1667 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
1668 delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
1669 ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
1672 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
1673 delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
1674 ast_stack.back()->children.back()->attributes.erase(ID::allconst);
1675 attr_allconst = true;
1677 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
1678 delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
1679 ast_stack.back()->children.back()->attributes.erase(ID::allseq);
1682 if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
1683 AstNode *wire = new AstNode(AST_IDENTIFIER);
1684 AstNode *fcall = new AstNode(AST_FCALL);
1685 wire->str = ast_stack.back()->children.back()->str;
1686 fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
1688 fcall->str = "\\$anyconst";
1690 fcall->str = "\\$anyseq";
1692 fcall->str = "\\$allconst";
1694 fcall->str = "\\$allseq";
1695 fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
1696 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
1699 wire_name '=' expr {
1700 AstNode *wire = new AstNode(AST_IDENTIFIER);
1701 wire->str = ast_stack.back()->children.back()->str;
1702 if (astbuf1->is_input) {
1703 if (astbuf1->attributes.count(ID::defaultvalue))
1704 delete astbuf1->attributes.at(ID::defaultvalue);
1705 astbuf1->attributes[ID::defaultvalue] = $3;
1707 else if (astbuf1->is_reg || astbuf1->is_logic){
1708 AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
1709 AstNode *block = new AstNode(AST_BLOCK, assign);
1710 AstNode *init = new AstNode(AST_INITIAL, block);
1712 SET_AST_NODE_LOC(assign, @1, @3);
1713 SET_AST_NODE_LOC(block, @1, @3);
1714 SET_AST_NODE_LOC(init, @1, @3);
1716 ast_stack.back()->children.push_back(init);
1719 AstNode *assign = new AstNode(AST_ASSIGN, wire, $3);
1720 SET_AST_NODE_LOC(assign, @1, @3);
1721 ast_stack.back()->children.push_back(assign);
1727 TOK_ID range_or_multirange {
1728 if (astbuf1 == nullptr)
1729 frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node.");
1730 AstNode *node = astbuf1->clone();
1732 append_attr_clone(node, albuf);
1733 if (astbuf2 != NULL)
1734 node->children.push_back(astbuf2->clone());
1736 if (node->is_input || node->is_output)
1737 frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
1738 if (!astbuf2 && !node->is_custom_type) {
1739 addRange(node, 0, 0, false);
1741 rewriteAsMemoryNode(node, $2);
1743 if (current_function_or_task == NULL) {
1744 if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
1745 port_stubs[*$1] = ++port_counter;
1747 if (port_stubs.count(*$1) != 0) {
1748 if (!node->is_input && !node->is_output)
1749 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
1750 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
1751 frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
1752 node->port_id = port_stubs[*$1];
1753 port_stubs.erase(*$1);
1755 if (node->is_input || node->is_output)
1756 frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
1759 if (node->is_input || node->is_output)
1760 node->port_id = current_function_or_task_port_id++;
1762 //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
1763 SET_AST_NODE_LOC(node, @1, @1);
1764 ast_stack.back()->children.push_back(node);
1770 TOK_ASSIGN delay assign_expr_list ';';
1773 assign_expr | assign_expr_list ',' assign_expr;
1777 AstNode *node = new AstNode(AST_ASSIGN, $1, $3);
1778 SET_AST_NODE_LOC(node, @$, @$);
1779 ast_stack.back()->children.push_back(node);
1782 type_name: TOK_ID // first time seen
1783 | TOK_USER_TYPE { if (isInLocalScope($1)) frontend_verilog_yyerror("Duplicate declaration of TYPEDEF '%s'", $1->c_str()+1); }
1787 TOK_TYPEDEF wire_type range type_name range_or_multirange ';' {
1789 astbuf2 = checkRange(astbuf1, $3);
1791 astbuf1->children.push_back(astbuf2);
1795 addRange(astbuf1, 0, 0, false);
1797 rewriteAsMemoryNode(astbuf1, $5);
1799 addTypedefNode($4, astbuf1); }
1800 | TOK_TYPEDEF non_wire_data_type type_name ';' { addTypedefNode($3, $2); }
1810 astbuf1 = new AstNode(AST_CELL);
1811 append_attr(astbuf1, $1);
1812 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
1813 astbuf1->children[0]->str = *$2;
1815 } cell_parameter_list_opt cell_list ';' {
1818 attr tok_prim_wrapper delay {
1819 astbuf1 = new AstNode(AST_PRIMITIVE);
1821 append_attr(astbuf1, $1);
1832 $$ = new std::string("or");
1837 cell_list ',' single_cell;
1841 astbuf2 = astbuf1->clone();
1842 if (astbuf2->type != AST_PRIMITIVE)
1845 ast_stack.back()->children.push_back(astbuf2);
1846 } '(' cell_port_list ')' {
1847 SET_AST_NODE_LOC(astbuf2, @1, @$);
1849 TOK_ID non_opt_range {
1850 astbuf2 = astbuf1->clone();
1851 if (astbuf2->type != AST_PRIMITIVE)
1854 ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
1855 } '(' cell_port_list ')'{
1856 SET_AST_NODE_LOC(astbuf2, @1, @$);
1861 prim_list ',' single_prim;
1866 astbuf2 = astbuf1->clone();
1867 ast_stack.back()->children.push_back(astbuf2);
1868 } '(' cell_port_list ')' {
1869 SET_AST_NODE_LOC(astbuf2, @1, @$);
1872 cell_parameter_list_opt:
1873 '#' '(' cell_parameter_list ')' | %empty;
1875 cell_parameter_list:
1876 cell_parameter | cell_parameter_list ',' cell_parameter;
1881 AstNode *node = new AstNode(AST_PARASET);
1882 astbuf1->children.push_back(node);
1883 node->children.push_back($1);
1885 '.' TOK_ID '(' expr ')' {
1886 AstNode *node = new AstNode(AST_PARASET);
1888 astbuf1->children.push_back(node);
1889 node->children.push_back($4);
1894 cell_port_list_rules {
1895 // remove empty args from end of list
1896 while (!astbuf2->children.empty()) {
1897 AstNode *node = astbuf2->children.back();
1898 if (node->type != AST_ARGUMENT) break;
1899 if (!node->children.empty()) break;
1900 if (!node->str.empty()) break;
1901 astbuf2->children.pop_back();
1906 bool has_positional_args = false;
1907 bool has_named_args = false;
1908 for (auto node : astbuf2->children) {
1909 if (node->type != AST_ARGUMENT) continue;
1910 if (node->str.empty())
1911 has_positional_args = true;
1913 has_named_args = true;
1916 if (has_positional_args && has_named_args)
1917 frontend_verilog_yyerror("Mix of positional and named cell ports.");
1920 cell_port_list_rules:
1921 cell_port | cell_port_list_rules ',' cell_port;
1925 AstNode *node = new AstNode(AST_ARGUMENT);
1926 astbuf2->children.push_back(node);
1930 AstNode *node = new AstNode(AST_ARGUMENT);
1931 astbuf2->children.push_back(node);
1932 node->children.push_back($2);
1935 attr '.' TOK_ID '(' expr ')' {
1936 AstNode *node = new AstNode(AST_ARGUMENT);
1938 astbuf2->children.push_back(node);
1939 node->children.push_back($5);
1943 attr '.' TOK_ID '(' ')' {
1944 AstNode *node = new AstNode(AST_ARGUMENT);
1946 astbuf2->children.push_back(node);
1951 AstNode *node = new AstNode(AST_ARGUMENT);
1953 astbuf2->children.push_back(node);
1954 node->children.push_back(new AstNode(AST_IDENTIFIER));
1955 node->children.back()->str = *$3;
1959 attr TOK_WILDCARD_CONNECT {
1961 frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
1962 astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
1965 always_comb_or_latch:
1973 always_or_always_ff:
1982 attr always_or_always_ff {
1983 AstNode *node = new AstNode(AST_ALWAYS);
1984 append_attr(node, $1);
1986 node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
1987 ast_stack.back()->children.push_back(node);
1988 ast_stack.push_back(node);
1990 AstNode *block = new AstNode(AST_BLOCK);
1991 ast_stack.back()->children.push_back(block);
1992 ast_stack.push_back(block);
1994 SET_AST_NODE_LOC(ast_stack.back(), @6, @6);
1995 ast_stack.pop_back();
1997 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
1998 ast_stack.pop_back();
2000 SET_RULE_LOC(@$, @2, @$);
2002 attr always_comb_or_latch {
2003 AstNode *node = new AstNode(AST_ALWAYS);
2004 append_attr(node, $1);
2006 node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
2008 node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
2009 ast_stack.back()->children.push_back(node);
2010 ast_stack.push_back(node);
2011 AstNode *block = new AstNode(AST_BLOCK);
2012 ast_stack.back()->children.push_back(block);
2013 ast_stack.push_back(block);
2015 ast_stack.pop_back();
2016 ast_stack.pop_back();
2019 AstNode *node = new AstNode(AST_INITIAL);
2020 append_attr(node, $1);
2021 ast_stack.back()->children.push_back(node);
2022 ast_stack.push_back(node);
2023 AstNode *block = new AstNode(AST_BLOCK);
2024 ast_stack.back()->children.push_back(block);
2025 ast_stack.push_back(block);
2027 ast_stack.pop_back();
2028 ast_stack.pop_back();
2032 '@' '(' always_events ')' |
2034 '@' ATTR_BEGIN ')' |
2041 always_events TOK_OR always_event |
2042 always_events ',' always_event;
2046 AstNode *node = new AstNode(AST_POSEDGE);
2047 SET_AST_NODE_LOC(node, @1, @1);
2048 ast_stack.back()->children.push_back(node);
2049 node->children.push_back($2);
2052 AstNode *node = new AstNode(AST_NEGEDGE);
2053 SET_AST_NODE_LOC(node, @1, @1);
2054 ast_stack.back()->children.push_back(node);
2055 node->children.push_back($2);
2058 AstNode *node = new AstNode(AST_EDGE);
2059 ast_stack.back()->children.push_back(node);
2060 node->children.push_back($1);
2091 TOK_MODPORT TOK_ID {
2092 AstNode *modport = new AstNode(AST_MODPORT);
2093 ast_stack.back()->children.push_back(modport);
2094 ast_stack.push_back(modport);
2097 } modport_args_opt {
2098 ast_stack.pop_back();
2099 log_assert(ast_stack.size() == 2);
2103 '(' ')' | '(' modport_args optional_comma ')';
2106 modport_arg | modport_args ',' modport_arg;
2109 modport_type_token modport_member |
2114 AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
2115 ast_stack.back()->children.push_back(modport_member);
2116 modport_member->str = *$1;
2117 modport_member->is_input = current_modport_input;
2118 modport_member->is_output = current_modport_output;
2123 TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
2126 opt_sva_label TOK_ASSERT opt_property '(' expr ')' ';' {
2127 if (noassert_mode) {
2130 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2131 SET_AST_NODE_LOC(node, @1, @6);
2134 ast_stack.back()->children.push_back(node);
2139 opt_sva_label TOK_ASSUME opt_property '(' expr ')' ';' {
2140 if (noassume_mode) {
2143 AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
2144 SET_AST_NODE_LOC(node, @1, @6);
2147 ast_stack.back()->children.push_back(node);
2152 opt_sva_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2153 if (noassert_mode) {
2156 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2157 SET_AST_NODE_LOC(node, @1, @7);
2160 ast_stack.back()->children.push_back(node);
2165 opt_sva_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2166 if (noassume_mode) {
2169 AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
2170 SET_AST_NODE_LOC(node, @1, @7);
2173 ast_stack.back()->children.push_back(node);
2178 opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
2179 AstNode *node = new AstNode(AST_COVER, $5);
2180 SET_AST_NODE_LOC(node, @1, @6);
2181 if ($1 != nullptr) {
2185 ast_stack.back()->children.push_back(node);
2187 opt_sva_label TOK_COVER opt_property '(' ')' ';' {
2188 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2189 SET_AST_NODE_LOC(node, @1, @5);
2190 if ($1 != nullptr) {
2194 ast_stack.back()->children.push_back(node);
2196 opt_sva_label TOK_COVER ';' {
2197 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2198 SET_AST_NODE_LOC(node, @1, @2);
2199 if ($1 != nullptr) {
2203 ast_stack.back()->children.push_back(node);
2205 opt_sva_label TOK_RESTRICT opt_property '(' expr ')' ';' {
2206 if (norestrict_mode) {
2209 AstNode *node = new AstNode(AST_ASSUME, $5);
2210 SET_AST_NODE_LOC(node, @1, @6);
2213 ast_stack.back()->children.push_back(node);
2216 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2220 opt_sva_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2221 if (norestrict_mode) {
2224 AstNode *node = new AstNode(AST_FAIR, $6);
2225 SET_AST_NODE_LOC(node, @1, @7);
2228 ast_stack.back()->children.push_back(node);
2231 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2237 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
2238 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2239 SET_AST_NODE_LOC(node, @1, @6);
2240 ast_stack.back()->children.push_back(node);
2241 if ($1 != nullptr) {
2242 ast_stack.back()->children.back()->str = *$1;
2246 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
2247 AstNode *node = new AstNode(AST_ASSUME, $5);
2248 SET_AST_NODE_LOC(node, @1, @6);
2249 ast_stack.back()->children.push_back(node);
2250 if ($1 != nullptr) {
2251 ast_stack.back()->children.back()->str = *$1;
2255 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2256 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2257 SET_AST_NODE_LOC(node, @1, @7);
2258 ast_stack.back()->children.push_back(node);
2259 if ($1 != nullptr) {
2260 ast_stack.back()->children.back()->str = *$1;
2264 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2265 AstNode *node = new AstNode(AST_FAIR, $6);
2266 SET_AST_NODE_LOC(node, @1, @7);
2267 ast_stack.back()->children.push_back(node);
2268 if ($1 != nullptr) {
2269 ast_stack.back()->children.back()->str = *$1;
2273 opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
2274 AstNode *node = new AstNode(AST_COVER, $5);
2275 SET_AST_NODE_LOC(node, @1, @6);
2276 ast_stack.back()->children.push_back(node);
2277 if ($1 != nullptr) {
2278 ast_stack.back()->children.back()->str = *$1;
2282 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
2283 if (norestrict_mode) {
2286 AstNode *node = new AstNode(AST_ASSUME, $5);
2287 SET_AST_NODE_LOC(node, @1, @6);
2288 ast_stack.back()->children.push_back(node);
2289 if ($1 != nullptr) {
2290 ast_stack.back()->children.back()->str = *$1;
2295 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2296 if (norestrict_mode) {
2299 AstNode *node = new AstNode(AST_FAIR, $6);
2300 SET_AST_NODE_LOC(node, @1, @7);
2301 ast_stack.back()->children.push_back(node);
2302 if ($1 != nullptr) {
2303 ast_stack.back()->children.back()->str = *$1;
2309 simple_behavioral_stmt:
2310 attr lvalue '=' delay expr {
2311 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $5);
2312 ast_stack.back()->children.push_back(node);
2313 SET_AST_NODE_LOC(node, @2, @5);
2314 append_attr(node, $1);
2316 attr lvalue TOK_INCREMENT {
2317 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)));
2318 ast_stack.back()->children.push_back(node);
2319 SET_AST_NODE_LOC(node, @2, @3);
2320 append_attr(node, $1);
2322 attr lvalue TOK_DECREMENT {
2323 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_SUB, $2->clone(), AstNode::mkconst_int(1, true)));
2324 ast_stack.back()->children.push_back(node);
2325 SET_AST_NODE_LOC(node, @2, @3);
2326 append_attr(node, $1);
2328 attr lvalue OP_LE delay expr {
2329 AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5);
2330 ast_stack.back()->children.push_back(node);
2331 SET_AST_NODE_LOC(node, @2, @5);
2332 append_attr(node, $1);
2334 attr lvalue TOK_XOR_ASSIGN delay expr {
2335 AstNode *xor_node = new AstNode(AST_BIT_XOR, $2->clone(), $5);
2336 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, xor_node);
2337 SET_AST_NODE_LOC(xor_node, @2, @5);
2338 SET_AST_NODE_LOC(node, @2, @5);
2339 ast_stack.back()->children.push_back(node);
2340 append_attr(node, $1);
2342 attr lvalue TOK_OR_ASSIGN delay expr {
2343 AstNode *or_node = new AstNode(AST_BIT_OR, $2->clone(), $5);
2344 SET_AST_NODE_LOC(or_node, @2, @5);
2345 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, or_node);
2346 SET_AST_NODE_LOC(node, @2, @5);
2347 ast_stack.back()->children.push_back(node);
2348 append_attr(node, $1);
2350 attr lvalue TOK_PLUS_ASSIGN delay expr {
2351 AstNode *add_node = new AstNode(AST_ADD, $2->clone(), $5);
2352 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, add_node);
2353 SET_AST_NODE_LOC(node, @2, @5);
2354 SET_AST_NODE_LOC(add_node, @2, @5);
2355 ast_stack.back()->children.push_back(node);
2356 append_attr(node, $1);
2358 attr lvalue TOK_SUB_ASSIGN delay expr {
2359 AstNode *sub_node = new AstNode(AST_SUB, $2->clone(), $5);
2360 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, sub_node);
2361 SET_AST_NODE_LOC(node, @2, @5);
2362 SET_AST_NODE_LOC(sub_node, @2, @5);
2363 ast_stack.back()->children.push_back(node);
2364 append_attr(node, $1);
2366 attr lvalue TOK_AND_ASSIGN delay expr {
2367 AstNode *and_node = new AstNode(AST_BIT_AND, $2->clone(), $5);
2368 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, and_node);
2369 SET_AST_NODE_LOC(node, @2, @5);
2370 SET_AST_NODE_LOC(and_node, @2, @5);
2371 ast_stack.back()->children.push_back(node);
2372 append_attr(node, $1);
2375 // this production creates the obligatory if-else shift/reduce conflict
2377 defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
2378 non_opt_delay behavioral_stmt |
2379 simple_behavioral_stmt ';' |
2383 attr hierarchical_id {
2384 AstNode *node = new AstNode(AST_TCALL);
2387 ast_stack.back()->children.push_back(node);
2388 ast_stack.push_back(node);
2389 append_attr(node, $1);
2391 ast_stack.pop_back();
2393 attr TOK_MSG_TASKS {
2394 AstNode *node = new AstNode(AST_TCALL);
2397 ast_stack.back()->children.push_back(node);
2398 ast_stack.push_back(node);
2399 append_attr(node, $1);
2401 ast_stack.pop_back();
2406 AstNode *node = new AstNode(AST_BLOCK);
2407 ast_stack.back()->children.push_back(node);
2408 ast_stack.push_back(node);
2409 append_attr(node, $1);
2412 } behavioral_stmt_list TOK_END opt_label {
2414 if ($4 != NULL && $8 != NULL && *$4 != *$8)
2415 frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
2416 SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
2419 ast_stack.pop_back();
2422 AstNode *node = new AstNode(AST_FOR);
2423 ast_stack.back()->children.push_back(node);
2424 ast_stack.push_back(node);
2425 append_attr(node, $1);
2426 } simple_behavioral_stmt ';' expr {
2427 ast_stack.back()->children.push_back($7);
2428 } ';' simple_behavioral_stmt ')' {
2429 AstNode *block = new AstNode(AST_BLOCK);
2430 ast_stack.back()->children.push_back(block);
2431 ast_stack.push_back(block);
2433 SET_AST_NODE_LOC(ast_stack.back(), @13, @13);
2434 ast_stack.pop_back();
2435 SET_AST_NODE_LOC(ast_stack.back(), @2, @13);
2436 ast_stack.pop_back();
2438 attr TOK_WHILE '(' expr ')' {
2439 AstNode *node = new AstNode(AST_WHILE);
2440 ast_stack.back()->children.push_back(node);
2441 ast_stack.push_back(node);
2442 append_attr(node, $1);
2443 AstNode *block = new AstNode(AST_BLOCK);
2444 ast_stack.back()->children.push_back($4);
2445 ast_stack.back()->children.push_back(block);
2446 ast_stack.push_back(block);
2448 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2449 ast_stack.pop_back();
2450 ast_stack.pop_back();
2452 attr TOK_REPEAT '(' expr ')' {
2453 AstNode *node = new AstNode(AST_REPEAT);
2454 ast_stack.back()->children.push_back(node);
2455 ast_stack.push_back(node);
2456 append_attr(node, $1);
2457 AstNode *block = new AstNode(AST_BLOCK);
2458 ast_stack.back()->children.push_back($4);
2459 ast_stack.back()->children.push_back(block);
2460 ast_stack.push_back(block);
2462 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2463 ast_stack.pop_back();
2464 ast_stack.pop_back();
2466 attr TOK_IF '(' expr ')' {
2467 AstNode *node = new AstNode(AST_CASE);
2468 AstNode *block = new AstNode(AST_BLOCK);
2469 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
2470 SET_AST_NODE_LOC(cond, @4, @4);
2471 ast_stack.back()->children.push_back(node);
2472 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
2473 node->children.push_back(cond);
2474 ast_stack.push_back(node);
2475 ast_stack.push_back(block);
2476 append_attr(node, $1);
2478 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2480 ast_stack.pop_back();
2481 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2482 ast_stack.pop_back();
2484 case_attr case_type '(' expr ')' {
2485 AstNode *node = new AstNode(AST_CASE, $4);
2486 ast_stack.back()->children.push_back(node);
2487 ast_stack.push_back(node);
2488 append_attr(node, $1);
2489 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2490 } opt_synopsys_attr case_body TOK_ENDCASE {
2491 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2492 case_type_stack.pop_back();
2493 ast_stack.pop_back();
2500 TOK_PRIORITY case_attr {
2503 TOK_UNIQUE case_attr {
2508 attr unique_case_attr {
2509 if ($2) (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false);
2515 case_type_stack.push_back(0);
2518 case_type_stack.push_back('x');
2521 case_type_stack.push_back('z');
2525 opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
2526 if (ast_stack.back()->attributes.count(ID::full_case) == 0)
2527 ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
2529 opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
2530 if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
2531 ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
2535 behavioral_stmt_list:
2536 behavioral_stmt_list behavioral_stmt |
2541 AstNode *block = new AstNode(AST_BLOCK);
2542 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
2543 SET_AST_NODE_LOC(cond, @1, @1);
2545 ast_stack.pop_back();
2546 ast_stack.back()->children.push_back(cond);
2547 ast_stack.push_back(block);
2549 SET_AST_NODE_LOC(ast_stack.back(), @3, @3);
2551 %empty %prec FAKE_THEN;
2554 case_body case_item |
2559 AstNode *node = new AstNode(
2560 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2561 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2562 ast_stack.back()->children.push_back(node);
2563 ast_stack.push_back(node);
2565 AstNode *block = new AstNode(AST_BLOCK);
2566 ast_stack.back()->children.push_back(block);
2567 ast_stack.push_back(block);
2568 case_type_stack.push_back(0);
2570 case_type_stack.pop_back();
2571 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2572 ast_stack.pop_back();
2573 ast_stack.pop_back();
2577 gen_case_body gen_case_item |
2582 AstNode *node = new AstNode(
2583 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2584 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2585 ast_stack.back()->children.push_back(node);
2586 ast_stack.push_back(node);
2588 case_type_stack.push_back(0);
2589 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2591 case_type_stack.pop_back();
2592 ast_stack.pop_back();
2596 case_expr_list ':' |
2601 AstNode *node = new AstNode(AST_DEFAULT);
2602 SET_AST_NODE_LOC(node, @1, @1);
2603 ast_stack.back()->children.push_back(node);
2606 AstNode *node = new AstNode(AST_IDENTIFIER);
2607 SET_AST_NODE_LOC(node, @1, @1);
2608 ast_stack.back()->children.push_back(node);
2609 ast_stack.back()->children.back()->str = *$1;
2613 ast_stack.back()->children.push_back($1);
2615 case_expr_list ',' expr {
2616 ast_stack.back()->children.push_back($3);
2620 hierarchical_id '[' expr ']' '.' rvalue {
2621 $$ = new AstNode(AST_PREFIX, $3, $6);
2625 hierarchical_id range {
2626 $$ = new AstNode(AST_IDENTIFIER, $2);
2628 SET_AST_NODE_LOC($$, @1, @1);
2630 if ($2 == nullptr && ($$->str == "\\$initstate" ||
2631 $$->str == "\\$anyconst" || $$->str == "\\$anyseq" ||
2632 $$->str == "\\$allconst" || $$->str == "\\$allseq"))
2633 $$->type = AST_FCALL;
2635 hierarchical_id non_opt_multirange {
2636 $$ = new AstNode(AST_IDENTIFIER, $2);
2638 SET_AST_NODE_LOC($$, @1, @1);
2646 '{' lvalue_concat_list '}' {
2652 $$ = new AstNode(AST_CONCAT);
2653 $$->children.push_back($1);
2655 expr ',' lvalue_concat_list {
2657 $$->children.push_back($1);
2661 '(' arg_list optional_comma ')' |
2670 arg_list ',' single_arg;
2674 ast_stack.back()->children.push_back($1);
2678 module_gen_body gen_stmt_or_module_body_stmt |
2681 gen_stmt_or_module_body_stmt:
2682 gen_stmt | module_body_stmt |
2687 // this production creates the obligatory if-else shift/reduce conflict
2690 AstNode *node = new AstNode(AST_GENFOR);
2691 ast_stack.back()->children.push_back(node);
2692 ast_stack.push_back(node);
2693 } simple_behavioral_stmt ';' expr {
2694 ast_stack.back()->children.push_back($6);
2695 } ';' simple_behavioral_stmt ')' gen_stmt_block {
2696 SET_AST_NODE_LOC(ast_stack.back(), @1, @11);
2697 ast_stack.pop_back();
2699 TOK_IF '(' expr ')' {
2700 AstNode *node = new AstNode(AST_GENIF);
2701 ast_stack.back()->children.push_back(node);
2702 ast_stack.push_back(node);
2703 ast_stack.back()->children.push_back($3);
2704 AstNode *block = new AstNode(AST_GENBLOCK);
2705 ast_stack.back()->children.push_back(block);
2706 ast_stack.push_back(block);
2708 ast_stack.pop_back();
2710 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2711 ast_stack.pop_back();
2713 case_type '(' expr ')' {
2714 AstNode *node = new AstNode(AST_GENCASE, $3);
2715 ast_stack.back()->children.push_back(node);
2716 ast_stack.push_back(node);
2717 } gen_case_body TOK_ENDCASE {
2718 case_type_stack.pop_back();
2719 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2720 ast_stack.pop_back();
2725 AstNode *node = new AstNode(AST_GENBLOCK);
2726 node->str = $3 ? *$3 : std::string();
2727 ast_stack.back()->children.push_back(node);
2728 ast_stack.push_back(node);
2729 } module_gen_body TOK_END opt_label {
2733 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2734 ast_stack.pop_back();
2737 AstNode *node = new AstNode(AST_TECALL);
2740 ast_stack.back()->children.push_back(node);
2741 ast_stack.push_back(node);
2743 SET_AST_NODE_LOC(ast_stack.back(), @1, @3);
2744 ast_stack.pop_back();
2749 AstNode *node = new AstNode(AST_GENBLOCK);
2750 ast_stack.back()->children.push_back(node);
2751 ast_stack.push_back(node);
2752 } gen_stmt_or_module_body_stmt {
2753 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2754 ast_stack.pop_back();
2758 TOK_ELSE gen_stmt_block | %empty %prec FAKE_THEN;
2764 basic_expr '?' attr expr ':' expr {
2765 $$ = new AstNode(AST_TERNARY);
2766 $$->children.push_back($1);
2767 $$->children.push_back($4);
2768 $$->children.push_back($6);
2769 SET_AST_NODE_LOC($$, @1, @$);
2770 append_attr($$, $3);
2777 '(' expr ')' integral_number {
2778 if ($4->compare(0, 1, "'") != 0)
2779 frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
2781 AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2783 log_error("Value conversion failed: `%s'\n", $4->c_str());
2784 $$ = new AstNode(AST_TO_BITS, bits, val);
2787 hierarchical_id integral_number {
2788 if ($2->compare(0, 1, "'") != 0)
2789 frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
2790 AstNode *bits = new AstNode(AST_IDENTIFIER);
2792 SET_AST_NODE_LOC(bits, @1, @1);
2793 AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2794 SET_AST_NODE_LOC(val, @2, @2);
2796 log_error("Value conversion failed: `%s'\n", $2->c_str());
2797 $$ = new AstNode(AST_TO_BITS, bits, val);
2802 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2803 SET_AST_NODE_LOC($$, @1, @1);
2805 log_error("Value conversion failed: `%s'\n", $1->c_str());
2809 $$ = new AstNode(AST_REALVALUE);
2810 char *p = (char*)malloc(GetSize(*$1) + 1), *q;
2811 for (int i = 0, j = 0; j < GetSize(*$1); j++)
2812 if ((*$1)[j] != '_')
2813 p[i++] = (*$1)[j], p[i] = 0;
2814 $$->realvalue = strtod(p, &q);
2815 SET_AST_NODE_LOC($$, @1, @1);
2816 log_assert(*q == 0);
2821 $$ = AstNode::mkconst_str(*$1);
2822 SET_AST_NODE_LOC($$, @1, @1);
2825 hierarchical_id attr {
2826 AstNode *node = new AstNode(AST_FCALL);
2829 ast_stack.push_back(node);
2830 SET_AST_NODE_LOC(node, @1, @1);
2831 append_attr(node, $2);
2832 } '(' arg_list optional_comma ')' {
2833 $$ = ast_stack.back();
2834 ast_stack.pop_back();
2836 TOK_TO_SIGNED attr '(' expr ')' {
2837 $$ = new AstNode(AST_TO_SIGNED, $4);
2838 append_attr($$, $2);
2840 TOK_TO_UNSIGNED attr '(' expr ')' {
2841 $$ = new AstNode(AST_TO_UNSIGNED, $4);
2842 append_attr($$, $2);
2847 '(' expr ':' expr ':' expr ')' {
2852 '{' concat_list '}' {
2855 '{' expr '{' concat_list '}' '}' {
2856 $$ = new AstNode(AST_REPLICATE, $2, $4);
2858 '~' attr basic_expr %prec UNARY_OPS {
2859 $$ = new AstNode(AST_BIT_NOT, $3);
2860 SET_AST_NODE_LOC($$, @1, @3);
2861 append_attr($$, $2);
2863 basic_expr '&' attr basic_expr {
2864 $$ = new AstNode(AST_BIT_AND, $1, $4);
2865 SET_AST_NODE_LOC($$, @1, @4);
2866 append_attr($$, $3);
2868 basic_expr OP_NAND attr basic_expr {
2869 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
2870 SET_AST_NODE_LOC($$, @1, @4);
2871 append_attr($$, $3);
2873 basic_expr '|' attr basic_expr {
2874 $$ = new AstNode(AST_BIT_OR, $1, $4);
2875 SET_AST_NODE_LOC($$, @1, @4);
2876 append_attr($$, $3);
2878 basic_expr OP_NOR attr basic_expr {
2879 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
2880 SET_AST_NODE_LOC($$, @1, @4);
2881 append_attr($$, $3);
2883 basic_expr '^' attr basic_expr {
2884 $$ = new AstNode(AST_BIT_XOR, $1, $4);
2885 SET_AST_NODE_LOC($$, @1, @4);
2886 append_attr($$, $3);
2888 basic_expr OP_XNOR attr basic_expr {
2889 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
2890 SET_AST_NODE_LOC($$, @1, @4);
2891 append_attr($$, $3);
2893 '&' attr basic_expr %prec UNARY_OPS {
2894 $$ = new AstNode(AST_REDUCE_AND, $3);
2895 SET_AST_NODE_LOC($$, @1, @3);
2896 append_attr($$, $2);
2898 OP_NAND attr basic_expr %prec UNARY_OPS {
2899 $$ = new AstNode(AST_REDUCE_AND, $3);
2900 SET_AST_NODE_LOC($$, @1, @3);
2901 append_attr($$, $2);
2902 $$ = new AstNode(AST_LOGIC_NOT, $$);
2904 '|' attr basic_expr %prec UNARY_OPS {
2905 $$ = new AstNode(AST_REDUCE_OR, $3);
2906 SET_AST_NODE_LOC($$, @1, @3);
2907 append_attr($$, $2);
2909 OP_NOR attr basic_expr %prec UNARY_OPS {
2910 $$ = new AstNode(AST_REDUCE_OR, $3);
2911 SET_AST_NODE_LOC($$, @1, @3);
2912 append_attr($$, $2);
2913 $$ = new AstNode(AST_LOGIC_NOT, $$);
2914 SET_AST_NODE_LOC($$, @1, @3);
2916 '^' attr basic_expr %prec UNARY_OPS {
2917 $$ = new AstNode(AST_REDUCE_XOR, $3);
2918 SET_AST_NODE_LOC($$, @1, @3);
2919 append_attr($$, $2);
2921 OP_XNOR attr basic_expr %prec UNARY_OPS {
2922 $$ = new AstNode(AST_REDUCE_XNOR, $3);
2923 SET_AST_NODE_LOC($$, @1, @3);
2924 append_attr($$, $2);
2926 basic_expr OP_SHL attr basic_expr {
2927 $$ = new AstNode(AST_SHIFT_LEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2928 SET_AST_NODE_LOC($$, @1, @4);
2929 append_attr($$, $3);
2931 basic_expr OP_SHR attr basic_expr {
2932 $$ = new AstNode(AST_SHIFT_RIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2933 SET_AST_NODE_LOC($$, @1, @4);
2934 append_attr($$, $3);
2936 basic_expr OP_SSHL attr basic_expr {
2937 $$ = new AstNode(AST_SHIFT_SLEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2938 SET_AST_NODE_LOC($$, @1, @4);
2939 append_attr($$, $3);
2941 basic_expr OP_SSHR attr basic_expr {
2942 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2943 SET_AST_NODE_LOC($$, @1, @4);
2944 append_attr($$, $3);
2946 basic_expr '<' attr basic_expr {
2947 $$ = new AstNode(AST_LT, $1, $4);
2948 SET_AST_NODE_LOC($$, @1, @4);
2949 append_attr($$, $3);
2951 basic_expr OP_LE attr basic_expr {
2952 $$ = new AstNode(AST_LE, $1, $4);
2953 SET_AST_NODE_LOC($$, @1, @4);
2954 append_attr($$, $3);
2956 basic_expr OP_EQ attr basic_expr {
2957 $$ = new AstNode(AST_EQ, $1, $4);
2958 SET_AST_NODE_LOC($$, @1, @4);
2959 append_attr($$, $3);
2961 basic_expr OP_NE attr basic_expr {
2962 $$ = new AstNode(AST_NE, $1, $4);
2963 SET_AST_NODE_LOC($$, @1, @4);
2964 append_attr($$, $3);
2966 basic_expr OP_EQX attr basic_expr {
2967 $$ = new AstNode(AST_EQX, $1, $4);
2968 SET_AST_NODE_LOC($$, @1, @4);
2969 append_attr($$, $3);
2971 basic_expr OP_NEX attr basic_expr {
2972 $$ = new AstNode(AST_NEX, $1, $4);
2973 SET_AST_NODE_LOC($$, @1, @4);
2974 append_attr($$, $3);
2976 basic_expr OP_GE attr basic_expr {
2977 $$ = new AstNode(AST_GE, $1, $4);
2978 SET_AST_NODE_LOC($$, @1, @4);
2979 append_attr($$, $3);
2981 basic_expr '>' attr basic_expr {
2982 $$ = new AstNode(AST_GT, $1, $4);
2983 SET_AST_NODE_LOC($$, @1, @4);
2984 append_attr($$, $3);
2986 basic_expr '+' attr basic_expr {
2987 $$ = new AstNode(AST_ADD, $1, $4);
2988 SET_AST_NODE_LOC($$, @1, @4);
2989 append_attr($$, $3);
2991 basic_expr '-' attr basic_expr {
2992 $$ = new AstNode(AST_SUB, $1, $4);
2993 SET_AST_NODE_LOC($$, @1, @4);
2994 append_attr($$, $3);
2996 basic_expr '*' attr basic_expr {
2997 $$ = new AstNode(AST_MUL, $1, $4);
2998 SET_AST_NODE_LOC($$, @1, @4);
2999 append_attr($$, $3);
3001 basic_expr '/' attr basic_expr {
3002 $$ = new AstNode(AST_DIV, $1, $4);
3003 SET_AST_NODE_LOC($$, @1, @4);
3004 append_attr($$, $3);
3006 basic_expr '%' attr basic_expr {
3007 $$ = new AstNode(AST_MOD, $1, $4);
3008 SET_AST_NODE_LOC($$, @1, @4);
3009 append_attr($$, $3);
3011 basic_expr OP_POW attr basic_expr {
3012 $$ = new AstNode(AST_POW, $1, $4);
3013 SET_AST_NODE_LOC($$, @1, @4);
3014 append_attr($$, $3);
3016 '+' attr basic_expr %prec UNARY_OPS {
3017 $$ = new AstNode(AST_POS, $3);
3018 SET_AST_NODE_LOC($$, @1, @3);
3019 append_attr($$, $2);
3021 '-' attr basic_expr %prec UNARY_OPS {
3022 $$ = new AstNode(AST_NEG, $3);
3023 SET_AST_NODE_LOC($$, @1, @3);
3024 append_attr($$, $2);
3026 basic_expr OP_LAND attr basic_expr {
3027 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
3028 SET_AST_NODE_LOC($$, @1, @4);
3029 append_attr($$, $3);
3031 basic_expr OP_LOR attr basic_expr {
3032 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
3033 SET_AST_NODE_LOC($$, @1, @4);
3034 append_attr($$, $3);
3036 '!' attr basic_expr %prec UNARY_OPS {
3037 $$ = new AstNode(AST_LOGIC_NOT, $3);
3038 SET_AST_NODE_LOC($$, @1, @3);
3039 append_attr($$, $2);
3041 TOK_SIGNED OP_CAST '(' expr ')' {
3043 frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
3044 $$ = new AstNode(AST_TO_SIGNED, $4);
3045 SET_AST_NODE_LOC($$, @1, @4);
3047 TOK_UNSIGNED OP_CAST '(' expr ')' {
3049 frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
3050 $$ = new AstNode(AST_TO_UNSIGNED, $4);
3051 SET_AST_NODE_LOC($$, @1, @4);
3053 basic_expr OP_CAST '(' expr ')' {
3055 frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
3056 $$ = new AstNode(AST_CAST_SIZE, $1, $4);
3057 SET_AST_NODE_LOC($$, @1, @4);
3062 $$ = new AstNode(AST_CONCAT, $1);
3064 expr ',' concat_list {
3066 $$->children.push_back($1);
3070 TOK_CONSTVAL { $$ = $1; } |
3071 TOK_UNBASED_UNSIZED_CONSTVAL { $$ = $1; } |
3072 TOK_BASE TOK_BASED_CONSTVAL {
3077 TOK_CONSTVAL TOK_BASE TOK_BASED_CONSTVAL {
3078 $1->append(*$2).append(*$3);