2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The Verilog frontend.
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
29 * This is the actual bison parser for Verilog code. The AST ist created directly
30 * from the bison reduce functions here. Note that this code uses a few global
31 * variables to hold the state of the AST generator and therefore this parser is
40 #include "frontends/verilog/verilog_frontend.h"
41 #include "kernel/log.h"
45 using namespace VERILOG_FRONTEND;
48 namespace VERILOG_FRONTEND {
50 std::map<std::string, int> port_stubs;
51 std::map<std::string, AstNode*> *attr_list, default_attr_list;
52 std::stack<std::map<std::string, AstNode*> *> attr_list_stack;
53 std::map<std::string, AstNode*> *albuf;
54 std::vector<AstNode*> ast_stack;
55 struct AstNode *astbuf1, *astbuf2, *astbuf3;
56 struct AstNode *current_function_or_task;
57 struct AstNode *current_ast, *current_ast_mod;
58 int current_function_or_task_port_id;
59 std::vector<char> case_type_stack;
60 bool do_not_require_port_stubs;
61 bool default_nettype_wire;
62 bool sv_mode, formal_mode, lib_mode, specify_mode;
63 bool noassert_mode, noassume_mode, norestrict_mode;
64 bool assume_asserts_mode, assert_assumes_mode;
65 bool current_wire_rand, current_wire_const;
66 bool current_modport_input, current_modport_output;
71 static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
73 for (auto &it : *al) {
74 if (ast->attributes.count(it.first) > 0)
75 delete ast->attributes[it.first];
76 ast->attributes[it.first] = it.second;
81 static void append_attr_clone(AstNode *ast, std::map<std::string, AstNode*> *al)
83 for (auto &it : *al) {
84 if (ast->attributes.count(it.first) > 0)
85 delete ast->attributes[it.first];
86 ast->attributes[it.first] = it.second->clone();
90 static void free_attr(std::map<std::string, AstNode*> *al)
97 struct specify_target {
102 struct specify_triple {
103 AstNode *t_min, *t_avg, *t_max;
106 struct specify_rise_fall {
113 %define api.prefix {frontend_verilog_yy}
115 /* The union is defined in the header, so we need to provide all the
116 * includes it requires
121 #include "frontends/verilog/verilog_frontend.h"
126 struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
127 std::map<std::string, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
128 struct specify_target *specify_target_ptr;
129 struct specify_triple *specify_triple_ptr;
130 struct specify_rise_fall *specify_rise_fall_ptr;
135 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
136 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
137 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
138 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
139 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
140 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
141 %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR
142 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
143 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
144 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
145 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
146 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
147 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
148 %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND
149 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
150 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
151 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
152 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
153 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
154 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
156 %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
157 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
158 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id
159 %type <boolean> opt_signed opt_property unique_case_attr
160 %type <al> attr case_attr
162 %type <specify_target_ptr> specify_target
163 %type <specify_triple_ptr> specify_triple
164 %type <specify_rise_fall_ptr> specify_rise_fall
165 %type <ast> specify_if specify_condition specify_opt_arg
166 %type <ch> specify_edge
168 // operator precedence from low to high
174 %left OP_EQ OP_NE OP_EQX OP_NEX
175 %left '<' OP_LE OP_GE '>'
176 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
182 %define parse.error verbose
183 %define parse.lac full
194 ast_stack.push_back(current_ast);
196 ast_stack.pop_back();
197 log_assert(GetSize(ast_stack) == 0);
198 for (auto &it : default_attr_list)
200 default_attr_list.clear();
206 task_func_decl design |
208 localparam_decl design |
215 if (attr_list != nullptr)
216 attr_list_stack.push(attr_list);
217 attr_list = new std::map<std::string, AstNode*>;
218 for (auto &it : default_attr_list)
219 (*attr_list)[it.first] = it.second->clone();
222 if (!attr_list_stack.empty()) {
223 attr_list = attr_list_stack.top();
224 attr_list_stack.pop();
230 attr_opt ATTR_BEGIN opt_attr_list ATTR_END |
235 if (attr_list != nullptr)
236 attr_list_stack.push(attr_list);
237 attr_list = new std::map<std::string, AstNode*>;
238 for (auto &it : default_attr_list)
240 default_attr_list.clear();
242 attr_list->swap(default_attr_list);
244 if (!attr_list_stack.empty()) {
245 attr_list = attr_list_stack.top();
246 attr_list_stack.pop();
252 attr_list | /* empty */;
256 attr_list ',' attr_assign;
260 if (attr_list->count(*$1) != 0)
261 delete (*attr_list)[*$1];
262 (*attr_list)[*$1] = AstNode::mkconst_int(1, false);
265 hierarchical_id '=' expr {
266 if (attr_list->count(*$1) != 0)
267 delete (*attr_list)[*$1];
268 (*attr_list)[*$1] = $3;
276 hierarchical_id TOK_PACKAGESEP TOK_ID {
277 if ($3->substr(0, 1) == "\\")
278 *$1 += "::" + $3->substr(1);
284 hierarchical_id '.' TOK_ID {
285 if ($3->substr(0, 1) == "\\")
286 *$1 += "." + $3->substr(1);
294 attr TOK_MODULE TOK_ID {
295 do_not_require_port_stubs = false;
296 AstNode *mod = new AstNode(AST_MODULE);
297 ast_stack.back()->children.push_back(mod);
298 ast_stack.push_back(mod);
299 current_ast_mod = mod;
303 append_attr(mod, $1);
305 } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
306 if (port_stubs.size() != 0)
307 frontend_verilog_yyerror("Missing details for module port `%s'.",
308 port_stubs.begin()->first.c_str());
309 ast_stack.pop_back();
310 log_assert(ast_stack.size() == 1);
311 current_ast_mod = NULL;
315 '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
318 single_module_para | module_para_list ',' single_module_para;
323 if (astbuf1) delete astbuf1;
324 astbuf1 = new AstNode(AST_PARAMETER);
325 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
326 append_attr(astbuf1, $1);
327 } param_signed param_integer param_range single_param_decl |
328 attr TOK_LOCALPARAM {
329 if (astbuf1) delete astbuf1;
330 astbuf1 = new AstNode(AST_LOCALPARAM);
331 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
332 append_attr(astbuf1, $1);
333 } param_signed param_integer param_range single_param_decl |
337 '(' ')' | /* empty */ | '(' module_args optional_comma ')';
340 module_arg | module_args ',' module_arg;
345 module_arg_opt_assignment:
347 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
348 AstNode *wire = new AstNode(AST_IDENTIFIER);
349 wire->str = ast_stack.back()->children.back()->str;
350 if (ast_stack.back()->children.back()->is_input) {
351 AstNode *n = ast_stack.back()->children.back();
352 if (n->attributes.count("\\defaultvalue"))
353 delete n->attributes.at("\\defaultvalue");
354 n->attributes["\\defaultvalue"] = $2;
356 if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
357 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
359 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
361 frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
367 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
368 AstNode *node = ast_stack.back()->children.back()->clone();
370 node->port_id = ++port_counter;
371 ast_stack.back()->children.push_back(node);
373 if (port_stubs.count(*$1) != 0)
374 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
375 port_stubs[*$1] = ++port_counter;
378 } module_arg_opt_assignment |
380 astbuf1 = new AstNode(AST_INTERFACEPORT);
381 astbuf1->children.push_back(new AstNode(AST_INTERFACEPORTTYPE));
382 astbuf1->children[0]->str = *$1;
384 } TOK_ID { /* SV interfaces */
386 frontend_verilog_yyerror("Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
387 astbuf2 = astbuf1->clone(); // really only needed if multiple instances of same type.
390 astbuf2->port_id = ++port_counter;
391 ast_stack.back()->children.push_back(astbuf2);
392 delete astbuf1; // really only needed if multiple instances of same type.
393 } module_arg_opt_assignment |
394 attr wire_type range TOK_ID {
397 node->port_id = ++port_counter;
399 node->children.push_back($3);
400 if (!node->is_input && !node->is_output)
401 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
402 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
403 frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
404 ast_stack.back()->children.push_back(node);
405 append_attr(node, $1);
407 } module_arg_opt_assignment |
409 do_not_require_port_stubs = true;
413 attr TOK_PACKAGE TOK_ID {
414 AstNode *mod = new AstNode(AST_PACKAGE);
415 ast_stack.back()->children.push_back(mod);
416 ast_stack.push_back(mod);
417 current_ast_mod = mod;
419 append_attr(mod, $1);
420 } ';' package_body TOK_ENDPACKAGE {
421 ast_stack.pop_back();
422 current_ast_mod = NULL;
426 package_body package_body_stmt |;
432 TOK_INTERFACE TOK_ID {
433 do_not_require_port_stubs = false;
434 AstNode *intf = new AstNode(AST_INTERFACE);
435 ast_stack.back()->children.push_back(intf);
436 ast_stack.push_back(intf);
437 current_ast_mod = intf;
442 } module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
443 if (port_stubs.size() != 0)
444 frontend_verilog_yyerror("Missing details for module port `%s'.",
445 port_stubs.begin()->first.c_str());
446 ast_stack.pop_back();
447 log_assert(ast_stack.size() == 1);
448 current_ast_mod = NULL;
452 interface_body interface_body_stmt |;
455 param_decl | localparam_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
459 '#' TOK_ID { delete $2; } |
460 '#' TOK_CONSTVAL { delete $2; } |
461 '#' TOK_REALVAL { delete $2; } |
462 '#' '(' expr ')' { delete $3; } |
463 '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
466 non_opt_delay | /* empty */;
470 astbuf3 = new AstNode(AST_WIRE);
471 current_wire_rand = false;
472 current_wire_const = false;
473 } wire_type_token_list delay {
477 wire_type_token_list:
478 wire_type_token | wire_type_token_list wire_type_token |
483 astbuf3->is_input = true;
486 astbuf3->is_output = true;
489 astbuf3->is_input = true;
490 astbuf3->is_output = true;
497 astbuf3->is_wor = true;
500 astbuf3->is_wand = true;
503 astbuf3->is_reg = true;
506 astbuf3->is_logic = true;
509 astbuf3->is_logic = true;
512 astbuf3->is_reg = true;
513 astbuf3->range_left = 31;
514 astbuf3->range_right = 0;
515 astbuf3->is_signed = true;
518 astbuf3->type = AST_GENVAR;
519 astbuf3->is_reg = true;
520 astbuf3->range_left = 31;
521 astbuf3->range_right = 0;
524 astbuf3->is_signed = true;
527 current_wire_rand = true;
530 current_wire_const = true;
534 '[' expr ':' expr ']' {
535 $$ = new AstNode(AST_RANGE);
536 $$->children.push_back($2);
537 $$->children.push_back($4);
539 '[' expr TOK_POS_INDEXED expr ']' {
540 $$ = new AstNode(AST_RANGE);
541 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), $4), AstNode::mkconst_int(1, true)));
542 $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
544 '[' expr TOK_NEG_INDEXED expr ']' {
545 $$ = new AstNode(AST_RANGE);
546 $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
547 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)), $4));
550 $$ = new AstNode(AST_RANGE);
551 $$->children.push_back($2);
555 non_opt_range non_opt_range {
556 $$ = new AstNode(AST_MULTIRANGE, $1, $2);
558 non_opt_multirange non_opt_range {
560 $$->children.push_back($2);
573 non_opt_multirange { $$ = $1; };
580 $$ = new AstNode(AST_RANGE);
581 $$->children.push_back(AstNode::mkconst_int(31, true));
582 $$->children.push_back(AstNode::mkconst_int(0, true));
583 $$->is_signed = true;
587 module_body module_body_stmt |
588 /* the following line makes the generate..endgenrate keywords optional */
589 module_body gen_stmt |
593 task_func_decl | specify_block |param_decl | localparam_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
594 always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
597 TOK_CHECKER TOK_ID ';' {
598 AstNode *node = new AstNode(AST_GENBLOCK);
600 ast_stack.back()->children.push_back(node);
601 ast_stack.push_back(node);
602 } module_body TOK_ENDCHECKER {
604 ast_stack.pop_back();
608 attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
609 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
610 current_function_or_task->str = *$4;
611 append_attr(current_function_or_task, $1);
612 ast_stack.back()->children.push_back(current_function_or_task);
615 } opt_dpi_function_args ';' {
616 current_function_or_task = NULL;
618 attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
619 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
620 current_function_or_task->str = *$6;
621 append_attr(current_function_or_task, $1);
622 ast_stack.back()->children.push_back(current_function_or_task);
626 } opt_dpi_function_args ';' {
627 current_function_or_task = NULL;
629 attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
630 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
631 current_function_or_task->str = *$8;
632 append_attr(current_function_or_task, $1);
633 ast_stack.back()->children.push_back(current_function_or_task);
638 } opt_dpi_function_args ';' {
639 current_function_or_task = NULL;
641 attr TOK_TASK opt_automatic TOK_ID {
642 current_function_or_task = new AstNode(AST_TASK);
643 current_function_or_task->str = *$4;
644 append_attr(current_function_or_task, $1);
645 ast_stack.back()->children.push_back(current_function_or_task);
646 ast_stack.push_back(current_function_or_task);
647 current_function_or_task_port_id = 1;
649 } task_func_args_opt ';' task_func_body TOK_ENDTASK {
650 current_function_or_task = NULL;
651 ast_stack.pop_back();
653 attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID {
654 current_function_or_task = new AstNode(AST_FUNCTION);
655 current_function_or_task->str = *$6;
656 append_attr(current_function_or_task, $1);
657 ast_stack.back()->children.push_back(current_function_or_task);
658 ast_stack.push_back(current_function_or_task);
659 AstNode *outreg = new AstNode(AST_WIRE);
661 outreg->is_signed = $4;
662 outreg->is_reg = true;
664 outreg->children.push_back($5);
665 outreg->is_signed = $4 || $5->is_signed;
666 $5->is_signed = false;
668 current_function_or_task->children.push_back(outreg);
669 current_function_or_task_port_id = 1;
671 } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
672 current_function_or_task = NULL;
673 ast_stack.pop_back();
678 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
683 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
687 opt_dpi_function_args:
688 '(' dpi_function_args ')' |
692 dpi_function_args ',' dpi_function_arg |
693 dpi_function_args ',' |
710 '(' ')' | /* empty */ | '(' {
714 } task_func_args optional_comma {
722 task_func_port | task_func_args ',' task_func_port;
725 attr wire_type range {
735 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
737 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions (task/function arguments)");
739 astbuf2 = new AstNode(AST_RANGE);
740 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
741 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
744 if (astbuf2 && astbuf2->children.size() != 2)
745 frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
746 } wire_name | wire_name;
749 task_func_body behavioral_stmt |
752 /*************************** specify parser ***************************/
755 TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
758 specify_item specify_item_list |
762 specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
763 AstNode *en_expr = $1;
764 char specify_edge = $3;
765 AstNode *src_expr = $4;
767 specify_target *target = $6;
768 specify_rise_fall *timing = $9;
770 if (specify_edge != 0 && target->dat == nullptr)
771 frontend_verilog_yyerror("Found specify edge but no data spec.\n");
773 AstNode *cell = new AstNode(AST_CELL);
774 ast_stack.back()->children.push_back(cell);
775 cell->str = stringf("$specify$%d", autoidx++);
776 cell->children.push_back(new AstNode(AST_CELLTYPE));
777 cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
779 char oper_polarity = 0;
780 char oper_type = oper->at(0);
782 if (oper->size() == 3) {
783 oper_polarity = oper->at(0);
784 oper_type = oper->at(1);
787 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
788 cell->children.back()->str = "\\FULL";
790 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
791 cell->children.back()->str = "\\SRC_DST_PEN";
793 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
794 cell->children.back()->str = "\\SRC_DST_POL";
796 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
797 cell->children.back()->str = "\\T_RISE_MIN";
799 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
800 cell->children.back()->str = "\\T_RISE_TYP";
802 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
803 cell->children.back()->str = "\\T_RISE_MAX";
805 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
806 cell->children.back()->str = "\\T_FALL_MIN";
808 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
809 cell->children.back()->str = "\\T_FALL_TYP";
811 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
812 cell->children.back()->str = "\\T_FALL_MAX";
814 cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
815 cell->children.back()->str = "\\EN";
817 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
818 cell->children.back()->str = "\\SRC";
820 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
821 cell->children.back()->str = "\\DST";
825 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
826 cell->children.back()->str = "\\EDGE_EN";
828 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
829 cell->children.back()->str = "\\EDGE_POL";
831 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
832 cell->children.back()->str = "\\DAT_DST_PEN";
834 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
835 cell->children.back()->str = "\\DAT_DST_POL";
837 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
838 cell->children.back()->str = "\\DAT";
845 TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' expr specify_opt_arg ')' ';' {
846 if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
847 *$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
848 frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
850 AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
851 AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
852 AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
854 AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
855 AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
856 AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
858 AstNode *limit = $11;
859 AstNode *limit2 = $12;
861 AstNode *cell = new AstNode(AST_CELL);
862 ast_stack.back()->children.push_back(cell);
863 cell->str = stringf("$specify$%d", autoidx++);
864 cell->children.push_back(new AstNode(AST_CELLTYPE));
865 cell->children.back()->str = "$specrule";
867 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
868 cell->children.back()->str = "\\TYPE";
870 cell->children.push_back(new AstNode(AST_PARASET, limit));
871 cell->children.back()->str = "\\T_LIMIT";
873 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2 : AstNode::mkconst_int(0, true)));
874 cell->children.back()->str = "\\T_LIMIT2";
876 cell->children.push_back(new AstNode(AST_PARASET, src_pen));
877 cell->children.back()->str = "\\SRC_PEN";
879 cell->children.push_back(new AstNode(AST_PARASET, src_pol));
880 cell->children.back()->str = "\\SRC_POL";
882 cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
883 cell->children.back()->str = "\\DST_PEN";
885 cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
886 cell->children.back()->str = "\\DST_POL";
888 cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
889 cell->children.back()->str = "\\SRC_EN";
891 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
892 cell->children.back()->str = "\\SRC";
894 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
895 cell->children.back()->str = "\\DST_EN";
897 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
898 cell->children.back()->str = "\\DST";
912 TOK_IF '(' expr ')' {
920 TOK_SPECIFY_AND expr {
929 $$ = new specify_target;
934 '(' expr ':' expr ')'{
935 $$ = new specify_target;
940 '(' expr TOK_NEG_INDEXED expr ')'{
941 $$ = new specify_target;
942 $$->polarity_op = '-';
946 '(' expr TOK_POS_INDEXED expr ')'{
947 $$ = new specify_target;
948 $$->polarity_op = '+';
954 TOK_POSEDGE { $$ = 'p'; } |
955 TOK_NEGEDGE { $$ = 'n'; } |
960 $$ = new specify_rise_fall;
962 $$->fall.t_min = $1->t_min->clone();
963 $$->fall.t_avg = $1->t_avg->clone();
964 $$->fall.t_max = $1->t_max->clone();
967 '(' specify_triple ',' specify_triple ')' {
968 $$ = new specify_rise_fall;
977 $$ = new specify_triple;
979 $$->t_avg = $1->clone();
980 $$->t_max = $1->clone();
982 expr ':' expr ':' expr {
983 $$ = new specify_triple;
989 /******************** ignored specify parser **************************/
991 ignored_specify_block:
992 TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
993 TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
995 ignored_specify_item_opt:
996 ignored_specify_item_opt ignored_specify_item |
997 ignored_specify_item ;
999 ignored_specify_item:
1000 specparam_declaration
1001 // | pulsestyle_declaration
1002 // | showcancelled_declaration
1004 | system_timing_declaration
1007 specparam_declaration:
1008 TOK_SPECPARAM list_of_specparam_assignments ';' |
1009 TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ;
1011 // IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match
1012 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
1013 // exxxxtending this for SV specparam would change this anyhow
1015 '[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
1017 list_of_specparam_assignments:
1018 specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
1020 specparam_assignment:
1021 ignspec_id '=' constant_mintypmax_expression ;
1024 pulsestyle_declaration :
1027 showcancelled_declaration :
1032 simple_path_declaration ';'
1033 // | edge_sensitive_path_declaration
1034 // | state_dependent_path_declaration
1037 simple_path_declaration :
1038 parallel_path_description '=' path_delay_value |
1039 full_path_description '=' path_delay_value
1043 '(' path_delay_expression list_of_path_delay_extra_expressions ')'
1044 | path_delay_expression
1045 | path_delay_expression list_of_path_delay_extra_expressions
1048 list_of_path_delay_extra_expressions :
1050 t_path_delay_expression
1051 | trise_path_delay_expression ',' tfall_path_delay_expression
1052 | trise_path_delay_expression ',' tfall_path_delay_expression ',' tz_path_delay_expression
1053 | t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
1054 tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression
1055 | t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
1056 tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression ','
1057 t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ','
1058 tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression
1060 ',' path_delay_expression
1061 | ',' path_delay_expression ',' path_delay_expression
1062 | ',' path_delay_expression ',' path_delay_expression ','
1063 path_delay_expression ',' path_delay_expression ',' path_delay_expression
1064 | ',' path_delay_expression ',' path_delay_expression ','
1065 path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
1066 path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
1067 path_delay_expression ',' path_delay_expression ',' path_delay_expression
1070 parallel_path_description :
1071 '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
1073 full_path_description :
1074 '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ;
1076 // This was broken into 2 rules to solve shift/reduce conflicts
1077 list_of_path_inputs :
1078 specify_input_terminal_descriptor opt_polarity_operator |
1079 specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
1082 ',' specify_input_terminal_descriptor |
1083 more_path_inputs ',' specify_input_terminal_descriptor ;
1085 list_of_path_outputs :
1086 specify_output_terminal_descriptor |
1087 list_of_path_outputs ',' specify_output_terminal_descriptor ;
1089 opt_polarity_operator :
1094 // Good enough for the time being
1095 specify_input_terminal_descriptor :
1098 // Good enough for the time being
1099 specify_output_terminal_descriptor :
1102 system_timing_declaration :
1103 ignspec_id '(' system_timing_args ')' ';' ;
1106 TOK_POSEDGE ignspec_id |
1107 TOK_NEGEDGE ignspec_id |
1110 system_timing_args :
1112 system_timing_args ',' system_timing_arg ;
1115 t_path_delay_expression :
1116 path_delay_expression;
1118 trise_path_delay_expression :
1119 path_delay_expression;
1121 tfall_path_delay_expression :
1122 path_delay_expression;
1124 tz_path_delay_expression :
1125 path_delay_expression;
1127 t01_path_delay_expression :
1128 path_delay_expression;
1130 t10_path_delay_expression :
1131 path_delay_expression;
1133 t0z_path_delay_expression :
1134 path_delay_expression;
1136 tz1_path_delay_expression :
1137 path_delay_expression;
1139 t1z_path_delay_expression :
1140 path_delay_expression;
1142 tz0_path_delay_expression :
1143 path_delay_expression;
1145 t0x_path_delay_expression :
1146 path_delay_expression;
1148 tx1_path_delay_expression :
1149 path_delay_expression;
1151 t1x_path_delay_expression :
1152 path_delay_expression;
1154 tx0_path_delay_expression :
1155 path_delay_expression;
1157 txz_path_delay_expression :
1158 path_delay_expression;
1160 tzx_path_delay_expression :
1161 path_delay_expression;
1164 path_delay_expression :
1165 ignspec_constant_expression;
1167 constant_mintypmax_expression :
1168 ignspec_constant_expression
1169 | ignspec_constant_expression ':' ignspec_constant_expression ':' ignspec_constant_expression
1172 // for the time being this is OK, but we may write our own expr here.
1173 // as I'm not sure it is legal to use a full expr here (probably not)
1174 // On the other hand, other rules requiring constant expressions also use 'expr'
1175 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
1176 ignspec_constant_expression:
1177 expr { delete $1; };
1180 expr { delete $1; };
1183 TOK_ID { delete $1; };
1185 /**********************************************************************/
1189 astbuf1->is_signed = true;
1194 if (astbuf1->children.size() != 1)
1195 frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
1196 astbuf1->children.push_back(new AstNode(AST_RANGE));
1197 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
1198 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
1199 astbuf1->is_signed = true;
1204 if (astbuf1->children.size() != 1)
1205 frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
1206 astbuf1->children.push_back(new AstNode(AST_REALVALUE));
1212 if (astbuf1->children.size() != 1)
1213 frontend_verilog_yyerror("integer/real parameters should not have a range.");
1214 astbuf1->children.push_back($1);
1219 attr TOK_PARAMETER {
1220 astbuf1 = new AstNode(AST_PARAMETER);
1221 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1222 append_attr(astbuf1, $1);
1223 } param_signed param_integer param_real param_range param_decl_list ';' {
1228 attr TOK_LOCALPARAM {
1229 astbuf1 = new AstNode(AST_LOCALPARAM);
1230 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1231 append_attr(astbuf1, $1);
1232 } param_signed param_integer param_real param_range param_decl_list ';' {
1237 single_param_decl | param_decl_list ',' single_param_decl;
1242 if (astbuf1 == nullptr) {
1244 frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword");
1245 node = new AstNode(AST_PARAMETER);
1246 node->children.push_back(AstNode::mkconst_int(0, true));
1248 node = astbuf1->clone();
1251 delete node->children[0];
1252 node->children[0] = $3;
1253 ast_stack.back()->children.push_back(node);
1258 TOK_DEFPARAM defparam_decl_list ';';
1261 single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
1263 single_defparam_decl:
1264 range rvalue '=' expr {
1265 AstNode *node = new AstNode(AST_DEFPARAM);
1266 node->children.push_back($2);
1267 node->children.push_back($4);
1269 node->children.push_back($1);
1270 ast_stack.back()->children.push_back(node);
1274 attr wire_type range {
1278 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
1280 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
1282 astbuf2 = new AstNode(AST_RANGE);
1283 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
1284 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
1287 if (astbuf2 && astbuf2->children.size() != 2)
1288 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
1291 if (astbuf2 != NULL)
1295 attr TOK_SUPPLY0 TOK_ID {
1296 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1297 ast_stack.back()->children.back()->str = *$3;
1298 append_attr(ast_stack.back()->children.back(), $1);
1299 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
1300 ast_stack.back()->children.back()->children[0]->str = *$3;
1302 } opt_supply_wires ';' |
1303 attr TOK_SUPPLY1 TOK_ID {
1304 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1305 ast_stack.back()->children.back()->str = *$3;
1306 append_attr(ast_stack.back()->children.back(), $1);
1307 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
1308 ast_stack.back()->children.back()->children[0]->str = *$3;
1310 } opt_supply_wires ';';
1314 opt_supply_wires ',' TOK_ID {
1315 AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
1316 AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
1317 wire_node->str = *$3;
1318 assign_node->children[0]->str = *$3;
1319 ast_stack.back()->children.push_back(wire_node);
1320 ast_stack.back()->children.push_back(assign_node);
1325 wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
1327 wire_name_and_opt_assign:
1329 bool attr_anyconst = false;
1330 bool attr_anyseq = false;
1331 bool attr_allconst = false;
1332 bool attr_allseq = false;
1333 if (ast_stack.back()->children.back()->get_bool_attribute("\\anyconst")) {
1334 delete ast_stack.back()->children.back()->attributes.at("\\anyconst");
1335 ast_stack.back()->children.back()->attributes.erase("\\anyconst");
1336 attr_anyconst = true;
1338 if (ast_stack.back()->children.back()->get_bool_attribute("\\anyseq")) {
1339 delete ast_stack.back()->children.back()->attributes.at("\\anyseq");
1340 ast_stack.back()->children.back()->attributes.erase("\\anyseq");
1343 if (ast_stack.back()->children.back()->get_bool_attribute("\\allconst")) {
1344 delete ast_stack.back()->children.back()->attributes.at("\\allconst");
1345 ast_stack.back()->children.back()->attributes.erase("\\allconst");
1346 attr_allconst = true;
1348 if (ast_stack.back()->children.back()->get_bool_attribute("\\allseq")) {
1349 delete ast_stack.back()->children.back()->attributes.at("\\allseq");
1350 ast_stack.back()->children.back()->attributes.erase("\\allseq");
1353 if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
1354 AstNode *wire = new AstNode(AST_IDENTIFIER);
1355 AstNode *fcall = new AstNode(AST_FCALL);
1356 wire->str = ast_stack.back()->children.back()->str;
1357 fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
1359 fcall->str = "\\$anyconst";
1361 fcall->str = "\\$anyseq";
1363 fcall->str = "\\$allconst";
1365 fcall->str = "\\$allseq";
1366 fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
1367 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
1370 wire_name '=' expr {
1371 AstNode *wire = new AstNode(AST_IDENTIFIER);
1372 wire->str = ast_stack.back()->children.back()->str;
1373 if (astbuf1->is_input) {
1374 if (astbuf1->attributes.count("\\defaultvalue"))
1375 delete astbuf1->attributes.at("\\defaultvalue");
1376 astbuf1->attributes["\\defaultvalue"] = $3;
1378 if (astbuf1->is_reg || astbuf1->is_logic)
1379 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $3))));
1381 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3));
1385 TOK_ID range_or_multirange {
1386 if (astbuf1 == nullptr)
1387 frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node.");
1388 AstNode *node = astbuf1->clone();
1390 append_attr_clone(node, albuf);
1391 if (astbuf2 != NULL)
1392 node->children.push_back(astbuf2->clone());
1394 if (node->is_input || node->is_output)
1395 frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
1397 AstNode *rng = new AstNode(AST_RANGE);
1398 rng->children.push_back(AstNode::mkconst_int(0, true));
1399 rng->children.push_back(AstNode::mkconst_int(0, true));
1400 node->children.push_back(rng);
1402 node->type = AST_MEMORY;
1403 auto *rangeNode = $2;
1404 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
1405 // SV array size [n], rewrite as [n-1:0]
1406 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
1407 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
1409 node->children.push_back(rangeNode);
1411 if (current_function_or_task == NULL) {
1412 if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
1413 port_stubs[*$1] = ++port_counter;
1415 if (port_stubs.count(*$1) != 0) {
1416 if (!node->is_input && !node->is_output)
1417 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
1418 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
1419 frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
1420 node->port_id = port_stubs[*$1];
1421 port_stubs.erase(*$1);
1423 if (node->is_input || node->is_output)
1424 frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
1427 if (node->is_input || node->is_output)
1428 node->port_id = current_function_or_task_port_id++;
1430 ast_stack.back()->children.push_back(node);
1436 TOK_ASSIGN delay assign_expr_list ';';
1439 assign_expr | assign_expr_list ',' assign_expr;
1443 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, $1, $3));
1448 astbuf1 = new AstNode(AST_CELL);
1449 append_attr(astbuf1, $1);
1450 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
1451 astbuf1->children[0]->str = *$2;
1453 } cell_parameter_list_opt cell_list ';' {
1456 attr tok_prim_wrapper delay {
1457 astbuf1 = new AstNode(AST_PRIMITIVE);
1459 append_attr(astbuf1, $1);
1470 $$ = new std::string("or");
1475 cell_list ',' single_cell;
1479 astbuf2 = astbuf1->clone();
1480 if (astbuf2->type != AST_PRIMITIVE)
1483 ast_stack.back()->children.push_back(astbuf2);
1484 } '(' cell_port_list ')' |
1485 TOK_ID non_opt_range {
1486 astbuf2 = astbuf1->clone();
1487 if (astbuf2->type != AST_PRIMITIVE)
1490 ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
1491 } '(' cell_port_list ')';
1495 prim_list ',' single_prim;
1500 astbuf2 = astbuf1->clone();
1501 ast_stack.back()->children.push_back(astbuf2);
1502 } '(' cell_port_list ')';
1504 cell_parameter_list_opt:
1505 '#' '(' cell_parameter_list ')' | /* empty */;
1507 cell_parameter_list:
1508 cell_parameter | cell_parameter_list ',' cell_parameter;
1513 AstNode *node = new AstNode(AST_PARASET);
1514 astbuf1->children.push_back(node);
1515 node->children.push_back($1);
1517 '.' TOK_ID '(' expr ')' {
1518 AstNode *node = new AstNode(AST_PARASET);
1520 astbuf1->children.push_back(node);
1521 node->children.push_back($4);
1526 cell_port_list_rules {
1527 // remove empty args from end of list
1528 while (!astbuf2->children.empty()) {
1529 AstNode *node = astbuf2->children.back();
1530 if (node->type != AST_ARGUMENT) break;
1531 if (!node->children.empty()) break;
1532 if (!node->str.empty()) break;
1533 astbuf2->children.pop_back();
1538 bool has_positional_args = false;
1539 bool has_named_args = false;
1540 for (auto node : astbuf2->children) {
1541 if (node->type != AST_ARGUMENT) continue;
1542 if (node->str.empty())
1543 has_positional_args = true;
1545 has_named_args = true;
1548 if (has_positional_args && has_named_args)
1549 frontend_verilog_yyerror("Mix of positional and named cell ports.");
1552 cell_port_list_rules:
1553 cell_port | cell_port_list_rules ',' cell_port;
1557 AstNode *node = new AstNode(AST_ARGUMENT);
1558 astbuf2->children.push_back(node);
1562 AstNode *node = new AstNode(AST_ARGUMENT);
1563 astbuf2->children.push_back(node);
1564 node->children.push_back($2);
1567 attr '.' TOK_ID '(' expr ')' {
1568 AstNode *node = new AstNode(AST_ARGUMENT);
1570 astbuf2->children.push_back(node);
1571 node->children.push_back($5);
1575 attr '.' TOK_ID '(' ')' {
1576 AstNode *node = new AstNode(AST_ARGUMENT);
1578 astbuf2->children.push_back(node);
1583 AstNode *node = new AstNode(AST_ARGUMENT);
1585 astbuf2->children.push_back(node);
1586 node->children.push_back(new AstNode(AST_IDENTIFIER));
1587 node->children.back()->str = *$3;
1594 AstNode *node = new AstNode(AST_ALWAYS);
1595 append_attr(node, $1);
1596 ast_stack.back()->children.push_back(node);
1597 ast_stack.push_back(node);
1599 AstNode *block = new AstNode(AST_BLOCK);
1600 ast_stack.back()->children.push_back(block);
1601 ast_stack.push_back(block);
1603 ast_stack.pop_back();
1604 ast_stack.pop_back();
1607 AstNode *node = new AstNode(AST_INITIAL);
1608 append_attr(node, $1);
1609 ast_stack.back()->children.push_back(node);
1610 ast_stack.push_back(node);
1611 AstNode *block = new AstNode(AST_BLOCK);
1612 ast_stack.back()->children.push_back(block);
1613 ast_stack.push_back(block);
1615 ast_stack.pop_back();
1616 ast_stack.pop_back();
1620 '@' '(' always_events ')' |
1622 '@' ATTR_BEGIN ')' |
1629 always_events TOK_OR always_event |
1630 always_events ',' always_event;
1634 AstNode *node = new AstNode(AST_POSEDGE);
1635 ast_stack.back()->children.push_back(node);
1636 node->children.push_back($2);
1639 AstNode *node = new AstNode(AST_NEGEDGE);
1640 ast_stack.back()->children.push_back(node);
1641 node->children.push_back($2);
1644 AstNode *node = new AstNode(AST_EDGE);
1645 ast_stack.back()->children.push_back(node);
1646 node->children.push_back($1);
1677 TOK_MODPORT TOK_ID {
1678 AstNode *modport = new AstNode(AST_MODPORT);
1679 ast_stack.back()->children.push_back(modport);
1680 ast_stack.push_back(modport);
1683 } modport_args_opt {
1684 ast_stack.pop_back();
1685 log_assert(ast_stack.size() == 2);
1689 '(' ')' | '(' modport_args optional_comma ')';
1692 modport_arg | modport_args ',' modport_arg;
1695 modport_type_token modport_member |
1700 AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
1701 ast_stack.back()->children.push_back(modport_member);
1702 modport_member->str = *$1;
1703 modport_member->is_input = current_modport_input;
1704 modport_member->is_output = current_modport_output;
1709 TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
1712 opt_sva_label TOK_ASSERT opt_property '(' expr ')' ';' {
1713 if (noassert_mode) {
1716 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
1719 ast_stack.back()->children.push_back(node);
1724 opt_sva_label TOK_ASSUME opt_property '(' expr ')' ';' {
1725 if (noassume_mode) {
1728 AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
1731 ast_stack.back()->children.push_back(node);
1736 opt_sva_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
1737 if (noassert_mode) {
1740 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
1743 ast_stack.back()->children.push_back(node);
1748 opt_sva_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
1749 if (noassume_mode) {
1752 AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
1755 ast_stack.back()->children.push_back(node);
1760 opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
1761 AstNode *node = new AstNode(AST_COVER, $5);
1762 if ($1 != nullptr) {
1766 ast_stack.back()->children.push_back(node);
1768 opt_sva_label TOK_COVER opt_property '(' ')' ';' {
1769 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
1770 if ($1 != nullptr) {
1774 ast_stack.back()->children.push_back(node);
1776 opt_sva_label TOK_COVER ';' {
1777 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
1778 if ($1 != nullptr) {
1782 ast_stack.back()->children.push_back(node);
1784 opt_sva_label TOK_RESTRICT opt_property '(' expr ')' ';' {
1785 if (norestrict_mode) {
1788 AstNode *node = new AstNode(AST_ASSUME, $5);
1791 ast_stack.back()->children.push_back(node);
1794 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
1798 opt_sva_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
1799 if (norestrict_mode) {
1802 AstNode *node = new AstNode(AST_FAIR, $6);
1805 ast_stack.back()->children.push_back(node);
1808 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
1814 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
1815 ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5));
1816 if ($1 != nullptr) {
1817 ast_stack.back()->children.back()->str = *$1;
1821 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
1822 ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
1823 if ($1 != nullptr) {
1824 ast_stack.back()->children.back()->str = *$1;
1828 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
1829 ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6));
1830 if ($1 != nullptr) {
1831 ast_stack.back()->children.back()->str = *$1;
1835 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
1836 ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
1837 if ($1 != nullptr) {
1838 ast_stack.back()->children.back()->str = *$1;
1842 opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
1843 ast_stack.back()->children.push_back(new AstNode(AST_COVER, $5));
1844 if ($1 != nullptr) {
1845 ast_stack.back()->children.back()->str = *$1;
1849 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
1850 if (norestrict_mode) {
1853 ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
1854 if ($1 != nullptr) {
1855 ast_stack.back()->children.back()->str = *$1;
1860 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
1861 if (norestrict_mode) {
1864 ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
1865 if ($1 != nullptr) {
1866 ast_stack.back()->children.back()->str = *$1;
1872 simple_behavioral_stmt:
1873 lvalue '=' delay expr {
1874 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4);
1875 ast_stack.back()->children.push_back(node);
1877 lvalue TOK_INCREMENT {
1878 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true)));
1879 ast_stack.back()->children.push_back(node);
1881 lvalue TOK_DECREMENT {
1882 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true)));
1883 ast_stack.back()->children.push_back(node);
1885 lvalue OP_LE delay expr {
1886 AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4);
1887 ast_stack.back()->children.push_back(node);
1890 // this production creates the obligatory if-else shift/reduce conflict
1892 defattr | assert | wire_decl | param_decl | localparam_decl |
1893 non_opt_delay behavioral_stmt |
1894 simple_behavioral_stmt ';' | ';' |
1895 hierarchical_id attr {
1896 AstNode *node = new AstNode(AST_TCALL);
1899 ast_stack.back()->children.push_back(node);
1900 ast_stack.push_back(node);
1901 append_attr(node, $2);
1903 ast_stack.pop_back();
1905 TOK_MSG_TASKS attr {
1906 AstNode *node = new AstNode(AST_TCALL);
1909 ast_stack.back()->children.push_back(node);
1910 ast_stack.push_back(node);
1911 append_attr(node, $2);
1913 ast_stack.pop_back();
1915 attr TOK_BEGIN opt_label {
1916 AstNode *node = new AstNode(AST_BLOCK);
1917 ast_stack.back()->children.push_back(node);
1918 ast_stack.push_back(node);
1919 append_attr(node, $1);
1922 } behavioral_stmt_list TOK_END opt_label {
1923 if ($3 != NULL && $7 != NULL && *$3 != *$7)
1924 frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1);
1929 ast_stack.pop_back();
1932 AstNode *node = new AstNode(AST_FOR);
1933 ast_stack.back()->children.push_back(node);
1934 ast_stack.push_back(node);
1935 append_attr(node, $1);
1936 } simple_behavioral_stmt ';' expr {
1937 ast_stack.back()->children.push_back($7);
1938 } ';' simple_behavioral_stmt ')' {
1939 AstNode *block = new AstNode(AST_BLOCK);
1940 ast_stack.back()->children.push_back(block);
1941 ast_stack.push_back(block);
1943 ast_stack.pop_back();
1944 ast_stack.pop_back();
1946 attr TOK_WHILE '(' expr ')' {
1947 AstNode *node = new AstNode(AST_WHILE);
1948 ast_stack.back()->children.push_back(node);
1949 ast_stack.push_back(node);
1950 append_attr(node, $1);
1951 AstNode *block = new AstNode(AST_BLOCK);
1952 ast_stack.back()->children.push_back($4);
1953 ast_stack.back()->children.push_back(block);
1954 ast_stack.push_back(block);
1956 ast_stack.pop_back();
1957 ast_stack.pop_back();
1959 attr TOK_REPEAT '(' expr ')' {
1960 AstNode *node = new AstNode(AST_REPEAT);
1961 ast_stack.back()->children.push_back(node);
1962 ast_stack.push_back(node);
1963 append_attr(node, $1);
1964 AstNode *block = new AstNode(AST_BLOCK);
1965 ast_stack.back()->children.push_back($4);
1966 ast_stack.back()->children.push_back(block);
1967 ast_stack.push_back(block);
1969 ast_stack.pop_back();
1970 ast_stack.pop_back();
1972 attr TOK_IF '(' expr ')' {
1973 AstNode *node = new AstNode(AST_CASE);
1974 AstNode *block = new AstNode(AST_BLOCK);
1975 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
1976 ast_stack.back()->children.push_back(node);
1977 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
1978 node->children.push_back(cond);
1979 ast_stack.push_back(node);
1980 ast_stack.push_back(block);
1981 append_attr(node, $1);
1982 } behavioral_stmt optional_else {
1983 ast_stack.pop_back();
1984 ast_stack.pop_back();
1986 case_attr case_type '(' expr ')' {
1987 AstNode *node = new AstNode(AST_CASE, $4);
1988 ast_stack.back()->children.push_back(node);
1989 ast_stack.push_back(node);
1990 append_attr(node, $1);
1991 } opt_synopsys_attr case_body TOK_ENDCASE {
1992 case_type_stack.pop_back();
1993 ast_stack.pop_back();
2000 TOK_PRIORITY case_attr {
2003 TOK_UNIQUE case_attr {
2008 attr unique_case_attr {
2009 if ($2) (*$1)["\\parallel_case"] = AstNode::mkconst_int(1, false);
2015 case_type_stack.push_back(0);
2018 case_type_stack.push_back('x');
2021 case_type_stack.push_back('z');
2025 opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
2026 if (ast_stack.back()->attributes.count("\\full_case") == 0)
2027 ast_stack.back()->attributes["\\full_case"] = AstNode::mkconst_int(1, false);
2029 opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
2030 if (ast_stack.back()->attributes.count("\\parallel_case") == 0)
2031 ast_stack.back()->attributes["\\parallel_case"] = AstNode::mkconst_int(1, false);
2035 behavioral_stmt_list:
2036 behavioral_stmt_list behavioral_stmt |
2041 AstNode *block = new AstNode(AST_BLOCK);
2042 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
2043 ast_stack.pop_back();
2044 ast_stack.back()->children.push_back(cond);
2045 ast_stack.push_back(block);
2047 /* empty */ %prec FAKE_THEN;
2050 case_body case_item |
2055 AstNode *node = new AstNode(
2056 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2057 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2058 ast_stack.back()->children.push_back(node);
2059 ast_stack.push_back(node);
2061 AstNode *block = new AstNode(AST_BLOCK);
2062 ast_stack.back()->children.push_back(block);
2063 ast_stack.push_back(block);
2064 case_type_stack.push_back(0);
2066 case_type_stack.pop_back();
2067 ast_stack.pop_back();
2068 ast_stack.pop_back();
2072 gen_case_body gen_case_item |
2077 AstNode *node = new AstNode(
2078 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2079 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2080 ast_stack.back()->children.push_back(node);
2081 ast_stack.push_back(node);
2083 case_type_stack.push_back(0);
2084 } gen_stmt_or_null {
2085 case_type_stack.pop_back();
2086 ast_stack.pop_back();
2090 case_expr_list ':' |
2095 ast_stack.back()->children.push_back(new AstNode(AST_DEFAULT));
2098 ast_stack.back()->children.push_back(new AstNode(AST_IDENTIFIER));
2099 ast_stack.back()->children.back()->str = *$1;
2103 ast_stack.back()->children.push_back($1);
2105 case_expr_list ',' expr {
2106 ast_stack.back()->children.push_back($3);
2110 hierarchical_id '[' expr ']' '.' rvalue {
2111 $$ = new AstNode(AST_PREFIX, $3, $6);
2115 hierarchical_id range {
2116 $$ = new AstNode(AST_IDENTIFIER, $2);
2119 if ($2 == nullptr && ($$->str == "\\$initstate" ||
2120 $$->str == "\\$anyconst" || $$->str == "\\$anyseq" ||
2121 $$->str == "\\$allconst" || $$->str == "\\$allseq"))
2122 $$->type = AST_FCALL;
2124 hierarchical_id non_opt_multirange {
2125 $$ = new AstNode(AST_IDENTIFIER, $2);
2134 '{' lvalue_concat_list '}' {
2140 $$ = new AstNode(AST_CONCAT);
2141 $$->children.push_back($1);
2143 expr ',' lvalue_concat_list {
2145 $$->children.push_back($1);
2149 '(' arg_list optional_comma ')' |
2158 arg_list ',' single_arg;
2162 ast_stack.back()->children.push_back($1);
2166 module_gen_body gen_stmt_or_module_body_stmt |
2169 gen_stmt_or_module_body_stmt:
2170 gen_stmt | module_body_stmt;
2172 // this production creates the obligatory if-else shift/reduce conflict
2175 AstNode *node = new AstNode(AST_GENFOR);
2176 ast_stack.back()->children.push_back(node);
2177 ast_stack.push_back(node);
2178 } simple_behavioral_stmt ';' expr {
2179 ast_stack.back()->children.push_back($6);
2180 } ';' simple_behavioral_stmt ')' gen_stmt_block {
2181 ast_stack.pop_back();
2183 TOK_IF '(' expr ')' {
2184 AstNode *node = new AstNode(AST_GENIF);
2185 ast_stack.back()->children.push_back(node);
2186 ast_stack.push_back(node);
2187 ast_stack.back()->children.push_back($3);
2188 } gen_stmt_block opt_gen_else {
2189 ast_stack.pop_back();
2191 case_type '(' expr ')' {
2192 AstNode *node = new AstNode(AST_GENCASE, $3);
2193 ast_stack.back()->children.push_back(node);
2194 ast_stack.push_back(node);
2195 } gen_case_body TOK_ENDCASE {
2196 case_type_stack.pop_back();
2197 ast_stack.pop_back();
2199 TOK_BEGIN opt_label {
2200 AstNode *node = new AstNode(AST_GENBLOCK);
2201 node->str = $2 ? *$2 : std::string();
2202 ast_stack.back()->children.push_back(node);
2203 ast_stack.push_back(node);
2204 } module_gen_body TOK_END opt_label {
2209 ast_stack.pop_back();
2212 AstNode *node = new AstNode(AST_TECALL);
2215 ast_stack.back()->children.push_back(node);
2216 ast_stack.push_back(node);
2218 ast_stack.pop_back();
2223 AstNode *node = new AstNode(AST_GENBLOCK);
2224 ast_stack.back()->children.push_back(node);
2225 ast_stack.push_back(node);
2226 } gen_stmt_or_module_body_stmt {
2227 ast_stack.pop_back();
2231 gen_stmt_block | ';';
2234 TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
2240 basic_expr '?' attr expr ':' expr {
2241 $$ = new AstNode(AST_TERNARY);
2242 $$->children.push_back($1);
2243 $$->children.push_back($4);
2244 $$->children.push_back($6);
2245 append_attr($$, $3);
2252 '(' expr ')' TOK_CONSTVAL {
2253 if ($4->substr(0, 1) != "'")
2254 frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
2256 AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2258 log_error("Value conversion failed: `%s'\n", $4->c_str());
2259 $$ = new AstNode(AST_TO_BITS, bits, val);
2262 hierarchical_id TOK_CONSTVAL {
2263 if ($2->substr(0, 1) != "'")
2264 frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
2265 AstNode *bits = new AstNode(AST_IDENTIFIER);
2267 AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2269 log_error("Value conversion failed: `%s'\n", $2->c_str());
2270 $$ = new AstNode(AST_TO_BITS, bits, val);
2274 TOK_CONSTVAL TOK_CONSTVAL {
2275 $$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2276 if ($$ == NULL || (*$2)[0] != '\'')
2277 log_error("Value conversion failed: `%s%s'\n", $1->c_str(), $2->c_str());
2282 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2284 log_error("Value conversion failed: `%s'\n", $1->c_str());
2288 $$ = new AstNode(AST_REALVALUE);
2289 char *p = (char*)malloc(GetSize(*$1) + 1), *q;
2290 for (int i = 0, j = 0; j < GetSize(*$1); j++)
2291 if ((*$1)[j] != '_')
2292 p[i++] = (*$1)[j], p[i] = 0;
2293 $$->realvalue = strtod(p, &q);
2294 log_assert(*q == 0);
2299 $$ = AstNode::mkconst_str(*$1);
2302 hierarchical_id attr {
2303 AstNode *node = new AstNode(AST_FCALL);
2306 ast_stack.push_back(node);
2307 append_attr(node, $2);
2308 } '(' arg_list optional_comma ')' {
2309 $$ = ast_stack.back();
2310 ast_stack.pop_back();
2312 TOK_TO_SIGNED attr '(' expr ')' {
2313 $$ = new AstNode(AST_TO_SIGNED, $4);
2314 append_attr($$, $2);
2316 TOK_TO_UNSIGNED attr '(' expr ')' {
2317 $$ = new AstNode(AST_TO_UNSIGNED, $4);
2318 append_attr($$, $2);
2323 '(' expr ':' expr ':' expr ')' {
2328 '{' concat_list '}' {
2331 '{' expr '{' concat_list '}' '}' {
2332 $$ = new AstNode(AST_REPLICATE, $2, $4);
2334 '~' attr basic_expr %prec UNARY_OPS {
2335 $$ = new AstNode(AST_BIT_NOT, $3);
2336 append_attr($$, $2);
2338 basic_expr '&' attr basic_expr {
2339 $$ = new AstNode(AST_BIT_AND, $1, $4);
2340 append_attr($$, $3);
2342 basic_expr OP_NAND attr basic_expr {
2343 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
2344 append_attr($$, $3);
2346 basic_expr '|' attr basic_expr {
2347 $$ = new AstNode(AST_BIT_OR, $1, $4);
2348 append_attr($$, $3);
2350 basic_expr OP_NOR attr basic_expr {
2351 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
2352 append_attr($$, $3);
2354 basic_expr '^' attr basic_expr {
2355 $$ = new AstNode(AST_BIT_XOR, $1, $4);
2356 append_attr($$, $3);
2358 basic_expr OP_XNOR attr basic_expr {
2359 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
2360 append_attr($$, $3);
2362 '&' attr basic_expr %prec UNARY_OPS {
2363 $$ = new AstNode(AST_REDUCE_AND, $3);
2364 append_attr($$, $2);
2366 OP_NAND attr basic_expr %prec UNARY_OPS {
2367 $$ = new AstNode(AST_REDUCE_AND, $3);
2368 append_attr($$, $2);
2369 $$ = new AstNode(AST_LOGIC_NOT, $$);
2371 '|' attr basic_expr %prec UNARY_OPS {
2372 $$ = new AstNode(AST_REDUCE_OR, $3);
2373 append_attr($$, $2);
2375 OP_NOR attr basic_expr %prec UNARY_OPS {
2376 $$ = new AstNode(AST_REDUCE_OR, $3);
2377 append_attr($$, $2);
2378 $$ = new AstNode(AST_LOGIC_NOT, $$);
2380 '^' attr basic_expr %prec UNARY_OPS {
2381 $$ = new AstNode(AST_REDUCE_XOR, $3);
2382 append_attr($$, $2);
2384 OP_XNOR attr basic_expr %prec UNARY_OPS {
2385 $$ = new AstNode(AST_REDUCE_XNOR, $3);
2386 append_attr($$, $2);
2388 basic_expr OP_SHL attr basic_expr {
2389 $$ = new AstNode(AST_SHIFT_LEFT, $1, $4);
2390 append_attr($$, $3);
2392 basic_expr OP_SHR attr basic_expr {
2393 $$ = new AstNode(AST_SHIFT_RIGHT, $1, $4);
2394 append_attr($$, $3);
2396 basic_expr OP_SSHL attr basic_expr {
2397 $$ = new AstNode(AST_SHIFT_SLEFT, $1, $4);
2398 append_attr($$, $3);
2400 basic_expr OP_SSHR attr basic_expr {
2401 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, $4);
2402 append_attr($$, $3);
2404 basic_expr '<' attr basic_expr {
2405 $$ = new AstNode(AST_LT, $1, $4);
2406 append_attr($$, $3);
2408 basic_expr OP_LE attr basic_expr {
2409 $$ = new AstNode(AST_LE, $1, $4);
2410 append_attr($$, $3);
2412 basic_expr OP_EQ attr basic_expr {
2413 $$ = new AstNode(AST_EQ, $1, $4);
2414 append_attr($$, $3);
2416 basic_expr OP_NE attr basic_expr {
2417 $$ = new AstNode(AST_NE, $1, $4);
2418 append_attr($$, $3);
2420 basic_expr OP_EQX attr basic_expr {
2421 $$ = new AstNode(AST_EQX, $1, $4);
2422 append_attr($$, $3);
2424 basic_expr OP_NEX attr basic_expr {
2425 $$ = new AstNode(AST_NEX, $1, $4);
2426 append_attr($$, $3);
2428 basic_expr OP_GE attr basic_expr {
2429 $$ = new AstNode(AST_GE, $1, $4);
2430 append_attr($$, $3);
2432 basic_expr '>' attr basic_expr {
2433 $$ = new AstNode(AST_GT, $1, $4);
2434 append_attr($$, $3);
2436 basic_expr '+' attr basic_expr {
2437 $$ = new AstNode(AST_ADD, $1, $4);
2438 append_attr($$, $3);
2440 basic_expr '-' attr basic_expr {
2441 $$ = new AstNode(AST_SUB, $1, $4);
2442 append_attr($$, $3);
2444 basic_expr '*' attr basic_expr {
2445 $$ = new AstNode(AST_MUL, $1, $4);
2446 append_attr($$, $3);
2448 basic_expr '/' attr basic_expr {
2449 $$ = new AstNode(AST_DIV, $1, $4);
2450 append_attr($$, $3);
2452 basic_expr '%' attr basic_expr {
2453 $$ = new AstNode(AST_MOD, $1, $4);
2454 append_attr($$, $3);
2456 basic_expr OP_POW attr basic_expr {
2457 $$ = new AstNode(AST_POW, $1, $4);
2458 append_attr($$, $3);
2460 '+' attr basic_expr %prec UNARY_OPS {
2461 $$ = new AstNode(AST_POS, $3);
2462 append_attr($$, $2);
2464 '-' attr basic_expr %prec UNARY_OPS {
2465 $$ = new AstNode(AST_NEG, $3);
2466 append_attr($$, $2);
2468 basic_expr OP_LAND attr basic_expr {
2469 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
2470 append_attr($$, $3);
2472 basic_expr OP_LOR attr basic_expr {
2473 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
2474 append_attr($$, $3);
2476 '!' attr basic_expr %prec UNARY_OPS {
2477 $$ = new AstNode(AST_LOGIC_NOT, $3);
2478 append_attr($$, $2);
2483 $$ = new AstNode(AST_CONCAT, $1);
2485 expr ',' concat_list {
2487 $$->children.push_back($1);