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correct wire declaration grammar for #1614
[yosys.git] / frontends / verilog / verilog_parser.y
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * The Verilog frontend.
21 *
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
26 *
27 * ---
28 *
29 * This is the actual bison parser for Verilog code. The AST ist created directly
30 * from the bison reduce functions here. Note that this code uses a few global
31 * variables to hold the state of the AST generator and therefore this parser is
32 * not reentrant.
33 *
34 */
35
36 %{
37 #include <list>
38 #include <stack>
39 #include <string.h>
40 #include "frontends/verilog/verilog_frontend.h"
41 #include "kernel/log.h"
42
43 USING_YOSYS_NAMESPACE
44 using namespace AST;
45 using namespace VERILOG_FRONTEND;
46
47 YOSYS_NAMESPACE_BEGIN
48 namespace VERILOG_FRONTEND {
49 int port_counter;
50 std::map<std::string, int> port_stubs;
51 std::map<std::string, AstNode*> *attr_list, default_attr_list;
52 std::stack<std::map<std::string, AstNode*> *> attr_list_stack;
53 std::map<std::string, AstNode*> *albuf;
54 std::vector<AstNode*> ast_stack;
55 struct AstNode *astbuf1, *astbuf2, *astbuf3;
56 struct AstNode *current_function_or_task;
57 struct AstNode *current_ast, *current_ast_mod;
58 int current_function_or_task_port_id;
59 std::vector<char> case_type_stack;
60 bool do_not_require_port_stubs;
61 bool default_nettype_wire;
62 bool sv_mode, formal_mode, lib_mode, specify_mode;
63 bool noassert_mode, noassume_mode, norestrict_mode;
64 bool assume_asserts_mode, assert_assumes_mode;
65 bool current_wire_rand, current_wire_const;
66 bool current_modport_input, current_modport_output;
67 std::istream *lexin;
68 }
69 YOSYS_NAMESPACE_END
70
71 static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
72 {
73 for (auto &it : *al) {
74 if (ast->attributes.count(it.first) > 0)
75 delete ast->attributes[it.first];
76 ast->attributes[it.first] = it.second;
77 }
78 delete al;
79 }
80
81 static void append_attr_clone(AstNode *ast, std::map<std::string, AstNode*> *al)
82 {
83 for (auto &it : *al) {
84 if (ast->attributes.count(it.first) > 0)
85 delete ast->attributes[it.first];
86 ast->attributes[it.first] = it.second->clone();
87 }
88 }
89
90 static void free_attr(std::map<std::string, AstNode*> *al)
91 {
92 for (auto &it : *al)
93 delete it.second;
94 delete al;
95 }
96
97 struct specify_target {
98 char polarity_op;
99 AstNode *dst, *dat;
100 };
101
102 struct specify_triple {
103 AstNode *t_min, *t_avg, *t_max;
104 };
105
106 struct specify_rise_fall {
107 specify_triple rise;
108 specify_triple fall;
109 };
110
111 %}
112
113 %define api.prefix {frontend_verilog_yy}
114
115 /* The union is defined in the header, so we need to provide all the
116 * includes it requires
117 */
118 %code requires {
119 #include <map>
120 #include <string>
121 #include "frontends/verilog/verilog_frontend.h"
122 }
123
124 %union {
125 std::string *string;
126 struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
127 std::map<std::string, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
128 struct specify_target *specify_target_ptr;
129 struct specify_triple *specify_triple_ptr;
130 struct specify_rise_fall *specify_rise_fall_ptr;
131 bool boolean;
132 char ch;
133 }
134
135 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
136 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
137 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
138 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
139 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
140 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
141 %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR
142 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
143 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
144 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
145 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
146 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
147 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
148 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
149 %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND
150 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
151 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
152 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
153 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
154 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
155 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
156
157 %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
158 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
159 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id
160 %type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
161 %type <al> attr case_attr
162
163 %type <specify_target_ptr> specify_target
164 %type <specify_triple_ptr> specify_triple
165 %type <specify_rise_fall_ptr> specify_rise_fall
166 %type <ast> specify_if specify_condition specify_opt_arg
167 %type <ch> specify_edge
168
169 // operator precedence from low to high
170 %left OP_LOR
171 %left OP_LAND
172 %left '|' OP_NOR
173 %left '^' OP_XNOR
174 %left '&' OP_NAND
175 %left OP_EQ OP_NE OP_EQX OP_NEX
176 %left '<' OP_LE OP_GE '>'
177 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
178 %left '+' '-'
179 %left '*' '/' '%'
180 %left OP_POW
181 %right UNARY_OPS
182
183 %define parse.error verbose
184 %define parse.lac full
185
186 %nonassoc FAKE_THEN
187 %nonassoc TOK_ELSE
188
189 %debug
190
191 %%
192
193 input: {
194 ast_stack.clear();
195 ast_stack.push_back(current_ast);
196 } design {
197 ast_stack.pop_back();
198 log_assert(GetSize(ast_stack) == 0);
199 for (auto &it : default_attr_list)
200 delete it.second;
201 default_attr_list.clear();
202 };
203
204 design:
205 module design |
206 defattr design |
207 task_func_decl design |
208 param_decl design |
209 localparam_decl design |
210 typedef_decl design |
211 package design |
212 interface design |
213 /* empty */;
214
215 attr:
216 {
217 if (attr_list != nullptr)
218 attr_list_stack.push(attr_list);
219 attr_list = new std::map<std::string, AstNode*>;
220 for (auto &it : default_attr_list)
221 (*attr_list)[it.first] = it.second->clone();
222 } attr_opt {
223 $$ = attr_list;
224 if (!attr_list_stack.empty()) {
225 attr_list = attr_list_stack.top();
226 attr_list_stack.pop();
227 } else
228 attr_list = nullptr;
229 };
230
231 attr_opt:
232 attr_opt ATTR_BEGIN opt_attr_list ATTR_END |
233 /* empty */;
234
235 defattr:
236 DEFATTR_BEGIN {
237 if (attr_list != nullptr)
238 attr_list_stack.push(attr_list);
239 attr_list = new std::map<std::string, AstNode*>;
240 for (auto &it : default_attr_list)
241 delete it.second;
242 default_attr_list.clear();
243 } opt_attr_list {
244 attr_list->swap(default_attr_list);
245 delete attr_list;
246 if (!attr_list_stack.empty()) {
247 attr_list = attr_list_stack.top();
248 attr_list_stack.pop();
249 } else
250 attr_list = nullptr;
251 } DEFATTR_END;
252
253 opt_attr_list:
254 attr_list | /* empty */;
255
256 attr_list:
257 attr_assign |
258 attr_list ',' attr_assign;
259
260 attr_assign:
261 hierarchical_id {
262 if (attr_list->count(*$1) != 0)
263 delete (*attr_list)[*$1];
264 (*attr_list)[*$1] = AstNode::mkconst_int(1, false);
265 delete $1;
266 } |
267 hierarchical_id '=' expr {
268 if (attr_list->count(*$1) != 0)
269 delete (*attr_list)[*$1];
270 (*attr_list)[*$1] = $3;
271 delete $1;
272 };
273
274 hierarchical_id:
275 TOK_ID {
276 $$ = $1;
277 } |
278 hierarchical_id TOK_PACKAGESEP TOK_ID {
279 if ($3->compare(0, 1, "\\") == 0)
280 *$1 += "::" + $3->substr(1);
281 else
282 *$1 += "::" + *$3;
283 delete $3;
284 $$ = $1;
285 } |
286 hierarchical_id '.' TOK_ID {
287 if ($3->compare(0, 1, "\\") == 0)
288 *$1 += "." + $3->substr(1);
289 else
290 *$1 += "." + *$3;
291 delete $3;
292 $$ = $1;
293 };
294
295 hierarchical_type_id:
296 '(' hierarchical_id ')' { $$ = $2; };
297
298 module:
299 attr TOK_MODULE TOK_ID {
300 do_not_require_port_stubs = false;
301 AstNode *mod = new AstNode(AST_MODULE);
302 ast_stack.back()->children.push_back(mod);
303 ast_stack.push_back(mod);
304 current_ast_mod = mod;
305 port_stubs.clear();
306 port_counter = 0;
307 mod->str = *$3;
308 append_attr(mod, $1);
309 delete $3;
310 } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
311 if (port_stubs.size() != 0)
312 frontend_verilog_yyerror("Missing details for module port `%s'.",
313 port_stubs.begin()->first.c_str());
314 ast_stack.pop_back();
315 log_assert(ast_stack.size() == 1);
316 current_ast_mod = NULL;
317 };
318
319 module_para_opt:
320 '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
321
322 module_para_list:
323 single_module_para | module_para_list ',' single_module_para;
324
325 single_module_para:
326 /* empty */ |
327 attr TOK_PARAMETER {
328 if (astbuf1) delete astbuf1;
329 astbuf1 = new AstNode(AST_PARAMETER);
330 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
331 append_attr(astbuf1, $1);
332 } param_type single_param_decl |
333 attr TOK_LOCALPARAM {
334 if (astbuf1) delete astbuf1;
335 astbuf1 = new AstNode(AST_LOCALPARAM);
336 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
337 append_attr(astbuf1, $1);
338 } param_type single_param_decl |
339 single_param_decl;
340
341 module_args_opt:
342 '(' ')' | /* empty */ | '(' module_args optional_comma ')';
343
344 module_args:
345 module_arg | module_args ',' module_arg;
346
347 optional_comma:
348 ',' | /* empty */;
349
350 module_arg_opt_assignment:
351 '=' expr {
352 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
353 AstNode *wire = new AstNode(AST_IDENTIFIER);
354 wire->str = ast_stack.back()->children.back()->str;
355 if (ast_stack.back()->children.back()->is_input) {
356 AstNode *n = ast_stack.back()->children.back();
357 if (n->attributes.count("\\defaultvalue"))
358 delete n->attributes.at("\\defaultvalue");
359 n->attributes["\\defaultvalue"] = $2;
360 } else
361 if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
362 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
363 else
364 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
365 } else
366 frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
367 } |
368 /* empty */;
369
370 module_arg:
371 TOK_ID {
372 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
373 AstNode *node = ast_stack.back()->children.back()->clone();
374 node->str = *$1;
375 node->port_id = ++port_counter;
376 ast_stack.back()->children.push_back(node);
377 } else {
378 if (port_stubs.count(*$1) != 0)
379 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
380 port_stubs[*$1] = ++port_counter;
381 }
382 delete $1;
383 } module_arg_opt_assignment |
384 TOK_ID {
385 astbuf1 = new AstNode(AST_INTERFACEPORT);
386 astbuf1->children.push_back(new AstNode(AST_INTERFACEPORTTYPE));
387 astbuf1->children[0]->str = *$1;
388 delete $1;
389 } TOK_ID { /* SV interfaces */
390 if (!sv_mode)
391 frontend_verilog_yyerror("Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
392 astbuf2 = astbuf1->clone(); // really only needed if multiple instances of same type.
393 astbuf2->str = *$3;
394 delete $3;
395 astbuf2->port_id = ++port_counter;
396 ast_stack.back()->children.push_back(astbuf2);
397 delete astbuf1; // really only needed if multiple instances of same type.
398 } module_arg_opt_assignment |
399 attr wire_type range TOK_ID {
400 AstNode *node = $2;
401 node->str = *$4;
402 node->port_id = ++port_counter;
403 if ($3 != NULL)
404 node->children.push_back($3);
405 if (!node->is_input && !node->is_output)
406 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
407 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
408 frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
409 ast_stack.back()->children.push_back(node);
410 append_attr(node, $1);
411 delete $4;
412 } module_arg_opt_assignment |
413 '.' '.' '.' {
414 do_not_require_port_stubs = true;
415 };
416
417 package:
418 attr TOK_PACKAGE TOK_ID {
419 AstNode *mod = new AstNode(AST_PACKAGE);
420 ast_stack.back()->children.push_back(mod);
421 ast_stack.push_back(mod);
422 current_ast_mod = mod;
423 mod->str = *$3;
424 append_attr(mod, $1);
425 } ';' package_body TOK_ENDPACKAGE {
426 ast_stack.pop_back();
427 current_ast_mod = NULL;
428 };
429
430 package_body:
431 package_body package_body_stmt |;
432
433 package_body_stmt:
434 typedef_decl |
435 localparam_decl;
436
437 interface:
438 TOK_INTERFACE TOK_ID {
439 do_not_require_port_stubs = false;
440 AstNode *intf = new AstNode(AST_INTERFACE);
441 ast_stack.back()->children.push_back(intf);
442 ast_stack.push_back(intf);
443 current_ast_mod = intf;
444 port_stubs.clear();
445 port_counter = 0;
446 intf->str = *$2;
447 delete $2;
448 } module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
449 if (port_stubs.size() != 0)
450 frontend_verilog_yyerror("Missing details for module port `%s'.",
451 port_stubs.begin()->first.c_str());
452 ast_stack.pop_back();
453 log_assert(ast_stack.size() == 1);
454 current_ast_mod = NULL;
455 };
456
457 interface_body:
458 interface_body interface_body_stmt |;
459
460 interface_body_stmt:
461 param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
462 modport_stmt;
463
464 non_opt_delay:
465 '#' TOK_ID { delete $2; } |
466 '#' TOK_CONSTVAL { delete $2; } |
467 '#' TOK_REALVAL { delete $2; } |
468 '#' '(' expr ')' { delete $3; } |
469 '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
470
471 delay:
472 non_opt_delay | /* empty */;
473
474 wire_type:
475 {
476 astbuf3 = new AstNode(AST_WIRE);
477 current_wire_rand = false;
478 current_wire_const = false;
479 } wire_type_token_list {
480 $$ = astbuf3;
481 };
482
483 wire_type_token_list:
484 wire_type_token |
485 wire_type_token_list wire_type_token |
486 wire_type_token_io |
487 hierarchical_type_id {
488 astbuf3->is_custom_type = true;
489 astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
490 astbuf3->children.back()->str = *$1;
491 };
492
493 wire_type_token_io:
494 TOK_INPUT {
495 astbuf3->is_input = true;
496 } |
497 TOK_OUTPUT {
498 astbuf3->is_output = true;
499 } |
500 TOK_INOUT {
501 astbuf3->is_input = true;
502 astbuf3->is_output = true;
503 };
504
505 wire_type_token:
506 TOK_WIRE {
507 } |
508 TOK_WOR {
509 astbuf3->is_wor = true;
510 } |
511 TOK_WAND {
512 astbuf3->is_wand = true;
513 } |
514 TOK_REG {
515 astbuf3->is_reg = true;
516 } |
517 TOK_LOGIC {
518 astbuf3->is_logic = true;
519 } |
520 TOK_VAR {
521 astbuf3->is_logic = true;
522 } |
523 TOK_INTEGER {
524 astbuf3->is_reg = true;
525 astbuf3->range_left = 31;
526 astbuf3->range_right = 0;
527 astbuf3->is_signed = true;
528 } |
529 TOK_GENVAR {
530 astbuf3->type = AST_GENVAR;
531 astbuf3->is_reg = true;
532 astbuf3->is_signed = true;
533 astbuf3->range_left = 31;
534 astbuf3->range_right = 0;
535 } |
536 TOK_SIGNED {
537 astbuf3->is_signed = true;
538 } |
539 TOK_RAND {
540 current_wire_rand = true;
541 } |
542 TOK_CONST {
543 current_wire_const = true;
544 };
545
546 non_opt_range:
547 '[' expr ':' expr ']' {
548 $$ = new AstNode(AST_RANGE);
549 $$->children.push_back($2);
550 $$->children.push_back($4);
551 } |
552 '[' expr TOK_POS_INDEXED expr ']' {
553 $$ = new AstNode(AST_RANGE);
554 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), $4), AstNode::mkconst_int(1, true)));
555 $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
556 } |
557 '[' expr TOK_NEG_INDEXED expr ']' {
558 $$ = new AstNode(AST_RANGE);
559 $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
560 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)), $4));
561 } |
562 '[' expr ']' {
563 $$ = new AstNode(AST_RANGE);
564 $$->children.push_back($2);
565 };
566
567 non_opt_multirange:
568 non_opt_range non_opt_range {
569 $$ = new AstNode(AST_MULTIRANGE, $1, $2);
570 } |
571 non_opt_multirange non_opt_range {
572 $$ = $1;
573 $$->children.push_back($2);
574 };
575
576 range:
577 non_opt_range {
578 $$ = $1;
579 } |
580 /* empty */ {
581 $$ = NULL;
582 };
583
584 range_or_multirange:
585 range { $$ = $1; } |
586 non_opt_multirange { $$ = $1; };
587
588 range_or_signed_int:
589 range {
590 $$ = $1;
591 } |
592 TOK_INTEGER {
593 $$ = new AstNode(AST_RANGE);
594 $$->children.push_back(AstNode::mkconst_int(31, true));
595 $$->children.push_back(AstNode::mkconst_int(0, true));
596 $$->is_signed = true;
597 };
598
599 module_body:
600 module_body module_body_stmt |
601 /* the following line makes the generate..endgenrate keywords optional */
602 module_body gen_stmt |
603 /* empty */;
604
605 module_body_stmt:
606 task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
607 always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
608
609 checker_decl:
610 TOK_CHECKER TOK_ID ';' {
611 AstNode *node = new AstNode(AST_GENBLOCK);
612 node->str = *$2;
613 ast_stack.back()->children.push_back(node);
614 ast_stack.push_back(node);
615 } module_body TOK_ENDCHECKER {
616 delete $2;
617 ast_stack.pop_back();
618 };
619
620 task_func_decl:
621 attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
622 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
623 current_function_or_task->str = *$4;
624 append_attr(current_function_or_task, $1);
625 ast_stack.back()->children.push_back(current_function_or_task);
626 delete $3;
627 delete $4;
628 } opt_dpi_function_args ';' {
629 current_function_or_task = NULL;
630 } |
631 attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
632 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
633 current_function_or_task->str = *$6;
634 append_attr(current_function_or_task, $1);
635 ast_stack.back()->children.push_back(current_function_or_task);
636 delete $3;
637 delete $5;
638 delete $6;
639 } opt_dpi_function_args ';' {
640 current_function_or_task = NULL;
641 } |
642 attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
643 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
644 current_function_or_task->str = *$8;
645 append_attr(current_function_or_task, $1);
646 ast_stack.back()->children.push_back(current_function_or_task);
647 delete $3;
648 delete $5;
649 delete $7;
650 delete $8;
651 } opt_dpi_function_args ';' {
652 current_function_or_task = NULL;
653 } |
654 attr TOK_TASK opt_automatic TOK_ID {
655 current_function_or_task = new AstNode(AST_TASK);
656 current_function_or_task->str = *$4;
657 append_attr(current_function_or_task, $1);
658 ast_stack.back()->children.push_back(current_function_or_task);
659 ast_stack.push_back(current_function_or_task);
660 current_function_or_task_port_id = 1;
661 delete $4;
662 } task_func_args_opt ';' task_func_body TOK_ENDTASK {
663 current_function_or_task = NULL;
664 ast_stack.pop_back();
665 } |
666 attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID {
667 current_function_or_task = new AstNode(AST_FUNCTION);
668 current_function_or_task->str = *$6;
669 append_attr(current_function_or_task, $1);
670 ast_stack.back()->children.push_back(current_function_or_task);
671 ast_stack.push_back(current_function_or_task);
672 AstNode *outreg = new AstNode(AST_WIRE);
673 outreg->str = *$6;
674 outreg->is_signed = $4;
675 outreg->is_reg = true;
676 if ($5 != NULL) {
677 outreg->children.push_back($5);
678 outreg->is_signed = $4 || $5->is_signed;
679 $5->is_signed = false;
680 }
681 current_function_or_task->children.push_back(outreg);
682 current_function_or_task_port_id = 1;
683 delete $6;
684 } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
685 current_function_or_task = NULL;
686 ast_stack.pop_back();
687 };
688
689 dpi_function_arg:
690 TOK_ID TOK_ID {
691 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
692 delete $1;
693 delete $2;
694 } |
695 TOK_ID {
696 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
697 delete $1;
698 };
699
700 opt_dpi_function_args:
701 '(' dpi_function_args ')' |
702 /* empty */;
703
704 dpi_function_args:
705 dpi_function_args ',' dpi_function_arg |
706 dpi_function_args ',' |
707 dpi_function_arg |
708 /* empty */;
709
710 opt_automatic:
711 TOK_AUTOMATIC |
712 /* empty */;
713
714 opt_signed:
715 TOK_SIGNED {
716 $$ = true;
717 } |
718 /* empty */ {
719 $$ = false;
720 };
721
722 task_func_args_opt:
723 '(' ')' | /* empty */ | '(' {
724 albuf = nullptr;
725 astbuf1 = nullptr;
726 astbuf2 = nullptr;
727 } task_func_args optional_comma {
728 delete astbuf1;
729 if (astbuf2 != NULL)
730 delete astbuf2;
731 free_attr(albuf);
732 } ')';
733
734 task_func_args:
735 task_func_port | task_func_args ',' task_func_port;
736
737 task_func_port:
738 attr wire_type range {
739 if (albuf) {
740 delete astbuf1;
741 if (astbuf2 != NULL)
742 delete astbuf2;
743 free_attr(albuf);
744 }
745 albuf = $1;
746 astbuf1 = $2;
747 astbuf2 = $3;
748 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
749 if (astbuf2) {
750 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions (task/function arguments)");
751 } else {
752 astbuf2 = new AstNode(AST_RANGE);
753 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
754 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
755 }
756 }
757 if (astbuf2 && astbuf2->children.size() != 2)
758 frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
759 } wire_name | wire_name;
760
761 task_func_body:
762 task_func_body behavioral_stmt |
763 /* empty */;
764
765 /*************************** specify parser ***************************/
766
767 specify_block:
768 TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
769
770 specify_item_list:
771 specify_item specify_item_list |
772 /* empty */;
773
774 specify_item:
775 specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
776 AstNode *en_expr = $1;
777 char specify_edge = $3;
778 AstNode *src_expr = $4;
779 string *oper = $5;
780 specify_target *target = $6;
781 specify_rise_fall *timing = $9;
782
783 if (specify_edge != 0 && target->dat == nullptr)
784 frontend_verilog_yyerror("Found specify edge but no data spec.\n");
785
786 AstNode *cell = new AstNode(AST_CELL);
787 ast_stack.back()->children.push_back(cell);
788 cell->str = stringf("$specify$%d", autoidx++);
789 cell->children.push_back(new AstNode(AST_CELLTYPE));
790 cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
791
792 char oper_polarity = 0;
793 char oper_type = oper->at(0);
794
795 if (oper->size() == 3) {
796 oper_polarity = oper->at(0);
797 oper_type = oper->at(1);
798 }
799
800 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
801 cell->children.back()->str = "\\FULL";
802
803 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
804 cell->children.back()->str = "\\SRC_DST_PEN";
805
806 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
807 cell->children.back()->str = "\\SRC_DST_POL";
808
809 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
810 cell->children.back()->str = "\\T_RISE_MIN";
811
812 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
813 cell->children.back()->str = "\\T_RISE_TYP";
814
815 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
816 cell->children.back()->str = "\\T_RISE_MAX";
817
818 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
819 cell->children.back()->str = "\\T_FALL_MIN";
820
821 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
822 cell->children.back()->str = "\\T_FALL_TYP";
823
824 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
825 cell->children.back()->str = "\\T_FALL_MAX";
826
827 cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
828 cell->children.back()->str = "\\EN";
829
830 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
831 cell->children.back()->str = "\\SRC";
832
833 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
834 cell->children.back()->str = "\\DST";
835
836 if (target->dat)
837 {
838 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
839 cell->children.back()->str = "\\EDGE_EN";
840
841 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
842 cell->children.back()->str = "\\EDGE_POL";
843
844 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
845 cell->children.back()->str = "\\DAT_DST_PEN";
846
847 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
848 cell->children.back()->str = "\\DAT_DST_POL";
849
850 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
851 cell->children.back()->str = "\\DAT";
852 }
853
854 delete oper;
855 delete target;
856 delete timing;
857 } |
858 TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' expr specify_opt_arg ')' ';' {
859 if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
860 *$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
861 frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
862
863 AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
864 AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
865 AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
866
867 AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
868 AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
869 AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
870
871 AstNode *limit = $11;
872 AstNode *limit2 = $12;
873
874 AstNode *cell = new AstNode(AST_CELL);
875 ast_stack.back()->children.push_back(cell);
876 cell->str = stringf("$specify$%d", autoidx++);
877 cell->children.push_back(new AstNode(AST_CELLTYPE));
878 cell->children.back()->str = "$specrule";
879
880 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
881 cell->children.back()->str = "\\TYPE";
882
883 cell->children.push_back(new AstNode(AST_PARASET, limit));
884 cell->children.back()->str = "\\T_LIMIT";
885
886 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2 : AstNode::mkconst_int(0, true)));
887 cell->children.back()->str = "\\T_LIMIT2";
888
889 cell->children.push_back(new AstNode(AST_PARASET, src_pen));
890 cell->children.back()->str = "\\SRC_PEN";
891
892 cell->children.push_back(new AstNode(AST_PARASET, src_pol));
893 cell->children.back()->str = "\\SRC_POL";
894
895 cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
896 cell->children.back()->str = "\\DST_PEN";
897
898 cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
899 cell->children.back()->str = "\\DST_POL";
900
901 cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
902 cell->children.back()->str = "\\SRC_EN";
903
904 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
905 cell->children.back()->str = "\\SRC";
906
907 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
908 cell->children.back()->str = "\\DST_EN";
909
910 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
911 cell->children.back()->str = "\\DST";
912
913 delete $1;
914 };
915
916 specify_opt_arg:
917 ',' expr {
918 $$ = $2;
919 } |
920 /* empty */ {
921 $$ = nullptr;
922 };
923
924 specify_if:
925 TOK_IF '(' expr ')' {
926 $$ = $3;
927 } |
928 /* empty */ {
929 $$ = nullptr;
930 };
931
932 specify_condition:
933 TOK_SPECIFY_AND expr {
934 $$ = $2;
935 } |
936 /* empty */ {
937 $$ = nullptr;
938 };
939
940 specify_target:
941 expr {
942 $$ = new specify_target;
943 $$->polarity_op = 0;
944 $$->dst = $1;
945 $$->dat = nullptr;
946 } |
947 '(' expr ':' expr ')'{
948 $$ = new specify_target;
949 $$->polarity_op = 0;
950 $$->dst = $2;
951 $$->dat = $4;
952 } |
953 '(' expr TOK_NEG_INDEXED expr ')'{
954 $$ = new specify_target;
955 $$->polarity_op = '-';
956 $$->dst = $2;
957 $$->dat = $4;
958 } |
959 '(' expr TOK_POS_INDEXED expr ')'{
960 $$ = new specify_target;
961 $$->polarity_op = '+';
962 $$->dst = $2;
963 $$->dat = $4;
964 };
965
966 specify_edge:
967 TOK_POSEDGE { $$ = 'p'; } |
968 TOK_NEGEDGE { $$ = 'n'; } |
969 { $$ = 0; };
970
971 specify_rise_fall:
972 specify_triple {
973 $$ = new specify_rise_fall;
974 $$->rise = *$1;
975 $$->fall.t_min = $1->t_min->clone();
976 $$->fall.t_avg = $1->t_avg->clone();
977 $$->fall.t_max = $1->t_max->clone();
978 delete $1;
979 } |
980 '(' specify_triple ',' specify_triple ')' {
981 $$ = new specify_rise_fall;
982 $$->rise = *$2;
983 $$->fall = *$4;
984 delete $2;
985 delete $4;
986 };
987
988 specify_triple:
989 expr {
990 $$ = new specify_triple;
991 $$->t_min = $1;
992 $$->t_avg = $1->clone();
993 $$->t_max = $1->clone();
994 } |
995 expr ':' expr ':' expr {
996 $$ = new specify_triple;
997 $$->t_min = $1;
998 $$->t_avg = $3;
999 $$->t_max = $5;
1000 };
1001
1002 /******************** ignored specify parser **************************/
1003
1004 ignored_specify_block:
1005 TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
1006 TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
1007
1008 ignored_specify_item_opt:
1009 ignored_specify_item_opt ignored_specify_item |
1010 ignored_specify_item ;
1011
1012 ignored_specify_item:
1013 specparam_declaration
1014 // | pulsestyle_declaration
1015 // | showcancelled_declaration
1016 | path_declaration
1017 | system_timing_declaration
1018 ;
1019
1020 specparam_declaration:
1021 TOK_SPECPARAM list_of_specparam_assignments ';' |
1022 TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ;
1023
1024 // IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match
1025 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
1026 // exxxxtending this for SV specparam would change this anyhow
1027 specparam_range:
1028 '[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
1029
1030 list_of_specparam_assignments:
1031 specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
1032
1033 specparam_assignment:
1034 ignspec_id '=' constant_mintypmax_expression ;
1035
1036 ignspec_opt_cond:
1037 TOK_IF '(' ignspec_expr ')' | /* empty */;
1038
1039 path_declaration :
1040 simple_path_declaration ';'
1041 // | edge_sensitive_path_declaration
1042 // | state_dependent_path_declaration
1043 ;
1044
1045 simple_path_declaration :
1046 ignspec_opt_cond parallel_path_description '=' path_delay_value |
1047 ignspec_opt_cond full_path_description '=' path_delay_value
1048 ;
1049
1050 path_delay_value :
1051 '(' path_delay_expression list_of_path_delay_extra_expressions ')'
1052 | path_delay_expression
1053 | path_delay_expression list_of_path_delay_extra_expressions
1054 ;
1055
1056 list_of_path_delay_extra_expressions :
1057 ',' path_delay_expression | ',' path_delay_expression list_of_path_delay_extra_expressions;
1058
1059 specify_edge_identifier :
1060 TOK_POSEDGE | TOK_NEGEDGE ;
1061
1062 parallel_path_description :
1063 '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
1064 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
1065 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
1066
1067 full_path_description :
1068 '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
1069 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
1070 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
1071
1072 // This was broken into 2 rules to solve shift/reduce conflicts
1073 list_of_path_inputs :
1074 specify_input_terminal_descriptor opt_polarity_operator |
1075 specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
1076
1077 more_path_inputs :
1078 ',' specify_input_terminal_descriptor |
1079 more_path_inputs ',' specify_input_terminal_descriptor ;
1080
1081 list_of_path_outputs :
1082 specify_output_terminal_descriptor |
1083 list_of_path_outputs ',' specify_output_terminal_descriptor ;
1084
1085 opt_polarity_operator :
1086 '+'
1087 | '-'
1088 | ;
1089
1090 // Good enough for the time being
1091 specify_input_terminal_descriptor :
1092 ignspec_id ;
1093
1094 // Good enough for the time being
1095 specify_output_terminal_descriptor :
1096 ignspec_id ;
1097
1098 system_timing_declaration :
1099 ignspec_id '(' system_timing_args ')' ';' ;
1100
1101 system_timing_arg :
1102 TOK_POSEDGE ignspec_id |
1103 TOK_NEGEDGE ignspec_id |
1104 ignspec_expr ;
1105
1106 system_timing_args :
1107 system_timing_arg |
1108 system_timing_args ',' system_timing_arg ;
1109
1110 path_delay_expression :
1111 ignspec_constant_expression;
1112
1113 constant_mintypmax_expression :
1114 ignspec_constant_expression
1115 | ignspec_constant_expression ':' ignspec_constant_expression ':' ignspec_constant_expression
1116 ;
1117
1118 // for the time being this is OK, but we may write our own expr here.
1119 // as I'm not sure it is legal to use a full expr here (probably not)
1120 // On the other hand, other rules requiring constant expressions also use 'expr'
1121 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
1122 ignspec_constant_expression:
1123 expr { delete $1; };
1124
1125 ignspec_expr:
1126 expr { delete $1; };
1127
1128 ignspec_id:
1129 TOK_ID { delete $1; };
1130
1131 /**********************************************************************/
1132
1133 param_signed:
1134 TOK_SIGNED {
1135 astbuf1->is_signed = true;
1136 } | /* empty */;
1137
1138 param_integer:
1139 TOK_INTEGER {
1140 if (astbuf1->children.size() != 1)
1141 frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
1142 astbuf1->children.push_back(new AstNode(AST_RANGE));
1143 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
1144 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
1145 astbuf1->is_signed = true;
1146 } | /* empty */;
1147
1148 param_real:
1149 TOK_REAL {
1150 if (astbuf1->children.size() != 1)
1151 frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
1152 astbuf1->children.push_back(new AstNode(AST_REALVALUE));
1153 } | /* empty */;
1154
1155 param_range:
1156 range {
1157 if ($1 != NULL) {
1158 if (astbuf1->children.size() != 1)
1159 frontend_verilog_yyerror("integer/real parameters should not have a range.");
1160 astbuf1->children.push_back($1);
1161 }
1162 };
1163
1164 param_type:
1165 param_signed param_integer param_real param_range |
1166 hierarchical_type_id {
1167 astbuf1->is_custom_type = true;
1168 astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
1169 astbuf1->children.back()->str = *$1;
1170 };
1171
1172 param_decl:
1173 attr TOK_PARAMETER {
1174 astbuf1 = new AstNode(AST_PARAMETER);
1175 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1176 append_attr(astbuf1, $1);
1177 } param_type param_decl_list ';' {
1178 delete astbuf1;
1179 };
1180
1181 localparam_decl:
1182 attr TOK_LOCALPARAM {
1183 astbuf1 = new AstNode(AST_LOCALPARAM);
1184 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1185 append_attr(astbuf1, $1);
1186 } param_type param_decl_list ';' {
1187 delete astbuf1;
1188 };
1189
1190 param_decl_list:
1191 single_param_decl | param_decl_list ',' single_param_decl;
1192
1193 single_param_decl:
1194 TOK_ID '=' expr {
1195 AstNode *node;
1196 if (astbuf1 == nullptr) {
1197 if (!sv_mode)
1198 frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword");
1199 node = new AstNode(AST_PARAMETER);
1200 node->children.push_back(AstNode::mkconst_int(0, true));
1201 } else {
1202 node = astbuf1->clone();
1203 }
1204 node->str = *$1;
1205 delete node->children[0];
1206 node->children[0] = $3;
1207 ast_stack.back()->children.push_back(node);
1208 delete $1;
1209 };
1210
1211 defparam_decl:
1212 TOK_DEFPARAM defparam_decl_list ';';
1213
1214 defparam_decl_list:
1215 single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
1216
1217 single_defparam_decl:
1218 range rvalue '=' expr {
1219 AstNode *node = new AstNode(AST_DEFPARAM);
1220 node->children.push_back($2);
1221 node->children.push_back($4);
1222 if ($1 != NULL)
1223 node->children.push_back($1);
1224 ast_stack.back()->children.push_back(node);
1225 };
1226
1227 wire_decl:
1228 attr wire_type range {
1229 albuf = $1;
1230 astbuf1 = $2;
1231 astbuf2 = $3;
1232 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
1233 if (astbuf2) {
1234 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
1235 } else {
1236 astbuf2 = new AstNode(AST_RANGE);
1237 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
1238 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
1239 }
1240 }
1241 if (astbuf2 && astbuf2->children.size() != 2)
1242 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
1243 } delay wire_name_list {
1244 delete astbuf1;
1245 if (astbuf2 != NULL)
1246 delete astbuf2;
1247 free_attr(albuf);
1248 } ';' |
1249 attr TOK_SUPPLY0 TOK_ID {
1250 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1251 ast_stack.back()->children.back()->str = *$3;
1252 append_attr(ast_stack.back()->children.back(), $1);
1253 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
1254 ast_stack.back()->children.back()->children[0]->str = *$3;
1255 delete $3;
1256 } opt_supply_wires ';' |
1257 attr TOK_SUPPLY1 TOK_ID {
1258 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1259 ast_stack.back()->children.back()->str = *$3;
1260 append_attr(ast_stack.back()->children.back(), $1);
1261 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
1262 ast_stack.back()->children.back()->children[0]->str = *$3;
1263 delete $3;
1264 } opt_supply_wires ';';
1265
1266 opt_supply_wires:
1267 /* empty */ |
1268 opt_supply_wires ',' TOK_ID {
1269 AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
1270 AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
1271 wire_node->str = *$3;
1272 assign_node->children[0]->str = *$3;
1273 ast_stack.back()->children.push_back(wire_node);
1274 ast_stack.back()->children.push_back(assign_node);
1275 delete $3;
1276 };
1277
1278 wire_name_list:
1279 wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
1280
1281 wire_name_and_opt_assign:
1282 wire_name {
1283 bool attr_anyconst = false;
1284 bool attr_anyseq = false;
1285 bool attr_allconst = false;
1286 bool attr_allseq = false;
1287 if (ast_stack.back()->children.back()->get_bool_attribute("\\anyconst")) {
1288 delete ast_stack.back()->children.back()->attributes.at("\\anyconst");
1289 ast_stack.back()->children.back()->attributes.erase("\\anyconst");
1290 attr_anyconst = true;
1291 }
1292 if (ast_stack.back()->children.back()->get_bool_attribute("\\anyseq")) {
1293 delete ast_stack.back()->children.back()->attributes.at("\\anyseq");
1294 ast_stack.back()->children.back()->attributes.erase("\\anyseq");
1295 attr_anyseq = true;
1296 }
1297 if (ast_stack.back()->children.back()->get_bool_attribute("\\allconst")) {
1298 delete ast_stack.back()->children.back()->attributes.at("\\allconst");
1299 ast_stack.back()->children.back()->attributes.erase("\\allconst");
1300 attr_allconst = true;
1301 }
1302 if (ast_stack.back()->children.back()->get_bool_attribute("\\allseq")) {
1303 delete ast_stack.back()->children.back()->attributes.at("\\allseq");
1304 ast_stack.back()->children.back()->attributes.erase("\\allseq");
1305 attr_allseq = true;
1306 }
1307 if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
1308 AstNode *wire = new AstNode(AST_IDENTIFIER);
1309 AstNode *fcall = new AstNode(AST_FCALL);
1310 wire->str = ast_stack.back()->children.back()->str;
1311 fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
1312 if (attr_anyconst)
1313 fcall->str = "\\$anyconst";
1314 if (attr_anyseq)
1315 fcall->str = "\\$anyseq";
1316 if (attr_allconst)
1317 fcall->str = "\\$allconst";
1318 if (attr_allseq)
1319 fcall->str = "\\$allseq";
1320 fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
1321 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
1322 }
1323 } |
1324 wire_name '=' expr {
1325 AstNode *wire = new AstNode(AST_IDENTIFIER);
1326 wire->str = ast_stack.back()->children.back()->str;
1327 if (astbuf1->is_input) {
1328 if (astbuf1->attributes.count("\\defaultvalue"))
1329 delete astbuf1->attributes.at("\\defaultvalue");
1330 astbuf1->attributes["\\defaultvalue"] = $3;
1331 } else
1332 if (astbuf1->is_reg || astbuf1->is_logic)
1333 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $3))));
1334 else
1335 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3));
1336 };
1337
1338 wire_name:
1339 TOK_ID range_or_multirange {
1340 if (astbuf1 == nullptr)
1341 frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node.");
1342 AstNode *node = astbuf1->clone();
1343 node->str = *$1;
1344 append_attr_clone(node, albuf);
1345 if (astbuf2 != NULL)
1346 node->children.push_back(astbuf2->clone());
1347 if ($2 != NULL) {
1348 if (node->is_input || node->is_output)
1349 frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
1350 if (!astbuf2 && !node->is_custom_type) {
1351 AstNode *rng = new AstNode(AST_RANGE);
1352 rng->children.push_back(AstNode::mkconst_int(0, true));
1353 rng->children.push_back(AstNode::mkconst_int(0, true));
1354 node->children.push_back(rng);
1355 }
1356 node->type = AST_MEMORY;
1357 auto *rangeNode = $2;
1358 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
1359 // SV array size [n], rewrite as [n-1:0]
1360 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
1361 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
1362 }
1363 node->children.push_back(rangeNode);
1364 }
1365 if (current_function_or_task == NULL) {
1366 if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
1367 port_stubs[*$1] = ++port_counter;
1368 }
1369 if (port_stubs.count(*$1) != 0) {
1370 if (!node->is_input && !node->is_output)
1371 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
1372 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
1373 frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
1374 node->port_id = port_stubs[*$1];
1375 port_stubs.erase(*$1);
1376 } else {
1377 if (node->is_input || node->is_output)
1378 frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
1379 }
1380 } else {
1381 if (node->is_input || node->is_output)
1382 node->port_id = current_function_or_task_port_id++;
1383 }
1384 ast_stack.back()->children.push_back(node);
1385
1386 delete $1;
1387 };
1388
1389 assign_stmt:
1390 TOK_ASSIGN delay assign_expr_list ';';
1391
1392 assign_expr_list:
1393 assign_expr | assign_expr_list ',' assign_expr;
1394
1395 assign_expr:
1396 lvalue '=' expr {
1397 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, $1, $3));
1398 };
1399
1400 typedef_decl:
1401 TOK_TYPEDEF wire_type range TOK_ID range_or_multirange ';' {
1402 astbuf1 = $2;
1403 astbuf2 = $3;
1404 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
1405 if (astbuf2) {
1406 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
1407 } else {
1408 astbuf2 = new AstNode(AST_RANGE);
1409 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
1410 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
1411 }
1412 }
1413 if (astbuf2 && astbuf2->children.size() != 2)
1414 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
1415 if (astbuf2)
1416 astbuf1->children.push_back(astbuf2);
1417
1418 if ($5 != NULL) {
1419 if (!astbuf2) {
1420 AstNode *rng = new AstNode(AST_RANGE);
1421 rng->children.push_back(AstNode::mkconst_int(0, true));
1422 rng->children.push_back(AstNode::mkconst_int(0, true));
1423 astbuf1->children.push_back(rng);
1424 }
1425 astbuf1->type = AST_MEMORY;
1426 auto *rangeNode = $5;
1427 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
1428 // SV array size [n], rewrite as [n-1:0]
1429 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
1430 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
1431 }
1432 astbuf1->children.push_back(rangeNode);
1433 }
1434
1435 ast_stack.back()->children.push_back(new AstNode(AST_TYPEDEF, astbuf1));
1436 ast_stack.back()->children.back()->str = *$4;
1437 };
1438
1439 cell_stmt:
1440 attr TOK_ID {
1441 astbuf1 = new AstNode(AST_CELL);
1442 append_attr(astbuf1, $1);
1443 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
1444 astbuf1->children[0]->str = *$2;
1445 delete $2;
1446 } cell_parameter_list_opt cell_list ';' {
1447 delete astbuf1;
1448 } |
1449 attr tok_prim_wrapper delay {
1450 astbuf1 = new AstNode(AST_PRIMITIVE);
1451 astbuf1->str = *$2;
1452 append_attr(astbuf1, $1);
1453 delete $2;
1454 } prim_list ';' {
1455 delete astbuf1;
1456 };
1457
1458 tok_prim_wrapper:
1459 TOK_PRIMITIVE {
1460 $$ = $1;
1461 } |
1462 TOK_OR {
1463 $$ = new std::string("or");
1464 };
1465
1466 cell_list:
1467 single_cell |
1468 cell_list ',' single_cell;
1469
1470 single_cell:
1471 TOK_ID {
1472 astbuf2 = astbuf1->clone();
1473 if (astbuf2->type != AST_PRIMITIVE)
1474 astbuf2->str = *$1;
1475 delete $1;
1476 ast_stack.back()->children.push_back(astbuf2);
1477 } '(' cell_port_list ')' |
1478 TOK_ID non_opt_range {
1479 astbuf2 = astbuf1->clone();
1480 if (astbuf2->type != AST_PRIMITIVE)
1481 astbuf2->str = *$1;
1482 delete $1;
1483 ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
1484 } '(' cell_port_list ')';
1485
1486 prim_list:
1487 single_prim |
1488 prim_list ',' single_prim;
1489
1490 single_prim:
1491 single_cell |
1492 /* no name */ {
1493 astbuf2 = astbuf1->clone();
1494 ast_stack.back()->children.push_back(astbuf2);
1495 } '(' cell_port_list ')';
1496
1497 cell_parameter_list_opt:
1498 '#' '(' cell_parameter_list ')' | /* empty */;
1499
1500 cell_parameter_list:
1501 cell_parameter | cell_parameter_list ',' cell_parameter;
1502
1503 cell_parameter:
1504 /* empty */ |
1505 expr {
1506 AstNode *node = new AstNode(AST_PARASET);
1507 astbuf1->children.push_back(node);
1508 node->children.push_back($1);
1509 } |
1510 '.' TOK_ID '(' expr ')' {
1511 AstNode *node = new AstNode(AST_PARASET);
1512 node->str = *$2;
1513 astbuf1->children.push_back(node);
1514 node->children.push_back($4);
1515 delete $2;
1516 };
1517
1518 cell_port_list:
1519 cell_port_list_rules {
1520 // remove empty args from end of list
1521 while (!astbuf2->children.empty()) {
1522 AstNode *node = astbuf2->children.back();
1523 if (node->type != AST_ARGUMENT) break;
1524 if (!node->children.empty()) break;
1525 if (!node->str.empty()) break;
1526 astbuf2->children.pop_back();
1527 delete node;
1528 }
1529
1530 // check port types
1531 bool has_positional_args = false;
1532 bool has_named_args = false;
1533 for (auto node : astbuf2->children) {
1534 if (node->type != AST_ARGUMENT) continue;
1535 if (node->str.empty())
1536 has_positional_args = true;
1537 else
1538 has_named_args = true;
1539 }
1540
1541 if (has_positional_args && has_named_args)
1542 frontend_verilog_yyerror("Mix of positional and named cell ports.");
1543 };
1544
1545 cell_port_list_rules:
1546 cell_port | cell_port_list_rules ',' cell_port;
1547
1548 cell_port:
1549 attr {
1550 AstNode *node = new AstNode(AST_ARGUMENT);
1551 astbuf2->children.push_back(node);
1552 free_attr($1);
1553 } |
1554 attr expr {
1555 AstNode *node = new AstNode(AST_ARGUMENT);
1556 astbuf2->children.push_back(node);
1557 node->children.push_back($2);
1558 free_attr($1);
1559 } |
1560 attr '.' TOK_ID '(' expr ')' {
1561 AstNode *node = new AstNode(AST_ARGUMENT);
1562 node->str = *$3;
1563 astbuf2->children.push_back(node);
1564 node->children.push_back($5);
1565 delete $3;
1566 free_attr($1);
1567 } |
1568 attr '.' TOK_ID '(' ')' {
1569 AstNode *node = new AstNode(AST_ARGUMENT);
1570 node->str = *$3;
1571 astbuf2->children.push_back(node);
1572 delete $3;
1573 free_attr($1);
1574 } |
1575 attr '.' TOK_ID {
1576 AstNode *node = new AstNode(AST_ARGUMENT);
1577 node->str = *$3;
1578 astbuf2->children.push_back(node);
1579 node->children.push_back(new AstNode(AST_IDENTIFIER));
1580 node->children.back()->str = *$3;
1581 delete $3;
1582 free_attr($1);
1583 };
1584
1585 always_comb_or_latch:
1586 TOK_ALWAYS_COMB {
1587 $$ = false;
1588 } |
1589 TOK_ALWAYS_LATCH {
1590 $$ = true;
1591 };
1592
1593 always_or_always_ff:
1594 TOK_ALWAYS {
1595 $$ = false;
1596 } |
1597 TOK_ALWAYS_FF {
1598 $$ = true;
1599 };
1600
1601 always_stmt:
1602 attr always_or_always_ff {
1603 AstNode *node = new AstNode(AST_ALWAYS);
1604 append_attr(node, $1);
1605 if ($2)
1606 node->attributes[ID(always_ff)] = AstNode::mkconst_int(1, false);
1607 ast_stack.back()->children.push_back(node);
1608 ast_stack.push_back(node);
1609 } always_cond {
1610 AstNode *block = new AstNode(AST_BLOCK);
1611 ast_stack.back()->children.push_back(block);
1612 ast_stack.push_back(block);
1613 } behavioral_stmt {
1614 ast_stack.pop_back();
1615 ast_stack.pop_back();
1616 } |
1617 attr always_comb_or_latch {
1618 AstNode *node = new AstNode(AST_ALWAYS);
1619 append_attr(node, $1);
1620 if ($2)
1621 node->attributes[ID(always_latch)] = AstNode::mkconst_int(1, false);
1622 else
1623 node->attributes[ID(always_comb)] = AstNode::mkconst_int(1, false);
1624 ast_stack.back()->children.push_back(node);
1625 ast_stack.push_back(node);
1626 AstNode *block = new AstNode(AST_BLOCK);
1627 ast_stack.back()->children.push_back(block);
1628 ast_stack.push_back(block);
1629 } behavioral_stmt {
1630 ast_stack.pop_back();
1631 ast_stack.pop_back();
1632 } |
1633 attr TOK_INITIAL {
1634 AstNode *node = new AstNode(AST_INITIAL);
1635 append_attr(node, $1);
1636 ast_stack.back()->children.push_back(node);
1637 ast_stack.push_back(node);
1638 AstNode *block = new AstNode(AST_BLOCK);
1639 ast_stack.back()->children.push_back(block);
1640 ast_stack.push_back(block);
1641 } behavioral_stmt {
1642 ast_stack.pop_back();
1643 ast_stack.pop_back();
1644 };
1645
1646 always_cond:
1647 '@' '(' always_events ')' |
1648 '@' '(' '*' ')' |
1649 '@' ATTR_BEGIN ')' |
1650 '@' '(' ATTR_END |
1651 '@' '*' |
1652 /* empty */;
1653
1654 always_events:
1655 always_event |
1656 always_events TOK_OR always_event |
1657 always_events ',' always_event;
1658
1659 always_event:
1660 TOK_POSEDGE expr {
1661 AstNode *node = new AstNode(AST_POSEDGE);
1662 ast_stack.back()->children.push_back(node);
1663 node->children.push_back($2);
1664 } |
1665 TOK_NEGEDGE expr {
1666 AstNode *node = new AstNode(AST_NEGEDGE);
1667 ast_stack.back()->children.push_back(node);
1668 node->children.push_back($2);
1669 } |
1670 expr {
1671 AstNode *node = new AstNode(AST_EDGE);
1672 ast_stack.back()->children.push_back(node);
1673 node->children.push_back($1);
1674 };
1675
1676 opt_label:
1677 ':' TOK_ID {
1678 $$ = $2;
1679 } |
1680 /* empty */ {
1681 $$ = NULL;
1682 };
1683
1684 opt_sva_label:
1685 TOK_SVA_LABEL ':' {
1686 $$ = $1;
1687 } |
1688 /* empty */ {
1689 $$ = NULL;
1690 };
1691
1692 opt_property:
1693 TOK_PROPERTY {
1694 $$ = true;
1695 } |
1696 TOK_FINAL {
1697 $$ = false;
1698 } |
1699 /* empty */ {
1700 $$ = false;
1701 };
1702
1703 modport_stmt:
1704 TOK_MODPORT TOK_ID {
1705 AstNode *modport = new AstNode(AST_MODPORT);
1706 ast_stack.back()->children.push_back(modport);
1707 ast_stack.push_back(modport);
1708 modport->str = *$2;
1709 delete $2;
1710 } modport_args_opt {
1711 ast_stack.pop_back();
1712 log_assert(ast_stack.size() == 2);
1713 } ';'
1714
1715 modport_args_opt:
1716 '(' ')' | '(' modport_args optional_comma ')';
1717
1718 modport_args:
1719 modport_arg | modport_args ',' modport_arg;
1720
1721 modport_arg:
1722 modport_type_token modport_member |
1723 modport_member
1724
1725 modport_member:
1726 TOK_ID {
1727 AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
1728 ast_stack.back()->children.push_back(modport_member);
1729 modport_member->str = *$1;
1730 modport_member->is_input = current_modport_input;
1731 modport_member->is_output = current_modport_output;
1732 delete $1;
1733 }
1734
1735 modport_type_token:
1736 TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
1737
1738 assert:
1739 opt_sva_label TOK_ASSERT opt_property '(' expr ')' ';' {
1740 if (noassert_mode) {
1741 delete $5;
1742 } else {
1743 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
1744 if ($1 != nullptr)
1745 node->str = *$1;
1746 ast_stack.back()->children.push_back(node);
1747 }
1748 if ($1 != nullptr)
1749 delete $1;
1750 } |
1751 opt_sva_label TOK_ASSUME opt_property '(' expr ')' ';' {
1752 if (noassume_mode) {
1753 delete $5;
1754 } else {
1755 AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
1756 if ($1 != nullptr)
1757 node->str = *$1;
1758 ast_stack.back()->children.push_back(node);
1759 }
1760 if ($1 != nullptr)
1761 delete $1;
1762 } |
1763 opt_sva_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
1764 if (noassert_mode) {
1765 delete $6;
1766 } else {
1767 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
1768 if ($1 != nullptr)
1769 node->str = *$1;
1770 ast_stack.back()->children.push_back(node);
1771 }
1772 if ($1 != nullptr)
1773 delete $1;
1774 } |
1775 opt_sva_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
1776 if (noassume_mode) {
1777 delete $6;
1778 } else {
1779 AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
1780 if ($1 != nullptr)
1781 node->str = *$1;
1782 ast_stack.back()->children.push_back(node);
1783 }
1784 if ($1 != nullptr)
1785 delete $1;
1786 } |
1787 opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
1788 AstNode *node = new AstNode(AST_COVER, $5);
1789 if ($1 != nullptr) {
1790 node->str = *$1;
1791 delete $1;
1792 }
1793 ast_stack.back()->children.push_back(node);
1794 } |
1795 opt_sva_label TOK_COVER opt_property '(' ')' ';' {
1796 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
1797 if ($1 != nullptr) {
1798 node->str = *$1;
1799 delete $1;
1800 }
1801 ast_stack.back()->children.push_back(node);
1802 } |
1803 opt_sva_label TOK_COVER ';' {
1804 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
1805 if ($1 != nullptr) {
1806 node->str = *$1;
1807 delete $1;
1808 }
1809 ast_stack.back()->children.push_back(node);
1810 } |
1811 opt_sva_label TOK_RESTRICT opt_property '(' expr ')' ';' {
1812 if (norestrict_mode) {
1813 delete $5;
1814 } else {
1815 AstNode *node = new AstNode(AST_ASSUME, $5);
1816 if ($1 != nullptr)
1817 node->str = *$1;
1818 ast_stack.back()->children.push_back(node);
1819 }
1820 if (!$3)
1821 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
1822 if ($1 != nullptr)
1823 delete $1;
1824 } |
1825 opt_sva_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
1826 if (norestrict_mode) {
1827 delete $6;
1828 } else {
1829 AstNode *node = new AstNode(AST_FAIR, $6);
1830 if ($1 != nullptr)
1831 node->str = *$1;
1832 ast_stack.back()->children.push_back(node);
1833 }
1834 if (!$3)
1835 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
1836 if ($1 != nullptr)
1837 delete $1;
1838 };
1839
1840 assert_property:
1841 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
1842 ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5));
1843 if ($1 != nullptr) {
1844 ast_stack.back()->children.back()->str = *$1;
1845 delete $1;
1846 }
1847 } |
1848 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
1849 ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
1850 if ($1 != nullptr) {
1851 ast_stack.back()->children.back()->str = *$1;
1852 delete $1;
1853 }
1854 } |
1855 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
1856 ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6));
1857 if ($1 != nullptr) {
1858 ast_stack.back()->children.back()->str = *$1;
1859 delete $1;
1860 }
1861 } |
1862 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
1863 ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
1864 if ($1 != nullptr) {
1865 ast_stack.back()->children.back()->str = *$1;
1866 delete $1;
1867 }
1868 } |
1869 opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
1870 ast_stack.back()->children.push_back(new AstNode(AST_COVER, $5));
1871 if ($1 != nullptr) {
1872 ast_stack.back()->children.back()->str = *$1;
1873 delete $1;
1874 }
1875 } |
1876 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
1877 if (norestrict_mode) {
1878 delete $5;
1879 } else {
1880 ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
1881 if ($1 != nullptr) {
1882 ast_stack.back()->children.back()->str = *$1;
1883 delete $1;
1884 }
1885 }
1886 } |
1887 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
1888 if (norestrict_mode) {
1889 delete $6;
1890 } else {
1891 ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
1892 if ($1 != nullptr) {
1893 ast_stack.back()->children.back()->str = *$1;
1894 delete $1;
1895 }
1896 }
1897 };
1898
1899 simple_behavioral_stmt:
1900 lvalue '=' delay expr {
1901 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4);
1902 ast_stack.back()->children.push_back(node);
1903 } |
1904 lvalue TOK_INCREMENT {
1905 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true)));
1906 ast_stack.back()->children.push_back(node);
1907 } |
1908 lvalue TOK_DECREMENT {
1909 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true)));
1910 ast_stack.back()->children.push_back(node);
1911 } |
1912 lvalue OP_LE delay expr {
1913 AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4);
1914 ast_stack.back()->children.push_back(node);
1915 };
1916
1917 // this production creates the obligatory if-else shift/reduce conflict
1918 behavioral_stmt:
1919 defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
1920 non_opt_delay behavioral_stmt |
1921 simple_behavioral_stmt ';' | ';' |
1922 hierarchical_id attr {
1923 AstNode *node = new AstNode(AST_TCALL);
1924 node->str = *$1;
1925 delete $1;
1926 ast_stack.back()->children.push_back(node);
1927 ast_stack.push_back(node);
1928 append_attr(node, $2);
1929 } opt_arg_list ';'{
1930 ast_stack.pop_back();
1931 } |
1932 TOK_MSG_TASKS attr {
1933 AstNode *node = new AstNode(AST_TCALL);
1934 node->str = *$1;
1935 delete $1;
1936 ast_stack.back()->children.push_back(node);
1937 ast_stack.push_back(node);
1938 append_attr(node, $2);
1939 } opt_arg_list ';'{
1940 ast_stack.pop_back();
1941 } |
1942 attr TOK_BEGIN opt_label {
1943 AstNode *node = new AstNode(AST_BLOCK);
1944 ast_stack.back()->children.push_back(node);
1945 ast_stack.push_back(node);
1946 append_attr(node, $1);
1947 if ($3 != NULL)
1948 node->str = *$3;
1949 } behavioral_stmt_list TOK_END opt_label {
1950 if ($3 != NULL && $7 != NULL && *$3 != *$7)
1951 frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1);
1952 if ($3 != NULL)
1953 delete $3;
1954 if ($7 != NULL)
1955 delete $7;
1956 ast_stack.pop_back();
1957 } |
1958 attr TOK_FOR '(' {
1959 AstNode *node = new AstNode(AST_FOR);
1960 ast_stack.back()->children.push_back(node);
1961 ast_stack.push_back(node);
1962 append_attr(node, $1);
1963 } simple_behavioral_stmt ';' expr {
1964 ast_stack.back()->children.push_back($7);
1965 } ';' simple_behavioral_stmt ')' {
1966 AstNode *block = new AstNode(AST_BLOCK);
1967 ast_stack.back()->children.push_back(block);
1968 ast_stack.push_back(block);
1969 } behavioral_stmt {
1970 ast_stack.pop_back();
1971 ast_stack.pop_back();
1972 } |
1973 attr TOK_WHILE '(' expr ')' {
1974 AstNode *node = new AstNode(AST_WHILE);
1975 ast_stack.back()->children.push_back(node);
1976 ast_stack.push_back(node);
1977 append_attr(node, $1);
1978 AstNode *block = new AstNode(AST_BLOCK);
1979 ast_stack.back()->children.push_back($4);
1980 ast_stack.back()->children.push_back(block);
1981 ast_stack.push_back(block);
1982 } behavioral_stmt {
1983 ast_stack.pop_back();
1984 ast_stack.pop_back();
1985 } |
1986 attr TOK_REPEAT '(' expr ')' {
1987 AstNode *node = new AstNode(AST_REPEAT);
1988 ast_stack.back()->children.push_back(node);
1989 ast_stack.push_back(node);
1990 append_attr(node, $1);
1991 AstNode *block = new AstNode(AST_BLOCK);
1992 ast_stack.back()->children.push_back($4);
1993 ast_stack.back()->children.push_back(block);
1994 ast_stack.push_back(block);
1995 } behavioral_stmt {
1996 ast_stack.pop_back();
1997 ast_stack.pop_back();
1998 } |
1999 attr TOK_IF '(' expr ')' {
2000 AstNode *node = new AstNode(AST_CASE);
2001 AstNode *block = new AstNode(AST_BLOCK);
2002 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
2003 ast_stack.back()->children.push_back(node);
2004 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
2005 node->children.push_back(cond);
2006 ast_stack.push_back(node);
2007 ast_stack.push_back(block);
2008 append_attr(node, $1);
2009 } behavioral_stmt optional_else {
2010 ast_stack.pop_back();
2011 ast_stack.pop_back();
2012 } |
2013 case_attr case_type '(' expr ')' {
2014 AstNode *node = new AstNode(AST_CASE, $4);
2015 ast_stack.back()->children.push_back(node);
2016 ast_stack.push_back(node);
2017 append_attr(node, $1);
2018 } opt_synopsys_attr case_body TOK_ENDCASE {
2019 case_type_stack.pop_back();
2020 ast_stack.pop_back();
2021 };
2022
2023 unique_case_attr:
2024 /* empty */ {
2025 $$ = false;
2026 } |
2027 TOK_PRIORITY case_attr {
2028 $$ = $2;
2029 } |
2030 TOK_UNIQUE case_attr {
2031 $$ = true;
2032 };
2033
2034 case_attr:
2035 attr unique_case_attr {
2036 if ($2) (*$1)["\\parallel_case"] = AstNode::mkconst_int(1, false);
2037 $$ = $1;
2038 };
2039
2040 case_type:
2041 TOK_CASE {
2042 case_type_stack.push_back(0);
2043 } |
2044 TOK_CASEX {
2045 case_type_stack.push_back('x');
2046 } |
2047 TOK_CASEZ {
2048 case_type_stack.push_back('z');
2049 };
2050
2051 opt_synopsys_attr:
2052 opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
2053 if (ast_stack.back()->attributes.count("\\full_case") == 0)
2054 ast_stack.back()->attributes["\\full_case"] = AstNode::mkconst_int(1, false);
2055 } |
2056 opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
2057 if (ast_stack.back()->attributes.count("\\parallel_case") == 0)
2058 ast_stack.back()->attributes["\\parallel_case"] = AstNode::mkconst_int(1, false);
2059 } |
2060 /* empty */;
2061
2062 behavioral_stmt_list:
2063 behavioral_stmt_list behavioral_stmt |
2064 /* empty */;
2065
2066 optional_else:
2067 TOK_ELSE {
2068 AstNode *block = new AstNode(AST_BLOCK);
2069 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
2070 ast_stack.pop_back();
2071 ast_stack.back()->children.push_back(cond);
2072 ast_stack.push_back(block);
2073 } behavioral_stmt |
2074 /* empty */ %prec FAKE_THEN;
2075
2076 case_body:
2077 case_body case_item |
2078 /* empty */;
2079
2080 case_item:
2081 {
2082 AstNode *node = new AstNode(
2083 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2084 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2085 ast_stack.back()->children.push_back(node);
2086 ast_stack.push_back(node);
2087 } case_select {
2088 AstNode *block = new AstNode(AST_BLOCK);
2089 ast_stack.back()->children.push_back(block);
2090 ast_stack.push_back(block);
2091 case_type_stack.push_back(0);
2092 } behavioral_stmt {
2093 case_type_stack.pop_back();
2094 ast_stack.pop_back();
2095 ast_stack.pop_back();
2096 };
2097
2098 gen_case_body:
2099 gen_case_body gen_case_item |
2100 /* empty */;
2101
2102 gen_case_item:
2103 {
2104 AstNode *node = new AstNode(
2105 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2106 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2107 ast_stack.back()->children.push_back(node);
2108 ast_stack.push_back(node);
2109 } case_select {
2110 case_type_stack.push_back(0);
2111 } gen_stmt_or_null {
2112 case_type_stack.pop_back();
2113 ast_stack.pop_back();
2114 };
2115
2116 case_select:
2117 case_expr_list ':' |
2118 TOK_DEFAULT;
2119
2120 case_expr_list:
2121 TOK_DEFAULT {
2122 ast_stack.back()->children.push_back(new AstNode(AST_DEFAULT));
2123 } |
2124 TOK_SVA_LABEL {
2125 ast_stack.back()->children.push_back(new AstNode(AST_IDENTIFIER));
2126 ast_stack.back()->children.back()->str = *$1;
2127 delete $1;
2128 } |
2129 expr {
2130 ast_stack.back()->children.push_back($1);
2131 } |
2132 case_expr_list ',' expr {
2133 ast_stack.back()->children.push_back($3);
2134 };
2135
2136 rvalue:
2137 hierarchical_id '[' expr ']' '.' rvalue {
2138 $$ = new AstNode(AST_PREFIX, $3, $6);
2139 $$->str = *$1;
2140 delete $1;
2141 } |
2142 hierarchical_id range {
2143 $$ = new AstNode(AST_IDENTIFIER, $2);
2144 $$->str = *$1;
2145 delete $1;
2146 if ($2 == nullptr && ($$->str == "\\$initstate" ||
2147 $$->str == "\\$anyconst" || $$->str == "\\$anyseq" ||
2148 $$->str == "\\$allconst" || $$->str == "\\$allseq"))
2149 $$->type = AST_FCALL;
2150 } |
2151 hierarchical_id non_opt_multirange {
2152 $$ = new AstNode(AST_IDENTIFIER, $2);
2153 $$->str = *$1;
2154 delete $1;
2155 };
2156
2157 lvalue:
2158 rvalue {
2159 $$ = $1;
2160 } |
2161 '{' lvalue_concat_list '}' {
2162 $$ = $2;
2163 };
2164
2165 lvalue_concat_list:
2166 expr {
2167 $$ = new AstNode(AST_CONCAT);
2168 $$->children.push_back($1);
2169 } |
2170 expr ',' lvalue_concat_list {
2171 $$ = $3;
2172 $$->children.push_back($1);
2173 };
2174
2175 opt_arg_list:
2176 '(' arg_list optional_comma ')' |
2177 /* empty */;
2178
2179 arg_list:
2180 arg_list2 |
2181 /* empty */;
2182
2183 arg_list2:
2184 single_arg |
2185 arg_list ',' single_arg;
2186
2187 single_arg:
2188 expr {
2189 ast_stack.back()->children.push_back($1);
2190 };
2191
2192 module_gen_body:
2193 module_gen_body gen_stmt_or_module_body_stmt |
2194 /* empty */;
2195
2196 gen_stmt_or_module_body_stmt:
2197 gen_stmt | module_body_stmt;
2198
2199 // this production creates the obligatory if-else shift/reduce conflict
2200 gen_stmt:
2201 TOK_FOR '(' {
2202 AstNode *node = new AstNode(AST_GENFOR);
2203 ast_stack.back()->children.push_back(node);
2204 ast_stack.push_back(node);
2205 } simple_behavioral_stmt ';' expr {
2206 ast_stack.back()->children.push_back($6);
2207 } ';' simple_behavioral_stmt ')' gen_stmt_block {
2208 ast_stack.pop_back();
2209 } |
2210 TOK_IF '(' expr ')' {
2211 AstNode *node = new AstNode(AST_GENIF);
2212 ast_stack.back()->children.push_back(node);
2213 ast_stack.push_back(node);
2214 ast_stack.back()->children.push_back($3);
2215 } gen_stmt_block opt_gen_else {
2216 ast_stack.pop_back();
2217 } |
2218 case_type '(' expr ')' {
2219 AstNode *node = new AstNode(AST_GENCASE, $3);
2220 ast_stack.back()->children.push_back(node);
2221 ast_stack.push_back(node);
2222 } gen_case_body TOK_ENDCASE {
2223 case_type_stack.pop_back();
2224 ast_stack.pop_back();
2225 } |
2226 TOK_BEGIN opt_label {
2227 AstNode *node = new AstNode(AST_GENBLOCK);
2228 node->str = $2 ? *$2 : std::string();
2229 ast_stack.back()->children.push_back(node);
2230 ast_stack.push_back(node);
2231 } module_gen_body TOK_END opt_label {
2232 if ($2 != NULL)
2233 delete $2;
2234 if ($6 != NULL)
2235 delete $6;
2236 ast_stack.pop_back();
2237 } |
2238 TOK_MSG_TASKS {
2239 AstNode *node = new AstNode(AST_TECALL);
2240 node->str = *$1;
2241 delete $1;
2242 ast_stack.back()->children.push_back(node);
2243 ast_stack.push_back(node);
2244 } opt_arg_list ';'{
2245 ast_stack.pop_back();
2246 };
2247
2248 gen_stmt_block:
2249 {
2250 AstNode *node = new AstNode(AST_GENBLOCK);
2251 ast_stack.back()->children.push_back(node);
2252 ast_stack.push_back(node);
2253 } gen_stmt_or_module_body_stmt {
2254 ast_stack.pop_back();
2255 };
2256
2257 gen_stmt_or_null:
2258 gen_stmt_block | ';';
2259
2260 opt_gen_else:
2261 TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
2262
2263 expr:
2264 basic_expr {
2265 $$ = $1;
2266 } |
2267 basic_expr '?' attr expr ':' expr {
2268 $$ = new AstNode(AST_TERNARY);
2269 $$->children.push_back($1);
2270 $$->children.push_back($4);
2271 $$->children.push_back($6);
2272 append_attr($$, $3);
2273 };
2274
2275 basic_expr:
2276 rvalue {
2277 $$ = $1;
2278 } |
2279 '(' expr ')' TOK_CONSTVAL {
2280 if ($4->compare(0, 1, "'") != 0)
2281 frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
2282 AstNode *bits = $2;
2283 AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2284 if (val == NULL)
2285 log_error("Value conversion failed: `%s'\n", $4->c_str());
2286 $$ = new AstNode(AST_TO_BITS, bits, val);
2287 delete $4;
2288 } |
2289 hierarchical_id TOK_CONSTVAL {
2290 if ($2->compare(0, 1, "'") != 0)
2291 frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
2292 AstNode *bits = new AstNode(AST_IDENTIFIER);
2293 bits->str = *$1;
2294 AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2295 if (val == NULL)
2296 log_error("Value conversion failed: `%s'\n", $2->c_str());
2297 $$ = new AstNode(AST_TO_BITS, bits, val);
2298 delete $1;
2299 delete $2;
2300 } |
2301 TOK_CONSTVAL TOK_CONSTVAL {
2302 $$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2303 if ($$ == NULL || (*$2)[0] != '\'')
2304 log_error("Value conversion failed: `%s%s'\n", $1->c_str(), $2->c_str());
2305 delete $1;
2306 delete $2;
2307 } |
2308 TOK_CONSTVAL {
2309 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2310 if ($$ == NULL)
2311 log_error("Value conversion failed: `%s'\n", $1->c_str());
2312 delete $1;
2313 } |
2314 TOK_REALVAL {
2315 $$ = new AstNode(AST_REALVALUE);
2316 char *p = (char*)malloc(GetSize(*$1) + 1), *q;
2317 for (int i = 0, j = 0; j < GetSize(*$1); j++)
2318 if ((*$1)[j] != '_')
2319 p[i++] = (*$1)[j], p[i] = 0;
2320 $$->realvalue = strtod(p, &q);
2321 log_assert(*q == 0);
2322 delete $1;
2323 free(p);
2324 } |
2325 TOK_STRING {
2326 $$ = AstNode::mkconst_str(*$1);
2327 delete $1;
2328 } |
2329 hierarchical_id attr {
2330 AstNode *node = new AstNode(AST_FCALL);
2331 node->str = *$1;
2332 delete $1;
2333 ast_stack.push_back(node);
2334 append_attr(node, $2);
2335 } '(' arg_list optional_comma ')' {
2336 $$ = ast_stack.back();
2337 ast_stack.pop_back();
2338 } |
2339 TOK_TO_SIGNED attr '(' expr ')' {
2340 $$ = new AstNode(AST_TO_SIGNED, $4);
2341 append_attr($$, $2);
2342 } |
2343 TOK_TO_UNSIGNED attr '(' expr ')' {
2344 $$ = new AstNode(AST_TO_UNSIGNED, $4);
2345 append_attr($$, $2);
2346 } |
2347 '(' expr ')' {
2348 $$ = $2;
2349 } |
2350 '(' expr ':' expr ':' expr ')' {
2351 delete $2;
2352 $$ = $4;
2353 delete $6;
2354 } |
2355 '{' concat_list '}' {
2356 $$ = $2;
2357 } |
2358 '{' expr '{' concat_list '}' '}' {
2359 $$ = new AstNode(AST_REPLICATE, $2, $4);
2360 } |
2361 '~' attr basic_expr %prec UNARY_OPS {
2362 $$ = new AstNode(AST_BIT_NOT, $3);
2363 append_attr($$, $2);
2364 } |
2365 basic_expr '&' attr basic_expr {
2366 $$ = new AstNode(AST_BIT_AND, $1, $4);
2367 append_attr($$, $3);
2368 } |
2369 basic_expr OP_NAND attr basic_expr {
2370 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
2371 append_attr($$, $3);
2372 } |
2373 basic_expr '|' attr basic_expr {
2374 $$ = new AstNode(AST_BIT_OR, $1, $4);
2375 append_attr($$, $3);
2376 } |
2377 basic_expr OP_NOR attr basic_expr {
2378 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
2379 append_attr($$, $3);
2380 } |
2381 basic_expr '^' attr basic_expr {
2382 $$ = new AstNode(AST_BIT_XOR, $1, $4);
2383 append_attr($$, $3);
2384 } |
2385 basic_expr OP_XNOR attr basic_expr {
2386 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
2387 append_attr($$, $3);
2388 } |
2389 '&' attr basic_expr %prec UNARY_OPS {
2390 $$ = new AstNode(AST_REDUCE_AND, $3);
2391 append_attr($$, $2);
2392 } |
2393 OP_NAND attr basic_expr %prec UNARY_OPS {
2394 $$ = new AstNode(AST_REDUCE_AND, $3);
2395 append_attr($$, $2);
2396 $$ = new AstNode(AST_LOGIC_NOT, $$);
2397 } |
2398 '|' attr basic_expr %prec UNARY_OPS {
2399 $$ = new AstNode(AST_REDUCE_OR, $3);
2400 append_attr($$, $2);
2401 } |
2402 OP_NOR attr basic_expr %prec UNARY_OPS {
2403 $$ = new AstNode(AST_REDUCE_OR, $3);
2404 append_attr($$, $2);
2405 $$ = new AstNode(AST_LOGIC_NOT, $$);
2406 } |
2407 '^' attr basic_expr %prec UNARY_OPS {
2408 $$ = new AstNode(AST_REDUCE_XOR, $3);
2409 append_attr($$, $2);
2410 } |
2411 OP_XNOR attr basic_expr %prec UNARY_OPS {
2412 $$ = new AstNode(AST_REDUCE_XNOR, $3);
2413 append_attr($$, $2);
2414 } |
2415 basic_expr OP_SHL attr basic_expr {
2416 $$ = new AstNode(AST_SHIFT_LEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2417 append_attr($$, $3);
2418 } |
2419 basic_expr OP_SHR attr basic_expr {
2420 $$ = new AstNode(AST_SHIFT_RIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2421 append_attr($$, $3);
2422 } |
2423 basic_expr OP_SSHL attr basic_expr {
2424 $$ = new AstNode(AST_SHIFT_SLEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2425 append_attr($$, $3);
2426 } |
2427 basic_expr OP_SSHR attr basic_expr {
2428 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2429 append_attr($$, $3);
2430 } |
2431 basic_expr '<' attr basic_expr {
2432 $$ = new AstNode(AST_LT, $1, $4);
2433 append_attr($$, $3);
2434 } |
2435 basic_expr OP_LE attr basic_expr {
2436 $$ = new AstNode(AST_LE, $1, $4);
2437 append_attr($$, $3);
2438 } |
2439 basic_expr OP_EQ attr basic_expr {
2440 $$ = new AstNode(AST_EQ, $1, $4);
2441 append_attr($$, $3);
2442 } |
2443 basic_expr OP_NE attr basic_expr {
2444 $$ = new AstNode(AST_NE, $1, $4);
2445 append_attr($$, $3);
2446 } |
2447 basic_expr OP_EQX attr basic_expr {
2448 $$ = new AstNode(AST_EQX, $1, $4);
2449 append_attr($$, $3);
2450 } |
2451 basic_expr OP_NEX attr basic_expr {
2452 $$ = new AstNode(AST_NEX, $1, $4);
2453 append_attr($$, $3);
2454 } |
2455 basic_expr OP_GE attr basic_expr {
2456 $$ = new AstNode(AST_GE, $1, $4);
2457 append_attr($$, $3);
2458 } |
2459 basic_expr '>' attr basic_expr {
2460 $$ = new AstNode(AST_GT, $1, $4);
2461 append_attr($$, $3);
2462 } |
2463 basic_expr '+' attr basic_expr {
2464 $$ = new AstNode(AST_ADD, $1, $4);
2465 append_attr($$, $3);
2466 } |
2467 basic_expr '-' attr basic_expr {
2468 $$ = new AstNode(AST_SUB, $1, $4);
2469 append_attr($$, $3);
2470 } |
2471 basic_expr '*' attr basic_expr {
2472 $$ = new AstNode(AST_MUL, $1, $4);
2473 append_attr($$, $3);
2474 } |
2475 basic_expr '/' attr basic_expr {
2476 $$ = new AstNode(AST_DIV, $1, $4);
2477 append_attr($$, $3);
2478 } |
2479 basic_expr '%' attr basic_expr {
2480 $$ = new AstNode(AST_MOD, $1, $4);
2481 append_attr($$, $3);
2482 } |
2483 basic_expr OP_POW attr basic_expr {
2484 $$ = new AstNode(AST_POW, $1, $4);
2485 append_attr($$, $3);
2486 } |
2487 '+' attr basic_expr %prec UNARY_OPS {
2488 $$ = new AstNode(AST_POS, $3);
2489 append_attr($$, $2);
2490 } |
2491 '-' attr basic_expr %prec UNARY_OPS {
2492 $$ = new AstNode(AST_NEG, $3);
2493 append_attr($$, $2);
2494 } |
2495 basic_expr OP_LAND attr basic_expr {
2496 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
2497 append_attr($$, $3);
2498 } |
2499 basic_expr OP_LOR attr basic_expr {
2500 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
2501 append_attr($$, $3);
2502 } |
2503 '!' attr basic_expr %prec UNARY_OPS {
2504 $$ = new AstNode(AST_LOGIC_NOT, $3);
2505 append_attr($$, $2);
2506 };
2507
2508 concat_list:
2509 expr {
2510 $$ = new AstNode(AST_CONCAT, $1);
2511 } |
2512 expr ',' concat_list {
2513 $$ = $3;
2514 $$->children.push_back($1);
2515 };