2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The Verilog frontend.
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
29 * This is the actual bison parser for Verilog code. The AST ist created directly
30 * from the bison reduce functions here. Note that this code uses a few global
31 * variables to hold the state of the AST generator and therefore this parser is
39 #include "frontends/verilog/verilog_frontend.h"
40 #include "kernel/log.h"
44 using namespace VERILOG_FRONTEND;
47 namespace VERILOG_FRONTEND {
49 std::map<std::string, int> port_stubs;
50 std::map<std::string, AstNode*> attr_list, default_attr_list;
51 std::map<std::string, AstNode*> *albuf;
52 std::vector<AstNode*> ast_stack;
53 struct AstNode *astbuf1, *astbuf2, *astbuf3;
54 struct AstNode *current_function_or_task;
55 struct AstNode *current_ast, *current_ast_mod;
56 int current_function_or_task_port_id;
57 std::vector<char> case_type_stack;
58 bool do_not_require_port_stubs;
59 bool default_nettype_wire;
60 bool sv_mode, formal_mode, lib_mode;
61 bool norestrict_mode, assume_asserts_mode;
62 bool current_wire_rand, current_wire_const;
67 static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
69 for (auto &it : *al) {
70 if (ast->attributes.count(it.first) > 0)
71 delete ast->attributes[it.first];
72 ast->attributes[it.first] = it.second;
77 static void append_attr_clone(AstNode *ast, std::map<std::string, AstNode*> *al)
79 for (auto &it : *al) {
80 if (ast->attributes.count(it.first) > 0)
81 delete ast->attributes[it.first];
82 ast->attributes[it.first] = it.second->clone();
86 static void free_attr(std::map<std::string, AstNode*> *al)
95 %name-prefix "frontend_verilog_yy"
99 struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
100 std::map<std::string, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
104 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
105 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
106 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
107 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
108 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG
109 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
110 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
111 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR
112 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
113 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK
114 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
115 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
116 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
117 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME
118 %token TOK_RESTRICT TOK_COVER TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
119 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
120 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
122 %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
123 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
124 %type <string> opt_label tok_prim_wrapper hierarchical_id
125 %type <boolean> opt_signed unique_case_attr
126 %type <al> attr case_attr
128 // operator precedence from low to high
134 %left OP_EQ OP_NE OP_EQX OP_NEX
135 %left '<' OP_LE OP_GE '>'
136 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
142 %define parse.error verbose
143 %define parse.lac full
154 ast_stack.push_back(current_ast);
156 ast_stack.pop_back();
157 log_assert(GetSize(ast_stack) == 0);
158 for (auto &it : default_attr_list)
160 default_attr_list.clear();
166 task_func_decl design |
168 localparam_decl design |
174 for (auto &it : attr_list)
177 for (auto &it : default_attr_list)
178 attr_list[it.first] = it.second->clone();
180 std::map<std::string, AstNode*> *al = new std::map<std::string, AstNode*>;
186 attr_opt ATTR_BEGIN opt_attr_list ATTR_END |
191 for (auto &it : default_attr_list)
193 default_attr_list.clear();
194 for (auto &it : attr_list)
198 default_attr_list = attr_list;
203 attr_list | /* empty */;
207 attr_list ',' attr_assign;
211 if (attr_list.count(*$1) != 0)
212 delete attr_list[*$1];
213 attr_list[*$1] = AstNode::mkconst_int(1, false);
216 hierarchical_id '=' expr {
217 if (attr_list.count(*$1) != 0)
218 delete attr_list[*$1];
227 hierarchical_id TOK_PACKAGESEP TOK_ID {
228 if ($3->substr(0, 1) == "\\")
229 *$1 += "::" + $3->substr(1);
235 hierarchical_id '.' TOK_ID {
236 if ($3->substr(0, 1) == "\\")
237 *$1 += "." + $3->substr(1);
245 attr TOK_MODULE TOK_ID {
246 do_not_require_port_stubs = false;
247 AstNode *mod = new AstNode(AST_MODULE);
248 ast_stack.back()->children.push_back(mod);
249 ast_stack.push_back(mod);
250 current_ast_mod = mod;
254 append_attr(mod, $1);
256 } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
257 if (port_stubs.size() != 0)
258 frontend_verilog_yyerror("Missing details for module port `%s'.",
259 port_stubs.begin()->first.c_str());
260 ast_stack.pop_back();
261 log_assert(ast_stack.size() == 1);
262 current_ast_mod = NULL;
266 '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
269 single_module_para | module_para_list ',' single_module_para;
274 if (astbuf1) delete astbuf1;
275 astbuf1 = new AstNode(AST_PARAMETER);
276 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
277 } param_signed param_integer param_range single_param_decl |
279 if (astbuf1) delete astbuf1;
280 astbuf1 = new AstNode(AST_LOCALPARAM);
281 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
282 } param_signed param_integer param_range single_param_decl |
286 '(' ')' | /* empty */ | '(' module_args optional_comma ')';
289 module_arg | module_args ',' module_arg;
294 module_arg_opt_assignment:
296 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
297 AstNode *wire = new AstNode(AST_IDENTIFIER);
298 wire->str = ast_stack.back()->children.back()->str;
299 if (ast_stack.back()->children.back()->is_reg)
300 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
302 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
304 frontend_verilog_yyerror("Syntax error.");
310 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
311 AstNode *node = ast_stack.back()->children.back()->clone();
313 node->port_id = ++port_counter;
314 ast_stack.back()->children.push_back(node);
316 if (port_stubs.count(*$1) != 0)
317 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
318 port_stubs[*$1] = ++port_counter;
321 } module_arg_opt_assignment |
322 attr wire_type range TOK_ID {
325 node->port_id = ++port_counter;
327 node->children.push_back($3);
328 if (!node->is_input && !node->is_output)
329 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
330 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
331 frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
332 ast_stack.back()->children.push_back(node);
333 append_attr(node, $1);
335 } module_arg_opt_assignment |
337 do_not_require_port_stubs = true;
341 attr TOK_PACKAGE TOK_ID {
342 AstNode *mod = new AstNode(AST_PACKAGE);
343 ast_stack.back()->children.push_back(mod);
344 ast_stack.push_back(mod);
345 current_ast_mod = mod;
347 append_attr(mod, $1);
348 } ';' package_body TOK_ENDPACKAGE {
349 ast_stack.pop_back();
350 current_ast_mod = NULL;
354 package_body package_body_stmt |;
360 '#' TOK_ID { delete $2; } |
361 '#' TOK_CONSTVAL { delete $2; } |
362 '#' '(' expr ')' { delete $3; } |
363 '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
366 non_opt_delay | /* empty */;
370 astbuf3 = new AstNode(AST_WIRE);
371 current_wire_rand = false;
372 current_wire_const = false;
373 } wire_type_token_list delay {
377 wire_type_token_list:
378 wire_type_token | wire_type_token_list wire_type_token;
382 astbuf3->is_input = true;
385 astbuf3->is_output = true;
388 astbuf3->is_input = true;
389 astbuf3->is_output = true;
394 astbuf3->is_reg = true;
397 astbuf3->is_reg = true;
398 astbuf3->range_left = 31;
399 astbuf3->range_right = 0;
400 astbuf3->is_signed = true;
403 astbuf3->type = AST_GENVAR;
404 astbuf3->is_reg = true;
405 astbuf3->range_left = 31;
406 astbuf3->range_right = 0;
409 astbuf3->is_signed = true;
412 current_wire_rand = true;
415 current_wire_const = true;
419 '[' expr ':' expr ']' {
420 $$ = new AstNode(AST_RANGE);
421 $$->children.push_back($2);
422 $$->children.push_back($4);
424 '[' expr TOK_POS_INDEXED expr ']' {
425 $$ = new AstNode(AST_RANGE);
426 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), $4), AstNode::mkconst_int(1, true)));
427 $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
429 '[' expr TOK_NEG_INDEXED expr ']' {
430 $$ = new AstNode(AST_RANGE);
431 $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
432 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)), $4));
435 $$ = new AstNode(AST_RANGE);
436 $$->children.push_back($2);
440 non_opt_range non_opt_range {
441 $$ = new AstNode(AST_MULTIRANGE, $1, $2);
443 non_opt_multirange non_opt_range {
445 $$->children.push_back($2);
458 non_opt_multirange { $$ = $1; };
465 $$ = new AstNode(AST_RANGE);
466 $$->children.push_back(AstNode::mkconst_int(31, true));
467 $$->children.push_back(AstNode::mkconst_int(0, true));
468 $$->is_signed = true;
472 module_body module_body_stmt |
473 /* the following line makes the generate..endgenrate keywords optional */
474 module_body gen_stmt |
478 task_func_decl | param_decl | localparam_decl | defparam_decl | wire_decl | assign_stmt | cell_stmt |
479 always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl;
482 TOK_CHECKER TOK_ID ';' {
483 AstNode *node = new AstNode(AST_GENBLOCK);
485 ast_stack.back()->children.push_back(node);
486 ast_stack.push_back(node);
487 } module_body TOK_ENDCHECKER {
489 ast_stack.pop_back();
493 attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
494 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
495 current_function_or_task->str = *$4;
496 append_attr(current_function_or_task, $1);
497 ast_stack.back()->children.push_back(current_function_or_task);
500 } opt_dpi_function_args ';' {
501 current_function_or_task = NULL;
503 attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
504 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
505 current_function_or_task->str = *$6;
506 append_attr(current_function_or_task, $1);
507 ast_stack.back()->children.push_back(current_function_or_task);
511 } opt_dpi_function_args ';' {
512 current_function_or_task = NULL;
514 attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
515 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
516 current_function_or_task->str = *$8;
517 append_attr(current_function_or_task, $1);
518 ast_stack.back()->children.push_back(current_function_or_task);
523 } opt_dpi_function_args ';' {
524 current_function_or_task = NULL;
526 attr TOK_TASK TOK_ID {
527 current_function_or_task = new AstNode(AST_TASK);
528 current_function_or_task->str = *$3;
529 append_attr(current_function_or_task, $1);
530 ast_stack.back()->children.push_back(current_function_or_task);
531 ast_stack.push_back(current_function_or_task);
532 current_function_or_task_port_id = 1;
534 } task_func_args_opt ';' task_func_body TOK_ENDTASK {
535 current_function_or_task = NULL;
536 ast_stack.pop_back();
538 attr TOK_FUNCTION opt_signed range_or_signed_int TOK_ID {
539 current_function_or_task = new AstNode(AST_FUNCTION);
540 current_function_or_task->str = *$5;
541 append_attr(current_function_or_task, $1);
542 ast_stack.back()->children.push_back(current_function_or_task);
543 ast_stack.push_back(current_function_or_task);
544 AstNode *outreg = new AstNode(AST_WIRE);
546 outreg->is_signed = $3;
548 outreg->children.push_back($4);
549 outreg->is_signed = $3 || $4->is_signed;
550 $4->is_signed = false;
552 current_function_or_task->children.push_back(outreg);
553 current_function_or_task_port_id = 1;
555 } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
556 current_function_or_task = NULL;
557 ast_stack.pop_back();
562 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
567 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
571 opt_dpi_function_args:
572 '(' dpi_function_args ')' |
576 dpi_function_args ',' dpi_function_arg |
577 dpi_function_args ',' |
590 '(' ')' | /* empty */ | '(' {
594 } task_func_args optional_comma {
602 task_func_port | task_func_args ',' task_func_port;
605 attr wire_type range {
615 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
617 frontend_verilog_yyerror("Syntax error.");
619 astbuf2 = new AstNode(AST_RANGE);
620 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
621 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
624 if (astbuf2 && astbuf2->children.size() != 2)
625 frontend_verilog_yyerror("Syntax error.");
626 } wire_name | wire_name;
629 task_func_body behavioral_stmt |
634 astbuf1->is_signed = true;
639 if (astbuf1->children.size() != 1)
640 frontend_verilog_yyerror("Syntax error.");
641 astbuf1->children.push_back(new AstNode(AST_RANGE));
642 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
643 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
644 astbuf1->is_signed = true;
649 if (astbuf1->children.size() != 1)
650 frontend_verilog_yyerror("Syntax error.");
651 astbuf1->children.push_back(new AstNode(AST_REALVALUE));
657 if (astbuf1->children.size() != 1)
658 frontend_verilog_yyerror("Syntax error.");
659 astbuf1->children.push_back($1);
665 astbuf1 = new AstNode(AST_PARAMETER);
666 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
667 } param_signed param_integer param_real param_range param_decl_list ';' {
673 astbuf1 = new AstNode(AST_LOCALPARAM);
674 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
675 } param_signed param_integer param_real param_range param_decl_list ';' {
680 single_param_decl | param_decl_list ',' single_param_decl;
684 if (astbuf1 == nullptr)
685 frontend_verilog_yyerror("syntax error");
686 AstNode *node = astbuf1->clone();
688 delete node->children[0];
689 node->children[0] = $3;
690 ast_stack.back()->children.push_back(node);
695 TOK_DEFPARAM defparam_decl_list ';';
698 single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
700 single_defparam_decl:
701 range rvalue '=' expr {
702 AstNode *node = new AstNode(AST_DEFPARAM);
703 node->children.push_back($2);
704 node->children.push_back($4);
706 node->children.push_back($1);
707 ast_stack.back()->children.push_back(node);
711 attr wire_type range {
715 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
717 frontend_verilog_yyerror("Syntax error.");
719 astbuf2 = new AstNode(AST_RANGE);
720 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
721 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
724 if (astbuf2 && astbuf2->children.size() != 2)
725 frontend_verilog_yyerror("Syntax error.");
732 attr TOK_SUPPLY0 TOK_ID {
733 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
734 ast_stack.back()->children.back()->str = *$3;
735 append_attr(ast_stack.back()->children.back(), $1);
736 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
737 ast_stack.back()->children.back()->children[0]->str = *$3;
739 } opt_supply_wires ';' |
740 attr TOK_SUPPLY1 TOK_ID {
741 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
742 ast_stack.back()->children.back()->str = *$3;
743 append_attr(ast_stack.back()->children.back(), $1);
744 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
745 ast_stack.back()->children.back()->children[0]->str = *$3;
747 } opt_supply_wires ';';
751 opt_supply_wires ',' TOK_ID {
752 AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
753 AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
754 wire_node->str = *$3;
755 assign_node->children[0]->str = *$3;
756 ast_stack.back()->children.push_back(wire_node);
757 ast_stack.back()->children.push_back(assign_node);
762 wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
764 wire_name_and_opt_assign:
766 if (current_wire_rand) {
767 AstNode *wire = new AstNode(AST_IDENTIFIER);
768 AstNode *fcall = new AstNode(AST_FCALL);
769 wire->str = ast_stack.back()->children.back()->str;
770 fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
771 fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
772 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
776 AstNode *wire = new AstNode(AST_IDENTIFIER);
777 wire->str = ast_stack.back()->children.back()->str;
779 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $3))));
781 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3));
785 TOK_ID range_or_multirange {
786 if (astbuf1 == nullptr)
787 frontend_verilog_yyerror("Syntax error.");
788 AstNode *node = astbuf1->clone();
790 append_attr_clone(node, albuf);
792 node->children.push_back(astbuf2->clone());
794 if (node->is_input || node->is_output)
795 frontend_verilog_yyerror("Syntax error.");
797 AstNode *rng = new AstNode(AST_RANGE);
798 rng->children.push_back(AstNode::mkconst_int(0, true));
799 rng->children.push_back(AstNode::mkconst_int(0, true));
800 node->children.push_back(rng);
802 node->type = AST_MEMORY;
803 node->children.push_back($2);
805 if (current_function_or_task == NULL) {
806 if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
807 port_stubs[*$1] = ++port_counter;
809 if (port_stubs.count(*$1) != 0) {
810 if (!node->is_input && !node->is_output)
811 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
812 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
813 frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
814 node->port_id = port_stubs[*$1];
815 port_stubs.erase(*$1);
817 if (node->is_input || node->is_output)
818 frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
821 if (node->is_input || node->is_output)
822 node->port_id = current_function_or_task_port_id++;
824 ast_stack.back()->children.push_back(node);
829 TOK_ASSIGN delay assign_expr_list ';';
832 assign_expr | assign_expr_list ',' assign_expr;
836 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, $1, $3));
841 astbuf1 = new AstNode(AST_CELL);
842 append_attr(astbuf1, $1);
843 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
844 astbuf1->children[0]->str = *$2;
846 } cell_parameter_list_opt cell_list ';' {
849 attr tok_prim_wrapper delay {
850 astbuf1 = new AstNode(AST_PRIMITIVE);
852 append_attr(astbuf1, $1);
863 $$ = new std::string("or");
868 cell_list ',' single_cell;
872 astbuf2 = astbuf1->clone();
873 if (astbuf2->type != AST_PRIMITIVE)
876 ast_stack.back()->children.push_back(astbuf2);
877 } '(' cell_port_list ')' |
878 TOK_ID non_opt_range {
879 astbuf2 = astbuf1->clone();
880 if (astbuf2->type != AST_PRIMITIVE)
883 ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
884 } '(' cell_port_list ')';
888 prim_list ',' single_prim;
893 astbuf2 = astbuf1->clone();
894 ast_stack.back()->children.push_back(astbuf2);
895 } '(' cell_port_list ')';
897 cell_parameter_list_opt:
898 '#' '(' cell_parameter_list ')' | /* empty */;
901 cell_parameter | cell_parameter_list ',' cell_parameter;
906 AstNode *node = new AstNode(AST_PARASET);
907 astbuf1->children.push_back(node);
908 node->children.push_back($1);
910 '.' TOK_ID '(' expr ')' {
911 AstNode *node = new AstNode(AST_PARASET);
913 astbuf1->children.push_back(node);
914 node->children.push_back($4);
919 cell_port_list_rules {
920 // remove empty args from end of list
921 while (!astbuf2->children.empty()) {
922 AstNode *node = astbuf2->children.back();
923 if (node->type != AST_ARGUMENT) break;
924 if (!node->children.empty()) break;
925 if (!node->str.empty()) break;
926 astbuf2->children.pop_back();
931 bool has_positional_args = false;
932 bool has_named_args = false;
933 for (auto node : astbuf2->children) {
934 if (node->type != AST_ARGUMENT) continue;
935 if (node->str.empty())
936 has_positional_args = true;
938 has_named_args = true;
941 if (has_positional_args && has_named_args)
942 frontend_verilog_yyerror("Mix of positional and named cell ports.");
945 cell_port_list_rules:
946 cell_port | cell_port_list_rules ',' cell_port;
950 AstNode *node = new AstNode(AST_ARGUMENT);
951 astbuf2->children.push_back(node);
954 AstNode *node = new AstNode(AST_ARGUMENT);
955 astbuf2->children.push_back(node);
956 node->children.push_back($1);
958 '.' TOK_ID '(' expr ')' {
959 AstNode *node = new AstNode(AST_ARGUMENT);
961 astbuf2->children.push_back(node);
962 node->children.push_back($4);
966 AstNode *node = new AstNode(AST_ARGUMENT);
968 astbuf2->children.push_back(node);
974 AstNode *node = new AstNode(AST_ALWAYS);
975 append_attr(node, $1);
976 ast_stack.back()->children.push_back(node);
977 ast_stack.push_back(node);
979 AstNode *block = new AstNode(AST_BLOCK);
980 ast_stack.back()->children.push_back(block);
981 ast_stack.push_back(block);
983 ast_stack.pop_back();
984 ast_stack.pop_back();
987 AstNode *node = new AstNode(AST_INITIAL);
988 append_attr(node, $1);
989 ast_stack.back()->children.push_back(node);
990 ast_stack.push_back(node);
991 AstNode *block = new AstNode(AST_BLOCK);
992 ast_stack.back()->children.push_back(block);
993 ast_stack.push_back(block);
995 ast_stack.pop_back();
996 ast_stack.pop_back();
1000 '@' '(' always_events ')' |
1002 '@' ATTR_BEGIN ')' |
1009 always_events TOK_OR always_event |
1010 always_events ',' always_event;
1014 AstNode *node = new AstNode(AST_POSEDGE);
1015 ast_stack.back()->children.push_back(node);
1016 node->children.push_back($2);
1019 AstNode *node = new AstNode(AST_NEGEDGE);
1020 ast_stack.back()->children.push_back(node);
1021 node->children.push_back($2);
1024 AstNode *node = new AstNode(AST_EDGE);
1025 ast_stack.back()->children.push_back(node);
1026 node->children.push_back($1);
1038 TOK_ASSERT '(' expr ')' ';' {
1039 ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $3));
1041 TOK_ASSUME '(' expr ')' ';' {
1042 ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
1044 TOK_ASSERT '(' TOK_EVENTUALLY expr ')' ';' {
1045 ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $4));
1047 TOK_ASSUME '(' TOK_EVENTUALLY expr ')' ';' {
1048 ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $4));
1050 TOK_COVER '(' expr ')' ';' {
1051 ast_stack.back()->children.push_back(new AstNode(AST_COVER, $3));
1053 TOK_COVER '(' ')' ';' {
1054 ast_stack.back()->children.push_back(new AstNode(AST_COVER, AstNode::mkconst_int(1, false)));
1057 ast_stack.back()->children.push_back(new AstNode(AST_COVER, AstNode::mkconst_int(1, false)));
1059 TOK_RESTRICT '(' expr ')' ';' {
1060 if (norestrict_mode)
1063 ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
1065 TOK_RESTRICT '(' TOK_EVENTUALLY expr ')' ';' {
1066 if (norestrict_mode)
1069 ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $4));
1073 TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
1074 ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $4));
1076 TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
1077 ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
1079 TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
1080 ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $5));
1082 TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
1083 ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
1085 TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
1086 ast_stack.back()->children.push_back(new AstNode(AST_COVER, $4));
1088 TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
1089 if (norestrict_mode)
1092 ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
1094 TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
1095 if (norestrict_mode)
1098 ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
1101 simple_behavioral_stmt:
1102 lvalue '=' delay expr {
1103 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4);
1104 ast_stack.back()->children.push_back(node);
1106 lvalue TOK_INCREMENT {
1107 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true)));
1108 ast_stack.back()->children.push_back(node);
1110 lvalue TOK_DECREMENT {
1111 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true)));
1112 ast_stack.back()->children.push_back(node);
1114 lvalue OP_LE delay expr {
1115 AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4);
1116 ast_stack.back()->children.push_back(node);
1119 // this production creates the obligatory if-else shift/reduce conflict
1121 defattr | assert | wire_decl | param_decl | localparam_decl |
1122 non_opt_delay behavioral_stmt |
1123 simple_behavioral_stmt ';' | ';' |
1124 hierarchical_id attr {
1125 AstNode *node = new AstNode(AST_TCALL);
1128 ast_stack.back()->children.push_back(node);
1129 ast_stack.push_back(node);
1130 append_attr(node, $2);
1132 ast_stack.pop_back();
1134 attr TOK_BEGIN opt_label {
1135 AstNode *node = new AstNode(AST_BLOCK);
1136 ast_stack.back()->children.push_back(node);
1137 ast_stack.push_back(node);
1138 append_attr(node, $1);
1141 } behavioral_stmt_list TOK_END opt_label {
1142 if ($3 != NULL && $7 != NULL && *$3 != *$7)
1143 frontend_verilog_yyerror("Syntax error.");
1148 ast_stack.pop_back();
1151 AstNode *node = new AstNode(AST_FOR);
1152 ast_stack.back()->children.push_back(node);
1153 ast_stack.push_back(node);
1154 append_attr(node, $1);
1155 } simple_behavioral_stmt ';' expr {
1156 ast_stack.back()->children.push_back($7);
1157 } ';' simple_behavioral_stmt ')' {
1158 AstNode *block = new AstNode(AST_BLOCK);
1159 ast_stack.back()->children.push_back(block);
1160 ast_stack.push_back(block);
1162 ast_stack.pop_back();
1163 ast_stack.pop_back();
1165 attr TOK_WHILE '(' expr ')' {
1166 AstNode *node = new AstNode(AST_WHILE);
1167 ast_stack.back()->children.push_back(node);
1168 ast_stack.push_back(node);
1169 append_attr(node, $1);
1170 AstNode *block = new AstNode(AST_BLOCK);
1171 ast_stack.back()->children.push_back($4);
1172 ast_stack.back()->children.push_back(block);
1173 ast_stack.push_back(block);
1175 ast_stack.pop_back();
1176 ast_stack.pop_back();
1178 attr TOK_REPEAT '(' expr ')' {
1179 AstNode *node = new AstNode(AST_REPEAT);
1180 ast_stack.back()->children.push_back(node);
1181 ast_stack.push_back(node);
1182 append_attr(node, $1);
1183 AstNode *block = new AstNode(AST_BLOCK);
1184 ast_stack.back()->children.push_back($4);
1185 ast_stack.back()->children.push_back(block);
1186 ast_stack.push_back(block);
1188 ast_stack.pop_back();
1189 ast_stack.pop_back();
1191 attr TOK_IF '(' expr ')' {
1192 AstNode *node = new AstNode(AST_CASE);
1193 AstNode *block = new AstNode(AST_BLOCK);
1194 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
1195 ast_stack.back()->children.push_back(node);
1196 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
1197 node->children.push_back(cond);
1198 ast_stack.push_back(node);
1199 ast_stack.push_back(block);
1200 append_attr(node, $1);
1201 } behavioral_stmt optional_else {
1202 ast_stack.pop_back();
1203 ast_stack.pop_back();
1205 case_attr case_type '(' expr ')' {
1206 AstNode *node = new AstNode(AST_CASE, $4);
1207 ast_stack.back()->children.push_back(node);
1208 ast_stack.push_back(node);
1209 append_attr(node, $1);
1210 } opt_synopsys_attr case_body TOK_ENDCASE {
1211 case_type_stack.pop_back();
1212 ast_stack.pop_back();
1219 TOK_PRIORITY case_attr {
1222 TOK_UNIQUE case_attr {
1227 attr unique_case_attr {
1228 if ($2) (*$1)["\\parallel_case"] = AstNode::mkconst_int(1, false);
1234 case_type_stack.push_back(0);
1237 case_type_stack.push_back('x');
1240 case_type_stack.push_back('z');
1244 opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
1245 if (ast_stack.back()->attributes.count("\\full_case") == 0)
1246 ast_stack.back()->attributes["\\full_case"] = AstNode::mkconst_int(1, false);
1248 opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
1249 if (ast_stack.back()->attributes.count("\\parallel_case") == 0)
1250 ast_stack.back()->attributes["\\parallel_case"] = AstNode::mkconst_int(1, false);
1254 behavioral_stmt_list:
1255 behavioral_stmt_list behavioral_stmt |
1260 AstNode *block = new AstNode(AST_BLOCK);
1261 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
1262 ast_stack.pop_back();
1263 ast_stack.back()->children.push_back(cond);
1264 ast_stack.push_back(block);
1266 /* empty */ %prec FAKE_THEN;
1269 case_body case_item |
1274 AstNode *node = new AstNode(
1275 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
1276 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
1277 ast_stack.back()->children.push_back(node);
1278 ast_stack.push_back(node);
1280 AstNode *block = new AstNode(AST_BLOCK);
1281 ast_stack.back()->children.push_back(block);
1282 ast_stack.push_back(block);
1283 case_type_stack.push_back(0);
1285 case_type_stack.pop_back();
1286 ast_stack.pop_back();
1287 ast_stack.pop_back();
1291 gen_case_body gen_case_item |
1296 AstNode *node = new AstNode(
1297 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
1298 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
1299 ast_stack.back()->children.push_back(node);
1300 ast_stack.push_back(node);
1302 case_type_stack.push_back(0);
1303 } gen_stmt_or_null {
1304 case_type_stack.pop_back();
1305 ast_stack.pop_back();
1309 case_expr_list ':' |
1314 ast_stack.back()->children.push_back(new AstNode(AST_DEFAULT));
1317 ast_stack.back()->children.push_back($1);
1319 case_expr_list ',' expr {
1320 ast_stack.back()->children.push_back($3);
1324 hierarchical_id '[' expr ']' '.' rvalue {
1325 $$ = new AstNode(AST_PREFIX, $3, $6);
1329 hierarchical_id range {
1330 $$ = new AstNode(AST_IDENTIFIER, $2);
1333 if ($2 == nullptr && ($$->str == "\\$initstate" || $$->str == "\\$anyconst" || $$->str == "\\$anyseq"))
1334 $$->type = AST_FCALL;
1336 hierarchical_id non_opt_multirange {
1337 $$ = new AstNode(AST_IDENTIFIER, $2);
1346 '{' lvalue_concat_list '}' {
1352 $$ = new AstNode(AST_CONCAT);
1353 $$->children.push_back($1);
1355 expr ',' lvalue_concat_list {
1357 $$->children.push_back($1);
1361 '(' arg_list optional_comma ')' |
1370 arg_list ',' single_arg;
1374 ast_stack.back()->children.push_back($1);
1378 module_gen_body gen_stmt_or_module_body_stmt |
1381 gen_stmt_or_module_body_stmt:
1382 gen_stmt | module_body_stmt;
1384 // this production creates the obligatory if-else shift/reduce conflict
1387 AstNode *node = new AstNode(AST_GENFOR);
1388 ast_stack.back()->children.push_back(node);
1389 ast_stack.push_back(node);
1390 } simple_behavioral_stmt ';' expr {
1391 ast_stack.back()->children.push_back($6);
1392 } ';' simple_behavioral_stmt ')' gen_stmt_block {
1393 ast_stack.pop_back();
1395 TOK_IF '(' expr ')' {
1396 AstNode *node = new AstNode(AST_GENIF);
1397 ast_stack.back()->children.push_back(node);
1398 ast_stack.push_back(node);
1399 ast_stack.back()->children.push_back($3);
1400 } gen_stmt_block opt_gen_else {
1401 ast_stack.pop_back();
1403 case_type '(' expr ')' {
1404 AstNode *node = new AstNode(AST_GENCASE, $3);
1405 ast_stack.back()->children.push_back(node);
1406 ast_stack.push_back(node);
1407 } gen_case_body TOK_ENDCASE {
1408 case_type_stack.pop_back();
1409 ast_stack.pop_back();
1411 TOK_BEGIN opt_label {
1412 AstNode *node = new AstNode(AST_GENBLOCK);
1413 node->str = $2 ? *$2 : std::string();
1414 ast_stack.back()->children.push_back(node);
1415 ast_stack.push_back(node);
1416 } module_gen_body TOK_END opt_label {
1421 ast_stack.pop_back();
1426 AstNode *node = new AstNode(AST_GENBLOCK);
1427 ast_stack.back()->children.push_back(node);
1428 ast_stack.push_back(node);
1429 } gen_stmt_or_module_body_stmt {
1430 ast_stack.pop_back();
1434 gen_stmt_block | ';';
1437 TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
1443 basic_expr '?' attr expr ':' expr {
1444 $$ = new AstNode(AST_TERNARY);
1445 $$->children.push_back($1);
1446 $$->children.push_back($4);
1447 $$->children.push_back($6);
1448 append_attr($$, $3);
1455 '(' expr ')' TOK_CONSTVAL {
1456 if ($4->substr(0, 1) != "'")
1457 frontend_verilog_yyerror("Syntax error.");
1459 AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
1461 log_error("Value conversion failed: `%s'\n", $4->c_str());
1462 $$ = new AstNode(AST_TO_BITS, bits, val);
1465 hierarchical_id TOK_CONSTVAL {
1466 if ($2->substr(0, 1) != "'")
1467 frontend_verilog_yyerror("Syntax error.");
1468 AstNode *bits = new AstNode(AST_IDENTIFIER);
1470 AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
1472 log_error("Value conversion failed: `%s'\n", $2->c_str());
1473 $$ = new AstNode(AST_TO_BITS, bits, val);
1477 TOK_CONSTVAL TOK_CONSTVAL {
1478 $$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
1479 if ($$ == NULL || (*$2)[0] != '\'')
1480 log_error("Value conversion failed: `%s%s'\n", $1->c_str(), $2->c_str());
1485 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
1487 log_error("Value conversion failed: `%s'\n", $1->c_str());
1491 $$ = new AstNode(AST_REALVALUE);
1492 char *p = (char*)malloc(GetSize(*$1) + 1), *q;
1493 for (int i = 0, j = 0; j < GetSize(*$1); j++)
1494 if ((*$1)[j] != '_')
1495 p[i++] = (*$1)[j], p[i] = 0;
1496 $$->realvalue = strtod(p, &q);
1497 log_assert(*q == 0);
1502 $$ = AstNode::mkconst_str(*$1);
1505 hierarchical_id attr {
1506 AstNode *node = new AstNode(AST_FCALL);
1509 ast_stack.push_back(node);
1510 append_attr(node, $2);
1511 } '(' arg_list optional_comma ')' {
1512 $$ = ast_stack.back();
1513 ast_stack.pop_back();
1515 TOK_TO_SIGNED attr '(' expr ')' {
1516 $$ = new AstNode(AST_TO_SIGNED, $4);
1517 append_attr($$, $2);
1519 TOK_TO_UNSIGNED attr '(' expr ')' {
1520 $$ = new AstNode(AST_TO_UNSIGNED, $4);
1521 append_attr($$, $2);
1526 '(' expr ':' expr ':' expr ')' {
1531 '{' concat_list '}' {
1534 '{' expr '{' concat_list '}' '}' {
1535 $$ = new AstNode(AST_REPLICATE, $2, $4);
1537 '~' attr basic_expr %prec UNARY_OPS {
1538 $$ = new AstNode(AST_BIT_NOT, $3);
1539 append_attr($$, $2);
1541 basic_expr '&' attr basic_expr {
1542 $$ = new AstNode(AST_BIT_AND, $1, $4);
1543 append_attr($$, $3);
1545 basic_expr OP_NAND attr basic_expr {
1546 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
1547 append_attr($$, $3);
1549 basic_expr '|' attr basic_expr {
1550 $$ = new AstNode(AST_BIT_OR, $1, $4);
1551 append_attr($$, $3);
1553 basic_expr OP_NOR attr basic_expr {
1554 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
1555 append_attr($$, $3);
1557 basic_expr '^' attr basic_expr {
1558 $$ = new AstNode(AST_BIT_XOR, $1, $4);
1559 append_attr($$, $3);
1561 basic_expr OP_XNOR attr basic_expr {
1562 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
1563 append_attr($$, $3);
1565 '&' attr basic_expr %prec UNARY_OPS {
1566 $$ = new AstNode(AST_REDUCE_AND, $3);
1567 append_attr($$, $2);
1569 OP_NAND attr basic_expr %prec UNARY_OPS {
1570 $$ = new AstNode(AST_REDUCE_AND, $3);
1571 append_attr($$, $2);
1572 $$ = new AstNode(AST_LOGIC_NOT, $$);
1574 '|' attr basic_expr %prec UNARY_OPS {
1575 $$ = new AstNode(AST_REDUCE_OR, $3);
1576 append_attr($$, $2);
1578 OP_NOR attr basic_expr %prec UNARY_OPS {
1579 $$ = new AstNode(AST_REDUCE_OR, $3);
1580 append_attr($$, $2);
1581 $$ = new AstNode(AST_LOGIC_NOT, $$);
1583 '^' attr basic_expr %prec UNARY_OPS {
1584 $$ = new AstNode(AST_REDUCE_XOR, $3);
1585 append_attr($$, $2);
1587 OP_XNOR attr basic_expr %prec UNARY_OPS {
1588 $$ = new AstNode(AST_REDUCE_XNOR, $3);
1589 append_attr($$, $2);
1591 basic_expr OP_SHL attr basic_expr {
1592 $$ = new AstNode(AST_SHIFT_LEFT, $1, $4);
1593 append_attr($$, $3);
1595 basic_expr OP_SHR attr basic_expr {
1596 $$ = new AstNode(AST_SHIFT_RIGHT, $1, $4);
1597 append_attr($$, $3);
1599 basic_expr OP_SSHL attr basic_expr {
1600 $$ = new AstNode(AST_SHIFT_SLEFT, $1, $4);
1601 append_attr($$, $3);
1603 basic_expr OP_SSHR attr basic_expr {
1604 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, $4);
1605 append_attr($$, $3);
1607 basic_expr '<' attr basic_expr {
1608 $$ = new AstNode(AST_LT, $1, $4);
1609 append_attr($$, $3);
1611 basic_expr OP_LE attr basic_expr {
1612 $$ = new AstNode(AST_LE, $1, $4);
1613 append_attr($$, $3);
1615 basic_expr OP_EQ attr basic_expr {
1616 $$ = new AstNode(AST_EQ, $1, $4);
1617 append_attr($$, $3);
1619 basic_expr OP_NE attr basic_expr {
1620 $$ = new AstNode(AST_NE, $1, $4);
1621 append_attr($$, $3);
1623 basic_expr OP_EQX attr basic_expr {
1624 $$ = new AstNode(AST_EQX, $1, $4);
1625 append_attr($$, $3);
1627 basic_expr OP_NEX attr basic_expr {
1628 $$ = new AstNode(AST_NEX, $1, $4);
1629 append_attr($$, $3);
1631 basic_expr OP_GE attr basic_expr {
1632 $$ = new AstNode(AST_GE, $1, $4);
1633 append_attr($$, $3);
1635 basic_expr '>' attr basic_expr {
1636 $$ = new AstNode(AST_GT, $1, $4);
1637 append_attr($$, $3);
1639 basic_expr '+' attr basic_expr {
1640 $$ = new AstNode(AST_ADD, $1, $4);
1641 append_attr($$, $3);
1643 basic_expr '-' attr basic_expr {
1644 $$ = new AstNode(AST_SUB, $1, $4);
1645 append_attr($$, $3);
1647 basic_expr '*' attr basic_expr {
1648 $$ = new AstNode(AST_MUL, $1, $4);
1649 append_attr($$, $3);
1651 basic_expr '/' attr basic_expr {
1652 $$ = new AstNode(AST_DIV, $1, $4);
1653 append_attr($$, $3);
1655 basic_expr '%' attr basic_expr {
1656 $$ = new AstNode(AST_MOD, $1, $4);
1657 append_attr($$, $3);
1659 basic_expr OP_POW attr basic_expr {
1660 $$ = new AstNode(AST_POW, $1, $4);
1661 append_attr($$, $3);
1663 '+' attr basic_expr %prec UNARY_OPS {
1664 $$ = new AstNode(AST_POS, $3);
1665 append_attr($$, $2);
1667 '-' attr basic_expr %prec UNARY_OPS {
1668 $$ = new AstNode(AST_NEG, $3);
1669 append_attr($$, $2);
1671 basic_expr OP_LAND attr basic_expr {
1672 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
1673 append_attr($$, $3);
1675 basic_expr OP_LOR attr basic_expr {
1676 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
1677 append_attr($$, $3);
1679 '!' attr basic_expr %prec UNARY_OPS {
1680 $$ = new AstNode(AST_LOGIC_NOT, $3);
1681 append_attr($$, $2);
1686 $$ = new AstNode(AST_CONCAT, $1);
1688 expr ',' concat_list {
1690 $$->children.push_back($1);