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[yosys.git] / frontends / verilog / verilog_parser.y
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * The Verilog frontend.
21 *
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
26 *
27 * ---
28 *
29 * This is the actual bison parser for Verilog code. The AST ist created directly
30 * from the bison reduce functions here. Note that this code uses a few global
31 * variables to hold the state of the AST generator and therefore this parser is
32 * not reentrant.
33 *
34 */
35
36 %{
37 #include <list>
38 #include <stack>
39 #include <string.h>
40 #include "frontends/verilog/verilog_frontend.h"
41 #include "frontends/verilog/verilog_parser.tab.hh"
42 #include "kernel/log.h"
43
44 #define YYLEX_PARAM &yylval, &yylloc
45
46 USING_YOSYS_NAMESPACE
47 using namespace AST;
48 using namespace VERILOG_FRONTEND;
49
50 YOSYS_NAMESPACE_BEGIN
51 namespace VERILOG_FRONTEND {
52 int port_counter;
53 dict<std::string, int> port_stubs;
54 dict<IdString, AstNode*> *attr_list, default_attr_list;
55 std::stack<dict<IdString, AstNode*> *> attr_list_stack;
56 dict<IdString, AstNode*> *albuf;
57 std::vector<UserTypeMap*> user_type_stack;
58 dict<std::string, AstNode*> pkg_user_types;
59 std::vector<AstNode*> ast_stack;
60 struct AstNode *astbuf1, *astbuf2, *astbuf3;
61 struct AstNode *current_function_or_task;
62 struct AstNode *current_ast, *current_ast_mod;
63 int current_function_or_task_port_id;
64 std::vector<char> case_type_stack;
65 bool do_not_require_port_stubs;
66 bool default_nettype_wire;
67 bool sv_mode, formal_mode, lib_mode, specify_mode;
68 bool noassert_mode, noassume_mode, norestrict_mode;
69 bool assume_asserts_mode, assert_assumes_mode;
70 bool current_wire_rand, current_wire_const;
71 bool current_modport_input, current_modport_output;
72 std::istream *lexin;
73 }
74 YOSYS_NAMESPACE_END
75
76 #define SET_AST_NODE_LOC(WHICH, BEGIN, END) \
77 do { (WHICH)->location.first_line = (BEGIN).first_line; \
78 (WHICH)->location.first_column = (BEGIN).first_column; \
79 (WHICH)->location.last_line = (END).last_line; \
80 (WHICH)->location.last_column = (END).last_column; } while(0)
81
82 #define SET_RULE_LOC(LHS, BEGIN, END) \
83 do { (LHS).first_line = (BEGIN).first_line; \
84 (LHS).first_column = (BEGIN).first_column; \
85 (LHS).last_line = (END).last_line; \
86 (LHS).last_column = (END).last_column; } while(0)
87
88 int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
89
90 static void append_attr(AstNode *ast, dict<IdString, AstNode*> *al)
91 {
92 for (auto &it : *al) {
93 if (ast->attributes.count(it.first) > 0)
94 delete ast->attributes[it.first];
95 ast->attributes[it.first] = it.second;
96 }
97 delete al;
98 }
99
100 static void append_attr_clone(AstNode *ast, dict<IdString, AstNode*> *al)
101 {
102 for (auto &it : *al) {
103 if (ast->attributes.count(it.first) > 0)
104 delete ast->attributes[it.first];
105 ast->attributes[it.first] = it.second->clone();
106 }
107 }
108
109 static void free_attr(dict<IdString, AstNode*> *al)
110 {
111 for (auto &it : *al)
112 delete it.second;
113 delete al;
114 }
115
116 struct specify_target {
117 char polarity_op;
118 AstNode *dst, *dat;
119 };
120
121 struct specify_triple {
122 AstNode *t_min, *t_avg, *t_max;
123 };
124
125 struct specify_rise_fall {
126 specify_triple rise;
127 specify_triple fall;
128 };
129
130 static void addTypedefNode(std::string *name, AstNode *node)
131 {
132 log_assert(node);
133 auto *tnode = new AstNode(AST_TYPEDEF, node);
134 tnode->str = *name;
135 auto user_types = user_type_stack.back();
136 (*user_types)[*name] = tnode;
137 if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {
138 // typedef inside a package so we need the qualified name
139 auto qname = current_ast_mod->str + "::" + (*name).substr(1);
140 pkg_user_types[qname] = tnode;
141 }
142 delete name;
143 ast_stack.back()->children.push_back(tnode);
144 }
145
146 static void enterTypeScope()
147 {
148 auto user_types = new UserTypeMap();
149 user_type_stack.push_back(user_types);
150 }
151
152 static void exitTypeScope()
153 {
154 user_type_stack.pop_back();
155 }
156
157 static bool isInLocalScope(const std::string *name)
158 {
159 // tests if a name was declared in the current block scope
160 auto user_types = user_type_stack.back();
161 return (user_types->count(*name) > 0);
162 }
163
164 static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
165 {
166 auto range = new AstNode(AST_RANGE);
167 range->children.push_back(AstNode::mkconst_int(msb, true));
168 range->children.push_back(AstNode::mkconst_int(lsb, true));
169 range->is_signed = isSigned;
170 return range;
171 }
172
173 static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned = true)
174 {
175 auto range = makeRange(msb, lsb, isSigned);
176 parent->children.push_back(range);
177 }
178 %}
179
180 %define api.prefix {frontend_verilog_yy}
181 %define api.pure
182
183 /* The union is defined in the header, so we need to provide all the
184 * includes it requires
185 */
186 %code requires {
187 #include <map>
188 #include <string>
189 #include "frontends/verilog/verilog_frontend.h"
190 }
191
192 %union {
193 std::string *string;
194 struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
195 YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
196 struct specify_target *specify_target_ptr;
197 struct specify_triple *specify_triple_ptr;
198 struct specify_rise_fall *specify_rise_fall_ptr;
199 bool boolean;
200 char ch;
201 }
202
203 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
204 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
205 %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL
206 %token <string> TOK_USER_TYPE TOK_PKG_USER_TYPE
207 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
208 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
209 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
210 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
211 %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
212 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
213 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
214 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
215 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
216 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
217 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
218 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
219 %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
220 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
221 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
222 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
223 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
224 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
225 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
226
227 %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
228 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
229 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
230 %type <string> type_name
231 %type <ast> opt_enum_init
232 %type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
233 %type <al> attr case_attr
234
235 %type <specify_target_ptr> specify_target
236 %type <specify_triple_ptr> specify_triple specify_opt_triple
237 %type <specify_rise_fall_ptr> specify_rise_fall
238 %type <ast> specify_if specify_condition
239 %type <ch> specify_edge
240
241 // operator precedence from low to high
242 %left OP_LOR
243 %left OP_LAND
244 %left '|' OP_NOR
245 %left '^' OP_XNOR
246 %left '&' OP_NAND
247 %left OP_EQ OP_NE OP_EQX OP_NEX
248 %left '<' OP_LE OP_GE '>'
249 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
250 %left '+' '-'
251 %left '*' '/' '%'
252 %left OP_POW
253 %right UNARY_OPS
254
255 %define parse.error verbose
256 %define parse.lac full
257
258 %nonassoc FAKE_THEN
259 %nonassoc TOK_ELSE
260
261 %debug
262 %locations
263
264 %%
265
266 input: {
267 ast_stack.clear();
268 ast_stack.push_back(current_ast);
269 } design {
270 ast_stack.pop_back();
271 log_assert(GetSize(ast_stack) == 0);
272 for (auto &it : default_attr_list)
273 delete it.second;
274 default_attr_list.clear();
275 };
276
277 design:
278 module design |
279 defattr design |
280 task_func_decl design |
281 param_decl design |
282 localparam_decl design |
283 typedef_decl design |
284 package design |
285 interface design |
286 /* empty */;
287
288 attr:
289 {
290 if (attr_list != nullptr)
291 attr_list_stack.push(attr_list);
292 attr_list = new dict<IdString, AstNode*>;
293 for (auto &it : default_attr_list)
294 (*attr_list)[it.first] = it.second->clone();
295 } attr_opt {
296 $$ = attr_list;
297 if (!attr_list_stack.empty()) {
298 attr_list = attr_list_stack.top();
299 attr_list_stack.pop();
300 } else
301 attr_list = nullptr;
302 };
303
304 attr_opt:
305 attr_opt ATTR_BEGIN opt_attr_list ATTR_END {
306 SET_RULE_LOC(@$, @2, @$);
307 }|
308 /* empty */;
309
310 defattr:
311 DEFATTR_BEGIN {
312 if (attr_list != nullptr)
313 attr_list_stack.push(attr_list);
314 attr_list = new dict<IdString, AstNode*>;
315 for (auto &it : default_attr_list)
316 delete it.second;
317 default_attr_list.clear();
318 } opt_attr_list {
319 attr_list->swap(default_attr_list);
320 delete attr_list;
321 if (!attr_list_stack.empty()) {
322 attr_list = attr_list_stack.top();
323 attr_list_stack.pop();
324 } else
325 attr_list = nullptr;
326 } DEFATTR_END;
327
328 opt_attr_list:
329 attr_list | /* empty */;
330
331 attr_list:
332 attr_assign |
333 attr_list ',' attr_assign;
334
335 attr_assign:
336 hierarchical_id {
337 if (attr_list->count(*$1) != 0)
338 delete (*attr_list)[*$1];
339 (*attr_list)[*$1] = AstNode::mkconst_int(1, false);
340 delete $1;
341 } |
342 hierarchical_id '=' expr {
343 if (attr_list->count(*$1) != 0)
344 delete (*attr_list)[*$1];
345 (*attr_list)[*$1] = $3;
346 delete $1;
347 };
348
349 hierarchical_id:
350 TOK_ID {
351 $$ = $1;
352 } |
353 hierarchical_id TOK_PACKAGESEP TOK_ID {
354 if ($3->compare(0, 1, "\\") == 0)
355 *$1 += "::" + $3->substr(1);
356 else
357 *$1 += "::" + *$3;
358 delete $3;
359 $$ = $1;
360 } |
361 hierarchical_id '.' TOK_ID {
362 if ($3->compare(0, 1, "\\") == 0)
363 *$1 += "." + $3->substr(1);
364 else
365 *$1 += "." + *$3;
366 delete $3;
367 $$ = $1;
368 };
369
370 hierarchical_type_id:
371 TOK_USER_TYPE
372 | TOK_PKG_USER_TYPE // package qualified type name
373 | '(' TOK_USER_TYPE ')' { $$ = $2; } // non-standard grammar
374 ;
375
376 module:
377 attr TOK_MODULE {
378 enterTypeScope();
379 } TOK_ID {
380 do_not_require_port_stubs = false;
381 AstNode *mod = new AstNode(AST_MODULE);
382 ast_stack.back()->children.push_back(mod);
383 ast_stack.push_back(mod);
384 current_ast_mod = mod;
385 port_stubs.clear();
386 port_counter = 0;
387 mod->str = *$4;
388 append_attr(mod, $1);
389 delete $4;
390 } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
391 if (port_stubs.size() != 0)
392 frontend_verilog_yyerror("Missing details for module port `%s'.",
393 port_stubs.begin()->first.c_str());
394 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
395 ast_stack.pop_back();
396 log_assert(ast_stack.size() == 1);
397 current_ast_mod = NULL;
398 exitTypeScope();
399 };
400
401 module_para_opt:
402 '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
403
404 module_para_list:
405 single_module_para | module_para_list ',' single_module_para;
406
407 single_module_para:
408 /* empty */ |
409 attr TOK_PARAMETER {
410 if (astbuf1) delete astbuf1;
411 astbuf1 = new AstNode(AST_PARAMETER);
412 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
413 append_attr(astbuf1, $1);
414 } param_type single_param_decl |
415 attr TOK_LOCALPARAM {
416 if (astbuf1) delete astbuf1;
417 astbuf1 = new AstNode(AST_LOCALPARAM);
418 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
419 append_attr(astbuf1, $1);
420 } param_type single_param_decl |
421 single_param_decl;
422
423 module_args_opt:
424 '(' ')' | /* empty */ | '(' module_args optional_comma ')';
425
426 module_args:
427 module_arg | module_args ',' module_arg;
428
429 optional_comma:
430 ',' | /* empty */;
431
432 module_arg_opt_assignment:
433 '=' expr {
434 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
435 AstNode *wire = new AstNode(AST_IDENTIFIER);
436 wire->str = ast_stack.back()->children.back()->str;
437 if (ast_stack.back()->children.back()->is_input) {
438 AstNode *n = ast_stack.back()->children.back();
439 if (n->attributes.count(ID::defaultvalue))
440 delete n->attributes.at(ID::defaultvalue);
441 n->attributes[ID::defaultvalue] = $2;
442 } else
443 if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
444 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
445 else
446 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
447 } else
448 frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
449 } |
450 /* empty */;
451
452 module_arg:
453 TOK_ID {
454 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
455 AstNode *node = ast_stack.back()->children.back()->clone();
456 node->str = *$1;
457 node->port_id = ++port_counter;
458 ast_stack.back()->children.push_back(node);
459 SET_AST_NODE_LOC(node, @1, @1);
460 } else {
461 if (port_stubs.count(*$1) != 0)
462 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
463 port_stubs[*$1] = ++port_counter;
464 }
465 delete $1;
466 } module_arg_opt_assignment |
467 TOK_ID {
468 astbuf1 = new AstNode(AST_INTERFACEPORT);
469 astbuf1->children.push_back(new AstNode(AST_INTERFACEPORTTYPE));
470 astbuf1->children[0]->str = *$1;
471 delete $1;
472 } TOK_ID { /* SV interfaces */
473 if (!sv_mode)
474 frontend_verilog_yyerror("Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
475 astbuf2 = astbuf1->clone(); // really only needed if multiple instances of same type.
476 astbuf2->str = *$3;
477 delete $3;
478 astbuf2->port_id = ++port_counter;
479 ast_stack.back()->children.push_back(astbuf2);
480 delete astbuf1; // really only needed if multiple instances of same type.
481 } module_arg_opt_assignment |
482 attr wire_type range TOK_ID {
483 AstNode *node = $2;
484 node->str = *$4;
485 SET_AST_NODE_LOC(node, @4, @4);
486 node->port_id = ++port_counter;
487 if ($3 != NULL)
488 node->children.push_back($3);
489 if (!node->is_input && !node->is_output)
490 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
491 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
492 frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
493 ast_stack.back()->children.push_back(node);
494 append_attr(node, $1);
495 delete $4;
496 } module_arg_opt_assignment |
497 '.' '.' '.' {
498 do_not_require_port_stubs = true;
499 };
500
501 package:
502 attr TOK_PACKAGE {
503 enterTypeScope();
504 } TOK_ID {
505 AstNode *mod = new AstNode(AST_PACKAGE);
506 ast_stack.back()->children.push_back(mod);
507 ast_stack.push_back(mod);
508 current_ast_mod = mod;
509 mod->str = *$4;
510 append_attr(mod, $1);
511 } ';' package_body TOK_ENDPACKAGE {
512 ast_stack.pop_back();
513 current_ast_mod = NULL;
514 exitTypeScope();
515 };
516
517 package_body:
518 package_body package_body_stmt
519 | // optional
520 ;
521
522 package_body_stmt:
523 typedef_decl |
524 localparam_decl |
525 param_decl;
526
527 interface:
528 TOK_INTERFACE {
529 enterTypeScope();
530 } TOK_ID {
531 do_not_require_port_stubs = false;
532 AstNode *intf = new AstNode(AST_INTERFACE);
533 ast_stack.back()->children.push_back(intf);
534 ast_stack.push_back(intf);
535 current_ast_mod = intf;
536 port_stubs.clear();
537 port_counter = 0;
538 intf->str = *$3;
539 delete $3;
540 } module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
541 if (port_stubs.size() != 0)
542 frontend_verilog_yyerror("Missing details for module port `%s'.",
543 port_stubs.begin()->first.c_str());
544 ast_stack.pop_back();
545 log_assert(ast_stack.size() == 1);
546 current_ast_mod = NULL;
547 exitTypeScope();
548 };
549
550 interface_body:
551 interface_body interface_body_stmt |;
552
553 interface_body_stmt:
554 param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
555 modport_stmt;
556
557 non_opt_delay:
558 '#' TOK_ID { delete $2; } |
559 '#' TOK_CONSTVAL { delete $2; } |
560 '#' TOK_REALVAL { delete $2; } |
561 '#' '(' expr ')' { delete $3; } |
562 '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
563
564 delay:
565 non_opt_delay | /* empty */;
566
567 wire_type:
568 {
569 astbuf3 = new AstNode(AST_WIRE);
570 current_wire_rand = false;
571 current_wire_const = false;
572 } wire_type_token_list {
573 $$ = astbuf3;
574 SET_RULE_LOC(@$, @2, @$);
575 };
576
577 wire_type_token_list:
578 wire_type_token |
579 wire_type_token_list wire_type_token |
580 wire_type_token_io |
581 hierarchical_type_id {
582 astbuf3->is_custom_type = true;
583 astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
584 astbuf3->children.back()->str = *$1;
585 };
586
587 wire_type_token_io:
588 TOK_INPUT {
589 astbuf3->is_input = true;
590 } |
591 TOK_OUTPUT {
592 astbuf3->is_output = true;
593 } |
594 TOK_INOUT {
595 astbuf3->is_input = true;
596 astbuf3->is_output = true;
597 };
598
599 wire_type_token:
600 TOK_WIRE {
601 } |
602 TOK_WOR {
603 astbuf3->is_wor = true;
604 } |
605 TOK_WAND {
606 astbuf3->is_wand = true;
607 } |
608 TOK_REG {
609 astbuf3->is_reg = true;
610 } |
611 TOK_LOGIC {
612 astbuf3->is_logic = true;
613 } |
614 TOK_VAR {
615 astbuf3->is_logic = true;
616 } |
617 TOK_INTEGER {
618 astbuf3->is_reg = true;
619 astbuf3->range_left = 31;
620 astbuf3->range_right = 0;
621 astbuf3->is_signed = true;
622 } |
623 TOK_GENVAR {
624 astbuf3->type = AST_GENVAR;
625 astbuf3->is_reg = true;
626 astbuf3->is_signed = true;
627 astbuf3->range_left = 31;
628 astbuf3->range_right = 0;
629 } |
630 TOK_SIGNED {
631 astbuf3->is_signed = true;
632 } |
633 TOK_RAND {
634 current_wire_rand = true;
635 } |
636 TOK_CONST {
637 current_wire_const = true;
638 };
639
640 non_opt_range:
641 '[' expr ':' expr ']' {
642 $$ = new AstNode(AST_RANGE);
643 $$->children.push_back($2);
644 $$->children.push_back($4);
645 } |
646 '[' expr TOK_POS_INDEXED expr ']' {
647 $$ = new AstNode(AST_RANGE);
648 AstNode *expr = new AstNode(AST_SELFSZ, $2);
649 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
650 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
651 } |
652 '[' expr TOK_NEG_INDEXED expr ']' {
653 $$ = new AstNode(AST_RANGE);
654 AstNode *expr = new AstNode(AST_SELFSZ, $2);
655 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
656 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
657 } |
658 '[' expr ']' {
659 $$ = new AstNode(AST_RANGE);
660 $$->children.push_back($2);
661 };
662
663 non_opt_multirange:
664 non_opt_range non_opt_range {
665 $$ = new AstNode(AST_MULTIRANGE, $1, $2);
666 } |
667 non_opt_multirange non_opt_range {
668 $$ = $1;
669 $$->children.push_back($2);
670 };
671
672 range:
673 non_opt_range {
674 $$ = $1;
675 } |
676 /* empty */ {
677 $$ = NULL;
678 };
679
680 range_or_multirange:
681 range { $$ = $1; } |
682 non_opt_multirange { $$ = $1; };
683
684 range_or_signed_int:
685 range {
686 $$ = $1;
687 } |
688 TOK_INTEGER {
689 $$ = new AstNode(AST_RANGE);
690 $$->children.push_back(AstNode::mkconst_int(31, true));
691 $$->children.push_back(AstNode::mkconst_int(0, true));
692 $$->is_signed = true;
693 };
694
695 module_body:
696 module_body module_body_stmt |
697 /* the following line makes the generate..endgenrate keywords optional */
698 module_body gen_stmt |
699 /* empty */;
700
701 module_body_stmt:
702 task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
703 enum_decl |
704 always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
705
706 checker_decl:
707 TOK_CHECKER TOK_ID ';' {
708 AstNode *node = new AstNode(AST_GENBLOCK);
709 node->str = *$2;
710 ast_stack.back()->children.push_back(node);
711 ast_stack.push_back(node);
712 } module_body TOK_ENDCHECKER {
713 delete $2;
714 ast_stack.pop_back();
715 };
716
717 task_func_decl:
718 attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
719 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
720 current_function_or_task->str = *$4;
721 append_attr(current_function_or_task, $1);
722 ast_stack.back()->children.push_back(current_function_or_task);
723 delete $3;
724 delete $4;
725 } opt_dpi_function_args ';' {
726 current_function_or_task = NULL;
727 } |
728 attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
729 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
730 current_function_or_task->str = *$6;
731 append_attr(current_function_or_task, $1);
732 ast_stack.back()->children.push_back(current_function_or_task);
733 delete $3;
734 delete $5;
735 delete $6;
736 } opt_dpi_function_args ';' {
737 current_function_or_task = NULL;
738 } |
739 attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
740 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
741 current_function_or_task->str = *$8;
742 append_attr(current_function_or_task, $1);
743 ast_stack.back()->children.push_back(current_function_or_task);
744 delete $3;
745 delete $5;
746 delete $7;
747 delete $8;
748 } opt_dpi_function_args ';' {
749 current_function_or_task = NULL;
750 } |
751 attr TOK_TASK opt_automatic TOK_ID {
752 current_function_or_task = new AstNode(AST_TASK);
753 current_function_or_task->str = *$4;
754 append_attr(current_function_or_task, $1);
755 ast_stack.back()->children.push_back(current_function_or_task);
756 ast_stack.push_back(current_function_or_task);
757 current_function_or_task_port_id = 1;
758 delete $4;
759 } task_func_args_opt ';' task_func_body TOK_ENDTASK {
760 current_function_or_task = NULL;
761 ast_stack.pop_back();
762 } |
763 attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID {
764 current_function_or_task = new AstNode(AST_FUNCTION);
765 current_function_or_task->str = *$6;
766 append_attr(current_function_or_task, $1);
767 ast_stack.back()->children.push_back(current_function_or_task);
768 ast_stack.push_back(current_function_or_task);
769 AstNode *outreg = new AstNode(AST_WIRE);
770 outreg->str = *$6;
771 outreg->is_signed = $4;
772 outreg->is_reg = true;
773 if ($5 != NULL) {
774 outreg->children.push_back($5);
775 outreg->is_signed = $4 || $5->is_signed;
776 $5->is_signed = false;
777 }
778 current_function_or_task->children.push_back(outreg);
779 current_function_or_task_port_id = 1;
780 delete $6;
781 } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
782 current_function_or_task = NULL;
783 ast_stack.pop_back();
784 };
785
786 dpi_function_arg:
787 TOK_ID TOK_ID {
788 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
789 delete $1;
790 delete $2;
791 } |
792 TOK_ID {
793 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
794 delete $1;
795 };
796
797 opt_dpi_function_args:
798 '(' dpi_function_args ')' |
799 /* empty */;
800
801 dpi_function_args:
802 dpi_function_args ',' dpi_function_arg |
803 dpi_function_args ',' |
804 dpi_function_arg |
805 /* empty */;
806
807 opt_automatic:
808 TOK_AUTOMATIC |
809 /* empty */;
810
811 opt_signed:
812 TOK_SIGNED {
813 $$ = true;
814 } |
815 /* empty */ {
816 $$ = false;
817 };
818
819 task_func_args_opt:
820 '(' ')' | /* empty */ | '(' {
821 albuf = nullptr;
822 astbuf1 = nullptr;
823 astbuf2 = nullptr;
824 } task_func_args optional_comma {
825 delete astbuf1;
826 if (astbuf2 != NULL)
827 delete astbuf2;
828 free_attr(albuf);
829 } ')';
830
831 task_func_args:
832 task_func_port | task_func_args ',' task_func_port;
833
834 task_func_port:
835 attr wire_type range {
836 if (albuf) {
837 delete astbuf1;
838 if (astbuf2 != NULL)
839 delete astbuf2;
840 free_attr(albuf);
841 }
842 albuf = $1;
843 astbuf1 = $2;
844 astbuf2 = $3;
845 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
846 if (astbuf2) {
847 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions (task/function arguments)");
848 } else {
849 astbuf2 = new AstNode(AST_RANGE);
850 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
851 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
852 }
853 }
854 if (astbuf2 && astbuf2->children.size() != 2)
855 frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
856 } wire_name |
857 {
858 if (!astbuf1) {
859 if (!sv_mode)
860 frontend_verilog_yyerror("task/function argument direction missing");
861 albuf = new dict<IdString, AstNode*>;
862 astbuf1 = new AstNode(AST_WIRE);
863 current_wire_rand = false;
864 current_wire_const = false;
865 astbuf1->is_input = true;
866 astbuf2 = NULL;
867 }
868 } wire_name;
869
870 task_func_body:
871 task_func_body behavioral_stmt |
872 /* empty */;
873
874 /*************************** specify parser ***************************/
875
876 specify_block:
877 TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
878
879 specify_item_list:
880 specify_item specify_item_list |
881 /* empty */;
882
883 specify_item:
884 specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
885 AstNode *en_expr = $1;
886 char specify_edge = $3;
887 AstNode *src_expr = $4;
888 string *oper = $5;
889 specify_target *target = $6;
890 specify_rise_fall *timing = $9;
891
892 if (specify_edge != 0 && target->dat == nullptr)
893 frontend_verilog_yyerror("Found specify edge but no data spec.\n");
894
895 AstNode *cell = new AstNode(AST_CELL);
896 ast_stack.back()->children.push_back(cell);
897 cell->str = stringf("$specify$%d", autoidx++);
898 cell->children.push_back(new AstNode(AST_CELLTYPE));
899 cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
900 SET_AST_NODE_LOC(cell, en_expr ? @1 : @2, @10);
901
902 char oper_polarity = 0;
903 char oper_type = oper->at(0);
904
905 if (oper->size() == 3) {
906 oper_polarity = oper->at(0);
907 oper_type = oper->at(1);
908 }
909
910 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
911 cell->children.back()->str = "\\FULL";
912
913 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
914 cell->children.back()->str = "\\SRC_DST_PEN";
915
916 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
917 cell->children.back()->str = "\\SRC_DST_POL";
918
919 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
920 cell->children.back()->str = "\\T_RISE_MIN";
921
922 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
923 cell->children.back()->str = "\\T_RISE_TYP";
924
925 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
926 cell->children.back()->str = "\\T_RISE_MAX";
927
928 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
929 cell->children.back()->str = "\\T_FALL_MIN";
930
931 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
932 cell->children.back()->str = "\\T_FALL_TYP";
933
934 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
935 cell->children.back()->str = "\\T_FALL_MAX";
936
937 cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
938 cell->children.back()->str = "\\EN";
939
940 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
941 cell->children.back()->str = "\\SRC";
942
943 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
944 cell->children.back()->str = "\\DST";
945
946 if (target->dat)
947 {
948 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
949 cell->children.back()->str = "\\EDGE_EN";
950
951 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
952 cell->children.back()->str = "\\EDGE_POL";
953
954 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
955 cell->children.back()->str = "\\DAT_DST_PEN";
956
957 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
958 cell->children.back()->str = "\\DAT_DST_POL";
959
960 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
961 cell->children.back()->str = "\\DAT";
962 }
963
964 delete oper;
965 delete target;
966 delete timing;
967 } |
968 TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' specify_triple specify_opt_triple ')' ';' {
969 if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
970 *$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
971 frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
972
973 AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
974 AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
975 AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
976
977 AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
978 AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
979 AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
980
981 specify_triple *limit = $11;
982 specify_triple *limit2 = $12;
983
984 AstNode *cell = new AstNode(AST_CELL);
985 ast_stack.back()->children.push_back(cell);
986 cell->str = stringf("$specify$%d", autoidx++);
987 cell->children.push_back(new AstNode(AST_CELLTYPE));
988 cell->children.back()->str = "$specrule";
989 SET_AST_NODE_LOC(cell, @1, @14);
990
991 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
992 cell->children.back()->str = "\\TYPE";
993
994 cell->children.push_back(new AstNode(AST_PARASET, limit->t_min));
995 cell->children.back()->str = "\\T_LIMIT_MIN";
996
997 cell->children.push_back(new AstNode(AST_PARASET, limit->t_avg));
998 cell->children.back()->str = "\\T_LIMIT_TYP";
999
1000 cell->children.push_back(new AstNode(AST_PARASET, limit->t_max));
1001 cell->children.back()->str = "\\T_LIMIT_MAX";
1002
1003 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_min : AstNode::mkconst_int(0, true)));
1004 cell->children.back()->str = "\\T_LIMIT2_MIN";
1005
1006 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_avg : AstNode::mkconst_int(0, true)));
1007 cell->children.back()->str = "\\T_LIMIT2_TYP";
1008
1009 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_max : AstNode::mkconst_int(0, true)));
1010 cell->children.back()->str = "\\T_LIMIT2_MAX";
1011
1012 cell->children.push_back(new AstNode(AST_PARASET, src_pen));
1013 cell->children.back()->str = "\\SRC_PEN";
1014
1015 cell->children.push_back(new AstNode(AST_PARASET, src_pol));
1016 cell->children.back()->str = "\\SRC_POL";
1017
1018 cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
1019 cell->children.back()->str = "\\DST_PEN";
1020
1021 cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
1022 cell->children.back()->str = "\\DST_POL";
1023
1024 cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
1025 cell->children.back()->str = "\\SRC_EN";
1026
1027 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
1028 cell->children.back()->str = "\\SRC";
1029
1030 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
1031 cell->children.back()->str = "\\DST_EN";
1032
1033 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
1034 cell->children.back()->str = "\\DST";
1035
1036 delete $1;
1037 };
1038
1039 specify_opt_triple:
1040 ',' specify_triple {
1041 $$ = $2;
1042 } |
1043 /* empty */ {
1044 $$ = nullptr;
1045 };
1046
1047 specify_if:
1048 TOK_IF '(' expr ')' {
1049 $$ = $3;
1050 } |
1051 /* empty */ {
1052 $$ = nullptr;
1053 };
1054
1055 specify_condition:
1056 TOK_SPECIFY_AND expr {
1057 $$ = $2;
1058 } |
1059 /* empty */ {
1060 $$ = nullptr;
1061 };
1062
1063 specify_target:
1064 expr {
1065 $$ = new specify_target;
1066 $$->polarity_op = 0;
1067 $$->dst = $1;
1068 $$->dat = nullptr;
1069 } |
1070 '(' expr ':' expr ')'{
1071 $$ = new specify_target;
1072 $$->polarity_op = 0;
1073 $$->dst = $2;
1074 $$->dat = $4;
1075 } |
1076 '(' expr TOK_NEG_INDEXED expr ')'{
1077 $$ = new specify_target;
1078 $$->polarity_op = '-';
1079 $$->dst = $2;
1080 $$->dat = $4;
1081 } |
1082 '(' expr TOK_POS_INDEXED expr ')'{
1083 $$ = new specify_target;
1084 $$->polarity_op = '+';
1085 $$->dst = $2;
1086 $$->dat = $4;
1087 };
1088
1089 specify_edge:
1090 TOK_POSEDGE { $$ = 'p'; } |
1091 TOK_NEGEDGE { $$ = 'n'; } |
1092 { $$ = 0; };
1093
1094 specify_rise_fall:
1095 specify_triple {
1096 $$ = new specify_rise_fall;
1097 $$->rise = *$1;
1098 $$->fall.t_min = $1->t_min->clone();
1099 $$->fall.t_avg = $1->t_avg->clone();
1100 $$->fall.t_max = $1->t_max->clone();
1101 delete $1;
1102 } |
1103 '(' specify_triple ',' specify_triple ')' {
1104 $$ = new specify_rise_fall;
1105 $$->rise = *$2;
1106 $$->fall = *$4;
1107 delete $2;
1108 delete $4;
1109 } |
1110 '(' specify_triple ',' specify_triple ',' specify_triple ')' {
1111 $$ = new specify_rise_fall;
1112 $$->rise = *$2;
1113 $$->fall = *$4;
1114 delete $2;
1115 delete $4;
1116 delete $6;
1117 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1118 } |
1119 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1120 $$ = new specify_rise_fall;
1121 $$->rise = *$2;
1122 $$->fall = *$4;
1123 delete $2;
1124 delete $4;
1125 delete $6;
1126 delete $8;
1127 delete $10;
1128 delete $12;
1129 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1130 } |
1131 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1132 $$ = new specify_rise_fall;
1133 $$->rise = *$2;
1134 $$->fall = *$4;
1135 delete $2;
1136 delete $4;
1137 delete $6;
1138 delete $8;
1139 delete $10;
1140 delete $12;
1141 delete $14;
1142 delete $16;
1143 delete $18;
1144 delete $20;
1145 delete $22;
1146 delete $24;
1147 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1148 }
1149
1150 specify_triple:
1151 expr {
1152 $$ = new specify_triple;
1153 $$->t_min = $1;
1154 $$->t_avg = $1->clone();
1155 $$->t_max = $1->clone();
1156 } |
1157 expr ':' expr ':' expr {
1158 $$ = new specify_triple;
1159 $$->t_min = $1;
1160 $$->t_avg = $3;
1161 $$->t_max = $5;
1162 };
1163
1164 /******************** ignored specify parser **************************/
1165
1166 ignored_specify_block:
1167 TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
1168 TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
1169
1170 ignored_specify_item_opt:
1171 ignored_specify_item_opt ignored_specify_item |
1172 ignored_specify_item ;
1173
1174 ignored_specify_item:
1175 specparam_declaration
1176 // | pulsestyle_declaration
1177 // | showcancelled_declaration
1178 | path_declaration
1179 | system_timing_declaration
1180 ;
1181
1182 specparam_declaration:
1183 TOK_SPECPARAM list_of_specparam_assignments ';' |
1184 TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ;
1185
1186 // IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match
1187 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
1188 // exxxxtending this for SV specparam would change this anyhow
1189 specparam_range:
1190 '[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
1191
1192 list_of_specparam_assignments:
1193 specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
1194
1195 specparam_assignment:
1196 ignspec_id '=' ignspec_expr ;
1197
1198 ignspec_opt_cond:
1199 TOK_IF '(' ignspec_expr ')' | /* empty */;
1200
1201 path_declaration :
1202 simple_path_declaration ';'
1203 // | edge_sensitive_path_declaration
1204 // | state_dependent_path_declaration
1205 ;
1206
1207 simple_path_declaration :
1208 ignspec_opt_cond parallel_path_description '=' path_delay_value |
1209 ignspec_opt_cond full_path_description '=' path_delay_value
1210 ;
1211
1212 path_delay_value :
1213 '(' ignspec_expr list_of_path_delay_extra_expressions ')'
1214 | ignspec_expr
1215 | ignspec_expr list_of_path_delay_extra_expressions
1216 ;
1217
1218 list_of_path_delay_extra_expressions :
1219 ',' ignspec_expr
1220 | ',' ignspec_expr list_of_path_delay_extra_expressions
1221 ;
1222
1223 specify_edge_identifier :
1224 TOK_POSEDGE | TOK_NEGEDGE ;
1225
1226 parallel_path_description :
1227 '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
1228 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
1229 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
1230
1231 full_path_description :
1232 '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
1233 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
1234 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
1235
1236 // This was broken into 2 rules to solve shift/reduce conflicts
1237 list_of_path_inputs :
1238 specify_input_terminal_descriptor opt_polarity_operator |
1239 specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
1240
1241 more_path_inputs :
1242 ',' specify_input_terminal_descriptor |
1243 more_path_inputs ',' specify_input_terminal_descriptor ;
1244
1245 list_of_path_outputs :
1246 specify_output_terminal_descriptor |
1247 list_of_path_outputs ',' specify_output_terminal_descriptor ;
1248
1249 opt_polarity_operator :
1250 '+'
1251 | '-'
1252 | ;
1253
1254 // Good enough for the time being
1255 specify_input_terminal_descriptor :
1256 ignspec_id ;
1257
1258 // Good enough for the time being
1259 specify_output_terminal_descriptor :
1260 ignspec_id ;
1261
1262 system_timing_declaration :
1263 ignspec_id '(' system_timing_args ')' ';' ;
1264
1265 system_timing_arg :
1266 TOK_POSEDGE ignspec_id |
1267 TOK_NEGEDGE ignspec_id |
1268 ignspec_expr ;
1269
1270 system_timing_args :
1271 system_timing_arg |
1272 system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
1273 system_timing_args ',' system_timing_arg ;
1274
1275 // for the time being this is OK, but we may write our own expr here.
1276 // as I'm not sure it is legal to use a full expr here (probably not)
1277 // On the other hand, other rules requiring constant expressions also use 'expr'
1278 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
1279 ignspec_constant_expression:
1280 expr { delete $1; };
1281
1282 ignspec_expr:
1283 expr { delete $1; } |
1284 expr ':' expr ':' expr {
1285 delete $1;
1286 delete $3;
1287 delete $5;
1288 };
1289
1290 ignspec_id:
1291 TOK_ID { delete $1; }
1292 range_or_multirange { delete $3; };
1293
1294 /**********************************************************************/
1295
1296 param_signed:
1297 TOK_SIGNED {
1298 astbuf1->is_signed = true;
1299 } | /* empty */;
1300
1301 param_integer:
1302 TOK_INTEGER {
1303 if (astbuf1->children.size() != 1)
1304 frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
1305 astbuf1->children.push_back(new AstNode(AST_RANGE));
1306 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
1307 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
1308 astbuf1->is_signed = true;
1309 } | /* empty */;
1310
1311 param_real:
1312 TOK_REAL {
1313 if (astbuf1->children.size() != 1)
1314 frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
1315 astbuf1->children.push_back(new AstNode(AST_REALVALUE));
1316 } | /* empty */;
1317
1318 param_range:
1319 range {
1320 if ($1 != NULL) {
1321 if (astbuf1->children.size() != 1)
1322 frontend_verilog_yyerror("integer/real parameters should not have a range.");
1323 astbuf1->children.push_back($1);
1324 }
1325 };
1326
1327 param_type:
1328 param_signed param_integer param_real param_range |
1329 hierarchical_type_id {
1330 astbuf1->is_custom_type = true;
1331 astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
1332 astbuf1->children.back()->str = *$1;
1333 };
1334
1335 param_decl:
1336 attr TOK_PARAMETER {
1337 astbuf1 = new AstNode(AST_PARAMETER);
1338 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1339 append_attr(astbuf1, $1);
1340 } param_type param_decl_list ';' {
1341 delete astbuf1;
1342 };
1343
1344 localparam_decl:
1345 attr TOK_LOCALPARAM {
1346 astbuf1 = new AstNode(AST_LOCALPARAM);
1347 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1348 append_attr(astbuf1, $1);
1349 } param_type param_decl_list ';' {
1350 delete astbuf1;
1351 };
1352
1353 param_decl_list:
1354 single_param_decl | param_decl_list ',' single_param_decl;
1355
1356 single_param_decl:
1357 TOK_ID '=' expr {
1358 AstNode *node;
1359 if (astbuf1 == nullptr) {
1360 if (!sv_mode)
1361 frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword");
1362 node = new AstNode(AST_PARAMETER);
1363 node->children.push_back(AstNode::mkconst_int(0, true));
1364 } else {
1365 node = astbuf1->clone();
1366 }
1367 node->str = *$1;
1368 delete node->children[0];
1369 node->children[0] = $3;
1370 ast_stack.back()->children.push_back(node);
1371 delete $1;
1372 };
1373
1374 defparam_decl:
1375 TOK_DEFPARAM defparam_decl_list ';';
1376
1377 defparam_decl_list:
1378 single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
1379
1380 single_defparam_decl:
1381 range rvalue '=' expr {
1382 AstNode *node = new AstNode(AST_DEFPARAM);
1383 node->children.push_back($2);
1384 node->children.push_back($4);
1385 if ($1 != NULL)
1386 node->children.push_back($1);
1387 ast_stack.back()->children.push_back(node);
1388 };
1389
1390 enum_type: TOK_ENUM {
1391 static int enum_count;
1392 // create parent node for the enum
1393 astbuf2 = new AstNode(AST_ENUM);
1394 ast_stack.back()->children.push_back(astbuf2);
1395 astbuf2->str = std::string("$enum");
1396 astbuf2->str += std::to_string(enum_count++);
1397 // create the template for the names
1398 astbuf1 = new AstNode(AST_ENUM_ITEM);
1399 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1400 } param_signed enum_base_type '{' enum_name_list '}' { // create template for the enum vars
1401 auto tnode = astbuf1->clone();
1402 delete astbuf1;
1403 astbuf1 = tnode;
1404 tnode->type = AST_WIRE;
1405 tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
1406 // drop constant but keep any range
1407 delete tnode->children[0];
1408 tnode->children.erase(tnode->children.begin()); }
1409 ;
1410
1411 enum_base_type: int_vec param_range
1412 | int_atom
1413 | /* nothing */ {astbuf1->is_reg = true; addRange(astbuf1); }
1414 ;
1415
1416 int_atom: TOK_INTEGER {astbuf1->is_reg=true; addRange(astbuf1); } // probably should do byte, range [7:0] here
1417 ;
1418
1419 int_vec: TOK_REG {astbuf1->is_reg = true;}
1420 | TOK_LOGIC {astbuf1->is_logic = true;}
1421 ;
1422
1423 enum_name_list:
1424 enum_name_decl
1425 | enum_name_list ',' enum_name_decl
1426 ;
1427
1428 enum_name_decl:
1429 TOK_ID opt_enum_init {
1430 // put in fn
1431 log_assert(astbuf1);
1432 log_assert(astbuf2);
1433 auto node = astbuf1->clone();
1434 node->str = *$1;
1435 delete $1;
1436 delete node->children[0];
1437 node->children[0] = $2 ?: new AstNode(AST_NONE);
1438 astbuf2->children.push_back(node);
1439 }
1440 ;
1441
1442 opt_enum_init:
1443 '=' basic_expr { $$ = $2; } // TODO: restrict this
1444 | /* optional */ { $$ = NULL; }
1445 ;
1446
1447 enum_var_list:
1448 enum_var
1449 | enum_var_list ',' enum_var
1450 ;
1451
1452 enum_var: TOK_ID {
1453 log_assert(astbuf1);
1454 log_assert(astbuf2);
1455 auto node = astbuf1->clone();
1456 ast_stack.back()->children.push_back(node);
1457 node->str = *$1;
1458 delete $1;
1459 node->is_enum = true;
1460 }
1461 ;
1462
1463 enum_decl: enum_type enum_var_list ';' {
1464 //enum_type creates astbuf1 for use by typedef only
1465 delete astbuf1;
1466 }
1467 ;
1468
1469 wire_decl:
1470 attr wire_type range {
1471 albuf = $1;
1472 astbuf1 = $2;
1473 astbuf2 = $3;
1474 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
1475 if (astbuf2) {
1476 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
1477 } else {
1478 astbuf2 = new AstNode(AST_RANGE);
1479 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
1480 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
1481 }
1482 }
1483 if (astbuf2 && astbuf2->children.size() != 2)
1484 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
1485 } delay wire_name_list {
1486 delete astbuf1;
1487 if (astbuf2 != NULL)
1488 delete astbuf2;
1489 free_attr(albuf);
1490 } ';' |
1491 attr TOK_SUPPLY0 TOK_ID {
1492 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1493 ast_stack.back()->children.back()->str = *$3;
1494 append_attr(ast_stack.back()->children.back(), $1);
1495 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
1496 ast_stack.back()->children.back()->children[0]->str = *$3;
1497 delete $3;
1498 } opt_supply_wires ';' |
1499 attr TOK_SUPPLY1 TOK_ID {
1500 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1501 ast_stack.back()->children.back()->str = *$3;
1502 append_attr(ast_stack.back()->children.back(), $1);
1503 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
1504 ast_stack.back()->children.back()->children[0]->str = *$3;
1505 delete $3;
1506 } opt_supply_wires ';';
1507
1508 opt_supply_wires:
1509 /* empty */ |
1510 opt_supply_wires ',' TOK_ID {
1511 AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
1512 AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
1513 wire_node->str = *$3;
1514 assign_node->children[0]->str = *$3;
1515 ast_stack.back()->children.push_back(wire_node);
1516 ast_stack.back()->children.push_back(assign_node);
1517 delete $3;
1518 };
1519
1520 wire_name_list:
1521 wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
1522
1523 wire_name_and_opt_assign:
1524 wire_name {
1525 bool attr_anyconst = false;
1526 bool attr_anyseq = false;
1527 bool attr_allconst = false;
1528 bool attr_allseq = false;
1529 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
1530 delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
1531 ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
1532 attr_anyconst = true;
1533 }
1534 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
1535 delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
1536 ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
1537 attr_anyseq = true;
1538 }
1539 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
1540 delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
1541 ast_stack.back()->children.back()->attributes.erase(ID::allconst);
1542 attr_allconst = true;
1543 }
1544 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
1545 delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
1546 ast_stack.back()->children.back()->attributes.erase(ID::allseq);
1547 attr_allseq = true;
1548 }
1549 if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
1550 AstNode *wire = new AstNode(AST_IDENTIFIER);
1551 AstNode *fcall = new AstNode(AST_FCALL);
1552 wire->str = ast_stack.back()->children.back()->str;
1553 fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
1554 if (attr_anyconst)
1555 fcall->str = "\\$anyconst";
1556 if (attr_anyseq)
1557 fcall->str = "\\$anyseq";
1558 if (attr_allconst)
1559 fcall->str = "\\$allconst";
1560 if (attr_allseq)
1561 fcall->str = "\\$allseq";
1562 fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
1563 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
1564 }
1565 } |
1566 wire_name '=' expr {
1567 AstNode *wire = new AstNode(AST_IDENTIFIER);
1568 wire->str = ast_stack.back()->children.back()->str;
1569 if (astbuf1->is_input) {
1570 if (astbuf1->attributes.count(ID::defaultvalue))
1571 delete astbuf1->attributes.at(ID::defaultvalue);
1572 astbuf1->attributes[ID::defaultvalue] = $3;
1573 }
1574 else if (astbuf1->is_reg || astbuf1->is_logic){
1575 AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
1576 AstNode *block = new AstNode(AST_BLOCK, assign);
1577 AstNode *init = new AstNode(AST_INITIAL, block);
1578
1579 SET_AST_NODE_LOC(assign, @1, @3);
1580 SET_AST_NODE_LOC(block, @1, @3);
1581 SET_AST_NODE_LOC(init, @1, @3);
1582
1583 ast_stack.back()->children.push_back(init);
1584 }
1585 else {
1586 AstNode *assign = new AstNode(AST_ASSIGN, wire, $3);
1587 SET_AST_NODE_LOC(assign, @1, @3);
1588 ast_stack.back()->children.push_back(assign);
1589 }
1590
1591 };
1592
1593 wire_name:
1594 TOK_ID range_or_multirange {
1595 if (astbuf1 == nullptr)
1596 frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node.");
1597 AstNode *node = astbuf1->clone();
1598 node->str = *$1;
1599 append_attr_clone(node, albuf);
1600 if (astbuf2 != NULL)
1601 node->children.push_back(astbuf2->clone());
1602 if ($2 != NULL) {
1603 if (node->is_input || node->is_output)
1604 frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
1605 if (!astbuf2 && !node->is_custom_type) {
1606 AstNode *rng = new AstNode(AST_RANGE);
1607 rng->children.push_back(AstNode::mkconst_int(0, true));
1608 rng->children.push_back(AstNode::mkconst_int(0, true));
1609 node->children.push_back(rng);
1610 }
1611 node->type = AST_MEMORY;
1612 auto *rangeNode = $2;
1613 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
1614 // SV array size [n], rewrite as [n-1:0]
1615 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
1616 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
1617 }
1618 node->children.push_back(rangeNode);
1619 }
1620 if (current_function_or_task == NULL) {
1621 if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
1622 port_stubs[*$1] = ++port_counter;
1623 }
1624 if (port_stubs.count(*$1) != 0) {
1625 if (!node->is_input && !node->is_output)
1626 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
1627 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
1628 frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
1629 node->port_id = port_stubs[*$1];
1630 port_stubs.erase(*$1);
1631 } else {
1632 if (node->is_input || node->is_output)
1633 frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
1634 }
1635 } else {
1636 if (node->is_input || node->is_output)
1637 node->port_id = current_function_or_task_port_id++;
1638 }
1639 //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
1640 SET_AST_NODE_LOC(node, @1, @1);
1641 ast_stack.back()->children.push_back(node);
1642
1643 delete $1;
1644 };
1645
1646 assign_stmt:
1647 TOK_ASSIGN delay assign_expr_list ';';
1648
1649 assign_expr_list:
1650 assign_expr | assign_expr_list ',' assign_expr;
1651
1652 assign_expr:
1653 lvalue '=' expr {
1654 AstNode *node = new AstNode(AST_ASSIGN, $1, $3);
1655 SET_AST_NODE_LOC(node, @$, @$);
1656 ast_stack.back()->children.push_back(node);
1657 };
1658
1659 type_name: TOK_ID // first time seen
1660 | TOK_USER_TYPE { if (isInLocalScope($1)) frontend_verilog_yyerror("Duplicate declaration of TYPEDEF '%s'", $1->c_str()+1); }
1661 ;
1662
1663 typedef_decl:
1664 TOK_TYPEDEF wire_type range type_name range_or_multirange ';' {
1665 astbuf1 = $2;
1666 astbuf2 = $3;
1667 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
1668 if (astbuf2) {
1669 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
1670 } else {
1671 astbuf2 = new AstNode(AST_RANGE);
1672 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
1673 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
1674 }
1675 }
1676 if (astbuf2 && astbuf2->children.size() != 2)
1677 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
1678 if (astbuf2)
1679 astbuf1->children.push_back(astbuf2);
1680
1681 if ($5 != NULL) {
1682 if (!astbuf2) {
1683 AstNode *rng = new AstNode(AST_RANGE);
1684 rng->children.push_back(AstNode::mkconst_int(0, true));
1685 rng->children.push_back(AstNode::mkconst_int(0, true));
1686 astbuf1->children.push_back(rng);
1687 }
1688 astbuf1->type = AST_MEMORY;
1689 auto *rangeNode = $5;
1690 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
1691 // SV array size [n], rewrite as [n-1:0]
1692 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
1693 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
1694 }
1695 astbuf1->children.push_back(rangeNode);
1696 }
1697 addTypedefNode($4, astbuf1);
1698 } |
1699 TOK_TYPEDEF enum_type type_name ';' {
1700 addTypedefNode($3, astbuf1);
1701 }
1702 ;
1703
1704 cell_stmt:
1705 attr TOK_ID {
1706 astbuf1 = new AstNode(AST_CELL);
1707 append_attr(astbuf1, $1);
1708 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
1709 astbuf1->children[0]->str = *$2;
1710 delete $2;
1711 } cell_parameter_list_opt cell_list ';' {
1712 delete astbuf1;
1713 } |
1714 attr tok_prim_wrapper delay {
1715 astbuf1 = new AstNode(AST_PRIMITIVE);
1716 astbuf1->str = *$2;
1717 append_attr(astbuf1, $1);
1718 delete $2;
1719 } prim_list ';' {
1720 delete astbuf1;
1721 };
1722
1723 tok_prim_wrapper:
1724 TOK_PRIMITIVE {
1725 $$ = $1;
1726 } |
1727 TOK_OR {
1728 $$ = new std::string("or");
1729 };
1730
1731 cell_list:
1732 single_cell |
1733 cell_list ',' single_cell;
1734
1735 single_cell:
1736 TOK_ID {
1737 astbuf2 = astbuf1->clone();
1738 if (astbuf2->type != AST_PRIMITIVE)
1739 astbuf2->str = *$1;
1740 delete $1;
1741 ast_stack.back()->children.push_back(astbuf2);
1742 } '(' cell_port_list ')' {
1743 SET_AST_NODE_LOC(astbuf2, @1, @$);
1744 } |
1745 TOK_ID non_opt_range {
1746 astbuf2 = astbuf1->clone();
1747 if (astbuf2->type != AST_PRIMITIVE)
1748 astbuf2->str = *$1;
1749 delete $1;
1750 ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
1751 } '(' cell_port_list ')'{
1752 SET_AST_NODE_LOC(astbuf2, @1, @$);
1753 };
1754
1755 prim_list:
1756 single_prim |
1757 prim_list ',' single_prim;
1758
1759 single_prim:
1760 single_cell |
1761 /* no name */ {
1762 astbuf2 = astbuf1->clone();
1763 ast_stack.back()->children.push_back(astbuf2);
1764 } '(' cell_port_list ')' {
1765 SET_AST_NODE_LOC(astbuf2, @1, @$);
1766 }
1767
1768 cell_parameter_list_opt:
1769 '#' '(' cell_parameter_list ')' | /* empty */;
1770
1771 cell_parameter_list:
1772 cell_parameter | cell_parameter_list ',' cell_parameter;
1773
1774 cell_parameter:
1775 /* empty */ |
1776 expr {
1777 AstNode *node = new AstNode(AST_PARASET);
1778 astbuf1->children.push_back(node);
1779 node->children.push_back($1);
1780 } |
1781 '.' TOK_ID '(' expr ')' {
1782 AstNode *node = new AstNode(AST_PARASET);
1783 node->str = *$2;
1784 astbuf1->children.push_back(node);
1785 node->children.push_back($4);
1786 delete $2;
1787 };
1788
1789 cell_port_list:
1790 cell_port_list_rules {
1791 // remove empty args from end of list
1792 while (!astbuf2->children.empty()) {
1793 AstNode *node = astbuf2->children.back();
1794 if (node->type != AST_ARGUMENT) break;
1795 if (!node->children.empty()) break;
1796 if (!node->str.empty()) break;
1797 astbuf2->children.pop_back();
1798 delete node;
1799 }
1800
1801 // check port types
1802 bool has_positional_args = false;
1803 bool has_named_args = false;
1804 for (auto node : astbuf2->children) {
1805 if (node->type != AST_ARGUMENT) continue;
1806 if (node->str.empty())
1807 has_positional_args = true;
1808 else
1809 has_named_args = true;
1810 }
1811
1812 if (has_positional_args && has_named_args)
1813 frontend_verilog_yyerror("Mix of positional and named cell ports.");
1814 };
1815
1816 cell_port_list_rules:
1817 cell_port | cell_port_list_rules ',' cell_port;
1818
1819 cell_port:
1820 attr {
1821 AstNode *node = new AstNode(AST_ARGUMENT);
1822 astbuf2->children.push_back(node);
1823 free_attr($1);
1824 } |
1825 attr expr {
1826 AstNode *node = new AstNode(AST_ARGUMENT);
1827 astbuf2->children.push_back(node);
1828 node->children.push_back($2);
1829 free_attr($1);
1830 } |
1831 attr '.' TOK_ID '(' expr ')' {
1832 AstNode *node = new AstNode(AST_ARGUMENT);
1833 node->str = *$3;
1834 astbuf2->children.push_back(node);
1835 node->children.push_back($5);
1836 delete $3;
1837 free_attr($1);
1838 } |
1839 attr '.' TOK_ID '(' ')' {
1840 AstNode *node = new AstNode(AST_ARGUMENT);
1841 node->str = *$3;
1842 astbuf2->children.push_back(node);
1843 delete $3;
1844 free_attr($1);
1845 } |
1846 attr '.' TOK_ID {
1847 AstNode *node = new AstNode(AST_ARGUMENT);
1848 node->str = *$3;
1849 astbuf2->children.push_back(node);
1850 node->children.push_back(new AstNode(AST_IDENTIFIER));
1851 node->children.back()->str = *$3;
1852 delete $3;
1853 free_attr($1);
1854 } |
1855 attr TOK_WILDCARD_CONNECT {
1856 if (!sv_mode)
1857 frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
1858 astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
1859 };
1860
1861 always_comb_or_latch:
1862 TOK_ALWAYS_COMB {
1863 $$ = false;
1864 } |
1865 TOK_ALWAYS_LATCH {
1866 $$ = true;
1867 };
1868
1869 always_or_always_ff:
1870 TOK_ALWAYS {
1871 $$ = false;
1872 } |
1873 TOK_ALWAYS_FF {
1874 $$ = true;
1875 };
1876
1877 always_stmt:
1878 attr always_or_always_ff {
1879 AstNode *node = new AstNode(AST_ALWAYS);
1880 append_attr(node, $1);
1881 if ($2)
1882 node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
1883 ast_stack.back()->children.push_back(node);
1884 ast_stack.push_back(node);
1885 } always_cond {
1886 AstNode *block = new AstNode(AST_BLOCK);
1887 ast_stack.back()->children.push_back(block);
1888 ast_stack.push_back(block);
1889 } behavioral_stmt {
1890 SET_AST_NODE_LOC(ast_stack.back(), @6, @6);
1891 ast_stack.pop_back();
1892
1893 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
1894 ast_stack.pop_back();
1895
1896 SET_RULE_LOC(@$, @2, @$);
1897 } |
1898 attr always_comb_or_latch {
1899 AstNode *node = new AstNode(AST_ALWAYS);
1900 append_attr(node, $1);
1901 if ($2)
1902 node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
1903 else
1904 node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
1905 ast_stack.back()->children.push_back(node);
1906 ast_stack.push_back(node);
1907 AstNode *block = new AstNode(AST_BLOCK);
1908 ast_stack.back()->children.push_back(block);
1909 ast_stack.push_back(block);
1910 } behavioral_stmt {
1911 ast_stack.pop_back();
1912 ast_stack.pop_back();
1913 } |
1914 attr TOK_INITIAL {
1915 AstNode *node = new AstNode(AST_INITIAL);
1916 append_attr(node, $1);
1917 ast_stack.back()->children.push_back(node);
1918 ast_stack.push_back(node);
1919 AstNode *block = new AstNode(AST_BLOCK);
1920 ast_stack.back()->children.push_back(block);
1921 ast_stack.push_back(block);
1922 } behavioral_stmt {
1923 ast_stack.pop_back();
1924 ast_stack.pop_back();
1925 };
1926
1927 always_cond:
1928 '@' '(' always_events ')' |
1929 '@' '(' '*' ')' |
1930 '@' ATTR_BEGIN ')' |
1931 '@' '(' ATTR_END |
1932 '@' '*' |
1933 /* empty */;
1934
1935 always_events:
1936 always_event |
1937 always_events TOK_OR always_event |
1938 always_events ',' always_event;
1939
1940 always_event:
1941 TOK_POSEDGE expr {
1942 AstNode *node = new AstNode(AST_POSEDGE);
1943 SET_AST_NODE_LOC(node, @1, @1);
1944 ast_stack.back()->children.push_back(node);
1945 node->children.push_back($2);
1946 } |
1947 TOK_NEGEDGE expr {
1948 AstNode *node = new AstNode(AST_NEGEDGE);
1949 SET_AST_NODE_LOC(node, @1, @1);
1950 ast_stack.back()->children.push_back(node);
1951 node->children.push_back($2);
1952 } |
1953 expr {
1954 AstNode *node = new AstNode(AST_EDGE);
1955 ast_stack.back()->children.push_back(node);
1956 node->children.push_back($1);
1957 };
1958
1959 opt_label:
1960 ':' TOK_ID {
1961 $$ = $2;
1962 } |
1963 /* empty */ {
1964 $$ = NULL;
1965 };
1966
1967 opt_sva_label:
1968 TOK_SVA_LABEL ':' {
1969 $$ = $1;
1970 } |
1971 /* empty */ {
1972 $$ = NULL;
1973 };
1974
1975 opt_property:
1976 TOK_PROPERTY {
1977 $$ = true;
1978 } |
1979 TOK_FINAL {
1980 $$ = false;
1981 } |
1982 /* empty */ {
1983 $$ = false;
1984 };
1985
1986 modport_stmt:
1987 TOK_MODPORT TOK_ID {
1988 AstNode *modport = new AstNode(AST_MODPORT);
1989 ast_stack.back()->children.push_back(modport);
1990 ast_stack.push_back(modport);
1991 modport->str = *$2;
1992 delete $2;
1993 } modport_args_opt {
1994 ast_stack.pop_back();
1995 log_assert(ast_stack.size() == 2);
1996 } ';'
1997
1998 modport_args_opt:
1999 '(' ')' | '(' modport_args optional_comma ')';
2000
2001 modport_args:
2002 modport_arg | modport_args ',' modport_arg;
2003
2004 modport_arg:
2005 modport_type_token modport_member |
2006 modport_member
2007
2008 modport_member:
2009 TOK_ID {
2010 AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
2011 ast_stack.back()->children.push_back(modport_member);
2012 modport_member->str = *$1;
2013 modport_member->is_input = current_modport_input;
2014 modport_member->is_output = current_modport_output;
2015 delete $1;
2016 }
2017
2018 modport_type_token:
2019 TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
2020
2021 assert:
2022 opt_sva_label TOK_ASSERT opt_property '(' expr ')' ';' {
2023 if (noassert_mode) {
2024 delete $5;
2025 } else {
2026 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2027 SET_AST_NODE_LOC(node, @1, @6);
2028 if ($1 != nullptr)
2029 node->str = *$1;
2030 ast_stack.back()->children.push_back(node);
2031 }
2032 if ($1 != nullptr)
2033 delete $1;
2034 } |
2035 opt_sva_label TOK_ASSUME opt_property '(' expr ')' ';' {
2036 if (noassume_mode) {
2037 delete $5;
2038 } else {
2039 AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
2040 SET_AST_NODE_LOC(node, @1, @6);
2041 if ($1 != nullptr)
2042 node->str = *$1;
2043 ast_stack.back()->children.push_back(node);
2044 }
2045 if ($1 != nullptr)
2046 delete $1;
2047 } |
2048 opt_sva_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2049 if (noassert_mode) {
2050 delete $6;
2051 } else {
2052 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2053 SET_AST_NODE_LOC(node, @1, @7);
2054 if ($1 != nullptr)
2055 node->str = *$1;
2056 ast_stack.back()->children.push_back(node);
2057 }
2058 if ($1 != nullptr)
2059 delete $1;
2060 } |
2061 opt_sva_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2062 if (noassume_mode) {
2063 delete $6;
2064 } else {
2065 AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
2066 SET_AST_NODE_LOC(node, @1, @7);
2067 if ($1 != nullptr)
2068 node->str = *$1;
2069 ast_stack.back()->children.push_back(node);
2070 }
2071 if ($1 != nullptr)
2072 delete $1;
2073 } |
2074 opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
2075 AstNode *node = new AstNode(AST_COVER, $5);
2076 SET_AST_NODE_LOC(node, @1, @6);
2077 if ($1 != nullptr) {
2078 node->str = *$1;
2079 delete $1;
2080 }
2081 ast_stack.back()->children.push_back(node);
2082 } |
2083 opt_sva_label TOK_COVER opt_property '(' ')' ';' {
2084 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2085 SET_AST_NODE_LOC(node, @1, @5);
2086 if ($1 != nullptr) {
2087 node->str = *$1;
2088 delete $1;
2089 }
2090 ast_stack.back()->children.push_back(node);
2091 } |
2092 opt_sva_label TOK_COVER ';' {
2093 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2094 SET_AST_NODE_LOC(node, @1, @2);
2095 if ($1 != nullptr) {
2096 node->str = *$1;
2097 delete $1;
2098 }
2099 ast_stack.back()->children.push_back(node);
2100 } |
2101 opt_sva_label TOK_RESTRICT opt_property '(' expr ')' ';' {
2102 if (norestrict_mode) {
2103 delete $5;
2104 } else {
2105 AstNode *node = new AstNode(AST_ASSUME, $5);
2106 SET_AST_NODE_LOC(node, @1, @6);
2107 if ($1 != nullptr)
2108 node->str = *$1;
2109 ast_stack.back()->children.push_back(node);
2110 }
2111 if (!$3)
2112 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2113 if ($1 != nullptr)
2114 delete $1;
2115 } |
2116 opt_sva_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2117 if (norestrict_mode) {
2118 delete $6;
2119 } else {
2120 AstNode *node = new AstNode(AST_FAIR, $6);
2121 SET_AST_NODE_LOC(node, @1, @7);
2122 if ($1 != nullptr)
2123 node->str = *$1;
2124 ast_stack.back()->children.push_back(node);
2125 }
2126 if (!$3)
2127 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2128 if ($1 != nullptr)
2129 delete $1;
2130 };
2131
2132 assert_property:
2133 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
2134 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2135 SET_AST_NODE_LOC(node, @1, @6);
2136 ast_stack.back()->children.push_back(node);
2137 if ($1 != nullptr) {
2138 ast_stack.back()->children.back()->str = *$1;
2139 delete $1;
2140 }
2141 } |
2142 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
2143 AstNode *node = new AstNode(AST_ASSUME, $5);
2144 SET_AST_NODE_LOC(node, @1, @6);
2145 ast_stack.back()->children.push_back(node);
2146 if ($1 != nullptr) {
2147 ast_stack.back()->children.back()->str = *$1;
2148 delete $1;
2149 }
2150 } |
2151 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2152 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2153 SET_AST_NODE_LOC(node, @1, @7);
2154 ast_stack.back()->children.push_back(node);
2155 if ($1 != nullptr) {
2156 ast_stack.back()->children.back()->str = *$1;
2157 delete $1;
2158 }
2159 } |
2160 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2161 AstNode *node = new AstNode(AST_FAIR, $6);
2162 SET_AST_NODE_LOC(node, @1, @7);
2163 ast_stack.back()->children.push_back(node);
2164 if ($1 != nullptr) {
2165 ast_stack.back()->children.back()->str = *$1;
2166 delete $1;
2167 }
2168 } |
2169 opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
2170 AstNode *node = new AstNode(AST_COVER, $5);
2171 SET_AST_NODE_LOC(node, @1, @6);
2172 ast_stack.back()->children.push_back(node);
2173 if ($1 != nullptr) {
2174 ast_stack.back()->children.back()->str = *$1;
2175 delete $1;
2176 }
2177 } |
2178 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
2179 if (norestrict_mode) {
2180 delete $5;
2181 } else {
2182 AstNode *node = new AstNode(AST_ASSUME, $5);
2183 SET_AST_NODE_LOC(node, @1, @6);
2184 ast_stack.back()->children.push_back(node);
2185 if ($1 != nullptr) {
2186 ast_stack.back()->children.back()->str = *$1;
2187 delete $1;
2188 }
2189 }
2190 } |
2191 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2192 if (norestrict_mode) {
2193 delete $6;
2194 } else {
2195 AstNode *node = new AstNode(AST_FAIR, $6);
2196 SET_AST_NODE_LOC(node, @1, @7);
2197 ast_stack.back()->children.push_back(node);
2198 if ($1 != nullptr) {
2199 ast_stack.back()->children.back()->str = *$1;
2200 delete $1;
2201 }
2202 }
2203 };
2204
2205 simple_behavioral_stmt:
2206 lvalue '=' delay expr {
2207 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4);
2208 ast_stack.back()->children.push_back(node);
2209 SET_AST_NODE_LOC(node, @1, @4);
2210 } |
2211 lvalue TOK_INCREMENT {
2212 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true)));
2213 ast_stack.back()->children.push_back(node);
2214 SET_AST_NODE_LOC(node, @1, @2);
2215 } |
2216 lvalue TOK_DECREMENT {
2217 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true)));
2218 ast_stack.back()->children.push_back(node);
2219 SET_AST_NODE_LOC(node, @1, @2);
2220 } |
2221 lvalue OP_LE delay expr {
2222 AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4);
2223 ast_stack.back()->children.push_back(node);
2224 SET_AST_NODE_LOC(node, @1, @4);
2225 };
2226
2227 // this production creates the obligatory if-else shift/reduce conflict
2228 behavioral_stmt:
2229 defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
2230 non_opt_delay behavioral_stmt |
2231 simple_behavioral_stmt ';' | ';' |
2232 hierarchical_id attr {
2233 AstNode *node = new AstNode(AST_TCALL);
2234 node->str = *$1;
2235 delete $1;
2236 ast_stack.back()->children.push_back(node);
2237 ast_stack.push_back(node);
2238 append_attr(node, $2);
2239 } opt_arg_list ';'{
2240 ast_stack.pop_back();
2241 } |
2242 TOK_MSG_TASKS attr {
2243 AstNode *node = new AstNode(AST_TCALL);
2244 node->str = *$1;
2245 delete $1;
2246 ast_stack.back()->children.push_back(node);
2247 ast_stack.push_back(node);
2248 append_attr(node, $2);
2249 } opt_arg_list ';'{
2250 ast_stack.pop_back();
2251 } |
2252 attr TOK_BEGIN {
2253 enterTypeScope();
2254 } opt_label {
2255 AstNode *node = new AstNode(AST_BLOCK);
2256 ast_stack.back()->children.push_back(node);
2257 ast_stack.push_back(node);
2258 append_attr(node, $1);
2259 if ($4 != NULL)
2260 node->str = *$4;
2261 } behavioral_stmt_list TOK_END opt_label {
2262 exitTypeScope();
2263 if ($4 != NULL && $8 != NULL && *$4 != *$8)
2264 frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
2265 SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
2266 delete $4;
2267 delete $8;
2268 ast_stack.pop_back();
2269 } |
2270 attr TOK_FOR '(' {
2271 AstNode *node = new AstNode(AST_FOR);
2272 ast_stack.back()->children.push_back(node);
2273 ast_stack.push_back(node);
2274 append_attr(node, $1);
2275 } simple_behavioral_stmt ';' expr {
2276 ast_stack.back()->children.push_back($7);
2277 } ';' simple_behavioral_stmt ')' {
2278 AstNode *block = new AstNode(AST_BLOCK);
2279 ast_stack.back()->children.push_back(block);
2280 ast_stack.push_back(block);
2281 } behavioral_stmt {
2282 SET_AST_NODE_LOC(ast_stack.back(), @13, @13);
2283 ast_stack.pop_back();
2284 SET_AST_NODE_LOC(ast_stack.back(), @2, @13);
2285 ast_stack.pop_back();
2286 } |
2287 attr TOK_WHILE '(' expr ')' {
2288 AstNode *node = new AstNode(AST_WHILE);
2289 ast_stack.back()->children.push_back(node);
2290 ast_stack.push_back(node);
2291 append_attr(node, $1);
2292 AstNode *block = new AstNode(AST_BLOCK);
2293 ast_stack.back()->children.push_back($4);
2294 ast_stack.back()->children.push_back(block);
2295 ast_stack.push_back(block);
2296 } behavioral_stmt {
2297 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2298 ast_stack.pop_back();
2299 ast_stack.pop_back();
2300 } |
2301 attr TOK_REPEAT '(' expr ')' {
2302 AstNode *node = new AstNode(AST_REPEAT);
2303 ast_stack.back()->children.push_back(node);
2304 ast_stack.push_back(node);
2305 append_attr(node, $1);
2306 AstNode *block = new AstNode(AST_BLOCK);
2307 ast_stack.back()->children.push_back($4);
2308 ast_stack.back()->children.push_back(block);
2309 ast_stack.push_back(block);
2310 } behavioral_stmt {
2311 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2312 ast_stack.pop_back();
2313 ast_stack.pop_back();
2314 } |
2315 attr TOK_IF '(' expr ')' {
2316 AstNode *node = new AstNode(AST_CASE);
2317 AstNode *block = new AstNode(AST_BLOCK);
2318 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
2319 SET_AST_NODE_LOC(cond, @4, @4);
2320 ast_stack.back()->children.push_back(node);
2321 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
2322 node->children.push_back(cond);
2323 ast_stack.push_back(node);
2324 ast_stack.push_back(block);
2325 append_attr(node, $1);
2326 } behavioral_stmt {
2327 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2328 } optional_else {
2329 ast_stack.pop_back();
2330 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2331 ast_stack.pop_back();
2332 } |
2333 case_attr case_type '(' expr ')' {
2334 AstNode *node = new AstNode(AST_CASE, $4);
2335 ast_stack.back()->children.push_back(node);
2336 ast_stack.push_back(node);
2337 append_attr(node, $1);
2338 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2339 } opt_synopsys_attr case_body TOK_ENDCASE {
2340 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2341 case_type_stack.pop_back();
2342 ast_stack.pop_back();
2343 };
2344
2345 ;
2346
2347 unique_case_attr:
2348 /* empty */ {
2349 $$ = false;
2350 } |
2351 TOK_PRIORITY case_attr {
2352 $$ = $2;
2353 } |
2354 TOK_UNIQUE case_attr {
2355 $$ = true;
2356 };
2357
2358 case_attr:
2359 attr unique_case_attr {
2360 if ($2) (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false);
2361 $$ = $1;
2362 };
2363
2364 case_type:
2365 TOK_CASE {
2366 case_type_stack.push_back(0);
2367 } |
2368 TOK_CASEX {
2369 case_type_stack.push_back('x');
2370 } |
2371 TOK_CASEZ {
2372 case_type_stack.push_back('z');
2373 };
2374
2375 opt_synopsys_attr:
2376 opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
2377 if (ast_stack.back()->attributes.count(ID::full_case) == 0)
2378 ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
2379 } |
2380 opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
2381 if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
2382 ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
2383 } |
2384 /* empty */;
2385
2386 behavioral_stmt_list:
2387 behavioral_stmt_list behavioral_stmt |
2388 /* empty */;
2389
2390 optional_else:
2391 TOK_ELSE {
2392 AstNode *block = new AstNode(AST_BLOCK);
2393 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
2394 SET_AST_NODE_LOC(cond, @1, @1);
2395
2396 ast_stack.pop_back();
2397 ast_stack.back()->children.push_back(cond);
2398 ast_stack.push_back(block);
2399 } behavioral_stmt {
2400 SET_AST_NODE_LOC(ast_stack.back(), @3, @3);
2401 } |
2402 /* empty */ %prec FAKE_THEN;
2403
2404 case_body:
2405 case_body case_item |
2406 /* empty */;
2407
2408 case_item:
2409 {
2410 AstNode *node = new AstNode(
2411 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2412 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2413 ast_stack.back()->children.push_back(node);
2414 ast_stack.push_back(node);
2415 } case_select {
2416 AstNode *block = new AstNode(AST_BLOCK);
2417 ast_stack.back()->children.push_back(block);
2418 ast_stack.push_back(block);
2419 case_type_stack.push_back(0);
2420 } behavioral_stmt {
2421 case_type_stack.pop_back();
2422 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2423 ast_stack.pop_back();
2424 ast_stack.pop_back();
2425 };
2426
2427 gen_case_body:
2428 gen_case_body gen_case_item |
2429 /* empty */;
2430
2431 gen_case_item:
2432 {
2433 AstNode *node = new AstNode(
2434 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2435 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2436 ast_stack.back()->children.push_back(node);
2437 ast_stack.push_back(node);
2438 } case_select {
2439 case_type_stack.push_back(0);
2440 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2441 } gen_stmt_or_null {
2442 case_type_stack.pop_back();
2443 ast_stack.pop_back();
2444 };
2445
2446 case_select:
2447 case_expr_list ':' |
2448 TOK_DEFAULT;
2449
2450 case_expr_list:
2451 TOK_DEFAULT {
2452 AstNode *node = new AstNode(AST_DEFAULT);
2453 SET_AST_NODE_LOC(node, @1, @1);
2454 ast_stack.back()->children.push_back(node);
2455 } |
2456 TOK_SVA_LABEL {
2457 AstNode *node = new AstNode(AST_IDENTIFIER);
2458 SET_AST_NODE_LOC(node, @1, @1);
2459 ast_stack.back()->children.push_back(node);
2460 ast_stack.back()->children.back()->str = *$1;
2461 delete $1;
2462 } |
2463 expr {
2464 ast_stack.back()->children.push_back($1);
2465 } |
2466 case_expr_list ',' expr {
2467 ast_stack.back()->children.push_back($3);
2468 };
2469
2470 rvalue:
2471 hierarchical_id '[' expr ']' '.' rvalue {
2472 $$ = new AstNode(AST_PREFIX, $3, $6);
2473 $$->str = *$1;
2474 delete $1;
2475 } |
2476 hierarchical_id range {
2477 $$ = new AstNode(AST_IDENTIFIER, $2);
2478 $$->str = *$1;
2479 SET_AST_NODE_LOC($$, @1, @1);
2480 delete $1;
2481 if ($2 == nullptr && ($$->str == "\\$initstate" ||
2482 $$->str == "\\$anyconst" || $$->str == "\\$anyseq" ||
2483 $$->str == "\\$allconst" || $$->str == "\\$allseq"))
2484 $$->type = AST_FCALL;
2485 } |
2486 hierarchical_id non_opt_multirange {
2487 $$ = new AstNode(AST_IDENTIFIER, $2);
2488 $$->str = *$1;
2489 SET_AST_NODE_LOC($$, @1, @1);
2490 delete $1;
2491 };
2492
2493 lvalue:
2494 rvalue {
2495 $$ = $1;
2496 } |
2497 '{' lvalue_concat_list '}' {
2498 $$ = $2;
2499 };
2500
2501 lvalue_concat_list:
2502 expr {
2503 $$ = new AstNode(AST_CONCAT);
2504 $$->children.push_back($1);
2505 } |
2506 expr ',' lvalue_concat_list {
2507 $$ = $3;
2508 $$->children.push_back($1);
2509 };
2510
2511 opt_arg_list:
2512 '(' arg_list optional_comma ')' |
2513 /* empty */;
2514
2515 arg_list:
2516 arg_list2 |
2517 /* empty */;
2518
2519 arg_list2:
2520 single_arg |
2521 arg_list ',' single_arg;
2522
2523 single_arg:
2524 expr {
2525 ast_stack.back()->children.push_back($1);
2526 };
2527
2528 module_gen_body:
2529 module_gen_body gen_stmt_or_module_body_stmt |
2530 /* empty */;
2531
2532 gen_stmt_or_module_body_stmt:
2533 gen_stmt | module_body_stmt;
2534
2535 // this production creates the obligatory if-else shift/reduce conflict
2536 gen_stmt:
2537 TOK_FOR '(' {
2538 AstNode *node = new AstNode(AST_GENFOR);
2539 ast_stack.back()->children.push_back(node);
2540 ast_stack.push_back(node);
2541 } simple_behavioral_stmt ';' expr {
2542 ast_stack.back()->children.push_back($6);
2543 } ';' simple_behavioral_stmt ')' gen_stmt_block {
2544 SET_AST_NODE_LOC(ast_stack.back(), @1, @11);
2545 ast_stack.pop_back();
2546 } |
2547 TOK_IF '(' expr ')' {
2548 AstNode *node = new AstNode(AST_GENIF);
2549 ast_stack.back()->children.push_back(node);
2550 ast_stack.push_back(node);
2551 ast_stack.back()->children.push_back($3);
2552 AstNode *block = new AstNode(AST_GENBLOCK);
2553 ast_stack.back()->children.push_back(block);
2554 ast_stack.push_back(block);
2555 } gen_stmt_or_null {
2556 ast_stack.pop_back();
2557 } opt_gen_else {
2558 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2559 ast_stack.pop_back();
2560 } |
2561 case_type '(' expr ')' {
2562 AstNode *node = new AstNode(AST_GENCASE, $3);
2563 ast_stack.back()->children.push_back(node);
2564 ast_stack.push_back(node);
2565 } gen_case_body TOK_ENDCASE {
2566 case_type_stack.pop_back();
2567 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2568 ast_stack.pop_back();
2569 } |
2570 TOK_BEGIN {
2571 enterTypeScope();
2572 } opt_label {
2573 AstNode *node = new AstNode(AST_GENBLOCK);
2574 node->str = $3 ? *$3 : std::string();
2575 ast_stack.back()->children.push_back(node);
2576 ast_stack.push_back(node);
2577 } module_gen_body TOK_END opt_label {
2578 exitTypeScope();
2579 delete $3;
2580 delete $7;
2581 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2582 ast_stack.pop_back();
2583 } |
2584 TOK_MSG_TASKS {
2585 AstNode *node = new AstNode(AST_TECALL);
2586 node->str = *$1;
2587 delete $1;
2588 ast_stack.back()->children.push_back(node);
2589 ast_stack.push_back(node);
2590 } opt_arg_list ';'{
2591 SET_AST_NODE_LOC(ast_stack.back(), @1, @3);
2592 ast_stack.pop_back();
2593 };
2594
2595 gen_stmt_block:
2596 {
2597 AstNode *node = new AstNode(AST_GENBLOCK);
2598 ast_stack.back()->children.push_back(node);
2599 ast_stack.push_back(node);
2600 } gen_stmt_or_module_body_stmt {
2601 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2602 ast_stack.pop_back();
2603 };
2604
2605 gen_stmt_or_null:
2606 gen_stmt_block | ';';
2607
2608 opt_gen_else:
2609 TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
2610
2611 expr:
2612 basic_expr {
2613 $$ = $1;
2614 } |
2615 basic_expr '?' attr expr ':' expr {
2616 $$ = new AstNode(AST_TERNARY);
2617 $$->children.push_back($1);
2618 $$->children.push_back($4);
2619 $$->children.push_back($6);
2620 SET_AST_NODE_LOC($$, @1, @$);
2621 append_attr($$, $3);
2622 };
2623
2624 basic_expr:
2625 rvalue {
2626 $$ = $1;
2627 } |
2628 '(' expr ')' integral_number {
2629 if ($4->compare(0, 1, "'") != 0)
2630 frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
2631 AstNode *bits = $2;
2632 AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2633 if (val == NULL)
2634 log_error("Value conversion failed: `%s'\n", $4->c_str());
2635 $$ = new AstNode(AST_TO_BITS, bits, val);
2636 delete $4;
2637 } |
2638 hierarchical_id integral_number {
2639 if ($2->compare(0, 1, "'") != 0)
2640 frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
2641 AstNode *bits = new AstNode(AST_IDENTIFIER);
2642 bits->str = *$1;
2643 SET_AST_NODE_LOC(bits, @1, @1);
2644 AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2645 SET_AST_NODE_LOC(val, @2, @2);
2646 if (val == NULL)
2647 log_error("Value conversion failed: `%s'\n", $2->c_str());
2648 $$ = new AstNode(AST_TO_BITS, bits, val);
2649 delete $1;
2650 delete $2;
2651 } |
2652 integral_number {
2653 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2654 SET_AST_NODE_LOC($$, @1, @1);
2655 if ($$ == NULL)
2656 log_error("Value conversion failed: `%s'\n", $1->c_str());
2657 delete $1;
2658 } |
2659 TOK_REALVAL {
2660 $$ = new AstNode(AST_REALVALUE);
2661 char *p = (char*)malloc(GetSize(*$1) + 1), *q;
2662 for (int i = 0, j = 0; j < GetSize(*$1); j++)
2663 if ((*$1)[j] != '_')
2664 p[i++] = (*$1)[j], p[i] = 0;
2665 $$->realvalue = strtod(p, &q);
2666 SET_AST_NODE_LOC($$, @1, @1);
2667 log_assert(*q == 0);
2668 delete $1;
2669 free(p);
2670 } |
2671 TOK_STRING {
2672 $$ = AstNode::mkconst_str(*$1);
2673 SET_AST_NODE_LOC($$, @1, @1);
2674 delete $1;
2675 } |
2676 hierarchical_id attr {
2677 AstNode *node = new AstNode(AST_FCALL);
2678 node->str = *$1;
2679 delete $1;
2680 ast_stack.push_back(node);
2681 SET_AST_NODE_LOC(node, @1, @1);
2682 append_attr(node, $2);
2683 } '(' arg_list optional_comma ')' {
2684 $$ = ast_stack.back();
2685 ast_stack.pop_back();
2686 } |
2687 TOK_TO_SIGNED attr '(' expr ')' {
2688 $$ = new AstNode(AST_TO_SIGNED, $4);
2689 append_attr($$, $2);
2690 } |
2691 TOK_TO_UNSIGNED attr '(' expr ')' {
2692 $$ = new AstNode(AST_TO_UNSIGNED, $4);
2693 append_attr($$, $2);
2694 } |
2695 '(' expr ')' {
2696 $$ = $2;
2697 } |
2698 '(' expr ':' expr ':' expr ')' {
2699 delete $2;
2700 $$ = $4;
2701 delete $6;
2702 } |
2703 '{' concat_list '}' {
2704 $$ = $2;
2705 } |
2706 '{' expr '{' concat_list '}' '}' {
2707 $$ = new AstNode(AST_REPLICATE, $2, $4);
2708 } |
2709 '~' attr basic_expr %prec UNARY_OPS {
2710 $$ = new AstNode(AST_BIT_NOT, $3);
2711 SET_AST_NODE_LOC($$, @1, @3);
2712 append_attr($$, $2);
2713 } |
2714 basic_expr '&' attr basic_expr {
2715 $$ = new AstNode(AST_BIT_AND, $1, $4);
2716 SET_AST_NODE_LOC($$, @1, @4);
2717 append_attr($$, $3);
2718 } |
2719 basic_expr OP_NAND attr basic_expr {
2720 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
2721 SET_AST_NODE_LOC($$, @1, @4);
2722 append_attr($$, $3);
2723 } |
2724 basic_expr '|' attr basic_expr {
2725 $$ = new AstNode(AST_BIT_OR, $1, $4);
2726 SET_AST_NODE_LOC($$, @1, @4);
2727 append_attr($$, $3);
2728 } |
2729 basic_expr OP_NOR attr basic_expr {
2730 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
2731 SET_AST_NODE_LOC($$, @1, @4);
2732 append_attr($$, $3);
2733 } |
2734 basic_expr '^' attr basic_expr {
2735 $$ = new AstNode(AST_BIT_XOR, $1, $4);
2736 SET_AST_NODE_LOC($$, @1, @4);
2737 append_attr($$, $3);
2738 } |
2739 basic_expr OP_XNOR attr basic_expr {
2740 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
2741 SET_AST_NODE_LOC($$, @1, @4);
2742 append_attr($$, $3);
2743 } |
2744 '&' attr basic_expr %prec UNARY_OPS {
2745 $$ = new AstNode(AST_REDUCE_AND, $3);
2746 SET_AST_NODE_LOC($$, @1, @3);
2747 append_attr($$, $2);
2748 } |
2749 OP_NAND attr basic_expr %prec UNARY_OPS {
2750 $$ = new AstNode(AST_REDUCE_AND, $3);
2751 SET_AST_NODE_LOC($$, @1, @3);
2752 append_attr($$, $2);
2753 $$ = new AstNode(AST_LOGIC_NOT, $$);
2754 } |
2755 '|' attr basic_expr %prec UNARY_OPS {
2756 $$ = new AstNode(AST_REDUCE_OR, $3);
2757 SET_AST_NODE_LOC($$, @1, @3);
2758 append_attr($$, $2);
2759 } |
2760 OP_NOR attr basic_expr %prec UNARY_OPS {
2761 $$ = new AstNode(AST_REDUCE_OR, $3);
2762 SET_AST_NODE_LOC($$, @1, @3);
2763 append_attr($$, $2);
2764 $$ = new AstNode(AST_LOGIC_NOT, $$);
2765 SET_AST_NODE_LOC($$, @1, @3);
2766 } |
2767 '^' attr basic_expr %prec UNARY_OPS {
2768 $$ = new AstNode(AST_REDUCE_XOR, $3);
2769 SET_AST_NODE_LOC($$, @1, @3);
2770 append_attr($$, $2);
2771 } |
2772 OP_XNOR attr basic_expr %prec UNARY_OPS {
2773 $$ = new AstNode(AST_REDUCE_XNOR, $3);
2774 SET_AST_NODE_LOC($$, @1, @3);
2775 append_attr($$, $2);
2776 } |
2777 basic_expr OP_SHL attr basic_expr {
2778 $$ = new AstNode(AST_SHIFT_LEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2779 SET_AST_NODE_LOC($$, @1, @4);
2780 append_attr($$, $3);
2781 } |
2782 basic_expr OP_SHR attr basic_expr {
2783 $$ = new AstNode(AST_SHIFT_RIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2784 SET_AST_NODE_LOC($$, @1, @4);
2785 append_attr($$, $3);
2786 } |
2787 basic_expr OP_SSHL attr basic_expr {
2788 $$ = new AstNode(AST_SHIFT_SLEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2789 SET_AST_NODE_LOC($$, @1, @4);
2790 append_attr($$, $3);
2791 } |
2792 basic_expr OP_SSHR attr basic_expr {
2793 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2794 SET_AST_NODE_LOC($$, @1, @4);
2795 append_attr($$, $3);
2796 } |
2797 basic_expr '<' attr basic_expr {
2798 $$ = new AstNode(AST_LT, $1, $4);
2799 SET_AST_NODE_LOC($$, @1, @4);
2800 append_attr($$, $3);
2801 } |
2802 basic_expr OP_LE attr basic_expr {
2803 $$ = new AstNode(AST_LE, $1, $4);
2804 SET_AST_NODE_LOC($$, @1, @4);
2805 append_attr($$, $3);
2806 } |
2807 basic_expr OP_EQ attr basic_expr {
2808 $$ = new AstNode(AST_EQ, $1, $4);
2809 SET_AST_NODE_LOC($$, @1, @4);
2810 append_attr($$, $3);
2811 } |
2812 basic_expr OP_NE attr basic_expr {
2813 $$ = new AstNode(AST_NE, $1, $4);
2814 SET_AST_NODE_LOC($$, @1, @4);
2815 append_attr($$, $3);
2816 } |
2817 basic_expr OP_EQX attr basic_expr {
2818 $$ = new AstNode(AST_EQX, $1, $4);
2819 SET_AST_NODE_LOC($$, @1, @4);
2820 append_attr($$, $3);
2821 } |
2822 basic_expr OP_NEX attr basic_expr {
2823 $$ = new AstNode(AST_NEX, $1, $4);
2824 SET_AST_NODE_LOC($$, @1, @4);
2825 append_attr($$, $3);
2826 } |
2827 basic_expr OP_GE attr basic_expr {
2828 $$ = new AstNode(AST_GE, $1, $4);
2829 SET_AST_NODE_LOC($$, @1, @4);
2830 append_attr($$, $3);
2831 } |
2832 basic_expr '>' attr basic_expr {
2833 $$ = new AstNode(AST_GT, $1, $4);
2834 SET_AST_NODE_LOC($$, @1, @4);
2835 append_attr($$, $3);
2836 } |
2837 basic_expr '+' attr basic_expr {
2838 $$ = new AstNode(AST_ADD, $1, $4);
2839 SET_AST_NODE_LOC($$, @1, @4);
2840 append_attr($$, $3);
2841 } |
2842 basic_expr '-' attr basic_expr {
2843 $$ = new AstNode(AST_SUB, $1, $4);
2844 SET_AST_NODE_LOC($$, @1, @4);
2845 append_attr($$, $3);
2846 } |
2847 basic_expr '*' attr basic_expr {
2848 $$ = new AstNode(AST_MUL, $1, $4);
2849 SET_AST_NODE_LOC($$, @1, @4);
2850 append_attr($$, $3);
2851 } |
2852 basic_expr '/' attr basic_expr {
2853 $$ = new AstNode(AST_DIV, $1, $4);
2854 SET_AST_NODE_LOC($$, @1, @4);
2855 append_attr($$, $3);
2856 } |
2857 basic_expr '%' attr basic_expr {
2858 $$ = new AstNode(AST_MOD, $1, $4);
2859 SET_AST_NODE_LOC($$, @1, @4);
2860 append_attr($$, $3);
2861 } |
2862 basic_expr OP_POW attr basic_expr {
2863 $$ = new AstNode(AST_POW, $1, $4);
2864 SET_AST_NODE_LOC($$, @1, @4);
2865 append_attr($$, $3);
2866 } |
2867 '+' attr basic_expr %prec UNARY_OPS {
2868 $$ = new AstNode(AST_POS, $3);
2869 SET_AST_NODE_LOC($$, @1, @3);
2870 append_attr($$, $2);
2871 } |
2872 '-' attr basic_expr %prec UNARY_OPS {
2873 $$ = new AstNode(AST_NEG, $3);
2874 SET_AST_NODE_LOC($$, @1, @3);
2875 append_attr($$, $2);
2876 } |
2877 basic_expr OP_LAND attr basic_expr {
2878 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
2879 SET_AST_NODE_LOC($$, @1, @4);
2880 append_attr($$, $3);
2881 } |
2882 basic_expr OP_LOR attr basic_expr {
2883 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
2884 SET_AST_NODE_LOC($$, @1, @4);
2885 append_attr($$, $3);
2886 } |
2887 '!' attr basic_expr %prec UNARY_OPS {
2888 $$ = new AstNode(AST_LOGIC_NOT, $3);
2889 SET_AST_NODE_LOC($$, @1, @3);
2890 append_attr($$, $2);
2891 };
2892
2893 concat_list:
2894 expr {
2895 $$ = new AstNode(AST_CONCAT, $1);
2896 } |
2897 expr ',' concat_list {
2898 $$ = $3;
2899 $$->children.push_back($1);
2900 };
2901
2902 integral_number:
2903 TOK_CONSTVAL { $$ = $1; } |
2904 TOK_UNBASED_UNSIZED_CONSTVAL { $$ = $1; } |
2905 TOK_BASE TOK_BASED_CONSTVAL {
2906 $1->append(*$2);
2907 $$ = $1;
2908 delete $2;
2909 } |
2910 TOK_CONSTVAL TOK_BASE TOK_BASED_CONSTVAL {
2911 $1->append(*$2).append(*$3);
2912 $$ = $1;
2913 delete $2;
2914 delete $3;
2915 };