2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The Verilog frontend.
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
29 * This is the actual bison parser for Verilog code. The AST ist created directly
30 * from the bison reduce functions here. Note that this code uses a few global
31 * variables to hold the state of the AST generator and therefore this parser is
40 #include "frontends/verilog/verilog_frontend.h"
41 #include "frontends/verilog/verilog_parser.tab.hh"
42 #include "kernel/log.h"
44 #define YYLEX_PARAM &yylval, &yylloc
48 using namespace VERILOG_FRONTEND;
51 namespace VERILOG_FRONTEND {
53 dict<std::string, int> port_stubs;
54 dict<IdString, AstNode*> *attr_list, default_attr_list;
55 std::stack<dict<IdString, AstNode*> *> attr_list_stack;
56 dict<IdString, AstNode*> *albuf;
57 std::vector<UserTypeMap*> user_type_stack;
58 dict<std::string, AstNode*> pkg_user_types;
59 std::vector<AstNode*> ast_stack;
60 struct AstNode *astbuf1, *astbuf2, *astbuf3;
61 struct AstNode *current_function_or_task;
62 struct AstNode *current_ast, *current_ast_mod;
63 int current_function_or_task_port_id;
64 std::vector<char> case_type_stack;
65 bool do_not_require_port_stubs;
66 bool default_nettype_wire;
67 bool sv_mode, formal_mode, lib_mode, specify_mode;
68 bool noassert_mode, noassume_mode, norestrict_mode;
69 bool assume_asserts_mode, assert_assumes_mode;
70 bool current_wire_rand, current_wire_const;
71 bool current_modport_input, current_modport_output;
76 #define SET_AST_NODE_LOC(WHICH, BEGIN, END) \
77 do { (WHICH)->location.first_line = (BEGIN).first_line; \
78 (WHICH)->location.first_column = (BEGIN).first_column; \
79 (WHICH)->location.last_line = (END).last_line; \
80 (WHICH)->location.last_column = (END).last_column; } while(0)
82 #define SET_RULE_LOC(LHS, BEGIN, END) \
83 do { (LHS).first_line = (BEGIN).first_line; \
84 (LHS).first_column = (BEGIN).first_column; \
85 (LHS).last_line = (END).last_line; \
86 (LHS).last_column = (END).last_column; } while(0)
88 int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
90 static void append_attr(AstNode *ast, dict<IdString, AstNode*> *al)
92 for (auto &it : *al) {
93 if (ast->attributes.count(it.first) > 0)
94 delete ast->attributes[it.first];
95 ast->attributes[it.first] = it.second;
100 static void append_attr_clone(AstNode *ast, dict<IdString, AstNode*> *al)
102 for (auto &it : *al) {
103 if (ast->attributes.count(it.first) > 0)
104 delete ast->attributes[it.first];
105 ast->attributes[it.first] = it.second->clone();
109 static void free_attr(dict<IdString, AstNode*> *al)
116 struct specify_target {
121 struct specify_triple {
122 AstNode *t_min, *t_avg, *t_max;
125 struct specify_rise_fall {
130 static void addTypedefNode(std::string *name, AstNode *node)
133 auto *tnode = new AstNode(AST_TYPEDEF, node);
135 auto user_types = user_type_stack.back();
136 (*user_types)[*name] = tnode;
137 if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {
138 // typedef inside a package so we need the qualified name
139 auto qname = current_ast_mod->str + "::" + (*name).substr(1);
140 pkg_user_types[qname] = tnode;
143 ast_stack.back()->children.push_back(tnode);
146 static void enterTypeScope()
148 auto user_types = new UserTypeMap();
149 user_type_stack.push_back(user_types);
152 static void exitTypeScope()
154 user_type_stack.pop_back();
157 static bool isInLocalScope(const std::string *name)
159 // tests if a name was declared in the current block scope
160 auto user_types = user_type_stack.back();
161 return (user_types->count(*name) > 0);
164 static AstNode *getTypeDefinitionNode(std::string type_name)
166 // return the definition nodes from the typedef statement
167 auto user_types = user_type_stack.back();
168 log_assert(user_types->count(type_name) > 0);
169 auto typedef_node = (*user_types)[type_name];
170 log_assert(typedef_node->type == AST_TYPEDEF);
171 return typedef_node->children[0];
174 static AstNode *copyTypeDefinition(std::string type_name)
176 // return a copy of the template from a typedef definition
177 auto typedef_node = getTypeDefinitionNode(type_name);
178 return typedef_node->clone();
181 static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
183 auto range = new AstNode(AST_RANGE);
184 range->children.push_back(AstNode::mkconst_int(msb, true));
185 range->children.push_back(AstNode::mkconst_int(lsb, true));
186 range->is_signed = isSigned;
190 static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned = true)
192 auto range = makeRange(msb, lsb, isSigned);
193 parent->children.push_back(range);
196 static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
198 if (type_node->range_left >= 0 && type_node->range_right >= 0) {
199 // type already restricts the range
201 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
204 range_node = makeRange(type_node->range_left, type_node->range_right, false);
207 if (range_node && range_node->children.size() != 2) {
208 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
213 static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
215 node->type = AST_MEMORY;
216 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
217 // SV array size [n], rewrite as [n-1:0]
218 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
219 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
221 node->children.push_back(rangeNode);
226 %define api.prefix {frontend_verilog_yy}
229 /* The union is defined in the header, so we need to provide all the
230 * includes it requires
235 #include "frontends/verilog/verilog_frontend.h"
240 struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
241 YOSYS_NAMESPACE_PREFIX AST::AstNodeType type;
242 YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
243 struct specify_target *specify_target_ptr;
244 struct specify_triple *specify_triple_ptr;
245 struct specify_rise_fall *specify_rise_fall_ptr;
250 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
251 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
252 %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL
253 %token <string> TOK_USER_TYPE TOK_PKG_USER_TYPE
254 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
255 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
256 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
257 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
258 %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
259 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
260 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
261 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
262 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
263 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
264 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
265 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
266 %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
267 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
268 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
269 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
270 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
271 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
272 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
273 %token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_UNION
275 %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
276 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
277 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
278 %type <string> type_name
279 %type <ast> opt_enum_init enum_type struct_type non_wire_data_type
280 %type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
281 %type <al> attr case_attr
282 %type <type> struct_union
284 %type <specify_target_ptr> specify_target
285 %type <specify_triple_ptr> specify_triple specify_opt_triple
286 %type <specify_rise_fall_ptr> specify_rise_fall
287 %type <ast> specify_if specify_condition
288 %type <ch> specify_edge
290 // operator precedence from low to high
296 %left OP_EQ OP_NE OP_EQX OP_NEX
297 %left '<' OP_LE OP_GE '>'
298 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
304 %define parse.error verbose
305 %define parse.lac full
317 ast_stack.push_back(current_ast);
319 ast_stack.pop_back();
320 log_assert(GetSize(ast_stack) == 0);
321 for (auto &it : default_attr_list)
323 default_attr_list.clear();
329 task_func_decl design |
331 localparam_decl design |
332 typedef_decl design |
339 if (attr_list != nullptr)
340 attr_list_stack.push(attr_list);
341 attr_list = new dict<IdString, AstNode*>;
342 for (auto &it : default_attr_list)
343 (*attr_list)[it.first] = it.second->clone();
346 if (!attr_list_stack.empty()) {
347 attr_list = attr_list_stack.top();
348 attr_list_stack.pop();
354 attr_opt ATTR_BEGIN opt_attr_list ATTR_END {
355 SET_RULE_LOC(@$, @2, @$);
361 if (attr_list != nullptr)
362 attr_list_stack.push(attr_list);
363 attr_list = new dict<IdString, AstNode*>;
364 for (auto &it : default_attr_list)
366 default_attr_list.clear();
368 attr_list->swap(default_attr_list);
370 if (!attr_list_stack.empty()) {
371 attr_list = attr_list_stack.top();
372 attr_list_stack.pop();
378 attr_list | /* empty */;
382 attr_list ',' attr_assign;
386 if (attr_list->count(*$1) != 0)
387 delete (*attr_list)[*$1];
388 (*attr_list)[*$1] = AstNode::mkconst_int(1, false);
391 hierarchical_id '=' expr {
392 if (attr_list->count(*$1) != 0)
393 delete (*attr_list)[*$1];
394 (*attr_list)[*$1] = $3;
402 hierarchical_id TOK_PACKAGESEP TOK_ID {
403 if ($3->compare(0, 1, "\\") == 0)
404 *$1 += "::" + $3->substr(1);
410 hierarchical_id '.' TOK_ID {
411 if ($3->compare(0, 1, "\\") == 0)
412 *$1 += "." + $3->substr(1);
419 hierarchical_type_id:
421 | TOK_PKG_USER_TYPE // package qualified type name
422 | '(' TOK_USER_TYPE ')' { $$ = $2; } // non-standard grammar
429 do_not_require_port_stubs = false;
430 AstNode *mod = new AstNode(AST_MODULE);
431 ast_stack.back()->children.push_back(mod);
432 ast_stack.push_back(mod);
433 current_ast_mod = mod;
437 append_attr(mod, $1);
439 } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
440 if (port_stubs.size() != 0)
441 frontend_verilog_yyerror("Missing details for module port `%s'.",
442 port_stubs.begin()->first.c_str());
443 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
444 ast_stack.pop_back();
445 log_assert(ast_stack.size() == 1);
446 current_ast_mod = NULL;
451 '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
454 single_module_para | module_para_list ',' single_module_para;
459 if (astbuf1) delete astbuf1;
460 astbuf1 = new AstNode(AST_PARAMETER);
461 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
462 append_attr(astbuf1, $1);
463 } param_type single_param_decl |
464 attr TOK_LOCALPARAM {
465 if (astbuf1) delete astbuf1;
466 astbuf1 = new AstNode(AST_LOCALPARAM);
467 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
468 append_attr(astbuf1, $1);
469 } param_type single_param_decl |
473 '(' ')' | /* empty */ | '(' module_args optional_comma ')';
476 module_arg | module_args ',' module_arg;
481 module_arg_opt_assignment:
483 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
484 AstNode *wire = new AstNode(AST_IDENTIFIER);
485 wire->str = ast_stack.back()->children.back()->str;
486 if (ast_stack.back()->children.back()->is_input) {
487 AstNode *n = ast_stack.back()->children.back();
488 if (n->attributes.count(ID::defaultvalue))
489 delete n->attributes.at(ID::defaultvalue);
490 n->attributes[ID::defaultvalue] = $2;
492 if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
493 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
495 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
497 frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
503 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
504 AstNode *node = ast_stack.back()->children.back()->clone();
506 node->port_id = ++port_counter;
507 ast_stack.back()->children.push_back(node);
508 SET_AST_NODE_LOC(node, @1, @1);
510 if (port_stubs.count(*$1) != 0)
511 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
512 port_stubs[*$1] = ++port_counter;
515 } module_arg_opt_assignment |
517 astbuf1 = new AstNode(AST_INTERFACEPORT);
518 astbuf1->children.push_back(new AstNode(AST_INTERFACEPORTTYPE));
519 astbuf1->children[0]->str = *$1;
521 } TOK_ID { /* SV interfaces */
523 frontend_verilog_yyerror("Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
524 astbuf2 = astbuf1->clone(); // really only needed if multiple instances of same type.
527 astbuf2->port_id = ++port_counter;
528 ast_stack.back()->children.push_back(astbuf2);
529 delete astbuf1; // really only needed if multiple instances of same type.
530 } module_arg_opt_assignment |
531 attr wire_type range TOK_ID {
534 SET_AST_NODE_LOC(node, @4, @4);
535 node->port_id = ++port_counter;
537 node->children.push_back($3);
538 if (!node->is_input && !node->is_output)
539 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
540 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
541 frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
542 ast_stack.back()->children.push_back(node);
543 append_attr(node, $1);
545 } module_arg_opt_assignment |
547 do_not_require_port_stubs = true;
554 AstNode *mod = new AstNode(AST_PACKAGE);
555 ast_stack.back()->children.push_back(mod);
556 ast_stack.push_back(mod);
557 current_ast_mod = mod;
559 append_attr(mod, $1);
560 } ';' package_body TOK_ENDPACKAGE {
561 ast_stack.pop_back();
562 current_ast_mod = NULL;
567 package_body package_body_stmt
581 do_not_require_port_stubs = false;
582 AstNode *intf = new AstNode(AST_INTERFACE);
583 ast_stack.back()->children.push_back(intf);
584 ast_stack.push_back(intf);
585 current_ast_mod = intf;
590 } module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
591 if (port_stubs.size() != 0)
592 frontend_verilog_yyerror("Missing details for module port `%s'.",
593 port_stubs.begin()->first.c_str());
594 ast_stack.pop_back();
595 log_assert(ast_stack.size() == 1);
596 current_ast_mod = NULL;
601 interface_body interface_body_stmt |;
604 param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
608 '#' TOK_ID { delete $2; } |
609 '#' TOK_CONSTVAL { delete $2; } |
610 '#' TOK_REALVAL { delete $2; } |
611 '#' '(' expr ')' { delete $3; } |
612 '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
615 non_opt_delay | /* empty */;
619 astbuf3 = new AstNode(AST_WIRE);
620 current_wire_rand = false;
621 current_wire_const = false;
622 } wire_type_token_list {
624 SET_RULE_LOC(@$, @2, @$);
627 wire_type_token_list:
629 wire_type_token_list wire_type_token |
631 hierarchical_type_id {
632 astbuf3->is_custom_type = true;
633 astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
634 astbuf3->children.back()->str = *$1;
640 astbuf3->is_input = true;
643 astbuf3->is_output = true;
646 astbuf3->is_input = true;
647 astbuf3->is_output = true;
654 astbuf3->is_wor = true;
657 astbuf3->is_wand = true;
660 astbuf3->is_reg = true;
663 astbuf3->is_logic = true;
666 astbuf3->is_logic = true;
669 astbuf3->is_reg = true;
670 astbuf3->range_left = 31;
671 astbuf3->range_right = 0;
672 astbuf3->is_signed = true;
675 astbuf3->type = AST_GENVAR;
676 astbuf3->is_reg = true;
677 astbuf3->is_signed = true;
678 astbuf3->range_left = 31;
679 astbuf3->range_right = 0;
682 astbuf3->is_signed = true;
685 current_wire_rand = true;
688 current_wire_const = true;
692 '[' expr ':' expr ']' {
693 $$ = new AstNode(AST_RANGE);
694 $$->children.push_back($2);
695 $$->children.push_back($4);
697 '[' expr TOK_POS_INDEXED expr ']' {
698 $$ = new AstNode(AST_RANGE);
699 AstNode *expr = new AstNode(AST_SELFSZ, $2);
700 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
701 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
703 '[' expr TOK_NEG_INDEXED expr ']' {
704 $$ = new AstNode(AST_RANGE);
705 AstNode *expr = new AstNode(AST_SELFSZ, $2);
706 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
707 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
710 $$ = new AstNode(AST_RANGE);
711 $$->children.push_back($2);
715 non_opt_range non_opt_range {
716 $$ = new AstNode(AST_MULTIRANGE, $1, $2);
718 non_opt_multirange non_opt_range {
720 $$->children.push_back($2);
733 non_opt_multirange { $$ = $1; };
737 | TOK_INTEGER { $$ = makeRange(); }
741 module_body module_body_stmt |
742 /* the following line makes the generate..endgenrate keywords optional */
743 module_body gen_stmt |
747 task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
748 enum_decl | struct_decl |
749 always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
752 TOK_CHECKER TOK_ID ';' {
753 AstNode *node = new AstNode(AST_GENBLOCK);
755 ast_stack.back()->children.push_back(node);
756 ast_stack.push_back(node);
757 } module_body TOK_ENDCHECKER {
759 ast_stack.pop_back();
763 attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
764 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
765 current_function_or_task->str = *$4;
766 append_attr(current_function_or_task, $1);
767 ast_stack.back()->children.push_back(current_function_or_task);
770 } opt_dpi_function_args ';' {
771 current_function_or_task = NULL;
773 attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
774 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
775 current_function_or_task->str = *$6;
776 append_attr(current_function_or_task, $1);
777 ast_stack.back()->children.push_back(current_function_or_task);
781 } opt_dpi_function_args ';' {
782 current_function_or_task = NULL;
784 attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
785 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
786 current_function_or_task->str = *$8;
787 append_attr(current_function_or_task, $1);
788 ast_stack.back()->children.push_back(current_function_or_task);
793 } opt_dpi_function_args ';' {
794 current_function_or_task = NULL;
796 attr TOK_TASK opt_automatic TOK_ID {
797 current_function_or_task = new AstNode(AST_TASK);
798 current_function_or_task->str = *$4;
799 append_attr(current_function_or_task, $1);
800 ast_stack.back()->children.push_back(current_function_or_task);
801 ast_stack.push_back(current_function_or_task);
802 current_function_or_task_port_id = 1;
804 } task_func_args_opt ';' task_func_body TOK_ENDTASK {
805 current_function_or_task = NULL;
806 ast_stack.pop_back();
808 attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID {
809 current_function_or_task = new AstNode(AST_FUNCTION);
810 current_function_or_task->str = *$6;
811 append_attr(current_function_or_task, $1);
812 ast_stack.back()->children.push_back(current_function_or_task);
813 ast_stack.push_back(current_function_or_task);
814 AstNode *outreg = new AstNode(AST_WIRE);
816 outreg->is_signed = $4;
817 outreg->is_reg = true;
819 outreg->children.push_back($5);
820 outreg->is_signed = $4 || $5->is_signed;
821 $5->is_signed = false;
823 current_function_or_task->children.push_back(outreg);
824 current_function_or_task_port_id = 1;
826 } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
827 current_function_or_task = NULL;
828 ast_stack.pop_back();
833 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
838 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
842 opt_dpi_function_args:
843 '(' dpi_function_args ')' |
847 dpi_function_args ',' dpi_function_arg |
848 dpi_function_args ',' |
865 '(' ')' | /* empty */ | '(' {
869 } task_func_args optional_comma {
877 task_func_port | task_func_args ',' task_func_port;
880 attr wire_type range {
889 astbuf2 = checkRange(astbuf1, $3);
890 } wire_name | wire_name;
893 task_func_body behavioral_stmt |
896 /*************************** specify parser ***************************/
899 TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
902 specify_item specify_item_list |
906 specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
907 AstNode *en_expr = $1;
908 char specify_edge = $3;
909 AstNode *src_expr = $4;
911 specify_target *target = $6;
912 specify_rise_fall *timing = $9;
914 if (specify_edge != 0 && target->dat == nullptr)
915 frontend_verilog_yyerror("Found specify edge but no data spec.\n");
917 AstNode *cell = new AstNode(AST_CELL);
918 ast_stack.back()->children.push_back(cell);
919 cell->str = stringf("$specify$%d", autoidx++);
920 cell->children.push_back(new AstNode(AST_CELLTYPE));
921 cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
922 SET_AST_NODE_LOC(cell, en_expr ? @1 : @2, @10);
924 char oper_polarity = 0;
925 char oper_type = oper->at(0);
927 if (oper->size() == 3) {
928 oper_polarity = oper->at(0);
929 oper_type = oper->at(1);
932 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
933 cell->children.back()->str = "\\FULL";
935 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
936 cell->children.back()->str = "\\SRC_DST_PEN";
938 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
939 cell->children.back()->str = "\\SRC_DST_POL";
941 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
942 cell->children.back()->str = "\\T_RISE_MIN";
944 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
945 cell->children.back()->str = "\\T_RISE_TYP";
947 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
948 cell->children.back()->str = "\\T_RISE_MAX";
950 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
951 cell->children.back()->str = "\\T_FALL_MIN";
953 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
954 cell->children.back()->str = "\\T_FALL_TYP";
956 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
957 cell->children.back()->str = "\\T_FALL_MAX";
959 cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
960 cell->children.back()->str = "\\EN";
962 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
963 cell->children.back()->str = "\\SRC";
965 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
966 cell->children.back()->str = "\\DST";
970 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
971 cell->children.back()->str = "\\EDGE_EN";
973 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
974 cell->children.back()->str = "\\EDGE_POL";
976 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
977 cell->children.back()->str = "\\DAT_DST_PEN";
979 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
980 cell->children.back()->str = "\\DAT_DST_POL";
982 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
983 cell->children.back()->str = "\\DAT";
990 TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' specify_triple specify_opt_triple ')' ';' {
991 if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
992 *$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
993 frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
995 AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
996 AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
997 AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
999 AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
1000 AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
1001 AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
1003 specify_triple *limit = $11;
1004 specify_triple *limit2 = $12;
1006 AstNode *cell = new AstNode(AST_CELL);
1007 ast_stack.back()->children.push_back(cell);
1008 cell->str = stringf("$specify$%d", autoidx++);
1009 cell->children.push_back(new AstNode(AST_CELLTYPE));
1010 cell->children.back()->str = "$specrule";
1011 SET_AST_NODE_LOC(cell, @1, @14);
1013 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
1014 cell->children.back()->str = "\\TYPE";
1016 cell->children.push_back(new AstNode(AST_PARASET, limit->t_min));
1017 cell->children.back()->str = "\\T_LIMIT_MIN";
1019 cell->children.push_back(new AstNode(AST_PARASET, limit->t_avg));
1020 cell->children.back()->str = "\\T_LIMIT_TYP";
1022 cell->children.push_back(new AstNode(AST_PARASET, limit->t_max));
1023 cell->children.back()->str = "\\T_LIMIT_MAX";
1025 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_min : AstNode::mkconst_int(0, true)));
1026 cell->children.back()->str = "\\T_LIMIT2_MIN";
1028 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_avg : AstNode::mkconst_int(0, true)));
1029 cell->children.back()->str = "\\T_LIMIT2_TYP";
1031 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_max : AstNode::mkconst_int(0, true)));
1032 cell->children.back()->str = "\\T_LIMIT2_MAX";
1034 cell->children.push_back(new AstNode(AST_PARASET, src_pen));
1035 cell->children.back()->str = "\\SRC_PEN";
1037 cell->children.push_back(new AstNode(AST_PARASET, src_pol));
1038 cell->children.back()->str = "\\SRC_POL";
1040 cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
1041 cell->children.back()->str = "\\DST_PEN";
1043 cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
1044 cell->children.back()->str = "\\DST_POL";
1046 cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
1047 cell->children.back()->str = "\\SRC_EN";
1049 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
1050 cell->children.back()->str = "\\SRC";
1052 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
1053 cell->children.back()->str = "\\DST_EN";
1055 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
1056 cell->children.back()->str = "\\DST";
1062 ',' specify_triple {
1070 TOK_IF '(' expr ')' {
1078 TOK_SPECIFY_AND expr {
1087 $$ = new specify_target;
1088 $$->polarity_op = 0;
1092 '(' expr ':' expr ')'{
1093 $$ = new specify_target;
1094 $$->polarity_op = 0;
1098 '(' expr TOK_NEG_INDEXED expr ')'{
1099 $$ = new specify_target;
1100 $$->polarity_op = '-';
1104 '(' expr TOK_POS_INDEXED expr ')'{
1105 $$ = new specify_target;
1106 $$->polarity_op = '+';
1112 TOK_POSEDGE { $$ = 'p'; } |
1113 TOK_NEGEDGE { $$ = 'n'; } |
1118 $$ = new specify_rise_fall;
1120 $$->fall.t_min = $1->t_min->clone();
1121 $$->fall.t_avg = $1->t_avg->clone();
1122 $$->fall.t_max = $1->t_max->clone();
1125 '(' specify_triple ',' specify_triple ')' {
1126 $$ = new specify_rise_fall;
1132 '(' specify_triple ',' specify_triple ',' specify_triple ')' {
1133 $$ = new specify_rise_fall;
1139 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1141 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1142 $$ = new specify_rise_fall;
1151 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1153 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1154 $$ = new specify_rise_fall;
1169 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1174 $$ = new specify_triple;
1176 $$->t_avg = $1->clone();
1177 $$->t_max = $1->clone();
1179 expr ':' expr ':' expr {
1180 $$ = new specify_triple;
1186 /******************** ignored specify parser **************************/
1188 ignored_specify_block:
1189 TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
1190 TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
1192 ignored_specify_item_opt:
1193 ignored_specify_item_opt ignored_specify_item |
1194 ignored_specify_item ;
1196 ignored_specify_item:
1197 specparam_declaration
1198 // | pulsestyle_declaration
1199 // | showcancelled_declaration
1201 | system_timing_declaration
1204 specparam_declaration:
1205 TOK_SPECPARAM list_of_specparam_assignments ';' |
1206 TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ;
1208 // IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match
1209 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
1210 // exxxxtending this for SV specparam would change this anyhow
1212 '[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
1214 list_of_specparam_assignments:
1215 specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
1217 specparam_assignment:
1218 ignspec_id '=' ignspec_expr ;
1221 TOK_IF '(' ignspec_expr ')' | /* empty */;
1224 simple_path_declaration ';'
1225 // | edge_sensitive_path_declaration
1226 // | state_dependent_path_declaration
1229 simple_path_declaration :
1230 ignspec_opt_cond parallel_path_description '=' path_delay_value |
1231 ignspec_opt_cond full_path_description '=' path_delay_value
1235 '(' ignspec_expr list_of_path_delay_extra_expressions ')'
1237 | ignspec_expr list_of_path_delay_extra_expressions
1240 list_of_path_delay_extra_expressions :
1242 | ',' ignspec_expr list_of_path_delay_extra_expressions
1245 specify_edge_identifier :
1246 TOK_POSEDGE | TOK_NEGEDGE ;
1248 parallel_path_description :
1249 '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
1250 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
1251 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
1253 full_path_description :
1254 '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
1255 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
1256 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
1258 // This was broken into 2 rules to solve shift/reduce conflicts
1259 list_of_path_inputs :
1260 specify_input_terminal_descriptor opt_polarity_operator |
1261 specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
1264 ',' specify_input_terminal_descriptor |
1265 more_path_inputs ',' specify_input_terminal_descriptor ;
1267 list_of_path_outputs :
1268 specify_output_terminal_descriptor |
1269 list_of_path_outputs ',' specify_output_terminal_descriptor ;
1271 opt_polarity_operator :
1276 // Good enough for the time being
1277 specify_input_terminal_descriptor :
1280 // Good enough for the time being
1281 specify_output_terminal_descriptor :
1284 system_timing_declaration :
1285 ignspec_id '(' system_timing_args ')' ';' ;
1288 TOK_POSEDGE ignspec_id |
1289 TOK_NEGEDGE ignspec_id |
1292 system_timing_args :
1294 system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
1295 system_timing_args ',' system_timing_arg ;
1297 // for the time being this is OK, but we may write our own expr here.
1298 // as I'm not sure it is legal to use a full expr here (probably not)
1299 // On the other hand, other rules requiring constant expressions also use 'expr'
1300 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
1301 ignspec_constant_expression:
1302 expr { delete $1; };
1305 expr { delete $1; } |
1306 expr ':' expr ':' expr {
1313 TOK_ID { delete $1; }
1314 range_or_multirange { delete $3; };
1316 /**********************************************************************/
1320 astbuf1->is_signed = true;
1325 if (astbuf1->children.size() != 1)
1326 frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
1327 astbuf1->children.push_back(new AstNode(AST_RANGE));
1328 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
1329 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
1330 astbuf1->is_signed = true;
1335 if (astbuf1->children.size() != 1)
1336 frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
1337 astbuf1->children.push_back(new AstNode(AST_REALVALUE));
1343 if (astbuf1->children.size() != 1)
1344 frontend_verilog_yyerror("integer/real parameters should not have a range.");
1345 astbuf1->children.push_back($1);
1350 param_signed param_integer param_real param_range |
1351 hierarchical_type_id {
1352 astbuf1->is_custom_type = true;
1353 astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
1354 astbuf1->children.back()->str = *$1;
1358 attr TOK_PARAMETER {
1359 astbuf1 = new AstNode(AST_PARAMETER);
1360 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1361 append_attr(astbuf1, $1);
1362 } param_type param_decl_list ';' {
1367 attr TOK_LOCALPARAM {
1368 astbuf1 = new AstNode(AST_LOCALPARAM);
1369 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1370 append_attr(astbuf1, $1);
1371 } param_type param_decl_list ';' {
1376 single_param_decl | param_decl_list ',' single_param_decl;
1381 if (astbuf1 == nullptr) {
1383 frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword");
1384 node = new AstNode(AST_PARAMETER);
1385 node->children.push_back(AstNode::mkconst_int(0, true));
1387 node = astbuf1->clone();
1390 delete node->children[0];
1391 node->children[0] = $3;
1392 ast_stack.back()->children.push_back(node);
1397 TOK_DEFPARAM defparam_decl_list ';';
1400 single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
1402 single_defparam_decl:
1403 range rvalue '=' expr {
1404 AstNode *node = new AstNode(AST_DEFPARAM);
1405 node->children.push_back($2);
1406 node->children.push_back($4);
1408 node->children.push_back($1);
1409 ast_stack.back()->children.push_back(node);
1416 enum_type: TOK_ENUM {
1417 static int enum_count;
1418 // create parent node for the enum
1419 astbuf2 = new AstNode(AST_ENUM);
1420 ast_stack.back()->children.push_back(astbuf2);
1421 astbuf2->str = std::string("$enum");
1422 astbuf2->str += std::to_string(enum_count++);
1423 // create the template for the names
1424 astbuf1 = new AstNode(AST_ENUM_ITEM);
1425 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1426 } enum_base_type '{' enum_name_list '}' { // create template for the enum vars
1427 auto tnode = astbuf1->clone();
1430 tnode->type = AST_WIRE;
1431 tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
1432 // drop constant but keep any range
1433 delete tnode->children[0];
1434 tnode->children.erase(tnode->children.begin());
1438 enum_base_type: type_atom type_signing
1439 | type_vec type_signing range { if ($3) astbuf1->children.push_back($3); }
1440 | /* nothing */ { astbuf1->is_reg = true; addRange(astbuf1); }
1443 type_atom: TOK_INTEGER { astbuf1->is_reg = true; addRange(astbuf1); } // 4-state signed
1444 | TOK_INT { astbuf1->is_reg = true; addRange(astbuf1); } // 2-state signed
1445 | TOK_SHORTINT { astbuf1->is_reg = true; addRange(astbuf1, 15, 0); } // 2-state signed
1446 | TOK_BYTE { astbuf1->is_reg = true; addRange(astbuf1, 7, 0); } // 2-state signed
1449 type_vec: TOK_REG { astbuf1->is_reg = true; } // unsigned
1450 | TOK_LOGIC { astbuf1->is_logic = true; } // unsigned
1454 TOK_SIGNED { astbuf1->is_signed = true; }
1455 | TOK_UNSIGNED { astbuf1->is_signed = false; }
1459 enum_name_list: enum_name_decl
1460 | enum_name_list ',' enum_name_decl
1464 TOK_ID opt_enum_init {
1466 log_assert(astbuf1);
1467 log_assert(astbuf2);
1468 auto node = astbuf1->clone();
1471 SET_AST_NODE_LOC(node, @1, @1);
1472 delete node->children[0];
1473 node->children[0] = $2 ?: new AstNode(AST_NONE);
1474 astbuf2->children.push_back(node);
1479 '=' basic_expr { $$ = $2; } // TODO: restrict this
1480 | /* optional */ { $$ = NULL; }
1485 | enum_var_list ',' enum_var
1489 log_assert(astbuf1);
1490 log_assert(astbuf2);
1491 auto node = astbuf1->clone();
1492 ast_stack.back()->children.push_back(node);
1495 SET_AST_NODE_LOC(node, @1, @1);
1496 node->is_enum = true;
1500 enum_decl: enum_type enum_var_list ';' { delete $1; }
1507 struct_decl: struct_type struct_var_list ';' { delete astbuf2; }
1510 struct_type: struct_union { astbuf2 = new AstNode($1); } opt_packed '{' struct_member_list '}' { $$ = astbuf2; }
1514 TOK_STRUCT { $$ = AST_STRUCT; }
1515 | TOK_UNION { $$ = AST_UNION; }
1519 opt_packed: TOK_PACKED opt_signed_struct
1520 | { frontend_verilog_yyerror("Only PACKED supported at this time"); }
1524 TOK_SIGNED { astbuf2->is_signed = true; }
1525 | TOK_UNSIGNED { astbuf2->is_signed = false; }
1526 | // default is unsigned
1529 struct_member_list: struct_member
1530 | struct_member_list struct_member
1533 struct_member: struct_member_type member_name_list ';' { delete astbuf1; }
1538 | member_name_list ',' member_name
1541 member_name: TOK_ID {
1542 astbuf1->str = $1->substr(1);
1544 auto member_node = astbuf1->clone();
1545 SET_AST_NODE_LOC(member_node, @1, @1);
1546 astbuf2->children.push_back(member_node);
1550 struct_member_type: { astbuf1 = new AstNode(AST_STRUCT_ITEM); } member_type_token_list
1553 member_type_token_list:
1555 | hierarchical_type_id {
1556 // use a clone of the typedef definition nodes
1557 auto template_node = copyTypeDefinition(*$1);
1559 switch (template_node->type) {
1561 template_node->type = AST_STRUCT_ITEM;
1567 frontend_verilog_yyerror("Invalid type for struct member: %s", type2str(template_node->type).c_str());
1570 astbuf1 = template_node;
1574 member_type: type_atom type_signing
1575 | type_vec type_signing range { if ($3) astbuf1->children.push_back($3); }
1578 struct_var_list: struct_var
1579 | struct_var_list ',' struct_var
1582 struct_var: TOK_ID { auto *var_node = astbuf2->clone();
1583 var_node->str = *$1;
1585 SET_AST_NODE_LOC(var_node, @1, @1);
1586 ast_stack.back()->children.push_back(var_node);
1595 attr wire_type range {
1598 astbuf2 = checkRange(astbuf1, $3);
1599 } delay wire_name_list {
1601 if (astbuf2 != NULL)
1605 attr TOK_SUPPLY0 TOK_ID {
1606 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1607 ast_stack.back()->children.back()->str = *$3;
1608 append_attr(ast_stack.back()->children.back(), $1);
1609 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
1610 ast_stack.back()->children.back()->children[0]->str = *$3;
1612 } opt_supply_wires ';' |
1613 attr TOK_SUPPLY1 TOK_ID {
1614 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1615 ast_stack.back()->children.back()->str = *$3;
1616 append_attr(ast_stack.back()->children.back(), $1);
1617 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
1618 ast_stack.back()->children.back()->children[0]->str = *$3;
1620 } opt_supply_wires ';';
1624 opt_supply_wires ',' TOK_ID {
1625 AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
1626 AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
1627 wire_node->str = *$3;
1628 assign_node->children[0]->str = *$3;
1629 ast_stack.back()->children.push_back(wire_node);
1630 ast_stack.back()->children.push_back(assign_node);
1635 wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
1637 wire_name_and_opt_assign:
1639 bool attr_anyconst = false;
1640 bool attr_anyseq = false;
1641 bool attr_allconst = false;
1642 bool attr_allseq = false;
1643 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
1644 delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
1645 ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
1646 attr_anyconst = true;
1648 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
1649 delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
1650 ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
1653 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
1654 delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
1655 ast_stack.back()->children.back()->attributes.erase(ID::allconst);
1656 attr_allconst = true;
1658 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
1659 delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
1660 ast_stack.back()->children.back()->attributes.erase(ID::allseq);
1663 if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
1664 AstNode *wire = new AstNode(AST_IDENTIFIER);
1665 AstNode *fcall = new AstNode(AST_FCALL);
1666 wire->str = ast_stack.back()->children.back()->str;
1667 fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
1669 fcall->str = "\\$anyconst";
1671 fcall->str = "\\$anyseq";
1673 fcall->str = "\\$allconst";
1675 fcall->str = "\\$allseq";
1676 fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
1677 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
1680 wire_name '=' expr {
1681 AstNode *wire = new AstNode(AST_IDENTIFIER);
1682 wire->str = ast_stack.back()->children.back()->str;
1683 if (astbuf1->is_input) {
1684 if (astbuf1->attributes.count(ID::defaultvalue))
1685 delete astbuf1->attributes.at(ID::defaultvalue);
1686 astbuf1->attributes[ID::defaultvalue] = $3;
1688 else if (astbuf1->is_reg || astbuf1->is_logic){
1689 AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
1690 AstNode *block = new AstNode(AST_BLOCK, assign);
1691 AstNode *init = new AstNode(AST_INITIAL, block);
1693 SET_AST_NODE_LOC(assign, @1, @3);
1694 SET_AST_NODE_LOC(block, @1, @3);
1695 SET_AST_NODE_LOC(init, @1, @3);
1697 ast_stack.back()->children.push_back(init);
1700 AstNode *assign = new AstNode(AST_ASSIGN, wire, $3);
1701 SET_AST_NODE_LOC(assign, @1, @3);
1702 ast_stack.back()->children.push_back(assign);
1708 TOK_ID range_or_multirange {
1709 if (astbuf1 == nullptr)
1710 frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node.");
1711 AstNode *node = astbuf1->clone();
1713 append_attr_clone(node, albuf);
1714 if (astbuf2 != NULL)
1715 node->children.push_back(astbuf2->clone());
1717 if (node->is_input || node->is_output)
1718 frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
1719 if (!astbuf2 && !node->is_custom_type) {
1720 addRange(node, 0, 0, false);
1722 rewriteAsMemoryNode(node, $2);
1724 if (current_function_or_task == NULL) {
1725 if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
1726 port_stubs[*$1] = ++port_counter;
1728 if (port_stubs.count(*$1) != 0) {
1729 if (!node->is_input && !node->is_output)
1730 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
1731 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
1732 frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
1733 node->port_id = port_stubs[*$1];
1734 port_stubs.erase(*$1);
1736 if (node->is_input || node->is_output)
1737 frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
1740 if (node->is_input || node->is_output)
1741 node->port_id = current_function_or_task_port_id++;
1743 //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
1744 SET_AST_NODE_LOC(node, @1, @1);
1745 ast_stack.back()->children.push_back(node);
1751 TOK_ASSIGN delay assign_expr_list ';';
1754 assign_expr | assign_expr_list ',' assign_expr;
1758 AstNode *node = new AstNode(AST_ASSIGN, $1, $3);
1759 SET_AST_NODE_LOC(node, @$, @$);
1760 ast_stack.back()->children.push_back(node);
1763 type_name: TOK_ID // first time seen
1764 | TOK_USER_TYPE { if (isInLocalScope($1)) frontend_verilog_yyerror("Duplicate declaration of TYPEDEF '%s'", $1->c_str()+1); }
1768 TOK_TYPEDEF wire_type range type_name range_or_multirange ';' {
1770 astbuf2 = checkRange(astbuf1, $3);
1772 astbuf1->children.push_back(astbuf2);
1776 addRange(astbuf1, 0, 0, false);
1778 rewriteAsMemoryNode(astbuf1, $5);
1780 addTypedefNode($4, astbuf1); }
1781 | TOK_TYPEDEF non_wire_data_type type_name ';' { addTypedefNode($3, $2); }
1791 astbuf1 = new AstNode(AST_CELL);
1792 append_attr(astbuf1, $1);
1793 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
1794 astbuf1->children[0]->str = *$2;
1796 } cell_parameter_list_opt cell_list ';' {
1799 attr tok_prim_wrapper delay {
1800 astbuf1 = new AstNode(AST_PRIMITIVE);
1802 append_attr(astbuf1, $1);
1813 $$ = new std::string("or");
1818 cell_list ',' single_cell;
1822 astbuf2 = astbuf1->clone();
1823 if (astbuf2->type != AST_PRIMITIVE)
1826 ast_stack.back()->children.push_back(astbuf2);
1827 } '(' cell_port_list ')' {
1828 SET_AST_NODE_LOC(astbuf2, @1, @$);
1830 TOK_ID non_opt_range {
1831 astbuf2 = astbuf1->clone();
1832 if (astbuf2->type != AST_PRIMITIVE)
1835 ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
1836 } '(' cell_port_list ')'{
1837 SET_AST_NODE_LOC(astbuf2, @1, @$);
1842 prim_list ',' single_prim;
1847 astbuf2 = astbuf1->clone();
1848 ast_stack.back()->children.push_back(astbuf2);
1849 } '(' cell_port_list ')' {
1850 SET_AST_NODE_LOC(astbuf2, @1, @$);
1853 cell_parameter_list_opt:
1854 '#' '(' cell_parameter_list ')' | /* empty */;
1856 cell_parameter_list:
1857 cell_parameter | cell_parameter_list ',' cell_parameter;
1862 AstNode *node = new AstNode(AST_PARASET);
1863 astbuf1->children.push_back(node);
1864 node->children.push_back($1);
1866 '.' TOK_ID '(' expr ')' {
1867 AstNode *node = new AstNode(AST_PARASET);
1869 astbuf1->children.push_back(node);
1870 node->children.push_back($4);
1875 cell_port_list_rules {
1876 // remove empty args from end of list
1877 while (!astbuf2->children.empty()) {
1878 AstNode *node = astbuf2->children.back();
1879 if (node->type != AST_ARGUMENT) break;
1880 if (!node->children.empty()) break;
1881 if (!node->str.empty()) break;
1882 astbuf2->children.pop_back();
1887 bool has_positional_args = false;
1888 bool has_named_args = false;
1889 for (auto node : astbuf2->children) {
1890 if (node->type != AST_ARGUMENT) continue;
1891 if (node->str.empty())
1892 has_positional_args = true;
1894 has_named_args = true;
1897 if (has_positional_args && has_named_args)
1898 frontend_verilog_yyerror("Mix of positional and named cell ports.");
1901 cell_port_list_rules:
1902 cell_port | cell_port_list_rules ',' cell_port;
1906 AstNode *node = new AstNode(AST_ARGUMENT);
1907 astbuf2->children.push_back(node);
1911 AstNode *node = new AstNode(AST_ARGUMENT);
1912 astbuf2->children.push_back(node);
1913 node->children.push_back($2);
1916 attr '.' TOK_ID '(' expr ')' {
1917 AstNode *node = new AstNode(AST_ARGUMENT);
1919 astbuf2->children.push_back(node);
1920 node->children.push_back($5);
1924 attr '.' TOK_ID '(' ')' {
1925 AstNode *node = new AstNode(AST_ARGUMENT);
1927 astbuf2->children.push_back(node);
1932 AstNode *node = new AstNode(AST_ARGUMENT);
1934 astbuf2->children.push_back(node);
1935 node->children.push_back(new AstNode(AST_IDENTIFIER));
1936 node->children.back()->str = *$3;
1940 attr TOK_WILDCARD_CONNECT {
1942 frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
1943 astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
1946 always_comb_or_latch:
1954 always_or_always_ff:
1963 attr always_or_always_ff {
1964 AstNode *node = new AstNode(AST_ALWAYS);
1965 append_attr(node, $1);
1967 node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
1968 ast_stack.back()->children.push_back(node);
1969 ast_stack.push_back(node);
1971 AstNode *block = new AstNode(AST_BLOCK);
1972 ast_stack.back()->children.push_back(block);
1973 ast_stack.push_back(block);
1975 SET_AST_NODE_LOC(ast_stack.back(), @6, @6);
1976 ast_stack.pop_back();
1978 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
1979 ast_stack.pop_back();
1981 SET_RULE_LOC(@$, @2, @$);
1983 attr always_comb_or_latch {
1984 AstNode *node = new AstNode(AST_ALWAYS);
1985 append_attr(node, $1);
1987 node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
1989 node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
1990 ast_stack.back()->children.push_back(node);
1991 ast_stack.push_back(node);
1992 AstNode *block = new AstNode(AST_BLOCK);
1993 ast_stack.back()->children.push_back(block);
1994 ast_stack.push_back(block);
1996 ast_stack.pop_back();
1997 ast_stack.pop_back();
2000 AstNode *node = new AstNode(AST_INITIAL);
2001 append_attr(node, $1);
2002 ast_stack.back()->children.push_back(node);
2003 ast_stack.push_back(node);
2004 AstNode *block = new AstNode(AST_BLOCK);
2005 ast_stack.back()->children.push_back(block);
2006 ast_stack.push_back(block);
2008 ast_stack.pop_back();
2009 ast_stack.pop_back();
2013 '@' '(' always_events ')' |
2015 '@' ATTR_BEGIN ')' |
2022 always_events TOK_OR always_event |
2023 always_events ',' always_event;
2027 AstNode *node = new AstNode(AST_POSEDGE);
2028 SET_AST_NODE_LOC(node, @1, @1);
2029 ast_stack.back()->children.push_back(node);
2030 node->children.push_back($2);
2033 AstNode *node = new AstNode(AST_NEGEDGE);
2034 SET_AST_NODE_LOC(node, @1, @1);
2035 ast_stack.back()->children.push_back(node);
2036 node->children.push_back($2);
2039 AstNode *node = new AstNode(AST_EDGE);
2040 ast_stack.back()->children.push_back(node);
2041 node->children.push_back($1);
2072 TOK_MODPORT TOK_ID {
2073 AstNode *modport = new AstNode(AST_MODPORT);
2074 ast_stack.back()->children.push_back(modport);
2075 ast_stack.push_back(modport);
2078 } modport_args_opt {
2079 ast_stack.pop_back();
2080 log_assert(ast_stack.size() == 2);
2084 '(' ')' | '(' modport_args optional_comma ')';
2087 modport_arg | modport_args ',' modport_arg;
2090 modport_type_token modport_member |
2095 AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
2096 ast_stack.back()->children.push_back(modport_member);
2097 modport_member->str = *$1;
2098 modport_member->is_input = current_modport_input;
2099 modport_member->is_output = current_modport_output;
2104 TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
2107 opt_sva_label TOK_ASSERT opt_property '(' expr ')' ';' {
2108 if (noassert_mode) {
2111 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2112 SET_AST_NODE_LOC(node, @1, @6);
2115 ast_stack.back()->children.push_back(node);
2120 opt_sva_label TOK_ASSUME opt_property '(' expr ')' ';' {
2121 if (noassume_mode) {
2124 AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
2125 SET_AST_NODE_LOC(node, @1, @6);
2128 ast_stack.back()->children.push_back(node);
2133 opt_sva_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2134 if (noassert_mode) {
2137 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2138 SET_AST_NODE_LOC(node, @1, @7);
2141 ast_stack.back()->children.push_back(node);
2146 opt_sva_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2147 if (noassume_mode) {
2150 AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
2151 SET_AST_NODE_LOC(node, @1, @7);
2154 ast_stack.back()->children.push_back(node);
2159 opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
2160 AstNode *node = new AstNode(AST_COVER, $5);
2161 SET_AST_NODE_LOC(node, @1, @6);
2162 if ($1 != nullptr) {
2166 ast_stack.back()->children.push_back(node);
2168 opt_sva_label TOK_COVER opt_property '(' ')' ';' {
2169 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2170 SET_AST_NODE_LOC(node, @1, @5);
2171 if ($1 != nullptr) {
2175 ast_stack.back()->children.push_back(node);
2177 opt_sva_label TOK_COVER ';' {
2178 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2179 SET_AST_NODE_LOC(node, @1, @2);
2180 if ($1 != nullptr) {
2184 ast_stack.back()->children.push_back(node);
2186 opt_sva_label TOK_RESTRICT opt_property '(' expr ')' ';' {
2187 if (norestrict_mode) {
2190 AstNode *node = new AstNode(AST_ASSUME, $5);
2191 SET_AST_NODE_LOC(node, @1, @6);
2194 ast_stack.back()->children.push_back(node);
2197 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2201 opt_sva_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2202 if (norestrict_mode) {
2205 AstNode *node = new AstNode(AST_FAIR, $6);
2206 SET_AST_NODE_LOC(node, @1, @7);
2209 ast_stack.back()->children.push_back(node);
2212 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2218 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
2219 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2220 SET_AST_NODE_LOC(node, @1, @6);
2221 ast_stack.back()->children.push_back(node);
2222 if ($1 != nullptr) {
2223 ast_stack.back()->children.back()->str = *$1;
2227 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
2228 AstNode *node = new AstNode(AST_ASSUME, $5);
2229 SET_AST_NODE_LOC(node, @1, @6);
2230 ast_stack.back()->children.push_back(node);
2231 if ($1 != nullptr) {
2232 ast_stack.back()->children.back()->str = *$1;
2236 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2237 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2238 SET_AST_NODE_LOC(node, @1, @7);
2239 ast_stack.back()->children.push_back(node);
2240 if ($1 != nullptr) {
2241 ast_stack.back()->children.back()->str = *$1;
2245 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2246 AstNode *node = new AstNode(AST_FAIR, $6);
2247 SET_AST_NODE_LOC(node, @1, @7);
2248 ast_stack.back()->children.push_back(node);
2249 if ($1 != nullptr) {
2250 ast_stack.back()->children.back()->str = *$1;
2254 opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
2255 AstNode *node = new AstNode(AST_COVER, $5);
2256 SET_AST_NODE_LOC(node, @1, @6);
2257 ast_stack.back()->children.push_back(node);
2258 if ($1 != nullptr) {
2259 ast_stack.back()->children.back()->str = *$1;
2263 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
2264 if (norestrict_mode) {
2267 AstNode *node = new AstNode(AST_ASSUME, $5);
2268 SET_AST_NODE_LOC(node, @1, @6);
2269 ast_stack.back()->children.push_back(node);
2270 if ($1 != nullptr) {
2271 ast_stack.back()->children.back()->str = *$1;
2276 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2277 if (norestrict_mode) {
2280 AstNode *node = new AstNode(AST_FAIR, $6);
2281 SET_AST_NODE_LOC(node, @1, @7);
2282 ast_stack.back()->children.push_back(node);
2283 if ($1 != nullptr) {
2284 ast_stack.back()->children.back()->str = *$1;
2290 simple_behavioral_stmt:
2291 lvalue '=' delay expr {
2292 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4);
2293 ast_stack.back()->children.push_back(node);
2294 SET_AST_NODE_LOC(node, @1, @4);
2296 lvalue TOK_INCREMENT {
2297 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true)));
2298 ast_stack.back()->children.push_back(node);
2299 SET_AST_NODE_LOC(node, @1, @2);
2301 lvalue TOK_DECREMENT {
2302 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true)));
2303 ast_stack.back()->children.push_back(node);
2304 SET_AST_NODE_LOC(node, @1, @2);
2306 lvalue OP_LE delay expr {
2307 AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4);
2308 ast_stack.back()->children.push_back(node);
2309 SET_AST_NODE_LOC(node, @1, @4);
2312 // this production creates the obligatory if-else shift/reduce conflict
2314 defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
2315 non_opt_delay behavioral_stmt |
2316 simple_behavioral_stmt ';' | ';' |
2317 hierarchical_id attr {
2318 AstNode *node = new AstNode(AST_TCALL);
2321 ast_stack.back()->children.push_back(node);
2322 ast_stack.push_back(node);
2323 append_attr(node, $2);
2325 ast_stack.pop_back();
2327 TOK_MSG_TASKS attr {
2328 AstNode *node = new AstNode(AST_TCALL);
2331 ast_stack.back()->children.push_back(node);
2332 ast_stack.push_back(node);
2333 append_attr(node, $2);
2335 ast_stack.pop_back();
2340 AstNode *node = new AstNode(AST_BLOCK);
2341 ast_stack.back()->children.push_back(node);
2342 ast_stack.push_back(node);
2343 append_attr(node, $1);
2346 } behavioral_stmt_list TOK_END opt_label {
2348 if ($4 != NULL && $8 != NULL && *$4 != *$8)
2349 frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
2350 SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
2353 ast_stack.pop_back();
2356 AstNode *node = new AstNode(AST_FOR);
2357 ast_stack.back()->children.push_back(node);
2358 ast_stack.push_back(node);
2359 append_attr(node, $1);
2360 } simple_behavioral_stmt ';' expr {
2361 ast_stack.back()->children.push_back($7);
2362 } ';' simple_behavioral_stmt ')' {
2363 AstNode *block = new AstNode(AST_BLOCK);
2364 ast_stack.back()->children.push_back(block);
2365 ast_stack.push_back(block);
2367 SET_AST_NODE_LOC(ast_stack.back(), @13, @13);
2368 ast_stack.pop_back();
2369 SET_AST_NODE_LOC(ast_stack.back(), @2, @13);
2370 ast_stack.pop_back();
2372 attr TOK_WHILE '(' expr ')' {
2373 AstNode *node = new AstNode(AST_WHILE);
2374 ast_stack.back()->children.push_back(node);
2375 ast_stack.push_back(node);
2376 append_attr(node, $1);
2377 AstNode *block = new AstNode(AST_BLOCK);
2378 ast_stack.back()->children.push_back($4);
2379 ast_stack.back()->children.push_back(block);
2380 ast_stack.push_back(block);
2382 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2383 ast_stack.pop_back();
2384 ast_stack.pop_back();
2386 attr TOK_REPEAT '(' expr ')' {
2387 AstNode *node = new AstNode(AST_REPEAT);
2388 ast_stack.back()->children.push_back(node);
2389 ast_stack.push_back(node);
2390 append_attr(node, $1);
2391 AstNode *block = new AstNode(AST_BLOCK);
2392 ast_stack.back()->children.push_back($4);
2393 ast_stack.back()->children.push_back(block);
2394 ast_stack.push_back(block);
2396 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2397 ast_stack.pop_back();
2398 ast_stack.pop_back();
2400 attr TOK_IF '(' expr ')' {
2401 AstNode *node = new AstNode(AST_CASE);
2402 AstNode *block = new AstNode(AST_BLOCK);
2403 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
2404 SET_AST_NODE_LOC(cond, @4, @4);
2405 ast_stack.back()->children.push_back(node);
2406 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
2407 node->children.push_back(cond);
2408 ast_stack.push_back(node);
2409 ast_stack.push_back(block);
2410 append_attr(node, $1);
2412 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2414 ast_stack.pop_back();
2415 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2416 ast_stack.pop_back();
2418 case_attr case_type '(' expr ')' {
2419 AstNode *node = new AstNode(AST_CASE, $4);
2420 ast_stack.back()->children.push_back(node);
2421 ast_stack.push_back(node);
2422 append_attr(node, $1);
2423 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2424 } opt_synopsys_attr case_body TOK_ENDCASE {
2425 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2426 case_type_stack.pop_back();
2427 ast_stack.pop_back();
2436 TOK_PRIORITY case_attr {
2439 TOK_UNIQUE case_attr {
2444 attr unique_case_attr {
2445 if ($2) (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false);
2451 case_type_stack.push_back(0);
2454 case_type_stack.push_back('x');
2457 case_type_stack.push_back('z');
2461 opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
2462 if (ast_stack.back()->attributes.count(ID::full_case) == 0)
2463 ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
2465 opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
2466 if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
2467 ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
2471 behavioral_stmt_list:
2472 behavioral_stmt_list behavioral_stmt |
2477 AstNode *block = new AstNode(AST_BLOCK);
2478 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
2479 SET_AST_NODE_LOC(cond, @1, @1);
2481 ast_stack.pop_back();
2482 ast_stack.back()->children.push_back(cond);
2483 ast_stack.push_back(block);
2485 SET_AST_NODE_LOC(ast_stack.back(), @3, @3);
2487 /* empty */ %prec FAKE_THEN;
2490 case_body case_item |
2495 AstNode *node = new AstNode(
2496 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2497 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2498 ast_stack.back()->children.push_back(node);
2499 ast_stack.push_back(node);
2501 AstNode *block = new AstNode(AST_BLOCK);
2502 ast_stack.back()->children.push_back(block);
2503 ast_stack.push_back(block);
2504 case_type_stack.push_back(0);
2506 case_type_stack.pop_back();
2507 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2508 ast_stack.pop_back();
2509 ast_stack.pop_back();
2513 gen_case_body gen_case_item |
2518 AstNode *node = new AstNode(
2519 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2520 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2521 ast_stack.back()->children.push_back(node);
2522 ast_stack.push_back(node);
2524 case_type_stack.push_back(0);
2525 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2526 } gen_stmt_or_null {
2527 case_type_stack.pop_back();
2528 ast_stack.pop_back();
2532 case_expr_list ':' |
2537 AstNode *node = new AstNode(AST_DEFAULT);
2538 SET_AST_NODE_LOC(node, @1, @1);
2539 ast_stack.back()->children.push_back(node);
2542 AstNode *node = new AstNode(AST_IDENTIFIER);
2543 SET_AST_NODE_LOC(node, @1, @1);
2544 ast_stack.back()->children.push_back(node);
2545 ast_stack.back()->children.back()->str = *$1;
2549 ast_stack.back()->children.push_back($1);
2551 case_expr_list ',' expr {
2552 ast_stack.back()->children.push_back($3);
2556 hierarchical_id '[' expr ']' '.' rvalue {
2557 $$ = new AstNode(AST_PREFIX, $3, $6);
2561 hierarchical_id range {
2562 $$ = new AstNode(AST_IDENTIFIER, $2);
2564 SET_AST_NODE_LOC($$, @1, @1);
2566 if ($2 == nullptr && ($$->str == "\\$initstate" ||
2567 $$->str == "\\$anyconst" || $$->str == "\\$anyseq" ||
2568 $$->str == "\\$allconst" || $$->str == "\\$allseq"))
2569 $$->type = AST_FCALL;
2571 hierarchical_id non_opt_multirange {
2572 $$ = new AstNode(AST_IDENTIFIER, $2);
2574 SET_AST_NODE_LOC($$, @1, @1);
2582 '{' lvalue_concat_list '}' {
2588 $$ = new AstNode(AST_CONCAT);
2589 $$->children.push_back($1);
2591 expr ',' lvalue_concat_list {
2593 $$->children.push_back($1);
2597 '(' arg_list optional_comma ')' |
2606 arg_list ',' single_arg;
2610 ast_stack.back()->children.push_back($1);
2614 module_gen_body gen_stmt_or_module_body_stmt |
2617 gen_stmt_or_module_body_stmt:
2618 gen_stmt | module_body_stmt;
2620 // this production creates the obligatory if-else shift/reduce conflict
2623 AstNode *node = new AstNode(AST_GENFOR);
2624 ast_stack.back()->children.push_back(node);
2625 ast_stack.push_back(node);
2626 } simple_behavioral_stmt ';' expr {
2627 ast_stack.back()->children.push_back($6);
2628 } ';' simple_behavioral_stmt ')' gen_stmt_block {
2629 SET_AST_NODE_LOC(ast_stack.back(), @1, @11);
2630 ast_stack.pop_back();
2632 TOK_IF '(' expr ')' {
2633 AstNode *node = new AstNode(AST_GENIF);
2634 ast_stack.back()->children.push_back(node);
2635 ast_stack.push_back(node);
2636 ast_stack.back()->children.push_back($3);
2637 AstNode *block = new AstNode(AST_GENBLOCK);
2638 ast_stack.back()->children.push_back(block);
2639 ast_stack.push_back(block);
2640 } gen_stmt_or_null {
2641 ast_stack.pop_back();
2643 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2644 ast_stack.pop_back();
2646 case_type '(' expr ')' {
2647 AstNode *node = new AstNode(AST_GENCASE, $3);
2648 ast_stack.back()->children.push_back(node);
2649 ast_stack.push_back(node);
2650 } gen_case_body TOK_ENDCASE {
2651 case_type_stack.pop_back();
2652 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2653 ast_stack.pop_back();
2658 AstNode *node = new AstNode(AST_GENBLOCK);
2659 node->str = $3 ? *$3 : std::string();
2660 ast_stack.back()->children.push_back(node);
2661 ast_stack.push_back(node);
2662 } module_gen_body TOK_END opt_label {
2666 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2667 ast_stack.pop_back();
2670 AstNode *node = new AstNode(AST_TECALL);
2673 ast_stack.back()->children.push_back(node);
2674 ast_stack.push_back(node);
2676 SET_AST_NODE_LOC(ast_stack.back(), @1, @3);
2677 ast_stack.pop_back();
2682 AstNode *node = new AstNode(AST_GENBLOCK);
2683 ast_stack.back()->children.push_back(node);
2684 ast_stack.push_back(node);
2685 } gen_stmt_or_module_body_stmt {
2686 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2687 ast_stack.pop_back();
2691 gen_stmt_block | ';';
2694 TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
2700 basic_expr '?' attr expr ':' expr {
2701 $$ = new AstNode(AST_TERNARY);
2702 $$->children.push_back($1);
2703 $$->children.push_back($4);
2704 $$->children.push_back($6);
2705 SET_AST_NODE_LOC($$, @1, @$);
2706 append_attr($$, $3);
2713 '(' expr ')' integral_number {
2714 if ($4->compare(0, 1, "'") != 0)
2715 frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
2717 AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2719 log_error("Value conversion failed: `%s'\n", $4->c_str());
2720 $$ = new AstNode(AST_TO_BITS, bits, val);
2723 hierarchical_id integral_number {
2724 if ($2->compare(0, 1, "'") != 0)
2725 frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
2726 AstNode *bits = new AstNode(AST_IDENTIFIER);
2728 SET_AST_NODE_LOC(bits, @1, @1);
2729 AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2730 SET_AST_NODE_LOC(val, @2, @2);
2732 log_error("Value conversion failed: `%s'\n", $2->c_str());
2733 $$ = new AstNode(AST_TO_BITS, bits, val);
2738 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2739 SET_AST_NODE_LOC($$, @1, @1);
2741 log_error("Value conversion failed: `%s'\n", $1->c_str());
2745 $$ = new AstNode(AST_REALVALUE);
2746 char *p = (char*)malloc(GetSize(*$1) + 1), *q;
2747 for (int i = 0, j = 0; j < GetSize(*$1); j++)
2748 if ((*$1)[j] != '_')
2749 p[i++] = (*$1)[j], p[i] = 0;
2750 $$->realvalue = strtod(p, &q);
2751 SET_AST_NODE_LOC($$, @1, @1);
2752 log_assert(*q == 0);
2757 $$ = AstNode::mkconst_str(*$1);
2758 SET_AST_NODE_LOC($$, @1, @1);
2761 hierarchical_id attr {
2762 AstNode *node = new AstNode(AST_FCALL);
2765 ast_stack.push_back(node);
2766 SET_AST_NODE_LOC(node, @1, @1);
2767 append_attr(node, $2);
2768 } '(' arg_list optional_comma ')' {
2769 $$ = ast_stack.back();
2770 ast_stack.pop_back();
2772 TOK_TO_SIGNED attr '(' expr ')' {
2773 $$ = new AstNode(AST_TO_SIGNED, $4);
2774 append_attr($$, $2);
2776 TOK_TO_UNSIGNED attr '(' expr ')' {
2777 $$ = new AstNode(AST_TO_UNSIGNED, $4);
2778 append_attr($$, $2);
2783 '(' expr ':' expr ':' expr ')' {
2788 '{' concat_list '}' {
2791 '{' expr '{' concat_list '}' '}' {
2792 $$ = new AstNode(AST_REPLICATE, $2, $4);
2794 '~' attr basic_expr %prec UNARY_OPS {
2795 $$ = new AstNode(AST_BIT_NOT, $3);
2796 SET_AST_NODE_LOC($$, @1, @3);
2797 append_attr($$, $2);
2799 basic_expr '&' attr basic_expr {
2800 $$ = new AstNode(AST_BIT_AND, $1, $4);
2801 SET_AST_NODE_LOC($$, @1, @4);
2802 append_attr($$, $3);
2804 basic_expr OP_NAND attr basic_expr {
2805 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
2806 SET_AST_NODE_LOC($$, @1, @4);
2807 append_attr($$, $3);
2809 basic_expr '|' attr basic_expr {
2810 $$ = new AstNode(AST_BIT_OR, $1, $4);
2811 SET_AST_NODE_LOC($$, @1, @4);
2812 append_attr($$, $3);
2814 basic_expr OP_NOR attr basic_expr {
2815 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
2816 SET_AST_NODE_LOC($$, @1, @4);
2817 append_attr($$, $3);
2819 basic_expr '^' attr basic_expr {
2820 $$ = new AstNode(AST_BIT_XOR, $1, $4);
2821 SET_AST_NODE_LOC($$, @1, @4);
2822 append_attr($$, $3);
2824 basic_expr OP_XNOR attr basic_expr {
2825 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
2826 SET_AST_NODE_LOC($$, @1, @4);
2827 append_attr($$, $3);
2829 '&' attr basic_expr %prec UNARY_OPS {
2830 $$ = new AstNode(AST_REDUCE_AND, $3);
2831 SET_AST_NODE_LOC($$, @1, @3);
2832 append_attr($$, $2);
2834 OP_NAND attr basic_expr %prec UNARY_OPS {
2835 $$ = new AstNode(AST_REDUCE_AND, $3);
2836 SET_AST_NODE_LOC($$, @1, @3);
2837 append_attr($$, $2);
2838 $$ = new AstNode(AST_LOGIC_NOT, $$);
2840 '|' attr basic_expr %prec UNARY_OPS {
2841 $$ = new AstNode(AST_REDUCE_OR, $3);
2842 SET_AST_NODE_LOC($$, @1, @3);
2843 append_attr($$, $2);
2845 OP_NOR attr basic_expr %prec UNARY_OPS {
2846 $$ = new AstNode(AST_REDUCE_OR, $3);
2847 SET_AST_NODE_LOC($$, @1, @3);
2848 append_attr($$, $2);
2849 $$ = new AstNode(AST_LOGIC_NOT, $$);
2850 SET_AST_NODE_LOC($$, @1, @3);
2852 '^' attr basic_expr %prec UNARY_OPS {
2853 $$ = new AstNode(AST_REDUCE_XOR, $3);
2854 SET_AST_NODE_LOC($$, @1, @3);
2855 append_attr($$, $2);
2857 OP_XNOR attr basic_expr %prec UNARY_OPS {
2858 $$ = new AstNode(AST_REDUCE_XNOR, $3);
2859 SET_AST_NODE_LOC($$, @1, @3);
2860 append_attr($$, $2);
2862 basic_expr OP_SHL attr basic_expr {
2863 $$ = new AstNode(AST_SHIFT_LEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2864 SET_AST_NODE_LOC($$, @1, @4);
2865 append_attr($$, $3);
2867 basic_expr OP_SHR attr basic_expr {
2868 $$ = new AstNode(AST_SHIFT_RIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2869 SET_AST_NODE_LOC($$, @1, @4);
2870 append_attr($$, $3);
2872 basic_expr OP_SSHL attr basic_expr {
2873 $$ = new AstNode(AST_SHIFT_SLEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2874 SET_AST_NODE_LOC($$, @1, @4);
2875 append_attr($$, $3);
2877 basic_expr OP_SSHR attr basic_expr {
2878 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2879 SET_AST_NODE_LOC($$, @1, @4);
2880 append_attr($$, $3);
2882 basic_expr '<' attr basic_expr {
2883 $$ = new AstNode(AST_LT, $1, $4);
2884 SET_AST_NODE_LOC($$, @1, @4);
2885 append_attr($$, $3);
2887 basic_expr OP_LE attr basic_expr {
2888 $$ = new AstNode(AST_LE, $1, $4);
2889 SET_AST_NODE_LOC($$, @1, @4);
2890 append_attr($$, $3);
2892 basic_expr OP_EQ attr basic_expr {
2893 $$ = new AstNode(AST_EQ, $1, $4);
2894 SET_AST_NODE_LOC($$, @1, @4);
2895 append_attr($$, $3);
2897 basic_expr OP_NE attr basic_expr {
2898 $$ = new AstNode(AST_NE, $1, $4);
2899 SET_AST_NODE_LOC($$, @1, @4);
2900 append_attr($$, $3);
2902 basic_expr OP_EQX attr basic_expr {
2903 $$ = new AstNode(AST_EQX, $1, $4);
2904 SET_AST_NODE_LOC($$, @1, @4);
2905 append_attr($$, $3);
2907 basic_expr OP_NEX attr basic_expr {
2908 $$ = new AstNode(AST_NEX, $1, $4);
2909 SET_AST_NODE_LOC($$, @1, @4);
2910 append_attr($$, $3);
2912 basic_expr OP_GE attr basic_expr {
2913 $$ = new AstNode(AST_GE, $1, $4);
2914 SET_AST_NODE_LOC($$, @1, @4);
2915 append_attr($$, $3);
2917 basic_expr '>' attr basic_expr {
2918 $$ = new AstNode(AST_GT, $1, $4);
2919 SET_AST_NODE_LOC($$, @1, @4);
2920 append_attr($$, $3);
2922 basic_expr '+' attr basic_expr {
2923 $$ = new AstNode(AST_ADD, $1, $4);
2924 SET_AST_NODE_LOC($$, @1, @4);
2925 append_attr($$, $3);
2927 basic_expr '-' attr basic_expr {
2928 $$ = new AstNode(AST_SUB, $1, $4);
2929 SET_AST_NODE_LOC($$, @1, @4);
2930 append_attr($$, $3);
2932 basic_expr '*' attr basic_expr {
2933 $$ = new AstNode(AST_MUL, $1, $4);
2934 SET_AST_NODE_LOC($$, @1, @4);
2935 append_attr($$, $3);
2937 basic_expr '/' attr basic_expr {
2938 $$ = new AstNode(AST_DIV, $1, $4);
2939 SET_AST_NODE_LOC($$, @1, @4);
2940 append_attr($$, $3);
2942 basic_expr '%' attr basic_expr {
2943 $$ = new AstNode(AST_MOD, $1, $4);
2944 SET_AST_NODE_LOC($$, @1, @4);
2945 append_attr($$, $3);
2947 basic_expr OP_POW attr basic_expr {
2948 $$ = new AstNode(AST_POW, $1, $4);
2949 SET_AST_NODE_LOC($$, @1, @4);
2950 append_attr($$, $3);
2952 '+' attr basic_expr %prec UNARY_OPS {
2953 $$ = new AstNode(AST_POS, $3);
2954 SET_AST_NODE_LOC($$, @1, @3);
2955 append_attr($$, $2);
2957 '-' attr basic_expr %prec UNARY_OPS {
2958 $$ = new AstNode(AST_NEG, $3);
2959 SET_AST_NODE_LOC($$, @1, @3);
2960 append_attr($$, $2);
2962 basic_expr OP_LAND attr basic_expr {
2963 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
2964 SET_AST_NODE_LOC($$, @1, @4);
2965 append_attr($$, $3);
2967 basic_expr OP_LOR attr basic_expr {
2968 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
2969 SET_AST_NODE_LOC($$, @1, @4);
2970 append_attr($$, $3);
2972 '!' attr basic_expr %prec UNARY_OPS {
2973 $$ = new AstNode(AST_LOGIC_NOT, $3);
2974 SET_AST_NODE_LOC($$, @1, @3);
2975 append_attr($$, $2);
2980 $$ = new AstNode(AST_CONCAT, $1);
2982 expr ',' concat_list {
2984 $$->children.push_back($1);
2988 TOK_CONSTVAL { $$ = $1; } |
2989 TOK_UNBASED_UNSIZED_CONSTVAL { $$ = $1; } |
2990 TOK_BASE TOK_BASED_CONSTVAL {
2995 TOK_CONSTVAL TOK_BASE TOK_BASED_CONSTVAL {
2996 $1->append(*$2).append(*$3);