2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The Verilog frontend.
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
29 * This is the actual bison parser for Verilog code. The AST ist created directly
30 * from the bison reduce functions here. Note that this code uses a few global
31 * variables to hold the state of the AST generator and therefore this parser is
40 #include "frontends/verilog/verilog_frontend.h"
41 #include "frontends/verilog/verilog_parser.tab.hh"
42 #include "kernel/log.h"
44 #define YYLEX_PARAM &yylval, &yylloc
48 using namespace VERILOG_FRONTEND;
51 namespace VERILOG_FRONTEND {
53 dict<std::string, int> port_stubs;
54 dict<IdString, AstNode*> *attr_list, default_attr_list;
55 std::stack<dict<IdString, AstNode*> *> attr_list_stack;
56 dict<IdString, AstNode*> *albuf;
57 std::vector<UserTypeMap*> user_type_stack;
58 dict<std::string, AstNode*> pkg_user_types;
59 std::vector<AstNode*> ast_stack;
60 struct AstNode *astbuf1, *astbuf2, *astbuf3;
61 struct AstNode *current_function_or_task;
62 struct AstNode *current_ast, *current_ast_mod;
63 int current_function_or_task_port_id;
64 std::vector<char> case_type_stack;
65 bool do_not_require_port_stubs;
66 bool default_nettype_wire;
67 bool sv_mode, formal_mode, lib_mode, specify_mode;
68 bool noassert_mode, noassume_mode, norestrict_mode;
69 bool assume_asserts_mode, assert_assumes_mode;
70 bool current_wire_rand, current_wire_const;
71 bool current_modport_input, current_modport_output;
76 #define SET_AST_NODE_LOC(WHICH, BEGIN, END) \
77 do { (WHICH)->location.first_line = (BEGIN).first_line; \
78 (WHICH)->location.first_column = (BEGIN).first_column; \
79 (WHICH)->location.last_line = (END).last_line; \
80 (WHICH)->location.last_column = (END).last_column; } while(0)
82 #define SET_RULE_LOC(LHS, BEGIN, END) \
83 do { (LHS).first_line = (BEGIN).first_line; \
84 (LHS).first_column = (BEGIN).first_column; \
85 (LHS).last_line = (END).last_line; \
86 (LHS).last_column = (END).last_column; } while(0)
88 int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
90 static void append_attr(AstNode *ast, dict<IdString, AstNode*> *al)
92 for (auto &it : *al) {
93 if (ast->attributes.count(it.first) > 0)
94 delete ast->attributes[it.first];
95 ast->attributes[it.first] = it.second;
100 static void append_attr_clone(AstNode *ast, dict<IdString, AstNode*> *al)
102 for (auto &it : *al) {
103 if (ast->attributes.count(it.first) > 0)
104 delete ast->attributes[it.first];
105 ast->attributes[it.first] = it.second->clone();
109 static void free_attr(dict<IdString, AstNode*> *al)
116 struct specify_target {
121 struct specify_triple {
122 AstNode *t_min, *t_avg, *t_max;
125 struct specify_rise_fall {
130 static void addTypedefNode(std::string *name, AstNode *node)
133 auto *tnode = new AstNode(AST_TYPEDEF, node);
135 auto user_types = user_type_stack.back();
136 (*user_types)[*name] = tnode;
137 if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {
138 // typedef inside a package so we need the qualified name
139 auto qname = current_ast_mod->str + "::" + (*name).substr(1);
140 pkg_user_types[qname] = tnode;
143 ast_stack.back()->children.push_back(tnode);
146 static void enterTypeScope()
148 auto user_types = new UserTypeMap();
149 user_type_stack.push_back(user_types);
152 static void exitTypeScope()
154 user_type_stack.pop_back();
157 static bool isInLocalScope(const std::string *name)
159 // tests if a name was declared in the current block scope
160 auto user_types = user_type_stack.back();
161 return (user_types->count(*name) > 0);
164 static AstNode *getTypeDefinitionNode(std::string type_name)
166 // return the definition nodes from the typedef statement
167 auto user_types = user_type_stack.back();
168 log_assert(user_types->count(type_name) > 0);
169 auto typedef_node = (*user_types)[type_name];
170 log_assert(typedef_node->type == AST_TYPEDEF);
171 return typedef_node->children[0];
174 static AstNode *copyTypeDefinition(std::string type_name)
176 // return a copy of the template from a typedef definition
177 auto typedef_node = getTypeDefinitionNode(type_name);
178 return typedef_node->clone();
181 static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
183 auto range = new AstNode(AST_RANGE);
184 range->children.push_back(AstNode::mkconst_int(msb, true));
185 range->children.push_back(AstNode::mkconst_int(lsb, true));
186 range->is_signed = isSigned;
190 static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned = true)
192 auto range = makeRange(msb, lsb, isSigned);
193 parent->children.push_back(range);
196 static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
198 if (type_node->range_left >= 0 && type_node->range_right >= 0) {
199 // type already restricts the range
201 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
204 range_node = makeRange(type_node->range_left, type_node->range_right, false);
207 if (range_node && range_node->children.size() != 2) {
208 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
213 static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
215 node->type = AST_MEMORY;
216 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
217 // SV array size [n], rewrite as [n-1:0]
218 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
219 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
221 node->children.push_back(rangeNode);
226 %define api.prefix {frontend_verilog_yy}
229 /* The union is defined in the header, so we need to provide all the
230 * includes it requires
235 #include "frontends/verilog/verilog_frontend.h"
240 struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
241 YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
242 struct specify_target *specify_target_ptr;
243 struct specify_triple *specify_triple_ptr;
244 struct specify_rise_fall *specify_rise_fall_ptr;
249 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
250 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
251 %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL
252 %token <string> TOK_USER_TYPE TOK_PKG_USER_TYPE
253 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
254 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
255 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
256 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
257 %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
258 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
259 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
260 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
261 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
262 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
263 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
264 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
265 %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
266 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
267 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
268 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
269 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
270 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
271 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
272 %token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_UNION
274 %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
275 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
276 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
277 %type <string> type_name
278 %type <ast> opt_enum_init enum_type struct_type non_wire_data_type
279 %type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
280 %type <al> attr case_attr
281 %type <ast> struct_union
283 %type <specify_target_ptr> specify_target
284 %type <specify_triple_ptr> specify_triple specify_opt_triple
285 %type <specify_rise_fall_ptr> specify_rise_fall
286 %type <ast> specify_if specify_condition
287 %type <ch> specify_edge
289 // operator precedence from low to high
295 %left OP_EQ OP_NE OP_EQX OP_NEX
296 %left '<' OP_LE OP_GE '>'
297 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
303 %define parse.error verbose
304 %define parse.lac full
316 ast_stack.push_back(current_ast);
318 ast_stack.pop_back();
319 log_assert(GetSize(ast_stack) == 0);
320 for (auto &it : default_attr_list)
322 default_attr_list.clear();
328 task_func_decl design |
330 localparam_decl design |
331 typedef_decl design |
338 if (attr_list != nullptr)
339 attr_list_stack.push(attr_list);
340 attr_list = new dict<IdString, AstNode*>;
341 for (auto &it : default_attr_list)
342 (*attr_list)[it.first] = it.second->clone();
345 if (!attr_list_stack.empty()) {
346 attr_list = attr_list_stack.top();
347 attr_list_stack.pop();
353 attr_opt ATTR_BEGIN opt_attr_list ATTR_END {
354 SET_RULE_LOC(@$, @2, @$);
360 if (attr_list != nullptr)
361 attr_list_stack.push(attr_list);
362 attr_list = new dict<IdString, AstNode*>;
363 for (auto &it : default_attr_list)
365 default_attr_list.clear();
367 attr_list->swap(default_attr_list);
369 if (!attr_list_stack.empty()) {
370 attr_list = attr_list_stack.top();
371 attr_list_stack.pop();
377 attr_list | /* empty */;
381 attr_list ',' attr_assign;
385 if (attr_list->count(*$1) != 0)
386 delete (*attr_list)[*$1];
387 (*attr_list)[*$1] = AstNode::mkconst_int(1, false);
390 hierarchical_id '=' expr {
391 if (attr_list->count(*$1) != 0)
392 delete (*attr_list)[*$1];
393 (*attr_list)[*$1] = $3;
401 hierarchical_id TOK_PACKAGESEP TOK_ID {
402 if ($3->compare(0, 1, "\\") == 0)
403 *$1 += "::" + $3->substr(1);
409 hierarchical_id '.' TOK_ID {
410 if ($3->compare(0, 1, "\\") == 0)
411 *$1 += "." + $3->substr(1);
418 hierarchical_type_id:
420 | TOK_PKG_USER_TYPE // package qualified type name
421 | '(' TOK_USER_TYPE ')' { $$ = $2; } // non-standard grammar
428 do_not_require_port_stubs = false;
429 AstNode *mod = new AstNode(AST_MODULE);
430 ast_stack.back()->children.push_back(mod);
431 ast_stack.push_back(mod);
432 current_ast_mod = mod;
436 append_attr(mod, $1);
438 } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
439 if (port_stubs.size() != 0)
440 frontend_verilog_yyerror("Missing details for module port `%s'.",
441 port_stubs.begin()->first.c_str());
442 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
443 ast_stack.pop_back();
444 log_assert(ast_stack.size() == 1);
445 current_ast_mod = NULL;
450 '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
453 single_module_para | module_para_list ',' single_module_para;
458 if (astbuf1) delete astbuf1;
459 astbuf1 = new AstNode(AST_PARAMETER);
460 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
461 append_attr(astbuf1, $1);
462 } param_type single_param_decl |
463 attr TOK_LOCALPARAM {
464 if (astbuf1) delete astbuf1;
465 astbuf1 = new AstNode(AST_LOCALPARAM);
466 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
467 append_attr(astbuf1, $1);
468 } param_type single_param_decl |
472 '(' ')' | /* empty */ | '(' module_args optional_comma ')';
475 module_arg | module_args ',' module_arg;
480 module_arg_opt_assignment:
482 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
483 AstNode *wire = new AstNode(AST_IDENTIFIER);
484 wire->str = ast_stack.back()->children.back()->str;
485 if (ast_stack.back()->children.back()->is_input) {
486 AstNode *n = ast_stack.back()->children.back();
487 if (n->attributes.count(ID::defaultvalue))
488 delete n->attributes.at(ID::defaultvalue);
489 n->attributes[ID::defaultvalue] = $2;
491 if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
492 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
494 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
496 frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
502 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
503 AstNode *node = ast_stack.back()->children.back()->clone();
505 node->port_id = ++port_counter;
506 ast_stack.back()->children.push_back(node);
507 SET_AST_NODE_LOC(node, @1, @1);
509 if (port_stubs.count(*$1) != 0)
510 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
511 port_stubs[*$1] = ++port_counter;
514 } module_arg_opt_assignment |
516 astbuf1 = new AstNode(AST_INTERFACEPORT);
517 astbuf1->children.push_back(new AstNode(AST_INTERFACEPORTTYPE));
518 astbuf1->children[0]->str = *$1;
520 } TOK_ID { /* SV interfaces */
522 frontend_verilog_yyerror("Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
523 astbuf2 = astbuf1->clone(); // really only needed if multiple instances of same type.
526 astbuf2->port_id = ++port_counter;
527 ast_stack.back()->children.push_back(astbuf2);
528 delete astbuf1; // really only needed if multiple instances of same type.
529 } module_arg_opt_assignment |
530 attr wire_type range TOK_ID {
533 SET_AST_NODE_LOC(node, @4, @4);
534 node->port_id = ++port_counter;
536 node->children.push_back($3);
537 if (!node->is_input && !node->is_output)
538 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
539 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
540 frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
541 ast_stack.back()->children.push_back(node);
542 append_attr(node, $1);
544 } module_arg_opt_assignment |
546 do_not_require_port_stubs = true;
553 AstNode *mod = new AstNode(AST_PACKAGE);
554 ast_stack.back()->children.push_back(mod);
555 ast_stack.push_back(mod);
556 current_ast_mod = mod;
558 append_attr(mod, $1);
559 } ';' package_body TOK_ENDPACKAGE {
560 ast_stack.pop_back();
561 current_ast_mod = NULL;
566 package_body package_body_stmt
580 do_not_require_port_stubs = false;
581 AstNode *intf = new AstNode(AST_INTERFACE);
582 ast_stack.back()->children.push_back(intf);
583 ast_stack.push_back(intf);
584 current_ast_mod = intf;
589 } module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
590 if (port_stubs.size() != 0)
591 frontend_verilog_yyerror("Missing details for module port `%s'.",
592 port_stubs.begin()->first.c_str());
593 ast_stack.pop_back();
594 log_assert(ast_stack.size() == 1);
595 current_ast_mod = NULL;
600 interface_body interface_body_stmt |;
603 param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
607 '#' TOK_ID { delete $2; } |
608 '#' TOK_CONSTVAL { delete $2; } |
609 '#' TOK_REALVAL { delete $2; } |
610 '#' '(' expr ')' { delete $3; } |
611 '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
614 non_opt_delay | /* empty */;
618 astbuf3 = new AstNode(AST_WIRE);
619 current_wire_rand = false;
620 current_wire_const = false;
621 } wire_type_token_list {
623 SET_RULE_LOC(@$, @2, @$);
626 wire_type_token_list:
628 wire_type_token_list wire_type_token |
630 hierarchical_type_id {
631 astbuf3->is_custom_type = true;
632 astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
633 astbuf3->children.back()->str = *$1;
639 astbuf3->is_input = true;
642 astbuf3->is_output = true;
645 astbuf3->is_input = true;
646 astbuf3->is_output = true;
653 astbuf3->is_wor = true;
656 astbuf3->is_wand = true;
659 astbuf3->is_reg = true;
662 astbuf3->is_logic = true;
665 astbuf3->is_logic = true;
668 astbuf3->is_reg = true;
669 astbuf3->range_left = 31;
670 astbuf3->range_right = 0;
671 astbuf3->is_signed = true;
674 astbuf3->type = AST_GENVAR;
675 astbuf3->is_reg = true;
676 astbuf3->is_signed = true;
677 astbuf3->range_left = 31;
678 astbuf3->range_right = 0;
681 astbuf3->is_signed = true;
684 current_wire_rand = true;
687 current_wire_const = true;
691 '[' expr ':' expr ']' {
692 $$ = new AstNode(AST_RANGE);
693 $$->children.push_back($2);
694 $$->children.push_back($4);
696 '[' expr TOK_POS_INDEXED expr ']' {
697 $$ = new AstNode(AST_RANGE);
698 AstNode *expr = new AstNode(AST_SELFSZ, $2);
699 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
700 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
702 '[' expr TOK_NEG_INDEXED expr ']' {
703 $$ = new AstNode(AST_RANGE);
704 AstNode *expr = new AstNode(AST_SELFSZ, $2);
705 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
706 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
709 $$ = new AstNode(AST_RANGE);
710 $$->children.push_back($2);
714 non_opt_range non_opt_range {
715 $$ = new AstNode(AST_MULTIRANGE, $1, $2);
717 non_opt_multirange non_opt_range {
719 $$->children.push_back($2);
732 non_opt_multirange { $$ = $1; };
736 | TOK_INTEGER { $$ = makeRange(); }
740 module_body module_body_stmt |
741 /* the following line makes the generate..endgenrate keywords optional */
742 module_body gen_stmt |
746 task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
747 enum_decl | struct_decl |
748 always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
751 TOK_CHECKER TOK_ID ';' {
752 AstNode *node = new AstNode(AST_GENBLOCK);
754 ast_stack.back()->children.push_back(node);
755 ast_stack.push_back(node);
756 } module_body TOK_ENDCHECKER {
758 ast_stack.pop_back();
762 attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
763 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
764 current_function_or_task->str = *$4;
765 append_attr(current_function_or_task, $1);
766 ast_stack.back()->children.push_back(current_function_or_task);
769 } opt_dpi_function_args ';' {
770 current_function_or_task = NULL;
772 attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
773 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
774 current_function_or_task->str = *$6;
775 append_attr(current_function_or_task, $1);
776 ast_stack.back()->children.push_back(current_function_or_task);
780 } opt_dpi_function_args ';' {
781 current_function_or_task = NULL;
783 attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
784 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
785 current_function_or_task->str = *$8;
786 append_attr(current_function_or_task, $1);
787 ast_stack.back()->children.push_back(current_function_or_task);
792 } opt_dpi_function_args ';' {
793 current_function_or_task = NULL;
795 attr TOK_TASK opt_automatic TOK_ID {
796 current_function_or_task = new AstNode(AST_TASK);
797 current_function_or_task->str = *$4;
798 append_attr(current_function_or_task, $1);
799 ast_stack.back()->children.push_back(current_function_or_task);
800 ast_stack.push_back(current_function_or_task);
801 current_function_or_task_port_id = 1;
803 } task_func_args_opt ';' task_func_body TOK_ENDTASK {
804 current_function_or_task = NULL;
805 ast_stack.pop_back();
807 attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID {
808 current_function_or_task = new AstNode(AST_FUNCTION);
809 current_function_or_task->str = *$6;
810 append_attr(current_function_or_task, $1);
811 ast_stack.back()->children.push_back(current_function_or_task);
812 ast_stack.push_back(current_function_or_task);
813 AstNode *outreg = new AstNode(AST_WIRE);
815 outreg->is_signed = $4;
816 outreg->is_reg = true;
818 outreg->children.push_back($5);
819 outreg->is_signed = $4 || $5->is_signed;
820 $5->is_signed = false;
822 current_function_or_task->children.push_back(outreg);
823 current_function_or_task_port_id = 1;
825 } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
826 current_function_or_task = NULL;
827 ast_stack.pop_back();
832 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
837 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
841 opt_dpi_function_args:
842 '(' dpi_function_args ')' |
846 dpi_function_args ',' dpi_function_arg |
847 dpi_function_args ',' |
864 '(' ')' | /* empty */ | '(' {
868 } task_func_args optional_comma {
876 task_func_port | task_func_args ',' task_func_port;
879 attr wire_type range {
888 astbuf2 = checkRange(astbuf1, $3);
893 frontend_verilog_yyerror("task/function argument direction missing");
894 albuf = new dict<IdString, AstNode*>;
895 astbuf1 = new AstNode(AST_WIRE);
896 current_wire_rand = false;
897 current_wire_const = false;
898 astbuf1->is_input = true;
904 task_func_body behavioral_stmt |
907 /*************************** specify parser ***************************/
910 TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
913 specify_item specify_item_list |
917 specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
918 AstNode *en_expr = $1;
919 char specify_edge = $3;
920 AstNode *src_expr = $4;
922 specify_target *target = $6;
923 specify_rise_fall *timing = $9;
925 if (specify_edge != 0 && target->dat == nullptr)
926 frontend_verilog_yyerror("Found specify edge but no data spec.\n");
928 AstNode *cell = new AstNode(AST_CELL);
929 ast_stack.back()->children.push_back(cell);
930 cell->str = stringf("$specify$%d", autoidx++);
931 cell->children.push_back(new AstNode(AST_CELLTYPE));
932 cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
933 SET_AST_NODE_LOC(cell, en_expr ? @1 : @2, @10);
935 char oper_polarity = 0;
936 char oper_type = oper->at(0);
938 if (oper->size() == 3) {
939 oper_polarity = oper->at(0);
940 oper_type = oper->at(1);
943 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
944 cell->children.back()->str = "\\FULL";
946 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
947 cell->children.back()->str = "\\SRC_DST_PEN";
949 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
950 cell->children.back()->str = "\\SRC_DST_POL";
952 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
953 cell->children.back()->str = "\\T_RISE_MIN";
955 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
956 cell->children.back()->str = "\\T_RISE_TYP";
958 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
959 cell->children.back()->str = "\\T_RISE_MAX";
961 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
962 cell->children.back()->str = "\\T_FALL_MIN";
964 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
965 cell->children.back()->str = "\\T_FALL_TYP";
967 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
968 cell->children.back()->str = "\\T_FALL_MAX";
970 cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
971 cell->children.back()->str = "\\EN";
973 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
974 cell->children.back()->str = "\\SRC";
976 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
977 cell->children.back()->str = "\\DST";
981 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
982 cell->children.back()->str = "\\EDGE_EN";
984 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
985 cell->children.back()->str = "\\EDGE_POL";
987 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
988 cell->children.back()->str = "\\DAT_DST_PEN";
990 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
991 cell->children.back()->str = "\\DAT_DST_POL";
993 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
994 cell->children.back()->str = "\\DAT";
1001 TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' specify_triple specify_opt_triple ')' ';' {
1002 if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
1003 *$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
1004 frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
1006 AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
1007 AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
1008 AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
1010 AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
1011 AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
1012 AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
1014 specify_triple *limit = $11;
1015 specify_triple *limit2 = $12;
1017 AstNode *cell = new AstNode(AST_CELL);
1018 ast_stack.back()->children.push_back(cell);
1019 cell->str = stringf("$specify$%d", autoidx++);
1020 cell->children.push_back(new AstNode(AST_CELLTYPE));
1021 cell->children.back()->str = "$specrule";
1022 SET_AST_NODE_LOC(cell, @1, @14);
1024 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
1025 cell->children.back()->str = "\\TYPE";
1027 cell->children.push_back(new AstNode(AST_PARASET, limit->t_min));
1028 cell->children.back()->str = "\\T_LIMIT_MIN";
1030 cell->children.push_back(new AstNode(AST_PARASET, limit->t_avg));
1031 cell->children.back()->str = "\\T_LIMIT_TYP";
1033 cell->children.push_back(new AstNode(AST_PARASET, limit->t_max));
1034 cell->children.back()->str = "\\T_LIMIT_MAX";
1036 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_min : AstNode::mkconst_int(0, true)));
1037 cell->children.back()->str = "\\T_LIMIT2_MIN";
1039 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_avg : AstNode::mkconst_int(0, true)));
1040 cell->children.back()->str = "\\T_LIMIT2_TYP";
1042 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_max : AstNode::mkconst_int(0, true)));
1043 cell->children.back()->str = "\\T_LIMIT2_MAX";
1045 cell->children.push_back(new AstNode(AST_PARASET, src_pen));
1046 cell->children.back()->str = "\\SRC_PEN";
1048 cell->children.push_back(new AstNode(AST_PARASET, src_pol));
1049 cell->children.back()->str = "\\SRC_POL";
1051 cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
1052 cell->children.back()->str = "\\DST_PEN";
1054 cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
1055 cell->children.back()->str = "\\DST_POL";
1057 cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
1058 cell->children.back()->str = "\\SRC_EN";
1060 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
1061 cell->children.back()->str = "\\SRC";
1063 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
1064 cell->children.back()->str = "\\DST_EN";
1066 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
1067 cell->children.back()->str = "\\DST";
1073 ',' specify_triple {
1081 TOK_IF '(' expr ')' {
1089 TOK_SPECIFY_AND expr {
1098 $$ = new specify_target;
1099 $$->polarity_op = 0;
1103 '(' expr ':' expr ')'{
1104 $$ = new specify_target;
1105 $$->polarity_op = 0;
1109 '(' expr TOK_NEG_INDEXED expr ')'{
1110 $$ = new specify_target;
1111 $$->polarity_op = '-';
1115 '(' expr TOK_POS_INDEXED expr ')'{
1116 $$ = new specify_target;
1117 $$->polarity_op = '+';
1123 TOK_POSEDGE { $$ = 'p'; } |
1124 TOK_NEGEDGE { $$ = 'n'; } |
1129 $$ = new specify_rise_fall;
1131 $$->fall.t_min = $1->t_min->clone();
1132 $$->fall.t_avg = $1->t_avg->clone();
1133 $$->fall.t_max = $1->t_max->clone();
1136 '(' specify_triple ',' specify_triple ')' {
1137 $$ = new specify_rise_fall;
1143 '(' specify_triple ',' specify_triple ',' specify_triple ')' {
1144 $$ = new specify_rise_fall;
1150 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1152 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1153 $$ = new specify_rise_fall;
1162 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1164 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1165 $$ = new specify_rise_fall;
1180 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1185 $$ = new specify_triple;
1187 $$->t_avg = $1->clone();
1188 $$->t_max = $1->clone();
1190 expr ':' expr ':' expr {
1191 $$ = new specify_triple;
1197 /******************** ignored specify parser **************************/
1199 ignored_specify_block:
1200 TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
1201 TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
1203 ignored_specify_item_opt:
1204 ignored_specify_item_opt ignored_specify_item |
1205 ignored_specify_item ;
1207 ignored_specify_item:
1208 specparam_declaration
1209 // | pulsestyle_declaration
1210 // | showcancelled_declaration
1212 | system_timing_declaration
1215 specparam_declaration:
1216 TOK_SPECPARAM list_of_specparam_assignments ';' |
1217 TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ;
1219 // IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match
1220 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
1221 // exxxxtending this for SV specparam would change this anyhow
1223 '[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
1225 list_of_specparam_assignments:
1226 specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
1228 specparam_assignment:
1229 ignspec_id '=' ignspec_expr ;
1232 TOK_IF '(' ignspec_expr ')' | /* empty */;
1235 simple_path_declaration ';'
1236 // | edge_sensitive_path_declaration
1237 // | state_dependent_path_declaration
1240 simple_path_declaration :
1241 ignspec_opt_cond parallel_path_description '=' path_delay_value |
1242 ignspec_opt_cond full_path_description '=' path_delay_value
1246 '(' ignspec_expr list_of_path_delay_extra_expressions ')'
1248 | ignspec_expr list_of_path_delay_extra_expressions
1251 list_of_path_delay_extra_expressions :
1253 | ',' ignspec_expr list_of_path_delay_extra_expressions
1256 specify_edge_identifier :
1257 TOK_POSEDGE | TOK_NEGEDGE ;
1259 parallel_path_description :
1260 '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
1261 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
1262 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
1264 full_path_description :
1265 '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
1266 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
1267 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
1269 // This was broken into 2 rules to solve shift/reduce conflicts
1270 list_of_path_inputs :
1271 specify_input_terminal_descriptor opt_polarity_operator |
1272 specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
1275 ',' specify_input_terminal_descriptor |
1276 more_path_inputs ',' specify_input_terminal_descriptor ;
1278 list_of_path_outputs :
1279 specify_output_terminal_descriptor |
1280 list_of_path_outputs ',' specify_output_terminal_descriptor ;
1282 opt_polarity_operator :
1287 // Good enough for the time being
1288 specify_input_terminal_descriptor :
1291 // Good enough for the time being
1292 specify_output_terminal_descriptor :
1295 system_timing_declaration :
1296 ignspec_id '(' system_timing_args ')' ';' ;
1299 TOK_POSEDGE ignspec_id |
1300 TOK_NEGEDGE ignspec_id |
1303 system_timing_args :
1305 system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
1306 system_timing_args ',' system_timing_arg ;
1308 // for the time being this is OK, but we may write our own expr here.
1309 // as I'm not sure it is legal to use a full expr here (probably not)
1310 // On the other hand, other rules requiring constant expressions also use 'expr'
1311 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
1312 ignspec_constant_expression:
1313 expr { delete $1; };
1316 expr { delete $1; } |
1317 expr ':' expr ':' expr {
1324 TOK_ID { delete $1; }
1325 range_or_multirange { delete $3; };
1327 /**********************************************************************/
1331 astbuf1->is_signed = true;
1336 if (astbuf1->children.size() != 1)
1337 frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
1338 astbuf1->children.push_back(new AstNode(AST_RANGE));
1339 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
1340 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
1341 astbuf1->is_signed = true;
1346 if (astbuf1->children.size() != 1)
1347 frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
1348 astbuf1->children.push_back(new AstNode(AST_REALVALUE));
1354 if (astbuf1->children.size() != 1)
1355 frontend_verilog_yyerror("integer/real parameters should not have a range.");
1356 astbuf1->children.push_back($1);
1361 param_signed param_integer param_real param_range |
1362 hierarchical_type_id {
1363 astbuf1->is_custom_type = true;
1364 astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
1365 astbuf1->children.back()->str = *$1;
1369 attr TOK_PARAMETER {
1370 astbuf1 = new AstNode(AST_PARAMETER);
1371 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1372 append_attr(astbuf1, $1);
1373 } param_type param_decl_list ';' {
1378 attr TOK_LOCALPARAM {
1379 astbuf1 = new AstNode(AST_LOCALPARAM);
1380 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1381 append_attr(astbuf1, $1);
1382 } param_type param_decl_list ';' {
1387 single_param_decl | param_decl_list ',' single_param_decl;
1392 if (astbuf1 == nullptr) {
1394 frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword");
1395 node = new AstNode(AST_PARAMETER);
1396 node->children.push_back(AstNode::mkconst_int(0, true));
1398 node = astbuf1->clone();
1401 delete node->children[0];
1402 node->children[0] = $3;
1403 ast_stack.back()->children.push_back(node);
1408 TOK_DEFPARAM defparam_decl_list ';';
1411 single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
1413 single_defparam_decl:
1414 range rvalue '=' expr {
1415 AstNode *node = new AstNode(AST_DEFPARAM);
1416 node->children.push_back($2);
1417 node->children.push_back($4);
1419 node->children.push_back($1);
1420 ast_stack.back()->children.push_back(node);
1427 enum_type: TOK_ENUM {
1428 static int enum_count;
1429 // create parent node for the enum
1430 astbuf2 = new AstNode(AST_ENUM);
1431 ast_stack.back()->children.push_back(astbuf2);
1432 astbuf2->str = std::string("$enum");
1433 astbuf2->str += std::to_string(enum_count++);
1434 // create the template for the names
1435 astbuf1 = new AstNode(AST_ENUM_ITEM);
1436 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1437 } enum_base_type '{' enum_name_list '}' { // create template for the enum vars
1438 auto tnode = astbuf1->clone();
1441 tnode->type = AST_WIRE;
1442 tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
1443 // drop constant but keep any range
1444 delete tnode->children[0];
1445 tnode->children.erase(tnode->children.begin());
1449 enum_base_type: type_atom type_signing
1450 | type_vec type_signing range { if ($3) astbuf1->children.push_back($3); }
1451 | /* nothing */ { astbuf1->is_reg = true; addRange(astbuf1); }
1454 type_atom: TOK_INTEGER { astbuf1->is_reg = true; addRange(astbuf1); } // 4-state signed
1455 | TOK_INT { astbuf1->is_reg = true; addRange(astbuf1); } // 2-state signed
1456 | TOK_SHORTINT { astbuf1->is_reg = true; addRange(astbuf1, 15, 0); } // 2-state signed
1457 | TOK_BYTE { astbuf1->is_reg = true; addRange(astbuf1, 7, 0); } // 2-state signed
1460 type_vec: TOK_REG { astbuf1->is_reg = true; } // unsigned
1461 | TOK_LOGIC { astbuf1->is_logic = true; } // unsigned
1465 TOK_SIGNED { astbuf1->is_signed = true; }
1466 | TOK_UNSIGNED { astbuf1->is_signed = false; }
1470 enum_name_list: enum_name_decl
1471 | enum_name_list ',' enum_name_decl
1475 TOK_ID opt_enum_init {
1477 log_assert(astbuf1);
1478 log_assert(astbuf2);
1479 auto node = astbuf1->clone();
1482 SET_AST_NODE_LOC(node, @1, @1);
1483 delete node->children[0];
1484 node->children[0] = $2 ?: new AstNode(AST_NONE);
1485 astbuf2->children.push_back(node);
1490 '=' basic_expr { $$ = $2; } // TODO: restrict this
1491 | /* optional */ { $$ = NULL; }
1496 | enum_var_list ',' enum_var
1500 log_assert(astbuf1);
1501 log_assert(astbuf2);
1502 auto node = astbuf1->clone();
1503 ast_stack.back()->children.push_back(node);
1506 SET_AST_NODE_LOC(node, @1, @1);
1507 node->is_enum = true;
1511 enum_decl: enum_type enum_var_list ';' { delete $1; }
1518 struct_decl: struct_type struct_var_list ';' { delete astbuf2; }
1521 struct_type: struct_union { astbuf2 = $1; } struct_body { $$ = astbuf2; }
1525 TOK_STRUCT { $$ = new AstNode(AST_STRUCT); }
1526 | TOK_UNION { $$ = new AstNode(AST_UNION); }
1529 struct_body: opt_packed '{' struct_member_list '}'
1532 opt_packed: TOK_PACKED opt_signed_struct
1533 | { frontend_verilog_yyerror("Only PACKED supported at this time"); }
1537 TOK_SIGNED { astbuf2->is_signed = true; }
1538 | TOK_UNSIGNED { astbuf2->is_signed = false; }
1539 | // default is unsigned
1542 struct_member_list: struct_member
1543 | struct_member_list struct_member
1546 struct_member: struct_member_type member_name_list ';' { delete astbuf1; }
1551 | member_name_list ',' member_name
1554 member_name: TOK_ID {
1555 astbuf1->str = $1->substr(1);
1557 astbuf3 = astbuf1->clone();
1558 SET_AST_NODE_LOC(astbuf3, @1, @1);
1559 astbuf2->children.push_back(astbuf3);
1560 } range { if ($3) astbuf3->children.push_back($3); }
1563 struct_member_type: { astbuf1 = new AstNode(AST_STRUCT_ITEM); } member_type_token
1568 | hierarchical_type_id {
1569 // use a clone of the typedef definition nodes
1570 auto template_node = copyTypeDefinition(*$1);
1572 switch (template_node->type) {
1574 template_node->type = AST_STRUCT_ITEM;
1580 frontend_verilog_yyerror("Invalid type for struct member: %s", type2str(template_node->type).c_str());
1583 astbuf1 = template_node;
1586 // stash state on ast_stack
1587 ast_stack.push_back(astbuf2);
1592 astbuf2 = ast_stack.back();
1593 ast_stack.pop_back();
1597 member_type: type_atom type_signing
1598 | type_vec type_signing range_or_multirange { if ($3) astbuf1->children.push_back($3); }
1601 struct_var_list: struct_var
1602 | struct_var_list ',' struct_var
1605 struct_var: TOK_ID { auto *var_node = astbuf2->clone();
1606 var_node->str = *$1;
1608 SET_AST_NODE_LOC(var_node, @1, @1);
1609 ast_stack.back()->children.push_back(var_node);
1618 attr wire_type range {
1621 astbuf2 = checkRange(astbuf1, $3);
1622 } delay wire_name_list {
1624 if (astbuf2 != NULL)
1628 attr TOK_SUPPLY0 TOK_ID {
1629 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1630 ast_stack.back()->children.back()->str = *$3;
1631 append_attr(ast_stack.back()->children.back(), $1);
1632 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
1633 ast_stack.back()->children.back()->children[0]->str = *$3;
1635 } opt_supply_wires ';' |
1636 attr TOK_SUPPLY1 TOK_ID {
1637 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1638 ast_stack.back()->children.back()->str = *$3;
1639 append_attr(ast_stack.back()->children.back(), $1);
1640 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
1641 ast_stack.back()->children.back()->children[0]->str = *$3;
1643 } opt_supply_wires ';';
1647 opt_supply_wires ',' TOK_ID {
1648 AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
1649 AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
1650 wire_node->str = *$3;
1651 assign_node->children[0]->str = *$3;
1652 ast_stack.back()->children.push_back(wire_node);
1653 ast_stack.back()->children.push_back(assign_node);
1658 wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
1660 wire_name_and_opt_assign:
1662 bool attr_anyconst = false;
1663 bool attr_anyseq = false;
1664 bool attr_allconst = false;
1665 bool attr_allseq = false;
1666 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
1667 delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
1668 ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
1669 attr_anyconst = true;
1671 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
1672 delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
1673 ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
1676 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
1677 delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
1678 ast_stack.back()->children.back()->attributes.erase(ID::allconst);
1679 attr_allconst = true;
1681 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
1682 delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
1683 ast_stack.back()->children.back()->attributes.erase(ID::allseq);
1686 if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
1687 AstNode *wire = new AstNode(AST_IDENTIFIER);
1688 AstNode *fcall = new AstNode(AST_FCALL);
1689 wire->str = ast_stack.back()->children.back()->str;
1690 fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
1692 fcall->str = "\\$anyconst";
1694 fcall->str = "\\$anyseq";
1696 fcall->str = "\\$allconst";
1698 fcall->str = "\\$allseq";
1699 fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
1700 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
1703 wire_name '=' expr {
1704 AstNode *wire = new AstNode(AST_IDENTIFIER);
1705 wire->str = ast_stack.back()->children.back()->str;
1706 if (astbuf1->is_input) {
1707 if (astbuf1->attributes.count(ID::defaultvalue))
1708 delete astbuf1->attributes.at(ID::defaultvalue);
1709 astbuf1->attributes[ID::defaultvalue] = $3;
1711 else if (astbuf1->is_reg || astbuf1->is_logic){
1712 AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
1713 AstNode *block = new AstNode(AST_BLOCK, assign);
1714 AstNode *init = new AstNode(AST_INITIAL, block);
1716 SET_AST_NODE_LOC(assign, @1, @3);
1717 SET_AST_NODE_LOC(block, @1, @3);
1718 SET_AST_NODE_LOC(init, @1, @3);
1720 ast_stack.back()->children.push_back(init);
1723 AstNode *assign = new AstNode(AST_ASSIGN, wire, $3);
1724 SET_AST_NODE_LOC(assign, @1, @3);
1725 ast_stack.back()->children.push_back(assign);
1731 TOK_ID range_or_multirange {
1732 if (astbuf1 == nullptr)
1733 frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node.");
1734 AstNode *node = astbuf1->clone();
1736 append_attr_clone(node, albuf);
1737 if (astbuf2 != NULL)
1738 node->children.push_back(astbuf2->clone());
1740 if (node->is_input || node->is_output)
1741 frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
1742 if (!astbuf2 && !node->is_custom_type) {
1743 addRange(node, 0, 0, false);
1745 rewriteAsMemoryNode(node, $2);
1747 if (current_function_or_task == NULL) {
1748 if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
1749 port_stubs[*$1] = ++port_counter;
1751 if (port_stubs.count(*$1) != 0) {
1752 if (!node->is_input && !node->is_output)
1753 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
1754 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
1755 frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
1756 node->port_id = port_stubs[*$1];
1757 port_stubs.erase(*$1);
1759 if (node->is_input || node->is_output)
1760 frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
1763 if (node->is_input || node->is_output)
1764 node->port_id = current_function_or_task_port_id++;
1766 //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
1767 SET_AST_NODE_LOC(node, @1, @1);
1768 ast_stack.back()->children.push_back(node);
1774 TOK_ASSIGN delay assign_expr_list ';';
1777 assign_expr | assign_expr_list ',' assign_expr;
1781 AstNode *node = new AstNode(AST_ASSIGN, $1, $3);
1782 SET_AST_NODE_LOC(node, @$, @$);
1783 ast_stack.back()->children.push_back(node);
1786 type_name: TOK_ID // first time seen
1787 | TOK_USER_TYPE { if (isInLocalScope($1)) frontend_verilog_yyerror("Duplicate declaration of TYPEDEF '%s'", $1->c_str()+1); }
1791 TOK_TYPEDEF wire_type range type_name range_or_multirange ';' {
1793 astbuf2 = checkRange(astbuf1, $3);
1795 astbuf1->children.push_back(astbuf2);
1799 addRange(astbuf1, 0, 0, false);
1801 rewriteAsMemoryNode(astbuf1, $5);
1803 addTypedefNode($4, astbuf1); }
1804 | TOK_TYPEDEF non_wire_data_type type_name ';' { addTypedefNode($3, $2); }
1814 astbuf1 = new AstNode(AST_CELL);
1815 append_attr(astbuf1, $1);
1816 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
1817 astbuf1->children[0]->str = *$2;
1819 } cell_parameter_list_opt cell_list ';' {
1822 attr tok_prim_wrapper delay {
1823 astbuf1 = new AstNode(AST_PRIMITIVE);
1825 append_attr(astbuf1, $1);
1836 $$ = new std::string("or");
1841 cell_list ',' single_cell;
1845 astbuf2 = astbuf1->clone();
1846 if (astbuf2->type != AST_PRIMITIVE)
1849 ast_stack.back()->children.push_back(astbuf2);
1850 } '(' cell_port_list ')' {
1851 SET_AST_NODE_LOC(astbuf2, @1, @$);
1853 TOK_ID non_opt_range {
1854 astbuf2 = astbuf1->clone();
1855 if (astbuf2->type != AST_PRIMITIVE)
1858 ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
1859 } '(' cell_port_list ')'{
1860 SET_AST_NODE_LOC(astbuf2, @1, @$);
1865 prim_list ',' single_prim;
1870 astbuf2 = astbuf1->clone();
1871 ast_stack.back()->children.push_back(astbuf2);
1872 } '(' cell_port_list ')' {
1873 SET_AST_NODE_LOC(astbuf2, @1, @$);
1876 cell_parameter_list_opt:
1877 '#' '(' cell_parameter_list ')' | /* empty */;
1879 cell_parameter_list:
1880 cell_parameter | cell_parameter_list ',' cell_parameter;
1885 AstNode *node = new AstNode(AST_PARASET);
1886 astbuf1->children.push_back(node);
1887 node->children.push_back($1);
1889 '.' TOK_ID '(' expr ')' {
1890 AstNode *node = new AstNode(AST_PARASET);
1892 astbuf1->children.push_back(node);
1893 node->children.push_back($4);
1898 cell_port_list_rules {
1899 // remove empty args from end of list
1900 while (!astbuf2->children.empty()) {
1901 AstNode *node = astbuf2->children.back();
1902 if (node->type != AST_ARGUMENT) break;
1903 if (!node->children.empty()) break;
1904 if (!node->str.empty()) break;
1905 astbuf2->children.pop_back();
1910 bool has_positional_args = false;
1911 bool has_named_args = false;
1912 for (auto node : astbuf2->children) {
1913 if (node->type != AST_ARGUMENT) continue;
1914 if (node->str.empty())
1915 has_positional_args = true;
1917 has_named_args = true;
1920 if (has_positional_args && has_named_args)
1921 frontend_verilog_yyerror("Mix of positional and named cell ports.");
1924 cell_port_list_rules:
1925 cell_port | cell_port_list_rules ',' cell_port;
1929 AstNode *node = new AstNode(AST_ARGUMENT);
1930 astbuf2->children.push_back(node);
1934 AstNode *node = new AstNode(AST_ARGUMENT);
1935 astbuf2->children.push_back(node);
1936 node->children.push_back($2);
1939 attr '.' TOK_ID '(' expr ')' {
1940 AstNode *node = new AstNode(AST_ARGUMENT);
1942 astbuf2->children.push_back(node);
1943 node->children.push_back($5);
1947 attr '.' TOK_ID '(' ')' {
1948 AstNode *node = new AstNode(AST_ARGUMENT);
1950 astbuf2->children.push_back(node);
1955 AstNode *node = new AstNode(AST_ARGUMENT);
1957 astbuf2->children.push_back(node);
1958 node->children.push_back(new AstNode(AST_IDENTIFIER));
1959 node->children.back()->str = *$3;
1963 attr TOK_WILDCARD_CONNECT {
1965 frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
1966 astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
1969 always_comb_or_latch:
1977 always_or_always_ff:
1986 attr always_or_always_ff {
1987 AstNode *node = new AstNode(AST_ALWAYS);
1988 append_attr(node, $1);
1990 node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
1991 ast_stack.back()->children.push_back(node);
1992 ast_stack.push_back(node);
1994 AstNode *block = new AstNode(AST_BLOCK);
1995 ast_stack.back()->children.push_back(block);
1996 ast_stack.push_back(block);
1998 SET_AST_NODE_LOC(ast_stack.back(), @6, @6);
1999 ast_stack.pop_back();
2001 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
2002 ast_stack.pop_back();
2004 SET_RULE_LOC(@$, @2, @$);
2006 attr always_comb_or_latch {
2007 AstNode *node = new AstNode(AST_ALWAYS);
2008 append_attr(node, $1);
2010 node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
2012 node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
2013 ast_stack.back()->children.push_back(node);
2014 ast_stack.push_back(node);
2015 AstNode *block = new AstNode(AST_BLOCK);
2016 ast_stack.back()->children.push_back(block);
2017 ast_stack.push_back(block);
2019 ast_stack.pop_back();
2020 ast_stack.pop_back();
2023 AstNode *node = new AstNode(AST_INITIAL);
2024 append_attr(node, $1);
2025 ast_stack.back()->children.push_back(node);
2026 ast_stack.push_back(node);
2027 AstNode *block = new AstNode(AST_BLOCK);
2028 ast_stack.back()->children.push_back(block);
2029 ast_stack.push_back(block);
2031 ast_stack.pop_back();
2032 ast_stack.pop_back();
2036 '@' '(' always_events ')' |
2038 '@' ATTR_BEGIN ')' |
2045 always_events TOK_OR always_event |
2046 always_events ',' always_event;
2050 AstNode *node = new AstNode(AST_POSEDGE);
2051 SET_AST_NODE_LOC(node, @1, @1);
2052 ast_stack.back()->children.push_back(node);
2053 node->children.push_back($2);
2056 AstNode *node = new AstNode(AST_NEGEDGE);
2057 SET_AST_NODE_LOC(node, @1, @1);
2058 ast_stack.back()->children.push_back(node);
2059 node->children.push_back($2);
2062 AstNode *node = new AstNode(AST_EDGE);
2063 ast_stack.back()->children.push_back(node);
2064 node->children.push_back($1);
2095 TOK_MODPORT TOK_ID {
2096 AstNode *modport = new AstNode(AST_MODPORT);
2097 ast_stack.back()->children.push_back(modport);
2098 ast_stack.push_back(modport);
2101 } modport_args_opt {
2102 ast_stack.pop_back();
2103 log_assert(ast_stack.size() == 2);
2107 '(' ')' | '(' modport_args optional_comma ')';
2110 modport_arg | modport_args ',' modport_arg;
2113 modport_type_token modport_member |
2118 AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
2119 ast_stack.back()->children.push_back(modport_member);
2120 modport_member->str = *$1;
2121 modport_member->is_input = current_modport_input;
2122 modport_member->is_output = current_modport_output;
2127 TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
2130 opt_sva_label TOK_ASSERT opt_property '(' expr ')' ';' {
2131 if (noassert_mode) {
2134 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2135 SET_AST_NODE_LOC(node, @1, @6);
2138 ast_stack.back()->children.push_back(node);
2143 opt_sva_label TOK_ASSUME opt_property '(' expr ')' ';' {
2144 if (noassume_mode) {
2147 AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
2148 SET_AST_NODE_LOC(node, @1, @6);
2151 ast_stack.back()->children.push_back(node);
2156 opt_sva_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2157 if (noassert_mode) {
2160 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2161 SET_AST_NODE_LOC(node, @1, @7);
2164 ast_stack.back()->children.push_back(node);
2169 opt_sva_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2170 if (noassume_mode) {
2173 AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
2174 SET_AST_NODE_LOC(node, @1, @7);
2177 ast_stack.back()->children.push_back(node);
2182 opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
2183 AstNode *node = new AstNode(AST_COVER, $5);
2184 SET_AST_NODE_LOC(node, @1, @6);
2185 if ($1 != nullptr) {
2189 ast_stack.back()->children.push_back(node);
2191 opt_sva_label TOK_COVER opt_property '(' ')' ';' {
2192 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2193 SET_AST_NODE_LOC(node, @1, @5);
2194 if ($1 != nullptr) {
2198 ast_stack.back()->children.push_back(node);
2200 opt_sva_label TOK_COVER ';' {
2201 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2202 SET_AST_NODE_LOC(node, @1, @2);
2203 if ($1 != nullptr) {
2207 ast_stack.back()->children.push_back(node);
2209 opt_sva_label TOK_RESTRICT opt_property '(' expr ')' ';' {
2210 if (norestrict_mode) {
2213 AstNode *node = new AstNode(AST_ASSUME, $5);
2214 SET_AST_NODE_LOC(node, @1, @6);
2217 ast_stack.back()->children.push_back(node);
2220 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2224 opt_sva_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2225 if (norestrict_mode) {
2228 AstNode *node = new AstNode(AST_FAIR, $6);
2229 SET_AST_NODE_LOC(node, @1, @7);
2232 ast_stack.back()->children.push_back(node);
2235 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2241 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
2242 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2243 SET_AST_NODE_LOC(node, @1, @6);
2244 ast_stack.back()->children.push_back(node);
2245 if ($1 != nullptr) {
2246 ast_stack.back()->children.back()->str = *$1;
2250 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
2251 AstNode *node = new AstNode(AST_ASSUME, $5);
2252 SET_AST_NODE_LOC(node, @1, @6);
2253 ast_stack.back()->children.push_back(node);
2254 if ($1 != nullptr) {
2255 ast_stack.back()->children.back()->str = *$1;
2259 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2260 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2261 SET_AST_NODE_LOC(node, @1, @7);
2262 ast_stack.back()->children.push_back(node);
2263 if ($1 != nullptr) {
2264 ast_stack.back()->children.back()->str = *$1;
2268 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2269 AstNode *node = new AstNode(AST_FAIR, $6);
2270 SET_AST_NODE_LOC(node, @1, @7);
2271 ast_stack.back()->children.push_back(node);
2272 if ($1 != nullptr) {
2273 ast_stack.back()->children.back()->str = *$1;
2277 opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
2278 AstNode *node = new AstNode(AST_COVER, $5);
2279 SET_AST_NODE_LOC(node, @1, @6);
2280 ast_stack.back()->children.push_back(node);
2281 if ($1 != nullptr) {
2282 ast_stack.back()->children.back()->str = *$1;
2286 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
2287 if (norestrict_mode) {
2290 AstNode *node = new AstNode(AST_ASSUME, $5);
2291 SET_AST_NODE_LOC(node, @1, @6);
2292 ast_stack.back()->children.push_back(node);
2293 if ($1 != nullptr) {
2294 ast_stack.back()->children.back()->str = *$1;
2299 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2300 if (norestrict_mode) {
2303 AstNode *node = new AstNode(AST_FAIR, $6);
2304 SET_AST_NODE_LOC(node, @1, @7);
2305 ast_stack.back()->children.push_back(node);
2306 if ($1 != nullptr) {
2307 ast_stack.back()->children.back()->str = *$1;
2313 simple_behavioral_stmt:
2314 attr lvalue '=' delay expr {
2315 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $5);
2316 ast_stack.back()->children.push_back(node);
2317 SET_AST_NODE_LOC(node, @2, @5);
2318 append_attr(node, $1);
2320 attr lvalue TOK_INCREMENT {
2321 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)));
2322 ast_stack.back()->children.push_back(node);
2323 SET_AST_NODE_LOC(node, @2, @3);
2324 append_attr(node, $1);
2326 attr lvalue TOK_DECREMENT {
2327 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_SUB, $2->clone(), AstNode::mkconst_int(1, true)));
2328 ast_stack.back()->children.push_back(node);
2329 SET_AST_NODE_LOC(node, @2, @3);
2330 append_attr(node, $1);
2332 attr lvalue OP_LE delay expr {
2333 AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5);
2334 ast_stack.back()->children.push_back(node);
2335 SET_AST_NODE_LOC(node, @2, @5);
2336 append_attr(node, $1);
2339 // this production creates the obligatory if-else shift/reduce conflict
2341 defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
2342 non_opt_delay behavioral_stmt |
2343 simple_behavioral_stmt ';' |
2347 attr hierarchical_id {
2348 AstNode *node = new AstNode(AST_TCALL);
2351 ast_stack.back()->children.push_back(node);
2352 ast_stack.push_back(node);
2353 append_attr(node, $1);
2355 ast_stack.pop_back();
2357 attr TOK_MSG_TASKS {
2358 AstNode *node = new AstNode(AST_TCALL);
2361 ast_stack.back()->children.push_back(node);
2362 ast_stack.push_back(node);
2363 append_attr(node, $1);
2365 ast_stack.pop_back();
2370 AstNode *node = new AstNode(AST_BLOCK);
2371 ast_stack.back()->children.push_back(node);
2372 ast_stack.push_back(node);
2373 append_attr(node, $1);
2376 } behavioral_stmt_list TOK_END opt_label {
2378 if ($4 != NULL && $8 != NULL && *$4 != *$8)
2379 frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
2380 SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
2383 ast_stack.pop_back();
2386 AstNode *node = new AstNode(AST_FOR);
2387 ast_stack.back()->children.push_back(node);
2388 ast_stack.push_back(node);
2389 append_attr(node, $1);
2390 } simple_behavioral_stmt ';' expr {
2391 ast_stack.back()->children.push_back($7);
2392 } ';' simple_behavioral_stmt ')' {
2393 AstNode *block = new AstNode(AST_BLOCK);
2394 ast_stack.back()->children.push_back(block);
2395 ast_stack.push_back(block);
2397 SET_AST_NODE_LOC(ast_stack.back(), @13, @13);
2398 ast_stack.pop_back();
2399 SET_AST_NODE_LOC(ast_stack.back(), @2, @13);
2400 ast_stack.pop_back();
2402 attr TOK_WHILE '(' expr ')' {
2403 AstNode *node = new AstNode(AST_WHILE);
2404 ast_stack.back()->children.push_back(node);
2405 ast_stack.push_back(node);
2406 append_attr(node, $1);
2407 AstNode *block = new AstNode(AST_BLOCK);
2408 ast_stack.back()->children.push_back($4);
2409 ast_stack.back()->children.push_back(block);
2410 ast_stack.push_back(block);
2412 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2413 ast_stack.pop_back();
2414 ast_stack.pop_back();
2416 attr TOK_REPEAT '(' expr ')' {
2417 AstNode *node = new AstNode(AST_REPEAT);
2418 ast_stack.back()->children.push_back(node);
2419 ast_stack.push_back(node);
2420 append_attr(node, $1);
2421 AstNode *block = new AstNode(AST_BLOCK);
2422 ast_stack.back()->children.push_back($4);
2423 ast_stack.back()->children.push_back(block);
2424 ast_stack.push_back(block);
2426 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2427 ast_stack.pop_back();
2428 ast_stack.pop_back();
2430 attr TOK_IF '(' expr ')' {
2431 AstNode *node = new AstNode(AST_CASE);
2432 AstNode *block = new AstNode(AST_BLOCK);
2433 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
2434 SET_AST_NODE_LOC(cond, @4, @4);
2435 ast_stack.back()->children.push_back(node);
2436 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
2437 node->children.push_back(cond);
2438 ast_stack.push_back(node);
2439 ast_stack.push_back(block);
2440 append_attr(node, $1);
2442 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2444 ast_stack.pop_back();
2445 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2446 ast_stack.pop_back();
2448 case_attr case_type '(' expr ')' {
2449 AstNode *node = new AstNode(AST_CASE, $4);
2450 ast_stack.back()->children.push_back(node);
2451 ast_stack.push_back(node);
2452 append_attr(node, $1);
2453 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2454 } opt_synopsys_attr case_body TOK_ENDCASE {
2455 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2456 case_type_stack.pop_back();
2457 ast_stack.pop_back();
2464 TOK_PRIORITY case_attr {
2467 TOK_UNIQUE case_attr {
2472 attr unique_case_attr {
2473 if ($2) (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false);
2479 case_type_stack.push_back(0);
2482 case_type_stack.push_back('x');
2485 case_type_stack.push_back('z');
2489 opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
2490 if (ast_stack.back()->attributes.count(ID::full_case) == 0)
2491 ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
2493 opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
2494 if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
2495 ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
2499 behavioral_stmt_list:
2500 behavioral_stmt_list behavioral_stmt |
2505 AstNode *block = new AstNode(AST_BLOCK);
2506 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
2507 SET_AST_NODE_LOC(cond, @1, @1);
2509 ast_stack.pop_back();
2510 ast_stack.back()->children.push_back(cond);
2511 ast_stack.push_back(block);
2513 SET_AST_NODE_LOC(ast_stack.back(), @3, @3);
2515 /* empty */ %prec FAKE_THEN;
2518 case_body case_item |
2523 AstNode *node = new AstNode(
2524 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2525 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2526 ast_stack.back()->children.push_back(node);
2527 ast_stack.push_back(node);
2529 AstNode *block = new AstNode(AST_BLOCK);
2530 ast_stack.back()->children.push_back(block);
2531 ast_stack.push_back(block);
2532 case_type_stack.push_back(0);
2534 case_type_stack.pop_back();
2535 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2536 ast_stack.pop_back();
2537 ast_stack.pop_back();
2541 gen_case_body gen_case_item |
2546 AstNode *node = new AstNode(
2547 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2548 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2549 ast_stack.back()->children.push_back(node);
2550 ast_stack.push_back(node);
2552 case_type_stack.push_back(0);
2553 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2555 case_type_stack.pop_back();
2556 ast_stack.pop_back();
2560 case_expr_list ':' |
2565 AstNode *node = new AstNode(AST_DEFAULT);
2566 SET_AST_NODE_LOC(node, @1, @1);
2567 ast_stack.back()->children.push_back(node);
2570 AstNode *node = new AstNode(AST_IDENTIFIER);
2571 SET_AST_NODE_LOC(node, @1, @1);
2572 ast_stack.back()->children.push_back(node);
2573 ast_stack.back()->children.back()->str = *$1;
2577 ast_stack.back()->children.push_back($1);
2579 case_expr_list ',' expr {
2580 ast_stack.back()->children.push_back($3);
2584 hierarchical_id '[' expr ']' '.' rvalue {
2585 $$ = new AstNode(AST_PREFIX, $3, $6);
2589 hierarchical_id range {
2590 $$ = new AstNode(AST_IDENTIFIER, $2);
2592 SET_AST_NODE_LOC($$, @1, @1);
2594 if ($2 == nullptr && ($$->str == "\\$initstate" ||
2595 $$->str == "\\$anyconst" || $$->str == "\\$anyseq" ||
2596 $$->str == "\\$allconst" || $$->str == "\\$allseq"))
2597 $$->type = AST_FCALL;
2599 hierarchical_id non_opt_multirange {
2600 $$ = new AstNode(AST_IDENTIFIER, $2);
2602 SET_AST_NODE_LOC($$, @1, @1);
2610 '{' lvalue_concat_list '}' {
2616 $$ = new AstNode(AST_CONCAT);
2617 $$->children.push_back($1);
2619 expr ',' lvalue_concat_list {
2621 $$->children.push_back($1);
2625 '(' arg_list optional_comma ')' |
2634 arg_list ',' single_arg;
2638 ast_stack.back()->children.push_back($1);
2642 module_gen_body gen_stmt_or_module_body_stmt |
2645 gen_stmt_or_module_body_stmt:
2646 gen_stmt | module_body_stmt |
2651 // this production creates the obligatory if-else shift/reduce conflict
2654 AstNode *node = new AstNode(AST_GENFOR);
2655 ast_stack.back()->children.push_back(node);
2656 ast_stack.push_back(node);
2657 } simple_behavioral_stmt ';' expr {
2658 ast_stack.back()->children.push_back($6);
2659 } ';' simple_behavioral_stmt ')' gen_stmt_block {
2660 SET_AST_NODE_LOC(ast_stack.back(), @1, @11);
2661 ast_stack.pop_back();
2663 TOK_IF '(' expr ')' {
2664 AstNode *node = new AstNode(AST_GENIF);
2665 ast_stack.back()->children.push_back(node);
2666 ast_stack.push_back(node);
2667 ast_stack.back()->children.push_back($3);
2668 AstNode *block = new AstNode(AST_GENBLOCK);
2669 ast_stack.back()->children.push_back(block);
2670 ast_stack.push_back(block);
2672 ast_stack.pop_back();
2674 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2675 ast_stack.pop_back();
2677 case_type '(' expr ')' {
2678 AstNode *node = new AstNode(AST_GENCASE, $3);
2679 ast_stack.back()->children.push_back(node);
2680 ast_stack.push_back(node);
2681 } gen_case_body TOK_ENDCASE {
2682 case_type_stack.pop_back();
2683 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2684 ast_stack.pop_back();
2689 AstNode *node = new AstNode(AST_GENBLOCK);
2690 node->str = $3 ? *$3 : std::string();
2691 ast_stack.back()->children.push_back(node);
2692 ast_stack.push_back(node);
2693 } module_gen_body TOK_END opt_label {
2697 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2698 ast_stack.pop_back();
2701 AstNode *node = new AstNode(AST_TECALL);
2704 ast_stack.back()->children.push_back(node);
2705 ast_stack.push_back(node);
2707 SET_AST_NODE_LOC(ast_stack.back(), @1, @3);
2708 ast_stack.pop_back();
2713 AstNode *node = new AstNode(AST_GENBLOCK);
2714 ast_stack.back()->children.push_back(node);
2715 ast_stack.push_back(node);
2716 } gen_stmt_or_module_body_stmt {
2717 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2718 ast_stack.pop_back();
2722 TOK_ELSE gen_stmt_block | /* empty */ %prec FAKE_THEN;
2728 basic_expr '?' attr expr ':' expr {
2729 $$ = new AstNode(AST_TERNARY);
2730 $$->children.push_back($1);
2731 $$->children.push_back($4);
2732 $$->children.push_back($6);
2733 SET_AST_NODE_LOC($$, @1, @$);
2734 append_attr($$, $3);
2741 '(' expr ')' integral_number {
2742 if ($4->compare(0, 1, "'") != 0)
2743 frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
2745 AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2747 log_error("Value conversion failed: `%s'\n", $4->c_str());
2748 $$ = new AstNode(AST_TO_BITS, bits, val);
2751 hierarchical_id integral_number {
2752 if ($2->compare(0, 1, "'") != 0)
2753 frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
2754 AstNode *bits = new AstNode(AST_IDENTIFIER);
2756 SET_AST_NODE_LOC(bits, @1, @1);
2757 AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2758 SET_AST_NODE_LOC(val, @2, @2);
2760 log_error("Value conversion failed: `%s'\n", $2->c_str());
2761 $$ = new AstNode(AST_TO_BITS, bits, val);
2766 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2767 SET_AST_NODE_LOC($$, @1, @1);
2769 log_error("Value conversion failed: `%s'\n", $1->c_str());
2773 $$ = new AstNode(AST_REALVALUE);
2774 char *p = (char*)malloc(GetSize(*$1) + 1), *q;
2775 for (int i = 0, j = 0; j < GetSize(*$1); j++)
2776 if ((*$1)[j] != '_')
2777 p[i++] = (*$1)[j], p[i] = 0;
2778 $$->realvalue = strtod(p, &q);
2779 SET_AST_NODE_LOC($$, @1, @1);
2780 log_assert(*q == 0);
2785 $$ = AstNode::mkconst_str(*$1);
2786 SET_AST_NODE_LOC($$, @1, @1);
2789 hierarchical_id attr {
2790 AstNode *node = new AstNode(AST_FCALL);
2793 ast_stack.push_back(node);
2794 SET_AST_NODE_LOC(node, @1, @1);
2795 append_attr(node, $2);
2796 } '(' arg_list optional_comma ')' {
2797 $$ = ast_stack.back();
2798 ast_stack.pop_back();
2800 TOK_TO_SIGNED attr '(' expr ')' {
2801 $$ = new AstNode(AST_TO_SIGNED, $4);
2802 append_attr($$, $2);
2804 TOK_TO_UNSIGNED attr '(' expr ')' {
2805 $$ = new AstNode(AST_TO_UNSIGNED, $4);
2806 append_attr($$, $2);
2811 '(' expr ':' expr ':' expr ')' {
2816 '{' concat_list '}' {
2819 '{' expr '{' concat_list '}' '}' {
2820 $$ = new AstNode(AST_REPLICATE, $2, $4);
2822 '~' attr basic_expr %prec UNARY_OPS {
2823 $$ = new AstNode(AST_BIT_NOT, $3);
2824 SET_AST_NODE_LOC($$, @1, @3);
2825 append_attr($$, $2);
2827 basic_expr '&' attr basic_expr {
2828 $$ = new AstNode(AST_BIT_AND, $1, $4);
2829 SET_AST_NODE_LOC($$, @1, @4);
2830 append_attr($$, $3);
2832 basic_expr OP_NAND attr basic_expr {
2833 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
2834 SET_AST_NODE_LOC($$, @1, @4);
2835 append_attr($$, $3);
2837 basic_expr '|' attr basic_expr {
2838 $$ = new AstNode(AST_BIT_OR, $1, $4);
2839 SET_AST_NODE_LOC($$, @1, @4);
2840 append_attr($$, $3);
2842 basic_expr OP_NOR attr basic_expr {
2843 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
2844 SET_AST_NODE_LOC($$, @1, @4);
2845 append_attr($$, $3);
2847 basic_expr '^' attr basic_expr {
2848 $$ = new AstNode(AST_BIT_XOR, $1, $4);
2849 SET_AST_NODE_LOC($$, @1, @4);
2850 append_attr($$, $3);
2852 basic_expr OP_XNOR attr basic_expr {
2853 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
2854 SET_AST_NODE_LOC($$, @1, @4);
2855 append_attr($$, $3);
2857 '&' attr basic_expr %prec UNARY_OPS {
2858 $$ = new AstNode(AST_REDUCE_AND, $3);
2859 SET_AST_NODE_LOC($$, @1, @3);
2860 append_attr($$, $2);
2862 OP_NAND attr basic_expr %prec UNARY_OPS {
2863 $$ = new AstNode(AST_REDUCE_AND, $3);
2864 SET_AST_NODE_LOC($$, @1, @3);
2865 append_attr($$, $2);
2866 $$ = new AstNode(AST_LOGIC_NOT, $$);
2868 '|' attr basic_expr %prec UNARY_OPS {
2869 $$ = new AstNode(AST_REDUCE_OR, $3);
2870 SET_AST_NODE_LOC($$, @1, @3);
2871 append_attr($$, $2);
2873 OP_NOR attr basic_expr %prec UNARY_OPS {
2874 $$ = new AstNode(AST_REDUCE_OR, $3);
2875 SET_AST_NODE_LOC($$, @1, @3);
2876 append_attr($$, $2);
2877 $$ = new AstNode(AST_LOGIC_NOT, $$);
2878 SET_AST_NODE_LOC($$, @1, @3);
2880 '^' attr basic_expr %prec UNARY_OPS {
2881 $$ = new AstNode(AST_REDUCE_XOR, $3);
2882 SET_AST_NODE_LOC($$, @1, @3);
2883 append_attr($$, $2);
2885 OP_XNOR attr basic_expr %prec UNARY_OPS {
2886 $$ = new AstNode(AST_REDUCE_XNOR, $3);
2887 SET_AST_NODE_LOC($$, @1, @3);
2888 append_attr($$, $2);
2890 basic_expr OP_SHL attr basic_expr {
2891 $$ = new AstNode(AST_SHIFT_LEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2892 SET_AST_NODE_LOC($$, @1, @4);
2893 append_attr($$, $3);
2895 basic_expr OP_SHR attr basic_expr {
2896 $$ = new AstNode(AST_SHIFT_RIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2897 SET_AST_NODE_LOC($$, @1, @4);
2898 append_attr($$, $3);
2900 basic_expr OP_SSHL attr basic_expr {
2901 $$ = new AstNode(AST_SHIFT_SLEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2902 SET_AST_NODE_LOC($$, @1, @4);
2903 append_attr($$, $3);
2905 basic_expr OP_SSHR attr basic_expr {
2906 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2907 SET_AST_NODE_LOC($$, @1, @4);
2908 append_attr($$, $3);
2910 basic_expr '<' attr basic_expr {
2911 $$ = new AstNode(AST_LT, $1, $4);
2912 SET_AST_NODE_LOC($$, @1, @4);
2913 append_attr($$, $3);
2915 basic_expr OP_LE attr basic_expr {
2916 $$ = new AstNode(AST_LE, $1, $4);
2917 SET_AST_NODE_LOC($$, @1, @4);
2918 append_attr($$, $3);
2920 basic_expr OP_EQ attr basic_expr {
2921 $$ = new AstNode(AST_EQ, $1, $4);
2922 SET_AST_NODE_LOC($$, @1, @4);
2923 append_attr($$, $3);
2925 basic_expr OP_NE attr basic_expr {
2926 $$ = new AstNode(AST_NE, $1, $4);
2927 SET_AST_NODE_LOC($$, @1, @4);
2928 append_attr($$, $3);
2930 basic_expr OP_EQX attr basic_expr {
2931 $$ = new AstNode(AST_EQX, $1, $4);
2932 SET_AST_NODE_LOC($$, @1, @4);
2933 append_attr($$, $3);
2935 basic_expr OP_NEX attr basic_expr {
2936 $$ = new AstNode(AST_NEX, $1, $4);
2937 SET_AST_NODE_LOC($$, @1, @4);
2938 append_attr($$, $3);
2940 basic_expr OP_GE attr basic_expr {
2941 $$ = new AstNode(AST_GE, $1, $4);
2942 SET_AST_NODE_LOC($$, @1, @4);
2943 append_attr($$, $3);
2945 basic_expr '>' attr basic_expr {
2946 $$ = new AstNode(AST_GT, $1, $4);
2947 SET_AST_NODE_LOC($$, @1, @4);
2948 append_attr($$, $3);
2950 basic_expr '+' attr basic_expr {
2951 $$ = new AstNode(AST_ADD, $1, $4);
2952 SET_AST_NODE_LOC($$, @1, @4);
2953 append_attr($$, $3);
2955 basic_expr '-' attr basic_expr {
2956 $$ = new AstNode(AST_SUB, $1, $4);
2957 SET_AST_NODE_LOC($$, @1, @4);
2958 append_attr($$, $3);
2960 basic_expr '*' attr basic_expr {
2961 $$ = new AstNode(AST_MUL, $1, $4);
2962 SET_AST_NODE_LOC($$, @1, @4);
2963 append_attr($$, $3);
2965 basic_expr '/' attr basic_expr {
2966 $$ = new AstNode(AST_DIV, $1, $4);
2967 SET_AST_NODE_LOC($$, @1, @4);
2968 append_attr($$, $3);
2970 basic_expr '%' attr basic_expr {
2971 $$ = new AstNode(AST_MOD, $1, $4);
2972 SET_AST_NODE_LOC($$, @1, @4);
2973 append_attr($$, $3);
2975 basic_expr OP_POW attr basic_expr {
2976 $$ = new AstNode(AST_POW, $1, $4);
2977 SET_AST_NODE_LOC($$, @1, @4);
2978 append_attr($$, $3);
2980 '+' attr basic_expr %prec UNARY_OPS {
2981 $$ = new AstNode(AST_POS, $3);
2982 SET_AST_NODE_LOC($$, @1, @3);
2983 append_attr($$, $2);
2985 '-' attr basic_expr %prec UNARY_OPS {
2986 $$ = new AstNode(AST_NEG, $3);
2987 SET_AST_NODE_LOC($$, @1, @3);
2988 append_attr($$, $2);
2990 basic_expr OP_LAND attr basic_expr {
2991 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
2992 SET_AST_NODE_LOC($$, @1, @4);
2993 append_attr($$, $3);
2995 basic_expr OP_LOR attr basic_expr {
2996 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
2997 SET_AST_NODE_LOC($$, @1, @4);
2998 append_attr($$, $3);
3000 '!' attr basic_expr %prec UNARY_OPS {
3001 $$ = new AstNode(AST_LOGIC_NOT, $3);
3002 SET_AST_NODE_LOC($$, @1, @3);
3003 append_attr($$, $2);
3008 $$ = new AstNode(AST_CONCAT, $1);
3010 expr ',' concat_list {
3012 $$->children.push_back($1);
3016 TOK_CONSTVAL { $$ = $1; } |
3017 TOK_UNBASED_UNSIZED_CONSTVAL { $$ = $1; } |
3018 TOK_BASE TOK_BASED_CONSTVAL {
3023 TOK_CONSTVAL TOK_BASE TOK_BASED_CONSTVAL {
3024 $1->append(*$2).append(*$3);