2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The Verilog frontend.
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
29 * This is the actual bison parser for Verilog code. The AST ist created directly
30 * from the bison reduce functions here. Note that this code uses a few global
31 * variables to hold the state of the AST generator and therefore this parser is
40 #include "frontends/verilog/verilog_frontend.h"
41 #include "frontends/verilog/verilog_parser.tab.hh"
42 #include "kernel/log.h"
44 #define YYLEX_PARAM &yylval, &yylloc
48 using namespace VERILOG_FRONTEND;
51 namespace VERILOG_FRONTEND {
53 dict<std::string, int> port_stubs;
54 dict<IdString, AstNode*> *attr_list, default_attr_list;
55 std::stack<dict<IdString, AstNode*> *> attr_list_stack;
56 dict<IdString, AstNode*> *albuf;
57 std::vector<UserTypeMap*> user_type_stack;
58 dict<std::string, AstNode*> pkg_user_types;
59 std::vector<AstNode*> ast_stack;
60 struct AstNode *astbuf1, *astbuf2, *astbuf3;
61 struct AstNode *current_function_or_task;
62 struct AstNode *current_ast, *current_ast_mod;
63 int current_function_or_task_port_id;
64 std::vector<char> case_type_stack;
65 bool do_not_require_port_stubs;
66 bool default_nettype_wire;
67 bool sv_mode, formal_mode, lib_mode, specify_mode;
68 bool noassert_mode, noassume_mode, norestrict_mode;
69 bool assume_asserts_mode, assert_assumes_mode;
70 bool current_wire_rand, current_wire_const;
71 bool current_modport_input, current_modport_output;
76 #define SET_AST_NODE_LOC(WHICH, BEGIN, END) \
77 do { (WHICH)->location.first_line = (BEGIN).first_line; \
78 (WHICH)->location.first_column = (BEGIN).first_column; \
79 (WHICH)->location.last_line = (END).last_line; \
80 (WHICH)->location.last_column = (END).last_column; } while(0)
82 #define SET_RULE_LOC(LHS, BEGIN, END) \
83 do { (LHS).first_line = (BEGIN).first_line; \
84 (LHS).first_column = (BEGIN).first_column; \
85 (LHS).last_line = (END).last_line; \
86 (LHS).last_column = (END).last_column; } while(0)
88 int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
90 static void append_attr(AstNode *ast, dict<IdString, AstNode*> *al)
92 for (auto &it : *al) {
93 if (ast->attributes.count(it.first) > 0)
94 delete ast->attributes[it.first];
95 ast->attributes[it.first] = it.second;
100 static void append_attr_clone(AstNode *ast, dict<IdString, AstNode*> *al)
102 for (auto &it : *al) {
103 if (ast->attributes.count(it.first) > 0)
104 delete ast->attributes[it.first];
105 ast->attributes[it.first] = it.second->clone();
109 static void free_attr(dict<IdString, AstNode*> *al)
116 struct specify_target {
121 struct specify_triple {
122 AstNode *t_min, *t_avg, *t_max;
125 struct specify_rise_fall {
130 static void addTypedefNode(std::string *name, AstNode *node)
133 auto *tnode = new AstNode(AST_TYPEDEF, node);
135 auto user_types = user_type_stack.back();
136 (*user_types)[*name] = tnode;
137 if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {
138 // typedef inside a package so we need the qualified name
139 auto qname = current_ast_mod->str + "::" + (*name).substr(1);
140 pkg_user_types[qname] = tnode;
143 ast_stack.back()->children.push_back(tnode);
146 static void enterTypeScope()
148 auto user_types = new UserTypeMap();
149 user_type_stack.push_back(user_types);
152 static void exitTypeScope()
154 user_type_stack.pop_back();
157 static bool isInLocalScope(const std::string *name)
159 // tests if a name was declared in the current block scope
160 auto user_types = user_type_stack.back();
161 return (user_types->count(*name) > 0);
164 static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
166 auto range = new AstNode(AST_RANGE);
167 range->children.push_back(AstNode::mkconst_int(msb, true));
168 range->children.push_back(AstNode::mkconst_int(lsb, true));
169 range->is_signed = isSigned;
173 static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned = true)
175 auto range = makeRange(msb, lsb, isSigned);
176 parent->children.push_back(range);
180 %define api.prefix {frontend_verilog_yy}
183 /* The union is defined in the header, so we need to provide all the
184 * includes it requires
189 #include "frontends/verilog/verilog_frontend.h"
194 struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
195 YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
196 struct specify_target *specify_target_ptr;
197 struct specify_triple *specify_triple_ptr;
198 struct specify_rise_fall *specify_rise_fall_ptr;
203 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
204 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
205 %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL
206 %token <string> TOK_USER_TYPE TOK_PKG_USER_TYPE
207 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
208 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
209 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
210 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
211 %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
212 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
213 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
214 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
215 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
216 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
217 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
218 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
219 %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
220 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
221 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
222 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
223 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
224 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
225 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
227 %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
228 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
229 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
230 %type <string> type_name
231 %type <ast> opt_enum_init
232 %type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
233 %type <al> attr case_attr
235 %type <specify_target_ptr> specify_target
236 %type <specify_triple_ptr> specify_triple specify_opt_triple
237 %type <specify_rise_fall_ptr> specify_rise_fall
238 %type <ast> specify_if specify_condition
239 %type <ch> specify_edge
241 // operator precedence from low to high
247 %left OP_EQ OP_NE OP_EQX OP_NEX
248 %left '<' OP_LE OP_GE '>'
249 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
255 %define parse.error verbose
256 %define parse.lac full
268 ast_stack.push_back(current_ast);
270 ast_stack.pop_back();
271 log_assert(GetSize(ast_stack) == 0);
272 for (auto &it : default_attr_list)
274 default_attr_list.clear();
280 task_func_decl design |
282 localparam_decl design |
283 typedef_decl design |
290 if (attr_list != nullptr)
291 attr_list_stack.push(attr_list);
292 attr_list = new dict<IdString, AstNode*>;
293 for (auto &it : default_attr_list)
294 (*attr_list)[it.first] = it.second->clone();
297 if (!attr_list_stack.empty()) {
298 attr_list = attr_list_stack.top();
299 attr_list_stack.pop();
305 attr_opt ATTR_BEGIN opt_attr_list ATTR_END {
306 SET_RULE_LOC(@$, @2, @$);
312 if (attr_list != nullptr)
313 attr_list_stack.push(attr_list);
314 attr_list = new dict<IdString, AstNode*>;
315 for (auto &it : default_attr_list)
317 default_attr_list.clear();
319 attr_list->swap(default_attr_list);
321 if (!attr_list_stack.empty()) {
322 attr_list = attr_list_stack.top();
323 attr_list_stack.pop();
329 attr_list | /* empty */;
333 attr_list ',' attr_assign;
337 if (attr_list->count(*$1) != 0)
338 delete (*attr_list)[*$1];
339 (*attr_list)[*$1] = AstNode::mkconst_int(1, false);
342 hierarchical_id '=' expr {
343 if (attr_list->count(*$1) != 0)
344 delete (*attr_list)[*$1];
345 (*attr_list)[*$1] = $3;
353 hierarchical_id TOK_PACKAGESEP TOK_ID {
354 if ($3->compare(0, 1, "\\") == 0)
355 *$1 += "::" + $3->substr(1);
361 hierarchical_id '.' TOK_ID {
362 if ($3->compare(0, 1, "\\") == 0)
363 *$1 += "." + $3->substr(1);
370 hierarchical_type_id:
372 | TOK_PKG_USER_TYPE // package qualified type name
373 | '(' TOK_USER_TYPE ')' { $$ = $2; } // non-standard grammar
380 do_not_require_port_stubs = false;
381 AstNode *mod = new AstNode(AST_MODULE);
382 ast_stack.back()->children.push_back(mod);
383 ast_stack.push_back(mod);
384 current_ast_mod = mod;
388 append_attr(mod, $1);
390 } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
391 if (port_stubs.size() != 0)
392 frontend_verilog_yyerror("Missing details for module port `%s'.",
393 port_stubs.begin()->first.c_str());
394 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
395 ast_stack.pop_back();
396 log_assert(ast_stack.size() == 1);
397 current_ast_mod = NULL;
402 '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
405 single_module_para | module_para_list ',' single_module_para;
410 if (astbuf1) delete astbuf1;
411 astbuf1 = new AstNode(AST_PARAMETER);
412 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
413 append_attr(astbuf1, $1);
414 } param_type single_param_decl |
415 attr TOK_LOCALPARAM {
416 if (astbuf1) delete astbuf1;
417 astbuf1 = new AstNode(AST_LOCALPARAM);
418 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
419 append_attr(astbuf1, $1);
420 } param_type single_param_decl |
424 '(' ')' | /* empty */ | '(' module_args optional_comma ')';
427 module_arg | module_args ',' module_arg;
432 module_arg_opt_assignment:
434 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
435 AstNode *wire = new AstNode(AST_IDENTIFIER);
436 wire->str = ast_stack.back()->children.back()->str;
437 if (ast_stack.back()->children.back()->is_input) {
438 AstNode *n = ast_stack.back()->children.back();
439 if (n->attributes.count(ID::defaultvalue))
440 delete n->attributes.at(ID::defaultvalue);
441 n->attributes[ID::defaultvalue] = $2;
443 if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
444 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
446 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
448 frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
454 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
455 AstNode *node = ast_stack.back()->children.back()->clone();
457 node->port_id = ++port_counter;
458 ast_stack.back()->children.push_back(node);
459 SET_AST_NODE_LOC(node, @1, @1);
461 if (port_stubs.count(*$1) != 0)
462 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
463 port_stubs[*$1] = ++port_counter;
466 } module_arg_opt_assignment |
468 astbuf1 = new AstNode(AST_INTERFACEPORT);
469 astbuf1->children.push_back(new AstNode(AST_INTERFACEPORTTYPE));
470 astbuf1->children[0]->str = *$1;
472 } TOK_ID { /* SV interfaces */
474 frontend_verilog_yyerror("Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
475 astbuf2 = astbuf1->clone(); // really only needed if multiple instances of same type.
478 astbuf2->port_id = ++port_counter;
479 ast_stack.back()->children.push_back(astbuf2);
480 delete astbuf1; // really only needed if multiple instances of same type.
481 } module_arg_opt_assignment |
482 attr wire_type range TOK_ID {
485 SET_AST_NODE_LOC(node, @4, @4);
486 node->port_id = ++port_counter;
488 node->children.push_back($3);
489 if (!node->is_input && !node->is_output)
490 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
491 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
492 frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
493 ast_stack.back()->children.push_back(node);
494 append_attr(node, $1);
496 } module_arg_opt_assignment |
498 do_not_require_port_stubs = true;
505 AstNode *mod = new AstNode(AST_PACKAGE);
506 ast_stack.back()->children.push_back(mod);
507 ast_stack.push_back(mod);
508 current_ast_mod = mod;
510 append_attr(mod, $1);
511 } ';' package_body TOK_ENDPACKAGE {
512 ast_stack.pop_back();
513 current_ast_mod = NULL;
518 package_body package_body_stmt
531 do_not_require_port_stubs = false;
532 AstNode *intf = new AstNode(AST_INTERFACE);
533 ast_stack.back()->children.push_back(intf);
534 ast_stack.push_back(intf);
535 current_ast_mod = intf;
540 } module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
541 if (port_stubs.size() != 0)
542 frontend_verilog_yyerror("Missing details for module port `%s'.",
543 port_stubs.begin()->first.c_str());
544 ast_stack.pop_back();
545 log_assert(ast_stack.size() == 1);
546 current_ast_mod = NULL;
551 interface_body interface_body_stmt |;
554 param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
558 '#' TOK_ID { delete $2; } |
559 '#' TOK_CONSTVAL { delete $2; } |
560 '#' TOK_REALVAL { delete $2; } |
561 '#' '(' expr ')' { delete $3; } |
562 '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
565 non_opt_delay | /* empty */;
569 astbuf3 = new AstNode(AST_WIRE);
570 current_wire_rand = false;
571 current_wire_const = false;
572 } wire_type_token_list {
574 SET_RULE_LOC(@$, @2, @$);
577 wire_type_token_list:
579 wire_type_token_list wire_type_token |
581 hierarchical_type_id {
582 astbuf3->is_custom_type = true;
583 astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
584 astbuf3->children.back()->str = *$1;
589 astbuf3->is_input = true;
592 astbuf3->is_output = true;
595 astbuf3->is_input = true;
596 astbuf3->is_output = true;
603 astbuf3->is_wor = true;
606 astbuf3->is_wand = true;
609 astbuf3->is_reg = true;
612 astbuf3->is_logic = true;
615 astbuf3->is_logic = true;
618 astbuf3->is_reg = true;
619 astbuf3->range_left = 31;
620 astbuf3->range_right = 0;
621 astbuf3->is_signed = true;
624 astbuf3->type = AST_GENVAR;
625 astbuf3->is_reg = true;
626 astbuf3->is_signed = true;
627 astbuf3->range_left = 31;
628 astbuf3->range_right = 0;
631 astbuf3->is_signed = true;
634 current_wire_rand = true;
637 current_wire_const = true;
641 '[' expr ':' expr ']' {
642 $$ = new AstNode(AST_RANGE);
643 $$->children.push_back($2);
644 $$->children.push_back($4);
646 '[' expr TOK_POS_INDEXED expr ']' {
647 $$ = new AstNode(AST_RANGE);
648 AstNode *expr = new AstNode(AST_SELFSZ, $2);
649 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
650 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
652 '[' expr TOK_NEG_INDEXED expr ']' {
653 $$ = new AstNode(AST_RANGE);
654 AstNode *expr = new AstNode(AST_SELFSZ, $2);
655 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
656 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
659 $$ = new AstNode(AST_RANGE);
660 $$->children.push_back($2);
664 non_opt_range non_opt_range {
665 $$ = new AstNode(AST_MULTIRANGE, $1, $2);
667 non_opt_multirange non_opt_range {
669 $$->children.push_back($2);
682 non_opt_multirange { $$ = $1; };
689 $$ = new AstNode(AST_RANGE);
690 $$->children.push_back(AstNode::mkconst_int(31, true));
691 $$->children.push_back(AstNode::mkconst_int(0, true));
692 $$->is_signed = true;
696 module_body module_body_stmt |
697 /* the following line makes the generate..endgenrate keywords optional */
698 module_body gen_stmt |
702 task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
704 always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
707 TOK_CHECKER TOK_ID ';' {
708 AstNode *node = new AstNode(AST_GENBLOCK);
710 ast_stack.back()->children.push_back(node);
711 ast_stack.push_back(node);
712 } module_body TOK_ENDCHECKER {
714 ast_stack.pop_back();
718 attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
719 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
720 current_function_or_task->str = *$4;
721 append_attr(current_function_or_task, $1);
722 ast_stack.back()->children.push_back(current_function_or_task);
725 } opt_dpi_function_args ';' {
726 current_function_or_task = NULL;
728 attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
729 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
730 current_function_or_task->str = *$6;
731 append_attr(current_function_or_task, $1);
732 ast_stack.back()->children.push_back(current_function_or_task);
736 } opt_dpi_function_args ';' {
737 current_function_or_task = NULL;
739 attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
740 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
741 current_function_or_task->str = *$8;
742 append_attr(current_function_or_task, $1);
743 ast_stack.back()->children.push_back(current_function_or_task);
748 } opt_dpi_function_args ';' {
749 current_function_or_task = NULL;
751 attr TOK_TASK opt_automatic TOK_ID {
752 current_function_or_task = new AstNode(AST_TASK);
753 current_function_or_task->str = *$4;
754 append_attr(current_function_or_task, $1);
755 ast_stack.back()->children.push_back(current_function_or_task);
756 ast_stack.push_back(current_function_or_task);
757 current_function_or_task_port_id = 1;
759 } task_func_args_opt ';' task_func_body TOK_ENDTASK {
760 current_function_or_task = NULL;
761 ast_stack.pop_back();
763 attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID {
764 current_function_or_task = new AstNode(AST_FUNCTION);
765 current_function_or_task->str = *$6;
766 append_attr(current_function_or_task, $1);
767 ast_stack.back()->children.push_back(current_function_or_task);
768 ast_stack.push_back(current_function_or_task);
769 AstNode *outreg = new AstNode(AST_WIRE);
771 outreg->is_signed = $4;
772 outreg->is_reg = true;
774 outreg->children.push_back($5);
775 outreg->is_signed = $4 || $5->is_signed;
776 $5->is_signed = false;
778 current_function_or_task->children.push_back(outreg);
779 current_function_or_task_port_id = 1;
781 } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
782 current_function_or_task = NULL;
783 ast_stack.pop_back();
788 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
793 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
797 opt_dpi_function_args:
798 '(' dpi_function_args ')' |
802 dpi_function_args ',' dpi_function_arg |
803 dpi_function_args ',' |
820 '(' ')' | /* empty */ | '(' {
824 } task_func_args optional_comma {
832 task_func_port | task_func_args ',' task_func_port;
835 attr wire_type range {
845 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
847 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions (task/function arguments)");
849 astbuf2 = new AstNode(AST_RANGE);
850 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
851 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
854 if (astbuf2 && astbuf2->children.size() != 2)
855 frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
860 frontend_verilog_yyerror("task/function argument direction missing");
861 albuf = new dict<IdString, AstNode*>;
862 astbuf1 = new AstNode(AST_WIRE);
863 current_wire_rand = false;
864 current_wire_const = false;
865 astbuf1->is_input = true;
871 task_func_body behavioral_stmt |
874 /*************************** specify parser ***************************/
877 TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
880 specify_item specify_item_list |
884 specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
885 AstNode *en_expr = $1;
886 char specify_edge = $3;
887 AstNode *src_expr = $4;
889 specify_target *target = $6;
890 specify_rise_fall *timing = $9;
892 if (specify_edge != 0 && target->dat == nullptr)
893 frontend_verilog_yyerror("Found specify edge but no data spec.\n");
895 AstNode *cell = new AstNode(AST_CELL);
896 ast_stack.back()->children.push_back(cell);
897 cell->str = stringf("$specify$%d", autoidx++);
898 cell->children.push_back(new AstNode(AST_CELLTYPE));
899 cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
900 SET_AST_NODE_LOC(cell, en_expr ? @1 : @2, @10);
902 char oper_polarity = 0;
903 char oper_type = oper->at(0);
905 if (oper->size() == 3) {
906 oper_polarity = oper->at(0);
907 oper_type = oper->at(1);
910 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
911 cell->children.back()->str = "\\FULL";
913 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
914 cell->children.back()->str = "\\SRC_DST_PEN";
916 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
917 cell->children.back()->str = "\\SRC_DST_POL";
919 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
920 cell->children.back()->str = "\\T_RISE_MIN";
922 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
923 cell->children.back()->str = "\\T_RISE_TYP";
925 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
926 cell->children.back()->str = "\\T_RISE_MAX";
928 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
929 cell->children.back()->str = "\\T_FALL_MIN";
931 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
932 cell->children.back()->str = "\\T_FALL_TYP";
934 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
935 cell->children.back()->str = "\\T_FALL_MAX";
937 cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
938 cell->children.back()->str = "\\EN";
940 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
941 cell->children.back()->str = "\\SRC";
943 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
944 cell->children.back()->str = "\\DST";
948 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
949 cell->children.back()->str = "\\EDGE_EN";
951 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
952 cell->children.back()->str = "\\EDGE_POL";
954 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
955 cell->children.back()->str = "\\DAT_DST_PEN";
957 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
958 cell->children.back()->str = "\\DAT_DST_POL";
960 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
961 cell->children.back()->str = "\\DAT";
968 TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' specify_triple specify_opt_triple ')' ';' {
969 if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
970 *$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
971 frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
973 AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
974 AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
975 AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
977 AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
978 AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
979 AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
981 specify_triple *limit = $11;
982 specify_triple *limit2 = $12;
984 AstNode *cell = new AstNode(AST_CELL);
985 ast_stack.back()->children.push_back(cell);
986 cell->str = stringf("$specify$%d", autoidx++);
987 cell->children.push_back(new AstNode(AST_CELLTYPE));
988 cell->children.back()->str = "$specrule";
989 SET_AST_NODE_LOC(cell, @1, @14);
991 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
992 cell->children.back()->str = "\\TYPE";
994 cell->children.push_back(new AstNode(AST_PARASET, limit->t_min));
995 cell->children.back()->str = "\\T_LIMIT_MIN";
997 cell->children.push_back(new AstNode(AST_PARASET, limit->t_avg));
998 cell->children.back()->str = "\\T_LIMIT_TYP";
1000 cell->children.push_back(new AstNode(AST_PARASET, limit->t_max));
1001 cell->children.back()->str = "\\T_LIMIT_MAX";
1003 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_min : AstNode::mkconst_int(0, true)));
1004 cell->children.back()->str = "\\T_LIMIT2_MIN";
1006 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_avg : AstNode::mkconst_int(0, true)));
1007 cell->children.back()->str = "\\T_LIMIT2_TYP";
1009 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_max : AstNode::mkconst_int(0, true)));
1010 cell->children.back()->str = "\\T_LIMIT2_MAX";
1012 cell->children.push_back(new AstNode(AST_PARASET, src_pen));
1013 cell->children.back()->str = "\\SRC_PEN";
1015 cell->children.push_back(new AstNode(AST_PARASET, src_pol));
1016 cell->children.back()->str = "\\SRC_POL";
1018 cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
1019 cell->children.back()->str = "\\DST_PEN";
1021 cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
1022 cell->children.back()->str = "\\DST_POL";
1024 cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
1025 cell->children.back()->str = "\\SRC_EN";
1027 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
1028 cell->children.back()->str = "\\SRC";
1030 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
1031 cell->children.back()->str = "\\DST_EN";
1033 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
1034 cell->children.back()->str = "\\DST";
1040 ',' specify_triple {
1048 TOK_IF '(' expr ')' {
1056 TOK_SPECIFY_AND expr {
1065 $$ = new specify_target;
1066 $$->polarity_op = 0;
1070 '(' expr ':' expr ')'{
1071 $$ = new specify_target;
1072 $$->polarity_op = 0;
1076 '(' expr TOK_NEG_INDEXED expr ')'{
1077 $$ = new specify_target;
1078 $$->polarity_op = '-';
1082 '(' expr TOK_POS_INDEXED expr ')'{
1083 $$ = new specify_target;
1084 $$->polarity_op = '+';
1090 TOK_POSEDGE { $$ = 'p'; } |
1091 TOK_NEGEDGE { $$ = 'n'; } |
1096 $$ = new specify_rise_fall;
1098 $$->fall.t_min = $1->t_min->clone();
1099 $$->fall.t_avg = $1->t_avg->clone();
1100 $$->fall.t_max = $1->t_max->clone();
1103 '(' specify_triple ',' specify_triple ')' {
1104 $$ = new specify_rise_fall;
1110 '(' specify_triple ',' specify_triple ',' specify_triple ')' {
1111 $$ = new specify_rise_fall;
1117 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1119 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1120 $$ = new specify_rise_fall;
1129 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1131 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1132 $$ = new specify_rise_fall;
1147 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1152 $$ = new specify_triple;
1154 $$->t_avg = $1->clone();
1155 $$->t_max = $1->clone();
1157 expr ':' expr ':' expr {
1158 $$ = new specify_triple;
1164 /******************** ignored specify parser **************************/
1166 ignored_specify_block:
1167 TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
1168 TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
1170 ignored_specify_item_opt:
1171 ignored_specify_item_opt ignored_specify_item |
1172 ignored_specify_item ;
1174 ignored_specify_item:
1175 specparam_declaration
1176 // | pulsestyle_declaration
1177 // | showcancelled_declaration
1179 | system_timing_declaration
1182 specparam_declaration:
1183 TOK_SPECPARAM list_of_specparam_assignments ';' |
1184 TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ;
1186 // IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match
1187 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
1188 // exxxxtending this for SV specparam would change this anyhow
1190 '[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
1192 list_of_specparam_assignments:
1193 specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
1195 specparam_assignment:
1196 ignspec_id '=' ignspec_expr ;
1199 TOK_IF '(' ignspec_expr ')' | /* empty */;
1202 simple_path_declaration ';'
1203 // | edge_sensitive_path_declaration
1204 // | state_dependent_path_declaration
1207 simple_path_declaration :
1208 ignspec_opt_cond parallel_path_description '=' path_delay_value |
1209 ignspec_opt_cond full_path_description '=' path_delay_value
1213 '(' ignspec_expr list_of_path_delay_extra_expressions ')'
1215 | ignspec_expr list_of_path_delay_extra_expressions
1218 list_of_path_delay_extra_expressions :
1220 | ',' ignspec_expr list_of_path_delay_extra_expressions
1223 specify_edge_identifier :
1224 TOK_POSEDGE | TOK_NEGEDGE ;
1226 parallel_path_description :
1227 '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
1228 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
1229 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
1231 full_path_description :
1232 '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
1233 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
1234 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
1236 // This was broken into 2 rules to solve shift/reduce conflicts
1237 list_of_path_inputs :
1238 specify_input_terminal_descriptor opt_polarity_operator |
1239 specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
1242 ',' specify_input_terminal_descriptor |
1243 more_path_inputs ',' specify_input_terminal_descriptor ;
1245 list_of_path_outputs :
1246 specify_output_terminal_descriptor |
1247 list_of_path_outputs ',' specify_output_terminal_descriptor ;
1249 opt_polarity_operator :
1254 // Good enough for the time being
1255 specify_input_terminal_descriptor :
1258 // Good enough for the time being
1259 specify_output_terminal_descriptor :
1262 system_timing_declaration :
1263 ignspec_id '(' system_timing_args ')' ';' ;
1266 TOK_POSEDGE ignspec_id |
1267 TOK_NEGEDGE ignspec_id |
1270 system_timing_args :
1272 system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
1273 system_timing_args ',' system_timing_arg ;
1275 // for the time being this is OK, but we may write our own expr here.
1276 // as I'm not sure it is legal to use a full expr here (probably not)
1277 // On the other hand, other rules requiring constant expressions also use 'expr'
1278 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
1279 ignspec_constant_expression:
1280 expr { delete $1; };
1283 expr { delete $1; } |
1284 expr ':' expr ':' expr {
1291 TOK_ID { delete $1; }
1292 range_or_multirange { delete $3; };
1294 /**********************************************************************/
1298 astbuf1->is_signed = true;
1303 if (astbuf1->children.size() != 1)
1304 frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
1305 astbuf1->children.push_back(new AstNode(AST_RANGE));
1306 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
1307 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
1308 astbuf1->is_signed = true;
1313 if (astbuf1->children.size() != 1)
1314 frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
1315 astbuf1->children.push_back(new AstNode(AST_REALVALUE));
1321 if (astbuf1->children.size() != 1)
1322 frontend_verilog_yyerror("integer/real parameters should not have a range.");
1323 astbuf1->children.push_back($1);
1328 param_signed param_integer param_real param_range |
1329 hierarchical_type_id {
1330 astbuf1->is_custom_type = true;
1331 astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
1332 astbuf1->children.back()->str = *$1;
1336 attr TOK_PARAMETER {
1337 astbuf1 = new AstNode(AST_PARAMETER);
1338 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1339 append_attr(astbuf1, $1);
1340 } param_type param_decl_list ';' {
1345 attr TOK_LOCALPARAM {
1346 astbuf1 = new AstNode(AST_LOCALPARAM);
1347 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1348 append_attr(astbuf1, $1);
1349 } param_type param_decl_list ';' {
1354 single_param_decl | param_decl_list ',' single_param_decl;
1359 if (astbuf1 == nullptr) {
1361 frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword");
1362 node = new AstNode(AST_PARAMETER);
1363 node->children.push_back(AstNode::mkconst_int(0, true));
1365 node = astbuf1->clone();
1368 delete node->children[0];
1369 node->children[0] = $3;
1370 ast_stack.back()->children.push_back(node);
1375 TOK_DEFPARAM defparam_decl_list ';';
1378 single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
1380 single_defparam_decl:
1381 range rvalue '=' expr {
1382 AstNode *node = new AstNode(AST_DEFPARAM);
1383 node->children.push_back($2);
1384 node->children.push_back($4);
1386 node->children.push_back($1);
1387 ast_stack.back()->children.push_back(node);
1390 enum_type: TOK_ENUM {
1391 static int enum_count;
1392 // create parent node for the enum
1393 astbuf2 = new AstNode(AST_ENUM);
1394 ast_stack.back()->children.push_back(astbuf2);
1395 astbuf2->str = std::string("$enum");
1396 astbuf2->str += std::to_string(enum_count++);
1397 // create the template for the names
1398 astbuf1 = new AstNode(AST_ENUM_ITEM);
1399 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1400 } param_signed enum_base_type '{' enum_name_list '}' { // create template for the enum vars
1401 auto tnode = astbuf1->clone();
1404 tnode->type = AST_WIRE;
1405 tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
1406 // drop constant but keep any range
1407 delete tnode->children[0];
1408 tnode->children.erase(tnode->children.begin()); }
1411 enum_base_type: int_vec param_range
1413 | /* nothing */ {astbuf1->is_reg = true; addRange(astbuf1); }
1416 int_atom: TOK_INTEGER {astbuf1->is_reg=true; addRange(astbuf1); } // probably should do byte, range [7:0] here
1419 int_vec: TOK_REG {astbuf1->is_reg = true;}
1420 | TOK_LOGIC {astbuf1->is_logic = true;}
1425 | enum_name_list ',' enum_name_decl
1429 TOK_ID opt_enum_init {
1431 log_assert(astbuf1);
1432 log_assert(astbuf2);
1433 auto node = astbuf1->clone();
1436 delete node->children[0];
1437 node->children[0] = $2 ?: new AstNode(AST_NONE);
1438 astbuf2->children.push_back(node);
1443 '=' basic_expr { $$ = $2; } // TODO: restrict this
1444 | /* optional */ { $$ = NULL; }
1449 | enum_var_list ',' enum_var
1453 log_assert(astbuf1);
1454 log_assert(astbuf2);
1455 auto node = astbuf1->clone();
1456 ast_stack.back()->children.push_back(node);
1459 node->is_enum = true;
1463 enum_decl: enum_type enum_var_list ';' {
1464 //enum_type creates astbuf1 for use by typedef only
1470 attr wire_type range {
1474 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
1476 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
1478 astbuf2 = new AstNode(AST_RANGE);
1479 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
1480 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
1483 if (astbuf2 && astbuf2->children.size() != 2)
1484 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
1485 } delay wire_name_list {
1487 if (astbuf2 != NULL)
1491 attr TOK_SUPPLY0 TOK_ID {
1492 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1493 ast_stack.back()->children.back()->str = *$3;
1494 append_attr(ast_stack.back()->children.back(), $1);
1495 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
1496 ast_stack.back()->children.back()->children[0]->str = *$3;
1498 } opt_supply_wires ';' |
1499 attr TOK_SUPPLY1 TOK_ID {
1500 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1501 ast_stack.back()->children.back()->str = *$3;
1502 append_attr(ast_stack.back()->children.back(), $1);
1503 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
1504 ast_stack.back()->children.back()->children[0]->str = *$3;
1506 } opt_supply_wires ';';
1510 opt_supply_wires ',' TOK_ID {
1511 AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
1512 AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
1513 wire_node->str = *$3;
1514 assign_node->children[0]->str = *$3;
1515 ast_stack.back()->children.push_back(wire_node);
1516 ast_stack.back()->children.push_back(assign_node);
1521 wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
1523 wire_name_and_opt_assign:
1525 bool attr_anyconst = false;
1526 bool attr_anyseq = false;
1527 bool attr_allconst = false;
1528 bool attr_allseq = false;
1529 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
1530 delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
1531 ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
1532 attr_anyconst = true;
1534 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
1535 delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
1536 ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
1539 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
1540 delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
1541 ast_stack.back()->children.back()->attributes.erase(ID::allconst);
1542 attr_allconst = true;
1544 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
1545 delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
1546 ast_stack.back()->children.back()->attributes.erase(ID::allseq);
1549 if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
1550 AstNode *wire = new AstNode(AST_IDENTIFIER);
1551 AstNode *fcall = new AstNode(AST_FCALL);
1552 wire->str = ast_stack.back()->children.back()->str;
1553 fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
1555 fcall->str = "\\$anyconst";
1557 fcall->str = "\\$anyseq";
1559 fcall->str = "\\$allconst";
1561 fcall->str = "\\$allseq";
1562 fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
1563 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
1566 wire_name '=' expr {
1567 AstNode *wire = new AstNode(AST_IDENTIFIER);
1568 wire->str = ast_stack.back()->children.back()->str;
1569 if (astbuf1->is_input) {
1570 if (astbuf1->attributes.count(ID::defaultvalue))
1571 delete astbuf1->attributes.at(ID::defaultvalue);
1572 astbuf1->attributes[ID::defaultvalue] = $3;
1574 else if (astbuf1->is_reg || astbuf1->is_logic){
1575 AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
1576 AstNode *block = new AstNode(AST_BLOCK, assign);
1577 AstNode *init = new AstNode(AST_INITIAL, block);
1579 SET_AST_NODE_LOC(assign, @1, @3);
1580 SET_AST_NODE_LOC(block, @1, @3);
1581 SET_AST_NODE_LOC(init, @1, @3);
1583 ast_stack.back()->children.push_back(init);
1586 AstNode *assign = new AstNode(AST_ASSIGN, wire, $3);
1587 SET_AST_NODE_LOC(assign, @1, @3);
1588 ast_stack.back()->children.push_back(assign);
1594 TOK_ID range_or_multirange {
1595 if (astbuf1 == nullptr)
1596 frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node.");
1597 AstNode *node = astbuf1->clone();
1599 append_attr_clone(node, albuf);
1600 if (astbuf2 != NULL)
1601 node->children.push_back(astbuf2->clone());
1603 if (node->is_input || node->is_output)
1604 frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
1605 if (!astbuf2 && !node->is_custom_type) {
1606 AstNode *rng = new AstNode(AST_RANGE);
1607 rng->children.push_back(AstNode::mkconst_int(0, true));
1608 rng->children.push_back(AstNode::mkconst_int(0, true));
1609 node->children.push_back(rng);
1611 node->type = AST_MEMORY;
1612 auto *rangeNode = $2;
1613 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
1614 // SV array size [n], rewrite as [n-1:0]
1615 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
1616 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
1618 node->children.push_back(rangeNode);
1620 if (current_function_or_task == NULL) {
1621 if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
1622 port_stubs[*$1] = ++port_counter;
1624 if (port_stubs.count(*$1) != 0) {
1625 if (!node->is_input && !node->is_output)
1626 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
1627 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
1628 frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
1629 node->port_id = port_stubs[*$1];
1630 port_stubs.erase(*$1);
1632 if (node->is_input || node->is_output)
1633 frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
1636 if (node->is_input || node->is_output)
1637 node->port_id = current_function_or_task_port_id++;
1639 //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
1640 SET_AST_NODE_LOC(node, @1, @1);
1641 ast_stack.back()->children.push_back(node);
1647 TOK_ASSIGN delay assign_expr_list ';';
1650 assign_expr | assign_expr_list ',' assign_expr;
1654 AstNode *node = new AstNode(AST_ASSIGN, $1, $3);
1655 SET_AST_NODE_LOC(node, @$, @$);
1656 ast_stack.back()->children.push_back(node);
1659 type_name: TOK_ID // first time seen
1660 | TOK_USER_TYPE { if (isInLocalScope($1)) frontend_verilog_yyerror("Duplicate declaration of TYPEDEF '%s'", $1->c_str()+1); }
1664 TOK_TYPEDEF wire_type range type_name range_or_multirange ';' {
1667 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
1669 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
1671 astbuf2 = new AstNode(AST_RANGE);
1672 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
1673 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
1676 if (astbuf2 && astbuf2->children.size() != 2)
1677 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
1679 astbuf1->children.push_back(astbuf2);
1683 AstNode *rng = new AstNode(AST_RANGE);
1684 rng->children.push_back(AstNode::mkconst_int(0, true));
1685 rng->children.push_back(AstNode::mkconst_int(0, true));
1686 astbuf1->children.push_back(rng);
1688 astbuf1->type = AST_MEMORY;
1689 auto *rangeNode = $5;
1690 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
1691 // SV array size [n], rewrite as [n-1:0]
1692 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
1693 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
1695 astbuf1->children.push_back(rangeNode);
1697 addTypedefNode($4, astbuf1);
1699 TOK_TYPEDEF enum_type type_name ';' {
1700 addTypedefNode($3, astbuf1);
1706 astbuf1 = new AstNode(AST_CELL);
1707 append_attr(astbuf1, $1);
1708 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
1709 astbuf1->children[0]->str = *$2;
1711 } cell_parameter_list_opt cell_list ';' {
1714 attr tok_prim_wrapper delay {
1715 astbuf1 = new AstNode(AST_PRIMITIVE);
1717 append_attr(astbuf1, $1);
1728 $$ = new std::string("or");
1733 cell_list ',' single_cell;
1737 astbuf2 = astbuf1->clone();
1738 if (astbuf2->type != AST_PRIMITIVE)
1741 ast_stack.back()->children.push_back(astbuf2);
1742 } '(' cell_port_list ')' {
1743 SET_AST_NODE_LOC(astbuf2, @1, @$);
1745 TOK_ID non_opt_range {
1746 astbuf2 = astbuf1->clone();
1747 if (astbuf2->type != AST_PRIMITIVE)
1750 ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
1751 } '(' cell_port_list ')'{
1752 SET_AST_NODE_LOC(astbuf2, @1, @$);
1757 prim_list ',' single_prim;
1762 astbuf2 = astbuf1->clone();
1763 ast_stack.back()->children.push_back(astbuf2);
1764 } '(' cell_port_list ')' {
1765 SET_AST_NODE_LOC(astbuf2, @1, @$);
1768 cell_parameter_list_opt:
1769 '#' '(' cell_parameter_list ')' | /* empty */;
1771 cell_parameter_list:
1772 cell_parameter | cell_parameter_list ',' cell_parameter;
1777 AstNode *node = new AstNode(AST_PARASET);
1778 astbuf1->children.push_back(node);
1779 node->children.push_back($1);
1781 '.' TOK_ID '(' expr ')' {
1782 AstNode *node = new AstNode(AST_PARASET);
1784 astbuf1->children.push_back(node);
1785 node->children.push_back($4);
1790 cell_port_list_rules {
1791 // remove empty args from end of list
1792 while (!astbuf2->children.empty()) {
1793 AstNode *node = astbuf2->children.back();
1794 if (node->type != AST_ARGUMENT) break;
1795 if (!node->children.empty()) break;
1796 if (!node->str.empty()) break;
1797 astbuf2->children.pop_back();
1802 bool has_positional_args = false;
1803 bool has_named_args = false;
1804 for (auto node : astbuf2->children) {
1805 if (node->type != AST_ARGUMENT) continue;
1806 if (node->str.empty())
1807 has_positional_args = true;
1809 has_named_args = true;
1812 if (has_positional_args && has_named_args)
1813 frontend_verilog_yyerror("Mix of positional and named cell ports.");
1816 cell_port_list_rules:
1817 cell_port | cell_port_list_rules ',' cell_port;
1821 AstNode *node = new AstNode(AST_ARGUMENT);
1822 astbuf2->children.push_back(node);
1826 AstNode *node = new AstNode(AST_ARGUMENT);
1827 astbuf2->children.push_back(node);
1828 node->children.push_back($2);
1831 attr '.' TOK_ID '(' expr ')' {
1832 AstNode *node = new AstNode(AST_ARGUMENT);
1834 astbuf2->children.push_back(node);
1835 node->children.push_back($5);
1839 attr '.' TOK_ID '(' ')' {
1840 AstNode *node = new AstNode(AST_ARGUMENT);
1842 astbuf2->children.push_back(node);
1847 AstNode *node = new AstNode(AST_ARGUMENT);
1849 astbuf2->children.push_back(node);
1850 node->children.push_back(new AstNode(AST_IDENTIFIER));
1851 node->children.back()->str = *$3;
1855 attr TOK_WILDCARD_CONNECT {
1857 frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
1858 astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
1861 always_comb_or_latch:
1869 always_or_always_ff:
1878 attr always_or_always_ff {
1879 AstNode *node = new AstNode(AST_ALWAYS);
1880 append_attr(node, $1);
1882 node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
1883 ast_stack.back()->children.push_back(node);
1884 ast_stack.push_back(node);
1886 AstNode *block = new AstNode(AST_BLOCK);
1887 ast_stack.back()->children.push_back(block);
1888 ast_stack.push_back(block);
1890 SET_AST_NODE_LOC(ast_stack.back(), @6, @6);
1891 ast_stack.pop_back();
1893 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
1894 ast_stack.pop_back();
1896 SET_RULE_LOC(@$, @2, @$);
1898 attr always_comb_or_latch {
1899 AstNode *node = new AstNode(AST_ALWAYS);
1900 append_attr(node, $1);
1902 node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
1904 node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
1905 ast_stack.back()->children.push_back(node);
1906 ast_stack.push_back(node);
1907 AstNode *block = new AstNode(AST_BLOCK);
1908 ast_stack.back()->children.push_back(block);
1909 ast_stack.push_back(block);
1911 ast_stack.pop_back();
1912 ast_stack.pop_back();
1915 AstNode *node = new AstNode(AST_INITIAL);
1916 append_attr(node, $1);
1917 ast_stack.back()->children.push_back(node);
1918 ast_stack.push_back(node);
1919 AstNode *block = new AstNode(AST_BLOCK);
1920 ast_stack.back()->children.push_back(block);
1921 ast_stack.push_back(block);
1923 ast_stack.pop_back();
1924 ast_stack.pop_back();
1928 '@' '(' always_events ')' |
1930 '@' ATTR_BEGIN ')' |
1937 always_events TOK_OR always_event |
1938 always_events ',' always_event;
1942 AstNode *node = new AstNode(AST_POSEDGE);
1943 SET_AST_NODE_LOC(node, @1, @1);
1944 ast_stack.back()->children.push_back(node);
1945 node->children.push_back($2);
1948 AstNode *node = new AstNode(AST_NEGEDGE);
1949 SET_AST_NODE_LOC(node, @1, @1);
1950 ast_stack.back()->children.push_back(node);
1951 node->children.push_back($2);
1954 AstNode *node = new AstNode(AST_EDGE);
1955 ast_stack.back()->children.push_back(node);
1956 node->children.push_back($1);
1987 TOK_MODPORT TOK_ID {
1988 AstNode *modport = new AstNode(AST_MODPORT);
1989 ast_stack.back()->children.push_back(modport);
1990 ast_stack.push_back(modport);
1993 } modport_args_opt {
1994 ast_stack.pop_back();
1995 log_assert(ast_stack.size() == 2);
1999 '(' ')' | '(' modport_args optional_comma ')';
2002 modport_arg | modport_args ',' modport_arg;
2005 modport_type_token modport_member |
2010 AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
2011 ast_stack.back()->children.push_back(modport_member);
2012 modport_member->str = *$1;
2013 modport_member->is_input = current_modport_input;
2014 modport_member->is_output = current_modport_output;
2019 TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
2022 opt_sva_label TOK_ASSERT opt_property '(' expr ')' ';' {
2023 if (noassert_mode) {
2026 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2027 SET_AST_NODE_LOC(node, @1, @6);
2030 ast_stack.back()->children.push_back(node);
2035 opt_sva_label TOK_ASSUME opt_property '(' expr ')' ';' {
2036 if (noassume_mode) {
2039 AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
2040 SET_AST_NODE_LOC(node, @1, @6);
2043 ast_stack.back()->children.push_back(node);
2048 opt_sva_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2049 if (noassert_mode) {
2052 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2053 SET_AST_NODE_LOC(node, @1, @7);
2056 ast_stack.back()->children.push_back(node);
2061 opt_sva_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2062 if (noassume_mode) {
2065 AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
2066 SET_AST_NODE_LOC(node, @1, @7);
2069 ast_stack.back()->children.push_back(node);
2074 opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
2075 AstNode *node = new AstNode(AST_COVER, $5);
2076 SET_AST_NODE_LOC(node, @1, @6);
2077 if ($1 != nullptr) {
2081 ast_stack.back()->children.push_back(node);
2083 opt_sva_label TOK_COVER opt_property '(' ')' ';' {
2084 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2085 SET_AST_NODE_LOC(node, @1, @5);
2086 if ($1 != nullptr) {
2090 ast_stack.back()->children.push_back(node);
2092 opt_sva_label TOK_COVER ';' {
2093 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2094 SET_AST_NODE_LOC(node, @1, @2);
2095 if ($1 != nullptr) {
2099 ast_stack.back()->children.push_back(node);
2101 opt_sva_label TOK_RESTRICT opt_property '(' expr ')' ';' {
2102 if (norestrict_mode) {
2105 AstNode *node = new AstNode(AST_ASSUME, $5);
2106 SET_AST_NODE_LOC(node, @1, @6);
2109 ast_stack.back()->children.push_back(node);
2112 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2116 opt_sva_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2117 if (norestrict_mode) {
2120 AstNode *node = new AstNode(AST_FAIR, $6);
2121 SET_AST_NODE_LOC(node, @1, @7);
2124 ast_stack.back()->children.push_back(node);
2127 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2133 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
2134 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2135 SET_AST_NODE_LOC(node, @1, @6);
2136 ast_stack.back()->children.push_back(node);
2137 if ($1 != nullptr) {
2138 ast_stack.back()->children.back()->str = *$1;
2142 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
2143 AstNode *node = new AstNode(AST_ASSUME, $5);
2144 SET_AST_NODE_LOC(node, @1, @6);
2145 ast_stack.back()->children.push_back(node);
2146 if ($1 != nullptr) {
2147 ast_stack.back()->children.back()->str = *$1;
2151 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2152 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2153 SET_AST_NODE_LOC(node, @1, @7);
2154 ast_stack.back()->children.push_back(node);
2155 if ($1 != nullptr) {
2156 ast_stack.back()->children.back()->str = *$1;
2160 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2161 AstNode *node = new AstNode(AST_FAIR, $6);
2162 SET_AST_NODE_LOC(node, @1, @7);
2163 ast_stack.back()->children.push_back(node);
2164 if ($1 != nullptr) {
2165 ast_stack.back()->children.back()->str = *$1;
2169 opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
2170 AstNode *node = new AstNode(AST_COVER, $5);
2171 SET_AST_NODE_LOC(node, @1, @6);
2172 ast_stack.back()->children.push_back(node);
2173 if ($1 != nullptr) {
2174 ast_stack.back()->children.back()->str = *$1;
2178 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
2179 if (norestrict_mode) {
2182 AstNode *node = new AstNode(AST_ASSUME, $5);
2183 SET_AST_NODE_LOC(node, @1, @6);
2184 ast_stack.back()->children.push_back(node);
2185 if ($1 != nullptr) {
2186 ast_stack.back()->children.back()->str = *$1;
2191 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2192 if (norestrict_mode) {
2195 AstNode *node = new AstNode(AST_FAIR, $6);
2196 SET_AST_NODE_LOC(node, @1, @7);
2197 ast_stack.back()->children.push_back(node);
2198 if ($1 != nullptr) {
2199 ast_stack.back()->children.back()->str = *$1;
2205 simple_behavioral_stmt:
2206 lvalue '=' delay expr {
2207 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4);
2208 ast_stack.back()->children.push_back(node);
2209 SET_AST_NODE_LOC(node, @1, @4);
2211 lvalue TOK_INCREMENT {
2212 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true)));
2213 ast_stack.back()->children.push_back(node);
2214 SET_AST_NODE_LOC(node, @1, @2);
2216 lvalue TOK_DECREMENT {
2217 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true)));
2218 ast_stack.back()->children.push_back(node);
2219 SET_AST_NODE_LOC(node, @1, @2);
2221 lvalue OP_LE delay expr {
2222 AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4);
2223 ast_stack.back()->children.push_back(node);
2224 SET_AST_NODE_LOC(node, @1, @4);
2227 // this production creates the obligatory if-else shift/reduce conflict
2229 defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
2230 non_opt_delay behavioral_stmt |
2231 attr simple_behavioral_stmt ';' |
2235 attr hierarchical_id {
2236 AstNode *node = new AstNode(AST_TCALL);
2239 ast_stack.back()->children.push_back(node);
2240 ast_stack.push_back(node);
2241 append_attr(node, $1);
2243 ast_stack.pop_back();
2245 attr TOK_MSG_TASKS {
2246 AstNode *node = new AstNode(AST_TCALL);
2249 ast_stack.back()->children.push_back(node);
2250 ast_stack.push_back(node);
2251 append_attr(node, $1);
2253 ast_stack.pop_back();
2258 AstNode *node = new AstNode(AST_BLOCK);
2259 ast_stack.back()->children.push_back(node);
2260 ast_stack.push_back(node);
2261 append_attr(node, $1);
2264 } behavioral_stmt_list TOK_END opt_label {
2266 if ($4 != NULL && $8 != NULL && *$4 != *$8)
2267 frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
2268 SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
2271 ast_stack.pop_back();
2274 AstNode *node = new AstNode(AST_FOR);
2275 ast_stack.back()->children.push_back(node);
2276 ast_stack.push_back(node);
2277 append_attr(node, $1);
2278 } simple_behavioral_stmt ';' expr {
2279 ast_stack.back()->children.push_back($7);
2280 } ';' simple_behavioral_stmt ')' {
2281 AstNode *block = new AstNode(AST_BLOCK);
2282 ast_stack.back()->children.push_back(block);
2283 ast_stack.push_back(block);
2285 SET_AST_NODE_LOC(ast_stack.back(), @13, @13);
2286 ast_stack.pop_back();
2287 SET_AST_NODE_LOC(ast_stack.back(), @2, @13);
2288 ast_stack.pop_back();
2290 attr TOK_WHILE '(' expr ')' {
2291 AstNode *node = new AstNode(AST_WHILE);
2292 ast_stack.back()->children.push_back(node);
2293 ast_stack.push_back(node);
2294 append_attr(node, $1);
2295 AstNode *block = new AstNode(AST_BLOCK);
2296 ast_stack.back()->children.push_back($4);
2297 ast_stack.back()->children.push_back(block);
2298 ast_stack.push_back(block);
2300 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2301 ast_stack.pop_back();
2302 ast_stack.pop_back();
2304 attr TOK_REPEAT '(' expr ')' {
2305 AstNode *node = new AstNode(AST_REPEAT);
2306 ast_stack.back()->children.push_back(node);
2307 ast_stack.push_back(node);
2308 append_attr(node, $1);
2309 AstNode *block = new AstNode(AST_BLOCK);
2310 ast_stack.back()->children.push_back($4);
2311 ast_stack.back()->children.push_back(block);
2312 ast_stack.push_back(block);
2314 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2315 ast_stack.pop_back();
2316 ast_stack.pop_back();
2318 attr TOK_IF '(' expr ')' {
2319 AstNode *node = new AstNode(AST_CASE);
2320 AstNode *block = new AstNode(AST_BLOCK);
2321 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
2322 SET_AST_NODE_LOC(cond, @4, @4);
2323 ast_stack.back()->children.push_back(node);
2324 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
2325 node->children.push_back(cond);
2326 ast_stack.push_back(node);
2327 ast_stack.push_back(block);
2328 append_attr(node, $1);
2330 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2332 ast_stack.pop_back();
2333 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2334 ast_stack.pop_back();
2336 case_attr case_type '(' expr ')' {
2337 AstNode *node = new AstNode(AST_CASE, $4);
2338 ast_stack.back()->children.push_back(node);
2339 ast_stack.push_back(node);
2340 append_attr(node, $1);
2341 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2342 } opt_synopsys_attr case_body TOK_ENDCASE {
2343 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2344 case_type_stack.pop_back();
2345 ast_stack.pop_back();
2352 TOK_PRIORITY case_attr {
2355 TOK_UNIQUE case_attr {
2360 attr unique_case_attr {
2361 if ($2) (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false);
2367 case_type_stack.push_back(0);
2370 case_type_stack.push_back('x');
2373 case_type_stack.push_back('z');
2377 opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
2378 if (ast_stack.back()->attributes.count(ID::full_case) == 0)
2379 ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
2381 opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
2382 if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
2383 ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
2387 behavioral_stmt_list:
2388 behavioral_stmt_list behavioral_stmt |
2393 AstNode *block = new AstNode(AST_BLOCK);
2394 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
2395 SET_AST_NODE_LOC(cond, @1, @1);
2397 ast_stack.pop_back();
2398 ast_stack.back()->children.push_back(cond);
2399 ast_stack.push_back(block);
2401 SET_AST_NODE_LOC(ast_stack.back(), @3, @3);
2403 /* empty */ %prec FAKE_THEN;
2406 case_body case_item |
2411 AstNode *node = new AstNode(
2412 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2413 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2414 ast_stack.back()->children.push_back(node);
2415 ast_stack.push_back(node);
2417 AstNode *block = new AstNode(AST_BLOCK);
2418 ast_stack.back()->children.push_back(block);
2419 ast_stack.push_back(block);
2420 case_type_stack.push_back(0);
2422 case_type_stack.pop_back();
2423 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2424 ast_stack.pop_back();
2425 ast_stack.pop_back();
2429 gen_case_body gen_case_item |
2434 AstNode *node = new AstNode(
2435 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2436 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2437 ast_stack.back()->children.push_back(node);
2438 ast_stack.push_back(node);
2440 case_type_stack.push_back(0);
2441 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2443 case_type_stack.pop_back();
2444 ast_stack.pop_back();
2448 case_expr_list ':' |
2453 AstNode *node = new AstNode(AST_DEFAULT);
2454 SET_AST_NODE_LOC(node, @1, @1);
2455 ast_stack.back()->children.push_back(node);
2458 AstNode *node = new AstNode(AST_IDENTIFIER);
2459 SET_AST_NODE_LOC(node, @1, @1);
2460 ast_stack.back()->children.push_back(node);
2461 ast_stack.back()->children.back()->str = *$1;
2465 ast_stack.back()->children.push_back($1);
2467 case_expr_list ',' expr {
2468 ast_stack.back()->children.push_back($3);
2472 hierarchical_id '[' expr ']' '.' rvalue {
2473 $$ = new AstNode(AST_PREFIX, $3, $6);
2477 hierarchical_id range {
2478 $$ = new AstNode(AST_IDENTIFIER, $2);
2480 SET_AST_NODE_LOC($$, @1, @1);
2482 if ($2 == nullptr && ($$->str == "\\$initstate" ||
2483 $$->str == "\\$anyconst" || $$->str == "\\$anyseq" ||
2484 $$->str == "\\$allconst" || $$->str == "\\$allseq"))
2485 $$->type = AST_FCALL;
2487 hierarchical_id non_opt_multirange {
2488 $$ = new AstNode(AST_IDENTIFIER, $2);
2490 SET_AST_NODE_LOC($$, @1, @1);
2498 '{' lvalue_concat_list '}' {
2504 $$ = new AstNode(AST_CONCAT);
2505 $$->children.push_back($1);
2507 expr ',' lvalue_concat_list {
2509 $$->children.push_back($1);
2513 '(' arg_list optional_comma ')' |
2522 arg_list ',' single_arg;
2526 ast_stack.back()->children.push_back($1);
2530 module_gen_body gen_stmt_or_module_body_stmt |
2533 gen_stmt_or_module_body_stmt:
2534 gen_stmt | module_body_stmt |
2539 // this production creates the obligatory if-else shift/reduce conflict
2542 AstNode *node = new AstNode(AST_GENFOR);
2543 ast_stack.back()->children.push_back(node);
2544 ast_stack.push_back(node);
2545 } simple_behavioral_stmt ';' expr {
2546 ast_stack.back()->children.push_back($6);
2547 } ';' simple_behavioral_stmt ')' gen_stmt_block {
2548 SET_AST_NODE_LOC(ast_stack.back(), @1, @11);
2549 ast_stack.pop_back();
2551 TOK_IF '(' expr ')' {
2552 AstNode *node = new AstNode(AST_GENIF);
2553 ast_stack.back()->children.push_back(node);
2554 ast_stack.push_back(node);
2555 ast_stack.back()->children.push_back($3);
2556 AstNode *block = new AstNode(AST_GENBLOCK);
2557 ast_stack.back()->children.push_back(block);
2558 ast_stack.push_back(block);
2560 ast_stack.pop_back();
2562 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2563 ast_stack.pop_back();
2565 case_type '(' expr ')' {
2566 AstNode *node = new AstNode(AST_GENCASE, $3);
2567 ast_stack.back()->children.push_back(node);
2568 ast_stack.push_back(node);
2569 } gen_case_body TOK_ENDCASE {
2570 case_type_stack.pop_back();
2571 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2572 ast_stack.pop_back();
2577 AstNode *node = new AstNode(AST_GENBLOCK);
2578 node->str = $3 ? *$3 : std::string();
2579 ast_stack.back()->children.push_back(node);
2580 ast_stack.push_back(node);
2581 } module_gen_body TOK_END opt_label {
2585 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2586 ast_stack.pop_back();
2589 AstNode *node = new AstNode(AST_TECALL);
2592 ast_stack.back()->children.push_back(node);
2593 ast_stack.push_back(node);
2595 SET_AST_NODE_LOC(ast_stack.back(), @1, @3);
2596 ast_stack.pop_back();
2601 AstNode *node = new AstNode(AST_GENBLOCK);
2602 ast_stack.back()->children.push_back(node);
2603 ast_stack.push_back(node);
2604 } gen_stmt_or_module_body_stmt {
2605 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2606 ast_stack.pop_back();
2610 TOK_ELSE gen_stmt_block | /* empty */ %prec FAKE_THEN;
2616 basic_expr '?' attr expr ':' expr {
2617 $$ = new AstNode(AST_TERNARY);
2618 $$->children.push_back($1);
2619 $$->children.push_back($4);
2620 $$->children.push_back($6);
2621 SET_AST_NODE_LOC($$, @1, @$);
2622 append_attr($$, $3);
2629 '(' expr ')' integral_number {
2630 if ($4->compare(0, 1, "'") != 0)
2631 frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
2633 AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2635 log_error("Value conversion failed: `%s'\n", $4->c_str());
2636 $$ = new AstNode(AST_TO_BITS, bits, val);
2639 hierarchical_id integral_number {
2640 if ($2->compare(0, 1, "'") != 0)
2641 frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
2642 AstNode *bits = new AstNode(AST_IDENTIFIER);
2644 SET_AST_NODE_LOC(bits, @1, @1);
2645 AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2646 SET_AST_NODE_LOC(val, @2, @2);
2648 log_error("Value conversion failed: `%s'\n", $2->c_str());
2649 $$ = new AstNode(AST_TO_BITS, bits, val);
2654 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2655 SET_AST_NODE_LOC($$, @1, @1);
2657 log_error("Value conversion failed: `%s'\n", $1->c_str());
2661 $$ = new AstNode(AST_REALVALUE);
2662 char *p = (char*)malloc(GetSize(*$1) + 1), *q;
2663 for (int i = 0, j = 0; j < GetSize(*$1); j++)
2664 if ((*$1)[j] != '_')
2665 p[i++] = (*$1)[j], p[i] = 0;
2666 $$->realvalue = strtod(p, &q);
2667 SET_AST_NODE_LOC($$, @1, @1);
2668 log_assert(*q == 0);
2673 $$ = AstNode::mkconst_str(*$1);
2674 SET_AST_NODE_LOC($$, @1, @1);
2677 hierarchical_id attr {
2678 AstNode *node = new AstNode(AST_FCALL);
2681 ast_stack.push_back(node);
2682 SET_AST_NODE_LOC(node, @1, @1);
2683 append_attr(node, $2);
2684 } '(' arg_list optional_comma ')' {
2685 $$ = ast_stack.back();
2686 ast_stack.pop_back();
2688 TOK_TO_SIGNED attr '(' expr ')' {
2689 $$ = new AstNode(AST_TO_SIGNED, $4);
2690 append_attr($$, $2);
2692 TOK_TO_UNSIGNED attr '(' expr ')' {
2693 $$ = new AstNode(AST_TO_UNSIGNED, $4);
2694 append_attr($$, $2);
2699 '(' expr ':' expr ':' expr ')' {
2704 '{' concat_list '}' {
2707 '{' expr '{' concat_list '}' '}' {
2708 $$ = new AstNode(AST_REPLICATE, $2, $4);
2710 '~' attr basic_expr %prec UNARY_OPS {
2711 $$ = new AstNode(AST_BIT_NOT, $3);
2712 SET_AST_NODE_LOC($$, @1, @3);
2713 append_attr($$, $2);
2715 basic_expr '&' attr basic_expr {
2716 $$ = new AstNode(AST_BIT_AND, $1, $4);
2717 SET_AST_NODE_LOC($$, @1, @4);
2718 append_attr($$, $3);
2720 basic_expr OP_NAND attr basic_expr {
2721 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
2722 SET_AST_NODE_LOC($$, @1, @4);
2723 append_attr($$, $3);
2725 basic_expr '|' attr basic_expr {
2726 $$ = new AstNode(AST_BIT_OR, $1, $4);
2727 SET_AST_NODE_LOC($$, @1, @4);
2728 append_attr($$, $3);
2730 basic_expr OP_NOR attr basic_expr {
2731 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
2732 SET_AST_NODE_LOC($$, @1, @4);
2733 append_attr($$, $3);
2735 basic_expr '^' attr basic_expr {
2736 $$ = new AstNode(AST_BIT_XOR, $1, $4);
2737 SET_AST_NODE_LOC($$, @1, @4);
2738 append_attr($$, $3);
2740 basic_expr OP_XNOR attr basic_expr {
2741 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
2742 SET_AST_NODE_LOC($$, @1, @4);
2743 append_attr($$, $3);
2745 '&' attr basic_expr %prec UNARY_OPS {
2746 $$ = new AstNode(AST_REDUCE_AND, $3);
2747 SET_AST_NODE_LOC($$, @1, @3);
2748 append_attr($$, $2);
2750 OP_NAND attr basic_expr %prec UNARY_OPS {
2751 $$ = new AstNode(AST_REDUCE_AND, $3);
2752 SET_AST_NODE_LOC($$, @1, @3);
2753 append_attr($$, $2);
2754 $$ = new AstNode(AST_LOGIC_NOT, $$);
2756 '|' attr basic_expr %prec UNARY_OPS {
2757 $$ = new AstNode(AST_REDUCE_OR, $3);
2758 SET_AST_NODE_LOC($$, @1, @3);
2759 append_attr($$, $2);
2761 OP_NOR attr basic_expr %prec UNARY_OPS {
2762 $$ = new AstNode(AST_REDUCE_OR, $3);
2763 SET_AST_NODE_LOC($$, @1, @3);
2764 append_attr($$, $2);
2765 $$ = new AstNode(AST_LOGIC_NOT, $$);
2766 SET_AST_NODE_LOC($$, @1, @3);
2768 '^' attr basic_expr %prec UNARY_OPS {
2769 $$ = new AstNode(AST_REDUCE_XOR, $3);
2770 SET_AST_NODE_LOC($$, @1, @3);
2771 append_attr($$, $2);
2773 OP_XNOR attr basic_expr %prec UNARY_OPS {
2774 $$ = new AstNode(AST_REDUCE_XNOR, $3);
2775 SET_AST_NODE_LOC($$, @1, @3);
2776 append_attr($$, $2);
2778 basic_expr OP_SHL attr basic_expr {
2779 $$ = new AstNode(AST_SHIFT_LEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2780 SET_AST_NODE_LOC($$, @1, @4);
2781 append_attr($$, $3);
2783 basic_expr OP_SHR attr basic_expr {
2784 $$ = new AstNode(AST_SHIFT_RIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2785 SET_AST_NODE_LOC($$, @1, @4);
2786 append_attr($$, $3);
2788 basic_expr OP_SSHL attr basic_expr {
2789 $$ = new AstNode(AST_SHIFT_SLEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2790 SET_AST_NODE_LOC($$, @1, @4);
2791 append_attr($$, $3);
2793 basic_expr OP_SSHR attr basic_expr {
2794 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2795 SET_AST_NODE_LOC($$, @1, @4);
2796 append_attr($$, $3);
2798 basic_expr '<' attr basic_expr {
2799 $$ = new AstNode(AST_LT, $1, $4);
2800 SET_AST_NODE_LOC($$, @1, @4);
2801 append_attr($$, $3);
2803 basic_expr OP_LE attr basic_expr {
2804 $$ = new AstNode(AST_LE, $1, $4);
2805 SET_AST_NODE_LOC($$, @1, @4);
2806 append_attr($$, $3);
2808 basic_expr OP_EQ attr basic_expr {
2809 $$ = new AstNode(AST_EQ, $1, $4);
2810 SET_AST_NODE_LOC($$, @1, @4);
2811 append_attr($$, $3);
2813 basic_expr OP_NE attr basic_expr {
2814 $$ = new AstNode(AST_NE, $1, $4);
2815 SET_AST_NODE_LOC($$, @1, @4);
2816 append_attr($$, $3);
2818 basic_expr OP_EQX attr basic_expr {
2819 $$ = new AstNode(AST_EQX, $1, $4);
2820 SET_AST_NODE_LOC($$, @1, @4);
2821 append_attr($$, $3);
2823 basic_expr OP_NEX attr basic_expr {
2824 $$ = new AstNode(AST_NEX, $1, $4);
2825 SET_AST_NODE_LOC($$, @1, @4);
2826 append_attr($$, $3);
2828 basic_expr OP_GE attr basic_expr {
2829 $$ = new AstNode(AST_GE, $1, $4);
2830 SET_AST_NODE_LOC($$, @1, @4);
2831 append_attr($$, $3);
2833 basic_expr '>' attr basic_expr {
2834 $$ = new AstNode(AST_GT, $1, $4);
2835 SET_AST_NODE_LOC($$, @1, @4);
2836 append_attr($$, $3);
2838 basic_expr '+' attr basic_expr {
2839 $$ = new AstNode(AST_ADD, $1, $4);
2840 SET_AST_NODE_LOC($$, @1, @4);
2841 append_attr($$, $3);
2843 basic_expr '-' attr basic_expr {
2844 $$ = new AstNode(AST_SUB, $1, $4);
2845 SET_AST_NODE_LOC($$, @1, @4);
2846 append_attr($$, $3);
2848 basic_expr '*' attr basic_expr {
2849 $$ = new AstNode(AST_MUL, $1, $4);
2850 SET_AST_NODE_LOC($$, @1, @4);
2851 append_attr($$, $3);
2853 basic_expr '/' attr basic_expr {
2854 $$ = new AstNode(AST_DIV, $1, $4);
2855 SET_AST_NODE_LOC($$, @1, @4);
2856 append_attr($$, $3);
2858 basic_expr '%' attr basic_expr {
2859 $$ = new AstNode(AST_MOD, $1, $4);
2860 SET_AST_NODE_LOC($$, @1, @4);
2861 append_attr($$, $3);
2863 basic_expr OP_POW attr basic_expr {
2864 $$ = new AstNode(AST_POW, $1, $4);
2865 SET_AST_NODE_LOC($$, @1, @4);
2866 append_attr($$, $3);
2868 '+' attr basic_expr %prec UNARY_OPS {
2869 $$ = new AstNode(AST_POS, $3);
2870 SET_AST_NODE_LOC($$, @1, @3);
2871 append_attr($$, $2);
2873 '-' attr basic_expr %prec UNARY_OPS {
2874 $$ = new AstNode(AST_NEG, $3);
2875 SET_AST_NODE_LOC($$, @1, @3);
2876 append_attr($$, $2);
2878 basic_expr OP_LAND attr basic_expr {
2879 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
2880 SET_AST_NODE_LOC($$, @1, @4);
2881 append_attr($$, $3);
2883 basic_expr OP_LOR attr basic_expr {
2884 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
2885 SET_AST_NODE_LOC($$, @1, @4);
2886 append_attr($$, $3);
2888 '!' attr basic_expr %prec UNARY_OPS {
2889 $$ = new AstNode(AST_LOGIC_NOT, $3);
2890 SET_AST_NODE_LOC($$, @1, @3);
2891 append_attr($$, $2);
2896 $$ = new AstNode(AST_CONCAT, $1);
2898 expr ',' concat_list {
2900 $$->children.push_back($1);
2904 TOK_CONSTVAL { $$ = $1; } |
2905 TOK_UNBASED_UNSIZED_CONSTVAL { $$ = $1; } |
2906 TOK_BASE TOK_BASED_CONSTVAL {
2911 TOK_CONSTVAL TOK_BASE TOK_BASED_CONSTVAL {
2912 $1->append(*$2).append(*$3);