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Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor
[yosys.git] / frontends / verilog / verilog_parser.y
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * The Verilog frontend.
21 *
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
26 *
27 * ---
28 *
29 * This is the actual bison parser for Verilog code. The AST ist created directly
30 * from the bison reduce functions here. Note that this code uses a few global
31 * variables to hold the state of the AST generator and therefore this parser is
32 * not reentrant.
33 *
34 */
35
36 %{
37 #include <list>
38 #include <stack>
39 #include <string.h>
40 #include "frontends/verilog/verilog_frontend.h"
41 #include "frontends/verilog/verilog_parser.tab.hh"
42 #include "kernel/log.h"
43
44 #define YYLEX_PARAM &yylval, &yylloc
45
46 USING_YOSYS_NAMESPACE
47 using namespace AST;
48 using namespace VERILOG_FRONTEND;
49
50 YOSYS_NAMESPACE_BEGIN
51 namespace VERILOG_FRONTEND {
52 int port_counter;
53 std::map<std::string, int> port_stubs;
54 std::map<std::string, AstNode*> *attr_list, default_attr_list;
55 std::stack<std::map<std::string, AstNode*> *> attr_list_stack;
56 std::map<std::string, AstNode*> *albuf;
57 std::vector<UserTypeMap*> user_type_stack;
58 std::map<std::string, AstNode*> pkg_user_types;
59 std::vector<AstNode*> ast_stack;
60 struct AstNode *astbuf1, *astbuf2, *astbuf3;
61 struct AstNode *current_function_or_task;
62 struct AstNode *current_ast, *current_ast_mod;
63 int current_function_or_task_port_id;
64 std::vector<char> case_type_stack;
65 bool do_not_require_port_stubs;
66 bool default_nettype_wire;
67 bool sv_mode, formal_mode, lib_mode, specify_mode;
68 bool noassert_mode, noassume_mode, norestrict_mode;
69 bool assume_asserts_mode, assert_assumes_mode;
70 bool current_wire_rand, current_wire_const;
71 bool current_modport_input, current_modport_output;
72 std::istream *lexin;
73 }
74 YOSYS_NAMESPACE_END
75
76 #define SET_AST_NODE_LOC(WHICH, BEGIN, END) \
77 do { (WHICH)->location.first_line = (BEGIN).first_line; \
78 (WHICH)->location.first_column = (BEGIN).first_column; \
79 (WHICH)->location.last_line = (END).last_line; \
80 (WHICH)->location.last_column = (END).last_column; } while(0)
81
82 #define SET_RULE_LOC(LHS, BEGIN, END) \
83 do { (LHS).first_line = (BEGIN).first_line; \
84 (LHS).first_column = (BEGIN).first_column; \
85 (LHS).last_line = (END).last_line; \
86 (LHS).last_column = (END).last_column; } while(0)
87
88 int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
89
90 static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
91 {
92 for (auto &it : *al) {
93 if (ast->attributes.count(it.first) > 0)
94 delete ast->attributes[it.first];
95 ast->attributes[it.first] = it.second;
96 }
97 delete al;
98 }
99
100 static void append_attr_clone(AstNode *ast, std::map<std::string, AstNode*> *al)
101 {
102 for (auto &it : *al) {
103 if (ast->attributes.count(it.first) > 0)
104 delete ast->attributes[it.first];
105 ast->attributes[it.first] = it.second->clone();
106 }
107 }
108
109 static void free_attr(std::map<std::string, AstNode*> *al)
110 {
111 for (auto &it : *al)
112 delete it.second;
113 delete al;
114 }
115
116 struct specify_target {
117 char polarity_op;
118 AstNode *dst, *dat;
119 };
120
121 struct specify_triple {
122 AstNode *t_min, *t_avg, *t_max;
123 };
124
125 struct specify_rise_fall {
126 specify_triple rise;
127 specify_triple fall;
128 };
129
130 static void addTypedefNode(std::string *name, AstNode *node)
131 {
132 log_assert(node);
133 auto *tnode = new AstNode(AST_TYPEDEF, node);
134 tnode->str = *name;
135 auto user_types = user_type_stack.back();
136 (*user_types)[*name] = tnode;
137 if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {
138 // typedef inside a package so we need the qualified name
139 auto qname = current_ast_mod->str + "::" + (*name).substr(1);
140 pkg_user_types[qname] = tnode;
141 }
142 delete name;
143 ast_stack.back()->children.push_back(tnode);
144 }
145
146 static void enterTypeScope()
147 {
148 auto user_types = new UserTypeMap();
149 user_type_stack.push_back(user_types);
150 }
151
152 static void exitTypeScope()
153 {
154 user_type_stack.pop_back();
155 }
156
157 static bool isInLocalScope(const std::string *name)
158 {
159 // tests if a name was declared in the current block scope
160 auto user_types = user_type_stack.back();
161 return (user_types->count(*name) > 0);
162 }
163
164 static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
165 {
166 auto range = new AstNode(AST_RANGE);
167 range->children.push_back(AstNode::mkconst_int(msb, true));
168 range->children.push_back(AstNode::mkconst_int(lsb, true));
169 range->is_signed = isSigned;
170 return range;
171 }
172
173 static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned = true)
174 {
175 auto range = makeRange(msb, lsb, isSigned);
176 parent->children.push_back(range);
177 }
178 %}
179
180 %define api.prefix {frontend_verilog_yy}
181 %define api.pure
182
183 /* The union is defined in the header, so we need to provide all the
184 * includes it requires
185 */
186 %code requires {
187 #include <map>
188 #include <string>
189 #include "frontends/verilog/verilog_frontend.h"
190 }
191
192 %union {
193 std::string *string;
194 struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
195 std::map<std::string, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
196 struct specify_target *specify_target_ptr;
197 struct specify_triple *specify_triple_ptr;
198 struct specify_rise_fall *specify_rise_fall_ptr;
199 bool boolean;
200 char ch;
201 }
202
203 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
204 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
205 %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL
206 %token <string> TOK_USER_TYPE TOK_PKG_USER_TYPE
207 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
208 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
209 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
210 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
211 %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
212 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
213 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
214 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
215 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
216 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
217 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
218 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
219 %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
220 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
221 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
222 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
223 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
224 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
225 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
226
227 %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
228 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
229 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
230 %type <string> type_name
231 %type <ast> opt_enum_init
232 %type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
233 %type <al> attr case_attr
234
235 %type <specify_target_ptr> specify_target
236 %type <specify_triple_ptr> specify_triple specify_opt_triple
237 %type <specify_rise_fall_ptr> specify_rise_fall
238 %type <ast> specify_if specify_condition
239 %type <ch> specify_edge
240
241 // operator precedence from low to high
242 %left OP_LOR
243 %left OP_LAND
244 %left '|' OP_NOR
245 %left '^' OP_XNOR
246 %left '&' OP_NAND
247 %left OP_EQ OP_NE OP_EQX OP_NEX
248 %left '<' OP_LE OP_GE '>'
249 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
250 %left '+' '-'
251 %left '*' '/' '%'
252 %left OP_POW
253 %right UNARY_OPS
254
255 %define parse.error verbose
256 %define parse.lac full
257
258 %nonassoc FAKE_THEN
259 %nonassoc TOK_ELSE
260
261 %debug
262 %locations
263
264 %%
265
266 input: {
267 ast_stack.clear();
268 ast_stack.push_back(current_ast);
269 } design {
270 ast_stack.pop_back();
271 log_assert(GetSize(ast_stack) == 0);
272 for (auto &it : default_attr_list)
273 delete it.second;
274 default_attr_list.clear();
275 };
276
277 design:
278 module design |
279 defattr design |
280 task_func_decl design |
281 param_decl design |
282 localparam_decl design |
283 typedef_decl design |
284 package design |
285 interface design |
286 /* empty */;
287
288 attr:
289 {
290 if (attr_list != nullptr)
291 attr_list_stack.push(attr_list);
292 attr_list = new std::map<std::string, AstNode*>;
293 for (auto &it : default_attr_list)
294 (*attr_list)[it.first] = it.second->clone();
295 } attr_opt {
296 $$ = attr_list;
297 if (!attr_list_stack.empty()) {
298 attr_list = attr_list_stack.top();
299 attr_list_stack.pop();
300 } else
301 attr_list = nullptr;
302 };
303
304 attr_opt:
305 attr_opt ATTR_BEGIN opt_attr_list ATTR_END {
306 SET_RULE_LOC(@$, @2, @$);
307 }|
308 /* empty */;
309
310 defattr:
311 DEFATTR_BEGIN {
312 if (attr_list != nullptr)
313 attr_list_stack.push(attr_list);
314 attr_list = new std::map<std::string, AstNode*>;
315 for (auto &it : default_attr_list)
316 delete it.second;
317 default_attr_list.clear();
318 } opt_attr_list {
319 attr_list->swap(default_attr_list);
320 delete attr_list;
321 if (!attr_list_stack.empty()) {
322 attr_list = attr_list_stack.top();
323 attr_list_stack.pop();
324 } else
325 attr_list = nullptr;
326 } DEFATTR_END;
327
328 opt_attr_list:
329 attr_list | /* empty */;
330
331 attr_list:
332 attr_assign |
333 attr_list ',' attr_assign;
334
335 attr_assign:
336 hierarchical_id {
337 if (attr_list->count(*$1) != 0)
338 delete (*attr_list)[*$1];
339 (*attr_list)[*$1] = AstNode::mkconst_int(1, false);
340 delete $1;
341 } |
342 hierarchical_id '=' expr {
343 if (attr_list->count(*$1) != 0)
344 delete (*attr_list)[*$1];
345 (*attr_list)[*$1] = $3;
346 delete $1;
347 };
348
349 hierarchical_id:
350 TOK_ID {
351 $$ = $1;
352 } |
353 hierarchical_id TOK_PACKAGESEP TOK_ID {
354 if ($3->compare(0, 1, "\\") == 0)
355 *$1 += "::" + $3->substr(1);
356 else
357 *$1 += "::" + *$3;
358 delete $3;
359 $$ = $1;
360 } |
361 hierarchical_id '.' TOK_ID {
362 if ($3->compare(0, 1, "\\") == 0)
363 *$1 += "." + $3->substr(1);
364 else
365 *$1 += "." + *$3;
366 delete $3;
367 $$ = $1;
368 };
369
370 hierarchical_type_id:
371 TOK_USER_TYPE
372 | TOK_PKG_USER_TYPE // package qualified type name
373 | '(' TOK_USER_TYPE ')' { $$ = $2; } // non-standard grammar
374 ;
375
376 module:
377 attr TOK_MODULE {
378 enterTypeScope();
379 } TOK_ID {
380 do_not_require_port_stubs = false;
381 AstNode *mod = new AstNode(AST_MODULE);
382 ast_stack.back()->children.push_back(mod);
383 ast_stack.push_back(mod);
384 current_ast_mod = mod;
385 port_stubs.clear();
386 port_counter = 0;
387 mod->str = *$4;
388 append_attr(mod, $1);
389 delete $4;
390 } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
391 if (port_stubs.size() != 0)
392 frontend_verilog_yyerror("Missing details for module port `%s'.",
393 port_stubs.begin()->first.c_str());
394 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
395 ast_stack.pop_back();
396 log_assert(ast_stack.size() == 1);
397 current_ast_mod = NULL;
398 exitTypeScope();
399 };
400
401 module_para_opt:
402 '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
403
404 module_para_list:
405 single_module_para | module_para_list ',' single_module_para;
406
407 single_module_para:
408 /* empty */ |
409 attr TOK_PARAMETER {
410 if (astbuf1) delete astbuf1;
411 astbuf1 = new AstNode(AST_PARAMETER);
412 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
413 append_attr(astbuf1, $1);
414 } param_type single_param_decl |
415 attr TOK_LOCALPARAM {
416 if (astbuf1) delete astbuf1;
417 astbuf1 = new AstNode(AST_LOCALPARAM);
418 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
419 append_attr(astbuf1, $1);
420 } param_type single_param_decl |
421 single_param_decl;
422
423 module_args_opt:
424 '(' ')' | /* empty */ | '(' module_args optional_comma ')';
425
426 module_args:
427 module_arg | module_args ',' module_arg;
428
429 optional_comma:
430 ',' | /* empty */;
431
432 module_arg_opt_assignment:
433 '=' expr {
434 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
435 AstNode *wire = new AstNode(AST_IDENTIFIER);
436 wire->str = ast_stack.back()->children.back()->str;
437 if (ast_stack.back()->children.back()->is_input) {
438 AstNode *n = ast_stack.back()->children.back();
439 if (n->attributes.count("\\defaultvalue"))
440 delete n->attributes.at("\\defaultvalue");
441 n->attributes["\\defaultvalue"] = $2;
442 } else
443 if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
444 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
445 else
446 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
447 } else
448 frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
449 } |
450 /* empty */;
451
452 module_arg:
453 TOK_ID {
454 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
455 AstNode *node = ast_stack.back()->children.back()->clone();
456 node->str = *$1;
457 node->port_id = ++port_counter;
458 ast_stack.back()->children.push_back(node);
459 SET_AST_NODE_LOC(node, @1, @1);
460 } else {
461 if (port_stubs.count(*$1) != 0)
462 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
463 port_stubs[*$1] = ++port_counter;
464 }
465 delete $1;
466 } module_arg_opt_assignment |
467 TOK_ID {
468 astbuf1 = new AstNode(AST_INTERFACEPORT);
469 astbuf1->children.push_back(new AstNode(AST_INTERFACEPORTTYPE));
470 astbuf1->children[0]->str = *$1;
471 delete $1;
472 } TOK_ID { /* SV interfaces */
473 if (!sv_mode)
474 frontend_verilog_yyerror("Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
475 astbuf2 = astbuf1->clone(); // really only needed if multiple instances of same type.
476 astbuf2->str = *$3;
477 delete $3;
478 astbuf2->port_id = ++port_counter;
479 ast_stack.back()->children.push_back(astbuf2);
480 delete astbuf1; // really only needed if multiple instances of same type.
481 } module_arg_opt_assignment |
482 attr wire_type range TOK_ID {
483 AstNode *node = $2;
484 node->str = *$4;
485 SET_AST_NODE_LOC(node, @4, @4);
486 node->port_id = ++port_counter;
487 if ($3 != NULL)
488 node->children.push_back($3);
489 if (!node->is_input && !node->is_output)
490 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
491 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
492 frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
493 ast_stack.back()->children.push_back(node);
494 append_attr(node, $1);
495 delete $4;
496 } module_arg_opt_assignment |
497 '.' '.' '.' {
498 do_not_require_port_stubs = true;
499 };
500
501 package:
502 attr TOK_PACKAGE {
503 enterTypeScope();
504 } TOK_ID {
505 AstNode *mod = new AstNode(AST_PACKAGE);
506 ast_stack.back()->children.push_back(mod);
507 ast_stack.push_back(mod);
508 current_ast_mod = mod;
509 mod->str = *$4;
510 append_attr(mod, $1);
511 } ';' package_body TOK_ENDPACKAGE {
512 ast_stack.pop_back();
513 current_ast_mod = NULL;
514 exitTypeScope();
515 };
516
517 package_body:
518 package_body package_body_stmt
519 | // optional
520 ;
521
522 package_body_stmt:
523 typedef_decl |
524 localparam_decl;
525
526 interface:
527 TOK_INTERFACE {
528 enterTypeScope();
529 } TOK_ID {
530 do_not_require_port_stubs = false;
531 AstNode *intf = new AstNode(AST_INTERFACE);
532 ast_stack.back()->children.push_back(intf);
533 ast_stack.push_back(intf);
534 current_ast_mod = intf;
535 port_stubs.clear();
536 port_counter = 0;
537 intf->str = *$3;
538 delete $3;
539 } module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
540 if (port_stubs.size() != 0)
541 frontend_verilog_yyerror("Missing details for module port `%s'.",
542 port_stubs.begin()->first.c_str());
543 ast_stack.pop_back();
544 log_assert(ast_stack.size() == 1);
545 current_ast_mod = NULL;
546 exitTypeScope();
547 };
548
549 interface_body:
550 interface_body interface_body_stmt |;
551
552 interface_body_stmt:
553 param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
554 modport_stmt;
555
556 non_opt_delay:
557 '#' TOK_ID { delete $2; } |
558 '#' TOK_CONSTVAL { delete $2; } |
559 '#' TOK_REALVAL { delete $2; } |
560 '#' '(' expr ')' { delete $3; } |
561 '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
562
563 delay:
564 non_opt_delay | /* empty */;
565
566 wire_type:
567 {
568 astbuf3 = new AstNode(AST_WIRE);
569 current_wire_rand = false;
570 current_wire_const = false;
571 } wire_type_token_list {
572 $$ = astbuf3;
573 SET_RULE_LOC(@$, @2, @$);
574 };
575
576 wire_type_token_list:
577 wire_type_token |
578 wire_type_token_list wire_type_token |
579 wire_type_token_io |
580 hierarchical_type_id {
581 astbuf3->is_custom_type = true;
582 astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
583 astbuf3->children.back()->str = *$1;
584 };
585
586 wire_type_token_io:
587 TOK_INPUT {
588 astbuf3->is_input = true;
589 } |
590 TOK_OUTPUT {
591 astbuf3->is_output = true;
592 } |
593 TOK_INOUT {
594 astbuf3->is_input = true;
595 astbuf3->is_output = true;
596 };
597
598 wire_type_token:
599 TOK_WIRE {
600 } |
601 TOK_WOR {
602 astbuf3->is_wor = true;
603 } |
604 TOK_WAND {
605 astbuf3->is_wand = true;
606 } |
607 TOK_REG {
608 astbuf3->is_reg = true;
609 } |
610 TOK_LOGIC {
611 astbuf3->is_logic = true;
612 } |
613 TOK_VAR {
614 astbuf3->is_logic = true;
615 } |
616 TOK_INTEGER {
617 astbuf3->is_reg = true;
618 astbuf3->range_left = 31;
619 astbuf3->range_right = 0;
620 astbuf3->is_signed = true;
621 } |
622 TOK_GENVAR {
623 astbuf3->type = AST_GENVAR;
624 astbuf3->is_reg = true;
625 astbuf3->is_signed = true;
626 astbuf3->range_left = 31;
627 astbuf3->range_right = 0;
628 } |
629 TOK_SIGNED {
630 astbuf3->is_signed = true;
631 } |
632 TOK_RAND {
633 current_wire_rand = true;
634 } |
635 TOK_CONST {
636 current_wire_const = true;
637 };
638
639 non_opt_range:
640 '[' expr ':' expr ']' {
641 $$ = new AstNode(AST_RANGE);
642 $$->children.push_back($2);
643 $$->children.push_back($4);
644 } |
645 '[' expr TOK_POS_INDEXED expr ']' {
646 $$ = new AstNode(AST_RANGE);
647 AstNode *expr = new AstNode(AST_CONCAT, $2);
648 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
649 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
650 } |
651 '[' expr TOK_NEG_INDEXED expr ']' {
652 $$ = new AstNode(AST_RANGE);
653 AstNode *expr = new AstNode(AST_CONCAT, $2);
654 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
655 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
656 } |
657 '[' expr ']' {
658 $$ = new AstNode(AST_RANGE);
659 $$->children.push_back($2);
660 };
661
662 non_opt_multirange:
663 non_opt_range non_opt_range {
664 $$ = new AstNode(AST_MULTIRANGE, $1, $2);
665 } |
666 non_opt_multirange non_opt_range {
667 $$ = $1;
668 $$->children.push_back($2);
669 };
670
671 range:
672 non_opt_range {
673 $$ = $1;
674 } |
675 /* empty */ {
676 $$ = NULL;
677 };
678
679 range_or_multirange:
680 range { $$ = $1; } |
681 non_opt_multirange { $$ = $1; };
682
683 range_or_signed_int:
684 range {
685 $$ = $1;
686 } |
687 TOK_INTEGER {
688 $$ = new AstNode(AST_RANGE);
689 $$->children.push_back(AstNode::mkconst_int(31, true));
690 $$->children.push_back(AstNode::mkconst_int(0, true));
691 $$->is_signed = true;
692 };
693
694 module_body:
695 module_body module_body_stmt |
696 /* the following line makes the generate..endgenrate keywords optional */
697 module_body gen_stmt |
698 /* empty */;
699
700 module_body_stmt:
701 task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
702 enum_decl |
703 always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
704
705 checker_decl:
706 TOK_CHECKER TOK_ID ';' {
707 AstNode *node = new AstNode(AST_GENBLOCK);
708 node->str = *$2;
709 ast_stack.back()->children.push_back(node);
710 ast_stack.push_back(node);
711 } module_body TOK_ENDCHECKER {
712 delete $2;
713 ast_stack.pop_back();
714 };
715
716 task_func_decl:
717 attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
718 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
719 current_function_or_task->str = *$4;
720 append_attr(current_function_or_task, $1);
721 ast_stack.back()->children.push_back(current_function_or_task);
722 delete $3;
723 delete $4;
724 } opt_dpi_function_args ';' {
725 current_function_or_task = NULL;
726 } |
727 attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
728 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
729 current_function_or_task->str = *$6;
730 append_attr(current_function_or_task, $1);
731 ast_stack.back()->children.push_back(current_function_or_task);
732 delete $3;
733 delete $5;
734 delete $6;
735 } opt_dpi_function_args ';' {
736 current_function_or_task = NULL;
737 } |
738 attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
739 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
740 current_function_or_task->str = *$8;
741 append_attr(current_function_or_task, $1);
742 ast_stack.back()->children.push_back(current_function_or_task);
743 delete $3;
744 delete $5;
745 delete $7;
746 delete $8;
747 } opt_dpi_function_args ';' {
748 current_function_or_task = NULL;
749 } |
750 attr TOK_TASK opt_automatic TOK_ID {
751 current_function_or_task = new AstNode(AST_TASK);
752 current_function_or_task->str = *$4;
753 append_attr(current_function_or_task, $1);
754 ast_stack.back()->children.push_back(current_function_or_task);
755 ast_stack.push_back(current_function_or_task);
756 current_function_or_task_port_id = 1;
757 delete $4;
758 } task_func_args_opt ';' task_func_body TOK_ENDTASK {
759 current_function_or_task = NULL;
760 ast_stack.pop_back();
761 } |
762 attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID {
763 current_function_or_task = new AstNode(AST_FUNCTION);
764 current_function_or_task->str = *$6;
765 append_attr(current_function_or_task, $1);
766 ast_stack.back()->children.push_back(current_function_or_task);
767 ast_stack.push_back(current_function_or_task);
768 AstNode *outreg = new AstNode(AST_WIRE);
769 outreg->str = *$6;
770 outreg->is_signed = $4;
771 outreg->is_reg = true;
772 if ($5 != NULL) {
773 outreg->children.push_back($5);
774 outreg->is_signed = $4 || $5->is_signed;
775 $5->is_signed = false;
776 }
777 current_function_or_task->children.push_back(outreg);
778 current_function_or_task_port_id = 1;
779 delete $6;
780 } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
781 current_function_or_task = NULL;
782 ast_stack.pop_back();
783 };
784
785 dpi_function_arg:
786 TOK_ID TOK_ID {
787 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
788 delete $1;
789 delete $2;
790 } |
791 TOK_ID {
792 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
793 delete $1;
794 };
795
796 opt_dpi_function_args:
797 '(' dpi_function_args ')' |
798 /* empty */;
799
800 dpi_function_args:
801 dpi_function_args ',' dpi_function_arg |
802 dpi_function_args ',' |
803 dpi_function_arg |
804 /* empty */;
805
806 opt_automatic:
807 TOK_AUTOMATIC |
808 /* empty */;
809
810 opt_signed:
811 TOK_SIGNED {
812 $$ = true;
813 } |
814 /* empty */ {
815 $$ = false;
816 };
817
818 task_func_args_opt:
819 '(' ')' | /* empty */ | '(' {
820 albuf = nullptr;
821 astbuf1 = nullptr;
822 astbuf2 = nullptr;
823 } task_func_args optional_comma {
824 delete astbuf1;
825 if (astbuf2 != NULL)
826 delete astbuf2;
827 free_attr(albuf);
828 } ')';
829
830 task_func_args:
831 task_func_port | task_func_args ',' task_func_port;
832
833 task_func_port:
834 attr wire_type range {
835 if (albuf) {
836 delete astbuf1;
837 if (astbuf2 != NULL)
838 delete astbuf2;
839 free_attr(albuf);
840 }
841 albuf = $1;
842 astbuf1 = $2;
843 astbuf2 = $3;
844 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
845 if (astbuf2) {
846 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions (task/function arguments)");
847 } else {
848 astbuf2 = new AstNode(AST_RANGE);
849 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
850 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
851 }
852 }
853 if (astbuf2 && astbuf2->children.size() != 2)
854 frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
855 } wire_name | wire_name;
856
857 task_func_body:
858 task_func_body behavioral_stmt |
859 /* empty */;
860
861 /*************************** specify parser ***************************/
862
863 specify_block:
864 TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
865
866 specify_item_list:
867 specify_item specify_item_list |
868 /* empty */;
869
870 specify_item:
871 specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
872 AstNode *en_expr = $1;
873 char specify_edge = $3;
874 AstNode *src_expr = $4;
875 string *oper = $5;
876 specify_target *target = $6;
877 specify_rise_fall *timing = $9;
878
879 if (specify_edge != 0 && target->dat == nullptr)
880 frontend_verilog_yyerror("Found specify edge but no data spec.\n");
881
882 AstNode *cell = new AstNode(AST_CELL);
883 ast_stack.back()->children.push_back(cell);
884 cell->str = stringf("$specify$%d", autoidx++);
885 cell->children.push_back(new AstNode(AST_CELLTYPE));
886 cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
887
888 char oper_polarity = 0;
889 char oper_type = oper->at(0);
890
891 if (oper->size() == 3) {
892 oper_polarity = oper->at(0);
893 oper_type = oper->at(1);
894 }
895
896 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
897 cell->children.back()->str = "\\FULL";
898
899 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
900 cell->children.back()->str = "\\SRC_DST_PEN";
901
902 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
903 cell->children.back()->str = "\\SRC_DST_POL";
904
905 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
906 cell->children.back()->str = "\\T_RISE_MIN";
907
908 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
909 cell->children.back()->str = "\\T_RISE_TYP";
910
911 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
912 cell->children.back()->str = "\\T_RISE_MAX";
913
914 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
915 cell->children.back()->str = "\\T_FALL_MIN";
916
917 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
918 cell->children.back()->str = "\\T_FALL_TYP";
919
920 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
921 cell->children.back()->str = "\\T_FALL_MAX";
922
923 cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
924 cell->children.back()->str = "\\EN";
925
926 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
927 cell->children.back()->str = "\\SRC";
928
929 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
930 cell->children.back()->str = "\\DST";
931
932 if (target->dat)
933 {
934 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
935 cell->children.back()->str = "\\EDGE_EN";
936
937 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
938 cell->children.back()->str = "\\EDGE_POL";
939
940 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
941 cell->children.back()->str = "\\DAT_DST_PEN";
942
943 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
944 cell->children.back()->str = "\\DAT_DST_POL";
945
946 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
947 cell->children.back()->str = "\\DAT";
948 }
949
950 delete oper;
951 delete target;
952 delete timing;
953 } |
954 TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' specify_triple specify_opt_triple ')' ';' {
955 if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
956 *$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
957 frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
958
959 AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
960 AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
961 AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
962
963 AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
964 AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
965 AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
966
967 specify_triple *limit = $11;
968 specify_triple *limit2 = $12;
969
970 AstNode *cell = new AstNode(AST_CELL);
971 ast_stack.back()->children.push_back(cell);
972 cell->str = stringf("$specify$%d", autoidx++);
973 cell->children.push_back(new AstNode(AST_CELLTYPE));
974 cell->children.back()->str = "$specrule";
975
976 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
977 cell->children.back()->str = "\\TYPE";
978
979 cell->children.push_back(new AstNode(AST_PARASET, limit->t_min));
980 cell->children.back()->str = "\\T_LIMIT_MIN";
981
982 cell->children.push_back(new AstNode(AST_PARASET, limit->t_avg));
983 cell->children.back()->str = "\\T_LIMIT_TYP";
984
985 cell->children.push_back(new AstNode(AST_PARASET, limit->t_max));
986 cell->children.back()->str = "\\T_LIMIT_MAX";
987
988 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_min : AstNode::mkconst_int(0, true)));
989 cell->children.back()->str = "\\T_LIMIT2_MIN";
990
991 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_avg : AstNode::mkconst_int(0, true)));
992 cell->children.back()->str = "\\T_LIMIT2_TYP";
993
994 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_max : AstNode::mkconst_int(0, true)));
995 cell->children.back()->str = "\\T_LIMIT2_MAX";
996
997 cell->children.push_back(new AstNode(AST_PARASET, src_pen));
998 cell->children.back()->str = "\\SRC_PEN";
999
1000 cell->children.push_back(new AstNode(AST_PARASET, src_pol));
1001 cell->children.back()->str = "\\SRC_POL";
1002
1003 cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
1004 cell->children.back()->str = "\\DST_PEN";
1005
1006 cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
1007 cell->children.back()->str = "\\DST_POL";
1008
1009 cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
1010 cell->children.back()->str = "\\SRC_EN";
1011
1012 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
1013 cell->children.back()->str = "\\SRC";
1014
1015 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
1016 cell->children.back()->str = "\\DST_EN";
1017
1018 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
1019 cell->children.back()->str = "\\DST";
1020
1021 delete $1;
1022 };
1023
1024 specify_opt_triple:
1025 ',' specify_triple {
1026 $$ = $2;
1027 } |
1028 /* empty */ {
1029 $$ = nullptr;
1030 };
1031
1032 specify_if:
1033 TOK_IF '(' expr ')' {
1034 $$ = $3;
1035 } |
1036 /* empty */ {
1037 $$ = nullptr;
1038 };
1039
1040 specify_condition:
1041 TOK_SPECIFY_AND expr {
1042 $$ = $2;
1043 } |
1044 /* empty */ {
1045 $$ = nullptr;
1046 };
1047
1048 specify_target:
1049 expr {
1050 $$ = new specify_target;
1051 $$->polarity_op = 0;
1052 $$->dst = $1;
1053 $$->dat = nullptr;
1054 } |
1055 '(' expr ':' expr ')'{
1056 $$ = new specify_target;
1057 $$->polarity_op = 0;
1058 $$->dst = $2;
1059 $$->dat = $4;
1060 } |
1061 '(' expr TOK_NEG_INDEXED expr ')'{
1062 $$ = new specify_target;
1063 $$->polarity_op = '-';
1064 $$->dst = $2;
1065 $$->dat = $4;
1066 } |
1067 '(' expr TOK_POS_INDEXED expr ')'{
1068 $$ = new specify_target;
1069 $$->polarity_op = '+';
1070 $$->dst = $2;
1071 $$->dat = $4;
1072 };
1073
1074 specify_edge:
1075 TOK_POSEDGE { $$ = 'p'; } |
1076 TOK_NEGEDGE { $$ = 'n'; } |
1077 { $$ = 0; };
1078
1079 specify_rise_fall:
1080 specify_triple {
1081 $$ = new specify_rise_fall;
1082 $$->rise = *$1;
1083 $$->fall.t_min = $1->t_min->clone();
1084 $$->fall.t_avg = $1->t_avg->clone();
1085 $$->fall.t_max = $1->t_max->clone();
1086 delete $1;
1087 } |
1088 '(' specify_triple ',' specify_triple ')' {
1089 $$ = new specify_rise_fall;
1090 $$->rise = *$2;
1091 $$->fall = *$4;
1092 delete $2;
1093 delete $4;
1094 } |
1095 '(' specify_triple ',' specify_triple ',' specify_triple ')' {
1096 $$ = new specify_rise_fall;
1097 $$->rise = *$2;
1098 $$->fall = *$4;
1099 delete $2;
1100 delete $4;
1101 delete $6;
1102 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1103 } |
1104 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1105 $$ = new specify_rise_fall;
1106 $$->rise = *$2;
1107 $$->fall = *$4;
1108 delete $2;
1109 delete $4;
1110 delete $6;
1111 delete $8;
1112 delete $10;
1113 delete $12;
1114 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1115 } |
1116 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1117 $$ = new specify_rise_fall;
1118 $$->rise = *$2;
1119 $$->fall = *$4;
1120 delete $2;
1121 delete $4;
1122 delete $6;
1123 delete $8;
1124 delete $10;
1125 delete $12;
1126 delete $14;
1127 delete $16;
1128 delete $18;
1129 delete $20;
1130 delete $22;
1131 delete $24;
1132 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1133 }
1134
1135 specify_triple:
1136 expr {
1137 $$ = new specify_triple;
1138 $$->t_min = $1;
1139 $$->t_avg = $1->clone();
1140 $$->t_max = $1->clone();
1141 } |
1142 expr ':' expr ':' expr {
1143 $$ = new specify_triple;
1144 $$->t_min = $1;
1145 $$->t_avg = $3;
1146 $$->t_max = $5;
1147 };
1148
1149 /******************** ignored specify parser **************************/
1150
1151 ignored_specify_block:
1152 TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
1153 TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
1154
1155 ignored_specify_item_opt:
1156 ignored_specify_item_opt ignored_specify_item |
1157 ignored_specify_item ;
1158
1159 ignored_specify_item:
1160 specparam_declaration
1161 // | pulsestyle_declaration
1162 // | showcancelled_declaration
1163 | path_declaration
1164 | system_timing_declaration
1165 ;
1166
1167 specparam_declaration:
1168 TOK_SPECPARAM list_of_specparam_assignments ';' |
1169 TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ;
1170
1171 // IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match
1172 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
1173 // exxxxtending this for SV specparam would change this anyhow
1174 specparam_range:
1175 '[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
1176
1177 list_of_specparam_assignments:
1178 specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
1179
1180 specparam_assignment:
1181 ignspec_id '=' ignspec_expr ;
1182
1183 ignspec_opt_cond:
1184 TOK_IF '(' ignspec_expr ')' | /* empty */;
1185
1186 path_declaration :
1187 simple_path_declaration ';'
1188 // | edge_sensitive_path_declaration
1189 // | state_dependent_path_declaration
1190 ;
1191
1192 simple_path_declaration :
1193 ignspec_opt_cond parallel_path_description '=' path_delay_value |
1194 ignspec_opt_cond full_path_description '=' path_delay_value
1195 ;
1196
1197 path_delay_value :
1198 '(' ignspec_expr list_of_path_delay_extra_expressions ')'
1199 | ignspec_expr
1200 | ignspec_expr list_of_path_delay_extra_expressions
1201 ;
1202
1203 list_of_path_delay_extra_expressions :
1204 ',' ignspec_expr
1205 | ',' ignspec_expr list_of_path_delay_extra_expressions
1206 ;
1207
1208 specify_edge_identifier :
1209 TOK_POSEDGE | TOK_NEGEDGE ;
1210
1211 parallel_path_description :
1212 '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
1213 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
1214 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
1215
1216 full_path_description :
1217 '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
1218 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
1219 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
1220
1221 // This was broken into 2 rules to solve shift/reduce conflicts
1222 list_of_path_inputs :
1223 specify_input_terminal_descriptor opt_polarity_operator |
1224 specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
1225
1226 more_path_inputs :
1227 ',' specify_input_terminal_descriptor |
1228 more_path_inputs ',' specify_input_terminal_descriptor ;
1229
1230 list_of_path_outputs :
1231 specify_output_terminal_descriptor |
1232 list_of_path_outputs ',' specify_output_terminal_descriptor ;
1233
1234 opt_polarity_operator :
1235 '+'
1236 | '-'
1237 | ;
1238
1239 // Good enough for the time being
1240 specify_input_terminal_descriptor :
1241 ignspec_id ;
1242
1243 // Good enough for the time being
1244 specify_output_terminal_descriptor :
1245 ignspec_id ;
1246
1247 system_timing_declaration :
1248 ignspec_id '(' system_timing_args ')' ';' ;
1249
1250 system_timing_arg :
1251 TOK_POSEDGE ignspec_id |
1252 TOK_NEGEDGE ignspec_id |
1253 ignspec_expr ;
1254
1255 system_timing_args :
1256 system_timing_arg |
1257 system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
1258 system_timing_args ',' system_timing_arg ;
1259
1260 // for the time being this is OK, but we may write our own expr here.
1261 // as I'm not sure it is legal to use a full expr here (probably not)
1262 // On the other hand, other rules requiring constant expressions also use 'expr'
1263 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
1264 ignspec_constant_expression:
1265 expr { delete $1; };
1266
1267 ignspec_expr:
1268 expr { delete $1; } |
1269 expr ':' expr ':' expr {
1270 delete $1;
1271 delete $3;
1272 delete $5;
1273 };
1274
1275 ignspec_id:
1276 TOK_ID { delete $1; }
1277 range_or_multirange { delete $3; };
1278
1279 /**********************************************************************/
1280
1281 param_signed:
1282 TOK_SIGNED {
1283 astbuf1->is_signed = true;
1284 } | /* empty */;
1285
1286 param_integer:
1287 TOK_INTEGER {
1288 if (astbuf1->children.size() != 1)
1289 frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
1290 astbuf1->children.push_back(new AstNode(AST_RANGE));
1291 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
1292 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
1293 astbuf1->is_signed = true;
1294 } | /* empty */;
1295
1296 param_real:
1297 TOK_REAL {
1298 if (astbuf1->children.size() != 1)
1299 frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
1300 astbuf1->children.push_back(new AstNode(AST_REALVALUE));
1301 } | /* empty */;
1302
1303 param_range:
1304 range {
1305 if ($1 != NULL) {
1306 if (astbuf1->children.size() != 1)
1307 frontend_verilog_yyerror("integer/real parameters should not have a range.");
1308 astbuf1->children.push_back($1);
1309 }
1310 };
1311
1312 param_type:
1313 param_signed param_integer param_real param_range |
1314 hierarchical_type_id {
1315 astbuf1->is_custom_type = true;
1316 astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
1317 astbuf1->children.back()->str = *$1;
1318 };
1319
1320 param_decl:
1321 attr TOK_PARAMETER {
1322 astbuf1 = new AstNode(AST_PARAMETER);
1323 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1324 append_attr(astbuf1, $1);
1325 } param_type param_decl_list ';' {
1326 delete astbuf1;
1327 };
1328
1329 localparam_decl:
1330 attr TOK_LOCALPARAM {
1331 astbuf1 = new AstNode(AST_LOCALPARAM);
1332 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1333 append_attr(astbuf1, $1);
1334 } param_type param_decl_list ';' {
1335 delete astbuf1;
1336 };
1337
1338 param_decl_list:
1339 single_param_decl | param_decl_list ',' single_param_decl;
1340
1341 single_param_decl:
1342 TOK_ID '=' expr {
1343 AstNode *node;
1344 if (astbuf1 == nullptr) {
1345 if (!sv_mode)
1346 frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword");
1347 node = new AstNode(AST_PARAMETER);
1348 node->children.push_back(AstNode::mkconst_int(0, true));
1349 } else {
1350 node = astbuf1->clone();
1351 }
1352 node->str = *$1;
1353 delete node->children[0];
1354 node->children[0] = $3;
1355 ast_stack.back()->children.push_back(node);
1356 delete $1;
1357 };
1358
1359 defparam_decl:
1360 TOK_DEFPARAM defparam_decl_list ';';
1361
1362 defparam_decl_list:
1363 single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
1364
1365 single_defparam_decl:
1366 range rvalue '=' expr {
1367 AstNode *node = new AstNode(AST_DEFPARAM);
1368 node->children.push_back($2);
1369 node->children.push_back($4);
1370 if ($1 != NULL)
1371 node->children.push_back($1);
1372 ast_stack.back()->children.push_back(node);
1373 };
1374
1375 enum_type: TOK_ENUM {
1376 static int enum_count;
1377 // create parent node for the enum
1378 astbuf2 = new AstNode(AST_ENUM);
1379 ast_stack.back()->children.push_back(astbuf2);
1380 astbuf2->str = std::string("$enum");
1381 astbuf2->str += std::to_string(enum_count++);
1382 // create the template for the names
1383 astbuf1 = new AstNode(AST_ENUM_ITEM);
1384 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1385 } param_signed enum_base_type '{' enum_name_list '}' { // create template for the enum vars
1386 auto tnode = astbuf1->clone();
1387 delete astbuf1;
1388 astbuf1 = tnode;
1389 tnode->type = AST_WIRE;
1390 tnode->attributes["\\enum_type"] = AstNode::mkconst_str(astbuf2->str);
1391 // drop constant but keep any range
1392 delete tnode->children[0];
1393 tnode->children.erase(tnode->children.begin()); }
1394 ;
1395
1396 enum_base_type: int_vec param_range
1397 | int_atom
1398 | /* nothing */ {astbuf1->is_reg = true; addRange(astbuf1); }
1399 ;
1400
1401 int_atom: TOK_INTEGER {astbuf1->is_reg=true; addRange(astbuf1); } // probably should do byte, range [7:0] here
1402 ;
1403
1404 int_vec: TOK_REG {astbuf1->is_reg = true;}
1405 | TOK_LOGIC {astbuf1->is_logic = true;}
1406 ;
1407
1408 enum_name_list:
1409 enum_name_decl
1410 | enum_name_list ',' enum_name_decl
1411 ;
1412
1413 enum_name_decl:
1414 TOK_ID opt_enum_init {
1415 // put in fn
1416 log_assert(astbuf1);
1417 log_assert(astbuf2);
1418 auto node = astbuf1->clone();
1419 node->str = *$1;
1420 delete $1;
1421 delete node->children[0];
1422 node->children[0] = $2 ?: new AstNode(AST_NONE);
1423 astbuf2->children.push_back(node);
1424 }
1425 ;
1426
1427 opt_enum_init:
1428 '=' basic_expr { $$ = $2; } // TODO: restrict this
1429 | /* optional */ { $$ = NULL; }
1430 ;
1431
1432 enum_var_list:
1433 enum_var
1434 | enum_var_list ',' enum_var
1435 ;
1436
1437 enum_var: TOK_ID {
1438 log_assert(astbuf1);
1439 log_assert(astbuf2);
1440 auto node = astbuf1->clone();
1441 ast_stack.back()->children.push_back(node);
1442 node->str = *$1;
1443 delete $1;
1444 node->is_enum = true;
1445 }
1446 ;
1447
1448 enum_decl: enum_type enum_var_list ';' {
1449 //enum_type creates astbuf1 for use by typedef only
1450 delete astbuf1;
1451 }
1452 ;
1453
1454 wire_decl:
1455 attr wire_type range {
1456 albuf = $1;
1457 astbuf1 = $2;
1458 astbuf2 = $3;
1459 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
1460 if (astbuf2) {
1461 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
1462 } else {
1463 astbuf2 = new AstNode(AST_RANGE);
1464 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
1465 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
1466 }
1467 }
1468 if (astbuf2 && astbuf2->children.size() != 2)
1469 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
1470 } delay wire_name_list {
1471 delete astbuf1;
1472 if (astbuf2 != NULL)
1473 delete astbuf2;
1474 free_attr(albuf);
1475 } ';' |
1476 attr TOK_SUPPLY0 TOK_ID {
1477 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1478 ast_stack.back()->children.back()->str = *$3;
1479 append_attr(ast_stack.back()->children.back(), $1);
1480 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
1481 ast_stack.back()->children.back()->children[0]->str = *$3;
1482 delete $3;
1483 } opt_supply_wires ';' |
1484 attr TOK_SUPPLY1 TOK_ID {
1485 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1486 ast_stack.back()->children.back()->str = *$3;
1487 append_attr(ast_stack.back()->children.back(), $1);
1488 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
1489 ast_stack.back()->children.back()->children[0]->str = *$3;
1490 delete $3;
1491 } opt_supply_wires ';';
1492
1493 opt_supply_wires:
1494 /* empty */ |
1495 opt_supply_wires ',' TOK_ID {
1496 AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
1497 AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
1498 wire_node->str = *$3;
1499 assign_node->children[0]->str = *$3;
1500 ast_stack.back()->children.push_back(wire_node);
1501 ast_stack.back()->children.push_back(assign_node);
1502 delete $3;
1503 };
1504
1505 wire_name_list:
1506 wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
1507
1508 wire_name_and_opt_assign:
1509 wire_name {
1510 bool attr_anyconst = false;
1511 bool attr_anyseq = false;
1512 bool attr_allconst = false;
1513 bool attr_allseq = false;
1514 if (ast_stack.back()->children.back()->get_bool_attribute("\\anyconst")) {
1515 delete ast_stack.back()->children.back()->attributes.at("\\anyconst");
1516 ast_stack.back()->children.back()->attributes.erase("\\anyconst");
1517 attr_anyconst = true;
1518 }
1519 if (ast_stack.back()->children.back()->get_bool_attribute("\\anyseq")) {
1520 delete ast_stack.back()->children.back()->attributes.at("\\anyseq");
1521 ast_stack.back()->children.back()->attributes.erase("\\anyseq");
1522 attr_anyseq = true;
1523 }
1524 if (ast_stack.back()->children.back()->get_bool_attribute("\\allconst")) {
1525 delete ast_stack.back()->children.back()->attributes.at("\\allconst");
1526 ast_stack.back()->children.back()->attributes.erase("\\allconst");
1527 attr_allconst = true;
1528 }
1529 if (ast_stack.back()->children.back()->get_bool_attribute("\\allseq")) {
1530 delete ast_stack.back()->children.back()->attributes.at("\\allseq");
1531 ast_stack.back()->children.back()->attributes.erase("\\allseq");
1532 attr_allseq = true;
1533 }
1534 if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
1535 AstNode *wire = new AstNode(AST_IDENTIFIER);
1536 AstNode *fcall = new AstNode(AST_FCALL);
1537 wire->str = ast_stack.back()->children.back()->str;
1538 fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
1539 if (attr_anyconst)
1540 fcall->str = "\\$anyconst";
1541 if (attr_anyseq)
1542 fcall->str = "\\$anyseq";
1543 if (attr_allconst)
1544 fcall->str = "\\$allconst";
1545 if (attr_allseq)
1546 fcall->str = "\\$allseq";
1547 fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
1548 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
1549 }
1550 } |
1551 wire_name '=' expr {
1552 AstNode *wire = new AstNode(AST_IDENTIFIER);
1553 wire->str = ast_stack.back()->children.back()->str;
1554 if (astbuf1->is_input) {
1555 if (astbuf1->attributes.count("\\defaultvalue"))
1556 delete astbuf1->attributes.at("\\defaultvalue");
1557 astbuf1->attributes["\\defaultvalue"] = $3;
1558 }
1559 else if (astbuf1->is_reg || astbuf1->is_logic){
1560 AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
1561 AstNode *block = new AstNode(AST_BLOCK, assign);
1562 AstNode *init = new AstNode(AST_INITIAL, block);
1563
1564 SET_AST_NODE_LOC(assign, @1, @3);
1565 SET_AST_NODE_LOC(block, @1, @3);
1566 SET_AST_NODE_LOC(init, @1, @3);
1567
1568 ast_stack.back()->children.push_back(init);
1569 }
1570 else {
1571 AstNode *assign = new AstNode(AST_ASSIGN, wire, $3);
1572 SET_AST_NODE_LOC(assign, @1, @3);
1573 ast_stack.back()->children.push_back(assign);
1574 }
1575
1576 };
1577
1578 wire_name:
1579 TOK_ID range_or_multirange {
1580 if (astbuf1 == nullptr)
1581 frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node.");
1582 AstNode *node = astbuf1->clone();
1583 node->str = *$1;
1584 append_attr_clone(node, albuf);
1585 if (astbuf2 != NULL)
1586 node->children.push_back(astbuf2->clone());
1587 if ($2 != NULL) {
1588 if (node->is_input || node->is_output)
1589 frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
1590 if (!astbuf2 && !node->is_custom_type) {
1591 AstNode *rng = new AstNode(AST_RANGE);
1592 rng->children.push_back(AstNode::mkconst_int(0, true));
1593 rng->children.push_back(AstNode::mkconst_int(0, true));
1594 node->children.push_back(rng);
1595 }
1596 node->type = AST_MEMORY;
1597 auto *rangeNode = $2;
1598 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
1599 // SV array size [n], rewrite as [n-1:0]
1600 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
1601 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
1602 }
1603 node->children.push_back(rangeNode);
1604 }
1605 if (current_function_or_task == NULL) {
1606 if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
1607 port_stubs[*$1] = ++port_counter;
1608 }
1609 if (port_stubs.count(*$1) != 0) {
1610 if (!node->is_input && !node->is_output)
1611 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
1612 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
1613 frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
1614 node->port_id = port_stubs[*$1];
1615 port_stubs.erase(*$1);
1616 } else {
1617 if (node->is_input || node->is_output)
1618 frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
1619 }
1620 } else {
1621 if (node->is_input || node->is_output)
1622 node->port_id = current_function_or_task_port_id++;
1623 }
1624 //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
1625 SET_AST_NODE_LOC(node, @1, @1);
1626 ast_stack.back()->children.push_back(node);
1627
1628 delete $1;
1629 };
1630
1631 assign_stmt:
1632 TOK_ASSIGN delay assign_expr_list ';';
1633
1634 assign_expr_list:
1635 assign_expr | assign_expr_list ',' assign_expr;
1636
1637 assign_expr:
1638 lvalue '=' expr {
1639 AstNode *node = new AstNode(AST_ASSIGN, $1, $3);
1640 SET_AST_NODE_LOC(node, @$, @$);
1641 ast_stack.back()->children.push_back(node);
1642 };
1643
1644 type_name: TOK_ID // first time seen
1645 | TOK_USER_TYPE { if (isInLocalScope($1)) frontend_verilog_yyerror("Duplicate declaration of TYPEDEF '%s'", $1->c_str()+1); }
1646 ;
1647
1648 typedef_decl:
1649 TOK_TYPEDEF wire_type range type_name range_or_multirange ';' {
1650 astbuf1 = $2;
1651 astbuf2 = $3;
1652 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
1653 if (astbuf2) {
1654 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
1655 } else {
1656 astbuf2 = new AstNode(AST_RANGE);
1657 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
1658 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
1659 }
1660 }
1661 if (astbuf2 && astbuf2->children.size() != 2)
1662 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
1663 if (astbuf2)
1664 astbuf1->children.push_back(astbuf2);
1665
1666 if ($5 != NULL) {
1667 if (!astbuf2) {
1668 AstNode *rng = new AstNode(AST_RANGE);
1669 rng->children.push_back(AstNode::mkconst_int(0, true));
1670 rng->children.push_back(AstNode::mkconst_int(0, true));
1671 astbuf1->children.push_back(rng);
1672 }
1673 astbuf1->type = AST_MEMORY;
1674 auto *rangeNode = $5;
1675 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
1676 // SV array size [n], rewrite as [n-1:0]
1677 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
1678 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
1679 }
1680 astbuf1->children.push_back(rangeNode);
1681 }
1682 addTypedefNode($4, astbuf1);
1683 } |
1684 TOK_TYPEDEF enum_type type_name ';' {
1685 addTypedefNode($3, astbuf1);
1686 }
1687 ;
1688
1689 cell_stmt:
1690 attr TOK_ID {
1691 astbuf1 = new AstNode(AST_CELL);
1692 append_attr(astbuf1, $1);
1693 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
1694 astbuf1->children[0]->str = *$2;
1695 delete $2;
1696 } cell_parameter_list_opt cell_list ';' {
1697 delete astbuf1;
1698 } |
1699 attr tok_prim_wrapper delay {
1700 astbuf1 = new AstNode(AST_PRIMITIVE);
1701 astbuf1->str = *$2;
1702 append_attr(astbuf1, $1);
1703 delete $2;
1704 } prim_list ';' {
1705 delete astbuf1;
1706 };
1707
1708 tok_prim_wrapper:
1709 TOK_PRIMITIVE {
1710 $$ = $1;
1711 } |
1712 TOK_OR {
1713 $$ = new std::string("or");
1714 };
1715
1716 cell_list:
1717 single_cell |
1718 cell_list ',' single_cell;
1719
1720 single_cell:
1721 TOK_ID {
1722 astbuf2 = astbuf1->clone();
1723 if (astbuf2->type != AST_PRIMITIVE)
1724 astbuf2->str = *$1;
1725 delete $1;
1726 ast_stack.back()->children.push_back(astbuf2);
1727 } '(' cell_port_list ')' {
1728 SET_AST_NODE_LOC(astbuf2, @1, @$);
1729 } |
1730 TOK_ID non_opt_range {
1731 astbuf2 = astbuf1->clone();
1732 if (astbuf2->type != AST_PRIMITIVE)
1733 astbuf2->str = *$1;
1734 delete $1;
1735 ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
1736 } '(' cell_port_list ')'{
1737 SET_AST_NODE_LOC(astbuf2, @1, @$);
1738 SET_AST_NODE_LOC(astbuf3, @1, @$);
1739 };
1740
1741 prim_list:
1742 single_prim |
1743 prim_list ',' single_prim;
1744
1745 single_prim:
1746 single_cell |
1747 /* no name */ {
1748 astbuf2 = astbuf1->clone();
1749 ast_stack.back()->children.push_back(astbuf2);
1750 } '(' cell_port_list ')';
1751
1752 cell_parameter_list_opt:
1753 '#' '(' cell_parameter_list ')' | /* empty */;
1754
1755 cell_parameter_list:
1756 cell_parameter | cell_parameter_list ',' cell_parameter;
1757
1758 cell_parameter:
1759 /* empty */ |
1760 expr {
1761 AstNode *node = new AstNode(AST_PARASET);
1762 astbuf1->children.push_back(node);
1763 node->children.push_back($1);
1764 } |
1765 '.' TOK_ID '(' expr ')' {
1766 AstNode *node = new AstNode(AST_PARASET);
1767 node->str = *$2;
1768 astbuf1->children.push_back(node);
1769 node->children.push_back($4);
1770 delete $2;
1771 };
1772
1773 cell_port_list:
1774 cell_port_list_rules {
1775 // remove empty args from end of list
1776 while (!astbuf2->children.empty()) {
1777 AstNode *node = astbuf2->children.back();
1778 if (node->type != AST_ARGUMENT) break;
1779 if (!node->children.empty()) break;
1780 if (!node->str.empty()) break;
1781 astbuf2->children.pop_back();
1782 delete node;
1783 }
1784
1785 // check port types
1786 bool has_positional_args = false;
1787 bool has_named_args = false;
1788 for (auto node : astbuf2->children) {
1789 if (node->type != AST_ARGUMENT) continue;
1790 if (node->str.empty())
1791 has_positional_args = true;
1792 else
1793 has_named_args = true;
1794 }
1795
1796 if (has_positional_args && has_named_args)
1797 frontend_verilog_yyerror("Mix of positional and named cell ports.");
1798 };
1799
1800 cell_port_list_rules:
1801 cell_port | cell_port_list_rules ',' cell_port;
1802
1803 cell_port:
1804 attr {
1805 AstNode *node = new AstNode(AST_ARGUMENT);
1806 astbuf2->children.push_back(node);
1807 free_attr($1);
1808 } |
1809 attr expr {
1810 AstNode *node = new AstNode(AST_ARGUMENT);
1811 astbuf2->children.push_back(node);
1812 node->children.push_back($2);
1813 free_attr($1);
1814 } |
1815 attr '.' TOK_ID '(' expr ')' {
1816 AstNode *node = new AstNode(AST_ARGUMENT);
1817 node->str = *$3;
1818 astbuf2->children.push_back(node);
1819 node->children.push_back($5);
1820 delete $3;
1821 free_attr($1);
1822 } |
1823 attr '.' TOK_ID '(' ')' {
1824 AstNode *node = new AstNode(AST_ARGUMENT);
1825 node->str = *$3;
1826 astbuf2->children.push_back(node);
1827 delete $3;
1828 free_attr($1);
1829 } |
1830 attr '.' TOK_ID {
1831 AstNode *node = new AstNode(AST_ARGUMENT);
1832 node->str = *$3;
1833 astbuf2->children.push_back(node);
1834 node->children.push_back(new AstNode(AST_IDENTIFIER));
1835 node->children.back()->str = *$3;
1836 delete $3;
1837 free_attr($1);
1838 } |
1839 attr TOK_WILDCARD_CONNECT {
1840 if (!sv_mode)
1841 frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
1842 astbuf2->attributes[ID(wildcard_port_conns)] = AstNode::mkconst_int(1, false);
1843 };
1844
1845 always_comb_or_latch:
1846 TOK_ALWAYS_COMB {
1847 $$ = false;
1848 } |
1849 TOK_ALWAYS_LATCH {
1850 $$ = true;
1851 };
1852
1853 always_or_always_ff:
1854 TOK_ALWAYS {
1855 $$ = false;
1856 } |
1857 TOK_ALWAYS_FF {
1858 $$ = true;
1859 };
1860
1861 always_stmt:
1862 attr always_or_always_ff {
1863 AstNode *node = new AstNode(AST_ALWAYS);
1864 append_attr(node, $1);
1865 if ($2)
1866 node->attributes[ID(always_ff)] = AstNode::mkconst_int(1, false);
1867 ast_stack.back()->children.push_back(node);
1868 ast_stack.push_back(node);
1869 } always_cond {
1870 AstNode *block = new AstNode(AST_BLOCK);
1871 ast_stack.back()->children.push_back(block);
1872 ast_stack.push_back(block);
1873 } behavioral_stmt {
1874 SET_AST_NODE_LOC(ast_stack.back(), @6, @6);
1875 ast_stack.pop_back();
1876
1877 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
1878 ast_stack.pop_back();
1879
1880 SET_RULE_LOC(@$, @2, @$);
1881 } |
1882 attr always_comb_or_latch {
1883 AstNode *node = new AstNode(AST_ALWAYS);
1884 append_attr(node, $1);
1885 if ($2)
1886 node->attributes[ID(always_latch)] = AstNode::mkconst_int(1, false);
1887 else
1888 node->attributes[ID(always_comb)] = AstNode::mkconst_int(1, false);
1889 ast_stack.back()->children.push_back(node);
1890 ast_stack.push_back(node);
1891 AstNode *block = new AstNode(AST_BLOCK);
1892 ast_stack.back()->children.push_back(block);
1893 ast_stack.push_back(block);
1894 } behavioral_stmt {
1895 ast_stack.pop_back();
1896 ast_stack.pop_back();
1897 } |
1898 attr TOK_INITIAL {
1899 AstNode *node = new AstNode(AST_INITIAL);
1900 append_attr(node, $1);
1901 ast_stack.back()->children.push_back(node);
1902 ast_stack.push_back(node);
1903 AstNode *block = new AstNode(AST_BLOCK);
1904 ast_stack.back()->children.push_back(block);
1905 ast_stack.push_back(block);
1906 } behavioral_stmt {
1907 ast_stack.pop_back();
1908 ast_stack.pop_back();
1909 };
1910
1911 always_cond:
1912 '@' '(' always_events ')' |
1913 '@' '(' '*' ')' |
1914 '@' ATTR_BEGIN ')' |
1915 '@' '(' ATTR_END |
1916 '@' '*' |
1917 /* empty */;
1918
1919 always_events:
1920 always_event |
1921 always_events TOK_OR always_event |
1922 always_events ',' always_event;
1923
1924 always_event:
1925 TOK_POSEDGE expr {
1926 AstNode *node = new AstNode(AST_POSEDGE);
1927 ast_stack.back()->children.push_back(node);
1928 node->children.push_back($2);
1929 } |
1930 TOK_NEGEDGE expr {
1931 AstNode *node = new AstNode(AST_NEGEDGE);
1932 ast_stack.back()->children.push_back(node);
1933 node->children.push_back($2);
1934 } |
1935 expr {
1936 AstNode *node = new AstNode(AST_EDGE);
1937 ast_stack.back()->children.push_back(node);
1938 node->children.push_back($1);
1939 };
1940
1941 opt_label:
1942 ':' TOK_ID {
1943 $$ = $2;
1944 } |
1945 /* empty */ {
1946 $$ = NULL;
1947 };
1948
1949 opt_sva_label:
1950 TOK_SVA_LABEL ':' {
1951 $$ = $1;
1952 } |
1953 /* empty */ {
1954 $$ = NULL;
1955 };
1956
1957 opt_property:
1958 TOK_PROPERTY {
1959 $$ = true;
1960 } |
1961 TOK_FINAL {
1962 $$ = false;
1963 } |
1964 /* empty */ {
1965 $$ = false;
1966 };
1967
1968 modport_stmt:
1969 TOK_MODPORT TOK_ID {
1970 AstNode *modport = new AstNode(AST_MODPORT);
1971 ast_stack.back()->children.push_back(modport);
1972 ast_stack.push_back(modport);
1973 modport->str = *$2;
1974 delete $2;
1975 } modport_args_opt {
1976 ast_stack.pop_back();
1977 log_assert(ast_stack.size() == 2);
1978 } ';'
1979
1980 modport_args_opt:
1981 '(' ')' | '(' modport_args optional_comma ')';
1982
1983 modport_args:
1984 modport_arg | modport_args ',' modport_arg;
1985
1986 modport_arg:
1987 modport_type_token modport_member |
1988 modport_member
1989
1990 modport_member:
1991 TOK_ID {
1992 AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
1993 ast_stack.back()->children.push_back(modport_member);
1994 modport_member->str = *$1;
1995 modport_member->is_input = current_modport_input;
1996 modport_member->is_output = current_modport_output;
1997 delete $1;
1998 }
1999
2000 modport_type_token:
2001 TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
2002
2003 assert:
2004 opt_sva_label TOK_ASSERT opt_property '(' expr ')' ';' {
2005 if (noassert_mode) {
2006 delete $5;
2007 } else {
2008 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2009 SET_AST_NODE_LOC(node, @1, @6);
2010 if ($1 != nullptr)
2011 node->str = *$1;
2012 ast_stack.back()->children.push_back(node);
2013 }
2014 if ($1 != nullptr)
2015 delete $1;
2016 } |
2017 opt_sva_label TOK_ASSUME opt_property '(' expr ')' ';' {
2018 if (noassume_mode) {
2019 delete $5;
2020 } else {
2021 AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
2022 SET_AST_NODE_LOC(node, @1, @6);
2023 if ($1 != nullptr)
2024 node->str = *$1;
2025 ast_stack.back()->children.push_back(node);
2026 }
2027 if ($1 != nullptr)
2028 delete $1;
2029 } |
2030 opt_sva_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2031 if (noassert_mode) {
2032 delete $6;
2033 } else {
2034 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2035 SET_AST_NODE_LOC(node, @1, @7);
2036 if ($1 != nullptr)
2037 node->str = *$1;
2038 ast_stack.back()->children.push_back(node);
2039 }
2040 if ($1 != nullptr)
2041 delete $1;
2042 } |
2043 opt_sva_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2044 if (noassume_mode) {
2045 delete $6;
2046 } else {
2047 AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
2048 SET_AST_NODE_LOC(node, @1, @7);
2049 if ($1 != nullptr)
2050 node->str = *$1;
2051 ast_stack.back()->children.push_back(node);
2052 }
2053 if ($1 != nullptr)
2054 delete $1;
2055 } |
2056 opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
2057 AstNode *node = new AstNode(AST_COVER, $5);
2058 SET_AST_NODE_LOC(node, @1, @6);
2059 if ($1 != nullptr) {
2060 node->str = *$1;
2061 delete $1;
2062 }
2063 ast_stack.back()->children.push_back(node);
2064 } |
2065 opt_sva_label TOK_COVER opt_property '(' ')' ';' {
2066 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2067 SET_AST_NODE_LOC(node, @1, @5);
2068 if ($1 != nullptr) {
2069 node->str = *$1;
2070 delete $1;
2071 }
2072 ast_stack.back()->children.push_back(node);
2073 } |
2074 opt_sva_label TOK_COVER ';' {
2075 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2076 SET_AST_NODE_LOC(node, @1, @2);
2077 if ($1 != nullptr) {
2078 node->str = *$1;
2079 delete $1;
2080 }
2081 ast_stack.back()->children.push_back(node);
2082 } |
2083 opt_sva_label TOK_RESTRICT opt_property '(' expr ')' ';' {
2084 if (norestrict_mode) {
2085 delete $5;
2086 } else {
2087 AstNode *node = new AstNode(AST_ASSUME, $5);
2088 SET_AST_NODE_LOC(node, @1, @6);
2089 if ($1 != nullptr)
2090 node->str = *$1;
2091 ast_stack.back()->children.push_back(node);
2092 }
2093 if (!$3)
2094 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2095 if ($1 != nullptr)
2096 delete $1;
2097 } |
2098 opt_sva_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2099 if (norestrict_mode) {
2100 delete $6;
2101 } else {
2102 AstNode *node = new AstNode(AST_FAIR, $6);
2103 SET_AST_NODE_LOC(node, @1, @7);
2104 if ($1 != nullptr)
2105 node->str = *$1;
2106 ast_stack.back()->children.push_back(node);
2107 }
2108 if (!$3)
2109 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2110 if ($1 != nullptr)
2111 delete $1;
2112 };
2113
2114 assert_property:
2115 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
2116 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2117 SET_AST_NODE_LOC(node, @1, @6);
2118 ast_stack.back()->children.push_back(node);
2119 if ($1 != nullptr) {
2120 ast_stack.back()->children.back()->str = *$1;
2121 delete $1;
2122 }
2123 } |
2124 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
2125 AstNode *node = new AstNode(AST_ASSUME, $5);
2126 SET_AST_NODE_LOC(node, @1, @6);
2127 ast_stack.back()->children.push_back(node);
2128 if ($1 != nullptr) {
2129 ast_stack.back()->children.back()->str = *$1;
2130 delete $1;
2131 }
2132 } |
2133 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2134 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2135 SET_AST_NODE_LOC(node, @1, @7);
2136 ast_stack.back()->children.push_back(node);
2137 if ($1 != nullptr) {
2138 ast_stack.back()->children.back()->str = *$1;
2139 delete $1;
2140 }
2141 } |
2142 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2143 AstNode *node = new AstNode(AST_FAIR, $6);
2144 SET_AST_NODE_LOC(node, @1, @7);
2145 ast_stack.back()->children.push_back(node);
2146 if ($1 != nullptr) {
2147 ast_stack.back()->children.back()->str = *$1;
2148 delete $1;
2149 }
2150 } |
2151 opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
2152 AstNode *node = new AstNode(AST_COVER, $5);
2153 SET_AST_NODE_LOC(node, @1, @6);
2154 ast_stack.back()->children.push_back(node);
2155 if ($1 != nullptr) {
2156 ast_stack.back()->children.back()->str = *$1;
2157 delete $1;
2158 }
2159 } |
2160 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
2161 if (norestrict_mode) {
2162 delete $5;
2163 } else {
2164 AstNode *node = new AstNode(AST_ASSUME, $5);
2165 SET_AST_NODE_LOC(node, @1, @6);
2166 ast_stack.back()->children.push_back(node);
2167 if ($1 != nullptr) {
2168 ast_stack.back()->children.back()->str = *$1;
2169 delete $1;
2170 }
2171 }
2172 } |
2173 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2174 if (norestrict_mode) {
2175 delete $6;
2176 } else {
2177 AstNode *node = new AstNode(AST_FAIR, $6);
2178 SET_AST_NODE_LOC(node, @1, @7);
2179 ast_stack.back()->children.push_back(node);
2180 if ($1 != nullptr) {
2181 ast_stack.back()->children.back()->str = *$1;
2182 delete $1;
2183 }
2184 }
2185 };
2186
2187 simple_behavioral_stmt:
2188 lvalue '=' delay expr {
2189 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4);
2190 ast_stack.back()->children.push_back(node);
2191 SET_AST_NODE_LOC(node, @1, @4);
2192 } |
2193 lvalue TOK_INCREMENT {
2194 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true)));
2195 ast_stack.back()->children.push_back(node);
2196 SET_AST_NODE_LOC(node, @1, @2);
2197 } |
2198 lvalue TOK_DECREMENT {
2199 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true)));
2200 ast_stack.back()->children.push_back(node);
2201 SET_AST_NODE_LOC(node, @1, @2);
2202 } |
2203 lvalue OP_LE delay expr {
2204 AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4);
2205 ast_stack.back()->children.push_back(node);
2206 SET_AST_NODE_LOC(node, @1, @4);
2207 };
2208
2209 // this production creates the obligatory if-else shift/reduce conflict
2210 behavioral_stmt:
2211 defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
2212 non_opt_delay behavioral_stmt |
2213 simple_behavioral_stmt ';' | ';' |
2214 hierarchical_id attr {
2215 AstNode *node = new AstNode(AST_TCALL);
2216 node->str = *$1;
2217 delete $1;
2218 ast_stack.back()->children.push_back(node);
2219 ast_stack.push_back(node);
2220 append_attr(node, $2);
2221 } opt_arg_list ';'{
2222 ast_stack.pop_back();
2223 } |
2224 TOK_MSG_TASKS attr {
2225 AstNode *node = new AstNode(AST_TCALL);
2226 node->str = *$1;
2227 delete $1;
2228 ast_stack.back()->children.push_back(node);
2229 ast_stack.push_back(node);
2230 append_attr(node, $2);
2231 } opt_arg_list ';'{
2232 ast_stack.pop_back();
2233 } |
2234 attr TOK_BEGIN {
2235 enterTypeScope();
2236 } opt_label {
2237 AstNode *node = new AstNode(AST_BLOCK);
2238 ast_stack.back()->children.push_back(node);
2239 ast_stack.push_back(node);
2240 append_attr(node, $1);
2241 if ($4 != NULL)
2242 node->str = *$4;
2243 } behavioral_stmt_list TOK_END opt_label {
2244 exitTypeScope();
2245 if ($4 != NULL && $8 != NULL && *$4 != *$8)
2246 frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
2247 delete $4;
2248 delete $8;
2249 ast_stack.pop_back();
2250 } |
2251 attr TOK_FOR '(' {
2252 AstNode *node = new AstNode(AST_FOR);
2253 ast_stack.back()->children.push_back(node);
2254 ast_stack.push_back(node);
2255 append_attr(node, $1);
2256 } simple_behavioral_stmt ';' expr {
2257 ast_stack.back()->children.push_back($7);
2258 } ';' simple_behavioral_stmt ')' {
2259 AstNode *block = new AstNode(AST_BLOCK);
2260 ast_stack.back()->children.push_back(block);
2261 ast_stack.push_back(block);
2262 } behavioral_stmt {
2263 SET_AST_NODE_LOC(ast_stack.back(), @13, @13);
2264 ast_stack.pop_back();
2265 SET_AST_NODE_LOC(ast_stack.back(), @2, @13);
2266 ast_stack.pop_back();
2267 } |
2268 attr TOK_WHILE '(' expr ')' {
2269 AstNode *node = new AstNode(AST_WHILE);
2270 ast_stack.back()->children.push_back(node);
2271 ast_stack.push_back(node);
2272 append_attr(node, $1);
2273 AstNode *block = new AstNode(AST_BLOCK);
2274 ast_stack.back()->children.push_back($4);
2275 ast_stack.back()->children.push_back(block);
2276 ast_stack.push_back(block);
2277 } behavioral_stmt {
2278 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2279 ast_stack.pop_back();
2280 ast_stack.pop_back();
2281 } |
2282 attr TOK_REPEAT '(' expr ')' {
2283 AstNode *node = new AstNode(AST_REPEAT);
2284 ast_stack.back()->children.push_back(node);
2285 ast_stack.push_back(node);
2286 append_attr(node, $1);
2287 AstNode *block = new AstNode(AST_BLOCK);
2288 ast_stack.back()->children.push_back($4);
2289 ast_stack.back()->children.push_back(block);
2290 ast_stack.push_back(block);
2291 } behavioral_stmt {
2292 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2293 ast_stack.pop_back();
2294 ast_stack.pop_back();
2295 } |
2296 attr TOK_IF '(' expr ')' {
2297 AstNode *node = new AstNode(AST_CASE);
2298 AstNode *block = new AstNode(AST_BLOCK);
2299 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
2300 SET_AST_NODE_LOC(cond, @4, @4);
2301 ast_stack.back()->children.push_back(node);
2302 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
2303 node->children.push_back(cond);
2304 ast_stack.push_back(node);
2305 ast_stack.push_back(block);
2306 append_attr(node, $1);
2307 } behavioral_stmt {
2308 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2309 } optional_else {
2310 ast_stack.pop_back();
2311 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2312 ast_stack.pop_back();
2313 } |
2314 case_attr case_type '(' expr ')' {
2315 AstNode *node = new AstNode(AST_CASE, $4);
2316 ast_stack.back()->children.push_back(node);
2317 ast_stack.push_back(node);
2318 append_attr(node, $1);
2319 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2320 } opt_synopsys_attr case_body TOK_ENDCASE {
2321 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2322 case_type_stack.pop_back();
2323 ast_stack.pop_back();
2324 };
2325
2326 ;
2327
2328 unique_case_attr:
2329 /* empty */ {
2330 $$ = false;
2331 } |
2332 TOK_PRIORITY case_attr {
2333 $$ = $2;
2334 } |
2335 TOK_UNIQUE case_attr {
2336 $$ = true;
2337 };
2338
2339 case_attr:
2340 attr unique_case_attr {
2341 if ($2) (*$1)["\\parallel_case"] = AstNode::mkconst_int(1, false);
2342 $$ = $1;
2343 };
2344
2345 case_type:
2346 TOK_CASE {
2347 case_type_stack.push_back(0);
2348 } |
2349 TOK_CASEX {
2350 case_type_stack.push_back('x');
2351 } |
2352 TOK_CASEZ {
2353 case_type_stack.push_back('z');
2354 };
2355
2356 opt_synopsys_attr:
2357 opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
2358 if (ast_stack.back()->attributes.count("\\full_case") == 0)
2359 ast_stack.back()->attributes["\\full_case"] = AstNode::mkconst_int(1, false);
2360 } |
2361 opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
2362 if (ast_stack.back()->attributes.count("\\parallel_case") == 0)
2363 ast_stack.back()->attributes["\\parallel_case"] = AstNode::mkconst_int(1, false);
2364 } |
2365 /* empty */;
2366
2367 behavioral_stmt_list:
2368 behavioral_stmt_list behavioral_stmt |
2369 /* empty */;
2370
2371 optional_else:
2372 TOK_ELSE {
2373 AstNode *block = new AstNode(AST_BLOCK);
2374 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
2375 SET_AST_NODE_LOC(cond, @1, @1);
2376
2377 ast_stack.pop_back();
2378 ast_stack.back()->children.push_back(cond);
2379 ast_stack.push_back(block);
2380 } behavioral_stmt {
2381 SET_AST_NODE_LOC(ast_stack.back(), @3, @3);
2382 } |
2383 /* empty */ %prec FAKE_THEN;
2384
2385 case_body:
2386 case_body case_item |
2387 /* empty */;
2388
2389 case_item:
2390 {
2391 AstNode *node = new AstNode(
2392 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2393 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2394 ast_stack.back()->children.push_back(node);
2395 ast_stack.push_back(node);
2396 } case_select {
2397 AstNode *block = new AstNode(AST_BLOCK);
2398 ast_stack.back()->children.push_back(block);
2399 ast_stack.push_back(block);
2400 case_type_stack.push_back(0);
2401 } behavioral_stmt {
2402 case_type_stack.pop_back();
2403 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2404 ast_stack.pop_back();
2405 ast_stack.pop_back();
2406 };
2407
2408 gen_case_body:
2409 gen_case_body gen_case_item |
2410 /* empty */;
2411
2412 gen_case_item:
2413 {
2414 AstNode *node = new AstNode(
2415 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2416 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2417 ast_stack.back()->children.push_back(node);
2418 ast_stack.push_back(node);
2419 } case_select {
2420 case_type_stack.push_back(0);
2421 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2422 } gen_stmt_or_null {
2423 case_type_stack.pop_back();
2424 ast_stack.pop_back();
2425 };
2426
2427 case_select:
2428 case_expr_list ':' |
2429 TOK_DEFAULT;
2430
2431 case_expr_list:
2432 TOK_DEFAULT {
2433 AstNode *node = new AstNode(AST_DEFAULT);
2434 SET_AST_NODE_LOC(node, @1, @1);
2435 ast_stack.back()->children.push_back(node);
2436 } |
2437 TOK_SVA_LABEL {
2438 AstNode *node = new AstNode(AST_IDENTIFIER);
2439 SET_AST_NODE_LOC(node, @1, @1);
2440 ast_stack.back()->children.push_back(node);
2441 ast_stack.back()->children.back()->str = *$1;
2442 delete $1;
2443 } |
2444 expr {
2445 ast_stack.back()->children.push_back($1);
2446 } |
2447 case_expr_list ',' expr {
2448 ast_stack.back()->children.push_back($3);
2449 };
2450
2451 rvalue:
2452 hierarchical_id '[' expr ']' '.' rvalue {
2453 $$ = new AstNode(AST_PREFIX, $3, $6);
2454 $$->str = *$1;
2455 delete $1;
2456 } |
2457 hierarchical_id range {
2458 $$ = new AstNode(AST_IDENTIFIER, $2);
2459 $$->str = *$1;
2460 SET_AST_NODE_LOC($$, @1, @1);
2461 delete $1;
2462 if ($2 == nullptr && ($$->str == "\\$initstate" ||
2463 $$->str == "\\$anyconst" || $$->str == "\\$anyseq" ||
2464 $$->str == "\\$allconst" || $$->str == "\\$allseq"))
2465 $$->type = AST_FCALL;
2466 } |
2467 hierarchical_id non_opt_multirange {
2468 $$ = new AstNode(AST_IDENTIFIER, $2);
2469 $$->str = *$1;
2470 SET_AST_NODE_LOC($$, @1, @1);
2471 delete $1;
2472 };
2473
2474 lvalue:
2475 rvalue {
2476 $$ = $1;
2477 } |
2478 '{' lvalue_concat_list '}' {
2479 $$ = $2;
2480 };
2481
2482 lvalue_concat_list:
2483 expr {
2484 $$ = new AstNode(AST_CONCAT);
2485 $$->children.push_back($1);
2486 } |
2487 expr ',' lvalue_concat_list {
2488 $$ = $3;
2489 $$->children.push_back($1);
2490 };
2491
2492 opt_arg_list:
2493 '(' arg_list optional_comma ')' |
2494 /* empty */;
2495
2496 arg_list:
2497 arg_list2 |
2498 /* empty */;
2499
2500 arg_list2:
2501 single_arg |
2502 arg_list ',' single_arg;
2503
2504 single_arg:
2505 expr {
2506 ast_stack.back()->children.push_back($1);
2507 };
2508
2509 module_gen_body:
2510 module_gen_body gen_stmt_or_module_body_stmt |
2511 /* empty */;
2512
2513 gen_stmt_or_module_body_stmt:
2514 gen_stmt | module_body_stmt;
2515
2516 // this production creates the obligatory if-else shift/reduce conflict
2517 gen_stmt:
2518 TOK_FOR '(' {
2519 AstNode *node = new AstNode(AST_GENFOR);
2520 ast_stack.back()->children.push_back(node);
2521 ast_stack.push_back(node);
2522 } simple_behavioral_stmt ';' expr {
2523 ast_stack.back()->children.push_back($6);
2524 } ';' simple_behavioral_stmt ')' gen_stmt_block {
2525 SET_AST_NODE_LOC(ast_stack.back(), @1, @11);
2526 ast_stack.pop_back();
2527 } |
2528 TOK_IF '(' expr ')' {
2529 AstNode *node = new AstNode(AST_GENIF);
2530 ast_stack.back()->children.push_back(node);
2531 ast_stack.push_back(node);
2532 ast_stack.back()->children.push_back($3);
2533 } gen_stmt_block opt_gen_else {
2534 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2535 ast_stack.pop_back();
2536 } |
2537 case_type '(' expr ')' {
2538 AstNode *node = new AstNode(AST_GENCASE, $3);
2539 ast_stack.back()->children.push_back(node);
2540 ast_stack.push_back(node);
2541 } gen_case_body TOK_ENDCASE {
2542 case_type_stack.pop_back();
2543 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2544 ast_stack.pop_back();
2545 } |
2546 TOK_BEGIN {
2547 enterTypeScope();
2548 } opt_label {
2549 AstNode *node = new AstNode(AST_GENBLOCK);
2550 node->str = $3 ? *$3 : std::string();
2551 ast_stack.back()->children.push_back(node);
2552 ast_stack.push_back(node);
2553 } module_gen_body TOK_END opt_label {
2554 exitTypeScope();
2555 delete $3;
2556 delete $7;
2557 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2558 ast_stack.pop_back();
2559 } |
2560 TOK_MSG_TASKS {
2561 AstNode *node = new AstNode(AST_TECALL);
2562 node->str = *$1;
2563 delete $1;
2564 ast_stack.back()->children.push_back(node);
2565 ast_stack.push_back(node);
2566 } opt_arg_list ';'{
2567 SET_AST_NODE_LOC(ast_stack.back(), @1, @3);
2568 ast_stack.pop_back();
2569 };
2570
2571 gen_stmt_block:
2572 {
2573 AstNode *node = new AstNode(AST_GENBLOCK);
2574 ast_stack.back()->children.push_back(node);
2575 ast_stack.push_back(node);
2576 } gen_stmt_or_module_body_stmt {
2577 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2578 ast_stack.pop_back();
2579 };
2580
2581 gen_stmt_or_null:
2582 gen_stmt_block | ';';
2583
2584 opt_gen_else:
2585 TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
2586
2587 expr:
2588 basic_expr {
2589 $$ = $1;
2590 } |
2591 basic_expr '?' attr expr ':' expr {
2592 $$ = new AstNode(AST_TERNARY);
2593 $$->children.push_back($1);
2594 $$->children.push_back($4);
2595 $$->children.push_back($6);
2596 SET_AST_NODE_LOC($$, @1, @$);
2597 append_attr($$, $3);
2598 };
2599
2600 basic_expr:
2601 rvalue {
2602 $$ = $1;
2603 } |
2604 '(' expr ')' integral_number {
2605 if ($4->compare(0, 1, "'") != 0)
2606 frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
2607 AstNode *bits = $2;
2608 AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2609 if (val == NULL)
2610 log_error("Value conversion failed: `%s'\n", $4->c_str());
2611 $$ = new AstNode(AST_TO_BITS, bits, val);
2612 delete $4;
2613 } |
2614 hierarchical_id integral_number {
2615 if ($2->compare(0, 1, "'") != 0)
2616 frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
2617 AstNode *bits = new AstNode(AST_IDENTIFIER);
2618 bits->str = *$1;
2619 SET_AST_NODE_LOC(bits, @1, @1);
2620 AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2621 if (val == NULL)
2622 log_error("Value conversion failed: `%s'\n", $2->c_str());
2623 $$ = new AstNode(AST_TO_BITS, bits, val);
2624 delete $1;
2625 delete $2;
2626 } |
2627 integral_number {
2628 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2629 if ($$ == NULL)
2630 log_error("Value conversion failed: `%s'\n", $1->c_str());
2631 delete $1;
2632 } |
2633 TOK_REALVAL {
2634 $$ = new AstNode(AST_REALVALUE);
2635 char *p = (char*)malloc(GetSize(*$1) + 1), *q;
2636 for (int i = 0, j = 0; j < GetSize(*$1); j++)
2637 if ((*$1)[j] != '_')
2638 p[i++] = (*$1)[j], p[i] = 0;
2639 $$->realvalue = strtod(p, &q);
2640 SET_AST_NODE_LOC($$, @1, @1);
2641 log_assert(*q == 0);
2642 delete $1;
2643 free(p);
2644 } |
2645 TOK_STRING {
2646 $$ = AstNode::mkconst_str(*$1);
2647 delete $1;
2648 } |
2649 hierarchical_id attr {
2650 AstNode *node = new AstNode(AST_FCALL);
2651 node->str = *$1;
2652 delete $1;
2653 ast_stack.push_back(node);
2654 SET_AST_NODE_LOC(node, @1, @1);
2655 append_attr(node, $2);
2656 } '(' arg_list optional_comma ')' {
2657 $$ = ast_stack.back();
2658 ast_stack.pop_back();
2659 } |
2660 TOK_TO_SIGNED attr '(' expr ')' {
2661 $$ = new AstNode(AST_TO_SIGNED, $4);
2662 append_attr($$, $2);
2663 } |
2664 TOK_TO_UNSIGNED attr '(' expr ')' {
2665 $$ = new AstNode(AST_TO_UNSIGNED, $4);
2666 append_attr($$, $2);
2667 } |
2668 '(' expr ')' {
2669 $$ = $2;
2670 } |
2671 '(' expr ':' expr ':' expr ')' {
2672 delete $2;
2673 $$ = $4;
2674 delete $6;
2675 } |
2676 '{' concat_list '}' {
2677 $$ = $2;
2678 } |
2679 '{' expr '{' concat_list '}' '}' {
2680 $$ = new AstNode(AST_REPLICATE, $2, $4);
2681 } |
2682 '~' attr basic_expr %prec UNARY_OPS {
2683 $$ = new AstNode(AST_BIT_NOT, $3);
2684 SET_AST_NODE_LOC($$, @1, @3);
2685 append_attr($$, $2);
2686 } |
2687 basic_expr '&' attr basic_expr {
2688 $$ = new AstNode(AST_BIT_AND, $1, $4);
2689 SET_AST_NODE_LOC($$, @1, @4);
2690 append_attr($$, $3);
2691 } |
2692 basic_expr OP_NAND attr basic_expr {
2693 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
2694 SET_AST_NODE_LOC($$, @1, @4);
2695 append_attr($$, $3);
2696 } |
2697 basic_expr '|' attr basic_expr {
2698 $$ = new AstNode(AST_BIT_OR, $1, $4);
2699 SET_AST_NODE_LOC($$, @1, @4);
2700 append_attr($$, $3);
2701 } |
2702 basic_expr OP_NOR attr basic_expr {
2703 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
2704 SET_AST_NODE_LOC($$, @1, @4);
2705 append_attr($$, $3);
2706 } |
2707 basic_expr '^' attr basic_expr {
2708 $$ = new AstNode(AST_BIT_XOR, $1, $4);
2709 SET_AST_NODE_LOC($$, @1, @4);
2710 append_attr($$, $3);
2711 } |
2712 basic_expr OP_XNOR attr basic_expr {
2713 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
2714 SET_AST_NODE_LOC($$, @1, @4);
2715 append_attr($$, $3);
2716 } |
2717 '&' attr basic_expr %prec UNARY_OPS {
2718 $$ = new AstNode(AST_REDUCE_AND, $3);
2719 SET_AST_NODE_LOC($$, @1, @3);
2720 append_attr($$, $2);
2721 } |
2722 OP_NAND attr basic_expr %prec UNARY_OPS {
2723 $$ = new AstNode(AST_REDUCE_AND, $3);
2724 SET_AST_NODE_LOC($$, @1, @3);
2725 append_attr($$, $2);
2726 $$ = new AstNode(AST_LOGIC_NOT, $$);
2727 } |
2728 '|' attr basic_expr %prec UNARY_OPS {
2729 $$ = new AstNode(AST_REDUCE_OR, $3);
2730 SET_AST_NODE_LOC($$, @1, @3);
2731 append_attr($$, $2);
2732 } |
2733 OP_NOR attr basic_expr %prec UNARY_OPS {
2734 $$ = new AstNode(AST_REDUCE_OR, $3);
2735 SET_AST_NODE_LOC($$, @1, @3);
2736 append_attr($$, $2);
2737 $$ = new AstNode(AST_LOGIC_NOT, $$);
2738 SET_AST_NODE_LOC($$, @1, @3);
2739 } |
2740 '^' attr basic_expr %prec UNARY_OPS {
2741 $$ = new AstNode(AST_REDUCE_XOR, $3);
2742 SET_AST_NODE_LOC($$, @1, @3);
2743 append_attr($$, $2);
2744 } |
2745 OP_XNOR attr basic_expr %prec UNARY_OPS {
2746 $$ = new AstNode(AST_REDUCE_XNOR, $3);
2747 SET_AST_NODE_LOC($$, @1, @3);
2748 append_attr($$, $2);
2749 } |
2750 basic_expr OP_SHL attr basic_expr {
2751 $$ = new AstNode(AST_SHIFT_LEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2752 SET_AST_NODE_LOC($$, @1, @4);
2753 append_attr($$, $3);
2754 } |
2755 basic_expr OP_SHR attr basic_expr {
2756 $$ = new AstNode(AST_SHIFT_RIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2757 SET_AST_NODE_LOC($$, @1, @4);
2758 append_attr($$, $3);
2759 } |
2760 basic_expr OP_SSHL attr basic_expr {
2761 $$ = new AstNode(AST_SHIFT_SLEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2762 SET_AST_NODE_LOC($$, @1, @4);
2763 append_attr($$, $3);
2764 } |
2765 basic_expr OP_SSHR attr basic_expr {
2766 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2767 SET_AST_NODE_LOC($$, @1, @4);
2768 append_attr($$, $3);
2769 } |
2770 basic_expr '<' attr basic_expr {
2771 $$ = new AstNode(AST_LT, $1, $4);
2772 SET_AST_NODE_LOC($$, @1, @4);
2773 append_attr($$, $3);
2774 } |
2775 basic_expr OP_LE attr basic_expr {
2776 $$ = new AstNode(AST_LE, $1, $4);
2777 SET_AST_NODE_LOC($$, @1, @4);
2778 append_attr($$, $3);
2779 } |
2780 basic_expr OP_EQ attr basic_expr {
2781 $$ = new AstNode(AST_EQ, $1, $4);
2782 SET_AST_NODE_LOC($$, @1, @4);
2783 append_attr($$, $3);
2784 } |
2785 basic_expr OP_NE attr basic_expr {
2786 $$ = new AstNode(AST_NE, $1, $4);
2787 SET_AST_NODE_LOC($$, @1, @4);
2788 append_attr($$, $3);
2789 } |
2790 basic_expr OP_EQX attr basic_expr {
2791 $$ = new AstNode(AST_EQX, $1, $4);
2792 SET_AST_NODE_LOC($$, @1, @4);
2793 append_attr($$, $3);
2794 } |
2795 basic_expr OP_NEX attr basic_expr {
2796 $$ = new AstNode(AST_NEX, $1, $4);
2797 SET_AST_NODE_LOC($$, @1, @4);
2798 append_attr($$, $3);
2799 } |
2800 basic_expr OP_GE attr basic_expr {
2801 $$ = new AstNode(AST_GE, $1, $4);
2802 SET_AST_NODE_LOC($$, @1, @4);
2803 append_attr($$, $3);
2804 } |
2805 basic_expr '>' attr basic_expr {
2806 $$ = new AstNode(AST_GT, $1, $4);
2807 SET_AST_NODE_LOC($$, @1, @4);
2808 append_attr($$, $3);
2809 } |
2810 basic_expr '+' attr basic_expr {
2811 $$ = new AstNode(AST_ADD, $1, $4);
2812 SET_AST_NODE_LOC($$, @1, @4);
2813 append_attr($$, $3);
2814 } |
2815 basic_expr '-' attr basic_expr {
2816 $$ = new AstNode(AST_SUB, $1, $4);
2817 SET_AST_NODE_LOC($$, @1, @4);
2818 append_attr($$, $3);
2819 } |
2820 basic_expr '*' attr basic_expr {
2821 $$ = new AstNode(AST_MUL, $1, $4);
2822 SET_AST_NODE_LOC($$, @1, @4);
2823 append_attr($$, $3);
2824 } |
2825 basic_expr '/' attr basic_expr {
2826 $$ = new AstNode(AST_DIV, $1, $4);
2827 SET_AST_NODE_LOC($$, @1, @4);
2828 append_attr($$, $3);
2829 } |
2830 basic_expr '%' attr basic_expr {
2831 $$ = new AstNode(AST_MOD, $1, $4);
2832 SET_AST_NODE_LOC($$, @1, @4);
2833 append_attr($$, $3);
2834 } |
2835 basic_expr OP_POW attr basic_expr {
2836 $$ = new AstNode(AST_POW, $1, $4);
2837 SET_AST_NODE_LOC($$, @1, @4);
2838 append_attr($$, $3);
2839 } |
2840 '+' attr basic_expr %prec UNARY_OPS {
2841 $$ = new AstNode(AST_POS, $3);
2842 SET_AST_NODE_LOC($$, @1, @3);
2843 append_attr($$, $2);
2844 } |
2845 '-' attr basic_expr %prec UNARY_OPS {
2846 $$ = new AstNode(AST_NEG, $3);
2847 SET_AST_NODE_LOC($$, @1, @3);
2848 append_attr($$, $2);
2849 } |
2850 basic_expr OP_LAND attr basic_expr {
2851 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
2852 SET_AST_NODE_LOC($$, @1, @4);
2853 append_attr($$, $3);
2854 } |
2855 basic_expr OP_LOR attr basic_expr {
2856 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
2857 SET_AST_NODE_LOC($$, @1, @4);
2858 append_attr($$, $3);
2859 } |
2860 '!' attr basic_expr %prec UNARY_OPS {
2861 $$ = new AstNode(AST_LOGIC_NOT, $3);
2862 SET_AST_NODE_LOC($$, @1, @3);
2863 append_attr($$, $2);
2864 };
2865
2866 concat_list:
2867 expr {
2868 $$ = new AstNode(AST_CONCAT, $1);
2869 } |
2870 expr ',' concat_list {
2871 $$ = $3;
2872 $$->children.push_back($1);
2873 };
2874
2875 integral_number:
2876 TOK_CONSTVAL { $$ = $1; } |
2877 TOK_UNBASED_UNSIZED_CONSTVAL { $$ = $1; } |
2878 TOK_BASE TOK_BASED_CONSTVAL {
2879 $1->append(*$2);
2880 $$ = $1;
2881 delete $2;
2882 } |
2883 TOK_CONSTVAL TOK_BASE TOK_BASED_CONSTVAL {
2884 $1->append(*$2).append(*$3);
2885 $$ = $1;
2886 delete $2;
2887 delete $3;
2888 };