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Merge pull request #1952 from boqwxp/add_edge_location
[yosys.git] / frontends / verilog / verilog_parser.y
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * The Verilog frontend.
21 *
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
26 *
27 * ---
28 *
29 * This is the actual bison parser for Verilog code. The AST ist created directly
30 * from the bison reduce functions here. Note that this code uses a few global
31 * variables to hold the state of the AST generator and therefore this parser is
32 * not reentrant.
33 *
34 */
35
36 %{
37 #include <list>
38 #include <stack>
39 #include <string.h>
40 #include "frontends/verilog/verilog_frontend.h"
41 #include "frontends/verilog/verilog_parser.tab.hh"
42 #include "kernel/log.h"
43
44 #define YYLEX_PARAM &yylval, &yylloc
45
46 USING_YOSYS_NAMESPACE
47 using namespace AST;
48 using namespace VERILOG_FRONTEND;
49
50 YOSYS_NAMESPACE_BEGIN
51 namespace VERILOG_FRONTEND {
52 int port_counter;
53 std::map<std::string, int> port_stubs;
54 std::map<std::string, AstNode*> *attr_list, default_attr_list;
55 std::stack<std::map<std::string, AstNode*> *> attr_list_stack;
56 std::map<std::string, AstNode*> *albuf;
57 std::vector<UserTypeMap*> user_type_stack;
58 std::map<std::string, AstNode*> pkg_user_types;
59 std::vector<AstNode*> ast_stack;
60 struct AstNode *astbuf1, *astbuf2, *astbuf3;
61 struct AstNode *current_function_or_task;
62 struct AstNode *current_ast, *current_ast_mod;
63 int current_function_or_task_port_id;
64 std::vector<char> case_type_stack;
65 bool do_not_require_port_stubs;
66 bool default_nettype_wire;
67 bool sv_mode, formal_mode, lib_mode, specify_mode;
68 bool noassert_mode, noassume_mode, norestrict_mode;
69 bool assume_asserts_mode, assert_assumes_mode;
70 bool current_wire_rand, current_wire_const;
71 bool current_modport_input, current_modport_output;
72 std::istream *lexin;
73 }
74 YOSYS_NAMESPACE_END
75
76 #define SET_AST_NODE_LOC(WHICH, BEGIN, END) \
77 do { (WHICH)->location.first_line = (BEGIN).first_line; \
78 (WHICH)->location.first_column = (BEGIN).first_column; \
79 (WHICH)->location.last_line = (END).last_line; \
80 (WHICH)->location.last_column = (END).last_column; } while(0)
81
82 #define SET_RULE_LOC(LHS, BEGIN, END) \
83 do { (LHS).first_line = (BEGIN).first_line; \
84 (LHS).first_column = (BEGIN).first_column; \
85 (LHS).last_line = (END).last_line; \
86 (LHS).last_column = (END).last_column; } while(0)
87
88 int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
89
90 static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
91 {
92 for (auto &it : *al) {
93 if (ast->attributes.count(it.first) > 0)
94 delete ast->attributes[it.first];
95 ast->attributes[it.first] = it.second;
96 }
97 delete al;
98 }
99
100 static void append_attr_clone(AstNode *ast, std::map<std::string, AstNode*> *al)
101 {
102 for (auto &it : *al) {
103 if (ast->attributes.count(it.first) > 0)
104 delete ast->attributes[it.first];
105 ast->attributes[it.first] = it.second->clone();
106 }
107 }
108
109 static void free_attr(std::map<std::string, AstNode*> *al)
110 {
111 for (auto &it : *al)
112 delete it.second;
113 delete al;
114 }
115
116 struct specify_target {
117 char polarity_op;
118 AstNode *dst, *dat;
119 };
120
121 struct specify_triple {
122 AstNode *t_min, *t_avg, *t_max;
123 };
124
125 struct specify_rise_fall {
126 specify_triple rise;
127 specify_triple fall;
128 };
129
130 static void addTypedefNode(std::string *name, AstNode *node)
131 {
132 log_assert(node);
133 auto *tnode = new AstNode(AST_TYPEDEF, node);
134 tnode->str = *name;
135 auto user_types = user_type_stack.back();
136 (*user_types)[*name] = tnode;
137 if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {
138 // typedef inside a package so we need the qualified name
139 auto qname = current_ast_mod->str + "::" + (*name).substr(1);
140 pkg_user_types[qname] = tnode;
141 }
142 delete name;
143 ast_stack.back()->children.push_back(tnode);
144 }
145
146 static void enterTypeScope()
147 {
148 auto user_types = new UserTypeMap();
149 user_type_stack.push_back(user_types);
150 }
151
152 static void exitTypeScope()
153 {
154 user_type_stack.pop_back();
155 }
156
157 static bool isInLocalScope(const std::string *name)
158 {
159 // tests if a name was declared in the current block scope
160 auto user_types = user_type_stack.back();
161 return (user_types->count(*name) > 0);
162 }
163
164 static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
165 {
166 auto range = new AstNode(AST_RANGE);
167 range->children.push_back(AstNode::mkconst_int(msb, true));
168 range->children.push_back(AstNode::mkconst_int(lsb, true));
169 range->is_signed = isSigned;
170 return range;
171 }
172
173 static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned = true)
174 {
175 auto range = makeRange(msb, lsb, isSigned);
176 parent->children.push_back(range);
177 }
178 %}
179
180 %define api.prefix {frontend_verilog_yy}
181 %define api.pure
182
183 /* The union is defined in the header, so we need to provide all the
184 * includes it requires
185 */
186 %code requires {
187 #include <map>
188 #include <string>
189 #include "frontends/verilog/verilog_frontend.h"
190 }
191
192 %union {
193 std::string *string;
194 struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
195 std::map<std::string, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
196 struct specify_target *specify_target_ptr;
197 struct specify_triple *specify_triple_ptr;
198 struct specify_rise_fall *specify_rise_fall_ptr;
199 bool boolean;
200 char ch;
201 }
202
203 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
204 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
205 %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL
206 %token <string> TOK_USER_TYPE TOK_PKG_USER_TYPE
207 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
208 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
209 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
210 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
211 %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
212 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
213 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
214 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
215 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
216 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
217 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
218 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
219 %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
220 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
221 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
222 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
223 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
224 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
225 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
226
227 %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
228 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
229 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
230 %type <string> type_name
231 %type <ast> opt_enum_init
232 %type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
233 %type <al> attr case_attr
234
235 %type <specify_target_ptr> specify_target
236 %type <specify_triple_ptr> specify_triple specify_opt_triple
237 %type <specify_rise_fall_ptr> specify_rise_fall
238 %type <ast> specify_if specify_condition
239 %type <ch> specify_edge
240
241 // operator precedence from low to high
242 %left OP_LOR
243 %left OP_LAND
244 %left '|' OP_NOR
245 %left '^' OP_XNOR
246 %left '&' OP_NAND
247 %left OP_EQ OP_NE OP_EQX OP_NEX
248 %left '<' OP_LE OP_GE '>'
249 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
250 %left '+' '-'
251 %left '*' '/' '%'
252 %left OP_POW
253 %right UNARY_OPS
254
255 %define parse.error verbose
256 %define parse.lac full
257
258 %nonassoc FAKE_THEN
259 %nonassoc TOK_ELSE
260
261 %debug
262 %locations
263
264 %%
265
266 input: {
267 ast_stack.clear();
268 ast_stack.push_back(current_ast);
269 } design {
270 ast_stack.pop_back();
271 log_assert(GetSize(ast_stack) == 0);
272 for (auto &it : default_attr_list)
273 delete it.second;
274 default_attr_list.clear();
275 };
276
277 design:
278 module design |
279 defattr design |
280 task_func_decl design |
281 param_decl design |
282 localparam_decl design |
283 typedef_decl design |
284 package design |
285 interface design |
286 /* empty */;
287
288 attr:
289 {
290 if (attr_list != nullptr)
291 attr_list_stack.push(attr_list);
292 attr_list = new std::map<std::string, AstNode*>;
293 for (auto &it : default_attr_list)
294 (*attr_list)[it.first] = it.second->clone();
295 } attr_opt {
296 $$ = attr_list;
297 if (!attr_list_stack.empty()) {
298 attr_list = attr_list_stack.top();
299 attr_list_stack.pop();
300 } else
301 attr_list = nullptr;
302 };
303
304 attr_opt:
305 attr_opt ATTR_BEGIN opt_attr_list ATTR_END {
306 SET_RULE_LOC(@$, @2, @$);
307 }|
308 /* empty */;
309
310 defattr:
311 DEFATTR_BEGIN {
312 if (attr_list != nullptr)
313 attr_list_stack.push(attr_list);
314 attr_list = new std::map<std::string, AstNode*>;
315 for (auto &it : default_attr_list)
316 delete it.second;
317 default_attr_list.clear();
318 } opt_attr_list {
319 attr_list->swap(default_attr_list);
320 delete attr_list;
321 if (!attr_list_stack.empty()) {
322 attr_list = attr_list_stack.top();
323 attr_list_stack.pop();
324 } else
325 attr_list = nullptr;
326 } DEFATTR_END;
327
328 opt_attr_list:
329 attr_list | /* empty */;
330
331 attr_list:
332 attr_assign |
333 attr_list ',' attr_assign;
334
335 attr_assign:
336 hierarchical_id {
337 if (attr_list->count(*$1) != 0)
338 delete (*attr_list)[*$1];
339 (*attr_list)[*$1] = AstNode::mkconst_int(1, false);
340 delete $1;
341 } |
342 hierarchical_id '=' expr {
343 if (attr_list->count(*$1) != 0)
344 delete (*attr_list)[*$1];
345 (*attr_list)[*$1] = $3;
346 delete $1;
347 };
348
349 hierarchical_id:
350 TOK_ID {
351 $$ = $1;
352 } |
353 hierarchical_id TOK_PACKAGESEP TOK_ID {
354 if ($3->compare(0, 1, "\\") == 0)
355 *$1 += "::" + $3->substr(1);
356 else
357 *$1 += "::" + *$3;
358 delete $3;
359 $$ = $1;
360 } |
361 hierarchical_id '.' TOK_ID {
362 if ($3->compare(0, 1, "\\") == 0)
363 *$1 += "." + $3->substr(1);
364 else
365 *$1 += "." + *$3;
366 delete $3;
367 $$ = $1;
368 };
369
370 hierarchical_type_id:
371 TOK_USER_TYPE
372 | TOK_PKG_USER_TYPE // package qualified type name
373 | '(' TOK_USER_TYPE ')' { $$ = $2; } // non-standard grammar
374 ;
375
376 module:
377 attr TOK_MODULE {
378 enterTypeScope();
379 } TOK_ID {
380 do_not_require_port_stubs = false;
381 AstNode *mod = new AstNode(AST_MODULE);
382 ast_stack.back()->children.push_back(mod);
383 ast_stack.push_back(mod);
384 current_ast_mod = mod;
385 port_stubs.clear();
386 port_counter = 0;
387 mod->str = *$4;
388 append_attr(mod, $1);
389 delete $4;
390 } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
391 if (port_stubs.size() != 0)
392 frontend_verilog_yyerror("Missing details for module port `%s'.",
393 port_stubs.begin()->first.c_str());
394 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
395 ast_stack.pop_back();
396 log_assert(ast_stack.size() == 1);
397 current_ast_mod = NULL;
398 exitTypeScope();
399 };
400
401 module_para_opt:
402 '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
403
404 module_para_list:
405 single_module_para | module_para_list ',' single_module_para;
406
407 single_module_para:
408 /* empty */ |
409 attr TOK_PARAMETER {
410 if (astbuf1) delete astbuf1;
411 astbuf1 = new AstNode(AST_PARAMETER);
412 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
413 append_attr(astbuf1, $1);
414 } param_type single_param_decl |
415 attr TOK_LOCALPARAM {
416 if (astbuf1) delete astbuf1;
417 astbuf1 = new AstNode(AST_LOCALPARAM);
418 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
419 append_attr(astbuf1, $1);
420 } param_type single_param_decl |
421 single_param_decl;
422
423 module_args_opt:
424 '(' ')' | /* empty */ | '(' module_args optional_comma ')';
425
426 module_args:
427 module_arg | module_args ',' module_arg;
428
429 optional_comma:
430 ',' | /* empty */;
431
432 module_arg_opt_assignment:
433 '=' expr {
434 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
435 AstNode *wire = new AstNode(AST_IDENTIFIER);
436 wire->str = ast_stack.back()->children.back()->str;
437 if (ast_stack.back()->children.back()->is_input) {
438 AstNode *n = ast_stack.back()->children.back();
439 if (n->attributes.count(ID::defaultvalue))
440 delete n->attributes.at(ID::defaultvalue);
441 n->attributes[ID::defaultvalue] = $2;
442 } else
443 if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
444 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
445 else
446 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
447 } else
448 frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
449 } |
450 /* empty */;
451
452 module_arg:
453 TOK_ID {
454 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
455 AstNode *node = ast_stack.back()->children.back()->clone();
456 node->str = *$1;
457 node->port_id = ++port_counter;
458 ast_stack.back()->children.push_back(node);
459 SET_AST_NODE_LOC(node, @1, @1);
460 } else {
461 if (port_stubs.count(*$1) != 0)
462 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
463 port_stubs[*$1] = ++port_counter;
464 }
465 delete $1;
466 } module_arg_opt_assignment |
467 TOK_ID {
468 astbuf1 = new AstNode(AST_INTERFACEPORT);
469 astbuf1->children.push_back(new AstNode(AST_INTERFACEPORTTYPE));
470 astbuf1->children[0]->str = *$1;
471 delete $1;
472 } TOK_ID { /* SV interfaces */
473 if (!sv_mode)
474 frontend_verilog_yyerror("Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
475 astbuf2 = astbuf1->clone(); // really only needed if multiple instances of same type.
476 astbuf2->str = *$3;
477 delete $3;
478 astbuf2->port_id = ++port_counter;
479 ast_stack.back()->children.push_back(astbuf2);
480 delete astbuf1; // really only needed if multiple instances of same type.
481 } module_arg_opt_assignment |
482 attr wire_type range TOK_ID {
483 AstNode *node = $2;
484 node->str = *$4;
485 SET_AST_NODE_LOC(node, @4, @4);
486 node->port_id = ++port_counter;
487 if ($3 != NULL)
488 node->children.push_back($3);
489 if (!node->is_input && !node->is_output)
490 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
491 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
492 frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
493 ast_stack.back()->children.push_back(node);
494 append_attr(node, $1);
495 delete $4;
496 } module_arg_opt_assignment |
497 '.' '.' '.' {
498 do_not_require_port_stubs = true;
499 };
500
501 package:
502 attr TOK_PACKAGE {
503 enterTypeScope();
504 } TOK_ID {
505 AstNode *mod = new AstNode(AST_PACKAGE);
506 ast_stack.back()->children.push_back(mod);
507 ast_stack.push_back(mod);
508 current_ast_mod = mod;
509 mod->str = *$4;
510 append_attr(mod, $1);
511 } ';' package_body TOK_ENDPACKAGE {
512 ast_stack.pop_back();
513 current_ast_mod = NULL;
514 exitTypeScope();
515 };
516
517 package_body:
518 package_body package_body_stmt
519 | // optional
520 ;
521
522 package_body_stmt:
523 typedef_decl |
524 localparam_decl |
525 param_decl;
526
527 interface:
528 TOK_INTERFACE {
529 enterTypeScope();
530 } TOK_ID {
531 do_not_require_port_stubs = false;
532 AstNode *intf = new AstNode(AST_INTERFACE);
533 ast_stack.back()->children.push_back(intf);
534 ast_stack.push_back(intf);
535 current_ast_mod = intf;
536 port_stubs.clear();
537 port_counter = 0;
538 intf->str = *$3;
539 delete $3;
540 } module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
541 if (port_stubs.size() != 0)
542 frontend_verilog_yyerror("Missing details for module port `%s'.",
543 port_stubs.begin()->first.c_str());
544 ast_stack.pop_back();
545 log_assert(ast_stack.size() == 1);
546 current_ast_mod = NULL;
547 exitTypeScope();
548 };
549
550 interface_body:
551 interface_body interface_body_stmt |;
552
553 interface_body_stmt:
554 param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
555 modport_stmt;
556
557 non_opt_delay:
558 '#' TOK_ID { delete $2; } |
559 '#' TOK_CONSTVAL { delete $2; } |
560 '#' TOK_REALVAL { delete $2; } |
561 '#' '(' expr ')' { delete $3; } |
562 '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
563
564 delay:
565 non_opt_delay | /* empty */;
566
567 wire_type:
568 {
569 astbuf3 = new AstNode(AST_WIRE);
570 current_wire_rand = false;
571 current_wire_const = false;
572 } wire_type_token_list {
573 $$ = astbuf3;
574 SET_RULE_LOC(@$, @2, @$);
575 };
576
577 wire_type_token_list:
578 wire_type_token |
579 wire_type_token_list wire_type_token |
580 wire_type_token_io |
581 hierarchical_type_id {
582 astbuf3->is_custom_type = true;
583 astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
584 astbuf3->children.back()->str = *$1;
585 };
586
587 wire_type_token_io:
588 TOK_INPUT {
589 astbuf3->is_input = true;
590 } |
591 TOK_OUTPUT {
592 astbuf3->is_output = true;
593 } |
594 TOK_INOUT {
595 astbuf3->is_input = true;
596 astbuf3->is_output = true;
597 };
598
599 wire_type_token:
600 TOK_WIRE {
601 } |
602 TOK_WOR {
603 astbuf3->is_wor = true;
604 } |
605 TOK_WAND {
606 astbuf3->is_wand = true;
607 } |
608 TOK_REG {
609 astbuf3->is_reg = true;
610 } |
611 TOK_LOGIC {
612 astbuf3->is_logic = true;
613 } |
614 TOK_VAR {
615 astbuf3->is_logic = true;
616 } |
617 TOK_INTEGER {
618 astbuf3->is_reg = true;
619 astbuf3->range_left = 31;
620 astbuf3->range_right = 0;
621 astbuf3->is_signed = true;
622 } |
623 TOK_GENVAR {
624 astbuf3->type = AST_GENVAR;
625 astbuf3->is_reg = true;
626 astbuf3->is_signed = true;
627 astbuf3->range_left = 31;
628 astbuf3->range_right = 0;
629 } |
630 TOK_SIGNED {
631 astbuf3->is_signed = true;
632 } |
633 TOK_RAND {
634 current_wire_rand = true;
635 } |
636 TOK_CONST {
637 current_wire_const = true;
638 };
639
640 non_opt_range:
641 '[' expr ':' expr ']' {
642 $$ = new AstNode(AST_RANGE);
643 $$->children.push_back($2);
644 $$->children.push_back($4);
645 } |
646 '[' expr TOK_POS_INDEXED expr ']' {
647 $$ = new AstNode(AST_RANGE);
648 AstNode *expr = new AstNode(AST_CONCAT, $2);
649 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
650 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
651 } |
652 '[' expr TOK_NEG_INDEXED expr ']' {
653 $$ = new AstNode(AST_RANGE);
654 AstNode *expr = new AstNode(AST_CONCAT, $2);
655 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
656 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
657 } |
658 '[' expr ']' {
659 $$ = new AstNode(AST_RANGE);
660 $$->children.push_back($2);
661 };
662
663 non_opt_multirange:
664 non_opt_range non_opt_range {
665 $$ = new AstNode(AST_MULTIRANGE, $1, $2);
666 } |
667 non_opt_multirange non_opt_range {
668 $$ = $1;
669 $$->children.push_back($2);
670 };
671
672 range:
673 non_opt_range {
674 $$ = $1;
675 } |
676 /* empty */ {
677 $$ = NULL;
678 };
679
680 range_or_multirange:
681 range { $$ = $1; } |
682 non_opt_multirange { $$ = $1; };
683
684 range_or_signed_int:
685 range {
686 $$ = $1;
687 } |
688 TOK_INTEGER {
689 $$ = new AstNode(AST_RANGE);
690 $$->children.push_back(AstNode::mkconst_int(31, true));
691 $$->children.push_back(AstNode::mkconst_int(0, true));
692 $$->is_signed = true;
693 };
694
695 module_body:
696 module_body module_body_stmt |
697 /* the following line makes the generate..endgenrate keywords optional */
698 module_body gen_stmt |
699 /* empty */;
700
701 module_body_stmt:
702 task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
703 enum_decl |
704 always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
705
706 checker_decl:
707 TOK_CHECKER TOK_ID ';' {
708 AstNode *node = new AstNode(AST_GENBLOCK);
709 node->str = *$2;
710 ast_stack.back()->children.push_back(node);
711 ast_stack.push_back(node);
712 } module_body TOK_ENDCHECKER {
713 delete $2;
714 ast_stack.pop_back();
715 };
716
717 task_func_decl:
718 attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
719 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
720 current_function_or_task->str = *$4;
721 append_attr(current_function_or_task, $1);
722 ast_stack.back()->children.push_back(current_function_or_task);
723 delete $3;
724 delete $4;
725 } opt_dpi_function_args ';' {
726 current_function_or_task = NULL;
727 } |
728 attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
729 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
730 current_function_or_task->str = *$6;
731 append_attr(current_function_or_task, $1);
732 ast_stack.back()->children.push_back(current_function_or_task);
733 delete $3;
734 delete $5;
735 delete $6;
736 } opt_dpi_function_args ';' {
737 current_function_or_task = NULL;
738 } |
739 attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
740 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
741 current_function_or_task->str = *$8;
742 append_attr(current_function_or_task, $1);
743 ast_stack.back()->children.push_back(current_function_or_task);
744 delete $3;
745 delete $5;
746 delete $7;
747 delete $8;
748 } opt_dpi_function_args ';' {
749 current_function_or_task = NULL;
750 } |
751 attr TOK_TASK opt_automatic TOK_ID {
752 current_function_or_task = new AstNode(AST_TASK);
753 current_function_or_task->str = *$4;
754 append_attr(current_function_or_task, $1);
755 ast_stack.back()->children.push_back(current_function_or_task);
756 ast_stack.push_back(current_function_or_task);
757 current_function_or_task_port_id = 1;
758 delete $4;
759 } task_func_args_opt ';' task_func_body TOK_ENDTASK {
760 current_function_or_task = NULL;
761 ast_stack.pop_back();
762 } |
763 attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID {
764 current_function_or_task = new AstNode(AST_FUNCTION);
765 current_function_or_task->str = *$6;
766 append_attr(current_function_or_task, $1);
767 ast_stack.back()->children.push_back(current_function_or_task);
768 ast_stack.push_back(current_function_or_task);
769 AstNode *outreg = new AstNode(AST_WIRE);
770 outreg->str = *$6;
771 outreg->is_signed = $4;
772 outreg->is_reg = true;
773 if ($5 != NULL) {
774 outreg->children.push_back($5);
775 outreg->is_signed = $4 || $5->is_signed;
776 $5->is_signed = false;
777 }
778 current_function_or_task->children.push_back(outreg);
779 current_function_or_task_port_id = 1;
780 delete $6;
781 } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
782 current_function_or_task = NULL;
783 ast_stack.pop_back();
784 };
785
786 dpi_function_arg:
787 TOK_ID TOK_ID {
788 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
789 delete $1;
790 delete $2;
791 } |
792 TOK_ID {
793 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
794 delete $1;
795 };
796
797 opt_dpi_function_args:
798 '(' dpi_function_args ')' |
799 /* empty */;
800
801 dpi_function_args:
802 dpi_function_args ',' dpi_function_arg |
803 dpi_function_args ',' |
804 dpi_function_arg |
805 /* empty */;
806
807 opt_automatic:
808 TOK_AUTOMATIC |
809 /* empty */;
810
811 opt_signed:
812 TOK_SIGNED {
813 $$ = true;
814 } |
815 /* empty */ {
816 $$ = false;
817 };
818
819 task_func_args_opt:
820 '(' ')' | /* empty */ | '(' {
821 albuf = nullptr;
822 astbuf1 = nullptr;
823 astbuf2 = nullptr;
824 } task_func_args optional_comma {
825 delete astbuf1;
826 if (astbuf2 != NULL)
827 delete astbuf2;
828 free_attr(albuf);
829 } ')';
830
831 task_func_args:
832 task_func_port | task_func_args ',' task_func_port;
833
834 task_func_port:
835 attr wire_type range {
836 if (albuf) {
837 delete astbuf1;
838 if (astbuf2 != NULL)
839 delete astbuf2;
840 free_attr(albuf);
841 }
842 albuf = $1;
843 astbuf1 = $2;
844 astbuf2 = $3;
845 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
846 if (astbuf2) {
847 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions (task/function arguments)");
848 } else {
849 astbuf2 = new AstNode(AST_RANGE);
850 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
851 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
852 }
853 }
854 if (astbuf2 && astbuf2->children.size() != 2)
855 frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
856 } wire_name | wire_name;
857
858 task_func_body:
859 task_func_body behavioral_stmt |
860 /* empty */;
861
862 /*************************** specify parser ***************************/
863
864 specify_block:
865 TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
866
867 specify_item_list:
868 specify_item specify_item_list |
869 /* empty */;
870
871 specify_item:
872 specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
873 AstNode *en_expr = $1;
874 char specify_edge = $3;
875 AstNode *src_expr = $4;
876 string *oper = $5;
877 specify_target *target = $6;
878 specify_rise_fall *timing = $9;
879
880 if (specify_edge != 0 && target->dat == nullptr)
881 frontend_verilog_yyerror("Found specify edge but no data spec.\n");
882
883 AstNode *cell = new AstNode(AST_CELL);
884 ast_stack.back()->children.push_back(cell);
885 cell->str = stringf("$specify$%d", autoidx++);
886 cell->children.push_back(new AstNode(AST_CELLTYPE));
887 cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
888
889 char oper_polarity = 0;
890 char oper_type = oper->at(0);
891
892 if (oper->size() == 3) {
893 oper_polarity = oper->at(0);
894 oper_type = oper->at(1);
895 }
896
897 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
898 cell->children.back()->str = "\\FULL";
899
900 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
901 cell->children.back()->str = "\\SRC_DST_PEN";
902
903 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
904 cell->children.back()->str = "\\SRC_DST_POL";
905
906 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
907 cell->children.back()->str = "\\T_RISE_MIN";
908
909 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
910 cell->children.back()->str = "\\T_RISE_TYP";
911
912 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
913 cell->children.back()->str = "\\T_RISE_MAX";
914
915 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
916 cell->children.back()->str = "\\T_FALL_MIN";
917
918 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
919 cell->children.back()->str = "\\T_FALL_TYP";
920
921 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
922 cell->children.back()->str = "\\T_FALL_MAX";
923
924 cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
925 cell->children.back()->str = "\\EN";
926
927 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
928 cell->children.back()->str = "\\SRC";
929
930 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
931 cell->children.back()->str = "\\DST";
932
933 if (target->dat)
934 {
935 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
936 cell->children.back()->str = "\\EDGE_EN";
937
938 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
939 cell->children.back()->str = "\\EDGE_POL";
940
941 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
942 cell->children.back()->str = "\\DAT_DST_PEN";
943
944 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
945 cell->children.back()->str = "\\DAT_DST_POL";
946
947 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
948 cell->children.back()->str = "\\DAT";
949 }
950
951 delete oper;
952 delete target;
953 delete timing;
954 } |
955 TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' specify_triple specify_opt_triple ')' ';' {
956 if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
957 *$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
958 frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
959
960 AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
961 AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
962 AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
963
964 AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
965 AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
966 AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
967
968 specify_triple *limit = $11;
969 specify_triple *limit2 = $12;
970
971 AstNode *cell = new AstNode(AST_CELL);
972 ast_stack.back()->children.push_back(cell);
973 cell->str = stringf("$specify$%d", autoidx++);
974 cell->children.push_back(new AstNode(AST_CELLTYPE));
975 cell->children.back()->str = "$specrule";
976
977 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
978 cell->children.back()->str = "\\TYPE";
979
980 cell->children.push_back(new AstNode(AST_PARASET, limit->t_min));
981 cell->children.back()->str = "\\T_LIMIT_MIN";
982
983 cell->children.push_back(new AstNode(AST_PARASET, limit->t_avg));
984 cell->children.back()->str = "\\T_LIMIT_TYP";
985
986 cell->children.push_back(new AstNode(AST_PARASET, limit->t_max));
987 cell->children.back()->str = "\\T_LIMIT_MAX";
988
989 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_min : AstNode::mkconst_int(0, true)));
990 cell->children.back()->str = "\\T_LIMIT2_MIN";
991
992 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_avg : AstNode::mkconst_int(0, true)));
993 cell->children.back()->str = "\\T_LIMIT2_TYP";
994
995 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_max : AstNode::mkconst_int(0, true)));
996 cell->children.back()->str = "\\T_LIMIT2_MAX";
997
998 cell->children.push_back(new AstNode(AST_PARASET, src_pen));
999 cell->children.back()->str = "\\SRC_PEN";
1000
1001 cell->children.push_back(new AstNode(AST_PARASET, src_pol));
1002 cell->children.back()->str = "\\SRC_POL";
1003
1004 cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
1005 cell->children.back()->str = "\\DST_PEN";
1006
1007 cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
1008 cell->children.back()->str = "\\DST_POL";
1009
1010 cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
1011 cell->children.back()->str = "\\SRC_EN";
1012
1013 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
1014 cell->children.back()->str = "\\SRC";
1015
1016 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
1017 cell->children.back()->str = "\\DST_EN";
1018
1019 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
1020 cell->children.back()->str = "\\DST";
1021
1022 delete $1;
1023 };
1024
1025 specify_opt_triple:
1026 ',' specify_triple {
1027 $$ = $2;
1028 } |
1029 /* empty */ {
1030 $$ = nullptr;
1031 };
1032
1033 specify_if:
1034 TOK_IF '(' expr ')' {
1035 $$ = $3;
1036 } |
1037 /* empty */ {
1038 $$ = nullptr;
1039 };
1040
1041 specify_condition:
1042 TOK_SPECIFY_AND expr {
1043 $$ = $2;
1044 } |
1045 /* empty */ {
1046 $$ = nullptr;
1047 };
1048
1049 specify_target:
1050 expr {
1051 $$ = new specify_target;
1052 $$->polarity_op = 0;
1053 $$->dst = $1;
1054 $$->dat = nullptr;
1055 } |
1056 '(' expr ':' expr ')'{
1057 $$ = new specify_target;
1058 $$->polarity_op = 0;
1059 $$->dst = $2;
1060 $$->dat = $4;
1061 } |
1062 '(' expr TOK_NEG_INDEXED expr ')'{
1063 $$ = new specify_target;
1064 $$->polarity_op = '-';
1065 $$->dst = $2;
1066 $$->dat = $4;
1067 } |
1068 '(' expr TOK_POS_INDEXED expr ')'{
1069 $$ = new specify_target;
1070 $$->polarity_op = '+';
1071 $$->dst = $2;
1072 $$->dat = $4;
1073 };
1074
1075 specify_edge:
1076 TOK_POSEDGE { $$ = 'p'; } |
1077 TOK_NEGEDGE { $$ = 'n'; } |
1078 { $$ = 0; };
1079
1080 specify_rise_fall:
1081 specify_triple {
1082 $$ = new specify_rise_fall;
1083 $$->rise = *$1;
1084 $$->fall.t_min = $1->t_min->clone();
1085 $$->fall.t_avg = $1->t_avg->clone();
1086 $$->fall.t_max = $1->t_max->clone();
1087 delete $1;
1088 } |
1089 '(' specify_triple ',' specify_triple ')' {
1090 $$ = new specify_rise_fall;
1091 $$->rise = *$2;
1092 $$->fall = *$4;
1093 delete $2;
1094 delete $4;
1095 } |
1096 '(' specify_triple ',' specify_triple ',' specify_triple ')' {
1097 $$ = new specify_rise_fall;
1098 $$->rise = *$2;
1099 $$->fall = *$4;
1100 delete $2;
1101 delete $4;
1102 delete $6;
1103 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1104 } |
1105 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1106 $$ = new specify_rise_fall;
1107 $$->rise = *$2;
1108 $$->fall = *$4;
1109 delete $2;
1110 delete $4;
1111 delete $6;
1112 delete $8;
1113 delete $10;
1114 delete $12;
1115 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1116 } |
1117 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1118 $$ = new specify_rise_fall;
1119 $$->rise = *$2;
1120 $$->fall = *$4;
1121 delete $2;
1122 delete $4;
1123 delete $6;
1124 delete $8;
1125 delete $10;
1126 delete $12;
1127 delete $14;
1128 delete $16;
1129 delete $18;
1130 delete $20;
1131 delete $22;
1132 delete $24;
1133 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1134 }
1135
1136 specify_triple:
1137 expr {
1138 $$ = new specify_triple;
1139 $$->t_min = $1;
1140 $$->t_avg = $1->clone();
1141 $$->t_max = $1->clone();
1142 } |
1143 expr ':' expr ':' expr {
1144 $$ = new specify_triple;
1145 $$->t_min = $1;
1146 $$->t_avg = $3;
1147 $$->t_max = $5;
1148 };
1149
1150 /******************** ignored specify parser **************************/
1151
1152 ignored_specify_block:
1153 TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
1154 TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
1155
1156 ignored_specify_item_opt:
1157 ignored_specify_item_opt ignored_specify_item |
1158 ignored_specify_item ;
1159
1160 ignored_specify_item:
1161 specparam_declaration
1162 // | pulsestyle_declaration
1163 // | showcancelled_declaration
1164 | path_declaration
1165 | system_timing_declaration
1166 ;
1167
1168 specparam_declaration:
1169 TOK_SPECPARAM list_of_specparam_assignments ';' |
1170 TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ;
1171
1172 // IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match
1173 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
1174 // exxxxtending this for SV specparam would change this anyhow
1175 specparam_range:
1176 '[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
1177
1178 list_of_specparam_assignments:
1179 specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
1180
1181 specparam_assignment:
1182 ignspec_id '=' ignspec_expr ;
1183
1184 ignspec_opt_cond:
1185 TOK_IF '(' ignspec_expr ')' | /* empty */;
1186
1187 path_declaration :
1188 simple_path_declaration ';'
1189 // | edge_sensitive_path_declaration
1190 // | state_dependent_path_declaration
1191 ;
1192
1193 simple_path_declaration :
1194 ignspec_opt_cond parallel_path_description '=' path_delay_value |
1195 ignspec_opt_cond full_path_description '=' path_delay_value
1196 ;
1197
1198 path_delay_value :
1199 '(' ignspec_expr list_of_path_delay_extra_expressions ')'
1200 | ignspec_expr
1201 | ignspec_expr list_of_path_delay_extra_expressions
1202 ;
1203
1204 list_of_path_delay_extra_expressions :
1205 ',' ignspec_expr
1206 | ',' ignspec_expr list_of_path_delay_extra_expressions
1207 ;
1208
1209 specify_edge_identifier :
1210 TOK_POSEDGE | TOK_NEGEDGE ;
1211
1212 parallel_path_description :
1213 '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
1214 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
1215 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
1216
1217 full_path_description :
1218 '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
1219 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
1220 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
1221
1222 // This was broken into 2 rules to solve shift/reduce conflicts
1223 list_of_path_inputs :
1224 specify_input_terminal_descriptor opt_polarity_operator |
1225 specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
1226
1227 more_path_inputs :
1228 ',' specify_input_terminal_descriptor |
1229 more_path_inputs ',' specify_input_terminal_descriptor ;
1230
1231 list_of_path_outputs :
1232 specify_output_terminal_descriptor |
1233 list_of_path_outputs ',' specify_output_terminal_descriptor ;
1234
1235 opt_polarity_operator :
1236 '+'
1237 | '-'
1238 | ;
1239
1240 // Good enough for the time being
1241 specify_input_terminal_descriptor :
1242 ignspec_id ;
1243
1244 // Good enough for the time being
1245 specify_output_terminal_descriptor :
1246 ignspec_id ;
1247
1248 system_timing_declaration :
1249 ignspec_id '(' system_timing_args ')' ';' ;
1250
1251 system_timing_arg :
1252 TOK_POSEDGE ignspec_id |
1253 TOK_NEGEDGE ignspec_id |
1254 ignspec_expr ;
1255
1256 system_timing_args :
1257 system_timing_arg |
1258 system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
1259 system_timing_args ',' system_timing_arg ;
1260
1261 // for the time being this is OK, but we may write our own expr here.
1262 // as I'm not sure it is legal to use a full expr here (probably not)
1263 // On the other hand, other rules requiring constant expressions also use 'expr'
1264 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
1265 ignspec_constant_expression:
1266 expr { delete $1; };
1267
1268 ignspec_expr:
1269 expr { delete $1; } |
1270 expr ':' expr ':' expr {
1271 delete $1;
1272 delete $3;
1273 delete $5;
1274 };
1275
1276 ignspec_id:
1277 TOK_ID { delete $1; }
1278 range_or_multirange { delete $3; };
1279
1280 /**********************************************************************/
1281
1282 param_signed:
1283 TOK_SIGNED {
1284 astbuf1->is_signed = true;
1285 } | /* empty */;
1286
1287 param_integer:
1288 TOK_INTEGER {
1289 if (astbuf1->children.size() != 1)
1290 frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
1291 astbuf1->children.push_back(new AstNode(AST_RANGE));
1292 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
1293 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
1294 astbuf1->is_signed = true;
1295 } | /* empty */;
1296
1297 param_real:
1298 TOK_REAL {
1299 if (astbuf1->children.size() != 1)
1300 frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
1301 astbuf1->children.push_back(new AstNode(AST_REALVALUE));
1302 } | /* empty */;
1303
1304 param_range:
1305 range {
1306 if ($1 != NULL) {
1307 if (astbuf1->children.size() != 1)
1308 frontend_verilog_yyerror("integer/real parameters should not have a range.");
1309 astbuf1->children.push_back($1);
1310 }
1311 };
1312
1313 param_type:
1314 param_signed param_integer param_real param_range |
1315 hierarchical_type_id {
1316 astbuf1->is_custom_type = true;
1317 astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
1318 astbuf1->children.back()->str = *$1;
1319 };
1320
1321 param_decl:
1322 attr TOK_PARAMETER {
1323 astbuf1 = new AstNode(AST_PARAMETER);
1324 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1325 append_attr(astbuf1, $1);
1326 } param_type param_decl_list ';' {
1327 delete astbuf1;
1328 };
1329
1330 localparam_decl:
1331 attr TOK_LOCALPARAM {
1332 astbuf1 = new AstNode(AST_LOCALPARAM);
1333 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1334 append_attr(astbuf1, $1);
1335 } param_type param_decl_list ';' {
1336 delete astbuf1;
1337 };
1338
1339 param_decl_list:
1340 single_param_decl | param_decl_list ',' single_param_decl;
1341
1342 single_param_decl:
1343 TOK_ID '=' expr {
1344 AstNode *node;
1345 if (astbuf1 == nullptr) {
1346 if (!sv_mode)
1347 frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword");
1348 node = new AstNode(AST_PARAMETER);
1349 node->children.push_back(AstNode::mkconst_int(0, true));
1350 } else {
1351 node = astbuf1->clone();
1352 }
1353 node->str = *$1;
1354 delete node->children[0];
1355 node->children[0] = $3;
1356 ast_stack.back()->children.push_back(node);
1357 delete $1;
1358 };
1359
1360 defparam_decl:
1361 TOK_DEFPARAM defparam_decl_list ';';
1362
1363 defparam_decl_list:
1364 single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
1365
1366 single_defparam_decl:
1367 range rvalue '=' expr {
1368 AstNode *node = new AstNode(AST_DEFPARAM);
1369 node->children.push_back($2);
1370 node->children.push_back($4);
1371 if ($1 != NULL)
1372 node->children.push_back($1);
1373 ast_stack.back()->children.push_back(node);
1374 };
1375
1376 enum_type: TOK_ENUM {
1377 static int enum_count;
1378 // create parent node for the enum
1379 astbuf2 = new AstNode(AST_ENUM);
1380 ast_stack.back()->children.push_back(astbuf2);
1381 astbuf2->str = std::string("$enum");
1382 astbuf2->str += std::to_string(enum_count++);
1383 // create the template for the names
1384 astbuf1 = new AstNode(AST_ENUM_ITEM);
1385 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1386 } param_signed enum_base_type '{' enum_name_list '}' { // create template for the enum vars
1387 auto tnode = astbuf1->clone();
1388 delete astbuf1;
1389 astbuf1 = tnode;
1390 tnode->type = AST_WIRE;
1391 tnode->attributes["\\enum_type"] = AstNode::mkconst_str(astbuf2->str);
1392 // drop constant but keep any range
1393 delete tnode->children[0];
1394 tnode->children.erase(tnode->children.begin()); }
1395 ;
1396
1397 enum_base_type: int_vec param_range
1398 | int_atom
1399 | /* nothing */ {astbuf1->is_reg = true; addRange(astbuf1); }
1400 ;
1401
1402 int_atom: TOK_INTEGER {astbuf1->is_reg=true; addRange(astbuf1); } // probably should do byte, range [7:0] here
1403 ;
1404
1405 int_vec: TOK_REG {astbuf1->is_reg = true;}
1406 | TOK_LOGIC {astbuf1->is_logic = true;}
1407 ;
1408
1409 enum_name_list:
1410 enum_name_decl
1411 | enum_name_list ',' enum_name_decl
1412 ;
1413
1414 enum_name_decl:
1415 TOK_ID opt_enum_init {
1416 // put in fn
1417 log_assert(astbuf1);
1418 log_assert(astbuf2);
1419 auto node = astbuf1->clone();
1420 node->str = *$1;
1421 delete $1;
1422 delete node->children[0];
1423 node->children[0] = $2 ?: new AstNode(AST_NONE);
1424 astbuf2->children.push_back(node);
1425 }
1426 ;
1427
1428 opt_enum_init:
1429 '=' basic_expr { $$ = $2; } // TODO: restrict this
1430 | /* optional */ { $$ = NULL; }
1431 ;
1432
1433 enum_var_list:
1434 enum_var
1435 | enum_var_list ',' enum_var
1436 ;
1437
1438 enum_var: TOK_ID {
1439 log_assert(astbuf1);
1440 log_assert(astbuf2);
1441 auto node = astbuf1->clone();
1442 ast_stack.back()->children.push_back(node);
1443 node->str = *$1;
1444 delete $1;
1445 node->is_enum = true;
1446 }
1447 ;
1448
1449 enum_decl: enum_type enum_var_list ';' {
1450 //enum_type creates astbuf1 for use by typedef only
1451 delete astbuf1;
1452 }
1453 ;
1454
1455 wire_decl:
1456 attr wire_type range {
1457 albuf = $1;
1458 astbuf1 = $2;
1459 astbuf2 = $3;
1460 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
1461 if (astbuf2) {
1462 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
1463 } else {
1464 astbuf2 = new AstNode(AST_RANGE);
1465 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
1466 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
1467 }
1468 }
1469 if (astbuf2 && astbuf2->children.size() != 2)
1470 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
1471 } delay wire_name_list {
1472 delete astbuf1;
1473 if (astbuf2 != NULL)
1474 delete astbuf2;
1475 free_attr(albuf);
1476 } ';' |
1477 attr TOK_SUPPLY0 TOK_ID {
1478 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1479 ast_stack.back()->children.back()->str = *$3;
1480 append_attr(ast_stack.back()->children.back(), $1);
1481 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
1482 ast_stack.back()->children.back()->children[0]->str = *$3;
1483 delete $3;
1484 } opt_supply_wires ';' |
1485 attr TOK_SUPPLY1 TOK_ID {
1486 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1487 ast_stack.back()->children.back()->str = *$3;
1488 append_attr(ast_stack.back()->children.back(), $1);
1489 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
1490 ast_stack.back()->children.back()->children[0]->str = *$3;
1491 delete $3;
1492 } opt_supply_wires ';';
1493
1494 opt_supply_wires:
1495 /* empty */ |
1496 opt_supply_wires ',' TOK_ID {
1497 AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
1498 AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
1499 wire_node->str = *$3;
1500 assign_node->children[0]->str = *$3;
1501 ast_stack.back()->children.push_back(wire_node);
1502 ast_stack.back()->children.push_back(assign_node);
1503 delete $3;
1504 };
1505
1506 wire_name_list:
1507 wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
1508
1509 wire_name_and_opt_assign:
1510 wire_name {
1511 bool attr_anyconst = false;
1512 bool attr_anyseq = false;
1513 bool attr_allconst = false;
1514 bool attr_allseq = false;
1515 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
1516 delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
1517 ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
1518 attr_anyconst = true;
1519 }
1520 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
1521 delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
1522 ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
1523 attr_anyseq = true;
1524 }
1525 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
1526 delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
1527 ast_stack.back()->children.back()->attributes.erase(ID::allconst);
1528 attr_allconst = true;
1529 }
1530 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
1531 delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
1532 ast_stack.back()->children.back()->attributes.erase(ID::allseq);
1533 attr_allseq = true;
1534 }
1535 if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
1536 AstNode *wire = new AstNode(AST_IDENTIFIER);
1537 AstNode *fcall = new AstNode(AST_FCALL);
1538 wire->str = ast_stack.back()->children.back()->str;
1539 fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
1540 if (attr_anyconst)
1541 fcall->str = "\\$anyconst";
1542 if (attr_anyseq)
1543 fcall->str = "\\$anyseq";
1544 if (attr_allconst)
1545 fcall->str = "\\$allconst";
1546 if (attr_allseq)
1547 fcall->str = "\\$allseq";
1548 fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
1549 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
1550 }
1551 } |
1552 wire_name '=' expr {
1553 AstNode *wire = new AstNode(AST_IDENTIFIER);
1554 wire->str = ast_stack.back()->children.back()->str;
1555 if (astbuf1->is_input) {
1556 if (astbuf1->attributes.count(ID::defaultvalue))
1557 delete astbuf1->attributes.at(ID::defaultvalue);
1558 astbuf1->attributes[ID::defaultvalue] = $3;
1559 }
1560 else if (astbuf1->is_reg || astbuf1->is_logic){
1561 AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
1562 AstNode *block = new AstNode(AST_BLOCK, assign);
1563 AstNode *init = new AstNode(AST_INITIAL, block);
1564
1565 SET_AST_NODE_LOC(assign, @1, @3);
1566 SET_AST_NODE_LOC(block, @1, @3);
1567 SET_AST_NODE_LOC(init, @1, @3);
1568
1569 ast_stack.back()->children.push_back(init);
1570 }
1571 else {
1572 AstNode *assign = new AstNode(AST_ASSIGN, wire, $3);
1573 SET_AST_NODE_LOC(assign, @1, @3);
1574 ast_stack.back()->children.push_back(assign);
1575 }
1576
1577 };
1578
1579 wire_name:
1580 TOK_ID range_or_multirange {
1581 if (astbuf1 == nullptr)
1582 frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node.");
1583 AstNode *node = astbuf1->clone();
1584 node->str = *$1;
1585 append_attr_clone(node, albuf);
1586 if (astbuf2 != NULL)
1587 node->children.push_back(astbuf2->clone());
1588 if ($2 != NULL) {
1589 if (node->is_input || node->is_output)
1590 frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
1591 if (!astbuf2 && !node->is_custom_type) {
1592 AstNode *rng = new AstNode(AST_RANGE);
1593 rng->children.push_back(AstNode::mkconst_int(0, true));
1594 rng->children.push_back(AstNode::mkconst_int(0, true));
1595 node->children.push_back(rng);
1596 }
1597 node->type = AST_MEMORY;
1598 auto *rangeNode = $2;
1599 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
1600 // SV array size [n], rewrite as [n-1:0]
1601 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
1602 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
1603 }
1604 node->children.push_back(rangeNode);
1605 }
1606 if (current_function_or_task == NULL) {
1607 if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
1608 port_stubs[*$1] = ++port_counter;
1609 }
1610 if (port_stubs.count(*$1) != 0) {
1611 if (!node->is_input && !node->is_output)
1612 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
1613 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
1614 frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
1615 node->port_id = port_stubs[*$1];
1616 port_stubs.erase(*$1);
1617 } else {
1618 if (node->is_input || node->is_output)
1619 frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
1620 }
1621 } else {
1622 if (node->is_input || node->is_output)
1623 node->port_id = current_function_or_task_port_id++;
1624 }
1625 //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
1626 SET_AST_NODE_LOC(node, @1, @1);
1627 ast_stack.back()->children.push_back(node);
1628
1629 delete $1;
1630 };
1631
1632 assign_stmt:
1633 TOK_ASSIGN delay assign_expr_list ';';
1634
1635 assign_expr_list:
1636 assign_expr | assign_expr_list ',' assign_expr;
1637
1638 assign_expr:
1639 lvalue '=' expr {
1640 AstNode *node = new AstNode(AST_ASSIGN, $1, $3);
1641 SET_AST_NODE_LOC(node, @$, @$);
1642 ast_stack.back()->children.push_back(node);
1643 };
1644
1645 type_name: TOK_ID // first time seen
1646 | TOK_USER_TYPE { if (isInLocalScope($1)) frontend_verilog_yyerror("Duplicate declaration of TYPEDEF '%s'", $1->c_str()+1); }
1647 ;
1648
1649 typedef_decl:
1650 TOK_TYPEDEF wire_type range type_name range_or_multirange ';' {
1651 astbuf1 = $2;
1652 astbuf2 = $3;
1653 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
1654 if (astbuf2) {
1655 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
1656 } else {
1657 astbuf2 = new AstNode(AST_RANGE);
1658 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
1659 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
1660 }
1661 }
1662 if (astbuf2 && astbuf2->children.size() != 2)
1663 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
1664 if (astbuf2)
1665 astbuf1->children.push_back(astbuf2);
1666
1667 if ($5 != NULL) {
1668 if (!astbuf2) {
1669 AstNode *rng = new AstNode(AST_RANGE);
1670 rng->children.push_back(AstNode::mkconst_int(0, true));
1671 rng->children.push_back(AstNode::mkconst_int(0, true));
1672 astbuf1->children.push_back(rng);
1673 }
1674 astbuf1->type = AST_MEMORY;
1675 auto *rangeNode = $5;
1676 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
1677 // SV array size [n], rewrite as [n-1:0]
1678 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
1679 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
1680 }
1681 astbuf1->children.push_back(rangeNode);
1682 }
1683 addTypedefNode($4, astbuf1);
1684 } |
1685 TOK_TYPEDEF enum_type type_name ';' {
1686 addTypedefNode($3, astbuf1);
1687 }
1688 ;
1689
1690 cell_stmt:
1691 attr TOK_ID {
1692 astbuf1 = new AstNode(AST_CELL);
1693 append_attr(astbuf1, $1);
1694 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
1695 astbuf1->children[0]->str = *$2;
1696 delete $2;
1697 } cell_parameter_list_opt cell_list ';' {
1698 delete astbuf1;
1699 } |
1700 attr tok_prim_wrapper delay {
1701 astbuf1 = new AstNode(AST_PRIMITIVE);
1702 astbuf1->str = *$2;
1703 append_attr(astbuf1, $1);
1704 delete $2;
1705 } prim_list ';' {
1706 delete astbuf1;
1707 };
1708
1709 tok_prim_wrapper:
1710 TOK_PRIMITIVE {
1711 $$ = $1;
1712 } |
1713 TOK_OR {
1714 $$ = new std::string("or");
1715 };
1716
1717 cell_list:
1718 single_cell |
1719 cell_list ',' single_cell;
1720
1721 single_cell:
1722 TOK_ID {
1723 astbuf2 = astbuf1->clone();
1724 if (astbuf2->type != AST_PRIMITIVE)
1725 astbuf2->str = *$1;
1726 delete $1;
1727 ast_stack.back()->children.push_back(astbuf2);
1728 } '(' cell_port_list ')' {
1729 SET_AST_NODE_LOC(astbuf2, @1, @$);
1730 } |
1731 TOK_ID non_opt_range {
1732 astbuf2 = astbuf1->clone();
1733 if (astbuf2->type != AST_PRIMITIVE)
1734 astbuf2->str = *$1;
1735 delete $1;
1736 ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
1737 } '(' cell_port_list ')'{
1738 SET_AST_NODE_LOC(astbuf2, @1, @$);
1739 };
1740
1741 prim_list:
1742 single_prim |
1743 prim_list ',' single_prim;
1744
1745 single_prim:
1746 single_cell |
1747 /* no name */ {
1748 astbuf2 = astbuf1->clone();
1749 ast_stack.back()->children.push_back(astbuf2);
1750 } '(' cell_port_list ')';
1751
1752 cell_parameter_list_opt:
1753 '#' '(' cell_parameter_list ')' | /* empty */;
1754
1755 cell_parameter_list:
1756 cell_parameter | cell_parameter_list ',' cell_parameter;
1757
1758 cell_parameter:
1759 /* empty */ |
1760 expr {
1761 AstNode *node = new AstNode(AST_PARASET);
1762 astbuf1->children.push_back(node);
1763 node->children.push_back($1);
1764 } |
1765 '.' TOK_ID '(' expr ')' {
1766 AstNode *node = new AstNode(AST_PARASET);
1767 node->str = *$2;
1768 astbuf1->children.push_back(node);
1769 node->children.push_back($4);
1770 delete $2;
1771 };
1772
1773 cell_port_list:
1774 cell_port_list_rules {
1775 // remove empty args from end of list
1776 while (!astbuf2->children.empty()) {
1777 AstNode *node = astbuf2->children.back();
1778 if (node->type != AST_ARGUMENT) break;
1779 if (!node->children.empty()) break;
1780 if (!node->str.empty()) break;
1781 astbuf2->children.pop_back();
1782 delete node;
1783 }
1784
1785 // check port types
1786 bool has_positional_args = false;
1787 bool has_named_args = false;
1788 for (auto node : astbuf2->children) {
1789 if (node->type != AST_ARGUMENT) continue;
1790 if (node->str.empty())
1791 has_positional_args = true;
1792 else
1793 has_named_args = true;
1794 }
1795
1796 if (has_positional_args && has_named_args)
1797 frontend_verilog_yyerror("Mix of positional and named cell ports.");
1798 };
1799
1800 cell_port_list_rules:
1801 cell_port | cell_port_list_rules ',' cell_port;
1802
1803 cell_port:
1804 attr {
1805 AstNode *node = new AstNode(AST_ARGUMENT);
1806 astbuf2->children.push_back(node);
1807 free_attr($1);
1808 } |
1809 attr expr {
1810 AstNode *node = new AstNode(AST_ARGUMENT);
1811 astbuf2->children.push_back(node);
1812 node->children.push_back($2);
1813 free_attr($1);
1814 } |
1815 attr '.' TOK_ID '(' expr ')' {
1816 AstNode *node = new AstNode(AST_ARGUMENT);
1817 node->str = *$3;
1818 astbuf2->children.push_back(node);
1819 node->children.push_back($5);
1820 delete $3;
1821 free_attr($1);
1822 } |
1823 attr '.' TOK_ID '(' ')' {
1824 AstNode *node = new AstNode(AST_ARGUMENT);
1825 node->str = *$3;
1826 astbuf2->children.push_back(node);
1827 delete $3;
1828 free_attr($1);
1829 } |
1830 attr '.' TOK_ID {
1831 AstNode *node = new AstNode(AST_ARGUMENT);
1832 node->str = *$3;
1833 astbuf2->children.push_back(node);
1834 node->children.push_back(new AstNode(AST_IDENTIFIER));
1835 node->children.back()->str = *$3;
1836 delete $3;
1837 free_attr($1);
1838 } |
1839 attr TOK_WILDCARD_CONNECT {
1840 if (!sv_mode)
1841 frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
1842 astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
1843 };
1844
1845 always_comb_or_latch:
1846 TOK_ALWAYS_COMB {
1847 $$ = false;
1848 } |
1849 TOK_ALWAYS_LATCH {
1850 $$ = true;
1851 };
1852
1853 always_or_always_ff:
1854 TOK_ALWAYS {
1855 $$ = false;
1856 } |
1857 TOK_ALWAYS_FF {
1858 $$ = true;
1859 };
1860
1861 always_stmt:
1862 attr always_or_always_ff {
1863 AstNode *node = new AstNode(AST_ALWAYS);
1864 append_attr(node, $1);
1865 if ($2)
1866 node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
1867 ast_stack.back()->children.push_back(node);
1868 ast_stack.push_back(node);
1869 } always_cond {
1870 AstNode *block = new AstNode(AST_BLOCK);
1871 ast_stack.back()->children.push_back(block);
1872 ast_stack.push_back(block);
1873 } behavioral_stmt {
1874 SET_AST_NODE_LOC(ast_stack.back(), @6, @6);
1875 ast_stack.pop_back();
1876
1877 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
1878 ast_stack.pop_back();
1879
1880 SET_RULE_LOC(@$, @2, @$);
1881 } |
1882 attr always_comb_or_latch {
1883 AstNode *node = new AstNode(AST_ALWAYS);
1884 append_attr(node, $1);
1885 if ($2)
1886 node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
1887 else
1888 node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
1889 ast_stack.back()->children.push_back(node);
1890 ast_stack.push_back(node);
1891 AstNode *block = new AstNode(AST_BLOCK);
1892 ast_stack.back()->children.push_back(block);
1893 ast_stack.push_back(block);
1894 } behavioral_stmt {
1895 ast_stack.pop_back();
1896 ast_stack.pop_back();
1897 } |
1898 attr TOK_INITIAL {
1899 AstNode *node = new AstNode(AST_INITIAL);
1900 append_attr(node, $1);
1901 ast_stack.back()->children.push_back(node);
1902 ast_stack.push_back(node);
1903 AstNode *block = new AstNode(AST_BLOCK);
1904 ast_stack.back()->children.push_back(block);
1905 ast_stack.push_back(block);
1906 } behavioral_stmt {
1907 ast_stack.pop_back();
1908 ast_stack.pop_back();
1909 };
1910
1911 always_cond:
1912 '@' '(' always_events ')' |
1913 '@' '(' '*' ')' |
1914 '@' ATTR_BEGIN ')' |
1915 '@' '(' ATTR_END |
1916 '@' '*' |
1917 /* empty */;
1918
1919 always_events:
1920 always_event |
1921 always_events TOK_OR always_event |
1922 always_events ',' always_event;
1923
1924 always_event:
1925 TOK_POSEDGE expr {
1926 AstNode *node = new AstNode(AST_POSEDGE);
1927 SET_AST_NODE_LOC(node, @1, @1);
1928 ast_stack.back()->children.push_back(node);
1929 node->children.push_back($2);
1930 } |
1931 TOK_NEGEDGE expr {
1932 AstNode *node = new AstNode(AST_NEGEDGE);
1933 SET_AST_NODE_LOC(node, @1, @1);
1934 ast_stack.back()->children.push_back(node);
1935 node->children.push_back($2);
1936 } |
1937 expr {
1938 AstNode *node = new AstNode(AST_EDGE);
1939 ast_stack.back()->children.push_back(node);
1940 node->children.push_back($1);
1941 };
1942
1943 opt_label:
1944 ':' TOK_ID {
1945 $$ = $2;
1946 } |
1947 /* empty */ {
1948 $$ = NULL;
1949 };
1950
1951 opt_sva_label:
1952 TOK_SVA_LABEL ':' {
1953 $$ = $1;
1954 } |
1955 /* empty */ {
1956 $$ = NULL;
1957 };
1958
1959 opt_property:
1960 TOK_PROPERTY {
1961 $$ = true;
1962 } |
1963 TOK_FINAL {
1964 $$ = false;
1965 } |
1966 /* empty */ {
1967 $$ = false;
1968 };
1969
1970 modport_stmt:
1971 TOK_MODPORT TOK_ID {
1972 AstNode *modport = new AstNode(AST_MODPORT);
1973 ast_stack.back()->children.push_back(modport);
1974 ast_stack.push_back(modport);
1975 modport->str = *$2;
1976 delete $2;
1977 } modport_args_opt {
1978 ast_stack.pop_back();
1979 log_assert(ast_stack.size() == 2);
1980 } ';'
1981
1982 modport_args_opt:
1983 '(' ')' | '(' modport_args optional_comma ')';
1984
1985 modport_args:
1986 modport_arg | modport_args ',' modport_arg;
1987
1988 modport_arg:
1989 modport_type_token modport_member |
1990 modport_member
1991
1992 modport_member:
1993 TOK_ID {
1994 AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
1995 ast_stack.back()->children.push_back(modport_member);
1996 modport_member->str = *$1;
1997 modport_member->is_input = current_modport_input;
1998 modport_member->is_output = current_modport_output;
1999 delete $1;
2000 }
2001
2002 modport_type_token:
2003 TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
2004
2005 assert:
2006 opt_sva_label TOK_ASSERT opt_property '(' expr ')' ';' {
2007 if (noassert_mode) {
2008 delete $5;
2009 } else {
2010 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2011 SET_AST_NODE_LOC(node, @1, @6);
2012 if ($1 != nullptr)
2013 node->str = *$1;
2014 ast_stack.back()->children.push_back(node);
2015 }
2016 if ($1 != nullptr)
2017 delete $1;
2018 } |
2019 opt_sva_label TOK_ASSUME opt_property '(' expr ')' ';' {
2020 if (noassume_mode) {
2021 delete $5;
2022 } else {
2023 AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
2024 SET_AST_NODE_LOC(node, @1, @6);
2025 if ($1 != nullptr)
2026 node->str = *$1;
2027 ast_stack.back()->children.push_back(node);
2028 }
2029 if ($1 != nullptr)
2030 delete $1;
2031 } |
2032 opt_sva_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2033 if (noassert_mode) {
2034 delete $6;
2035 } else {
2036 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2037 SET_AST_NODE_LOC(node, @1, @7);
2038 if ($1 != nullptr)
2039 node->str = *$1;
2040 ast_stack.back()->children.push_back(node);
2041 }
2042 if ($1 != nullptr)
2043 delete $1;
2044 } |
2045 opt_sva_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2046 if (noassume_mode) {
2047 delete $6;
2048 } else {
2049 AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
2050 SET_AST_NODE_LOC(node, @1, @7);
2051 if ($1 != nullptr)
2052 node->str = *$1;
2053 ast_stack.back()->children.push_back(node);
2054 }
2055 if ($1 != nullptr)
2056 delete $1;
2057 } |
2058 opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
2059 AstNode *node = new AstNode(AST_COVER, $5);
2060 SET_AST_NODE_LOC(node, @1, @6);
2061 if ($1 != nullptr) {
2062 node->str = *$1;
2063 delete $1;
2064 }
2065 ast_stack.back()->children.push_back(node);
2066 } |
2067 opt_sva_label TOK_COVER opt_property '(' ')' ';' {
2068 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2069 SET_AST_NODE_LOC(node, @1, @5);
2070 if ($1 != nullptr) {
2071 node->str = *$1;
2072 delete $1;
2073 }
2074 ast_stack.back()->children.push_back(node);
2075 } |
2076 opt_sva_label TOK_COVER ';' {
2077 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2078 SET_AST_NODE_LOC(node, @1, @2);
2079 if ($1 != nullptr) {
2080 node->str = *$1;
2081 delete $1;
2082 }
2083 ast_stack.back()->children.push_back(node);
2084 } |
2085 opt_sva_label TOK_RESTRICT opt_property '(' expr ')' ';' {
2086 if (norestrict_mode) {
2087 delete $5;
2088 } else {
2089 AstNode *node = new AstNode(AST_ASSUME, $5);
2090 SET_AST_NODE_LOC(node, @1, @6);
2091 if ($1 != nullptr)
2092 node->str = *$1;
2093 ast_stack.back()->children.push_back(node);
2094 }
2095 if (!$3)
2096 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2097 if ($1 != nullptr)
2098 delete $1;
2099 } |
2100 opt_sva_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2101 if (norestrict_mode) {
2102 delete $6;
2103 } else {
2104 AstNode *node = new AstNode(AST_FAIR, $6);
2105 SET_AST_NODE_LOC(node, @1, @7);
2106 if ($1 != nullptr)
2107 node->str = *$1;
2108 ast_stack.back()->children.push_back(node);
2109 }
2110 if (!$3)
2111 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2112 if ($1 != nullptr)
2113 delete $1;
2114 };
2115
2116 assert_property:
2117 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
2118 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2119 SET_AST_NODE_LOC(node, @1, @6);
2120 ast_stack.back()->children.push_back(node);
2121 if ($1 != nullptr) {
2122 ast_stack.back()->children.back()->str = *$1;
2123 delete $1;
2124 }
2125 } |
2126 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
2127 AstNode *node = new AstNode(AST_ASSUME, $5);
2128 SET_AST_NODE_LOC(node, @1, @6);
2129 ast_stack.back()->children.push_back(node);
2130 if ($1 != nullptr) {
2131 ast_stack.back()->children.back()->str = *$1;
2132 delete $1;
2133 }
2134 } |
2135 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2136 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2137 SET_AST_NODE_LOC(node, @1, @7);
2138 ast_stack.back()->children.push_back(node);
2139 if ($1 != nullptr) {
2140 ast_stack.back()->children.back()->str = *$1;
2141 delete $1;
2142 }
2143 } |
2144 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2145 AstNode *node = new AstNode(AST_FAIR, $6);
2146 SET_AST_NODE_LOC(node, @1, @7);
2147 ast_stack.back()->children.push_back(node);
2148 if ($1 != nullptr) {
2149 ast_stack.back()->children.back()->str = *$1;
2150 delete $1;
2151 }
2152 } |
2153 opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
2154 AstNode *node = new AstNode(AST_COVER, $5);
2155 SET_AST_NODE_LOC(node, @1, @6);
2156 ast_stack.back()->children.push_back(node);
2157 if ($1 != nullptr) {
2158 ast_stack.back()->children.back()->str = *$1;
2159 delete $1;
2160 }
2161 } |
2162 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
2163 if (norestrict_mode) {
2164 delete $5;
2165 } else {
2166 AstNode *node = new AstNode(AST_ASSUME, $5);
2167 SET_AST_NODE_LOC(node, @1, @6);
2168 ast_stack.back()->children.push_back(node);
2169 if ($1 != nullptr) {
2170 ast_stack.back()->children.back()->str = *$1;
2171 delete $1;
2172 }
2173 }
2174 } |
2175 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2176 if (norestrict_mode) {
2177 delete $6;
2178 } else {
2179 AstNode *node = new AstNode(AST_FAIR, $6);
2180 SET_AST_NODE_LOC(node, @1, @7);
2181 ast_stack.back()->children.push_back(node);
2182 if ($1 != nullptr) {
2183 ast_stack.back()->children.back()->str = *$1;
2184 delete $1;
2185 }
2186 }
2187 };
2188
2189 simple_behavioral_stmt:
2190 lvalue '=' delay expr {
2191 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4);
2192 ast_stack.back()->children.push_back(node);
2193 SET_AST_NODE_LOC(node, @1, @4);
2194 } |
2195 lvalue TOK_INCREMENT {
2196 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true)));
2197 ast_stack.back()->children.push_back(node);
2198 SET_AST_NODE_LOC(node, @1, @2);
2199 } |
2200 lvalue TOK_DECREMENT {
2201 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true)));
2202 ast_stack.back()->children.push_back(node);
2203 SET_AST_NODE_LOC(node, @1, @2);
2204 } |
2205 lvalue OP_LE delay expr {
2206 AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4);
2207 ast_stack.back()->children.push_back(node);
2208 SET_AST_NODE_LOC(node, @1, @4);
2209 };
2210
2211 // this production creates the obligatory if-else shift/reduce conflict
2212 behavioral_stmt:
2213 defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
2214 non_opt_delay behavioral_stmt |
2215 simple_behavioral_stmt ';' | ';' |
2216 hierarchical_id attr {
2217 AstNode *node = new AstNode(AST_TCALL);
2218 node->str = *$1;
2219 delete $1;
2220 ast_stack.back()->children.push_back(node);
2221 ast_stack.push_back(node);
2222 append_attr(node, $2);
2223 } opt_arg_list ';'{
2224 ast_stack.pop_back();
2225 } |
2226 TOK_MSG_TASKS attr {
2227 AstNode *node = new AstNode(AST_TCALL);
2228 node->str = *$1;
2229 delete $1;
2230 ast_stack.back()->children.push_back(node);
2231 ast_stack.push_back(node);
2232 append_attr(node, $2);
2233 } opt_arg_list ';'{
2234 ast_stack.pop_back();
2235 } |
2236 attr TOK_BEGIN {
2237 enterTypeScope();
2238 } opt_label {
2239 AstNode *node = new AstNode(AST_BLOCK);
2240 ast_stack.back()->children.push_back(node);
2241 ast_stack.push_back(node);
2242 append_attr(node, $1);
2243 if ($4 != NULL)
2244 node->str = *$4;
2245 } behavioral_stmt_list TOK_END opt_label {
2246 exitTypeScope();
2247 if ($4 != NULL && $8 != NULL && *$4 != *$8)
2248 frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
2249 SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
2250 delete $4;
2251 delete $8;
2252 ast_stack.pop_back();
2253 } |
2254 attr TOK_FOR '(' {
2255 AstNode *node = new AstNode(AST_FOR);
2256 ast_stack.back()->children.push_back(node);
2257 ast_stack.push_back(node);
2258 append_attr(node, $1);
2259 } simple_behavioral_stmt ';' expr {
2260 ast_stack.back()->children.push_back($7);
2261 } ';' simple_behavioral_stmt ')' {
2262 AstNode *block = new AstNode(AST_BLOCK);
2263 ast_stack.back()->children.push_back(block);
2264 ast_stack.push_back(block);
2265 } behavioral_stmt {
2266 SET_AST_NODE_LOC(ast_stack.back(), @13, @13);
2267 ast_stack.pop_back();
2268 SET_AST_NODE_LOC(ast_stack.back(), @2, @13);
2269 ast_stack.pop_back();
2270 } |
2271 attr TOK_WHILE '(' expr ')' {
2272 AstNode *node = new AstNode(AST_WHILE);
2273 ast_stack.back()->children.push_back(node);
2274 ast_stack.push_back(node);
2275 append_attr(node, $1);
2276 AstNode *block = new AstNode(AST_BLOCK);
2277 ast_stack.back()->children.push_back($4);
2278 ast_stack.back()->children.push_back(block);
2279 ast_stack.push_back(block);
2280 } behavioral_stmt {
2281 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2282 ast_stack.pop_back();
2283 ast_stack.pop_back();
2284 } |
2285 attr TOK_REPEAT '(' expr ')' {
2286 AstNode *node = new AstNode(AST_REPEAT);
2287 ast_stack.back()->children.push_back(node);
2288 ast_stack.push_back(node);
2289 append_attr(node, $1);
2290 AstNode *block = new AstNode(AST_BLOCK);
2291 ast_stack.back()->children.push_back($4);
2292 ast_stack.back()->children.push_back(block);
2293 ast_stack.push_back(block);
2294 } behavioral_stmt {
2295 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2296 ast_stack.pop_back();
2297 ast_stack.pop_back();
2298 } |
2299 attr TOK_IF '(' expr ')' {
2300 AstNode *node = new AstNode(AST_CASE);
2301 AstNode *block = new AstNode(AST_BLOCK);
2302 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
2303 SET_AST_NODE_LOC(cond, @4, @4);
2304 ast_stack.back()->children.push_back(node);
2305 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
2306 node->children.push_back(cond);
2307 ast_stack.push_back(node);
2308 ast_stack.push_back(block);
2309 append_attr(node, $1);
2310 } behavioral_stmt {
2311 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2312 } optional_else {
2313 ast_stack.pop_back();
2314 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2315 ast_stack.pop_back();
2316 } |
2317 case_attr case_type '(' expr ')' {
2318 AstNode *node = new AstNode(AST_CASE, $4);
2319 ast_stack.back()->children.push_back(node);
2320 ast_stack.push_back(node);
2321 append_attr(node, $1);
2322 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2323 } opt_synopsys_attr case_body TOK_ENDCASE {
2324 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2325 case_type_stack.pop_back();
2326 ast_stack.pop_back();
2327 };
2328
2329 ;
2330
2331 unique_case_attr:
2332 /* empty */ {
2333 $$ = false;
2334 } |
2335 TOK_PRIORITY case_attr {
2336 $$ = $2;
2337 } |
2338 TOK_UNIQUE case_attr {
2339 $$ = true;
2340 };
2341
2342 case_attr:
2343 attr unique_case_attr {
2344 if ($2) (*$1)["\\parallel_case"] = AstNode::mkconst_int(1, false);
2345 $$ = $1;
2346 };
2347
2348 case_type:
2349 TOK_CASE {
2350 case_type_stack.push_back(0);
2351 } |
2352 TOK_CASEX {
2353 case_type_stack.push_back('x');
2354 } |
2355 TOK_CASEZ {
2356 case_type_stack.push_back('z');
2357 };
2358
2359 opt_synopsys_attr:
2360 opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
2361 if (ast_stack.back()->attributes.count(ID::full_case) == 0)
2362 ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
2363 } |
2364 opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
2365 if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
2366 ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
2367 } |
2368 /* empty */;
2369
2370 behavioral_stmt_list:
2371 behavioral_stmt_list behavioral_stmt |
2372 /* empty */;
2373
2374 optional_else:
2375 TOK_ELSE {
2376 AstNode *block = new AstNode(AST_BLOCK);
2377 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
2378 SET_AST_NODE_LOC(cond, @1, @1);
2379
2380 ast_stack.pop_back();
2381 ast_stack.back()->children.push_back(cond);
2382 ast_stack.push_back(block);
2383 } behavioral_stmt {
2384 SET_AST_NODE_LOC(ast_stack.back(), @3, @3);
2385 } |
2386 /* empty */ %prec FAKE_THEN;
2387
2388 case_body:
2389 case_body case_item |
2390 /* empty */;
2391
2392 case_item:
2393 {
2394 AstNode *node = new AstNode(
2395 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2396 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2397 ast_stack.back()->children.push_back(node);
2398 ast_stack.push_back(node);
2399 } case_select {
2400 AstNode *block = new AstNode(AST_BLOCK);
2401 ast_stack.back()->children.push_back(block);
2402 ast_stack.push_back(block);
2403 case_type_stack.push_back(0);
2404 } behavioral_stmt {
2405 case_type_stack.pop_back();
2406 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2407 ast_stack.pop_back();
2408 ast_stack.pop_back();
2409 };
2410
2411 gen_case_body:
2412 gen_case_body gen_case_item |
2413 /* empty */;
2414
2415 gen_case_item:
2416 {
2417 AstNode *node = new AstNode(
2418 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2419 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2420 ast_stack.back()->children.push_back(node);
2421 ast_stack.push_back(node);
2422 } case_select {
2423 case_type_stack.push_back(0);
2424 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2425 } gen_stmt_or_null {
2426 case_type_stack.pop_back();
2427 ast_stack.pop_back();
2428 };
2429
2430 case_select:
2431 case_expr_list ':' |
2432 TOK_DEFAULT;
2433
2434 case_expr_list:
2435 TOK_DEFAULT {
2436 AstNode *node = new AstNode(AST_DEFAULT);
2437 SET_AST_NODE_LOC(node, @1, @1);
2438 ast_stack.back()->children.push_back(node);
2439 } |
2440 TOK_SVA_LABEL {
2441 AstNode *node = new AstNode(AST_IDENTIFIER);
2442 SET_AST_NODE_LOC(node, @1, @1);
2443 ast_stack.back()->children.push_back(node);
2444 ast_stack.back()->children.back()->str = *$1;
2445 delete $1;
2446 } |
2447 expr {
2448 ast_stack.back()->children.push_back($1);
2449 } |
2450 case_expr_list ',' expr {
2451 ast_stack.back()->children.push_back($3);
2452 };
2453
2454 rvalue:
2455 hierarchical_id '[' expr ']' '.' rvalue {
2456 $$ = new AstNode(AST_PREFIX, $3, $6);
2457 $$->str = *$1;
2458 delete $1;
2459 } |
2460 hierarchical_id range {
2461 $$ = new AstNode(AST_IDENTIFIER, $2);
2462 $$->str = *$1;
2463 SET_AST_NODE_LOC($$, @1, @1);
2464 delete $1;
2465 if ($2 == nullptr && ($$->str == "\\$initstate" ||
2466 $$->str == "\\$anyconst" || $$->str == "\\$anyseq" ||
2467 $$->str == "\\$allconst" || $$->str == "\\$allseq"))
2468 $$->type = AST_FCALL;
2469 } |
2470 hierarchical_id non_opt_multirange {
2471 $$ = new AstNode(AST_IDENTIFIER, $2);
2472 $$->str = *$1;
2473 SET_AST_NODE_LOC($$, @1, @1);
2474 delete $1;
2475 };
2476
2477 lvalue:
2478 rvalue {
2479 $$ = $1;
2480 } |
2481 '{' lvalue_concat_list '}' {
2482 $$ = $2;
2483 };
2484
2485 lvalue_concat_list:
2486 expr {
2487 $$ = new AstNode(AST_CONCAT);
2488 $$->children.push_back($1);
2489 } |
2490 expr ',' lvalue_concat_list {
2491 $$ = $3;
2492 $$->children.push_back($1);
2493 };
2494
2495 opt_arg_list:
2496 '(' arg_list optional_comma ')' |
2497 /* empty */;
2498
2499 arg_list:
2500 arg_list2 |
2501 /* empty */;
2502
2503 arg_list2:
2504 single_arg |
2505 arg_list ',' single_arg;
2506
2507 single_arg:
2508 expr {
2509 ast_stack.back()->children.push_back($1);
2510 };
2511
2512 module_gen_body:
2513 module_gen_body gen_stmt_or_module_body_stmt |
2514 /* empty */;
2515
2516 gen_stmt_or_module_body_stmt:
2517 gen_stmt | module_body_stmt;
2518
2519 // this production creates the obligatory if-else shift/reduce conflict
2520 gen_stmt:
2521 TOK_FOR '(' {
2522 AstNode *node = new AstNode(AST_GENFOR);
2523 ast_stack.back()->children.push_back(node);
2524 ast_stack.push_back(node);
2525 } simple_behavioral_stmt ';' expr {
2526 ast_stack.back()->children.push_back($6);
2527 } ';' simple_behavioral_stmt ')' gen_stmt_block {
2528 SET_AST_NODE_LOC(ast_stack.back(), @1, @11);
2529 ast_stack.pop_back();
2530 } |
2531 TOK_IF '(' expr ')' {
2532 AstNode *node = new AstNode(AST_GENIF);
2533 ast_stack.back()->children.push_back(node);
2534 ast_stack.push_back(node);
2535 ast_stack.back()->children.push_back($3);
2536 } gen_stmt_block opt_gen_else {
2537 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2538 ast_stack.pop_back();
2539 } |
2540 case_type '(' expr ')' {
2541 AstNode *node = new AstNode(AST_GENCASE, $3);
2542 ast_stack.back()->children.push_back(node);
2543 ast_stack.push_back(node);
2544 } gen_case_body TOK_ENDCASE {
2545 case_type_stack.pop_back();
2546 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2547 ast_stack.pop_back();
2548 } |
2549 TOK_BEGIN {
2550 enterTypeScope();
2551 } opt_label {
2552 AstNode *node = new AstNode(AST_GENBLOCK);
2553 node->str = $3 ? *$3 : std::string();
2554 ast_stack.back()->children.push_back(node);
2555 ast_stack.push_back(node);
2556 } module_gen_body TOK_END opt_label {
2557 exitTypeScope();
2558 delete $3;
2559 delete $7;
2560 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2561 ast_stack.pop_back();
2562 } |
2563 TOK_MSG_TASKS {
2564 AstNode *node = new AstNode(AST_TECALL);
2565 node->str = *$1;
2566 delete $1;
2567 ast_stack.back()->children.push_back(node);
2568 ast_stack.push_back(node);
2569 } opt_arg_list ';'{
2570 SET_AST_NODE_LOC(ast_stack.back(), @1, @3);
2571 ast_stack.pop_back();
2572 };
2573
2574 gen_stmt_block:
2575 {
2576 AstNode *node = new AstNode(AST_GENBLOCK);
2577 ast_stack.back()->children.push_back(node);
2578 ast_stack.push_back(node);
2579 } gen_stmt_or_module_body_stmt {
2580 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2581 ast_stack.pop_back();
2582 };
2583
2584 gen_stmt_or_null:
2585 gen_stmt_block | ';';
2586
2587 opt_gen_else:
2588 TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
2589
2590 expr:
2591 basic_expr {
2592 $$ = $1;
2593 } |
2594 basic_expr '?' attr expr ':' expr {
2595 $$ = new AstNode(AST_TERNARY);
2596 $$->children.push_back($1);
2597 $$->children.push_back($4);
2598 $$->children.push_back($6);
2599 SET_AST_NODE_LOC($$, @1, @$);
2600 append_attr($$, $3);
2601 };
2602
2603 basic_expr:
2604 rvalue {
2605 $$ = $1;
2606 } |
2607 '(' expr ')' integral_number {
2608 if ($4->compare(0, 1, "'") != 0)
2609 frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
2610 AstNode *bits = $2;
2611 AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2612 if (val == NULL)
2613 log_error("Value conversion failed: `%s'\n", $4->c_str());
2614 $$ = new AstNode(AST_TO_BITS, bits, val);
2615 delete $4;
2616 } |
2617 hierarchical_id integral_number {
2618 if ($2->compare(0, 1, "'") != 0)
2619 frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
2620 AstNode *bits = new AstNode(AST_IDENTIFIER);
2621 bits->str = *$1;
2622 SET_AST_NODE_LOC(bits, @1, @1);
2623 AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2624 SET_AST_NODE_LOC(val, @2, @2);
2625 if (val == NULL)
2626 log_error("Value conversion failed: `%s'\n", $2->c_str());
2627 $$ = new AstNode(AST_TO_BITS, bits, val);
2628 delete $1;
2629 delete $2;
2630 } |
2631 integral_number {
2632 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2633 SET_AST_NODE_LOC($$, @1, @1);
2634 if ($$ == NULL)
2635 log_error("Value conversion failed: `%s'\n", $1->c_str());
2636 delete $1;
2637 } |
2638 TOK_REALVAL {
2639 $$ = new AstNode(AST_REALVALUE);
2640 char *p = (char*)malloc(GetSize(*$1) + 1), *q;
2641 for (int i = 0, j = 0; j < GetSize(*$1); j++)
2642 if ((*$1)[j] != '_')
2643 p[i++] = (*$1)[j], p[i] = 0;
2644 $$->realvalue = strtod(p, &q);
2645 SET_AST_NODE_LOC($$, @1, @1);
2646 log_assert(*q == 0);
2647 delete $1;
2648 free(p);
2649 } |
2650 TOK_STRING {
2651 $$ = AstNode::mkconst_str(*$1);
2652 SET_AST_NODE_LOC($$, @1, @1);
2653 delete $1;
2654 } |
2655 hierarchical_id attr {
2656 AstNode *node = new AstNode(AST_FCALL);
2657 node->str = *$1;
2658 delete $1;
2659 ast_stack.push_back(node);
2660 SET_AST_NODE_LOC(node, @1, @1);
2661 append_attr(node, $2);
2662 } '(' arg_list optional_comma ')' {
2663 $$ = ast_stack.back();
2664 ast_stack.pop_back();
2665 } |
2666 TOK_TO_SIGNED attr '(' expr ')' {
2667 $$ = new AstNode(AST_TO_SIGNED, $4);
2668 append_attr($$, $2);
2669 } |
2670 TOK_TO_UNSIGNED attr '(' expr ')' {
2671 $$ = new AstNode(AST_TO_UNSIGNED, $4);
2672 append_attr($$, $2);
2673 } |
2674 '(' expr ')' {
2675 $$ = $2;
2676 } |
2677 '(' expr ':' expr ':' expr ')' {
2678 delete $2;
2679 $$ = $4;
2680 delete $6;
2681 } |
2682 '{' concat_list '}' {
2683 $$ = $2;
2684 } |
2685 '{' expr '{' concat_list '}' '}' {
2686 $$ = new AstNode(AST_REPLICATE, $2, $4);
2687 } |
2688 '~' attr basic_expr %prec UNARY_OPS {
2689 $$ = new AstNode(AST_BIT_NOT, $3);
2690 SET_AST_NODE_LOC($$, @1, @3);
2691 append_attr($$, $2);
2692 } |
2693 basic_expr '&' attr basic_expr {
2694 $$ = new AstNode(AST_BIT_AND, $1, $4);
2695 SET_AST_NODE_LOC($$, @1, @4);
2696 append_attr($$, $3);
2697 } |
2698 basic_expr OP_NAND attr basic_expr {
2699 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
2700 SET_AST_NODE_LOC($$, @1, @4);
2701 append_attr($$, $3);
2702 } |
2703 basic_expr '|' attr basic_expr {
2704 $$ = new AstNode(AST_BIT_OR, $1, $4);
2705 SET_AST_NODE_LOC($$, @1, @4);
2706 append_attr($$, $3);
2707 } |
2708 basic_expr OP_NOR attr basic_expr {
2709 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
2710 SET_AST_NODE_LOC($$, @1, @4);
2711 append_attr($$, $3);
2712 } |
2713 basic_expr '^' attr basic_expr {
2714 $$ = new AstNode(AST_BIT_XOR, $1, $4);
2715 SET_AST_NODE_LOC($$, @1, @4);
2716 append_attr($$, $3);
2717 } |
2718 basic_expr OP_XNOR attr basic_expr {
2719 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
2720 SET_AST_NODE_LOC($$, @1, @4);
2721 append_attr($$, $3);
2722 } |
2723 '&' attr basic_expr %prec UNARY_OPS {
2724 $$ = new AstNode(AST_REDUCE_AND, $3);
2725 SET_AST_NODE_LOC($$, @1, @3);
2726 append_attr($$, $2);
2727 } |
2728 OP_NAND attr basic_expr %prec UNARY_OPS {
2729 $$ = new AstNode(AST_REDUCE_AND, $3);
2730 SET_AST_NODE_LOC($$, @1, @3);
2731 append_attr($$, $2);
2732 $$ = new AstNode(AST_LOGIC_NOT, $$);
2733 } |
2734 '|' attr basic_expr %prec UNARY_OPS {
2735 $$ = new AstNode(AST_REDUCE_OR, $3);
2736 SET_AST_NODE_LOC($$, @1, @3);
2737 append_attr($$, $2);
2738 } |
2739 OP_NOR attr basic_expr %prec UNARY_OPS {
2740 $$ = new AstNode(AST_REDUCE_OR, $3);
2741 SET_AST_NODE_LOC($$, @1, @3);
2742 append_attr($$, $2);
2743 $$ = new AstNode(AST_LOGIC_NOT, $$);
2744 SET_AST_NODE_LOC($$, @1, @3);
2745 } |
2746 '^' attr basic_expr %prec UNARY_OPS {
2747 $$ = new AstNode(AST_REDUCE_XOR, $3);
2748 SET_AST_NODE_LOC($$, @1, @3);
2749 append_attr($$, $2);
2750 } |
2751 OP_XNOR attr basic_expr %prec UNARY_OPS {
2752 $$ = new AstNode(AST_REDUCE_XNOR, $3);
2753 SET_AST_NODE_LOC($$, @1, @3);
2754 append_attr($$, $2);
2755 } |
2756 basic_expr OP_SHL attr basic_expr {
2757 $$ = new AstNode(AST_SHIFT_LEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2758 SET_AST_NODE_LOC($$, @1, @4);
2759 append_attr($$, $3);
2760 } |
2761 basic_expr OP_SHR attr basic_expr {
2762 $$ = new AstNode(AST_SHIFT_RIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2763 SET_AST_NODE_LOC($$, @1, @4);
2764 append_attr($$, $3);
2765 } |
2766 basic_expr OP_SSHL attr basic_expr {
2767 $$ = new AstNode(AST_SHIFT_SLEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2768 SET_AST_NODE_LOC($$, @1, @4);
2769 append_attr($$, $3);
2770 } |
2771 basic_expr OP_SSHR attr basic_expr {
2772 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2773 SET_AST_NODE_LOC($$, @1, @4);
2774 append_attr($$, $3);
2775 } |
2776 basic_expr '<' attr basic_expr {
2777 $$ = new AstNode(AST_LT, $1, $4);
2778 SET_AST_NODE_LOC($$, @1, @4);
2779 append_attr($$, $3);
2780 } |
2781 basic_expr OP_LE attr basic_expr {
2782 $$ = new AstNode(AST_LE, $1, $4);
2783 SET_AST_NODE_LOC($$, @1, @4);
2784 append_attr($$, $3);
2785 } |
2786 basic_expr OP_EQ attr basic_expr {
2787 $$ = new AstNode(AST_EQ, $1, $4);
2788 SET_AST_NODE_LOC($$, @1, @4);
2789 append_attr($$, $3);
2790 } |
2791 basic_expr OP_NE attr basic_expr {
2792 $$ = new AstNode(AST_NE, $1, $4);
2793 SET_AST_NODE_LOC($$, @1, @4);
2794 append_attr($$, $3);
2795 } |
2796 basic_expr OP_EQX attr basic_expr {
2797 $$ = new AstNode(AST_EQX, $1, $4);
2798 SET_AST_NODE_LOC($$, @1, @4);
2799 append_attr($$, $3);
2800 } |
2801 basic_expr OP_NEX attr basic_expr {
2802 $$ = new AstNode(AST_NEX, $1, $4);
2803 SET_AST_NODE_LOC($$, @1, @4);
2804 append_attr($$, $3);
2805 } |
2806 basic_expr OP_GE attr basic_expr {
2807 $$ = new AstNode(AST_GE, $1, $4);
2808 SET_AST_NODE_LOC($$, @1, @4);
2809 append_attr($$, $3);
2810 } |
2811 basic_expr '>' attr basic_expr {
2812 $$ = new AstNode(AST_GT, $1, $4);
2813 SET_AST_NODE_LOC($$, @1, @4);
2814 append_attr($$, $3);
2815 } |
2816 basic_expr '+' attr basic_expr {
2817 $$ = new AstNode(AST_ADD, $1, $4);
2818 SET_AST_NODE_LOC($$, @1, @4);
2819 append_attr($$, $3);
2820 } |
2821 basic_expr '-' attr basic_expr {
2822 $$ = new AstNode(AST_SUB, $1, $4);
2823 SET_AST_NODE_LOC($$, @1, @4);
2824 append_attr($$, $3);
2825 } |
2826 basic_expr '*' attr basic_expr {
2827 $$ = new AstNode(AST_MUL, $1, $4);
2828 SET_AST_NODE_LOC($$, @1, @4);
2829 append_attr($$, $3);
2830 } |
2831 basic_expr '/' attr basic_expr {
2832 $$ = new AstNode(AST_DIV, $1, $4);
2833 SET_AST_NODE_LOC($$, @1, @4);
2834 append_attr($$, $3);
2835 } |
2836 basic_expr '%' attr basic_expr {
2837 $$ = new AstNode(AST_MOD, $1, $4);
2838 SET_AST_NODE_LOC($$, @1, @4);
2839 append_attr($$, $3);
2840 } |
2841 basic_expr OP_POW attr basic_expr {
2842 $$ = new AstNode(AST_POW, $1, $4);
2843 SET_AST_NODE_LOC($$, @1, @4);
2844 append_attr($$, $3);
2845 } |
2846 '+' attr basic_expr %prec UNARY_OPS {
2847 $$ = new AstNode(AST_POS, $3);
2848 SET_AST_NODE_LOC($$, @1, @3);
2849 append_attr($$, $2);
2850 } |
2851 '-' attr basic_expr %prec UNARY_OPS {
2852 $$ = new AstNode(AST_NEG, $3);
2853 SET_AST_NODE_LOC($$, @1, @3);
2854 append_attr($$, $2);
2855 } |
2856 basic_expr OP_LAND attr basic_expr {
2857 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
2858 SET_AST_NODE_LOC($$, @1, @4);
2859 append_attr($$, $3);
2860 } |
2861 basic_expr OP_LOR attr basic_expr {
2862 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
2863 SET_AST_NODE_LOC($$, @1, @4);
2864 append_attr($$, $3);
2865 } |
2866 '!' attr basic_expr %prec UNARY_OPS {
2867 $$ = new AstNode(AST_LOGIC_NOT, $3);
2868 SET_AST_NODE_LOC($$, @1, @3);
2869 append_attr($$, $2);
2870 };
2871
2872 concat_list:
2873 expr {
2874 $$ = new AstNode(AST_CONCAT, $1);
2875 } |
2876 expr ',' concat_list {
2877 $$ = $3;
2878 $$->children.push_back($1);
2879 };
2880
2881 integral_number:
2882 TOK_CONSTVAL { $$ = $1; } |
2883 TOK_UNBASED_UNSIZED_CONSTVAL { $$ = $1; } |
2884 TOK_BASE TOK_BASED_CONSTVAL {
2885 $1->append(*$2);
2886 $$ = $1;
2887 delete $2;
2888 } |
2889 TOK_CONSTVAL TOK_BASE TOK_BASED_CONSTVAL {
2890 $1->append(*$2).append(*$3);
2891 $$ = $1;
2892 delete $2;
2893 delete $3;
2894 };