2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The Verilog frontend.
22 * This frontend is using the AST frontend library (see frontends/ast/).
23 * Thus this frontend does not generate RTLIL code directly but creates an
24 * AST directly from the Verilog parse tree and then passes this AST to
25 * the AST frontend library.
29 * This is the actual bison parser for Verilog code. The AST ist created directly
30 * from the bison reduce functions here. Note that this code uses a few global
31 * variables to hold the state of the AST generator and therefore this parser is
40 #include "frontends/verilog/verilog_frontend.h"
41 #include "frontends/verilog/verilog_parser.tab.hh"
42 #include "kernel/log.h"
44 #define YYLEX_PARAM &yylval, &yylloc
48 using namespace VERILOG_FRONTEND;
51 namespace VERILOG_FRONTEND {
53 dict<std::string, int> port_stubs;
54 dict<IdString, AstNode*> *attr_list, default_attr_list;
55 std::stack<dict<IdString, AstNode*> *> attr_list_stack;
56 dict<IdString, AstNode*> *albuf;
57 std::vector<UserTypeMap*> user_type_stack;
58 dict<std::string, AstNode*> pkg_user_types;
59 std::vector<AstNode*> ast_stack;
60 struct AstNode *astbuf1, *astbuf2, *astbuf3;
61 struct AstNode *current_function_or_task;
62 struct AstNode *current_ast, *current_ast_mod;
63 int current_function_or_task_port_id;
64 std::vector<char> case_type_stack;
65 bool do_not_require_port_stubs;
66 bool default_nettype_wire;
67 bool sv_mode, formal_mode, lib_mode, specify_mode;
68 bool noassert_mode, noassume_mode, norestrict_mode;
69 bool assume_asserts_mode, assert_assumes_mode;
70 bool current_wire_rand, current_wire_const;
71 bool current_modport_input, current_modport_output;
76 #define SET_AST_NODE_LOC(WHICH, BEGIN, END) \
77 do { (WHICH)->location.first_line = (BEGIN).first_line; \
78 (WHICH)->location.first_column = (BEGIN).first_column; \
79 (WHICH)->location.last_line = (END).last_line; \
80 (WHICH)->location.last_column = (END).last_column; } while(0)
82 #define SET_RULE_LOC(LHS, BEGIN, END) \
83 do { (LHS).first_line = (BEGIN).first_line; \
84 (LHS).first_column = (BEGIN).first_column; \
85 (LHS).last_line = (END).last_line; \
86 (LHS).last_column = (END).last_column; } while(0)
88 int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
90 static void append_attr(AstNode *ast, dict<IdString, AstNode*> *al)
92 for (auto &it : *al) {
93 if (ast->attributes.count(it.first) > 0)
94 delete ast->attributes[it.first];
95 ast->attributes[it.first] = it.second;
100 static void append_attr_clone(AstNode *ast, dict<IdString, AstNode*> *al)
102 for (auto &it : *al) {
103 if (ast->attributes.count(it.first) > 0)
104 delete ast->attributes[it.first];
105 ast->attributes[it.first] = it.second->clone();
109 static void free_attr(dict<IdString, AstNode*> *al)
116 struct specify_target {
121 struct specify_triple {
122 AstNode *t_min, *t_avg, *t_max;
125 struct specify_rise_fall {
130 static void addTypedefNode(std::string *name, AstNode *node)
133 auto *tnode = new AstNode(AST_TYPEDEF, node);
135 auto user_types = user_type_stack.back();
136 (*user_types)[*name] = tnode;
137 if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {
138 // typedef inside a package so we need the qualified name
139 auto qname = current_ast_mod->str + "::" + (*name).substr(1);
140 pkg_user_types[qname] = tnode;
143 ast_stack.back()->children.push_back(tnode);
146 static void enterTypeScope()
148 auto user_types = new UserTypeMap();
149 user_type_stack.push_back(user_types);
152 static void exitTypeScope()
154 user_type_stack.pop_back();
157 static bool isInLocalScope(const std::string *name)
159 // tests if a name was declared in the current block scope
160 auto user_types = user_type_stack.back();
161 return (user_types->count(*name) > 0);
164 static AstNode *getTypeDefinitionNode(std::string type_name)
166 // return the definition nodes from the typedef statement
167 auto user_types = user_type_stack.back();
168 log_assert(user_types->count(type_name) > 0);
169 auto typedef_node = (*user_types)[type_name];
170 log_assert(typedef_node->type == AST_TYPEDEF);
171 return typedef_node->children[0];
174 static AstNode *copyTypeDefinition(std::string type_name)
176 // return a copy of the template from a typedef definition
177 auto typedef_node = getTypeDefinitionNode(type_name);
178 return typedef_node->clone();
181 static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
183 auto range = new AstNode(AST_RANGE);
184 range->children.push_back(AstNode::mkconst_int(msb, true));
185 range->children.push_back(AstNode::mkconst_int(lsb, true));
186 range->is_signed = isSigned;
190 static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned = true)
192 auto range = makeRange(msb, lsb, isSigned);
193 parent->children.push_back(range);
196 static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
198 if (type_node->range_left >= 0 && type_node->range_right >= 0) {
199 // type already restricts the range
201 frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
204 range_node = makeRange(type_node->range_left, type_node->range_right, false);
207 if (range_node && range_node->children.size() != 2) {
208 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
213 static void rewriteRange(AstNode *rangeNode)
215 if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
216 // SV array size [n], rewrite as [n-1:0]
217 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
218 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
222 static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
224 node->type = AST_MEMORY;
225 if (rangeNode->type == AST_MULTIRANGE) {
226 for (auto *itr : rangeNode->children)
229 rewriteRange(rangeNode);
230 node->children.push_back(rangeNode);
235 %define api.prefix {frontend_verilog_yy}
238 /* The union is defined in the header, so we need to provide all the
239 * includes it requires
244 #include "frontends/verilog/verilog_frontend.h"
249 struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
250 YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
251 struct specify_target *specify_target_ptr;
252 struct specify_triple *specify_triple_ptr;
253 struct specify_rise_fall *specify_rise_fall_ptr;
258 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
259 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
260 %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL
261 %token <string> TOK_USER_TYPE TOK_PKG_USER_TYPE
262 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
263 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
264 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
265 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
266 %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
267 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
268 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_PLUS_ASSIGN TOK_ALWAYS TOK_INITIAL
269 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
270 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
271 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
272 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
273 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
274 %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
275 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
276 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
277 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
278 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
279 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
280 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
281 %token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_UNION
282 %token TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AND_ASSIGN TOK_SUB_ASSIGN
284 %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
285 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list non_io_wire_type io_wire_type
286 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
287 %type <string> type_name
288 %type <ast> opt_enum_init enum_type struct_type non_wire_data_type
289 %type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
290 %type <al> attr case_attr
291 %type <ast> struct_union
293 %type <specify_target_ptr> specify_target
294 %type <specify_triple_ptr> specify_triple specify_opt_triple
295 %type <specify_rise_fall_ptr> specify_rise_fall
296 %type <ast> specify_if specify_condition
297 %type <ch> specify_edge
299 // operator precedence from low to high
305 %left OP_EQ OP_NE OP_EQX OP_NEX
306 %left '<' OP_LE OP_GE '>'
307 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
312 %precedence UNARY_OPS
314 %define parse.error verbose
315 %define parse.lac full
317 %precedence FAKE_THEN
327 ast_stack.push_back(current_ast);
329 ast_stack.pop_back();
330 log_assert(GetSize(ast_stack) == 0);
331 for (auto &it : default_attr_list)
333 default_attr_list.clear();
339 task_func_decl design |
341 localparam_decl design |
342 typedef_decl design |
349 if (attr_list != nullptr)
350 attr_list_stack.push(attr_list);
351 attr_list = new dict<IdString, AstNode*>;
352 for (auto &it : default_attr_list)
353 (*attr_list)[it.first] = it.second->clone();
356 if (!attr_list_stack.empty()) {
357 attr_list = attr_list_stack.top();
358 attr_list_stack.pop();
364 attr_opt ATTR_BEGIN opt_attr_list ATTR_END {
365 SET_RULE_LOC(@$, @2, @$);
371 if (attr_list != nullptr)
372 attr_list_stack.push(attr_list);
373 attr_list = new dict<IdString, AstNode*>;
374 for (auto &it : default_attr_list)
376 default_attr_list.clear();
378 attr_list->swap(default_attr_list);
380 if (!attr_list_stack.empty()) {
381 attr_list = attr_list_stack.top();
382 attr_list_stack.pop();
392 attr_list ',' attr_assign;
396 if (attr_list->count(*$1) != 0)
397 delete (*attr_list)[*$1];
398 (*attr_list)[*$1] = AstNode::mkconst_int(1, false);
401 hierarchical_id '=' expr {
402 if (attr_list->count(*$1) != 0)
403 delete (*attr_list)[*$1];
404 (*attr_list)[*$1] = $3;
412 hierarchical_id TOK_PACKAGESEP TOK_ID {
413 if ($3->compare(0, 1, "\\") == 0)
414 *$1 += "::" + $3->substr(1);
420 hierarchical_id '.' TOK_ID {
421 if ($3->compare(0, 1, "\\") == 0)
422 *$1 += "." + $3->substr(1);
429 hierarchical_type_id:
431 | TOK_PKG_USER_TYPE // package qualified type name
432 | '(' TOK_USER_TYPE ')' { $$ = $2; } // non-standard grammar
439 do_not_require_port_stubs = false;
440 AstNode *mod = new AstNode(AST_MODULE);
441 ast_stack.back()->children.push_back(mod);
442 ast_stack.push_back(mod);
443 current_ast_mod = mod;
447 append_attr(mod, $1);
449 } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE opt_label {
450 if (port_stubs.size() != 0)
451 frontend_verilog_yyerror("Missing details for module port `%s'.",
452 port_stubs.begin()->first.c_str());
453 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
454 ast_stack.pop_back();
455 log_assert(ast_stack.size() == 1);
456 current_ast_mod = NULL;
461 '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | %empty;
464 single_module_para | module_para_list ',' single_module_para;
469 if (astbuf1) delete astbuf1;
470 astbuf1 = new AstNode(AST_PARAMETER);
471 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
472 append_attr(astbuf1, $1);
473 } param_type single_param_decl |
474 attr TOK_LOCALPARAM {
475 if (astbuf1) delete astbuf1;
476 astbuf1 = new AstNode(AST_LOCALPARAM);
477 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
478 append_attr(astbuf1, $1);
479 } param_type single_param_decl |
483 '(' ')' | %empty | '(' module_args optional_comma ')';
486 module_arg | module_args ',' module_arg;
491 module_arg_opt_assignment:
493 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
494 AstNode *wire = new AstNode(AST_IDENTIFIER);
495 wire->str = ast_stack.back()->children.back()->str;
496 if (ast_stack.back()->children.back()->is_input) {
497 AstNode *n = ast_stack.back()->children.back();
498 if (n->attributes.count(ID::defaultvalue))
499 delete n->attributes.at(ID::defaultvalue);
500 n->attributes[ID::defaultvalue] = $2;
502 if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
503 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
505 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
507 frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
513 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
514 AstNode *node = ast_stack.back()->children.back()->clone();
516 node->port_id = ++port_counter;
517 ast_stack.back()->children.push_back(node);
518 SET_AST_NODE_LOC(node, @1, @1);
520 if (port_stubs.count(*$1) != 0)
521 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
522 port_stubs[*$1] = ++port_counter;
525 } module_arg_opt_assignment |
527 astbuf1 = new AstNode(AST_INTERFACEPORT);
528 astbuf1->children.push_back(new AstNode(AST_INTERFACEPORTTYPE));
529 astbuf1->children[0]->str = *$1;
531 } TOK_ID { /* SV interfaces */
533 frontend_verilog_yyerror("Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
534 astbuf2 = astbuf1->clone(); // really only needed if multiple instances of same type.
537 astbuf2->port_id = ++port_counter;
538 ast_stack.back()->children.push_back(astbuf2);
539 delete astbuf1; // really only needed if multiple instances of same type.
540 } module_arg_opt_assignment |
541 attr wire_type range TOK_ID {
544 SET_AST_NODE_LOC(node, @4, @4);
545 node->port_id = ++port_counter;
547 node->children.push_back($3);
548 if (!node->is_input && !node->is_output)
549 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
550 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
551 frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
552 ast_stack.back()->children.push_back(node);
553 append_attr(node, $1);
555 } module_arg_opt_assignment |
557 do_not_require_port_stubs = true;
564 AstNode *mod = new AstNode(AST_PACKAGE);
565 ast_stack.back()->children.push_back(mod);
566 ast_stack.push_back(mod);
567 current_ast_mod = mod;
569 append_attr(mod, $1);
570 } ';' package_body TOK_ENDPACKAGE opt_label {
571 ast_stack.pop_back();
572 current_ast_mod = NULL;
577 package_body package_body_stmt | %empty;
580 typedef_decl | localparam_decl | param_decl;
586 do_not_require_port_stubs = false;
587 AstNode *intf = new AstNode(AST_INTERFACE);
588 ast_stack.back()->children.push_back(intf);
589 ast_stack.push_back(intf);
590 current_ast_mod = intf;
595 } module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
596 if (port_stubs.size() != 0)
597 frontend_verilog_yyerror("Missing details for module port `%s'.",
598 port_stubs.begin()->first.c_str());
599 ast_stack.pop_back();
600 log_assert(ast_stack.size() == 1);
601 current_ast_mod = NULL;
606 interface_body interface_body_stmt | %empty;
609 param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
613 '#' TOK_ID { delete $2; } |
614 '#' TOK_CONSTVAL { delete $2; } |
615 '#' TOK_REALVAL { delete $2; } |
616 '#' '(' expr ')' { delete $3; } |
617 '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
620 non_opt_delay | %empty;
623 { astbuf3 = new AstNode(AST_WIRE); current_wire_rand = false; current_wire_const = false; }
624 wire_type_token_io wire_type_const_rand opt_wire_type_token wire_type_signedness
625 { $$ = astbuf3; SET_RULE_LOC(@$, @2, @$); };
628 { astbuf3 = new AstNode(AST_WIRE); current_wire_rand = false; current_wire_const = false; }
629 wire_type_const_rand wire_type_token wire_type_signedness
630 { $$ = astbuf3; SET_RULE_LOC(@$, @2, @$); };
638 astbuf3->is_input = true;
641 astbuf3->is_output = true;
644 astbuf3->is_input = true;
645 astbuf3->is_output = true;
648 wire_type_signedness:
649 TOK_SIGNED { astbuf3->is_signed = true; } |
650 TOK_UNSIGNED { astbuf3->is_signed = false; } |
653 wire_type_const_rand:
655 current_wire_rand = true;
656 current_wire_const = true;
659 current_wire_const = true;
662 current_wire_rand = true;
667 wire_type_token | %empty;
670 hierarchical_type_id {
671 astbuf3->is_custom_type = true;
672 astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
673 astbuf3->children.back()->str = *$1;
676 astbuf3->is_wor = true;
679 astbuf3->is_wand = true;
684 TOK_WIRE logic_type {
688 astbuf3->is_reg = true;
691 astbuf3->is_reg = true;
695 astbuf3->is_logic = true;
698 astbuf3->is_logic = true;
701 astbuf3->is_logic = true;
704 astbuf3->type = AST_GENVAR;
705 astbuf3->is_reg = true;
706 astbuf3->is_signed = true;
707 astbuf3->range_left = 31;
708 astbuf3->range_right = 0;
715 astbuf3->range_left = 31;
716 astbuf3->range_right = 0;
717 astbuf3->is_signed = true;
721 '[' expr ':' expr ']' {
722 $$ = new AstNode(AST_RANGE);
723 $$->children.push_back($2);
724 $$->children.push_back($4);
726 '[' expr TOK_POS_INDEXED expr ']' {
727 $$ = new AstNode(AST_RANGE);
728 AstNode *expr = new AstNode(AST_SELFSZ, $2);
729 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
730 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
732 '[' expr TOK_NEG_INDEXED expr ']' {
733 $$ = new AstNode(AST_RANGE);
734 AstNode *expr = new AstNode(AST_SELFSZ, $2);
735 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
736 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
739 $$ = new AstNode(AST_RANGE);
740 $$->children.push_back($2);
744 non_opt_range non_opt_range {
745 $$ = new AstNode(AST_MULTIRANGE, $1, $2);
747 non_opt_multirange non_opt_range {
749 $$->children.push_back($2);
762 non_opt_multirange { $$ = $1; };
766 | TOK_INTEGER { $$ = makeRange(); }
770 module_body module_body_stmt |
771 /* the following line makes the generate..endgenrate keywords optional */
772 module_body gen_stmt |
773 module_body gen_block |
778 task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
779 enum_decl | struct_decl |
780 always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
783 TOK_CHECKER TOK_ID ';' {
784 AstNode *node = new AstNode(AST_GENBLOCK);
786 ast_stack.back()->children.push_back(node);
787 ast_stack.push_back(node);
788 } module_body TOK_ENDCHECKER {
790 ast_stack.pop_back();
794 attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
795 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
796 current_function_or_task->str = *$4;
797 append_attr(current_function_or_task, $1);
798 ast_stack.back()->children.push_back(current_function_or_task);
801 } opt_dpi_function_args ';' {
802 current_function_or_task = NULL;
804 attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
805 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
806 current_function_or_task->str = *$6;
807 append_attr(current_function_or_task, $1);
808 ast_stack.back()->children.push_back(current_function_or_task);
812 } opt_dpi_function_args ';' {
813 current_function_or_task = NULL;
815 attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
816 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
817 current_function_or_task->str = *$8;
818 append_attr(current_function_or_task, $1);
819 ast_stack.back()->children.push_back(current_function_or_task);
824 } opt_dpi_function_args ';' {
825 current_function_or_task = NULL;
827 attr TOK_TASK opt_automatic TOK_ID {
828 current_function_or_task = new AstNode(AST_TASK);
829 current_function_or_task->str = *$4;
830 append_attr(current_function_or_task, $1);
831 ast_stack.back()->children.push_back(current_function_or_task);
832 ast_stack.push_back(current_function_or_task);
833 current_function_or_task_port_id = 1;
835 } task_func_args_opt ';' task_func_body TOK_ENDTASK {
836 current_function_or_task = NULL;
837 ast_stack.pop_back();
839 attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID {
840 current_function_or_task = new AstNode(AST_FUNCTION);
841 current_function_or_task->str = *$6;
842 append_attr(current_function_or_task, $1);
843 ast_stack.back()->children.push_back(current_function_or_task);
844 ast_stack.push_back(current_function_or_task);
845 AstNode *outreg = new AstNode(AST_WIRE);
847 outreg->is_signed = $4;
848 outreg->is_reg = true;
850 outreg->children.push_back($5);
851 outreg->is_signed = $4 || $5->is_signed;
852 $5->is_signed = false;
854 current_function_or_task->children.push_back(outreg);
855 current_function_or_task_port_id = 1;
857 } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
858 current_function_or_task = NULL;
859 ast_stack.pop_back();
864 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
869 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
873 opt_dpi_function_args:
874 '(' dpi_function_args ')' |
878 dpi_function_args ',' dpi_function_arg |
879 dpi_function_args ',' |
896 '(' ')' | %empty | '(' {
900 } task_func_args optional_comma {
908 task_func_port | task_func_args ',' task_func_port;
911 attr wire_type range {
912 bool prev_was_input = true;
913 bool prev_was_output = false;
915 prev_was_input = astbuf1->is_input;
916 prev_was_output = astbuf1->is_output;
924 astbuf2 = checkRange(astbuf1, $3);
925 if (!astbuf1->is_input && !astbuf1->is_output) {
927 frontend_verilog_yyerror("task/function argument direction missing");
928 astbuf1->is_input = prev_was_input;
929 astbuf1->is_output = prev_was_output;
935 frontend_verilog_yyerror("task/function argument direction missing");
936 albuf = new dict<IdString, AstNode*>;
937 astbuf1 = new AstNode(AST_WIRE);
938 current_wire_rand = false;
939 current_wire_const = false;
940 astbuf1->is_input = true;
946 task_func_body behavioral_stmt |
949 /*************************** specify parser ***************************/
952 TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
955 specify_item specify_item_list |
959 specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
960 AstNode *en_expr = $1;
961 char specify_edge = $3;
962 AstNode *src_expr = $4;
964 specify_target *target = $6;
965 specify_rise_fall *timing = $9;
967 if (specify_edge != 0 && target->dat == nullptr)
968 frontend_verilog_yyerror("Found specify edge but no data spec.\n");
970 AstNode *cell = new AstNode(AST_CELL);
971 ast_stack.back()->children.push_back(cell);
972 cell->str = stringf("$specify$%d", autoidx++);
973 cell->children.push_back(new AstNode(AST_CELLTYPE));
974 cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
975 SET_AST_NODE_LOC(cell, en_expr ? @1 : @2, @10);
977 char oper_polarity = 0;
978 char oper_type = oper->at(0);
980 if (oper->size() == 3) {
981 oper_polarity = oper->at(0);
982 oper_type = oper->at(1);
985 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
986 cell->children.back()->str = "\\FULL";
988 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
989 cell->children.back()->str = "\\SRC_DST_PEN";
991 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
992 cell->children.back()->str = "\\SRC_DST_POL";
994 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
995 cell->children.back()->str = "\\T_RISE_MIN";
997 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
998 cell->children.back()->str = "\\T_RISE_TYP";
1000 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
1001 cell->children.back()->str = "\\T_RISE_MAX";
1003 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
1004 cell->children.back()->str = "\\T_FALL_MIN";
1006 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
1007 cell->children.back()->str = "\\T_FALL_TYP";
1009 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
1010 cell->children.back()->str = "\\T_FALL_MAX";
1012 cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
1013 cell->children.back()->str = "\\EN";
1015 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
1016 cell->children.back()->str = "\\SRC";
1018 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
1019 cell->children.back()->str = "\\DST";
1023 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
1024 cell->children.back()->str = "\\EDGE_EN";
1026 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
1027 cell->children.back()->str = "\\EDGE_POL";
1029 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
1030 cell->children.back()->str = "\\DAT_DST_PEN";
1032 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
1033 cell->children.back()->str = "\\DAT_DST_POL";
1035 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
1036 cell->children.back()->str = "\\DAT";
1043 TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' specify_triple specify_opt_triple ')' ';' {
1044 if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
1045 *$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
1046 frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
1048 AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
1049 AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
1050 AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
1052 AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
1053 AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
1054 AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
1056 specify_triple *limit = $11;
1057 specify_triple *limit2 = $12;
1059 AstNode *cell = new AstNode(AST_CELL);
1060 ast_stack.back()->children.push_back(cell);
1061 cell->str = stringf("$specify$%d", autoidx++);
1062 cell->children.push_back(new AstNode(AST_CELLTYPE));
1063 cell->children.back()->str = "$specrule";
1064 SET_AST_NODE_LOC(cell, @1, @14);
1066 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
1067 cell->children.back()->str = "\\TYPE";
1069 cell->children.push_back(new AstNode(AST_PARASET, limit->t_min));
1070 cell->children.back()->str = "\\T_LIMIT_MIN";
1072 cell->children.push_back(new AstNode(AST_PARASET, limit->t_avg));
1073 cell->children.back()->str = "\\T_LIMIT_TYP";
1075 cell->children.push_back(new AstNode(AST_PARASET, limit->t_max));
1076 cell->children.back()->str = "\\T_LIMIT_MAX";
1078 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_min : AstNode::mkconst_int(0, true)));
1079 cell->children.back()->str = "\\T_LIMIT2_MIN";
1081 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_avg : AstNode::mkconst_int(0, true)));
1082 cell->children.back()->str = "\\T_LIMIT2_TYP";
1084 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_max : AstNode::mkconst_int(0, true)));
1085 cell->children.back()->str = "\\T_LIMIT2_MAX";
1087 cell->children.push_back(new AstNode(AST_PARASET, src_pen));
1088 cell->children.back()->str = "\\SRC_PEN";
1090 cell->children.push_back(new AstNode(AST_PARASET, src_pol));
1091 cell->children.back()->str = "\\SRC_POL";
1093 cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
1094 cell->children.back()->str = "\\DST_PEN";
1096 cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
1097 cell->children.back()->str = "\\DST_POL";
1099 cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
1100 cell->children.back()->str = "\\SRC_EN";
1102 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
1103 cell->children.back()->str = "\\SRC";
1105 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
1106 cell->children.back()->str = "\\DST_EN";
1108 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
1109 cell->children.back()->str = "\\DST";
1115 ',' specify_triple {
1123 TOK_IF '(' expr ')' {
1131 TOK_SPECIFY_AND expr {
1140 $$ = new specify_target;
1141 $$->polarity_op = 0;
1145 '(' expr ':' expr ')'{
1146 $$ = new specify_target;
1147 $$->polarity_op = 0;
1151 '(' expr TOK_NEG_INDEXED expr ')'{
1152 $$ = new specify_target;
1153 $$->polarity_op = '-';
1157 '(' expr TOK_POS_INDEXED expr ')'{
1158 $$ = new specify_target;
1159 $$->polarity_op = '+';
1165 TOK_POSEDGE { $$ = 'p'; } |
1166 TOK_NEGEDGE { $$ = 'n'; } |
1171 $$ = new specify_rise_fall;
1173 $$->fall.t_min = $1->t_min->clone();
1174 $$->fall.t_avg = $1->t_avg->clone();
1175 $$->fall.t_max = $1->t_max->clone();
1178 '(' specify_triple ',' specify_triple ')' {
1179 $$ = new specify_rise_fall;
1185 '(' specify_triple ',' specify_triple ',' specify_triple ')' {
1186 $$ = new specify_rise_fall;
1192 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1194 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1195 $$ = new specify_rise_fall;
1204 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1206 '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1207 $$ = new specify_rise_fall;
1222 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1227 $$ = new specify_triple;
1229 $$->t_avg = $1->clone();
1230 $$->t_max = $1->clone();
1232 expr ':' expr ':' expr {
1233 $$ = new specify_triple;
1239 /******************** ignored specify parser **************************/
1241 ignored_specify_block:
1242 TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
1243 TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
1245 ignored_specify_item_opt:
1246 ignored_specify_item_opt ignored_specify_item |
1247 ignored_specify_item ;
1249 ignored_specify_item:
1250 specparam_declaration
1251 // | pulsestyle_declaration
1252 // | showcancelled_declaration
1254 | system_timing_declaration
1257 specparam_declaration:
1258 TOK_SPECPARAM list_of_specparam_assignments ';' |
1259 TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ;
1261 // IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match
1262 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
1263 // exxxxtending this for SV specparam would change this anyhow
1265 '[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
1267 list_of_specparam_assignments:
1268 specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
1270 specparam_assignment:
1271 ignspec_id '=' ignspec_expr ;
1274 TOK_IF '(' ignspec_expr ')' | %empty;
1277 simple_path_declaration ';'
1278 // | edge_sensitive_path_declaration
1279 // | state_dependent_path_declaration
1282 simple_path_declaration :
1283 ignspec_opt_cond parallel_path_description '=' path_delay_value |
1284 ignspec_opt_cond full_path_description '=' path_delay_value
1288 '(' ignspec_expr list_of_path_delay_extra_expressions ')'
1290 | ignspec_expr list_of_path_delay_extra_expressions
1293 list_of_path_delay_extra_expressions :
1295 | ',' ignspec_expr list_of_path_delay_extra_expressions
1298 specify_edge_identifier :
1299 TOK_POSEDGE | TOK_NEGEDGE ;
1301 parallel_path_description :
1302 '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
1303 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
1304 '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
1306 full_path_description :
1307 '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
1308 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
1309 '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
1311 // This was broken into 2 rules to solve shift/reduce conflicts
1312 list_of_path_inputs :
1313 specify_input_terminal_descriptor opt_polarity_operator |
1314 specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
1317 ',' specify_input_terminal_descriptor |
1318 more_path_inputs ',' specify_input_terminal_descriptor ;
1320 list_of_path_outputs :
1321 specify_output_terminal_descriptor |
1322 list_of_path_outputs ',' specify_output_terminal_descriptor ;
1324 opt_polarity_operator :
1327 // Good enough for the time being
1328 specify_input_terminal_descriptor :
1331 // Good enough for the time being
1332 specify_output_terminal_descriptor :
1335 system_timing_declaration :
1336 ignspec_id '(' system_timing_args ')' ';' ;
1339 TOK_POSEDGE ignspec_id |
1340 TOK_NEGEDGE ignspec_id |
1343 system_timing_args :
1345 system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
1346 system_timing_args ',' system_timing_arg ;
1348 // for the time being this is OK, but we may write our own expr here.
1349 // as I'm not sure it is legal to use a full expr here (probably not)
1350 // On the other hand, other rules requiring constant expressions also use 'expr'
1351 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
1352 ignspec_constant_expression:
1353 expr { delete $1; };
1356 expr { delete $1; } |
1357 expr ':' expr ':' expr {
1364 TOK_ID { delete $1; }
1365 range_or_multirange { delete $3; };
1367 /**********************************************************************/
1371 astbuf1->is_signed = true;
1373 astbuf1->is_signed = false;
1378 astbuf1->children.push_back(new AstNode(AST_RANGE));
1379 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
1380 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
1381 astbuf1->is_signed = true;
1386 astbuf1->children.push_back(new AstNode(AST_REALVALUE));
1392 astbuf1->children.push_back($1);
1396 param_integer_type: param_integer param_signed;
1397 param_range_type: type_vec param_signed param_range;
1398 param_implicit_type: param_signed param_range;
1401 param_integer_type | param_real | param_range_type | param_implicit_type |
1402 hierarchical_type_id {
1403 astbuf1->is_custom_type = true;
1404 astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
1405 astbuf1->children.back()->str = *$1;
1409 attr TOK_PARAMETER {
1410 astbuf1 = new AstNode(AST_PARAMETER);
1411 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1412 append_attr(astbuf1, $1);
1413 } param_type param_decl_list ';' {
1418 attr TOK_LOCALPARAM {
1419 astbuf1 = new AstNode(AST_LOCALPARAM);
1420 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1421 append_attr(astbuf1, $1);
1422 } param_type param_decl_list ';' {
1427 single_param_decl | param_decl_list ',' single_param_decl;
1432 if (astbuf1 == nullptr) {
1434 frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword");
1435 node = new AstNode(AST_PARAMETER);
1436 node->children.push_back(AstNode::mkconst_int(0, true));
1438 node = astbuf1->clone();
1441 delete node->children[0];
1442 node->children[0] = $3;
1443 ast_stack.back()->children.push_back(node);
1448 TOK_DEFPARAM defparam_decl_list ';';
1451 single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
1453 single_defparam_decl:
1454 range rvalue '=' expr {
1455 AstNode *node = new AstNode(AST_DEFPARAM);
1456 node->children.push_back($2);
1457 node->children.push_back($4);
1459 node->children.push_back($1);
1460 ast_stack.back()->children.push_back(node);
1467 enum_type: TOK_ENUM {
1468 static int enum_count;
1469 // create parent node for the enum
1470 astbuf2 = new AstNode(AST_ENUM);
1471 ast_stack.back()->children.push_back(astbuf2);
1472 astbuf2->str = std::string("$enum");
1473 astbuf2->str += std::to_string(enum_count++);
1474 // create the template for the names
1475 astbuf1 = new AstNode(AST_ENUM_ITEM);
1476 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1477 } enum_base_type '{' enum_name_list '}' { // create template for the enum vars
1478 auto tnode = astbuf1->clone();
1481 tnode->type = AST_WIRE;
1482 tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
1483 // drop constant but keep any range
1484 delete tnode->children[0];
1485 tnode->children.erase(tnode->children.begin());
1489 enum_base_type: type_atom type_signing
1490 | type_vec type_signing range { if ($3) astbuf1->children.push_back($3); }
1491 | %empty { astbuf1->is_reg = true; addRange(astbuf1); }
1494 type_atom: TOK_INTEGER { astbuf1->is_reg = true; addRange(astbuf1); } // 4-state signed
1495 | TOK_INT { astbuf1->is_reg = true; addRange(astbuf1); } // 2-state signed
1496 | TOK_SHORTINT { astbuf1->is_reg = true; addRange(astbuf1, 15, 0); } // 2-state signed
1497 | TOK_BYTE { astbuf1->is_reg = true; addRange(astbuf1, 7, 0); } // 2-state signed
1500 type_vec: TOK_REG { astbuf1->is_reg = true; } // unsigned
1501 | TOK_LOGIC { astbuf1->is_logic = true; } // unsigned
1505 TOK_SIGNED { astbuf1->is_signed = true; }
1506 | TOK_UNSIGNED { astbuf1->is_signed = false; }
1510 enum_name_list: enum_name_decl
1511 | enum_name_list ',' enum_name_decl
1515 TOK_ID opt_enum_init {
1517 log_assert(astbuf1);
1518 log_assert(astbuf2);
1519 auto node = astbuf1->clone();
1522 SET_AST_NODE_LOC(node, @1, @1);
1523 delete node->children[0];
1524 node->children[0] = $2 ? $2 : new AstNode(AST_NONE);
1525 astbuf2->children.push_back(node);
1530 '=' basic_expr { $$ = $2; } // TODO: restrict this
1531 | %empty { $$ = NULL; }
1536 | enum_var_list ',' enum_var
1540 log_assert(astbuf1);
1541 log_assert(astbuf2);
1542 auto node = astbuf1->clone();
1543 ast_stack.back()->children.push_back(node);
1546 SET_AST_NODE_LOC(node, @1, @1);
1547 node->is_enum = true;
1551 enum_decl: enum_type enum_var_list ';' { delete $1; }
1558 struct_decl: struct_type struct_var_list ';' { delete astbuf2; }
1561 struct_type: struct_union { astbuf2 = $1; } struct_body { $$ = astbuf2; }
1565 TOK_STRUCT { $$ = new AstNode(AST_STRUCT); }
1566 | TOK_UNION { $$ = new AstNode(AST_UNION); }
1569 struct_body: opt_packed '{' struct_member_list '}'
1573 TOK_PACKED opt_signed_struct |
1574 %empty { frontend_verilog_yyerror("Only PACKED supported at this time"); };
1577 TOK_SIGNED { astbuf2->is_signed = true; }
1578 | TOK_UNSIGNED { astbuf2->is_signed = false; }
1579 | %empty // default is unsigned
1582 struct_member_list: struct_member
1583 | struct_member_list struct_member
1586 struct_member: struct_member_type member_name_list ';' { delete astbuf1; }
1591 | member_name_list ',' member_name
1594 member_name: TOK_ID {
1595 astbuf1->str = $1->substr(1);
1597 astbuf3 = astbuf1->clone();
1598 SET_AST_NODE_LOC(astbuf3, @1, @1);
1599 astbuf2->children.push_back(astbuf3);
1600 } range { if ($3) astbuf3->children.push_back($3); }
1603 struct_member_type: { astbuf1 = new AstNode(AST_STRUCT_ITEM); } member_type_token
1608 | hierarchical_type_id {
1609 // use a clone of the typedef definition nodes
1610 auto template_node = copyTypeDefinition(*$1);
1612 switch (template_node->type) {
1614 template_node->type = AST_STRUCT_ITEM;
1620 frontend_verilog_yyerror("Invalid type for struct member: %s", type2str(template_node->type).c_str());
1623 astbuf1 = template_node;
1626 // stash state on ast_stack
1627 ast_stack.push_back(astbuf2);
1632 astbuf2 = ast_stack.back();
1633 ast_stack.pop_back();
1637 member_type: type_atom type_signing
1638 | type_vec type_signing range_or_multirange { if ($3) astbuf1->children.push_back($3); }
1641 struct_var_list: struct_var
1642 | struct_var_list ',' struct_var
1645 struct_var: TOK_ID { auto *var_node = astbuf2->clone();
1646 var_node->str = *$1;
1648 SET_AST_NODE_LOC(var_node, @1, @1);
1649 ast_stack.back()->children.push_back(var_node);
1658 attr wire_type range {
1661 astbuf2 = checkRange(astbuf1, $3);
1662 } delay wire_name_list {
1664 if (astbuf2 != NULL)
1668 attr TOK_SUPPLY0 TOK_ID {
1669 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1670 ast_stack.back()->children.back()->str = *$3;
1671 append_attr(ast_stack.back()->children.back(), $1);
1672 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
1673 ast_stack.back()->children.back()->children[0]->str = *$3;
1675 } opt_supply_wires ';' |
1676 attr TOK_SUPPLY1 TOK_ID {
1677 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1678 ast_stack.back()->children.back()->str = *$3;
1679 append_attr(ast_stack.back()->children.back(), $1);
1680 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
1681 ast_stack.back()->children.back()->children[0]->str = *$3;
1683 } opt_supply_wires ';';
1687 opt_supply_wires ',' TOK_ID {
1688 AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
1689 AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
1690 wire_node->str = *$3;
1691 assign_node->children[0]->str = *$3;
1692 ast_stack.back()->children.push_back(wire_node);
1693 ast_stack.back()->children.push_back(assign_node);
1698 wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
1700 wire_name_and_opt_assign:
1702 bool attr_anyconst = false;
1703 bool attr_anyseq = false;
1704 bool attr_allconst = false;
1705 bool attr_allseq = false;
1706 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
1707 delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
1708 ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
1709 attr_anyconst = true;
1711 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
1712 delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
1713 ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
1716 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
1717 delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
1718 ast_stack.back()->children.back()->attributes.erase(ID::allconst);
1719 attr_allconst = true;
1721 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
1722 delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
1723 ast_stack.back()->children.back()->attributes.erase(ID::allseq);
1726 if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
1727 AstNode *wire = new AstNode(AST_IDENTIFIER);
1728 AstNode *fcall = new AstNode(AST_FCALL);
1729 wire->str = ast_stack.back()->children.back()->str;
1730 fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
1732 fcall->str = "\\$anyconst";
1734 fcall->str = "\\$anyseq";
1736 fcall->str = "\\$allconst";
1738 fcall->str = "\\$allseq";
1739 fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
1740 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
1743 wire_name '=' expr {
1744 AstNode *wire = new AstNode(AST_IDENTIFIER);
1745 wire->str = ast_stack.back()->children.back()->str;
1746 if (astbuf1->is_input) {
1747 if (astbuf1->attributes.count(ID::defaultvalue))
1748 delete astbuf1->attributes.at(ID::defaultvalue);
1749 astbuf1->attributes[ID::defaultvalue] = $3;
1751 else if (astbuf1->is_reg || astbuf1->is_logic){
1752 AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
1753 AstNode *block = new AstNode(AST_BLOCK, assign);
1754 AstNode *init = new AstNode(AST_INITIAL, block);
1756 SET_AST_NODE_LOC(assign, @1, @3);
1757 SET_AST_NODE_LOC(block, @1, @3);
1758 SET_AST_NODE_LOC(init, @1, @3);
1760 ast_stack.back()->children.push_back(init);
1763 AstNode *assign = new AstNode(AST_ASSIGN, wire, $3);
1764 SET_AST_NODE_LOC(assign, @1, @3);
1765 ast_stack.back()->children.push_back(assign);
1771 TOK_ID range_or_multirange {
1772 if (astbuf1 == nullptr)
1773 frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node.");
1774 AstNode *node = astbuf1->clone();
1776 append_attr_clone(node, albuf);
1777 if (astbuf2 != NULL)
1778 node->children.push_back(astbuf2->clone());
1780 if (node->is_input || node->is_output)
1781 frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
1782 if (!astbuf2 && !node->is_custom_type) {
1783 addRange(node, 0, 0, false);
1785 rewriteAsMemoryNode(node, $2);
1787 if (current_function_or_task == NULL) {
1788 if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
1789 port_stubs[*$1] = ++port_counter;
1791 if (port_stubs.count(*$1) != 0) {
1792 if (!node->is_input && !node->is_output)
1793 frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
1794 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
1795 frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
1796 node->port_id = port_stubs[*$1];
1797 port_stubs.erase(*$1);
1799 if (node->is_input || node->is_output)
1800 frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
1803 if (node->is_input || node->is_output)
1804 node->port_id = current_function_or_task_port_id++;
1806 //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
1807 SET_AST_NODE_LOC(node, @1, @1);
1808 ast_stack.back()->children.push_back(node);
1814 TOK_ASSIGN delay assign_expr_list ';';
1817 assign_expr | assign_expr_list ',' assign_expr;
1821 AstNode *node = new AstNode(AST_ASSIGN, $1, $3);
1822 SET_AST_NODE_LOC(node, @$, @$);
1823 ast_stack.back()->children.push_back(node);
1826 type_name: TOK_ID // first time seen
1827 | TOK_USER_TYPE { if (isInLocalScope($1)) frontend_verilog_yyerror("Duplicate declaration of TYPEDEF '%s'", $1->c_str()+1); }
1831 TOK_TYPEDEF non_io_wire_type range type_name range_or_multirange ';' {
1833 astbuf2 = checkRange(astbuf1, $3);
1835 astbuf1->children.push_back(astbuf2);
1839 addRange(astbuf1, 0, 0, false);
1841 rewriteAsMemoryNode(astbuf1, $5);
1843 addTypedefNode($4, astbuf1); }
1844 | TOK_TYPEDEF non_wire_data_type type_name ';' { addTypedefNode($3, $2); }
1854 astbuf1 = new AstNode(AST_CELL);
1855 append_attr(astbuf1, $1);
1856 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
1857 astbuf1->children[0]->str = *$2;
1859 } cell_parameter_list_opt cell_list ';' {
1862 attr tok_prim_wrapper delay {
1863 astbuf1 = new AstNode(AST_PRIMITIVE);
1865 append_attr(astbuf1, $1);
1876 $$ = new std::string("or");
1881 cell_list ',' single_cell;
1885 astbuf2 = astbuf1->clone();
1886 if (astbuf2->type != AST_PRIMITIVE)
1889 ast_stack.back()->children.push_back(astbuf2);
1890 } '(' cell_port_list ')' {
1891 SET_AST_NODE_LOC(astbuf2, @1, @$);
1893 TOK_ID non_opt_range {
1894 astbuf2 = astbuf1->clone();
1895 if (astbuf2->type != AST_PRIMITIVE)
1898 ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
1899 } '(' cell_port_list ')'{
1900 SET_AST_NODE_LOC(astbuf2, @1, @$);
1905 prim_list ',' single_prim;
1910 astbuf2 = astbuf1->clone();
1911 ast_stack.back()->children.push_back(astbuf2);
1912 } '(' cell_port_list ')' {
1913 SET_AST_NODE_LOC(astbuf2, @1, @$);
1916 cell_parameter_list_opt:
1917 '#' '(' cell_parameter_list ')' | %empty;
1919 cell_parameter_list:
1920 cell_parameter | cell_parameter_list ',' cell_parameter;
1925 AstNode *node = new AstNode(AST_PARASET);
1926 astbuf1->children.push_back(node);
1927 node->children.push_back($1);
1929 '.' TOK_ID '(' ')' {
1930 // just ignore empty parameters
1932 '.' TOK_ID '(' expr ')' {
1933 AstNode *node = new AstNode(AST_PARASET);
1935 astbuf1->children.push_back(node);
1936 node->children.push_back($4);
1941 cell_port_list_rules {
1942 // remove empty args from end of list
1943 while (!astbuf2->children.empty()) {
1944 AstNode *node = astbuf2->children.back();
1945 if (node->type != AST_ARGUMENT) break;
1946 if (!node->children.empty()) break;
1947 if (!node->str.empty()) break;
1948 astbuf2->children.pop_back();
1953 bool has_positional_args = false;
1954 bool has_named_args = false;
1955 for (auto node : astbuf2->children) {
1956 if (node->type != AST_ARGUMENT) continue;
1957 if (node->str.empty())
1958 has_positional_args = true;
1960 has_named_args = true;
1963 if (has_positional_args && has_named_args)
1964 frontend_verilog_yyerror("Mix of positional and named cell ports.");
1967 cell_port_list_rules:
1968 cell_port | cell_port_list_rules ',' cell_port;
1972 AstNode *node = new AstNode(AST_ARGUMENT);
1973 astbuf2->children.push_back(node);
1977 AstNode *node = new AstNode(AST_ARGUMENT);
1978 astbuf2->children.push_back(node);
1979 node->children.push_back($2);
1982 attr '.' TOK_ID '(' expr ')' {
1983 AstNode *node = new AstNode(AST_ARGUMENT);
1985 astbuf2->children.push_back(node);
1986 node->children.push_back($5);
1990 attr '.' TOK_ID '(' ')' {
1991 AstNode *node = new AstNode(AST_ARGUMENT);
1993 astbuf2->children.push_back(node);
1998 AstNode *node = new AstNode(AST_ARGUMENT);
2000 astbuf2->children.push_back(node);
2001 node->children.push_back(new AstNode(AST_IDENTIFIER));
2002 node->children.back()->str = *$3;
2006 attr TOK_WILDCARD_CONNECT {
2008 frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
2009 astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
2012 always_comb_or_latch:
2020 always_or_always_ff:
2029 attr always_or_always_ff {
2030 AstNode *node = new AstNode(AST_ALWAYS);
2031 append_attr(node, $1);
2033 node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
2034 ast_stack.back()->children.push_back(node);
2035 ast_stack.push_back(node);
2037 AstNode *block = new AstNode(AST_BLOCK);
2038 ast_stack.back()->children.push_back(block);
2039 ast_stack.push_back(block);
2041 SET_AST_NODE_LOC(ast_stack.back(), @6, @6);
2042 ast_stack.pop_back();
2044 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
2045 ast_stack.pop_back();
2047 SET_RULE_LOC(@$, @2, @$);
2049 attr always_comb_or_latch {
2050 AstNode *node = new AstNode(AST_ALWAYS);
2051 append_attr(node, $1);
2053 node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
2055 node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
2056 ast_stack.back()->children.push_back(node);
2057 ast_stack.push_back(node);
2058 AstNode *block = new AstNode(AST_BLOCK);
2059 ast_stack.back()->children.push_back(block);
2060 ast_stack.push_back(block);
2062 ast_stack.pop_back();
2063 ast_stack.pop_back();
2066 AstNode *node = new AstNode(AST_INITIAL);
2067 append_attr(node, $1);
2068 ast_stack.back()->children.push_back(node);
2069 ast_stack.push_back(node);
2070 AstNode *block = new AstNode(AST_BLOCK);
2071 ast_stack.back()->children.push_back(block);
2072 ast_stack.push_back(block);
2074 ast_stack.pop_back();
2075 ast_stack.pop_back();
2079 '@' '(' always_events ')' |
2081 '@' ATTR_BEGIN ')' |
2088 always_events TOK_OR always_event |
2089 always_events ',' always_event;
2093 AstNode *node = new AstNode(AST_POSEDGE);
2094 SET_AST_NODE_LOC(node, @1, @1);
2095 ast_stack.back()->children.push_back(node);
2096 node->children.push_back($2);
2099 AstNode *node = new AstNode(AST_NEGEDGE);
2100 SET_AST_NODE_LOC(node, @1, @1);
2101 ast_stack.back()->children.push_back(node);
2102 node->children.push_back($2);
2105 AstNode *node = new AstNode(AST_EDGE);
2106 ast_stack.back()->children.push_back(node);
2107 node->children.push_back($1);
2138 TOK_MODPORT TOK_ID {
2139 AstNode *modport = new AstNode(AST_MODPORT);
2140 ast_stack.back()->children.push_back(modport);
2141 ast_stack.push_back(modport);
2144 } modport_args_opt {
2145 ast_stack.pop_back();
2146 log_assert(ast_stack.size() == 2);
2150 '(' ')' | '(' modport_args optional_comma ')';
2153 modport_arg | modport_args ',' modport_arg;
2156 modport_type_token modport_member |
2161 AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
2162 ast_stack.back()->children.push_back(modport_member);
2163 modport_member->str = *$1;
2164 modport_member->is_input = current_modport_input;
2165 modport_member->is_output = current_modport_output;
2170 TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
2173 opt_sva_label TOK_ASSERT opt_property '(' expr ')' ';' {
2174 if (noassert_mode) {
2177 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2178 SET_AST_NODE_LOC(node, @1, @6);
2181 ast_stack.back()->children.push_back(node);
2186 opt_sva_label TOK_ASSUME opt_property '(' expr ')' ';' {
2187 if (noassume_mode) {
2190 AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
2191 SET_AST_NODE_LOC(node, @1, @6);
2194 ast_stack.back()->children.push_back(node);
2199 opt_sva_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2200 if (noassert_mode) {
2203 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2204 SET_AST_NODE_LOC(node, @1, @7);
2207 ast_stack.back()->children.push_back(node);
2212 opt_sva_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2213 if (noassume_mode) {
2216 AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
2217 SET_AST_NODE_LOC(node, @1, @7);
2220 ast_stack.back()->children.push_back(node);
2225 opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
2226 AstNode *node = new AstNode(AST_COVER, $5);
2227 SET_AST_NODE_LOC(node, @1, @6);
2228 if ($1 != nullptr) {
2232 ast_stack.back()->children.push_back(node);
2234 opt_sva_label TOK_COVER opt_property '(' ')' ';' {
2235 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2236 SET_AST_NODE_LOC(node, @1, @5);
2237 if ($1 != nullptr) {
2241 ast_stack.back()->children.push_back(node);
2243 opt_sva_label TOK_COVER ';' {
2244 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2245 SET_AST_NODE_LOC(node, @1, @2);
2246 if ($1 != nullptr) {
2250 ast_stack.back()->children.push_back(node);
2252 opt_sva_label TOK_RESTRICT opt_property '(' expr ')' ';' {
2253 if (norestrict_mode) {
2256 AstNode *node = new AstNode(AST_ASSUME, $5);
2257 SET_AST_NODE_LOC(node, @1, @6);
2260 ast_stack.back()->children.push_back(node);
2263 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2267 opt_sva_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2268 if (norestrict_mode) {
2271 AstNode *node = new AstNode(AST_FAIR, $6);
2272 SET_AST_NODE_LOC(node, @1, @7);
2275 ast_stack.back()->children.push_back(node);
2278 log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2284 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
2285 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2286 SET_AST_NODE_LOC(node, @1, @6);
2287 ast_stack.back()->children.push_back(node);
2288 if ($1 != nullptr) {
2289 ast_stack.back()->children.back()->str = *$1;
2293 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
2294 AstNode *node = new AstNode(AST_ASSUME, $5);
2295 SET_AST_NODE_LOC(node, @1, @6);
2296 ast_stack.back()->children.push_back(node);
2297 if ($1 != nullptr) {
2298 ast_stack.back()->children.back()->str = *$1;
2302 opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2303 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2304 SET_AST_NODE_LOC(node, @1, @7);
2305 ast_stack.back()->children.push_back(node);
2306 if ($1 != nullptr) {
2307 ast_stack.back()->children.back()->str = *$1;
2311 opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2312 AstNode *node = new AstNode(AST_FAIR, $6);
2313 SET_AST_NODE_LOC(node, @1, @7);
2314 ast_stack.back()->children.push_back(node);
2315 if ($1 != nullptr) {
2316 ast_stack.back()->children.back()->str = *$1;
2320 opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
2321 AstNode *node = new AstNode(AST_COVER, $5);
2322 SET_AST_NODE_LOC(node, @1, @6);
2323 ast_stack.back()->children.push_back(node);
2324 if ($1 != nullptr) {
2325 ast_stack.back()->children.back()->str = *$1;
2329 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
2330 if (norestrict_mode) {
2333 AstNode *node = new AstNode(AST_ASSUME, $5);
2334 SET_AST_NODE_LOC(node, @1, @6);
2335 ast_stack.back()->children.push_back(node);
2336 if ($1 != nullptr) {
2337 ast_stack.back()->children.back()->str = *$1;
2342 opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2343 if (norestrict_mode) {
2346 AstNode *node = new AstNode(AST_FAIR, $6);
2347 SET_AST_NODE_LOC(node, @1, @7);
2348 ast_stack.back()->children.push_back(node);
2349 if ($1 != nullptr) {
2350 ast_stack.back()->children.back()->str = *$1;
2356 simple_behavioral_stmt:
2357 attr lvalue '=' delay expr {
2358 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $5);
2359 ast_stack.back()->children.push_back(node);
2360 SET_AST_NODE_LOC(node, @2, @5);
2361 append_attr(node, $1);
2363 attr lvalue TOK_INCREMENT {
2364 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)));
2365 ast_stack.back()->children.push_back(node);
2366 SET_AST_NODE_LOC(node, @2, @3);
2367 append_attr(node, $1);
2369 attr lvalue TOK_DECREMENT {
2370 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_SUB, $2->clone(), AstNode::mkconst_int(1, true)));
2371 ast_stack.back()->children.push_back(node);
2372 SET_AST_NODE_LOC(node, @2, @3);
2373 append_attr(node, $1);
2375 attr lvalue OP_LE delay expr {
2376 AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5);
2377 ast_stack.back()->children.push_back(node);
2378 SET_AST_NODE_LOC(node, @2, @5);
2379 append_attr(node, $1);
2381 attr lvalue TOK_XOR_ASSIGN delay expr {
2382 AstNode *xor_node = new AstNode(AST_BIT_XOR, $2->clone(), $5);
2383 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, xor_node);
2384 SET_AST_NODE_LOC(xor_node, @2, @5);
2385 SET_AST_NODE_LOC(node, @2, @5);
2386 ast_stack.back()->children.push_back(node);
2387 append_attr(node, $1);
2389 attr lvalue TOK_OR_ASSIGN delay expr {
2390 AstNode *or_node = new AstNode(AST_BIT_OR, $2->clone(), $5);
2391 SET_AST_NODE_LOC(or_node, @2, @5);
2392 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, or_node);
2393 SET_AST_NODE_LOC(node, @2, @5);
2394 ast_stack.back()->children.push_back(node);
2395 append_attr(node, $1);
2397 attr lvalue TOK_PLUS_ASSIGN delay expr {
2398 AstNode *add_node = new AstNode(AST_ADD, $2->clone(), $5);
2399 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, add_node);
2400 SET_AST_NODE_LOC(node, @2, @5);
2401 SET_AST_NODE_LOC(add_node, @2, @5);
2402 ast_stack.back()->children.push_back(node);
2403 append_attr(node, $1);
2405 attr lvalue TOK_SUB_ASSIGN delay expr {
2406 AstNode *sub_node = new AstNode(AST_SUB, $2->clone(), $5);
2407 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, sub_node);
2408 SET_AST_NODE_LOC(node, @2, @5);
2409 SET_AST_NODE_LOC(sub_node, @2, @5);
2410 ast_stack.back()->children.push_back(node);
2411 append_attr(node, $1);
2413 attr lvalue TOK_AND_ASSIGN delay expr {
2414 AstNode *and_node = new AstNode(AST_BIT_AND, $2->clone(), $5);
2415 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, and_node);
2416 SET_AST_NODE_LOC(node, @2, @5);
2417 SET_AST_NODE_LOC(and_node, @2, @5);
2418 ast_stack.back()->children.push_back(node);
2419 append_attr(node, $1);
2422 // this production creates the obligatory if-else shift/reduce conflict
2424 defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
2425 non_opt_delay behavioral_stmt |
2426 simple_behavioral_stmt ';' |
2430 attr hierarchical_id {
2431 AstNode *node = new AstNode(AST_TCALL);
2434 ast_stack.back()->children.push_back(node);
2435 ast_stack.push_back(node);
2436 append_attr(node, $1);
2438 ast_stack.pop_back();
2440 attr TOK_MSG_TASKS {
2441 AstNode *node = new AstNode(AST_TCALL);
2444 ast_stack.back()->children.push_back(node);
2445 ast_stack.push_back(node);
2446 append_attr(node, $1);
2448 ast_stack.pop_back();
2453 AstNode *node = new AstNode(AST_BLOCK);
2454 ast_stack.back()->children.push_back(node);
2455 ast_stack.push_back(node);
2456 append_attr(node, $1);
2459 } behavioral_stmt_list TOK_END opt_label {
2461 if ($4 != NULL && $8 != NULL && *$4 != *$8)
2462 frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
2463 AstNode *node = ast_stack.back();
2464 // In SystemVerilog, unnamed blocks with block item declarations
2465 // create an implicit hierarchy scope
2466 if (sv_mode && node->str.empty())
2467 for (const AstNode* child : node->children)
2468 if (child->type == AST_WIRE || child->type == AST_MEMORY || child->type == AST_PARAMETER
2469 || child->type == AST_LOCALPARAM || child->type == AST_TYPEDEF) {
2470 node->str = "$unnamed_block$" + std::to_string(autoidx++);
2473 SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
2476 ast_stack.pop_back();
2479 AstNode *node = new AstNode(AST_FOR);
2480 ast_stack.back()->children.push_back(node);
2481 ast_stack.push_back(node);
2482 append_attr(node, $1);
2483 } simple_behavioral_stmt ';' expr {
2484 ast_stack.back()->children.push_back($7);
2485 } ';' simple_behavioral_stmt ')' {
2486 AstNode *block = new AstNode(AST_BLOCK);
2487 block->str = "$for_loop$" + std::to_string(autoidx++);
2488 ast_stack.back()->children.push_back(block);
2489 ast_stack.push_back(block);
2491 SET_AST_NODE_LOC(ast_stack.back(), @13, @13);
2492 ast_stack.pop_back();
2493 SET_AST_NODE_LOC(ast_stack.back(), @2, @13);
2494 ast_stack.pop_back();
2496 attr TOK_WHILE '(' expr ')' {
2497 AstNode *node = new AstNode(AST_WHILE);
2498 ast_stack.back()->children.push_back(node);
2499 ast_stack.push_back(node);
2500 append_attr(node, $1);
2501 AstNode *block = new AstNode(AST_BLOCK);
2502 ast_stack.back()->children.push_back($4);
2503 ast_stack.back()->children.push_back(block);
2504 ast_stack.push_back(block);
2506 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2507 ast_stack.pop_back();
2508 ast_stack.pop_back();
2510 attr TOK_REPEAT '(' expr ')' {
2511 AstNode *node = new AstNode(AST_REPEAT);
2512 ast_stack.back()->children.push_back(node);
2513 ast_stack.push_back(node);
2514 append_attr(node, $1);
2515 AstNode *block = new AstNode(AST_BLOCK);
2516 ast_stack.back()->children.push_back($4);
2517 ast_stack.back()->children.push_back(block);
2518 ast_stack.push_back(block);
2520 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2521 ast_stack.pop_back();
2522 ast_stack.pop_back();
2524 attr TOK_IF '(' expr ')' {
2525 AstNode *node = new AstNode(AST_CASE);
2526 AstNode *block = new AstNode(AST_BLOCK);
2527 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
2528 SET_AST_NODE_LOC(cond, @4, @4);
2529 ast_stack.back()->children.push_back(node);
2530 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
2531 node->children.push_back(cond);
2532 ast_stack.push_back(node);
2533 ast_stack.push_back(block);
2534 append_attr(node, $1);
2536 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2538 ast_stack.pop_back();
2539 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2540 ast_stack.pop_back();
2542 case_attr case_type '(' expr ')' {
2543 AstNode *node = new AstNode(AST_CASE, $4);
2544 ast_stack.back()->children.push_back(node);
2545 ast_stack.push_back(node);
2546 append_attr(node, $1);
2547 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2548 } opt_synopsys_attr case_body TOK_ENDCASE {
2549 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2550 case_type_stack.pop_back();
2551 ast_stack.pop_back();
2558 TOK_PRIORITY case_attr {
2561 TOK_UNIQUE case_attr {
2566 attr unique_case_attr {
2567 if ($2) (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false);
2573 case_type_stack.push_back(0);
2576 case_type_stack.push_back('x');
2579 case_type_stack.push_back('z');
2583 opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
2584 if (ast_stack.back()->attributes.count(ID::full_case) == 0)
2585 ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
2587 opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
2588 if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
2589 ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
2593 behavioral_stmt_list:
2594 behavioral_stmt_list behavioral_stmt |
2599 AstNode *block = new AstNode(AST_BLOCK);
2600 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
2601 SET_AST_NODE_LOC(cond, @1, @1);
2603 ast_stack.pop_back();
2604 ast_stack.back()->children.push_back(cond);
2605 ast_stack.push_back(block);
2607 SET_AST_NODE_LOC(ast_stack.back(), @3, @3);
2609 %empty %prec FAKE_THEN;
2612 case_body case_item |
2617 AstNode *node = new AstNode(
2618 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2619 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2620 ast_stack.back()->children.push_back(node);
2621 ast_stack.push_back(node);
2623 AstNode *block = new AstNode(AST_BLOCK);
2624 ast_stack.back()->children.push_back(block);
2625 ast_stack.push_back(block);
2626 case_type_stack.push_back(0);
2628 case_type_stack.pop_back();
2629 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2630 ast_stack.pop_back();
2631 ast_stack.pop_back();
2635 gen_case_body gen_case_item |
2640 AstNode *node = new AstNode(
2641 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2642 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2643 ast_stack.back()->children.push_back(node);
2644 ast_stack.push_back(node);
2646 case_type_stack.push_back(0);
2647 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2649 case_type_stack.pop_back();
2650 ast_stack.pop_back();
2654 case_expr_list ':' |
2659 AstNode *node = new AstNode(AST_DEFAULT);
2660 SET_AST_NODE_LOC(node, @1, @1);
2661 ast_stack.back()->children.push_back(node);
2664 AstNode *node = new AstNode(AST_IDENTIFIER);
2665 SET_AST_NODE_LOC(node, @1, @1);
2666 ast_stack.back()->children.push_back(node);
2667 ast_stack.back()->children.back()->str = *$1;
2671 ast_stack.back()->children.push_back($1);
2673 case_expr_list ',' expr {
2674 ast_stack.back()->children.push_back($3);
2678 hierarchical_id '[' expr ']' '.' rvalue {
2679 $$ = new AstNode(AST_PREFIX, $3, $6);
2683 hierarchical_id range {
2684 $$ = new AstNode(AST_IDENTIFIER, $2);
2686 SET_AST_NODE_LOC($$, @1, @1);
2688 if ($2 == nullptr && ($$->str == "\\$initstate" ||
2689 $$->str == "\\$anyconst" || $$->str == "\\$anyseq" ||
2690 $$->str == "\\$allconst" || $$->str == "\\$allseq"))
2691 $$->type = AST_FCALL;
2693 hierarchical_id non_opt_multirange {
2694 $$ = new AstNode(AST_IDENTIFIER, $2);
2696 SET_AST_NODE_LOC($$, @1, @1);
2704 '{' lvalue_concat_list '}' {
2710 $$ = new AstNode(AST_CONCAT);
2711 $$->children.push_back($1);
2713 expr ',' lvalue_concat_list {
2715 $$->children.push_back($1);
2719 '(' arg_list optional_comma ')' |
2728 arg_list ',' single_arg;
2732 ast_stack.back()->children.push_back($1);
2736 module_gen_body gen_stmt_or_module_body_stmt |
2737 module_gen_body gen_block |
2740 gen_stmt_or_module_body_stmt:
2741 gen_stmt | module_body_stmt |
2746 // this production creates the obligatory if-else shift/reduce conflict
2749 AstNode *node = new AstNode(AST_GENFOR);
2750 ast_stack.back()->children.push_back(node);
2751 ast_stack.push_back(node);
2752 } simple_behavioral_stmt ';' expr {
2753 ast_stack.back()->children.push_back($6);
2754 } ';' simple_behavioral_stmt ')' gen_stmt_block {
2755 SET_AST_NODE_LOC(ast_stack.back(), @1, @11);
2756 ast_stack.pop_back();
2758 TOK_IF '(' expr ')' {
2759 AstNode *node = new AstNode(AST_GENIF);
2760 ast_stack.back()->children.push_back(node);
2761 ast_stack.push_back(node);
2762 ast_stack.back()->children.push_back($3);
2763 } gen_stmt_block opt_gen_else {
2764 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2765 ast_stack.pop_back();
2767 case_type '(' expr ')' {
2768 AstNode *node = new AstNode(AST_GENCASE, $3);
2769 ast_stack.back()->children.push_back(node);
2770 ast_stack.push_back(node);
2771 } gen_case_body TOK_ENDCASE {
2772 case_type_stack.pop_back();
2773 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2774 ast_stack.pop_back();
2777 AstNode *node = new AstNode(AST_TECALL);
2780 ast_stack.back()->children.push_back(node);
2781 ast_stack.push_back(node);
2783 SET_AST_NODE_LOC(ast_stack.back(), @1, @3);
2784 ast_stack.pop_back();
2791 AstNode *node = new AstNode(AST_GENBLOCK);
2792 node->str = $3 ? *$3 : std::string();
2793 ast_stack.back()->children.push_back(node);
2794 ast_stack.push_back(node);
2795 } module_gen_body TOK_END opt_label {
2799 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2800 ast_stack.pop_back();
2803 // result is wrapped in a genblock only if necessary
2806 AstNode *node = new AstNode(AST_GENBLOCK);
2807 ast_stack.back()->children.push_back(node);
2808 ast_stack.push_back(node);
2809 } gen_stmt_or_module_body_stmt {
2810 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2811 ast_stack.pop_back();
2815 TOK_ELSE gen_stmt_block | %empty %prec FAKE_THEN;
2821 basic_expr '?' attr expr ':' expr {
2822 $$ = new AstNode(AST_TERNARY);
2823 $$->children.push_back($1);
2824 $$->children.push_back($4);
2825 $$->children.push_back($6);
2826 SET_AST_NODE_LOC($$, @1, @$);
2827 append_attr($$, $3);
2834 '(' expr ')' integral_number {
2835 if ($4->compare(0, 1, "'") != 0)
2836 frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
2838 AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2840 log_error("Value conversion failed: `%s'\n", $4->c_str());
2841 $$ = new AstNode(AST_TO_BITS, bits, val);
2844 hierarchical_id integral_number {
2845 if ($2->compare(0, 1, "'") != 0)
2846 frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
2847 AstNode *bits = new AstNode(AST_IDENTIFIER);
2849 SET_AST_NODE_LOC(bits, @1, @1);
2850 AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2851 SET_AST_NODE_LOC(val, @2, @2);
2853 log_error("Value conversion failed: `%s'\n", $2->c_str());
2854 $$ = new AstNode(AST_TO_BITS, bits, val);
2859 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2860 SET_AST_NODE_LOC($$, @1, @1);
2862 log_error("Value conversion failed: `%s'\n", $1->c_str());
2866 $$ = new AstNode(AST_REALVALUE);
2867 char *p = (char*)malloc(GetSize(*$1) + 1), *q;
2868 for (int i = 0, j = 0; j < GetSize(*$1); j++)
2869 if ((*$1)[j] != '_')
2870 p[i++] = (*$1)[j], p[i] = 0;
2871 $$->realvalue = strtod(p, &q);
2872 SET_AST_NODE_LOC($$, @1, @1);
2873 log_assert(*q == 0);
2878 $$ = AstNode::mkconst_str(*$1);
2879 SET_AST_NODE_LOC($$, @1, @1);
2882 hierarchical_id attr {
2883 AstNode *node = new AstNode(AST_FCALL);
2886 ast_stack.push_back(node);
2887 SET_AST_NODE_LOC(node, @1, @1);
2888 append_attr(node, $2);
2889 } '(' arg_list optional_comma ')' {
2890 $$ = ast_stack.back();
2891 ast_stack.pop_back();
2893 TOK_TO_SIGNED attr '(' expr ')' {
2894 $$ = new AstNode(AST_TO_SIGNED, $4);
2895 append_attr($$, $2);
2897 TOK_TO_UNSIGNED attr '(' expr ')' {
2898 $$ = new AstNode(AST_TO_UNSIGNED, $4);
2899 append_attr($$, $2);
2904 '(' expr ':' expr ':' expr ')' {
2909 '{' concat_list '}' {
2912 '{' expr '{' concat_list '}' '}' {
2913 $$ = new AstNode(AST_REPLICATE, $2, $4);
2915 '~' attr basic_expr %prec UNARY_OPS {
2916 $$ = new AstNode(AST_BIT_NOT, $3);
2917 SET_AST_NODE_LOC($$, @1, @3);
2918 append_attr($$, $2);
2920 basic_expr '&' attr basic_expr {
2921 $$ = new AstNode(AST_BIT_AND, $1, $4);
2922 SET_AST_NODE_LOC($$, @1, @4);
2923 append_attr($$, $3);
2925 basic_expr OP_NAND attr basic_expr {
2926 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
2927 SET_AST_NODE_LOC($$, @1, @4);
2928 append_attr($$, $3);
2930 basic_expr '|' attr basic_expr {
2931 $$ = new AstNode(AST_BIT_OR, $1, $4);
2932 SET_AST_NODE_LOC($$, @1, @4);
2933 append_attr($$, $3);
2935 basic_expr OP_NOR attr basic_expr {
2936 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
2937 SET_AST_NODE_LOC($$, @1, @4);
2938 append_attr($$, $3);
2940 basic_expr '^' attr basic_expr {
2941 $$ = new AstNode(AST_BIT_XOR, $1, $4);
2942 SET_AST_NODE_LOC($$, @1, @4);
2943 append_attr($$, $3);
2945 basic_expr OP_XNOR attr basic_expr {
2946 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
2947 SET_AST_NODE_LOC($$, @1, @4);
2948 append_attr($$, $3);
2950 '&' attr basic_expr %prec UNARY_OPS {
2951 $$ = new AstNode(AST_REDUCE_AND, $3);
2952 SET_AST_NODE_LOC($$, @1, @3);
2953 append_attr($$, $2);
2955 OP_NAND attr basic_expr %prec UNARY_OPS {
2956 $$ = new AstNode(AST_REDUCE_AND, $3);
2957 SET_AST_NODE_LOC($$, @1, @3);
2958 append_attr($$, $2);
2959 $$ = new AstNode(AST_LOGIC_NOT, $$);
2961 '|' attr basic_expr %prec UNARY_OPS {
2962 $$ = new AstNode(AST_REDUCE_OR, $3);
2963 SET_AST_NODE_LOC($$, @1, @3);
2964 append_attr($$, $2);
2966 OP_NOR attr basic_expr %prec UNARY_OPS {
2967 $$ = new AstNode(AST_REDUCE_OR, $3);
2968 SET_AST_NODE_LOC($$, @1, @3);
2969 append_attr($$, $2);
2970 $$ = new AstNode(AST_LOGIC_NOT, $$);
2971 SET_AST_NODE_LOC($$, @1, @3);
2973 '^' attr basic_expr %prec UNARY_OPS {
2974 $$ = new AstNode(AST_REDUCE_XOR, $3);
2975 SET_AST_NODE_LOC($$, @1, @3);
2976 append_attr($$, $2);
2978 OP_XNOR attr basic_expr %prec UNARY_OPS {
2979 $$ = new AstNode(AST_REDUCE_XNOR, $3);
2980 SET_AST_NODE_LOC($$, @1, @3);
2981 append_attr($$, $2);
2983 basic_expr OP_SHL attr basic_expr {
2984 $$ = new AstNode(AST_SHIFT_LEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2985 SET_AST_NODE_LOC($$, @1, @4);
2986 append_attr($$, $3);
2988 basic_expr OP_SHR attr basic_expr {
2989 $$ = new AstNode(AST_SHIFT_RIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2990 SET_AST_NODE_LOC($$, @1, @4);
2991 append_attr($$, $3);
2993 basic_expr OP_SSHL attr basic_expr {
2994 $$ = new AstNode(AST_SHIFT_SLEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2995 SET_AST_NODE_LOC($$, @1, @4);
2996 append_attr($$, $3);
2998 basic_expr OP_SSHR attr basic_expr {
2999 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
3000 SET_AST_NODE_LOC($$, @1, @4);
3001 append_attr($$, $3);
3003 basic_expr '<' attr basic_expr {
3004 $$ = new AstNode(AST_LT, $1, $4);
3005 SET_AST_NODE_LOC($$, @1, @4);
3006 append_attr($$, $3);
3008 basic_expr OP_LE attr basic_expr {
3009 $$ = new AstNode(AST_LE, $1, $4);
3010 SET_AST_NODE_LOC($$, @1, @4);
3011 append_attr($$, $3);
3013 basic_expr OP_EQ attr basic_expr {
3014 $$ = new AstNode(AST_EQ, $1, $4);
3015 SET_AST_NODE_LOC($$, @1, @4);
3016 append_attr($$, $3);
3018 basic_expr OP_NE attr basic_expr {
3019 $$ = new AstNode(AST_NE, $1, $4);
3020 SET_AST_NODE_LOC($$, @1, @4);
3021 append_attr($$, $3);
3023 basic_expr OP_EQX attr basic_expr {
3024 $$ = new AstNode(AST_EQX, $1, $4);
3025 SET_AST_NODE_LOC($$, @1, @4);
3026 append_attr($$, $3);
3028 basic_expr OP_NEX attr basic_expr {
3029 $$ = new AstNode(AST_NEX, $1, $4);
3030 SET_AST_NODE_LOC($$, @1, @4);
3031 append_attr($$, $3);
3033 basic_expr OP_GE attr basic_expr {
3034 $$ = new AstNode(AST_GE, $1, $4);
3035 SET_AST_NODE_LOC($$, @1, @4);
3036 append_attr($$, $3);
3038 basic_expr '>' attr basic_expr {
3039 $$ = new AstNode(AST_GT, $1, $4);
3040 SET_AST_NODE_LOC($$, @1, @4);
3041 append_attr($$, $3);
3043 basic_expr '+' attr basic_expr {
3044 $$ = new AstNode(AST_ADD, $1, $4);
3045 SET_AST_NODE_LOC($$, @1, @4);
3046 append_attr($$, $3);
3048 basic_expr '-' attr basic_expr {
3049 $$ = new AstNode(AST_SUB, $1, $4);
3050 SET_AST_NODE_LOC($$, @1, @4);
3051 append_attr($$, $3);
3053 basic_expr '*' attr basic_expr {
3054 $$ = new AstNode(AST_MUL, $1, $4);
3055 SET_AST_NODE_LOC($$, @1, @4);
3056 append_attr($$, $3);
3058 basic_expr '/' attr basic_expr {
3059 $$ = new AstNode(AST_DIV, $1, $4);
3060 SET_AST_NODE_LOC($$, @1, @4);
3061 append_attr($$, $3);
3063 basic_expr '%' attr basic_expr {
3064 $$ = new AstNode(AST_MOD, $1, $4);
3065 SET_AST_NODE_LOC($$, @1, @4);
3066 append_attr($$, $3);
3068 basic_expr OP_POW attr basic_expr {
3069 $$ = new AstNode(AST_POW, $1, $4);
3070 SET_AST_NODE_LOC($$, @1, @4);
3071 append_attr($$, $3);
3073 '+' attr basic_expr %prec UNARY_OPS {
3074 $$ = new AstNode(AST_POS, $3);
3075 SET_AST_NODE_LOC($$, @1, @3);
3076 append_attr($$, $2);
3078 '-' attr basic_expr %prec UNARY_OPS {
3079 $$ = new AstNode(AST_NEG, $3);
3080 SET_AST_NODE_LOC($$, @1, @3);
3081 append_attr($$, $2);
3083 basic_expr OP_LAND attr basic_expr {
3084 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
3085 SET_AST_NODE_LOC($$, @1, @4);
3086 append_attr($$, $3);
3088 basic_expr OP_LOR attr basic_expr {
3089 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
3090 SET_AST_NODE_LOC($$, @1, @4);
3091 append_attr($$, $3);
3093 '!' attr basic_expr %prec UNARY_OPS {
3094 $$ = new AstNode(AST_LOGIC_NOT, $3);
3095 SET_AST_NODE_LOC($$, @1, @3);
3096 append_attr($$, $2);
3098 TOK_SIGNED OP_CAST '(' expr ')' {
3100 frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
3101 $$ = new AstNode(AST_TO_SIGNED, $4);
3102 SET_AST_NODE_LOC($$, @1, @4);
3104 TOK_UNSIGNED OP_CAST '(' expr ')' {
3106 frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
3107 $$ = new AstNode(AST_TO_UNSIGNED, $4);
3108 SET_AST_NODE_LOC($$, @1, @4);
3110 basic_expr OP_CAST '(' expr ')' {
3112 frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
3113 $$ = new AstNode(AST_CAST_SIZE, $1, $4);
3114 SET_AST_NODE_LOC($$, @1, @4);
3119 $$ = new AstNode(AST_CONCAT, $1);
3121 expr ',' concat_list {
3123 $$->children.push_back($1);
3127 TOK_CONSTVAL { $$ = $1; } |
3128 TOK_UNBASED_UNSIZED_CONSTVAL { $$ = $1; } |
3129 TOK_BASE TOK_BASED_CONSTVAL {
3134 TOK_CONSTVAL TOK_BASE TOK_BASED_CONSTVAL {
3135 $1->append(*$2).append(*$3);