frontends/verilog/verilog_parser.y

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The Verilog frontend.
  21  *
  22  *  This frontend is using the AST frontend library (see frontends/ast/).
  23  *  Thus this frontend does not generate RTLIL code directly but creates an
  24  *  AST directly from the Verilog parse tree and then passes this AST to
  25  *  the AST frontend library.
  26  *
  27  *  ---
  28  *
  29  *  This is the actual bison parser for Verilog code. The AST ist created directly
  30  *  from the bison reduce functions here. Note that this code uses a few global
  31  *  variables to hold the state of the AST generator and therefore this parser is
  32  *  not reentrant.
  33  *
  34  */
  35
  36 %{
  37 #include <list>
  38 #include <stack>
  39 #include <string.h>
  40 #include "frontends/verilog/verilog_frontend.h"
  41 #include "frontends/verilog/verilog_parser.tab.hh"
  42 #include "kernel/log.h"
  43
  44 #define YYLEX_PARAM &yylval, &yylloc
  45
  46 USING_YOSYS_NAMESPACE
  47 using namespace AST;
  48 using namespace VERILOG_FRONTEND;
  49
  50 YOSYS_NAMESPACE_BEGIN
  51 namespace VERILOG_FRONTEND {
  52         int port_counter;
  53         dict<std::string, int> port_stubs;
  54         dict<IdString, AstNode*> *attr_list, default_attr_list;
  55         std::stack<dict<IdString, AstNode*> *> attr_list_stack;
  56         dict<IdString, AstNode*> *albuf;
  57         std::vector<UserTypeMap*> user_type_stack;
  58         dict<std::string, AstNode*> pkg_user_types;
  59         std::vector<AstNode*> ast_stack;
  60         struct AstNode *astbuf1, *astbuf2, *astbuf3;
  61         struct AstNode *current_function_or_task;
  62         struct AstNode *current_ast, *current_ast_mod;
  63         int current_function_or_task_port_id;
  64         std::vector<char> case_type_stack;
  65         bool do_not_require_port_stubs;
  66         bool default_nettype_wire;
  67         bool sv_mode, formal_mode, lib_mode, specify_mode;
  68         bool noassert_mode, noassume_mode, norestrict_mode;
  69         bool assume_asserts_mode, assert_assumes_mode;
  70         bool current_wire_rand, current_wire_const;
  71         bool current_modport_input, current_modport_output;
  72         std::istream *lexin;
  73 }
  74 YOSYS_NAMESPACE_END
  75
  76 #define SET_AST_NODE_LOC(WHICH, BEGIN, END) \
  77     do { (WHICH)->location.first_line = (BEGIN).first_line; \
  78     (WHICH)->location.first_column = (BEGIN).first_column; \
  79     (WHICH)->location.last_line = (END).last_line; \
  80     (WHICH)->location.last_column = (END).last_column; } while(0)
  81
  82 #define SET_RULE_LOC(LHS, BEGIN, END) \
  83     do { (LHS).first_line = (BEGIN).first_line; \
  84     (LHS).first_column = (BEGIN).first_column; \
  85     (LHS).last_line = (END).last_line; \
  86     (LHS).last_column = (END).last_column; } while(0)
  87
  88 int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
  89
  90 static void append_attr(AstNode *ast, dict<IdString, AstNode*> *al)
  91 {
  92         for (auto &it : *al) {
  93                 if (ast->attributes.count(it.first) > 0)
  94                         delete ast->attributes[it.first];
  95                 ast->attributes[it.first] = it.second;
  96         }
  97         delete al;
  98 }
  99
 100 static void append_attr_clone(AstNode *ast, dict<IdString, AstNode*> *al)
 101 {
 102         for (auto &it : *al) {
 103                 if (ast->attributes.count(it.first) > 0)
 104                         delete ast->attributes[it.first];
 105                 ast->attributes[it.first] = it.second->clone();
 106         }
 107 }
 108
 109 static void free_attr(dict<IdString, AstNode*> *al)
 110 {
 111         for (auto &it : *al)
 112                 delete it.second;
 113         delete al;
 114 }
 115
 116 struct specify_target {
 117         char polarity_op;
 118         AstNode *dst, *dat;
 119 };
 120
 121 struct specify_triple {
 122         AstNode *t_min, *t_avg, *t_max;
 123 };
 124
 125 struct specify_rise_fall {
 126         specify_triple rise;
 127         specify_triple fall;
 128 };
 129
 130 static void addTypedefNode(std::string *name, AstNode *node)
 131 {
 132         log_assert(node);
 133         auto *tnode = new AstNode(AST_TYPEDEF, node);
 134         tnode->str = *name;
 135         auto user_types = user_type_stack.back();
 136         (*user_types)[*name] = tnode;
 137         if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {
 138                 // typedef inside a package so we need the qualified name
 139                 auto qname = current_ast_mod->str + "::" + (*name).substr(1);
 140                 pkg_user_types[qname] = tnode;
 141         }
 142         delete name;
 143         ast_stack.back()->children.push_back(tnode);
 144 }
 145
 146 static void enterTypeScope()
 147 {
 148         auto user_types = new UserTypeMap();
 149         user_type_stack.push_back(user_types);
 150 }
 151
 152 static void exitTypeScope()
 153 {
 154         user_type_stack.pop_back();
 155 }
 156
 157 static bool isInLocalScope(const std::string *name)
 158 {
 159         // tests if a name was declared in the current block scope
 160         auto user_types = user_type_stack.back();
 161         return (user_types->count(*name) > 0);
 162 }
 163
 164 static AstNode *getTypeDefinitionNode(std::string type_name)
 165 {
 166         // return the definition nodes from the typedef statement
 167         auto user_types = user_type_stack.back();
 168         log_assert(user_types->count(type_name) > 0);
 169         auto typedef_node = (*user_types)[type_name];
 170         log_assert(typedef_node->type == AST_TYPEDEF);
 171         return typedef_node->children[0];
 172 }
 173
 174 static AstNode *copyTypeDefinition(std::string type_name)
 175 {
 176         // return a copy of the template from a typedef definition
 177         auto typedef_node = getTypeDefinitionNode(type_name);
 178         return typedef_node->clone();
 179 }
 180
 181 static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
 182 {
 183         auto range = new AstNode(AST_RANGE);
 184         range->children.push_back(AstNode::mkconst_int(msb, true));
 185         range->children.push_back(AstNode::mkconst_int(lsb, true));
 186         range->is_signed = isSigned;
 187         return range;
 188 }
 189
 190 static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned = true)
 191 {
 192         auto range = makeRange(msb, lsb, isSigned);
 193         parent->children.push_back(range);
 194 }
 195
 196 static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
 197 {
 198         if (type_node->range_left >= 0 && type_node->range_right >= 0) {
 199                 // type already restricts the range
 200                 if (range_node) {
 201                         frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
 202                 }
 203                 else {
 204                         range_node = makeRange(type_node->range_left, type_node->range_right, false);
 205                 }
 206         }
 207         if (range_node && range_node->children.size() != 2) {
 208                 frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
 209         }
 210         return range_node;
 211 }
 212
 213 static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
 214 {
 215         node->type = AST_MEMORY;
 216         if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
 217                 // SV array size [n], rewrite as [n-1:0]
 218                 rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
 219                 rangeNode->children.push_back(AstNode::mkconst_int(0, false));
 220         }
 221         node->children.push_back(rangeNode);
 222 }
 223
 224 %}
 225
 226 %define api.prefix {frontend_verilog_yy}
 227 %define api.pure
 228
 229 /* The union is defined in the header, so we need to provide all the
 230  * includes it requires
 231  */
 232 %code requires {
 233 #include <map>
 234 #include <string>
 235 #include "frontends/verilog/verilog_frontend.h"
 236 }
 237
 238 %union {
 239         std::string *string;
 240         struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
 241         YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
 242         struct specify_target *specify_target_ptr;
 243         struct specify_triple *specify_triple_ptr;
 244         struct specify_rise_fall *specify_rise_fall_ptr;
 245         bool boolean;
 246         char ch;
 247 }
 248
 249 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
 250 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
 251 %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL
 252 %token <string> TOK_USER_TYPE TOK_PKG_USER_TYPE
 253 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
 254 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 255 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 256 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
 257 %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
 258 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
 259 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_PLUS_ASSIGN TOK_ALWAYS TOK_INITIAL
 260 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
 261 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
 262 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
 263 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
 264 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
 265 %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
 266 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
 267 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 268 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
 269 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
 270 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
 271 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
 272 %token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_UNION
 273 %token TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AND_ASSIGN TOK_SUB_ASSIGN
 274
 275 %type <ast> range range_or_multirange  non_opt_range non_opt_multirange range_or_signed_int
 276 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
 277 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
 278 %type <string> type_name
 279 %type <ast> opt_enum_init enum_type struct_type non_wire_data_type
 280 %type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
 281 %type <al> attr case_attr
 282 %type <ast> struct_union
 283
 284 %type <specify_target_ptr> specify_target
 285 %type <specify_triple_ptr> specify_triple specify_opt_triple
 286 %type <specify_rise_fall_ptr> specify_rise_fall
 287 %type <ast> specify_if specify_condition
 288 %type <ch> specify_edge
 289
 290 // operator precedence from low to high
 291 %left OP_LOR
 292 %left OP_LAND
 293 %left '|' OP_NOR
 294 %left '^' OP_XNOR
 295 %left '&' OP_NAND
 296 %left OP_EQ OP_NE OP_EQX OP_NEX
 297 %left '<' OP_LE OP_GE '>'
 298 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
 299 %left '+' '-'
 300 %left '*' '/' '%'
 301 %left OP_POW
 302 %left OP_CAST
 303 %right UNARY_OPS
 304
 305 %define parse.error verbose
 306 %define parse.lac full
 307
 308 %nonassoc FAKE_THEN
 309 %nonassoc TOK_ELSE
 310
 311 %debug
 312 %locations
 313
 314 %%
 315
 316 input: {
 317         ast_stack.clear();
 318         ast_stack.push_back(current_ast);
 319 } design {
 320         ast_stack.pop_back();
 321         log_assert(GetSize(ast_stack) == 0);
 322         for (auto &it : default_attr_list)
 323                 delete it.second;
 324         default_attr_list.clear();
 325 };
 326
 327 design:
 328         module design |
 329         defattr design |
 330         task_func_decl design |
 331         param_decl design |
 332         localparam_decl design |
 333         typedef_decl design |
 334         package design |
 335         interface design |
 336         /* empty */;
 337
 338 attr:
 339         {
 340                 if (attr_list != nullptr)
 341                         attr_list_stack.push(attr_list);
 342                 attr_list = new dict<IdString, AstNode*>;
 343                 for (auto &it : default_attr_list)
 344                         (*attr_list)[it.first] = it.second->clone();
 345         } attr_opt {
 346                 $$ = attr_list;
 347                 if (!attr_list_stack.empty()) {
 348                         attr_list = attr_list_stack.top();
 349                         attr_list_stack.pop();
 350                 } else
 351                         attr_list = nullptr;
 352         };
 353
 354 attr_opt:
 355         attr_opt ATTR_BEGIN opt_attr_list ATTR_END {
 356                 SET_RULE_LOC(@$, @2, @$);
 357         }|
 358         /* empty */;
 359
 360 defattr:
 361         DEFATTR_BEGIN {
 362                 if (attr_list != nullptr)
 363                         attr_list_stack.push(attr_list);
 364                 attr_list = new dict<IdString, AstNode*>;
 365                 for (auto &it : default_attr_list)
 366                         delete it.second;
 367                 default_attr_list.clear();
 368         } opt_attr_list {
 369                 attr_list->swap(default_attr_list);
 370                 delete attr_list;
 371                 if (!attr_list_stack.empty()) {
 372                         attr_list = attr_list_stack.top();
 373                         attr_list_stack.pop();
 374                 } else
 375                         attr_list = nullptr;
 376         } DEFATTR_END;
 377
 378 opt_attr_list:
 379         attr_list | /* empty */;
 380
 381 attr_list:
 382         attr_assign |
 383         attr_list ',' attr_assign;
 384
 385 attr_assign:
 386         hierarchical_id {
 387                 if (attr_list->count(*$1) != 0)
 388                         delete (*attr_list)[*$1];
 389                 (*attr_list)[*$1] = AstNode::mkconst_int(1, false);
 390                 delete $1;
 391         } |
 392         hierarchical_id '=' expr {
 393                 if (attr_list->count(*$1) != 0)
 394                         delete (*attr_list)[*$1];
 395                 (*attr_list)[*$1] = $3;
 396                 delete $1;
 397         };
 398
 399 hierarchical_id:
 400         TOK_ID {
 401                 $$ = $1;
 402         } |
 403         hierarchical_id TOK_PACKAGESEP TOK_ID {
 404                 if ($3->compare(0, 1, "\\") == 0)
 405                         *$1 += "::" + $3->substr(1);
 406                 else
 407                         *$1 += "::" + *$3;
 408                 delete $3;
 409                 $$ = $1;
 410         } |
 411         hierarchical_id '.' TOK_ID {
 412                 if ($3->compare(0, 1, "\\") == 0)
 413                         *$1 += "." + $3->substr(1);
 414                 else
 415                         *$1 += "." + *$3;
 416                 delete $3;
 417                 $$ = $1;
 418         };
 419
 420 hierarchical_type_id:
 421         TOK_USER_TYPE
 422         | TOK_PKG_USER_TYPE                             // package qualified type name
 423         | '(' TOK_USER_TYPE ')' { $$ = $2; }            // non-standard grammar
 424         ;
 425
 426 module:
 427         attr TOK_MODULE {
 428                 enterTypeScope();
 429         } TOK_ID {
 430                 do_not_require_port_stubs = false;
 431                 AstNode *mod = new AstNode(AST_MODULE);
 432                 ast_stack.back()->children.push_back(mod);
 433                 ast_stack.push_back(mod);
 434                 current_ast_mod = mod;
 435                 port_stubs.clear();
 436                 port_counter = 0;
 437                 mod->str = *$4;
 438                 append_attr(mod, $1);
 439                 delete $4;
 440         } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE opt_label {
 441                 if (port_stubs.size() != 0)
 442                         frontend_verilog_yyerror("Missing details for module port `%s'.",
 443                                         port_stubs.begin()->first.c_str());
 444                 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
 445                 ast_stack.pop_back();
 446                 log_assert(ast_stack.size() == 1);
 447                 current_ast_mod = NULL;
 448                 exitTypeScope();
 449         };
 450
 451 module_para_opt:
 452         '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
 453
 454 module_para_list:
 455         single_module_para | module_para_list ',' single_module_para;
 456
 457 single_module_para:
 458         /* empty */ |
 459         attr TOK_PARAMETER {
 460                 if (astbuf1) delete astbuf1;
 461                 astbuf1 = new AstNode(AST_PARAMETER);
 462                 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
 463                 append_attr(astbuf1, $1);
 464         } param_type single_param_decl |
 465         attr TOK_LOCALPARAM {
 466                 if (astbuf1) delete astbuf1;
 467                 astbuf1 = new AstNode(AST_LOCALPARAM);
 468                 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
 469                 append_attr(astbuf1, $1);
 470         } param_type single_param_decl |
 471         single_param_decl;
 472
 473 module_args_opt:
 474         '(' ')' | /* empty */ | '(' module_args optional_comma ')';
 475
 476 module_args:
 477         module_arg | module_args ',' module_arg;
 478
 479 optional_comma:
 480         ',' | /* empty */;
 481
 482 module_arg_opt_assignment:
 483         '=' expr {
 484                 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
 485                         AstNode *wire = new AstNode(AST_IDENTIFIER);
 486                         wire->str = ast_stack.back()->children.back()->str;
 487                         if (ast_stack.back()->children.back()->is_input) {
 488                                 AstNode *n = ast_stack.back()->children.back();
 489                                 if (n->attributes.count(ID::defaultvalue))
 490                                         delete n->attributes.at(ID::defaultvalue);
 491                                 n->attributes[ID::defaultvalue] = $2;
 492                         } else
 493                         if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
 494                                 ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
 495                         else
 496                                 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
 497                 } else
 498                         frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
 499         } |
 500         /* empty */;
 501
 502 module_arg:
 503         TOK_ID {
 504                 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
 505                         AstNode *node = ast_stack.back()->children.back()->clone();
 506                         node->str = *$1;
 507                         node->port_id = ++port_counter;
 508                         ast_stack.back()->children.push_back(node);
 509                         SET_AST_NODE_LOC(node, @1, @1);
 510                 } else {
 511                         if (port_stubs.count(*$1) != 0)
 512                                 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
 513                         port_stubs[*$1] = ++port_counter;
 514                 }
 515                 delete $1;
 516         } module_arg_opt_assignment |
 517         TOK_ID {
 518                 astbuf1 = new AstNode(AST_INTERFACEPORT);
 519                 astbuf1->children.push_back(new AstNode(AST_INTERFACEPORTTYPE));
 520                 astbuf1->children[0]->str = *$1;
 521                 delete $1;
 522         } TOK_ID {  /* SV interfaces */
 523                 if (!sv_mode)
 524                         frontend_verilog_yyerror("Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
 525                 astbuf2 = astbuf1->clone(); // really only needed if multiple instances of same type.
 526                 astbuf2->str = *$3;
 527                 delete $3;
 528                 astbuf2->port_id = ++port_counter;
 529                 ast_stack.back()->children.push_back(astbuf2);
 530                 delete astbuf1; // really only needed if multiple instances of same type.
 531         } module_arg_opt_assignment |
 532         attr wire_type range TOK_ID {
 533                 AstNode *node = $2;
 534                 node->str = *$4;
 535                 SET_AST_NODE_LOC(node, @4, @4);
 536                 node->port_id = ++port_counter;
 537                 if ($3 != NULL)
 538                         node->children.push_back($3);
 539                 if (!node->is_input && !node->is_output)
 540                         frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
 541                 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
 542                         frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
 543                 ast_stack.back()->children.push_back(node);
 544                 append_attr(node, $1);
 545                 delete $4;
 546         } module_arg_opt_assignment |
 547         '.' '.' '.' {
 548                 do_not_require_port_stubs = true;
 549         };
 550
 551 package:
 552         attr TOK_PACKAGE {
 553                 enterTypeScope();
 554         } TOK_ID {
 555                 AstNode *mod = new AstNode(AST_PACKAGE);
 556                 ast_stack.back()->children.push_back(mod);
 557                 ast_stack.push_back(mod);
 558                 current_ast_mod = mod;
 559                 mod->str = *$4;
 560                 append_attr(mod, $1);
 561         } ';' package_body TOK_ENDPACKAGE opt_label {
 562                 ast_stack.pop_back();
 563                 current_ast_mod = NULL;
 564                 exitTypeScope();
 565         };
 566
 567 package_body:
 568         package_body package_body_stmt
 569         | // optional
 570         ;
 571
 572 package_body_stmt:
 573           typedef_decl
 574         | localparam_decl
 575         | param_decl
 576         ;
 577
 578 interface:
 579         TOK_INTERFACE {
 580                 enterTypeScope();
 581         } TOK_ID {
 582                 do_not_require_port_stubs = false;
 583                 AstNode *intf = new AstNode(AST_INTERFACE);
 584                 ast_stack.back()->children.push_back(intf);
 585                 ast_stack.push_back(intf);
 586                 current_ast_mod = intf;
 587                 port_stubs.clear();
 588                 port_counter = 0;
 589                 intf->str = *$3;
 590                 delete $3;
 591         } module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
 592                 if (port_stubs.size() != 0)
 593                         frontend_verilog_yyerror("Missing details for module port `%s'.",
 594                                 port_stubs.begin()->first.c_str());
 595                 ast_stack.pop_back();
 596                 log_assert(ast_stack.size() == 1);
 597                 current_ast_mod = NULL;
 598                 exitTypeScope();
 599         };
 600
 601 interface_body:
 602         interface_body interface_body_stmt |;
 603
 604 interface_body_stmt:
 605         param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
 606         modport_stmt;
 607
 608 non_opt_delay:
 609         '#' TOK_ID { delete $2; } |
 610         '#' TOK_CONSTVAL { delete $2; } |
 611         '#' TOK_REALVAL { delete $2; } |
 612         '#' '(' expr ')' { delete $3; } |
 613         '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
 614
 615 delay:
 616         non_opt_delay | /* empty */;
 617
 618 wire_type:
 619         {
 620                 astbuf3 = new AstNode(AST_WIRE);
 621                 current_wire_rand = false;
 622                 current_wire_const = false;
 623         } wire_type_token_list {
 624                 $$ = astbuf3;
 625                 SET_RULE_LOC(@$, @2, @$);
 626         };
 627
 628 wire_type_token_list:
 629         wire_type_token |
 630         wire_type_token_list wire_type_token |
 631         wire_type_token_io |
 632         hierarchical_type_id {
 633                 astbuf3->is_custom_type = true;
 634                 astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
 635                 astbuf3->children.back()->str = *$1;
 636                 delete $1;
 637         };
 638
 639 wire_type_token_io:
 640         TOK_INPUT {
 641                 astbuf3->is_input = true;
 642         } |
 643         TOK_OUTPUT {
 644                 astbuf3->is_output = true;
 645         } |
 646         TOK_INOUT {
 647                 astbuf3->is_input = true;
 648                 astbuf3->is_output = true;
 649         };
 650
 651 wire_type_token:
 652         TOK_WIRE {
 653         } |
 654         TOK_WOR {
 655                 astbuf3->is_wor = true;
 656         } |
 657         TOK_WAND {
 658                 astbuf3->is_wand = true;
 659         } |
 660         TOK_REG {
 661                 astbuf3->is_reg = true;
 662         } |
 663         TOK_LOGIC {
 664                 astbuf3->is_logic = true;
 665         } |
 666         TOK_VAR {
 667                 astbuf3->is_logic = true;
 668         } |
 669         TOK_INTEGER {
 670                 astbuf3->is_reg = true;
 671                 astbuf3->range_left = 31;
 672                 astbuf3->range_right = 0;
 673                 astbuf3->is_signed = true;
 674         } |
 675         TOK_GENVAR {
 676                 astbuf3->type = AST_GENVAR;
 677                 astbuf3->is_reg = true;
 678                 astbuf3->is_signed = true;
 679                 astbuf3->range_left = 31;
 680                 astbuf3->range_right = 0;
 681         } |
 682         TOK_SIGNED {
 683                 astbuf3->is_signed = true;
 684         } |
 685         TOK_RAND {
 686                 current_wire_rand = true;
 687         } |
 688         TOK_CONST {
 689                 current_wire_const = true;
 690         };
 691
 692 non_opt_range:
 693         '[' expr ':' expr ']' {
 694                 $$ = new AstNode(AST_RANGE);
 695                 $$->children.push_back($2);
 696                 $$->children.push_back($4);
 697         } |
 698         '[' expr TOK_POS_INDEXED expr ']' {
 699                 $$ = new AstNode(AST_RANGE);
 700                 AstNode *expr = new AstNode(AST_SELFSZ, $2);
 701                 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
 702                 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
 703         } |
 704         '[' expr TOK_NEG_INDEXED expr ']' {
 705                 $$ = new AstNode(AST_RANGE);
 706                 AstNode *expr = new AstNode(AST_SELFSZ, $2);
 707                 $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
 708                 $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
 709         } |
 710         '[' expr ']' {
 711                 $$ = new AstNode(AST_RANGE);
 712                 $$->children.push_back($2);
 713         };
 714
 715 non_opt_multirange:
 716         non_opt_range non_opt_range {
 717                 $$ = new AstNode(AST_MULTIRANGE, $1, $2);
 718         } |
 719         non_opt_multirange non_opt_range {
 720                 $$ = $1;
 721                 $$->children.push_back($2);
 722         };
 723
 724 range:
 725         non_opt_range {
 726                 $$ = $1;
 727         } |
 728         /* empty */ {
 729                 $$ = NULL;
 730         };
 731
 732 range_or_multirange:
 733         range { $$ = $1; } |
 734         non_opt_multirange { $$ = $1; };
 735
 736 range_or_signed_int:
 737           range                 { $$ = $1; }
 738         | TOK_INTEGER           { $$ = makeRange(); }
 739         ;
 740
 741 module_body:
 742         module_body module_body_stmt |
 743         /* the following line makes the generate..endgenrate keywords optional */
 744         module_body gen_stmt |
 745         /* empty */;
 746
 747 module_body_stmt:
 748         task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
 749         enum_decl | struct_decl |
 750         always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block | /* empty statement */ ';';
 751
 752 checker_decl:
 753         TOK_CHECKER TOK_ID ';' {
 754                 AstNode *node = new AstNode(AST_GENBLOCK);
 755                 node->str = *$2;
 756                 ast_stack.back()->children.push_back(node);
 757                 ast_stack.push_back(node);
 758         } module_body TOK_ENDCHECKER {
 759                 delete $2;
 760                 ast_stack.pop_back();
 761         };
 762
 763 task_func_decl:
 764         attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
 765                 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
 766                 current_function_or_task->str = *$4;
 767                 append_attr(current_function_or_task, $1);
 768                 ast_stack.back()->children.push_back(current_function_or_task);
 769                 delete $3;
 770                 delete $4;
 771         } opt_dpi_function_args ';' {
 772                 current_function_or_task = NULL;
 773         } |
 774         attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
 775                 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
 776                 current_function_or_task->str = *$6;
 777                 append_attr(current_function_or_task, $1);
 778                 ast_stack.back()->children.push_back(current_function_or_task);
 779                 delete $3;
 780                 delete $5;
 781                 delete $6;
 782         } opt_dpi_function_args ';' {
 783                 current_function_or_task = NULL;
 784         } |
 785         attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
 786                 current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
 787                 current_function_or_task->str = *$8;
 788                 append_attr(current_function_or_task, $1);
 789                 ast_stack.back()->children.push_back(current_function_or_task);
 790                 delete $3;
 791                 delete $5;
 792                 delete $7;
 793                 delete $8;
 794         } opt_dpi_function_args ';' {
 795                 current_function_or_task = NULL;
 796         } |
 797         attr TOK_TASK opt_automatic TOK_ID {
 798                 current_function_or_task = new AstNode(AST_TASK);
 799                 current_function_or_task->str = *$4;
 800                 append_attr(current_function_or_task, $1);
 801                 ast_stack.back()->children.push_back(current_function_or_task);
 802                 ast_stack.push_back(current_function_or_task);
 803                 current_function_or_task_port_id = 1;
 804                 delete $4;
 805         } task_func_args_opt ';' task_func_body TOK_ENDTASK {
 806                 current_function_or_task = NULL;
 807                 ast_stack.pop_back();
 808         } |
 809         attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID {
 810                 current_function_or_task = new AstNode(AST_FUNCTION);
 811                 current_function_or_task->str = *$6;
 812                 append_attr(current_function_or_task, $1);
 813                 ast_stack.back()->children.push_back(current_function_or_task);
 814                 ast_stack.push_back(current_function_or_task);
 815                 AstNode *outreg = new AstNode(AST_WIRE);
 816                 outreg->str = *$6;
 817                 outreg->is_signed = $4;
 818                 outreg->is_reg = true;
 819                 if ($5 != NULL) {
 820                         outreg->children.push_back($5);
 821                         outreg->is_signed = $4 || $5->is_signed;
 822                         $5->is_signed = false;
 823                 }
 824                 current_function_or_task->children.push_back(outreg);
 825                 current_function_or_task_port_id = 1;
 826                 delete $6;
 827         } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION {
 828                 current_function_or_task = NULL;
 829                 ast_stack.pop_back();
 830         };
 831
 832 dpi_function_arg:
 833         TOK_ID TOK_ID {
 834                 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
 835                 delete $1;
 836                 delete $2;
 837         } |
 838         TOK_ID {
 839                 current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
 840                 delete $1;
 841         };
 842
 843 opt_dpi_function_args:
 844         '(' dpi_function_args ')' |
 845         /* empty */;
 846
 847 dpi_function_args:
 848         dpi_function_args ',' dpi_function_arg |
 849         dpi_function_args ',' |
 850         dpi_function_arg |
 851         /* empty */;
 852
 853 opt_automatic:
 854         TOK_AUTOMATIC |
 855         /* empty */;
 856
 857 opt_signed:
 858         TOK_SIGNED {
 859                 $$ = true;
 860         } |
 861         /* empty */ {
 862                 $$ = false;
 863         };
 864
 865 task_func_args_opt:
 866         '(' ')' | /* empty */ | '(' {
 867                 albuf = nullptr;
 868                 astbuf1 = nullptr;
 869                 astbuf2 = nullptr;
 870         } task_func_args optional_comma {
 871                 delete astbuf1;
 872                 if (astbuf2 != NULL)
 873                         delete astbuf2;
 874                 free_attr(albuf);
 875         } ')';
 876
 877 task_func_args:
 878         task_func_port | task_func_args ',' task_func_port;
 879
 880 task_func_port:
 881         attr wire_type range {
 882                 if (albuf) {
 883                         delete astbuf1;
 884                         if (astbuf2 != NULL)
 885                                 delete astbuf2;
 886                         free_attr(albuf);
 887                 }
 888                 albuf = $1;
 889                 astbuf1 = $2;
 890                 astbuf2 = checkRange(astbuf1, $3);
 891         } wire_name |
 892         {
 893                 if (!astbuf1) {
 894                         if (!sv_mode)
 895                                 frontend_verilog_yyerror("task/function argument direction missing");
 896                         albuf = new dict<IdString, AstNode*>;
 897                         astbuf1 = new AstNode(AST_WIRE);
 898                         current_wire_rand = false;
 899                         current_wire_const = false;
 900                         astbuf1->is_input = true;
 901                         astbuf2 = NULL;
 902                 }
 903         } wire_name;
 904
 905 task_func_body:
 906         task_func_body behavioral_stmt |
 907         /* empty */;
 908
 909 /*************************** specify parser ***************************/
 910
 911 specify_block:
 912         TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
 913
 914 specify_item_list:
 915         specify_item specify_item_list |
 916         /* empty */;
 917
 918 specify_item:
 919         specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
 920                 AstNode *en_expr = $1;
 921                 char specify_edge = $3;
 922                 AstNode *src_expr = $4;
 923                 string *oper = $5;
 924                 specify_target *target = $6;
 925                 specify_rise_fall *timing = $9;
 926
 927                 if (specify_edge != 0 && target->dat == nullptr)
 928                         frontend_verilog_yyerror("Found specify edge but no data spec.\n");
 929
 930                 AstNode *cell = new AstNode(AST_CELL);
 931                 ast_stack.back()->children.push_back(cell);
 932                 cell->str = stringf("$specify$%d", autoidx++);
 933                 cell->children.push_back(new AstNode(AST_CELLTYPE));
 934                 cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
 935                 SET_AST_NODE_LOC(cell, en_expr ? @1 : @2, @10);
 936
 937                 char oper_polarity = 0;
 938                 char oper_type = oper->at(0);
 939
 940                 if (oper->size() == 3) {
 941                         oper_polarity = oper->at(0);
 942                         oper_type = oper->at(1);
 943                 }
 944
 945                 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
 946                 cell->children.back()->str = "\\FULL";
 947
 948                 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
 949                 cell->children.back()->str = "\\SRC_DST_PEN";
 950
 951                 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
 952                 cell->children.back()->str = "\\SRC_DST_POL";
 953
 954                 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
 955                 cell->children.back()->str = "\\T_RISE_MIN";
 956
 957                 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
 958                 cell->children.back()->str = "\\T_RISE_TYP";
 959
 960                 cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
 961                 cell->children.back()->str = "\\T_RISE_MAX";
 962
 963                 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
 964                 cell->children.back()->str = "\\T_FALL_MIN";
 965
 966                 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
 967                 cell->children.back()->str = "\\T_FALL_TYP";
 968
 969                 cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
 970                 cell->children.back()->str = "\\T_FALL_MAX";
 971
 972                 cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
 973                 cell->children.back()->str = "\\EN";
 974
 975                 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
 976                 cell->children.back()->str = "\\SRC";
 977
 978                 cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
 979                 cell->children.back()->str = "\\DST";
 980
 981                 if (target->dat)
 982                 {
 983                         cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
 984                         cell->children.back()->str = "\\EDGE_EN";
 985
 986                         cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
 987                         cell->children.back()->str = "\\EDGE_POL";
 988
 989                         cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
 990                         cell->children.back()->str = "\\DAT_DST_PEN";
 991
 992                         cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
 993                         cell->children.back()->str = "\\DAT_DST_POL";
 994
 995                         cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
 996                         cell->children.back()->str = "\\DAT";
 997                 }
 998
 999                 delete oper;
1000                 delete target;
1001                 delete timing;
1002         } |
1003         TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' specify_triple specify_opt_triple ')' ';' {
1004                 if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
1005                                 *$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
1006                         frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
1007
1008                 AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
1009                 AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
1010                 AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
1011
1012                 AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
1013                 AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
1014                 AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
1015
1016                 specify_triple *limit = $11;
1017                 specify_triple *limit2 = $12;
1018
1019                 AstNode *cell = new AstNode(AST_CELL);
1020                 ast_stack.back()->children.push_back(cell);
1021                 cell->str = stringf("$specify$%d", autoidx++);
1022                 cell->children.push_back(new AstNode(AST_CELLTYPE));
1023                 cell->children.back()->str = "$specrule";
1024                 SET_AST_NODE_LOC(cell, @1, @14);
1025
1026                 cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
1027                 cell->children.back()->str = "\\TYPE";
1028
1029                 cell->children.push_back(new AstNode(AST_PARASET, limit->t_min));
1030                 cell->children.back()->str = "\\T_LIMIT_MIN";
1031
1032                 cell->children.push_back(new AstNode(AST_PARASET, limit->t_avg));
1033                 cell->children.back()->str = "\\T_LIMIT_TYP";
1034
1035                 cell->children.push_back(new AstNode(AST_PARASET, limit->t_max));
1036                 cell->children.back()->str = "\\T_LIMIT_MAX";
1037
1038                 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_min : AstNode::mkconst_int(0, true)));
1039                 cell->children.back()->str = "\\T_LIMIT2_MIN";
1040
1041                 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_avg : AstNode::mkconst_int(0, true)));
1042                 cell->children.back()->str = "\\T_LIMIT2_TYP";
1043
1044                 cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2->t_max : AstNode::mkconst_int(0, true)));
1045                 cell->children.back()->str = "\\T_LIMIT2_MAX";
1046
1047                 cell->children.push_back(new AstNode(AST_PARASET, src_pen));
1048                 cell->children.back()->str = "\\SRC_PEN";
1049
1050                 cell->children.push_back(new AstNode(AST_PARASET, src_pol));
1051                 cell->children.back()->str = "\\SRC_POL";
1052
1053                 cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
1054                 cell->children.back()->str = "\\DST_PEN";
1055
1056                 cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
1057                 cell->children.back()->str = "\\DST_POL";
1058
1059                 cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
1060                 cell->children.back()->str = "\\SRC_EN";
1061
1062                 cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
1063                 cell->children.back()->str = "\\SRC";
1064
1065                 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
1066                 cell->children.back()->str = "\\DST_EN";
1067
1068                 cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
1069                 cell->children.back()->str = "\\DST";
1070
1071                 delete $1;
1072         };
1073
1074 specify_opt_triple:
1075         ',' specify_triple {
1076                 $$ = $2;
1077         } |
1078         /* empty */ {
1079                 $$ = nullptr;
1080         };
1081
1082 specify_if:
1083         TOK_IF '(' expr ')' {
1084                 $$ = $3;
1085         } |
1086         /* empty */ {
1087                 $$ = nullptr;
1088         };
1089
1090 specify_condition:
1091         TOK_SPECIFY_AND expr {
1092                 $$ = $2;
1093         } |
1094         /* empty */ {
1095                 $$ = nullptr;
1096         };
1097
1098 specify_target:
1099         expr {
1100                 $$ = new specify_target;
1101                 $$->polarity_op = 0;
1102                 $$->dst = $1;
1103                 $$->dat = nullptr;
1104         } |
1105         '(' expr ':' expr ')'{
1106                 $$ = new specify_target;
1107                 $$->polarity_op = 0;
1108                 $$->dst = $2;
1109                 $$->dat = $4;
1110         } |
1111         '(' expr TOK_NEG_INDEXED expr ')'{
1112                 $$ = new specify_target;
1113                 $$->polarity_op = '-';
1114                 $$->dst = $2;
1115                 $$->dat = $4;
1116         } |
1117         '(' expr TOK_POS_INDEXED expr ')'{
1118                 $$ = new specify_target;
1119                 $$->polarity_op = '+';
1120                 $$->dst = $2;
1121                 $$->dat = $4;
1122         };
1123
1124 specify_edge:
1125         TOK_POSEDGE { $$ = 'p'; } |
1126         TOK_NEGEDGE { $$ = 'n'; } |
1127         { $$ = 0; };
1128
1129 specify_rise_fall:
1130         specify_triple {
1131                 $$ = new specify_rise_fall;
1132                 $$->rise = *$1;
1133                 $$->fall.t_min = $1->t_min->clone();
1134                 $$->fall.t_avg = $1->t_avg->clone();
1135                 $$->fall.t_max = $1->t_max->clone();
1136                 delete $1;
1137         } |
1138         '(' specify_triple ',' specify_triple ')' {
1139                 $$ = new specify_rise_fall;
1140                 $$->rise = *$2;
1141                 $$->fall = *$4;
1142                 delete $2;
1143                 delete $4;
1144         } |
1145         '(' specify_triple ',' specify_triple ',' specify_triple ')' {
1146                 $$ = new specify_rise_fall;
1147                 $$->rise = *$2;
1148                 $$->fall = *$4;
1149                 delete $2;
1150                 delete $4;
1151                 delete $6;
1152                 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1153         } |
1154         '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1155                 $$ = new specify_rise_fall;
1156                 $$->rise = *$2;
1157                 $$->fall = *$4;
1158                 delete $2;
1159                 delete $4;
1160                 delete $6;
1161                 delete $8;
1162                 delete $10;
1163                 delete $12;
1164                 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1165         } |
1166         '(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
1167                 $$ = new specify_rise_fall;
1168                 $$->rise = *$2;
1169                 $$->fall = *$4;
1170                 delete $2;
1171                 delete $4;
1172                 delete $6;
1173                 delete $8;
1174                 delete $10;
1175                 delete $12;
1176                 delete $14;
1177                 delete $16;
1178                 delete $18;
1179                 delete $20;
1180                 delete $22;
1181                 delete $24;
1182                 log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
1183         }
1184
1185 specify_triple:
1186         expr {
1187                 $$ = new specify_triple;
1188                 $$->t_min = $1;
1189                 $$->t_avg = $1->clone();
1190                 $$->t_max = $1->clone();
1191         } |
1192         expr ':' expr ':' expr {
1193                 $$ = new specify_triple;
1194                 $$->t_min = $1;
1195                 $$->t_avg = $3;
1196                 $$->t_max = $5;
1197         };
1198
1199 /******************** ignored specify parser **************************/
1200
1201 ignored_specify_block:
1202         TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
1203         TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
1204
1205 ignored_specify_item_opt:
1206         ignored_specify_item_opt ignored_specify_item |
1207         ignored_specify_item ;
1208
1209 ignored_specify_item:
1210         specparam_declaration
1211         // | pulsestyle_declaration
1212         // | showcancelled_declaration
1213         | path_declaration
1214         | system_timing_declaration
1215         ;
1216
1217 specparam_declaration:
1218         TOK_SPECPARAM list_of_specparam_assignments ';' |
1219         TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ;
1220
1221 // IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match
1222 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
1223 // exxxxtending this for SV specparam would change this anyhow
1224 specparam_range:
1225         '[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
1226
1227 list_of_specparam_assignments:
1228         specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
1229
1230 specparam_assignment:
1231         ignspec_id '=' ignspec_expr ;
1232
1233 ignspec_opt_cond:
1234         TOK_IF '(' ignspec_expr ')' | /* empty */;
1235
1236 path_declaration :
1237         simple_path_declaration ';'
1238         // | edge_sensitive_path_declaration
1239         // | state_dependent_path_declaration
1240         ;
1241
1242 simple_path_declaration :
1243         ignspec_opt_cond parallel_path_description '=' path_delay_value |
1244         ignspec_opt_cond full_path_description '=' path_delay_value
1245         ;
1246
1247 path_delay_value :
1248         '(' ignspec_expr list_of_path_delay_extra_expressions ')'
1249         |     ignspec_expr
1250         |     ignspec_expr list_of_path_delay_extra_expressions
1251         ;
1252
1253 list_of_path_delay_extra_expressions :
1254         ',' ignspec_expr
1255         | ',' ignspec_expr list_of_path_delay_extra_expressions
1256         ;
1257
1258 specify_edge_identifier :
1259         TOK_POSEDGE | TOK_NEGEDGE ;
1260
1261 parallel_path_description :
1262         '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
1263         '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
1264         '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
1265
1266 full_path_description :
1267         '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
1268         '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
1269         '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
1270
1271 // This was broken into 2 rules to solve shift/reduce conflicts
1272 list_of_path_inputs :
1273         specify_input_terminal_descriptor                  opt_polarity_operator  |
1274         specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
1275
1276 more_path_inputs :
1277     ',' specify_input_terminal_descriptor |
1278     more_path_inputs ',' specify_input_terminal_descriptor ;
1279
1280 list_of_path_outputs :
1281         specify_output_terminal_descriptor |
1282         list_of_path_outputs ',' specify_output_terminal_descriptor ;
1283
1284 opt_polarity_operator :
1285         '+'
1286         | '-'
1287         | ;
1288
1289 // Good enough for the time being
1290 specify_input_terminal_descriptor :
1291         ignspec_id ;
1292
1293 // Good enough for the time being
1294 specify_output_terminal_descriptor :
1295         ignspec_id ;
1296
1297 system_timing_declaration :
1298         ignspec_id '(' system_timing_args ')' ';' ;
1299
1300 system_timing_arg :
1301         TOK_POSEDGE ignspec_id |
1302         TOK_NEGEDGE ignspec_id |
1303         ignspec_expr ;
1304
1305 system_timing_args :
1306         system_timing_arg |
1307         system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
1308         system_timing_args ',' system_timing_arg ;
1309
1310 // for the time being this is OK, but we may write our own expr here.
1311 // as I'm not sure it is legal to use a full expr here (probably not)
1312 // On the other hand, other rules requiring constant expressions also use 'expr'
1313 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
1314 ignspec_constant_expression:
1315         expr { delete $1; };
1316
1317 ignspec_expr:
1318         expr { delete $1; } |
1319         expr ':' expr ':' expr {
1320                 delete $1;
1321                 delete $3;
1322                 delete $5;
1323         };
1324
1325 ignspec_id:
1326         TOK_ID { delete $1; }
1327         range_or_multirange { delete $3; };
1328
1329 /**********************************************************************/
1330
1331 param_signed:
1332         TOK_SIGNED {
1333                 astbuf1->is_signed = true;
1334         } | TOK_UNSIGNED {
1335                 astbuf1->is_signed = false;
1336         } | /* empty */;
1337
1338 param_integer:
1339         TOK_INTEGER {
1340                 if (astbuf1->children.size() != 1)
1341                         frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
1342                 astbuf1->children.push_back(new AstNode(AST_RANGE));
1343                 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
1344                 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
1345                 astbuf1->is_signed = true;
1346         }
1347
1348 param_real:
1349         TOK_REAL {
1350                 if (astbuf1->children.size() != 1)
1351                         frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
1352                 astbuf1->children.push_back(new AstNode(AST_REALVALUE));
1353         }
1354
1355 param_range:
1356         range {
1357                 if ($1 != NULL) {
1358                         if (astbuf1->children.size() != 1)
1359                                 frontend_verilog_yyerror("integer/real parameters should not have a range.");
1360                         astbuf1->children.push_back($1);
1361                 }
1362         };
1363
1364 param_integer_type: param_integer param_signed
1365 param_range_type: type_vec param_signed param_range
1366 param_implicit_type: param_signed param_range
1367
1368 param_type:
1369         param_integer_type | param_real | param_range_type | param_implicit_type |
1370         hierarchical_type_id {
1371                 astbuf1->is_custom_type = true;
1372                 astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
1373                 astbuf1->children.back()->str = *$1;
1374         };
1375
1376 param_decl:
1377         attr TOK_PARAMETER {
1378                 astbuf1 = new AstNode(AST_PARAMETER);
1379                 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1380                 append_attr(astbuf1, $1);
1381         } param_type param_decl_list ';' {
1382                 delete astbuf1;
1383         };
1384
1385 localparam_decl:
1386         attr TOK_LOCALPARAM {
1387                 astbuf1 = new AstNode(AST_LOCALPARAM);
1388                 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1389                 append_attr(astbuf1, $1);
1390         } param_type param_decl_list ';' {
1391                 delete astbuf1;
1392         };
1393
1394 param_decl_list:
1395         single_param_decl | param_decl_list ',' single_param_decl;
1396
1397 single_param_decl:
1398         TOK_ID '=' expr {
1399                 AstNode *node;
1400                 if (astbuf1 == nullptr) {
1401                         if (!sv_mode)
1402                                 frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword");
1403                         node = new AstNode(AST_PARAMETER);
1404                         node->children.push_back(AstNode::mkconst_int(0, true));
1405                 } else {
1406                         node = astbuf1->clone();
1407                 }
1408                 node->str = *$1;
1409                 delete node->children[0];
1410                 node->children[0] = $3;
1411                 ast_stack.back()->children.push_back(node);
1412                 delete $1;
1413         };
1414
1415 defparam_decl:
1416         TOK_DEFPARAM defparam_decl_list ';';
1417
1418 defparam_decl_list:
1419         single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
1420
1421 single_defparam_decl:
1422         range rvalue '=' expr {
1423                 AstNode *node = new AstNode(AST_DEFPARAM);
1424                 node->children.push_back($2);
1425                 node->children.push_back($4);
1426                 if ($1 != NULL)
1427                         node->children.push_back($1);
1428                 ast_stack.back()->children.push_back(node);
1429         };
1430
1431 /////////
1432 // enum
1433 /////////
1434
1435 enum_type: TOK_ENUM {
1436                 static int enum_count;
1437                 // create parent node for the enum
1438                 astbuf2 = new AstNode(AST_ENUM);
1439                 ast_stack.back()->children.push_back(astbuf2);
1440                 astbuf2->str = std::string("$enum");
1441                 astbuf2->str += std::to_string(enum_count++);
1442                 // create the template for the names
1443                 astbuf1 = new AstNode(AST_ENUM_ITEM);
1444                 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
1445          } enum_base_type '{' enum_name_list '}' {      // create template for the enum vars
1446                                                         auto tnode = astbuf1->clone();
1447                                                         delete astbuf1;
1448                                                         astbuf1 = tnode;
1449                                                         tnode->type = AST_WIRE;
1450                                                         tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
1451                                                         // drop constant but keep any range
1452                                                         delete tnode->children[0];
1453                                                         tnode->children.erase(tnode->children.begin());
1454                                                         $$ = astbuf1; }
1455          ;
1456
1457 enum_base_type: type_atom type_signing
1458         | type_vec type_signing range   { if ($3) astbuf1->children.push_back($3); }
1459         | /* nothing */                 { astbuf1->is_reg = true; addRange(astbuf1); }
1460         ;
1461
1462 type_atom: TOK_INTEGER          { astbuf1->is_reg = true; addRange(astbuf1); }          // 4-state signed
1463         |  TOK_INT              { astbuf1->is_reg = true; addRange(astbuf1); }          // 2-state signed
1464         |  TOK_SHORTINT         { astbuf1->is_reg = true; addRange(astbuf1, 15, 0); }   // 2-state signed
1465         |  TOK_BYTE             { astbuf1->is_reg = true; addRange(astbuf1,  7, 0); }   // 2-state signed
1466         ;
1467
1468 type_vec: TOK_REG               { astbuf1->is_reg   = true; }           // unsigned
1469         | TOK_LOGIC             { astbuf1->is_logic = true; }           // unsigned
1470         ;
1471
1472 type_signing:
1473           TOK_SIGNED            { astbuf1->is_signed = true; }
1474         | TOK_UNSIGNED          { astbuf1->is_signed = false; }
1475         | // optional
1476         ;
1477
1478 enum_name_list: enum_name_decl
1479         | enum_name_list ',' enum_name_decl
1480         ;
1481
1482 enum_name_decl:
1483         TOK_ID opt_enum_init {
1484                 // put in fn
1485                 log_assert(astbuf1);
1486                 log_assert(astbuf2);
1487                 auto node = astbuf1->clone();
1488                 node->str = *$1;
1489                 delete $1;
1490                 SET_AST_NODE_LOC(node, @1, @1);
1491                 delete node->children[0];
1492                 node->children[0] = $2 ? $2 : new AstNode(AST_NONE);
1493                 astbuf2->children.push_back(node);
1494         }
1495         ;
1496
1497 opt_enum_init:
1498         '=' basic_expr          { $$ = $2; }    // TODO: restrict this
1499         | /* optional */        { $$ = NULL; }
1500         ;
1501
1502 enum_var_list:
1503         enum_var
1504         | enum_var_list ',' enum_var
1505         ;
1506
1507 enum_var: TOK_ID {
1508                 log_assert(astbuf1);
1509                 log_assert(astbuf2);
1510                 auto node = astbuf1->clone();
1511                 ast_stack.back()->children.push_back(node);
1512                 node->str = *$1;
1513                 delete $1;
1514                 SET_AST_NODE_LOC(node, @1, @1);
1515                 node->is_enum = true;
1516         }
1517         ;
1518
1519 enum_decl: enum_type enum_var_list ';'          { delete $1; }
1520         ;
1521
1522 //////////////////
1523 // struct or union
1524 //////////////////
1525
1526 struct_decl: struct_type struct_var_list ';'    { delete astbuf2; }
1527         ;
1528
1529 struct_type: struct_union { astbuf2 = $1; } struct_body { $$ = astbuf2; }
1530         ;
1531
1532 struct_union:
1533           TOK_STRUCT            { $$ = new AstNode(AST_STRUCT); }
1534         | TOK_UNION             { $$ = new AstNode(AST_UNION); }
1535         ;
1536
1537 struct_body: opt_packed '{' struct_member_list '}'
1538         ;
1539
1540 opt_packed: TOK_PACKED opt_signed_struct
1541         | { frontend_verilog_yyerror("Only PACKED supported at this time"); }
1542         ;
1543
1544 opt_signed_struct:
1545           TOK_SIGNED            { astbuf2->is_signed = true; }
1546         | TOK_UNSIGNED          { astbuf2->is_signed = false; }
1547         | // default is unsigned
1548         ;
1549
1550 struct_member_list: struct_member
1551         | struct_member_list struct_member
1552         ;
1553
1554 struct_member: struct_member_type member_name_list ';'          { delete astbuf1; }
1555         ;
1556
1557 member_name_list:
1558           member_name
1559         | member_name_list ',' member_name
1560         ;
1561
1562 member_name: TOK_ID {
1563                         astbuf1->str = $1->substr(1);
1564                         delete $1;
1565                         astbuf3 = astbuf1->clone();
1566                         SET_AST_NODE_LOC(astbuf3, @1, @1);
1567                         astbuf2->children.push_back(astbuf3);
1568                 } range { if ($3) astbuf3->children.push_back($3); }
1569         ;
1570
1571 struct_member_type: { astbuf1 = new AstNode(AST_STRUCT_ITEM); } member_type_token
1572         ;
1573
1574 member_type_token:
1575           member_type
1576         | hierarchical_type_id {
1577                         // use a clone of the typedef definition nodes
1578                         auto template_node = copyTypeDefinition(*$1);
1579                         delete $1;
1580                         switch (template_node->type) {
1581                         case AST_WIRE:
1582                                 template_node->type = AST_STRUCT_ITEM;
1583                                 break;
1584                         case AST_STRUCT:
1585                         case AST_UNION:
1586                                 break;
1587                         default:
1588                                 frontend_verilog_yyerror("Invalid type for struct member: %s", type2str(template_node->type).c_str());
1589                         }
1590                         delete astbuf1;
1591                         astbuf1 = template_node;
1592                 }
1593         | struct_union {
1594                         // stash state on ast_stack
1595                         ast_stack.push_back(astbuf2);
1596                         astbuf2 = $1;
1597                 } struct_body  {
1598                         astbuf1 = astbuf2;
1599                         // recover state
1600                         astbuf2 = ast_stack.back();
1601                         ast_stack.pop_back();
1602                 }
1603         ;
1604
1605 member_type: type_atom type_signing
1606         | type_vec type_signing range_or_multirange     { if ($3) astbuf1->children.push_back($3); }
1607         ;
1608
1609 struct_var_list: struct_var
1610         | struct_var_list ',' struct_var
1611         ;
1612
1613 struct_var: TOK_ID      {       auto *var_node = astbuf2->clone();
1614                                 var_node->str = *$1;
1615                                 delete $1;
1616                                 SET_AST_NODE_LOC(var_node, @1, @1);
1617                                 ast_stack.back()->children.push_back(var_node);
1618                         }
1619         ;
1620
1621 /////////
1622 // wire
1623 /////////
1624
1625 wire_decl:
1626         attr wire_type range {
1627                 albuf = $1;
1628                 astbuf1 = $2;
1629                 astbuf2 = checkRange(astbuf1, $3);
1630         } delay wire_name_list {
1631                 delete astbuf1;
1632                 if (astbuf2 != NULL)
1633                         delete astbuf2;
1634                 free_attr(albuf);
1635         } ';' |
1636         attr TOK_SUPPLY0 TOK_ID {
1637                 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1638                 ast_stack.back()->children.back()->str = *$3;
1639                 append_attr(ast_stack.back()->children.back(), $1);
1640                 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
1641                 ast_stack.back()->children.back()->children[0]->str = *$3;
1642                 delete $3;
1643         } opt_supply_wires ';' |
1644         attr TOK_SUPPLY1 TOK_ID {
1645                 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
1646                 ast_stack.back()->children.back()->str = *$3;
1647                 append_attr(ast_stack.back()->children.back(), $1);
1648                 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
1649                 ast_stack.back()->children.back()->children[0]->str = *$3;
1650                 delete $3;
1651         } opt_supply_wires ';';
1652
1653 opt_supply_wires:
1654         /* empty */ |
1655         opt_supply_wires ',' TOK_ID {
1656                 AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
1657                 AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
1658                 wire_node->str = *$3;
1659                 assign_node->children[0]->str = *$3;
1660                 ast_stack.back()->children.push_back(wire_node);
1661                 ast_stack.back()->children.push_back(assign_node);
1662                 delete $3;
1663         };
1664
1665 wire_name_list:
1666         wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
1667
1668 wire_name_and_opt_assign:
1669         wire_name {
1670                 bool attr_anyconst = false;
1671                 bool attr_anyseq = false;
1672                 bool attr_allconst = false;
1673                 bool attr_allseq = false;
1674                 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
1675                         delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
1676                         ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
1677                         attr_anyconst = true;
1678                 }
1679                 if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
1680                         delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
1681                         ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
1682                         attr_anyseq = true;
1683                 }
1684                 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
1685                         delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
1686                         ast_stack.back()->children.back()->attributes.erase(ID::allconst);
1687                         attr_allconst = true;
1688                 }
1689                 if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
1690                         delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
1691                         ast_stack.back()->children.back()->attributes.erase(ID::allseq);
1692                         attr_allseq = true;
1693                 }
1694                 if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
1695                         AstNode *wire = new AstNode(AST_IDENTIFIER);
1696                         AstNode *fcall = new AstNode(AST_FCALL);
1697                         wire->str = ast_stack.back()->children.back()->str;
1698                         fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
1699                         if (attr_anyconst)
1700                                 fcall->str = "\\$anyconst";
1701                         if (attr_anyseq)
1702                                 fcall->str = "\\$anyseq";
1703                         if (attr_allconst)
1704                                 fcall->str = "\\$allconst";
1705                         if (attr_allseq)
1706                                 fcall->str = "\\$allseq";
1707                         fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
1708                         ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
1709                 }
1710         } |
1711         wire_name '=' expr {
1712                 AstNode *wire = new AstNode(AST_IDENTIFIER);
1713                 wire->str = ast_stack.back()->children.back()->str;
1714                 if (astbuf1->is_input) {
1715                         if (astbuf1->attributes.count(ID::defaultvalue))
1716                                 delete astbuf1->attributes.at(ID::defaultvalue);
1717                         astbuf1->attributes[ID::defaultvalue] = $3;
1718                 }
1719                 else if (astbuf1->is_reg || astbuf1->is_logic){
1720                         AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
1721                         AstNode *block = new AstNode(AST_BLOCK, assign);
1722                         AstNode *init = new AstNode(AST_INITIAL, block);
1723
1724                         SET_AST_NODE_LOC(assign, @1, @3);
1725                         SET_AST_NODE_LOC(block, @1, @3);
1726                         SET_AST_NODE_LOC(init, @1, @3);
1727
1728                         ast_stack.back()->children.push_back(init);
1729                 }
1730                 else {
1731                         AstNode *assign = new AstNode(AST_ASSIGN, wire, $3);
1732                         SET_AST_NODE_LOC(assign, @1, @3);
1733                         ast_stack.back()->children.push_back(assign);
1734                 }
1735
1736         };
1737
1738 wire_name:
1739         TOK_ID range_or_multirange {
1740                 if (astbuf1 == nullptr)
1741                         frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node.");
1742                 AstNode *node = astbuf1->clone();
1743                 node->str = *$1;
1744                 append_attr_clone(node, albuf);
1745                 if (astbuf2 != NULL)
1746                         node->children.push_back(astbuf2->clone());
1747                 if ($2 != NULL) {
1748                         if (node->is_input || node->is_output)
1749                                 frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
1750                         if (!astbuf2 && !node->is_custom_type) {
1751                                 addRange(node, 0, 0, false);
1752                         }
1753                         rewriteAsMemoryNode(node, $2);
1754                 }
1755                 if (current_function_or_task == NULL) {
1756                         if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
1757                                 port_stubs[*$1] = ++port_counter;
1758                         }
1759                         if (port_stubs.count(*$1) != 0) {
1760                                 if (!node->is_input && !node->is_output)
1761                                         frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
1762                                 if (node->is_reg && node->is_input && !node->is_output && !sv_mode)
1763                                         frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
1764                                 node->port_id = port_stubs[*$1];
1765                                 port_stubs.erase(*$1);
1766                         } else {
1767                                 if (node->is_input || node->is_output)
1768                                         frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
1769                         }
1770                 } else {
1771                         if (node->is_input || node->is_output)
1772                                 node->port_id = current_function_or_task_port_id++;
1773                 }
1774                 //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
1775                 SET_AST_NODE_LOC(node, @1, @1);
1776                 ast_stack.back()->children.push_back(node);
1777
1778                 delete $1;
1779         };
1780
1781 assign_stmt:
1782         TOK_ASSIGN delay assign_expr_list ';';
1783
1784 assign_expr_list:
1785         assign_expr | assign_expr_list ',' assign_expr;
1786
1787 assign_expr:
1788         lvalue '=' expr {
1789                 AstNode *node = new AstNode(AST_ASSIGN, $1, $3);
1790                 SET_AST_NODE_LOC(node, @$, @$);
1791                 ast_stack.back()->children.push_back(node);
1792         };
1793
1794 type_name: TOK_ID               // first time seen
1795          | TOK_USER_TYPE        { if (isInLocalScope($1)) frontend_verilog_yyerror("Duplicate declaration of TYPEDEF '%s'", $1->c_str()+1); }
1796          ;
1797
1798 typedef_decl:
1799         TOK_TYPEDEF wire_type range type_name range_or_multirange ';' {
1800                 astbuf1 = $2;
1801                 astbuf2 = checkRange(astbuf1, $3);
1802                 if (astbuf2)
1803                         astbuf1->children.push_back(astbuf2);
1804
1805                 if ($5 != NULL) {
1806                         if (!astbuf2) {
1807                                 addRange(astbuf1, 0, 0, false);
1808                         }
1809                         rewriteAsMemoryNode(astbuf1, $5);
1810                 }
1811                 addTypedefNode($4, astbuf1); }
1812         | TOK_TYPEDEF non_wire_data_type type_name ';'   { addTypedefNode($3, $2); }
1813         ;
1814
1815 non_wire_data_type:
1816           enum_type
1817         | struct_type
1818         ;
1819
1820 cell_stmt:
1821         attr TOK_ID {
1822                 astbuf1 = new AstNode(AST_CELL);
1823                 append_attr(astbuf1, $1);
1824                 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
1825                 astbuf1->children[0]->str = *$2;
1826                 delete $2;
1827         } cell_parameter_list_opt cell_list ';' {
1828                 delete astbuf1;
1829         } |
1830         attr tok_prim_wrapper delay {
1831                 astbuf1 = new AstNode(AST_PRIMITIVE);
1832                 astbuf1->str = *$2;
1833                 append_attr(astbuf1, $1);
1834                 delete $2;
1835         } prim_list ';' {
1836                 delete astbuf1;
1837         };
1838
1839 tok_prim_wrapper:
1840         TOK_PRIMITIVE {
1841                 $$ = $1;
1842         } |
1843         TOK_OR {
1844                 $$ = new std::string("or");
1845         };
1846
1847 cell_list:
1848         single_cell |
1849         cell_list ',' single_cell;
1850
1851 single_cell:
1852         TOK_ID {
1853                 astbuf2 = astbuf1->clone();
1854                 if (astbuf2->type != AST_PRIMITIVE)
1855                         astbuf2->str = *$1;
1856                 delete $1;
1857                 ast_stack.back()->children.push_back(astbuf2);
1858         } '(' cell_port_list ')' {
1859                 SET_AST_NODE_LOC(astbuf2, @1, @$);
1860         } |
1861         TOK_ID non_opt_range {
1862                 astbuf2 = astbuf1->clone();
1863                 if (astbuf2->type != AST_PRIMITIVE)
1864                         astbuf2->str = *$1;
1865                 delete $1;
1866                 ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
1867         } '(' cell_port_list ')'{
1868                 SET_AST_NODE_LOC(astbuf2, @1, @$);
1869         };
1870
1871 prim_list:
1872         single_prim |
1873         prim_list ',' single_prim;
1874
1875 single_prim:
1876         single_cell |
1877         /* no name */ {
1878                 astbuf2 = astbuf1->clone();
1879                 ast_stack.back()->children.push_back(astbuf2);
1880         } '(' cell_port_list ')' {
1881                 SET_AST_NODE_LOC(astbuf2, @1, @$);
1882         }
1883
1884 cell_parameter_list_opt:
1885         '#' '(' cell_parameter_list ')' | /* empty */;
1886
1887 cell_parameter_list:
1888         cell_parameter | cell_parameter_list ',' cell_parameter;
1889
1890 cell_parameter:
1891         /* empty */ |
1892         expr {
1893                 AstNode *node = new AstNode(AST_PARASET);
1894                 astbuf1->children.push_back(node);
1895                 node->children.push_back($1);
1896         } |
1897         '.' TOK_ID '(' expr ')' {
1898                 AstNode *node = new AstNode(AST_PARASET);
1899                 node->str = *$2;
1900                 astbuf1->children.push_back(node);
1901                 node->children.push_back($4);
1902                 delete $2;
1903         };
1904
1905 cell_port_list:
1906         cell_port_list_rules {
1907                 // remove empty args from end of list
1908                 while (!astbuf2->children.empty()) {
1909                         AstNode *node = astbuf2->children.back();
1910                         if (node->type != AST_ARGUMENT) break;
1911                         if (!node->children.empty()) break;
1912                         if (!node->str.empty()) break;
1913                         astbuf2->children.pop_back();
1914                         delete node;
1915                 }
1916
1917                 // check port types
1918                 bool has_positional_args = false;
1919                 bool has_named_args = false;
1920                 for (auto node : astbuf2->children) {
1921                         if (node->type != AST_ARGUMENT) continue;
1922                         if (node->str.empty())
1923                                 has_positional_args = true;
1924                         else
1925                                 has_named_args = true;
1926                 }
1927
1928                 if (has_positional_args && has_named_args)
1929                         frontend_verilog_yyerror("Mix of positional and named cell ports.");
1930         };
1931
1932 cell_port_list_rules:
1933         cell_port | cell_port_list_rules ',' cell_port;
1934
1935 cell_port:
1936         attr {
1937                 AstNode *node = new AstNode(AST_ARGUMENT);
1938                 astbuf2->children.push_back(node);
1939                 free_attr($1);
1940         } |
1941         attr expr {
1942                 AstNode *node = new AstNode(AST_ARGUMENT);
1943                 astbuf2->children.push_back(node);
1944                 node->children.push_back($2);
1945                 free_attr($1);
1946         } |
1947         attr '.' TOK_ID '(' expr ')' {
1948                 AstNode *node = new AstNode(AST_ARGUMENT);
1949                 node->str = *$3;
1950                 astbuf2->children.push_back(node);
1951                 node->children.push_back($5);
1952                 delete $3;
1953                 free_attr($1);
1954         } |
1955         attr '.' TOK_ID '(' ')' {
1956                 AstNode *node = new AstNode(AST_ARGUMENT);
1957                 node->str = *$3;
1958                 astbuf2->children.push_back(node);
1959                 delete $3;
1960                 free_attr($1);
1961         } |
1962         attr '.' TOK_ID {
1963                 AstNode *node = new AstNode(AST_ARGUMENT);
1964                 node->str = *$3;
1965                 astbuf2->children.push_back(node);
1966                 node->children.push_back(new AstNode(AST_IDENTIFIER));
1967                 node->children.back()->str = *$3;
1968                 delete $3;
1969                 free_attr($1);
1970         } |
1971         attr TOK_WILDCARD_CONNECT {
1972                 if (!sv_mode)
1973                         frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
1974                 astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
1975         };
1976
1977 always_comb_or_latch:
1978         TOK_ALWAYS_COMB {
1979                 $$ = false;
1980         } |
1981         TOK_ALWAYS_LATCH {
1982                 $$ = true;
1983         };
1984
1985 always_or_always_ff:
1986         TOK_ALWAYS {
1987                 $$ = false;
1988         } |
1989         TOK_ALWAYS_FF {
1990                 $$ = true;
1991         };
1992
1993 always_stmt:
1994         attr always_or_always_ff {
1995                 AstNode *node = new AstNode(AST_ALWAYS);
1996                 append_attr(node, $1);
1997                 if ($2)
1998                         node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
1999                 ast_stack.back()->children.push_back(node);
2000                 ast_stack.push_back(node);
2001         } always_cond {
2002                 AstNode *block = new AstNode(AST_BLOCK);
2003                 ast_stack.back()->children.push_back(block);
2004                 ast_stack.push_back(block);
2005         } behavioral_stmt {
2006                 SET_AST_NODE_LOC(ast_stack.back(), @6, @6);
2007                 ast_stack.pop_back();
2008
2009                 SET_AST_NODE_LOC(ast_stack.back(), @2, @$);
2010                 ast_stack.pop_back();
2011
2012                 SET_RULE_LOC(@$, @2, @$);
2013         } |
2014         attr always_comb_or_latch {
2015                 AstNode *node = new AstNode(AST_ALWAYS);
2016                 append_attr(node, $1);
2017                 if ($2)
2018                         node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
2019                 else
2020                         node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
2021                 ast_stack.back()->children.push_back(node);
2022                 ast_stack.push_back(node);
2023                 AstNode *block = new AstNode(AST_BLOCK);
2024                 ast_stack.back()->children.push_back(block);
2025                 ast_stack.push_back(block);
2026         } behavioral_stmt {
2027                 ast_stack.pop_back();
2028                 ast_stack.pop_back();
2029         } |
2030         attr TOK_INITIAL {
2031                 AstNode *node = new AstNode(AST_INITIAL);
2032                 append_attr(node, $1);
2033                 ast_stack.back()->children.push_back(node);
2034                 ast_stack.push_back(node);
2035                 AstNode *block = new AstNode(AST_BLOCK);
2036                 ast_stack.back()->children.push_back(block);
2037                 ast_stack.push_back(block);
2038         } behavioral_stmt {
2039                 ast_stack.pop_back();
2040                 ast_stack.pop_back();
2041         };
2042
2043 always_cond:
2044         '@' '(' always_events ')' |
2045         '@' '(' '*' ')' |
2046         '@' ATTR_BEGIN ')' |
2047         '@' '(' ATTR_END |
2048         '@' '*' |
2049         /* empty */;
2050
2051 always_events:
2052         always_event |
2053         always_events TOK_OR always_event |
2054         always_events ',' always_event;
2055
2056 always_event:
2057         TOK_POSEDGE expr {
2058                 AstNode *node = new AstNode(AST_POSEDGE);
2059                 SET_AST_NODE_LOC(node, @1, @1);
2060                 ast_stack.back()->children.push_back(node);
2061                 node->children.push_back($2);
2062         } |
2063         TOK_NEGEDGE expr {
2064                 AstNode *node = new AstNode(AST_NEGEDGE);
2065                 SET_AST_NODE_LOC(node, @1, @1);
2066                 ast_stack.back()->children.push_back(node);
2067                 node->children.push_back($2);
2068         } |
2069         expr {
2070                 AstNode *node = new AstNode(AST_EDGE);
2071                 ast_stack.back()->children.push_back(node);
2072                 node->children.push_back($1);
2073         };
2074
2075 opt_label:
2076         ':' TOK_ID {
2077                 $$ = $2;
2078         } |
2079         /* empty */ {
2080                 $$ = NULL;
2081         };
2082
2083 opt_sva_label:
2084         TOK_SVA_LABEL ':' {
2085                 $$ = $1;
2086         } |
2087         /* empty */ {
2088                 $$ = NULL;
2089         };
2090
2091 opt_property:
2092         TOK_PROPERTY {
2093                 $$ = true;
2094         } |
2095         TOK_FINAL {
2096                 $$ = false;
2097         } |
2098         /* empty */ {
2099                 $$ = false;
2100         };
2101
2102 modport_stmt:
2103     TOK_MODPORT TOK_ID {
2104         AstNode *modport = new AstNode(AST_MODPORT);
2105         ast_stack.back()->children.push_back(modport);
2106         ast_stack.push_back(modport);
2107         modport->str = *$2;
2108         delete $2;
2109     }  modport_args_opt {
2110         ast_stack.pop_back();
2111         log_assert(ast_stack.size() == 2);
2112     } ';'
2113
2114 modport_args_opt:
2115     '(' ')' | '(' modport_args optional_comma ')';
2116
2117 modport_args:
2118     modport_arg | modport_args ',' modport_arg;
2119
2120 modport_arg:
2121     modport_type_token modport_member |
2122     modport_member
2123
2124 modport_member:
2125     TOK_ID {
2126         AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
2127         ast_stack.back()->children.push_back(modport_member);
2128         modport_member->str = *$1;
2129         modport_member->is_input = current_modport_input;
2130         modport_member->is_output = current_modport_output;
2131         delete $1;
2132     }
2133
2134 modport_type_token:
2135     TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
2136
2137 assert:
2138         opt_sva_label TOK_ASSERT opt_property '(' expr ')' ';' {
2139                 if (noassert_mode) {
2140                         delete $5;
2141                 } else {
2142                         AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2143                         SET_AST_NODE_LOC(node, @1, @6);
2144                         if ($1 != nullptr)
2145                                 node->str = *$1;
2146                         ast_stack.back()->children.push_back(node);
2147                 }
2148                 if ($1 != nullptr)
2149                         delete $1;
2150         } |
2151         opt_sva_label TOK_ASSUME opt_property '(' expr ')' ';' {
2152                 if (noassume_mode) {
2153                         delete $5;
2154                 } else {
2155                         AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
2156                         SET_AST_NODE_LOC(node, @1, @6);
2157                         if ($1 != nullptr)
2158                                 node->str = *$1;
2159                         ast_stack.back()->children.push_back(node);
2160                 }
2161                 if ($1 != nullptr)
2162                         delete $1;
2163         } |
2164         opt_sva_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2165                 if (noassert_mode) {
2166                         delete $6;
2167                 } else {
2168                         AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2169                         SET_AST_NODE_LOC(node, @1, @7);
2170                         if ($1 != nullptr)
2171                                 node->str = *$1;
2172                         ast_stack.back()->children.push_back(node);
2173                 }
2174                 if ($1 != nullptr)
2175                         delete $1;
2176         } |
2177         opt_sva_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2178                 if (noassume_mode) {
2179                         delete $6;
2180                 } else {
2181                         AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
2182                         SET_AST_NODE_LOC(node, @1, @7);
2183                         if ($1 != nullptr)
2184                                 node->str = *$1;
2185                         ast_stack.back()->children.push_back(node);
2186                 }
2187                 if ($1 != nullptr)
2188                         delete $1;
2189         } |
2190         opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
2191                 AstNode *node = new AstNode(AST_COVER, $5);
2192                 SET_AST_NODE_LOC(node, @1, @6);
2193                 if ($1 != nullptr) {
2194                         node->str = *$1;
2195                         delete $1;
2196                 }
2197                 ast_stack.back()->children.push_back(node);
2198         } |
2199         opt_sva_label TOK_COVER opt_property '(' ')' ';' {
2200                 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2201                 SET_AST_NODE_LOC(node, @1, @5);
2202                 if ($1 != nullptr) {
2203                         node->str = *$1;
2204                         delete $1;
2205                 }
2206                 ast_stack.back()->children.push_back(node);
2207         } |
2208         opt_sva_label TOK_COVER ';' {
2209                 AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
2210                 SET_AST_NODE_LOC(node, @1, @2);
2211                 if ($1 != nullptr) {
2212                         node->str = *$1;
2213                         delete $1;
2214                 }
2215                 ast_stack.back()->children.push_back(node);
2216         } |
2217         opt_sva_label TOK_RESTRICT opt_property '(' expr ')' ';' {
2218                 if (norestrict_mode) {
2219                         delete $5;
2220                 } else {
2221                         AstNode *node = new AstNode(AST_ASSUME, $5);
2222                         SET_AST_NODE_LOC(node, @1, @6);
2223                         if ($1 != nullptr)
2224                                 node->str = *$1;
2225                         ast_stack.back()->children.push_back(node);
2226                 }
2227                 if (!$3)
2228                         log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2229                 if ($1 != nullptr)
2230                         delete $1;
2231         } |
2232         opt_sva_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
2233                 if (norestrict_mode) {
2234                         delete $6;
2235                 } else {
2236                         AstNode *node = new AstNode(AST_FAIR, $6);
2237                         SET_AST_NODE_LOC(node, @1, @7);
2238                         if ($1 != nullptr)
2239                                 node->str = *$1;
2240                         ast_stack.back()->children.push_back(node);
2241                 }
2242                 if (!$3)
2243                         log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
2244                 if ($1 != nullptr)
2245                         delete $1;
2246         };
2247
2248 assert_property:
2249         opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
2250                 AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
2251                 SET_AST_NODE_LOC(node, @1, @6);
2252                 ast_stack.back()->children.push_back(node);
2253                 if ($1 != nullptr) {
2254                         ast_stack.back()->children.back()->str = *$1;
2255                         delete $1;
2256                 }
2257         } |
2258         opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
2259                 AstNode *node = new AstNode(AST_ASSUME, $5);
2260                 SET_AST_NODE_LOC(node, @1, @6);
2261                 ast_stack.back()->children.push_back(node);
2262                 if ($1 != nullptr) {
2263                         ast_stack.back()->children.back()->str = *$1;
2264                         delete $1;
2265                 }
2266         } |
2267         opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2268                 AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
2269                 SET_AST_NODE_LOC(node, @1, @7);
2270                 ast_stack.back()->children.push_back(node);
2271                 if ($1 != nullptr) {
2272                         ast_stack.back()->children.back()->str = *$1;
2273                         delete $1;
2274                 }
2275         } |
2276         opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2277                 AstNode *node = new AstNode(AST_FAIR, $6);
2278                 SET_AST_NODE_LOC(node, @1, @7);
2279                 ast_stack.back()->children.push_back(node);
2280                 if ($1 != nullptr) {
2281                         ast_stack.back()->children.back()->str = *$1;
2282                         delete $1;
2283                 }
2284         } |
2285         opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
2286                 AstNode *node = new AstNode(AST_COVER, $5);
2287                 SET_AST_NODE_LOC(node, @1, @6);
2288                 ast_stack.back()->children.push_back(node);
2289                 if ($1 != nullptr) {
2290                         ast_stack.back()->children.back()->str = *$1;
2291                         delete $1;
2292                 }
2293         } |
2294         opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
2295                 if (norestrict_mode) {
2296                         delete $5;
2297                 } else {
2298                         AstNode *node = new AstNode(AST_ASSUME, $5);
2299                         SET_AST_NODE_LOC(node, @1, @6);
2300                         ast_stack.back()->children.push_back(node);
2301                         if ($1 != nullptr) {
2302                                 ast_stack.back()->children.back()->str = *$1;
2303                                 delete $1;
2304                         }
2305                 }
2306         } |
2307         opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
2308                 if (norestrict_mode) {
2309                         delete $6;
2310                 } else {
2311                         AstNode *node = new AstNode(AST_FAIR, $6);
2312                         SET_AST_NODE_LOC(node, @1, @7);
2313                         ast_stack.back()->children.push_back(node);
2314                         if ($1 != nullptr) {
2315                                 ast_stack.back()->children.back()->str = *$1;
2316                                 delete $1;
2317                         }
2318                 }
2319         };
2320
2321 simple_behavioral_stmt:
2322         attr lvalue '=' delay expr {
2323                 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $5);
2324                 ast_stack.back()->children.push_back(node);
2325                 SET_AST_NODE_LOC(node, @2, @5);
2326                 append_attr(node, $1);
2327         } |
2328         attr lvalue TOK_INCREMENT {
2329                 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)));
2330                 ast_stack.back()->children.push_back(node);
2331                 SET_AST_NODE_LOC(node, @2, @3);
2332                 append_attr(node, $1);
2333         } |
2334         attr lvalue TOK_DECREMENT {
2335                 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_SUB, $2->clone(), AstNode::mkconst_int(1, true)));
2336                 ast_stack.back()->children.push_back(node);
2337                 SET_AST_NODE_LOC(node, @2, @3);
2338                 append_attr(node, $1);
2339         } |
2340         attr lvalue OP_LE delay expr {
2341                 AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5);
2342                 ast_stack.back()->children.push_back(node);
2343                 SET_AST_NODE_LOC(node, @2, @5);
2344                 append_attr(node, $1);
2345         } |
2346         attr lvalue TOK_XOR_ASSIGN delay expr {
2347                 AstNode *xor_node = new AstNode(AST_BIT_XOR, $2->clone(), $5);
2348                 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, xor_node);
2349                 SET_AST_NODE_LOC(xor_node, @2, @5);
2350                 SET_AST_NODE_LOC(node, @2, @5);
2351                 ast_stack.back()->children.push_back(node);
2352                 append_attr(node, $1);
2353         } |
2354         attr lvalue TOK_OR_ASSIGN delay expr {
2355                 AstNode *or_node = new AstNode(AST_BIT_OR, $2->clone(), $5);
2356                 SET_AST_NODE_LOC(or_node, @2, @5);
2357                 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, or_node);
2358                 SET_AST_NODE_LOC(node, @2, @5);
2359                 ast_stack.back()->children.push_back(node);
2360                 append_attr(node, $1);
2361         } |
2362         attr lvalue TOK_PLUS_ASSIGN delay expr {
2363                 AstNode *add_node = new AstNode(AST_ADD, $2->clone(), $5);
2364                 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, add_node);
2365                 SET_AST_NODE_LOC(node, @2, @5);
2366                 SET_AST_NODE_LOC(add_node, @2, @5);
2367                 ast_stack.back()->children.push_back(node);
2368                 append_attr(node, $1);
2369         } |
2370         attr lvalue TOK_SUB_ASSIGN delay expr {
2371                 AstNode *sub_node = new AstNode(AST_SUB, $2->clone(), $5);
2372                 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, sub_node);
2373                 SET_AST_NODE_LOC(node, @2, @5);
2374                 SET_AST_NODE_LOC(sub_node, @2, @5);
2375                 ast_stack.back()->children.push_back(node);
2376                 append_attr(node, $1);
2377         } |
2378         attr lvalue TOK_AND_ASSIGN delay expr {
2379                 AstNode *and_node = new AstNode(AST_BIT_AND, $2->clone(), $5);
2380                 AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, and_node);
2381                 SET_AST_NODE_LOC(node, @2, @5);
2382                 SET_AST_NODE_LOC(and_node, @2, @5);
2383                 ast_stack.back()->children.push_back(node);
2384                 append_attr(node, $1);
2385         };
2386
2387 // this production creates the obligatory if-else shift/reduce conflict
2388 behavioral_stmt:
2389         defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
2390         non_opt_delay behavioral_stmt |
2391         simple_behavioral_stmt ';' |
2392         attr ';' {
2393                 free_attr($1);
2394         } |
2395         attr hierarchical_id {
2396                 AstNode *node = new AstNode(AST_TCALL);
2397                 node->str = *$2;
2398                 delete $2;
2399                 ast_stack.back()->children.push_back(node);
2400                 ast_stack.push_back(node);
2401                 append_attr(node, $1);
2402         } opt_arg_list ';'{
2403                 ast_stack.pop_back();
2404         } |
2405         attr TOK_MSG_TASKS {
2406                 AstNode *node = new AstNode(AST_TCALL);
2407                 node->str = *$2;
2408                 delete $2;
2409                 ast_stack.back()->children.push_back(node);
2410                 ast_stack.push_back(node);
2411                 append_attr(node, $1);
2412         } opt_arg_list ';'{
2413                 ast_stack.pop_back();
2414         } |
2415         attr TOK_BEGIN {
2416                 enterTypeScope();
2417         } opt_label {
2418                 AstNode *node = new AstNode(AST_BLOCK);
2419                 ast_stack.back()->children.push_back(node);
2420                 ast_stack.push_back(node);
2421                 append_attr(node, $1);
2422                 if ($4 != NULL)
2423                         node->str = *$4;
2424         } behavioral_stmt_list TOK_END opt_label {
2425                 exitTypeScope();
2426                 if ($4 != NULL && $8 != NULL && *$4 != *$8)
2427                         frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
2428                 SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
2429                 delete $4;
2430                 delete $8;
2431                 ast_stack.pop_back();
2432         } |
2433         attr TOK_FOR '(' {
2434                 AstNode *node = new AstNode(AST_FOR);
2435                 ast_stack.back()->children.push_back(node);
2436                 ast_stack.push_back(node);
2437                 append_attr(node, $1);
2438         } simple_behavioral_stmt ';' expr {
2439                 ast_stack.back()->children.push_back($7);
2440         } ';' simple_behavioral_stmt ')' {
2441                 AstNode *block = new AstNode(AST_BLOCK);
2442                 ast_stack.back()->children.push_back(block);
2443                 ast_stack.push_back(block);
2444         } behavioral_stmt {
2445                 SET_AST_NODE_LOC(ast_stack.back(), @13, @13);
2446                 ast_stack.pop_back();
2447                 SET_AST_NODE_LOC(ast_stack.back(), @2, @13);
2448                 ast_stack.pop_back();
2449         } |
2450         attr TOK_WHILE '(' expr ')' {
2451                 AstNode *node = new AstNode(AST_WHILE);
2452                 ast_stack.back()->children.push_back(node);
2453                 ast_stack.push_back(node);
2454                 append_attr(node, $1);
2455                 AstNode *block = new AstNode(AST_BLOCK);
2456                 ast_stack.back()->children.push_back($4);
2457                 ast_stack.back()->children.push_back(block);
2458                 ast_stack.push_back(block);
2459         } behavioral_stmt {
2460                 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2461                 ast_stack.pop_back();
2462                 ast_stack.pop_back();
2463         } |
2464         attr TOK_REPEAT '(' expr ')' {
2465                 AstNode *node = new AstNode(AST_REPEAT);
2466                 ast_stack.back()->children.push_back(node);
2467                 ast_stack.push_back(node);
2468                 append_attr(node, $1);
2469                 AstNode *block = new AstNode(AST_BLOCK);
2470                 ast_stack.back()->children.push_back($4);
2471                 ast_stack.back()->children.push_back(block);
2472                 ast_stack.push_back(block);
2473         } behavioral_stmt {
2474                 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2475                 ast_stack.pop_back();
2476                 ast_stack.pop_back();
2477         } |
2478         attr TOK_IF '(' expr ')' {
2479                 AstNode *node = new AstNode(AST_CASE);
2480                 AstNode *block = new AstNode(AST_BLOCK);
2481                 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
2482                 SET_AST_NODE_LOC(cond, @4, @4);
2483                 ast_stack.back()->children.push_back(node);
2484                 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
2485                 node->children.push_back(cond);
2486                 ast_stack.push_back(node);
2487                 ast_stack.push_back(block);
2488                 append_attr(node, $1);
2489         } behavioral_stmt {
2490                 SET_AST_NODE_LOC(ast_stack.back(), @7, @7);
2491         } optional_else {
2492                 ast_stack.pop_back();
2493                 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2494                 ast_stack.pop_back();
2495         } |
2496         case_attr case_type '(' expr ')' {
2497                 AstNode *node = new AstNode(AST_CASE, $4);
2498                 ast_stack.back()->children.push_back(node);
2499                 ast_stack.push_back(node);
2500                 append_attr(node, $1);
2501                 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2502         } opt_synopsys_attr case_body TOK_ENDCASE {
2503                 SET_AST_NODE_LOC(ast_stack.back(), @2, @9);
2504                 case_type_stack.pop_back();
2505                 ast_stack.pop_back();
2506         };
2507
2508 unique_case_attr:
2509         /* empty */ {
2510                 $$ = false;
2511         } |
2512         TOK_PRIORITY case_attr {
2513                 $$ = $2;
2514         } |
2515         TOK_UNIQUE case_attr {
2516                 $$ = true;
2517         };
2518
2519 case_attr:
2520         attr unique_case_attr {
2521                 if ($2) (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false);
2522                 $$ = $1;
2523         };
2524
2525 case_type:
2526         TOK_CASE {
2527                 case_type_stack.push_back(0);
2528         } |
2529         TOK_CASEX {
2530                 case_type_stack.push_back('x');
2531         } |
2532         TOK_CASEZ {
2533                 case_type_stack.push_back('z');
2534         };
2535
2536 opt_synopsys_attr:
2537         opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
2538                 if (ast_stack.back()->attributes.count(ID::full_case) == 0)
2539                         ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
2540         } |
2541         opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
2542                 if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
2543                         ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
2544         } |
2545         /* empty */;
2546
2547 behavioral_stmt_list:
2548         behavioral_stmt_list behavioral_stmt |
2549         /* empty */;
2550
2551 optional_else:
2552         TOK_ELSE {
2553                 AstNode *block = new AstNode(AST_BLOCK);
2554                 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
2555                 SET_AST_NODE_LOC(cond, @1, @1);
2556
2557                 ast_stack.pop_back();
2558                 ast_stack.back()->children.push_back(cond);
2559                 ast_stack.push_back(block);
2560         } behavioral_stmt {
2561                 SET_AST_NODE_LOC(ast_stack.back(), @3, @3);
2562         } |
2563         /* empty */ %prec FAKE_THEN;
2564
2565 case_body:
2566         case_body case_item |
2567         /* empty */;
2568
2569 case_item:
2570         {
2571                 AstNode *node = new AstNode(
2572                                 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2573                                 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2574                 ast_stack.back()->children.push_back(node);
2575                 ast_stack.push_back(node);
2576         } case_select {
2577                 AstNode *block = new AstNode(AST_BLOCK);
2578                 ast_stack.back()->children.push_back(block);
2579                 ast_stack.push_back(block);
2580                 case_type_stack.push_back(0);
2581         } behavioral_stmt {
2582                 case_type_stack.pop_back();
2583                 SET_AST_NODE_LOC(ast_stack.back(), @4, @4);
2584                 ast_stack.pop_back();
2585                 ast_stack.pop_back();
2586         };
2587
2588 gen_case_body:
2589         gen_case_body gen_case_item |
2590         /* empty */;
2591
2592 gen_case_item:
2593         {
2594                 AstNode *node = new AstNode(
2595                                 case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
2596                                 case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
2597                 ast_stack.back()->children.push_back(node);
2598                 ast_stack.push_back(node);
2599         } case_select {
2600                 case_type_stack.push_back(0);
2601                 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2602         } gen_stmt_block {
2603                 case_type_stack.pop_back();
2604                 ast_stack.pop_back();
2605         };
2606
2607 case_select:
2608         case_expr_list ':' |
2609         TOK_DEFAULT;
2610
2611 case_expr_list:
2612         TOK_DEFAULT {
2613                 AstNode *node = new AstNode(AST_DEFAULT);
2614                 SET_AST_NODE_LOC(node, @1, @1);
2615                 ast_stack.back()->children.push_back(node);
2616         } |
2617         TOK_SVA_LABEL {
2618                 AstNode *node = new AstNode(AST_IDENTIFIER);
2619                 SET_AST_NODE_LOC(node, @1, @1);
2620                 ast_stack.back()->children.push_back(node);
2621                 ast_stack.back()->children.back()->str = *$1;
2622                 delete $1;
2623         } |
2624         expr {
2625                 ast_stack.back()->children.push_back($1);
2626         } |
2627         case_expr_list ',' expr {
2628                 ast_stack.back()->children.push_back($3);
2629         };
2630
2631 rvalue:
2632         hierarchical_id '[' expr ']' '.' rvalue {
2633                 $$ = new AstNode(AST_PREFIX, $3, $6);
2634                 $$->str = *$1;
2635                 delete $1;
2636         } |
2637         hierarchical_id range {
2638                 $$ = new AstNode(AST_IDENTIFIER, $2);
2639                 $$->str = *$1;
2640                 SET_AST_NODE_LOC($$, @1, @1);
2641                 delete $1;
2642                 if ($2 == nullptr && ($$->str == "\\$initstate" ||
2643                                 $$->str == "\\$anyconst" || $$->str == "\\$anyseq" ||
2644                                 $$->str == "\\$allconst" || $$->str == "\\$allseq"))
2645                         $$->type = AST_FCALL;
2646         } |
2647         hierarchical_id non_opt_multirange {
2648                 $$ = new AstNode(AST_IDENTIFIER, $2);
2649                 $$->str = *$1;
2650                 SET_AST_NODE_LOC($$, @1, @1);
2651                 delete $1;
2652         };
2653
2654 lvalue:
2655         rvalue {
2656                 $$ = $1;
2657         } |
2658         '{' lvalue_concat_list '}' {
2659                 $$ = $2;
2660         };
2661
2662 lvalue_concat_list:
2663         expr {
2664                 $$ = new AstNode(AST_CONCAT);
2665                 $$->children.push_back($1);
2666         } |
2667         expr ',' lvalue_concat_list {
2668                 $$ = $3;
2669                 $$->children.push_back($1);
2670         };
2671
2672 opt_arg_list:
2673         '(' arg_list optional_comma ')' |
2674         /* empty */;
2675
2676 arg_list:
2677         arg_list2 |
2678         /* empty */;
2679
2680 arg_list2:
2681         single_arg |
2682         arg_list ',' single_arg;
2683
2684 single_arg:
2685         expr {
2686                 ast_stack.back()->children.push_back($1);
2687         };
2688
2689 module_gen_body:
2690         module_gen_body gen_stmt_or_module_body_stmt |
2691         /* empty */;
2692
2693 gen_stmt_or_module_body_stmt:
2694         gen_stmt | module_body_stmt |
2695         attr ';' {
2696                 free_attr($1);
2697         };
2698
2699 // this production creates the obligatory if-else shift/reduce conflict
2700 gen_stmt:
2701         TOK_FOR '(' {
2702                 AstNode *node = new AstNode(AST_GENFOR);
2703                 ast_stack.back()->children.push_back(node);
2704                 ast_stack.push_back(node);
2705         } simple_behavioral_stmt ';' expr {
2706                 ast_stack.back()->children.push_back($6);
2707         } ';' simple_behavioral_stmt ')' gen_stmt_block {
2708                 SET_AST_NODE_LOC(ast_stack.back(), @1, @11);
2709                 ast_stack.pop_back();
2710         } |
2711         TOK_IF '(' expr ')' {
2712                 AstNode *node = new AstNode(AST_GENIF);
2713                 ast_stack.back()->children.push_back(node);
2714                 ast_stack.push_back(node);
2715                 ast_stack.back()->children.push_back($3);
2716                 AstNode *block = new AstNode(AST_GENBLOCK);
2717                 ast_stack.back()->children.push_back(block);
2718                 ast_stack.push_back(block);
2719         } gen_stmt_block {
2720                 ast_stack.pop_back();
2721         } opt_gen_else {
2722                 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2723                 ast_stack.pop_back();
2724         } |
2725         case_type '(' expr ')' {
2726                 AstNode *node = new AstNode(AST_GENCASE, $3);
2727                 ast_stack.back()->children.push_back(node);
2728                 ast_stack.push_back(node);
2729         } gen_case_body TOK_ENDCASE {
2730                 case_type_stack.pop_back();
2731                 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2732                 ast_stack.pop_back();
2733         } |
2734         TOK_BEGIN {
2735                 enterTypeScope();
2736         } opt_label {
2737                 AstNode *node = new AstNode(AST_GENBLOCK);
2738                 node->str = $3 ? *$3 : std::string();
2739                 ast_stack.back()->children.push_back(node);
2740                 ast_stack.push_back(node);
2741         } module_gen_body TOK_END opt_label {
2742                 exitTypeScope();
2743                 delete $3;
2744                 delete $7;
2745                 SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
2746                 ast_stack.pop_back();
2747         } |
2748         TOK_MSG_TASKS {
2749                 AstNode *node = new AstNode(AST_TECALL);
2750                 node->str = *$1;
2751                 delete $1;
2752                 ast_stack.back()->children.push_back(node);
2753                 ast_stack.push_back(node);
2754         } opt_arg_list ';'{
2755                 SET_AST_NODE_LOC(ast_stack.back(), @1, @3);
2756                 ast_stack.pop_back();
2757         };
2758
2759 gen_stmt_block:
2760         {
2761                 AstNode *node = new AstNode(AST_GENBLOCK);
2762                 ast_stack.back()->children.push_back(node);
2763                 ast_stack.push_back(node);
2764         } gen_stmt_or_module_body_stmt {
2765                 SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
2766                 ast_stack.pop_back();
2767         };
2768
2769 opt_gen_else:
2770         TOK_ELSE gen_stmt_block | /* empty */ %prec FAKE_THEN;
2771
2772 expr:
2773         basic_expr {
2774                 $$ = $1;
2775         } |
2776         basic_expr '?' attr expr ':' expr {
2777                 $$ = new AstNode(AST_TERNARY);
2778                 $$->children.push_back($1);
2779                 $$->children.push_back($4);
2780                 $$->children.push_back($6);
2781                 SET_AST_NODE_LOC($$, @1, @$);
2782                 append_attr($$, $3);
2783         };
2784
2785 basic_expr:
2786         rvalue {
2787                 $$ = $1;
2788         } |
2789         '(' expr ')' integral_number {
2790                 if ($4->compare(0, 1, "'") != 0)
2791                         frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
2792                 AstNode *bits = $2;
2793                 AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2794                 if (val == NULL)
2795                         log_error("Value conversion failed: `%s'\n", $4->c_str());
2796                 $$ = new AstNode(AST_TO_BITS, bits, val);
2797                 delete $4;
2798         } |
2799         hierarchical_id integral_number {
2800                 if ($2->compare(0, 1, "'") != 0)
2801                         frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
2802                 AstNode *bits = new AstNode(AST_IDENTIFIER);
2803                 bits->str = *$1;
2804                 SET_AST_NODE_LOC(bits, @1, @1);
2805                 AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2806                 SET_AST_NODE_LOC(val, @2, @2);
2807                 if (val == NULL)
2808                         log_error("Value conversion failed: `%s'\n", $2->c_str());
2809                 $$ = new AstNode(AST_TO_BITS, bits, val);
2810                 delete $1;
2811                 delete $2;
2812         } |
2813         integral_number {
2814                 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
2815                 SET_AST_NODE_LOC($$, @1, @1);
2816                 if ($$ == NULL)
2817                         log_error("Value conversion failed: `%s'\n", $1->c_str());
2818                 delete $1;
2819         } |
2820         TOK_REALVAL {
2821                 $$ = new AstNode(AST_REALVALUE);
2822                 char *p = (char*)malloc(GetSize(*$1) + 1), *q;
2823                 for (int i = 0, j = 0; j < GetSize(*$1); j++)
2824                         if ((*$1)[j] != '_')
2825                                 p[i++] = (*$1)[j], p[i] = 0;
2826                 $$->realvalue = strtod(p, &q);
2827                 SET_AST_NODE_LOC($$, @1, @1);
2828                 log_assert(*q == 0);
2829                 delete $1;
2830                 free(p);
2831         } |
2832         TOK_STRING {
2833                 $$ = AstNode::mkconst_str(*$1);
2834                 SET_AST_NODE_LOC($$, @1, @1);
2835                 delete $1;
2836         } |
2837         hierarchical_id attr {
2838                 AstNode *node = new AstNode(AST_FCALL);
2839                 node->str = *$1;
2840                 delete $1;
2841                 ast_stack.push_back(node);
2842                 SET_AST_NODE_LOC(node, @1, @1);
2843                 append_attr(node, $2);
2844         } '(' arg_list optional_comma ')' {
2845                 $$ = ast_stack.back();
2846                 ast_stack.pop_back();
2847         } |
2848         TOK_TO_SIGNED attr '(' expr ')' {
2849                 $$ = new AstNode(AST_TO_SIGNED, $4);
2850                 append_attr($$, $2);
2851         } |
2852         TOK_TO_UNSIGNED attr '(' expr ')' {
2853                 $$ = new AstNode(AST_TO_UNSIGNED, $4);
2854                 append_attr($$, $2);
2855         } |
2856         '(' expr ')' {
2857                 $$ = $2;
2858         } |
2859         '(' expr ':' expr ':' expr ')' {
2860                 delete $2;
2861                 $$ = $4;
2862                 delete $6;
2863         } |
2864         '{' concat_list '}' {
2865                 $$ = $2;
2866         } |
2867         '{' expr '{' concat_list '}' '}' {
2868                 $$ = new AstNode(AST_REPLICATE, $2, $4);
2869         } |
2870         '~' attr basic_expr %prec UNARY_OPS {
2871                 $$ = new AstNode(AST_BIT_NOT, $3);
2872                 SET_AST_NODE_LOC($$, @1, @3);
2873                 append_attr($$, $2);
2874         } |
2875         basic_expr '&' attr basic_expr {
2876                 $$ = new AstNode(AST_BIT_AND, $1, $4);
2877                 SET_AST_NODE_LOC($$, @1, @4);
2878                 append_attr($$, $3);
2879         } |
2880         basic_expr OP_NAND attr basic_expr {
2881                 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
2882                 SET_AST_NODE_LOC($$, @1, @4);
2883                 append_attr($$, $3);
2884         } |
2885         basic_expr '|' attr basic_expr {
2886                 $$ = new AstNode(AST_BIT_OR, $1, $4);
2887                 SET_AST_NODE_LOC($$, @1, @4);
2888                 append_attr($$, $3);
2889         } |
2890         basic_expr OP_NOR attr basic_expr {
2891                 $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
2892                 SET_AST_NODE_LOC($$, @1, @4);
2893                 append_attr($$, $3);
2894         } |
2895         basic_expr '^' attr basic_expr {
2896                 $$ = new AstNode(AST_BIT_XOR, $1, $4);
2897                 SET_AST_NODE_LOC($$, @1, @4);
2898                 append_attr($$, $3);
2899         } |
2900         basic_expr OP_XNOR attr basic_expr {
2901                 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
2902                 SET_AST_NODE_LOC($$, @1, @4);
2903                 append_attr($$, $3);
2904         } |
2905         '&' attr basic_expr %prec UNARY_OPS {
2906                 $$ = new AstNode(AST_REDUCE_AND, $3);
2907                 SET_AST_NODE_LOC($$, @1, @3);
2908                 append_attr($$, $2);
2909         } |
2910         OP_NAND attr basic_expr %prec UNARY_OPS {
2911                 $$ = new AstNode(AST_REDUCE_AND, $3);
2912                 SET_AST_NODE_LOC($$, @1, @3);
2913                 append_attr($$, $2);
2914                 $$ = new AstNode(AST_LOGIC_NOT, $$);
2915         } |
2916         '|' attr basic_expr %prec UNARY_OPS {
2917                 $$ = new AstNode(AST_REDUCE_OR, $3);
2918                 SET_AST_NODE_LOC($$, @1, @3);
2919                 append_attr($$, $2);
2920         } |
2921         OP_NOR attr basic_expr %prec UNARY_OPS {
2922                 $$ = new AstNode(AST_REDUCE_OR, $3);
2923                 SET_AST_NODE_LOC($$, @1, @3);
2924                 append_attr($$, $2);
2925                 $$ = new AstNode(AST_LOGIC_NOT, $$);
2926                 SET_AST_NODE_LOC($$, @1, @3);
2927         } |
2928         '^' attr basic_expr %prec UNARY_OPS {
2929                 $$ = new AstNode(AST_REDUCE_XOR, $3);
2930                 SET_AST_NODE_LOC($$, @1, @3);
2931                 append_attr($$, $2);
2932         } |
2933         OP_XNOR attr basic_expr %prec UNARY_OPS {
2934                 $$ = new AstNode(AST_REDUCE_XNOR, $3);
2935                 SET_AST_NODE_LOC($$, @1, @3);
2936                 append_attr($$, $2);
2937         } |
2938         basic_expr OP_SHL attr basic_expr {
2939                 $$ = new AstNode(AST_SHIFT_LEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2940                 SET_AST_NODE_LOC($$, @1, @4);
2941                 append_attr($$, $3);
2942         } |
2943         basic_expr OP_SHR attr basic_expr {
2944                 $$ = new AstNode(AST_SHIFT_RIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2945                 SET_AST_NODE_LOC($$, @1, @4);
2946                 append_attr($$, $3);
2947         } |
2948         basic_expr OP_SSHL attr basic_expr {
2949                 $$ = new AstNode(AST_SHIFT_SLEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2950                 SET_AST_NODE_LOC($$, @1, @4);
2951                 append_attr($$, $3);
2952         } |
2953         basic_expr OP_SSHR attr basic_expr {
2954                 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
2955                 SET_AST_NODE_LOC($$, @1, @4);
2956                 append_attr($$, $3);
2957         } |
2958         basic_expr '<' attr basic_expr {
2959                 $$ = new AstNode(AST_LT, $1, $4);
2960                 SET_AST_NODE_LOC($$, @1, @4);
2961                 append_attr($$, $3);
2962         } |
2963         basic_expr OP_LE attr basic_expr {
2964                 $$ = new AstNode(AST_LE, $1, $4);
2965                 SET_AST_NODE_LOC($$, @1, @4);
2966                 append_attr($$, $3);
2967         } |
2968         basic_expr OP_EQ attr basic_expr {
2969                 $$ = new AstNode(AST_EQ, $1, $4);
2970                 SET_AST_NODE_LOC($$, @1, @4);
2971                 append_attr($$, $3);
2972         } |
2973         basic_expr OP_NE attr basic_expr {
2974                 $$ = new AstNode(AST_NE, $1, $4);
2975                 SET_AST_NODE_LOC($$, @1, @4);
2976                 append_attr($$, $3);
2977         } |
2978         basic_expr OP_EQX attr basic_expr {
2979                 $$ = new AstNode(AST_EQX, $1, $4);
2980                 SET_AST_NODE_LOC($$, @1, @4);
2981                 append_attr($$, $3);
2982         } |
2983         basic_expr OP_NEX attr basic_expr {
2984                 $$ = new AstNode(AST_NEX, $1, $4);
2985                 SET_AST_NODE_LOC($$, @1, @4);
2986                 append_attr($$, $3);
2987         } |
2988         basic_expr OP_GE attr basic_expr {
2989                 $$ = new AstNode(AST_GE, $1, $4);
2990                 SET_AST_NODE_LOC($$, @1, @4);
2991                 append_attr($$, $3);
2992         } |
2993         basic_expr '>' attr basic_expr {
2994                 $$ = new AstNode(AST_GT, $1, $4);
2995                 SET_AST_NODE_LOC($$, @1, @4);
2996                 append_attr($$, $3);
2997         } |
2998         basic_expr '+' attr basic_expr {
2999                 $$ = new AstNode(AST_ADD, $1, $4);
3000                 SET_AST_NODE_LOC($$, @1, @4);
3001                 append_attr($$, $3);
3002         } |
3003         basic_expr '-' attr basic_expr {
3004                 $$ = new AstNode(AST_SUB, $1, $4);
3005                 SET_AST_NODE_LOC($$, @1, @4);
3006                 append_attr($$, $3);
3007         } |
3008         basic_expr '*' attr basic_expr {
3009                 $$ = new AstNode(AST_MUL, $1, $4);
3010                 SET_AST_NODE_LOC($$, @1, @4);
3011                 append_attr($$, $3);
3012         } |
3013         basic_expr '/' attr basic_expr {
3014                 $$ = new AstNode(AST_DIV, $1, $4);
3015                 SET_AST_NODE_LOC($$, @1, @4);
3016                 append_attr($$, $3);
3017         } |
3018         basic_expr '%' attr basic_expr {
3019                 $$ = new AstNode(AST_MOD, $1, $4);
3020                 SET_AST_NODE_LOC($$, @1, @4);
3021                 append_attr($$, $3);
3022         } |
3023         basic_expr OP_POW attr basic_expr {
3024                 $$ = new AstNode(AST_POW, $1, $4);
3025                 SET_AST_NODE_LOC($$, @1, @4);
3026                 append_attr($$, $3);
3027         } |
3028         '+' attr basic_expr %prec UNARY_OPS {
3029                 $$ = new AstNode(AST_POS, $3);
3030                 SET_AST_NODE_LOC($$, @1, @3);
3031                 append_attr($$, $2);
3032         } |
3033         '-' attr basic_expr %prec UNARY_OPS {
3034                 $$ = new AstNode(AST_NEG, $3);
3035                 SET_AST_NODE_LOC($$, @1, @3);
3036                 append_attr($$, $2);
3037         } |
3038         basic_expr OP_LAND attr basic_expr {
3039                 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
3040                 SET_AST_NODE_LOC($$, @1, @4);
3041                 append_attr($$, $3);
3042         } |
3043         basic_expr OP_LOR attr basic_expr {
3044                 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
3045                 SET_AST_NODE_LOC($$, @1, @4);
3046                 append_attr($$, $3);
3047         } |
3048         '!' attr basic_expr %prec UNARY_OPS {
3049                 $$ = new AstNode(AST_LOGIC_NOT, $3);
3050                 SET_AST_NODE_LOC($$, @1, @3);
3051                 append_attr($$, $2);
3052         } |
3053         TOK_SIGNED OP_CAST '(' expr ')' {
3054                 if (!sv_mode)
3055                         frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
3056                 $$ = new AstNode(AST_TO_SIGNED, $4);
3057                 SET_AST_NODE_LOC($$, @1, @4);
3058         } |
3059         TOK_UNSIGNED OP_CAST '(' expr ')' {
3060                 if (!sv_mode)
3061                         frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
3062                 $$ = new AstNode(AST_TO_UNSIGNED, $4);
3063                 SET_AST_NODE_LOC($$, @1, @4);
3064         } |
3065         basic_expr OP_CAST '(' expr ')' {
3066                 if (!sv_mode)
3067                         frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
3068                 $$ = new AstNode(AST_CAST_SIZE, $1, $4);
3069                 SET_AST_NODE_LOC($$, @1, @4);
3070         };
3071
3072 concat_list:
3073         expr {
3074                 $$ = new AstNode(AST_CONCAT, $1);
3075         } |
3076         expr ',' concat_list {
3077                 $$ = $3;
3078                 $$->children.push_back($1);
3079         };
3080
3081 integral_number:
3082         TOK_CONSTVAL { $$ = $1; } |
3083         TOK_UNBASED_UNSIZED_CONSTVAL { $$ = $1; } |
3084         TOK_BASE TOK_BASED_CONSTVAL {
3085                 $1->append(*$2);
3086                 $$ = $1;
3087                 delete $2;
3088         } |
3089         TOK_CONSTVAL TOK_BASE TOK_BASED_CONSTVAL {
3090                 $1->append(*$2).append(*$3);
3091                 $$ = $1;
3092                 delete $2;
3093                 delete $3;
3094         };