1 2006-06-23 H.J. Lu <hongjiu.lu@intel.com>
3 * config/tc-i386.c (cpu_arch_tune_set): New.
4 (cpu_arch_isa): Likewise.
5 (i386_align_code): Use xchg %ax,%ax for 2 byte nop. Optimize
6 nops with short or long nop sequences based on -march=/.arch
8 (set_cpu_arch): Set cpu_arch_isa. If cpu_arch_tune_set is 0,
9 set cpu_arch_tune and cpu_arch_tune_flags.
10 (md_parse_option): For -march=, set cpu_arch_isa and set
11 cpu_arch_tune and cpu_arch_tune_flags if cpu_arch_tune_set is
12 0. Set cpu_arch_tune_set to 1 for -mtune=.
13 (i386_target_format): Don't set cpu_arch_tune.
15 2006-06-23 Nigel Stephens <nigel@mips.com>
17 * config/tc-mips.c (nopic_need_relax): Handle -fdata-sections
18 generated .sbss.* and .gnu.linkonce.sb.*.
20 2006-06-23 Thiemo Seufer <ths@mips.com>
21 David Ung <davidu@mips.com>
23 * config/tc-mips.h (TC_SEGMENT_INFO_TYPE): Declare per-segment
25 * config/tc-mips.c (label_list): Define per-segment label_list.
26 (mips_clear_insn_labels, mips_move_labels, mips16_mark_labels,
27 append_insn, s_align, s_cons, s_float_cons, s_gpword, s_gpdword,
28 mips_from_file_after_relocs, mips_define_label): Use per-segment
31 2006-06-22 Thiemo Seufer <ths@mips.com>
33 * config/tc-mips.c (ISA_SUPPORTS_MIPS16E): New macro.
34 (append_insn): Use it.
35 (md_apply_fix): Whitespace formatting.
36 (md_begin, append_insn, macro, macro2, mips16_immed, mips_align,
37 mips16_extended_frag): Remove register specifier.
38 (md_convert_frag): Likewise. Use TRUE ans FALSE instead of numeric
41 2006-06-21 Mark Shinwell <shinwell@codesourcery.com>
43 * config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New. Parse
44 a directive saving VFP registers for ARMv6 or later.
45 (s_arm_unwind_save): Add parameter arch_v6 and call
46 s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as
48 (md_pseudo_table): Add entry for new "vsave" directive.
49 * doc/c-arm.texi: Correct error in example for "save"
50 directive (fstmdf -> fstmdx). Also document "vsave" directive.
52 2006-06-18 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
53 Anatoly Sokolov <aesok@post.ru>
55 * config/tc-avr.c (mcu_types): Add support for atmega165p, atmega169p
56 and atmega644p devices. Rename atmega164/atmega324 devices to
57 atmega164p/atmega324p.
58 * doc/c-avr.texi: Document new mcu and arch options.
60 2006-06-17 Nick Clifton <nickc@redhat.com>
62 * config/tc-arm.c (enum parse_operand_result): Move outside of
63 #ifdef OBJ_ELF so that non-ELF targeted ARM ports can build.
65 2006-06-16 H.J. Lu <hongjiu.lu@intel.com>
67 * config/tc-i386.h (processor_type): New.
68 (arch_entry): Add type.
70 * config/tc-i386.c (cpu_arch_tune): New.
71 (cpu_arch_tune_flags): Likewise.
72 (cpu_arch_isa_flags): Likewise.
74 (set_cpu_arch): Also update cpu_arch_isa_flags.
75 (md_assemble): Update cpu_arch_isa_flags.
77 (OPTION_MTUNE): Likewise.
78 (md_longopts): Add -march= and -mtune=.
79 (md_parse_option): Support -march= and -mtune=.
80 (md_show_usage): Add -march=CPU/-mtune=CPU.
81 (i386_target_format): Also update cpu_arch_isa_flags,
82 cpu_arch_tune and cpu_arch_tune_flags.
84 * doc/as.texinfo: Add -march=CPU/-mtune=CPU.
86 * doc/c-i386.texi: Document -march=CPU/-mtune=CPU.
88 2006-06-15 Mark Shinwell <shinwell@codesourcery.com>
90 * config/tc-arm.c (enum parse_operand_result): New.
91 (struct group_reloc_table_entry): New.
92 (enum group_reloc_type): New.
93 (group_reloc_table): New array.
94 (find_group_reloc_table_entry): New function.
95 (parse_shifter_operand_group_reloc): New function.
96 (parse_address_main): New function, incorporating code
97 from the old parse_address function. To be used via...
98 (parse_address): wrapper for parse_address_main; and
99 (parse_address_group_reloc): new function, likewise.
100 (enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
101 OP_ADDRGLDRS, OP_ADDRGLDC.
102 (parse_operands): Support for these new operand codes.
103 New macro po_misc_or_fail_no_backtrack.
104 (encode_arm_cp_address): Preserve group relocations.
105 (insns): Modify to use the above operand codes where group
106 relocations are permitted.
107 (md_apply_fix): Handle the group relocations
108 ALU_PC_G0_NC through LDC_SB_G2.
109 (tc_gen_reloc): Likewise.
110 (arm_force_relocation): Leave group relocations for the linker.
111 (arm_fix_adjustable): Likewise.
113 2006-06-15 Julian Brown <julian@codesourcery.com>
115 * config/tc-arm.c (do_vfp_nsyn_ldr_str): Remove, fold into...
116 (do_neon_ldr_str): Always defer to VFP encoding routines, which handle
119 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
121 * config/tc-i386.c (process_suffix): Don't add rex64 for
124 2006-06-09 Thiemo Seufer <ths@mips.com>
126 * config/tc-mips.c (mips_ip): Maintain argument count.
128 2006-06-09 Alan Modra <amodra@bigpond.net.au>
130 * config/tc-iq2000.c: Include sb.h.
132 2006-06-08 Nigel Stephens <nigel@mips.com>
134 * config/tc-mips.c (mips_pseudo_table): Add "origin" and "repeat"
135 aliases for better compatibility with SGI tools.
137 2006-06-08 Alan Modra <amodra@bigpond.net.au>
139 * configure.in (BFDLIB, BFDVER_H, ALL_OBJ_DEPS): Delete.
140 * Makefile.am (GASLIBS): Expand @BFDLIB@.
142 (OBJS): Expand @ALL_OBJ_DEPS@. Depend on all fopen-*.h variants.
143 (obj-aout.o): Depend on $(DEP_@target_get_type@_aout)
144 (obj-coff.o, obj-ecoff.o, obj-elf.o): Similarly.
146 * dep-in.sed: Don't substitute bfdver.h. Do remove symcat.h.
147 * Makefile.in: Regenerate.
148 * doc/Makefile.in: Regenerate.
149 * configure: Regenerate.
151 2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
153 * po/Make-in (pdf, ps): New dummy targets.
155 2006-06-07 Julian Brown <julian@codesourcery.com>
157 * config/tc-arm.c (stdarg.h): include.
158 (arm_it): Add uncond_value field. Add isvec and issingle to operand
160 (arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and
161 REG_TYPE_NSDQ (single, double or quad vector reg).
162 (reg_expected_msgs): Update.
163 (BAD_FPU): Add macro for unsupported FPU instruction error.
164 (parse_neon_type): Support 'd' as an alias for .f64.
165 (parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ
167 (parse_vfp_reg_list): Don't update first arg on error.
168 (parse_neon_mov): Support extra syntax for VFP moves.
169 (operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO,
170 OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ.
171 (parse_operands): Support isvec, issingle operands fields, new parse
173 (do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs,
175 (do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above.
176 (NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez.
177 (NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros.
178 (NEON_SHAPE_DEF): New macro. Define table of possible instruction
180 (neon_shape): Redefine in terms of above.
181 (neon_shape_class): New enumeration, table of shape classes.
182 (neon_shape_el): New enumeration. One element of a shape.
183 (neon_shape_el_size): Register widths of above, where appropriate.
184 (neon_shape_info): New struct. Info for shape table.
185 (neon_shape_tab): New array.
186 (neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL.
187 (neon_check_shape): Rewrite as...
188 (neon_select_shape): New function to classify instruction shapes,
189 driven by new table neon_shape_tab array.
190 (neon_quad): New function. Return 1 if shape should set Q flag in
191 instructions (or equivalent), 0 otherwise.
192 (type_chk_of_el_type): Support F64.
193 (el_type_of_type_chk): Likewise.
194 (neon_check_type): Add support for VFP type checking (VFP data
195 elements fill their containing registers).
196 (do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE
197 in thumb mode for VFP instructions.
198 (do_vfp_nsyn_opcode): New function. Look up the opcode in argument,
199 and encode the current instruction as if it were that opcode.
200 (try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS
201 arguments, call function in PFN.
202 (do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul)
203 (do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str)
204 (do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul)
205 (do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push)
206 (do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions.
207 Redirect Neon-syntax VFP instructions to VFP instruction handlers.
208 (do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm)
209 (do_neon_qshl_imm, do_neon_logic, do_neon_bitfield)
210 (neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh)
211 (do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri)
212 (do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext)
213 (do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn)
214 (do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long)
215 (do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt)
216 (do_neon_swp): Use neon_select_shape not neon_check_shape. Use
218 (vfp_or_neon_is_neon): New function. Call if a mnemonic shared
219 between VFP and Neon turns out to belong to Neon. Perform
220 architecture check and fill in condition field if appropriate.
221 (do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg)
222 (do_neon_cvt): Add support for VFP variants of instructions.
223 (neon_cvt_flavour): Extend to cover VFP conversions.
224 (do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP
226 (do_neon_ldr_str): Handle single-precision VFP load/store.
227 (do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use
228 NS_NULL not NS_IGNORE.
229 (opcode_tag): Add OT_csuffixF for operands which either take a
230 conditional suffix, or have 0xF in the condition field.
231 (md_assemble): Add support for OT_csuffixF.
232 (NCE): Replace macro with...
233 (NCE_tag, NCE, NCEF): New macros.
234 (nCE): Replace macro with...
235 (nCE_tag, nCE, nCEF): New macros.
236 (insns): Add support for VFP insns or VFP versions of insns msr,
237 mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop,
238 vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia,
239 vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared
240 VFP/Neon insns together.
242 2006-06-07 Alan Modra <amodra@bigpond.net.au>
243 Ladislav Michl <ladis@linux-mips.org>
245 * app.c: Don't include headers already included by as.h.
247 * atof-generic.c: Likewise.
249 * dwarf2dbg.c: Likewise.
251 * input-file.c: Likewise.
252 * input-scrub.c: Likewise.
254 * output-file.c: Likewise.
257 * config/bfin-lex.l: Likewise.
258 * config/obj-coff.h: Likewise.
259 * config/obj-elf.h: Likewise.
260 * config/obj-som.h: Likewise.
261 * config/tc-arc.c: Likewise.
262 * config/tc-arm.c: Likewise.
263 * config/tc-avr.c: Likewise.
264 * config/tc-bfin.c: Likewise.
265 * config/tc-cris.c: Likewise.
266 * config/tc-d10v.c: Likewise.
267 * config/tc-d30v.c: Likewise.
268 * config/tc-dlx.h: Likewise.
269 * config/tc-fr30.c: Likewise.
270 * config/tc-frv.c: Likewise.
271 * config/tc-h8300.c: Likewise.
272 * config/tc-hppa.c: Likewise.
273 * config/tc-i370.c: Likewise.
274 * config/tc-i860.c: Likewise.
275 * config/tc-i960.c: Likewise.
276 * config/tc-ip2k.c: Likewise.
277 * config/tc-iq2000.c: Likewise.
278 * config/tc-m32c.c: Likewise.
279 * config/tc-m32r.c: Likewise.
280 * config/tc-maxq.c: Likewise.
281 * config/tc-mcore.c: Likewise.
282 * config/tc-mips.c: Likewise.
283 * config/tc-mmix.c: Likewise.
284 * config/tc-mn10200.c: Likewise.
285 * config/tc-mn10300.c: Likewise.
286 * config/tc-msp430.c: Likewise.
287 * config/tc-mt.c: Likewise.
288 * config/tc-ns32k.c: Likewise.
289 * config/tc-openrisc.c: Likewise.
290 * config/tc-ppc.c: Likewise.
291 * config/tc-s390.c: Likewise.
292 * config/tc-sh.c: Likewise.
293 * config/tc-sh64.c: Likewise.
294 * config/tc-sparc.c: Likewise.
295 * config/tc-tic30.c: Likewise.
296 * config/tc-tic4x.c: Likewise.
297 * config/tc-tic54x.c: Likewise.
298 * config/tc-v850.c: Likewise.
299 * config/tc-vax.c: Likewise.
300 * config/tc-xc16x.c: Likewise.
301 * config/tc-xstormy16.c: Likewise.
302 * config/tc-xtensa.c: Likewise.
303 * config/tc-z80.c: Likewise.
304 * config/tc-z8k.c: Likewise.
305 * macro.h: Don't include sb.h or ansidecl.h.
306 * sb.h: Don't include stdio.h or ansidecl.h.
307 * cond.c: Include sb.h.
308 * itbl-lex.l: Include as.h instead of other system headers.
309 * itbl-parse.y: Likewise.
310 * itbl-ops.c: Similarly.
311 * itbl-ops.h: Don't include as.h or ansidecl.h.
312 * config/bfin-defs.h: Don't include bfd.h or as.h.
313 * config/bfin-parse.y: Include as.h instead of other system headers.
315 2006-06-06 Ben Elliston <bje@au.ibm.com>
316 Anton Blanchard <anton@samba.org>
318 * config/tc-ppc.c (parse_cpu): Handle "-mpower6".
319 (md_show_usage): Document it.
320 (ppc_setup_opcodes): Test power6 opcode flag bits.
321 * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
323 2006-06-06 Thiemo Seufer <ths@mips.com>
324 Chao-ying Fu <fu@mips.com>
326 * config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
327 (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
328 (macro_build): Update comment.
329 (mips_ip): Allow DSP64 instructions for MIPS64R2.
330 (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
332 (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
333 MIPS_CPU_ASE_MDMX flags for sb1.
335 2006-06-05 Thiemo Seufer <ths@mips.com>
337 * config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
339 (mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
340 (mips_ip): Make overflowed/underflowed constant arguments in DSP
341 and MT instructions a fatal error. Use INSERT_OPERAND where
342 appropriate. Improve warnings for break and wait code overflows.
343 Use symbolic constant of OP_MASK_COPZ.
344 (mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.
346 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
348 * po/Make-in (top_builddir): Define.
350 2006-06-02 Joseph S. Myers <joseph@codesourcery.com>
352 * doc/Makefile.am (TEXI2DVI): Define.
353 * doc/Makefile.in: Regenerate.
354 * doc/c-arc.texi: Fix typo.
356 2006-06-01 Alan Modra <amodra@bigpond.net.au>
358 * config/obj-ieee.c: Delete.
359 * config/obj-ieee.h: Delete.
360 * Makefile.am (OBJ_FORMATS): Remove ieee.
361 (OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly.
362 (obj-ieee.o): Remove rule.
363 * Makefile.in: Regenerate.
364 * configure.in (atof): Remove tahoe.
365 (OBJ_MAYBE_IEEE): Don't define.
366 * configure: Regenerate.
367 * config.in: Regenerate.
368 * doc/Makefile.in: Regenerate.
369 * po/POTFILES.in: Regenerate.
371 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
373 * Makefile.am: Replace INTLLIBS and INTLDEPS with LIBINTL
374 and LIBINTL_DEP everywhere.
376 (INCLUDES, DEP_INCLUDES): Use @INCINTL@.
377 * acinclude.m4: Include new gettext macros.
378 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
379 Remove local code for po/Makefile.
380 * Makefile.in, configure, doc/Makefile.in: Regenerated.
382 2006-05-30 Nick Clifton <nickc@redhat.com>
384 * po/es.po: Updated Spanish translation.
386 2006-05-06 Denis Chertykov <denisc@overta.ru>
388 * doc/c-avr.texi: New file.
389 * doc/Makefile.am (CPU_DOCS): Add c-avr.texi
390 * doc/all.texi: Set AVR
391 * doc/as.texinfo: Include c-avr.texi
393 2006-05-28 Jie Zhang <jie.zhang@analog.com>
395 * config/bfin-parse.y (check_macfunc): Loose the condition of
396 calling check_multiply_halfregs ().
398 2006-05-25 Jie Zhang <jie.zhang@analog.com>
400 * config/bfin-parse.y (asm_1): Better check and deal with
401 vector and scalar Multiply 16-Bit Operands instructions.
403 2006-05-24 Nick Clifton <nickc@redhat.com>
405 * config/tc-hppa.c: Convert to ISO C90 format.
406 * config/tc-hppa.h: Likewise.
408 2006-05-24 Carlos O'Donell <carlos@systemhalted.org>
409 Randolph Chung <randolph@tausq.org>
411 * config/tc-hppa.c (is_tls_gdidx, is_tls_ldidx, is_tls_dtpoff,
412 is_tls_ieoff, is_tls_leoff): Define.
413 (fix_new_hppa): Handle TLS.
414 (cons_fix_new_hppa): Likewise.
416 (md_apply_fix): Handle TLS relocs.
417 * config/tc-hppa.h (hppa_fix_adjustable): Handle TLS.
419 2006-05-24 Bjoern Haase <bjoern.m.haase@web.de>
421 * config/tc-avr.c: Add new cpu targets avr6, avr2560 and avr2561.
423 2006-05-23 Thiemo Seufer <ths@mips.com>
424 David Ung <davidu@mips.com>
425 Nigel Stephens <nigel@mips.com>
428 * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
429 (ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
430 ISA_HAS_MXHC1): New macros.
431 (HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
432 ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
433 (mips_cpu_info): Change to use combined ASE/IS_ISA flag.
434 (MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
435 MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
436 (mips_after_parse_args): Change default handling of float register
437 size to account for 32bit code with 64bit FP. Better sanity checking
438 of ISA/ASE/ABI option combinations.
439 (s_mipsset): Support switching of GPR and FPR sizes via
440 .set {g,f}p={32,64,default}. Better sanity checking for .set ASE
442 (mips_elf_final_processing): We should record the use of 64bit FP
443 registers in 32bit code but we don't, because ELF header flags are
445 (mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
446 extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
447 24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
448 (mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
449 * doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
450 missing -march options. Document .set arch=CPU. Move .set smartmips
451 to ASE page. Use @code for .set FOO examples.
453 2006-05-23 Jie Zhang <jie.zhang@analog.com>
455 * config/tc-bfin.c (bfin_start_line_hook): Bump line counters
458 2006-05-23 Jie Zhang <jie.zhang@analog.com>
460 * config/bfin-defs.h (bfin_equals): Remove declaration.
461 * config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr".
462 * config/tc-bfin.c (bfin_name_is_register): Remove.
463 (bfin_equals): Remove.
464 * config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1.
465 (bfin_name_is_register): Remove declaration.
467 2006-05-19 Thiemo Seufer <ths@mips.com>
468 Nigel Stephens <nigel@mips.com>
470 * config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.
471 (mips_oddfpreg_ok): New function.
474 2006-05-19 Thiemo Seufer <ths@mips.com>
475 David Ung <davidu@mips.com>
477 * config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.
478 * config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS,
479 ISA_HAS_DROR, ISA_HAS_ROR): Reformat.
480 (regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC,
481 RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK,
482 RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES,
483 FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES,
484 N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES,
485 SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES,
486 MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names,
487 reg_names_o32, reg_names_n32n64): Define register classes.
488 (reg_lookup): New function, use register classes.
489 (md_begin): Reserve register names in the symbol table. Simplify
491 (mips_ip): Fix comment formatting. Handle symbolic COP0 registers.
493 (mips16_ip): Use reg_lookup.
494 (tc_get_register): Likewise.
495 (tc_mips_regname_to_dw2regnum): New function.
497 2006-05-19 Thiemo Seufer <ths@mips.com>
499 * config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum):
500 Un-constify string argument.
501 * config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum):
503 * config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum):
505 * config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum):
507 * config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum):
509 * config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum):
511 * config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum):
514 2006-05-19 Nathan Sidwell <nathan@codesourcery.com>
516 * gas/config/tc-m68k.c (m68k_init_arch): Move checking of
517 cfloat/m68881 to correct architecture before using it.
519 2006-05-16 Bjoern Haase <bjoern.m.haase@web.de>
521 * config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate
524 2006-05-15 Paul Brook <paul@codesourcery.com>
526 * config/tc-arm.c (arm_adjust_symtab): Use
527 bfd_is_arm_special_symbol_name.
529 2006-05-15 Bob Wilson <bob.wilson@acm.org>
531 * config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next,
532 xg_assemble_vliw_tokens, xtensa_mark_narrow_branches,
533 xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed):
534 Handle errors from calls to xtensa_opcode_is_* functions.
536 2006-05-14 Thiemo Seufer <ths@mips.com>
538 * config/tc-mips.c (macro_build): Test for currently active
540 (mips16_ip): Reject invalid opcodes.
542 2006-05-11 Carlos O'Donell <carlos@codesourcery.com>
544 * doc/as.texinfo: Rename "Index" to "AS Index",
545 and "ABORT" to "ABORT (COFF)".
547 2006-05-11 Paul Brook <paul@codesourcery.com>
549 * config/tc-arm.c (parse_half): New function.
550 (operand_parse_code): Remove OP_Iffff. Add OP_HALF.
551 (parse_operands): Ditto.
552 (do_mov16): Reject invalid relocations.
553 (do_t_mov16): Ditto. Use Thumb reloc numbers.
554 (insns): Replace Iffff with HALF.
555 (md_apply_fix): Add MOVW and MOVT relocs.
556 (tc_gen_reloc): Ditto.
557 * doc/c-arm.texi: Document relocation operators
559 2006-05-11 Paul Brook <paul@codesourcery.com>
561 * config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols.
563 2006-05-11 Thiemo Seufer <ths@mips.com>
565 * config/tc-mips.c (append_insn): Don't check the range of j or
568 2006-05-11 Pedro Alves <pedro_alves@portugalmail.pt>
570 * config/tc-arm.c (md_pcrel_from_section): Force a bias for
571 relocs against external symbols for WinCE targets.
572 (md_apply_fix): Likewise.
574 2006-05-09 David Ung <davidu@mips.com>
576 * config/tc-mips.c (append_insn): Only warn about an out-of-range
579 2006-05-09 Nick Clifton <nickc@redhat.com>
581 * config/tc-arm.c (arm_fix_adjustable): For COFF, convert fixups
582 against symbols which are not going to be placed into the symbol
585 2006-05-09 Ben Elliston <bje@au.ibm.com>
587 * expr.c (operand): Remove `if (0 && ..)' statement and
588 subsequently unused target_op label. Collapse `if (1 || ..)'
590 * app.c (do_scrub_chars): Remove unused case 0, as it is handled
591 separately above the switch.
593 2006-05-08 Nick Clifton <nickc@redhat.com>
596 * config/tc-msp430.c (line_separator_character): Define as |.
598 2006-05-08 Thiemo Seufer <ths@mips.com>
599 Nigel Stephens <nigel@mips.com>
600 David Ung <davidu@mips.com>
602 * config/tc-mips.c (mips_set_options): Add ase_smartmips flag.
603 (mips_opts): Likewise.
604 (file_ase_smartmips): New variable.
605 (ISA_HAS_ROR): SmartMIPS implements rotate instructions.
606 (macro_build): Handle SmartMIPS instructions.
608 (md_longopts): Add argument handling for smartmips.
609 (md_parse_options, mips_after_parse_args): Likewise.
610 (s_mipsset): Add .set smartmips support.
611 (md_show_usage): Document -msmartmips/-mno-smartmips.
612 * doc/as.texinfo: Document -msmartmips/-mno-smartmips and
614 * doc/c-mips.texi: Likewise.
616 2006-05-08 Alan Modra <amodra@bigpond.net.au>
618 * write.c (relax_segment): Add pass count arg. Don't error on
619 negative org/space on first two passes.
620 (relax_seg_info): New struct.
621 (relax_seg, write_object_file): Adjust.
622 * write.h (relax_segment): Update prototype.
624 2006-05-05 Julian Brown <julian@codesourcery.com>
626 * config/tc-arm.c (parse_vfp_reg_list): Improve register bounds
628 (do_neon_mov): Enable several VMOV variants for VFP. Add suitable
629 architecture version checks.
630 (insns): Allow overlapping instructions to be used in VFP mode.
632 2006-05-05 H.J. Lu <hongjiu.lu@intel.com>
635 * config/obj-elf.c (obj_elf_change_section): Allow user
636 specified SHF_ALPHA_GPREL.
638 2006-05-05 Bjoern Haase <bjoern.m.haase@web.de>
640 * gas/config/tc-avr.h (TC_VALIDATE_FIX): Define. Disable fixups
641 for PMEM related expressions.
643 2006-05-05 Nick Clifton <nickc@redhat.com>
646 * dwarf2dbg.c (INSERT_DIR_SEPARATOR): New macro. Handles the
647 insertion of a directory separator character into a string at a
648 given offset. Uses heuristics to decide when to use a backslash
649 character rather than a forward-slash character.
650 (dwarf2_directive_loc): Use the macro.
651 (out_debug_info): Likewise.
653 2006-05-05 Thiemo Seufer <ths@mips.com>
654 David Ung <davidu@mips.com>
656 * config/tc-mips.c (macro_build): Add case 'k' to handle cache
658 (macro): Add new case M_CACHE_AB.
660 2006-05-04 Kazu Hirata <kazu@codesourcery.com>
662 * config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated.
663 (opcode_lookup): Issue a warning for opcode with
664 OT_cinfix3_deprecated. Otherwise treat OT_cinfix3_deprecated
665 identical to OT_cinfix3.
666 (TxC3w, TC3w, tC3w): New.
667 (insns): Use tC3w and TC3w for comparison instructions with
670 2006-05-04 Alan Modra <amodra@bigpond.net.au>
672 * subsegs.h (struct frchain): Delete frch_seg.
673 (frchain_root): Delete.
674 (seg_info): Define as macro.
675 * subsegs.c (frchain_root): Delete.
676 (abs_seg_info, und_seg_info, absolute_frchain): Delete.
677 (subsegs_begin, subseg_change): Adjust for above.
678 (subseg_set_rest): Likewise. Add new frchain structs to seginfo
679 rather than to one big list.
680 (subseg_get): Don't special case abs, und sections.
681 (subseg_new, subseg_force_new): Don't set frchainP here.
683 (subsegs_print_statistics): Adjust frag chain control list traversal.
684 * debug.c (dmp_frags): Likewise.
685 * dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag
686 at frchain_root. Make use of known frchain ordering.
687 (last_frag_for_seg): Likewise.
688 (get_frag_fix): Likewise. Add seg param.
689 (process_entries, out_debug_aranges): Adjust get_frag_fix calls.
690 * write.c (chain_frchains_together_1): Adjust for struct frchain.
691 (SUB_SEGMENT_ALIGN): Likewise.
692 (subsegs_finish): Adjust frchain list traversal.
693 * config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise.
694 (xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise.
695 (xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise.
696 (xtensa_fix_b_j_loop_end_frags): Likewise.
697 (xtensa_fix_close_loop_end_frags): Likewise.
698 (xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise.
699 (retrieve_segment_info): Delete frch_seg initialisation.
701 2006-05-03 Alan Modra <amodra@bigpond.net.au>
703 * subsegs.c (subseg_get): Don't call obj_sec_set_private_data.
704 * config/obj-elf.h (obj_sec_set_private_data): Delete.
705 * config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol.
706 * config/tc-mn10300.c (tc_gen_reloc): Likewise.
708 2006-05-02 Joseph Myers <joseph@codesourcery.com>
710 * config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
712 (md_apply_fix3): Multiply offset by 4 here for
713 BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
715 2006-05-02 H.J. Lu <hongjiu.lu@intel.com>
716 Jan Beulich <jbeulich@novell.com>
718 * config/tc-i386.c (output_invalid_buf): Change size for
720 * config/tc-tic30.c (output_invalid_buf): Likewise.
722 * config/tc-i386.c (output_invalid): Cast none-ascii char to
724 * config/tc-tic30.c (output_invalid): Likewise.
726 2006-05-02 Daniel Jacobowitz <dan@codesourcery.com>
728 * doc/Makefile.am (AM_MAKEINFOFLAGS): New.
729 (TEXI2POD): Use AM_MAKEINFOFLAGS.
730 (asconfig.texi): Don't set top_srcdir.
731 * doc/as.texinfo: Don't use top_srcdir.
732 * aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
734 2006-05-02 H.J. Lu <hongjiu.lu@intel.com>
736 * config/tc-i386.c (output_invalid_buf): Change size to 16.
737 * config/tc-tic30.c (output_invalid_buf): Likewise.
739 * config/tc-i386.c (output_invalid): Use snprintf instead of
741 * config/tc-ia64.c (declare_register_set): Likewise.
742 (emit_one_bundle): Likewise.
743 (check_dependencies): Likewise.
744 * config/tc-tic30.c (output_invalid): Likewise.
746 2006-05-02 Paul Brook <paul@codesourcery.com>
748 * config/tc-arm.c (arm_optimize_expr): New function.
749 * config/tc-arm.h (md_optimize_expr): Define
750 (arm_optimize_expr): Add prototype.
751 (TC_FORCE_RELOCATION_SUB_SAME): Define.
753 2006-05-02 Ben Elliston <bje@au.ibm.com>
755 * config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit
758 * sb.h (sb_list_vector): Move to sb.c.
759 * sb.c (free_list): Use type of sb_list_vector directly.
760 (sb_build): Fix off-by-one error in assertion about `size'.
762 2006-05-01 Ben Elliston <bje@au.ibm.com>
764 * listing.c (listing_listing): Remove useless loop.
765 * macro.c (macro_expand): Remove is_positional local variable.
766 * read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1
767 and simplify surrounding expressions, where possible.
768 (assign_symbol): Likewise.
769 (s_weakref): Likewise.
770 * symbols.c (colon): Likewise.
772 2006-05-01 James Lemke <jwlemke@wasabisystems.com>
774 * subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
776 2006-04-30 Thiemo Seufer <ths@mips.com>
777 David Ung <davidu@mips.com>
779 * config/tc-mips.c (validate_mips_insn): Handling of udi cases.
780 (mips_immed): New table that records various handling of udi
781 instruction patterns.
782 (mips_ip): Adds udi handling.
784 2006-04-28 Alan Modra <amodra@bigpond.net.au>
786 * dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
787 of list rather than beginning.
789 2006-04-26 Julian Brown <julian@codesourcery.com>
791 * gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to...
792 (is_quarter_float): Rename from above. Simplify slightly.
793 (parse_qfloat_immediate): Parse a "quarter precision" floating-point
795 (parse_neon_mov): Parse floating-point constants.
796 (neon_qfloat_bits): Fix encoding.
797 (neon_cmode_for_move_imm): Tweak to use floating-point encoding in
798 preference to integer encoding when using the F32 type.
800 2006-04-26 Julian Brown <julian@codesourcery.com>
802 * config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
803 zero-initialising structures containing it will lead to invalid types).
804 (arm_it): Add vectype to each operand.
805 (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
807 (neon_typed_alias): New structure. Extra information for typed
809 (reg_entry): Add neon type info field.
810 (arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
811 Break out alternative syntax for coprocessor registers, etc. into...
812 (arm_reg_alt_syntax): New function. Alternate syntax handling broken
813 out from arm_reg_parse.
814 (parse_neon_type): Move. Return SUCCESS/FAIL.
815 (first_error): New function. Call to ensure first error which occurs is
817 (parse_neon_operand_type): Parse exactly one type.
818 (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
819 (parse_typed_reg_or_scalar): New function. Handle core of both
820 arm_typed_reg_parse and parse_scalar.
821 (arm_typed_reg_parse): Parse a register with an optional type.
822 (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
824 (parse_scalar): Parse a Neon scalar with optional type.
825 (parse_reg_list): Use first_error.
826 (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
827 (neon_alias_types_same): New function. Return true if two (alias) types
829 (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
831 (insert_reg_alias): Return new reg_entry not void.
832 (insert_neon_reg_alias): New function. Insert type/index information as
833 well as register for alias.
834 (create_neon_reg_alias): New function. Parse .dn/.qn directives and
835 make typed register aliases accordingly.
836 (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
838 (s_unreq): Delete type information if present.
839 (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
840 (s_arm_unwind_save_mmxwcg): Likewise.
841 (s_arm_unwind_movsp): Likewise.
842 (s_arm_unwind_setfp): Likewise.
843 (parse_shift): Likewise.
844 (parse_shifter_operand): Likewise.
845 (parse_address): Likewise.
846 (parse_tb): Likewise.
847 (tc_arm_regname_to_dw2regnum): Likewise.
848 (md_pseudo_table): Add dn, qn.
849 (parse_neon_mov): Handle typed operands.
850 (parse_operands): Likewise.
851 (neon_type_mask): Add N_SIZ.
852 (N_ALLMODS): New macro.
853 (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
854 (el_type_of_type_chk): Add some safeguards.
855 (modify_types_allowed): Fix logic bug.
856 (neon_check_type): Handle operands with types.
857 (neon_three_same): Remove redundant optional arg handling.
858 (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
859 (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
860 (do_neon_step): Adjust accordingly.
861 (neon_cmode_for_logic_imm): Use first_error.
862 (do_neon_bitfield): Call neon_check_type.
863 (neon_dyadic): Rename to...
864 (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
865 to allow modification of type of the destination.
866 (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
867 (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
868 (do_neon_compare): Make destination be an untyped bitfield.
869 (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
870 (neon_mul_mac): Return early in case of errors.
871 (neon_move_immediate): Use first_error.
872 (neon_mac_reg_scalar_long): Fix type to include scalar.
873 (do_neon_dup): Likewise.
874 (do_neon_mov): Likewise (in several places).
875 (do_neon_tbl_tbx): Fix type.
876 (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
877 (do_neon_ld_dup): Exit early in case of errors and/or use
879 (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
880 Handle .dn/.qn directives.
881 (REGDEF): Add zero for reg_entry neon field.
883 2006-04-26 Julian Brown <julian@codesourcery.com>
885 * config/tc-arm.c (limits.h): Include.
886 (fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
887 (fpu_vfp_v3_or_neon_ext): Declare constants.
888 (neon_el_type): New enumeration of types for Neon vector elements.
889 (neon_type_el): New struct. Define type and size of a vector element.
890 (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
892 (neon_type): Define struct. The type of an instruction.
893 (arm_it): Add 'vectype' for the current instruction.
894 (isscalar, immisalign, regisimm, isquad): New predicates for operands.
895 (vfp_sp_reg_pos): Rename to...
896 (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
898 (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
899 (Neon D or Q register).
900 (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
902 (GE_OPT_PREFIX_BIG): Define constant, for use in...
903 (my_get_expression): Allow above constant as argument to accept
904 64-bit constants with optional prefix.
905 (arm_reg_parse): Add extra argument to return the specific type of
906 register in when either a D or Q register (REG_TYPE_NDQ) is
907 requested. Can be NULL.
908 (parse_scalar): New function. Parse Neon scalar (vector reg and index).
909 (parse_reg_list): Update for new arm_reg_parse args.
910 (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
911 (parse_neon_el_struct_list): New function. Parse element/structure
912 register lists for VLD<n>/VST<n> instructions.
913 (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
914 (s_arm_unwind_save_mmxwr): Likewise.
915 (s_arm_unwind_save_mmxwcg): Likewise.
916 (s_arm_unwind_movsp): Likewise.
917 (s_arm_unwind_setfp): Likewise.
918 (parse_big_immediate): New function. Parse an immediate, which may be
919 64 bits wide. Put results in inst.operands[i].
920 (parse_shift): Update for new arm_reg_parse args.
921 (parse_address): Likewise. Add parsing of alignment specifiers.
922 (parse_neon_mov): Parse the operands of a VMOV instruction.
923 (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
924 OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
925 OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
926 OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
927 (parse_operands): Handle new codes above.
928 (encode_arm_vfp_sp_reg): Rename to...
929 (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
930 selected VFP version only supports D0-D15.
931 (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
932 (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
933 (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
934 (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
935 encode_arm_vfp_reg name, and allow 32 D regs.
936 (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
937 (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
939 (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
940 (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
941 constant-load and conversion insns introduced with VFPv3.
942 (neon_tab_entry): New struct.
943 (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
944 those which are the targets of pseudo-instructions.
945 (neon_opc): Enumerate opcodes, use as indices into...
946 (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
947 (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
948 (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
949 (NEON_ENC_DUP): Define meaningful helper macros to look up values in
951 (neon_shape): Enumerate shapes (permitted register widths, etc.) for
953 (neon_type_mask): New. Compact type representation for type checking.
954 (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
955 permitted type combinations.
956 (N_IGNORE_TYPE): New macro.
957 (neon_check_shape): New function. Check an instruction shape for
958 multiple alternatives. Return the specific shape for the current
960 (neon_modify_type_size): New function. Modify a vector type and size,
961 depending on the bit mask in argument 1.
962 (neon_type_promote): New function. Convert a given "key" type (of an
963 operand) into the correct type for a different operand, based on a bit
965 (type_chk_of_el_type): New function. Convert a type and size into the
966 compact representation used for type checking.
967 (el_type_of_type_ckh): New function. Reverse of above (only when a
968 single bit is set in the bit mask).
969 (modify_types_allowed): New function. Alter a mask of allowed types
970 based on a bit mask of modifications.
971 (neon_check_type): New function. Check the type of the current
972 instruction against the variable argument list. The "key" type of the
973 instruction is returned.
974 (neon_dp_fixup): New function. Fill in and modify instruction bits for
975 a Neon data-processing instruction depending on whether we're in ARM
976 mode or Thumb-2 mode.
977 (neon_logbits): New function.
978 (neon_three_same, neon_two_same, do_neon_dyadic_i_su)
979 (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
980 (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
981 (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
982 (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
983 (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
984 (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
985 (do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
986 (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
987 (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
988 (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
989 (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
990 (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
991 (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
992 (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
993 (neon_move_immediate, do_neon_mvn, neon_mixed_length)
994 (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
995 (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
996 (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
997 (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
998 (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
999 (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
1000 (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
1001 (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
1002 (do_neon_ldx_stx): New functions. Neon bit encoding and encoding
1004 (parse_neon_type): New function. Parse Neon type specifier.
1005 (opcode_lookup): Allow parsing of Neon type specifiers.
1006 (REGNUM2, REGSETH, REGSET2): New macros.
1007 (reg_names): Add new VFPv3 and Neon registers.
1008 (NUF, nUF, NCE, nCE): New macros for opcode table.
1009 (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
1010 fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
1011 fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
1012 Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
1013 vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
1014 vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
1015 vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
1016 vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
1017 vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
1018 vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
1019 vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
1020 vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
1021 vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
1022 vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
1024 (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
1025 (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
1026 (arm_option_cpu_value): Add vfp3 and neon.
1027 (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
1030 2006-04-25 Bob Wilson <bob.wilson@acm.org>
1032 * config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
1033 syntax instead of hardcoded opcodes with ".w18" suffixes.
1034 (wide_branch_opcode): New.
1035 (build_transition): Use it to check for wide branch opcodes with
1036 either ".w18" or ".w15" suffixes.
1038 2006-04-25 Bob Wilson <bob.wilson@acm.org>
1040 * config/tc-xtensa.c (xtensa_create_literal_symbol,
1041 xg_assemble_literal, xg_assemble_literal_space): Do not set the
1042 frag's is_literal flag.
1044 2006-04-25 Bob Wilson <bob.wilson@acm.org>
1046 * config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
1048 2006-04-23 Kazu Hirata <kazu@codesourcery.com>
1050 * config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
1051 config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
1052 config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
1053 config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
1054 config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
1056 2005-04-20 Paul Brook <paul@codesourcery.com>
1058 * config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
1060 (md_pseudo_table): Enable .arch, .cpu and .fpu for all targets.
1062 2006-04-19 Alan Modra <amodra@bigpond.net.au>
1064 * Makefile.am (CPU_TYPES): Add maxq and mt. Sort.
1065 (CPU_OBJ_VALID): Change sense of COFF test to default to invalid.
1066 Make some cpus unsupported on ELF. Run "make dep-am".
1067 * Makefile.in: Regenerate.
1069 2006-04-19 Alan Modra <amodra@bigpond.net.au>
1071 * configure.in (--enable-targets): Indent help message.
1072 * configure: Regenerate.
1074 2006-04-18 H.J. Lu <hongjiu.lu@intel.com>
1077 * config/tc-i386.c (i386_immediate): Check illegal immediate
1080 2006-04-18 Alan Modra <amodra@bigpond.net.au>
1082 * config/tc-i386.c: Formatting.
1083 (output_disp, output_imm): ISO C90 params.
1085 * frags.c (frag_offset_fixed_p): Constify args.
1086 * frags.h (frag_offset_fixed_p): Ditto.
1088 * config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete.
1089 (COFF_MAGIC): Delete.
1091 * config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.
1093 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
1095 * po/POTFILES.in: Regenerated.
1097 2006-04-16 Mark Mitchell <mark@codesourcery.com>
1099 * doc/as.texinfo: Mention that some .type syntaxes are not
1100 supported on all architectures.
1102 2006-04-14 Sterling Augustine <sterling@tensilica.com>
1104 * config/tc-xtensa.c (emit_single_op): Do not relax MOVI
1105 instructions when such transformations have been disabled.
1107 2006-04-10 Sterling Augustine <sterling@tensilica.com>
1109 * config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
1110 symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
1111 (xtensa_fix_close_loop_end_frags): Use the recorded values instead of
1112 decoding the loop instructions. Remove current_offset variable.
1113 (xtensa_fix_short_loop_frags): Likewise.
1114 (min_bytes_to_other_loop_end): Remove current_offset argument.
1116 2006-04-09 Arnold Metselaar <arnold.metselaar@planet.nl>
1118 * config/tc-z80.c (z80_optimize_expr): Removed.
1119 * config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
1121 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1123 * gas/config/tc-avr.c (mcu_types): Add support for attiny261,
1124 attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
1125 attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
1126 atmega644, atmega329, atmega3290, atmega649, atmega6490,
1127 atmega406, atmega640, atmega1280, atmega1281, at90can32,
1128 at90can64, at90usb646, at90usb647, at90usb1286 and
1130 Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
1132 2006-04-07 Paul Brook <paul@codesourcery.com>
1134 * config/tc-arm.c (parse_operands): Set default error message.
1136 2006-04-07 Paul Brook <paul@codesourcery.com>
1138 * config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
1140 2006-04-07 Paul Brook <paul@codesourcery.com>
1142 * config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
1144 2006-04-07 Paul Brook <paul@codesourcery.com>
1146 * config/tc-arm.c (THUMB2_LOAD_BIT): Define.
1147 (move_or_literal_pool): Handle Thumb-2 instructions.
1148 (do_t_ldst): Call move_or_literal_pool for =N addressing modes.
1150 2006-04-07 Alan Modra <amodra@bigpond.net.au>
1153 * config/tc-i386.c (match_template): Move 64-bit operand tests
1156 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
1158 * po/Make-in: Add install-html target.
1159 * Makefile.am: Add install-html and install-html-recursive targets.
1160 * Makefile.in: Regenerate.
1161 * configure.in: AC_SUBST datarootdir, docdir, htmldir.
1162 * configure: Regenerate.
1163 * doc/Makefile.am: Add install-html and install-html-am targets.
1164 * doc/Makefile.in: Regenerate.
1166 2006-04-06 Alan Modra <amodra@bigpond.net.au>
1168 * frags.c (frag_offset_fixed_p): Reinitialise offset before
1171 2006-04-05 Richard Sandiford <richard@codesourcery.com>
1172 Daniel Jacobowitz <dan@codesourcery.com>
1174 * config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
1175 (GOTT_BASE, GOTT_INDEX): New.
1176 (tc_gen_reloc): Don't alter relocations against GOTT_BASE and
1177 GOTT_INDEX when generating VxWorks PIC.
1178 * configure.tgt (sparc*-*-vxworks*): Remove this special case;
1179 use the generic *-*-vxworks* stanza instead.
1181 2006-04-04 Alan Modra <amodra@bigpond.net.au>
1184 * frags.c (frag_offset_fixed_p): New function.
1185 * frags.h (frag_offset_fixed_p): Declare.
1186 * expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
1187 (resolve_expression): Likewise.
1189 2006-04-03 Sterling Augustine <sterling@tensilica.com>
1191 * config/tc-xtensa.c (init_op_placement_info_table): Check for formats
1192 of the same length but different numbers of slots.
1194 2006-03-30 Andreas Schwab <schwab@suse.de>
1196 * configure.in: Fix help string for --enable-targets option.
1197 * configure: Regenerate.
1199 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1201 * gas/config/tc-m68k.c (find_cf_chip): Merge into ...
1202 (m68k_ip): ... here. Use for all chips. Protect against buffer
1203 overrun and avoid excessive copying.
1205 * config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
1206 m68020_control_regs, m68040_control_regs, m68060_control_regs,
1207 mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
1208 mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
1209 mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
1210 (m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
1211 mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
1212 mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
1213 mcf5282_ctrl, mcfv4e_ctrl): ... these.
1214 (mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
1215 (struct m68k_cpu): Change chip field to control_regs.
1216 (current_chip): Remove.
1217 (control_regs): New.
1218 (m68k_archs, m68k_extensions): Adjust.
1219 (m68k_cpus): Reorder to be in cpu number order. Adjust.
1220 (CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
1221 (find_cf_chip): Reimplement for new organization of cpu table.
1222 (select_control_regs): Remove.
1224 (struct save_opts): Save control regs, not chip.
1225 (s_save, s_restore): Adjust.
1226 (m68k_lookup_cpu): Give deprecated warning when necessary.
1227 (m68k_init_arch): Adjust.
1228 (md_show_usage): Adjust for new cpu table organization.
1230 2006-03-25 Bernd Schmidt <bernd.schmidt@analog.com>
1232 * config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
1233 * config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
1234 * config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
1236 (GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
1237 (any_gotrel): New rule.
1238 (got): Use it, and create Expr_Node_GOT_Reloc nodes.
1239 * config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
1241 (DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
1242 (bfin_pic_ptr): New function.
1243 (md_pseudo_table): Add it for ".picptr".
1244 (OPTION_FDPIC): New macro.
1245 (md_longopts): Add -mfdpic.
1246 (md_parse_option): Handle it.
1247 (md_begin): Set BFD flags.
1248 (md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
1249 (bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
1251 * Makefile.am (bfin-parse.o): Update dependencies.
1252 (DEPTC_bfin_elf): Likewise.
1253 * Makefile.in: Regenerate.
1255 2006-03-25 Richard Sandiford <richard@codesourcery.com>
1257 * config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
1258 mcfemac instead of mcfmac.
1260 2006-03-23 Michael Matz <matz@suse.de>
1262 * config/tc-i386.c (type_names): Correct placement of 'static'.
1263 (reloc): Map some more relocs to their 64 bit counterpart when
1265 (output_insn): Work around breakage if DEBUG386 is defined.
1266 (output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
1267 needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
1268 BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing
1269 different from i386.
1270 (output_imm): Ditto.
1271 (lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also
1273 (md_convert_frag): Jumps can now be larger than 2GB away, error
1275 (tc_gen_reloc): New relocs are passed through. BFD_RELOC_64
1276 and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
1278 2006-03-22 Richard Sandiford <richard@codesourcery.com>
1279 Daniel Jacobowitz <dan@codesourcery.com>
1280 Phil Edwards <phil@codesourcery.com>
1281 Zack Weinberg <zack@codesourcery.com>
1282 Mark Mitchell <mark@codesourcery.com>
1283 Nathan Sidwell <nathan@codesourcery.com>
1285 * config/tc-mips.c (mips_target_format): Handle vxworks targets.
1286 (md_begin): Complain about -G being used for PIC. Don't change
1287 the text, data and bss alignments on VxWorks.
1288 (reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
1289 generating VxWorks PIC.
1290 (load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
1291 (macro): Likewise, but do not treat la $25 specially for
1292 VxWorks PIC, and do not handle jal.
1293 (OPTION_MVXWORKS_PIC): New macro.
1294 (md_longopts): Add -mvxworks-pic.
1295 (md_parse_option): Don't complain about using PIC and -G together here.
1296 Handle OPTION_MVXWORKS_PIC.
1297 (md_estimate_size_before_relax): Always use the first relaxation
1298 sequence on VxWorks.
1299 * config/tc-mips.h (VXWORKS_PIC): New.
1301 2006-03-21 Paul Brook <paul@codesourcery.com>
1303 * config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
1305 2006-03-21 Sterling Augustine <sterling@tensilica.com>
1307 * config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
1308 (xtensa_setup_hw_workarounds): Set this new flag for older hardware.
1309 (get_loop_align_size): New.
1310 (xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
1311 (xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
1312 (get_text_align_power): Rewrite to handle inputs in the range 2-8.
1313 (get_noop_aligned_address): Use get_loop_align_size.
1314 (get_aligned_diff): Likewise.
1316 2006-03-21 Paul Brook <paul@codesourcery.com>
1318 * config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
1320 2006-03-20 Paul Brook <paul@codesourcery.com>
1322 * config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
1323 (do_t_branch): Encode branches inside IT blocks as unconditional.
1324 (do_t_cps): New function.
1325 (do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
1326 do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
1327 (opcode_lookup): Allow conditional suffixes on all instructions in
1329 (md_assemble): Advance condexec state before checking for errors.
1330 (insns): Use do_t_cps.
1332 2006-03-20 Paul Brook <paul@codesourcery.com>
1334 * config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
1335 outputting the insn.
1337 2006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1339 * config/tc-vax.c: Update copyright year.
1340 * config/tc-vax.h: Likewise.
1342 2006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1344 * config/tc-vax.c (md_chars_to_number): Used only locally, so
1346 * config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
1348 2006-03-17 Paul Brook <paul@codesourcery.com>
1350 * config/tc-arm.c (insns): Add ldm and stm.
1352 2006-03-17 Ben Elliston <bje@au.ibm.com>
1355 * doc/as.texinfo (Ident): Document this directive more thoroughly.
1357 2006-03-16 Paul Brook <paul@codesourcery.com>
1359 * config/tc-arm.c (insns): Add "svc".
1361 2006-03-13 Bob Wilson <bob.wilson@acm.org>
1363 * config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
1364 flag and avoid double underscore prefixes.
1366 2006-03-10 Paul Brook <paul@codesourcery.com>
1368 * config/tc-arm.c (md_begin): Handle EABIv5.
1369 (arm_eabis): Add EF_ARM_EABI_VER5.
1370 * doc/c-arm.texi: Document -meabi=5.
1372 2006-03-10 Ben Elliston <bje@au.ibm.com>
1374 * app.c (do_scrub_chars): Simplify string handling.
1376 2006-03-07 Richard Sandiford <richard@codesourcery.com>
1377 Daniel Jacobowitz <dan@codesourcery.com>
1378 Zack Weinberg <zack@codesourcery.com>
1379 Nathan Sidwell <nathan@codesourcery.com>
1380 Paul Brook <paul@codesourcery.com>
1381 Ricardo Anguiano <anguiano@codesourcery.com>
1382 Phil Edwards <phil@codesourcery.com>
1384 * config/tc-arm.c (md_apply_fix): Install a value of zero into a
1385 BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
1387 (tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
1388 relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
1389 relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
1391 2006-03-06 Bob Wilson <bob.wilson@acm.org>
1393 * config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
1394 even when using the text-section-literals option.
1396 2006-03-06 Nathan Sidwell <nathan@codesourcery.com>
1398 * config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
1400 (m68k_ip): <case 'J'> Check we have some control regs.
1401 (md_parse_option): Allow raw arch switch.
1402 (m68k_init_arch): Better detection of arch/cpu mismatch. Detect
1403 whether 68881 or cfloat was meant by -mfloat.
1404 (md_show_usage): Adjust extension display.
1405 (m68k_elf_final_processing): Adjust.
1407 2006-03-03 Bjoern Haase <bjoern.m.haase@web.de>
1409 * config/tc-avr.c (avr_mod_hash_value): New function.
1410 (md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
1411 BFD_RELOC_MS8_LDI for hlo8() and hhi8()
1412 (md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
1413 instead of int avr_ldi_expression: use avr_mod_hash_value instead
1415 (tc_gen_reloc): Handle substractions of symbols, if possible do
1416 fixups, abort otherwise.
1417 * config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
1418 tc_fix_adjustable): Define.
1420 2006-03-02 James E Wilson <wilson@specifix.com>
1422 * config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
1423 change the template, then clear md.slot[curr].end_of_insn_group.
1425 2006-02-28 Jan Beulich <jbeulich@novell.com>
1427 * macro.c (get_any_string): Don't insert quotes for <>-quoted input.
1429 2006-02-28 Jan Beulich <jbeulich@novell.com>
1432 * macro.c (getstring): Don't treat parentheses special anymore.
1433 (get_any_string): Don't consider '(' and ')' as quoting anymore.
1434 Special-case '(', ')', '[', and ']' when dealing with non-quoting
1437 2006-02-28 Mat <mat@csail.mit.edu>
1439 * dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
1441 2006-02-27 Jakub Jelinek <jakub@redhat.com>
1443 * dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
1445 (CFI_signal_frame): Define.
1446 (cfi_pseudo_table): Add .cfi_signal_frame.
1447 (dot_cfi): Handle CFI_signal_frame.
1448 (output_cie): Handle cie->signal_frame.
1449 (select_cie_for_fde): Don't share CIE if signal_frame flag is
1450 different. Copy signal_frame from FDE to newly created CIE.
1451 * doc/as.texinfo: Document .cfi_signal_frame.
1453 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
1455 * doc/Makefile.am: Add html target.
1456 * doc/Makefile.in: Regenerate.
1457 * po/Make-in: Add html target.
1459 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1461 * config/tc-i386.c (output_insn): Support Intel Merom New
1464 * config/tc-i386.h (CpuMNI): New.
1465 (CpuUnknownFlags): Add CpuMNI.
1467 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
1469 * config/tc-sparc.c (priv_reg_table): Add entry for "gl".
1470 (hpriv_reg_table): New table for hyperprivileged registers.
1471 (sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
1474 2006-02-24 DJ Delorie <dj@redhat.com>
1476 * config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
1477 (tc_gen_reloc): Don't define.
1478 * config/tc-m32c.c (rl_for, relaxable): New convenience macros.
1479 (OPTION_LINKRELAX): New.
1480 (md_longopts): Add it.
1482 (md_parse_options): Set it.
1483 (md_assemble): Emit relaxation relocs as needed.
1484 (md_convert_frag): Emit relaxation relocs as needed.
1485 (md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
1486 (m32c_apply_fix): New.
1487 (tc_gen_reloc): New.
1488 (m32c_force_relocation): Force out jump relocs when relaxing.
1489 (m32c_fix_adjustable): Return false if relaxing.
1491 2006-02-24 Paul Brook <paul@codesourcery.com>
1493 * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
1494 arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
1495 (struct asm_barrier_opt): Define.
1496 (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
1497 (parse_psr): Accept V7M psr names.
1498 (parse_barrier): New function.
1499 (enum operand_parse_code): Add OP_oBARRIER.
1500 (parse_operands): Implement OP_oBARRIER.
1501 (do_barrier): New function.
1502 (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
1503 (do_t_cpsi): Add V7M restrictions.
1504 (do_t_mrs, do_t_msr): Validate V7M variants.
1505 (md_assemble): Check for NULL variants.
1506 (v7m_psrs, barrier_opt_names): New tables.
1507 (insns): Add V7 instructions. Mark V6 instructions absent from V7M.
1508 (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
1509 (arm_cpu_option_table): Add Cortex-M3, R4 and A8.
1510 (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
1511 (struct cpu_arch_ver_table): Define.
1512 (cpu_arch_ver): New.
1513 (aeabi_set_public_attributes): Use cpu_arch_ver. Set
1514 Tag_CPU_arch_profile.
1515 * doc/c-arm.texi: Document new cpu and arch options.
1517 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1519 * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
1521 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1523 * config/tc-ia64.c: Update copyright years.
1525 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
1527 * config/tc-ia64.c (specify_resource): Add the rule 17 from
1530 2005-02-22 Paul Brook <paul@codesourcery.com>
1532 * config/tc-arm.c (do_pld): Remove incorrect write to
1534 (encode_thumb32_addr_mode): Use correct operand.
1536 2006-02-21 Paul Brook <paul@codesourcery.com>
1538 * config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
1540 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
1541 Anil Paranjape <anilp1@kpitcummins.com>
1542 Shilin Shakti <shilins@kpitcummins.com>
1544 * Makefile.am: Add xc16x related entry.
1545 * Makefile.in: Regenerate.
1546 * configure.in: Added xc16x related entry.
1547 * configure: Regenerate.
1548 * config/tc-xc16x.h: New file
1549 * config/tc-xc16x.c: New file
1550 * doc/c-xc16x.texi: New file for xc16x
1551 * doc/all.texi: Entry for xc16x
1552 * doc/Makefile.texi: Added c-xc16x.texi
1553 * NEWS: Announce the support for the new target.
1555 2006-02-16 Nick Hudson <nick.hudson@dsl.pipex.com>
1557 * configure.tgt: set emulation for mips-*-netbsd*
1559 2006-02-14 Jakub Jelinek <jakub@redhat.com>
1561 * config.in: Rebuilt.
1563 2006-02-13 Bob Wilson <bob.wilson@acm.org>
1565 * config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
1566 from 1, not 0, in error messages.
1567 (md_assemble): Simplify special-case check for ENTRY instructions.
1568 (tinsn_has_invalid_symbolic_operands): Do not include opcode and
1569 operand in error message.
1571 2006-02-13 Joseph S. Myers <joseph@codesourcery.com>
1573 * configure.tgt (arm-*-linux-gnueabi*): Change to
1576 2006-02-10 Nick Clifton <nickc@redhat.com>
1578 * config/tc-crx.c (check_range): Ensure that the sign bit of a
1579 32-bit value is propagated into the upper bits of a 64-bit long.
1581 * config/tc-arc.c (init_opcode_tables): Fix cast.
1582 (arc_extoper, md_operand): Likewise.
1584 2006-02-09 David Heine <dlheine@tensilica.com>
1586 * config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
1587 each relaxation step.
1589 2006-02-09 Eric Botcazou <ebotcazou@libertysurf.fr>
1591 * configure.in (CHECK_DECLS): Add vsnprintf.
1592 * configure: Regenerate.
1593 * messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
1594 include/declare here, but...
1595 * as.h: Move code detecting VARARGS idiom to the top.
1596 (errno.h, stdarg.h, varargs.h, va_list): ...here.
1597 (vsnprintf): Declare if not already declared.
1599 2006-02-08 H.J. Lu <hongjiu.lu@intel.com>
1601 * as.c (close_output_file): New.
1602 (main): Register close_output_file with xatexit before
1603 dump_statistics. Don't call output_file_close.
1605 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1607 * config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
1608 mcf5329_control_regs): New.
1609 (not_current_architecture, selected_arch, selected_cpu): New.
1610 (m68k_archs, m68k_extensions): New.
1611 (archs): Renamed to ...
1612 (m68k_cpus): ... here. Adjust.
1614 (md_pseudo_table): Add arch and cpu directives.
1615 (find_cf_chip, m68k_ip): Adjust table scanning.
1616 (no_68851, no_68881): Remove.
1617 (md_assemble): Lazily initialize.
1618 (select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
1619 (md_init_after_args): Move functionality to m68k_init_arch.
1620 (mri_chip): Adjust table scanning.
1621 (md_parse_option): Reimplement 'm' processing to add -march & -mcpu
1622 options with saner parsing.
1623 (m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
1624 m68k_init_arch): New.
1625 (s_m68k_cpu, s_m68k_arch): New.
1626 (md_show_usage): Adjust.
1627 (m68k_elf_final_processing): Set CF EF flags.
1628 * config/tc-m68k.h (m68k_init_after_args): Remove.
1629 (tc_init_after_args): Remove.
1630 * doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
1631 (M68k-Directives): Document .arch and .cpu directives.
1633 2006-02-05 Arnold Metselaar <arnold.metselaar@planet.nl>
1635 * config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
1636 synonyms for equ and defl.
1637 (z80_cons_fix_new): New function.
1638 (emit_byte): Disallow relative jumps to absolute locations.
1639 (emit_data): Only handle defb, prototype changed, because defb is
1640 now handled as pseudo-op rather than an instruction.
1641 (instab): Entries for defb,defw,db,dw moved from here...
1642 (md_pseudo_table): ... to here, use generic cons() for defw,dw.
1643 Add entries for def24,def32,d24,d32.
1644 (md_assemble): Improved error handling.
1645 (md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
1646 * config/tc-z80.h (TC_CONS_FIX_NEW): Define.
1647 (z80_cons_fix_new): Declare.
1648 * doc/c-z80.texi (defb, db): Mention warning on overflow.
1649 (def24,d24,def32,d32): New pseudo-ops.
1651 2006-02-02 Paul Brook <paul@codesourcery.com>
1653 * config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
1655 2005-02-02 Paul Brook <paul@codesourcery.com>
1657 * config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
1658 T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
1659 T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
1660 T2_OPCODE_RSB): Define.
1661 (thumb32_negate_data_op): New function.
1662 (md_apply_fix): Use it.
1664 2006-01-31 Bob Wilson <bob.wilson@acm.org>
1666 * config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
1668 * config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
1669 * config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
1671 (relaxation_requirements): Add pfinish_frag argument and use it to
1672 replace setting tinsn->record_fix fields.
1673 (xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
1674 and vinsn_to_insnbuf. Remove references to record_fix and
1675 slot_sub_symbols fields.
1676 (xtensa_mark_narrow_branches): Delete unused code.
1677 (is_narrow_branch_guaranteed_in_range): Handle expr that is not just
1679 (convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
1681 (tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
1682 (vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
1683 of the record_fix field. Simplify error messages for unexpected
1685 (set_expr_symbol_offset_diff): Delete.
1687 2006-01-31 Paul Brook <paul@codesourcery.com>
1689 * config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
1691 2006-01-31 Paul Brook <paul@codesourcery.com>
1692 Richard Earnshaw <rearnsha@arm.com>
1694 * config/tc-arm.c: Use arm_feature_set.
1695 (arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
1696 arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
1697 fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
1700 (md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
1701 md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
1702 arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
1703 s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
1705 (arm_legacy_option_table, arm_option_cpu_value_table): New types.
1706 (arm_opts): Move old cpu/arch options from here...
1707 (arm_legacy_opts): ... to here.
1708 (md_parse_option): Search arm_legacy_opts.
1709 (arm_cpus, arm_archs, arm_extensions, arm_fpus)
1710 (arm_float_abis, arm_eabis): Make const.
1712 2006-01-25 Bob Wilson <bob.wilson@acm.org>
1714 * config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
1716 2006-01-21 Jie Zhang <jie.zhang@analog.com>
1718 * config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
1719 in load immediate intruction.
1721 2006-01-21 Jie Zhang <jie.zhang@analog.com>
1723 * config/bfin-parse.y (value_match): Use correct conversion
1724 specifications in template string for __FILE__ and __LINE__.
1728 2006-01-18 Alexandre Oliva <aoliva@redhat.com>
1730 Introduce TLS descriptors for i386 and x86_64.
1731 * config/tc-i386.c (tc_i386_fix_adjustable): Handle
1732 BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
1733 BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
1734 (optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
1735 BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
1737 (build_modrm_byte): Set up zero modrm for TLS desc calls.
1738 (lex_got): Handle @tlsdesc and @tlscall.
1739 (md_apply_fix, tc_gen_reloc): Handle the new relocations.
1741 2006-01-11 Nick Clifton <nickc@redhat.com>
1743 Fixes for building on 64-bit hosts:
1744 * config/tc-avr.c (mod_index): New union to allow conversion
1745 between pointers and integers.
1746 (md_begin, avr_ldi_expression): Use it.
1747 * config/tc-i370.c (md_assemble): Add cast for argument to print
1749 * config/tc-tic54x.c (subsym_substitute): Likewise.
1750 * config/tc-mn10200.c (md_assemble): Use a union to convert the
1751 opindex field of fr_cgen structure into a pointer so that it can
1752 be stored in a frag.
1753 * config/tc-mn10300.c (md_assemble): Likewise.
1754 * config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
1756 * config/tc-v850.c: Replace uses of (int) casts with correct
1759 2006-01-09 H.J. Lu <hongjiu.lu@intel.com>
1762 * symbols.c (snapshot_symbol): Don't change a defined symbol.
1764 2006-01-03 Hans-Peter Nilsson <hp@bitrange.com>
1767 * config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
1768 a local-label reference.
1770 For older changes see ChangeLog-2005
1776 version-control: never