1 2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
3 * config/tc-i386.c (cpu_arch): Remove Cpu086, CpuAthlon and
5 (smallest_imm_type): Remove Cpu086.
6 (i386_target_format): Likewise.
8 * config/tc-i386.h: Remove Cpu086, CpuAthlon and CpuAmdFam10.
11 2006-07-13 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
12 Michael Meissner <michael.meissner@amd.com>
14 * config/tc-i386.h (PROCESSOR_AMDFAM10): New processor_type.
15 (CpuSSE4a, CpuABM, CpuAmdFam10): New Cpu directives.
16 * config/tc-i386.c (cpu_arch): Add support for AmdFam10
18 (i386_align_code): Ditto.
19 (md_assemble_code): Add support for insertq/extrq instructions,
20 swapping as needed for intel syntax.
21 (swap_imm_operands): New function to swap immediate operands.
22 (swap_operands): Deal with 4 operand instructions.
23 (build_modrm_byte): Add support for insertq instruction.
25 2006-07-13 H.J. Lu <hongjiu.lu@intel.com>
27 * config/tc-i386.h (Size64): Fix a typo in comment.
29 2006-07-12 Nick Clifton <nickc@redhat.com>
31 * config/tc-sh.c (md_apply_fix): Do not allow the generic code in
32 fixup_segment() to repeat a range check on a value that has
33 already been checked here.
35 2006-07-07 James E Wilson <wilson@specifix.com>
37 * config/tc-mips.c (mips_cpu_info_table): Add sb1a.
39 2006-07-06 Mohammed Adnène Trojette <adn@diwi.org>
40 Nick Clifton <nickc@redhat.com>
43 * doc/as.texi: Fix spelling typo: branchs => branches.
44 * doc/c-m68hc11.texi: Likewise.
45 * config/tc-m68hc11.c: Likewise.
46 Support old spelling of command line switch for backwards
49 2006-07-04 Thiemo Seufer <ths@mips.com>
50 David Ung <davidu@mips.com>
52 * config/tc-mips.c (s_is_linkonce): New function.
53 (mips16_mark_labels): Don't adjust mips16 symbol addresses for
54 weak, external, and linkonce symbols.
55 (pic_need_relax): Use s_is_linkonce.
57 2006-06-24 H.J. Lu <hongjiu.lu@intel.com>
59 * doc/as.texinfo (Org): Remove space.
60 (P2align): Add "@var{abs-expr},".
62 2006-06-23 H.J. Lu <hongjiu.lu@intel.com>
64 * config/tc-i386.c (cpu_arch_tune_set): New.
65 (cpu_arch_isa): Likewise.
66 (i386_align_code): Use xchg %ax,%ax for 2 byte nop. Optimize
67 nops with short or long nop sequences based on -march=/.arch
69 (set_cpu_arch): Set cpu_arch_isa. If cpu_arch_tune_set is 0,
70 set cpu_arch_tune and cpu_arch_tune_flags.
71 (md_parse_option): For -march=, set cpu_arch_isa and set
72 cpu_arch_tune and cpu_arch_tune_flags if cpu_arch_tune_set is
73 0. Set cpu_arch_tune_set to 1 for -mtune=.
74 (i386_target_format): Don't set cpu_arch_tune.
76 2006-06-23 Nigel Stephens <nigel@mips.com>
78 * config/tc-mips.c (nopic_need_relax): Handle -fdata-sections
79 generated .sbss.* and .gnu.linkonce.sb.*.
81 2006-06-23 Thiemo Seufer <ths@mips.com>
82 David Ung <davidu@mips.com>
84 * config/tc-mips.h (TC_SEGMENT_INFO_TYPE): Declare per-segment
86 * config/tc-mips.c (label_list): Define per-segment label_list.
87 (mips_clear_insn_labels, mips_move_labels, mips16_mark_labels,
88 append_insn, s_align, s_cons, s_float_cons, s_gpword, s_gpdword,
89 mips_from_file_after_relocs, mips_define_label): Use per-segment
92 2006-06-22 Thiemo Seufer <ths@mips.com>
94 * config/tc-mips.c (ISA_SUPPORTS_MIPS16E): New macro.
95 (append_insn): Use it.
96 (md_apply_fix): Whitespace formatting.
97 (md_begin, append_insn, macro, macro2, mips16_immed, mips_align,
98 mips16_extended_frag): Remove register specifier.
99 (md_convert_frag): Likewise. Use TRUE ans FALSE instead of numeric
102 2006-06-21 Mark Shinwell <shinwell@codesourcery.com>
104 * config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New. Parse
105 a directive saving VFP registers for ARMv6 or later.
106 (s_arm_unwind_save): Add parameter arch_v6 and call
107 s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as
109 (md_pseudo_table): Add entry for new "vsave" directive.
110 * doc/c-arm.texi: Correct error in example for "save"
111 directive (fstmdf -> fstmdx). Also document "vsave" directive.
113 2006-06-18 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
114 Anatoly Sokolov <aesok@post.ru>
116 * config/tc-avr.c (mcu_types): Add support for atmega165p, atmega169p
117 and atmega644p devices. Rename atmega164/atmega324 devices to
118 atmega164p/atmega324p.
119 * doc/c-avr.texi: Document new mcu and arch options.
121 2006-06-17 Nick Clifton <nickc@redhat.com>
123 * config/tc-arm.c (enum parse_operand_result): Move outside of
124 #ifdef OBJ_ELF so that non-ELF targeted ARM ports can build.
126 2006-06-16 H.J. Lu <hongjiu.lu@intel.com>
128 * config/tc-i386.h (processor_type): New.
129 (arch_entry): Add type.
131 * config/tc-i386.c (cpu_arch_tune): New.
132 (cpu_arch_tune_flags): Likewise.
133 (cpu_arch_isa_flags): Likewise.
135 (set_cpu_arch): Also update cpu_arch_isa_flags.
136 (md_assemble): Update cpu_arch_isa_flags.
138 (OPTION_MTUNE): Likewise.
139 (md_longopts): Add -march= and -mtune=.
140 (md_parse_option): Support -march= and -mtune=.
141 (md_show_usage): Add -march=CPU/-mtune=CPU.
142 (i386_target_format): Also update cpu_arch_isa_flags,
143 cpu_arch_tune and cpu_arch_tune_flags.
145 * doc/as.texinfo: Add -march=CPU/-mtune=CPU.
147 * doc/c-i386.texi: Document -march=CPU/-mtune=CPU.
149 2006-06-15 Mark Shinwell <shinwell@codesourcery.com>
151 * config/tc-arm.c (enum parse_operand_result): New.
152 (struct group_reloc_table_entry): New.
153 (enum group_reloc_type): New.
154 (group_reloc_table): New array.
155 (find_group_reloc_table_entry): New function.
156 (parse_shifter_operand_group_reloc): New function.
157 (parse_address_main): New function, incorporating code
158 from the old parse_address function. To be used via...
159 (parse_address): wrapper for parse_address_main; and
160 (parse_address_group_reloc): new function, likewise.
161 (enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
162 OP_ADDRGLDRS, OP_ADDRGLDC.
163 (parse_operands): Support for these new operand codes.
164 New macro po_misc_or_fail_no_backtrack.
165 (encode_arm_cp_address): Preserve group relocations.
166 (insns): Modify to use the above operand codes where group
167 relocations are permitted.
168 (md_apply_fix): Handle the group relocations
169 ALU_PC_G0_NC through LDC_SB_G2.
170 (tc_gen_reloc): Likewise.
171 (arm_force_relocation): Leave group relocations for the linker.
172 (arm_fix_adjustable): Likewise.
174 2006-06-15 Julian Brown <julian@codesourcery.com>
176 * config/tc-arm.c (do_vfp_nsyn_ldr_str): Remove, fold into...
177 (do_neon_ldr_str): Always defer to VFP encoding routines, which handle
180 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
182 * config/tc-i386.c (process_suffix): Don't add rex64 for
185 2006-06-09 Thiemo Seufer <ths@mips.com>
187 * config/tc-mips.c (mips_ip): Maintain argument count.
189 2006-06-09 Alan Modra <amodra@bigpond.net.au>
191 * config/tc-iq2000.c: Include sb.h.
193 2006-06-08 Nigel Stephens <nigel@mips.com>
195 * config/tc-mips.c (mips_pseudo_table): Add "origin" and "repeat"
196 aliases for better compatibility with SGI tools.
198 2006-06-08 Alan Modra <amodra@bigpond.net.au>
200 * configure.in (BFDLIB, BFDVER_H, ALL_OBJ_DEPS): Delete.
201 * Makefile.am (GASLIBS): Expand @BFDLIB@.
203 (OBJS): Expand @ALL_OBJ_DEPS@. Depend on all fopen-*.h variants.
204 (obj-aout.o): Depend on $(DEP_@target_get_type@_aout)
205 (obj-coff.o, obj-ecoff.o, obj-elf.o): Similarly.
207 * dep-in.sed: Don't substitute bfdver.h. Do remove symcat.h.
208 * Makefile.in: Regenerate.
209 * doc/Makefile.in: Regenerate.
210 * configure: Regenerate.
212 2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
214 * po/Make-in (pdf, ps): New dummy targets.
216 2006-06-07 Julian Brown <julian@codesourcery.com>
218 * config/tc-arm.c (stdarg.h): include.
219 (arm_it): Add uncond_value field. Add isvec and issingle to operand
221 (arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and
222 REG_TYPE_NSDQ (single, double or quad vector reg).
223 (reg_expected_msgs): Update.
224 (BAD_FPU): Add macro for unsupported FPU instruction error.
225 (parse_neon_type): Support 'd' as an alias for .f64.
226 (parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ
228 (parse_vfp_reg_list): Don't update first arg on error.
229 (parse_neon_mov): Support extra syntax for VFP moves.
230 (operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO,
231 OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ.
232 (parse_operands): Support isvec, issingle operands fields, new parse
234 (do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs,
236 (do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above.
237 (NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez.
238 (NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros.
239 (NEON_SHAPE_DEF): New macro. Define table of possible instruction
241 (neon_shape): Redefine in terms of above.
242 (neon_shape_class): New enumeration, table of shape classes.
243 (neon_shape_el): New enumeration. One element of a shape.
244 (neon_shape_el_size): Register widths of above, where appropriate.
245 (neon_shape_info): New struct. Info for shape table.
246 (neon_shape_tab): New array.
247 (neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL.
248 (neon_check_shape): Rewrite as...
249 (neon_select_shape): New function to classify instruction shapes,
250 driven by new table neon_shape_tab array.
251 (neon_quad): New function. Return 1 if shape should set Q flag in
252 instructions (or equivalent), 0 otherwise.
253 (type_chk_of_el_type): Support F64.
254 (el_type_of_type_chk): Likewise.
255 (neon_check_type): Add support for VFP type checking (VFP data
256 elements fill their containing registers).
257 (do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE
258 in thumb mode for VFP instructions.
259 (do_vfp_nsyn_opcode): New function. Look up the opcode in argument,
260 and encode the current instruction as if it were that opcode.
261 (try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS
262 arguments, call function in PFN.
263 (do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul)
264 (do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str)
265 (do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul)
266 (do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push)
267 (do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions.
268 Redirect Neon-syntax VFP instructions to VFP instruction handlers.
269 (do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm)
270 (do_neon_qshl_imm, do_neon_logic, do_neon_bitfield)
271 (neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh)
272 (do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri)
273 (do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext)
274 (do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn)
275 (do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long)
276 (do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt)
277 (do_neon_swp): Use neon_select_shape not neon_check_shape. Use
279 (vfp_or_neon_is_neon): New function. Call if a mnemonic shared
280 between VFP and Neon turns out to belong to Neon. Perform
281 architecture check and fill in condition field if appropriate.
282 (do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg)
283 (do_neon_cvt): Add support for VFP variants of instructions.
284 (neon_cvt_flavour): Extend to cover VFP conversions.
285 (do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP
287 (do_neon_ldr_str): Handle single-precision VFP load/store.
288 (do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use
289 NS_NULL not NS_IGNORE.
290 (opcode_tag): Add OT_csuffixF for operands which either take a
291 conditional suffix, or have 0xF in the condition field.
292 (md_assemble): Add support for OT_csuffixF.
293 (NCE): Replace macro with...
294 (NCE_tag, NCE, NCEF): New macros.
295 (nCE): Replace macro with...
296 (nCE_tag, nCE, nCEF): New macros.
297 (insns): Add support for VFP insns or VFP versions of insns msr,
298 mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop,
299 vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia,
300 vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared
301 VFP/Neon insns together.
303 2006-06-07 Alan Modra <amodra@bigpond.net.au>
304 Ladislav Michl <ladis@linux-mips.org>
306 * app.c: Don't include headers already included by as.h.
308 * atof-generic.c: Likewise.
310 * dwarf2dbg.c: Likewise.
312 * input-file.c: Likewise.
313 * input-scrub.c: Likewise.
315 * output-file.c: Likewise.
318 * config/bfin-lex.l: Likewise.
319 * config/obj-coff.h: Likewise.
320 * config/obj-elf.h: Likewise.
321 * config/obj-som.h: Likewise.
322 * config/tc-arc.c: Likewise.
323 * config/tc-arm.c: Likewise.
324 * config/tc-avr.c: Likewise.
325 * config/tc-bfin.c: Likewise.
326 * config/tc-cris.c: Likewise.
327 * config/tc-d10v.c: Likewise.
328 * config/tc-d30v.c: Likewise.
329 * config/tc-dlx.h: Likewise.
330 * config/tc-fr30.c: Likewise.
331 * config/tc-frv.c: Likewise.
332 * config/tc-h8300.c: Likewise.
333 * config/tc-hppa.c: Likewise.
334 * config/tc-i370.c: Likewise.
335 * config/tc-i860.c: Likewise.
336 * config/tc-i960.c: Likewise.
337 * config/tc-ip2k.c: Likewise.
338 * config/tc-iq2000.c: Likewise.
339 * config/tc-m32c.c: Likewise.
340 * config/tc-m32r.c: Likewise.
341 * config/tc-maxq.c: Likewise.
342 * config/tc-mcore.c: Likewise.
343 * config/tc-mips.c: Likewise.
344 * config/tc-mmix.c: Likewise.
345 * config/tc-mn10200.c: Likewise.
346 * config/tc-mn10300.c: Likewise.
347 * config/tc-msp430.c: Likewise.
348 * config/tc-mt.c: Likewise.
349 * config/tc-ns32k.c: Likewise.
350 * config/tc-openrisc.c: Likewise.
351 * config/tc-ppc.c: Likewise.
352 * config/tc-s390.c: Likewise.
353 * config/tc-sh.c: Likewise.
354 * config/tc-sh64.c: Likewise.
355 * config/tc-sparc.c: Likewise.
356 * config/tc-tic30.c: Likewise.
357 * config/tc-tic4x.c: Likewise.
358 * config/tc-tic54x.c: Likewise.
359 * config/tc-v850.c: Likewise.
360 * config/tc-vax.c: Likewise.
361 * config/tc-xc16x.c: Likewise.
362 * config/tc-xstormy16.c: Likewise.
363 * config/tc-xtensa.c: Likewise.
364 * config/tc-z80.c: Likewise.
365 * config/tc-z8k.c: Likewise.
366 * macro.h: Don't include sb.h or ansidecl.h.
367 * sb.h: Don't include stdio.h or ansidecl.h.
368 * cond.c: Include sb.h.
369 * itbl-lex.l: Include as.h instead of other system headers.
370 * itbl-parse.y: Likewise.
371 * itbl-ops.c: Similarly.
372 * itbl-ops.h: Don't include as.h or ansidecl.h.
373 * config/bfin-defs.h: Don't include bfd.h or as.h.
374 * config/bfin-parse.y: Include as.h instead of other system headers.
376 2006-06-06 Ben Elliston <bje@au.ibm.com>
377 Anton Blanchard <anton@samba.org>
379 * config/tc-ppc.c (parse_cpu): Handle "-mpower6".
380 (md_show_usage): Document it.
381 (ppc_setup_opcodes): Test power6 opcode flag bits.
382 * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
384 2006-06-06 Thiemo Seufer <ths@mips.com>
385 Chao-ying Fu <fu@mips.com>
387 * config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
388 (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
389 (macro_build): Update comment.
390 (mips_ip): Allow DSP64 instructions for MIPS64R2.
391 (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
393 (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
394 MIPS_CPU_ASE_MDMX flags for sb1.
396 2006-06-05 Thiemo Seufer <ths@mips.com>
398 * config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
400 (mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
401 (mips_ip): Make overflowed/underflowed constant arguments in DSP
402 and MT instructions a fatal error. Use INSERT_OPERAND where
403 appropriate. Improve warnings for break and wait code overflows.
404 Use symbolic constant of OP_MASK_COPZ.
405 (mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.
407 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
409 * po/Make-in (top_builddir): Define.
411 2006-06-02 Joseph S. Myers <joseph@codesourcery.com>
413 * doc/Makefile.am (TEXI2DVI): Define.
414 * doc/Makefile.in: Regenerate.
415 * doc/c-arc.texi: Fix typo.
417 2006-06-01 Alan Modra <amodra@bigpond.net.au>
419 * config/obj-ieee.c: Delete.
420 * config/obj-ieee.h: Delete.
421 * Makefile.am (OBJ_FORMATS): Remove ieee.
422 (OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly.
423 (obj-ieee.o): Remove rule.
424 * Makefile.in: Regenerate.
425 * configure.in (atof): Remove tahoe.
426 (OBJ_MAYBE_IEEE): Don't define.
427 * configure: Regenerate.
428 * config.in: Regenerate.
429 * doc/Makefile.in: Regenerate.
430 * po/POTFILES.in: Regenerate.
432 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
434 * Makefile.am: Replace INTLLIBS and INTLDEPS with LIBINTL
435 and LIBINTL_DEP everywhere.
437 (INCLUDES, DEP_INCLUDES): Use @INCINTL@.
438 * acinclude.m4: Include new gettext macros.
439 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
440 Remove local code for po/Makefile.
441 * Makefile.in, configure, doc/Makefile.in: Regenerated.
443 2006-05-30 Nick Clifton <nickc@redhat.com>
445 * po/es.po: Updated Spanish translation.
447 2006-05-06 Denis Chertykov <denisc@overta.ru>
449 * doc/c-avr.texi: New file.
450 * doc/Makefile.am (CPU_DOCS): Add c-avr.texi
451 * doc/all.texi: Set AVR
452 * doc/as.texinfo: Include c-avr.texi
454 2006-05-28 Jie Zhang <jie.zhang@analog.com>
456 * config/bfin-parse.y (check_macfunc): Loose the condition of
457 calling check_multiply_halfregs ().
459 2006-05-25 Jie Zhang <jie.zhang@analog.com>
461 * config/bfin-parse.y (asm_1): Better check and deal with
462 vector and scalar Multiply 16-Bit Operands instructions.
464 2006-05-24 Nick Clifton <nickc@redhat.com>
466 * config/tc-hppa.c: Convert to ISO C90 format.
467 * config/tc-hppa.h: Likewise.
469 2006-05-24 Carlos O'Donell <carlos@systemhalted.org>
470 Randolph Chung <randolph@tausq.org>
472 * config/tc-hppa.c (is_tls_gdidx, is_tls_ldidx, is_tls_dtpoff,
473 is_tls_ieoff, is_tls_leoff): Define.
474 (fix_new_hppa): Handle TLS.
475 (cons_fix_new_hppa): Likewise.
477 (md_apply_fix): Handle TLS relocs.
478 * config/tc-hppa.h (hppa_fix_adjustable): Handle TLS.
480 2006-05-24 Bjoern Haase <bjoern.m.haase@web.de>
482 * config/tc-avr.c: Add new cpu targets avr6, avr2560 and avr2561.
484 2006-05-23 Thiemo Seufer <ths@mips.com>
485 David Ung <davidu@mips.com>
486 Nigel Stephens <nigel@mips.com>
489 * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
490 (ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
491 ISA_HAS_MXHC1): New macros.
492 (HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
493 ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
494 (mips_cpu_info): Change to use combined ASE/IS_ISA flag.
495 (MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
496 MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
497 (mips_after_parse_args): Change default handling of float register
498 size to account for 32bit code with 64bit FP. Better sanity checking
499 of ISA/ASE/ABI option combinations.
500 (s_mipsset): Support switching of GPR and FPR sizes via
501 .set {g,f}p={32,64,default}. Better sanity checking for .set ASE
503 (mips_elf_final_processing): We should record the use of 64bit FP
504 registers in 32bit code but we don't, because ELF header flags are
506 (mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
507 extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
508 24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
509 (mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
510 * doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
511 missing -march options. Document .set arch=CPU. Move .set smartmips
512 to ASE page. Use @code for .set FOO examples.
514 2006-05-23 Jie Zhang <jie.zhang@analog.com>
516 * config/tc-bfin.c (bfin_start_line_hook): Bump line counters
519 2006-05-23 Jie Zhang <jie.zhang@analog.com>
521 * config/bfin-defs.h (bfin_equals): Remove declaration.
522 * config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr".
523 * config/tc-bfin.c (bfin_name_is_register): Remove.
524 (bfin_equals): Remove.
525 * config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1.
526 (bfin_name_is_register): Remove declaration.
528 2006-05-19 Thiemo Seufer <ths@mips.com>
529 Nigel Stephens <nigel@mips.com>
531 * config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.
532 (mips_oddfpreg_ok): New function.
535 2006-05-19 Thiemo Seufer <ths@mips.com>
536 David Ung <davidu@mips.com>
538 * config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.
539 * config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS,
540 ISA_HAS_DROR, ISA_HAS_ROR): Reformat.
541 (regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC,
542 RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK,
543 RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES,
544 FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES,
545 N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES,
546 SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES,
547 MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names,
548 reg_names_o32, reg_names_n32n64): Define register classes.
549 (reg_lookup): New function, use register classes.
550 (md_begin): Reserve register names in the symbol table. Simplify
552 (mips_ip): Fix comment formatting. Handle symbolic COP0 registers.
554 (mips16_ip): Use reg_lookup.
555 (tc_get_register): Likewise.
556 (tc_mips_regname_to_dw2regnum): New function.
558 2006-05-19 Thiemo Seufer <ths@mips.com>
560 * config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum):
561 Un-constify string argument.
562 * config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum):
564 * config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum):
566 * config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum):
568 * config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum):
570 * config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum):
572 * config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum):
575 2006-05-19 Nathan Sidwell <nathan@codesourcery.com>
577 * gas/config/tc-m68k.c (m68k_init_arch): Move checking of
578 cfloat/m68881 to correct architecture before using it.
580 2006-05-16 Bjoern Haase <bjoern.m.haase@web.de>
582 * config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate
585 2006-05-15 Paul Brook <paul@codesourcery.com>
587 * config/tc-arm.c (arm_adjust_symtab): Use
588 bfd_is_arm_special_symbol_name.
590 2006-05-15 Bob Wilson <bob.wilson@acm.org>
592 * config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next,
593 xg_assemble_vliw_tokens, xtensa_mark_narrow_branches,
594 xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed):
595 Handle errors from calls to xtensa_opcode_is_* functions.
597 2006-05-14 Thiemo Seufer <ths@mips.com>
599 * config/tc-mips.c (macro_build): Test for currently active
601 (mips16_ip): Reject invalid opcodes.
603 2006-05-11 Carlos O'Donell <carlos@codesourcery.com>
605 * doc/as.texinfo: Rename "Index" to "AS Index",
606 and "ABORT" to "ABORT (COFF)".
608 2006-05-11 Paul Brook <paul@codesourcery.com>
610 * config/tc-arm.c (parse_half): New function.
611 (operand_parse_code): Remove OP_Iffff. Add OP_HALF.
612 (parse_operands): Ditto.
613 (do_mov16): Reject invalid relocations.
614 (do_t_mov16): Ditto. Use Thumb reloc numbers.
615 (insns): Replace Iffff with HALF.
616 (md_apply_fix): Add MOVW and MOVT relocs.
617 (tc_gen_reloc): Ditto.
618 * doc/c-arm.texi: Document relocation operators
620 2006-05-11 Paul Brook <paul@codesourcery.com>
622 * config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols.
624 2006-05-11 Thiemo Seufer <ths@mips.com>
626 * config/tc-mips.c (append_insn): Don't check the range of j or
629 2006-05-11 Pedro Alves <pedro_alves@portugalmail.pt>
631 * config/tc-arm.c (md_pcrel_from_section): Force a bias for
632 relocs against external symbols for WinCE targets.
633 (md_apply_fix): Likewise.
635 2006-05-09 David Ung <davidu@mips.com>
637 * config/tc-mips.c (append_insn): Only warn about an out-of-range
640 2006-05-09 Nick Clifton <nickc@redhat.com>
642 * config/tc-arm.c (arm_fix_adjustable): For COFF, convert fixups
643 against symbols which are not going to be placed into the symbol
646 2006-05-09 Ben Elliston <bje@au.ibm.com>
648 * expr.c (operand): Remove `if (0 && ..)' statement and
649 subsequently unused target_op label. Collapse `if (1 || ..)'
651 * app.c (do_scrub_chars): Remove unused case 0, as it is handled
652 separately above the switch.
654 2006-05-08 Nick Clifton <nickc@redhat.com>
657 * config/tc-msp430.c (line_separator_character): Define as |.
659 2006-05-08 Thiemo Seufer <ths@mips.com>
660 Nigel Stephens <nigel@mips.com>
661 David Ung <davidu@mips.com>
663 * config/tc-mips.c (mips_set_options): Add ase_smartmips flag.
664 (mips_opts): Likewise.
665 (file_ase_smartmips): New variable.
666 (ISA_HAS_ROR): SmartMIPS implements rotate instructions.
667 (macro_build): Handle SmartMIPS instructions.
669 (md_longopts): Add argument handling for smartmips.
670 (md_parse_options, mips_after_parse_args): Likewise.
671 (s_mipsset): Add .set smartmips support.
672 (md_show_usage): Document -msmartmips/-mno-smartmips.
673 * doc/as.texinfo: Document -msmartmips/-mno-smartmips and
675 * doc/c-mips.texi: Likewise.
677 2006-05-08 Alan Modra <amodra@bigpond.net.au>
679 * write.c (relax_segment): Add pass count arg. Don't error on
680 negative org/space on first two passes.
681 (relax_seg_info): New struct.
682 (relax_seg, write_object_file): Adjust.
683 * write.h (relax_segment): Update prototype.
685 2006-05-05 Julian Brown <julian@codesourcery.com>
687 * config/tc-arm.c (parse_vfp_reg_list): Improve register bounds
689 (do_neon_mov): Enable several VMOV variants for VFP. Add suitable
690 architecture version checks.
691 (insns): Allow overlapping instructions to be used in VFP mode.
693 2006-05-05 H.J. Lu <hongjiu.lu@intel.com>
696 * config/obj-elf.c (obj_elf_change_section): Allow user
697 specified SHF_ALPHA_GPREL.
699 2006-05-05 Bjoern Haase <bjoern.m.haase@web.de>
701 * gas/config/tc-avr.h (TC_VALIDATE_FIX): Define. Disable fixups
702 for PMEM related expressions.
704 2006-05-05 Nick Clifton <nickc@redhat.com>
707 * dwarf2dbg.c (INSERT_DIR_SEPARATOR): New macro. Handles the
708 insertion of a directory separator character into a string at a
709 given offset. Uses heuristics to decide when to use a backslash
710 character rather than a forward-slash character.
711 (dwarf2_directive_loc): Use the macro.
712 (out_debug_info): Likewise.
714 2006-05-05 Thiemo Seufer <ths@mips.com>
715 David Ung <davidu@mips.com>
717 * config/tc-mips.c (macro_build): Add case 'k' to handle cache
719 (macro): Add new case M_CACHE_AB.
721 2006-05-04 Kazu Hirata <kazu@codesourcery.com>
723 * config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated.
724 (opcode_lookup): Issue a warning for opcode with
725 OT_cinfix3_deprecated. Otherwise treat OT_cinfix3_deprecated
726 identical to OT_cinfix3.
727 (TxC3w, TC3w, tC3w): New.
728 (insns): Use tC3w and TC3w for comparison instructions with
731 2006-05-04 Alan Modra <amodra@bigpond.net.au>
733 * subsegs.h (struct frchain): Delete frch_seg.
734 (frchain_root): Delete.
735 (seg_info): Define as macro.
736 * subsegs.c (frchain_root): Delete.
737 (abs_seg_info, und_seg_info, absolute_frchain): Delete.
738 (subsegs_begin, subseg_change): Adjust for above.
739 (subseg_set_rest): Likewise. Add new frchain structs to seginfo
740 rather than to one big list.
741 (subseg_get): Don't special case abs, und sections.
742 (subseg_new, subseg_force_new): Don't set frchainP here.
744 (subsegs_print_statistics): Adjust frag chain control list traversal.
745 * debug.c (dmp_frags): Likewise.
746 * dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag
747 at frchain_root. Make use of known frchain ordering.
748 (last_frag_for_seg): Likewise.
749 (get_frag_fix): Likewise. Add seg param.
750 (process_entries, out_debug_aranges): Adjust get_frag_fix calls.
751 * write.c (chain_frchains_together_1): Adjust for struct frchain.
752 (SUB_SEGMENT_ALIGN): Likewise.
753 (subsegs_finish): Adjust frchain list traversal.
754 * config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise.
755 (xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise.
756 (xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise.
757 (xtensa_fix_b_j_loop_end_frags): Likewise.
758 (xtensa_fix_close_loop_end_frags): Likewise.
759 (xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise.
760 (retrieve_segment_info): Delete frch_seg initialisation.
762 2006-05-03 Alan Modra <amodra@bigpond.net.au>
764 * subsegs.c (subseg_get): Don't call obj_sec_set_private_data.
765 * config/obj-elf.h (obj_sec_set_private_data): Delete.
766 * config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol.
767 * config/tc-mn10300.c (tc_gen_reloc): Likewise.
769 2006-05-02 Joseph Myers <joseph@codesourcery.com>
771 * config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
773 (md_apply_fix3): Multiply offset by 4 here for
774 BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
776 2006-05-02 H.J. Lu <hongjiu.lu@intel.com>
777 Jan Beulich <jbeulich@novell.com>
779 * config/tc-i386.c (output_invalid_buf): Change size for
781 * config/tc-tic30.c (output_invalid_buf): Likewise.
783 * config/tc-i386.c (output_invalid): Cast none-ascii char to
785 * config/tc-tic30.c (output_invalid): Likewise.
787 2006-05-02 Daniel Jacobowitz <dan@codesourcery.com>
789 * doc/Makefile.am (AM_MAKEINFOFLAGS): New.
790 (TEXI2POD): Use AM_MAKEINFOFLAGS.
791 (asconfig.texi): Don't set top_srcdir.
792 * doc/as.texinfo: Don't use top_srcdir.
793 * aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
795 2006-05-02 H.J. Lu <hongjiu.lu@intel.com>
797 * config/tc-i386.c (output_invalid_buf): Change size to 16.
798 * config/tc-tic30.c (output_invalid_buf): Likewise.
800 * config/tc-i386.c (output_invalid): Use snprintf instead of
802 * config/tc-ia64.c (declare_register_set): Likewise.
803 (emit_one_bundle): Likewise.
804 (check_dependencies): Likewise.
805 * config/tc-tic30.c (output_invalid): Likewise.
807 2006-05-02 Paul Brook <paul@codesourcery.com>
809 * config/tc-arm.c (arm_optimize_expr): New function.
810 * config/tc-arm.h (md_optimize_expr): Define
811 (arm_optimize_expr): Add prototype.
812 (TC_FORCE_RELOCATION_SUB_SAME): Define.
814 2006-05-02 Ben Elliston <bje@au.ibm.com>
816 * config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit
819 * sb.h (sb_list_vector): Move to sb.c.
820 * sb.c (free_list): Use type of sb_list_vector directly.
821 (sb_build): Fix off-by-one error in assertion about `size'.
823 2006-05-01 Ben Elliston <bje@au.ibm.com>
825 * listing.c (listing_listing): Remove useless loop.
826 * macro.c (macro_expand): Remove is_positional local variable.
827 * read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1
828 and simplify surrounding expressions, where possible.
829 (assign_symbol): Likewise.
830 (s_weakref): Likewise.
831 * symbols.c (colon): Likewise.
833 2006-05-01 James Lemke <jwlemke@wasabisystems.com>
835 * subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
837 2006-04-30 Thiemo Seufer <ths@mips.com>
838 David Ung <davidu@mips.com>
840 * config/tc-mips.c (validate_mips_insn): Handling of udi cases.
841 (mips_immed): New table that records various handling of udi
842 instruction patterns.
843 (mips_ip): Adds udi handling.
845 2006-04-28 Alan Modra <amodra@bigpond.net.au>
847 * dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
848 of list rather than beginning.
850 2006-04-26 Julian Brown <julian@codesourcery.com>
852 * gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to...
853 (is_quarter_float): Rename from above. Simplify slightly.
854 (parse_qfloat_immediate): Parse a "quarter precision" floating-point
856 (parse_neon_mov): Parse floating-point constants.
857 (neon_qfloat_bits): Fix encoding.
858 (neon_cmode_for_move_imm): Tweak to use floating-point encoding in
859 preference to integer encoding when using the F32 type.
861 2006-04-26 Julian Brown <julian@codesourcery.com>
863 * config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
864 zero-initialising structures containing it will lead to invalid types).
865 (arm_it): Add vectype to each operand.
866 (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
868 (neon_typed_alias): New structure. Extra information for typed
870 (reg_entry): Add neon type info field.
871 (arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
872 Break out alternative syntax for coprocessor registers, etc. into...
873 (arm_reg_alt_syntax): New function. Alternate syntax handling broken
874 out from arm_reg_parse.
875 (parse_neon_type): Move. Return SUCCESS/FAIL.
876 (first_error): New function. Call to ensure first error which occurs is
878 (parse_neon_operand_type): Parse exactly one type.
879 (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
880 (parse_typed_reg_or_scalar): New function. Handle core of both
881 arm_typed_reg_parse and parse_scalar.
882 (arm_typed_reg_parse): Parse a register with an optional type.
883 (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
885 (parse_scalar): Parse a Neon scalar with optional type.
886 (parse_reg_list): Use first_error.
887 (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
888 (neon_alias_types_same): New function. Return true if two (alias) types
890 (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
892 (insert_reg_alias): Return new reg_entry not void.
893 (insert_neon_reg_alias): New function. Insert type/index information as
894 well as register for alias.
895 (create_neon_reg_alias): New function. Parse .dn/.qn directives and
896 make typed register aliases accordingly.
897 (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
899 (s_unreq): Delete type information if present.
900 (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
901 (s_arm_unwind_save_mmxwcg): Likewise.
902 (s_arm_unwind_movsp): Likewise.
903 (s_arm_unwind_setfp): Likewise.
904 (parse_shift): Likewise.
905 (parse_shifter_operand): Likewise.
906 (parse_address): Likewise.
907 (parse_tb): Likewise.
908 (tc_arm_regname_to_dw2regnum): Likewise.
909 (md_pseudo_table): Add dn, qn.
910 (parse_neon_mov): Handle typed operands.
911 (parse_operands): Likewise.
912 (neon_type_mask): Add N_SIZ.
913 (N_ALLMODS): New macro.
914 (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
915 (el_type_of_type_chk): Add some safeguards.
916 (modify_types_allowed): Fix logic bug.
917 (neon_check_type): Handle operands with types.
918 (neon_three_same): Remove redundant optional arg handling.
919 (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
920 (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
921 (do_neon_step): Adjust accordingly.
922 (neon_cmode_for_logic_imm): Use first_error.
923 (do_neon_bitfield): Call neon_check_type.
924 (neon_dyadic): Rename to...
925 (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
926 to allow modification of type of the destination.
927 (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
928 (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
929 (do_neon_compare): Make destination be an untyped bitfield.
930 (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
931 (neon_mul_mac): Return early in case of errors.
932 (neon_move_immediate): Use first_error.
933 (neon_mac_reg_scalar_long): Fix type to include scalar.
934 (do_neon_dup): Likewise.
935 (do_neon_mov): Likewise (in several places).
936 (do_neon_tbl_tbx): Fix type.
937 (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
938 (do_neon_ld_dup): Exit early in case of errors and/or use
940 (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
941 Handle .dn/.qn directives.
942 (REGDEF): Add zero for reg_entry neon field.
944 2006-04-26 Julian Brown <julian@codesourcery.com>
946 * config/tc-arm.c (limits.h): Include.
947 (fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
948 (fpu_vfp_v3_or_neon_ext): Declare constants.
949 (neon_el_type): New enumeration of types for Neon vector elements.
950 (neon_type_el): New struct. Define type and size of a vector element.
951 (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
953 (neon_type): Define struct. The type of an instruction.
954 (arm_it): Add 'vectype' for the current instruction.
955 (isscalar, immisalign, regisimm, isquad): New predicates for operands.
956 (vfp_sp_reg_pos): Rename to...
957 (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
959 (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
960 (Neon D or Q register).
961 (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
963 (GE_OPT_PREFIX_BIG): Define constant, for use in...
964 (my_get_expression): Allow above constant as argument to accept
965 64-bit constants with optional prefix.
966 (arm_reg_parse): Add extra argument to return the specific type of
967 register in when either a D or Q register (REG_TYPE_NDQ) is
968 requested. Can be NULL.
969 (parse_scalar): New function. Parse Neon scalar (vector reg and index).
970 (parse_reg_list): Update for new arm_reg_parse args.
971 (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
972 (parse_neon_el_struct_list): New function. Parse element/structure
973 register lists for VLD<n>/VST<n> instructions.
974 (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
975 (s_arm_unwind_save_mmxwr): Likewise.
976 (s_arm_unwind_save_mmxwcg): Likewise.
977 (s_arm_unwind_movsp): Likewise.
978 (s_arm_unwind_setfp): Likewise.
979 (parse_big_immediate): New function. Parse an immediate, which may be
980 64 bits wide. Put results in inst.operands[i].
981 (parse_shift): Update for new arm_reg_parse args.
982 (parse_address): Likewise. Add parsing of alignment specifiers.
983 (parse_neon_mov): Parse the operands of a VMOV instruction.
984 (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
985 OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
986 OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
987 OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
988 (parse_operands): Handle new codes above.
989 (encode_arm_vfp_sp_reg): Rename to...
990 (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
991 selected VFP version only supports D0-D15.
992 (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
993 (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
994 (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
995 (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
996 encode_arm_vfp_reg name, and allow 32 D regs.
997 (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
998 (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
1000 (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
1001 (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
1002 constant-load and conversion insns introduced with VFPv3.
1003 (neon_tab_entry): New struct.
1004 (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
1005 those which are the targets of pseudo-instructions.
1006 (neon_opc): Enumerate opcodes, use as indices into...
1007 (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
1008 (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
1009 (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
1010 (NEON_ENC_DUP): Define meaningful helper macros to look up values in
1012 (neon_shape): Enumerate shapes (permitted register widths, etc.) for
1014 (neon_type_mask): New. Compact type representation for type checking.
1015 (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
1016 permitted type combinations.
1017 (N_IGNORE_TYPE): New macro.
1018 (neon_check_shape): New function. Check an instruction shape for
1019 multiple alternatives. Return the specific shape for the current
1021 (neon_modify_type_size): New function. Modify a vector type and size,
1022 depending on the bit mask in argument 1.
1023 (neon_type_promote): New function. Convert a given "key" type (of an
1024 operand) into the correct type for a different operand, based on a bit
1026 (type_chk_of_el_type): New function. Convert a type and size into the
1027 compact representation used for type checking.
1028 (el_type_of_type_ckh): New function. Reverse of above (only when a
1029 single bit is set in the bit mask).
1030 (modify_types_allowed): New function. Alter a mask of allowed types
1031 based on a bit mask of modifications.
1032 (neon_check_type): New function. Check the type of the current
1033 instruction against the variable argument list. The "key" type of the
1034 instruction is returned.
1035 (neon_dp_fixup): New function. Fill in and modify instruction bits for
1036 a Neon data-processing instruction depending on whether we're in ARM
1037 mode or Thumb-2 mode.
1038 (neon_logbits): New function.
1039 (neon_three_same, neon_two_same, do_neon_dyadic_i_su)
1040 (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
1041 (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
1042 (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
1043 (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
1044 (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
1045 (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
1046 (do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
1047 (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
1048 (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
1049 (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
1050 (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
1051 (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
1052 (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
1053 (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
1054 (neon_move_immediate, do_neon_mvn, neon_mixed_length)
1055 (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
1056 (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
1057 (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
1058 (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
1059 (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
1060 (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
1061 (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
1062 (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
1063 (do_neon_ldx_stx): New functions. Neon bit encoding and encoding
1065 (parse_neon_type): New function. Parse Neon type specifier.
1066 (opcode_lookup): Allow parsing of Neon type specifiers.
1067 (REGNUM2, REGSETH, REGSET2): New macros.
1068 (reg_names): Add new VFPv3 and Neon registers.
1069 (NUF, nUF, NCE, nCE): New macros for opcode table.
1070 (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
1071 fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
1072 fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
1073 Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
1074 vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
1075 vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
1076 vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
1077 vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
1078 vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
1079 vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
1080 vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
1081 vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
1082 vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
1083 vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
1085 (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
1086 (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
1087 (arm_option_cpu_value): Add vfp3 and neon.
1088 (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
1091 2006-04-25 Bob Wilson <bob.wilson@acm.org>
1093 * config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
1094 syntax instead of hardcoded opcodes with ".w18" suffixes.
1095 (wide_branch_opcode): New.
1096 (build_transition): Use it to check for wide branch opcodes with
1097 either ".w18" or ".w15" suffixes.
1099 2006-04-25 Bob Wilson <bob.wilson@acm.org>
1101 * config/tc-xtensa.c (xtensa_create_literal_symbol,
1102 xg_assemble_literal, xg_assemble_literal_space): Do not set the
1103 frag's is_literal flag.
1105 2006-04-25 Bob Wilson <bob.wilson@acm.org>
1107 * config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
1109 2006-04-23 Kazu Hirata <kazu@codesourcery.com>
1111 * config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
1112 config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
1113 config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
1114 config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
1115 config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
1117 2005-04-20 Paul Brook <paul@codesourcery.com>
1119 * config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
1121 (md_pseudo_table): Enable .arch, .cpu and .fpu for all targets.
1123 2006-04-19 Alan Modra <amodra@bigpond.net.au>
1125 * Makefile.am (CPU_TYPES): Add maxq and mt. Sort.
1126 (CPU_OBJ_VALID): Change sense of COFF test to default to invalid.
1127 Make some cpus unsupported on ELF. Run "make dep-am".
1128 * Makefile.in: Regenerate.
1130 2006-04-19 Alan Modra <amodra@bigpond.net.au>
1132 * configure.in (--enable-targets): Indent help message.
1133 * configure: Regenerate.
1135 2006-04-18 H.J. Lu <hongjiu.lu@intel.com>
1138 * config/tc-i386.c (i386_immediate): Check illegal immediate
1141 2006-04-18 Alan Modra <amodra@bigpond.net.au>
1143 * config/tc-i386.c: Formatting.
1144 (output_disp, output_imm): ISO C90 params.
1146 * frags.c (frag_offset_fixed_p): Constify args.
1147 * frags.h (frag_offset_fixed_p): Ditto.
1149 * config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete.
1150 (COFF_MAGIC): Delete.
1152 * config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.
1154 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
1156 * po/POTFILES.in: Regenerated.
1158 2006-04-16 Mark Mitchell <mark@codesourcery.com>
1160 * doc/as.texinfo: Mention that some .type syntaxes are not
1161 supported on all architectures.
1163 2006-04-14 Sterling Augustine <sterling@tensilica.com>
1165 * config/tc-xtensa.c (emit_single_op): Do not relax MOVI
1166 instructions when such transformations have been disabled.
1168 2006-04-10 Sterling Augustine <sterling@tensilica.com>
1170 * config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
1171 symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
1172 (xtensa_fix_close_loop_end_frags): Use the recorded values instead of
1173 decoding the loop instructions. Remove current_offset variable.
1174 (xtensa_fix_short_loop_frags): Likewise.
1175 (min_bytes_to_other_loop_end): Remove current_offset argument.
1177 2006-04-09 Arnold Metselaar <arnold.metselaar@planet.nl>
1179 * config/tc-z80.c (z80_optimize_expr): Removed.
1180 * config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
1182 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1184 * gas/config/tc-avr.c (mcu_types): Add support for attiny261,
1185 attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
1186 attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
1187 atmega644, atmega329, atmega3290, atmega649, atmega6490,
1188 atmega406, atmega640, atmega1280, atmega1281, at90can32,
1189 at90can64, at90usb646, at90usb647, at90usb1286 and
1191 Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
1193 2006-04-07 Paul Brook <paul@codesourcery.com>
1195 * config/tc-arm.c (parse_operands): Set default error message.
1197 2006-04-07 Paul Brook <paul@codesourcery.com>
1199 * config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
1201 2006-04-07 Paul Brook <paul@codesourcery.com>
1203 * config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
1205 2006-04-07 Paul Brook <paul@codesourcery.com>
1207 * config/tc-arm.c (THUMB2_LOAD_BIT): Define.
1208 (move_or_literal_pool): Handle Thumb-2 instructions.
1209 (do_t_ldst): Call move_or_literal_pool for =N addressing modes.
1211 2006-04-07 Alan Modra <amodra@bigpond.net.au>
1214 * config/tc-i386.c (match_template): Move 64-bit operand tests
1217 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
1219 * po/Make-in: Add install-html target.
1220 * Makefile.am: Add install-html and install-html-recursive targets.
1221 * Makefile.in: Regenerate.
1222 * configure.in: AC_SUBST datarootdir, docdir, htmldir.
1223 * configure: Regenerate.
1224 * doc/Makefile.am: Add install-html and install-html-am targets.
1225 * doc/Makefile.in: Regenerate.
1227 2006-04-06 Alan Modra <amodra@bigpond.net.au>
1229 * frags.c (frag_offset_fixed_p): Reinitialise offset before
1232 2006-04-05 Richard Sandiford <richard@codesourcery.com>
1233 Daniel Jacobowitz <dan@codesourcery.com>
1235 * config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
1236 (GOTT_BASE, GOTT_INDEX): New.
1237 (tc_gen_reloc): Don't alter relocations against GOTT_BASE and
1238 GOTT_INDEX when generating VxWorks PIC.
1239 * configure.tgt (sparc*-*-vxworks*): Remove this special case;
1240 use the generic *-*-vxworks* stanza instead.
1242 2006-04-04 Alan Modra <amodra@bigpond.net.au>
1245 * frags.c (frag_offset_fixed_p): New function.
1246 * frags.h (frag_offset_fixed_p): Declare.
1247 * expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
1248 (resolve_expression): Likewise.
1250 2006-04-03 Sterling Augustine <sterling@tensilica.com>
1252 * config/tc-xtensa.c (init_op_placement_info_table): Check for formats
1253 of the same length but different numbers of slots.
1255 2006-03-30 Andreas Schwab <schwab@suse.de>
1257 * configure.in: Fix help string for --enable-targets option.
1258 * configure: Regenerate.
1260 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1262 * gas/config/tc-m68k.c (find_cf_chip): Merge into ...
1263 (m68k_ip): ... here. Use for all chips. Protect against buffer
1264 overrun and avoid excessive copying.
1266 * config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
1267 m68020_control_regs, m68040_control_regs, m68060_control_regs,
1268 mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
1269 mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
1270 mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
1271 (m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
1272 mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
1273 mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
1274 mcf5282_ctrl, mcfv4e_ctrl): ... these.
1275 (mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
1276 (struct m68k_cpu): Change chip field to control_regs.
1277 (current_chip): Remove.
1278 (control_regs): New.
1279 (m68k_archs, m68k_extensions): Adjust.
1280 (m68k_cpus): Reorder to be in cpu number order. Adjust.
1281 (CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
1282 (find_cf_chip): Reimplement for new organization of cpu table.
1283 (select_control_regs): Remove.
1285 (struct save_opts): Save control regs, not chip.
1286 (s_save, s_restore): Adjust.
1287 (m68k_lookup_cpu): Give deprecated warning when necessary.
1288 (m68k_init_arch): Adjust.
1289 (md_show_usage): Adjust for new cpu table organization.
1291 2006-03-25 Bernd Schmidt <bernd.schmidt@analog.com>
1293 * config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
1294 * config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
1295 * config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
1297 (GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
1298 (any_gotrel): New rule.
1299 (got): Use it, and create Expr_Node_GOT_Reloc nodes.
1300 * config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
1302 (DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
1303 (bfin_pic_ptr): New function.
1304 (md_pseudo_table): Add it for ".picptr".
1305 (OPTION_FDPIC): New macro.
1306 (md_longopts): Add -mfdpic.
1307 (md_parse_option): Handle it.
1308 (md_begin): Set BFD flags.
1309 (md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
1310 (bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
1312 * Makefile.am (bfin-parse.o): Update dependencies.
1313 (DEPTC_bfin_elf): Likewise.
1314 * Makefile.in: Regenerate.
1316 2006-03-25 Richard Sandiford <richard@codesourcery.com>
1318 * config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
1319 mcfemac instead of mcfmac.
1321 2006-03-23 Michael Matz <matz@suse.de>
1323 * config/tc-i386.c (type_names): Correct placement of 'static'.
1324 (reloc): Map some more relocs to their 64 bit counterpart when
1326 (output_insn): Work around breakage if DEBUG386 is defined.
1327 (output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
1328 needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
1329 BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing
1330 different from i386.
1331 (output_imm): Ditto.
1332 (lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also
1334 (md_convert_frag): Jumps can now be larger than 2GB away, error
1336 (tc_gen_reloc): New relocs are passed through. BFD_RELOC_64
1337 and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
1339 2006-03-22 Richard Sandiford <richard@codesourcery.com>
1340 Daniel Jacobowitz <dan@codesourcery.com>
1341 Phil Edwards <phil@codesourcery.com>
1342 Zack Weinberg <zack@codesourcery.com>
1343 Mark Mitchell <mark@codesourcery.com>
1344 Nathan Sidwell <nathan@codesourcery.com>
1346 * config/tc-mips.c (mips_target_format): Handle vxworks targets.
1347 (md_begin): Complain about -G being used for PIC. Don't change
1348 the text, data and bss alignments on VxWorks.
1349 (reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
1350 generating VxWorks PIC.
1351 (load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
1352 (macro): Likewise, but do not treat la $25 specially for
1353 VxWorks PIC, and do not handle jal.
1354 (OPTION_MVXWORKS_PIC): New macro.
1355 (md_longopts): Add -mvxworks-pic.
1356 (md_parse_option): Don't complain about using PIC and -G together here.
1357 Handle OPTION_MVXWORKS_PIC.
1358 (md_estimate_size_before_relax): Always use the first relaxation
1359 sequence on VxWorks.
1360 * config/tc-mips.h (VXWORKS_PIC): New.
1362 2006-03-21 Paul Brook <paul@codesourcery.com>
1364 * config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
1366 2006-03-21 Sterling Augustine <sterling@tensilica.com>
1368 * config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
1369 (xtensa_setup_hw_workarounds): Set this new flag for older hardware.
1370 (get_loop_align_size): New.
1371 (xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
1372 (xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
1373 (get_text_align_power): Rewrite to handle inputs in the range 2-8.
1374 (get_noop_aligned_address): Use get_loop_align_size.
1375 (get_aligned_diff): Likewise.
1377 2006-03-21 Paul Brook <paul@codesourcery.com>
1379 * config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
1381 2006-03-20 Paul Brook <paul@codesourcery.com>
1383 * config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
1384 (do_t_branch): Encode branches inside IT blocks as unconditional.
1385 (do_t_cps): New function.
1386 (do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
1387 do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
1388 (opcode_lookup): Allow conditional suffixes on all instructions in
1390 (md_assemble): Advance condexec state before checking for errors.
1391 (insns): Use do_t_cps.
1393 2006-03-20 Paul Brook <paul@codesourcery.com>
1395 * config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
1396 outputting the insn.
1398 2006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1400 * config/tc-vax.c: Update copyright year.
1401 * config/tc-vax.h: Likewise.
1403 2006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1405 * config/tc-vax.c (md_chars_to_number): Used only locally, so
1407 * config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
1409 2006-03-17 Paul Brook <paul@codesourcery.com>
1411 * config/tc-arm.c (insns): Add ldm and stm.
1413 2006-03-17 Ben Elliston <bje@au.ibm.com>
1416 * doc/as.texinfo (Ident): Document this directive more thoroughly.
1418 2006-03-16 Paul Brook <paul@codesourcery.com>
1420 * config/tc-arm.c (insns): Add "svc".
1422 2006-03-13 Bob Wilson <bob.wilson@acm.org>
1424 * config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
1425 flag and avoid double underscore prefixes.
1427 2006-03-10 Paul Brook <paul@codesourcery.com>
1429 * config/tc-arm.c (md_begin): Handle EABIv5.
1430 (arm_eabis): Add EF_ARM_EABI_VER5.
1431 * doc/c-arm.texi: Document -meabi=5.
1433 2006-03-10 Ben Elliston <bje@au.ibm.com>
1435 * app.c (do_scrub_chars): Simplify string handling.
1437 2006-03-07 Richard Sandiford <richard@codesourcery.com>
1438 Daniel Jacobowitz <dan@codesourcery.com>
1439 Zack Weinberg <zack@codesourcery.com>
1440 Nathan Sidwell <nathan@codesourcery.com>
1441 Paul Brook <paul@codesourcery.com>
1442 Ricardo Anguiano <anguiano@codesourcery.com>
1443 Phil Edwards <phil@codesourcery.com>
1445 * config/tc-arm.c (md_apply_fix): Install a value of zero into a
1446 BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
1448 (tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
1449 relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
1450 relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
1452 2006-03-06 Bob Wilson <bob.wilson@acm.org>
1454 * config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
1455 even when using the text-section-literals option.
1457 2006-03-06 Nathan Sidwell <nathan@codesourcery.com>
1459 * config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
1461 (m68k_ip): <case 'J'> Check we have some control regs.
1462 (md_parse_option): Allow raw arch switch.
1463 (m68k_init_arch): Better detection of arch/cpu mismatch. Detect
1464 whether 68881 or cfloat was meant by -mfloat.
1465 (md_show_usage): Adjust extension display.
1466 (m68k_elf_final_processing): Adjust.
1468 2006-03-03 Bjoern Haase <bjoern.m.haase@web.de>
1470 * config/tc-avr.c (avr_mod_hash_value): New function.
1471 (md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
1472 BFD_RELOC_MS8_LDI for hlo8() and hhi8()
1473 (md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
1474 instead of int avr_ldi_expression: use avr_mod_hash_value instead
1476 (tc_gen_reloc): Handle substractions of symbols, if possible do
1477 fixups, abort otherwise.
1478 * config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
1479 tc_fix_adjustable): Define.
1481 2006-03-02 James E Wilson <wilson@specifix.com>
1483 * config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
1484 change the template, then clear md.slot[curr].end_of_insn_group.
1486 2006-02-28 Jan Beulich <jbeulich@novell.com>
1488 * macro.c (get_any_string): Don't insert quotes for <>-quoted input.
1490 2006-02-28 Jan Beulich <jbeulich@novell.com>
1493 * macro.c (getstring): Don't treat parentheses special anymore.
1494 (get_any_string): Don't consider '(' and ')' as quoting anymore.
1495 Special-case '(', ')', '[', and ']' when dealing with non-quoting
1498 2006-02-28 Mat <mat@csail.mit.edu>
1500 * dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
1502 2006-02-27 Jakub Jelinek <jakub@redhat.com>
1504 * dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
1506 (CFI_signal_frame): Define.
1507 (cfi_pseudo_table): Add .cfi_signal_frame.
1508 (dot_cfi): Handle CFI_signal_frame.
1509 (output_cie): Handle cie->signal_frame.
1510 (select_cie_for_fde): Don't share CIE if signal_frame flag is
1511 different. Copy signal_frame from FDE to newly created CIE.
1512 * doc/as.texinfo: Document .cfi_signal_frame.
1514 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
1516 * doc/Makefile.am: Add html target.
1517 * doc/Makefile.in: Regenerate.
1518 * po/Make-in: Add html target.
1520 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1522 * config/tc-i386.c (output_insn): Support Intel Merom New
1525 * config/tc-i386.h (CpuMNI): New.
1526 (CpuUnknownFlags): Add CpuMNI.
1528 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
1530 * config/tc-sparc.c (priv_reg_table): Add entry for "gl".
1531 (hpriv_reg_table): New table for hyperprivileged registers.
1532 (sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
1535 2006-02-24 DJ Delorie <dj@redhat.com>
1537 * config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
1538 (tc_gen_reloc): Don't define.
1539 * config/tc-m32c.c (rl_for, relaxable): New convenience macros.
1540 (OPTION_LINKRELAX): New.
1541 (md_longopts): Add it.
1543 (md_parse_options): Set it.
1544 (md_assemble): Emit relaxation relocs as needed.
1545 (md_convert_frag): Emit relaxation relocs as needed.
1546 (md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
1547 (m32c_apply_fix): New.
1548 (tc_gen_reloc): New.
1549 (m32c_force_relocation): Force out jump relocs when relaxing.
1550 (m32c_fix_adjustable): Return false if relaxing.
1552 2006-02-24 Paul Brook <paul@codesourcery.com>
1554 * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
1555 arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
1556 (struct asm_barrier_opt): Define.
1557 (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
1558 (parse_psr): Accept V7M psr names.
1559 (parse_barrier): New function.
1560 (enum operand_parse_code): Add OP_oBARRIER.
1561 (parse_operands): Implement OP_oBARRIER.
1562 (do_barrier): New function.
1563 (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
1564 (do_t_cpsi): Add V7M restrictions.
1565 (do_t_mrs, do_t_msr): Validate V7M variants.
1566 (md_assemble): Check for NULL variants.
1567 (v7m_psrs, barrier_opt_names): New tables.
1568 (insns): Add V7 instructions. Mark V6 instructions absent from V7M.
1569 (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
1570 (arm_cpu_option_table): Add Cortex-M3, R4 and A8.
1571 (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
1572 (struct cpu_arch_ver_table): Define.
1573 (cpu_arch_ver): New.
1574 (aeabi_set_public_attributes): Use cpu_arch_ver. Set
1575 Tag_CPU_arch_profile.
1576 * doc/c-arm.texi: Document new cpu and arch options.
1578 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1580 * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
1582 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1584 * config/tc-ia64.c: Update copyright years.
1586 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
1588 * config/tc-ia64.c (specify_resource): Add the rule 17 from
1591 2005-02-22 Paul Brook <paul@codesourcery.com>
1593 * config/tc-arm.c (do_pld): Remove incorrect write to
1595 (encode_thumb32_addr_mode): Use correct operand.
1597 2006-02-21 Paul Brook <paul@codesourcery.com>
1599 * config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
1601 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
1602 Anil Paranjape <anilp1@kpitcummins.com>
1603 Shilin Shakti <shilins@kpitcummins.com>
1605 * Makefile.am: Add xc16x related entry.
1606 * Makefile.in: Regenerate.
1607 * configure.in: Added xc16x related entry.
1608 * configure: Regenerate.
1609 * config/tc-xc16x.h: New file
1610 * config/tc-xc16x.c: New file
1611 * doc/c-xc16x.texi: New file for xc16x
1612 * doc/all.texi: Entry for xc16x
1613 * doc/Makefile.texi: Added c-xc16x.texi
1614 * NEWS: Announce the support for the new target.
1616 2006-02-16 Nick Hudson <nick.hudson@dsl.pipex.com>
1618 * configure.tgt: set emulation for mips-*-netbsd*
1620 2006-02-14 Jakub Jelinek <jakub@redhat.com>
1622 * config.in: Rebuilt.
1624 2006-02-13 Bob Wilson <bob.wilson@acm.org>
1626 * config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
1627 from 1, not 0, in error messages.
1628 (md_assemble): Simplify special-case check for ENTRY instructions.
1629 (tinsn_has_invalid_symbolic_operands): Do not include opcode and
1630 operand in error message.
1632 2006-02-13 Joseph S. Myers <joseph@codesourcery.com>
1634 * configure.tgt (arm-*-linux-gnueabi*): Change to
1637 2006-02-10 Nick Clifton <nickc@redhat.com>
1639 * config/tc-crx.c (check_range): Ensure that the sign bit of a
1640 32-bit value is propagated into the upper bits of a 64-bit long.
1642 * config/tc-arc.c (init_opcode_tables): Fix cast.
1643 (arc_extoper, md_operand): Likewise.
1645 2006-02-09 David Heine <dlheine@tensilica.com>
1647 * config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
1648 each relaxation step.
1650 2006-02-09 Eric Botcazou <ebotcazou@libertysurf.fr>
1652 * configure.in (CHECK_DECLS): Add vsnprintf.
1653 * configure: Regenerate.
1654 * messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
1655 include/declare here, but...
1656 * as.h: Move code detecting VARARGS idiom to the top.
1657 (errno.h, stdarg.h, varargs.h, va_list): ...here.
1658 (vsnprintf): Declare if not already declared.
1660 2006-02-08 H.J. Lu <hongjiu.lu@intel.com>
1662 * as.c (close_output_file): New.
1663 (main): Register close_output_file with xatexit before
1664 dump_statistics. Don't call output_file_close.
1666 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1668 * config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
1669 mcf5329_control_regs): New.
1670 (not_current_architecture, selected_arch, selected_cpu): New.
1671 (m68k_archs, m68k_extensions): New.
1672 (archs): Renamed to ...
1673 (m68k_cpus): ... here. Adjust.
1675 (md_pseudo_table): Add arch and cpu directives.
1676 (find_cf_chip, m68k_ip): Adjust table scanning.
1677 (no_68851, no_68881): Remove.
1678 (md_assemble): Lazily initialize.
1679 (select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
1680 (md_init_after_args): Move functionality to m68k_init_arch.
1681 (mri_chip): Adjust table scanning.
1682 (md_parse_option): Reimplement 'm' processing to add -march & -mcpu
1683 options with saner parsing.
1684 (m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
1685 m68k_init_arch): New.
1686 (s_m68k_cpu, s_m68k_arch): New.
1687 (md_show_usage): Adjust.
1688 (m68k_elf_final_processing): Set CF EF flags.
1689 * config/tc-m68k.h (m68k_init_after_args): Remove.
1690 (tc_init_after_args): Remove.
1691 * doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
1692 (M68k-Directives): Document .arch and .cpu directives.
1694 2006-02-05 Arnold Metselaar <arnold.metselaar@planet.nl>
1696 * config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
1697 synonyms for equ and defl.
1698 (z80_cons_fix_new): New function.
1699 (emit_byte): Disallow relative jumps to absolute locations.
1700 (emit_data): Only handle defb, prototype changed, because defb is
1701 now handled as pseudo-op rather than an instruction.
1702 (instab): Entries for defb,defw,db,dw moved from here...
1703 (md_pseudo_table): ... to here, use generic cons() for defw,dw.
1704 Add entries for def24,def32,d24,d32.
1705 (md_assemble): Improved error handling.
1706 (md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
1707 * config/tc-z80.h (TC_CONS_FIX_NEW): Define.
1708 (z80_cons_fix_new): Declare.
1709 * doc/c-z80.texi (defb, db): Mention warning on overflow.
1710 (def24,d24,def32,d32): New pseudo-ops.
1712 2006-02-02 Paul Brook <paul@codesourcery.com>
1714 * config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
1716 2005-02-02 Paul Brook <paul@codesourcery.com>
1718 * config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
1719 T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
1720 T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
1721 T2_OPCODE_RSB): Define.
1722 (thumb32_negate_data_op): New function.
1723 (md_apply_fix): Use it.
1725 2006-01-31 Bob Wilson <bob.wilson@acm.org>
1727 * config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
1729 * config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
1730 * config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
1732 (relaxation_requirements): Add pfinish_frag argument and use it to
1733 replace setting tinsn->record_fix fields.
1734 (xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
1735 and vinsn_to_insnbuf. Remove references to record_fix and
1736 slot_sub_symbols fields.
1737 (xtensa_mark_narrow_branches): Delete unused code.
1738 (is_narrow_branch_guaranteed_in_range): Handle expr that is not just
1740 (convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
1742 (tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
1743 (vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
1744 of the record_fix field. Simplify error messages for unexpected
1746 (set_expr_symbol_offset_diff): Delete.
1748 2006-01-31 Paul Brook <paul@codesourcery.com>
1750 * config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
1752 2006-01-31 Paul Brook <paul@codesourcery.com>
1753 Richard Earnshaw <rearnsha@arm.com>
1755 * config/tc-arm.c: Use arm_feature_set.
1756 (arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
1757 arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
1758 fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
1761 (md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
1762 md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
1763 arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
1764 s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
1766 (arm_legacy_option_table, arm_option_cpu_value_table): New types.
1767 (arm_opts): Move old cpu/arch options from here...
1768 (arm_legacy_opts): ... to here.
1769 (md_parse_option): Search arm_legacy_opts.
1770 (arm_cpus, arm_archs, arm_extensions, arm_fpus)
1771 (arm_float_abis, arm_eabis): Make const.
1773 2006-01-25 Bob Wilson <bob.wilson@acm.org>
1775 * config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
1777 2006-01-21 Jie Zhang <jie.zhang@analog.com>
1779 * config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
1780 in load immediate intruction.
1782 2006-01-21 Jie Zhang <jie.zhang@analog.com>
1784 * config/bfin-parse.y (value_match): Use correct conversion
1785 specifications in template string for __FILE__ and __LINE__.
1789 2006-01-18 Alexandre Oliva <aoliva@redhat.com>
1791 Introduce TLS descriptors for i386 and x86_64.
1792 * config/tc-i386.c (tc_i386_fix_adjustable): Handle
1793 BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
1794 BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
1795 (optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
1796 BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
1798 (build_modrm_byte): Set up zero modrm for TLS desc calls.
1799 (lex_got): Handle @tlsdesc and @tlscall.
1800 (md_apply_fix, tc_gen_reloc): Handle the new relocations.
1802 2006-01-11 Nick Clifton <nickc@redhat.com>
1804 Fixes for building on 64-bit hosts:
1805 * config/tc-avr.c (mod_index): New union to allow conversion
1806 between pointers and integers.
1807 (md_begin, avr_ldi_expression): Use it.
1808 * config/tc-i370.c (md_assemble): Add cast for argument to print
1810 * config/tc-tic54x.c (subsym_substitute): Likewise.
1811 * config/tc-mn10200.c (md_assemble): Use a union to convert the
1812 opindex field of fr_cgen structure into a pointer so that it can
1813 be stored in a frag.
1814 * config/tc-mn10300.c (md_assemble): Likewise.
1815 * config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
1817 * config/tc-v850.c: Replace uses of (int) casts with correct
1820 2006-01-09 H.J. Lu <hongjiu.lu@intel.com>
1823 * symbols.c (snapshot_symbol): Don't change a defined symbol.
1825 2006-01-03 Hans-Peter Nilsson <hp@bitrange.com>
1828 * config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
1829 a local-label reference.
1831 For older changes see ChangeLog-2005
1837 version-control: never