gas/config/bfin-parse.y

   1 /* bfin-parse.y  ADI Blackfin parser
   2    Copyright 2005, 2006, 2007
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21 %{
  22
  23 #include "as.h"
  24 #include <obstack.h>
  25
  26 #include "bfin-aux.h"  // opcode generating auxiliaries
  27 #include "libbfd.h"
  28 #include "elf/common.h"
  29 #include "elf/bfin.h"
  30
  31 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
  32         bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
  33
  34 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
  35         bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
  36                            dst, src0, src1, w0)
  37
  38 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
  39         bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
  40                             dst, src0, src1, w0)
  41
  42 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls)  \
  43         bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
  44
  45 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls)  \
  46         bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
  47
  48 #define LDIMMHALF_R(reg, h, s, z, hword) \
  49         bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
  50
  51 #define LDIMMHALF_R5(reg, h, s, z, hword) \
  52         bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
  53
  54 #define LDSTIDXI(ptr, reg, w, sz, z, offset)  \
  55         bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
  56
  57 #define LDST(ptr, reg, aop, sz, z, w)  \
  58         bfin_gen_ldst (ptr, reg, aop, sz, z, w)
  59
  60 #define LDSTII(ptr, reg, offset, w, op)  \
  61         bfin_gen_ldstii (ptr, reg, offset, w, op)
  62
  63 #define DSPLDST(i, m, reg, aop, w) \
  64         bfin_gen_dspldst (i, reg, aop, w, m)
  65
  66 #define LDSTPMOD(ptr, reg, idx, aop, w) \
  67         bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
  68
  69 #define LDSTIIFP(offset, reg, w)  \
  70         bfin_gen_ldstiifp (reg, offset, w)
  71
  72 #define LOGI2OP(dst, src, opc) \
  73         bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
  74
  75 #define ALU2OP(dst, src, opc)  \
  76         bfin_gen_alu2op (dst, src, opc)
  77
  78 #define BRCC(t, b, offset) \
  79         bfin_gen_brcc (t, b, offset)
  80
  81 #define UJUMP(offset) \
  82         bfin_gen_ujump (offset)
  83
  84 #define PROGCTRL(prgfunc, poprnd) \
  85         bfin_gen_progctrl (prgfunc, poprnd)
  86
  87 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
  88         bfin_gen_pushpopmultiple (dr, pr, d, p, w)
  89
  90 #define PUSHPOPREG(reg, w) \
  91         bfin_gen_pushpopreg (reg, w)
  92
  93 #define CALLA(addr, s)  \
  94         bfin_gen_calla (addr, s)
  95
  96 #define LINKAGE(r, framesize) \
  97         bfin_gen_linkage (r, framesize)
  98
  99 #define COMPI2OPD(dst, src, op)  \
 100         bfin_gen_compi2opd (dst, src, op)
 101
 102 #define COMPI2OPP(dst, src, op)  \
 103         bfin_gen_compi2opp (dst, src, op)
 104
 105 #define DAGMODIK(i, op)  \
 106         bfin_gen_dagmodik (i, op)
 107
 108 #define DAGMODIM(i, m, op, br)  \
 109         bfin_gen_dagmodim (i, m, op, br)
 110
 111 #define COMP3OP(dst, src0, src1, opc)   \
 112         bfin_gen_comp3op (src0, src1, dst, opc)
 113
 114 #define PTR2OP(dst, src, opc)   \
 115         bfin_gen_ptr2op (dst, src, opc)
 116
 117 #define CCFLAG(x, y, opc, i, g)  \
 118         bfin_gen_ccflag (x, y, opc, i, g)
 119
 120 #define CCMV(src, dst, t) \
 121         bfin_gen_ccmv (src, dst, t)
 122
 123 #define CACTRL(reg, a, op) \
 124         bfin_gen_cactrl (reg, a, op)
 125
 126 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
 127         bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
 128
 129 #define HL2(r1, r0)  (IS_H (r1) << 1 | IS_H (r0))
 130 #define IS_RANGE(bits, expr, sign, mul)    \
 131         value_match(expr, bits, sign, mul, 1)
 132 #define IS_URANGE(bits, expr, sign, mul)    \
 133         value_match(expr, bits, sign, mul, 0)
 134 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
 135 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
 136 #define IS_IMM(expr, bits)  value_match (expr, bits, 0, 1, 1)
 137 #define IS_UIMM(expr, bits)  value_match (expr, bits, 0, 1, 0)
 138
 139 #define IS_PCREL4(expr) \
 140         (value_match (expr, 4, 0, 2, 0))
 141
 142 #define IS_LPPCREL10(expr) \
 143         (value_match (expr, 10, 0, 2, 0))
 144
 145 #define IS_PCREL10(expr) \
 146         (value_match (expr, 10, 0, 2, 1))
 147
 148 #define IS_PCREL12(expr) \
 149         (value_match (expr, 12, 0, 2, 1))
 150
 151 #define IS_PCREL24(expr) \
 152         (value_match (expr, 24, 0, 2, 1))
 153
 154
 155 static int value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned);
 156
 157 extern FILE *errorf;
 158 extern INSTR_T insn;
 159
 160 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
 161 static Expr_Node *unary  (Expr_Op_Type, Expr_Node *);
 162
 163 static void notethat (char *format, ...);
 164
 165 char *current_inputline;
 166 extern char *yytext;
 167 int yyerror (char *msg);
 168
 169 void error (char *format, ...)
 170 {
 171     va_list ap;
 172     char buffer[2000];
 173
 174     va_start (ap, format);
 175     vsprintf (buffer, format, ap);
 176     va_end (ap);
 177
 178     as_bad (buffer);
 179 }
 180
 181 int
 182 yyerror (char *msg)
 183 {
 184   if (msg[0] == '\0')
 185     error ("%s", msg);
 186
 187   else if (yytext[0] != ';')
 188     error ("%s. Input text was %s.", msg, yytext);
 189   else
 190     error ("%s.", msg);
 191
 192   return -1;
 193 }
 194
 195 static int
 196 in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
 197 {
 198   int val = EXPR_VALUE (expr);
 199   if (expr->type != Expr_Node_Constant)
 200     return 0;
 201   if (val < from || val > to)
 202     return 0;
 203   return (val & mask) == 0;
 204 }
 205
 206 extern int yylex (void);
 207
 208 #define imm3(x) EXPR_VALUE (x)
 209 #define imm4(x) EXPR_VALUE (x)
 210 #define uimm4(x) EXPR_VALUE (x)
 211 #define imm5(x) EXPR_VALUE (x)
 212 #define uimm5(x) EXPR_VALUE (x)
 213 #define imm6(x) EXPR_VALUE (x)
 214 #define imm7(x) EXPR_VALUE (x)
 215 #define imm16(x) EXPR_VALUE (x)
 216 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
 217 #define uimm16(x) EXPR_VALUE (x)
 218
 219 /* Return true if a value is inside a range.  */
 220 #define IN_RANGE(x, low, high) \
 221   (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
 222
 223 /* Auxiliary functions.  */
 224
 225 static void
 226 neg_value (Expr_Node *expr)
 227 {
 228   expr->value.i_value = -expr->value.i_value;
 229 }
 230
 231 static int
 232 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
 233 {
 234   if (!IS_DREG (*reg1))
 235     {
 236       yyerror ("Dregs expected");
 237       return 0;
 238     }
 239
 240   if (reg1->regno != 1 && reg1->regno != 3)
 241     {
 242       yyerror ("Bad register pair");
 243       return 0;
 244     }
 245
 246   if (imm7 (reg2) != reg1->regno - 1)
 247     {
 248       yyerror ("Bad register pair");
 249       return 0;
 250     }
 251
 252   reg1->regno--;
 253   return 1;
 254 }
 255
 256 static int
 257 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
 258 {
 259   if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
 260       || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
 261     return yyerror ("Source multiplication register mismatch");
 262
 263   return 0;
 264 }
 265
 266
 267 /* Check mac option.  */
 268
 269 static int
 270 check_macfunc_option (Macfunc *a, Opt_mode *opt)
 271 {
 272   /* Default option is always valid.  */
 273   if (opt->mod == 0)
 274     return 0;
 275
 276   if ((a->op == 3 && a->w == 1 && a->P == 1
 277        && opt->mod != M_FU && opt->mod != M_S2RND && opt->mod != M_ISS2)
 278       || (a->op == 3 && a->w == 1 && a->P == 0
 279           && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
 280           && opt->mod != M_T && opt->mod != M_S2RND && opt->mod != M_ISS2
 281           && opt->mod != M_IH)
 282       || (a->w == 0 && a->P == 0
 283           && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32)
 284       || (a->w == 1 && a->P == 1
 285           && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_S2RND
 286           && opt->mod != M_ISS2)
 287       || (a->w == 1 && a->P == 0
 288           && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
 289           && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
 290           && opt->mod != M_ISS2 && opt->mod != M_IH))
 291     return -1;
 292
 293   return 0;
 294 }
 295
 296 /* Check (vector) mac funcs and ops.  */
 297
 298 static int
 299 check_macfuncs (Macfunc *aa, Opt_mode *opa,
 300                 Macfunc *ab, Opt_mode *opb)
 301 {
 302   /* Variables for swapping.  */
 303   Macfunc mtmp;
 304   Opt_mode otmp;
 305
 306   /* The option mode should be put at the end of the second instruction
 307      of the vector except M, which should follow MAC1 instruction.  */
 308   if (opa->mod != 0)
 309     return yyerror ("Bad opt mode");
 310
 311   /* If a0macfunc comes before a1macfunc, swap them.  */
 312
 313   if (aa->n == 0)
 314     {
 315       /*  (M) is not allowed here.  */
 316       if (opa->MM != 0)
 317         return yyerror ("(M) not allowed with A0MAC");
 318       if (ab->n != 1)
 319         return yyerror ("Vector AxMACs can't be same");
 320
 321       mtmp = *aa; *aa = *ab; *ab = mtmp;
 322       otmp = *opa; *opa = *opb; *opb = otmp;
 323     }
 324   else
 325     {
 326       if (opb->MM != 0)
 327         return yyerror ("(M) not allowed with A0MAC");
 328       if (ab->n != 0)
 329         return yyerror ("Vector AxMACs can't be same");
 330     }
 331
 332   /*  If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
 333   assignment_or_macfuncs.  */
 334   if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
 335       && (ab->op == 0 || ab->op == 1 || ab->op == 2))
 336     {
 337       if (check_multiply_halfregs (aa, ab) < 0)
 338         return -1;
 339     }
 340   else
 341     {
 342       /*  Only one of the assign_macfuncs has a half reg multiply
 343       Evil trick: Just 'OR' their source register codes:
 344       We can do that, because we know they were initialized to 0
 345       in the rules that don't use multiply_halfregs.  */
 346       aa->s0.regno |= (ab->s0.regno & CODE_MASK);
 347       aa->s1.regno |= (ab->s1.regno & CODE_MASK);
 348     }
 349
 350   if (aa->w == ab->w  && aa->P != ab->P)
 351     {
 352       return yyerror ("macfuncs must differ");
 353       if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
 354         return yyerror ("Destination Dregs must differ by one");
 355     }
 356   /* We assign to full regs, thus obey even/odd rules.  */
 357   else if ((aa->w && aa->P && IS_EVEN (aa->dst))
 358            || (ab->w && ab->P && !IS_EVEN (ab->dst)))
 359     return yyerror ("Even/Odd register assignment mismatch");
 360   /* We assign to half regs, thus obey hi/low rules.  */
 361   else if ( (aa->w && !aa->P && !IS_H (aa->dst))
 362             || (ab->w && !aa->P && IS_H (ab->dst)))
 363     return yyerror ("High/Low register assignment mismatch");
 364
 365   /* Make sure mod flags get ORed, too.  */
 366   opb->mod |= opa->mod;
 367
 368   /* Check option.  */
 369   if (check_macfunc_option (aa, opb) < 0
 370       && check_macfunc_option (ab, opb) < 0)
 371     return yyerror ("bad option");
 372
 373   /* Make sure first macfunc has got both P flags ORed.  */
 374   aa->P |= ab->P;
 375
 376   return 0;
 377 }
 378
 379
 380 static int
 381 is_group1 (INSTR_T x)
 382 {
 383   /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii.  */
 384   if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
 385     return 1;
 386
 387   return 0;
 388 }
 389
 390 static int
 391 is_group2 (INSTR_T x)
 392 {
 393   if ((((x->value & 0xfc00) == 0x9c00)  /* dspLDST.  */
 394        && !((x->value & 0xfde0) == 0x9c60)  /* dagMODim.  */
 395        && !((x->value & 0xfde0) == 0x9ce0)  /* dagMODim with bit rev.  */
 396        && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik.  */
 397       || (x->value == 0x0000))
 398     return 1;
 399   return 0;
 400 }
 401
 402 %}
 403
 404 %union {
 405   INSTR_T instr;
 406   Expr_Node *expr;
 407   SYMBOL_T symbol;
 408   long value;
 409   Register reg;
 410   Macfunc macfunc;
 411   struct { int r0; int s0; int x0; int aop; } modcodes;
 412   struct { int r0; } r0;
 413   Opt_mode mod;
 414 }
 415
 416
 417 /* Tokens.  */
 418
 419 /* Vector Specific.  */
 420 %token BYTEOP16P BYTEOP16M
 421 %token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
 422 %token BYTEUNPACK BYTEPACK
 423 %token PACK
 424 %token SAA
 425 %token ALIGN8 ALIGN16 ALIGN24
 426 %token VIT_MAX
 427 %token EXTRACT DEPOSIT EXPADJ SEARCH
 428 %token ONES SIGN SIGNBITS
 429
 430 /* Stack.  */
 431 %token LINK UNLINK
 432
 433 /* Registers.  */
 434 %token REG
 435 %token PC
 436 %token CCREG BYTE_DREG
 437 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
 438 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
 439 %token HALF_REG
 440
 441 /* Progctrl.  */
 442 %token NOP
 443 %token RTI RTS RTX RTN RTE
 444 %token HLT IDLE
 445 %token STI CLI
 446 %token CSYNC SSYNC
 447 %token EMUEXCPT
 448 %token RAISE EXCPT
 449 %token LSETUP
 450 %token LOOP
 451 %token LOOP_BEGIN
 452 %token LOOP_END
 453 %token DISALGNEXCPT
 454 %token JUMP JUMP_DOT_S JUMP_DOT_L
 455 %token CALL
 456
 457 /* Emulator only.  */
 458 %token ABORT
 459
 460 /* Operators.  */
 461 %token NOT TILDA BANG
 462 %token AMPERSAND BAR
 463 %token PERCENT
 464 %token CARET
 465 %token BXOR
 466
 467 %token MINUS PLUS STAR SLASH
 468 %token NEG
 469 %token MIN MAX ABS
 470 %token DOUBLE_BAR
 471 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
 472 %token _MINUS_MINUS _PLUS_PLUS
 473
 474 /* Shift/rotate ops.  */
 475 %token SHIFT LSHIFT ASHIFT BXORSHIFT
 476 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
 477 %token ROT
 478 %token LESS_LESS GREATER_GREATER
 479 %token _GREATER_GREATER_GREATER
 480 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
 481 %token DIVS DIVQ
 482
 483 /* In place operators.  */
 484 %token ASSIGN _STAR_ASSIGN
 485 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
 486 %token _MINUS_ASSIGN _PLUS_ASSIGN
 487
 488 /* Assignments, comparisons.  */
 489 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
 490 %token GE LT LE GT
 491 %token LESS_THAN
 492
 493 /* Cache.  */
 494 %token FLUSHINV FLUSH
 495 %token IFLUSH PREFETCH
 496
 497 /* Misc.  */
 498 %token PRNT
 499 %token OUTC
 500 %token WHATREG
 501 %token TESTSET
 502
 503 /* Modifiers.  */
 504 %token ASL ASR
 505 %token B W
 506 %token NS S CO SCO
 507 %token TH TL
 508 %token BP
 509 %token BREV
 510 %token X Z
 511 %token M MMOD
 512 %token R RND RNDL RNDH RND12 RND20
 513 %token V
 514 %token LO HI
 515
 516 /* Bit ops.  */
 517 %token BITTGL BITCLR BITSET BITTST BITMUX
 518
 519 /* Debug.  */
 520 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
 521
 522 /* Semantic auxiliaries.  */
 523
 524 %token IF COMMA BY
 525 %token COLON SEMICOLON
 526 %token RPAREN LPAREN LBRACK RBRACK
 527 %token STATUS_REG
 528 %token MNOP
 529 %token SYMBOL NUMBER
 530 %token GOT GOT17M4 FUNCDESC_GOT17M4
 531 %token AT PLTPC
 532
 533 /* Types.  */
 534 %type <instr> asm
 535 %type <value> MMOD
 536 %type <mod> opt_mode
 537
 538 %type <value> NUMBER
 539 %type <r0> aligndir
 540 %type <modcodes> byteop_mod
 541 %type <reg> a_assign
 542 %type <reg> a_plusassign
 543 %type <reg> a_minusassign
 544 %type <macfunc> multiply_halfregs
 545 %type <macfunc> assign_macfunc
 546 %type <macfunc> a_macfunc
 547 %type <expr> expr_1
 548 %type <instr> asm_1
 549 %type <r0> vmod
 550 %type <modcodes> vsmod
 551 %type <modcodes> ccstat
 552 %type <r0> cc_op
 553 %type <reg> CCREG
 554 %type <reg> reg_with_postinc
 555 %type <reg> reg_with_predec
 556
 557 %type <r0> searchmod
 558 %type <expr> symbol
 559 %type <symbol> SYMBOL
 560 %type <expr> eterm
 561 %type <reg> REG
 562 %type <reg> BYTE_DREG
 563 %type <reg> REG_A_DOUBLE_ZERO
 564 %type <reg> REG_A_DOUBLE_ONE
 565 %type <reg> REG_A
 566 %type <reg> STATUS_REG
 567 %type <expr> expr
 568 %type <r0> xpmod
 569 %type <r0> xpmod1
 570 %type <modcodes> smod
 571 %type <modcodes> b3_op
 572 %type <modcodes> rnd_op
 573 %type <modcodes> post_op
 574 %type <reg> HALF_REG
 575 %type <r0> iu_or_nothing
 576 %type <r0> plus_minus
 577 %type <r0> asr_asl
 578 %type <r0> asr_asl_0
 579 %type <modcodes> sco
 580 %type <modcodes> amod0
 581 %type <modcodes> amod1
 582 %type <modcodes> amod2
 583 %type <r0> op_bar_op
 584 %type <r0> w32_or_nothing
 585 %type <r0> c_align
 586 %type <r0> min_max
 587 %type <expr> got
 588 %type <expr> got_or_expr
 589 %type <expr> pltpc
 590 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
 591
 592 /* Precedence rules.  */
 593 %left BAR
 594 %left CARET
 595 %left AMPERSAND
 596 %left LESS_LESS GREATER_GREATER
 597 %left PLUS MINUS
 598 %left STAR SLASH PERCENT
 599
 600 %right ASSIGN
 601
 602 %right TILDA BANG
 603 %start statement
 604 %%
 605 statement:
 606         | asm
 607         {
 608           insn = $1;
 609           if (insn == (INSTR_T) 0)
 610             return NO_INSN_GENERATED;
 611           else if (insn == (INSTR_T) - 1)
 612             return SEMANTIC_ERROR;
 613           else
 614             return INSN_GENERATED;
 615         }
 616         ;
 617
 618 asm: asm_1 SEMICOLON
 619         /* Parallel instructions.  */
 620         | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
 621         {
 622           if (($1->value & 0xf800) == 0xc000)
 623             {
 624               if (is_group1 ($3) && is_group2 ($5))
 625                 $$ = bfin_gen_multi_instr ($1, $3, $5);
 626               else if (is_group2 ($3) && is_group1 ($5))
 627                 $$ = bfin_gen_multi_instr ($1, $5, $3);
 628               else
 629                 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
 630             }
 631           else if (($3->value & 0xf800) == 0xc000)
 632             {
 633               if (is_group1 ($1) && is_group2 ($5))
 634                 $$ = bfin_gen_multi_instr ($3, $1, $5);
 635               else if (is_group2 ($1) && is_group1 ($5))
 636                 $$ = bfin_gen_multi_instr ($3, $5, $1);
 637               else
 638                 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
 639             }
 640           else if (($5->value & 0xf800) == 0xc000)
 641             {
 642               if (is_group1 ($1) && is_group2 ($3))
 643                 $$ = bfin_gen_multi_instr ($5, $1, $3);
 644               else if (is_group2 ($1) && is_group1 ($3))
 645                 $$ = bfin_gen_multi_instr ($5, $3, $1);
 646               else
 647                 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
 648             }
 649           else
 650             error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
 651         }
 652
 653         | asm_1 DOUBLE_BAR asm_1 SEMICOLON
 654         {
 655           if (($1->value & 0xf800) == 0xc000)
 656             {
 657               if (is_group1 ($3))
 658                 $$ = bfin_gen_multi_instr ($1, $3, 0);
 659               else if (is_group2 ($3))
 660                 $$ = bfin_gen_multi_instr ($1, 0, $3);
 661               else
 662                 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
 663             }
 664           else if (($3->value & 0xf800) == 0xc000)
 665             {
 666               if (is_group1 ($1))
 667                 $$ = bfin_gen_multi_instr ($3, $1, 0);
 668               else if (is_group2 ($1))
 669                 $$ = bfin_gen_multi_instr ($3, 0, $1);
 670               else
 671                 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
 672             }
 673           else if (is_group1 ($1) && is_group2 ($3))
 674               $$ = bfin_gen_multi_instr (0, $1, $3);
 675           else if (is_group2 ($1) && is_group1 ($3))
 676             $$ = bfin_gen_multi_instr (0, $3, $1);
 677           else
 678             return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
 679         }
 680         | error
 681         {
 682         $$ = 0;
 683         yyerror ("");
 684         yyerrok;
 685         }
 686         ;
 687
 688 /* DSPMAC.  */
 689
 690 asm_1:
 691         MNOP
 692         {
 693           $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
 694         }
 695         | assign_macfunc opt_mode
 696         {
 697           int op0, op1;
 698           int w0 = 0, w1 = 0;
 699           int h00, h10, h01, h11;
 700
 701           if (check_macfunc_option (&$1, &$2) < 0)
 702             return yyerror ("bad option");
 703
 704           if ($1.n == 0)
 705             {
 706               if ($2.MM)
 707                 return yyerror ("(m) not allowed with a0 unit");
 708               op1 = 3;
 709               op0 = $1.op;
 710               w1 = 0;
 711               w0 = $1.w;
 712               h00 = IS_H ($1.s0);
 713               h10 = IS_H ($1.s1);
 714               h01 = h11 = 0;
 715             }
 716           else
 717             {
 718               op1 = $1.op;
 719               op0 = 3;
 720               w1 = $1.w;
 721               w0 = 0;
 722               h00 = h10 = 0;
 723               h01 = IS_H ($1.s0);
 724               h11 = IS_H ($1.s1);
 725             }
 726           $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
 727                          &$1.dst, op0, &$1.s0, &$1.s1, w0);
 728         }
 729
 730
 731 /* VECTOR MACs.  */
 732
 733         | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
 734         {
 735           Register *dst;
 736
 737           if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
 738             return -1;
 739           notethat ("assign_macfunc (.), assign_macfunc (.)\n");
 740
 741           if ($1.w)
 742             dst = &$1.dst;
 743           else
 744             dst = &$4.dst;
 745
 746           $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
 747                          IS_H ($1.s0),  IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
 748                          dst, $4.op, &$1.s0, &$1.s1, $4.w);
 749         }
 750
 751 /* DSPALU.  */
 752
 753         | DISALGNEXCPT
 754         {
 755           notethat ("dsp32alu: DISALGNEXCPT\n");
 756           $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
 757         }
 758         | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
 759         {
 760           if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
 761             {
 762               notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
 763               $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
 764             }
 765           else
 766             return yyerror ("Register mismatch");
 767         }
 768         | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
 769         {
 770           if (!IS_A1 ($4) && IS_A1 ($5))
 771             {
 772               notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
 773               $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
 774             }
 775           else
 776             return yyerror ("Register mismatch");
 777         }
 778         | A_ZERO_DOT_H ASSIGN HALF_REG
 779         {
 780           notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
 781           $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
 782         }
 783         | A_ONE_DOT_H ASSIGN HALF_REG
 784         {
 785           notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
 786           $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
 787         }
 788         | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
 789           COLON expr COMMA REG COLON expr RPAREN aligndir
 790         {
 791           if (!IS_DREG ($2) || !IS_DREG ($4))
 792             return yyerror ("Dregs expected");
 793           else if (!valid_dreg_pair (&$9, $11))
 794             return yyerror ("Bad dreg pair");
 795           else if (!valid_dreg_pair (&$13, $15))
 796             return yyerror ("Bad dreg pair");
 797           else
 798             {
 799               notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
 800               $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
 801             }
 802         }
 803
 804         | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
 805           REG COLON expr RPAREN aligndir
 806         {
 807           if (!IS_DREG ($2) || !IS_DREG($4))
 808             return yyerror ("Dregs expected");
 809           else if (!valid_dreg_pair (&$9, $11))
 810             return yyerror ("Bad dreg pair");
 811           else if (!valid_dreg_pair (&$13, $15))
 812             return yyerror ("Bad dreg pair");
 813           else
 814             {
 815               notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
 816               $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
 817             }
 818         }
 819
 820         | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
 821         {
 822           if (!IS_DREG ($2) || !IS_DREG ($4))
 823             return yyerror ("Dregs expected");
 824           else if (!valid_dreg_pair (&$8, $10))
 825             return yyerror ("Bad dreg pair");
 826           else
 827             {
 828               notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
 829               $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
 830             }
 831         }
 832         | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
 833         {
 834           if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
 835             {
 836               notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
 837               $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
 838             }
 839           else
 840             return yyerror ("Register mismatch");
 841         }
 842         | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
 843           REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
 844         {
 845           if (IS_DREG ($1) && IS_DREG ($7))
 846             {
 847               notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h  \n");
 848               $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
 849             }
 850           else
 851             return yyerror ("Register mismatch");
 852         }
 853
 854
 855         | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
 856         {
 857           if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
 858               && IS_A1 ($9) && !IS_A1 ($11))
 859             {
 860               notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
 861               $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
 862
 863             }
 864           else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
 865                    && !IS_A1 ($9) && IS_A1 ($11))
 866             {
 867               notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
 868               $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
 869             }
 870           else
 871             return yyerror ("Register mismatch");
 872         }
 873
 874         | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
 875         {
 876           if ($4.r0 == $10.r0)
 877             return yyerror ("Operators must differ");
 878
 879           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
 880               && REG_SAME ($3, $9) && REG_SAME ($5, $11))
 881             {
 882               notethat ("dsp32alu: dregs = dregs + dregs,"
 883                        "dregs = dregs - dregs (amod1)\n");
 884               $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
 885             }
 886           else
 887             return yyerror ("Register mismatch");
 888         }
 889
 890 /*  Bar Operations.  */
 891
 892         | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
 893         {
 894           if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
 895             return yyerror ("Differing source registers");
 896
 897           if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
 898             return yyerror ("Dregs expected");
 899
 900
 901           if ($4.r0 == 1 && $10.r0 == 2)
 902             {
 903               notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
 904               $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
 905             }
 906           else if ($4.r0 == 0 && $10.r0 == 3)
 907             {
 908               notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
 909               $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
 910             }
 911           else
 912             return yyerror ("Bar operand mismatch");
 913         }
 914
 915         | REG ASSIGN ABS REG vmod
 916         {
 917           int op;
 918
 919           if (IS_DREG ($1) && IS_DREG ($4))
 920             {
 921               if ($5.r0)
 922                 {
 923                   notethat ("dsp32alu: dregs = ABS dregs (v)\n");
 924                   op = 6;
 925                 }
 926               else
 927                 {
 928                   /* Vector version of ABS.  */
 929                   notethat ("dsp32alu: dregs = ABS dregs\n");
 930                   op = 7;
 931                 }
 932               $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
 933             }
 934           else
 935             return yyerror ("Dregs expected");
 936         }
 937         | a_assign ABS REG_A
 938         {
 939           notethat ("dsp32alu: Ax = ABS Ax\n");
 940           $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
 941         }
 942         | A_ZERO_DOT_L ASSIGN HALF_REG
 943         {
 944           if (IS_DREG_L ($3))
 945             {
 946               notethat ("dsp32alu: A0.l = reg_half\n");
 947               $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
 948             }
 949           else
 950             return yyerror ("A0.l = Rx.l expected");
 951         }
 952         | A_ONE_DOT_L ASSIGN HALF_REG
 953         {
 954           if (IS_DREG_L ($3))
 955             {
 956               notethat ("dsp32alu: A1.l = reg_half\n");
 957               $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
 958             }
 959           else
 960             return yyerror ("A1.l = Rx.l expected");
 961         }
 962
 963         | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
 964         {
 965           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
 966             {
 967               notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
 968               $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
 969             }
 970           else
 971             return yyerror ("Dregs expected");
 972         }
 973
 974         | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
 975         {
 976           if (!IS_DREG ($1))
 977             return yyerror ("Dregs expected");
 978           else if (!valid_dreg_pair (&$5, $7))
 979             return yyerror ("Bad dreg pair");
 980           else if (!valid_dreg_pair (&$9, $11))
 981             return yyerror ("Bad dreg pair");
 982           else
 983             {
 984               notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
 985               $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
 986             }
 987         }
 988         | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
 989         {
 990           if (!IS_DREG ($1))
 991             return yyerror ("Dregs expected");
 992           else if (!valid_dreg_pair (&$5, $7))
 993             return yyerror ("Bad dreg pair");
 994           else if (!valid_dreg_pair (&$9, $11))
 995             return yyerror ("Bad dreg pair");
 996           else
 997             {
 998               notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
 999               $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1000             }
1001         }
1002
1003         | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1004           rnd_op
1005         {
1006           if (!IS_DREG ($1))
1007             return yyerror ("Dregs expected");
1008           else if (!valid_dreg_pair (&$5, $7))
1009             return yyerror ("Bad dreg pair");
1010           else if (!valid_dreg_pair (&$9, $11))
1011             return yyerror ("Bad dreg pair");
1012           else
1013             {
1014               notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1015               $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1016             }
1017         }
1018
1019         | REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1020           rnd_op
1021         {
1022           if (!IS_DREG ($1))
1023             return yyerror ("Dregs expected");
1024           else if (!valid_dreg_pair (&$5, $7))
1025             return yyerror ("Bad dreg pair");
1026           else if (!valid_dreg_pair (&$9, $11))
1027             return yyerror ("Bad dreg pair");
1028           else
1029             {
1030               notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1031               $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, 0, $13.x0);
1032             }
1033         }
1034
1035         | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1036           b3_op
1037         {
1038           if (!IS_DREG ($1))
1039             return yyerror ("Dregs expected");
1040           else if (!valid_dreg_pair (&$5, $7))
1041             return yyerror ("Bad dreg pair");
1042           else if (!valid_dreg_pair (&$9, $11))
1043             return yyerror ("Bad dreg pair");
1044           else
1045             {
1046               notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1047               $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1048             }
1049         }
1050
1051         | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1052         {
1053           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1054             {
1055               notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1056               $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1057             }
1058           else
1059             return yyerror ("Dregs expected");
1060         }
1061
1062         | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1063           HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1064         {
1065           if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1066             {
1067               notethat ("dsp32alu:      dregs_hi = dregs_lo ="
1068                        "SIGN (dregs_hi) * dregs_hi + "
1069                        "SIGN (dregs_lo) * dregs_lo \n");
1070
1071                 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1072             }
1073           else
1074             return yyerror ("Dregs expected");
1075         }
1076         | REG ASSIGN REG plus_minus REG amod1
1077         {
1078           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1079             {
1080               if ($6.aop == 0)
1081                 {
1082                   /* No saturation flag specified, generate the 16 bit variant.  */
1083                   notethat ("COMP3op: dregs = dregs +- dregs\n");
1084                   $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1085                 }
1086               else
1087                 {
1088                  /* Saturation flag specified, generate the 32 bit variant.  */
1089                  notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1090                  $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1091                 }
1092             }
1093           else
1094             if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1095               {
1096                 notethat ("COMP3op: pregs = pregs + pregs\n");
1097                 $$ = COMP3OP (&$1, &$3, &$5, 5);
1098               }
1099             else
1100               return yyerror ("Dregs expected");
1101         }
1102         | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1103         {
1104           int op;
1105
1106           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1107             {
1108               if ($9.r0)
1109                 op = 6;
1110               else
1111                 op = 7;
1112
1113               notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1114               $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1115             }
1116           else
1117             return yyerror ("Dregs expected");
1118         }
1119
1120         | a_assign MINUS REG_A
1121         {
1122           notethat ("dsp32alu: Ax = - Ax\n");
1123           $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1124         }
1125         | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1126         {
1127           notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1128           $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1129                          $6.s0, $6.x0, HL2 ($3, $5));
1130         }
1131         | a_assign a_assign expr
1132         {
1133           if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1134             {
1135               notethat ("dsp32alu: A1 = A0 = 0\n");
1136               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1137             }
1138           else
1139             return yyerror ("Bad value, 0 expected");
1140         }
1141
1142         /* Saturating.  */
1143         | a_assign REG_A LPAREN S RPAREN
1144         {
1145           if (REG_SAME ($1, $2))
1146             {
1147               notethat ("dsp32alu: Ax = Ax (S)\n");
1148               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1149             }
1150           else
1151             return yyerror ("Registers must be equal");
1152         }
1153
1154         | HALF_REG ASSIGN REG LPAREN RND RPAREN
1155         {
1156           if (IS_DREG ($3))
1157             {
1158               notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1159               $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1160             }
1161           else
1162             return yyerror ("Dregs expected");
1163         }
1164
1165         | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1166         {
1167           if (IS_DREG ($3) && IS_DREG ($5))
1168             {
1169               notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1170               $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1171             }
1172           else
1173             return yyerror ("Dregs expected");
1174         }
1175
1176         | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1177         {
1178           if (IS_DREG ($3) && IS_DREG ($5))
1179             {
1180               notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1181               $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1182             }
1183           else
1184             return yyerror ("Dregs expected");
1185         }
1186
1187         | a_assign REG_A
1188         {
1189           if (!REG_SAME ($1, $2))
1190             {
1191               notethat ("dsp32alu: An = Am\n");
1192               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1193             }
1194           else
1195             return yyerror ("Accu reg arguments must differ");
1196         }
1197
1198         | a_assign REG
1199         {
1200           if (IS_DREG ($2))
1201             {
1202               notethat ("dsp32alu: An = dregs\n");
1203               $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1204             }
1205           else
1206             return yyerror ("Dregs expected");
1207         }
1208
1209         | REG ASSIGN HALF_REG xpmod
1210         {
1211           if (!IS_H ($3))
1212             {
1213               if ($1.regno == REG_A0x && IS_DREG ($3))
1214                 {
1215                   notethat ("dsp32alu: A0.x = dregs_lo\n");
1216                   $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1217                 }
1218               else if ($1.regno == REG_A1x && IS_DREG ($3))
1219                 {
1220                   notethat ("dsp32alu: A1.x = dregs_lo\n");
1221                   $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1222                 }
1223               else if (IS_DREG ($1) && IS_DREG ($3))
1224                 {
1225                   notethat ("ALU2op: dregs = dregs_lo\n");
1226                   $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1227                 }
1228               else
1229                 return yyerror ("Register mismatch");
1230             }
1231           else
1232             return yyerror ("Low reg expected");
1233         }
1234
1235         | HALF_REG ASSIGN expr
1236         {
1237           notethat ("LDIMMhalf: pregs_half = imm16\n");
1238
1239           if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1240               && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1241             return yyerror ("Wrong register for load immediate");
1242
1243           if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1244             return yyerror ("Constant out of range");
1245
1246           $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1247         }
1248
1249         | a_assign expr
1250         {
1251           notethat ("dsp32alu: An = 0\n");
1252
1253           if (imm7 ($2) != 0)
1254             return yyerror ("0 expected");
1255
1256           $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1257         }
1258
1259         | REG ASSIGN expr xpmod1
1260         {
1261           if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1262               && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1263             return yyerror ("Wrong register for load immediate");
1264
1265           if ($4.r0 == 0)
1266             {
1267               /* 7 bit immediate value if possible.
1268                  We will check for that constant value for efficiency
1269                  If it goes to reloc, it will be 16 bit.  */
1270               if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1271                 {
1272                   notethat ("COMPI2opD: dregs = imm7 (x) \n");
1273                   $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1274                 }
1275               else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1276                 {
1277                   notethat ("COMPI2opP: pregs = imm7 (x)\n");
1278                   $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1279                 }
1280               else
1281                 {
1282                   if (IS_CONST ($3) && !IS_IMM ($3, 16))
1283                     return yyerror ("Immediate value out of range");
1284
1285                   notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1286                   /* reg, H, S, Z.   */
1287                   $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1288                 }
1289             }
1290           else
1291             {
1292               /* (z) There is no 7 bit zero extended instruction.
1293               If the expr is a relocation, generate it.   */
1294
1295               if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1296                 return yyerror ("Immediate value out of range");
1297
1298               notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1299               /* reg, H, S, Z.  */
1300               $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1301             }
1302         }
1303
1304         | HALF_REG ASSIGN REG
1305         {
1306           if (IS_H ($1))
1307             return yyerror ("Low reg expected");
1308
1309           if (IS_DREG ($1) && $3.regno == REG_A0x)
1310             {
1311               notethat ("dsp32alu: dregs_lo = A0.x\n");
1312               $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1313             }
1314           else if (IS_DREG ($1) && $3.regno == REG_A1x)
1315             {
1316               notethat ("dsp32alu: dregs_lo = A1.x\n");
1317               $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1318             }
1319           else
1320             return yyerror ("Register mismatch");
1321         }
1322
1323         | REG ASSIGN REG op_bar_op REG amod0
1324         {
1325           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1326             {
1327               notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1328               $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1329             }
1330           else
1331             return yyerror ("Register mismatch");
1332         }
1333
1334         | REG ASSIGN BYTE_DREG xpmod
1335         {
1336           if (IS_DREG ($1) && IS_DREG ($3))
1337             {
1338               notethat ("ALU2op: dregs = dregs_byte\n");
1339               $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1340             }
1341           else
1342             return yyerror ("Register mismatch");
1343         }
1344
1345         | a_assign ABS REG_A COMMA a_assign ABS REG_A
1346         {
1347           if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1348             {
1349               notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1350               $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1351             }
1352           else
1353             return yyerror ("Register mismatch");
1354         }
1355
1356         | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1357         {
1358           if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1359             {
1360               notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1361               $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1362             }
1363           else
1364             return yyerror ("Register mismatch");
1365         }
1366
1367         | a_minusassign REG_A w32_or_nothing
1368         {
1369           if (!IS_A1 ($1) && IS_A1 ($2))
1370             {
1371               notethat ("dsp32alu: A0 -= A1\n");
1372               $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1373             }
1374           else
1375             return yyerror ("Register mismatch");
1376         }
1377
1378         | REG _MINUS_ASSIGN expr
1379         {
1380           if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1381             {
1382               notethat ("dagMODik: iregs -= 4\n");
1383               $$ = DAGMODIK (&$1, 3);
1384             }
1385           else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1386             {
1387               notethat ("dagMODik: iregs -= 2\n");
1388               $$ = DAGMODIK (&$1, 1);
1389             }
1390           else
1391             return yyerror ("Register or value mismatch");
1392         }
1393
1394         | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1395         {
1396           if (IS_IREG ($1) && IS_MREG ($3))
1397             {
1398               notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1399               /* i, m, op, br.  */
1400               $$ = DAGMODIM (&$1, &$3, 0, 1);
1401             }
1402           else if (IS_PREG ($1) && IS_PREG ($3))
1403             {
1404               notethat ("PTR2op: pregs += pregs (BREV )\n");
1405               $$ = PTR2OP (&$1, &$3, 5);
1406             }
1407           else
1408             return yyerror ("Register mismatch");
1409         }
1410
1411         | REG _MINUS_ASSIGN REG
1412         {
1413           if (IS_IREG ($1) && IS_MREG ($3))
1414             {
1415               notethat ("dagMODim: iregs -= mregs\n");
1416               $$ = DAGMODIM (&$1, &$3, 1, 0);
1417             }
1418           else if (IS_PREG ($1) && IS_PREG ($3))
1419             {
1420               notethat ("PTR2op: pregs -= pregs\n");
1421               $$ = PTR2OP (&$1, &$3, 0);
1422             }
1423           else
1424             return yyerror ("Register mismatch");
1425         }
1426
1427         | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1428         {
1429           if (!IS_A1 ($1) && IS_A1 ($3))
1430             {
1431               notethat ("dsp32alu: A0 += A1 (W32)\n");
1432               $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1433             }
1434           else
1435             return yyerror ("Register mismatch");
1436         }
1437
1438         | REG _PLUS_ASSIGN REG
1439         {
1440           if (IS_IREG ($1) && IS_MREG ($3))
1441             {
1442               notethat ("dagMODim: iregs += mregs\n");
1443               $$ = DAGMODIM (&$1, &$3, 0, 0);
1444             }
1445           else
1446             return yyerror ("iregs += mregs expected");
1447         }
1448
1449         | REG _PLUS_ASSIGN expr
1450         {
1451           if (IS_IREG ($1))
1452             {
1453               if (EXPR_VALUE ($3) == 4)
1454                 {
1455                   notethat ("dagMODik: iregs += 4\n");
1456                   $$ = DAGMODIK (&$1, 2);
1457                 }
1458               else if (EXPR_VALUE ($3) == 2)
1459                 {
1460                   notethat ("dagMODik: iregs += 2\n");
1461                   $$ = DAGMODIK (&$1, 0);
1462                 }
1463               else
1464                 return yyerror ("iregs += [ 2 | 4 ");
1465             }
1466           else if (IS_PREG ($1) && IS_IMM ($3, 7))
1467             {
1468               notethat ("COMPI2opP: pregs += imm7\n");
1469               $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1470             }
1471           else if (IS_DREG ($1) && IS_IMM ($3, 7))
1472             {
1473               notethat ("COMPI2opD: dregs += imm7\n");
1474               $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1475             }
1476           else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1477             return yyerror ("Immediate value out of range");
1478           else
1479             return yyerror ("Register mismatch");
1480         }
1481
1482         | REG _STAR_ASSIGN REG
1483         {
1484           if (IS_DREG ($1) && IS_DREG ($3))
1485             {
1486               notethat ("ALU2op: dregs *= dregs\n");
1487               $$ = ALU2OP (&$1, &$3, 3);
1488             }
1489           else
1490             return yyerror ("Register mismatch");
1491         }
1492
1493         | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1494         {
1495           if (!valid_dreg_pair (&$3, $5))
1496             return yyerror ("Bad dreg pair");
1497           else if (!valid_dreg_pair (&$7, $9))
1498             return yyerror ("Bad dreg pair");
1499           else
1500             {
1501               notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1502               $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1503             }
1504         }
1505
1506         | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1507         {
1508           if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1509             {
1510               notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1511               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1512             }
1513           else
1514             return yyerror ("Register mismatch");
1515         }
1516
1517         | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1518         {
1519           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1520               && REG_SAME ($1, $4))
1521             {
1522               if (EXPR_VALUE ($9) == 1)
1523                 {
1524                   notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1525                   $$ = ALU2OP (&$1, &$6, 4);
1526                 }
1527               else if (EXPR_VALUE ($9) == 2)
1528                 {
1529                   notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1530                   $$ = ALU2OP (&$1, &$6, 5);
1531                 }
1532               else
1533                 return yyerror ("Bad shift value");
1534             }
1535           else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1536                    && REG_SAME ($1, $4))
1537             {
1538               if (EXPR_VALUE ($9) == 1)
1539                 {
1540                   notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1541                   $$ = PTR2OP (&$1, &$6, 6);
1542                 }
1543               else if (EXPR_VALUE ($9) == 2)
1544                 {
1545                   notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1546                   $$ = PTR2OP (&$1, &$6, 7);
1547                 }
1548               else
1549                 return yyerror ("Bad shift value");
1550             }
1551           else
1552             return yyerror ("Register mismatch");
1553         }
1554
1555 /*  COMP3 CCFLAG.  */
1556         | REG ASSIGN REG BAR REG
1557         {
1558           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1559             {
1560               notethat ("COMP3op: dregs = dregs | dregs\n");
1561               $$ = COMP3OP (&$1, &$3, &$5, 3);
1562             }
1563           else
1564             return yyerror ("Dregs expected");
1565         }
1566         | REG ASSIGN REG CARET REG
1567         {
1568           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1569             {
1570               notethat ("COMP3op: dregs = dregs ^ dregs\n");
1571               $$ = COMP3OP (&$1, &$3, &$5, 4);
1572             }
1573           else
1574             return yyerror ("Dregs expected");
1575         }
1576         | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1577         {
1578           if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1579             {
1580               if (EXPR_VALUE ($8) == 1)
1581                 {
1582                   notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1583                   $$ = COMP3OP (&$1, &$3, &$6, 6);
1584                 }
1585               else if (EXPR_VALUE ($8) == 2)
1586                 {
1587                   notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1588                   $$ = COMP3OP (&$1, &$3, &$6, 7);
1589                 }
1590               else
1591                   return yyerror ("Bad shift value");
1592             }
1593           else
1594             return yyerror ("Dregs expected");
1595         }
1596         | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1597         {
1598           if ($3.regno == REG_A0 && $5.regno == REG_A1)
1599             {
1600               notethat ("CCflag: CC = A0 == A1\n");
1601               $$ = CCFLAG (0, 0, 5, 0, 0);
1602             }
1603           else
1604             return yyerror ("AREGs are in bad order or same");
1605         }
1606         | CCREG ASSIGN REG_A LESS_THAN REG_A
1607         {
1608           if ($3.regno == REG_A0 && $5.regno == REG_A1)
1609             {
1610               notethat ("CCflag: CC = A0 < A1\n");
1611               $$ = CCFLAG (0, 0, 6, 0, 0);
1612             }
1613           else
1614             return yyerror ("AREGs are in bad order or same");
1615         }
1616         | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1617         {
1618           if (REG_CLASS($3) == REG_CLASS($5))
1619             {
1620               notethat ("CCflag: CC = dpregs < dpregs\n");
1621               $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1622             }
1623           else
1624             return yyerror ("Compare only of same register class");
1625         }
1626         | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1627         {
1628           if (($6.r0 == 1 && IS_IMM ($5, 3))
1629               || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1630             {
1631               notethat ("CCflag: CC = dpregs < (u)imm3\n");
1632               $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1633             }
1634           else
1635             return yyerror ("Bad constant value");
1636         }
1637         | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1638         {
1639           if (REG_CLASS($3) == REG_CLASS($5))
1640             {
1641               notethat ("CCflag: CC = dpregs == dpregs\n");
1642               $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1643             }
1644           else
1645             return yyerror ("Compare only of same register class");
1646         }
1647         | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1648         {
1649           if (IS_IMM ($5, 3))
1650             {
1651               notethat ("CCflag: CC = dpregs == imm3\n");
1652               $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1653             }
1654           else
1655             return yyerror ("Bad constant range");
1656         }
1657         | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1658         {
1659           if ($3.regno == REG_A0 && $5.regno == REG_A1)
1660             {
1661               notethat ("CCflag: CC = A0 <= A1\n");
1662               $$ = CCFLAG (0, 0, 7, 0, 0);
1663             }
1664           else
1665             return yyerror ("AREGs are in bad order or same");
1666         }
1667         | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1668         {
1669           if (REG_CLASS($3) == REG_CLASS($5))
1670             {
1671               notethat ("CCflag: CC = pregs <= pregs (..)\n");
1672               $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1673                            1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1674             }
1675           else
1676             return yyerror ("Compare only of same register class");
1677         }
1678         | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1679         {
1680           if (($6.r0 == 1 && IS_IMM ($5, 3))
1681               || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1682             {
1683               if (IS_DREG ($3))
1684                 {
1685                   notethat ("CCflag: CC = dregs <= (u)imm3\n");
1686                   /*    x       y     opc     I     G   */
1687                   $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 0);
1688                 }
1689               else if (IS_PREG ($3))
1690                 {
1691                   notethat ("CCflag: CC = pregs <= (u)imm3\n");
1692                   /*    x       y     opc     I     G   */
1693                   $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 1);
1694                 }
1695               else
1696                 return yyerror ("Dreg or Preg expected");
1697             }
1698           else
1699             return yyerror ("Bad constant value");
1700         }
1701
1702         | REG ASSIGN REG AMPERSAND REG
1703         {
1704           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1705             {
1706               notethat ("COMP3op: dregs = dregs & dregs\n");
1707               $$ = COMP3OP (&$1, &$3, &$5, 2);
1708             }
1709           else
1710             return yyerror ("Dregs expected");
1711         }
1712
1713         | ccstat
1714         {
1715           notethat ("CC2stat operation\n");
1716           $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1717         }
1718
1719         | REG ASSIGN REG
1720         {
1721           if (IS_ALLREG ($1) && IS_ALLREG ($3))
1722             {
1723               notethat ("REGMV: allregs = allregs\n");
1724               $$ = bfin_gen_regmv (&$3, &$1);
1725             }
1726           else
1727             return yyerror ("Register mismatch");
1728         }
1729
1730         | CCREG ASSIGN REG
1731         {
1732           if (IS_DREG ($3))
1733             {
1734               notethat ("CC2dreg: CC = dregs\n");
1735               $$ = bfin_gen_cc2dreg (1, &$3);
1736             }
1737           else
1738             return yyerror ("Register mismatch");
1739         }
1740
1741         | REG ASSIGN CCREG
1742         {
1743           if (IS_DREG ($1))
1744             {
1745               notethat ("CC2dreg: dregs = CC\n");
1746               $$ = bfin_gen_cc2dreg (0, &$1);
1747             }
1748           else
1749             return yyerror ("Register mismatch");
1750         }
1751
1752         | CCREG _ASSIGN_BANG CCREG
1753         {
1754           notethat ("CC2dreg: CC =! CC\n");
1755           $$ = bfin_gen_cc2dreg (3, 0);
1756         }
1757
1758 /* DSPMULT.  */
1759
1760         | HALF_REG ASSIGN multiply_halfregs opt_mode
1761         {
1762           notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1763
1764           if (!IS_H ($1) && $4.MM)
1765             return yyerror ("(M) not allowed with MAC0");
1766
1767           if (IS_H ($1))
1768             {
1769               $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1770                               IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1771                               &$1, 0, &$3.s0, &$3.s1, 0);
1772             }
1773           else
1774             {
1775               $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1776                               0, 0, IS_H ($3.s0), IS_H ($3.s1),
1777                               &$1, 0, &$3.s0, &$3.s1, 1);
1778             }
1779         }
1780
1781         | REG ASSIGN multiply_halfregs opt_mode
1782         {
1783           /* Odd registers can use (M).  */
1784           if (!IS_DREG ($1))
1785             return yyerror ("Dreg expected");
1786
1787           if (IS_EVEN ($1) && $4.MM)
1788             return yyerror ("(M) not allowed with MAC0");
1789
1790           if (!IS_EVEN ($1))
1791             {
1792               notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1793
1794               $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1795                               IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1796                               &$1, 0, &$3.s0, &$3.s1, 0);
1797             }
1798           else
1799             {
1800               notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1801               $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1802                               0, 0, IS_H ($3.s0), IS_H ($3.s1),
1803                               &$1,  0, &$3.s0, &$3.s1, 1);
1804             }
1805         }
1806
1807         | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1808           HALF_REG ASSIGN multiply_halfregs opt_mode
1809         {
1810           if (!IS_DREG ($1) || !IS_DREG ($6))
1811             return yyerror ("Dregs expected");
1812
1813           if (!IS_HCOMPL($1, $6))
1814             return yyerror ("Dest registers mismatch");
1815
1816           if (check_multiply_halfregs (&$3, &$8) < 0)
1817             return -1;
1818
1819           if ((!IS_H ($1) && $4.MM)
1820               || (!IS_H ($6) && $9.MM))
1821             return yyerror ("(M) not allowed with MAC0");
1822
1823           notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1824                     "dregs_lo = multiply_halfregs opt_mode\n");
1825
1826           if (IS_H ($1))
1827             $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1828                             IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1829                             &$1, 0, &$3.s0, &$3.s1, 1);
1830           else
1831             $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1832                             IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1833                             &$1, 0, &$3.s0, &$3.s1, 1);
1834         }
1835
1836         | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1837         {
1838           if (!IS_DREG ($1) || !IS_DREG ($6))
1839             return yyerror ("Dregs expected");
1840
1841           if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1842               || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1843             return yyerror ("Dest registers mismatch");
1844
1845           if (check_multiply_halfregs (&$3, &$8) < 0)
1846             return -1;
1847
1848           if ((IS_EVEN ($1) && $4.MM)
1849               || (IS_EVEN ($6) && $9.MM))
1850             return yyerror ("(M) not allowed with MAC0");
1851
1852           notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1853                    "dregs = multiply_halfregs opt_mode\n");
1854
1855           if (IS_EVEN ($1))
1856             $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1857                             IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1858                             &$1, 0, &$3.s0, &$3.s1, 1);
1859           else
1860             $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1861                             IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1862                             &$1, 0, &$3.s0, &$3.s1, 1);
1863         }
1864
1865 \f
1866 /* SHIFTs.  */
1867         | a_assign ASHIFT REG_A BY HALF_REG
1868         {
1869           if (!REG_SAME ($1, $3))
1870             return yyerror ("Aregs must be same");
1871
1872           if (IS_DREG ($5) && !IS_H ($5))
1873             {
1874               notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1875               $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1876             }
1877           else
1878             return yyerror ("Dregs expected");
1879         }
1880
1881         | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1882         {
1883           if (IS_DREG ($6) && !IS_H ($6))
1884             {
1885               notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1886               $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1887             }
1888           else
1889             return yyerror ("Dregs expected");
1890         }
1891
1892         | a_assign REG_A LESS_LESS expr
1893         {
1894           if (!REG_SAME ($1, $2))
1895             return yyerror ("Aregs must be same");
1896
1897           if (IS_UIMM ($4, 5))
1898             {
1899               notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1900               $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1901             }
1902           else
1903             return yyerror ("Bad shift value");
1904         }
1905
1906         | REG ASSIGN REG LESS_LESS expr vsmod
1907         {
1908           if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1909             {
1910               if ($6.r0)
1911                 {
1912                   /*  Vector?  */
1913                   notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1914                   $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1915                 }
1916               else
1917                 {
1918                   notethat ("dsp32shiftimm: dregs =  dregs << uimm5 (.)\n");
1919                   $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1920                 }
1921             }
1922           else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1923             {
1924               if (EXPR_VALUE ($5) == 2)
1925                 {
1926                   notethat ("PTR2op: pregs = pregs << 2\n");
1927                   $$ = PTR2OP (&$1, &$3, 1);
1928                 }
1929               else if (EXPR_VALUE ($5) == 1)
1930                 {
1931                   notethat ("COMP3op: pregs = pregs << 1\n");
1932                   $$ = COMP3OP (&$1, &$3, &$3, 5);
1933                 }
1934               else
1935                 return yyerror ("Bad shift value");
1936             }
1937           else
1938             return yyerror ("Bad shift value or register");
1939         }
1940         | HALF_REG ASSIGN HALF_REG LESS_LESS expr
1941         {
1942           if (IS_UIMM ($5, 4))
1943             {
1944               notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1945               $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
1946             }
1947           else
1948             return yyerror ("Bad shift value");
1949         }
1950         | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1951         {
1952           if (IS_UIMM ($5, 4))
1953             {
1954               notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1955               $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
1956             }
1957           else
1958             return yyerror ("Bad shift value");
1959         }
1960         | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
1961         {
1962           int op;
1963
1964           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
1965             {
1966               if ($7.r0)
1967                 {
1968                   op = 1;
1969                   notethat ("dsp32shift: dregs = ASHIFT dregs BY "
1970                            "dregs_lo (V, .)\n");
1971                 }
1972               else
1973                 {
1974
1975                   op = 2;
1976                   notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
1977                 }
1978               $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
1979             }
1980           else
1981             return yyerror ("Dregs expected");
1982         }
1983
1984 /*  EXPADJ.  */
1985         | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
1986         {
1987           if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
1988             {
1989               notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
1990               $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
1991             }
1992           else
1993             return yyerror ("Bad shift value or register");
1994         }
1995
1996
1997         | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
1998         {
1999           if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2000             {
2001               notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2002               $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
2003             }
2004           else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
2005             {
2006               notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2007               $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2008             }
2009           else
2010             return yyerror ("Bad shift value or register");
2011         }
2012
2013 /* DEPOSIT.  */
2014
2015         | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2016         {
2017           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2018             {
2019               notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2020               $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2021             }
2022           else
2023             return yyerror ("Register mismatch");
2024         }
2025
2026         | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2027         {
2028           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2029             {
2030               notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2031               $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2032             }
2033           else
2034             return yyerror ("Register mismatch");
2035         }
2036
2037         | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2038         {
2039           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2040             {
2041               notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2042               $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2043             }
2044           else
2045             return yyerror ("Register mismatch");
2046         }
2047
2048         | a_assign REG_A _GREATER_GREATER_GREATER expr
2049         {
2050           if (!REG_SAME ($1, $2))
2051             return yyerror ("Aregs must be same");
2052
2053           if (IS_UIMM ($4, 5))
2054             {
2055               notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2056               $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2057             }
2058           else
2059             return yyerror ("Shift value range error");
2060         }
2061         | a_assign LSHIFT REG_A BY HALF_REG
2062         {
2063           if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2064             {
2065               notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2066               $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2067             }
2068           else
2069             return yyerror ("Register mismatch");
2070         }
2071
2072         | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2073         {
2074           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2075             {
2076               notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2077               $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2078             }
2079           else
2080             return yyerror ("Register mismatch");
2081         }
2082
2083         | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2084         {
2085           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2086             {
2087               notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2088               $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2089             }
2090           else
2091             return yyerror ("Register mismatch");
2092         }
2093
2094         | REG ASSIGN SHIFT REG BY HALF_REG
2095         {
2096           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2097             {
2098               notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2099               $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2100             }
2101           else
2102             return yyerror ("Register mismatch");
2103         }
2104
2105         | a_assign REG_A GREATER_GREATER expr
2106         {
2107           if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2108             {
2109               notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2110               $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2111             }
2112           else
2113             return yyerror ("Accu register expected");
2114         }
2115
2116         | REG ASSIGN REG GREATER_GREATER expr vmod
2117         {
2118           if ($6.r0 == 1)
2119             {
2120               if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2121                 {
2122                   notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2123                   $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2124                 }
2125               else
2126                 return yyerror ("Register mismatch");
2127             }
2128           else
2129             {
2130               if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2131                 {
2132                   notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2133                   $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2134                 }
2135               else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2136                 {
2137                   notethat ("PTR2op: pregs = pregs >> 2\n");
2138                   $$ = PTR2OP (&$1, &$3, 3);
2139                 }
2140               else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2141                 {
2142                   notethat ("PTR2op: pregs = pregs >> 1\n");
2143                   $$ = PTR2OP (&$1, &$3, 4);
2144                 }
2145               else
2146                 return yyerror ("Register mismatch");
2147             }
2148         }
2149         | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2150         {
2151           if (IS_UIMM ($5, 5))
2152             {
2153               notethat ("dsp32shiftimm:  dregs_half =  dregs_half >> uimm5\n");
2154               $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2155             }
2156           else
2157             return yyerror ("Register mismatch");
2158         }
2159         | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2160         {
2161           if (IS_UIMM ($5, 5))
2162             {
2163               notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2164               $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2165                                   $6.s0, HL2 ($1, $3));
2166             }
2167           else
2168             return yyerror ("Register or modifier mismatch");
2169         }
2170
2171
2172         | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2173         {
2174           if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2175             {
2176               if ($6.r0)
2177                 {
2178                   /* Vector?  */
2179                   notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (V, .)\n");
2180                   $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2181                 }
2182               else
2183                 {
2184                   notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (.)\n");
2185                   $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2186                 }
2187             }
2188           else
2189             return yyerror ("Register mismatch");
2190         }
2191
2192         | HALF_REG ASSIGN ONES REG
2193         {
2194           if (IS_DREG_L ($1) && IS_DREG ($4))
2195             {
2196               notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2197               $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2198             }
2199           else
2200             return yyerror ("Register mismatch");
2201         }
2202
2203         | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2204         {
2205           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2206             {
2207               notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2208               $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2209             }
2210           else
2211             return yyerror ("Register mismatch");
2212         }
2213
2214         | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2215         {
2216           if (IS_DREG ($1)
2217               && $7.regno == REG_A0
2218               && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2219             {
2220               notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2221               $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2222             }
2223           else
2224             return yyerror ("Register mismatch");
2225         }
2226
2227         | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2228         {
2229           if (IS_DREG ($1)
2230               && $7.regno == REG_A0
2231               && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2232             {
2233               notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2234               $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2235             }
2236           else
2237             return yyerror ("Register mismatch");
2238         }
2239
2240         | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2241         {
2242           if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2243             {
2244               notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2245               $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2246             }
2247           else
2248             return yyerror ("Register mismatch");
2249         }
2250
2251         | a_assign ROT REG_A BY HALF_REG
2252         {
2253           if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2254             {
2255               notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2256               $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2257             }
2258           else
2259             return yyerror ("Register mismatch");
2260         }
2261
2262         | REG ASSIGN ROT REG BY HALF_REG
2263         {
2264           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2265             {
2266               notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2267               $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2268             }
2269           else
2270             return yyerror ("Register mismatch");
2271         }
2272
2273         | a_assign ROT REG_A BY expr
2274         {
2275           if (IS_IMM ($5, 6))
2276             {
2277               notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2278               $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2279             }
2280           else
2281             return yyerror ("Register mismatch");
2282         }
2283
2284         | REG ASSIGN ROT REG BY expr
2285         {
2286           if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2287             {
2288               $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2289             }
2290           else
2291             return yyerror ("Register mismatch");
2292         }
2293
2294         | HALF_REG ASSIGN SIGNBITS REG_A
2295         {
2296           if (IS_DREG_L ($1))
2297             {
2298               notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2299               $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2300             }
2301           else
2302             return yyerror ("Register mismatch");
2303         }
2304
2305         | HALF_REG ASSIGN SIGNBITS REG
2306         {
2307           if (IS_DREG_L ($1) && IS_DREG ($4))
2308             {
2309               notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2310               $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2311             }
2312           else
2313             return yyerror ("Register mismatch");
2314         }
2315
2316         | HALF_REG ASSIGN SIGNBITS HALF_REG
2317         {
2318           if (IS_DREG_L ($1))
2319             {
2320               notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2321               $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2322             }
2323           else
2324             return yyerror ("Register mismatch");
2325         }
2326
2327         /* The ASR bit is just inverted here. */
2328         | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2329         {
2330           if (IS_DREG_L ($1) && IS_DREG ($5))
2331             {
2332               notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2333               $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2334             }
2335           else
2336             return yyerror ("Register mismatch");
2337         }
2338
2339         | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2340         {
2341           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2342             {
2343               notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2344               $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2345             }
2346           else
2347             return yyerror ("Register mismatch");
2348         }
2349
2350         | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2351         {
2352           if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2353             {
2354               notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2355               $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2356             }
2357           else
2358             return yyerror ("Register mismatch");
2359         }
2360
2361         | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2362         {
2363           if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2364             {
2365               notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2366               $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2367             }
2368           else
2369             return yyerror ("Dregs expected");
2370         }
2371
2372
2373 /* LOGI2op:     BITCLR (dregs, uimm5).  */
2374         | BITCLR LPAREN REG COMMA expr RPAREN
2375         {
2376           if (IS_DREG ($3) && IS_UIMM ($5, 5))
2377             {
2378               notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2379               $$ = LOGI2OP ($3, uimm5 ($5), 4);
2380             }
2381           else
2382             return yyerror ("Register mismatch");
2383         }
2384
2385 /* LOGI2op:     BITSET (dregs, uimm5).  */
2386         | BITSET LPAREN REG COMMA expr RPAREN
2387         {
2388           if (IS_DREG ($3) && IS_UIMM ($5, 5))
2389             {
2390               notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2391               $$ = LOGI2OP ($3, uimm5 ($5), 2);
2392             }
2393           else
2394             return yyerror ("Register mismatch");
2395         }
2396
2397 /* LOGI2op:     BITTGL (dregs, uimm5).  */
2398         | BITTGL LPAREN REG COMMA expr RPAREN
2399         {
2400           if (IS_DREG ($3) && IS_UIMM ($5, 5))
2401             {
2402               notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2403               $$ = LOGI2OP ($3, uimm5 ($5), 3);
2404             }
2405           else
2406             return yyerror ("Register mismatch");
2407         }
2408
2409         | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2410         {
2411           if (IS_DREG ($5) && IS_UIMM ($7, 5))
2412             {
2413               notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2414               $$ = LOGI2OP ($5, uimm5 ($7), 0);
2415             }
2416           else
2417             return yyerror ("Register mismatch or value error");
2418         }
2419
2420         | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2421         {
2422           if (IS_DREG ($5) && IS_UIMM ($7, 5))
2423             {
2424               notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2425               $$ = LOGI2OP ($5, uimm5 ($7), 1);
2426             }
2427           else
2428             return yyerror ("Register mismatch or value error");
2429         }
2430
2431         | IF BANG CCREG REG ASSIGN REG
2432         {
2433           if ((IS_DREG ($4) || IS_PREG ($4))
2434               && (IS_DREG ($6) || IS_PREG ($6)))
2435             {
2436               notethat ("ccMV: IF ! CC gregs = gregs\n");
2437               $$ = CCMV (&$6, &$4, 0);
2438             }
2439           else
2440             return yyerror ("Register mismatch");
2441         }
2442
2443         | IF CCREG REG ASSIGN REG
2444         {
2445           if ((IS_DREG ($5) || IS_PREG ($5))
2446               && (IS_DREG ($3) || IS_PREG ($3)))
2447             {
2448               notethat ("ccMV: IF CC gregs = gregs\n");
2449               $$ = CCMV (&$5, &$3, 1);
2450             }
2451           else
2452             return yyerror ("Register mismatch");
2453         }
2454
2455         | IF BANG CCREG JUMP expr
2456         {
2457           if (IS_PCREL10 ($5))
2458             {
2459               notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
2460               $$ = BRCC (0, 0, $5);
2461             }
2462           else
2463             return yyerror ("Bad jump offset");
2464         }
2465
2466         | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2467         {
2468           if (IS_PCREL10 ($5))
2469             {
2470               notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
2471               $$ = BRCC (0, 1, $5);
2472             }
2473           else
2474             return yyerror ("Bad jump offset");
2475         }
2476
2477         | IF CCREG JUMP expr
2478         {
2479           if (IS_PCREL10 ($4))
2480             {
2481               notethat ("BRCC: IF CC JUMP  pcrel11m2\n");
2482               $$ = BRCC (1, 0, $4);
2483             }
2484           else
2485             return yyerror ("Bad jump offset");
2486         }
2487
2488         | IF CCREG JUMP expr LPAREN BP RPAREN
2489         {
2490           if (IS_PCREL10 ($4))
2491             {
2492               notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
2493               $$ = BRCC (1, 1, $4);
2494             }
2495           else
2496             return yyerror ("Bad jump offset");
2497         }
2498         | NOP
2499         {
2500           notethat ("ProgCtrl: NOP\n");
2501           $$ = PROGCTRL (0, 0);
2502         }
2503
2504         | RTS
2505         {
2506           notethat ("ProgCtrl: RTS\n");
2507           $$ = PROGCTRL (1, 0);
2508         }
2509
2510         | RTI
2511         {
2512           notethat ("ProgCtrl: RTI\n");
2513           $$ = PROGCTRL (1, 1);
2514         }
2515
2516         | RTX
2517         {
2518           notethat ("ProgCtrl: RTX\n");
2519           $$ = PROGCTRL (1, 2);
2520         }
2521
2522         | RTN
2523         {
2524           notethat ("ProgCtrl: RTN\n");
2525           $$ = PROGCTRL (1, 3);
2526         }
2527
2528         | RTE
2529         {
2530           notethat ("ProgCtrl: RTE\n");
2531           $$ = PROGCTRL (1, 4);
2532         }
2533
2534         | IDLE
2535         {
2536           notethat ("ProgCtrl: IDLE\n");
2537           $$ = PROGCTRL (2, 0);
2538         }
2539
2540         | CSYNC
2541         {
2542           notethat ("ProgCtrl: CSYNC\n");
2543           $$ = PROGCTRL (2, 3);
2544         }
2545
2546         | SSYNC
2547         {
2548           notethat ("ProgCtrl: SSYNC\n");
2549           $$ = PROGCTRL (2, 4);
2550         }
2551
2552         | EMUEXCPT
2553         {
2554           notethat ("ProgCtrl: EMUEXCPT\n");
2555           $$ = PROGCTRL (2, 5);
2556         }
2557
2558         | CLI REG
2559         {
2560           if (IS_DREG ($2))
2561             {
2562               notethat ("ProgCtrl: CLI dregs\n");
2563               $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2564             }
2565           else
2566             return yyerror ("Dreg expected for CLI");
2567         }
2568
2569         | STI REG
2570         {
2571           if (IS_DREG ($2))
2572             {
2573               notethat ("ProgCtrl: STI dregs\n");
2574               $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2575             }
2576           else
2577             return yyerror ("Dreg expected for STI");
2578         }
2579
2580         | JUMP LPAREN REG RPAREN
2581         {
2582           if (IS_PREG ($3))
2583             {
2584               notethat ("ProgCtrl: JUMP (pregs )\n");
2585               $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2586             }
2587           else
2588             return yyerror ("Bad register for indirect jump");
2589         }
2590
2591         | CALL LPAREN REG RPAREN
2592         {
2593           if (IS_PREG ($3))
2594             {
2595               notethat ("ProgCtrl: CALL (pregs )\n");
2596               $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2597             }
2598           else
2599             return yyerror ("Bad register for indirect call");
2600         }
2601
2602         | CALL LPAREN PC PLUS REG RPAREN
2603         {
2604           if (IS_PREG ($5))
2605             {
2606               notethat ("ProgCtrl: CALL (PC + pregs )\n");
2607               $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2608             }
2609           else
2610             return yyerror ("Bad register for indirect call");
2611         }
2612
2613         | JUMP LPAREN PC PLUS REG RPAREN
2614         {
2615           if (IS_PREG ($5))
2616             {
2617               notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2618               $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2619             }
2620           else
2621             return yyerror ("Bad register for indirect jump");
2622         }
2623
2624         | RAISE expr
2625         {
2626           if (IS_UIMM ($2, 4))
2627             {
2628               notethat ("ProgCtrl: RAISE uimm4\n");
2629               $$ = PROGCTRL (9, uimm4 ($2));
2630             }
2631           else
2632             return yyerror ("Bad value for RAISE");
2633         }
2634
2635         | EXCPT expr
2636         {
2637                 notethat ("ProgCtrl: EMUEXCPT\n");
2638                 $$ = PROGCTRL (10, uimm4 ($2));
2639         }
2640
2641         | TESTSET LPAREN REG RPAREN
2642         {
2643           if (IS_PREG ($3))
2644             {
2645               notethat ("ProgCtrl: TESTSET (pregs )\n");
2646               $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2647             }
2648           else
2649             return yyerror ("Preg expected");
2650         }
2651
2652         | JUMP expr
2653         {
2654           if (IS_PCREL12 ($2))
2655             {
2656               notethat ("UJUMP: JUMP pcrel12\n");
2657               $$ = UJUMP ($2);
2658             }
2659           else
2660             return yyerror ("Bad value for relative jump");
2661         }
2662
2663         | JUMP_DOT_S expr
2664         {
2665           if (IS_PCREL12 ($2))
2666             {
2667               notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2668               $$ = UJUMP($2);
2669             }
2670           else
2671             return yyerror ("Bad value for relative jump");
2672         }
2673
2674         | JUMP_DOT_L expr
2675         {
2676           if (IS_PCREL24 ($2))
2677             {
2678               notethat ("CALLa: jump.l pcrel24\n");
2679               $$ = CALLA ($2, 0);
2680             }
2681           else
2682             return yyerror ("Bad value for long jump");
2683         }
2684
2685         | JUMP_DOT_L pltpc
2686         {
2687           if (IS_PCREL24 ($2))
2688             {
2689               notethat ("CALLa: jump.l pcrel24\n");
2690               $$ = CALLA ($2, 2);
2691             }
2692           else
2693             return yyerror ("Bad value for long jump");
2694         }
2695
2696         | CALL expr
2697         {
2698           if (IS_PCREL24 ($2))
2699             {
2700               notethat ("CALLa: CALL pcrel25m2\n");
2701               $$ = CALLA ($2, 1);
2702             }
2703           else
2704             return yyerror ("Bad call address");
2705         }
2706         | CALL pltpc
2707         {
2708           if (IS_PCREL24 ($2))
2709             {
2710               notethat ("CALLa: CALL pcrel25m2\n");
2711               $$ = CALLA ($2, 2);
2712             }
2713           else
2714             return yyerror ("Bad call address");
2715         }
2716
2717 /* ALU2ops.  */
2718 /* ALU2op:      DIVQ (dregs, dregs).  */
2719         | DIVQ LPAREN REG COMMA REG RPAREN
2720         {
2721           if (IS_DREG ($3) && IS_DREG ($5))
2722             $$ = ALU2OP (&$3, &$5, 8);
2723           else
2724             return yyerror ("Bad registers for DIVQ");
2725         }
2726
2727         | DIVS LPAREN REG COMMA REG RPAREN
2728         {
2729           if (IS_DREG ($3) && IS_DREG ($5))
2730             $$ = ALU2OP (&$3, &$5, 9);
2731           else
2732             return yyerror ("Bad registers for DIVS");
2733         }
2734
2735         | REG ASSIGN MINUS REG vsmod
2736         {
2737           if (IS_DREG ($1) && IS_DREG ($4))
2738             {
2739               if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2740                 {
2741                   notethat ("ALU2op: dregs = - dregs\n");
2742                   $$ = ALU2OP (&$1, &$4, 14);
2743                 }
2744               else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2745                 {
2746                   notethat ("dsp32alu: dregs = - dregs (.)\n");
2747                   $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2748                 }
2749               else
2750                 {
2751                   notethat ("dsp32alu: dregs = - dregs (.)\n");
2752                   $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2753                 }
2754             }
2755           else
2756             return yyerror ("Dregs expected");
2757         }
2758
2759         | REG ASSIGN TILDA REG
2760         {
2761           if (IS_DREG ($1) && IS_DREG ($4))
2762             {
2763               notethat ("ALU2op: dregs = ~dregs\n");
2764               $$ = ALU2OP (&$1, &$4, 15);
2765             }
2766           else
2767             return yyerror ("Dregs expected");
2768         }
2769
2770         | REG _GREATER_GREATER_ASSIGN REG
2771         {
2772           if (IS_DREG ($1) && IS_DREG ($3))
2773             {
2774               notethat ("ALU2op: dregs >>= dregs\n");
2775               $$ = ALU2OP (&$1, &$3, 1);
2776             }
2777           else
2778             return yyerror ("Dregs expected");
2779         }
2780
2781         | REG _GREATER_GREATER_ASSIGN expr
2782         {
2783           if (IS_DREG ($1) && IS_UIMM ($3, 5))
2784             {
2785               notethat ("LOGI2op: dregs >>= uimm5\n");
2786               $$ = LOGI2OP ($1, uimm5 ($3), 6);
2787             }
2788           else
2789             return yyerror ("Dregs expected or value error");
2790         }
2791
2792         | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2793         {
2794           if (IS_DREG ($1) && IS_DREG ($3))
2795             {
2796               notethat ("ALU2op: dregs >>>= dregs\n");
2797               $$ = ALU2OP (&$1, &$3, 0);
2798             }
2799           else
2800             return yyerror ("Dregs expected");
2801         }
2802
2803         | REG _LESS_LESS_ASSIGN REG
2804         {
2805           if (IS_DREG ($1) && IS_DREG ($3))
2806             {
2807               notethat ("ALU2op: dregs <<= dregs\n");
2808               $$ = ALU2OP (&$1, &$3, 2);
2809             }
2810           else
2811             return yyerror ("Dregs expected");
2812         }
2813
2814         | REG _LESS_LESS_ASSIGN expr
2815         {
2816           if (IS_DREG ($1) && IS_UIMM ($3, 5))
2817             {
2818               notethat ("LOGI2op: dregs <<= uimm5\n");
2819               $$ = LOGI2OP ($1, uimm5 ($3), 7);
2820             }
2821           else
2822             return yyerror ("Dregs expected or const value error");
2823         }
2824
2825
2826         | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2827         {
2828           if (IS_DREG ($1) && IS_UIMM ($3, 5))
2829             {
2830               notethat ("LOGI2op: dregs >>>= uimm5\n");
2831               $$ = LOGI2OP ($1, uimm5 ($3), 5);
2832             }
2833           else
2834             return yyerror ("Dregs expected");
2835         }
2836
2837 /* Cache Control.  */
2838
2839         | FLUSH LBRACK REG RBRACK
2840         {
2841           notethat ("CaCTRL: FLUSH [ pregs ]\n");
2842           if (IS_PREG ($3))
2843             $$ = CACTRL (&$3, 0, 2);
2844           else
2845             return yyerror ("Bad register(s) for FLUSH");
2846         }
2847
2848         | FLUSH reg_with_postinc
2849         {
2850           if (IS_PREG ($2))
2851             {
2852               notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2853               $$ = CACTRL (&$2, 1, 2);
2854             }
2855           else
2856             return yyerror ("Bad register(s) for FLUSH");
2857         }
2858
2859         | FLUSHINV LBRACK REG RBRACK
2860         {
2861           if (IS_PREG ($3))
2862             {
2863               notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2864               $$ = CACTRL (&$3, 0, 1);
2865             }
2866           else
2867             return yyerror ("Bad register(s) for FLUSH");
2868         }
2869
2870         | FLUSHINV reg_with_postinc
2871         {
2872           if (IS_PREG ($2))
2873             {
2874               notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2875               $$ = CACTRL (&$2, 1, 1);
2876             }
2877           else
2878             return yyerror ("Bad register(s) for FLUSH");
2879         }
2880
2881 /* CaCTRL:      IFLUSH [pregs].  */
2882         | IFLUSH LBRACK REG RBRACK
2883         {
2884           if (IS_PREG ($3))
2885             {
2886               notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2887               $$ = CACTRL (&$3, 0, 3);
2888             }
2889           else
2890             return yyerror ("Bad register(s) for FLUSH");
2891         }
2892
2893         | IFLUSH reg_with_postinc
2894         {
2895           if (IS_PREG ($2))
2896             {
2897               notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2898               $$ = CACTRL (&$2, 1, 3);
2899             }
2900           else
2901             return yyerror ("Bad register(s) for FLUSH");
2902         }
2903
2904         | PREFETCH LBRACK REG RBRACK
2905         {
2906           if (IS_PREG ($3))
2907             {
2908               notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2909               $$ = CACTRL (&$3, 0, 0);
2910             }
2911           else
2912             return yyerror ("Bad register(s) for PREFETCH");
2913         }
2914
2915         | PREFETCH reg_with_postinc
2916         {
2917           if (IS_PREG ($2))
2918             {
2919               notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2920               $$ = CACTRL (&$2, 1, 0);
2921             }
2922           else
2923             return yyerror ("Bad register(s) for PREFETCH");
2924         }
2925
2926 /* LOAD/STORE.  */
2927 /* LDST:        B [ pregs <post_op> ] = dregs.  */
2928
2929         | B LBRACK REG post_op RBRACK ASSIGN REG
2930         {
2931           if (IS_PREG ($3) && IS_DREG ($7))
2932             {
2933               notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2934               $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2935             }
2936           else
2937             return yyerror ("Register mismatch");
2938         }
2939
2940 /* LDSTidxI:    B [ pregs + imm16 ] = dregs.  */
2941         | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
2942         {
2943           if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 1) && IS_DREG ($8))
2944             {
2945               notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
2946               if ($4.r0)
2947                 neg_value ($5);
2948               $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
2949             }
2950           else
2951             return yyerror ("Register mismatch or const size wrong");
2952         }
2953
2954
2955 /* LDSTii:      W [ pregs + uimm4s2 ] = dregs.  */
2956         | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
2957         {
2958           if (IS_PREG ($3) && IS_URANGE (4, $5, $4.r0, 2) && IS_DREG ($8))
2959             {
2960               notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
2961               $$ = LDSTII (&$3, &$8, $5, 1, 1);
2962             }
2963           else if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 2) && IS_DREG ($8))
2964             {
2965               notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
2966               if ($4.r0)
2967                 neg_value ($5);
2968               $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, $5);
2969             }
2970           else
2971             return yyerror ("Bad register(s) or wrong constant size");
2972         }
2973
2974 /* LDST:        W [ pregs <post_op> ] = dregs.  */
2975         | W LBRACK REG post_op RBRACK ASSIGN REG
2976         {
2977           if (IS_PREG ($3) && IS_DREG ($7))
2978             {
2979               notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
2980               $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
2981             }
2982           else
2983             return yyerror ("Bad register(s) for STORE");
2984         }
2985
2986         | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
2987         {
2988           if (IS_IREG ($3))
2989             {
2990               notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
2991               $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
2992             }
2993           else if ($4.x0 == 2 && IS_PREG ($3) && IS_DREG ($7))
2994             {
2995               notethat ("LDSTpmod: W [ pregs <post_op>] = dregs_half\n");
2996               $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
2997
2998             }
2999           else
3000             return yyerror ("Bad register(s) for STORE");
3001         }
3002
3003 /* LDSTiiFP:    [ FP - const ] = dpregs.  */
3004         | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3005         {
3006           Expr_Node *tmp = $4;
3007           int ispreg = IS_PREG ($7);
3008
3009           if (!IS_PREG ($2))
3010             return yyerror ("Preg expected for indirect");
3011
3012           if (!IS_DREG ($7) && !ispreg)
3013             return yyerror ("Bad source register for STORE");
3014
3015           if ($3.r0)
3016             tmp = unary (Expr_Op_Type_NEG, tmp);
3017
3018           if (in_range_p (tmp, 0, 63, 3))
3019             {
3020               notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3021               $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3022             }
3023           else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3024             {
3025               notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3026               tmp = unary (Expr_Op_Type_NEG, tmp);
3027               $$ = LDSTIIFP (tmp, &$7, 1);
3028             }
3029           else if (in_range_p (tmp, -131072, 131071, 3))
3030             {
3031               notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3032               $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1: 0, tmp);
3033             }
3034           else
3035             return yyerror ("Displacement out of range for store");
3036         }
3037
3038         | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3039         {
3040           if (IS_DREG ($1) && IS_PREG ($5) && IS_URANGE (4, $7, $6.r0, 2))
3041             {
3042               notethat ("LDSTii: dregs = W [ pregs + uimm4s2 ] (.)\n");
3043               $$ = LDSTII (&$5, &$1, $7, 0, 1 << $9.r0);
3044             }
3045           else if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 2))
3046             {
3047               notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3048               if ($6.r0)
3049                 neg_value ($7);
3050               $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, $7);
3051             }
3052           else
3053             return yyerror ("Bad register or constant for LOAD");
3054         }
3055
3056         | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3057         {
3058           if (IS_IREG ($5))
3059             {
3060               notethat ("dspLDST: dregs_half = W [ iregs ]\n");
3061               $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3062             }
3063           else if ($6.x0 == 2 && IS_DREG ($1) && IS_PREG ($5))
3064             {
3065               notethat ("LDSTpmod: dregs_half = W [ pregs ]\n");
3066               $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3067             }
3068           else
3069             return yyerror ("Bad register or post_op for LOAD");
3070         }
3071
3072
3073         | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3074         {
3075           if (IS_DREG ($1) && IS_PREG ($5))
3076             {
3077               notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3078               $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3079             }
3080           else
3081             return yyerror ("Bad register for LOAD");
3082         }
3083
3084         | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3085         {
3086           if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3087             {
3088               notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3089               $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3090             }
3091           else
3092             return yyerror ("Bad register for LOAD");
3093         }
3094
3095         | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3096         {
3097           if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3098             {
3099               notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3100               $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3101             }
3102           else
3103             return yyerror ("Bad register for LOAD");
3104         }
3105
3106         | LBRACK REG post_op RBRACK ASSIGN REG
3107         {
3108           if (IS_IREG ($2) && IS_DREG ($6))
3109             {
3110               notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3111               $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3112             }
3113           else if (IS_PREG ($2) && IS_DREG ($6))
3114             {
3115               notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3116               $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3117             }
3118           else if (IS_PREG ($2) && IS_PREG ($6))
3119             {
3120               notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3121               $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3122             }
3123           else
3124             return yyerror ("Bad register for STORE");
3125         }
3126
3127         | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3128         {
3129           if (! IS_DREG ($7))
3130             return yyerror ("Expected Dreg for last argument");
3131
3132           if (IS_IREG ($2) && IS_MREG ($4))
3133             {
3134               notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3135               $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3136             }
3137           else if (IS_PREG ($2) && IS_PREG ($4))
3138             {
3139               notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3140               $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3141             }
3142           else
3143             return yyerror ("Bad register for STORE");
3144         }
3145
3146         | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3147         {
3148           if (!IS_DREG ($8))
3149             return yyerror ("Expect Dreg as last argument");
3150           if (IS_PREG ($3) && IS_PREG ($5))
3151             {
3152               notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3153               $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3154             }
3155           else
3156             return yyerror ("Bad register for STORE");
3157         }
3158
3159         | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3160         {
3161           if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 1))
3162             {
3163               notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3164                        $9.r0 ? 'X' : 'Z');
3165               if ($6.r0)
3166                 neg_value ($7);
3167               $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, $7);
3168             }
3169           else
3170             return yyerror ("Bad register or value for LOAD");
3171         }
3172
3173         | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3174         {
3175           if (IS_DREG ($1) && IS_PREG ($5))
3176             {
3177               notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3178                        $8.r0 ? 'X' : 'Z');
3179               $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3180             }
3181           else
3182             return yyerror ("Bad register for LOAD");
3183         }
3184
3185         | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3186         {
3187           if (IS_DREG ($1) && IS_IREG ($4) && IS_MREG ($6))
3188             {
3189               notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3190               $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3191             }
3192           else if (IS_DREG ($1) && IS_PREG ($4) && IS_PREG ($6))
3193             {
3194               notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3195               $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3196             }
3197           else
3198             return yyerror ("Bad register for LOAD");
3199         }
3200
3201         | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3202         {
3203           Expr_Node *tmp = $6;
3204           int ispreg = IS_PREG ($1);
3205           int isgot = IS_RELOC($6);
3206
3207           if (!IS_PREG ($4))
3208             return yyerror ("Preg expected for indirect");
3209
3210           if (!IS_DREG ($1) && !ispreg)
3211             return yyerror ("Bad destination register for LOAD");
3212
3213           if ($5.r0)
3214             tmp = unary (Expr_Op_Type_NEG, tmp);
3215
3216           if(isgot){
3217               notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3218               $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3219           }
3220           else if (in_range_p (tmp, 0, 63, 3))
3221             {
3222               notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3223               $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3224             }
3225           else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3226             {
3227               notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3228               tmp = unary (Expr_Op_Type_NEG, tmp);
3229               $$ = LDSTIIFP (tmp, &$1, 0);
3230             }
3231           else if (in_range_p (tmp, -131072, 131071, 3))
3232             {
3233               notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3234               $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3235
3236             }
3237           else
3238             return yyerror ("Displacement out of range for load");
3239         }
3240
3241         | REG ASSIGN LBRACK REG post_op RBRACK
3242         {
3243           if (IS_DREG ($1) && IS_IREG ($4))
3244             {
3245               notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3246               $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3247             }
3248           else if (IS_DREG ($1) && IS_PREG ($4))
3249             {
3250               notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3251               $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3252             }
3253           else if (IS_PREG ($1) && IS_PREG ($4))
3254             {
3255               if (REG_SAME ($1, $4) && $5.x0 != 2)
3256                 return yyerror ("Pregs can't be same");
3257
3258               notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3259               $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3260             }
3261           else if ($4.regno == REG_SP && IS_ALLREG ($1) && $5.x0 == 0)
3262             {
3263               notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3264               $$ = PUSHPOPREG (&$1, 0);
3265             }
3266           else
3267             return yyerror ("Bad register or value");
3268         }
3269
3270
3271 /*  PushPopMultiple.  */
3272         | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3273         {
3274           if ($1.regno != REG_SP)
3275             yyerror ("Stack Pointer expected");
3276           if ($4.regno == REG_R7
3277               && IN_RANGE ($6, 0, 7)
3278               && $8.regno == REG_P5
3279               && IN_RANGE ($10, 0, 5))
3280             {
3281               notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3282               $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3283             }
3284           else
3285             return yyerror ("Bad register for PushPopMultiple");
3286         }
3287
3288         | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3289         {
3290           if ($1.regno != REG_SP)
3291             yyerror ("Stack Pointer expected");
3292
3293           if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3294             {
3295               notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3296               $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3297             }
3298           else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3299             {
3300               notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3301               $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3302             }
3303           else
3304             return yyerror ("Bad register for PushPopMultiple");
3305         }
3306
3307         | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3308         {
3309           if ($11.regno != REG_SP)
3310             yyerror ("Stack Pointer expected");
3311           if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3312               && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3313             {
3314               notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3315               $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3316             }
3317           else
3318             return yyerror ("Bad register range for PushPopMultiple");
3319         }
3320
3321         | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3322         {
3323           if ($7.regno != REG_SP)
3324             yyerror ("Stack Pointer expected");
3325
3326           if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3327             {
3328               notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3329               $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3330             }
3331           else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3332             {
3333               notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3334               $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3335             }
3336           else
3337             return yyerror ("Bad register range for PushPopMultiple");
3338         }
3339
3340         | reg_with_predec ASSIGN REG
3341         {
3342           if ($1.regno != REG_SP)
3343             yyerror ("Stack Pointer expected");
3344
3345           if (IS_ALLREG ($3))
3346             {
3347               notethat ("PushPopReg: [ -- SP ] = allregs\n");
3348               $$ = PUSHPOPREG (&$3, 1);
3349             }
3350           else
3351             return yyerror ("Bad register for PushPopReg");
3352         }
3353
3354 /* Linkage.  */
3355
3356         | LINK expr
3357         {
3358           if (IS_URANGE (16, $2, 0, 4))
3359             $$ = LINKAGE (0, uimm16s4 ($2));
3360           else
3361             return yyerror ("Bad constant for LINK");
3362         }
3363
3364         | UNLINK
3365         {
3366                 notethat ("linkage: UNLINK\n");
3367                 $$ = LINKAGE (1, 0);
3368         }
3369
3370
3371 /* LSETUP.  */
3372
3373         | LSETUP LPAREN expr COMMA expr RPAREN REG
3374         {
3375           if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3376             {
3377               notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3378               $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3379             }
3380           else
3381             return yyerror ("Bad register or values for LSETUP");
3382
3383         }
3384         | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3385         {
3386           if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3387               && IS_PREG ($9) && IS_CREG ($7))
3388             {
3389               notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3390               $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3391             }
3392           else
3393             return yyerror ("Bad register or values for LSETUP");
3394         }
3395
3396         | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3397         {
3398           if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3399               && IS_PREG ($9) && IS_CREG ($7)
3400               && EXPR_VALUE ($11) == 1)
3401             {
3402               notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3403               $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3404             }
3405           else
3406             return yyerror ("Bad register or values for LSETUP");
3407         }
3408
3409 /* LOOP.  */
3410         | LOOP expr REG
3411         {
3412           if (!IS_RELOC ($2))
3413             return yyerror ("Invalid expression in loop statement");
3414           if (!IS_CREG ($3))
3415             return yyerror ("Invalid loop counter register");
3416         $$ = bfin_gen_loop ($2, &$3, 0, 0);
3417         }
3418         | LOOP expr REG ASSIGN REG
3419         {
3420           if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3421             {
3422               notethat ("Loop: LOOP expr counters = pregs\n");
3423               $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3424             }
3425           else
3426             return yyerror ("Bad register or values for LOOP");
3427         }
3428         | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3429         {
3430           if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3431             {
3432               notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3433               $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3434             }
3435           else
3436             return yyerror ("Bad register or values for LOOP");
3437         }
3438 /* pseudoDEBUG.  */
3439
3440         | DBG
3441         {
3442           notethat ("pseudoDEBUG: DBG\n");
3443           $$ = bfin_gen_pseudodbg (3, 7, 0);
3444         }
3445         | DBG REG_A
3446         {
3447           notethat ("pseudoDEBUG: DBG REG_A\n");
3448           $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3449         }
3450         | DBG REG
3451         {
3452           notethat ("pseudoDEBUG: DBG allregs\n");
3453           $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, $2.regno & CLASS_MASK);
3454         }
3455
3456         | DBGCMPLX LPAREN REG RPAREN
3457         {
3458           if (!IS_DREG ($3))
3459             return yyerror ("Dregs expected");
3460           notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3461           $$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
3462         }
3463
3464         | DBGHALT
3465         {
3466           notethat ("psedoDEBUG: DBGHALT\n");
3467           $$ = bfin_gen_pseudodbg (3, 5, 0);
3468         }
3469
3470         | DBGA LPAREN HALF_REG COMMA expr RPAREN
3471         {
3472           notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
3473           $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3474         }
3475
3476         | DBGAH LPAREN REG COMMA expr RPAREN
3477         {
3478           notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
3479           $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3480         }
3481
3482         | DBGAL LPAREN REG COMMA expr RPAREN
3483         {
3484           notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
3485           $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3486         }
3487
3488
3489 ;
3490
3491 /*  AUX RULES.  */
3492
3493 /*  Register rules.  */
3494
3495 REG_A:  REG_A_DOUBLE_ZERO
3496         {
3497         $$ = $1;
3498         }
3499         | REG_A_DOUBLE_ONE
3500         {
3501         $$ = $1;
3502         }
3503         ;
3504
3505
3506 /*  Modifiers. */
3507
3508 opt_mode:
3509         {
3510         $$.MM = 0;
3511         $$.mod = 0;
3512         }
3513         | LPAREN M COMMA MMOD RPAREN
3514         {
3515         $$.MM = 1;
3516         $$.mod = $4;
3517         }
3518         | LPAREN MMOD COMMA M RPAREN
3519         {
3520         $$.MM = 1;
3521         $$.mod = $2;
3522         }
3523         | LPAREN MMOD RPAREN
3524         {
3525         $$.MM = 0;
3526         $$.mod = $2;
3527         }
3528         | LPAREN M RPAREN
3529         {
3530         $$.MM = 1;
3531         $$.mod = 0;
3532         }
3533         ;
3534
3535 asr_asl: LPAREN ASL RPAREN
3536         {
3537         $$.r0 = 1;
3538         }
3539         | LPAREN ASR RPAREN
3540         {
3541         $$.r0 = 0;
3542         }
3543         ;
3544
3545 sco:
3546         {
3547         $$.s0 = 0;
3548         $$.x0 = 0;
3549         }
3550         | S
3551         {
3552         $$.s0 = 1;
3553         $$.x0 = 0;
3554         }
3555         | CO
3556         {
3557         $$.s0 = 0;
3558         $$.x0 = 1;
3559         }
3560         | SCO
3561         {
3562         $$.s0 = 1;
3563         $$.x0 = 1;
3564         }
3565         ;
3566
3567 asr_asl_0:
3568         ASL
3569         {
3570         $$.r0 = 1;
3571         }
3572         | ASR
3573         {
3574         $$.r0 = 0;
3575         }
3576         ;
3577
3578 amod0:
3579         {
3580         $$.s0 = 0;
3581         $$.x0 = 0;
3582         }
3583         | LPAREN sco RPAREN
3584         {
3585         $$.s0 = $2.s0;
3586         $$.x0 = $2.x0;
3587         }
3588         ;
3589
3590 amod1:
3591         {
3592         $$.s0 = 0;
3593         $$.x0 = 0;
3594         $$.aop = 0;
3595         }
3596         | LPAREN NS RPAREN
3597         {
3598         $$.s0 = 0;
3599         $$.x0 = 0;
3600         $$.aop = 1;
3601         }
3602         | LPAREN S RPAREN
3603         {
3604         $$.s0 = 1;
3605         $$.x0 = 0;
3606         $$.aop = 1;
3607         }
3608         ;
3609
3610 amod2:
3611         {
3612         $$.r0 = 0;
3613         $$.s0 = 0;
3614         $$.x0 = 0;
3615         }
3616         | LPAREN asr_asl_0 RPAREN
3617         {
3618         $$.r0 = 2 + $2.r0;
3619         $$.s0 = 0;
3620         $$.x0 = 0;
3621         }
3622         | LPAREN sco RPAREN
3623         {
3624         $$.r0 = 0;
3625         $$.s0 = $2.s0;
3626         $$.x0 = $2.x0;
3627         }
3628         | LPAREN asr_asl_0 COMMA sco RPAREN
3629         {
3630         $$.r0 = 2 + $2.r0;
3631         $$.s0 = $4.s0;
3632         $$.x0 = $4.x0;
3633         }
3634         | LPAREN sco COMMA asr_asl_0 RPAREN
3635         {
3636         $$.r0 = 2 + $4.r0;
3637         $$.s0 = $2.s0;
3638         $$.x0 = $2.x0;
3639         }
3640         ;
3641
3642 xpmod:
3643         {
3644         $$.r0 = 0;
3645         }
3646         | LPAREN Z RPAREN
3647         {
3648         $$.r0 = 0;
3649         }
3650         | LPAREN X RPAREN
3651         {
3652         $$.r0 = 1;
3653         }
3654         ;
3655
3656 xpmod1:
3657         {
3658         $$.r0 = 0;
3659         }
3660         | LPAREN X RPAREN
3661         {
3662         $$.r0 = 0;
3663         }
3664         | LPAREN Z RPAREN
3665         {
3666         $$.r0 = 1;
3667         }
3668         ;
3669
3670 vsmod:
3671         {
3672         $$.r0 = 0;
3673         $$.s0 = 0;
3674         $$.aop = 0;
3675         }
3676         | LPAREN NS RPAREN
3677         {
3678         $$.r0 = 0;
3679         $$.s0 = 0;
3680         $$.aop = 3;
3681         }
3682         | LPAREN S RPAREN
3683         {
3684         $$.r0 = 0;
3685         $$.s0 = 1;
3686         $$.aop = 3;
3687         }
3688         | LPAREN V RPAREN
3689         {
3690         $$.r0 = 1;
3691         $$.s0 = 0;
3692         $$.aop = 3;
3693         }
3694         | LPAREN V COMMA S RPAREN
3695         {
3696         $$.r0 = 1;
3697         $$.s0 = 1;
3698         }
3699         | LPAREN S COMMA V RPAREN
3700         {
3701         $$.r0 = 1;
3702         $$.s0 = 1;
3703         }
3704         ;
3705
3706 vmod:
3707         {
3708         $$.r0 = 0;
3709         }
3710         | LPAREN V RPAREN
3711         {
3712         $$.r0 = 1;
3713         }
3714         ;
3715
3716 smod:
3717         {
3718         $$.s0 = 0;
3719         }
3720         | LPAREN S RPAREN
3721         {
3722         $$.s0 = 1;
3723         }
3724         ;
3725
3726 searchmod:
3727           GE
3728         {
3729         $$.r0 = 1;
3730         }
3731         | GT
3732         {
3733         $$.r0 = 0;
3734         }
3735         | LE
3736         {
3737         $$.r0 = 3;
3738         }
3739         | LT
3740         {
3741         $$.r0 = 2;
3742         }
3743         ;
3744
3745 aligndir:
3746         {
3747         $$.r0 = 0;
3748         }
3749         | LPAREN R RPAREN
3750         {
3751         $$.r0 = 1;
3752         }
3753         ;
3754
3755 byteop_mod:
3756         LPAREN R RPAREN
3757         {
3758         $$.r0 = 0;
3759         $$.s0 = 1;
3760         }
3761         | LPAREN MMOD RPAREN
3762         {
3763         if ($2 != M_T)
3764           return yyerror ("Bad modifier");
3765         $$.r0 = 1;
3766         $$.s0 = 0;
3767         }
3768         | LPAREN MMOD COMMA R RPAREN
3769         {
3770         if ($2 != M_T)
3771           return yyerror ("Bad modifier");
3772         $$.r0 = 1;
3773         $$.s0 = 1;
3774         }
3775         | LPAREN R COMMA MMOD RPAREN
3776         {
3777         if ($4 != M_T)
3778           return yyerror ("Bad modifier");
3779         $$.r0 = 1;
3780         $$.s0 = 1;
3781         }
3782         ;
3783
3784
3785
3786 c_align:
3787         ALIGN8
3788         {
3789         $$.r0 = 0;
3790         }
3791         | ALIGN16
3792         {
3793         $$.r0 = 1;
3794         }
3795         | ALIGN24
3796         {
3797         $$.r0 = 2;
3798         }
3799         ;
3800
3801 w32_or_nothing:
3802         {
3803         $$.r0 = 0;
3804         }
3805         | LPAREN MMOD RPAREN
3806         {
3807           if ($2 == M_W32)
3808             $$.r0 = 1;
3809           else
3810             return yyerror ("Only (W32) allowed");
3811         }
3812         ;
3813
3814 iu_or_nothing:
3815         {
3816         $$.r0 = 1;
3817         }
3818         | LPAREN MMOD RPAREN
3819         {
3820           if ($2 == M_IU)
3821             $$.r0 = 3;
3822           else
3823             return yyerror ("(IU) expected");
3824         }
3825         ;
3826
3827 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
3828         {
3829         $$ = $3;
3830         }
3831         ;
3832
3833 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
3834         {
3835         $$ = $2;
3836         }
3837         ;
3838
3839 /* Operators.  */
3840
3841 min_max:
3842         MIN
3843         {
3844         $$.r0 = 1;
3845         }
3846         | MAX
3847         {
3848         $$.r0 = 0;
3849         }
3850         ;
3851
3852 op_bar_op:
3853         _PLUS_BAR_PLUS
3854         {
3855         $$.r0 = 0;
3856         }
3857         | _PLUS_BAR_MINUS
3858         {
3859         $$.r0 = 1;
3860         }
3861         | _MINUS_BAR_PLUS
3862         {
3863         $$.r0 = 2;
3864         }
3865         | _MINUS_BAR_MINUS
3866         {
3867         $$.r0 = 3;
3868         }
3869         ;
3870
3871 plus_minus:
3872         PLUS
3873         {
3874         $$.r0 = 0;
3875         }
3876         | MINUS
3877         {
3878         $$.r0 = 1;
3879         }
3880         ;
3881
3882 rnd_op:
3883         LPAREN RNDH RPAREN
3884         {
3885           $$.r0 = 1;    /* HL.  */
3886           $$.s0 = 0;    /* s.  */
3887           $$.x0 = 0;    /* x.  */
3888           $$.aop = 0;   /* aop.  */
3889         }
3890
3891         | LPAREN TH RPAREN
3892         {
3893           $$.r0 = 1;    /* HL.  */
3894           $$.s0 = 0;    /* s.  */
3895           $$.x0 = 0;    /* x.  */
3896           $$.aop = 1;   /* aop.  */
3897         }
3898
3899         | LPAREN RNDL RPAREN
3900         {
3901           $$.r0 = 0;    /* HL.  */
3902           $$.s0 = 0;    /* s.  */
3903           $$.x0 = 0;    /* x.  */
3904           $$.aop = 0;   /* aop.  */
3905         }
3906
3907         | LPAREN TL RPAREN
3908         {
3909           $$.r0 = 0;    /* HL.  */
3910           $$.s0 = 0;    /* s.  */
3911           $$.x0 = 0;    /* x.  */
3912           $$.aop = 1;
3913         }
3914
3915         | LPAREN RNDH COMMA R RPAREN
3916         {
3917           $$.r0 = 1;    /* HL.  */
3918           $$.s0 = 1;    /* s.  */
3919           $$.x0 = 0;    /* x.  */
3920           $$.aop = 0;   /* aop.  */
3921         }
3922         | LPAREN TH COMMA R RPAREN
3923         {
3924           $$.r0 = 1;    /* HL.  */
3925           $$.s0 = 1;    /* s.  */
3926           $$.x0 = 0;    /* x.  */
3927           $$.aop = 1;   /* aop.  */
3928         }
3929         | LPAREN RNDL COMMA R RPAREN
3930         {
3931           $$.r0 = 0;    /* HL.  */
3932           $$.s0 = 1;    /* s.  */
3933           $$.x0 = 0;    /* x.  */
3934           $$.aop = 0;   /* aop.  */
3935         }
3936
3937         | LPAREN TL COMMA R RPAREN
3938         {
3939           $$.r0 = 0;    /* HL.  */
3940           $$.s0 = 1;    /* s.  */
3941           $$.x0 = 0;    /* x.  */
3942           $$.aop = 1;   /* aop.  */
3943         }
3944         ;
3945
3946 b3_op:
3947         LPAREN LO RPAREN
3948         {
3949           $$.s0 = 0;    /* s.  */
3950           $$.x0 = 0;    /* HL.  */
3951         }
3952         | LPAREN HI RPAREN
3953         {
3954           $$.s0 = 0;    /* s.  */
3955           $$.x0 = 1;    /* HL.  */
3956         }
3957         | LPAREN LO COMMA R RPAREN
3958         {
3959           $$.s0 = 1;    /* s.  */
3960           $$.x0 = 0;    /* HL.  */
3961         }
3962         | LPAREN HI COMMA R RPAREN
3963         {
3964           $$.s0 = 1;    /* s.  */
3965           $$.x0 = 1;    /* HL.  */
3966         }
3967         ;
3968
3969 post_op:
3970         {
3971         $$.x0 = 2;
3972         }
3973         | _PLUS_PLUS
3974         {
3975         $$.x0 = 0;
3976         }
3977         | _MINUS_MINUS
3978         {
3979         $$.x0 = 1;
3980         }
3981         ;
3982
3983 /* Assignments, Macfuncs.  */
3984
3985 a_assign:
3986         REG_A ASSIGN
3987         {
3988         $$ = $1;
3989         }
3990         ;
3991
3992 a_minusassign:
3993         REG_A _MINUS_ASSIGN
3994         {
3995         $$ = $1;
3996         }
3997         ;
3998
3999 a_plusassign:
4000         REG_A _PLUS_ASSIGN
4001         {
4002         $$ = $1;
4003         }
4004         ;
4005
4006 assign_macfunc:
4007         REG ASSIGN REG_A
4008         {
4009           $$.w = 1;
4010           $$.P = 1;
4011           $$.n = IS_A1 ($3);
4012           $$.op = 3;
4013           $$.dst = $1;
4014           $$.s0.regno = 0;
4015           $$.s1.regno = 0;
4016
4017           if (IS_A1 ($3) && IS_EVEN ($1))
4018             return yyerror ("Cannot move A1 to even register");
4019           else if (!IS_A1 ($3) && !IS_EVEN ($1))
4020             return yyerror ("Cannot move A0 to odd register");
4021         }
4022         | a_macfunc
4023         {
4024           $$ = $1;
4025           $$.w = 0; $$.P = 0;
4026           $$.dst.regno = 0;
4027         }
4028         | REG ASSIGN LPAREN a_macfunc RPAREN
4029         {
4030           $$ = $4;
4031           $$.w = 1;
4032           $$.P = 1;
4033           $$.dst = $1;
4034         }
4035
4036         | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4037         {
4038           $$ = $4;
4039           $$.w = 1;
4040           $$.P = 0;
4041           $$.dst = $1;
4042         }
4043
4044         | HALF_REG ASSIGN REG_A
4045         {
4046           $$.w = 1;
4047           $$.P = 0;
4048           $$.n = IS_A1 ($3);
4049           $$.op = 3;
4050           $$.dst = $1;
4051           $$.s0.regno = 0;
4052           $$.s1.regno = 0;
4053
4054           if (IS_A1 ($3) && !IS_H ($1))
4055             return yyerror ("Cannot move A1 to low half of register");
4056           else if (!IS_A1 ($3) && IS_H ($1))
4057             return yyerror ("Cannot move A0 to high half of register");
4058         }
4059         ;
4060
4061 a_macfunc:
4062         a_assign multiply_halfregs
4063         {
4064           $$.n = IS_A1 ($1);
4065           $$.op = 0;
4066           $$.s0 = $2.s0;
4067           $$.s1 = $2.s1;
4068         }
4069         | a_plusassign multiply_halfregs
4070         {
4071           $$.n = IS_A1 ($1);
4072           $$.op = 1;
4073           $$.s0 = $2.s0;
4074           $$.s1 = $2.s1;
4075         }
4076         | a_minusassign multiply_halfregs
4077         {
4078           $$.n = IS_A1 ($1);
4079           $$.op = 2;
4080           $$.s0 = $2.s0;
4081           $$.s1 = $2.s1;
4082         }
4083         ;
4084
4085 multiply_halfregs:
4086         HALF_REG STAR HALF_REG
4087         {
4088           if (IS_DREG ($1) && IS_DREG ($3))
4089             {
4090               $$.s0 = $1;
4091               $$.s1 = $3;
4092             }
4093           else
4094             return yyerror ("Dregs expected");
4095         }
4096         ;
4097
4098 cc_op:
4099         ASSIGN
4100         {
4101         $$.r0 = 0;
4102         }
4103         | _BAR_ASSIGN
4104         {
4105         $$.r0 = 1;
4106         }
4107         | _AMPERSAND_ASSIGN
4108         {
4109         $$.r0 = 2;
4110         }
4111         | _CARET_ASSIGN
4112         {
4113         $$.r0 = 3;
4114         }
4115         ;
4116
4117 ccstat:
4118         CCREG cc_op STATUS_REG
4119         {
4120         $$.r0 = $3.regno;
4121         $$.x0 = $2.r0;
4122         $$.s0 = 0;
4123         }
4124         | CCREG cc_op V
4125         {
4126         $$.r0 = 0x18;
4127         $$.x0 = $2.r0;
4128         $$.s0 = 0;
4129         }
4130         | STATUS_REG cc_op CCREG
4131         {
4132         $$.r0 = $1.regno;
4133         $$.x0 = $2.r0;
4134         $$.s0 = 1;
4135         }
4136         | V cc_op CCREG
4137         {
4138         $$.r0 = 0x18;
4139         $$.x0 = $2.r0;
4140         $$.s0 = 1;
4141         }
4142         ;
4143
4144 /* Expressions and Symbols.  */
4145
4146 symbol: SYMBOL
4147         {
4148         Expr_Node_Value val;
4149         val.s_value = S_GET_NAME($1);
4150         $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4151         }
4152         ;
4153
4154 any_gotrel:
4155         GOT
4156         { $$ = BFD_RELOC_BFIN_GOT; }
4157         | GOT17M4
4158         { $$ = BFD_RELOC_BFIN_GOT17M4; }
4159         | FUNCDESC_GOT17M4
4160         { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4161         ;
4162
4163 got:    symbol AT any_gotrel
4164         {
4165         Expr_Node_Value val;
4166         val.i_value = $3;
4167         $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4168         }
4169         ;
4170
4171 got_or_expr:    got
4172         {
4173         $$ = $1;
4174         }
4175         | expr
4176         {
4177         $$ = $1;
4178         }
4179         ;
4180
4181 pltpc :
4182         symbol AT PLTPC
4183         {
4184         $$ = $1;
4185         }
4186         ;
4187
4188 eterm: NUMBER
4189         {
4190         Expr_Node_Value val;
4191         val.i_value = $1;
4192         $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4193         }
4194         | symbol
4195         {
4196         $$ = $1;
4197         }
4198         | LPAREN expr_1 RPAREN
4199         {
4200         $$ = $2;
4201         }
4202         | TILDA expr_1
4203         {
4204         $$ = unary (Expr_Op_Type_COMP, $2);
4205         }
4206         | MINUS expr_1 %prec TILDA
4207         {
4208         $$ = unary (Expr_Op_Type_NEG, $2);
4209         }
4210         ;
4211
4212 expr: expr_1
4213         {
4214         $$ = $1;
4215         }
4216         ;
4217
4218 expr_1: expr_1 STAR expr_1
4219         {
4220         $$ = binary (Expr_Op_Type_Mult, $1, $3);
4221         }
4222         | expr_1 SLASH expr_1
4223         {
4224         $$ = binary (Expr_Op_Type_Div, $1, $3);
4225         }
4226         | expr_1 PERCENT expr_1
4227         {
4228         $$ = binary (Expr_Op_Type_Mod, $1, $3);
4229         }
4230         | expr_1 PLUS expr_1
4231         {
4232         $$ = binary (Expr_Op_Type_Add, $1, $3);
4233         }
4234         | expr_1 MINUS expr_1
4235         {
4236         $$ = binary (Expr_Op_Type_Sub, $1, $3);
4237         }
4238         | expr_1 LESS_LESS expr_1
4239         {
4240         $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4241         }
4242         | expr_1 GREATER_GREATER expr_1
4243         {
4244         $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4245         }
4246         | expr_1 AMPERSAND expr_1
4247         {
4248         $$ = binary (Expr_Op_Type_BAND, $1, $3);
4249         }
4250         | expr_1 CARET expr_1
4251         {
4252         $$ = binary (Expr_Op_Type_LOR, $1, $3);
4253         }
4254         | expr_1 BAR expr_1
4255         {
4256         $$ = binary (Expr_Op_Type_BOR, $1, $3);
4257         }
4258         | eterm
4259         {
4260         $$ = $1;
4261         }
4262         ;
4263
4264
4265 %%
4266
4267 EXPR_T
4268 mkexpr (int x, SYMBOL_T s)
4269 {
4270   EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4271   e->value = x;
4272   EXPR_SYMBOL(e) = s;
4273   return e;
4274 }
4275
4276 static int
4277 value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
4278 {
4279   long umax = (1L << sz) - 1;
4280   long min = -1L << (sz - 1);
4281   long max = (1L << (sz - 1)) - 1;
4282
4283   long v = EXPR_VALUE (expr);
4284
4285   if ((v % mul) != 0)
4286     {
4287       error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4288       return 0;
4289     }
4290
4291   v /= mul;
4292
4293   if (sign)
4294     v = -v;
4295
4296   if (issigned)
4297     {
4298       if (v >= min && v <= max) return 1;
4299
4300 #ifdef DEBUG
4301       fprintf(stderr, "signed value %lx out of range\n", v * mul);
4302 #endif
4303       return 0;
4304     }
4305   if (v <= umax && v >= 0)
4306     return 1;
4307 #ifdef DEBUG
4308   fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4309 #endif
4310   return 0;
4311 }
4312
4313 /* Return the expression structure that allows symbol operations.
4314    If the left and right children are constants, do the operation.  */
4315 static Expr_Node *
4316 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4317 {
4318   Expr_Node_Value val;
4319
4320   if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4321     {
4322       switch (op)
4323         {
4324         case Expr_Op_Type_Add:
4325           x->value.i_value += y->value.i_value;
4326           break;
4327         case Expr_Op_Type_Sub:
4328           x->value.i_value -= y->value.i_value;
4329           break;
4330         case Expr_Op_Type_Mult:
4331           x->value.i_value *= y->value.i_value;
4332           break;
4333         case Expr_Op_Type_Div:
4334           if (y->value.i_value == 0)
4335             error ("Illegal Expression:  Division by zero.");
4336           else
4337             x->value.i_value /= y->value.i_value;
4338           break;
4339         case Expr_Op_Type_Mod:
4340           x->value.i_value %= y->value.i_value;
4341           break;
4342         case Expr_Op_Type_Lshift:
4343           x->value.i_value <<= y->value.i_value;
4344           break;
4345         case Expr_Op_Type_Rshift:
4346           x->value.i_value >>= y->value.i_value;
4347           break;
4348         case Expr_Op_Type_BAND:
4349           x->value.i_value &= y->value.i_value;
4350           break;
4351         case Expr_Op_Type_BOR:
4352           x->value.i_value |= y->value.i_value;
4353           break;
4354         case Expr_Op_Type_BXOR:
4355           x->value.i_value ^= y->value.i_value;
4356           break;
4357         case Expr_Op_Type_LAND:
4358           x->value.i_value = x->value.i_value && y->value.i_value;
4359           break;
4360         case Expr_Op_Type_LOR:
4361           x->value.i_value = x->value.i_value || y->value.i_value;
4362           break;
4363
4364         default:
4365           error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__);
4366         }
4367       return x;
4368     }
4369   /* Canonicalize order to EXPR OP CONSTANT.  */
4370   if (x->type == Expr_Node_Constant)
4371     {
4372       Expr_Node *t = x;
4373       x = y;
4374       y = t;
4375     }
4376   /* Canonicalize subtraction of const to addition of negated const.  */
4377   if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4378     {
4379       op = Expr_Op_Type_Add;
4380       y->value.i_value = -y->value.i_value;
4381     }
4382   if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4383       && x->Right_Child->type == Expr_Node_Constant)
4384     {
4385       if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4386         {
4387           x->Right_Child->value.i_value += y->value.i_value;
4388           return x;
4389         }
4390     }
4391
4392   /* Create a new expression structure.  */
4393   val.op_value = op;
4394   return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4395 }
4396
4397 static Expr_Node *
4398 unary (Expr_Op_Type op, Expr_Node *x)
4399 {
4400   if (x->type == Expr_Node_Constant)
4401     {
4402       switch (op)
4403         {
4404         case Expr_Op_Type_NEG:
4405           x->value.i_value = -x->value.i_value;
4406           break;
4407         case Expr_Op_Type_COMP:
4408           x->value.i_value = ~x->value.i_value;
4409           break;
4410         default:
4411           error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__);
4412         }
4413       return x;
4414     }
4415   else
4416     {
4417       /* Create a new expression structure.  */
4418       Expr_Node_Value val;
4419       val.op_value = op;
4420       return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4421     }
4422 }
4423
4424 int debug_codeselection = 0;
4425 static void
4426 notethat (char *format, ...)
4427 {
4428   va_list ap;
4429   va_start (ap, format);
4430   if (debug_codeselection)
4431     {
4432       vfprintf (errorf, format, ap);
4433     }
4434   va_end (ap);
4435 }
4436
4437 #ifdef TEST
4438 main (int argc, char **argv)
4439 {
4440   yyparse();
4441 }
4442 #endif
4443