gas/config/m68k-parse.h

   1 /* m68k-parse.h -- header file for m68k assembler
   2    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
   3    2003, 2004 Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 #ifndef M68K_PARSE_H
  23 #define M68K_PARSE_H
  24
  25 /* This header file defines things which are shared between the
  26    operand parser in m68k.y and the m68k assembler proper in
  27    tc-m68k.c.  */
  28
  29 /* The various m68k registers.  */
  30
  31 /* DATA and ADDR have to be contiguous, so that reg-DATA gives
  32    0-7==data reg, 8-15==addr reg for operands that take both types.
  33
  34    We don't use forms like "ADDR0 = ADDR" here because this file is
  35    likely to be used on an Apollo, and the broken Apollo compiler
  36    gives an `undefined variable' error if we do that, according to
  37    troy@cbme.unsw.edu.au.  */
  38
  39 #define DATA DATA0
  40 #define ADDR ADDR0
  41 #define SP ADDR7
  42 #define BAD BAD0
  43 #define BAC BAC0
  44
  45 enum m68k_register
  46 {
  47   DATA0 = 1,                    /*   1- 8 == data registers 0-7 */
  48   DATA1,
  49   DATA2,
  50   DATA3,
  51   DATA4,
  52   DATA5,
  53   DATA6,
  54   DATA7,
  55
  56   ADDR0,
  57   ADDR1,
  58   ADDR2,
  59   ADDR3,
  60   ADDR4,
  61   ADDR5,
  62   ADDR6,
  63   ADDR7,
  64
  65   FP0,                          /* Eight FP registers */
  66   FP1,
  67   FP2,
  68   FP3,
  69   FP4,
  70   FP5,
  71   FP6,
  72   FP7,
  73
  74   COP0,                         /* Co-processor #0-#7 */
  75   COP1,
  76   COP2,
  77   COP3,
  78   COP4,
  79   COP5,
  80   COP6,
  81   COP7,
  82
  83   PC,                           /* Program counter */
  84   ZPC,                          /* Hack for Program space, but 0 addressing */
  85   SR,                           /* Status Reg */
  86   CCR,                          /* Condition code Reg */
  87   ACC,                          /* Accumulator Reg0 (EMAC or ACC on MAC).  */
  88   ACC1,                         /* Accumulator Reg 1 (EMAC).  */
  89   ACC2,                         /* Accumulator Reg 2 (EMAC).  */
  90   ACC3,                         /* Accumulator Reg 3 (EMAC).  */
  91   ACCEXT01,                     /* Accumulator extension 0&1 (EMAC).  */
  92   ACCEXT23,                     /* Accumulator extension 2&3 (EMAC).  */
  93   MACSR,                        /* MAC Status Reg */
  94   MASK,                         /* Modulus Reg */
  95
  96   /* These have to be grouped together for the movec instruction to work.  */
  97   USP,                          /*  User Stack Pointer */
  98   ISP,                          /*  Interrupt stack pointer */
  99   SFC,
 100   DFC,
 101   CACR,
 102   VBR,
 103   CAAR,
 104   MSP,
 105   ITT0,
 106   ITT1,
 107   DTT0,
 108   DTT1,
 109   MMUSR,
 110   TC,
 111   SRP,
 112   URP,
 113   BUSCR,                        /* 68060 added these.  */
 114   PCR,
 115   ROMBAR,                       /* mcf5200 added these.  */
 116   RAMBAR0,
 117   RAMBAR1,
 118   MMUBAR,                       /* mcfv4e added these.  */
 119   ROMBAR1,                      /* mcfv4e added these.  */
 120   MPCR, EDRAMBAR, SECMBAR,      /* mcfv4e added these.  */
 121   PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these.  */
 122   PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these.  */
 123   PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these.  */
 124   MBAR0, MBAR1,                 /* mcfv4e added these.  */
 125   ACR0, ACR1, ACR2, ACR3,       /* mcf5200 added these.  */
 126   FLASHBAR, RAMBAR,             /* mcf528x added these.  */
 127   MBAR2,                        /* mcf5249 added this.  */
 128   MBAR,
 129 #define last_movec_reg MBAR
 130   /* End of movec ordering constraints.  */
 131
 132   FPI,
 133   FPS,
 134   FPC,
 135
 136   DRP,                          /* 68851 or 68030 MMU regs */
 137   CRP,
 138   CAL,
 139   VAL,
 140   SCC,
 141   AC,
 142   BAD0,
 143   BAD1,
 144   BAD2,
 145   BAD3,
 146   BAD4,
 147   BAD5,
 148   BAD6,
 149   BAD7,
 150   BAC0,
 151   BAC1,
 152   BAC2,
 153   BAC3,
 154   BAC4,
 155   BAC5,
 156   BAC6,
 157   BAC7,
 158   PSR,                          /* aka MMUSR on 68030 (but not MMUSR on 68040)
 159                                    and ACUSR on 68ec030 */
 160   PCSR,
 161
 162   IC,                           /* instruction cache token */
 163   DC,                           /* data cache token */
 164   NC,                           /* no cache token */
 165   BC,                           /* both caches token */
 166
 167   TT0,                          /* 68030 access control unit regs */
 168   TT1,
 169
 170   ZDATA0,                       /* suppressed data registers.  */
 171   ZDATA1,
 172   ZDATA2,
 173   ZDATA3,
 174   ZDATA4,
 175   ZDATA5,
 176   ZDATA6,
 177   ZDATA7,
 178
 179   ZADDR0,                       /* suppressed address registers.  */
 180   ZADDR1,
 181   ZADDR2,
 182   ZADDR3,
 183   ZADDR4,
 184   ZADDR5,
 185   ZADDR6,
 186   ZADDR7,
 187
 188   /* Upper and lower half of data and address registers.  Order *must*
 189      be DATAxL, ADDRxL, DATAxU, ADDRxU.  */
 190   DATA0L,                       /* lower half of data registers */
 191   DATA1L,
 192   DATA2L,
 193   DATA3L,
 194   DATA4L,
 195   DATA5L,
 196   DATA6L,
 197   DATA7L,
 198
 199   ADDR0L,                       /* lower half of address registers */
 200   ADDR1L,
 201   ADDR2L,
 202   ADDR3L,
 203   ADDR4L,
 204   ADDR5L,
 205   ADDR6L,
 206   ADDR7L,
 207
 208   DATA0U,                       /* upper half of data registers */
 209   DATA1U,
 210   DATA2U,
 211   DATA3U,
 212   DATA4U,
 213   DATA5U,
 214   DATA6U,
 215   DATA7U,
 216
 217   ADDR0U,                       /* upper half of address registers */
 218   ADDR1U,
 219   ADDR2U,
 220   ADDR3U,
 221   ADDR4U,
 222   ADDR5U,
 223   ADDR6U,
 224   ADDR7U,
 225 };
 226
 227 /* Size information.  */
 228
 229 enum m68k_size
 230 {
 231   /* Unspecified.  */
 232   SIZE_UNSPEC,
 233
 234   /* Byte.  */
 235   SIZE_BYTE,
 236
 237   /* Word (2 bytes).  */
 238   SIZE_WORD,
 239
 240   /* Longword (4 bytes).  */
 241   SIZE_LONG
 242 };
 243
 244 /* The structure used to hold information about an index register.  */
 245
 246 struct m68k_indexreg
 247 {
 248   /* The index register itself.  */
 249   enum m68k_register reg;
 250
 251   /* The size to use.  */
 252   enum m68k_size size;
 253
 254   /* The value to scale by.  */
 255   int scale;
 256 };
 257
 258 #ifdef OBJ_ELF
 259 /* The type of a PIC expression.  */
 260
 261 enum pic_relocation
 262 {
 263   pic_none,                     /* not pic */
 264   pic_plt_pcrel,                /* @PLTPC */
 265   pic_got_pcrel,                /* @GOTPC */
 266   pic_plt_off,                  /* @PLT */
 267   pic_got_off                   /* @GOT */
 268 };
 269 #endif
 270
 271 /* The structure used to hold information about an expression.  */
 272
 273 struct m68k_exp
 274 {
 275   /* The size to use.  */
 276   enum m68k_size size;
 277
 278 #ifdef OBJ_ELF
 279   /* The type of pic relocation if any.  */
 280   enum pic_relocation pic_reloc;
 281 #endif
 282
 283   /* The expression itself.  */
 284   expressionS exp;
 285 };
 286
 287 /* The operand modes.  */
 288
 289 enum m68k_operand_type
 290 {
 291   IMMED = 1,
 292   ABSL,
 293   DREG,
 294   AREG,
 295   FPREG,
 296   CONTROL,
 297   AINDR,
 298   AINC,
 299   ADEC,
 300   DISP,
 301   BASE,
 302   POST,
 303   PRE,
 304   LSH,  /* MAC/EMAC scalefactor '<<'.  */
 305   RSH,  /* MAC/EMAC scalefactor '>>'.  */
 306   REGLST
 307 };
 308
 309 /* The structure used to hold a parsed operand.  */
 310
 311 struct m68k_op
 312 {
 313   /* The type of operand.  */
 314   enum m68k_operand_type mode;
 315
 316   /* The main register.  */
 317   enum m68k_register reg;
 318
 319   /* The register mask for mode REGLST.  */
 320   unsigned long mask;
 321
 322   /* An error message.  */
 323   const char *error;
 324
 325   /* The index register.  */
 326   struct m68k_indexreg index;
 327
 328   /* The displacement.  */
 329   struct m68k_exp disp;
 330
 331   /* The outer displacement.  */
 332   struct m68k_exp odisp;
 333
 334   /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing).  */
 335   int trailing_ampersand;
 336 };
 337
 338 #endif /* ! defined (M68K_PARSE_H) */
 339
 340 /* The parsing function.  */
 341
 342 extern int m68k_ip_op PARAMS ((char *, struct m68k_op *));
 343
 344 /* Whether register prefixes are optional.  */
 345 extern int flag_reg_prefix_optional;