1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in neon_type_el. */
91 #define NTA_HASINDEX 2
95 enum neon_el_type type
;
96 unsigned char defined
;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type
;
108 enum aarch64_opnd opnd
;
110 unsigned need_libopcodes_p
: 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind
;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool
: 1;
131 typedef struct aarch64_instruction aarch64_instruction
;
133 static aarch64_instruction inst
;
135 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
136 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
159 inst
.parsing_error
.error
= NULL
;
162 static inline bfd_boolean
165 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
168 static inline const char *
169 get_error_message (void)
171 return inst
.parsing_error
.error
;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst
.parsing_error
.kind
;
181 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
183 inst
.parsing_error
.kind
= kind
;
184 inst
.parsing_error
.error
= error
;
188 set_recoverable_error (const char *error
)
190 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
202 set_syntax_error (const char *error
)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
208 set_first_syntax_error (const char *error
)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
215 set_fatal_syntax_error (const char *error
)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc
;
250 /* Structure for a hash table entry for a register. */
254 unsigned char number
;
256 unsigned char builtin
;
259 /* Macros to define the register types and masks for the purpose
262 #undef AARCH64_REG_TYPES
263 #define AARCH64_REG_TYPES \
264 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
265 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
266 BASIC_REG_TYPE(SP_32) /* wsp */ \
267 BASIC_REG_TYPE(SP_64) /* sp */ \
268 BASIC_REG_TYPE(Z_32) /* wzr */ \
269 BASIC_REG_TYPE(Z_64) /* xzr */ \
270 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
271 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
272 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
273 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
274 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
275 BASIC_REG_TYPE(CN) /* c[0-7] */ \
276 BASIC_REG_TYPE(VN) /* v[0-31] */ \
277 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
278 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
279 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
280 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
281 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
282 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
283 /* Typecheck: any [BHSDQ]P FP. */ \
284 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
285 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
286 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
287 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
289 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
290 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
291 /* Any integer register; used for error messages only. */ \
292 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
293 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Pseudo type to mark the end of the enumerator sequence. */ \
298 #undef BASIC_REG_TYPE
299 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
300 #undef MULTI_REG_TYPE
301 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
303 /* Register type enumerators. */
306 /* A list of REG_TYPE_*. */
310 #undef BASIC_REG_TYPE
311 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
313 #define REG_TYPE(T) (1 << REG_TYPE_##T)
314 #undef MULTI_REG_TYPE
315 #define MULTI_REG_TYPE(T,V) V,
317 /* Values indexed by aarch64_reg_type to assist the type checking. */
318 static const unsigned reg_type_masks
[] =
323 #undef BASIC_REG_TYPE
325 #undef MULTI_REG_TYPE
326 #undef AARCH64_REG_TYPES
328 /* Diagnostics used when we don't get a register of the expected type.
329 Note: this has to synchronized with aarch64_reg_type definitions
332 get_reg_expected_msg (aarch64_reg_type reg_type
)
339 msg
= N_("integer 32-bit register expected");
342 msg
= N_("integer 64-bit register expected");
345 msg
= N_("integer register expected");
347 case REG_TYPE_R_Z_SP
:
348 msg
= N_("integer, zero or SP register expected");
351 msg
= N_("8-bit SIMD scalar register expected");
354 msg
= N_("16-bit SIMD scalar or floating-point half precision "
355 "register expected");
358 msg
= N_("32-bit SIMD scalar or floating-point single precision "
359 "register expected");
362 msg
= N_("64-bit SIMD scalar or floating-point double precision "
363 "register expected");
366 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
367 "register expected");
370 msg
= N_("C0 - C15 expected");
372 case REG_TYPE_R_Z_BHSDQ_V
:
373 msg
= N_("register expected");
375 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
376 msg
= N_("SIMD scalar or floating-point register expected");
378 case REG_TYPE_VN
: /* any V reg */
379 msg
= N_("vector register expected");
382 as_fatal (_("invalid register type %d"), reg_type
);
387 /* Some well known registers that we refer to directly elsewhere. */
390 /* Instructions take 4 bytes in the object file. */
393 /* Define some common error messages. */
394 #define BAD_SP _("SP not allowed here")
396 static struct hash_control
*aarch64_ops_hsh
;
397 static struct hash_control
*aarch64_cond_hsh
;
398 static struct hash_control
*aarch64_shift_hsh
;
399 static struct hash_control
*aarch64_sys_regs_hsh
;
400 static struct hash_control
*aarch64_pstatefield_hsh
;
401 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
402 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
403 static struct hash_control
*aarch64_sys_regs_at_hsh
;
404 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
405 static struct hash_control
*aarch64_reg_hsh
;
406 static struct hash_control
*aarch64_barrier_opt_hsh
;
407 static struct hash_control
*aarch64_nzcv_hsh
;
408 static struct hash_control
*aarch64_pldop_hsh
;
409 static struct hash_control
*aarch64_hint_opt_hsh
;
411 /* Stuff needed to resolve the label ambiguity
420 static symbolS
*last_label_seen
;
422 /* Literal pool structure. Held on a per-section
423 and per-sub-section basis. */
425 #define MAX_LITERAL_POOL_SIZE 1024
426 typedef struct literal_expression
429 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
430 LITTLENUM_TYPE
* bignum
;
431 } literal_expression
;
433 typedef struct literal_pool
435 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
436 unsigned int next_free_entry
;
442 struct literal_pool
*next
;
445 /* Pointer to a linked list of literal pools. */
446 static literal_pool
*list_of_pools
= NULL
;
450 /* This array holds the chars that always start a comment. If the
451 pre-processor is disabled, these aren't very useful. */
452 const char comment_chars
[] = "";
454 /* This array holds the chars that only start a comment at the beginning of
455 a line. If the line seems to have the form '# 123 filename'
456 .line and .file directives will appear in the pre-processed output. */
457 /* Note that input_file.c hand checks for '#' at the beginning of the
458 first line of the input file. This is because the compiler outputs
459 #NO_APP at the beginning of its output. */
460 /* Also note that comments like this one will always work. */
461 const char line_comment_chars
[] = "#";
463 const char line_separator_chars
[] = ";";
465 /* Chars that can be used to separate mant
466 from exp in floating point numbers. */
467 const char EXP_CHARS
[] = "eE";
469 /* Chars that mean this number is a floating point constant. */
473 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
475 /* Prefix character that indicates the start of an immediate value. */
476 #define is_immediate_prefix(C) ((C) == '#')
478 /* Separator character handling. */
480 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
482 static inline bfd_boolean
483 skip_past_char (char **str
, char c
)
494 #define skip_past_comma(str) skip_past_char (str, ',')
496 /* Arithmetic expressions (possibly involving symbols). */
498 static bfd_boolean in_my_get_expression_p
= FALSE
;
500 /* Third argument to my_get_expression. */
501 #define GE_NO_PREFIX 0
502 #define GE_OPT_PREFIX 1
504 /* Return TRUE if the string pointed by *STR is successfully parsed
505 as an valid expression; *EP will be filled with the information of
506 such an expression. Otherwise return FALSE. */
509 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
514 int prefix_present_p
= 0;
521 if (is_immediate_prefix (**str
))
524 prefix_present_p
= 1;
531 memset (ep
, 0, sizeof (expressionS
));
533 save_in
= input_line_pointer
;
534 input_line_pointer
= *str
;
535 in_my_get_expression_p
= TRUE
;
536 seg
= expression (ep
);
537 in_my_get_expression_p
= FALSE
;
539 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
541 /* We found a bad expression in md_operand(). */
542 *str
= input_line_pointer
;
543 input_line_pointer
= save_in
;
544 if (prefix_present_p
&& ! error_p ())
545 set_fatal_syntax_error (_("bad expression"));
547 set_first_syntax_error (_("bad expression"));
552 if (seg
!= absolute_section
553 && seg
!= text_section
554 && seg
!= data_section
555 && seg
!= bss_section
&& seg
!= undefined_section
)
557 set_syntax_error (_("bad segment"));
558 *str
= input_line_pointer
;
559 input_line_pointer
= save_in
;
566 *str
= input_line_pointer
;
567 input_line_pointer
= save_in
;
571 /* Turn a string in input_line_pointer into a floating point constant
572 of type TYPE, and store the appropriate bytes in *LITP. The number
573 of LITTLENUMS emitted is stored in *SIZEP. An error message is
574 returned, or NULL on OK. */
577 md_atof (int type
, char *litP
, int *sizeP
)
579 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
582 /* We handle all bad expressions here, so that we can report the faulty
583 instruction in the error message. */
585 md_operand (expressionS
* exp
)
587 if (in_my_get_expression_p
)
588 exp
->X_op
= O_illegal
;
591 /* Immediate values. */
593 /* Errors may be set multiple times during parsing or bit encoding
594 (particularly in the Neon bits), but usually the earliest error which is set
595 will be the most meaningful. Avoid overwriting it with later (cascading)
596 errors by calling this function. */
599 first_error (const char *error
)
602 set_syntax_error (error
);
605 /* Similiar to first_error, but this function accepts formatted error
608 first_error_fmt (const char *format
, ...)
613 /* N.B. this single buffer will not cause error messages for different
614 instructions to pollute each other; this is because at the end of
615 processing of each assembly line, error message if any will be
616 collected by as_bad. */
617 static char buffer
[size
];
621 int ret ATTRIBUTE_UNUSED
;
622 va_start (args
, format
);
623 ret
= vsnprintf (buffer
, size
, format
, args
);
624 know (ret
<= size
- 1 && ret
>= 0);
626 set_syntax_error (buffer
);
630 /* Register parsing. */
632 /* Generic register parser which is called by other specialized
634 CCP points to what should be the beginning of a register name.
635 If it is indeed a valid register name, advance CCP over it and
636 return the reg_entry structure; otherwise return NULL.
637 It does not issue diagnostics. */
640 parse_reg (char **ccp
)
646 #ifdef REGISTER_PREFIX
647 if (*start
!= REGISTER_PREFIX
)
653 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
658 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
660 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
669 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
672 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
674 if (reg
->type
== type
)
679 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
680 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
681 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
682 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
683 case REG_TYPE_VN
: /* Vector register. */
684 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
685 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
686 == reg_type_masks
[reg
->type
]);
688 as_fatal ("unhandled type %d", type
);
693 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
694 Return the register number otherwise. *ISREG32 is set to one if the
695 register is 32-bit wide; *ISREGZERO is set to one if the register is
696 of type Z_32 or Z_64.
697 Note that this function does not issue any diagnostics. */
700 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
701 int *isreg32
, int *isregzero
)
704 const reg_entry
*reg
= parse_reg (&str
);
709 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
718 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
723 *isreg32
= reg
->type
== REG_TYPE_R_32
;
730 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
742 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
743 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
744 otherwise return FALSE.
746 Accept only one occurrence of:
747 8b 16b 4h 8h 2s 4s 1d 2d
750 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
754 unsigned element_size
;
755 enum neon_el_type type
;
765 width
= strtoul (ptr
, &ptr
, 10);
766 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
768 first_error_fmt (_("bad size %d in vector width specifier"), width
);
773 switch (TOLOWER (*ptr
))
801 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
803 first_error (_("missing element size"));
806 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128)
809 ("invalid element size %d and vector size combination %c"),
815 parsed_type
->type
= type
;
816 parsed_type
->width
= width
;
823 /* Parse a single type, e.g. ".8b", leading period included.
824 Only applicable to Vn registers.
826 Return TRUE on success; otherwise return FALSE. */
828 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
834 if (! parse_neon_type_for_operand (vectype
, &str
))
836 first_error (_("vector type expected"));
848 /* Parse a register of the type TYPE.
850 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
851 name or the parsed register is not of TYPE.
853 Otherwise return the register number, and optionally fill in the actual
854 type of the register in *RTYPE when multiple alternatives were given, and
855 return the register shape and element index information in *TYPEINFO.
857 IN_REG_LIST should be set with TRUE if the caller is parsing a register
861 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
862 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
865 const reg_entry
*reg
= parse_reg (&str
);
866 struct neon_type_el atype
;
867 struct neon_type_el parsetype
;
868 bfd_boolean is_typed_vecreg
= FALSE
;
871 atype
.type
= NT_invtype
;
879 set_default_error ();
883 if (! aarch64_check_reg_type (reg
, type
))
885 DEBUG_TRACE ("reg type check failed");
886 set_default_error ();
891 if (type
== REG_TYPE_VN
892 && parse_neon_operand_type (&parsetype
, &str
))
894 /* Register if of the form Vn.[bhsdq]. */
895 is_typed_vecreg
= TRUE
;
897 if (parsetype
.width
== 0)
898 /* Expect index. In the new scheme we cannot have
899 Vn.[bhsdq] represent a scalar. Therefore any
900 Vn.[bhsdq] should have an index following it.
901 Except in reglists ofcourse. */
902 atype
.defined
|= NTA_HASINDEX
;
904 atype
.defined
|= NTA_HASTYPE
;
906 atype
.type
= parsetype
.type
;
907 atype
.width
= parsetype
.width
;
910 if (skip_past_char (&str
, '['))
914 /* Reject Sn[index] syntax. */
915 if (!is_typed_vecreg
)
917 first_error (_("this type of register can't be indexed"));
921 if (in_reg_list
== TRUE
)
923 first_error (_("index not allowed inside register list"));
927 atype
.defined
|= NTA_HASINDEX
;
929 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
931 if (exp
.X_op
!= O_constant
)
933 first_error (_("constant expression required"));
937 if (! skip_past_char (&str
, ']'))
940 atype
.index
= exp
.X_add_number
;
942 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
944 /* Indexed vector register expected. */
945 first_error (_("indexed vector register expected"));
949 /* A vector reg Vn should be typed or indexed. */
950 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
952 first_error (_("invalid use of vector register"));
968 Return the register number on success; return PARSE_FAIL otherwise.
970 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
971 the register (e.g. NEON double or quad reg when either has been requested).
973 If this is a NEON vector register with additional type information, fill
974 in the struct pointed to by VECTYPE (if non-NULL).
976 This parser does not handle register list. */
979 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
980 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
982 struct neon_type_el atype
;
984 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
985 /*in_reg_list= */ FALSE
);
987 if (reg
== PARSE_FAIL
)
998 static inline bfd_boolean
999 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
1003 && e1
.defined
== e2
.defined
1004 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1007 /* This function parses the NEON register list. On success, it returns
1008 the parsed register list information in the following encoded format:
1010 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1011 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1013 The information of the register shape and/or index is returned in
1016 It returns PARSE_FAIL if the register list is invalid.
1018 The list contains one to four registers.
1019 Each register can be one of:
1022 All <T> should be identical.
1023 All <index> should be identical.
1024 There are restrictions on <Vt> numbers which are checked later
1025 (by reg_list_valid_p). */
1028 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1032 struct neon_type_el typeinfo
, typeinfo_first
;
1037 bfd_boolean error
= FALSE
;
1038 bfd_boolean expect_index
= FALSE
;
1042 set_syntax_error (_("expecting {"));
1048 typeinfo_first
.defined
= 0;
1049 typeinfo_first
.type
= NT_invtype
;
1050 typeinfo_first
.width
= -1;
1051 typeinfo_first
.index
= 0;
1060 str
++; /* skip over '-' */
1063 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1064 /*in_reg_list= */ TRUE
);
1065 if (val
== PARSE_FAIL
)
1067 set_first_syntax_error (_("invalid vector register in list"));
1071 /* reject [bhsd]n */
1072 if (typeinfo
.defined
== 0)
1074 set_first_syntax_error (_("invalid scalar register in list"));
1079 if (typeinfo
.defined
& NTA_HASINDEX
)
1080 expect_index
= TRUE
;
1084 if (val
< val_range
)
1086 set_first_syntax_error
1087 (_("invalid range in vector register list"));
1096 typeinfo_first
= typeinfo
;
1097 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1099 set_first_syntax_error
1100 (_("type mismatch in vector register list"));
1105 for (i
= val_range
; i
<= val
; i
++)
1107 ret_val
|= i
<< (5 * nb_regs
);
1112 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1114 skip_whitespace (str
);
1117 set_first_syntax_error (_("end of vector register list not found"));
1122 skip_whitespace (str
);
1126 if (skip_past_char (&str
, '['))
1130 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1131 if (exp
.X_op
!= O_constant
)
1133 set_first_syntax_error (_("constant expression required."));
1136 if (! skip_past_char (&str
, ']'))
1139 typeinfo_first
.index
= exp
.X_add_number
;
1143 set_first_syntax_error (_("expected index"));
1150 set_first_syntax_error (_("too many registers in vector register list"));
1153 else if (nb_regs
== 0)
1155 set_first_syntax_error (_("empty vector register list"));
1161 *vectype
= typeinfo_first
;
1163 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1166 /* Directives: register aliases. */
1169 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1174 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1177 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1180 /* Only warn about a redefinition if it's not defined as the
1182 else if (new->number
!= number
|| new->type
!= type
)
1183 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1188 name
= xstrdup (str
);
1189 new = xmalloc (sizeof (reg_entry
));
1192 new->number
= number
;
1194 new->builtin
= FALSE
;
1196 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1202 /* Look for the .req directive. This is of the form:
1204 new_register_name .req existing_register_name
1206 If we find one, or if it looks sufficiently like one that we want to
1207 handle any error here, return TRUE. Otherwise return FALSE. */
1210 create_register_alias (char *newname
, char *p
)
1212 const reg_entry
*old
;
1213 char *oldname
, *nbuf
;
1216 /* The input scrubber ensures that whitespace after the mnemonic is
1217 collapsed to single spaces. */
1219 if (strncmp (oldname
, " .req ", 6) != 0)
1223 if (*oldname
== '\0')
1226 old
= hash_find (aarch64_reg_hsh
, oldname
);
1229 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1233 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1234 the desired alias name, and p points to its end. If not, then
1235 the desired alias name is in the global original_case_string. */
1236 #ifdef TC_CASE_SENSITIVE
1239 newname
= original_case_string
;
1240 nlen
= strlen (newname
);
1243 nbuf
= alloca (nlen
+ 1);
1244 memcpy (nbuf
, newname
, nlen
);
1247 /* Create aliases under the new name as stated; an all-lowercase
1248 version of the new name; and an all-uppercase version of the new
1250 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1252 for (p
= nbuf
; *p
; p
++)
1255 if (strncmp (nbuf
, newname
, nlen
))
1257 /* If this attempt to create an additional alias fails, do not bother
1258 trying to create the all-lower case alias. We will fail and issue
1259 a second, duplicate error message. This situation arises when the
1260 programmer does something like:
1263 The second .req creates the "Foo" alias but then fails to create
1264 the artificial FOO alias because it has already been created by the
1266 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1270 for (p
= nbuf
; *p
; p
++)
1273 if (strncmp (nbuf
, newname
, nlen
))
1274 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1280 /* Should never be called, as .req goes between the alias and the
1281 register name, not at the beginning of the line. */
1283 s_req (int a ATTRIBUTE_UNUSED
)
1285 as_bad (_("invalid syntax for .req directive"));
1288 /* The .unreq directive deletes an alias which was previously defined
1289 by .req. For example:
1295 s_unreq (int a ATTRIBUTE_UNUSED
)
1300 name
= input_line_pointer
;
1302 while (*input_line_pointer
!= 0
1303 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1304 ++input_line_pointer
;
1306 saved_char
= *input_line_pointer
;
1307 *input_line_pointer
= 0;
1310 as_bad (_("invalid syntax for .unreq directive"));
1313 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1316 as_bad (_("unknown register alias '%s'"), name
);
1317 else if (reg
->builtin
)
1318 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1325 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1326 free ((char *) reg
->name
);
1329 /* Also locate the all upper case and all lower case versions.
1330 Do not complain if we cannot find one or the other as it
1331 was probably deleted above. */
1333 nbuf
= strdup (name
);
1334 for (p
= nbuf
; *p
; p
++)
1336 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1339 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1340 free ((char *) reg
->name
);
1344 for (p
= nbuf
; *p
; p
++)
1346 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1349 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1350 free ((char *) reg
->name
);
1358 *input_line_pointer
= saved_char
;
1359 demand_empty_rest_of_line ();
1362 /* Directives: Instruction set selection. */
1365 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1366 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1367 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1368 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1370 /* Create a new mapping symbol for the transition to STATE. */
1373 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1376 const char *symname
;
1383 type
= BSF_NO_FLAGS
;
1387 type
= BSF_NO_FLAGS
;
1393 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1394 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1396 /* Save the mapping symbols for future reference. Also check that
1397 we do not place two mapping symbols at the same offset within a
1398 frag. We'll handle overlap between frags in
1399 check_mapping_symbols.
1401 If .fill or other data filling directive generates zero sized data,
1402 the mapping symbol for the following code will have the same value
1403 as the one generated for the data filling directive. In this case,
1404 we replace the old symbol with the new one at the same address. */
1407 if (frag
->tc_frag_data
.first_map
!= NULL
)
1409 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1410 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1413 frag
->tc_frag_data
.first_map
= symbolP
;
1415 if (frag
->tc_frag_data
.last_map
!= NULL
)
1417 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1418 S_GET_VALUE (symbolP
));
1419 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1420 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1423 frag
->tc_frag_data
.last_map
= symbolP
;
1426 /* We must sometimes convert a region marked as code to data during
1427 code alignment, if an odd number of bytes have to be padded. The
1428 code mapping symbol is pushed to an aligned address. */
1431 insert_data_mapping_symbol (enum mstate state
,
1432 valueT value
, fragS
* frag
, offsetT bytes
)
1434 /* If there was already a mapping symbol, remove it. */
1435 if (frag
->tc_frag_data
.last_map
!= NULL
1436 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1437 frag
->fr_address
+ value
)
1439 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1443 know (frag
->tc_frag_data
.first_map
== symp
);
1444 frag
->tc_frag_data
.first_map
= NULL
;
1446 frag
->tc_frag_data
.last_map
= NULL
;
1447 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1450 make_mapping_symbol (MAP_DATA
, value
, frag
);
1451 make_mapping_symbol (state
, value
+ bytes
, frag
);
1454 static void mapping_state_2 (enum mstate state
, int max_chars
);
1456 /* Set the mapping state to STATE. Only call this when about to
1457 emit some STATE bytes to the file. */
1460 mapping_state (enum mstate state
)
1462 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1464 if (state
== MAP_INSN
)
1465 /* AArch64 instructions require 4-byte alignment. When emitting
1466 instructions into any section, record the appropriate section
1468 record_alignment (now_seg
, 2);
1470 if (mapstate
== state
)
1471 /* The mapping symbol has already been emitted.
1472 There is nothing else to do. */
1475 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1476 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1477 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1478 evaluated later in the next else. */
1480 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1482 /* Only add the symbol if the offset is > 0:
1483 if we're at the first frag, check it's size > 0;
1484 if we're not at the first frag, then for sure
1485 the offset is > 0. */
1486 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1487 const int add_symbol
= (frag_now
!= frag_first
)
1488 || (frag_now_fix () > 0);
1491 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1495 mapping_state_2 (state
, 0);
1498 /* Same as mapping_state, but MAX_CHARS bytes have already been
1499 allocated. Put the mapping symbol that far back. */
1502 mapping_state_2 (enum mstate state
, int max_chars
)
1504 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1506 if (!SEG_NORMAL (now_seg
))
1509 if (mapstate
== state
)
1510 /* The mapping symbol has already been emitted.
1511 There is nothing else to do. */
1514 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1515 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1518 #define mapping_state(x) /* nothing */
1519 #define mapping_state_2(x, y) /* nothing */
1522 /* Directives: sectioning and alignment. */
1525 s_bss (int ignore ATTRIBUTE_UNUSED
)
1527 /* We don't support putting frags in the BSS segment, we fake it by
1528 marking in_bss, then looking at s_skip for clues. */
1529 subseg_set (bss_section
, 0);
1530 demand_empty_rest_of_line ();
1531 mapping_state (MAP_DATA
);
1535 s_even (int ignore ATTRIBUTE_UNUSED
)
1537 /* Never make frag if expect extra pass. */
1539 frag_align (1, 0, 0);
1541 record_alignment (now_seg
, 1);
1543 demand_empty_rest_of_line ();
1546 /* Directives: Literal pools. */
1548 static literal_pool
*
1549 find_literal_pool (int size
)
1553 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1555 if (pool
->section
== now_seg
1556 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1563 static literal_pool
*
1564 find_or_make_literal_pool (int size
)
1566 /* Next literal pool ID number. */
1567 static unsigned int latest_pool_num
= 1;
1570 pool
= find_literal_pool (size
);
1574 /* Create a new pool. */
1575 pool
= xmalloc (sizeof (*pool
));
1579 /* Currently we always put the literal pool in the current text
1580 section. If we were generating "small" model code where we
1581 knew that all code and initialised data was within 1MB then
1582 we could output literals to mergeable, read-only data
1585 pool
->next_free_entry
= 0;
1586 pool
->section
= now_seg
;
1587 pool
->sub_section
= now_subseg
;
1589 pool
->next
= list_of_pools
;
1590 pool
->symbol
= NULL
;
1592 /* Add it to the list. */
1593 list_of_pools
= pool
;
1596 /* New pools, and emptied pools, will have a NULL symbol. */
1597 if (pool
->symbol
== NULL
)
1599 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1600 (valueT
) 0, &zero_address_frag
);
1601 pool
->id
= latest_pool_num
++;
1608 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1609 Return TRUE on success, otherwise return FALSE. */
1611 add_to_lit_pool (expressionS
*exp
, int size
)
1616 pool
= find_or_make_literal_pool (size
);
1618 /* Check if this literal value is already in the pool. */
1619 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1621 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1623 if ((litexp
->X_op
== exp
->X_op
)
1624 && (exp
->X_op
== O_constant
)
1625 && (litexp
->X_add_number
== exp
->X_add_number
)
1626 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1629 if ((litexp
->X_op
== exp
->X_op
)
1630 && (exp
->X_op
== O_symbol
)
1631 && (litexp
->X_add_number
== exp
->X_add_number
)
1632 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1633 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1637 /* Do we need to create a new entry? */
1638 if (entry
== pool
->next_free_entry
)
1640 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1642 set_syntax_error (_("literal pool overflow"));
1646 pool
->literals
[entry
].exp
= *exp
;
1647 pool
->next_free_entry
+= 1;
1648 if (exp
->X_op
== O_big
)
1650 /* PR 16688: Bignums are held in a single global array. We must
1651 copy and preserve that value now, before it is overwritten. */
1652 pool
->literals
[entry
].bignum
= xmalloc (CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1653 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1654 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1657 pool
->literals
[entry
].bignum
= NULL
;
1660 exp
->X_op
= O_symbol
;
1661 exp
->X_add_number
= ((int) entry
) * size
;
1662 exp
->X_add_symbol
= pool
->symbol
;
1667 /* Can't use symbol_new here, so have to create a symbol and then at
1668 a later date assign it a value. Thats what these functions do. */
1671 symbol_locate (symbolS
* symbolP
,
1672 const char *name
,/* It is copied, the caller can modify. */
1673 segT segment
, /* Segment identifier (SEG_<something>). */
1674 valueT valu
, /* Symbol value. */
1675 fragS
* frag
) /* Associated fragment. */
1678 char *preserved_copy_of_name
;
1680 name_length
= strlen (name
) + 1; /* +1 for \0. */
1681 obstack_grow (¬es
, name
, name_length
);
1682 preserved_copy_of_name
= obstack_finish (¬es
);
1684 #ifdef tc_canonicalize_symbol_name
1685 preserved_copy_of_name
=
1686 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1689 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1691 S_SET_SEGMENT (symbolP
, segment
);
1692 S_SET_VALUE (symbolP
, valu
);
1693 symbol_clear_list_pointers (symbolP
);
1695 symbol_set_frag (symbolP
, frag
);
1697 /* Link to end of symbol chain. */
1699 extern int symbol_table_frozen
;
1701 if (symbol_table_frozen
)
1705 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1707 obj_symbol_new_hook (symbolP
);
1709 #ifdef tc_symbol_new_hook
1710 tc_symbol_new_hook (symbolP
);
1714 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1715 #endif /* DEBUG_SYMS */
1720 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1727 for (align
= 2; align
<= 4; align
++)
1729 int size
= 1 << align
;
1731 pool
= find_literal_pool (size
);
1732 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1735 mapping_state (MAP_DATA
);
1737 /* Align pool as you have word accesses.
1738 Only make a frag if we have to. */
1740 frag_align (align
, 0, 0);
1742 record_alignment (now_seg
, align
);
1744 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1746 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1747 (valueT
) frag_now_fix (), frag_now
);
1748 symbol_table_insert (pool
->symbol
);
1750 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1752 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1754 if (exp
->X_op
== O_big
)
1756 /* PR 16688: Restore the global bignum value. */
1757 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1758 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1759 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1762 /* First output the expression in the instruction to the pool. */
1763 emit_expr (exp
, size
); /* .word|.xword */
1765 if (exp
->X_op
== O_big
)
1767 free (pool
->literals
[entry
].bignum
);
1768 pool
->literals
[entry
].bignum
= NULL
;
1772 /* Mark the pool as empty. */
1773 pool
->next_free_entry
= 0;
1774 pool
->symbol
= NULL
;
1779 /* Forward declarations for functions below, in the MD interface
1781 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1782 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1784 /* Directives: Data. */
1785 /* N.B. the support for relocation suffix in this directive needs to be
1786 implemented properly. */
1789 s_aarch64_elf_cons (int nbytes
)
1793 #ifdef md_flush_pending_output
1794 md_flush_pending_output ();
1797 if (is_it_end_of_statement ())
1799 demand_empty_rest_of_line ();
1803 #ifdef md_cons_align
1804 md_cons_align (nbytes
);
1807 mapping_state (MAP_DATA
);
1810 struct reloc_table_entry
*reloc
;
1814 if (exp
.X_op
!= O_symbol
)
1815 emit_expr (&exp
, (unsigned int) nbytes
);
1818 skip_past_char (&input_line_pointer
, '#');
1819 if (skip_past_char (&input_line_pointer
, ':'))
1821 reloc
= find_reloc_table_entry (&input_line_pointer
);
1823 as_bad (_("unrecognized relocation suffix"));
1825 as_bad (_("unimplemented relocation suffix"));
1826 ignore_rest_of_line ();
1830 emit_expr (&exp
, (unsigned int) nbytes
);
1833 while (*input_line_pointer
++ == ',');
1835 /* Put terminator back into stream. */
1836 input_line_pointer
--;
1837 demand_empty_rest_of_line ();
1840 #endif /* OBJ_ELF */
1842 /* Output a 32-bit word, but mark as an instruction. */
1845 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1849 #ifdef md_flush_pending_output
1850 md_flush_pending_output ();
1853 if (is_it_end_of_statement ())
1855 demand_empty_rest_of_line ();
1859 /* Sections are assumed to start aligned. In executable section, there is no
1860 MAP_DATA symbol pending. So we only align the address during
1861 MAP_DATA --> MAP_INSN transition.
1862 For other sections, this is not guaranteed. */
1863 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1864 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1865 frag_align_code (2, 0);
1868 mapping_state (MAP_INSN
);
1874 if (exp
.X_op
!= O_constant
)
1876 as_bad (_("constant expression required"));
1877 ignore_rest_of_line ();
1881 if (target_big_endian
)
1883 unsigned int val
= exp
.X_add_number
;
1884 exp
.X_add_number
= SWAP_32 (val
);
1886 emit_expr (&exp
, 4);
1888 while (*input_line_pointer
++ == ',');
1890 /* Put terminator back into stream. */
1891 input_line_pointer
--;
1892 demand_empty_rest_of_line ();
1896 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1899 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1905 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1906 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1908 demand_empty_rest_of_line ();
1911 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1914 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1918 /* Since we're just labelling the code, there's no need to define a
1921 /* Make sure there is enough room in this frag for the following
1922 blr. This trick only works if the blr follows immediately after
1923 the .tlsdesc directive. */
1925 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1926 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1928 demand_empty_rest_of_line ();
1931 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
1934 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
1940 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1941 BFD_RELOC_AARCH64_TLSDESC_LDR
);
1943 demand_empty_rest_of_line ();
1945 #endif /* OBJ_ELF */
1947 static void s_aarch64_arch (int);
1948 static void s_aarch64_cpu (int);
1949 static void s_aarch64_arch_extension (int);
1951 /* This table describes all the machine specific pseudo-ops the assembler
1952 has to support. The fields are:
1953 pseudo-op name without dot
1954 function to call to execute this pseudo-op
1955 Integer arg to pass to the function. */
1957 const pseudo_typeS md_pseudo_table
[] = {
1958 /* Never called because '.req' does not start a line. */
1960 {"unreq", s_unreq
, 0},
1962 {"even", s_even
, 0},
1963 {"ltorg", s_ltorg
, 0},
1964 {"pool", s_ltorg
, 0},
1965 {"cpu", s_aarch64_cpu
, 0},
1966 {"arch", s_aarch64_arch
, 0},
1967 {"arch_extension", s_aarch64_arch_extension
, 0},
1968 {"inst", s_aarch64_inst
, 0},
1970 {"tlsdescadd", s_tlsdescadd
, 0},
1971 {"tlsdesccall", s_tlsdesccall
, 0},
1972 {"tlsdescldr", s_tlsdescldr
, 0},
1973 {"word", s_aarch64_elf_cons
, 4},
1974 {"long", s_aarch64_elf_cons
, 4},
1975 {"xword", s_aarch64_elf_cons
, 8},
1976 {"dword", s_aarch64_elf_cons
, 8},
1982 /* Check whether STR points to a register name followed by a comma or the
1983 end of line; REG_TYPE indicates which register types are checked
1984 against. Return TRUE if STR is such a register name; otherwise return
1985 FALSE. The function does not intend to produce any diagnostics, but since
1986 the register parser aarch64_reg_parse, which is called by this function,
1987 does produce diagnostics, we call clear_error to clear any diagnostics
1988 that may be generated by aarch64_reg_parse.
1989 Also, the function returns FALSE directly if there is any user error
1990 present at the function entry. This prevents the existing diagnostics
1991 state from being spoiled.
1992 The function currently serves parse_constant_immediate and
1993 parse_big_immediate only. */
1995 reg_name_p (char *str
, aarch64_reg_type reg_type
)
1999 /* Prevent the diagnostics state from being spoiled. */
2003 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2005 /* Clear the parsing error that may be set by the reg parser. */
2008 if (reg
== PARSE_FAIL
)
2011 skip_whitespace (str
);
2012 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2018 /* Parser functions used exclusively in instruction operands. */
2020 /* Parse an immediate expression which may not be constant.
2022 To prevent the expression parser from pushing a register name
2023 into the symbol table as an undefined symbol, firstly a check is
2024 done to find out whether STR is a valid register name followed
2025 by a comma or the end of line. Return FALSE if STR is such a
2029 parse_immediate_expression (char **str
, expressionS
*exp
)
2031 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
2033 set_recoverable_error (_("immediate operand required"));
2037 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2039 if (exp
->X_op
== O_absent
)
2041 set_fatal_syntax_error (_("missing immediate expression"));
2048 /* Constant immediate-value read function for use in insn parsing.
2049 STR points to the beginning of the immediate (with the optional
2050 leading #); *VAL receives the value.
2052 Return TRUE on success; otherwise return FALSE. */
2055 parse_constant_immediate (char **str
, int64_t * val
)
2059 if (! parse_immediate_expression (str
, &exp
))
2062 if (exp
.X_op
!= O_constant
)
2064 set_syntax_error (_("constant expression required"));
2068 *val
= exp
.X_add_number
;
2073 encode_imm_float_bits (uint32_t imm
)
2075 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2076 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2079 /* Return TRUE if the single-precision floating-point value encoded in IMM
2080 can be expressed in the AArch64 8-bit signed floating-point format with
2081 3-bit exponent and normalized 4 bits of precision; in other words, the
2082 floating-point value must be expressable as
2083 (+/-) n / 16 * power (2, r)
2084 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2087 aarch64_imm_float_p (uint32_t imm
)
2089 /* If a single-precision floating-point value has the following bit
2090 pattern, it can be expressed in the AArch64 8-bit floating-point
2093 3 32222222 2221111111111
2094 1 09876543 21098765432109876543210
2095 n Eeeeeexx xxxx0000000000000000000
2097 where n, e and each x are either 0 or 1 independently, with
2102 /* Prepare the pattern for 'Eeeeee'. */
2103 if (((imm
>> 30) & 0x1) == 0)
2104 pattern
= 0x3e000000;
2106 pattern
= 0x40000000;
2108 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2109 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2112 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2114 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2115 8-bit signed floating-point format with 3-bit exponent and normalized 4
2116 bits of precision (i.e. can be used in an FMOV instruction); return the
2117 equivalent single-precision encoding in *FPWORD.
2119 Otherwise return FALSE. */
2122 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2124 /* If a double-precision floating-point value has the following bit
2125 pattern, it can be expressed in the AArch64 8-bit floating-point
2128 6 66655555555 554444444...21111111111
2129 3 21098765432 109876543...098765432109876543210
2130 n Eeeeeeeeexx xxxx00000...000000000000000000000
2132 where n, e and each x are either 0 or 1 independently, with
2136 uint32_t high32
= imm
>> 32;
2138 /* Lower 32 bits need to be 0s. */
2139 if ((imm
& 0xffffffff) != 0)
2142 /* Prepare the pattern for 'Eeeeeeeee'. */
2143 if (((high32
>> 30) & 0x1) == 0)
2144 pattern
= 0x3fc00000;
2146 pattern
= 0x40000000;
2148 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2149 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2151 /* Convert to the single-precision encoding.
2153 n Eeeeeeeeexx xxxx00000...000000000000000000000
2155 n Eeeeeexx xxxx0000000000000000000. */
2156 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2157 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2164 /* Parse a floating-point immediate. Return TRUE on success and return the
2165 value in *IMMED in the format of IEEE754 single-precision encoding.
2166 *CCP points to the start of the string; DP_P is TRUE when the immediate
2167 is expected to be in double-precision (N.B. this only matters when
2168 hexadecimal representation is involved).
2170 N.B. 0.0 is accepted by this function. */
2173 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2177 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2178 int found_fpchar
= 0;
2180 unsigned fpword
= 0;
2181 bfd_boolean hex_p
= FALSE
;
2183 skip_past_char (&str
, '#');
2186 skip_whitespace (fpnum
);
2188 if (strncmp (fpnum
, "0x", 2) == 0)
2190 /* Support the hexadecimal representation of the IEEE754 encoding.
2191 Double-precision is expected when DP_P is TRUE, otherwise the
2192 representation should be in single-precision. */
2193 if (! parse_constant_immediate (&str
, &val
))
2198 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2201 else if ((uint64_t) val
> 0xffffffff)
2210 /* We must not accidentally parse an integer as a floating-point number.
2211 Make sure that the value we parse is not an integer by checking for
2212 special characters '.' or 'e'. */
2213 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2214 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2228 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2231 /* Our FP word must be 32 bits (single-precision FP). */
2232 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2234 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2239 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2247 set_fatal_syntax_error (_("invalid floating-point constant"));
2251 /* Less-generic immediate-value read function with the possibility of loading
2252 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2255 To prevent the expression parser from pushing a register name into the
2256 symbol table as an undefined symbol, a check is firstly done to find
2257 out whether STR is a valid register name followed by a comma or the end
2258 of line. Return FALSE if STR is such a register. */
2261 parse_big_immediate (char **str
, int64_t *imm
)
2265 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2267 set_syntax_error (_("immediate operand required"));
2271 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2273 if (inst
.reloc
.exp
.X_op
== O_constant
)
2274 *imm
= inst
.reloc
.exp
.X_add_number
;
2281 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2282 if NEED_LIBOPCODES is non-zero, the fixup will need
2283 assistance from the libopcodes. */
2286 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2287 const aarch64_opnd_info
*operand
,
2288 int need_libopcodes_p
)
2290 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2291 reloc
->opnd
= operand
->type
;
2292 if (need_libopcodes_p
)
2293 reloc
->need_libopcodes_p
= 1;
2296 /* Return TRUE if the instruction needs to be fixed up later internally by
2297 the GAS; otherwise return FALSE. */
2299 static inline bfd_boolean
2300 aarch64_gas_internal_fixup_p (void)
2302 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2305 /* Assign the immediate value to the relavant field in *OPERAND if
2306 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2307 needs an internal fixup in a later stage.
2308 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2309 IMM.VALUE that may get assigned with the constant. */
2311 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2312 aarch64_opnd_info
*operand
,
2314 int need_libopcodes_p
,
2317 if (reloc
->exp
.X_op
== O_constant
)
2320 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2322 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2323 reloc
->type
= BFD_RELOC_UNUSED
;
2327 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2328 /* Tell libopcodes to ignore this operand or not. This is helpful
2329 when one of the operands needs to be fixed up later but we need
2330 libopcodes to check the other operands. */
2331 operand
->skip
= skip_p
;
2335 /* Relocation modifiers. Each entry in the table contains the textual
2336 name for the relocation which may be placed before a symbol used as
2337 a load/store offset, or add immediate. It must be surrounded by a
2338 leading and trailing colon, for example:
2340 ldr x0, [x1, #:rello:varsym]
2341 add x0, x1, #:rello:varsym */
2343 struct reloc_table_entry
2347 bfd_reloc_code_real_type adr_type
;
2348 bfd_reloc_code_real_type adrp_type
;
2349 bfd_reloc_code_real_type movw_type
;
2350 bfd_reloc_code_real_type add_type
;
2351 bfd_reloc_code_real_type ldst_type
;
2352 bfd_reloc_code_real_type ld_literal_type
;
2355 static struct reloc_table_entry reloc_table
[] = {
2356 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2361 BFD_RELOC_AARCH64_ADD_LO12
,
2362 BFD_RELOC_AARCH64_LDST_LO12
,
2365 /* Higher 21 bits of pc-relative page offset: ADRP */
2368 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2374 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2377 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2383 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2387 BFD_RELOC_AARCH64_MOVW_G0
,
2392 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2396 BFD_RELOC_AARCH64_MOVW_G0_S
,
2401 /* Less significant bits 0-15 of address/value: MOVK, no check */
2405 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2410 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2414 BFD_RELOC_AARCH64_MOVW_G1
,
2419 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2423 BFD_RELOC_AARCH64_MOVW_G1_S
,
2428 /* Less significant bits 16-31 of address/value: MOVK, no check */
2432 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2437 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2441 BFD_RELOC_AARCH64_MOVW_G2
,
2446 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2450 BFD_RELOC_AARCH64_MOVW_G2_S
,
2455 /* Less significant bits 32-47 of address/value: MOVK, no check */
2459 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2464 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2468 BFD_RELOC_AARCH64_MOVW_G3
,
2473 /* Get to the page containing GOT entry for a symbol. */
2476 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2480 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2482 /* 12 bit offset into the page containing GOT entry for that symbol. */
2488 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2491 /* 0-15 bits of address/value: MOVk, no check. */
2495 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2500 /* Most significant bits 16-31 of address/value: MOVZ. */
2504 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2509 /* 15 bit offset into the page containing GOT entry for that symbol. */
2515 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2518 /* Get to the page containing GOT TLS entry for a symbol */
2519 {"gottprel_g0_nc", 0,
2522 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2527 /* Get to the page containing GOT TLS entry for a symbol */
2531 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2536 /* Get to the page containing GOT TLS entry for a symbol */
2538 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2539 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2545 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2550 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2554 /* Lower 16 bits address/value: MOVk. */
2558 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2563 /* Most significant bits 16-31 of address/value: MOVZ. */
2567 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2572 /* Get to the page containing GOT TLS entry for a symbol */
2574 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2575 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2579 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2581 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2586 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2587 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2590 /* Get to the page containing GOT TLS entry for a symbol.
2591 The same as GD, we allocate two consecutive GOT slots
2592 for module index and module offset, the only difference
2593 with GD is the module offset should be intialized to
2594 zero without any outstanding runtime relocation. */
2596 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2597 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2603 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2604 {"tlsldm_lo12_nc", 0,
2608 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2612 /* 12 bit offset into the module TLS base address. */
2617 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2618 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2621 /* Same as dtprel_lo12, no overflow check. */
2622 {"dtprel_lo12_nc", 0,
2626 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2627 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2630 /* bits[23:12] of offset to the module TLS base address. */
2635 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2639 /* bits[15:0] of offset to the module TLS base address. */
2643 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2648 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2652 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2657 /* bits[31:16] of offset to the module TLS base address. */
2661 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2666 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2670 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2675 /* bits[47:32] of offset to the module TLS base address. */
2679 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2684 /* Lower 16 bit offset into GOT entry for a symbol */
2685 {"tlsdesc_off_g0_nc", 0,
2688 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2693 /* Higher 16 bit offset into GOT entry for a symbol */
2694 {"tlsdesc_off_g1", 0,
2697 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2702 /* Get to the page containing GOT TLS entry for a symbol */
2705 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2709 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2711 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2712 {"gottprel_lo12", 0,
2717 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2720 /* Get tp offset for a symbol. */
2725 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2729 /* Get tp offset for a symbol. */
2734 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2738 /* Get tp offset for a symbol. */
2743 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2747 /* Get tp offset for a symbol. */
2748 {"tprel_lo12_nc", 0,
2752 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2756 /* Most significant bits 32-47 of address/value: MOVZ. */
2760 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2765 /* Most significant bits 16-31 of address/value: MOVZ. */
2769 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2774 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2778 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2783 /* Most significant bits 0-15 of address/value: MOVZ. */
2787 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2792 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2796 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2801 /* 15bit offset from got entry to base address of GOT table. */
2807 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2810 /* 14bit offset from got entry to base address of GOT table. */
2816 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2820 /* Given the address of a pointer pointing to the textual name of a
2821 relocation as may appear in assembler source, attempt to find its
2822 details in reloc_table. The pointer will be updated to the character
2823 after the trailing colon. On failure, NULL will be returned;
2824 otherwise return the reloc_table_entry. */
2826 static struct reloc_table_entry
*
2827 find_reloc_table_entry (char **str
)
2830 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2832 int length
= strlen (reloc_table
[i
].name
);
2834 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2835 && (*str
)[length
] == ':')
2837 *str
+= (length
+ 1);
2838 return &reloc_table
[i
];
2845 /* Mode argument to parse_shift and parser_shifter_operand. */
2846 enum parse_shift_mode
2848 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2850 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2852 SHIFTED_LSL
, /* bare "lsl #n" */
2853 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2854 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2857 /* Parse a <shift> operator on an AArch64 data processing instruction.
2858 Return TRUE on success; otherwise return FALSE. */
2860 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2862 const struct aarch64_name_value_pair
*shift_op
;
2863 enum aarch64_modifier_kind kind
;
2869 for (p
= *str
; ISALPHA (*p
); p
++)
2874 set_syntax_error (_("shift expression expected"));
2878 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2880 if (shift_op
== NULL
)
2882 set_syntax_error (_("shift operator expected"));
2886 kind
= aarch64_get_operand_modifier (shift_op
);
2888 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2890 set_syntax_error (_("invalid use of 'MSL'"));
2896 case SHIFTED_LOGIC_IMM
:
2897 if (aarch64_extend_operator_p (kind
) == TRUE
)
2899 set_syntax_error (_("extending shift is not permitted"));
2904 case SHIFTED_ARITH_IMM
:
2905 if (kind
== AARCH64_MOD_ROR
)
2907 set_syntax_error (_("'ROR' shift is not permitted"));
2913 if (kind
!= AARCH64_MOD_LSL
)
2915 set_syntax_error (_("only 'LSL' shift is permitted"));
2920 case SHIFTED_REG_OFFSET
:
2921 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2922 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2924 set_fatal_syntax_error
2925 (_("invalid shift for the register offset addressing mode"));
2930 case SHIFTED_LSL_MSL
:
2931 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2933 set_syntax_error (_("invalid shift operator"));
2942 /* Whitespace can appear here if the next thing is a bare digit. */
2943 skip_whitespace (p
);
2945 /* Parse shift amount. */
2947 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2948 exp
.X_op
= O_absent
;
2951 if (is_immediate_prefix (*p
))
2956 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2958 if (exp
.X_op
== O_absent
)
2960 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2962 set_syntax_error (_("missing shift amount"));
2965 operand
->shifter
.amount
= 0;
2967 else if (exp
.X_op
!= O_constant
)
2969 set_syntax_error (_("constant shift amount required"));
2972 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2974 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2979 operand
->shifter
.amount
= exp
.X_add_number
;
2980 operand
->shifter
.amount_present
= 1;
2983 operand
->shifter
.operator_present
= 1;
2984 operand
->shifter
.kind
= kind
;
2990 /* Parse a <shifter_operand> for a data processing instruction:
2993 #<immediate>, LSL #imm
2995 Validation of immediate operands is deferred to md_apply_fix.
2997 Return TRUE on success; otherwise return FALSE. */
3000 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3001 enum parse_shift_mode mode
)
3005 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3010 /* Accept an immediate expression. */
3011 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3014 /* Accept optional LSL for arithmetic immediate values. */
3015 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3016 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3019 /* Not accept any shifter for logical immediate values. */
3020 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3021 && parse_shift (&p
, operand
, mode
))
3023 set_syntax_error (_("unexpected shift operator"));
3031 /* Parse a <shifter_operand> for a data processing instruction:
3036 #<immediate>, LSL #imm
3038 where <shift> is handled by parse_shift above, and the last two
3039 cases are handled by the function above.
3041 Validation of immediate operands is deferred to md_apply_fix.
3043 Return TRUE on success; otherwise return FALSE. */
3046 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3047 enum parse_shift_mode mode
)
3050 int isreg32
, isregzero
;
3051 enum aarch64_operand_class opd_class
3052 = aarch64_get_operand_class (operand
->type
);
3055 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
3057 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3059 set_syntax_error (_("unexpected register in the immediate operand"));
3063 if (!isregzero
&& reg
== REG_SP
)
3065 set_syntax_error (BAD_SP
);
3069 operand
->reg
.regno
= reg
;
3070 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
3072 /* Accept optional shift operation on register. */
3073 if (! skip_past_comma (str
))
3076 if (! parse_shift (str
, operand
, mode
))
3081 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3084 (_("integer register expected in the extended/shifted operand "
3089 /* We have a shifted immediate variable. */
3090 return parse_shifter_operand_imm (str
, operand
, mode
);
3093 /* Return TRUE on success; return FALSE otherwise. */
3096 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3097 enum parse_shift_mode mode
)
3101 /* Determine if we have the sequence of characters #: or just :
3102 coming next. If we do, then we check for a :rello: relocation
3103 modifier. If we don't, punt the whole lot to
3104 parse_shifter_operand. */
3106 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3108 struct reloc_table_entry
*entry
;
3116 /* Try to parse a relocation. Anything else is an error. */
3117 if (!(entry
= find_reloc_table_entry (str
)))
3119 set_syntax_error (_("unknown relocation modifier"));
3123 if (entry
->add_type
== 0)
3126 (_("this relocation modifier is not allowed on this instruction"));
3130 /* Save str before we decompose it. */
3133 /* Next, we parse the expression. */
3134 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3137 /* Record the relocation type (use the ADD variant here). */
3138 inst
.reloc
.type
= entry
->add_type
;
3139 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3141 /* If str is empty, we've reached the end, stop here. */
3145 /* Otherwise, we have a shifted reloc modifier, so rewind to
3146 recover the variable name and continue parsing for the shifter. */
3148 return parse_shifter_operand_imm (str
, operand
, mode
);
3151 return parse_shifter_operand (str
, operand
, mode
);
3154 /* Parse all forms of an address expression. Information is written
3155 to *OPERAND and/or inst.reloc.
3157 The A64 instruction set has the following addressing modes:
3160 [base] // in SIMD ld/st structure
3161 [base{,#0}] // in ld/st exclusive
3163 [base,Xm{,LSL #imm}]
3164 [base,Xm,SXTX {#imm}]
3165 [base,Wm,(S|U)XTW {#imm}]
3170 [base],Xm // in SIMD ld/st structure
3171 PC-relative (literal)
3175 (As a convenience, the notation "=immediate" is permitted in conjunction
3176 with the pc-relative literal load instructions to automatically place an
3177 immediate value or symbolic address in a nearby literal pool and generate
3178 a hidden label which references it.)
3180 Upon a successful parsing, the address structure in *OPERAND will be
3181 filled in the following way:
3183 .base_regno = <base>
3184 .offset.is_reg // 1 if the offset is a register
3186 .offset.regno = <Rm>
3188 For different addressing modes defined in the A64 ISA:
3191 .pcrel=0; .preind=1; .postind=0; .writeback=0
3193 .pcrel=0; .preind=1; .postind=0; .writeback=1
3195 .pcrel=0; .preind=0; .postind=1; .writeback=1
3196 PC-relative (literal)
3197 .pcrel=1; .preind=1; .postind=0; .writeback=0
3199 The shift/extension information, if any, will be stored in .shifter.
3201 It is the caller's responsibility to check for addressing modes not
3202 supported by the instruction, and to set inst.reloc.type. */
3205 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
3206 int accept_reg_post_index
)
3210 int isreg32
, isregzero
;
3211 expressionS
*exp
= &inst
.reloc
.exp
;
3213 if (! skip_past_char (&p
, '['))
3215 /* =immediate or label. */
3216 operand
->addr
.pcrel
= 1;
3217 operand
->addr
.preind
= 1;
3219 /* #:<reloc_op>:<symbol> */
3220 skip_past_char (&p
, '#');
3221 if (reloc
&& skip_past_char (&p
, ':'))
3223 bfd_reloc_code_real_type ty
;
3224 struct reloc_table_entry
*entry
;
3226 /* Try to parse a relocation modifier. Anything else is
3228 entry
= find_reloc_table_entry (&p
);
3231 set_syntax_error (_("unknown relocation modifier"));
3235 switch (operand
->type
)
3237 case AARCH64_OPND_ADDR_PCREL21
:
3239 ty
= entry
->adr_type
;
3243 ty
= entry
->ld_literal_type
;
3250 (_("this relocation modifier is not allowed on this "
3256 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3258 set_syntax_error (_("invalid relocation expression"));
3262 /* #:<reloc_op>:<expr> */
3263 /* Record the relocation type. */
3264 inst
.reloc
.type
= ty
;
3265 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3270 if (skip_past_char (&p
, '='))
3271 /* =immediate; need to generate the literal in the literal pool. */
3272 inst
.gen_lit_pool
= 1;
3274 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3276 set_syntax_error (_("invalid address"));
3287 /* Accept SP and reject ZR */
3288 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
3289 if (reg
== PARSE_FAIL
|| isreg32
)
3291 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3294 operand
->addr
.base_regno
= reg
;
3297 if (skip_past_comma (&p
))
3300 operand
->addr
.preind
= 1;
3302 /* Reject SP and accept ZR */
3303 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3304 if (reg
!= PARSE_FAIL
)
3307 operand
->addr
.offset
.regno
= reg
;
3308 operand
->addr
.offset
.is_reg
= 1;
3309 /* Shifted index. */
3310 if (skip_past_comma (&p
))
3313 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3314 /* Use the diagnostics set in parse_shift, so not set new
3315 error message here. */
3319 [base,Xm{,LSL #imm}]
3320 [base,Xm,SXTX {#imm}]
3321 [base,Wm,(S|U)XTW {#imm}] */
3322 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3323 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3324 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3328 set_syntax_error (_("invalid use of 32-bit register offset"));
3334 set_syntax_error (_("invalid use of 64-bit register offset"));
3340 /* [Xn,#:<reloc_op>:<symbol> */
3341 skip_past_char (&p
, '#');
3342 if (reloc
&& skip_past_char (&p
, ':'))
3344 struct reloc_table_entry
*entry
;
3346 /* Try to parse a relocation modifier. Anything else is
3348 if (!(entry
= find_reloc_table_entry (&p
)))
3350 set_syntax_error (_("unknown relocation modifier"));
3354 if (entry
->ldst_type
== 0)
3357 (_("this relocation modifier is not allowed on this "
3362 /* [Xn,#:<reloc_op>: */
3363 /* We now have the group relocation table entry corresponding to
3364 the name in the assembler source. Next, we parse the
3366 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3368 set_syntax_error (_("invalid relocation expression"));
3372 /* [Xn,#:<reloc_op>:<expr> */
3373 /* Record the load/store relocation type. */
3374 inst
.reloc
.type
= entry
->ldst_type
;
3375 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3377 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3379 set_syntax_error (_("invalid expression in the address"));
3386 if (! skip_past_char (&p
, ']'))
3388 set_syntax_error (_("']' expected"));
3392 if (skip_past_char (&p
, '!'))
3394 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3396 set_syntax_error (_("register offset not allowed in pre-indexed "
3397 "addressing mode"));
3401 operand
->addr
.writeback
= 1;
3403 else if (skip_past_comma (&p
))
3406 operand
->addr
.postind
= 1;
3407 operand
->addr
.writeback
= 1;
3409 if (operand
->addr
.preind
)
3411 set_syntax_error (_("cannot combine pre- and post-indexing"));
3415 if (accept_reg_post_index
3416 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3417 &isregzero
)) != PARSE_FAIL
)
3422 set_syntax_error (_("invalid 32-bit register offset"));
3425 operand
->addr
.offset
.regno
= reg
;
3426 operand
->addr
.offset
.is_reg
= 1;
3428 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3431 set_syntax_error (_("invalid expression in the address"));
3436 /* If at this point neither .preind nor .postind is set, we have a
3437 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3438 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3440 if (operand
->addr
.writeback
)
3443 set_syntax_error (_("missing offset in the pre-indexed address"));
3446 operand
->addr
.preind
= 1;
3447 inst
.reloc
.exp
.X_op
= O_constant
;
3448 inst
.reloc
.exp
.X_add_number
= 0;
3455 /* Return TRUE on success; otherwise return FALSE. */
3457 parse_address (char **str
, aarch64_opnd_info
*operand
,
3458 int accept_reg_post_index
)
3460 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3463 /* Return TRUE on success; otherwise return FALSE. */
3465 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3467 return parse_address_main (str
, operand
, 1, 0);
3470 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3471 Return TRUE on success; otherwise return FALSE. */
3473 parse_half (char **str
, int *internal_fixup_p
)
3479 skip_past_char (&p
, '#');
3481 gas_assert (internal_fixup_p
);
3482 *internal_fixup_p
= 0;
3486 struct reloc_table_entry
*entry
;
3488 /* Try to parse a relocation. Anything else is an error. */
3490 if (!(entry
= find_reloc_table_entry (&p
)))
3492 set_syntax_error (_("unknown relocation modifier"));
3496 if (entry
->movw_type
== 0)
3499 (_("this relocation modifier is not allowed on this instruction"));
3503 inst
.reloc
.type
= entry
->movw_type
;
3506 *internal_fixup_p
= 1;
3508 /* Avoid parsing a register as a general symbol. */
3510 if (aarch64_reg_parse_32_64 (&p
, 0, 0, &dummy
, &dummy
) != PARSE_FAIL
)
3514 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3521 /* Parse an operand for an ADRP instruction:
3523 Return TRUE on success; otherwise return FALSE. */
3526 parse_adrp (char **str
)
3533 struct reloc_table_entry
*entry
;
3535 /* Try to parse a relocation. Anything else is an error. */
3537 if (!(entry
= find_reloc_table_entry (&p
)))
3539 set_syntax_error (_("unknown relocation modifier"));
3543 if (entry
->adrp_type
== 0)
3546 (_("this relocation modifier is not allowed on this instruction"));
3550 inst
.reloc
.type
= entry
->adrp_type
;
3553 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3555 inst
.reloc
.pc_rel
= 1;
3557 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3564 /* Miscellaneous. */
3566 /* Parse an option for a preload instruction. Returns the encoding for the
3567 option, or PARSE_FAIL. */
3570 parse_pldop (char **str
)
3573 const struct aarch64_name_value_pair
*o
;
3576 while (ISALNUM (*q
))
3579 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3587 /* Parse an option for a barrier instruction. Returns the encoding for the
3588 option, or PARSE_FAIL. */
3591 parse_barrier (char **str
)
3594 const asm_barrier_opt
*o
;
3597 while (ISALPHA (*q
))
3600 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3608 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3609 return 0 if successful. Otherwise return PARSE_FAIL. */
3612 parse_barrier_psb (char **str
,
3613 const struct aarch64_name_value_pair
** hint_opt
)
3616 const struct aarch64_name_value_pair
*o
;
3619 while (ISALPHA (*q
))
3622 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3625 set_fatal_syntax_error
3626 ( _("unknown or missing option to PSB"));
3630 if (o
->value
!= 0x11)
3632 /* PSB only accepts option name 'CSYNC'. */
3634 (_("the specified option is not accepted for PSB"));
3643 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3644 Returns the encoding for the option, or PARSE_FAIL.
3646 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3647 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3649 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3650 field, otherwise as a system register.
3654 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3655 int imple_defined_p
, int pstatefield_p
)
3659 const aarch64_sys_reg
*o
;
3663 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3665 *p
++ = TOLOWER (*q
);
3667 /* Assert that BUF be large enough. */
3668 gas_assert (p
- buf
== q
- *str
);
3670 o
= hash_find (sys_regs
, buf
);
3673 if (!imple_defined_p
)
3677 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3678 unsigned int op0
, op1
, cn
, cm
, op2
;
3680 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3683 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3685 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3690 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3691 as_bad (_("selected processor does not support PSTATE field "
3693 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3694 as_bad (_("selected processor does not support system register "
3696 if (aarch64_sys_reg_deprecated_p (o
))
3697 as_warn (_("system register name '%s' is deprecated and may be "
3698 "removed in a future release"), buf
);
3706 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3707 for the option, or NULL. */
3709 static const aarch64_sys_ins_reg
*
3710 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3714 const aarch64_sys_ins_reg
*o
;
3717 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3719 *p
++ = TOLOWER (*q
);
3722 o
= hash_find (sys_ins_regs
, buf
);
3726 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
3727 as_bad (_("selected processor does not support system register "
3734 #define po_char_or_fail(chr) do { \
3735 if (! skip_past_char (&str, chr)) \
3739 #define po_reg_or_fail(regtype) do { \
3740 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3741 if (val == PARSE_FAIL) \
3743 set_default_error (); \
3748 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3749 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3750 &isreg32, &isregzero); \
3751 if (val == PARSE_FAIL) \
3753 set_default_error (); \
3756 info->reg.regno = val; \
3758 info->qualifier = AARCH64_OPND_QLF_W; \
3760 info->qualifier = AARCH64_OPND_QLF_X; \
3763 #define po_imm_nc_or_fail() do { \
3764 if (! parse_constant_immediate (&str, &val)) \
3768 #define po_imm_or_fail(min, max) do { \
3769 if (! parse_constant_immediate (&str, &val)) \
3771 if (val < min || val > max) \
3773 set_fatal_syntax_error (_("immediate value out of range "\
3774 #min " to "#max)); \
3779 #define po_misc_or_fail(expr) do { \
3784 /* encode the 12-bit imm field of Add/sub immediate */
3785 static inline uint32_t
3786 encode_addsub_imm (uint32_t imm
)
3791 /* encode the shift amount field of Add/sub immediate */
3792 static inline uint32_t
3793 encode_addsub_imm_shift_amount (uint32_t cnt
)
3799 /* encode the imm field of Adr instruction */
3800 static inline uint32_t
3801 encode_adr_imm (uint32_t imm
)
3803 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3804 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3807 /* encode the immediate field of Move wide immediate */
3808 static inline uint32_t
3809 encode_movw_imm (uint32_t imm
)
3814 /* encode the 26-bit offset of unconditional branch */
3815 static inline uint32_t
3816 encode_branch_ofs_26 (uint32_t ofs
)
3818 return ofs
& ((1 << 26) - 1);
3821 /* encode the 19-bit offset of conditional branch and compare & branch */
3822 static inline uint32_t
3823 encode_cond_branch_ofs_19 (uint32_t ofs
)
3825 return (ofs
& ((1 << 19) - 1)) << 5;
3828 /* encode the 19-bit offset of ld literal */
3829 static inline uint32_t
3830 encode_ld_lit_ofs_19 (uint32_t ofs
)
3832 return (ofs
& ((1 << 19) - 1)) << 5;
3835 /* Encode the 14-bit offset of test & branch. */
3836 static inline uint32_t
3837 encode_tst_branch_ofs_14 (uint32_t ofs
)
3839 return (ofs
& ((1 << 14) - 1)) << 5;
3842 /* Encode the 16-bit imm field of svc/hvc/smc. */
3843 static inline uint32_t
3844 encode_svc_imm (uint32_t imm
)
3849 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3850 static inline uint32_t
3851 reencode_addsub_switch_add_sub (uint32_t opcode
)
3853 return opcode
^ (1 << 30);
3856 static inline uint32_t
3857 reencode_movzn_to_movz (uint32_t opcode
)
3859 return opcode
| (1 << 30);
3862 static inline uint32_t
3863 reencode_movzn_to_movn (uint32_t opcode
)
3865 return opcode
& ~(1 << 30);
3868 /* Overall per-instruction processing. */
3870 /* We need to be able to fix up arbitrary expressions in some statements.
3871 This is so that we can handle symbols that are an arbitrary distance from
3872 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3873 which returns part of an address in a form which will be valid for
3874 a data instruction. We do this by pushing the expression into a symbol
3875 in the expr_section, and creating a fix for that. */
3878 fix_new_aarch64 (fragS
* frag
,
3880 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3890 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3894 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3901 /* Diagnostics on operands errors. */
3903 /* By default, output verbose error message.
3904 Disable the verbose error message by -mno-verbose-error. */
3905 static int verbose_error_p
= 1;
3907 #ifdef DEBUG_AARCH64
3908 /* N.B. this is only for the purpose of debugging. */
3909 const char* operand_mismatch_kind_names
[] =
3912 "AARCH64_OPDE_RECOVERABLE",
3913 "AARCH64_OPDE_SYNTAX_ERROR",
3914 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3915 "AARCH64_OPDE_INVALID_VARIANT",
3916 "AARCH64_OPDE_OUT_OF_RANGE",
3917 "AARCH64_OPDE_UNALIGNED",
3918 "AARCH64_OPDE_REG_LIST",
3919 "AARCH64_OPDE_OTHER_ERROR",
3921 #endif /* DEBUG_AARCH64 */
3923 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3925 When multiple errors of different kinds are found in the same assembly
3926 line, only the error of the highest severity will be picked up for
3927 issuing the diagnostics. */
3929 static inline bfd_boolean
3930 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3931 enum aarch64_operand_error_kind rhs
)
3933 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3934 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3935 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3936 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3937 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3938 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3939 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3940 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3944 /* Helper routine to get the mnemonic name from the assembly instruction
3945 line; should only be called for the diagnosis purpose, as there is
3946 string copy operation involved, which may affect the runtime
3947 performance if used in elsewhere. */
3950 get_mnemonic_name (const char *str
)
3952 static char mnemonic
[32];
3955 /* Get the first 15 bytes and assume that the full name is included. */
3956 strncpy (mnemonic
, str
, 31);
3957 mnemonic
[31] = '\0';
3959 /* Scan up to the end of the mnemonic, which must end in white space,
3960 '.', or end of string. */
3961 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3966 /* Append '...' to the truncated long name. */
3967 if (ptr
- mnemonic
== 31)
3968 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3974 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3976 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3977 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3980 /* Data strutures storing one user error in the assembly code related to
3983 struct operand_error_record
3985 const aarch64_opcode
*opcode
;
3986 aarch64_operand_error detail
;
3987 struct operand_error_record
*next
;
3990 typedef struct operand_error_record operand_error_record
;
3992 struct operand_errors
3994 operand_error_record
*head
;
3995 operand_error_record
*tail
;
3998 typedef struct operand_errors operand_errors
;
4000 /* Top-level data structure reporting user errors for the current line of
4002 The way md_assemble works is that all opcodes sharing the same mnemonic
4003 name are iterated to find a match to the assembly line. In this data
4004 structure, each of the such opcodes will have one operand_error_record
4005 allocated and inserted. In other words, excessive errors related with
4006 a single opcode are disregarded. */
4007 operand_errors operand_error_report
;
4009 /* Free record nodes. */
4010 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4012 /* Initialize the data structure that stores the operand mismatch
4013 information on assembling one line of the assembly code. */
4015 init_operand_error_report (void)
4017 if (operand_error_report
.head
!= NULL
)
4019 gas_assert (operand_error_report
.tail
!= NULL
);
4020 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4021 free_opnd_error_record_nodes
= operand_error_report
.head
;
4022 operand_error_report
.head
= NULL
;
4023 operand_error_report
.tail
= NULL
;
4026 gas_assert (operand_error_report
.tail
== NULL
);
4029 /* Return TRUE if some operand error has been recorded during the
4030 parsing of the current assembly line using the opcode *OPCODE;
4031 otherwise return FALSE. */
4032 static inline bfd_boolean
4033 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4035 operand_error_record
*record
= operand_error_report
.head
;
4036 return record
&& record
->opcode
== opcode
;
4039 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4040 OPCODE field is initialized with OPCODE.
4041 N.B. only one record for each opcode, i.e. the maximum of one error is
4042 recorded for each instruction template. */
4045 add_operand_error_record (const operand_error_record
* new_record
)
4047 const aarch64_opcode
*opcode
= new_record
->opcode
;
4048 operand_error_record
* record
= operand_error_report
.head
;
4050 /* The record may have been created for this opcode. If not, we need
4052 if (! opcode_has_operand_error_p (opcode
))
4054 /* Get one empty record. */
4055 if (free_opnd_error_record_nodes
== NULL
)
4057 record
= xmalloc (sizeof (operand_error_record
));
4063 record
= free_opnd_error_record_nodes
;
4064 free_opnd_error_record_nodes
= record
->next
;
4066 record
->opcode
= opcode
;
4067 /* Insert at the head. */
4068 record
->next
= operand_error_report
.head
;
4069 operand_error_report
.head
= record
;
4070 if (operand_error_report
.tail
== NULL
)
4071 operand_error_report
.tail
= record
;
4073 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4074 && record
->detail
.index
<= new_record
->detail
.index
4075 && operand_error_higher_severity_p (record
->detail
.kind
,
4076 new_record
->detail
.kind
))
4078 /* In the case of multiple errors found on operands related with a
4079 single opcode, only record the error of the leftmost operand and
4080 only if the error is of higher severity. */
4081 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4082 " the existing error %s on operand %d",
4083 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4084 new_record
->detail
.index
,
4085 operand_mismatch_kind_names
[record
->detail
.kind
],
4086 record
->detail
.index
);
4090 record
->detail
= new_record
->detail
;
4094 record_operand_error_info (const aarch64_opcode
*opcode
,
4095 aarch64_operand_error
*error_info
)
4097 operand_error_record record
;
4098 record
.opcode
= opcode
;
4099 record
.detail
= *error_info
;
4100 add_operand_error_record (&record
);
4103 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4104 error message *ERROR, for operand IDX (count from 0). */
4107 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4108 enum aarch64_operand_error_kind kind
,
4111 aarch64_operand_error info
;
4112 memset(&info
, 0, sizeof (info
));
4116 record_operand_error_info (opcode
, &info
);
4120 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4121 enum aarch64_operand_error_kind kind
,
4122 const char* error
, const int *extra_data
)
4124 aarch64_operand_error info
;
4128 info
.data
[0] = extra_data
[0];
4129 info
.data
[1] = extra_data
[1];
4130 info
.data
[2] = extra_data
[2];
4131 record_operand_error_info (opcode
, &info
);
4135 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4136 const char* error
, int lower_bound
,
4139 int data
[3] = {lower_bound
, upper_bound
, 0};
4140 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4144 /* Remove the operand error record for *OPCODE. */
4145 static void ATTRIBUTE_UNUSED
4146 remove_operand_error_record (const aarch64_opcode
*opcode
)
4148 if (opcode_has_operand_error_p (opcode
))
4150 operand_error_record
* record
= operand_error_report
.head
;
4151 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4152 operand_error_report
.head
= record
->next
;
4153 record
->next
= free_opnd_error_record_nodes
;
4154 free_opnd_error_record_nodes
= record
;
4155 if (operand_error_report
.head
== NULL
)
4157 gas_assert (operand_error_report
.tail
== record
);
4158 operand_error_report
.tail
= NULL
;
4163 /* Given the instruction in *INSTR, return the index of the best matched
4164 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4166 Return -1 if there is no qualifier sequence; return the first match
4167 if there is multiple matches found. */
4170 find_best_match (const aarch64_inst
*instr
,
4171 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4173 int i
, num_opnds
, max_num_matched
, idx
;
4175 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4178 DEBUG_TRACE ("no operand");
4182 max_num_matched
= 0;
4185 /* For each pattern. */
4186 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4189 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4191 /* Most opcodes has much fewer patterns in the list. */
4192 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
4194 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4195 if (i
!= 0 && idx
== -1)
4196 /* If nothing has been matched, return the 1st sequence. */
4201 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4202 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4205 if (num_matched
> max_num_matched
)
4207 max_num_matched
= num_matched
;
4212 DEBUG_TRACE ("return with %d", idx
);
4216 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4217 corresponding operands in *INSTR. */
4220 assign_qualifier_sequence (aarch64_inst
*instr
,
4221 const aarch64_opnd_qualifier_t
*qualifiers
)
4224 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4225 gas_assert (num_opnds
);
4226 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4227 instr
->operands
[i
].qualifier
= *qualifiers
;
4230 /* Print operands for the diagnosis purpose. */
4233 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4234 const aarch64_opnd_info
*opnds
)
4238 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4240 const size_t size
= 128;
4243 /* We regard the opcode operand info more, however we also look into
4244 the inst->operands to support the disassembling of the optional
4246 The two operand code should be the same in all cases, apart from
4247 when the operand can be optional. */
4248 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4249 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4252 /* Generate the operand string in STR. */
4253 aarch64_print_operand (str
, size
, 0, opcode
, opnds
, i
, NULL
, NULL
);
4257 strcat (buf
, i
== 0 ? " " : ",");
4259 /* Append the operand string. */
4264 /* Send to stderr a string as information. */
4267 output_info (const char *format
, ...)
4273 as_where (&file
, &line
);
4277 fprintf (stderr
, "%s:%u: ", file
, line
);
4279 fprintf (stderr
, "%s: ", file
);
4281 fprintf (stderr
, _("Info: "));
4282 va_start (args
, format
);
4283 vfprintf (stderr
, format
, args
);
4285 (void) putc ('\n', stderr
);
4288 /* Output one operand error record. */
4291 output_operand_error_record (const operand_error_record
*record
, char *str
)
4293 const aarch64_operand_error
*detail
= &record
->detail
;
4294 int idx
= detail
->index
;
4295 const aarch64_opcode
*opcode
= record
->opcode
;
4296 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4297 : AARCH64_OPND_NIL
);
4299 switch (detail
->kind
)
4301 case AARCH64_OPDE_NIL
:
4305 case AARCH64_OPDE_SYNTAX_ERROR
:
4306 case AARCH64_OPDE_RECOVERABLE
:
4307 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4308 case AARCH64_OPDE_OTHER_ERROR
:
4309 /* Use the prepared error message if there is, otherwise use the
4310 operand description string to describe the error. */
4311 if (detail
->error
!= NULL
)
4314 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4316 as_bad (_("%s at operand %d -- `%s'"),
4317 detail
->error
, idx
+ 1, str
);
4321 gas_assert (idx
>= 0);
4322 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4323 aarch64_get_operand_desc (opd_code
), str
);
4327 case AARCH64_OPDE_INVALID_VARIANT
:
4328 as_bad (_("operand mismatch -- `%s'"), str
);
4329 if (verbose_error_p
)
4331 /* We will try to correct the erroneous instruction and also provide
4332 more information e.g. all other valid variants.
4334 The string representation of the corrected instruction and other
4335 valid variants are generated by
4337 1) obtaining the intermediate representation of the erroneous
4339 2) manipulating the IR, e.g. replacing the operand qualifier;
4340 3) printing out the instruction by calling the printer functions
4341 shared with the disassembler.
4343 The limitation of this method is that the exact input assembly
4344 line cannot be accurately reproduced in some cases, for example an
4345 optional operand present in the actual assembly line will be
4346 omitted in the output; likewise for the optional syntax rules,
4347 e.g. the # before the immediate. Another limitation is that the
4348 assembly symbols and relocation operations in the assembly line
4349 currently cannot be printed out in the error report. Last but not
4350 least, when there is other error(s) co-exist with this error, the
4351 'corrected' instruction may be still incorrect, e.g. given
4352 'ldnp h0,h1,[x0,#6]!'
4353 this diagnosis will provide the version:
4354 'ldnp s0,s1,[x0,#6]!'
4355 which is still not right. */
4356 size_t len
= strlen (get_mnemonic_name (str
));
4359 const size_t size
= 2048;
4361 aarch64_inst
*inst_base
= &inst
.base
;
4362 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4365 reset_aarch64_instruction (&inst
);
4366 inst_base
->opcode
= opcode
;
4368 /* Reset the error report so that there is no side effect on the
4369 following operand parsing. */
4370 init_operand_error_report ();
4373 result
= parse_operands (str
+ len
, opcode
)
4374 && programmer_friendly_fixup (&inst
);
4375 gas_assert (result
);
4376 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4378 gas_assert (!result
);
4380 /* Find the most matched qualifier sequence. */
4381 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4382 gas_assert (qlf_idx
> -1);
4384 /* Assign the qualifiers. */
4385 assign_qualifier_sequence (inst_base
,
4386 opcode
->qualifiers_list
[qlf_idx
]);
4388 /* Print the hint. */
4389 output_info (_(" did you mean this?"));
4390 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4391 print_operands (buf
, opcode
, inst_base
->operands
);
4392 output_info (_(" %s"), buf
);
4394 /* Print out other variant(s) if there is any. */
4396 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4397 output_info (_(" other valid variant(s):"));
4399 /* For each pattern. */
4400 qualifiers_list
= opcode
->qualifiers_list
;
4401 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4403 /* Most opcodes has much fewer patterns in the list.
4404 First NIL qualifier indicates the end in the list. */
4405 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4410 /* Mnemonics name. */
4411 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4413 /* Assign the qualifiers. */
4414 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4416 /* Print instruction. */
4417 print_operands (buf
, opcode
, inst_base
->operands
);
4419 output_info (_(" %s"), buf
);
4425 case AARCH64_OPDE_OUT_OF_RANGE
:
4426 if (detail
->data
[0] != detail
->data
[1])
4427 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4428 detail
->error
? detail
->error
: _("immediate value"),
4429 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4431 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4432 detail
->error
? detail
->error
: _("immediate value"),
4433 detail
->data
[0], idx
+ 1, str
);
4436 case AARCH64_OPDE_REG_LIST
:
4437 if (detail
->data
[0] == 1)
4438 as_bad (_("invalid number of registers in the list; "
4439 "only 1 register is expected at operand %d -- `%s'"),
4442 as_bad (_("invalid number of registers in the list; "
4443 "%d registers are expected at operand %d -- `%s'"),
4444 detail
->data
[0], idx
+ 1, str
);
4447 case AARCH64_OPDE_UNALIGNED
:
4448 as_bad (_("immediate value should be a multiple of "
4449 "%d at operand %d -- `%s'"),
4450 detail
->data
[0], idx
+ 1, str
);
4459 /* Process and output the error message about the operand mismatching.
4461 When this function is called, the operand error information had
4462 been collected for an assembly line and there will be multiple
4463 errors in the case of mulitple instruction templates; output the
4464 error message that most closely describes the problem. */
4467 output_operand_error_report (char *str
)
4469 int largest_error_pos
;
4470 const char *msg
= NULL
;
4471 enum aarch64_operand_error_kind kind
;
4472 operand_error_record
*curr
;
4473 operand_error_record
*head
= operand_error_report
.head
;
4474 operand_error_record
*record
= NULL
;
4476 /* No error to report. */
4480 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4482 /* Only one error. */
4483 if (head
== operand_error_report
.tail
)
4485 DEBUG_TRACE ("single opcode entry with error kind: %s",
4486 operand_mismatch_kind_names
[head
->detail
.kind
]);
4487 output_operand_error_record (head
, str
);
4491 /* Find the error kind of the highest severity. */
4492 DEBUG_TRACE ("multiple opcode entres with error kind");
4493 kind
= AARCH64_OPDE_NIL
;
4494 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4496 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4497 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4498 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4499 kind
= curr
->detail
.kind
;
4501 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4503 /* Pick up one of errors of KIND to report. */
4504 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4505 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4507 if (curr
->detail
.kind
!= kind
)
4509 /* If there are multiple errors, pick up the one with the highest
4510 mismatching operand index. In the case of multiple errors with
4511 the equally highest operand index, pick up the first one or the
4512 first one with non-NULL error message. */
4513 if (curr
->detail
.index
> largest_error_pos
4514 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4515 && curr
->detail
.error
!= NULL
))
4517 largest_error_pos
= curr
->detail
.index
;
4519 msg
= record
->detail
.error
;
4523 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4524 DEBUG_TRACE ("Pick up error kind %s to report",
4525 operand_mismatch_kind_names
[record
->detail
.kind
]);
4528 output_operand_error_record (record
, str
);
4531 /* Write an AARCH64 instruction to buf - always little-endian. */
4533 put_aarch64_insn (char *buf
, uint32_t insn
)
4535 unsigned char *where
= (unsigned char *) buf
;
4537 where
[1] = insn
>> 8;
4538 where
[2] = insn
>> 16;
4539 where
[3] = insn
>> 24;
4543 get_aarch64_insn (char *buf
)
4545 unsigned char *where
= (unsigned char *) buf
;
4547 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4552 output_inst (struct aarch64_inst
*new_inst
)
4556 to
= frag_more (INSN_SIZE
);
4558 frag_now
->tc_frag_data
.recorded
= 1;
4560 put_aarch64_insn (to
, inst
.base
.value
);
4562 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4564 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4565 INSN_SIZE
, &inst
.reloc
.exp
,
4568 DEBUG_TRACE ("Prepared relocation fix up");
4569 /* Don't check the addend value against the instruction size,
4570 that's the job of our code in md_apply_fix(). */
4571 fixp
->fx_no_overflow
= 1;
4572 if (new_inst
!= NULL
)
4573 fixp
->tc_fix_data
.inst
= new_inst
;
4574 if (aarch64_gas_internal_fixup_p ())
4576 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4577 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4578 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4582 dwarf2_emit_insn (INSN_SIZE
);
4585 /* Link together opcodes of the same name. */
4589 aarch64_opcode
*opcode
;
4590 struct templates
*next
;
4593 typedef struct templates templates
;
4596 lookup_mnemonic (const char *start
, int len
)
4598 templates
*templ
= NULL
;
4600 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4604 /* Subroutine of md_assemble, responsible for looking up the primary
4605 opcode from the mnemonic the user wrote. STR points to the
4606 beginning of the mnemonic. */
4609 opcode_lookup (char **str
)
4612 const aarch64_cond
*cond
;
4616 /* Scan up to the end of the mnemonic, which must end in white space,
4617 '.', or end of string. */
4618 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4625 inst
.cond
= COND_ALWAYS
;
4627 /* Handle a possible condition. */
4630 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4633 inst
.cond
= cond
->value
;
4647 if (inst
.cond
== COND_ALWAYS
)
4649 /* Look for unaffixed mnemonic. */
4650 return lookup_mnemonic (base
, len
);
4654 /* append ".c" to mnemonic if conditional */
4655 memcpy (condname
, base
, len
);
4656 memcpy (condname
+ len
, ".c", 2);
4659 return lookup_mnemonic (base
, len
);
4665 /* Internal helper routine converting a vector neon_type_el structure
4666 *VECTYPE to a corresponding operand qualifier. */
4668 static inline aarch64_opnd_qualifier_t
4669 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4671 /* Element size in bytes indexed by neon_el_type. */
4672 const unsigned char ele_size
[5]
4674 const unsigned int ele_base
[5] =
4676 AARCH64_OPND_QLF_V_8B
,
4677 AARCH64_OPND_QLF_V_4H
,
4678 AARCH64_OPND_QLF_V_2S
,
4679 AARCH64_OPND_QLF_V_1D
,
4680 AARCH64_OPND_QLF_V_1Q
4683 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4684 goto vectype_conversion_fail
;
4686 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4688 if (vectype
->defined
& NTA_HASINDEX
)
4689 /* Vector element register. */
4690 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4693 /* Vector register. */
4694 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4697 if (reg_size
!= 16 && reg_size
!= 8)
4698 goto vectype_conversion_fail
;
4700 /* The conversion is by calculating the offset from the base operand
4701 qualifier for the vector type. The operand qualifiers are regular
4702 enough that the offset can established by shifting the vector width by
4703 a vector-type dependent amount. */
4705 if (vectype
->type
== NT_b
)
4707 else if (vectype
->type
== NT_h
)
4709 else if (vectype
->type
== NT_s
)
4711 else if (vectype
->type
>= NT_d
)
4716 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
4717 gas_assert (AARCH64_OPND_QLF_V_8B
<= offset
4718 && offset
<= AARCH64_OPND_QLF_V_1Q
);
4722 vectype_conversion_fail
:
4723 first_error (_("bad vector arrangement type"));
4724 return AARCH64_OPND_QLF_NIL
;
4727 /* Process an optional operand that is found omitted from the assembly line.
4728 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4729 instruction's opcode entry while IDX is the index of this omitted operand.
4733 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4734 int idx
, aarch64_opnd_info
*operand
)
4736 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4737 gas_assert (optional_operand_p (opcode
, idx
));
4738 gas_assert (!operand
->present
);
4742 case AARCH64_OPND_Rd
:
4743 case AARCH64_OPND_Rn
:
4744 case AARCH64_OPND_Rm
:
4745 case AARCH64_OPND_Rt
:
4746 case AARCH64_OPND_Rt2
:
4747 case AARCH64_OPND_Rs
:
4748 case AARCH64_OPND_Ra
:
4749 case AARCH64_OPND_Rt_SYS
:
4750 case AARCH64_OPND_Rd_SP
:
4751 case AARCH64_OPND_Rn_SP
:
4752 case AARCH64_OPND_Fd
:
4753 case AARCH64_OPND_Fn
:
4754 case AARCH64_OPND_Fm
:
4755 case AARCH64_OPND_Fa
:
4756 case AARCH64_OPND_Ft
:
4757 case AARCH64_OPND_Ft2
:
4758 case AARCH64_OPND_Sd
:
4759 case AARCH64_OPND_Sn
:
4760 case AARCH64_OPND_Sm
:
4761 case AARCH64_OPND_Vd
:
4762 case AARCH64_OPND_Vn
:
4763 case AARCH64_OPND_Vm
:
4764 case AARCH64_OPND_VdD1
:
4765 case AARCH64_OPND_VnD1
:
4766 operand
->reg
.regno
= default_value
;
4769 case AARCH64_OPND_Ed
:
4770 case AARCH64_OPND_En
:
4771 case AARCH64_OPND_Em
:
4772 operand
->reglane
.regno
= default_value
;
4775 case AARCH64_OPND_IDX
:
4776 case AARCH64_OPND_BIT_NUM
:
4777 case AARCH64_OPND_IMMR
:
4778 case AARCH64_OPND_IMMS
:
4779 case AARCH64_OPND_SHLL_IMM
:
4780 case AARCH64_OPND_IMM_VLSL
:
4781 case AARCH64_OPND_IMM_VLSR
:
4782 case AARCH64_OPND_CCMP_IMM
:
4783 case AARCH64_OPND_FBITS
:
4784 case AARCH64_OPND_UIMM4
:
4785 case AARCH64_OPND_UIMM3_OP1
:
4786 case AARCH64_OPND_UIMM3_OP2
:
4787 case AARCH64_OPND_IMM
:
4788 case AARCH64_OPND_WIDTH
:
4789 case AARCH64_OPND_UIMM7
:
4790 case AARCH64_OPND_NZCV
:
4791 operand
->imm
.value
= default_value
;
4794 case AARCH64_OPND_EXCEPTION
:
4795 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4798 case AARCH64_OPND_BARRIER_ISB
:
4799 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4806 /* Process the relocation type for move wide instructions.
4807 Return TRUE on success; otherwise return FALSE. */
4810 process_movw_reloc_info (void)
4815 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4817 if (inst
.base
.opcode
->op
== OP_MOVK
)
4818 switch (inst
.reloc
.type
)
4820 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4821 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4822 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4823 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4824 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4825 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4826 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4828 (_("the specified relocation type is not allowed for MOVK"));
4834 switch (inst
.reloc
.type
)
4836 case BFD_RELOC_AARCH64_MOVW_G0
:
4837 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4838 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4839 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
4840 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
4841 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
4842 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
4843 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
4844 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
4845 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4846 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4849 case BFD_RELOC_AARCH64_MOVW_G1
:
4850 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4851 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4852 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
4853 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
4854 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4855 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
4856 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
4857 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
4858 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4859 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4862 case BFD_RELOC_AARCH64_MOVW_G2
:
4863 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4864 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4865 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
4866 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4869 set_fatal_syntax_error
4870 (_("the specified relocation type is not allowed for 32-bit "
4876 case BFD_RELOC_AARCH64_MOVW_G3
:
4879 set_fatal_syntax_error
4880 (_("the specified relocation type is not allowed for 32-bit "
4887 /* More cases should be added when more MOVW-related relocation types
4888 are supported in GAS. */
4889 gas_assert (aarch64_gas_internal_fixup_p ());
4890 /* The shift amount should have already been set by the parser. */
4893 inst
.base
.operands
[1].shifter
.amount
= shift
;
4897 /* A primitive log caculator. */
4899 static inline unsigned int
4900 get_logsz (unsigned int size
)
4902 const unsigned char ls
[16] =
4903 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4909 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4910 return ls
[size
- 1];
4913 /* Determine and return the real reloc type code for an instruction
4914 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4916 static inline bfd_reloc_code_real_type
4917 ldst_lo12_determine_real_reloc_type (void)
4920 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4921 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4923 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
4925 BFD_RELOC_AARCH64_LDST8_LO12
,
4926 BFD_RELOC_AARCH64_LDST16_LO12
,
4927 BFD_RELOC_AARCH64_LDST32_LO12
,
4928 BFD_RELOC_AARCH64_LDST64_LO12
,
4929 BFD_RELOC_AARCH64_LDST128_LO12
4932 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
4933 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
4934 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
4935 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
4936 BFD_RELOC_AARCH64_NONE
4939 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
4940 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
4941 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
4942 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
4943 BFD_RELOC_AARCH64_NONE
4947 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
4948 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4950 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
4951 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4953 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4955 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4957 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4959 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4960 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4961 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
4962 gas_assert (logsz
<= 3);
4964 gas_assert (logsz
<= 4);
4966 /* In reloc.c, these pseudo relocation types should be defined in similar
4967 order as above reloc_ldst_lo12 array. Because the array index calcuation
4968 below relies on this. */
4969 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
4972 /* Check whether a register list REGINFO is valid. The registers must be
4973 numbered in increasing order (modulo 32), in increments of one or two.
4975 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4978 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4981 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4983 uint32_t i
, nb_regs
, prev_regno
, incr
;
4985 nb_regs
= 1 + (reginfo
& 0x3);
4987 prev_regno
= reginfo
& 0x1f;
4988 incr
= accept_alternate
? 2 : 1;
4990 for (i
= 1; i
< nb_regs
; ++i
)
4992 uint32_t curr_regno
;
4994 curr_regno
= reginfo
& 0x1f;
4995 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4997 prev_regno
= curr_regno
;
5003 /* Generic instruction operand parser. This does no encoding and no
5004 semantic validation; it merely squirrels values away in the inst
5005 structure. Returns TRUE or FALSE depending on whether the
5006 specified grammar matched. */
5009 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5012 char *backtrack_pos
= 0;
5013 const enum aarch64_opnd
*operands
= opcode
->operands
;
5016 skip_whitespace (str
);
5018 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5021 int isreg32
, isregzero
;
5022 int comma_skipped_p
= 0;
5023 aarch64_reg_type rtype
;
5024 struct neon_type_el vectype
;
5025 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5027 DEBUG_TRACE ("parse operand %d", i
);
5029 /* Assign the operand code. */
5030 info
->type
= operands
[i
];
5032 if (optional_operand_p (opcode
, i
))
5034 /* Remember where we are in case we need to backtrack. */
5035 gas_assert (!backtrack_pos
);
5036 backtrack_pos
= str
;
5039 /* Expect comma between operands; the backtrack mechanizm will take
5040 care of cases of omitted optional operand. */
5041 if (i
> 0 && ! skip_past_char (&str
, ','))
5043 set_syntax_error (_("comma expected between operands"));
5047 comma_skipped_p
= 1;
5049 switch (operands
[i
])
5051 case AARCH64_OPND_Rd
:
5052 case AARCH64_OPND_Rn
:
5053 case AARCH64_OPND_Rm
:
5054 case AARCH64_OPND_Rt
:
5055 case AARCH64_OPND_Rt2
:
5056 case AARCH64_OPND_Rs
:
5057 case AARCH64_OPND_Ra
:
5058 case AARCH64_OPND_Rt_SYS
:
5059 case AARCH64_OPND_PAIRREG
:
5060 po_int_reg_or_fail (1, 0);
5063 case AARCH64_OPND_Rd_SP
:
5064 case AARCH64_OPND_Rn_SP
:
5065 po_int_reg_or_fail (0, 1);
5068 case AARCH64_OPND_Rm_EXT
:
5069 case AARCH64_OPND_Rm_SFT
:
5070 po_misc_or_fail (parse_shifter_operand
5071 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5073 : SHIFTED_LOGIC_IMM
)));
5074 if (!info
->shifter
.operator_present
)
5076 /* Default to LSL if not present. Libopcodes prefers shifter
5077 kind to be explicit. */
5078 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5079 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5080 /* For Rm_EXT, libopcodes will carry out further check on whether
5081 or not stack pointer is used in the instruction (Recall that
5082 "the extend operator is not optional unless at least one of
5083 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5087 case AARCH64_OPND_Fd
:
5088 case AARCH64_OPND_Fn
:
5089 case AARCH64_OPND_Fm
:
5090 case AARCH64_OPND_Fa
:
5091 case AARCH64_OPND_Ft
:
5092 case AARCH64_OPND_Ft2
:
5093 case AARCH64_OPND_Sd
:
5094 case AARCH64_OPND_Sn
:
5095 case AARCH64_OPND_Sm
:
5096 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5097 if (val
== PARSE_FAIL
)
5099 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5102 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5104 info
->reg
.regno
= val
;
5105 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5108 case AARCH64_OPND_Vd
:
5109 case AARCH64_OPND_Vn
:
5110 case AARCH64_OPND_Vm
:
5111 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5112 if (val
== PARSE_FAIL
)
5114 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5117 if (vectype
.defined
& NTA_HASINDEX
)
5120 info
->reg
.regno
= val
;
5121 info
->qualifier
= vectype_to_qualifier (&vectype
);
5122 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5126 case AARCH64_OPND_VdD1
:
5127 case AARCH64_OPND_VnD1
:
5128 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5129 if (val
== PARSE_FAIL
)
5131 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5134 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5136 set_fatal_syntax_error
5137 (_("the top half of a 128-bit FP/SIMD register is expected"));
5140 info
->reg
.regno
= val
;
5141 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5142 here; it is correct for the purpose of encoding/decoding since
5143 only the register number is explicitly encoded in the related
5144 instructions, although this appears a bit hacky. */
5145 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5148 case AARCH64_OPND_Ed
:
5149 case AARCH64_OPND_En
:
5150 case AARCH64_OPND_Em
:
5151 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5152 if (val
== PARSE_FAIL
)
5154 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5157 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5160 info
->reglane
.regno
= val
;
5161 info
->reglane
.index
= vectype
.index
;
5162 info
->qualifier
= vectype_to_qualifier (&vectype
);
5163 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5167 case AARCH64_OPND_LVn
:
5168 case AARCH64_OPND_LVt
:
5169 case AARCH64_OPND_LVt_AL
:
5170 case AARCH64_OPND_LEt
:
5171 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
5173 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5175 set_fatal_syntax_error (_("invalid register list"));
5178 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5179 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5180 if (operands
[i
] == AARCH64_OPND_LEt
)
5182 if (!(vectype
.defined
& NTA_HASINDEX
))
5184 info
->reglist
.has_index
= 1;
5185 info
->reglist
.index
= vectype
.index
;
5187 else if (!(vectype
.defined
& NTA_HASTYPE
))
5189 info
->qualifier
= vectype_to_qualifier (&vectype
);
5190 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5194 case AARCH64_OPND_Cn
:
5195 case AARCH64_OPND_Cm
:
5196 po_reg_or_fail (REG_TYPE_CN
);
5199 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
5202 inst
.base
.operands
[i
].reg
.regno
= val
;
5205 case AARCH64_OPND_SHLL_IMM
:
5206 case AARCH64_OPND_IMM_VLSR
:
5207 po_imm_or_fail (1, 64);
5208 info
->imm
.value
= val
;
5211 case AARCH64_OPND_CCMP_IMM
:
5212 case AARCH64_OPND_FBITS
:
5213 case AARCH64_OPND_UIMM4
:
5214 case AARCH64_OPND_UIMM3_OP1
:
5215 case AARCH64_OPND_UIMM3_OP2
:
5216 case AARCH64_OPND_IMM_VLSL
:
5217 case AARCH64_OPND_IMM
:
5218 case AARCH64_OPND_WIDTH
:
5219 po_imm_nc_or_fail ();
5220 info
->imm
.value
= val
;
5223 case AARCH64_OPND_UIMM7
:
5224 po_imm_or_fail (0, 127);
5225 info
->imm
.value
= val
;
5228 case AARCH64_OPND_IDX
:
5229 case AARCH64_OPND_BIT_NUM
:
5230 case AARCH64_OPND_IMMR
:
5231 case AARCH64_OPND_IMMS
:
5232 po_imm_or_fail (0, 63);
5233 info
->imm
.value
= val
;
5236 case AARCH64_OPND_IMM0
:
5237 po_imm_nc_or_fail ();
5240 set_fatal_syntax_error (_("immediate zero expected"));
5243 info
->imm
.value
= 0;
5246 case AARCH64_OPND_FPIMM0
:
5249 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5250 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5251 it is probably not worth the effort to support it. */
5252 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
5253 && !(res2
= parse_constant_immediate (&str
, &val
)))
5255 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5257 info
->imm
.value
= 0;
5258 info
->imm
.is_fp
= 1;
5261 set_fatal_syntax_error (_("immediate zero expected"));
5265 case AARCH64_OPND_IMM_MOV
:
5268 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5269 reg_name_p (str
, REG_TYPE_VN
))
5272 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5274 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5275 later. fix_mov_imm_insn will try to determine a machine
5276 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5277 message if the immediate cannot be moved by a single
5279 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5280 inst
.base
.operands
[i
].skip
= 1;
5284 case AARCH64_OPND_SIMD_IMM
:
5285 case AARCH64_OPND_SIMD_IMM_SFT
:
5286 if (! parse_big_immediate (&str
, &val
))
5288 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5290 /* need_libopcodes_p */ 1,
5293 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5294 shift, we don't check it here; we leave the checking to
5295 the libopcodes (operand_general_constraint_met_p). By
5296 doing this, we achieve better diagnostics. */
5297 if (skip_past_comma (&str
)
5298 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5300 if (!info
->shifter
.operator_present
5301 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5303 /* Default to LSL if not present. Libopcodes prefers shifter
5304 kind to be explicit. */
5305 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5306 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5310 case AARCH64_OPND_FPIMM
:
5311 case AARCH64_OPND_SIMD_FPIMM
:
5315 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
5317 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
5321 set_fatal_syntax_error (_("invalid floating-point constant"));
5324 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5325 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5329 case AARCH64_OPND_LIMM
:
5330 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5331 SHIFTED_LOGIC_IMM
));
5332 if (info
->shifter
.operator_present
)
5334 set_fatal_syntax_error
5335 (_("shift not allowed for bitmask immediate"));
5338 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5340 /* need_libopcodes_p */ 1,
5344 case AARCH64_OPND_AIMM
:
5345 if (opcode
->op
== OP_ADD
)
5346 /* ADD may have relocation types. */
5347 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5348 SHIFTED_ARITH_IMM
));
5350 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5351 SHIFTED_ARITH_IMM
));
5352 switch (inst
.reloc
.type
)
5354 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5355 info
->shifter
.amount
= 12;
5357 case BFD_RELOC_UNUSED
:
5358 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5359 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5360 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5361 inst
.reloc
.pc_rel
= 0;
5366 info
->imm
.value
= 0;
5367 if (!info
->shifter
.operator_present
)
5369 /* Default to LSL if not present. Libopcodes prefers shifter
5370 kind to be explicit. */
5371 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5372 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5376 case AARCH64_OPND_HALF
:
5378 /* #<imm16> or relocation. */
5379 int internal_fixup_p
;
5380 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5381 if (internal_fixup_p
)
5382 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5383 skip_whitespace (str
);
5384 if (skip_past_comma (&str
))
5386 /* {, LSL #<shift>} */
5387 if (! aarch64_gas_internal_fixup_p ())
5389 set_fatal_syntax_error (_("can't mix relocation modifier "
5390 "with explicit shift"));
5393 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5396 inst
.base
.operands
[i
].shifter
.amount
= 0;
5397 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5398 inst
.base
.operands
[i
].imm
.value
= 0;
5399 if (! process_movw_reloc_info ())
5404 case AARCH64_OPND_EXCEPTION
:
5405 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
5406 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5408 /* need_libopcodes_p */ 0,
5412 case AARCH64_OPND_NZCV
:
5414 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5418 info
->imm
.value
= nzcv
->value
;
5421 po_imm_or_fail (0, 15);
5422 info
->imm
.value
= val
;
5426 case AARCH64_OPND_COND
:
5427 case AARCH64_OPND_COND1
:
5428 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5430 if (info
->cond
== NULL
)
5432 set_syntax_error (_("invalid condition"));
5435 else if (operands
[i
] == AARCH64_OPND_COND1
5436 && (info
->cond
->value
& 0xe) == 0xe)
5438 /* Not allow AL or NV. */
5439 set_default_error ();
5444 case AARCH64_OPND_ADDR_ADRP
:
5445 po_misc_or_fail (parse_adrp (&str
));
5446 /* Clear the value as operand needs to be relocated. */
5447 info
->imm
.value
= 0;
5450 case AARCH64_OPND_ADDR_PCREL14
:
5451 case AARCH64_OPND_ADDR_PCREL19
:
5452 case AARCH64_OPND_ADDR_PCREL21
:
5453 case AARCH64_OPND_ADDR_PCREL26
:
5454 po_misc_or_fail (parse_address_reloc (&str
, info
));
5455 if (!info
->addr
.pcrel
)
5457 set_syntax_error (_("invalid pc-relative address"));
5460 if (inst
.gen_lit_pool
5461 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5463 /* Only permit "=value" in the literal load instructions.
5464 The literal will be generated by programmer_friendly_fixup. */
5465 set_syntax_error (_("invalid use of \"=immediate\""));
5468 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5470 set_syntax_error (_("unrecognized relocation suffix"));
5473 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5475 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5476 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5480 info
->imm
.value
= 0;
5481 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5482 switch (opcode
->iclass
)
5486 /* e.g. CBZ or B.COND */
5487 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5488 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5492 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5493 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5497 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5499 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5500 : BFD_RELOC_AARCH64_JUMP26
;
5503 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5504 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5507 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5508 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5514 inst
.reloc
.pc_rel
= 1;
5518 case AARCH64_OPND_ADDR_SIMPLE
:
5519 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5520 /* [<Xn|SP>{, #<simm>}] */
5521 po_char_or_fail ('[');
5522 po_reg_or_fail (REG_TYPE_R64_SP
);
5523 /* Accept optional ", #0". */
5524 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5525 && skip_past_char (&str
, ','))
5527 skip_past_char (&str
, '#');
5528 if (! skip_past_char (&str
, '0'))
5530 set_fatal_syntax_error
5531 (_("the optional immediate offset can only be 0"));
5535 po_char_or_fail (']');
5536 info
->addr
.base_regno
= val
;
5539 case AARCH64_OPND_ADDR_REGOFF
:
5540 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5541 po_misc_or_fail (parse_address (&str
, info
, 0));
5542 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5543 || !info
->addr
.preind
|| info
->addr
.postind
5544 || info
->addr
.writeback
)
5546 set_syntax_error (_("invalid addressing mode"));
5549 if (!info
->shifter
.operator_present
)
5551 /* Default to LSL if not present. Libopcodes prefers shifter
5552 kind to be explicit. */
5553 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5554 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5556 /* Qualifier to be deduced by libopcodes. */
5559 case AARCH64_OPND_ADDR_SIMM7
:
5560 po_misc_or_fail (parse_address (&str
, info
, 0));
5561 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5562 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5564 set_syntax_error (_("invalid addressing mode"));
5567 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5569 /* need_libopcodes_p */ 1,
5573 case AARCH64_OPND_ADDR_SIMM9
:
5574 case AARCH64_OPND_ADDR_SIMM9_2
:
5575 po_misc_or_fail (parse_address_reloc (&str
, info
));
5576 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5577 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5578 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5579 && info
->addr
.writeback
))
5581 set_syntax_error (_("invalid addressing mode"));
5584 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5586 set_syntax_error (_("relocation not allowed"));
5589 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5591 /* need_libopcodes_p */ 1,
5595 case AARCH64_OPND_ADDR_UIMM12
:
5596 po_misc_or_fail (parse_address_reloc (&str
, info
));
5597 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5598 || !info
->addr
.preind
|| info
->addr
.writeback
)
5600 set_syntax_error (_("invalid addressing mode"));
5603 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5604 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5605 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5607 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
5609 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
5610 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5611 /* Leave qualifier to be determined by libopcodes. */
5614 case AARCH64_OPND_SIMD_ADDR_POST
:
5615 /* [<Xn|SP>], <Xm|#<amount>> */
5616 po_misc_or_fail (parse_address (&str
, info
, 1));
5617 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5619 set_syntax_error (_("invalid addressing mode"));
5622 if (!info
->addr
.offset
.is_reg
)
5624 if (inst
.reloc
.exp
.X_op
== O_constant
)
5625 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5628 set_fatal_syntax_error
5629 (_("writeback value should be an immediate constant"));
5636 case AARCH64_OPND_SYSREG
:
5637 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
5640 set_syntax_error (_("unknown or missing system register name"));
5643 inst
.base
.operands
[i
].sysreg
= val
;
5646 case AARCH64_OPND_PSTATEFIELD
:
5647 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
5650 set_syntax_error (_("unknown or missing PSTATE field name"));
5653 inst
.base
.operands
[i
].pstatefield
= val
;
5656 case AARCH64_OPND_SYSREG_IC
:
5657 inst
.base
.operands
[i
].sysins_op
=
5658 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5660 case AARCH64_OPND_SYSREG_DC
:
5661 inst
.base
.operands
[i
].sysins_op
=
5662 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5664 case AARCH64_OPND_SYSREG_AT
:
5665 inst
.base
.operands
[i
].sysins_op
=
5666 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5668 case AARCH64_OPND_SYSREG_TLBI
:
5669 inst
.base
.operands
[i
].sysins_op
=
5670 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5672 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5674 set_fatal_syntax_error ( _("unknown or missing operation name"));
5679 case AARCH64_OPND_BARRIER
:
5680 case AARCH64_OPND_BARRIER_ISB
:
5681 val
= parse_barrier (&str
);
5682 if (val
!= PARSE_FAIL
5683 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5685 /* ISB only accepts options name 'sy'. */
5687 (_("the specified option is not accepted in ISB"));
5688 /* Turn off backtrack as this optional operand is present. */
5692 /* This is an extension to accept a 0..15 immediate. */
5693 if (val
== PARSE_FAIL
)
5694 po_imm_or_fail (0, 15);
5695 info
->barrier
= aarch64_barrier_options
+ val
;
5698 case AARCH64_OPND_PRFOP
:
5699 val
= parse_pldop (&str
);
5700 /* This is an extension to accept a 0..31 immediate. */
5701 if (val
== PARSE_FAIL
)
5702 po_imm_or_fail (0, 31);
5703 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5706 case AARCH64_OPND_BARRIER_PSB
:
5707 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
5708 if (val
== PARSE_FAIL
)
5713 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5716 /* If we get here, this operand was successfully parsed. */
5717 inst
.base
.operands
[i
].present
= 1;
5721 /* The parse routine should already have set the error, but in case
5722 not, set a default one here. */
5724 set_default_error ();
5726 if (! backtrack_pos
)
5727 goto parse_operands_return
;
5730 /* We reach here because this operand is marked as optional, and
5731 either no operand was supplied or the operand was supplied but it
5732 was syntactically incorrect. In the latter case we report an
5733 error. In the former case we perform a few more checks before
5734 dropping through to the code to insert the default operand. */
5736 char *tmp
= backtrack_pos
;
5737 char endchar
= END_OF_INSN
;
5739 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5741 skip_past_char (&tmp
, ',');
5743 if (*tmp
!= endchar
)
5744 /* The user has supplied an operand in the wrong format. */
5745 goto parse_operands_return
;
5747 /* Make sure there is not a comma before the optional operand.
5748 For example the fifth operand of 'sys' is optional:
5750 sys #0,c0,c0,#0, <--- wrong
5751 sys #0,c0,c0,#0 <--- correct. */
5752 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5754 set_fatal_syntax_error
5755 (_("unexpected comma before the omitted optional operand"));
5756 goto parse_operands_return
;
5760 /* Reaching here means we are dealing with an optional operand that is
5761 omitted from the assembly line. */
5762 gas_assert (optional_operand_p (opcode
, i
));
5764 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5766 /* Try again, skipping the optional operand at backtrack_pos. */
5767 str
= backtrack_pos
;
5770 /* Clear any error record after the omitted optional operand has been
5771 successfully handled. */
5775 /* Check if we have parsed all the operands. */
5776 if (*str
!= '\0' && ! error_p ())
5778 /* Set I to the index of the last present operand; this is
5779 for the purpose of diagnostics. */
5780 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5782 set_fatal_syntax_error
5783 (_("unexpected characters following instruction"));
5786 parse_operands_return
:
5790 DEBUG_TRACE ("parsing FAIL: %s - %s",
5791 operand_mismatch_kind_names
[get_error_kind ()],
5792 get_error_message ());
5793 /* Record the operand error properly; this is useful when there
5794 are multiple instruction templates for a mnemonic name, so that
5795 later on, we can select the error that most closely describes
5797 record_operand_error (opcode
, i
, get_error_kind (),
5798 get_error_message ());
5803 DEBUG_TRACE ("parsing SUCCESS");
5808 /* It does some fix-up to provide some programmer friendly feature while
5809 keeping the libopcodes happy, i.e. libopcodes only accepts
5810 the preferred architectural syntax.
5811 Return FALSE if there is any failure; otherwise return TRUE. */
5814 programmer_friendly_fixup (aarch64_instruction
*instr
)
5816 aarch64_inst
*base
= &instr
->base
;
5817 const aarch64_opcode
*opcode
= base
->opcode
;
5818 enum aarch64_op op
= opcode
->op
;
5819 aarch64_opnd_info
*operands
= base
->operands
;
5821 DEBUG_TRACE ("enter");
5823 switch (opcode
->iclass
)
5826 /* TBNZ Xn|Wn, #uimm6, label
5827 Test and Branch Not Zero: conditionally jumps to label if bit number
5828 uimm6 in register Xn is not zero. The bit number implies the width of
5829 the register, which may be written and should be disassembled as Wn if
5830 uimm is less than 32. */
5831 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5833 if (operands
[1].imm
.value
>= 32)
5835 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5839 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5843 /* LDR Wt, label | =value
5844 As a convenience assemblers will typically permit the notation
5845 "=value" in conjunction with the pc-relative literal load instructions
5846 to automatically place an immediate value or symbolic address in a
5847 nearby literal pool and generate a hidden label which references it.
5848 ISREG has been set to 0 in the case of =value. */
5849 if (instr
->gen_lit_pool
5850 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5852 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5853 if (op
== OP_LDRSW_LIT
)
5855 if (instr
->reloc
.exp
.X_op
!= O_constant
5856 && instr
->reloc
.exp
.X_op
!= O_big
5857 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5859 record_operand_error (opcode
, 1,
5860 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5861 _("constant expression expected"));
5864 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5866 record_operand_error (opcode
, 1,
5867 AARCH64_OPDE_OTHER_ERROR
,
5868 _("literal pool insertion failed"));
5876 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5877 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5878 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5879 A programmer-friendly assembler should accept a destination Xd in
5880 place of Wd, however that is not the preferred form for disassembly.
5882 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5883 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5884 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5885 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5890 /* In the 64-bit form, the final register operand is written as Wm
5891 for all but the (possibly omitted) UXTX/LSL and SXTX
5893 As a programmer-friendly assembler, we accept e.g.
5894 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5895 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5896 int idx
= aarch64_operand_index (opcode
->operands
,
5897 AARCH64_OPND_Rm_EXT
);
5898 gas_assert (idx
== 1 || idx
== 2);
5899 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5900 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5901 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5902 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5903 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5904 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5912 DEBUG_TRACE ("exit with SUCCESS");
5916 /* Check for loads and stores that will cause unpredictable behavior. */
5919 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5921 aarch64_inst
*base
= &instr
->base
;
5922 const aarch64_opcode
*opcode
= base
->opcode
;
5923 const aarch64_opnd_info
*opnds
= base
->operands
;
5924 switch (opcode
->iclass
)
5930 /* Loading/storing the base register is unpredictable if writeback. */
5931 if ((aarch64_get_operand_class (opnds
[0].type
)
5932 == AARCH64_OPND_CLASS_INT_REG
)
5933 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5934 && opnds
[1].addr
.base_regno
!= REG_SP
5935 && opnds
[1].addr
.writeback
)
5936 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5939 case ldstnapair_offs
:
5940 case ldstpair_indexed
:
5941 /* Loading/storing the base register is unpredictable if writeback. */
5942 if ((aarch64_get_operand_class (opnds
[0].type
)
5943 == AARCH64_OPND_CLASS_INT_REG
)
5944 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5945 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5946 && opnds
[2].addr
.base_regno
!= REG_SP
5947 && opnds
[2].addr
.writeback
)
5948 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5949 /* Load operations must load different registers. */
5950 if ((opcode
->opcode
& (1 << 22))
5951 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5952 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5959 /* A wrapper function to interface with libopcodes on encoding and
5960 record the error message if there is any.
5962 Return TRUE on success; otherwise return FALSE. */
5965 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5968 aarch64_operand_error error_info
;
5969 error_info
.kind
= AARCH64_OPDE_NIL
;
5970 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5974 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5975 record_operand_error_info (opcode
, &error_info
);
5980 #ifdef DEBUG_AARCH64
5982 dump_opcode_operands (const aarch64_opcode
*opcode
)
5985 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5987 aarch64_verbose ("\t\t opnd%d: %s", i
,
5988 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5989 ? aarch64_get_operand_name (opcode
->operands
[i
])
5990 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5994 #endif /* DEBUG_AARCH64 */
5996 /* This is the guts of the machine-dependent assembler. STR points to a
5997 machine dependent instruction. This function is supposed to emit
5998 the frags/bytes it assembles to. */
6001 md_assemble (char *str
)
6004 templates
*template;
6005 aarch64_opcode
*opcode
;
6006 aarch64_inst
*inst_base
;
6007 unsigned saved_cond
;
6009 /* Align the previous label if needed. */
6010 if (last_label_seen
!= NULL
)
6012 symbol_set_frag (last_label_seen
, frag_now
);
6013 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6014 S_SET_SEGMENT (last_label_seen
, now_seg
);
6017 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6019 DEBUG_TRACE ("\n\n");
6020 DEBUG_TRACE ("==============================");
6021 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6023 template = opcode_lookup (&p
);
6026 /* It wasn't an instruction, but it might be a register alias of
6027 the form alias .req reg directive. */
6028 if (!create_register_alias (str
, p
))
6029 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6034 skip_whitespace (p
);
6037 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6038 get_mnemonic_name (str
), str
);
6042 init_operand_error_report ();
6044 /* Sections are assumed to start aligned. In executable section, there is no
6045 MAP_DATA symbol pending. So we only align the address during
6046 MAP_DATA --> MAP_INSN transition.
6047 For other sections, this is not guaranteed. */
6048 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6049 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6050 frag_align_code (2, 0);
6052 saved_cond
= inst
.cond
;
6053 reset_aarch64_instruction (&inst
);
6054 inst
.cond
= saved_cond
;
6056 /* Iterate through all opcode entries with the same mnemonic name. */
6059 opcode
= template->opcode
;
6061 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6062 #ifdef DEBUG_AARCH64
6064 dump_opcode_operands (opcode
);
6065 #endif /* DEBUG_AARCH64 */
6067 mapping_state (MAP_INSN
);
6069 inst_base
= &inst
.base
;
6070 inst_base
->opcode
= opcode
;
6072 /* Truly conditionally executed instructions, e.g. b.cond. */
6073 if (opcode
->flags
& F_COND
)
6075 gas_assert (inst
.cond
!= COND_ALWAYS
);
6076 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6077 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6079 else if (inst
.cond
!= COND_ALWAYS
)
6081 /* It shouldn't arrive here, where the assembly looks like a
6082 conditional instruction but the found opcode is unconditional. */
6087 if (parse_operands (p
, opcode
)
6088 && programmer_friendly_fixup (&inst
)
6089 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6091 /* Check that this instruction is supported for this CPU. */
6092 if (!opcode
->avariant
6093 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
6095 as_bad (_("selected processor does not support `%s'"), str
);
6099 warn_unpredictable_ldst (&inst
, str
);
6101 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6102 || !inst
.reloc
.need_libopcodes_p
)
6106 /* If there is relocation generated for the instruction,
6107 store the instruction information for the future fix-up. */
6108 struct aarch64_inst
*copy
;
6109 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6110 if ((copy
= xmalloc (sizeof (struct aarch64_inst
))) == NULL
)
6112 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6118 template = template->next
;
6119 if (template != NULL
)
6121 reset_aarch64_instruction (&inst
);
6122 inst
.cond
= saved_cond
;
6125 while (template != NULL
);
6127 /* Issue the error messages if any. */
6128 output_operand_error_report (str
);
6131 /* Various frobbings of labels and their addresses. */
6134 aarch64_start_line_hook (void)
6136 last_label_seen
= NULL
;
6140 aarch64_frob_label (symbolS
* sym
)
6142 last_label_seen
= sym
;
6144 dwarf2_emit_label (sym
);
6148 aarch64_data_in_code (void)
6150 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6152 *input_line_pointer
= '/';
6153 input_line_pointer
+= 5;
6154 *input_line_pointer
= 0;
6162 aarch64_canonicalize_symbol_name (char *name
)
6166 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6167 *(name
+ len
- 5) = 0;
6172 /* Table of all register names defined by default. The user can
6173 define additional names with .req. Note that all register names
6174 should appear in both upper and lowercase variants. Some registers
6175 also have mixed-case names. */
6177 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6178 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6179 #define REGSET31(p,t) \
6180 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6181 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6182 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6183 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
6184 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6185 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6186 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6187 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6188 #define REGSET(p,t) \
6189 REGSET31(p,t), REGNUM(p,31,t)
6191 /* These go into aarch64_reg_hsh hash-table. */
6192 static const reg_entry reg_names
[] = {
6193 /* Integer registers. */
6194 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6195 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6197 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6198 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6200 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6201 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6203 /* Coprocessor register numbers. */
6204 REGSET (c
, CN
), REGSET (C
, CN
),
6206 /* Floating-point single precision registers. */
6207 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6209 /* Floating-point double precision registers. */
6210 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6212 /* Floating-point half precision registers. */
6213 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6215 /* Floating-point byte precision registers. */
6216 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6218 /* Floating-point quad precision registers. */
6219 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6221 /* FP/SIMD registers. */
6222 REGSET (v
, VN
), REGSET (V
, VN
),
6237 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6238 static const asm_nzcv nzcv_names
[] = {
6239 {"nzcv", B (n
, z
, c
, v
)},
6240 {"nzcV", B (n
, z
, c
, V
)},
6241 {"nzCv", B (n
, z
, C
, v
)},
6242 {"nzCV", B (n
, z
, C
, V
)},
6243 {"nZcv", B (n
, Z
, c
, v
)},
6244 {"nZcV", B (n
, Z
, c
, V
)},
6245 {"nZCv", B (n
, Z
, C
, v
)},
6246 {"nZCV", B (n
, Z
, C
, V
)},
6247 {"Nzcv", B (N
, z
, c
, v
)},
6248 {"NzcV", B (N
, z
, c
, V
)},
6249 {"NzCv", B (N
, z
, C
, v
)},
6250 {"NzCV", B (N
, z
, C
, V
)},
6251 {"NZcv", B (N
, Z
, c
, v
)},
6252 {"NZcV", B (N
, Z
, c
, V
)},
6253 {"NZCv", B (N
, Z
, C
, v
)},
6254 {"NZCV", B (N
, Z
, C
, V
)}
6267 /* MD interface: bits in the object file. */
6269 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6270 for use in the a.out file, and stores them in the array pointed to by buf.
6271 This knows about the endian-ness of the target machine and does
6272 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6273 2 (short) and 4 (long) Floating numbers are put out as a series of
6274 LITTLENUMS (shorts, here at least). */
6277 md_number_to_chars (char *buf
, valueT val
, int n
)
6279 if (target_big_endian
)
6280 number_to_chars_bigendian (buf
, val
, n
);
6282 number_to_chars_littleendian (buf
, val
, n
);
6285 /* MD interface: Sections. */
6287 /* Estimate the size of a frag before relaxing. Assume everything fits in
6291 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6297 /* Round up a section size to the appropriate boundary. */
6300 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
6305 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6306 of an rs_align_code fragment.
6308 Here we fill the frag with the appropriate info for padding the
6309 output stream. The resulting frag will consist of a fixed (fr_fix)
6310 and of a repeating (fr_var) part.
6312 The fixed content is always emitted before the repeating content and
6313 these two parts are used as follows in constructing the output:
6314 - the fixed part will be used to align to a valid instruction word
6315 boundary, in case that we start at a misaligned address; as no
6316 executable instruction can live at the misaligned location, we
6317 simply fill with zeros;
6318 - the variable part will be used to cover the remaining padding and
6319 we fill using the AArch64 NOP instruction.
6321 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6322 enough storage space for up to 3 bytes for padding the back to a valid
6323 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6326 aarch64_handle_align (fragS
* fragP
)
6328 /* NOP = d503201f */
6329 /* AArch64 instructions are always little-endian. */
6330 static char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6332 int bytes
, fix
, noop_size
;
6335 if (fragP
->fr_type
!= rs_align_code
)
6338 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6339 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6342 gas_assert (fragP
->tc_frag_data
.recorded
);
6345 noop_size
= sizeof (aarch64_noop
);
6347 fix
= bytes
& (noop_size
- 1);
6351 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6355 fragP
->fr_fix
+= fix
;
6359 memcpy (p
, aarch64_noop
, noop_size
);
6360 fragP
->fr_var
= noop_size
;
6363 /* Perform target specific initialisation of a frag.
6364 Note - despite the name this initialisation is not done when the frag
6365 is created, but only when its type is assigned. A frag can be created
6366 and used a long time before its type is set, so beware of assuming that
6367 this initialisationis performed first. */
6371 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6372 int max_chars ATTRIBUTE_UNUSED
)
6376 #else /* OBJ_ELF is defined. */
6378 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6380 /* Record a mapping symbol for alignment frags. We will delete this
6381 later if the alignment ends up empty. */
6382 if (!fragP
->tc_frag_data
.recorded
)
6383 fragP
->tc_frag_data
.recorded
= 1;
6385 switch (fragP
->fr_type
)
6390 mapping_state_2 (MAP_DATA
, max_chars
);
6393 mapping_state_2 (MAP_INSN
, max_chars
);
6400 /* Initialize the DWARF-2 unwind information for this procedure. */
6403 tc_aarch64_frame_initial_instructions (void)
6405 cfi_add_CFA_def_cfa (REG_SP
, 0);
6407 #endif /* OBJ_ELF */
6409 /* Convert REGNAME to a DWARF-2 register number. */
6412 tc_aarch64_regname_to_dw2regnum (char *regname
)
6414 const reg_entry
*reg
= parse_reg (®name
);
6420 case REG_TYPE_SP_32
:
6421 case REG_TYPE_SP_64
:
6431 return reg
->number
+ 64;
6439 /* Implement DWARF2_ADDR_SIZE. */
6442 aarch64_dwarf2_addr_size (void)
6444 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6448 return bfd_arch_bits_per_address (stdoutput
) / 8;
6451 /* MD interface: Symbol and relocation handling. */
6453 /* Return the address within the segment that a PC-relative fixup is
6454 relative to. For AArch64 PC-relative fixups applied to instructions
6455 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6458 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6460 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6462 /* If this is pc-relative and we are going to emit a relocation
6463 then we just want to put out any pipeline compensation that the linker
6464 will need. Otherwise we want to use the calculated base. */
6466 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6467 || aarch64_force_relocation (fixP
)))
6470 /* AArch64 should be consistent for all pc-relative relocations. */
6471 return base
+ AARCH64_PCREL_OFFSET
;
6474 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6475 Otherwise we have no need to default values of symbols. */
6478 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6481 if (name
[0] == '_' && name
[1] == 'G'
6482 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6486 if (symbol_find (name
))
6487 as_bad (_("GOT already in the symbol table"));
6489 GOT_symbol
= symbol_new (name
, undefined_section
,
6490 (valueT
) 0, &zero_address_frag
);
6500 /* Return non-zero if the indicated VALUE has overflowed the maximum
6501 range expressible by a unsigned number with the indicated number of
6505 unsigned_overflow (valueT value
, unsigned bits
)
6508 if (bits
>= sizeof (valueT
) * 8)
6510 lim
= (valueT
) 1 << bits
;
6511 return (value
>= lim
);
6515 /* Return non-zero if the indicated VALUE has overflowed the maximum
6516 range expressible by an signed number with the indicated number of
6520 signed_overflow (offsetT value
, unsigned bits
)
6523 if (bits
>= sizeof (offsetT
) * 8)
6525 lim
= (offsetT
) 1 << (bits
- 1);
6526 return (value
< -lim
|| value
>= lim
);
6529 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6530 unsigned immediate offset load/store instruction, try to encode it as
6531 an unscaled, 9-bit, signed immediate offset load/store instruction.
6532 Return TRUE if it is successful; otherwise return FALSE.
6534 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6535 in response to the standard LDR/STR mnemonics when the immediate offset is
6536 unambiguous, i.e. when it is negative or unaligned. */
6539 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6542 enum aarch64_op new_op
;
6543 const aarch64_opcode
*new_opcode
;
6545 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6547 switch (instr
->opcode
->op
)
6549 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6550 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6551 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6552 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6553 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6554 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6555 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6556 case OP_STR_POS
: new_op
= OP_STUR
; break;
6557 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6558 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6559 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6560 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6561 default: new_op
= OP_NIL
; break;
6564 if (new_op
== OP_NIL
)
6567 new_opcode
= aarch64_get_opcode (new_op
);
6568 gas_assert (new_opcode
!= NULL
);
6570 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6571 instr
->opcode
->op
, new_opcode
->op
);
6573 aarch64_replace_opcode (instr
, new_opcode
);
6575 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6576 qualifier matching may fail because the out-of-date qualifier will
6577 prevent the operand being updated with a new and correct qualifier. */
6578 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6579 AARCH64_OPND_ADDR_SIMM9
);
6580 gas_assert (idx
== 1);
6581 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6583 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6585 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6591 /* Called by fix_insn to fix a MOV immediate alias instruction.
6593 Operand for a generic move immediate instruction, which is an alias
6594 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6595 a 32-bit/64-bit immediate value into general register. An assembler error
6596 shall result if the immediate cannot be created by a single one of these
6597 instructions. If there is a choice, then to ensure reversability an
6598 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6601 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6603 const aarch64_opcode
*opcode
;
6605 /* Need to check if the destination is SP/ZR. The check has to be done
6606 before any aarch64_replace_opcode. */
6607 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6608 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6610 instr
->operands
[1].imm
.value
= value
;
6611 instr
->operands
[1].skip
= 0;
6615 /* Try the MOVZ alias. */
6616 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6617 aarch64_replace_opcode (instr
, opcode
);
6618 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6619 &instr
->value
, NULL
, NULL
))
6621 put_aarch64_insn (buf
, instr
->value
);
6624 /* Try the MOVK alias. */
6625 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6626 aarch64_replace_opcode (instr
, opcode
);
6627 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6628 &instr
->value
, NULL
, NULL
))
6630 put_aarch64_insn (buf
, instr
->value
);
6635 if (try_mov_bitmask_p
)
6637 /* Try the ORR alias. */
6638 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6639 aarch64_replace_opcode (instr
, opcode
);
6640 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6641 &instr
->value
, NULL
, NULL
))
6643 put_aarch64_insn (buf
, instr
->value
);
6648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6649 _("immediate cannot be moved by a single instruction"));
6652 /* An instruction operand which is immediate related may have symbol used
6653 in the assembly, e.g.
6656 .set u32, 0x00ffff00
6658 At the time when the assembly instruction is parsed, a referenced symbol,
6659 like 'u32' in the above example may not have been seen; a fixS is created
6660 in such a case and is handled here after symbols have been resolved.
6661 Instruction is fixed up with VALUE using the information in *FIXP plus
6662 extra information in FLAGS.
6664 This function is called by md_apply_fix to fix up instructions that need
6665 a fix-up described above but does not involve any linker-time relocation. */
6668 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6672 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6673 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6674 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6678 /* Now the instruction is about to be fixed-up, so the operand that
6679 was previously marked as 'ignored' needs to be unmarked in order
6680 to get the encoding done properly. */
6681 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6682 new_inst
->operands
[idx
].skip
= 0;
6685 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6689 case AARCH64_OPND_EXCEPTION
:
6690 if (unsigned_overflow (value
, 16))
6691 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6692 _("immediate out of range"));
6693 insn
= get_aarch64_insn (buf
);
6694 insn
|= encode_svc_imm (value
);
6695 put_aarch64_insn (buf
, insn
);
6698 case AARCH64_OPND_AIMM
:
6699 /* ADD or SUB with immediate.
6700 NOTE this assumes we come here with a add/sub shifted reg encoding
6701 3 322|2222|2 2 2 21111 111111
6702 1 098|7654|3 2 1 09876 543210 98765 43210
6703 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6704 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6705 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6706 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6708 3 322|2222|2 2 221111111111
6709 1 098|7654|3 2 109876543210 98765 43210
6710 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6711 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6712 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6713 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6714 Fields sf Rn Rd are already set. */
6715 insn
= get_aarch64_insn (buf
);
6719 insn
= reencode_addsub_switch_add_sub (insn
);
6723 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6724 && unsigned_overflow (value
, 12))
6726 /* Try to shift the value by 12 to make it fit. */
6727 if (((value
>> 12) << 12) == value
6728 && ! unsigned_overflow (value
, 12 + 12))
6731 insn
|= encode_addsub_imm_shift_amount (1);
6735 if (unsigned_overflow (value
, 12))
6736 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6737 _("immediate out of range"));
6739 insn
|= encode_addsub_imm (value
);
6741 put_aarch64_insn (buf
, insn
);
6744 case AARCH64_OPND_SIMD_IMM
:
6745 case AARCH64_OPND_SIMD_IMM_SFT
:
6746 case AARCH64_OPND_LIMM
:
6747 /* Bit mask immediate. */
6748 gas_assert (new_inst
!= NULL
);
6749 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6750 new_inst
->operands
[idx
].imm
.value
= value
;
6751 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6752 &new_inst
->value
, NULL
, NULL
))
6753 put_aarch64_insn (buf
, new_inst
->value
);
6755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6756 _("invalid immediate"));
6759 case AARCH64_OPND_HALF
:
6760 /* 16-bit unsigned immediate. */
6761 if (unsigned_overflow (value
, 16))
6762 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6763 _("immediate out of range"));
6764 insn
= get_aarch64_insn (buf
);
6765 insn
|= encode_movw_imm (value
& 0xffff);
6766 put_aarch64_insn (buf
, insn
);
6769 case AARCH64_OPND_IMM_MOV
:
6770 /* Operand for a generic move immediate instruction, which is
6771 an alias instruction that generates a single MOVZ, MOVN or ORR
6772 instruction to loads a 32-bit/64-bit immediate value into general
6773 register. An assembler error shall result if the immediate cannot be
6774 created by a single one of these instructions. If there is a choice,
6775 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6776 and MOVZ or MOVN to ORR. */
6777 gas_assert (new_inst
!= NULL
);
6778 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6781 case AARCH64_OPND_ADDR_SIMM7
:
6782 case AARCH64_OPND_ADDR_SIMM9
:
6783 case AARCH64_OPND_ADDR_SIMM9_2
:
6784 case AARCH64_OPND_ADDR_UIMM12
:
6785 /* Immediate offset in an address. */
6786 insn
= get_aarch64_insn (buf
);
6788 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6789 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6790 || new_inst
->opcode
->operands
[2] == opnd
);
6792 /* Get the index of the address operand. */
6793 if (new_inst
->opcode
->operands
[1] == opnd
)
6794 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6797 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6800 /* Update the resolved offset value. */
6801 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6803 /* Encode/fix-up. */
6804 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6805 &new_inst
->value
, NULL
, NULL
))
6807 put_aarch64_insn (buf
, new_inst
->value
);
6810 else if (new_inst
->opcode
->iclass
== ldst_pos
6811 && try_to_encode_as_unscaled_ldst (new_inst
))
6813 put_aarch64_insn (buf
, new_inst
->value
);
6817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6818 _("immediate offset out of range"));
6823 as_fatal (_("unhandled operand code %d"), opnd
);
6827 /* Apply a fixup (fixP) to segment data, once it has been determined
6828 by our caller that we have all the info we need to fix it up.
6830 Parameter valP is the pointer to the value of the bits. */
6833 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6835 offsetT value
= *valP
;
6837 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6839 unsigned flags
= fixP
->fx_addnumber
;
6841 DEBUG_TRACE ("\n\n");
6842 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6843 DEBUG_TRACE ("Enter md_apply_fix");
6845 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6847 /* Note whether this will delete the relocation. */
6849 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6852 /* Process the relocations. */
6853 switch (fixP
->fx_r_type
)
6855 case BFD_RELOC_NONE
:
6856 /* This will need to go in the object file. */
6861 case BFD_RELOC_8_PCREL
:
6862 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6863 md_number_to_chars (buf
, value
, 1);
6867 case BFD_RELOC_16_PCREL
:
6868 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6869 md_number_to_chars (buf
, value
, 2);
6873 case BFD_RELOC_32_PCREL
:
6874 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6875 md_number_to_chars (buf
, value
, 4);
6879 case BFD_RELOC_64_PCREL
:
6880 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6881 md_number_to_chars (buf
, value
, 8);
6884 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6885 /* We claim that these fixups have been processed here, even if
6886 in fact we generate an error because we do not have a reloc
6887 for them, so tc_gen_reloc() will reject them. */
6889 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6891 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6892 _("undefined symbol %s used as an immediate value"),
6893 S_GET_NAME (fixP
->fx_addsy
));
6894 goto apply_fix_return
;
6896 fix_insn (fixP
, flags
, value
);
6899 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6900 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6903 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6904 _("pc-relative load offset not word aligned"));
6905 if (signed_overflow (value
, 21))
6906 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6907 _("pc-relative load offset out of range"));
6908 insn
= get_aarch64_insn (buf
);
6909 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6910 put_aarch64_insn (buf
, insn
);
6914 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6915 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6917 if (signed_overflow (value
, 21))
6918 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6919 _("pc-relative address offset out of range"));
6920 insn
= get_aarch64_insn (buf
);
6921 insn
|= encode_adr_imm (value
);
6922 put_aarch64_insn (buf
, insn
);
6926 case BFD_RELOC_AARCH64_BRANCH19
:
6927 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6930 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6931 _("conditional branch target not word aligned"));
6932 if (signed_overflow (value
, 21))
6933 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6934 _("conditional branch out of range"));
6935 insn
= get_aarch64_insn (buf
);
6936 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6937 put_aarch64_insn (buf
, insn
);
6941 case BFD_RELOC_AARCH64_TSTBR14
:
6942 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6945 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6946 _("conditional branch target not word aligned"));
6947 if (signed_overflow (value
, 16))
6948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6949 _("conditional branch out of range"));
6950 insn
= get_aarch64_insn (buf
);
6951 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6952 put_aarch64_insn (buf
, insn
);
6956 case BFD_RELOC_AARCH64_CALL26
:
6957 case BFD_RELOC_AARCH64_JUMP26
:
6958 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6962 _("branch target not word aligned"));
6963 if (signed_overflow (value
, 28))
6964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6965 _("branch out of range"));
6966 insn
= get_aarch64_insn (buf
);
6967 insn
|= encode_branch_ofs_26 (value
>> 2);
6968 put_aarch64_insn (buf
, insn
);
6972 case BFD_RELOC_AARCH64_MOVW_G0
:
6973 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6974 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6975 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6978 case BFD_RELOC_AARCH64_MOVW_G1
:
6979 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6980 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6981 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6984 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6986 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6987 /* Should always be exported to object file, see
6988 aarch64_force_relocation(). */
6989 gas_assert (!fixP
->fx_done
);
6990 gas_assert (seg
->use_rela_p
);
6992 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6994 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6995 /* Should always be exported to object file, see
6996 aarch64_force_relocation(). */
6997 gas_assert (!fixP
->fx_done
);
6998 gas_assert (seg
->use_rela_p
);
7000 case BFD_RELOC_AARCH64_MOVW_G2
:
7001 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7002 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7005 case BFD_RELOC_AARCH64_MOVW_G3
:
7008 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7010 insn
= get_aarch64_insn (buf
);
7014 /* REL signed addend must fit in 16 bits */
7015 if (signed_overflow (value
, 16))
7016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7017 _("offset out of range"));
7021 /* Check for overflow and scale. */
7022 switch (fixP
->fx_r_type
)
7024 case BFD_RELOC_AARCH64_MOVW_G0
:
7025 case BFD_RELOC_AARCH64_MOVW_G1
:
7026 case BFD_RELOC_AARCH64_MOVW_G2
:
7027 case BFD_RELOC_AARCH64_MOVW_G3
:
7028 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7029 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7030 if (unsigned_overflow (value
, scale
+ 16))
7031 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7032 _("unsigned value out of range"));
7034 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7035 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7036 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7037 /* NOTE: We can only come here with movz or movn. */
7038 if (signed_overflow (value
, scale
+ 16))
7039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7040 _("signed value out of range"));
7043 /* Force use of MOVN. */
7045 insn
= reencode_movzn_to_movn (insn
);
7049 /* Force use of MOVZ. */
7050 insn
= reencode_movzn_to_movz (insn
);
7054 /* Unchecked relocations. */
7060 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7061 insn
|= encode_movw_imm (value
& 0xffff);
7063 put_aarch64_insn (buf
, insn
);
7067 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7068 fixP
->fx_r_type
= (ilp32_p
7069 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7070 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7071 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7072 /* Should always be exported to object file, see
7073 aarch64_force_relocation(). */
7074 gas_assert (!fixP
->fx_done
);
7075 gas_assert (seg
->use_rela_p
);
7078 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7079 fixP
->fx_r_type
= (ilp32_p
7080 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7081 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
7082 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7083 /* Should always be exported to object file, see
7084 aarch64_force_relocation(). */
7085 gas_assert (!fixP
->fx_done
);
7086 gas_assert (seg
->use_rela_p
);
7089 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7090 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7091 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7092 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7093 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7094 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7095 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7096 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7097 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7098 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7099 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7100 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7101 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7102 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7103 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7104 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7105 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7106 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7107 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7108 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7109 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7110 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7111 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7112 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7113 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7114 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7115 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7116 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7117 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7118 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7119 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7120 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7121 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7122 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7123 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7124 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7125 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7126 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7127 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7128 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7129 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7130 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7131 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7132 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7133 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7134 /* Should always be exported to object file, see
7135 aarch64_force_relocation(). */
7136 gas_assert (!fixP
->fx_done
);
7137 gas_assert (seg
->use_rela_p
);
7140 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7141 /* Should always be exported to object file, see
7142 aarch64_force_relocation(). */
7143 fixP
->fx_r_type
= (ilp32_p
7144 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7145 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7146 gas_assert (!fixP
->fx_done
);
7147 gas_assert (seg
->use_rela_p
);
7150 case BFD_RELOC_AARCH64_ADD_LO12
:
7151 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7152 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7153 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7154 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7155 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7156 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7157 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7158 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7159 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7160 case BFD_RELOC_AARCH64_LDST128_LO12
:
7161 case BFD_RELOC_AARCH64_LDST16_LO12
:
7162 case BFD_RELOC_AARCH64_LDST32_LO12
:
7163 case BFD_RELOC_AARCH64_LDST64_LO12
:
7164 case BFD_RELOC_AARCH64_LDST8_LO12
:
7165 /* Should always be exported to object file, see
7166 aarch64_force_relocation(). */
7167 gas_assert (!fixP
->fx_done
);
7168 gas_assert (seg
->use_rela_p
);
7171 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7172 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7173 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7176 case BFD_RELOC_UNUSED
:
7177 /* An error will already have been reported. */
7181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7182 _("unexpected %s fixup"),
7183 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7188 /* Free the allocated the struct aarch64_inst.
7189 N.B. currently there are very limited number of fix-up types actually use
7190 this field, so the impact on the performance should be minimal . */
7191 if (fixP
->tc_fix_data
.inst
!= NULL
)
7192 free (fixP
->tc_fix_data
.inst
);
7197 /* Translate internal representation of relocation info to BFD target
7201 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7204 bfd_reloc_code_real_type code
;
7206 reloc
= xmalloc (sizeof (arelent
));
7208 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
7209 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7210 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7214 if (section
->use_rela_p
)
7215 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7217 fixp
->fx_offset
= reloc
->address
;
7219 reloc
->addend
= fixp
->fx_offset
;
7221 code
= fixp
->fx_r_type
;
7226 code
= BFD_RELOC_16_PCREL
;
7231 code
= BFD_RELOC_32_PCREL
;
7236 code
= BFD_RELOC_64_PCREL
;
7243 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7244 if (reloc
->howto
== NULL
)
7246 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7248 ("cannot represent %s relocation in this object file format"),
7249 bfd_get_reloc_code_name (code
));
7256 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7259 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7261 bfd_reloc_code_real_type type
;
7265 FIXME: @@ Should look at CPU word size. */
7272 type
= BFD_RELOC_16
;
7275 type
= BFD_RELOC_32
;
7278 type
= BFD_RELOC_64
;
7281 as_bad (_("cannot do %u-byte relocation"), size
);
7282 type
= BFD_RELOC_UNUSED
;
7286 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7290 aarch64_force_relocation (struct fix
*fixp
)
7292 switch (fixp
->fx_r_type
)
7294 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7295 /* Perform these "immediate" internal relocations
7296 even if the symbol is extern or weak. */
7299 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7300 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7301 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7302 /* Pseudo relocs that need to be fixed up according to
7306 case BFD_RELOC_AARCH64_ADD_LO12
:
7307 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7308 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7309 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7310 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7311 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7312 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7313 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7314 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7315 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7316 case BFD_RELOC_AARCH64_LDST128_LO12
:
7317 case BFD_RELOC_AARCH64_LDST16_LO12
:
7318 case BFD_RELOC_AARCH64_LDST32_LO12
:
7319 case BFD_RELOC_AARCH64_LDST64_LO12
:
7320 case BFD_RELOC_AARCH64_LDST8_LO12
:
7321 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7322 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7323 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7324 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7325 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7326 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7327 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7328 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7329 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7330 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7331 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7332 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7333 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7334 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7335 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7336 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7337 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7338 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7339 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7340 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7341 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7342 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7343 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7344 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7345 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7346 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7347 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7348 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7349 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7350 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7351 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7352 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7353 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7354 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7355 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7356 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7357 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7358 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7359 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7360 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7361 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7362 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7363 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7364 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7365 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7366 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7367 /* Always leave these relocations for the linker. */
7374 return generic_force_reloc (fixp
);
7380 elf64_aarch64_target_format (void)
7382 if (strcmp (TARGET_OS
, "cloudabi") == 0)
7384 /* FIXME: What to do for ilp32_p ? */
7385 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7387 if (target_big_endian
)
7388 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7390 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7394 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7396 elf_frob_symbol (symp
, puntp
);
7400 /* MD interface: Finalization. */
7402 /* A good place to do this, although this was probably not intended
7403 for this kind of use. We need to dump the literal pool before
7404 references are made to a null symbol pointer. */
7407 aarch64_cleanup (void)
7411 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7413 /* Put it at the end of the relevant section. */
7414 subseg_set (pool
->section
, pool
->sub_section
);
7420 /* Remove any excess mapping symbols generated for alignment frags in
7421 SEC. We may have created a mapping symbol before a zero byte
7422 alignment; remove it if there's a mapping symbol after the
7425 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7426 void *dummy ATTRIBUTE_UNUSED
)
7428 segment_info_type
*seginfo
= seg_info (sec
);
7431 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7434 for (fragp
= seginfo
->frchainP
->frch_root
;
7435 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7437 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7438 fragS
*next
= fragp
->fr_next
;
7440 /* Variable-sized frags have been converted to fixed size by
7441 this point. But if this was variable-sized to start with,
7442 there will be a fixed-size frag after it. So don't handle
7444 if (sym
== NULL
|| next
== NULL
)
7447 if (S_GET_VALUE (sym
) < next
->fr_address
)
7448 /* Not at the end of this frag. */
7450 know (S_GET_VALUE (sym
) == next
->fr_address
);
7454 if (next
->tc_frag_data
.first_map
!= NULL
)
7456 /* Next frag starts with a mapping symbol. Discard this
7458 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7462 if (next
->fr_next
== NULL
)
7464 /* This mapping symbol is at the end of the section. Discard
7466 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7467 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7471 /* As long as we have empty frags without any mapping symbols,
7473 /* If the next frag is non-empty and does not start with a
7474 mapping symbol, then this mapping symbol is required. */
7475 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7478 next
= next
->fr_next
;
7480 while (next
!= NULL
);
7485 /* Adjust the symbol table. */
7488 aarch64_adjust_symtab (void)
7491 /* Remove any overlapping mapping symbols generated by alignment frags. */
7492 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7493 /* Now do generic ELF adjustments. */
7494 elf_adjust_symtab ();
7499 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7501 const char *hash_err
;
7503 hash_err
= hash_insert (table
, key
, value
);
7505 printf ("Internal Error: Can't hash %s\n", key
);
7509 fill_instruction_hash_table (void)
7511 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7513 while (opcode
->name
!= NULL
)
7515 templates
*templ
, *new_templ
;
7516 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7518 new_templ
= (templates
*) xmalloc (sizeof (templates
));
7519 new_templ
->opcode
= opcode
;
7520 new_templ
->next
= NULL
;
7523 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7526 new_templ
->next
= templ
->next
;
7527 templ
->next
= new_templ
;
7534 convert_to_upper (char *dst
, const char *src
, size_t num
)
7537 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7538 *dst
= TOUPPER (*src
);
7542 /* Assume STR point to a lower-case string, allocate, convert and return
7543 the corresponding upper-case string. */
7544 static inline const char*
7545 get_upper_str (const char *str
)
7548 size_t len
= strlen (str
);
7549 if ((ret
= xmalloc (len
+ 1)) == NULL
)
7551 convert_to_upper (ret
, str
, len
);
7555 /* MD interface: Initialization. */
7563 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7564 || (aarch64_cond_hsh
= hash_new ()) == NULL
7565 || (aarch64_shift_hsh
= hash_new ()) == NULL
7566 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7567 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7568 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7569 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7570 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7571 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7572 || (aarch64_reg_hsh
= hash_new ()) == NULL
7573 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7574 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7575 || (aarch64_pldop_hsh
= hash_new ()) == NULL
7576 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
7577 as_fatal (_("virtual memory exhausted"));
7579 fill_instruction_hash_table ();
7581 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7582 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7583 (void *) (aarch64_sys_regs
+ i
));
7585 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7586 checked_hash_insert (aarch64_pstatefield_hsh
,
7587 aarch64_pstatefields
[i
].name
,
7588 (void *) (aarch64_pstatefields
+ i
));
7590 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
7591 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7592 aarch64_sys_regs_ic
[i
].name
,
7593 (void *) (aarch64_sys_regs_ic
+ i
));
7595 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
7596 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7597 aarch64_sys_regs_dc
[i
].name
,
7598 (void *) (aarch64_sys_regs_dc
+ i
));
7600 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
7601 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7602 aarch64_sys_regs_at
[i
].name
,
7603 (void *) (aarch64_sys_regs_at
+ i
));
7605 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
7606 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7607 aarch64_sys_regs_tlbi
[i
].name
,
7608 (void *) (aarch64_sys_regs_tlbi
+ i
));
7610 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7611 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7612 (void *) (reg_names
+ i
));
7614 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7615 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7616 (void *) (nzcv_names
+ i
));
7618 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7620 const char *name
= aarch64_operand_modifiers
[i
].name
;
7621 checked_hash_insert (aarch64_shift_hsh
, name
,
7622 (void *) (aarch64_operand_modifiers
+ i
));
7623 /* Also hash the name in the upper case. */
7624 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7625 (void *) (aarch64_operand_modifiers
+ i
));
7628 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7631 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7632 the same condition code. */
7633 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7635 const char *name
= aarch64_conds
[i
].names
[j
];
7638 checked_hash_insert (aarch64_cond_hsh
, name
,
7639 (void *) (aarch64_conds
+ i
));
7640 /* Also hash the name in the upper case. */
7641 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7642 (void *) (aarch64_conds
+ i
));
7646 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7648 const char *name
= aarch64_barrier_options
[i
].name
;
7649 /* Skip xx00 - the unallocated values of option. */
7652 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7653 (void *) (aarch64_barrier_options
+ i
));
7654 /* Also hash the name in the upper case. */
7655 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7656 (void *) (aarch64_barrier_options
+ i
));
7659 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7661 const char* name
= aarch64_prfops
[i
].name
;
7662 /* Skip the unallocated hint encodings. */
7665 checked_hash_insert (aarch64_pldop_hsh
, name
,
7666 (void *) (aarch64_prfops
+ i
));
7667 /* Also hash the name in the upper case. */
7668 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7669 (void *) (aarch64_prfops
+ i
));
7672 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
7674 const char* name
= aarch64_hint_options
[i
].name
;
7676 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
7677 (void *) (aarch64_hint_options
+ i
));
7678 /* Also hash the name in the upper case. */
7679 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7680 (void *) (aarch64_hint_options
+ i
));
7683 /* Set the cpu variant based on the command-line options. */
7685 mcpu_cpu_opt
= march_cpu_opt
;
7688 mcpu_cpu_opt
= &cpu_default
;
7690 cpu_variant
= *mcpu_cpu_opt
;
7692 /* Record the CPU type. */
7693 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7695 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7698 /* Command line processing. */
7700 const char *md_shortopts
= "m:";
7702 #ifdef AARCH64_BI_ENDIAN
7703 #define OPTION_EB (OPTION_MD_BASE + 0)
7704 #define OPTION_EL (OPTION_MD_BASE + 1)
7706 #if TARGET_BYTES_BIG_ENDIAN
7707 #define OPTION_EB (OPTION_MD_BASE + 0)
7709 #define OPTION_EL (OPTION_MD_BASE + 1)
7713 struct option md_longopts
[] = {
7715 {"EB", no_argument
, NULL
, OPTION_EB
},
7718 {"EL", no_argument
, NULL
, OPTION_EL
},
7720 {NULL
, no_argument
, NULL
, 0}
7723 size_t md_longopts_size
= sizeof (md_longopts
);
7725 struct aarch64_option_table
7727 char *option
; /* Option name to match. */
7728 char *help
; /* Help information. */
7729 int *var
; /* Variable to change. */
7730 int value
; /* What to change it to. */
7731 char *deprecated
; /* If non-null, print this message. */
7734 static struct aarch64_option_table aarch64_opts
[] = {
7735 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7736 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7738 #ifdef DEBUG_AARCH64
7739 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7740 #endif /* DEBUG_AARCH64 */
7741 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7743 {"mno-verbose-error", N_("do not output verbose error messages"),
7744 &verbose_error_p
, 0, NULL
},
7745 {NULL
, NULL
, NULL
, 0, NULL
}
7748 struct aarch64_cpu_option_table
7751 const aarch64_feature_set value
;
7752 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7754 const char *canonical_name
;
7757 /* This list should, at a minimum, contain all the cpu names
7758 recognized by GCC. */
7759 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7760 {"all", AARCH64_ANY
, NULL
},
7761 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7762 AARCH64_FEATURE_CRC
), "Cortex-A35"},
7763 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7764 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7765 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7766 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7767 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7768 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7769 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7770 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7771 "Samsung Exynos M1"},
7772 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7773 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7774 "Qualcomm QDF24XX"},
7775 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7776 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7778 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7779 in earlier releases and is superseded by 'xgene1' in all
7781 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7782 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7783 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7784 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7785 {"generic", AARCH64_ARCH_V8
, NULL
},
7787 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7790 struct aarch64_arch_option_table
7793 const aarch64_feature_set value
;
7796 /* This list should, at a minimum, contain all the architecture names
7797 recognized by GCC. */
7798 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7799 {"all", AARCH64_ANY
},
7800 {"armv8-a", AARCH64_ARCH_V8
},
7801 {"armv8.1-a", AARCH64_ARCH_V8_1
},
7802 {"armv8.2-a", AARCH64_ARCH_V8_2
},
7803 {NULL
, AARCH64_ARCH_NONE
}
7806 /* ISA extensions. */
7807 struct aarch64_option_cpu_value_table
7810 const aarch64_feature_set value
;
7813 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7814 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0)},
7815 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
7816 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7817 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0)},
7818 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7819 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0)},
7820 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0)},
7821 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
7822 | AARCH64_FEATURE_RDMA
, 0)},
7823 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
7824 | AARCH64_FEATURE_FP
, 0)},
7825 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0)},
7826 {NULL
, AARCH64_ARCH_NONE
}
7829 struct aarch64_long_option_table
7831 char *option
; /* Substring to match. */
7832 char *help
; /* Help information. */
7833 int (*func
) (char *subopt
); /* Function to decode sub-option. */
7834 char *deprecated
; /* If non-null, print this message. */
7838 aarch64_parse_features (char *str
, const aarch64_feature_set
**opt_p
,
7839 bfd_boolean ext_only
)
7841 /* We insist on extensions being added before being removed. We achieve
7842 this by using the ADDING_VALUE variable to indicate whether we are
7843 adding an extension (1) or removing it (0) and only allowing it to
7844 change in the order -1 -> 1 -> 0. */
7845 int adding_value
= -1;
7846 aarch64_feature_set
*ext_set
= xmalloc (sizeof (aarch64_feature_set
));
7848 /* Copy the feature set, so that we can modify it. */
7852 while (str
!= NULL
&& *str
!= 0)
7854 const struct aarch64_option_cpu_value_table
*opt
;
7862 as_bad (_("invalid architectural extension"));
7866 ext
= strchr (++str
, '+');
7872 optlen
= strlen (str
);
7874 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7876 if (adding_value
!= 0)
7881 else if (optlen
> 0)
7883 if (adding_value
== -1)
7885 else if (adding_value
!= 1)
7887 as_bad (_("must specify extensions to add before specifying "
7888 "those to remove"));
7895 as_bad (_("missing architectural extension"));
7899 gas_assert (adding_value
!= -1);
7901 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7902 if (strncmp (opt
->name
, str
, optlen
) == 0)
7904 /* Add or remove the extension. */
7906 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7908 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7912 if (opt
->name
== NULL
)
7914 as_bad (_("unknown architectural extension `%s'"), str
);
7925 aarch64_parse_cpu (char *str
)
7927 const struct aarch64_cpu_option_table
*opt
;
7928 char *ext
= strchr (str
, '+');
7934 optlen
= strlen (str
);
7938 as_bad (_("missing cpu name `%s'"), str
);
7942 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7943 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7945 mcpu_cpu_opt
= &opt
->value
;
7947 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7952 as_bad (_("unknown cpu `%s'"), str
);
7957 aarch64_parse_arch (char *str
)
7959 const struct aarch64_arch_option_table
*opt
;
7960 char *ext
= strchr (str
, '+');
7966 optlen
= strlen (str
);
7970 as_bad (_("missing architecture name `%s'"), str
);
7974 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7975 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7977 march_cpu_opt
= &opt
->value
;
7979 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
7984 as_bad (_("unknown architecture `%s'\n"), str
);
7989 struct aarch64_option_abi_value_table
7992 enum aarch64_abi_type value
;
7995 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
7996 {"ilp32", AARCH64_ABI_ILP32
},
7997 {"lp64", AARCH64_ABI_LP64
},
8002 aarch64_parse_abi (char *str
)
8004 const struct aarch64_option_abi_value_table
*opt
;
8005 size_t optlen
= strlen (str
);
8009 as_bad (_("missing abi name `%s'"), str
);
8013 for (opt
= aarch64_abis
; opt
->name
!= NULL
; opt
++)
8014 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8016 aarch64_abi
= opt
->value
;
8020 as_bad (_("unknown abi `%s'\n"), str
);
8024 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8026 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8027 aarch64_parse_abi
, NULL
},
8028 #endif /* OBJ_ELF */
8029 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8030 aarch64_parse_cpu
, NULL
},
8031 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8032 aarch64_parse_arch
, NULL
},
8033 {NULL
, NULL
, 0, NULL
}
8037 md_parse_option (int c
, char *arg
)
8039 struct aarch64_option_table
*opt
;
8040 struct aarch64_long_option_table
*lopt
;
8046 target_big_endian
= 1;
8052 target_big_endian
= 0;
8057 /* Listing option. Just ignore these, we don't support additional
8062 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8064 if (c
== opt
->option
[0]
8065 && ((arg
== NULL
&& opt
->option
[1] == 0)
8066 || streq (arg
, opt
->option
+ 1)))
8068 /* If the option is deprecated, tell the user. */
8069 if (opt
->deprecated
!= NULL
)
8070 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8071 arg
? arg
: "", _(opt
->deprecated
));
8073 if (opt
->var
!= NULL
)
8074 *opt
->var
= opt
->value
;
8080 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8082 /* These options are expected to have an argument. */
8083 if (c
== lopt
->option
[0]
8085 && strncmp (arg
, lopt
->option
+ 1,
8086 strlen (lopt
->option
+ 1)) == 0)
8088 /* If the option is deprecated, tell the user. */
8089 if (lopt
->deprecated
!= NULL
)
8090 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8091 _(lopt
->deprecated
));
8093 /* Call the sup-option parser. */
8094 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8105 md_show_usage (FILE * fp
)
8107 struct aarch64_option_table
*opt
;
8108 struct aarch64_long_option_table
*lopt
;
8110 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8112 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8113 if (opt
->help
!= NULL
)
8114 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8116 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8117 if (lopt
->help
!= NULL
)
8118 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
8122 -EB assemble code for a big-endian cpu\n"));
8127 -EL assemble code for a little-endian cpu\n"));
8131 /* Parse a .cpu directive. */
8134 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
8136 const struct aarch64_cpu_option_table
*opt
;
8142 name
= input_line_pointer
;
8143 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8144 input_line_pointer
++;
8145 saved_char
= *input_line_pointer
;
8146 *input_line_pointer
= 0;
8148 ext
= strchr (name
, '+');
8151 optlen
= ext
- name
;
8153 optlen
= strlen (name
);
8155 /* Skip the first "all" entry. */
8156 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
8157 if (strlen (opt
->name
) == optlen
8158 && strncmp (name
, opt
->name
, optlen
) == 0)
8160 mcpu_cpu_opt
= &opt
->value
;
8162 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8165 cpu_variant
= *mcpu_cpu_opt
;
8167 *input_line_pointer
= saved_char
;
8168 demand_empty_rest_of_line ();
8171 as_bad (_("unknown cpu `%s'"), name
);
8172 *input_line_pointer
= saved_char
;
8173 ignore_rest_of_line ();
8177 /* Parse a .arch directive. */
8180 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
8182 const struct aarch64_arch_option_table
*opt
;
8188 name
= input_line_pointer
;
8189 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8190 input_line_pointer
++;
8191 saved_char
= *input_line_pointer
;
8192 *input_line_pointer
= 0;
8194 ext
= strchr (name
, '+');
8197 optlen
= ext
- name
;
8199 optlen
= strlen (name
);
8201 /* Skip the first "all" entry. */
8202 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
8203 if (strlen (opt
->name
) == optlen
8204 && strncmp (name
, opt
->name
, optlen
) == 0)
8206 mcpu_cpu_opt
= &opt
->value
;
8208 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8211 cpu_variant
= *mcpu_cpu_opt
;
8213 *input_line_pointer
= saved_char
;
8214 demand_empty_rest_of_line ();
8218 as_bad (_("unknown architecture `%s'\n"), name
);
8219 *input_line_pointer
= saved_char
;
8220 ignore_rest_of_line ();
8223 /* Parse a .arch_extension directive. */
8226 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
8229 char *ext
= input_line_pointer
;;
8231 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8232 input_line_pointer
++;
8233 saved_char
= *input_line_pointer
;
8234 *input_line_pointer
= 0;
8236 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
8239 cpu_variant
= *mcpu_cpu_opt
;
8241 *input_line_pointer
= saved_char
;
8242 demand_empty_rest_of_line ();
8245 /* Copy symbol information. */
8248 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
8250 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);