1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in neon_type_el. */
91 #define NTA_HASINDEX 2
95 enum neon_el_type type
;
96 unsigned char defined
;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type
;
108 enum aarch64_opnd opnd
;
110 unsigned need_libopcodes_p
: 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind
;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool
: 1;
131 typedef struct aarch64_instruction aarch64_instruction
;
133 static aarch64_instruction inst
;
135 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
136 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
159 inst
.parsing_error
.error
= NULL
;
162 static inline bfd_boolean
165 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
168 static inline const char *
169 get_error_message (void)
171 return inst
.parsing_error
.error
;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst
.parsing_error
.kind
;
181 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
183 inst
.parsing_error
.kind
= kind
;
184 inst
.parsing_error
.error
= error
;
188 set_recoverable_error (const char *error
)
190 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
202 set_syntax_error (const char *error
)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
208 set_first_syntax_error (const char *error
)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
215 set_fatal_syntax_error (const char *error
)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc
;
250 /* Structure for a hash table entry for a register. */
254 unsigned char number
;
256 unsigned char builtin
;
259 /* Macros to define the register types and masks for the purpose
262 #undef AARCH64_REG_TYPES
263 #define AARCH64_REG_TYPES \
264 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
265 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
266 BASIC_REG_TYPE(SP_32) /* wsp */ \
267 BASIC_REG_TYPE(SP_64) /* sp */ \
268 BASIC_REG_TYPE(Z_32) /* wzr */ \
269 BASIC_REG_TYPE(Z_64) /* xzr */ \
270 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
271 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
272 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
273 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
274 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
275 BASIC_REG_TYPE(CN) /* c[0-7] */ \
276 BASIC_REG_TYPE(VN) /* v[0-31] */ \
277 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
278 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
279 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
280 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
281 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
282 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
283 /* Typecheck: any [BHSDQ]P FP. */ \
284 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
285 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
286 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
287 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
289 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
290 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
291 /* Any integer register; used for error messages only. */ \
292 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
293 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Pseudo type to mark the end of the enumerator sequence. */ \
298 #undef BASIC_REG_TYPE
299 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
300 #undef MULTI_REG_TYPE
301 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
303 /* Register type enumerators. */
306 /* A list of REG_TYPE_*. */
310 #undef BASIC_REG_TYPE
311 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
313 #define REG_TYPE(T) (1 << REG_TYPE_##T)
314 #undef MULTI_REG_TYPE
315 #define MULTI_REG_TYPE(T,V) V,
317 /* Values indexed by aarch64_reg_type to assist the type checking. */
318 static const unsigned reg_type_masks
[] =
323 #undef BASIC_REG_TYPE
325 #undef MULTI_REG_TYPE
326 #undef AARCH64_REG_TYPES
328 /* Diagnostics used when we don't get a register of the expected type.
329 Note: this has to synchronized with aarch64_reg_type definitions
332 get_reg_expected_msg (aarch64_reg_type reg_type
)
339 msg
= N_("integer 32-bit register expected");
342 msg
= N_("integer 64-bit register expected");
345 msg
= N_("integer register expected");
347 case REG_TYPE_R_Z_SP
:
348 msg
= N_("integer, zero or SP register expected");
351 msg
= N_("8-bit SIMD scalar register expected");
354 msg
= N_("16-bit SIMD scalar or floating-point half precision "
355 "register expected");
358 msg
= N_("32-bit SIMD scalar or floating-point single precision "
359 "register expected");
362 msg
= N_("64-bit SIMD scalar or floating-point double precision "
363 "register expected");
366 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
367 "register expected");
370 msg
= N_("C0 - C15 expected");
372 case REG_TYPE_R_Z_BHSDQ_V
:
373 msg
= N_("register expected");
375 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
376 msg
= N_("SIMD scalar or floating-point register expected");
378 case REG_TYPE_VN
: /* any V reg */
379 msg
= N_("vector register expected");
382 as_fatal (_("invalid register type %d"), reg_type
);
387 /* Some well known registers that we refer to directly elsewhere. */
390 /* Instructions take 4 bytes in the object file. */
393 /* Define some common error messages. */
394 #define BAD_SP _("SP not allowed here")
396 static struct hash_control
*aarch64_ops_hsh
;
397 static struct hash_control
*aarch64_cond_hsh
;
398 static struct hash_control
*aarch64_shift_hsh
;
399 static struct hash_control
*aarch64_sys_regs_hsh
;
400 static struct hash_control
*aarch64_pstatefield_hsh
;
401 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
402 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
403 static struct hash_control
*aarch64_sys_regs_at_hsh
;
404 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
405 static struct hash_control
*aarch64_reg_hsh
;
406 static struct hash_control
*aarch64_barrier_opt_hsh
;
407 static struct hash_control
*aarch64_nzcv_hsh
;
408 static struct hash_control
*aarch64_pldop_hsh
;
410 /* Stuff needed to resolve the label ambiguity
419 static symbolS
*last_label_seen
;
421 /* Literal pool structure. Held on a per-section
422 and per-sub-section basis. */
424 #define MAX_LITERAL_POOL_SIZE 1024
425 typedef struct literal_expression
428 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
429 LITTLENUM_TYPE
* bignum
;
430 } literal_expression
;
432 typedef struct literal_pool
434 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
435 unsigned int next_free_entry
;
441 struct literal_pool
*next
;
444 /* Pointer to a linked list of literal pools. */
445 static literal_pool
*list_of_pools
= NULL
;
449 /* This array holds the chars that always start a comment. If the
450 pre-processor is disabled, these aren't very useful. */
451 const char comment_chars
[] = "";
453 /* This array holds the chars that only start a comment at the beginning of
454 a line. If the line seems to have the form '# 123 filename'
455 .line and .file directives will appear in the pre-processed output. */
456 /* Note that input_file.c hand checks for '#' at the beginning of the
457 first line of the input file. This is because the compiler outputs
458 #NO_APP at the beginning of its output. */
459 /* Also note that comments like this one will always work. */
460 const char line_comment_chars
[] = "#";
462 const char line_separator_chars
[] = ";";
464 /* Chars that can be used to separate mant
465 from exp in floating point numbers. */
466 const char EXP_CHARS
[] = "eE";
468 /* Chars that mean this number is a floating point constant. */
472 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
474 /* Prefix character that indicates the start of an immediate value. */
475 #define is_immediate_prefix(C) ((C) == '#')
477 /* Separator character handling. */
479 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
481 static inline bfd_boolean
482 skip_past_char (char **str
, char c
)
493 #define skip_past_comma(str) skip_past_char (str, ',')
495 /* Arithmetic expressions (possibly involving symbols). */
497 static bfd_boolean in_my_get_expression_p
= FALSE
;
499 /* Third argument to my_get_expression. */
500 #define GE_NO_PREFIX 0
501 #define GE_OPT_PREFIX 1
503 /* Return TRUE if the string pointed by *STR is successfully parsed
504 as an valid expression; *EP will be filled with the information of
505 such an expression. Otherwise return FALSE. */
508 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
513 int prefix_present_p
= 0;
520 if (is_immediate_prefix (**str
))
523 prefix_present_p
= 1;
530 memset (ep
, 0, sizeof (expressionS
));
532 save_in
= input_line_pointer
;
533 input_line_pointer
= *str
;
534 in_my_get_expression_p
= TRUE
;
535 seg
= expression (ep
);
536 in_my_get_expression_p
= FALSE
;
538 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
540 /* We found a bad expression in md_operand(). */
541 *str
= input_line_pointer
;
542 input_line_pointer
= save_in
;
543 if (prefix_present_p
&& ! error_p ())
544 set_fatal_syntax_error (_("bad expression"));
546 set_first_syntax_error (_("bad expression"));
551 if (seg
!= absolute_section
552 && seg
!= text_section
553 && seg
!= data_section
554 && seg
!= bss_section
&& seg
!= undefined_section
)
556 set_syntax_error (_("bad segment"));
557 *str
= input_line_pointer
;
558 input_line_pointer
= save_in
;
565 *str
= input_line_pointer
;
566 input_line_pointer
= save_in
;
570 /* Turn a string in input_line_pointer into a floating point constant
571 of type TYPE, and store the appropriate bytes in *LITP. The number
572 of LITTLENUMS emitted is stored in *SIZEP. An error message is
573 returned, or NULL on OK. */
576 md_atof (int type
, char *litP
, int *sizeP
)
578 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
581 /* We handle all bad expressions here, so that we can report the faulty
582 instruction in the error message. */
584 md_operand (expressionS
* exp
)
586 if (in_my_get_expression_p
)
587 exp
->X_op
= O_illegal
;
590 /* Immediate values. */
592 /* Errors may be set multiple times during parsing or bit encoding
593 (particularly in the Neon bits), but usually the earliest error which is set
594 will be the most meaningful. Avoid overwriting it with later (cascading)
595 errors by calling this function. */
598 first_error (const char *error
)
601 set_syntax_error (error
);
604 /* Similiar to first_error, but this function accepts formatted error
607 first_error_fmt (const char *format
, ...)
612 /* N.B. this single buffer will not cause error messages for different
613 instructions to pollute each other; this is because at the end of
614 processing of each assembly line, error message if any will be
615 collected by as_bad. */
616 static char buffer
[size
];
620 int ret ATTRIBUTE_UNUSED
;
621 va_start (args
, format
);
622 ret
= vsnprintf (buffer
, size
, format
, args
);
623 know (ret
<= size
- 1 && ret
>= 0);
625 set_syntax_error (buffer
);
629 /* Register parsing. */
631 /* Generic register parser which is called by other specialized
633 CCP points to what should be the beginning of a register name.
634 If it is indeed a valid register name, advance CCP over it and
635 return the reg_entry structure; otherwise return NULL.
636 It does not issue diagnostics. */
639 parse_reg (char **ccp
)
645 #ifdef REGISTER_PREFIX
646 if (*start
!= REGISTER_PREFIX
)
652 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
657 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
659 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
668 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
671 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
673 if (reg
->type
== type
)
678 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
679 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
680 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
681 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
682 case REG_TYPE_VN
: /* Vector register. */
683 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
684 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
685 == reg_type_masks
[reg
->type
]);
687 as_fatal ("unhandled type %d", type
);
692 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
693 Return the register number otherwise. *ISREG32 is set to one if the
694 register is 32-bit wide; *ISREGZERO is set to one if the register is
695 of type Z_32 or Z_64.
696 Note that this function does not issue any diagnostics. */
699 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
700 int *isreg32
, int *isregzero
)
703 const reg_entry
*reg
= parse_reg (&str
);
708 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
717 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
722 *isreg32
= reg
->type
== REG_TYPE_R_32
;
729 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
741 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
742 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
743 otherwise return FALSE.
745 Accept only one occurrence of:
746 8b 16b 4h 8h 2s 4s 1d 2d
749 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
753 unsigned element_size
;
754 enum neon_el_type type
;
764 width
= strtoul (ptr
, &ptr
, 10);
765 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
767 first_error_fmt (_("bad size %d in vector width specifier"), width
);
772 switch (TOLOWER (*ptr
))
800 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
802 first_error (_("missing element size"));
805 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128)
808 ("invalid element size %d and vector size combination %c"),
814 parsed_type
->type
= type
;
815 parsed_type
->width
= width
;
822 /* Parse a single type, e.g. ".8b", leading period included.
823 Only applicable to Vn registers.
825 Return TRUE on success; otherwise return FALSE. */
827 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
833 if (! parse_neon_type_for_operand (vectype
, &str
))
835 first_error (_("vector type expected"));
847 /* Parse a register of the type TYPE.
849 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
850 name or the parsed register is not of TYPE.
852 Otherwise return the register number, and optionally fill in the actual
853 type of the register in *RTYPE when multiple alternatives were given, and
854 return the register shape and element index information in *TYPEINFO.
856 IN_REG_LIST should be set with TRUE if the caller is parsing a register
860 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
861 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
864 const reg_entry
*reg
= parse_reg (&str
);
865 struct neon_type_el atype
;
866 struct neon_type_el parsetype
;
867 bfd_boolean is_typed_vecreg
= FALSE
;
870 atype
.type
= NT_invtype
;
878 set_default_error ();
882 if (! aarch64_check_reg_type (reg
, type
))
884 DEBUG_TRACE ("reg type check failed");
885 set_default_error ();
890 if (type
== REG_TYPE_VN
891 && parse_neon_operand_type (&parsetype
, &str
))
893 /* Register if of the form Vn.[bhsdq]. */
894 is_typed_vecreg
= TRUE
;
896 if (parsetype
.width
== 0)
897 /* Expect index. In the new scheme we cannot have
898 Vn.[bhsdq] represent a scalar. Therefore any
899 Vn.[bhsdq] should have an index following it.
900 Except in reglists ofcourse. */
901 atype
.defined
|= NTA_HASINDEX
;
903 atype
.defined
|= NTA_HASTYPE
;
905 atype
.type
= parsetype
.type
;
906 atype
.width
= parsetype
.width
;
909 if (skip_past_char (&str
, '['))
913 /* Reject Sn[index] syntax. */
914 if (!is_typed_vecreg
)
916 first_error (_("this type of register can't be indexed"));
920 if (in_reg_list
== TRUE
)
922 first_error (_("index not allowed inside register list"));
926 atype
.defined
|= NTA_HASINDEX
;
928 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
930 if (exp
.X_op
!= O_constant
)
932 first_error (_("constant expression required"));
936 if (! skip_past_char (&str
, ']'))
939 atype
.index
= exp
.X_add_number
;
941 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
943 /* Indexed vector register expected. */
944 first_error (_("indexed vector register expected"));
948 /* A vector reg Vn should be typed or indexed. */
949 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
951 first_error (_("invalid use of vector register"));
967 Return the register number on success; return PARSE_FAIL otherwise.
969 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
970 the register (e.g. NEON double or quad reg when either has been requested).
972 If this is a NEON vector register with additional type information, fill
973 in the struct pointed to by VECTYPE (if non-NULL).
975 This parser does not handle register list. */
978 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
979 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
981 struct neon_type_el atype
;
983 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
984 /*in_reg_list= */ FALSE
);
986 if (reg
== PARSE_FAIL
)
997 static inline bfd_boolean
998 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
1002 && e1
.defined
== e2
.defined
1003 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1006 /* This function parses the NEON register list. On success, it returns
1007 the parsed register list information in the following encoded format:
1009 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1010 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1012 The information of the register shape and/or index is returned in
1015 It returns PARSE_FAIL if the register list is invalid.
1017 The list contains one to four registers.
1018 Each register can be one of:
1021 All <T> should be identical.
1022 All <index> should be identical.
1023 There are restrictions on <Vt> numbers which are checked later
1024 (by reg_list_valid_p). */
1027 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1031 struct neon_type_el typeinfo
, typeinfo_first
;
1036 bfd_boolean error
= FALSE
;
1037 bfd_boolean expect_index
= FALSE
;
1041 set_syntax_error (_("expecting {"));
1047 typeinfo_first
.defined
= 0;
1048 typeinfo_first
.type
= NT_invtype
;
1049 typeinfo_first
.width
= -1;
1050 typeinfo_first
.index
= 0;
1059 str
++; /* skip over '-' */
1062 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1063 /*in_reg_list= */ TRUE
);
1064 if (val
== PARSE_FAIL
)
1066 set_first_syntax_error (_("invalid vector register in list"));
1070 /* reject [bhsd]n */
1071 if (typeinfo
.defined
== 0)
1073 set_first_syntax_error (_("invalid scalar register in list"));
1078 if (typeinfo
.defined
& NTA_HASINDEX
)
1079 expect_index
= TRUE
;
1083 if (val
< val_range
)
1085 set_first_syntax_error
1086 (_("invalid range in vector register list"));
1095 typeinfo_first
= typeinfo
;
1096 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1098 set_first_syntax_error
1099 (_("type mismatch in vector register list"));
1104 for (i
= val_range
; i
<= val
; i
++)
1106 ret_val
|= i
<< (5 * nb_regs
);
1111 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1113 skip_whitespace (str
);
1116 set_first_syntax_error (_("end of vector register list not found"));
1121 skip_whitespace (str
);
1125 if (skip_past_char (&str
, '['))
1129 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1130 if (exp
.X_op
!= O_constant
)
1132 set_first_syntax_error (_("constant expression required."));
1135 if (! skip_past_char (&str
, ']'))
1138 typeinfo_first
.index
= exp
.X_add_number
;
1142 set_first_syntax_error (_("expected index"));
1149 set_first_syntax_error (_("too many registers in vector register list"));
1152 else if (nb_regs
== 0)
1154 set_first_syntax_error (_("empty vector register list"));
1160 *vectype
= typeinfo_first
;
1162 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1165 /* Directives: register aliases. */
1168 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1173 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1176 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1179 /* Only warn about a redefinition if it's not defined as the
1181 else if (new->number
!= number
|| new->type
!= type
)
1182 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1187 name
= xstrdup (str
);
1188 new = xmalloc (sizeof (reg_entry
));
1191 new->number
= number
;
1193 new->builtin
= FALSE
;
1195 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1201 /* Look for the .req directive. This is of the form:
1203 new_register_name .req existing_register_name
1205 If we find one, or if it looks sufficiently like one that we want to
1206 handle any error here, return TRUE. Otherwise return FALSE. */
1209 create_register_alias (char *newname
, char *p
)
1211 const reg_entry
*old
;
1212 char *oldname
, *nbuf
;
1215 /* The input scrubber ensures that whitespace after the mnemonic is
1216 collapsed to single spaces. */
1218 if (strncmp (oldname
, " .req ", 6) != 0)
1222 if (*oldname
== '\0')
1225 old
= hash_find (aarch64_reg_hsh
, oldname
);
1228 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1232 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1233 the desired alias name, and p points to its end. If not, then
1234 the desired alias name is in the global original_case_string. */
1235 #ifdef TC_CASE_SENSITIVE
1238 newname
= original_case_string
;
1239 nlen
= strlen (newname
);
1242 nbuf
= alloca (nlen
+ 1);
1243 memcpy (nbuf
, newname
, nlen
);
1246 /* Create aliases under the new name as stated; an all-lowercase
1247 version of the new name; and an all-uppercase version of the new
1249 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1251 for (p
= nbuf
; *p
; p
++)
1254 if (strncmp (nbuf
, newname
, nlen
))
1256 /* If this attempt to create an additional alias fails, do not bother
1257 trying to create the all-lower case alias. We will fail and issue
1258 a second, duplicate error message. This situation arises when the
1259 programmer does something like:
1262 The second .req creates the "Foo" alias but then fails to create
1263 the artificial FOO alias because it has already been created by the
1265 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1269 for (p
= nbuf
; *p
; p
++)
1272 if (strncmp (nbuf
, newname
, nlen
))
1273 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1279 /* Should never be called, as .req goes between the alias and the
1280 register name, not at the beginning of the line. */
1282 s_req (int a ATTRIBUTE_UNUSED
)
1284 as_bad (_("invalid syntax for .req directive"));
1287 /* The .unreq directive deletes an alias which was previously defined
1288 by .req. For example:
1294 s_unreq (int a ATTRIBUTE_UNUSED
)
1299 name
= input_line_pointer
;
1301 while (*input_line_pointer
!= 0
1302 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1303 ++input_line_pointer
;
1305 saved_char
= *input_line_pointer
;
1306 *input_line_pointer
= 0;
1309 as_bad (_("invalid syntax for .unreq directive"));
1312 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1315 as_bad (_("unknown register alias '%s'"), name
);
1316 else if (reg
->builtin
)
1317 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1324 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1325 free ((char *) reg
->name
);
1328 /* Also locate the all upper case and all lower case versions.
1329 Do not complain if we cannot find one or the other as it
1330 was probably deleted above. */
1332 nbuf
= strdup (name
);
1333 for (p
= nbuf
; *p
; p
++)
1335 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1338 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1339 free ((char *) reg
->name
);
1343 for (p
= nbuf
; *p
; p
++)
1345 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1348 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1349 free ((char *) reg
->name
);
1357 *input_line_pointer
= saved_char
;
1358 demand_empty_rest_of_line ();
1361 /* Directives: Instruction set selection. */
1364 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1365 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1366 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1367 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1369 /* Create a new mapping symbol for the transition to STATE. */
1372 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1375 const char *symname
;
1382 type
= BSF_NO_FLAGS
;
1386 type
= BSF_NO_FLAGS
;
1392 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1393 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1395 /* Save the mapping symbols for future reference. Also check that
1396 we do not place two mapping symbols at the same offset within a
1397 frag. We'll handle overlap between frags in
1398 check_mapping_symbols.
1400 If .fill or other data filling directive generates zero sized data,
1401 the mapping symbol for the following code will have the same value
1402 as the one generated for the data filling directive. In this case,
1403 we replace the old symbol with the new one at the same address. */
1406 if (frag
->tc_frag_data
.first_map
!= NULL
)
1408 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1409 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1412 frag
->tc_frag_data
.first_map
= symbolP
;
1414 if (frag
->tc_frag_data
.last_map
!= NULL
)
1416 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1417 S_GET_VALUE (symbolP
));
1418 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1419 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1422 frag
->tc_frag_data
.last_map
= symbolP
;
1425 /* We must sometimes convert a region marked as code to data during
1426 code alignment, if an odd number of bytes have to be padded. The
1427 code mapping symbol is pushed to an aligned address. */
1430 insert_data_mapping_symbol (enum mstate state
,
1431 valueT value
, fragS
* frag
, offsetT bytes
)
1433 /* If there was already a mapping symbol, remove it. */
1434 if (frag
->tc_frag_data
.last_map
!= NULL
1435 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1436 frag
->fr_address
+ value
)
1438 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1442 know (frag
->tc_frag_data
.first_map
== symp
);
1443 frag
->tc_frag_data
.first_map
= NULL
;
1445 frag
->tc_frag_data
.last_map
= NULL
;
1446 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1449 make_mapping_symbol (MAP_DATA
, value
, frag
);
1450 make_mapping_symbol (state
, value
+ bytes
, frag
);
1453 static void mapping_state_2 (enum mstate state
, int max_chars
);
1455 /* Set the mapping state to STATE. Only call this when about to
1456 emit some STATE bytes to the file. */
1459 mapping_state (enum mstate state
)
1461 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1463 if (state
== MAP_INSN
)
1464 /* AArch64 instructions require 4-byte alignment. When emitting
1465 instructions into any section, record the appropriate section
1467 record_alignment (now_seg
, 2);
1469 if (mapstate
== state
)
1470 /* The mapping symbol has already been emitted.
1471 There is nothing else to do. */
1474 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1475 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1476 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1477 evaluated later in the next else. */
1479 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1481 /* Only add the symbol if the offset is > 0:
1482 if we're at the first frag, check it's size > 0;
1483 if we're not at the first frag, then for sure
1484 the offset is > 0. */
1485 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1486 const int add_symbol
= (frag_now
!= frag_first
)
1487 || (frag_now_fix () > 0);
1490 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1494 mapping_state_2 (state
, 0);
1497 /* Same as mapping_state, but MAX_CHARS bytes have already been
1498 allocated. Put the mapping symbol that far back. */
1501 mapping_state_2 (enum mstate state
, int max_chars
)
1503 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1505 if (!SEG_NORMAL (now_seg
))
1508 if (mapstate
== state
)
1509 /* The mapping symbol has already been emitted.
1510 There is nothing else to do. */
1513 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1514 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1517 #define mapping_state(x) /* nothing */
1518 #define mapping_state_2(x, y) /* nothing */
1521 /* Directives: sectioning and alignment. */
1524 s_bss (int ignore ATTRIBUTE_UNUSED
)
1526 /* We don't support putting frags in the BSS segment, we fake it by
1527 marking in_bss, then looking at s_skip for clues. */
1528 subseg_set (bss_section
, 0);
1529 demand_empty_rest_of_line ();
1530 mapping_state (MAP_DATA
);
1534 s_even (int ignore ATTRIBUTE_UNUSED
)
1536 /* Never make frag if expect extra pass. */
1538 frag_align (1, 0, 0);
1540 record_alignment (now_seg
, 1);
1542 demand_empty_rest_of_line ();
1545 /* Directives: Literal pools. */
1547 static literal_pool
*
1548 find_literal_pool (int size
)
1552 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1554 if (pool
->section
== now_seg
1555 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1562 static literal_pool
*
1563 find_or_make_literal_pool (int size
)
1565 /* Next literal pool ID number. */
1566 static unsigned int latest_pool_num
= 1;
1569 pool
= find_literal_pool (size
);
1573 /* Create a new pool. */
1574 pool
= xmalloc (sizeof (*pool
));
1578 /* Currently we always put the literal pool in the current text
1579 section. If we were generating "small" model code where we
1580 knew that all code and initialised data was within 1MB then
1581 we could output literals to mergeable, read-only data
1584 pool
->next_free_entry
= 0;
1585 pool
->section
= now_seg
;
1586 pool
->sub_section
= now_subseg
;
1588 pool
->next
= list_of_pools
;
1589 pool
->symbol
= NULL
;
1591 /* Add it to the list. */
1592 list_of_pools
= pool
;
1595 /* New pools, and emptied pools, will have a NULL symbol. */
1596 if (pool
->symbol
== NULL
)
1598 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1599 (valueT
) 0, &zero_address_frag
);
1600 pool
->id
= latest_pool_num
++;
1607 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1608 Return TRUE on success, otherwise return FALSE. */
1610 add_to_lit_pool (expressionS
*exp
, int size
)
1615 pool
= find_or_make_literal_pool (size
);
1617 /* Check if this literal value is already in the pool. */
1618 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1620 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1622 if ((litexp
->X_op
== exp
->X_op
)
1623 && (exp
->X_op
== O_constant
)
1624 && (litexp
->X_add_number
== exp
->X_add_number
)
1625 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1628 if ((litexp
->X_op
== exp
->X_op
)
1629 && (exp
->X_op
== O_symbol
)
1630 && (litexp
->X_add_number
== exp
->X_add_number
)
1631 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1632 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1636 /* Do we need to create a new entry? */
1637 if (entry
== pool
->next_free_entry
)
1639 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1641 set_syntax_error (_("literal pool overflow"));
1645 pool
->literals
[entry
].exp
= *exp
;
1646 pool
->next_free_entry
+= 1;
1647 if (exp
->X_op
== O_big
)
1649 /* PR 16688: Bignums are held in a single global array. We must
1650 copy and preserve that value now, before it is overwritten. */
1651 pool
->literals
[entry
].bignum
= xmalloc (CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1652 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1653 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1656 pool
->literals
[entry
].bignum
= NULL
;
1659 exp
->X_op
= O_symbol
;
1660 exp
->X_add_number
= ((int) entry
) * size
;
1661 exp
->X_add_symbol
= pool
->symbol
;
1666 /* Can't use symbol_new here, so have to create a symbol and then at
1667 a later date assign it a value. Thats what these functions do. */
1670 symbol_locate (symbolS
* symbolP
,
1671 const char *name
,/* It is copied, the caller can modify. */
1672 segT segment
, /* Segment identifier (SEG_<something>). */
1673 valueT valu
, /* Symbol value. */
1674 fragS
* frag
) /* Associated fragment. */
1677 char *preserved_copy_of_name
;
1679 name_length
= strlen (name
) + 1; /* +1 for \0. */
1680 obstack_grow (¬es
, name
, name_length
);
1681 preserved_copy_of_name
= obstack_finish (¬es
);
1683 #ifdef tc_canonicalize_symbol_name
1684 preserved_copy_of_name
=
1685 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1688 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1690 S_SET_SEGMENT (symbolP
, segment
);
1691 S_SET_VALUE (symbolP
, valu
);
1692 symbol_clear_list_pointers (symbolP
);
1694 symbol_set_frag (symbolP
, frag
);
1696 /* Link to end of symbol chain. */
1698 extern int symbol_table_frozen
;
1700 if (symbol_table_frozen
)
1704 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1706 obj_symbol_new_hook (symbolP
);
1708 #ifdef tc_symbol_new_hook
1709 tc_symbol_new_hook (symbolP
);
1713 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1714 #endif /* DEBUG_SYMS */
1719 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1726 for (align
= 2; align
<= 4; align
++)
1728 int size
= 1 << align
;
1730 pool
= find_literal_pool (size
);
1731 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1734 mapping_state (MAP_DATA
);
1736 /* Align pool as you have word accesses.
1737 Only make a frag if we have to. */
1739 frag_align (align
, 0, 0);
1741 record_alignment (now_seg
, align
);
1743 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1745 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1746 (valueT
) frag_now_fix (), frag_now
);
1747 symbol_table_insert (pool
->symbol
);
1749 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1751 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1753 if (exp
->X_op
== O_big
)
1755 /* PR 16688: Restore the global bignum value. */
1756 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1757 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1758 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1761 /* First output the expression in the instruction to the pool. */
1762 emit_expr (exp
, size
); /* .word|.xword */
1764 if (exp
->X_op
== O_big
)
1766 free (pool
->literals
[entry
].bignum
);
1767 pool
->literals
[entry
].bignum
= NULL
;
1771 /* Mark the pool as empty. */
1772 pool
->next_free_entry
= 0;
1773 pool
->symbol
= NULL
;
1778 /* Forward declarations for functions below, in the MD interface
1780 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1781 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1783 /* Directives: Data. */
1784 /* N.B. the support for relocation suffix in this directive needs to be
1785 implemented properly. */
1788 s_aarch64_elf_cons (int nbytes
)
1792 #ifdef md_flush_pending_output
1793 md_flush_pending_output ();
1796 if (is_it_end_of_statement ())
1798 demand_empty_rest_of_line ();
1802 #ifdef md_cons_align
1803 md_cons_align (nbytes
);
1806 mapping_state (MAP_DATA
);
1809 struct reloc_table_entry
*reloc
;
1813 if (exp
.X_op
!= O_symbol
)
1814 emit_expr (&exp
, (unsigned int) nbytes
);
1817 skip_past_char (&input_line_pointer
, '#');
1818 if (skip_past_char (&input_line_pointer
, ':'))
1820 reloc
= find_reloc_table_entry (&input_line_pointer
);
1822 as_bad (_("unrecognized relocation suffix"));
1824 as_bad (_("unimplemented relocation suffix"));
1825 ignore_rest_of_line ();
1829 emit_expr (&exp
, (unsigned int) nbytes
);
1832 while (*input_line_pointer
++ == ',');
1834 /* Put terminator back into stream. */
1835 input_line_pointer
--;
1836 demand_empty_rest_of_line ();
1839 #endif /* OBJ_ELF */
1841 /* Output a 32-bit word, but mark as an instruction. */
1844 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1848 #ifdef md_flush_pending_output
1849 md_flush_pending_output ();
1852 if (is_it_end_of_statement ())
1854 demand_empty_rest_of_line ();
1858 /* Sections are assumed to start aligned. In executable section, there is no
1859 MAP_DATA symbol pending. So we only align the address during
1860 MAP_DATA --> MAP_INSN transition.
1861 For other sections, this is not guaranteed. */
1862 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1863 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1864 frag_align_code (2, 0);
1867 mapping_state (MAP_INSN
);
1873 if (exp
.X_op
!= O_constant
)
1875 as_bad (_("constant expression required"));
1876 ignore_rest_of_line ();
1880 if (target_big_endian
)
1882 unsigned int val
= exp
.X_add_number
;
1883 exp
.X_add_number
= SWAP_32 (val
);
1885 emit_expr (&exp
, 4);
1887 while (*input_line_pointer
++ == ',');
1889 /* Put terminator back into stream. */
1890 input_line_pointer
--;
1891 demand_empty_rest_of_line ();
1895 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1898 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1902 /* Since we're just labelling the code, there's no need to define a
1905 /* Make sure there is enough room in this frag for the following
1906 blr. This trick only works if the blr follows immediately after
1907 the .tlsdesc directive. */
1909 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1910 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1912 demand_empty_rest_of_line ();
1914 #endif /* OBJ_ELF */
1916 static void s_aarch64_arch (int);
1917 static void s_aarch64_cpu (int);
1918 static void s_aarch64_arch_extension (int);
1920 /* This table describes all the machine specific pseudo-ops the assembler
1921 has to support. The fields are:
1922 pseudo-op name without dot
1923 function to call to execute this pseudo-op
1924 Integer arg to pass to the function. */
1926 const pseudo_typeS md_pseudo_table
[] = {
1927 /* Never called because '.req' does not start a line. */
1929 {"unreq", s_unreq
, 0},
1931 {"even", s_even
, 0},
1932 {"ltorg", s_ltorg
, 0},
1933 {"pool", s_ltorg
, 0},
1934 {"cpu", s_aarch64_cpu
, 0},
1935 {"arch", s_aarch64_arch
, 0},
1936 {"arch_extension", s_aarch64_arch_extension
, 0},
1937 {"inst", s_aarch64_inst
, 0},
1939 {"tlsdesccall", s_tlsdesccall
, 0},
1940 {"word", s_aarch64_elf_cons
, 4},
1941 {"long", s_aarch64_elf_cons
, 4},
1942 {"xword", s_aarch64_elf_cons
, 8},
1943 {"dword", s_aarch64_elf_cons
, 8},
1949 /* Check whether STR points to a register name followed by a comma or the
1950 end of line; REG_TYPE indicates which register types are checked
1951 against. Return TRUE if STR is such a register name; otherwise return
1952 FALSE. The function does not intend to produce any diagnostics, but since
1953 the register parser aarch64_reg_parse, which is called by this function,
1954 does produce diagnostics, we call clear_error to clear any diagnostics
1955 that may be generated by aarch64_reg_parse.
1956 Also, the function returns FALSE directly if there is any user error
1957 present at the function entry. This prevents the existing diagnostics
1958 state from being spoiled.
1959 The function currently serves parse_constant_immediate and
1960 parse_big_immediate only. */
1962 reg_name_p (char *str
, aarch64_reg_type reg_type
)
1966 /* Prevent the diagnostics state from being spoiled. */
1970 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
1972 /* Clear the parsing error that may be set by the reg parser. */
1975 if (reg
== PARSE_FAIL
)
1978 skip_whitespace (str
);
1979 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
1985 /* Parser functions used exclusively in instruction operands. */
1987 /* Parse an immediate expression which may not be constant.
1989 To prevent the expression parser from pushing a register name
1990 into the symbol table as an undefined symbol, firstly a check is
1991 done to find out whether STR is a valid register name followed
1992 by a comma or the end of line. Return FALSE if STR is such a
1996 parse_immediate_expression (char **str
, expressionS
*exp
)
1998 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
2000 set_recoverable_error (_("immediate operand required"));
2004 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2006 if (exp
->X_op
== O_absent
)
2008 set_fatal_syntax_error (_("missing immediate expression"));
2015 /* Constant immediate-value read function for use in insn parsing.
2016 STR points to the beginning of the immediate (with the optional
2017 leading #); *VAL receives the value.
2019 Return TRUE on success; otherwise return FALSE. */
2022 parse_constant_immediate (char **str
, int64_t * val
)
2026 if (! parse_immediate_expression (str
, &exp
))
2029 if (exp
.X_op
!= O_constant
)
2031 set_syntax_error (_("constant expression required"));
2035 *val
= exp
.X_add_number
;
2040 encode_imm_float_bits (uint32_t imm
)
2042 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2043 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2046 /* Return TRUE if the single-precision floating-point value encoded in IMM
2047 can be expressed in the AArch64 8-bit signed floating-point format with
2048 3-bit exponent and normalized 4 bits of precision; in other words, the
2049 floating-point value must be expressable as
2050 (+/-) n / 16 * power (2, r)
2051 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2054 aarch64_imm_float_p (uint32_t imm
)
2056 /* If a single-precision floating-point value has the following bit
2057 pattern, it can be expressed in the AArch64 8-bit floating-point
2060 3 32222222 2221111111111
2061 1 09876543 21098765432109876543210
2062 n Eeeeeexx xxxx0000000000000000000
2064 where n, e and each x are either 0 or 1 independently, with
2069 /* Prepare the pattern for 'Eeeeee'. */
2070 if (((imm
>> 30) & 0x1) == 0)
2071 pattern
= 0x3e000000;
2073 pattern
= 0x40000000;
2075 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2076 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2079 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2081 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2082 8-bit signed floating-point format with 3-bit exponent and normalized 4
2083 bits of precision (i.e. can be used in an FMOV instruction); return the
2084 equivalent single-precision encoding in *FPWORD.
2086 Otherwise return FALSE. */
2089 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2091 /* If a double-precision floating-point value has the following bit
2092 pattern, it can be expressed in the AArch64 8-bit floating-point
2095 6 66655555555 554444444...21111111111
2096 3 21098765432 109876543...098765432109876543210
2097 n Eeeeeeeeexx xxxx00000...000000000000000000000
2099 where n, e and each x are either 0 or 1 independently, with
2103 uint32_t high32
= imm
>> 32;
2105 /* Lower 32 bits need to be 0s. */
2106 if ((imm
& 0xffffffff) != 0)
2109 /* Prepare the pattern for 'Eeeeeeeee'. */
2110 if (((high32
>> 30) & 0x1) == 0)
2111 pattern
= 0x3fc00000;
2113 pattern
= 0x40000000;
2115 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2116 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2118 /* Convert to the single-precision encoding.
2120 n Eeeeeeeeexx xxxx00000...000000000000000000000
2122 n Eeeeeexx xxxx0000000000000000000. */
2123 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2124 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2131 /* Parse a floating-point immediate. Return TRUE on success and return the
2132 value in *IMMED in the format of IEEE754 single-precision encoding.
2133 *CCP points to the start of the string; DP_P is TRUE when the immediate
2134 is expected to be in double-precision (N.B. this only matters when
2135 hexadecimal representation is involved).
2137 N.B. 0.0 is accepted by this function. */
2140 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2144 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2145 int found_fpchar
= 0;
2147 unsigned fpword
= 0;
2148 bfd_boolean hex_p
= FALSE
;
2150 skip_past_char (&str
, '#');
2153 skip_whitespace (fpnum
);
2155 if (strncmp (fpnum
, "0x", 2) == 0)
2157 /* Support the hexadecimal representation of the IEEE754 encoding.
2158 Double-precision is expected when DP_P is TRUE, otherwise the
2159 representation should be in single-precision. */
2160 if (! parse_constant_immediate (&str
, &val
))
2165 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2168 else if ((uint64_t) val
> 0xffffffff)
2177 /* We must not accidentally parse an integer as a floating-point number.
2178 Make sure that the value we parse is not an integer by checking for
2179 special characters '.' or 'e'. */
2180 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2181 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2195 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2198 /* Our FP word must be 32 bits (single-precision FP). */
2199 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2201 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2206 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2214 set_fatal_syntax_error (_("invalid floating-point constant"));
2218 /* Less-generic immediate-value read function with the possibility of loading
2219 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2222 To prevent the expression parser from pushing a register name into the
2223 symbol table as an undefined symbol, a check is firstly done to find
2224 out whether STR is a valid register name followed by a comma or the end
2225 of line. Return FALSE if STR is such a register. */
2228 parse_big_immediate (char **str
, int64_t *imm
)
2232 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2234 set_syntax_error (_("immediate operand required"));
2238 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2240 if (inst
.reloc
.exp
.X_op
== O_constant
)
2241 *imm
= inst
.reloc
.exp
.X_add_number
;
2248 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2249 if NEED_LIBOPCODES is non-zero, the fixup will need
2250 assistance from the libopcodes. */
2253 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2254 const aarch64_opnd_info
*operand
,
2255 int need_libopcodes_p
)
2257 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2258 reloc
->opnd
= operand
->type
;
2259 if (need_libopcodes_p
)
2260 reloc
->need_libopcodes_p
= 1;
2263 /* Return TRUE if the instruction needs to be fixed up later internally by
2264 the GAS; otherwise return FALSE. */
2266 static inline bfd_boolean
2267 aarch64_gas_internal_fixup_p (void)
2269 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2272 /* Assign the immediate value to the relavant field in *OPERAND if
2273 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2274 needs an internal fixup in a later stage.
2275 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2276 IMM.VALUE that may get assigned with the constant. */
2278 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2279 aarch64_opnd_info
*operand
,
2281 int need_libopcodes_p
,
2284 if (reloc
->exp
.X_op
== O_constant
)
2287 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2289 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2290 reloc
->type
= BFD_RELOC_UNUSED
;
2294 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2295 /* Tell libopcodes to ignore this operand or not. This is helpful
2296 when one of the operands needs to be fixed up later but we need
2297 libopcodes to check the other operands. */
2298 operand
->skip
= skip_p
;
2302 /* Relocation modifiers. Each entry in the table contains the textual
2303 name for the relocation which may be placed before a symbol used as
2304 a load/store offset, or add immediate. It must be surrounded by a
2305 leading and trailing colon, for example:
2307 ldr x0, [x1, #:rello:varsym]
2308 add x0, x1, #:rello:varsym */
2310 struct reloc_table_entry
2314 bfd_reloc_code_real_type adr_type
;
2315 bfd_reloc_code_real_type adrp_type
;
2316 bfd_reloc_code_real_type movw_type
;
2317 bfd_reloc_code_real_type add_type
;
2318 bfd_reloc_code_real_type ldst_type
;
2319 bfd_reloc_code_real_type ld_literal_type
;
2322 static struct reloc_table_entry reloc_table
[] = {
2323 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2328 BFD_RELOC_AARCH64_ADD_LO12
,
2329 BFD_RELOC_AARCH64_LDST_LO12
,
2332 /* Higher 21 bits of pc-relative page offset: ADRP */
2335 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2341 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2344 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2350 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2354 BFD_RELOC_AARCH64_MOVW_G0
,
2359 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2363 BFD_RELOC_AARCH64_MOVW_G0_S
,
2368 /* Less significant bits 0-15 of address/value: MOVK, no check */
2372 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2377 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2381 BFD_RELOC_AARCH64_MOVW_G1
,
2386 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2390 BFD_RELOC_AARCH64_MOVW_G1_S
,
2395 /* Less significant bits 16-31 of address/value: MOVK, no check */
2399 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2404 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2408 BFD_RELOC_AARCH64_MOVW_G2
,
2413 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2417 BFD_RELOC_AARCH64_MOVW_G2_S
,
2422 /* Less significant bits 32-47 of address/value: MOVK, no check */
2426 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2431 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2435 BFD_RELOC_AARCH64_MOVW_G3
,
2440 /* Get to the page containing GOT entry for a symbol. */
2443 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2447 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2449 /* 12 bit offset into the page containing GOT entry for that symbol. */
2455 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2458 /* 0-15 bits of address/value: MOVk, no check. */
2462 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2467 /* Most significant bits 16-31 of address/value: MOVZ. */
2471 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2476 /* 15 bit offset into the page containing GOT entry for that symbol. */
2482 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2485 /* Get to the page containing GOT TLS entry for a symbol */
2487 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2488 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2494 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2499 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2503 /* Get to the page containing GOT TLS entry for a symbol */
2505 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2506 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2510 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2512 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2517 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2518 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2521 /* Get to the page containing GOT TLS entry for a symbol.
2522 The same as GD, we allocate two consecutive GOT slots
2523 for module index and module offset, the only difference
2524 with GD is the module offset should be intialized to
2525 zero without any outstanding runtime relocation. */
2527 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2528 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2534 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2535 {"tlsldm_lo12_nc", 0,
2539 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2543 /* 12 bit offset into the module TLS base address. */
2548 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2549 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2552 /* Same as dtprel_lo12, no overflow check. */
2553 {"dtprel_lo12_nc", 0,
2557 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2558 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2561 /* bits[23:12] of offset to the module TLS base address. */
2566 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2570 /* bits[15:0] of offset to the module TLS base address. */
2574 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2579 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2583 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2588 /* bits[31:16] of offset to the module TLS base address. */
2592 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2597 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2601 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2606 /* bits[47:32] of offset to the module TLS base address. */
2610 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2615 /* Get to the page containing GOT TLS entry for a symbol */
2618 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2622 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2624 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2625 {"gottprel_lo12", 0,
2630 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2633 /* Get tp offset for a symbol. */
2638 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2642 /* Get tp offset for a symbol. */
2647 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2651 /* Get tp offset for a symbol. */
2656 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2660 /* Get tp offset for a symbol. */
2661 {"tprel_lo12_nc", 0,
2665 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2669 /* Most significant bits 32-47 of address/value: MOVZ. */
2673 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2678 /* Most significant bits 16-31 of address/value: MOVZ. */
2682 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2687 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2691 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2696 /* Most significant bits 0-15 of address/value: MOVZ. */
2700 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2705 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2709 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2714 /* 15bit offset from got entry to base address of GOT table. */
2720 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2723 /* 14bit offset from got entry to base address of GOT table. */
2729 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2733 /* Given the address of a pointer pointing to the textual name of a
2734 relocation as may appear in assembler source, attempt to find its
2735 details in reloc_table. The pointer will be updated to the character
2736 after the trailing colon. On failure, NULL will be returned;
2737 otherwise return the reloc_table_entry. */
2739 static struct reloc_table_entry
*
2740 find_reloc_table_entry (char **str
)
2743 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2745 int length
= strlen (reloc_table
[i
].name
);
2747 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2748 && (*str
)[length
] == ':')
2750 *str
+= (length
+ 1);
2751 return &reloc_table
[i
];
2758 /* Mode argument to parse_shift and parser_shifter_operand. */
2759 enum parse_shift_mode
2761 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2763 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2765 SHIFTED_LSL
, /* bare "lsl #n" */
2766 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2767 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2770 /* Parse a <shift> operator on an AArch64 data processing instruction.
2771 Return TRUE on success; otherwise return FALSE. */
2773 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2775 const struct aarch64_name_value_pair
*shift_op
;
2776 enum aarch64_modifier_kind kind
;
2782 for (p
= *str
; ISALPHA (*p
); p
++)
2787 set_syntax_error (_("shift expression expected"));
2791 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2793 if (shift_op
== NULL
)
2795 set_syntax_error (_("shift operator expected"));
2799 kind
= aarch64_get_operand_modifier (shift_op
);
2801 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2803 set_syntax_error (_("invalid use of 'MSL'"));
2809 case SHIFTED_LOGIC_IMM
:
2810 if (aarch64_extend_operator_p (kind
) == TRUE
)
2812 set_syntax_error (_("extending shift is not permitted"));
2817 case SHIFTED_ARITH_IMM
:
2818 if (kind
== AARCH64_MOD_ROR
)
2820 set_syntax_error (_("'ROR' shift is not permitted"));
2826 if (kind
!= AARCH64_MOD_LSL
)
2828 set_syntax_error (_("only 'LSL' shift is permitted"));
2833 case SHIFTED_REG_OFFSET
:
2834 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2835 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2837 set_fatal_syntax_error
2838 (_("invalid shift for the register offset addressing mode"));
2843 case SHIFTED_LSL_MSL
:
2844 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2846 set_syntax_error (_("invalid shift operator"));
2855 /* Whitespace can appear here if the next thing is a bare digit. */
2856 skip_whitespace (p
);
2858 /* Parse shift amount. */
2860 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2861 exp
.X_op
= O_absent
;
2864 if (is_immediate_prefix (*p
))
2869 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2871 if (exp
.X_op
== O_absent
)
2873 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2875 set_syntax_error (_("missing shift amount"));
2878 operand
->shifter
.amount
= 0;
2880 else if (exp
.X_op
!= O_constant
)
2882 set_syntax_error (_("constant shift amount required"));
2885 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2887 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2892 operand
->shifter
.amount
= exp
.X_add_number
;
2893 operand
->shifter
.amount_present
= 1;
2896 operand
->shifter
.operator_present
= 1;
2897 operand
->shifter
.kind
= kind
;
2903 /* Parse a <shifter_operand> for a data processing instruction:
2906 #<immediate>, LSL #imm
2908 Validation of immediate operands is deferred to md_apply_fix.
2910 Return TRUE on success; otherwise return FALSE. */
2913 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
2914 enum parse_shift_mode mode
)
2918 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
2923 /* Accept an immediate expression. */
2924 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
2927 /* Accept optional LSL for arithmetic immediate values. */
2928 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
2929 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
2932 /* Not accept any shifter for logical immediate values. */
2933 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
2934 && parse_shift (&p
, operand
, mode
))
2936 set_syntax_error (_("unexpected shift operator"));
2944 /* Parse a <shifter_operand> for a data processing instruction:
2949 #<immediate>, LSL #imm
2951 where <shift> is handled by parse_shift above, and the last two
2952 cases are handled by the function above.
2954 Validation of immediate operands is deferred to md_apply_fix.
2956 Return TRUE on success; otherwise return FALSE. */
2959 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
2960 enum parse_shift_mode mode
)
2963 int isreg32
, isregzero
;
2964 enum aarch64_operand_class opd_class
2965 = aarch64_get_operand_class (operand
->type
);
2968 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
2970 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
2972 set_syntax_error (_("unexpected register in the immediate operand"));
2976 if (!isregzero
&& reg
== REG_SP
)
2978 set_syntax_error (BAD_SP
);
2982 operand
->reg
.regno
= reg
;
2983 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2985 /* Accept optional shift operation on register. */
2986 if (! skip_past_comma (str
))
2989 if (! parse_shift (str
, operand
, mode
))
2994 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
2997 (_("integer register expected in the extended/shifted operand "
3002 /* We have a shifted immediate variable. */
3003 return parse_shifter_operand_imm (str
, operand
, mode
);
3006 /* Return TRUE on success; return FALSE otherwise. */
3009 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3010 enum parse_shift_mode mode
)
3014 /* Determine if we have the sequence of characters #: or just :
3015 coming next. If we do, then we check for a :rello: relocation
3016 modifier. If we don't, punt the whole lot to
3017 parse_shifter_operand. */
3019 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3021 struct reloc_table_entry
*entry
;
3029 /* Try to parse a relocation. Anything else is an error. */
3030 if (!(entry
= find_reloc_table_entry (str
)))
3032 set_syntax_error (_("unknown relocation modifier"));
3036 if (entry
->add_type
== 0)
3039 (_("this relocation modifier is not allowed on this instruction"));
3043 /* Save str before we decompose it. */
3046 /* Next, we parse the expression. */
3047 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3050 /* Record the relocation type (use the ADD variant here). */
3051 inst
.reloc
.type
= entry
->add_type
;
3052 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3054 /* If str is empty, we've reached the end, stop here. */
3058 /* Otherwise, we have a shifted reloc modifier, so rewind to
3059 recover the variable name and continue parsing for the shifter. */
3061 return parse_shifter_operand_imm (str
, operand
, mode
);
3064 return parse_shifter_operand (str
, operand
, mode
);
3067 /* Parse all forms of an address expression. Information is written
3068 to *OPERAND and/or inst.reloc.
3070 The A64 instruction set has the following addressing modes:
3073 [base] // in SIMD ld/st structure
3074 [base{,#0}] // in ld/st exclusive
3076 [base,Xm{,LSL #imm}]
3077 [base,Xm,SXTX {#imm}]
3078 [base,Wm,(S|U)XTW {#imm}]
3083 [base],Xm // in SIMD ld/st structure
3084 PC-relative (literal)
3088 (As a convenience, the notation "=immediate" is permitted in conjunction
3089 with the pc-relative literal load instructions to automatically place an
3090 immediate value or symbolic address in a nearby literal pool and generate
3091 a hidden label which references it.)
3093 Upon a successful parsing, the address structure in *OPERAND will be
3094 filled in the following way:
3096 .base_regno = <base>
3097 .offset.is_reg // 1 if the offset is a register
3099 .offset.regno = <Rm>
3101 For different addressing modes defined in the A64 ISA:
3104 .pcrel=0; .preind=1; .postind=0; .writeback=0
3106 .pcrel=0; .preind=1; .postind=0; .writeback=1
3108 .pcrel=0; .preind=0; .postind=1; .writeback=1
3109 PC-relative (literal)
3110 .pcrel=1; .preind=1; .postind=0; .writeback=0
3112 The shift/extension information, if any, will be stored in .shifter.
3114 It is the caller's responsibility to check for addressing modes not
3115 supported by the instruction, and to set inst.reloc.type. */
3118 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
3119 int accept_reg_post_index
)
3123 int isreg32
, isregzero
;
3124 expressionS
*exp
= &inst
.reloc
.exp
;
3126 if (! skip_past_char (&p
, '['))
3128 /* =immediate or label. */
3129 operand
->addr
.pcrel
= 1;
3130 operand
->addr
.preind
= 1;
3132 /* #:<reloc_op>:<symbol> */
3133 skip_past_char (&p
, '#');
3134 if (reloc
&& skip_past_char (&p
, ':'))
3136 bfd_reloc_code_real_type ty
;
3137 struct reloc_table_entry
*entry
;
3139 /* Try to parse a relocation modifier. Anything else is
3141 entry
= find_reloc_table_entry (&p
);
3144 set_syntax_error (_("unknown relocation modifier"));
3148 switch (operand
->type
)
3150 case AARCH64_OPND_ADDR_PCREL21
:
3152 ty
= entry
->adr_type
;
3156 ty
= entry
->ld_literal_type
;
3163 (_("this relocation modifier is not allowed on this "
3169 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3171 set_syntax_error (_("invalid relocation expression"));
3175 /* #:<reloc_op>:<expr> */
3176 /* Record the relocation type. */
3177 inst
.reloc
.type
= ty
;
3178 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3183 if (skip_past_char (&p
, '='))
3184 /* =immediate; need to generate the literal in the literal pool. */
3185 inst
.gen_lit_pool
= 1;
3187 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3189 set_syntax_error (_("invalid address"));
3200 /* Accept SP and reject ZR */
3201 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
3202 if (reg
== PARSE_FAIL
|| isreg32
)
3204 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3207 operand
->addr
.base_regno
= reg
;
3210 if (skip_past_comma (&p
))
3213 operand
->addr
.preind
= 1;
3215 /* Reject SP and accept ZR */
3216 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3217 if (reg
!= PARSE_FAIL
)
3220 operand
->addr
.offset
.regno
= reg
;
3221 operand
->addr
.offset
.is_reg
= 1;
3222 /* Shifted index. */
3223 if (skip_past_comma (&p
))
3226 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3227 /* Use the diagnostics set in parse_shift, so not set new
3228 error message here. */
3232 [base,Xm{,LSL #imm}]
3233 [base,Xm,SXTX {#imm}]
3234 [base,Wm,(S|U)XTW {#imm}] */
3235 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3236 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3237 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3241 set_syntax_error (_("invalid use of 32-bit register offset"));
3247 set_syntax_error (_("invalid use of 64-bit register offset"));
3253 /* [Xn,#:<reloc_op>:<symbol> */
3254 skip_past_char (&p
, '#');
3255 if (reloc
&& skip_past_char (&p
, ':'))
3257 struct reloc_table_entry
*entry
;
3259 /* Try to parse a relocation modifier. Anything else is
3261 if (!(entry
= find_reloc_table_entry (&p
)))
3263 set_syntax_error (_("unknown relocation modifier"));
3267 if (entry
->ldst_type
== 0)
3270 (_("this relocation modifier is not allowed on this "
3275 /* [Xn,#:<reloc_op>: */
3276 /* We now have the group relocation table entry corresponding to
3277 the name in the assembler source. Next, we parse the
3279 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3281 set_syntax_error (_("invalid relocation expression"));
3285 /* [Xn,#:<reloc_op>:<expr> */
3286 /* Record the load/store relocation type. */
3287 inst
.reloc
.type
= entry
->ldst_type
;
3288 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3290 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3292 set_syntax_error (_("invalid expression in the address"));
3299 if (! skip_past_char (&p
, ']'))
3301 set_syntax_error (_("']' expected"));
3305 if (skip_past_char (&p
, '!'))
3307 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3309 set_syntax_error (_("register offset not allowed in pre-indexed "
3310 "addressing mode"));
3314 operand
->addr
.writeback
= 1;
3316 else if (skip_past_comma (&p
))
3319 operand
->addr
.postind
= 1;
3320 operand
->addr
.writeback
= 1;
3322 if (operand
->addr
.preind
)
3324 set_syntax_error (_("cannot combine pre- and post-indexing"));
3328 if (accept_reg_post_index
3329 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3330 &isregzero
)) != PARSE_FAIL
)
3335 set_syntax_error (_("invalid 32-bit register offset"));
3338 operand
->addr
.offset
.regno
= reg
;
3339 operand
->addr
.offset
.is_reg
= 1;
3341 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3344 set_syntax_error (_("invalid expression in the address"));
3349 /* If at this point neither .preind nor .postind is set, we have a
3350 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3351 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3353 if (operand
->addr
.writeback
)
3356 set_syntax_error (_("missing offset in the pre-indexed address"));
3359 operand
->addr
.preind
= 1;
3360 inst
.reloc
.exp
.X_op
= O_constant
;
3361 inst
.reloc
.exp
.X_add_number
= 0;
3368 /* Return TRUE on success; otherwise return FALSE. */
3370 parse_address (char **str
, aarch64_opnd_info
*operand
,
3371 int accept_reg_post_index
)
3373 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3376 /* Return TRUE on success; otherwise return FALSE. */
3378 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3380 return parse_address_main (str
, operand
, 1, 0);
3383 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3384 Return TRUE on success; otherwise return FALSE. */
3386 parse_half (char **str
, int *internal_fixup_p
)
3392 skip_past_char (&p
, '#');
3394 gas_assert (internal_fixup_p
);
3395 *internal_fixup_p
= 0;
3399 struct reloc_table_entry
*entry
;
3401 /* Try to parse a relocation. Anything else is an error. */
3403 if (!(entry
= find_reloc_table_entry (&p
)))
3405 set_syntax_error (_("unknown relocation modifier"));
3409 if (entry
->movw_type
== 0)
3412 (_("this relocation modifier is not allowed on this instruction"));
3416 inst
.reloc
.type
= entry
->movw_type
;
3419 *internal_fixup_p
= 1;
3421 /* Avoid parsing a register as a general symbol. */
3423 if (aarch64_reg_parse_32_64 (&p
, 0, 0, &dummy
, &dummy
) != PARSE_FAIL
)
3427 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3434 /* Parse an operand for an ADRP instruction:
3436 Return TRUE on success; otherwise return FALSE. */
3439 parse_adrp (char **str
)
3446 struct reloc_table_entry
*entry
;
3448 /* Try to parse a relocation. Anything else is an error. */
3450 if (!(entry
= find_reloc_table_entry (&p
)))
3452 set_syntax_error (_("unknown relocation modifier"));
3456 if (entry
->adrp_type
== 0)
3459 (_("this relocation modifier is not allowed on this instruction"));
3463 inst
.reloc
.type
= entry
->adrp_type
;
3466 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3468 inst
.reloc
.pc_rel
= 1;
3470 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3477 /* Miscellaneous. */
3479 /* Parse an option for a preload instruction. Returns the encoding for the
3480 option, or PARSE_FAIL. */
3483 parse_pldop (char **str
)
3486 const struct aarch64_name_value_pair
*o
;
3489 while (ISALNUM (*q
))
3492 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3500 /* Parse an option for a barrier instruction. Returns the encoding for the
3501 option, or PARSE_FAIL. */
3504 parse_barrier (char **str
)
3507 const asm_barrier_opt
*o
;
3510 while (ISALPHA (*q
))
3513 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3521 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3522 Returns the encoding for the option, or PARSE_FAIL.
3524 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3525 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3527 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3528 field, otherwise as a system register.
3532 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3533 int imple_defined_p
, int pstatefield_p
)
3537 const aarch64_sys_reg
*o
;
3541 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3543 *p
++ = TOLOWER (*q
);
3545 /* Assert that BUF be large enough. */
3546 gas_assert (p
- buf
== q
- *str
);
3548 o
= hash_find (sys_regs
, buf
);
3551 if (!imple_defined_p
)
3555 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3556 unsigned int op0
, op1
, cn
, cm
, op2
;
3558 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3561 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3563 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3568 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3569 as_bad (_("selected processor does not support PSTATE field "
3571 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3572 as_bad (_("selected processor does not support system register "
3574 if (aarch64_sys_reg_deprecated_p (o
))
3575 as_warn (_("system register name '%s' is deprecated and may be "
3576 "removed in a future release"), buf
);
3584 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3585 for the option, or NULL. */
3587 static const aarch64_sys_ins_reg
*
3588 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3592 const aarch64_sys_ins_reg
*o
;
3595 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3597 *p
++ = TOLOWER (*q
);
3600 o
= hash_find (sys_ins_regs
, buf
);
3608 #define po_char_or_fail(chr) do { \
3609 if (! skip_past_char (&str, chr)) \
3613 #define po_reg_or_fail(regtype) do { \
3614 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3615 if (val == PARSE_FAIL) \
3617 set_default_error (); \
3622 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3623 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3624 &isreg32, &isregzero); \
3625 if (val == PARSE_FAIL) \
3627 set_default_error (); \
3630 info->reg.regno = val; \
3632 info->qualifier = AARCH64_OPND_QLF_W; \
3634 info->qualifier = AARCH64_OPND_QLF_X; \
3637 #define po_imm_nc_or_fail() do { \
3638 if (! parse_constant_immediate (&str, &val)) \
3642 #define po_imm_or_fail(min, max) do { \
3643 if (! parse_constant_immediate (&str, &val)) \
3645 if (val < min || val > max) \
3647 set_fatal_syntax_error (_("immediate value out of range "\
3648 #min " to "#max)); \
3653 #define po_misc_or_fail(expr) do { \
3658 /* encode the 12-bit imm field of Add/sub immediate */
3659 static inline uint32_t
3660 encode_addsub_imm (uint32_t imm
)
3665 /* encode the shift amount field of Add/sub immediate */
3666 static inline uint32_t
3667 encode_addsub_imm_shift_amount (uint32_t cnt
)
3673 /* encode the imm field of Adr instruction */
3674 static inline uint32_t
3675 encode_adr_imm (uint32_t imm
)
3677 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3678 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3681 /* encode the immediate field of Move wide immediate */
3682 static inline uint32_t
3683 encode_movw_imm (uint32_t imm
)
3688 /* encode the 26-bit offset of unconditional branch */
3689 static inline uint32_t
3690 encode_branch_ofs_26 (uint32_t ofs
)
3692 return ofs
& ((1 << 26) - 1);
3695 /* encode the 19-bit offset of conditional branch and compare & branch */
3696 static inline uint32_t
3697 encode_cond_branch_ofs_19 (uint32_t ofs
)
3699 return (ofs
& ((1 << 19) - 1)) << 5;
3702 /* encode the 19-bit offset of ld literal */
3703 static inline uint32_t
3704 encode_ld_lit_ofs_19 (uint32_t ofs
)
3706 return (ofs
& ((1 << 19) - 1)) << 5;
3709 /* Encode the 14-bit offset of test & branch. */
3710 static inline uint32_t
3711 encode_tst_branch_ofs_14 (uint32_t ofs
)
3713 return (ofs
& ((1 << 14) - 1)) << 5;
3716 /* Encode the 16-bit imm field of svc/hvc/smc. */
3717 static inline uint32_t
3718 encode_svc_imm (uint32_t imm
)
3723 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3724 static inline uint32_t
3725 reencode_addsub_switch_add_sub (uint32_t opcode
)
3727 return opcode
^ (1 << 30);
3730 static inline uint32_t
3731 reencode_movzn_to_movz (uint32_t opcode
)
3733 return opcode
| (1 << 30);
3736 static inline uint32_t
3737 reencode_movzn_to_movn (uint32_t opcode
)
3739 return opcode
& ~(1 << 30);
3742 /* Overall per-instruction processing. */
3744 /* We need to be able to fix up arbitrary expressions in some statements.
3745 This is so that we can handle symbols that are an arbitrary distance from
3746 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3747 which returns part of an address in a form which will be valid for
3748 a data instruction. We do this by pushing the expression into a symbol
3749 in the expr_section, and creating a fix for that. */
3752 fix_new_aarch64 (fragS
* frag
,
3754 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3764 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3768 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3775 /* Diagnostics on operands errors. */
3777 /* By default, output verbose error message.
3778 Disable the verbose error message by -mno-verbose-error. */
3779 static int verbose_error_p
= 1;
3781 #ifdef DEBUG_AARCH64
3782 /* N.B. this is only for the purpose of debugging. */
3783 const char* operand_mismatch_kind_names
[] =
3786 "AARCH64_OPDE_RECOVERABLE",
3787 "AARCH64_OPDE_SYNTAX_ERROR",
3788 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3789 "AARCH64_OPDE_INVALID_VARIANT",
3790 "AARCH64_OPDE_OUT_OF_RANGE",
3791 "AARCH64_OPDE_UNALIGNED",
3792 "AARCH64_OPDE_REG_LIST",
3793 "AARCH64_OPDE_OTHER_ERROR",
3795 #endif /* DEBUG_AARCH64 */
3797 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3799 When multiple errors of different kinds are found in the same assembly
3800 line, only the error of the highest severity will be picked up for
3801 issuing the diagnostics. */
3803 static inline bfd_boolean
3804 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3805 enum aarch64_operand_error_kind rhs
)
3807 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3808 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3809 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3810 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3811 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3812 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3813 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3814 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3818 /* Helper routine to get the mnemonic name from the assembly instruction
3819 line; should only be called for the diagnosis purpose, as there is
3820 string copy operation involved, which may affect the runtime
3821 performance if used in elsewhere. */
3824 get_mnemonic_name (const char *str
)
3826 static char mnemonic
[32];
3829 /* Get the first 15 bytes and assume that the full name is included. */
3830 strncpy (mnemonic
, str
, 31);
3831 mnemonic
[31] = '\0';
3833 /* Scan up to the end of the mnemonic, which must end in white space,
3834 '.', or end of string. */
3835 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3840 /* Append '...' to the truncated long name. */
3841 if (ptr
- mnemonic
== 31)
3842 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3848 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3850 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3851 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3854 /* Data strutures storing one user error in the assembly code related to
3857 struct operand_error_record
3859 const aarch64_opcode
*opcode
;
3860 aarch64_operand_error detail
;
3861 struct operand_error_record
*next
;
3864 typedef struct operand_error_record operand_error_record
;
3866 struct operand_errors
3868 operand_error_record
*head
;
3869 operand_error_record
*tail
;
3872 typedef struct operand_errors operand_errors
;
3874 /* Top-level data structure reporting user errors for the current line of
3876 The way md_assemble works is that all opcodes sharing the same mnemonic
3877 name are iterated to find a match to the assembly line. In this data
3878 structure, each of the such opcodes will have one operand_error_record
3879 allocated and inserted. In other words, excessive errors related with
3880 a single opcode are disregarded. */
3881 operand_errors operand_error_report
;
3883 /* Free record nodes. */
3884 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
3886 /* Initialize the data structure that stores the operand mismatch
3887 information on assembling one line of the assembly code. */
3889 init_operand_error_report (void)
3891 if (operand_error_report
.head
!= NULL
)
3893 gas_assert (operand_error_report
.tail
!= NULL
);
3894 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
3895 free_opnd_error_record_nodes
= operand_error_report
.head
;
3896 operand_error_report
.head
= NULL
;
3897 operand_error_report
.tail
= NULL
;
3900 gas_assert (operand_error_report
.tail
== NULL
);
3903 /* Return TRUE if some operand error has been recorded during the
3904 parsing of the current assembly line using the opcode *OPCODE;
3905 otherwise return FALSE. */
3906 static inline bfd_boolean
3907 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
3909 operand_error_record
*record
= operand_error_report
.head
;
3910 return record
&& record
->opcode
== opcode
;
3913 /* Add the error record *NEW_RECORD to operand_error_report. The record's
3914 OPCODE field is initialized with OPCODE.
3915 N.B. only one record for each opcode, i.e. the maximum of one error is
3916 recorded for each instruction template. */
3919 add_operand_error_record (const operand_error_record
* new_record
)
3921 const aarch64_opcode
*opcode
= new_record
->opcode
;
3922 operand_error_record
* record
= operand_error_report
.head
;
3924 /* The record may have been created for this opcode. If not, we need
3926 if (! opcode_has_operand_error_p (opcode
))
3928 /* Get one empty record. */
3929 if (free_opnd_error_record_nodes
== NULL
)
3931 record
= xmalloc (sizeof (operand_error_record
));
3937 record
= free_opnd_error_record_nodes
;
3938 free_opnd_error_record_nodes
= record
->next
;
3940 record
->opcode
= opcode
;
3941 /* Insert at the head. */
3942 record
->next
= operand_error_report
.head
;
3943 operand_error_report
.head
= record
;
3944 if (operand_error_report
.tail
== NULL
)
3945 operand_error_report
.tail
= record
;
3947 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
3948 && record
->detail
.index
<= new_record
->detail
.index
3949 && operand_error_higher_severity_p (record
->detail
.kind
,
3950 new_record
->detail
.kind
))
3952 /* In the case of multiple errors found on operands related with a
3953 single opcode, only record the error of the leftmost operand and
3954 only if the error is of higher severity. */
3955 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
3956 " the existing error %s on operand %d",
3957 operand_mismatch_kind_names
[new_record
->detail
.kind
],
3958 new_record
->detail
.index
,
3959 operand_mismatch_kind_names
[record
->detail
.kind
],
3960 record
->detail
.index
);
3964 record
->detail
= new_record
->detail
;
3968 record_operand_error_info (const aarch64_opcode
*opcode
,
3969 aarch64_operand_error
*error_info
)
3971 operand_error_record record
;
3972 record
.opcode
= opcode
;
3973 record
.detail
= *error_info
;
3974 add_operand_error_record (&record
);
3977 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
3978 error message *ERROR, for operand IDX (count from 0). */
3981 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
3982 enum aarch64_operand_error_kind kind
,
3985 aarch64_operand_error info
;
3986 memset(&info
, 0, sizeof (info
));
3990 record_operand_error_info (opcode
, &info
);
3994 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
3995 enum aarch64_operand_error_kind kind
,
3996 const char* error
, const int *extra_data
)
3998 aarch64_operand_error info
;
4002 info
.data
[0] = extra_data
[0];
4003 info
.data
[1] = extra_data
[1];
4004 info
.data
[2] = extra_data
[2];
4005 record_operand_error_info (opcode
, &info
);
4009 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4010 const char* error
, int lower_bound
,
4013 int data
[3] = {lower_bound
, upper_bound
, 0};
4014 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4018 /* Remove the operand error record for *OPCODE. */
4019 static void ATTRIBUTE_UNUSED
4020 remove_operand_error_record (const aarch64_opcode
*opcode
)
4022 if (opcode_has_operand_error_p (opcode
))
4024 operand_error_record
* record
= operand_error_report
.head
;
4025 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4026 operand_error_report
.head
= record
->next
;
4027 record
->next
= free_opnd_error_record_nodes
;
4028 free_opnd_error_record_nodes
= record
;
4029 if (operand_error_report
.head
== NULL
)
4031 gas_assert (operand_error_report
.tail
== record
);
4032 operand_error_report
.tail
= NULL
;
4037 /* Given the instruction in *INSTR, return the index of the best matched
4038 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4040 Return -1 if there is no qualifier sequence; return the first match
4041 if there is multiple matches found. */
4044 find_best_match (const aarch64_inst
*instr
,
4045 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4047 int i
, num_opnds
, max_num_matched
, idx
;
4049 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4052 DEBUG_TRACE ("no operand");
4056 max_num_matched
= 0;
4059 /* For each pattern. */
4060 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4063 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4065 /* Most opcodes has much fewer patterns in the list. */
4066 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
4068 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4069 if (i
!= 0 && idx
== -1)
4070 /* If nothing has been matched, return the 1st sequence. */
4075 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4076 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4079 if (num_matched
> max_num_matched
)
4081 max_num_matched
= num_matched
;
4086 DEBUG_TRACE ("return with %d", idx
);
4090 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4091 corresponding operands in *INSTR. */
4094 assign_qualifier_sequence (aarch64_inst
*instr
,
4095 const aarch64_opnd_qualifier_t
*qualifiers
)
4098 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4099 gas_assert (num_opnds
);
4100 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4101 instr
->operands
[i
].qualifier
= *qualifiers
;
4104 /* Print operands for the diagnosis purpose. */
4107 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4108 const aarch64_opnd_info
*opnds
)
4112 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4114 const size_t size
= 128;
4117 /* We regard the opcode operand info more, however we also look into
4118 the inst->operands to support the disassembling of the optional
4120 The two operand code should be the same in all cases, apart from
4121 when the operand can be optional. */
4122 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4123 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4126 /* Generate the operand string in STR. */
4127 aarch64_print_operand (str
, size
, 0, opcode
, opnds
, i
, NULL
, NULL
);
4131 strcat (buf
, i
== 0 ? " " : ",");
4133 /* Append the operand string. */
4138 /* Send to stderr a string as information. */
4141 output_info (const char *format
, ...)
4147 as_where (&file
, &line
);
4151 fprintf (stderr
, "%s:%u: ", file
, line
);
4153 fprintf (stderr
, "%s: ", file
);
4155 fprintf (stderr
, _("Info: "));
4156 va_start (args
, format
);
4157 vfprintf (stderr
, format
, args
);
4159 (void) putc ('\n', stderr
);
4162 /* Output one operand error record. */
4165 output_operand_error_record (const operand_error_record
*record
, char *str
)
4167 const aarch64_operand_error
*detail
= &record
->detail
;
4168 int idx
= detail
->index
;
4169 const aarch64_opcode
*opcode
= record
->opcode
;
4170 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4171 : AARCH64_OPND_NIL
);
4173 switch (detail
->kind
)
4175 case AARCH64_OPDE_NIL
:
4179 case AARCH64_OPDE_SYNTAX_ERROR
:
4180 case AARCH64_OPDE_RECOVERABLE
:
4181 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4182 case AARCH64_OPDE_OTHER_ERROR
:
4183 /* Use the prepared error message if there is, otherwise use the
4184 operand description string to describe the error. */
4185 if (detail
->error
!= NULL
)
4188 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4190 as_bad (_("%s at operand %d -- `%s'"),
4191 detail
->error
, idx
+ 1, str
);
4195 gas_assert (idx
>= 0);
4196 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4197 aarch64_get_operand_desc (opd_code
), str
);
4201 case AARCH64_OPDE_INVALID_VARIANT
:
4202 as_bad (_("operand mismatch -- `%s'"), str
);
4203 if (verbose_error_p
)
4205 /* We will try to correct the erroneous instruction and also provide
4206 more information e.g. all other valid variants.
4208 The string representation of the corrected instruction and other
4209 valid variants are generated by
4211 1) obtaining the intermediate representation of the erroneous
4213 2) manipulating the IR, e.g. replacing the operand qualifier;
4214 3) printing out the instruction by calling the printer functions
4215 shared with the disassembler.
4217 The limitation of this method is that the exact input assembly
4218 line cannot be accurately reproduced in some cases, for example an
4219 optional operand present in the actual assembly line will be
4220 omitted in the output; likewise for the optional syntax rules,
4221 e.g. the # before the immediate. Another limitation is that the
4222 assembly symbols and relocation operations in the assembly line
4223 currently cannot be printed out in the error report. Last but not
4224 least, when there is other error(s) co-exist with this error, the
4225 'corrected' instruction may be still incorrect, e.g. given
4226 'ldnp h0,h1,[x0,#6]!'
4227 this diagnosis will provide the version:
4228 'ldnp s0,s1,[x0,#6]!'
4229 which is still not right. */
4230 size_t len
= strlen (get_mnemonic_name (str
));
4233 const size_t size
= 2048;
4235 aarch64_inst
*inst_base
= &inst
.base
;
4236 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4239 reset_aarch64_instruction (&inst
);
4240 inst_base
->opcode
= opcode
;
4242 /* Reset the error report so that there is no side effect on the
4243 following operand parsing. */
4244 init_operand_error_report ();
4247 result
= parse_operands (str
+ len
, opcode
)
4248 && programmer_friendly_fixup (&inst
);
4249 gas_assert (result
);
4250 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4252 gas_assert (!result
);
4254 /* Find the most matched qualifier sequence. */
4255 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4256 gas_assert (qlf_idx
> -1);
4258 /* Assign the qualifiers. */
4259 assign_qualifier_sequence (inst_base
,
4260 opcode
->qualifiers_list
[qlf_idx
]);
4262 /* Print the hint. */
4263 output_info (_(" did you mean this?"));
4264 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4265 print_operands (buf
, opcode
, inst_base
->operands
);
4266 output_info (_(" %s"), buf
);
4268 /* Print out other variant(s) if there is any. */
4270 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4271 output_info (_(" other valid variant(s):"));
4273 /* For each pattern. */
4274 qualifiers_list
= opcode
->qualifiers_list
;
4275 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4277 /* Most opcodes has much fewer patterns in the list.
4278 First NIL qualifier indicates the end in the list. */
4279 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4284 /* Mnemonics name. */
4285 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4287 /* Assign the qualifiers. */
4288 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4290 /* Print instruction. */
4291 print_operands (buf
, opcode
, inst_base
->operands
);
4293 output_info (_(" %s"), buf
);
4299 case AARCH64_OPDE_OUT_OF_RANGE
:
4300 if (detail
->data
[0] != detail
->data
[1])
4301 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4302 detail
->error
? detail
->error
: _("immediate value"),
4303 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4305 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4306 detail
->error
? detail
->error
: _("immediate value"),
4307 detail
->data
[0], idx
+ 1, str
);
4310 case AARCH64_OPDE_REG_LIST
:
4311 if (detail
->data
[0] == 1)
4312 as_bad (_("invalid number of registers in the list; "
4313 "only 1 register is expected at operand %d -- `%s'"),
4316 as_bad (_("invalid number of registers in the list; "
4317 "%d registers are expected at operand %d -- `%s'"),
4318 detail
->data
[0], idx
+ 1, str
);
4321 case AARCH64_OPDE_UNALIGNED
:
4322 as_bad (_("immediate value should be a multiple of "
4323 "%d at operand %d -- `%s'"),
4324 detail
->data
[0], idx
+ 1, str
);
4333 /* Process and output the error message about the operand mismatching.
4335 When this function is called, the operand error information had
4336 been collected for an assembly line and there will be multiple
4337 errors in the case of mulitple instruction templates; output the
4338 error message that most closely describes the problem. */
4341 output_operand_error_report (char *str
)
4343 int largest_error_pos
;
4344 const char *msg
= NULL
;
4345 enum aarch64_operand_error_kind kind
;
4346 operand_error_record
*curr
;
4347 operand_error_record
*head
= operand_error_report
.head
;
4348 operand_error_record
*record
= NULL
;
4350 /* No error to report. */
4354 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4356 /* Only one error. */
4357 if (head
== operand_error_report
.tail
)
4359 DEBUG_TRACE ("single opcode entry with error kind: %s",
4360 operand_mismatch_kind_names
[head
->detail
.kind
]);
4361 output_operand_error_record (head
, str
);
4365 /* Find the error kind of the highest severity. */
4366 DEBUG_TRACE ("multiple opcode entres with error kind");
4367 kind
= AARCH64_OPDE_NIL
;
4368 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4370 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4371 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4372 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4373 kind
= curr
->detail
.kind
;
4375 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4377 /* Pick up one of errors of KIND to report. */
4378 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4379 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4381 if (curr
->detail
.kind
!= kind
)
4383 /* If there are multiple errors, pick up the one with the highest
4384 mismatching operand index. In the case of multiple errors with
4385 the equally highest operand index, pick up the first one or the
4386 first one with non-NULL error message. */
4387 if (curr
->detail
.index
> largest_error_pos
4388 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4389 && curr
->detail
.error
!= NULL
))
4391 largest_error_pos
= curr
->detail
.index
;
4393 msg
= record
->detail
.error
;
4397 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4398 DEBUG_TRACE ("Pick up error kind %s to report",
4399 operand_mismatch_kind_names
[record
->detail
.kind
]);
4402 output_operand_error_record (record
, str
);
4405 /* Write an AARCH64 instruction to buf - always little-endian. */
4407 put_aarch64_insn (char *buf
, uint32_t insn
)
4409 unsigned char *where
= (unsigned char *) buf
;
4411 where
[1] = insn
>> 8;
4412 where
[2] = insn
>> 16;
4413 where
[3] = insn
>> 24;
4417 get_aarch64_insn (char *buf
)
4419 unsigned char *where
= (unsigned char *) buf
;
4421 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4426 output_inst (struct aarch64_inst
*new_inst
)
4430 to
= frag_more (INSN_SIZE
);
4432 frag_now
->tc_frag_data
.recorded
= 1;
4434 put_aarch64_insn (to
, inst
.base
.value
);
4436 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4438 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4439 INSN_SIZE
, &inst
.reloc
.exp
,
4442 DEBUG_TRACE ("Prepared relocation fix up");
4443 /* Don't check the addend value against the instruction size,
4444 that's the job of our code in md_apply_fix(). */
4445 fixp
->fx_no_overflow
= 1;
4446 if (new_inst
!= NULL
)
4447 fixp
->tc_fix_data
.inst
= new_inst
;
4448 if (aarch64_gas_internal_fixup_p ())
4450 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4451 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4452 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4456 dwarf2_emit_insn (INSN_SIZE
);
4459 /* Link together opcodes of the same name. */
4463 aarch64_opcode
*opcode
;
4464 struct templates
*next
;
4467 typedef struct templates templates
;
4470 lookup_mnemonic (const char *start
, int len
)
4472 templates
*templ
= NULL
;
4474 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4478 /* Subroutine of md_assemble, responsible for looking up the primary
4479 opcode from the mnemonic the user wrote. STR points to the
4480 beginning of the mnemonic. */
4483 opcode_lookup (char **str
)
4486 const aarch64_cond
*cond
;
4490 /* Scan up to the end of the mnemonic, which must end in white space,
4491 '.', or end of string. */
4492 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4499 inst
.cond
= COND_ALWAYS
;
4501 /* Handle a possible condition. */
4504 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4507 inst
.cond
= cond
->value
;
4521 if (inst
.cond
== COND_ALWAYS
)
4523 /* Look for unaffixed mnemonic. */
4524 return lookup_mnemonic (base
, len
);
4528 /* append ".c" to mnemonic if conditional */
4529 memcpy (condname
, base
, len
);
4530 memcpy (condname
+ len
, ".c", 2);
4533 return lookup_mnemonic (base
, len
);
4539 /* Internal helper routine converting a vector neon_type_el structure
4540 *VECTYPE to a corresponding operand qualifier. */
4542 static inline aarch64_opnd_qualifier_t
4543 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4545 /* Element size in bytes indexed by neon_el_type. */
4546 const unsigned char ele_size
[5]
4549 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4550 goto vectype_conversion_fail
;
4552 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4554 if (vectype
->defined
& NTA_HASINDEX
)
4555 /* Vector element register. */
4556 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4559 /* Vector register. */
4560 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4562 if (reg_size
!= 16 && reg_size
!= 8)
4563 goto vectype_conversion_fail
;
4564 /* The conversion is calculated based on the relation of the order of
4565 qualifiers to the vector element size and vector register size. */
4566 offset
= (vectype
->type
== NT_q
)
4567 ? 8 : (vectype
->type
<< 1) + (reg_size
>> 4);
4568 gas_assert (offset
<= 8);
4569 return AARCH64_OPND_QLF_V_8B
+ offset
;
4572 vectype_conversion_fail
:
4573 first_error (_("bad vector arrangement type"));
4574 return AARCH64_OPND_QLF_NIL
;
4577 /* Process an optional operand that is found omitted from the assembly line.
4578 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4579 instruction's opcode entry while IDX is the index of this omitted operand.
4583 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4584 int idx
, aarch64_opnd_info
*operand
)
4586 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4587 gas_assert (optional_operand_p (opcode
, idx
));
4588 gas_assert (!operand
->present
);
4592 case AARCH64_OPND_Rd
:
4593 case AARCH64_OPND_Rn
:
4594 case AARCH64_OPND_Rm
:
4595 case AARCH64_OPND_Rt
:
4596 case AARCH64_OPND_Rt2
:
4597 case AARCH64_OPND_Rs
:
4598 case AARCH64_OPND_Ra
:
4599 case AARCH64_OPND_Rt_SYS
:
4600 case AARCH64_OPND_Rd_SP
:
4601 case AARCH64_OPND_Rn_SP
:
4602 case AARCH64_OPND_Fd
:
4603 case AARCH64_OPND_Fn
:
4604 case AARCH64_OPND_Fm
:
4605 case AARCH64_OPND_Fa
:
4606 case AARCH64_OPND_Ft
:
4607 case AARCH64_OPND_Ft2
:
4608 case AARCH64_OPND_Sd
:
4609 case AARCH64_OPND_Sn
:
4610 case AARCH64_OPND_Sm
:
4611 case AARCH64_OPND_Vd
:
4612 case AARCH64_OPND_Vn
:
4613 case AARCH64_OPND_Vm
:
4614 case AARCH64_OPND_VdD1
:
4615 case AARCH64_OPND_VnD1
:
4616 operand
->reg
.regno
= default_value
;
4619 case AARCH64_OPND_Ed
:
4620 case AARCH64_OPND_En
:
4621 case AARCH64_OPND_Em
:
4622 operand
->reglane
.regno
= default_value
;
4625 case AARCH64_OPND_IDX
:
4626 case AARCH64_OPND_BIT_NUM
:
4627 case AARCH64_OPND_IMMR
:
4628 case AARCH64_OPND_IMMS
:
4629 case AARCH64_OPND_SHLL_IMM
:
4630 case AARCH64_OPND_IMM_VLSL
:
4631 case AARCH64_OPND_IMM_VLSR
:
4632 case AARCH64_OPND_CCMP_IMM
:
4633 case AARCH64_OPND_FBITS
:
4634 case AARCH64_OPND_UIMM4
:
4635 case AARCH64_OPND_UIMM3_OP1
:
4636 case AARCH64_OPND_UIMM3_OP2
:
4637 case AARCH64_OPND_IMM
:
4638 case AARCH64_OPND_WIDTH
:
4639 case AARCH64_OPND_UIMM7
:
4640 case AARCH64_OPND_NZCV
:
4641 operand
->imm
.value
= default_value
;
4644 case AARCH64_OPND_EXCEPTION
:
4645 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4648 case AARCH64_OPND_BARRIER_ISB
:
4649 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4656 /* Process the relocation type for move wide instructions.
4657 Return TRUE on success; otherwise return FALSE. */
4660 process_movw_reloc_info (void)
4665 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4667 if (inst
.base
.opcode
->op
== OP_MOVK
)
4668 switch (inst
.reloc
.type
)
4670 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4671 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4672 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4673 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4674 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4675 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4677 (_("the specified relocation type is not allowed for MOVK"));
4683 switch (inst
.reloc
.type
)
4685 case BFD_RELOC_AARCH64_MOVW_G0
:
4686 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4687 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4688 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
4689 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
4690 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
4691 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4692 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4695 case BFD_RELOC_AARCH64_MOVW_G1
:
4696 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4697 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4698 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
4699 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
4700 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
4701 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4702 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4705 case BFD_RELOC_AARCH64_MOVW_G2
:
4706 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4707 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4708 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
4709 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4712 set_fatal_syntax_error
4713 (_("the specified relocation type is not allowed for 32-bit "
4719 case BFD_RELOC_AARCH64_MOVW_G3
:
4722 set_fatal_syntax_error
4723 (_("the specified relocation type is not allowed for 32-bit "
4730 /* More cases should be added when more MOVW-related relocation types
4731 are supported in GAS. */
4732 gas_assert (aarch64_gas_internal_fixup_p ());
4733 /* The shift amount should have already been set by the parser. */
4736 inst
.base
.operands
[1].shifter
.amount
= shift
;
4740 /* A primitive log caculator. */
4742 static inline unsigned int
4743 get_logsz (unsigned int size
)
4745 const unsigned char ls
[16] =
4746 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4752 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4753 return ls
[size
- 1];
4756 /* Determine and return the real reloc type code for an instruction
4757 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4759 static inline bfd_reloc_code_real_type
4760 ldst_lo12_determine_real_reloc_type (void)
4763 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4764 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4766 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
4768 BFD_RELOC_AARCH64_LDST8_LO12
,
4769 BFD_RELOC_AARCH64_LDST16_LO12
,
4770 BFD_RELOC_AARCH64_LDST32_LO12
,
4771 BFD_RELOC_AARCH64_LDST64_LO12
,
4772 BFD_RELOC_AARCH64_LDST128_LO12
4775 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
4776 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
4777 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
4778 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
4779 BFD_RELOC_AARCH64_NONE
4782 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
4783 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
4784 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
4785 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
4786 BFD_RELOC_AARCH64_NONE
4790 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
4791 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4793 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
4794 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4796 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4798 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4800 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4802 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4803 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4804 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
4805 gas_assert (logsz
<= 3);
4807 gas_assert (logsz
<= 4);
4809 /* In reloc.c, these pseudo relocation types should be defined in similar
4810 order as above reloc_ldst_lo12 array. Because the array index calcuation
4811 below relies on this. */
4812 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
4815 /* Check whether a register list REGINFO is valid. The registers must be
4816 numbered in increasing order (modulo 32), in increments of one or two.
4818 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4821 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4824 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4826 uint32_t i
, nb_regs
, prev_regno
, incr
;
4828 nb_regs
= 1 + (reginfo
& 0x3);
4830 prev_regno
= reginfo
& 0x1f;
4831 incr
= accept_alternate
? 2 : 1;
4833 for (i
= 1; i
< nb_regs
; ++i
)
4835 uint32_t curr_regno
;
4837 curr_regno
= reginfo
& 0x1f;
4838 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4840 prev_regno
= curr_regno
;
4846 /* Generic instruction operand parser. This does no encoding and no
4847 semantic validation; it merely squirrels values away in the inst
4848 structure. Returns TRUE or FALSE depending on whether the
4849 specified grammar matched. */
4852 parse_operands (char *str
, const aarch64_opcode
*opcode
)
4855 char *backtrack_pos
= 0;
4856 const enum aarch64_opnd
*operands
= opcode
->operands
;
4859 skip_whitespace (str
);
4861 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
4864 int isreg32
, isregzero
;
4865 int comma_skipped_p
= 0;
4866 aarch64_reg_type rtype
;
4867 struct neon_type_el vectype
;
4868 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
4870 DEBUG_TRACE ("parse operand %d", i
);
4872 /* Assign the operand code. */
4873 info
->type
= operands
[i
];
4875 if (optional_operand_p (opcode
, i
))
4877 /* Remember where we are in case we need to backtrack. */
4878 gas_assert (!backtrack_pos
);
4879 backtrack_pos
= str
;
4882 /* Expect comma between operands; the backtrack mechanizm will take
4883 care of cases of omitted optional operand. */
4884 if (i
> 0 && ! skip_past_char (&str
, ','))
4886 set_syntax_error (_("comma expected between operands"));
4890 comma_skipped_p
= 1;
4892 switch (operands
[i
])
4894 case AARCH64_OPND_Rd
:
4895 case AARCH64_OPND_Rn
:
4896 case AARCH64_OPND_Rm
:
4897 case AARCH64_OPND_Rt
:
4898 case AARCH64_OPND_Rt2
:
4899 case AARCH64_OPND_Rs
:
4900 case AARCH64_OPND_Ra
:
4901 case AARCH64_OPND_Rt_SYS
:
4902 case AARCH64_OPND_PAIRREG
:
4903 po_int_reg_or_fail (1, 0);
4906 case AARCH64_OPND_Rd_SP
:
4907 case AARCH64_OPND_Rn_SP
:
4908 po_int_reg_or_fail (0, 1);
4911 case AARCH64_OPND_Rm_EXT
:
4912 case AARCH64_OPND_Rm_SFT
:
4913 po_misc_or_fail (parse_shifter_operand
4914 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
4916 : SHIFTED_LOGIC_IMM
)));
4917 if (!info
->shifter
.operator_present
)
4919 /* Default to LSL if not present. Libopcodes prefers shifter
4920 kind to be explicit. */
4921 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
4922 info
->shifter
.kind
= AARCH64_MOD_LSL
;
4923 /* For Rm_EXT, libopcodes will carry out further check on whether
4924 or not stack pointer is used in the instruction (Recall that
4925 "the extend operator is not optional unless at least one of
4926 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
4930 case AARCH64_OPND_Fd
:
4931 case AARCH64_OPND_Fn
:
4932 case AARCH64_OPND_Fm
:
4933 case AARCH64_OPND_Fa
:
4934 case AARCH64_OPND_Ft
:
4935 case AARCH64_OPND_Ft2
:
4936 case AARCH64_OPND_Sd
:
4937 case AARCH64_OPND_Sn
:
4938 case AARCH64_OPND_Sm
:
4939 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
4940 if (val
== PARSE_FAIL
)
4942 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
4945 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
4947 info
->reg
.regno
= val
;
4948 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
4951 case AARCH64_OPND_Vd
:
4952 case AARCH64_OPND_Vn
:
4953 case AARCH64_OPND_Vm
:
4954 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4955 if (val
== PARSE_FAIL
)
4957 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4960 if (vectype
.defined
& NTA_HASINDEX
)
4963 info
->reg
.regno
= val
;
4964 info
->qualifier
= vectype_to_qualifier (&vectype
);
4965 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
4969 case AARCH64_OPND_VdD1
:
4970 case AARCH64_OPND_VnD1
:
4971 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4972 if (val
== PARSE_FAIL
)
4974 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
4977 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
4979 set_fatal_syntax_error
4980 (_("the top half of a 128-bit FP/SIMD register is expected"));
4983 info
->reg
.regno
= val
;
4984 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
4985 here; it is correct for the purpose of encoding/decoding since
4986 only the register number is explicitly encoded in the related
4987 instructions, although this appears a bit hacky. */
4988 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
4991 case AARCH64_OPND_Ed
:
4992 case AARCH64_OPND_En
:
4993 case AARCH64_OPND_Em
:
4994 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
4995 if (val
== PARSE_FAIL
)
4997 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5000 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5003 info
->reglane
.regno
= val
;
5004 info
->reglane
.index
= vectype
.index
;
5005 info
->qualifier
= vectype_to_qualifier (&vectype
);
5006 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5010 case AARCH64_OPND_LVn
:
5011 case AARCH64_OPND_LVt
:
5012 case AARCH64_OPND_LVt_AL
:
5013 case AARCH64_OPND_LEt
:
5014 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
5016 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5018 set_fatal_syntax_error (_("invalid register list"));
5021 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5022 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5023 if (operands
[i
] == AARCH64_OPND_LEt
)
5025 if (!(vectype
.defined
& NTA_HASINDEX
))
5027 info
->reglist
.has_index
= 1;
5028 info
->reglist
.index
= vectype
.index
;
5030 else if (!(vectype
.defined
& NTA_HASTYPE
))
5032 info
->qualifier
= vectype_to_qualifier (&vectype
);
5033 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5037 case AARCH64_OPND_Cn
:
5038 case AARCH64_OPND_Cm
:
5039 po_reg_or_fail (REG_TYPE_CN
);
5042 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
5045 inst
.base
.operands
[i
].reg
.regno
= val
;
5048 case AARCH64_OPND_SHLL_IMM
:
5049 case AARCH64_OPND_IMM_VLSR
:
5050 po_imm_or_fail (1, 64);
5051 info
->imm
.value
= val
;
5054 case AARCH64_OPND_CCMP_IMM
:
5055 case AARCH64_OPND_FBITS
:
5056 case AARCH64_OPND_UIMM4
:
5057 case AARCH64_OPND_UIMM3_OP1
:
5058 case AARCH64_OPND_UIMM3_OP2
:
5059 case AARCH64_OPND_IMM_VLSL
:
5060 case AARCH64_OPND_IMM
:
5061 case AARCH64_OPND_WIDTH
:
5062 po_imm_nc_or_fail ();
5063 info
->imm
.value
= val
;
5066 case AARCH64_OPND_UIMM7
:
5067 po_imm_or_fail (0, 127);
5068 info
->imm
.value
= val
;
5071 case AARCH64_OPND_IDX
:
5072 case AARCH64_OPND_BIT_NUM
:
5073 case AARCH64_OPND_IMMR
:
5074 case AARCH64_OPND_IMMS
:
5075 po_imm_or_fail (0, 63);
5076 info
->imm
.value
= val
;
5079 case AARCH64_OPND_IMM0
:
5080 po_imm_nc_or_fail ();
5083 set_fatal_syntax_error (_("immediate zero expected"));
5086 info
->imm
.value
= 0;
5089 case AARCH64_OPND_FPIMM0
:
5092 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5093 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5094 it is probably not worth the effort to support it. */
5095 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
5096 && !(res2
= parse_constant_immediate (&str
, &val
)))
5098 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5100 info
->imm
.value
= 0;
5101 info
->imm
.is_fp
= 1;
5104 set_fatal_syntax_error (_("immediate zero expected"));
5108 case AARCH64_OPND_IMM_MOV
:
5111 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5112 reg_name_p (str
, REG_TYPE_VN
))
5115 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5117 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5118 later. fix_mov_imm_insn will try to determine a machine
5119 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5120 message if the immediate cannot be moved by a single
5122 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5123 inst
.base
.operands
[i
].skip
= 1;
5127 case AARCH64_OPND_SIMD_IMM
:
5128 case AARCH64_OPND_SIMD_IMM_SFT
:
5129 if (! parse_big_immediate (&str
, &val
))
5131 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5133 /* need_libopcodes_p */ 1,
5136 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5137 shift, we don't check it here; we leave the checking to
5138 the libopcodes (operand_general_constraint_met_p). By
5139 doing this, we achieve better diagnostics. */
5140 if (skip_past_comma (&str
)
5141 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5143 if (!info
->shifter
.operator_present
5144 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5146 /* Default to LSL if not present. Libopcodes prefers shifter
5147 kind to be explicit. */
5148 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5149 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5153 case AARCH64_OPND_FPIMM
:
5154 case AARCH64_OPND_SIMD_FPIMM
:
5158 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
5160 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
5164 set_fatal_syntax_error (_("invalid floating-point constant"));
5167 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5168 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5172 case AARCH64_OPND_LIMM
:
5173 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5174 SHIFTED_LOGIC_IMM
));
5175 if (info
->shifter
.operator_present
)
5177 set_fatal_syntax_error
5178 (_("shift not allowed for bitmask immediate"));
5181 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5183 /* need_libopcodes_p */ 1,
5187 case AARCH64_OPND_AIMM
:
5188 if (opcode
->op
== OP_ADD
)
5189 /* ADD may have relocation types. */
5190 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5191 SHIFTED_ARITH_IMM
));
5193 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5194 SHIFTED_ARITH_IMM
));
5195 switch (inst
.reloc
.type
)
5197 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5198 info
->shifter
.amount
= 12;
5200 case BFD_RELOC_UNUSED
:
5201 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5202 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5203 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5204 inst
.reloc
.pc_rel
= 0;
5209 info
->imm
.value
= 0;
5210 if (!info
->shifter
.operator_present
)
5212 /* Default to LSL if not present. Libopcodes prefers shifter
5213 kind to be explicit. */
5214 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5215 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5219 case AARCH64_OPND_HALF
:
5221 /* #<imm16> or relocation. */
5222 int internal_fixup_p
;
5223 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5224 if (internal_fixup_p
)
5225 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5226 skip_whitespace (str
);
5227 if (skip_past_comma (&str
))
5229 /* {, LSL #<shift>} */
5230 if (! aarch64_gas_internal_fixup_p ())
5232 set_fatal_syntax_error (_("can't mix relocation modifier "
5233 "with explicit shift"));
5236 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5239 inst
.base
.operands
[i
].shifter
.amount
= 0;
5240 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5241 inst
.base
.operands
[i
].imm
.value
= 0;
5242 if (! process_movw_reloc_info ())
5247 case AARCH64_OPND_EXCEPTION
:
5248 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
5249 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5251 /* need_libopcodes_p */ 0,
5255 case AARCH64_OPND_NZCV
:
5257 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5261 info
->imm
.value
= nzcv
->value
;
5264 po_imm_or_fail (0, 15);
5265 info
->imm
.value
= val
;
5269 case AARCH64_OPND_COND
:
5270 case AARCH64_OPND_COND1
:
5271 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5273 if (info
->cond
== NULL
)
5275 set_syntax_error (_("invalid condition"));
5278 else if (operands
[i
] == AARCH64_OPND_COND1
5279 && (info
->cond
->value
& 0xe) == 0xe)
5281 /* Not allow AL or NV. */
5282 set_default_error ();
5287 case AARCH64_OPND_ADDR_ADRP
:
5288 po_misc_or_fail (parse_adrp (&str
));
5289 /* Clear the value as operand needs to be relocated. */
5290 info
->imm
.value
= 0;
5293 case AARCH64_OPND_ADDR_PCREL14
:
5294 case AARCH64_OPND_ADDR_PCREL19
:
5295 case AARCH64_OPND_ADDR_PCREL21
:
5296 case AARCH64_OPND_ADDR_PCREL26
:
5297 po_misc_or_fail (parse_address_reloc (&str
, info
));
5298 if (!info
->addr
.pcrel
)
5300 set_syntax_error (_("invalid pc-relative address"));
5303 if (inst
.gen_lit_pool
5304 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5306 /* Only permit "=value" in the literal load instructions.
5307 The literal will be generated by programmer_friendly_fixup. */
5308 set_syntax_error (_("invalid use of \"=immediate\""));
5311 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5313 set_syntax_error (_("unrecognized relocation suffix"));
5316 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5318 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5319 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5323 info
->imm
.value
= 0;
5324 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5325 switch (opcode
->iclass
)
5329 /* e.g. CBZ or B.COND */
5330 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5331 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5335 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5336 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5340 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5342 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5343 : BFD_RELOC_AARCH64_JUMP26
;
5346 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5347 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5350 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5351 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5357 inst
.reloc
.pc_rel
= 1;
5361 case AARCH64_OPND_ADDR_SIMPLE
:
5362 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5363 /* [<Xn|SP>{, #<simm>}] */
5364 po_char_or_fail ('[');
5365 po_reg_or_fail (REG_TYPE_R64_SP
);
5366 /* Accept optional ", #0". */
5367 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5368 && skip_past_char (&str
, ','))
5370 skip_past_char (&str
, '#');
5371 if (! skip_past_char (&str
, '0'))
5373 set_fatal_syntax_error
5374 (_("the optional immediate offset can only be 0"));
5378 po_char_or_fail (']');
5379 info
->addr
.base_regno
= val
;
5382 case AARCH64_OPND_ADDR_REGOFF
:
5383 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5384 po_misc_or_fail (parse_address (&str
, info
, 0));
5385 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5386 || !info
->addr
.preind
|| info
->addr
.postind
5387 || info
->addr
.writeback
)
5389 set_syntax_error (_("invalid addressing mode"));
5392 if (!info
->shifter
.operator_present
)
5394 /* Default to LSL if not present. Libopcodes prefers shifter
5395 kind to be explicit. */
5396 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5397 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5399 /* Qualifier to be deduced by libopcodes. */
5402 case AARCH64_OPND_ADDR_SIMM7
:
5403 po_misc_or_fail (parse_address (&str
, info
, 0));
5404 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5405 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5407 set_syntax_error (_("invalid addressing mode"));
5410 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5412 /* need_libopcodes_p */ 1,
5416 case AARCH64_OPND_ADDR_SIMM9
:
5417 case AARCH64_OPND_ADDR_SIMM9_2
:
5418 po_misc_or_fail (parse_address_reloc (&str
, info
));
5419 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5420 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5421 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5422 && info
->addr
.writeback
))
5424 set_syntax_error (_("invalid addressing mode"));
5427 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5429 set_syntax_error (_("relocation not allowed"));
5432 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5434 /* need_libopcodes_p */ 1,
5438 case AARCH64_OPND_ADDR_UIMM12
:
5439 po_misc_or_fail (parse_address_reloc (&str
, info
));
5440 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5441 || !info
->addr
.preind
|| info
->addr
.writeback
)
5443 set_syntax_error (_("invalid addressing mode"));
5446 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5447 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5448 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5450 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
5452 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
5453 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5454 /* Leave qualifier to be determined by libopcodes. */
5457 case AARCH64_OPND_SIMD_ADDR_POST
:
5458 /* [<Xn|SP>], <Xm|#<amount>> */
5459 po_misc_or_fail (parse_address (&str
, info
, 1));
5460 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5462 set_syntax_error (_("invalid addressing mode"));
5465 if (!info
->addr
.offset
.is_reg
)
5467 if (inst
.reloc
.exp
.X_op
== O_constant
)
5468 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5471 set_fatal_syntax_error
5472 (_("writeback value should be an immediate constant"));
5479 case AARCH64_OPND_SYSREG
:
5480 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
5483 set_syntax_error (_("unknown or missing system register name"));
5486 inst
.base
.operands
[i
].sysreg
= val
;
5489 case AARCH64_OPND_PSTATEFIELD
:
5490 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
5493 set_syntax_error (_("unknown or missing PSTATE field name"));
5496 inst
.base
.operands
[i
].pstatefield
= val
;
5499 case AARCH64_OPND_SYSREG_IC
:
5500 inst
.base
.operands
[i
].sysins_op
=
5501 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5503 case AARCH64_OPND_SYSREG_DC
:
5504 inst
.base
.operands
[i
].sysins_op
=
5505 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5507 case AARCH64_OPND_SYSREG_AT
:
5508 inst
.base
.operands
[i
].sysins_op
=
5509 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5511 case AARCH64_OPND_SYSREG_TLBI
:
5512 inst
.base
.operands
[i
].sysins_op
=
5513 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5515 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5517 set_fatal_syntax_error ( _("unknown or missing operation name"));
5522 case AARCH64_OPND_BARRIER
:
5523 case AARCH64_OPND_BARRIER_ISB
:
5524 val
= parse_barrier (&str
);
5525 if (val
!= PARSE_FAIL
5526 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5528 /* ISB only accepts options name 'sy'. */
5530 (_("the specified option is not accepted in ISB"));
5531 /* Turn off backtrack as this optional operand is present. */
5535 /* This is an extension to accept a 0..15 immediate. */
5536 if (val
== PARSE_FAIL
)
5537 po_imm_or_fail (0, 15);
5538 info
->barrier
= aarch64_barrier_options
+ val
;
5541 case AARCH64_OPND_PRFOP
:
5542 val
= parse_pldop (&str
);
5543 /* This is an extension to accept a 0..31 immediate. */
5544 if (val
== PARSE_FAIL
)
5545 po_imm_or_fail (0, 31);
5546 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5550 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5553 /* If we get here, this operand was successfully parsed. */
5554 inst
.base
.operands
[i
].present
= 1;
5558 /* The parse routine should already have set the error, but in case
5559 not, set a default one here. */
5561 set_default_error ();
5563 if (! backtrack_pos
)
5564 goto parse_operands_return
;
5567 /* We reach here because this operand is marked as optional, and
5568 either no operand was supplied or the operand was supplied but it
5569 was syntactically incorrect. In the latter case we report an
5570 error. In the former case we perform a few more checks before
5571 dropping through to the code to insert the default operand. */
5573 char *tmp
= backtrack_pos
;
5574 char endchar
= END_OF_INSN
;
5576 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5578 skip_past_char (&tmp
, ',');
5580 if (*tmp
!= endchar
)
5581 /* The user has supplied an operand in the wrong format. */
5582 goto parse_operands_return
;
5584 /* Make sure there is not a comma before the optional operand.
5585 For example the fifth operand of 'sys' is optional:
5587 sys #0,c0,c0,#0, <--- wrong
5588 sys #0,c0,c0,#0 <--- correct. */
5589 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5591 set_fatal_syntax_error
5592 (_("unexpected comma before the omitted optional operand"));
5593 goto parse_operands_return
;
5597 /* Reaching here means we are dealing with an optional operand that is
5598 omitted from the assembly line. */
5599 gas_assert (optional_operand_p (opcode
, i
));
5601 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5603 /* Try again, skipping the optional operand at backtrack_pos. */
5604 str
= backtrack_pos
;
5607 /* Clear any error record after the omitted optional operand has been
5608 successfully handled. */
5612 /* Check if we have parsed all the operands. */
5613 if (*str
!= '\0' && ! error_p ())
5615 /* Set I to the index of the last present operand; this is
5616 for the purpose of diagnostics. */
5617 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5619 set_fatal_syntax_error
5620 (_("unexpected characters following instruction"));
5623 parse_operands_return
:
5627 DEBUG_TRACE ("parsing FAIL: %s - %s",
5628 operand_mismatch_kind_names
[get_error_kind ()],
5629 get_error_message ());
5630 /* Record the operand error properly; this is useful when there
5631 are multiple instruction templates for a mnemonic name, so that
5632 later on, we can select the error that most closely describes
5634 record_operand_error (opcode
, i
, get_error_kind (),
5635 get_error_message ());
5640 DEBUG_TRACE ("parsing SUCCESS");
5645 /* It does some fix-up to provide some programmer friendly feature while
5646 keeping the libopcodes happy, i.e. libopcodes only accepts
5647 the preferred architectural syntax.
5648 Return FALSE if there is any failure; otherwise return TRUE. */
5651 programmer_friendly_fixup (aarch64_instruction
*instr
)
5653 aarch64_inst
*base
= &instr
->base
;
5654 const aarch64_opcode
*opcode
= base
->opcode
;
5655 enum aarch64_op op
= opcode
->op
;
5656 aarch64_opnd_info
*operands
= base
->operands
;
5658 DEBUG_TRACE ("enter");
5660 switch (opcode
->iclass
)
5663 /* TBNZ Xn|Wn, #uimm6, label
5664 Test and Branch Not Zero: conditionally jumps to label if bit number
5665 uimm6 in register Xn is not zero. The bit number implies the width of
5666 the register, which may be written and should be disassembled as Wn if
5667 uimm is less than 32. */
5668 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5670 if (operands
[1].imm
.value
>= 32)
5672 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5676 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5680 /* LDR Wt, label | =value
5681 As a convenience assemblers will typically permit the notation
5682 "=value" in conjunction with the pc-relative literal load instructions
5683 to automatically place an immediate value or symbolic address in a
5684 nearby literal pool and generate a hidden label which references it.
5685 ISREG has been set to 0 in the case of =value. */
5686 if (instr
->gen_lit_pool
5687 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5689 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5690 if (op
== OP_LDRSW_LIT
)
5692 if (instr
->reloc
.exp
.X_op
!= O_constant
5693 && instr
->reloc
.exp
.X_op
!= O_big
5694 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5696 record_operand_error (opcode
, 1,
5697 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5698 _("constant expression expected"));
5701 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5703 record_operand_error (opcode
, 1,
5704 AARCH64_OPDE_OTHER_ERROR
,
5705 _("literal pool insertion failed"));
5713 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5714 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5715 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5716 A programmer-friendly assembler should accept a destination Xd in
5717 place of Wd, however that is not the preferred form for disassembly.
5719 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5720 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5721 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5722 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5727 /* In the 64-bit form, the final register operand is written as Wm
5728 for all but the (possibly omitted) UXTX/LSL and SXTX
5730 As a programmer-friendly assembler, we accept e.g.
5731 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5732 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5733 int idx
= aarch64_operand_index (opcode
->operands
,
5734 AARCH64_OPND_Rm_EXT
);
5735 gas_assert (idx
== 1 || idx
== 2);
5736 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5737 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5738 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5739 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5740 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5741 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5749 DEBUG_TRACE ("exit with SUCCESS");
5753 /* Check for loads and stores that will cause unpredictable behavior. */
5756 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5758 aarch64_inst
*base
= &instr
->base
;
5759 const aarch64_opcode
*opcode
= base
->opcode
;
5760 const aarch64_opnd_info
*opnds
= base
->operands
;
5761 switch (opcode
->iclass
)
5767 /* Loading/storing the base register is unpredictable if writeback. */
5768 if ((aarch64_get_operand_class (opnds
[0].type
)
5769 == AARCH64_OPND_CLASS_INT_REG
)
5770 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5771 && opnds
[1].addr
.base_regno
!= REG_SP
5772 && opnds
[1].addr
.writeback
)
5773 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5776 case ldstnapair_offs
:
5777 case ldstpair_indexed
:
5778 /* Loading/storing the base register is unpredictable if writeback. */
5779 if ((aarch64_get_operand_class (opnds
[0].type
)
5780 == AARCH64_OPND_CLASS_INT_REG
)
5781 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5782 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5783 && opnds
[2].addr
.base_regno
!= REG_SP
5784 && opnds
[2].addr
.writeback
)
5785 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5786 /* Load operations must load different registers. */
5787 if ((opcode
->opcode
& (1 << 22))
5788 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5789 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5796 /* A wrapper function to interface with libopcodes on encoding and
5797 record the error message if there is any.
5799 Return TRUE on success; otherwise return FALSE. */
5802 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5805 aarch64_operand_error error_info
;
5806 error_info
.kind
= AARCH64_OPDE_NIL
;
5807 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5811 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5812 record_operand_error_info (opcode
, &error_info
);
5817 #ifdef DEBUG_AARCH64
5819 dump_opcode_operands (const aarch64_opcode
*opcode
)
5822 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5824 aarch64_verbose ("\t\t opnd%d: %s", i
,
5825 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5826 ? aarch64_get_operand_name (opcode
->operands
[i
])
5827 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5831 #endif /* DEBUG_AARCH64 */
5833 /* This is the guts of the machine-dependent assembler. STR points to a
5834 machine dependent instruction. This function is supposed to emit
5835 the frags/bytes it assembles to. */
5838 md_assemble (char *str
)
5841 templates
*template;
5842 aarch64_opcode
*opcode
;
5843 aarch64_inst
*inst_base
;
5844 unsigned saved_cond
;
5846 /* Align the previous label if needed. */
5847 if (last_label_seen
!= NULL
)
5849 symbol_set_frag (last_label_seen
, frag_now
);
5850 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
5851 S_SET_SEGMENT (last_label_seen
, now_seg
);
5854 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5856 DEBUG_TRACE ("\n\n");
5857 DEBUG_TRACE ("==============================");
5858 DEBUG_TRACE ("Enter md_assemble with %s", str
);
5860 template = opcode_lookup (&p
);
5863 /* It wasn't an instruction, but it might be a register alias of
5864 the form alias .req reg directive. */
5865 if (!create_register_alias (str
, p
))
5866 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
5871 skip_whitespace (p
);
5874 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5875 get_mnemonic_name (str
), str
);
5879 init_operand_error_report ();
5881 /* Sections are assumed to start aligned. In executable section, there is no
5882 MAP_DATA symbol pending. So we only align the address during
5883 MAP_DATA --> MAP_INSN transition.
5884 For other sections, this is not guaranteed. */
5885 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
5886 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
5887 frag_align_code (2, 0);
5889 saved_cond
= inst
.cond
;
5890 reset_aarch64_instruction (&inst
);
5891 inst
.cond
= saved_cond
;
5893 /* Iterate through all opcode entries with the same mnemonic name. */
5896 opcode
= template->opcode
;
5898 DEBUG_TRACE ("opcode %s found", opcode
->name
);
5899 #ifdef DEBUG_AARCH64
5901 dump_opcode_operands (opcode
);
5902 #endif /* DEBUG_AARCH64 */
5904 mapping_state (MAP_INSN
);
5906 inst_base
= &inst
.base
;
5907 inst_base
->opcode
= opcode
;
5909 /* Truly conditionally executed instructions, e.g. b.cond. */
5910 if (opcode
->flags
& F_COND
)
5912 gas_assert (inst
.cond
!= COND_ALWAYS
);
5913 inst_base
->cond
= get_cond_from_value (inst
.cond
);
5914 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
5916 else if (inst
.cond
!= COND_ALWAYS
)
5918 /* It shouldn't arrive here, where the assembly looks like a
5919 conditional instruction but the found opcode is unconditional. */
5924 if (parse_operands (p
, opcode
)
5925 && programmer_friendly_fixup (&inst
)
5926 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
5928 /* Check that this instruction is supported for this CPU. */
5929 if (!opcode
->avariant
5930 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
5932 as_bad (_("selected processor does not support `%s'"), str
);
5936 warn_unpredictable_ldst (&inst
, str
);
5938 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
5939 || !inst
.reloc
.need_libopcodes_p
)
5943 /* If there is relocation generated for the instruction,
5944 store the instruction information for the future fix-up. */
5945 struct aarch64_inst
*copy
;
5946 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
5947 if ((copy
= xmalloc (sizeof (struct aarch64_inst
))) == NULL
)
5949 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
5955 template = template->next
;
5956 if (template != NULL
)
5958 reset_aarch64_instruction (&inst
);
5959 inst
.cond
= saved_cond
;
5962 while (template != NULL
);
5964 /* Issue the error messages if any. */
5965 output_operand_error_report (str
);
5968 /* Various frobbings of labels and their addresses. */
5971 aarch64_start_line_hook (void)
5973 last_label_seen
= NULL
;
5977 aarch64_frob_label (symbolS
* sym
)
5979 last_label_seen
= sym
;
5981 dwarf2_emit_label (sym
);
5985 aarch64_data_in_code (void)
5987 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
5989 *input_line_pointer
= '/';
5990 input_line_pointer
+= 5;
5991 *input_line_pointer
= 0;
5999 aarch64_canonicalize_symbol_name (char *name
)
6003 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6004 *(name
+ len
- 5) = 0;
6009 /* Table of all register names defined by default. The user can
6010 define additional names with .req. Note that all register names
6011 should appear in both upper and lowercase variants. Some registers
6012 also have mixed-case names. */
6014 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6015 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6016 #define REGSET31(p,t) \
6017 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6018 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6019 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6020 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
6021 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6022 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6023 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6024 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6025 #define REGSET(p,t) \
6026 REGSET31(p,t), REGNUM(p,31,t)
6028 /* These go into aarch64_reg_hsh hash-table. */
6029 static const reg_entry reg_names
[] = {
6030 /* Integer registers. */
6031 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6032 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6034 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6035 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6037 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6038 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6040 /* Coprocessor register numbers. */
6041 REGSET (c
, CN
), REGSET (C
, CN
),
6043 /* Floating-point single precision registers. */
6044 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6046 /* Floating-point double precision registers. */
6047 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6049 /* Floating-point half precision registers. */
6050 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6052 /* Floating-point byte precision registers. */
6053 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6055 /* Floating-point quad precision registers. */
6056 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6058 /* FP/SIMD registers. */
6059 REGSET (v
, VN
), REGSET (V
, VN
),
6074 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6075 static const asm_nzcv nzcv_names
[] = {
6076 {"nzcv", B (n
, z
, c
, v
)},
6077 {"nzcV", B (n
, z
, c
, V
)},
6078 {"nzCv", B (n
, z
, C
, v
)},
6079 {"nzCV", B (n
, z
, C
, V
)},
6080 {"nZcv", B (n
, Z
, c
, v
)},
6081 {"nZcV", B (n
, Z
, c
, V
)},
6082 {"nZCv", B (n
, Z
, C
, v
)},
6083 {"nZCV", B (n
, Z
, C
, V
)},
6084 {"Nzcv", B (N
, z
, c
, v
)},
6085 {"NzcV", B (N
, z
, c
, V
)},
6086 {"NzCv", B (N
, z
, C
, v
)},
6087 {"NzCV", B (N
, z
, C
, V
)},
6088 {"NZcv", B (N
, Z
, c
, v
)},
6089 {"NZcV", B (N
, Z
, c
, V
)},
6090 {"NZCv", B (N
, Z
, C
, v
)},
6091 {"NZCV", B (N
, Z
, C
, V
)}
6104 /* MD interface: bits in the object file. */
6106 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6107 for use in the a.out file, and stores them in the array pointed to by buf.
6108 This knows about the endian-ness of the target machine and does
6109 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6110 2 (short) and 4 (long) Floating numbers are put out as a series of
6111 LITTLENUMS (shorts, here at least). */
6114 md_number_to_chars (char *buf
, valueT val
, int n
)
6116 if (target_big_endian
)
6117 number_to_chars_bigendian (buf
, val
, n
);
6119 number_to_chars_littleendian (buf
, val
, n
);
6122 /* MD interface: Sections. */
6124 /* Estimate the size of a frag before relaxing. Assume everything fits in
6128 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6134 /* Round up a section size to the appropriate boundary. */
6137 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
6142 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6143 of an rs_align_code fragment.
6145 Here we fill the frag with the appropriate info for padding the
6146 output stream. The resulting frag will consist of a fixed (fr_fix)
6147 and of a repeating (fr_var) part.
6149 The fixed content is always emitted before the repeating content and
6150 these two parts are used as follows in constructing the output:
6151 - the fixed part will be used to align to a valid instruction word
6152 boundary, in case that we start at a misaligned address; as no
6153 executable instruction can live at the misaligned location, we
6154 simply fill with zeros;
6155 - the variable part will be used to cover the remaining padding and
6156 we fill using the AArch64 NOP instruction.
6158 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6159 enough storage space for up to 3 bytes for padding the back to a valid
6160 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6163 aarch64_handle_align (fragS
* fragP
)
6165 /* NOP = d503201f */
6166 /* AArch64 instructions are always little-endian. */
6167 static char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6169 int bytes
, fix
, noop_size
;
6172 if (fragP
->fr_type
!= rs_align_code
)
6175 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6176 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6179 gas_assert (fragP
->tc_frag_data
.recorded
);
6182 noop_size
= sizeof (aarch64_noop
);
6184 fix
= bytes
& (noop_size
- 1);
6188 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6192 fragP
->fr_fix
+= fix
;
6196 memcpy (p
, aarch64_noop
, noop_size
);
6197 fragP
->fr_var
= noop_size
;
6200 /* Perform target specific initialisation of a frag.
6201 Note - despite the name this initialisation is not done when the frag
6202 is created, but only when its type is assigned. A frag can be created
6203 and used a long time before its type is set, so beware of assuming that
6204 this initialisationis performed first. */
6208 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6209 int max_chars ATTRIBUTE_UNUSED
)
6213 #else /* OBJ_ELF is defined. */
6215 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6217 /* Record a mapping symbol for alignment frags. We will delete this
6218 later if the alignment ends up empty. */
6219 if (!fragP
->tc_frag_data
.recorded
)
6220 fragP
->tc_frag_data
.recorded
= 1;
6222 switch (fragP
->fr_type
)
6227 mapping_state_2 (MAP_DATA
, max_chars
);
6230 mapping_state_2 (MAP_INSN
, max_chars
);
6237 /* Initialize the DWARF-2 unwind information for this procedure. */
6240 tc_aarch64_frame_initial_instructions (void)
6242 cfi_add_CFA_def_cfa (REG_SP
, 0);
6244 #endif /* OBJ_ELF */
6246 /* Convert REGNAME to a DWARF-2 register number. */
6249 tc_aarch64_regname_to_dw2regnum (char *regname
)
6251 const reg_entry
*reg
= parse_reg (®name
);
6257 case REG_TYPE_SP_32
:
6258 case REG_TYPE_SP_64
:
6268 return reg
->number
+ 64;
6276 /* Implement DWARF2_ADDR_SIZE. */
6279 aarch64_dwarf2_addr_size (void)
6281 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6285 return bfd_arch_bits_per_address (stdoutput
) / 8;
6288 /* MD interface: Symbol and relocation handling. */
6290 /* Return the address within the segment that a PC-relative fixup is
6291 relative to. For AArch64 PC-relative fixups applied to instructions
6292 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6295 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6297 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6299 /* If this is pc-relative and we are going to emit a relocation
6300 then we just want to put out any pipeline compensation that the linker
6301 will need. Otherwise we want to use the calculated base. */
6303 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6304 || aarch64_force_relocation (fixP
)))
6307 /* AArch64 should be consistent for all pc-relative relocations. */
6308 return base
+ AARCH64_PCREL_OFFSET
;
6311 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6312 Otherwise we have no need to default values of symbols. */
6315 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6318 if (name
[0] == '_' && name
[1] == 'G'
6319 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6323 if (symbol_find (name
))
6324 as_bad (_("GOT already in the symbol table"));
6326 GOT_symbol
= symbol_new (name
, undefined_section
,
6327 (valueT
) 0, &zero_address_frag
);
6337 /* Return non-zero if the indicated VALUE has overflowed the maximum
6338 range expressible by a unsigned number with the indicated number of
6342 unsigned_overflow (valueT value
, unsigned bits
)
6345 if (bits
>= sizeof (valueT
) * 8)
6347 lim
= (valueT
) 1 << bits
;
6348 return (value
>= lim
);
6352 /* Return non-zero if the indicated VALUE has overflowed the maximum
6353 range expressible by an signed number with the indicated number of
6357 signed_overflow (offsetT value
, unsigned bits
)
6360 if (bits
>= sizeof (offsetT
) * 8)
6362 lim
= (offsetT
) 1 << (bits
- 1);
6363 return (value
< -lim
|| value
>= lim
);
6366 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6367 unsigned immediate offset load/store instruction, try to encode it as
6368 an unscaled, 9-bit, signed immediate offset load/store instruction.
6369 Return TRUE if it is successful; otherwise return FALSE.
6371 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6372 in response to the standard LDR/STR mnemonics when the immediate offset is
6373 unambiguous, i.e. when it is negative or unaligned. */
6376 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6379 enum aarch64_op new_op
;
6380 const aarch64_opcode
*new_opcode
;
6382 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6384 switch (instr
->opcode
->op
)
6386 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6387 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6388 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6389 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6390 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6391 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6392 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6393 case OP_STR_POS
: new_op
= OP_STUR
; break;
6394 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6395 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6396 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6397 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6398 default: new_op
= OP_NIL
; break;
6401 if (new_op
== OP_NIL
)
6404 new_opcode
= aarch64_get_opcode (new_op
);
6405 gas_assert (new_opcode
!= NULL
);
6407 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6408 instr
->opcode
->op
, new_opcode
->op
);
6410 aarch64_replace_opcode (instr
, new_opcode
);
6412 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6413 qualifier matching may fail because the out-of-date qualifier will
6414 prevent the operand being updated with a new and correct qualifier. */
6415 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6416 AARCH64_OPND_ADDR_SIMM9
);
6417 gas_assert (idx
== 1);
6418 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6420 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6422 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6428 /* Called by fix_insn to fix a MOV immediate alias instruction.
6430 Operand for a generic move immediate instruction, which is an alias
6431 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6432 a 32-bit/64-bit immediate value into general register. An assembler error
6433 shall result if the immediate cannot be created by a single one of these
6434 instructions. If there is a choice, then to ensure reversability an
6435 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6438 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6440 const aarch64_opcode
*opcode
;
6442 /* Need to check if the destination is SP/ZR. The check has to be done
6443 before any aarch64_replace_opcode. */
6444 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6445 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6447 instr
->operands
[1].imm
.value
= value
;
6448 instr
->operands
[1].skip
= 0;
6452 /* Try the MOVZ alias. */
6453 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6454 aarch64_replace_opcode (instr
, opcode
);
6455 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6456 &instr
->value
, NULL
, NULL
))
6458 put_aarch64_insn (buf
, instr
->value
);
6461 /* Try the MOVK alias. */
6462 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6463 aarch64_replace_opcode (instr
, opcode
);
6464 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6465 &instr
->value
, NULL
, NULL
))
6467 put_aarch64_insn (buf
, instr
->value
);
6472 if (try_mov_bitmask_p
)
6474 /* Try the ORR alias. */
6475 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6476 aarch64_replace_opcode (instr
, opcode
);
6477 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6478 &instr
->value
, NULL
, NULL
))
6480 put_aarch64_insn (buf
, instr
->value
);
6485 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6486 _("immediate cannot be moved by a single instruction"));
6489 /* An instruction operand which is immediate related may have symbol used
6490 in the assembly, e.g.
6493 .set u32, 0x00ffff00
6495 At the time when the assembly instruction is parsed, a referenced symbol,
6496 like 'u32' in the above example may not have been seen; a fixS is created
6497 in such a case and is handled here after symbols have been resolved.
6498 Instruction is fixed up with VALUE using the information in *FIXP plus
6499 extra information in FLAGS.
6501 This function is called by md_apply_fix to fix up instructions that need
6502 a fix-up described above but does not involve any linker-time relocation. */
6505 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6509 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6510 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6511 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6515 /* Now the instruction is about to be fixed-up, so the operand that
6516 was previously marked as 'ignored' needs to be unmarked in order
6517 to get the encoding done properly. */
6518 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6519 new_inst
->operands
[idx
].skip
= 0;
6522 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6526 case AARCH64_OPND_EXCEPTION
:
6527 if (unsigned_overflow (value
, 16))
6528 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6529 _("immediate out of range"));
6530 insn
= get_aarch64_insn (buf
);
6531 insn
|= encode_svc_imm (value
);
6532 put_aarch64_insn (buf
, insn
);
6535 case AARCH64_OPND_AIMM
:
6536 /* ADD or SUB with immediate.
6537 NOTE this assumes we come here with a add/sub shifted reg encoding
6538 3 322|2222|2 2 2 21111 111111
6539 1 098|7654|3 2 1 09876 543210 98765 43210
6540 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6541 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6542 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6543 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6545 3 322|2222|2 2 221111111111
6546 1 098|7654|3 2 109876543210 98765 43210
6547 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6548 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6549 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6550 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6551 Fields sf Rn Rd are already set. */
6552 insn
= get_aarch64_insn (buf
);
6556 insn
= reencode_addsub_switch_add_sub (insn
);
6560 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6561 && unsigned_overflow (value
, 12))
6563 /* Try to shift the value by 12 to make it fit. */
6564 if (((value
>> 12) << 12) == value
6565 && ! unsigned_overflow (value
, 12 + 12))
6568 insn
|= encode_addsub_imm_shift_amount (1);
6572 if (unsigned_overflow (value
, 12))
6573 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6574 _("immediate out of range"));
6576 insn
|= encode_addsub_imm (value
);
6578 put_aarch64_insn (buf
, insn
);
6581 case AARCH64_OPND_SIMD_IMM
:
6582 case AARCH64_OPND_SIMD_IMM_SFT
:
6583 case AARCH64_OPND_LIMM
:
6584 /* Bit mask immediate. */
6585 gas_assert (new_inst
!= NULL
);
6586 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6587 new_inst
->operands
[idx
].imm
.value
= value
;
6588 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6589 &new_inst
->value
, NULL
, NULL
))
6590 put_aarch64_insn (buf
, new_inst
->value
);
6592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6593 _("invalid immediate"));
6596 case AARCH64_OPND_HALF
:
6597 /* 16-bit unsigned immediate. */
6598 if (unsigned_overflow (value
, 16))
6599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6600 _("immediate out of range"));
6601 insn
= get_aarch64_insn (buf
);
6602 insn
|= encode_movw_imm (value
& 0xffff);
6603 put_aarch64_insn (buf
, insn
);
6606 case AARCH64_OPND_IMM_MOV
:
6607 /* Operand for a generic move immediate instruction, which is
6608 an alias instruction that generates a single MOVZ, MOVN or ORR
6609 instruction to loads a 32-bit/64-bit immediate value into general
6610 register. An assembler error shall result if the immediate cannot be
6611 created by a single one of these instructions. If there is a choice,
6612 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6613 and MOVZ or MOVN to ORR. */
6614 gas_assert (new_inst
!= NULL
);
6615 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6618 case AARCH64_OPND_ADDR_SIMM7
:
6619 case AARCH64_OPND_ADDR_SIMM9
:
6620 case AARCH64_OPND_ADDR_SIMM9_2
:
6621 case AARCH64_OPND_ADDR_UIMM12
:
6622 /* Immediate offset in an address. */
6623 insn
= get_aarch64_insn (buf
);
6625 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6626 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6627 || new_inst
->opcode
->operands
[2] == opnd
);
6629 /* Get the index of the address operand. */
6630 if (new_inst
->opcode
->operands
[1] == opnd
)
6631 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6634 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6637 /* Update the resolved offset value. */
6638 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6640 /* Encode/fix-up. */
6641 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6642 &new_inst
->value
, NULL
, NULL
))
6644 put_aarch64_insn (buf
, new_inst
->value
);
6647 else if (new_inst
->opcode
->iclass
== ldst_pos
6648 && try_to_encode_as_unscaled_ldst (new_inst
))
6650 put_aarch64_insn (buf
, new_inst
->value
);
6654 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6655 _("immediate offset out of range"));
6660 as_fatal (_("unhandled operand code %d"), opnd
);
6664 /* Apply a fixup (fixP) to segment data, once it has been determined
6665 by our caller that we have all the info we need to fix it up.
6667 Parameter valP is the pointer to the value of the bits. */
6670 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6672 offsetT value
= *valP
;
6674 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6676 unsigned flags
= fixP
->fx_addnumber
;
6678 DEBUG_TRACE ("\n\n");
6679 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6680 DEBUG_TRACE ("Enter md_apply_fix");
6682 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6684 /* Note whether this will delete the relocation. */
6686 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6689 /* Process the relocations. */
6690 switch (fixP
->fx_r_type
)
6692 case BFD_RELOC_NONE
:
6693 /* This will need to go in the object file. */
6698 case BFD_RELOC_8_PCREL
:
6699 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6700 md_number_to_chars (buf
, value
, 1);
6704 case BFD_RELOC_16_PCREL
:
6705 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6706 md_number_to_chars (buf
, value
, 2);
6710 case BFD_RELOC_32_PCREL
:
6711 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6712 md_number_to_chars (buf
, value
, 4);
6716 case BFD_RELOC_64_PCREL
:
6717 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6718 md_number_to_chars (buf
, value
, 8);
6721 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6722 /* We claim that these fixups have been processed here, even if
6723 in fact we generate an error because we do not have a reloc
6724 for them, so tc_gen_reloc() will reject them. */
6726 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6729 _("undefined symbol %s used as an immediate value"),
6730 S_GET_NAME (fixP
->fx_addsy
));
6731 goto apply_fix_return
;
6733 fix_insn (fixP
, flags
, value
);
6736 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6737 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6740 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6741 _("pc-relative load offset not word aligned"));
6742 if (signed_overflow (value
, 21))
6743 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6744 _("pc-relative load offset out of range"));
6745 insn
= get_aarch64_insn (buf
);
6746 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6747 put_aarch64_insn (buf
, insn
);
6751 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6752 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6754 if (signed_overflow (value
, 21))
6755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6756 _("pc-relative address offset out of range"));
6757 insn
= get_aarch64_insn (buf
);
6758 insn
|= encode_adr_imm (value
);
6759 put_aarch64_insn (buf
, insn
);
6763 case BFD_RELOC_AARCH64_BRANCH19
:
6764 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6767 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6768 _("conditional branch target not word aligned"));
6769 if (signed_overflow (value
, 21))
6770 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6771 _("conditional branch out of range"));
6772 insn
= get_aarch64_insn (buf
);
6773 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6774 put_aarch64_insn (buf
, insn
);
6778 case BFD_RELOC_AARCH64_TSTBR14
:
6779 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6782 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6783 _("conditional branch target not word aligned"));
6784 if (signed_overflow (value
, 16))
6785 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6786 _("conditional branch out of range"));
6787 insn
= get_aarch64_insn (buf
);
6788 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6789 put_aarch64_insn (buf
, insn
);
6793 case BFD_RELOC_AARCH64_CALL26
:
6794 case BFD_RELOC_AARCH64_JUMP26
:
6795 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6798 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6799 _("branch target not word aligned"));
6800 if (signed_overflow (value
, 28))
6801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6802 _("branch out of range"));
6803 insn
= get_aarch64_insn (buf
);
6804 insn
|= encode_branch_ofs_26 (value
>> 2);
6805 put_aarch64_insn (buf
, insn
);
6809 case BFD_RELOC_AARCH64_MOVW_G0
:
6810 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6811 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6812 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6815 case BFD_RELOC_AARCH64_MOVW_G1
:
6816 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6817 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6818 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6821 case BFD_RELOC_AARCH64_MOVW_G2
:
6822 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6823 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6826 case BFD_RELOC_AARCH64_MOVW_G3
:
6829 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6831 insn
= get_aarch64_insn (buf
);
6835 /* REL signed addend must fit in 16 bits */
6836 if (signed_overflow (value
, 16))
6837 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6838 _("offset out of range"));
6842 /* Check for overflow and scale. */
6843 switch (fixP
->fx_r_type
)
6845 case BFD_RELOC_AARCH64_MOVW_G0
:
6846 case BFD_RELOC_AARCH64_MOVW_G1
:
6847 case BFD_RELOC_AARCH64_MOVW_G2
:
6848 case BFD_RELOC_AARCH64_MOVW_G3
:
6849 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6850 if (unsigned_overflow (value
, scale
+ 16))
6851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6852 _("unsigned value out of range"));
6854 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6855 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6856 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6857 /* NOTE: We can only come here with movz or movn. */
6858 if (signed_overflow (value
, scale
+ 16))
6859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6860 _("signed value out of range"));
6863 /* Force use of MOVN. */
6865 insn
= reencode_movzn_to_movn (insn
);
6869 /* Force use of MOVZ. */
6870 insn
= reencode_movzn_to_movz (insn
);
6874 /* Unchecked relocations. */
6880 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6881 insn
|= encode_movw_imm (value
& 0xffff);
6883 put_aarch64_insn (buf
, insn
);
6887 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
6888 fixP
->fx_r_type
= (ilp32_p
6889 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6890 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
6891 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6892 /* Should always be exported to object file, see
6893 aarch64_force_relocation(). */
6894 gas_assert (!fixP
->fx_done
);
6895 gas_assert (seg
->use_rela_p
);
6898 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
6899 fixP
->fx_r_type
= (ilp32_p
6900 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6901 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
6902 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6903 /* Should always be exported to object file, see
6904 aarch64_force_relocation(). */
6905 gas_assert (!fixP
->fx_done
);
6906 gas_assert (seg
->use_rela_p
);
6909 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
6910 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
6911 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
6912 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
6913 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
6914 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
6915 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
6916 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
6917 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
6918 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
6919 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
6920 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
6921 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
6922 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
6923 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
6924 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
6925 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
6926 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
6927 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
6928 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
6929 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
6930 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
6931 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
6932 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
6933 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
6934 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
6935 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
6936 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6937 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6938 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6939 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6940 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6941 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6942 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
6943 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
6944 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6945 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6946 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6947 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6948 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6949 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6950 /* Should always be exported to object file, see
6951 aarch64_force_relocation(). */
6952 gas_assert (!fixP
->fx_done
);
6953 gas_assert (seg
->use_rela_p
);
6956 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
6957 /* Should always be exported to object file, see
6958 aarch64_force_relocation(). */
6959 fixP
->fx_r_type
= (ilp32_p
6960 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6961 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
6962 gas_assert (!fixP
->fx_done
);
6963 gas_assert (seg
->use_rela_p
);
6966 case BFD_RELOC_AARCH64_ADD_LO12
:
6967 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
6968 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
6969 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
6970 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
6971 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
6972 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
6973 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
6974 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
6975 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
6976 case BFD_RELOC_AARCH64_LDST128_LO12
:
6977 case BFD_RELOC_AARCH64_LDST16_LO12
:
6978 case BFD_RELOC_AARCH64_LDST32_LO12
:
6979 case BFD_RELOC_AARCH64_LDST64_LO12
:
6980 case BFD_RELOC_AARCH64_LDST8_LO12
:
6981 /* Should always be exported to object file, see
6982 aarch64_force_relocation(). */
6983 gas_assert (!fixP
->fx_done
);
6984 gas_assert (seg
->use_rela_p
);
6987 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
6988 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
6989 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
6992 case BFD_RELOC_UNUSED
:
6993 /* An error will already have been reported. */
6997 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6998 _("unexpected %s fixup"),
6999 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7004 /* Free the allocated the struct aarch64_inst.
7005 N.B. currently there are very limited number of fix-up types actually use
7006 this field, so the impact on the performance should be minimal . */
7007 if (fixP
->tc_fix_data
.inst
!= NULL
)
7008 free (fixP
->tc_fix_data
.inst
);
7013 /* Translate internal representation of relocation info to BFD target
7017 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7020 bfd_reloc_code_real_type code
;
7022 reloc
= xmalloc (sizeof (arelent
));
7024 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
7025 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7026 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7030 if (section
->use_rela_p
)
7031 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7033 fixp
->fx_offset
= reloc
->address
;
7035 reloc
->addend
= fixp
->fx_offset
;
7037 code
= fixp
->fx_r_type
;
7042 code
= BFD_RELOC_16_PCREL
;
7047 code
= BFD_RELOC_32_PCREL
;
7052 code
= BFD_RELOC_64_PCREL
;
7059 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7060 if (reloc
->howto
== NULL
)
7062 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7064 ("cannot represent %s relocation in this object file format"),
7065 bfd_get_reloc_code_name (code
));
7072 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7075 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7077 bfd_reloc_code_real_type type
;
7081 FIXME: @@ Should look at CPU word size. */
7088 type
= BFD_RELOC_16
;
7091 type
= BFD_RELOC_32
;
7094 type
= BFD_RELOC_64
;
7097 as_bad (_("cannot do %u-byte relocation"), size
);
7098 type
= BFD_RELOC_UNUSED
;
7102 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7106 aarch64_force_relocation (struct fix
*fixp
)
7108 switch (fixp
->fx_r_type
)
7110 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7111 /* Perform these "immediate" internal relocations
7112 even if the symbol is extern or weak. */
7115 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7116 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7117 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7118 /* Pseudo relocs that need to be fixed up according to
7122 case BFD_RELOC_AARCH64_ADD_LO12
:
7123 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7124 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7125 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7126 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7127 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7128 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7129 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7130 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7131 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7132 case BFD_RELOC_AARCH64_LDST128_LO12
:
7133 case BFD_RELOC_AARCH64_LDST16_LO12
:
7134 case BFD_RELOC_AARCH64_LDST32_LO12
:
7135 case BFD_RELOC_AARCH64_LDST64_LO12
:
7136 case BFD_RELOC_AARCH64_LDST8_LO12
:
7137 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7138 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7139 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7140 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7141 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7142 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7143 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7144 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7145 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7146 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7147 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7148 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7149 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7150 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7151 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7152 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7153 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7154 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7155 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7156 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7157 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7158 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7159 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7160 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7161 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7162 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7163 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7164 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7165 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7166 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7167 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7168 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7169 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7170 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7171 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7172 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7173 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7174 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7175 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7176 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7177 /* Always leave these relocations for the linker. */
7184 return generic_force_reloc (fixp
);
7190 elf64_aarch64_target_format (void)
7192 if (target_big_endian
)
7193 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7195 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7199 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7201 elf_frob_symbol (symp
, puntp
);
7205 /* MD interface: Finalization. */
7207 /* A good place to do this, although this was probably not intended
7208 for this kind of use. We need to dump the literal pool before
7209 references are made to a null symbol pointer. */
7212 aarch64_cleanup (void)
7216 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7218 /* Put it at the end of the relevant section. */
7219 subseg_set (pool
->section
, pool
->sub_section
);
7225 /* Remove any excess mapping symbols generated for alignment frags in
7226 SEC. We may have created a mapping symbol before a zero byte
7227 alignment; remove it if there's a mapping symbol after the
7230 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7231 void *dummy ATTRIBUTE_UNUSED
)
7233 segment_info_type
*seginfo
= seg_info (sec
);
7236 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7239 for (fragp
= seginfo
->frchainP
->frch_root
;
7240 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7242 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7243 fragS
*next
= fragp
->fr_next
;
7245 /* Variable-sized frags have been converted to fixed size by
7246 this point. But if this was variable-sized to start with,
7247 there will be a fixed-size frag after it. So don't handle
7249 if (sym
== NULL
|| next
== NULL
)
7252 if (S_GET_VALUE (sym
) < next
->fr_address
)
7253 /* Not at the end of this frag. */
7255 know (S_GET_VALUE (sym
) == next
->fr_address
);
7259 if (next
->tc_frag_data
.first_map
!= NULL
)
7261 /* Next frag starts with a mapping symbol. Discard this
7263 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7267 if (next
->fr_next
== NULL
)
7269 /* This mapping symbol is at the end of the section. Discard
7271 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7272 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7276 /* As long as we have empty frags without any mapping symbols,
7278 /* If the next frag is non-empty and does not start with a
7279 mapping symbol, then this mapping symbol is required. */
7280 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7283 next
= next
->fr_next
;
7285 while (next
!= NULL
);
7290 /* Adjust the symbol table. */
7293 aarch64_adjust_symtab (void)
7296 /* Remove any overlapping mapping symbols generated by alignment frags. */
7297 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7298 /* Now do generic ELF adjustments. */
7299 elf_adjust_symtab ();
7304 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7306 const char *hash_err
;
7308 hash_err
= hash_insert (table
, key
, value
);
7310 printf ("Internal Error: Can't hash %s\n", key
);
7314 fill_instruction_hash_table (void)
7316 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7318 while (opcode
->name
!= NULL
)
7320 templates
*templ
, *new_templ
;
7321 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7323 new_templ
= (templates
*) xmalloc (sizeof (templates
));
7324 new_templ
->opcode
= opcode
;
7325 new_templ
->next
= NULL
;
7328 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7331 new_templ
->next
= templ
->next
;
7332 templ
->next
= new_templ
;
7339 convert_to_upper (char *dst
, const char *src
, size_t num
)
7342 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7343 *dst
= TOUPPER (*src
);
7347 /* Assume STR point to a lower-case string, allocate, convert and return
7348 the corresponding upper-case string. */
7349 static inline const char*
7350 get_upper_str (const char *str
)
7353 size_t len
= strlen (str
);
7354 if ((ret
= xmalloc (len
+ 1)) == NULL
)
7356 convert_to_upper (ret
, str
, len
);
7360 /* MD interface: Initialization. */
7368 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7369 || (aarch64_cond_hsh
= hash_new ()) == NULL
7370 || (aarch64_shift_hsh
= hash_new ()) == NULL
7371 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7372 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7373 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7374 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7375 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7376 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7377 || (aarch64_reg_hsh
= hash_new ()) == NULL
7378 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7379 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7380 || (aarch64_pldop_hsh
= hash_new ()) == NULL
)
7381 as_fatal (_("virtual memory exhausted"));
7383 fill_instruction_hash_table ();
7385 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7386 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7387 (void *) (aarch64_sys_regs
+ i
));
7389 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7390 checked_hash_insert (aarch64_pstatefield_hsh
,
7391 aarch64_pstatefields
[i
].name
,
7392 (void *) (aarch64_pstatefields
+ i
));
7394 for (i
= 0; aarch64_sys_regs_ic
[i
].template != NULL
; i
++)
7395 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7396 aarch64_sys_regs_ic
[i
].template,
7397 (void *) (aarch64_sys_regs_ic
+ i
));
7399 for (i
= 0; aarch64_sys_regs_dc
[i
].template != NULL
; i
++)
7400 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7401 aarch64_sys_regs_dc
[i
].template,
7402 (void *) (aarch64_sys_regs_dc
+ i
));
7404 for (i
= 0; aarch64_sys_regs_at
[i
].template != NULL
; i
++)
7405 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7406 aarch64_sys_regs_at
[i
].template,
7407 (void *) (aarch64_sys_regs_at
+ i
));
7409 for (i
= 0; aarch64_sys_regs_tlbi
[i
].template != NULL
; i
++)
7410 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7411 aarch64_sys_regs_tlbi
[i
].template,
7412 (void *) (aarch64_sys_regs_tlbi
+ i
));
7414 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7415 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7416 (void *) (reg_names
+ i
));
7418 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7419 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7420 (void *) (nzcv_names
+ i
));
7422 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7424 const char *name
= aarch64_operand_modifiers
[i
].name
;
7425 checked_hash_insert (aarch64_shift_hsh
, name
,
7426 (void *) (aarch64_operand_modifiers
+ i
));
7427 /* Also hash the name in the upper case. */
7428 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7429 (void *) (aarch64_operand_modifiers
+ i
));
7432 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7435 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7436 the same condition code. */
7437 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7439 const char *name
= aarch64_conds
[i
].names
[j
];
7442 checked_hash_insert (aarch64_cond_hsh
, name
,
7443 (void *) (aarch64_conds
+ i
));
7444 /* Also hash the name in the upper case. */
7445 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7446 (void *) (aarch64_conds
+ i
));
7450 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7452 const char *name
= aarch64_barrier_options
[i
].name
;
7453 /* Skip xx00 - the unallocated values of option. */
7456 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7457 (void *) (aarch64_barrier_options
+ i
));
7458 /* Also hash the name in the upper case. */
7459 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7460 (void *) (aarch64_barrier_options
+ i
));
7463 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7465 const char* name
= aarch64_prfops
[i
].name
;
7466 /* Skip the unallocated hint encodings. */
7469 checked_hash_insert (aarch64_pldop_hsh
, name
,
7470 (void *) (aarch64_prfops
+ i
));
7471 /* Also hash the name in the upper case. */
7472 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7473 (void *) (aarch64_prfops
+ i
));
7476 /* Set the cpu variant based on the command-line options. */
7478 mcpu_cpu_opt
= march_cpu_opt
;
7481 mcpu_cpu_opt
= &cpu_default
;
7483 cpu_variant
= *mcpu_cpu_opt
;
7485 /* Record the CPU type. */
7486 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7488 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7491 /* Command line processing. */
7493 const char *md_shortopts
= "m:";
7495 #ifdef AARCH64_BI_ENDIAN
7496 #define OPTION_EB (OPTION_MD_BASE + 0)
7497 #define OPTION_EL (OPTION_MD_BASE + 1)
7499 #if TARGET_BYTES_BIG_ENDIAN
7500 #define OPTION_EB (OPTION_MD_BASE + 0)
7502 #define OPTION_EL (OPTION_MD_BASE + 1)
7506 struct option md_longopts
[] = {
7508 {"EB", no_argument
, NULL
, OPTION_EB
},
7511 {"EL", no_argument
, NULL
, OPTION_EL
},
7513 {NULL
, no_argument
, NULL
, 0}
7516 size_t md_longopts_size
= sizeof (md_longopts
);
7518 struct aarch64_option_table
7520 char *option
; /* Option name to match. */
7521 char *help
; /* Help information. */
7522 int *var
; /* Variable to change. */
7523 int value
; /* What to change it to. */
7524 char *deprecated
; /* If non-null, print this message. */
7527 static struct aarch64_option_table aarch64_opts
[] = {
7528 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7529 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7531 #ifdef DEBUG_AARCH64
7532 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7533 #endif /* DEBUG_AARCH64 */
7534 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7536 {"mno-verbose-error", N_("do not output verbose error messages"),
7537 &verbose_error_p
, 0, NULL
},
7538 {NULL
, NULL
, NULL
, 0, NULL
}
7541 struct aarch64_cpu_option_table
7544 const aarch64_feature_set value
;
7545 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7547 const char *canonical_name
;
7550 /* This list should, at a minimum, contain all the cpu names
7551 recognized by GCC. */
7552 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7553 {"all", AARCH64_ANY
, NULL
},
7554 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7555 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7556 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7557 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7558 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7559 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7560 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7561 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7562 "Samsung Exynos M1"},
7563 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7564 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7566 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7567 in earlier releases and is superseded by 'xgene1' in all
7569 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7570 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7571 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7572 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7573 {"generic", AARCH64_ARCH_V8
, NULL
},
7575 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7578 struct aarch64_arch_option_table
7581 const aarch64_feature_set value
;
7584 /* This list should, at a minimum, contain all the architecture names
7585 recognized by GCC. */
7586 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7587 {"all", AARCH64_ANY
},
7588 {"armv8-a", AARCH64_ARCH_V8
},
7589 {"armv8.1-a", AARCH64_ARCH_V8_1
},
7590 {NULL
, AARCH64_ARCH_NONE
}
7593 /* ISA extensions. */
7594 struct aarch64_option_cpu_value_table
7597 const aarch64_feature_set value
;
7600 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7601 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0)},
7602 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
7603 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7604 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0)},
7605 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7606 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0)},
7607 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0)},
7608 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
7609 | AARCH64_FEATURE_RDMA
, 0)},
7610 {NULL
, AARCH64_ARCH_NONE
}
7613 struct aarch64_long_option_table
7615 char *option
; /* Substring to match. */
7616 char *help
; /* Help information. */
7617 int (*func
) (char *subopt
); /* Function to decode sub-option. */
7618 char *deprecated
; /* If non-null, print this message. */
7622 aarch64_parse_features (char *str
, const aarch64_feature_set
**opt_p
,
7623 bfd_boolean ext_only
)
7625 /* We insist on extensions being added before being removed. We achieve
7626 this by using the ADDING_VALUE variable to indicate whether we are
7627 adding an extension (1) or removing it (0) and only allowing it to
7628 change in the order -1 -> 1 -> 0. */
7629 int adding_value
= -1;
7630 aarch64_feature_set
*ext_set
= xmalloc (sizeof (aarch64_feature_set
));
7632 /* Copy the feature set, so that we can modify it. */
7636 while (str
!= NULL
&& *str
!= 0)
7638 const struct aarch64_option_cpu_value_table
*opt
;
7646 as_bad (_("invalid architectural extension"));
7650 ext
= strchr (++str
, '+');
7656 optlen
= strlen (str
);
7658 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7660 if (adding_value
!= 0)
7665 else if (optlen
> 0)
7667 if (adding_value
== -1)
7669 else if (adding_value
!= 1)
7671 as_bad (_("must specify extensions to add before specifying "
7672 "those to remove"));
7679 as_bad (_("missing architectural extension"));
7683 gas_assert (adding_value
!= -1);
7685 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7686 if (strncmp (opt
->name
, str
, optlen
) == 0)
7688 /* Add or remove the extension. */
7690 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7692 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7696 if (opt
->name
== NULL
)
7698 as_bad (_("unknown architectural extension `%s'"), str
);
7709 aarch64_parse_cpu (char *str
)
7711 const struct aarch64_cpu_option_table
*opt
;
7712 char *ext
= strchr (str
, '+');
7718 optlen
= strlen (str
);
7722 as_bad (_("missing cpu name `%s'"), str
);
7726 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7727 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7729 mcpu_cpu_opt
= &opt
->value
;
7731 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7736 as_bad (_("unknown cpu `%s'"), str
);
7741 aarch64_parse_arch (char *str
)
7743 const struct aarch64_arch_option_table
*opt
;
7744 char *ext
= strchr (str
, '+');
7750 optlen
= strlen (str
);
7754 as_bad (_("missing architecture name `%s'"), str
);
7758 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7759 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7761 march_cpu_opt
= &opt
->value
;
7763 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
7768 as_bad (_("unknown architecture `%s'\n"), str
);
7773 struct aarch64_option_abi_value_table
7776 enum aarch64_abi_type value
;
7779 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
7780 {"ilp32", AARCH64_ABI_ILP32
},
7781 {"lp64", AARCH64_ABI_LP64
},
7786 aarch64_parse_abi (char *str
)
7788 const struct aarch64_option_abi_value_table
*opt
;
7789 size_t optlen
= strlen (str
);
7793 as_bad (_("missing abi name `%s'"), str
);
7797 for (opt
= aarch64_abis
; opt
->name
!= NULL
; opt
++)
7798 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7800 aarch64_abi
= opt
->value
;
7804 as_bad (_("unknown abi `%s'\n"), str
);
7808 static struct aarch64_long_option_table aarch64_long_opts
[] = {
7810 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
7811 aarch64_parse_abi
, NULL
},
7812 #endif /* OBJ_ELF */
7813 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7814 aarch64_parse_cpu
, NULL
},
7815 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7816 aarch64_parse_arch
, NULL
},
7817 {NULL
, NULL
, 0, NULL
}
7821 md_parse_option (int c
, char *arg
)
7823 struct aarch64_option_table
*opt
;
7824 struct aarch64_long_option_table
*lopt
;
7830 target_big_endian
= 1;
7836 target_big_endian
= 0;
7841 /* Listing option. Just ignore these, we don't support additional
7846 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7848 if (c
== opt
->option
[0]
7849 && ((arg
== NULL
&& opt
->option
[1] == 0)
7850 || streq (arg
, opt
->option
+ 1)))
7852 /* If the option is deprecated, tell the user. */
7853 if (opt
->deprecated
!= NULL
)
7854 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
7855 arg
? arg
: "", _(opt
->deprecated
));
7857 if (opt
->var
!= NULL
)
7858 *opt
->var
= opt
->value
;
7864 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7866 /* These options are expected to have an argument. */
7867 if (c
== lopt
->option
[0]
7869 && strncmp (arg
, lopt
->option
+ 1,
7870 strlen (lopt
->option
+ 1)) == 0)
7872 /* If the option is deprecated, tell the user. */
7873 if (lopt
->deprecated
!= NULL
)
7874 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
7875 _(lopt
->deprecated
));
7877 /* Call the sup-option parser. */
7878 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
7889 md_show_usage (FILE * fp
)
7891 struct aarch64_option_table
*opt
;
7892 struct aarch64_long_option_table
*lopt
;
7894 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
7896 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
7897 if (opt
->help
!= NULL
)
7898 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
7900 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
7901 if (lopt
->help
!= NULL
)
7902 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
7906 -EB assemble code for a big-endian cpu\n"));
7911 -EL assemble code for a little-endian cpu\n"));
7915 /* Parse a .cpu directive. */
7918 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
7920 const struct aarch64_cpu_option_table
*opt
;
7926 name
= input_line_pointer
;
7927 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7928 input_line_pointer
++;
7929 saved_char
= *input_line_pointer
;
7930 *input_line_pointer
= 0;
7932 ext
= strchr (name
, '+');
7935 optlen
= ext
- name
;
7937 optlen
= strlen (name
);
7939 /* Skip the first "all" entry. */
7940 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
7941 if (strlen (opt
->name
) == optlen
7942 && strncmp (name
, opt
->name
, optlen
) == 0)
7944 mcpu_cpu_opt
= &opt
->value
;
7946 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7949 cpu_variant
= *mcpu_cpu_opt
;
7951 *input_line_pointer
= saved_char
;
7952 demand_empty_rest_of_line ();
7955 as_bad (_("unknown cpu `%s'"), name
);
7956 *input_line_pointer
= saved_char
;
7957 ignore_rest_of_line ();
7961 /* Parse a .arch directive. */
7964 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
7966 const struct aarch64_arch_option_table
*opt
;
7972 name
= input_line_pointer
;
7973 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
7974 input_line_pointer
++;
7975 saved_char
= *input_line_pointer
;
7976 *input_line_pointer
= 0;
7978 ext
= strchr (name
, '+');
7981 optlen
= ext
- name
;
7983 optlen
= strlen (name
);
7985 /* Skip the first "all" entry. */
7986 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
7987 if (strlen (opt
->name
) == optlen
7988 && strncmp (name
, opt
->name
, optlen
) == 0)
7990 mcpu_cpu_opt
= &opt
->value
;
7992 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
7995 cpu_variant
= *mcpu_cpu_opt
;
7997 *input_line_pointer
= saved_char
;
7998 demand_empty_rest_of_line ();
8002 as_bad (_("unknown architecture `%s'\n"), name
);
8003 *input_line_pointer
= saved_char
;
8004 ignore_rest_of_line ();
8007 /* Parse a .arch_extension directive. */
8010 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
8013 char *ext
= input_line_pointer
;;
8015 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8016 input_line_pointer
++;
8017 saved_char
= *input_line_pointer
;
8018 *input_line_pointer
= 0;
8020 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
8023 cpu_variant
= *mcpu_cpu_opt
;
8025 *input_line_pointer
= saved_char
;
8026 demand_empty_rest_of_line ();
8029 /* Copy symbol information. */
8032 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
8034 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);