1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2021 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* SME horizontal or vertical slice indicator, encoded in "V".
113 /* Bits for DEFINED field in vector_type_el. */
114 #define NTA_HASTYPE 1
115 #define NTA_HASINDEX 2
116 #define NTA_HASVARWIDTH 4
118 struct vector_type_el
120 enum vector_el_type type
;
121 unsigned char defined
;
126 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
130 bfd_reloc_code_real_type type
;
133 enum aarch64_opnd opnd
;
135 unsigned need_libopcodes_p
: 1;
138 struct aarch64_instruction
140 /* libopcodes structure for instruction intermediate representation. */
142 /* Record assembly errors found during the parsing. */
145 enum aarch64_operand_error_kind kind
;
148 /* The condition that appears in the assembly line. */
150 /* Relocation information (including the GAS internal fixup). */
152 /* Need to generate an immediate in the literal pool. */
153 unsigned gen_lit_pool
: 1;
156 typedef struct aarch64_instruction aarch64_instruction
;
158 static aarch64_instruction inst
;
160 static bool parse_operands (char *, const aarch64_opcode
*);
161 static bool programmer_friendly_fixup (aarch64_instruction
*);
164 # define now_instr_sequence seg_info \
165 (now_seg)->tc_segment_info_data.insn_sequence
167 static struct aarch64_instr_sequence now_instr_sequence
;
170 /* Diagnostics inline function utilities.
172 These are lightweight utilities which should only be called by parse_operands
173 and other parsers. GAS processes each assembly line by parsing it against
174 instruction template(s), in the case of multiple templates (for the same
175 mnemonic name), those templates are tried one by one until one succeeds or
176 all fail. An assembly line may fail a few templates before being
177 successfully parsed; an error saved here in most cases is not a user error
178 but an error indicating the current template is not the right template.
179 Therefore it is very important that errors can be saved at a low cost during
180 the parsing; we don't want to slow down the whole parsing by recording
181 non-user errors in detail.
183 Remember that the objective is to help GAS pick up the most appropriate
184 error message in the case of multiple templates, e.g. FMOV which has 8
190 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
191 inst
.parsing_error
.error
= NULL
;
197 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
200 static inline const char *
201 get_error_message (void)
203 return inst
.parsing_error
.error
;
206 static inline enum aarch64_operand_error_kind
207 get_error_kind (void)
209 return inst
.parsing_error
.kind
;
213 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
215 inst
.parsing_error
.kind
= kind
;
216 inst
.parsing_error
.error
= error
;
220 set_recoverable_error (const char *error
)
222 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
225 /* Use the DESC field of the corresponding aarch64_operand entry to compose
226 the error message. */
228 set_default_error (void)
230 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
234 set_syntax_error (const char *error
)
236 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
240 set_first_syntax_error (const char *error
)
243 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
247 set_fatal_syntax_error (const char *error
)
249 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
252 /* Return value for certain parsers when the parsing fails; those parsers
253 return the information of the parsed result, e.g. register number, on
255 #define PARSE_FAIL -1
257 /* This is an invalid condition code that means no conditional field is
259 #define COND_ALWAYS 0x10
263 const char *template;
270 bfd_reloc_code_real_type reloc
;
273 /* Macros to define the register types and masks for the purpose
276 #undef AARCH64_REG_TYPES
277 #define AARCH64_REG_TYPES \
278 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
279 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
280 BASIC_REG_TYPE(SP_32) /* wsp */ \
281 BASIC_REG_TYPE(SP_64) /* sp */ \
282 BASIC_REG_TYPE(Z_32) /* wzr */ \
283 BASIC_REG_TYPE(Z_64) /* xzr */ \
284 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
285 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
286 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
287 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
288 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
289 BASIC_REG_TYPE(VN) /* v[0-31] */ \
290 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
291 BASIC_REG_TYPE(PN) /* p[0-15] */ \
292 BASIC_REG_TYPE(ZA) /* za[0-15] */ \
293 BASIC_REG_TYPE(ZAH) /* za[0-15]h */ \
294 BASIC_REG_TYPE(ZAV) /* za[0-15]v */ \
295 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
296 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
297 /* Typecheck: same, plus SVE registers. */ \
298 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
300 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
301 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
302 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
303 /* Typecheck: same, plus SVE registers. */ \
304 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
305 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
307 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
308 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
309 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
310 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
311 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
312 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
313 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
314 /* Typecheck: any [BHSDQ]P FP. */ \
315 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
316 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
317 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
318 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
319 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
320 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
321 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
322 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
323 be used for SVE instructions, since Zn and Pn are valid symbols \
324 in other contexts. */ \
325 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
326 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
327 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
328 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
329 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
330 | REG_TYPE(ZN) | REG_TYPE(PN)) \
331 /* Any integer register; used for error messages only. */ \
332 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
333 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
334 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
335 /* Pseudo type to mark the end of the enumerator sequence. */ \
338 #undef BASIC_REG_TYPE
339 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
340 #undef MULTI_REG_TYPE
341 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
343 /* Register type enumerators. */
344 typedef enum aarch64_reg_type_
346 /* A list of REG_TYPE_*. */
350 #undef BASIC_REG_TYPE
351 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
353 #define REG_TYPE(T) (1 << REG_TYPE_##T)
354 #undef MULTI_REG_TYPE
355 #define MULTI_REG_TYPE(T,V) V,
357 /* Structure for a hash table entry for a register. */
361 unsigned char number
;
362 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
363 unsigned char builtin
;
366 /* Values indexed by aarch64_reg_type to assist the type checking. */
367 static const unsigned reg_type_masks
[] =
372 #undef BASIC_REG_TYPE
374 #undef MULTI_REG_TYPE
375 #undef AARCH64_REG_TYPES
377 /* Diagnostics used when we don't get a register of the expected type.
378 Note: this has to synchronized with aarch64_reg_type definitions
381 get_reg_expected_msg (aarch64_reg_type reg_type
)
388 msg
= N_("integer 32-bit register expected");
391 msg
= N_("integer 64-bit register expected");
394 msg
= N_("integer register expected");
396 case REG_TYPE_R64_SP
:
397 msg
= N_("64-bit integer or SP register expected");
399 case REG_TYPE_SVE_BASE
:
400 msg
= N_("base register expected");
403 msg
= N_("integer or zero register expected");
405 case REG_TYPE_SVE_OFFSET
:
406 msg
= N_("offset register expected");
409 msg
= N_("integer or SP register expected");
411 case REG_TYPE_R_Z_SP
:
412 msg
= N_("integer, zero or SP register expected");
415 msg
= N_("8-bit SIMD scalar register expected");
418 msg
= N_("16-bit SIMD scalar or floating-point half precision "
419 "register expected");
422 msg
= N_("32-bit SIMD scalar or floating-point single precision "
423 "register expected");
426 msg
= N_("64-bit SIMD scalar or floating-point double precision "
427 "register expected");
430 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
431 "register expected");
433 case REG_TYPE_R_Z_BHSDQ_V
:
434 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
435 msg
= N_("register expected");
437 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
438 msg
= N_("SIMD scalar or floating-point register expected");
440 case REG_TYPE_VN
: /* any V reg */
441 msg
= N_("vector register expected");
444 msg
= N_("SVE vector register expected");
447 msg
= N_("SVE predicate register expected");
450 as_fatal (_("invalid register type %d"), reg_type
);
455 /* Some well known registers that we refer to directly elsewhere. */
459 /* Instructions take 4 bytes in the object file. */
462 static htab_t aarch64_ops_hsh
;
463 static htab_t aarch64_cond_hsh
;
464 static htab_t aarch64_shift_hsh
;
465 static htab_t aarch64_sys_regs_hsh
;
466 static htab_t aarch64_pstatefield_hsh
;
467 static htab_t aarch64_sys_regs_ic_hsh
;
468 static htab_t aarch64_sys_regs_dc_hsh
;
469 static htab_t aarch64_sys_regs_at_hsh
;
470 static htab_t aarch64_sys_regs_tlbi_hsh
;
471 static htab_t aarch64_sys_regs_sr_hsh
;
472 static htab_t aarch64_reg_hsh
;
473 static htab_t aarch64_barrier_opt_hsh
;
474 static htab_t aarch64_nzcv_hsh
;
475 static htab_t aarch64_pldop_hsh
;
476 static htab_t aarch64_hint_opt_hsh
;
478 /* Stuff needed to resolve the label ambiguity
487 static symbolS
*last_label_seen
;
489 /* Literal pool structure. Held on a per-section
490 and per-sub-section basis. */
492 #define MAX_LITERAL_POOL_SIZE 1024
493 typedef struct literal_expression
496 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
497 LITTLENUM_TYPE
* bignum
;
498 } literal_expression
;
500 typedef struct literal_pool
502 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
503 unsigned int next_free_entry
;
509 struct literal_pool
*next
;
512 /* Pointer to a linked list of literal pools. */
513 static literal_pool
*list_of_pools
= NULL
;
517 /* This array holds the chars that always start a comment. If the
518 pre-processor is disabled, these aren't very useful. */
519 const char comment_chars
[] = "";
521 /* This array holds the chars that only start a comment at the beginning of
522 a line. If the line seems to have the form '# 123 filename'
523 .line and .file directives will appear in the pre-processed output. */
524 /* Note that input_file.c hand checks for '#' at the beginning of the
525 first line of the input file. This is because the compiler outputs
526 #NO_APP at the beginning of its output. */
527 /* Also note that comments like this one will always work. */
528 const char line_comment_chars
[] = "#";
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant
533 from exp in floating point numbers. */
534 const char EXP_CHARS
[] = "eE";
536 /* Chars that mean this number is a floating point constant. */
540 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
542 /* Prefix character that indicates the start of an immediate value. */
543 #define is_immediate_prefix(C) ((C) == '#')
545 /* Separator character handling. */
547 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
550 skip_past_char (char **str
, char c
)
561 #define skip_past_comma(str) skip_past_char (str, ',')
563 /* Arithmetic expressions (possibly involving symbols). */
565 static bool in_aarch64_get_expression
= false;
567 /* Third argument to aarch64_get_expression. */
568 #define GE_NO_PREFIX false
569 #define GE_OPT_PREFIX true
571 /* Fourth argument to aarch64_get_expression. */
572 #define ALLOW_ABSENT false
573 #define REJECT_ABSENT true
575 /* Fifth argument to aarch64_get_expression. */
576 #define NORMAL_RESOLUTION false
578 /* Return TRUE if the string pointed by *STR is successfully parsed
579 as an valid expression; *EP will be filled with the information of
580 such an expression. Otherwise return FALSE.
582 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
583 If REJECT_ABSENT is true then trat missing expressions as an error.
584 If DEFER_RESOLUTION is true, then do not resolve expressions against
585 constant symbols. Necessary if the expression is part of a fixup
586 that uses a reloc that must be emitted. */
589 aarch64_get_expression (expressionS
* ep
,
591 bool allow_immediate_prefix
,
593 bool defer_resolution
)
597 bool prefix_present
= false;
599 if (allow_immediate_prefix
)
601 if (is_immediate_prefix (**str
))
604 prefix_present
= true;
608 memset (ep
, 0, sizeof (expressionS
));
610 save_in
= input_line_pointer
;
611 input_line_pointer
= *str
;
612 in_aarch64_get_expression
= true;
613 if (defer_resolution
)
614 seg
= deferred_expression (ep
);
616 seg
= expression (ep
);
617 in_aarch64_get_expression
= false;
619 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
621 /* We found a bad expression in md_operand(). */
622 *str
= input_line_pointer
;
623 input_line_pointer
= save_in
;
624 if (prefix_present
&& ! error_p ())
625 set_fatal_syntax_error (_("bad expression"));
627 set_first_syntax_error (_("bad expression"));
632 if (seg
!= absolute_section
633 && seg
!= text_section
634 && seg
!= data_section
635 && seg
!= bss_section
636 && seg
!= undefined_section
)
638 set_syntax_error (_("bad segment"));
639 *str
= input_line_pointer
;
640 input_line_pointer
= save_in
;
647 *str
= input_line_pointer
;
648 input_line_pointer
= save_in
;
652 /* Turn a string in input_line_pointer into a floating point constant
653 of type TYPE, and store the appropriate bytes in *LITP. The number
654 of LITTLENUMS emitted is stored in *SIZEP. An error message is
655 returned, or NULL on OK. */
658 md_atof (int type
, char *litP
, int *sizeP
)
660 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
663 /* We handle all bad expressions here, so that we can report the faulty
664 instruction in the error message. */
666 md_operand (expressionS
* exp
)
668 if (in_aarch64_get_expression
)
669 exp
->X_op
= O_illegal
;
672 /* Immediate values. */
674 /* Errors may be set multiple times during parsing or bit encoding
675 (particularly in the Neon bits), but usually the earliest error which is set
676 will be the most meaningful. Avoid overwriting it with later (cascading)
677 errors by calling this function. */
680 first_error (const char *error
)
683 set_syntax_error (error
);
686 /* Similar to first_error, but this function accepts formatted error
689 first_error_fmt (const char *format
, ...)
694 /* N.B. this single buffer will not cause error messages for different
695 instructions to pollute each other; this is because at the end of
696 processing of each assembly line, error message if any will be
697 collected by as_bad. */
698 static char buffer
[size
];
702 int ret ATTRIBUTE_UNUSED
;
703 va_start (args
, format
);
704 ret
= vsnprintf (buffer
, size
, format
, args
);
705 know (ret
<= size
- 1 && ret
>= 0);
707 set_syntax_error (buffer
);
711 /* Register parsing. */
713 /* Generic register parser which is called by other specialized
715 CCP points to what should be the beginning of a register name.
716 If it is indeed a valid register name, advance CCP over it and
717 return the reg_entry structure; otherwise return NULL.
718 It does not issue diagnostics. */
721 parse_reg (char **ccp
)
727 #ifdef REGISTER_PREFIX
728 if (*start
!= REGISTER_PREFIX
)
734 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
739 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
741 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
750 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
753 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
755 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
758 /* Try to parse a base or offset register. Allow SVE base and offset
759 registers if REG_TYPE includes SVE registers. Return the register
760 entry on success, setting *QUALIFIER to the register qualifier.
761 Return null otherwise.
763 Note that this function does not issue any diagnostics. */
765 static const reg_entry
*
766 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
767 aarch64_opnd_qualifier_t
*qualifier
)
770 const reg_entry
*reg
= parse_reg (&str
);
780 *qualifier
= AARCH64_OPND_QLF_W
;
786 *qualifier
= AARCH64_OPND_QLF_X
;
790 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
793 switch (TOLOWER (str
[1]))
796 *qualifier
= AARCH64_OPND_QLF_S_S
;
799 *qualifier
= AARCH64_OPND_QLF_S_D
;
816 /* Try to parse a base or offset register. Return the register entry
817 on success, setting *QUALIFIER to the register qualifier. Return null
820 Note that this function does not issue any diagnostics. */
822 static const reg_entry
*
823 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
825 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
828 /* Parse the qualifier of a vector register or vector element of type
829 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
830 succeeds; otherwise return FALSE.
832 Accept only one occurrence of:
833 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
836 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
837 struct vector_type_el
*parsed_type
, char **str
)
841 unsigned element_size
;
842 enum vector_el_type type
;
845 gas_assert (*ptr
== '.');
848 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
853 width
= strtoul (ptr
, &ptr
, 10);
854 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
856 first_error_fmt (_("bad size %d in vector width specifier"), width
);
861 switch (TOLOWER (*ptr
))
880 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
889 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
891 first_error (_("missing element size"));
894 if (width
!= 0 && width
* element_size
!= 64
895 && width
* element_size
!= 128
896 && !(width
== 2 && element_size
== 16)
897 && !(width
== 4 && element_size
== 8))
900 ("invalid element size %d and vector size combination %c"),
906 parsed_type
->type
= type
;
907 parsed_type
->width
= width
;
914 /* *STR contains an SVE zero/merge predication suffix. Parse it into
915 *PARSED_TYPE and point *STR at the end of the suffix. */
918 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
923 gas_assert (*ptr
== '/');
925 switch (TOLOWER (*ptr
))
928 parsed_type
->type
= NT_zero
;
931 parsed_type
->type
= NT_merge
;
934 if (*ptr
!= '\0' && *ptr
!= ',')
935 first_error_fmt (_("unexpected character `%c' in predication type"),
938 first_error (_("missing predication type"));
941 parsed_type
->width
= 0;
946 /* Parse a register of the type TYPE.
948 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
949 name or the parsed register is not of TYPE.
951 Otherwise return the register number, and optionally fill in the actual
952 type of the register in *RTYPE when multiple alternatives were given, and
953 return the register shape and element index information in *TYPEINFO.
955 IN_REG_LIST should be set with TRUE if the caller is parsing a register
959 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
960 struct vector_type_el
*typeinfo
, bool in_reg_list
)
963 const reg_entry
*reg
= parse_reg (&str
);
964 struct vector_type_el atype
;
965 struct vector_type_el parsetype
;
966 bool is_typed_vecreg
= false;
969 atype
.type
= NT_invtype
;
977 set_default_error ();
981 if (! aarch64_check_reg_type (reg
, type
))
983 DEBUG_TRACE ("reg type check failed");
984 set_default_error ();
989 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
990 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
994 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
999 if (!parse_predication_for_operand (&parsetype
, &str
))
1003 /* Register if of the form Vn.[bhsdq]. */
1004 is_typed_vecreg
= true;
1006 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1008 /* The width is always variable; we don't allow an integer width
1010 gas_assert (parsetype
.width
== 0);
1011 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1013 else if (parsetype
.width
== 0)
1014 /* Expect index. In the new scheme we cannot have
1015 Vn.[bhsdq] represent a scalar. Therefore any
1016 Vn.[bhsdq] should have an index following it.
1017 Except in reglists of course. */
1018 atype
.defined
|= NTA_HASINDEX
;
1020 atype
.defined
|= NTA_HASTYPE
;
1022 atype
.type
= parsetype
.type
;
1023 atype
.width
= parsetype
.width
;
1026 if (skip_past_char (&str
, '['))
1030 /* Reject Sn[index] syntax. */
1031 if (!is_typed_vecreg
)
1033 first_error (_("this type of register can't be indexed"));
1039 first_error (_("index not allowed inside register list"));
1043 atype
.defined
|= NTA_HASINDEX
;
1045 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
,
1048 if (exp
.X_op
!= O_constant
)
1050 first_error (_("constant expression required"));
1054 if (! skip_past_char (&str
, ']'))
1057 atype
.index
= exp
.X_add_number
;
1059 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1061 /* Indexed vector register expected. */
1062 first_error (_("indexed vector register expected"));
1066 /* A vector reg Vn should be typed or indexed. */
1067 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1069 first_error (_("invalid use of vector register"));
1085 Return the register number on success; return PARSE_FAIL otherwise.
1087 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1088 the register (e.g. NEON double or quad reg when either has been requested).
1090 If this is a NEON vector register with additional type information, fill
1091 in the struct pointed to by VECTYPE (if non-NULL).
1093 This parser does not handle register list. */
1096 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1097 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1099 struct vector_type_el atype
;
1101 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1102 /*in_reg_list= */ false);
1104 if (reg
== PARSE_FAIL
)
1116 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1120 && e1
.defined
== e2
.defined
1121 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1124 /* This function parses a list of vector registers of type TYPE.
1125 On success, it returns the parsed register list information in the
1126 following encoded format:
1128 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1129 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1131 The information of the register shape and/or index is returned in
1134 It returns PARSE_FAIL if the register list is invalid.
1136 The list contains one to four registers.
1137 Each register can be one of:
1140 All <T> should be identical.
1141 All <index> should be identical.
1142 There are restrictions on <Vt> numbers which are checked later
1143 (by reg_list_valid_p). */
1146 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1147 struct vector_type_el
*vectype
)
1151 struct vector_type_el typeinfo
, typeinfo_first
;
1157 bool expect_index
= false;
1161 set_syntax_error (_("expecting {"));
1167 typeinfo_first
.defined
= 0;
1168 typeinfo_first
.type
= NT_invtype
;
1169 typeinfo_first
.width
= -1;
1170 typeinfo_first
.index
= 0;
1179 str
++; /* skip over '-' */
1182 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1183 /*in_reg_list= */ true);
1184 if (val
== PARSE_FAIL
)
1186 set_first_syntax_error (_("invalid vector register in list"));
1190 /* reject [bhsd]n */
1191 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1193 set_first_syntax_error (_("invalid scalar register in list"));
1198 if (typeinfo
.defined
& NTA_HASINDEX
)
1199 expect_index
= true;
1203 if (val
< val_range
)
1205 set_first_syntax_error
1206 (_("invalid range in vector register list"));
1215 typeinfo_first
= typeinfo
;
1216 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1218 set_first_syntax_error
1219 (_("type mismatch in vector register list"));
1224 for (i
= val_range
; i
<= val
; i
++)
1226 ret_val
|= i
<< (5 * nb_regs
);
1231 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1233 skip_whitespace (str
);
1236 set_first_syntax_error (_("end of vector register list not found"));
1241 skip_whitespace (str
);
1245 if (skip_past_char (&str
, '['))
1249 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
,
1251 if (exp
.X_op
!= O_constant
)
1253 set_first_syntax_error (_("constant expression required."));
1256 if (! skip_past_char (&str
, ']'))
1259 typeinfo_first
.index
= exp
.X_add_number
;
1263 set_first_syntax_error (_("expected index"));
1270 set_first_syntax_error (_("too many registers in vector register list"));
1273 else if (nb_regs
== 0)
1275 set_first_syntax_error (_("empty vector register list"));
1281 *vectype
= typeinfo_first
;
1283 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1286 /* Directives: register aliases. */
1289 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1294 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1297 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1300 /* Only warn about a redefinition if it's not defined as the
1302 else if (new->number
!= number
|| new->type
!= type
)
1303 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1308 name
= xstrdup (str
);
1309 new = XNEW (reg_entry
);
1312 new->number
= number
;
1314 new->builtin
= false;
1316 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1321 /* Look for the .req directive. This is of the form:
1323 new_register_name .req existing_register_name
1325 If we find one, or if it looks sufficiently like one that we want to
1326 handle any error here, return TRUE. Otherwise return FALSE. */
1329 create_register_alias (char *newname
, char *p
)
1331 const reg_entry
*old
;
1332 char *oldname
, *nbuf
;
1335 /* The input scrubber ensures that whitespace after the mnemonic is
1336 collapsed to single spaces. */
1338 if (!startswith (oldname
, " .req "))
1342 if (*oldname
== '\0')
1345 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1348 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1352 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1353 the desired alias name, and p points to its end. If not, then
1354 the desired alias name is in the global original_case_string. */
1355 #ifdef TC_CASE_SENSITIVE
1358 newname
= original_case_string
;
1359 nlen
= strlen (newname
);
1362 nbuf
= xmemdup0 (newname
, nlen
);
1364 /* Create aliases under the new name as stated; an all-lowercase
1365 version of the new name; and an all-uppercase version of the new
1367 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1369 for (p
= nbuf
; *p
; p
++)
1372 if (strncmp (nbuf
, newname
, nlen
))
1374 /* If this attempt to create an additional alias fails, do not bother
1375 trying to create the all-lower case alias. We will fail and issue
1376 a second, duplicate error message. This situation arises when the
1377 programmer does something like:
1380 The second .req creates the "Foo" alias but then fails to create
1381 the artificial FOO alias because it has already been created by the
1383 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1390 for (p
= nbuf
; *p
; p
++)
1393 if (strncmp (nbuf
, newname
, nlen
))
1394 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1401 /* Should never be called, as .req goes between the alias and the
1402 register name, not at the beginning of the line. */
1404 s_req (int a ATTRIBUTE_UNUSED
)
1406 as_bad (_("invalid syntax for .req directive"));
1409 /* The .unreq directive deletes an alias which was previously defined
1410 by .req. For example:
1416 s_unreq (int a ATTRIBUTE_UNUSED
)
1421 name
= input_line_pointer
;
1423 while (*input_line_pointer
!= 0
1424 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1425 ++input_line_pointer
;
1427 saved_char
= *input_line_pointer
;
1428 *input_line_pointer
= 0;
1431 as_bad (_("invalid syntax for .unreq directive"));
1434 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1437 as_bad (_("unknown register alias '%s'"), name
);
1438 else if (reg
->builtin
)
1439 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1446 str_hash_delete (aarch64_reg_hsh
, name
);
1447 free ((char *) reg
->name
);
1450 /* Also locate the all upper case and all lower case versions.
1451 Do not complain if we cannot find one or the other as it
1452 was probably deleted above. */
1454 nbuf
= strdup (name
);
1455 for (p
= nbuf
; *p
; p
++)
1457 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1460 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1461 free ((char *) reg
->name
);
1465 for (p
= nbuf
; *p
; p
++)
1467 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1470 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1471 free ((char *) reg
->name
);
1479 *input_line_pointer
= saved_char
;
1480 demand_empty_rest_of_line ();
1483 /* Directives: Instruction set selection. */
1486 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1487 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1488 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1489 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1491 /* Create a new mapping symbol for the transition to STATE. */
1494 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1497 const char *symname
;
1504 type
= BSF_NO_FLAGS
;
1508 type
= BSF_NO_FLAGS
;
1514 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1515 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1517 /* Save the mapping symbols for future reference. Also check that
1518 we do not place two mapping symbols at the same offset within a
1519 frag. We'll handle overlap between frags in
1520 check_mapping_symbols.
1522 If .fill or other data filling directive generates zero sized data,
1523 the mapping symbol for the following code will have the same value
1524 as the one generated for the data filling directive. In this case,
1525 we replace the old symbol with the new one at the same address. */
1528 if (frag
->tc_frag_data
.first_map
!= NULL
)
1530 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1531 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1534 frag
->tc_frag_data
.first_map
= symbolP
;
1536 if (frag
->tc_frag_data
.last_map
!= NULL
)
1538 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1539 S_GET_VALUE (symbolP
));
1540 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1541 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1544 frag
->tc_frag_data
.last_map
= symbolP
;
1547 /* We must sometimes convert a region marked as code to data during
1548 code alignment, if an odd number of bytes have to be padded. The
1549 code mapping symbol is pushed to an aligned address. */
1552 insert_data_mapping_symbol (enum mstate state
,
1553 valueT value
, fragS
* frag
, offsetT bytes
)
1555 /* If there was already a mapping symbol, remove it. */
1556 if (frag
->tc_frag_data
.last_map
!= NULL
1557 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1558 frag
->fr_address
+ value
)
1560 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1564 know (frag
->tc_frag_data
.first_map
== symp
);
1565 frag
->tc_frag_data
.first_map
= NULL
;
1567 frag
->tc_frag_data
.last_map
= NULL
;
1568 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1571 make_mapping_symbol (MAP_DATA
, value
, frag
);
1572 make_mapping_symbol (state
, value
+ bytes
, frag
);
1575 static void mapping_state_2 (enum mstate state
, int max_chars
);
1577 /* Set the mapping state to STATE. Only call this when about to
1578 emit some STATE bytes to the file. */
1581 mapping_state (enum mstate state
)
1583 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1585 if (state
== MAP_INSN
)
1586 /* AArch64 instructions require 4-byte alignment. When emitting
1587 instructions into any section, record the appropriate section
1589 record_alignment (now_seg
, 2);
1591 if (mapstate
== state
)
1592 /* The mapping symbol has already been emitted.
1593 There is nothing else to do. */
1596 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1597 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1598 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1599 evaluated later in the next else. */
1601 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1603 /* Only add the symbol if the offset is > 0:
1604 if we're at the first frag, check it's size > 0;
1605 if we're not at the first frag, then for sure
1606 the offset is > 0. */
1607 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1608 const int add_symbol
= (frag_now
!= frag_first
)
1609 || (frag_now_fix () > 0);
1612 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1616 mapping_state_2 (state
, 0);
1619 /* Same as mapping_state, but MAX_CHARS bytes have already been
1620 allocated. Put the mapping symbol that far back. */
1623 mapping_state_2 (enum mstate state
, int max_chars
)
1625 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1627 if (!SEG_NORMAL (now_seg
))
1630 if (mapstate
== state
)
1631 /* The mapping symbol has already been emitted.
1632 There is nothing else to do. */
1635 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1636 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1639 #define mapping_state(x) /* nothing */
1640 #define mapping_state_2(x, y) /* nothing */
1643 /* Directives: sectioning and alignment. */
1646 s_bss (int ignore ATTRIBUTE_UNUSED
)
1648 /* We don't support putting frags in the BSS segment, we fake it by
1649 marking in_bss, then looking at s_skip for clues. */
1650 subseg_set (bss_section
, 0);
1651 demand_empty_rest_of_line ();
1652 mapping_state (MAP_DATA
);
1656 s_even (int ignore ATTRIBUTE_UNUSED
)
1658 /* Never make frag if expect extra pass. */
1660 frag_align (1, 0, 0);
1662 record_alignment (now_seg
, 1);
1664 demand_empty_rest_of_line ();
1667 /* Directives: Literal pools. */
1669 static literal_pool
*
1670 find_literal_pool (int size
)
1674 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1676 if (pool
->section
== now_seg
1677 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1684 static literal_pool
*
1685 find_or_make_literal_pool (int size
)
1687 /* Next literal pool ID number. */
1688 static unsigned int latest_pool_num
= 1;
1691 pool
= find_literal_pool (size
);
1695 /* Create a new pool. */
1696 pool
= XNEW (literal_pool
);
1700 /* Currently we always put the literal pool in the current text
1701 section. If we were generating "small" model code where we
1702 knew that all code and initialised data was within 1MB then
1703 we could output literals to mergeable, read-only data
1706 pool
->next_free_entry
= 0;
1707 pool
->section
= now_seg
;
1708 pool
->sub_section
= now_subseg
;
1710 pool
->next
= list_of_pools
;
1711 pool
->symbol
= NULL
;
1713 /* Add it to the list. */
1714 list_of_pools
= pool
;
1717 /* New pools, and emptied pools, will have a NULL symbol. */
1718 if (pool
->symbol
== NULL
)
1720 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1721 &zero_address_frag
, 0);
1722 pool
->id
= latest_pool_num
++;
1729 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1730 Return TRUE on success, otherwise return FALSE. */
1732 add_to_lit_pool (expressionS
*exp
, int size
)
1737 pool
= find_or_make_literal_pool (size
);
1739 /* Check if this literal value is already in the pool. */
1740 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1742 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1744 if ((litexp
->X_op
== exp
->X_op
)
1745 && (exp
->X_op
== O_constant
)
1746 && (litexp
->X_add_number
== exp
->X_add_number
)
1747 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1750 if ((litexp
->X_op
== exp
->X_op
)
1751 && (exp
->X_op
== O_symbol
)
1752 && (litexp
->X_add_number
== exp
->X_add_number
)
1753 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1754 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1758 /* Do we need to create a new entry? */
1759 if (entry
== pool
->next_free_entry
)
1761 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1763 set_syntax_error (_("literal pool overflow"));
1767 pool
->literals
[entry
].exp
= *exp
;
1768 pool
->next_free_entry
+= 1;
1769 if (exp
->X_op
== O_big
)
1771 /* PR 16688: Bignums are held in a single global array. We must
1772 copy and preserve that value now, before it is overwritten. */
1773 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1775 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1776 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1779 pool
->literals
[entry
].bignum
= NULL
;
1782 exp
->X_op
= O_symbol
;
1783 exp
->X_add_number
= ((int) entry
) * size
;
1784 exp
->X_add_symbol
= pool
->symbol
;
1789 /* Can't use symbol_new here, so have to create a symbol and then at
1790 a later date assign it a value. That's what these functions do. */
1793 symbol_locate (symbolS
* symbolP
,
1794 const char *name
,/* It is copied, the caller can modify. */
1795 segT segment
, /* Segment identifier (SEG_<something>). */
1796 valueT valu
, /* Symbol value. */
1797 fragS
* frag
) /* Associated fragment. */
1800 char *preserved_copy_of_name
;
1802 name_length
= strlen (name
) + 1; /* +1 for \0. */
1803 obstack_grow (¬es
, name
, name_length
);
1804 preserved_copy_of_name
= obstack_finish (¬es
);
1806 #ifdef tc_canonicalize_symbol_name
1807 preserved_copy_of_name
=
1808 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1811 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1813 S_SET_SEGMENT (symbolP
, segment
);
1814 S_SET_VALUE (symbolP
, valu
);
1815 symbol_clear_list_pointers (symbolP
);
1817 symbol_set_frag (symbolP
, frag
);
1819 /* Link to end of symbol chain. */
1821 extern int symbol_table_frozen
;
1823 if (symbol_table_frozen
)
1827 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1829 obj_symbol_new_hook (symbolP
);
1831 #ifdef tc_symbol_new_hook
1832 tc_symbol_new_hook (symbolP
);
1836 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1837 #endif /* DEBUG_SYMS */
1842 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1849 for (align
= 2; align
<= 4; align
++)
1851 int size
= 1 << align
;
1853 pool
= find_literal_pool (size
);
1854 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1857 /* Align pool as you have word accesses.
1858 Only make a frag if we have to. */
1860 frag_align (align
, 0, 0);
1862 mapping_state (MAP_DATA
);
1864 record_alignment (now_seg
, align
);
1866 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1868 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1869 (valueT
) frag_now_fix (), frag_now
);
1870 symbol_table_insert (pool
->symbol
);
1872 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1874 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1876 if (exp
->X_op
== O_big
)
1878 /* PR 16688: Restore the global bignum value. */
1879 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1880 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1881 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1884 /* First output the expression in the instruction to the pool. */
1885 emit_expr (exp
, size
); /* .word|.xword */
1887 if (exp
->X_op
== O_big
)
1889 free (pool
->literals
[entry
].bignum
);
1890 pool
->literals
[entry
].bignum
= NULL
;
1894 /* Mark the pool as empty. */
1895 pool
->next_free_entry
= 0;
1896 pool
->symbol
= NULL
;
1901 /* Forward declarations for functions below, in the MD interface
1903 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1904 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1906 /* Directives: Data. */
1907 /* N.B. the support for relocation suffix in this directive needs to be
1908 implemented properly. */
1911 s_aarch64_elf_cons (int nbytes
)
1915 #ifdef md_flush_pending_output
1916 md_flush_pending_output ();
1919 if (is_it_end_of_statement ())
1921 demand_empty_rest_of_line ();
1925 #ifdef md_cons_align
1926 md_cons_align (nbytes
);
1929 mapping_state (MAP_DATA
);
1932 struct reloc_table_entry
*reloc
;
1936 if (exp
.X_op
!= O_symbol
)
1937 emit_expr (&exp
, (unsigned int) nbytes
);
1940 skip_past_char (&input_line_pointer
, '#');
1941 if (skip_past_char (&input_line_pointer
, ':'))
1943 reloc
= find_reloc_table_entry (&input_line_pointer
);
1945 as_bad (_("unrecognized relocation suffix"));
1947 as_bad (_("unimplemented relocation suffix"));
1948 ignore_rest_of_line ();
1952 emit_expr (&exp
, (unsigned int) nbytes
);
1955 while (*input_line_pointer
++ == ',');
1957 /* Put terminator back into stream. */
1958 input_line_pointer
--;
1959 demand_empty_rest_of_line ();
1962 /* Mark symbol that it follows a variant PCS convention. */
1965 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1971 elf_symbol_type
*elfsym
;
1973 c
= get_symbol_name (&name
);
1975 as_bad (_("Missing symbol name in directive"));
1976 sym
= symbol_find_or_make (name
);
1977 restore_line_pointer (c
);
1978 demand_empty_rest_of_line ();
1979 bfdsym
= symbol_get_bfdsym (sym
);
1980 elfsym
= elf_symbol_from (bfdsym
);
1981 gas_assert (elfsym
);
1982 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
1984 #endif /* OBJ_ELF */
1986 /* Output a 32-bit word, but mark as an instruction. */
1989 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1993 #ifdef md_flush_pending_output
1994 md_flush_pending_output ();
1997 if (is_it_end_of_statement ())
1999 demand_empty_rest_of_line ();
2003 /* Sections are assumed to start aligned. In executable section, there is no
2004 MAP_DATA symbol pending. So we only align the address during
2005 MAP_DATA --> MAP_INSN transition.
2006 For other sections, this is not guaranteed. */
2007 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2008 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2009 frag_align_code (2, 0);
2012 mapping_state (MAP_INSN
);
2018 if (exp
.X_op
!= O_constant
)
2020 as_bad (_("constant expression required"));
2021 ignore_rest_of_line ();
2025 if (target_big_endian
)
2027 unsigned int val
= exp
.X_add_number
;
2028 exp
.X_add_number
= SWAP_32 (val
);
2030 emit_expr (&exp
, 4);
2032 while (*input_line_pointer
++ == ',');
2034 /* Put terminator back into stream. */
2035 input_line_pointer
--;
2036 demand_empty_rest_of_line ();
2040 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2042 demand_empty_rest_of_line ();
2043 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2044 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2048 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2051 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2057 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2058 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2060 demand_empty_rest_of_line ();
2063 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2066 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2070 /* Since we're just labelling the code, there's no need to define a
2073 /* Make sure there is enough room in this frag for the following
2074 blr. This trick only works if the blr follows immediately after
2075 the .tlsdesc directive. */
2077 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2078 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2080 demand_empty_rest_of_line ();
2083 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2086 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2092 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2093 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2095 demand_empty_rest_of_line ();
2097 #endif /* OBJ_ELF */
2099 static void s_aarch64_arch (int);
2100 static void s_aarch64_cpu (int);
2101 static void s_aarch64_arch_extension (int);
2103 /* This table describes all the machine specific pseudo-ops the assembler
2104 has to support. The fields are:
2105 pseudo-op name without dot
2106 function to call to execute this pseudo-op
2107 Integer arg to pass to the function. */
2109 const pseudo_typeS md_pseudo_table
[] = {
2110 /* Never called because '.req' does not start a line. */
2112 {"unreq", s_unreq
, 0},
2114 {"even", s_even
, 0},
2115 {"ltorg", s_ltorg
, 0},
2116 {"pool", s_ltorg
, 0},
2117 {"cpu", s_aarch64_cpu
, 0},
2118 {"arch", s_aarch64_arch
, 0},
2119 {"arch_extension", s_aarch64_arch_extension
, 0},
2120 {"inst", s_aarch64_inst
, 0},
2121 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2123 {"tlsdescadd", s_tlsdescadd
, 0},
2124 {"tlsdesccall", s_tlsdesccall
, 0},
2125 {"tlsdescldr", s_tlsdescldr
, 0},
2126 {"word", s_aarch64_elf_cons
, 4},
2127 {"long", s_aarch64_elf_cons
, 4},
2128 {"xword", s_aarch64_elf_cons
, 8},
2129 {"dword", s_aarch64_elf_cons
, 8},
2130 {"variant_pcs", s_variant_pcs
, 0},
2132 {"float16", float_cons
, 'h'},
2133 {"bfloat16", float_cons
, 'b'},
2138 /* Check whether STR points to a register name followed by a comma or the
2139 end of line; REG_TYPE indicates which register types are checked
2140 against. Return TRUE if STR is such a register name; otherwise return
2141 FALSE. The function does not intend to produce any diagnostics, but since
2142 the register parser aarch64_reg_parse, which is called by this function,
2143 does produce diagnostics, we call clear_error to clear any diagnostics
2144 that may be generated by aarch64_reg_parse.
2145 Also, the function returns FALSE directly if there is any user error
2146 present at the function entry. This prevents the existing diagnostics
2147 state from being spoiled.
2148 The function currently serves parse_constant_immediate and
2149 parse_big_immediate only. */
2151 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2155 /* Prevent the diagnostics state from being spoiled. */
2159 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2161 /* Clear the parsing error that may be set by the reg parser. */
2164 if (reg
== PARSE_FAIL
)
2167 skip_whitespace (str
);
2168 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2174 /* Parser functions used exclusively in instruction operands. */
2176 /* Parse an immediate expression which may not be constant.
2178 To prevent the expression parser from pushing a register name
2179 into the symbol table as an undefined symbol, firstly a check is
2180 done to find out whether STR is a register of type REG_TYPE followed
2181 by a comma or the end of line. Return FALSE if STR is such a string. */
2184 parse_immediate_expression (char **str
, expressionS
*exp
,
2185 aarch64_reg_type reg_type
)
2187 if (reg_name_p (*str
, reg_type
))
2189 set_recoverable_error (_("immediate operand required"));
2193 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
,
2196 if (exp
->X_op
== O_absent
)
2198 set_fatal_syntax_error (_("missing immediate expression"));
2205 /* Constant immediate-value read function for use in insn parsing.
2206 STR points to the beginning of the immediate (with the optional
2207 leading #); *VAL receives the value. REG_TYPE says which register
2208 names should be treated as registers rather than as symbolic immediates.
2210 Return TRUE on success; otherwise return FALSE. */
2213 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2217 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2220 if (exp
.X_op
!= O_constant
)
2222 set_syntax_error (_("constant expression required"));
2226 *val
= exp
.X_add_number
;
2231 encode_imm_float_bits (uint32_t imm
)
2233 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2234 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2237 /* Return TRUE if the single-precision floating-point value encoded in IMM
2238 can be expressed in the AArch64 8-bit signed floating-point format with
2239 3-bit exponent and normalized 4 bits of precision; in other words, the
2240 floating-point value must be expressable as
2241 (+/-) n / 16 * power (2, r)
2242 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2245 aarch64_imm_float_p (uint32_t imm
)
2247 /* If a single-precision floating-point value has the following bit
2248 pattern, it can be expressed in the AArch64 8-bit floating-point
2251 3 32222222 2221111111111
2252 1 09876543 21098765432109876543210
2253 n Eeeeeexx xxxx0000000000000000000
2255 where n, e and each x are either 0 or 1 independently, with
2260 /* Prepare the pattern for 'Eeeeee'. */
2261 if (((imm
>> 30) & 0x1) == 0)
2262 pattern
= 0x3e000000;
2264 pattern
= 0x40000000;
2266 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2267 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2270 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2271 as an IEEE float without any loss of precision. Store the value in
2275 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2277 /* If a double-precision floating-point value has the following bit
2278 pattern, it can be expressed in a float:
2280 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2281 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2282 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2284 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2285 if Eeee_eeee != 1111_1111
2287 where n, e, s and S are either 0 or 1 independently and where ~ is the
2291 uint32_t high32
= imm
>> 32;
2292 uint32_t low32
= imm
;
2294 /* Lower 29 bits need to be 0s. */
2295 if ((imm
& 0x1fffffff) != 0)
2298 /* Prepare the pattern for 'Eeeeeeeee'. */
2299 if (((high32
>> 30) & 0x1) == 0)
2300 pattern
= 0x38000000;
2302 pattern
= 0x40000000;
2305 if ((high32
& 0x78000000) != pattern
)
2308 /* Check Eeee_eeee != 1111_1111. */
2309 if ((high32
& 0x7ff00000) == 0x47f00000)
2312 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2313 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2314 | (low32
>> 29)); /* 3 S bits. */
2318 /* Return true if we should treat OPERAND as a double-precision
2319 floating-point operand rather than a single-precision one. */
2321 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2323 /* Check for unsuffixed SVE registers, which are allowed
2324 for LDR and STR but not in instructions that require an
2325 immediate. We get better error messages if we arbitrarily
2326 pick one size, parse the immediate normally, and then
2327 report the match failure in the normal way. */
2328 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2329 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2332 /* Parse a floating-point immediate. Return TRUE on success and return the
2333 value in *IMMED in the format of IEEE754 single-precision encoding.
2334 *CCP points to the start of the string; DP_P is TRUE when the immediate
2335 is expected to be in double-precision (N.B. this only matters when
2336 hexadecimal representation is involved). REG_TYPE says which register
2337 names should be treated as registers rather than as symbolic immediates.
2339 This routine accepts any IEEE float; it is up to the callers to reject
2343 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2344 aarch64_reg_type reg_type
)
2348 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2350 unsigned fpword
= 0;
2353 skip_past_char (&str
, '#');
2356 skip_whitespace (fpnum
);
2358 if (startswith (fpnum
, "0x"))
2360 /* Support the hexadecimal representation of the IEEE754 encoding.
2361 Double-precision is expected when DP_P is TRUE, otherwise the
2362 representation should be in single-precision. */
2363 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2368 if (!can_convert_double_to_float (val
, &fpword
))
2371 else if ((uint64_t) val
> 0xffffffff)
2378 else if (reg_name_p (str
, reg_type
))
2380 set_recoverable_error (_("immediate operand required"));
2388 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2391 /* Our FP word must be 32 bits (single-precision FP). */
2392 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2394 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2404 set_fatal_syntax_error (_("invalid floating-point constant"));
2408 /* Less-generic immediate-value read function with the possibility of loading
2409 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2412 To prevent the expression parser from pushing a register name into the
2413 symbol table as an undefined symbol, a check is firstly done to find
2414 out whether STR is a register of type REG_TYPE followed by a comma or
2415 the end of line. Return FALSE if STR is such a register. */
2418 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2422 if (reg_name_p (ptr
, reg_type
))
2424 set_syntax_error (_("immediate operand required"));
2428 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
,
2431 if (inst
.reloc
.exp
.X_op
== O_constant
)
2432 *imm
= inst
.reloc
.exp
.X_add_number
;
2439 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2440 if NEED_LIBOPCODES is non-zero, the fixup will need
2441 assistance from the libopcodes. */
2444 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2445 const aarch64_opnd_info
*operand
,
2446 int need_libopcodes_p
)
2448 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2449 reloc
->opnd
= operand
->type
;
2450 if (need_libopcodes_p
)
2451 reloc
->need_libopcodes_p
= 1;
2454 /* Return TRUE if the instruction needs to be fixed up later internally by
2455 the GAS; otherwise return FALSE. */
2458 aarch64_gas_internal_fixup_p (void)
2460 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2463 /* Assign the immediate value to the relevant field in *OPERAND if
2464 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2465 needs an internal fixup in a later stage.
2466 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2467 IMM.VALUE that may get assigned with the constant. */
2469 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2470 aarch64_opnd_info
*operand
,
2472 int need_libopcodes_p
,
2475 if (reloc
->exp
.X_op
== O_constant
)
2478 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2480 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2481 reloc
->type
= BFD_RELOC_UNUSED
;
2485 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2486 /* Tell libopcodes to ignore this operand or not. This is helpful
2487 when one of the operands needs to be fixed up later but we need
2488 libopcodes to check the other operands. */
2489 operand
->skip
= skip_p
;
2493 /* Relocation modifiers. Each entry in the table contains the textual
2494 name for the relocation which may be placed before a symbol used as
2495 a load/store offset, or add immediate. It must be surrounded by a
2496 leading and trailing colon, for example:
2498 ldr x0, [x1, #:rello:varsym]
2499 add x0, x1, #:rello:varsym */
2501 struct reloc_table_entry
2505 bfd_reloc_code_real_type adr_type
;
2506 bfd_reloc_code_real_type adrp_type
;
2507 bfd_reloc_code_real_type movw_type
;
2508 bfd_reloc_code_real_type add_type
;
2509 bfd_reloc_code_real_type ldst_type
;
2510 bfd_reloc_code_real_type ld_literal_type
;
2513 static struct reloc_table_entry reloc_table
[] =
2515 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2520 BFD_RELOC_AARCH64_ADD_LO12
,
2521 BFD_RELOC_AARCH64_LDST_LO12
,
2524 /* Higher 21 bits of pc-relative page offset: ADRP */
2527 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2533 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2536 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2542 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2546 BFD_RELOC_AARCH64_MOVW_G0
,
2551 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2555 BFD_RELOC_AARCH64_MOVW_G0_S
,
2560 /* Less significant bits 0-15 of address/value: MOVK, no check */
2564 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2569 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2573 BFD_RELOC_AARCH64_MOVW_G1
,
2578 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2582 BFD_RELOC_AARCH64_MOVW_G1_S
,
2587 /* Less significant bits 16-31 of address/value: MOVK, no check */
2591 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2596 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2600 BFD_RELOC_AARCH64_MOVW_G2
,
2605 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2609 BFD_RELOC_AARCH64_MOVW_G2_S
,
2614 /* Less significant bits 32-47 of address/value: MOVK, no check */
2618 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2623 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2627 BFD_RELOC_AARCH64_MOVW_G3
,
2632 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2636 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2641 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2645 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2650 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2654 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2659 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2663 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2668 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2672 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2677 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2681 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2686 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2690 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2695 /* Get to the page containing GOT entry for a symbol. */
2698 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2702 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2704 /* 12 bit offset into the page containing GOT entry for that symbol. */
2710 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2713 /* 0-15 bits of address/value: MOVk, no check. */
2717 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2722 /* Most significant bits 16-31 of address/value: MOVZ. */
2726 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2731 /* 15 bit offset into the page containing GOT entry for that symbol. */
2737 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2740 /* Get to the page containing GOT TLS entry for a symbol */
2741 {"gottprel_g0_nc", 0,
2744 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2749 /* Get to the page containing GOT TLS entry for a symbol */
2753 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2758 /* Get to the page containing GOT TLS entry for a symbol */
2760 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2761 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2767 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2772 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2776 /* Lower 16 bits address/value: MOVk. */
2780 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2785 /* Most significant bits 16-31 of address/value: MOVZ. */
2789 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2794 /* Get to the page containing GOT TLS entry for a symbol */
2796 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2797 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2801 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2803 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2808 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2809 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2812 /* Get to the page containing GOT TLS entry for a symbol.
2813 The same as GD, we allocate two consecutive GOT slots
2814 for module index and module offset, the only difference
2815 with GD is the module offset should be initialized to
2816 zero without any outstanding runtime relocation. */
2818 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2819 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2825 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2826 {"tlsldm_lo12_nc", 0,
2830 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2834 /* 12 bit offset into the module TLS base address. */
2839 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2840 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2843 /* Same as dtprel_lo12, no overflow check. */
2844 {"dtprel_lo12_nc", 0,
2848 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2849 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2852 /* bits[23:12] of offset to the module TLS base address. */
2857 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2861 /* bits[15:0] of offset to the module TLS base address. */
2865 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2870 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2874 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2879 /* bits[31:16] of offset to the module TLS base address. */
2883 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2888 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2892 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2897 /* bits[47:32] of offset to the module TLS base address. */
2901 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2906 /* Lower 16 bit offset into GOT entry for a symbol */
2907 {"tlsdesc_off_g0_nc", 0,
2910 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2915 /* Higher 16 bit offset into GOT entry for a symbol */
2916 {"tlsdesc_off_g1", 0,
2919 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2924 /* Get to the page containing GOT TLS entry for a symbol */
2927 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2931 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2933 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2934 {"gottprel_lo12", 0,
2939 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2942 /* Get tp offset for a symbol. */
2947 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2951 /* Get tp offset for a symbol. */
2956 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2957 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2960 /* Get tp offset for a symbol. */
2965 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2969 /* Get tp offset for a symbol. */
2970 {"tprel_lo12_nc", 0,
2974 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2975 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2978 /* Most significant bits 32-47 of address/value: MOVZ. */
2982 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2987 /* Most significant bits 16-31 of address/value: MOVZ. */
2991 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2996 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3000 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3005 /* Most significant bits 0-15 of address/value: MOVZ. */
3009 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3014 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3018 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3023 /* 15bit offset from got entry to base address of GOT table. */
3029 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3032 /* 14bit offset from got entry to base address of GOT table. */
3038 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3042 /* Given the address of a pointer pointing to the textual name of a
3043 relocation as may appear in assembler source, attempt to find its
3044 details in reloc_table. The pointer will be updated to the character
3045 after the trailing colon. On failure, NULL will be returned;
3046 otherwise return the reloc_table_entry. */
3048 static struct reloc_table_entry
*
3049 find_reloc_table_entry (char **str
)
3052 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3054 int length
= strlen (reloc_table
[i
].name
);
3056 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3057 && (*str
)[length
] == ':')
3059 *str
+= (length
+ 1);
3060 return &reloc_table
[i
];
3067 /* Returns 0 if the relocation should never be forced,
3068 1 if the relocation must be forced, and -1 if either
3072 aarch64_force_reloc (unsigned int type
)
3076 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3077 /* Perform these "immediate" internal relocations
3078 even if the symbol is extern or weak. */
3081 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3082 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3083 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3084 /* Pseudo relocs that need to be fixed up according to
3088 case BFD_RELOC_AARCH64_ADD_LO12
:
3089 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3090 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3091 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3092 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3093 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3094 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3095 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3096 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3097 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3098 case BFD_RELOC_AARCH64_LDST128_LO12
:
3099 case BFD_RELOC_AARCH64_LDST16_LO12
:
3100 case BFD_RELOC_AARCH64_LDST32_LO12
:
3101 case BFD_RELOC_AARCH64_LDST64_LO12
:
3102 case BFD_RELOC_AARCH64_LDST8_LO12
:
3103 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3104 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3105 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3106 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3107 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3108 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3109 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3110 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3111 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3112 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3113 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3114 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3115 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3116 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3117 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3118 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3119 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3120 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3121 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3122 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3123 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3124 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3125 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3126 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3127 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3128 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3129 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3130 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3131 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3132 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3133 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3134 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3135 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3136 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3137 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3138 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3139 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3140 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3141 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3142 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3143 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3144 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3145 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3146 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3147 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3148 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3149 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3150 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3151 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3152 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3153 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3154 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3155 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3156 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3157 /* Always leave these relocations for the linker. */
3166 aarch64_force_relocation (struct fix
*fixp
)
3168 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3171 return generic_force_reloc (fixp
);
3175 /* Mode argument to parse_shift and parser_shifter_operand. */
3176 enum parse_shift_mode
3178 SHIFTED_NONE
, /* no shifter allowed */
3179 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3181 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3183 SHIFTED_LSL
, /* bare "lsl #n" */
3184 SHIFTED_MUL
, /* bare "mul #n" */
3185 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3186 SHIFTED_MUL_VL
, /* "mul vl" */
3187 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3190 /* Parse a <shift> operator on an AArch64 data processing instruction.
3191 Return TRUE on success; otherwise return FALSE. */
3193 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3195 const struct aarch64_name_value_pair
*shift_op
;
3196 enum aarch64_modifier_kind kind
;
3202 for (p
= *str
; ISALPHA (*p
); p
++)
3207 set_syntax_error (_("shift expression expected"));
3211 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3213 if (shift_op
== NULL
)
3215 set_syntax_error (_("shift operator expected"));
3219 kind
= aarch64_get_operand_modifier (shift_op
);
3221 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3223 set_syntax_error (_("invalid use of 'MSL'"));
3227 if (kind
== AARCH64_MOD_MUL
3228 && mode
!= SHIFTED_MUL
3229 && mode
!= SHIFTED_MUL_VL
)
3231 set_syntax_error (_("invalid use of 'MUL'"));
3237 case SHIFTED_LOGIC_IMM
:
3238 if (aarch64_extend_operator_p (kind
))
3240 set_syntax_error (_("extending shift is not permitted"));
3245 case SHIFTED_ARITH_IMM
:
3246 if (kind
== AARCH64_MOD_ROR
)
3248 set_syntax_error (_("'ROR' shift is not permitted"));
3254 if (kind
!= AARCH64_MOD_LSL
)
3256 set_syntax_error (_("only 'LSL' shift is permitted"));
3262 if (kind
!= AARCH64_MOD_MUL
)
3264 set_syntax_error (_("only 'MUL' is permitted"));
3269 case SHIFTED_MUL_VL
:
3270 /* "MUL VL" consists of two separate tokens. Require the first
3271 token to be "MUL" and look for a following "VL". */
3272 if (kind
== AARCH64_MOD_MUL
)
3274 skip_whitespace (p
);
3275 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3278 kind
= AARCH64_MOD_MUL_VL
;
3282 set_syntax_error (_("only 'MUL VL' is permitted"));
3285 case SHIFTED_REG_OFFSET
:
3286 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3287 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3289 set_fatal_syntax_error
3290 (_("invalid shift for the register offset addressing mode"));
3295 case SHIFTED_LSL_MSL
:
3296 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3298 set_syntax_error (_("invalid shift operator"));
3307 /* Whitespace can appear here if the next thing is a bare digit. */
3308 skip_whitespace (p
);
3310 /* Parse shift amount. */
3312 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3313 exp
.X_op
= O_absent
;
3316 if (is_immediate_prefix (*p
))
3321 (void) aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
,
3324 if (kind
== AARCH64_MOD_MUL_VL
)
3325 /* For consistency, give MUL VL the same shift amount as an implicit
3327 operand
->shifter
.amount
= 1;
3328 else if (exp
.X_op
== O_absent
)
3330 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3332 set_syntax_error (_("missing shift amount"));
3335 operand
->shifter
.amount
= 0;
3337 else if (exp
.X_op
!= O_constant
)
3339 set_syntax_error (_("constant shift amount required"));
3342 /* For parsing purposes, MUL #n has no inherent range. The range
3343 depends on the operand and will be checked by operand-specific
3345 else if (kind
!= AARCH64_MOD_MUL
3346 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3348 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3353 operand
->shifter
.amount
= exp
.X_add_number
;
3354 operand
->shifter
.amount_present
= 1;
3357 operand
->shifter
.operator_present
= 1;
3358 operand
->shifter
.kind
= kind
;
3364 /* Parse a <shifter_operand> for a data processing instruction:
3367 #<immediate>, LSL #imm
3369 Validation of immediate operands is deferred to md_apply_fix.
3371 Return TRUE on success; otherwise return FALSE. */
3374 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3375 enum parse_shift_mode mode
)
3379 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3384 /* Accept an immediate expression. */
3385 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3386 REJECT_ABSENT
, NORMAL_RESOLUTION
))
3389 /* Accept optional LSL for arithmetic immediate values. */
3390 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3391 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3394 /* Not accept any shifter for logical immediate values. */
3395 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3396 && parse_shift (&p
, operand
, mode
))
3398 set_syntax_error (_("unexpected shift operator"));
3406 /* Parse a <shifter_operand> for a data processing instruction:
3411 #<immediate>, LSL #imm
3413 where <shift> is handled by parse_shift above, and the last two
3414 cases are handled by the function above.
3416 Validation of immediate operands is deferred to md_apply_fix.
3418 Return TRUE on success; otherwise return FALSE. */
3421 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3422 enum parse_shift_mode mode
)
3424 const reg_entry
*reg
;
3425 aarch64_opnd_qualifier_t qualifier
;
3426 enum aarch64_operand_class opd_class
3427 = aarch64_get_operand_class (operand
->type
);
3429 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3432 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3434 set_syntax_error (_("unexpected register in the immediate operand"));
3438 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3440 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3444 operand
->reg
.regno
= reg
->number
;
3445 operand
->qualifier
= qualifier
;
3447 /* Accept optional shift operation on register. */
3448 if (! skip_past_comma (str
))
3451 if (! parse_shift (str
, operand
, mode
))
3456 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3459 (_("integer register expected in the extended/shifted operand "
3464 /* We have a shifted immediate variable. */
3465 return parse_shifter_operand_imm (str
, operand
, mode
);
3468 /* Return TRUE on success; return FALSE otherwise. */
3471 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3472 enum parse_shift_mode mode
)
3476 /* Determine if we have the sequence of characters #: or just :
3477 coming next. If we do, then we check for a :rello: relocation
3478 modifier. If we don't, punt the whole lot to
3479 parse_shifter_operand. */
3481 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3483 struct reloc_table_entry
*entry
;
3491 /* Try to parse a relocation. Anything else is an error. */
3492 if (!(entry
= find_reloc_table_entry (str
)))
3494 set_syntax_error (_("unknown relocation modifier"));
3498 if (entry
->add_type
== 0)
3501 (_("this relocation modifier is not allowed on this instruction"));
3505 /* Save str before we decompose it. */
3508 /* Next, we parse the expression. */
3509 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3511 aarch64_force_reloc (entry
->add_type
) == 1))
3514 /* Record the relocation type (use the ADD variant here). */
3515 inst
.reloc
.type
= entry
->add_type
;
3516 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3518 /* If str is empty, we've reached the end, stop here. */
3522 /* Otherwise, we have a shifted reloc modifier, so rewind to
3523 recover the variable name and continue parsing for the shifter. */
3525 return parse_shifter_operand_imm (str
, operand
, mode
);
3528 return parse_shifter_operand (str
, operand
, mode
);
3531 /* Parse all forms of an address expression. Information is written
3532 to *OPERAND and/or inst.reloc.
3534 The A64 instruction set has the following addressing modes:
3537 [base] // in SIMD ld/st structure
3538 [base{,#0}] // in ld/st exclusive
3540 [base,Xm{,LSL #imm}]
3541 [base,Xm,SXTX {#imm}]
3542 [base,Wm,(S|U)XTW {#imm}]
3544 [base]! // in ldraa/ldrab exclusive
3548 [base],Xm // in SIMD ld/st structure
3549 PC-relative (literal)
3553 [base,Zm.D{,LSL #imm}]
3554 [base,Zm.S,(S|U)XTW {#imm}]
3555 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3559 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3560 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3561 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3563 (As a convenience, the notation "=immediate" is permitted in conjunction
3564 with the pc-relative literal load instructions to automatically place an
3565 immediate value or symbolic address in a nearby literal pool and generate
3566 a hidden label which references it.)
3568 Upon a successful parsing, the address structure in *OPERAND will be
3569 filled in the following way:
3571 .base_regno = <base>
3572 .offset.is_reg // 1 if the offset is a register
3574 .offset.regno = <Rm>
3576 For different addressing modes defined in the A64 ISA:
3579 .pcrel=0; .preind=1; .postind=0; .writeback=0
3581 .pcrel=0; .preind=1; .postind=0; .writeback=1
3583 .pcrel=0; .preind=0; .postind=1; .writeback=1
3584 PC-relative (literal)
3585 .pcrel=1; .preind=1; .postind=0; .writeback=0
3587 The shift/extension information, if any, will be stored in .shifter.
3588 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3589 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3590 corresponding register.
3592 BASE_TYPE says which types of base register should be accepted and
3593 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3594 is the type of shifter that is allowed for immediate offsets,
3595 or SHIFTED_NONE if none.
3597 In all other respects, it is the caller's responsibility to check
3598 for addressing modes not supported by the instruction, and to set
3602 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3603 aarch64_opnd_qualifier_t
*base_qualifier
,
3604 aarch64_opnd_qualifier_t
*offset_qualifier
,
3605 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3606 enum parse_shift_mode imm_shift_mode
)
3609 const reg_entry
*reg
;
3610 expressionS
*exp
= &inst
.reloc
.exp
;
3612 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3613 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3614 if (! skip_past_char (&p
, '['))
3616 /* =immediate or label. */
3617 operand
->addr
.pcrel
= 1;
3618 operand
->addr
.preind
= 1;
3620 /* #:<reloc_op>:<symbol> */
3621 skip_past_char (&p
, '#');
3622 if (skip_past_char (&p
, ':'))
3624 bfd_reloc_code_real_type ty
;
3625 struct reloc_table_entry
*entry
;
3627 /* Try to parse a relocation modifier. Anything else is
3629 entry
= find_reloc_table_entry (&p
);
3632 set_syntax_error (_("unknown relocation modifier"));
3636 switch (operand
->type
)
3638 case AARCH64_OPND_ADDR_PCREL21
:
3640 ty
= entry
->adr_type
;
3644 ty
= entry
->ld_literal_type
;
3651 (_("this relocation modifier is not allowed on this "
3657 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3658 aarch64_force_reloc (entry
->add_type
) == 1))
3660 set_syntax_error (_("invalid relocation expression"));
3663 /* #:<reloc_op>:<expr> */
3664 /* Record the relocation type. */
3665 inst
.reloc
.type
= ty
;
3666 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3670 if (skip_past_char (&p
, '='))
3671 /* =immediate; need to generate the literal in the literal pool. */
3672 inst
.gen_lit_pool
= 1;
3674 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3677 set_syntax_error (_("invalid address"));
3688 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3689 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3691 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3694 operand
->addr
.base_regno
= reg
->number
;
3697 if (skip_past_comma (&p
))
3700 operand
->addr
.preind
= 1;
3702 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3705 if (!aarch64_check_reg_type (reg
, offset_type
))
3707 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3712 operand
->addr
.offset
.regno
= reg
->number
;
3713 operand
->addr
.offset
.is_reg
= 1;
3714 /* Shifted index. */
3715 if (skip_past_comma (&p
))
3718 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3719 /* Use the diagnostics set in parse_shift, so not set new
3720 error message here. */
3724 [base,Xm] # For vector plus scalar SVE2 indexing.
3725 [base,Xm{,LSL #imm}]
3726 [base,Xm,SXTX {#imm}]
3727 [base,Wm,(S|U)XTW {#imm}] */
3728 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3729 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3730 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3732 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3734 set_syntax_error (_("invalid use of 32-bit register offset"));
3737 if (aarch64_get_qualifier_esize (*base_qualifier
)
3738 != aarch64_get_qualifier_esize (*offset_qualifier
)
3739 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3740 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3741 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3743 set_syntax_error (_("offset has different size from base"));
3747 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3749 set_syntax_error (_("invalid use of 64-bit register offset"));
3755 /* [Xn,#:<reloc_op>:<symbol> */
3756 skip_past_char (&p
, '#');
3757 if (skip_past_char (&p
, ':'))
3759 struct reloc_table_entry
*entry
;
3761 /* Try to parse a relocation modifier. Anything else is
3763 if (!(entry
= find_reloc_table_entry (&p
)))
3765 set_syntax_error (_("unknown relocation modifier"));
3769 if (entry
->ldst_type
== 0)
3772 (_("this relocation modifier is not allowed on this "
3777 /* [Xn,#:<reloc_op>: */
3778 /* We now have the group relocation table entry corresponding to
3779 the name in the assembler source. Next, we parse the
3781 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3782 aarch64_force_reloc (entry
->add_type
) == 1))
3784 set_syntax_error (_("invalid relocation expression"));
3788 /* [Xn,#:<reloc_op>:<expr> */
3789 /* Record the load/store relocation type. */
3790 inst
.reloc
.type
= entry
->ldst_type
;
3791 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3795 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
,
3798 set_syntax_error (_("invalid expression in the address"));
3802 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3803 /* [Xn,<expr>,<shifter> */
3804 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3810 if (! skip_past_char (&p
, ']'))
3812 set_syntax_error (_("']' expected"));
3816 if (skip_past_char (&p
, '!'))
3818 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3820 set_syntax_error (_("register offset not allowed in pre-indexed "
3821 "addressing mode"));
3825 operand
->addr
.writeback
= 1;
3827 else if (skip_past_comma (&p
))
3830 operand
->addr
.postind
= 1;
3831 operand
->addr
.writeback
= 1;
3833 if (operand
->addr
.preind
)
3835 set_syntax_error (_("cannot combine pre- and post-indexing"));
3839 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3843 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3845 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3849 operand
->addr
.offset
.regno
= reg
->number
;
3850 operand
->addr
.offset
.is_reg
= 1;
3852 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
,
3856 set_syntax_error (_("invalid expression in the address"));
3861 /* If at this point neither .preind nor .postind is set, we have a
3862 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3863 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3864 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3866 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3868 if (operand
->addr
.writeback
)
3870 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3872 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3873 operand
->addr
.offset
.is_reg
= 0;
3874 operand
->addr
.offset
.imm
= 0;
3875 operand
->addr
.preind
= 1;
3880 set_syntax_error (_("missing offset in the pre-indexed address"));
3886 operand
->addr
.preind
= 1;
3887 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3889 operand
->addr
.offset
.is_reg
= 1;
3890 operand
->addr
.offset
.regno
= REG_ZR
;
3891 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3895 inst
.reloc
.exp
.X_op
= O_constant
;
3896 inst
.reloc
.exp
.X_add_number
= 0;
3905 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3908 parse_address (char **str
, aarch64_opnd_info
*operand
)
3910 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3911 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3912 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3915 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3916 The arguments have the same meaning as for parse_address_main.
3917 Return TRUE on success. */
3919 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3920 aarch64_opnd_qualifier_t
*base_qualifier
,
3921 aarch64_opnd_qualifier_t
*offset_qualifier
)
3923 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3924 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3928 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3929 Return TRUE on success; otherwise return FALSE. */
3931 parse_half (char **str
, int *internal_fixup_p
)
3935 skip_past_char (&p
, '#');
3937 gas_assert (internal_fixup_p
);
3938 *internal_fixup_p
= 0;
3942 struct reloc_table_entry
*entry
;
3944 /* Try to parse a relocation. Anything else is an error. */
3947 if (!(entry
= find_reloc_table_entry (&p
)))
3949 set_syntax_error (_("unknown relocation modifier"));
3953 if (entry
->movw_type
== 0)
3956 (_("this relocation modifier is not allowed on this instruction"));
3960 inst
.reloc
.type
= entry
->movw_type
;
3963 *internal_fixup_p
= 1;
3965 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3966 aarch64_force_reloc (inst
.reloc
.type
) == 1))
3973 /* Parse an operand for an ADRP instruction:
3975 Return TRUE on success; otherwise return FALSE. */
3978 parse_adrp (char **str
)
3985 struct reloc_table_entry
*entry
;
3987 /* Try to parse a relocation. Anything else is an error. */
3989 if (!(entry
= find_reloc_table_entry (&p
)))
3991 set_syntax_error (_("unknown relocation modifier"));
3995 if (entry
->adrp_type
== 0)
3998 (_("this relocation modifier is not allowed on this instruction"));
4002 inst
.reloc
.type
= entry
->adrp_type
;
4005 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4007 inst
.reloc
.pc_rel
= 1;
4008 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
4009 aarch64_force_reloc (inst
.reloc
.type
) == 1))
4015 /* Miscellaneous. */
4017 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4018 of SIZE tokens in which index I gives the token for field value I,
4019 or is null if field value I is invalid. REG_TYPE says which register
4020 names should be treated as registers rather than as symbolic immediates.
4022 Return true on success, moving *STR past the operand and storing the
4023 field value in *VAL. */
4026 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4027 size_t size
, aarch64_reg_type reg_type
)
4033 /* Match C-like tokens. */
4035 while (ISALNUM (*q
))
4038 for (i
= 0; i
< size
; ++i
)
4040 && strncasecmp (array
[i
], p
, q
- p
) == 0
4041 && array
[i
][q
- p
] == 0)
4048 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4051 if (exp
.X_op
== O_constant
4052 && (uint64_t) exp
.X_add_number
< size
)
4054 *val
= exp
.X_add_number
;
4059 /* Use the default error for this operand. */
4063 /* Parse an option for a preload instruction. Returns the encoding for the
4064 option, or PARSE_FAIL. */
4067 parse_pldop (char **str
)
4070 const struct aarch64_name_value_pair
*o
;
4073 while (ISALNUM (*q
))
4076 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4084 /* Parse an option for a barrier instruction. Returns the encoding for the
4085 option, or PARSE_FAIL. */
4088 parse_barrier (char **str
)
4091 const struct aarch64_name_value_pair
*o
;
4094 while (ISALPHA (*q
))
4097 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4105 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4106 return 0 if successful. Otherwise return PARSE_FAIL. */
4109 parse_barrier_psb (char **str
,
4110 const struct aarch64_name_value_pair
** hint_opt
)
4113 const struct aarch64_name_value_pair
*o
;
4116 while (ISALPHA (*q
))
4119 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4122 set_fatal_syntax_error
4123 ( _("unknown or missing option to PSB/TSB"));
4127 if (o
->value
!= 0x11)
4129 /* PSB only accepts option name 'CSYNC'. */
4131 (_("the specified option is not accepted for PSB/TSB"));
4140 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4141 return 0 if successful. Otherwise return PARSE_FAIL. */
4144 parse_bti_operand (char **str
,
4145 const struct aarch64_name_value_pair
** hint_opt
)
4148 const struct aarch64_name_value_pair
*o
;
4151 while (ISALPHA (*q
))
4154 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4157 set_fatal_syntax_error
4158 ( _("unknown option to BTI"));
4164 /* Valid BTI operands. */
4172 (_("unknown option to BTI"));
4181 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4182 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4187 Side effect: Update STR with current parse position of success.
4190 static const reg_entry
*
4191 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4192 aarch64_opnd_qualifier_t
*qualifier
)
4196 reg_entry
*reg
= parse_reg (str
);
4197 if (reg
!= NULL
&& reg
->type
== reg_type
)
4199 if (!skip_past_char (str
, '.'))
4201 set_syntax_error (_("missing ZA tile element size separator"));
4206 switch (TOLOWER (*q
))
4209 *qualifier
= AARCH64_OPND_QLF_S_B
;
4212 *qualifier
= AARCH64_OPND_QLF_S_H
;
4215 *qualifier
= AARCH64_OPND_QLF_S_S
;
4218 *qualifier
= AARCH64_OPND_QLF_S_D
;
4221 *qualifier
= AARCH64_OPND_QLF_S_Q
;
4235 /* Parse SME ZA tile encoded in <ZAda> assembler symbol.
4236 Function return tile QUALIFIER on success.
4238 Tiles are in example format: za[0-9]\.[bhsd]
4240 Function returns <ZAda> register number or PARSE_FAIL.
4243 parse_sme_zada_operand (char **str
, aarch64_opnd_qualifier_t
*qualifier
)
4246 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_ZA
, qualifier
);
4250 regno
= reg
->number
;
4254 case AARCH64_OPND_QLF_S_B
:
4257 set_syntax_error (_("invalid ZA tile register number, expected za0"));
4261 case AARCH64_OPND_QLF_S_H
:
4264 set_syntax_error (_("invalid ZA tile register number, expected za0-za1"));
4268 case AARCH64_OPND_QLF_S_S
:
4271 /* For the 32-bit variant: is the name of the ZA tile ZA0-ZA3. */
4272 set_syntax_error (_("invalid ZA tile register number, expected za0-za3"));
4276 case AARCH64_OPND_QLF_S_D
:
4279 /* For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 */
4280 set_syntax_error (_("invalid ZA tile register number, expected za0-za7"));
4285 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s and d"));
4292 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4297 Function return TRUE if immediate was found, or FALSE.
4300 parse_sme_immediate (char **str
, int64_t *imm
)
4303 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4310 /* Parse index with vector select register and immediate:
4314 where <Wv> is in W12-W15 range and # is optional for immediate.
4316 Function performs extra check for mandatory immediate value if REQUIRE_IMM
4319 On success function returns TRUE and populated VECTOR_SELECT_REGISTER and
4323 parse_sme_za_hv_tiles_operand_index (char **str
,
4324 int *vector_select_register
,
4327 const reg_entry
*reg
;
4329 if (!skip_past_char (str
, '['))
4331 set_syntax_error (_("expected '['"));
4335 /* Vector select register W12-W15 encoded in the 2-bit Rv field. */
4336 reg
= parse_reg (str
);
4337 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
4338 || reg
->number
< 12 || reg
->number
> 15)
4340 set_syntax_error (_("expected vector select register W12-W15"));
4343 *vector_select_register
= reg
->number
;
4345 if (!skip_past_char (str
, ',')) /* Optional index offset immediate. */
4347 set_syntax_error (_("expected ','"));
4351 if (!parse_sme_immediate (str
, imm
))
4353 set_syntax_error (_("index offset immediate expected"));
4357 if (!skip_past_char (str
, ']'))
4359 set_syntax_error (_("expected ']'"));
4366 /* Parse SME ZA horizontal or vertical vector access to tiles.
4367 Function extracts from STR to SLICE_INDICATOR <HV> horizontal (0) or
4368 vertical (1) ZA tile vector orientation. VECTOR_SELECT_REGISTER
4369 contains <Wv> select register and corresponding optional IMMEDIATE.
4370 In addition QUALIFIER is extracted.
4372 Field format examples:
4374 ZA0<HV>.B[<Wv>, #<imm>]
4375 <ZAn><HV>.H[<Wv>, #<imm>]
4376 <ZAn><HV>.S[<Wv>, #<imm>]
4377 <ZAn><HV>.D[<Wv>, #<imm>]
4378 <ZAn><HV>.Q[<Wv>, #<imm>]
4380 Function returns <ZAda> register number or PARSE_FAIL.
4383 parse_sme_za_hv_tiles_operand (char **str
,
4384 enum sme_hv_slice
*slice_indicator
,
4385 int *vector_select_register
,
4387 aarch64_opnd_qualifier_t
*qualifier
)
4394 const reg_entry
*reg
;
4397 if ((reg
= parse_reg_with_qual (&qh
, REG_TYPE_ZAH
, qualifier
)) != NULL
)
4399 *slice_indicator
= HV_horizontal
;
4402 else if ((reg
= parse_reg_with_qual (&qv
, REG_TYPE_ZAV
, qualifier
)) != NULL
)
4404 *slice_indicator
= HV_vertical
;
4409 regno
= reg
->number
;
4413 case AARCH64_OPND_QLF_S_B
:
4417 case AARCH64_OPND_QLF_S_H
:
4421 case AARCH64_OPND_QLF_S_S
:
4425 case AARCH64_OPND_QLF_S_D
:
4429 case AARCH64_OPND_QLF_S_Q
:
4434 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q"));
4438 /* Check if destination register ZA tile vector is in range for given
4439 instruction variant. */
4440 if (regno
< 0 || regno
> regno_limit
)
4442 set_syntax_error (_("ZA tile vector out of range"));
4446 if (!parse_sme_za_hv_tiles_operand_index (str
, vector_select_register
,
4450 /* Check if optional index offset is in the range for instruction
4452 if (imm_value
< 0 || imm_value
> imm_limit
)
4454 set_syntax_error (_("index offset out of range"));
4465 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4466 enum sme_hv_slice
*slice_indicator
,
4467 int *vector_select_register
,
4469 aarch64_opnd_qualifier_t
*qualifier
)
4473 if (!skip_past_char (str
, '{'))
4475 set_syntax_error (_("expected '{'"));
4479 regno
= parse_sme_za_hv_tiles_operand (str
, slice_indicator
,
4480 vector_select_register
, imm
,
4483 if (regno
== PARSE_FAIL
)
4486 if (!skip_past_char (str
, '}'))
4488 set_syntax_error (_("expected '}'"));
4495 /* Parse list of up to eight 64-bit element tile names separated by commas in
4496 SME's ZERO instruction:
4500 Function returns <mask>:
4502 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4505 parse_sme_zero_mask(char **str
)
4509 aarch64_opnd_qualifier_t qualifier
;
4515 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZA
, &qualifier
);
4518 int regno
= reg
->number
;
4519 if (qualifier
== AARCH64_OPND_QLF_S_B
&& regno
== 0)
4521 /* { ZA0.B } is assembled as all-ones immediate. */
4524 else if (qualifier
== AARCH64_OPND_QLF_S_H
&& regno
< 2)
4525 mask
|= 0x55 << regno
;
4526 else if (qualifier
== AARCH64_OPND_QLF_S_S
&& regno
< 4)
4527 mask
|= 0x11 << regno
;
4528 else if (qualifier
== AARCH64_OPND_QLF_S_D
&& regno
< 8)
4529 mask
|= 0x01 << regno
;
4532 set_syntax_error (_("wrong ZA tile element format"));
4537 else if (strncasecmp (q
, "za", 2) == 0
4540 /* { ZA } is assembled as all-ones immediate. */
4547 set_syntax_error (_("wrong ZA tile element format"));
4551 while (skip_past_char (&q
, ','));
4557 /* Wraps in curly braces <mask> operand ZERO instruction:
4561 Function returns value of <mask> bit-field.
4564 parse_sme_list_of_64bit_tiles (char **str
)
4568 if (!skip_past_char (str
, '{'))
4570 set_syntax_error (_("expected '{'"));
4574 /* Empty <mask> list is an all-zeros immediate. */
4575 if (!skip_past_char (str
, '}'))
4577 regno
= parse_sme_zero_mask (str
);
4578 if (regno
== PARSE_FAIL
)
4581 if (!skip_past_char (str
, '}'))
4583 set_syntax_error (_("expected '}'"));
4593 /* Parse ZA array operand used in e.g. STR and LDR instruction.
4599 Function returns <Wv> or PARSE_FAIL.
4602 parse_sme_za_array (char **str
, int *imm
)
4609 while (ISALPHA (*q
))
4612 if ((q
- p
!= 2) || strncasecmp ("za", p
, q
- p
) != 0)
4614 set_syntax_error (_("expected ZA array"));
4618 if (! parse_sme_za_hv_tiles_operand_index (&q
, ®no
, &imm_value
))
4621 if (imm_value
< 0 || imm_value
> 15)
4623 set_syntax_error (_("offset out of range"));
4632 /* Parse streaming mode operand for SMSTART and SMSTOP.
4636 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4639 parse_sme_sm_za (char **str
)
4644 while (ISALPHA (*q
))
4648 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4650 set_syntax_error (_("expected SM or ZA operand"));
4655 return TOLOWER (p
[0]);
4658 /* Parse the name of the source scalable predicate register, the index base
4659 register W12-W15 and the element index. Function performs element index
4660 limit checks as well as qualifier type checks.
4662 <Pn>.<T>[<Wv>, <imm>]
4663 <Pn>.<T>[<Wv>, #<imm>]
4665 On success function sets <Wv> to INDEX_BASE_REG, <T> to QUALIFIER and
4667 Function returns <Pn>, or PARSE_FAIL.
4670 parse_sme_pred_reg_with_index(char **str
,
4671 int *index_base_reg
,
4673 aarch64_opnd_qualifier_t
*qualifier
)
4678 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_PN
, qualifier
);
4682 regno
= reg
->number
;
4686 case AARCH64_OPND_QLF_S_B
:
4689 case AARCH64_OPND_QLF_S_H
:
4692 case AARCH64_OPND_QLF_S_S
:
4695 case AARCH64_OPND_QLF_S_D
:
4699 set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d"));
4703 if (! parse_sme_za_hv_tiles_operand_index (str
, index_base_reg
, &imm_value
))
4706 if (imm_value
< 0 || imm_value
> imm_limit
)
4708 set_syntax_error (_("element index out of range for given variant"));
4717 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4718 Returns the encoding for the option, or PARSE_FAIL.
4720 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4721 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4723 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4724 field, otherwise as a system register.
4728 parse_sys_reg (char **str
, htab_t sys_regs
,
4729 int imple_defined_p
, int pstatefield_p
,
4733 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4734 const aarch64_sys_reg
*o
;
4738 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4739 if (p
< buf
+ (sizeof (buf
) - 1))
4740 *p
++ = TOLOWER (*q
);
4743 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4744 valid system register. This is enforced by construction of the hash
4746 if (p
- buf
!= q
- *str
)
4749 o
= str_hash_find (sys_regs
, buf
);
4752 if (!imple_defined_p
)
4756 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4757 unsigned int op0
, op1
, cn
, cm
, op2
;
4759 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4762 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4764 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4771 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4772 as_bad (_("selected processor does not support PSTATE field "
4775 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4776 o
->value
, o
->flags
, o
->features
))
4777 as_bad (_("selected processor does not support system register "
4779 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4780 as_warn (_("system register name '%s' is deprecated and may be "
4781 "removed in a future release"), buf
);
4791 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4792 for the option, or NULL. */
4794 static const aarch64_sys_ins_reg
*
4795 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4798 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4799 const aarch64_sys_ins_reg
*o
;
4802 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4803 if (p
< buf
+ (sizeof (buf
) - 1))
4804 *p
++ = TOLOWER (*q
);
4807 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4808 valid system register. This is enforced by construction of the hash
4810 if (p
- buf
!= q
- *str
)
4813 o
= str_hash_find (sys_ins_regs
, buf
);
4817 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4818 o
->name
, o
->value
, o
->flags
, 0))
4819 as_bad (_("selected processor does not support system register "
4821 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4822 as_warn (_("system register name '%s' is deprecated and may be "
4823 "removed in a future release"), buf
);
4829 #define po_char_or_fail(chr) do { \
4830 if (! skip_past_char (&str, chr)) \
4834 #define po_reg_or_fail(regtype) do { \
4835 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4836 if (val == PARSE_FAIL) \
4838 set_default_error (); \
4843 #define po_int_reg_or_fail(reg_type) do { \
4844 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4845 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4847 set_default_error (); \
4850 info->reg.regno = reg->number; \
4851 info->qualifier = qualifier; \
4854 #define po_imm_nc_or_fail() do { \
4855 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4859 #define po_imm_or_fail(min, max) do { \
4860 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4862 if (val < min || val > max) \
4864 set_fatal_syntax_error (_("immediate value out of range "\
4865 #min " to "#max)); \
4870 #define po_enum_or_fail(array) do { \
4871 if (!parse_enum_string (&str, &val, array, \
4872 ARRAY_SIZE (array), imm_reg_type)) \
4876 #define po_misc_or_fail(expr) do { \
4881 /* encode the 12-bit imm field of Add/sub immediate */
4882 static inline uint32_t
4883 encode_addsub_imm (uint32_t imm
)
4888 /* encode the shift amount field of Add/sub immediate */
4889 static inline uint32_t
4890 encode_addsub_imm_shift_amount (uint32_t cnt
)
4896 /* encode the imm field of Adr instruction */
4897 static inline uint32_t
4898 encode_adr_imm (uint32_t imm
)
4900 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4901 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4904 /* encode the immediate field of Move wide immediate */
4905 static inline uint32_t
4906 encode_movw_imm (uint32_t imm
)
4911 /* encode the 26-bit offset of unconditional branch */
4912 static inline uint32_t
4913 encode_branch_ofs_26 (uint32_t ofs
)
4915 return ofs
& ((1 << 26) - 1);
4918 /* encode the 19-bit offset of conditional branch and compare & branch */
4919 static inline uint32_t
4920 encode_cond_branch_ofs_19 (uint32_t ofs
)
4922 return (ofs
& ((1 << 19) - 1)) << 5;
4925 /* encode the 19-bit offset of ld literal */
4926 static inline uint32_t
4927 encode_ld_lit_ofs_19 (uint32_t ofs
)
4929 return (ofs
& ((1 << 19) - 1)) << 5;
4932 /* Encode the 14-bit offset of test & branch. */
4933 static inline uint32_t
4934 encode_tst_branch_ofs_14 (uint32_t ofs
)
4936 return (ofs
& ((1 << 14) - 1)) << 5;
4939 /* Encode the 16-bit imm field of svc/hvc/smc. */
4940 static inline uint32_t
4941 encode_svc_imm (uint32_t imm
)
4946 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4947 static inline uint32_t
4948 reencode_addsub_switch_add_sub (uint32_t opcode
)
4950 return opcode
^ (1 << 30);
4953 static inline uint32_t
4954 reencode_movzn_to_movz (uint32_t opcode
)
4956 return opcode
| (1 << 30);
4959 static inline uint32_t
4960 reencode_movzn_to_movn (uint32_t opcode
)
4962 return opcode
& ~(1 << 30);
4965 /* Overall per-instruction processing. */
4967 /* We need to be able to fix up arbitrary expressions in some statements.
4968 This is so that we can handle symbols that are an arbitrary distance from
4969 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4970 which returns part of an address in a form which will be valid for
4971 a data instruction. We do this by pushing the expression into a symbol
4972 in the expr_section, and creating a fix for that. */
4975 fix_new_aarch64 (fragS
* frag
,
4990 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4994 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
5001 /* Diagnostics on operands errors. */
5003 /* By default, output verbose error message.
5004 Disable the verbose error message by -mno-verbose-error. */
5005 static int verbose_error_p
= 1;
5007 #ifdef DEBUG_AARCH64
5008 /* N.B. this is only for the purpose of debugging. */
5009 const char* operand_mismatch_kind_names
[] =
5012 "AARCH64_OPDE_RECOVERABLE",
5013 "AARCH64_OPDE_SYNTAX_ERROR",
5014 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5015 "AARCH64_OPDE_INVALID_VARIANT",
5016 "AARCH64_OPDE_OUT_OF_RANGE",
5017 "AARCH64_OPDE_UNALIGNED",
5018 "AARCH64_OPDE_REG_LIST",
5019 "AARCH64_OPDE_OTHER_ERROR",
5021 #endif /* DEBUG_AARCH64 */
5023 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5025 When multiple errors of different kinds are found in the same assembly
5026 line, only the error of the highest severity will be picked up for
5027 issuing the diagnostics. */
5030 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5031 enum aarch64_operand_error_kind rhs
)
5033 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5034 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
5035 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5036 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5037 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
5038 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5039 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
5040 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
5044 /* Helper routine to get the mnemonic name from the assembly instruction
5045 line; should only be called for the diagnosis purpose, as there is
5046 string copy operation involved, which may affect the runtime
5047 performance if used in elsewhere. */
5050 get_mnemonic_name (const char *str
)
5052 static char mnemonic
[32];
5055 /* Get the first 15 bytes and assume that the full name is included. */
5056 strncpy (mnemonic
, str
, 31);
5057 mnemonic
[31] = '\0';
5059 /* Scan up to the end of the mnemonic, which must end in white space,
5060 '.', or end of string. */
5061 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5066 /* Append '...' to the truncated long name. */
5067 if (ptr
- mnemonic
== 31)
5068 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5074 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5076 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5077 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5080 /* Data structures storing one user error in the assembly code related to
5083 struct operand_error_record
5085 const aarch64_opcode
*opcode
;
5086 aarch64_operand_error detail
;
5087 struct operand_error_record
*next
;
5090 typedef struct operand_error_record operand_error_record
;
5092 struct operand_errors
5094 operand_error_record
*head
;
5095 operand_error_record
*tail
;
5098 typedef struct operand_errors operand_errors
;
5100 /* Top-level data structure reporting user errors for the current line of
5102 The way md_assemble works is that all opcodes sharing the same mnemonic
5103 name are iterated to find a match to the assembly line. In this data
5104 structure, each of the such opcodes will have one operand_error_record
5105 allocated and inserted. In other words, excessive errors related with
5106 a single opcode are disregarded. */
5107 operand_errors operand_error_report
;
5109 /* Free record nodes. */
5110 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5112 /* Initialize the data structure that stores the operand mismatch
5113 information on assembling one line of the assembly code. */
5115 init_operand_error_report (void)
5117 if (operand_error_report
.head
!= NULL
)
5119 gas_assert (operand_error_report
.tail
!= NULL
);
5120 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5121 free_opnd_error_record_nodes
= operand_error_report
.head
;
5122 operand_error_report
.head
= NULL
;
5123 operand_error_report
.tail
= NULL
;
5126 gas_assert (operand_error_report
.tail
== NULL
);
5129 /* Return TRUE if some operand error has been recorded during the
5130 parsing of the current assembly line using the opcode *OPCODE;
5131 otherwise return FALSE. */
5133 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5135 operand_error_record
*record
= operand_error_report
.head
;
5136 return record
&& record
->opcode
== opcode
;
5139 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5140 OPCODE field is initialized with OPCODE.
5141 N.B. only one record for each opcode, i.e. the maximum of one error is
5142 recorded for each instruction template. */
5145 add_operand_error_record (const operand_error_record
* new_record
)
5147 const aarch64_opcode
*opcode
= new_record
->opcode
;
5148 operand_error_record
* record
= operand_error_report
.head
;
5150 /* The record may have been created for this opcode. If not, we need
5152 if (! opcode_has_operand_error_p (opcode
))
5154 /* Get one empty record. */
5155 if (free_opnd_error_record_nodes
== NULL
)
5157 record
= XNEW (operand_error_record
);
5161 record
= free_opnd_error_record_nodes
;
5162 free_opnd_error_record_nodes
= record
->next
;
5164 record
->opcode
= opcode
;
5165 /* Insert at the head. */
5166 record
->next
= operand_error_report
.head
;
5167 operand_error_report
.head
= record
;
5168 if (operand_error_report
.tail
== NULL
)
5169 operand_error_report
.tail
= record
;
5171 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5172 && record
->detail
.index
<= new_record
->detail
.index
5173 && operand_error_higher_severity_p (record
->detail
.kind
,
5174 new_record
->detail
.kind
))
5176 /* In the case of multiple errors found on operands related with a
5177 single opcode, only record the error of the leftmost operand and
5178 only if the error is of higher severity. */
5179 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5180 " the existing error %s on operand %d",
5181 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5182 new_record
->detail
.index
,
5183 operand_mismatch_kind_names
[record
->detail
.kind
],
5184 record
->detail
.index
);
5188 record
->detail
= new_record
->detail
;
5192 record_operand_error_info (const aarch64_opcode
*opcode
,
5193 aarch64_operand_error
*error_info
)
5195 operand_error_record record
;
5196 record
.opcode
= opcode
;
5197 record
.detail
= *error_info
;
5198 add_operand_error_record (&record
);
5201 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5202 error message *ERROR, for operand IDX (count from 0). */
5205 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5206 enum aarch64_operand_error_kind kind
,
5209 aarch64_operand_error info
;
5210 memset(&info
, 0, sizeof (info
));
5214 info
.non_fatal
= false;
5215 record_operand_error_info (opcode
, &info
);
5219 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5220 enum aarch64_operand_error_kind kind
,
5221 const char* error
, const int *extra_data
)
5223 aarch64_operand_error info
;
5227 info
.data
[0] = extra_data
[0];
5228 info
.data
[1] = extra_data
[1];
5229 info
.data
[2] = extra_data
[2];
5230 info
.non_fatal
= false;
5231 record_operand_error_info (opcode
, &info
);
5235 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5236 const char* error
, int lower_bound
,
5239 int data
[3] = {lower_bound
, upper_bound
, 0};
5240 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5244 /* Remove the operand error record for *OPCODE. */
5245 static void ATTRIBUTE_UNUSED
5246 remove_operand_error_record (const aarch64_opcode
*opcode
)
5248 if (opcode_has_operand_error_p (opcode
))
5250 operand_error_record
* record
= operand_error_report
.head
;
5251 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5252 operand_error_report
.head
= record
->next
;
5253 record
->next
= free_opnd_error_record_nodes
;
5254 free_opnd_error_record_nodes
= record
;
5255 if (operand_error_report
.head
== NULL
)
5257 gas_assert (operand_error_report
.tail
== record
);
5258 operand_error_report
.tail
= NULL
;
5263 /* Given the instruction in *INSTR, return the index of the best matched
5264 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5266 Return -1 if there is no qualifier sequence; return the first match
5267 if there is multiple matches found. */
5270 find_best_match (const aarch64_inst
*instr
,
5271 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5273 int i
, num_opnds
, max_num_matched
, idx
;
5275 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5278 DEBUG_TRACE ("no operand");
5282 max_num_matched
= 0;
5285 /* For each pattern. */
5286 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5289 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5291 /* Most opcodes has much fewer patterns in the list. */
5292 if (empty_qualifier_sequence_p (qualifiers
))
5294 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5298 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5299 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5302 if (num_matched
> max_num_matched
)
5304 max_num_matched
= num_matched
;
5309 DEBUG_TRACE ("return with %d", idx
);
5313 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5314 corresponding operands in *INSTR. */
5317 assign_qualifier_sequence (aarch64_inst
*instr
,
5318 const aarch64_opnd_qualifier_t
*qualifiers
)
5321 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5322 gas_assert (num_opnds
);
5323 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5324 instr
->operands
[i
].qualifier
= *qualifiers
;
5327 /* Print operands for the diagnosis purpose. */
5330 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5331 const aarch64_opnd_info
*opnds
)
5335 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5339 /* We regard the opcode operand info more, however we also look into
5340 the inst->operands to support the disassembling of the optional
5342 The two operand code should be the same in all cases, apart from
5343 when the operand can be optional. */
5344 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5345 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5348 /* Generate the operand string in STR. */
5349 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5354 strcat (buf
, i
== 0 ? " " : ", ");
5356 /* Append the operand string. */
5361 /* Send to stderr a string as information. */
5364 output_info (const char *format
, ...)
5370 file
= as_where (&line
);
5374 fprintf (stderr
, "%s:%u: ", file
, line
);
5376 fprintf (stderr
, "%s: ", file
);
5378 fprintf (stderr
, _("Info: "));
5379 va_start (args
, format
);
5380 vfprintf (stderr
, format
, args
);
5382 (void) putc ('\n', stderr
);
5385 /* Output one operand error record. */
5388 output_operand_error_record (const operand_error_record
*record
, char *str
)
5390 const aarch64_operand_error
*detail
= &record
->detail
;
5391 int idx
= detail
->index
;
5392 const aarch64_opcode
*opcode
= record
->opcode
;
5393 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5394 : AARCH64_OPND_NIL
);
5396 typedef void (*handler_t
)(const char *format
, ...);
5397 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5399 switch (detail
->kind
)
5401 case AARCH64_OPDE_NIL
:
5404 case AARCH64_OPDE_SYNTAX_ERROR
:
5405 case AARCH64_OPDE_RECOVERABLE
:
5406 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5407 case AARCH64_OPDE_OTHER_ERROR
:
5408 /* Use the prepared error message if there is, otherwise use the
5409 operand description string to describe the error. */
5410 if (detail
->error
!= NULL
)
5413 handler (_("%s -- `%s'"), detail
->error
, str
);
5415 handler (_("%s at operand %d -- `%s'"),
5416 detail
->error
, idx
+ 1, str
);
5420 gas_assert (idx
>= 0);
5421 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5422 aarch64_get_operand_desc (opd_code
), str
);
5426 case AARCH64_OPDE_INVALID_VARIANT
:
5427 handler (_("operand mismatch -- `%s'"), str
);
5428 if (verbose_error_p
)
5430 /* We will try to correct the erroneous instruction and also provide
5431 more information e.g. all other valid variants.
5433 The string representation of the corrected instruction and other
5434 valid variants are generated by
5436 1) obtaining the intermediate representation of the erroneous
5438 2) manipulating the IR, e.g. replacing the operand qualifier;
5439 3) printing out the instruction by calling the printer functions
5440 shared with the disassembler.
5442 The limitation of this method is that the exact input assembly
5443 line cannot be accurately reproduced in some cases, for example an
5444 optional operand present in the actual assembly line will be
5445 omitted in the output; likewise for the optional syntax rules,
5446 e.g. the # before the immediate. Another limitation is that the
5447 assembly symbols and relocation operations in the assembly line
5448 currently cannot be printed out in the error report. Last but not
5449 least, when there is other error(s) co-exist with this error, the
5450 'corrected' instruction may be still incorrect, e.g. given
5451 'ldnp h0,h1,[x0,#6]!'
5452 this diagnosis will provide the version:
5453 'ldnp s0,s1,[x0,#6]!'
5454 which is still not right. */
5455 size_t len
= strlen (get_mnemonic_name (str
));
5459 aarch64_inst
*inst_base
= &inst
.base
;
5460 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5463 reset_aarch64_instruction (&inst
);
5464 inst_base
->opcode
= opcode
;
5466 /* Reset the error report so that there is no side effect on the
5467 following operand parsing. */
5468 init_operand_error_report ();
5471 result
= parse_operands (str
+ len
, opcode
)
5472 && programmer_friendly_fixup (&inst
);
5473 gas_assert (result
);
5474 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5475 NULL
, NULL
, insn_sequence
);
5476 gas_assert (!result
);
5478 /* Find the most matched qualifier sequence. */
5479 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5480 gas_assert (qlf_idx
> -1);
5482 /* Assign the qualifiers. */
5483 assign_qualifier_sequence (inst_base
,
5484 opcode
->qualifiers_list
[qlf_idx
]);
5486 /* Print the hint. */
5487 output_info (_(" did you mean this?"));
5488 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5489 print_operands (buf
, opcode
, inst_base
->operands
);
5490 output_info (_(" %s"), buf
);
5492 /* Print out other variant(s) if there is any. */
5494 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5495 output_info (_(" other valid variant(s):"));
5497 /* For each pattern. */
5498 qualifiers_list
= opcode
->qualifiers_list
;
5499 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5501 /* Most opcodes has much fewer patterns in the list.
5502 First NIL qualifier indicates the end in the list. */
5503 if (empty_qualifier_sequence_p (*qualifiers_list
))
5508 /* Mnemonics name. */
5509 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5511 /* Assign the qualifiers. */
5512 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5514 /* Print instruction. */
5515 print_operands (buf
, opcode
, inst_base
->operands
);
5517 output_info (_(" %s"), buf
);
5523 case AARCH64_OPDE_UNTIED_IMMS
:
5524 handler (_("operand %d must have the same immediate value "
5525 "as operand 1 -- `%s'"),
5526 detail
->index
+ 1, str
);
5529 case AARCH64_OPDE_UNTIED_OPERAND
:
5530 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5531 detail
->index
+ 1, str
);
5534 case AARCH64_OPDE_OUT_OF_RANGE
:
5535 if (detail
->data
[0] != detail
->data
[1])
5536 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5537 detail
->error
? detail
->error
: _("immediate value"),
5538 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
5540 handler (_("%s must be %d at operand %d -- `%s'"),
5541 detail
->error
? detail
->error
: _("immediate value"),
5542 detail
->data
[0], idx
+ 1, str
);
5545 case AARCH64_OPDE_REG_LIST
:
5546 if (detail
->data
[0] == 1)
5547 handler (_("invalid number of registers in the list; "
5548 "only 1 register is expected at operand %d -- `%s'"),
5551 handler (_("invalid number of registers in the list; "
5552 "%d registers are expected at operand %d -- `%s'"),
5553 detail
->data
[0], idx
+ 1, str
);
5556 case AARCH64_OPDE_UNALIGNED
:
5557 handler (_("immediate value must be a multiple of "
5558 "%d at operand %d -- `%s'"),
5559 detail
->data
[0], idx
+ 1, str
);
5568 /* Process and output the error message about the operand mismatching.
5570 When this function is called, the operand error information had
5571 been collected for an assembly line and there will be multiple
5572 errors in the case of multiple instruction templates; output the
5573 error message that most closely describes the problem.
5575 The errors to be printed can be filtered on printing all errors
5576 or only non-fatal errors. This distinction has to be made because
5577 the error buffer may already be filled with fatal errors we don't want to
5578 print due to the different instruction templates. */
5581 output_operand_error_report (char *str
, bool non_fatal_only
)
5583 int largest_error_pos
;
5584 const char *msg
= NULL
;
5585 enum aarch64_operand_error_kind kind
;
5586 operand_error_record
*curr
;
5587 operand_error_record
*head
= operand_error_report
.head
;
5588 operand_error_record
*record
= NULL
;
5590 /* No error to report. */
5594 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5596 /* Only one error. */
5597 if (head
== operand_error_report
.tail
)
5599 /* If the only error is a non-fatal one and we don't want to print it,
5601 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5603 DEBUG_TRACE ("single opcode entry with error kind: %s",
5604 operand_mismatch_kind_names
[head
->detail
.kind
]);
5605 output_operand_error_record (head
, str
);
5610 /* Find the error kind of the highest severity. */
5611 DEBUG_TRACE ("multiple opcode entries with error kind");
5612 kind
= AARCH64_OPDE_NIL
;
5613 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5615 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5616 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5617 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5618 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5619 kind
= curr
->detail
.kind
;
5622 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5624 /* Pick up one of errors of KIND to report. */
5625 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5626 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5628 /* If we don't want to print non-fatal errors then don't consider them
5630 if (curr
->detail
.kind
!= kind
5631 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5633 /* If there are multiple errors, pick up the one with the highest
5634 mismatching operand index. In the case of multiple errors with
5635 the equally highest operand index, pick up the first one or the
5636 first one with non-NULL error message. */
5637 if (curr
->detail
.index
> largest_error_pos
5638 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5639 && curr
->detail
.error
!= NULL
))
5641 largest_error_pos
= curr
->detail
.index
;
5643 msg
= record
->detail
.error
;
5647 /* The way errors are collected in the back-end is a bit non-intuitive. But
5648 essentially, because each operand template is tried recursively you may
5649 always have errors collected from the previous tried OPND. These are
5650 usually skipped if there is one successful match. However now with the
5651 non-fatal errors we have to ignore those previously collected hard errors
5652 when we're only interested in printing the non-fatal ones. This condition
5653 prevents us from printing errors that are not appropriate, since we did
5654 match a condition, but it also has warnings that it wants to print. */
5655 if (non_fatal_only
&& !record
)
5658 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5659 DEBUG_TRACE ("Pick up error kind %s to report",
5660 operand_mismatch_kind_names
[record
->detail
.kind
]);
5663 output_operand_error_record (record
, str
);
5666 /* Write an AARCH64 instruction to buf - always little-endian. */
5668 put_aarch64_insn (char *buf
, uint32_t insn
)
5670 unsigned char *where
= (unsigned char *) buf
;
5672 where
[1] = insn
>> 8;
5673 where
[2] = insn
>> 16;
5674 where
[3] = insn
>> 24;
5678 get_aarch64_insn (char *buf
)
5680 unsigned char *where
= (unsigned char *) buf
;
5682 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5683 | ((uint32_t) where
[3] << 24)));
5688 output_inst (struct aarch64_inst
*new_inst
)
5692 to
= frag_more (INSN_SIZE
);
5694 frag_now
->tc_frag_data
.recorded
= 1;
5696 put_aarch64_insn (to
, inst
.base
.value
);
5698 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5700 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5701 INSN_SIZE
, &inst
.reloc
.exp
,
5704 DEBUG_TRACE ("Prepared relocation fix up");
5705 /* Don't check the addend value against the instruction size,
5706 that's the job of our code in md_apply_fix(). */
5707 fixp
->fx_no_overflow
= 1;
5708 if (new_inst
!= NULL
)
5709 fixp
->tc_fix_data
.inst
= new_inst
;
5710 if (aarch64_gas_internal_fixup_p ())
5712 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5713 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5714 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5718 dwarf2_emit_insn (INSN_SIZE
);
5721 /* Link together opcodes of the same name. */
5725 const aarch64_opcode
*opcode
;
5726 struct templates
*next
;
5729 typedef struct templates templates
;
5732 lookup_mnemonic (const char *start
, int len
)
5734 templates
*templ
= NULL
;
5736 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5740 /* Subroutine of md_assemble, responsible for looking up the primary
5741 opcode from the mnemonic the user wrote. STR points to the
5742 beginning of the mnemonic. */
5745 opcode_lookup (char **str
)
5747 char *end
, *base
, *dot
;
5748 const aarch64_cond
*cond
;
5752 /* Scan up to the end of the mnemonic, which must end in white space,
5753 '.', or end of string. */
5755 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
5756 if (*end
== '.' && !dot
)
5759 if (end
== base
|| dot
== base
)
5762 inst
.cond
= COND_ALWAYS
;
5764 /* Handle a possible condition. */
5767 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5770 inst
.cond
= cond
->value
;
5786 if (inst
.cond
== COND_ALWAYS
)
5788 /* Look for unaffixed mnemonic. */
5789 return lookup_mnemonic (base
, len
);
5793 /* append ".c" to mnemonic if conditional */
5794 memcpy (condname
, base
, len
);
5795 memcpy (condname
+ len
, ".c", 2);
5798 return lookup_mnemonic (base
, len
);
5804 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5805 to a corresponding operand qualifier. */
5807 static inline aarch64_opnd_qualifier_t
5808 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5810 /* Element size in bytes indexed by vector_el_type. */
5811 const unsigned char ele_size
[5]
5813 const unsigned int ele_base
[5] =
5815 AARCH64_OPND_QLF_V_4B
,
5816 AARCH64_OPND_QLF_V_2H
,
5817 AARCH64_OPND_QLF_V_2S
,
5818 AARCH64_OPND_QLF_V_1D
,
5819 AARCH64_OPND_QLF_V_1Q
5822 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5823 goto vectype_conversion_fail
;
5825 if (vectype
->type
== NT_zero
)
5826 return AARCH64_OPND_QLF_P_Z
;
5827 if (vectype
->type
== NT_merge
)
5828 return AARCH64_OPND_QLF_P_M
;
5830 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5832 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5834 /* Special case S_4B. */
5835 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5836 return AARCH64_OPND_QLF_S_4B
;
5838 /* Special case S_2H. */
5839 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5840 return AARCH64_OPND_QLF_S_2H
;
5842 /* Vector element register. */
5843 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5847 /* Vector register. */
5848 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5851 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5852 goto vectype_conversion_fail
;
5854 /* The conversion is by calculating the offset from the base operand
5855 qualifier for the vector type. The operand qualifiers are regular
5856 enough that the offset can established by shifting the vector width by
5857 a vector-type dependent amount. */
5859 if (vectype
->type
== NT_b
)
5861 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5863 else if (vectype
->type
>= NT_d
)
5868 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5869 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5870 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5874 vectype_conversion_fail
:
5875 first_error (_("bad vector arrangement type"));
5876 return AARCH64_OPND_QLF_NIL
;
5879 /* Process an optional operand that is found omitted from the assembly line.
5880 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5881 instruction's opcode entry while IDX is the index of this omitted operand.
5885 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5886 int idx
, aarch64_opnd_info
*operand
)
5888 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5889 gas_assert (optional_operand_p (opcode
, idx
));
5890 gas_assert (!operand
->present
);
5894 case AARCH64_OPND_Rd
:
5895 case AARCH64_OPND_Rn
:
5896 case AARCH64_OPND_Rm
:
5897 case AARCH64_OPND_Rt
:
5898 case AARCH64_OPND_Rt2
:
5899 case AARCH64_OPND_Rt_LS64
:
5900 case AARCH64_OPND_Rt_SP
:
5901 case AARCH64_OPND_Rs
:
5902 case AARCH64_OPND_Ra
:
5903 case AARCH64_OPND_Rt_SYS
:
5904 case AARCH64_OPND_Rd_SP
:
5905 case AARCH64_OPND_Rn_SP
:
5906 case AARCH64_OPND_Rm_SP
:
5907 case AARCH64_OPND_Fd
:
5908 case AARCH64_OPND_Fn
:
5909 case AARCH64_OPND_Fm
:
5910 case AARCH64_OPND_Fa
:
5911 case AARCH64_OPND_Ft
:
5912 case AARCH64_OPND_Ft2
:
5913 case AARCH64_OPND_Sd
:
5914 case AARCH64_OPND_Sn
:
5915 case AARCH64_OPND_Sm
:
5916 case AARCH64_OPND_Va
:
5917 case AARCH64_OPND_Vd
:
5918 case AARCH64_OPND_Vn
:
5919 case AARCH64_OPND_Vm
:
5920 case AARCH64_OPND_VdD1
:
5921 case AARCH64_OPND_VnD1
:
5922 operand
->reg
.regno
= default_value
;
5925 case AARCH64_OPND_Ed
:
5926 case AARCH64_OPND_En
:
5927 case AARCH64_OPND_Em
:
5928 case AARCH64_OPND_Em16
:
5929 case AARCH64_OPND_SM3_IMM2
:
5930 operand
->reglane
.regno
= default_value
;
5933 case AARCH64_OPND_IDX
:
5934 case AARCH64_OPND_BIT_NUM
:
5935 case AARCH64_OPND_IMMR
:
5936 case AARCH64_OPND_IMMS
:
5937 case AARCH64_OPND_SHLL_IMM
:
5938 case AARCH64_OPND_IMM_VLSL
:
5939 case AARCH64_OPND_IMM_VLSR
:
5940 case AARCH64_OPND_CCMP_IMM
:
5941 case AARCH64_OPND_FBITS
:
5942 case AARCH64_OPND_UIMM4
:
5943 case AARCH64_OPND_UIMM3_OP1
:
5944 case AARCH64_OPND_UIMM3_OP2
:
5945 case AARCH64_OPND_IMM
:
5946 case AARCH64_OPND_IMM_2
:
5947 case AARCH64_OPND_WIDTH
:
5948 case AARCH64_OPND_UIMM7
:
5949 case AARCH64_OPND_NZCV
:
5950 case AARCH64_OPND_SVE_PATTERN
:
5951 case AARCH64_OPND_SVE_PRFOP
:
5952 operand
->imm
.value
= default_value
;
5955 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5956 operand
->imm
.value
= default_value
;
5957 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5958 operand
->shifter
.amount
= 1;
5961 case AARCH64_OPND_EXCEPTION
:
5962 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5965 case AARCH64_OPND_BARRIER_ISB
:
5966 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5969 case AARCH64_OPND_BTI_TARGET
:
5970 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5978 /* Process the relocation type for move wide instructions.
5979 Return TRUE on success; otherwise return FALSE. */
5982 process_movw_reloc_info (void)
5987 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5989 if (inst
.base
.opcode
->op
== OP_MOVK
)
5990 switch (inst
.reloc
.type
)
5992 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5993 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5994 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5995 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5996 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5997 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5998 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5999 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6000 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6001 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6002 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6004 (_("the specified relocation type is not allowed for MOVK"));
6010 switch (inst
.reloc
.type
)
6012 case BFD_RELOC_AARCH64_MOVW_G0
:
6013 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6014 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6015 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6016 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6017 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6018 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6019 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6020 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6021 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6022 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6023 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6024 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6027 case BFD_RELOC_AARCH64_MOVW_G1
:
6028 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6029 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6030 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6031 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6032 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6033 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6034 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6035 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6036 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6037 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6038 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6039 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6042 case BFD_RELOC_AARCH64_MOVW_G2
:
6043 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6044 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6045 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6046 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6047 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6048 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6051 set_fatal_syntax_error
6052 (_("the specified relocation type is not allowed for 32-bit "
6058 case BFD_RELOC_AARCH64_MOVW_G3
:
6059 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6062 set_fatal_syntax_error
6063 (_("the specified relocation type is not allowed for 32-bit "
6070 /* More cases should be added when more MOVW-related relocation types
6071 are supported in GAS. */
6072 gas_assert (aarch64_gas_internal_fixup_p ());
6073 /* The shift amount should have already been set by the parser. */
6076 inst
.base
.operands
[1].shifter
.amount
= shift
;
6080 /* A primitive log calculator. */
6082 static inline unsigned int
6083 get_logsz (unsigned int size
)
6085 const unsigned char ls
[16] =
6086 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
6092 gas_assert (ls
[size
- 1] != (unsigned char)-1);
6093 return ls
[size
- 1];
6096 /* Determine and return the real reloc type code for an instruction
6097 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6099 static inline bfd_reloc_code_real_type
6100 ldst_lo12_determine_real_reloc_type (void)
6102 unsigned logsz
, max_logsz
;
6103 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6104 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6106 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6108 BFD_RELOC_AARCH64_LDST8_LO12
,
6109 BFD_RELOC_AARCH64_LDST16_LO12
,
6110 BFD_RELOC_AARCH64_LDST32_LO12
,
6111 BFD_RELOC_AARCH64_LDST64_LO12
,
6112 BFD_RELOC_AARCH64_LDST128_LO12
6115 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6116 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6117 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6118 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6119 BFD_RELOC_AARCH64_NONE
6122 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6123 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6124 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6125 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6126 BFD_RELOC_AARCH64_NONE
6129 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6130 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6131 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6132 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6133 BFD_RELOC_AARCH64_NONE
6136 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6137 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6138 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6139 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6140 BFD_RELOC_AARCH64_NONE
6144 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6145 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6147 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6149 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6151 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6152 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6154 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6156 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6158 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6160 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
6162 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6163 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6164 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6165 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6170 if (logsz
> max_logsz
)
6172 /* SEE PR 27904 for an example of this. */
6173 set_fatal_syntax_error
6174 (_("relocation qualifier does not match instruction size"));
6175 return BFD_RELOC_AARCH64_NONE
;
6178 /* In reloc.c, these pseudo relocation types should be defined in similar
6179 order as above reloc_ldst_lo12 array. Because the array index calculation
6180 below relies on this. */
6181 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6184 /* Check whether a register list REGINFO is valid. The registers must be
6185 numbered in increasing order (modulo 32), in increments of one or two.
6187 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
6190 Return FALSE if such a register list is invalid, otherwise return TRUE. */
6193 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
6195 uint32_t i
, nb_regs
, prev_regno
, incr
;
6197 nb_regs
= 1 + (reginfo
& 0x3);
6199 prev_regno
= reginfo
& 0x1f;
6200 incr
= accept_alternate
? 2 : 1;
6202 for (i
= 1; i
< nb_regs
; ++i
)
6204 uint32_t curr_regno
;
6206 curr_regno
= reginfo
& 0x1f;
6207 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
6209 prev_regno
= curr_regno
;
6215 /* Generic instruction operand parser. This does no encoding and no
6216 semantic validation; it merely squirrels values away in the inst
6217 structure. Returns TRUE or FALSE depending on whether the
6218 specified grammar matched. */
6221 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6224 char *backtrack_pos
= 0;
6225 const enum aarch64_opnd
*operands
= opcode
->operands
;
6226 aarch64_reg_type imm_reg_type
;
6229 skip_whitespace (str
);
6231 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
6232 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
6234 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
6236 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6239 const reg_entry
*reg
;
6240 int comma_skipped_p
= 0;
6241 aarch64_reg_type rtype
;
6242 struct vector_type_el vectype
;
6243 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6244 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6245 aarch64_reg_type reg_type
;
6247 DEBUG_TRACE ("parse operand %d", i
);
6249 /* Assign the operand code. */
6250 info
->type
= operands
[i
];
6252 if (optional_operand_p (opcode
, i
))
6254 /* Remember where we are in case we need to backtrack. */
6255 gas_assert (!backtrack_pos
);
6256 backtrack_pos
= str
;
6259 /* Expect comma between operands; the backtrack mechanism will take
6260 care of cases of omitted optional operand. */
6261 if (i
> 0 && ! skip_past_char (&str
, ','))
6263 set_syntax_error (_("comma expected between operands"));
6267 comma_skipped_p
= 1;
6269 switch (operands
[i
])
6271 case AARCH64_OPND_Rd
:
6272 case AARCH64_OPND_Rn
:
6273 case AARCH64_OPND_Rm
:
6274 case AARCH64_OPND_Rt
:
6275 case AARCH64_OPND_Rt2
:
6276 case AARCH64_OPND_Rs
:
6277 case AARCH64_OPND_Ra
:
6278 case AARCH64_OPND_Rt_LS64
:
6279 case AARCH64_OPND_Rt_SYS
:
6280 case AARCH64_OPND_PAIRREG
:
6281 case AARCH64_OPND_SVE_Rm
:
6282 po_int_reg_or_fail (REG_TYPE_R_Z
);
6284 /* In LS64 load/store instructions Rt register number must be even
6286 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6288 /* We've already checked if this is valid register.
6289 This will check if register number (Rt) is not undefined for LS64
6291 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6292 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6294 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6300 case AARCH64_OPND_Rd_SP
:
6301 case AARCH64_OPND_Rn_SP
:
6302 case AARCH64_OPND_Rt_SP
:
6303 case AARCH64_OPND_SVE_Rn_SP
:
6304 case AARCH64_OPND_Rm_SP
:
6305 po_int_reg_or_fail (REG_TYPE_R_SP
);
6308 case AARCH64_OPND_Rm_EXT
:
6309 case AARCH64_OPND_Rm_SFT
:
6310 po_misc_or_fail (parse_shifter_operand
6311 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6313 : SHIFTED_LOGIC_IMM
)));
6314 if (!info
->shifter
.operator_present
)
6316 /* Default to LSL if not present. Libopcodes prefers shifter
6317 kind to be explicit. */
6318 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6319 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6320 /* For Rm_EXT, libopcodes will carry out further check on whether
6321 or not stack pointer is used in the instruction (Recall that
6322 "the extend operator is not optional unless at least one of
6323 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6327 case AARCH64_OPND_Fd
:
6328 case AARCH64_OPND_Fn
:
6329 case AARCH64_OPND_Fm
:
6330 case AARCH64_OPND_Fa
:
6331 case AARCH64_OPND_Ft
:
6332 case AARCH64_OPND_Ft2
:
6333 case AARCH64_OPND_Sd
:
6334 case AARCH64_OPND_Sn
:
6335 case AARCH64_OPND_Sm
:
6336 case AARCH64_OPND_SVE_VZn
:
6337 case AARCH64_OPND_SVE_Vd
:
6338 case AARCH64_OPND_SVE_Vm
:
6339 case AARCH64_OPND_SVE_Vn
:
6340 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
6341 if (val
== PARSE_FAIL
)
6343 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
6346 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
6348 info
->reg
.regno
= val
;
6349 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
6352 case AARCH64_OPND_SVE_Pd
:
6353 case AARCH64_OPND_SVE_Pg3
:
6354 case AARCH64_OPND_SVE_Pg4_5
:
6355 case AARCH64_OPND_SVE_Pg4_10
:
6356 case AARCH64_OPND_SVE_Pg4_16
:
6357 case AARCH64_OPND_SVE_Pm
:
6358 case AARCH64_OPND_SVE_Pn
:
6359 case AARCH64_OPND_SVE_Pt
:
6360 case AARCH64_OPND_SME_Pm
:
6361 reg_type
= REG_TYPE_PN
;
6364 case AARCH64_OPND_SVE_Za_5
:
6365 case AARCH64_OPND_SVE_Za_16
:
6366 case AARCH64_OPND_SVE_Zd
:
6367 case AARCH64_OPND_SVE_Zm_5
:
6368 case AARCH64_OPND_SVE_Zm_16
:
6369 case AARCH64_OPND_SVE_Zn
:
6370 case AARCH64_OPND_SVE_Zt
:
6371 reg_type
= REG_TYPE_ZN
;
6374 case AARCH64_OPND_Va
:
6375 case AARCH64_OPND_Vd
:
6376 case AARCH64_OPND_Vn
:
6377 case AARCH64_OPND_Vm
:
6378 reg_type
= REG_TYPE_VN
;
6380 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6381 if (val
== PARSE_FAIL
)
6383 first_error (_(get_reg_expected_msg (reg_type
)));
6386 if (vectype
.defined
& NTA_HASINDEX
)
6389 info
->reg
.regno
= val
;
6390 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
6391 && vectype
.type
== NT_invtype
)
6392 /* Unqualified Pn and Zn registers are allowed in certain
6393 contexts. Rely on F_STRICT qualifier checking to catch
6395 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6398 info
->qualifier
= vectype_to_qualifier (&vectype
);
6399 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6404 case AARCH64_OPND_VdD1
:
6405 case AARCH64_OPND_VnD1
:
6406 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
6407 if (val
== PARSE_FAIL
)
6409 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
6412 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6414 set_fatal_syntax_error
6415 (_("the top half of a 128-bit FP/SIMD register is expected"));
6418 info
->reg
.regno
= val
;
6419 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6420 here; it is correct for the purpose of encoding/decoding since
6421 only the register number is explicitly encoded in the related
6422 instructions, although this appears a bit hacky. */
6423 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6426 case AARCH64_OPND_SVE_Zm3_INDEX
:
6427 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6428 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6429 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6430 case AARCH64_OPND_SVE_Zm4_INDEX
:
6431 case AARCH64_OPND_SVE_Zn_INDEX
:
6432 reg_type
= REG_TYPE_ZN
;
6433 goto vector_reg_index
;
6435 case AARCH64_OPND_Ed
:
6436 case AARCH64_OPND_En
:
6437 case AARCH64_OPND_Em
:
6438 case AARCH64_OPND_Em16
:
6439 case AARCH64_OPND_SM3_IMM2
:
6440 reg_type
= REG_TYPE_VN
;
6442 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6443 if (val
== PARSE_FAIL
)
6445 first_error (_(get_reg_expected_msg (reg_type
)));
6448 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6451 info
->reglane
.regno
= val
;
6452 info
->reglane
.index
= vectype
.index
;
6453 info
->qualifier
= vectype_to_qualifier (&vectype
);
6454 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6458 case AARCH64_OPND_SVE_ZnxN
:
6459 case AARCH64_OPND_SVE_ZtxN
:
6460 reg_type
= REG_TYPE_ZN
;
6461 goto vector_reg_list
;
6463 case AARCH64_OPND_LVn
:
6464 case AARCH64_OPND_LVt
:
6465 case AARCH64_OPND_LVt_AL
:
6466 case AARCH64_OPND_LEt
:
6467 reg_type
= REG_TYPE_VN
;
6469 if (reg_type
== REG_TYPE_ZN
6470 && get_opcode_dependent_value (opcode
) == 1
6473 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6474 if (val
== PARSE_FAIL
)
6476 first_error (_(get_reg_expected_msg (reg_type
)));
6479 info
->reglist
.first_regno
= val
;
6480 info
->reglist
.num_regs
= 1;
6484 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6485 if (val
== PARSE_FAIL
)
6488 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6490 set_fatal_syntax_error (_("invalid register list"));
6494 if (vectype
.width
!= 0 && *str
!= ',')
6496 set_fatal_syntax_error
6497 (_("expected element type rather than vector type"));
6501 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6502 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6504 if (operands
[i
] == AARCH64_OPND_LEt
)
6506 if (!(vectype
.defined
& NTA_HASINDEX
))
6508 info
->reglist
.has_index
= 1;
6509 info
->reglist
.index
= vectype
.index
;
6513 if (vectype
.defined
& NTA_HASINDEX
)
6515 if (!(vectype
.defined
& NTA_HASTYPE
))
6517 if (reg_type
== REG_TYPE_ZN
)
6518 set_fatal_syntax_error (_("missing type suffix"));
6522 info
->qualifier
= vectype_to_qualifier (&vectype
);
6523 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6527 case AARCH64_OPND_CRn
:
6528 case AARCH64_OPND_CRm
:
6530 char prefix
= *(str
++);
6531 if (prefix
!= 'c' && prefix
!= 'C')
6534 po_imm_nc_or_fail ();
6537 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6540 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6541 info
->imm
.value
= val
;
6545 case AARCH64_OPND_SHLL_IMM
:
6546 case AARCH64_OPND_IMM_VLSR
:
6547 po_imm_or_fail (1, 64);
6548 info
->imm
.value
= val
;
6551 case AARCH64_OPND_CCMP_IMM
:
6552 case AARCH64_OPND_SIMM5
:
6553 case AARCH64_OPND_FBITS
:
6554 case AARCH64_OPND_TME_UIMM16
:
6555 case AARCH64_OPND_UIMM4
:
6556 case AARCH64_OPND_UIMM4_ADDG
:
6557 case AARCH64_OPND_UIMM10
:
6558 case AARCH64_OPND_UIMM3_OP1
:
6559 case AARCH64_OPND_UIMM3_OP2
:
6560 case AARCH64_OPND_IMM_VLSL
:
6561 case AARCH64_OPND_IMM
:
6562 case AARCH64_OPND_IMM_2
:
6563 case AARCH64_OPND_WIDTH
:
6564 case AARCH64_OPND_SVE_INV_LIMM
:
6565 case AARCH64_OPND_SVE_LIMM
:
6566 case AARCH64_OPND_SVE_LIMM_MOV
:
6567 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6568 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6569 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6570 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6571 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6572 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6573 case AARCH64_OPND_SVE_SIMM5
:
6574 case AARCH64_OPND_SVE_SIMM5B
:
6575 case AARCH64_OPND_SVE_SIMM6
:
6576 case AARCH64_OPND_SVE_SIMM8
:
6577 case AARCH64_OPND_SVE_UIMM3
:
6578 case AARCH64_OPND_SVE_UIMM7
:
6579 case AARCH64_OPND_SVE_UIMM8
:
6580 case AARCH64_OPND_SVE_UIMM8_53
:
6581 case AARCH64_OPND_IMM_ROT1
:
6582 case AARCH64_OPND_IMM_ROT2
:
6583 case AARCH64_OPND_IMM_ROT3
:
6584 case AARCH64_OPND_SVE_IMM_ROT1
:
6585 case AARCH64_OPND_SVE_IMM_ROT2
:
6586 case AARCH64_OPND_SVE_IMM_ROT3
:
6587 po_imm_nc_or_fail ();
6588 info
->imm
.value
= val
;
6591 case AARCH64_OPND_SVE_AIMM
:
6592 case AARCH64_OPND_SVE_ASIMM
:
6593 po_imm_nc_or_fail ();
6594 info
->imm
.value
= val
;
6595 skip_whitespace (str
);
6596 if (skip_past_comma (&str
))
6597 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6599 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6602 case AARCH64_OPND_SVE_PATTERN
:
6603 po_enum_or_fail (aarch64_sve_pattern_array
);
6604 info
->imm
.value
= val
;
6607 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6608 po_enum_or_fail (aarch64_sve_pattern_array
);
6609 info
->imm
.value
= val
;
6610 if (skip_past_comma (&str
)
6611 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6613 if (!info
->shifter
.operator_present
)
6615 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6616 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6617 info
->shifter
.amount
= 1;
6621 case AARCH64_OPND_SVE_PRFOP
:
6622 po_enum_or_fail (aarch64_sve_prfop_array
);
6623 info
->imm
.value
= val
;
6626 case AARCH64_OPND_UIMM7
:
6627 po_imm_or_fail (0, 127);
6628 info
->imm
.value
= val
;
6631 case AARCH64_OPND_IDX
:
6632 case AARCH64_OPND_MASK
:
6633 case AARCH64_OPND_BIT_NUM
:
6634 case AARCH64_OPND_IMMR
:
6635 case AARCH64_OPND_IMMS
:
6636 po_imm_or_fail (0, 63);
6637 info
->imm
.value
= val
;
6640 case AARCH64_OPND_IMM0
:
6641 po_imm_nc_or_fail ();
6644 set_fatal_syntax_error (_("immediate zero expected"));
6647 info
->imm
.value
= 0;
6650 case AARCH64_OPND_FPIMM0
:
6653 bool res1
= false, res2
= false;
6654 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6655 it is probably not worth the effort to support it. */
6656 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6659 || !(res2
= parse_constant_immediate (&str
, &val
,
6662 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6664 info
->imm
.value
= 0;
6665 info
->imm
.is_fp
= 1;
6668 set_fatal_syntax_error (_("immediate zero expected"));
6672 case AARCH64_OPND_IMM_MOV
:
6675 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6676 reg_name_p (str
, REG_TYPE_VN
))
6679 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6680 GE_OPT_PREFIX
, REJECT_ABSENT
,
6681 NORMAL_RESOLUTION
));
6682 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6683 later. fix_mov_imm_insn will try to determine a machine
6684 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6685 message if the immediate cannot be moved by a single
6687 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6688 inst
.base
.operands
[i
].skip
= 1;
6692 case AARCH64_OPND_SIMD_IMM
:
6693 case AARCH64_OPND_SIMD_IMM_SFT
:
6694 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6696 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6698 /* need_libopcodes_p */ 1,
6701 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6702 shift, we don't check it here; we leave the checking to
6703 the libopcodes (operand_general_constraint_met_p). By
6704 doing this, we achieve better diagnostics. */
6705 if (skip_past_comma (&str
)
6706 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6708 if (!info
->shifter
.operator_present
6709 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6711 /* Default to LSL if not present. Libopcodes prefers shifter
6712 kind to be explicit. */
6713 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6714 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6718 case AARCH64_OPND_FPIMM
:
6719 case AARCH64_OPND_SIMD_FPIMM
:
6720 case AARCH64_OPND_SVE_FPIMM8
:
6725 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6726 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6727 || !aarch64_imm_float_p (qfloat
))
6730 set_fatal_syntax_error (_("invalid floating-point"
6734 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6735 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6739 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6740 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6741 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6746 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6747 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6750 set_fatal_syntax_error (_("invalid floating-point"
6754 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6755 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6759 case AARCH64_OPND_LIMM
:
6760 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6761 SHIFTED_LOGIC_IMM
));
6762 if (info
->shifter
.operator_present
)
6764 set_fatal_syntax_error
6765 (_("shift not allowed for bitmask immediate"));
6768 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6770 /* need_libopcodes_p */ 1,
6774 case AARCH64_OPND_AIMM
:
6775 if (opcode
->op
== OP_ADD
)
6776 /* ADD may have relocation types. */
6777 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6778 SHIFTED_ARITH_IMM
));
6780 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6781 SHIFTED_ARITH_IMM
));
6782 switch (inst
.reloc
.type
)
6784 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6785 info
->shifter
.amount
= 12;
6787 case BFD_RELOC_UNUSED
:
6788 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6789 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6790 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6791 inst
.reloc
.pc_rel
= 0;
6796 info
->imm
.value
= 0;
6797 if (!info
->shifter
.operator_present
)
6799 /* Default to LSL if not present. Libopcodes prefers shifter
6800 kind to be explicit. */
6801 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6802 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6806 case AARCH64_OPND_HALF
:
6808 /* #<imm16> or relocation. */
6809 int internal_fixup_p
;
6810 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6811 if (internal_fixup_p
)
6812 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6813 skip_whitespace (str
);
6814 if (skip_past_comma (&str
))
6816 /* {, LSL #<shift>} */
6817 if (! aarch64_gas_internal_fixup_p ())
6819 set_fatal_syntax_error (_("can't mix relocation modifier "
6820 "with explicit shift"));
6823 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6826 inst
.base
.operands
[i
].shifter
.amount
= 0;
6827 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6828 inst
.base
.operands
[i
].imm
.value
= 0;
6829 if (! process_movw_reloc_info ())
6834 case AARCH64_OPND_EXCEPTION
:
6835 case AARCH64_OPND_UNDEFINED
:
6836 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6838 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6840 /* need_libopcodes_p */ 0,
6844 case AARCH64_OPND_NZCV
:
6846 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6850 info
->imm
.value
= nzcv
->value
;
6853 po_imm_or_fail (0, 15);
6854 info
->imm
.value
= val
;
6858 case AARCH64_OPND_COND
:
6859 case AARCH64_OPND_COND1
:
6864 while (ISALPHA (*str
));
6865 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6866 if (info
->cond
== NULL
)
6868 set_syntax_error (_("invalid condition"));
6871 else if (operands
[i
] == AARCH64_OPND_COND1
6872 && (info
->cond
->value
& 0xe) == 0xe)
6874 /* Do not allow AL or NV. */
6875 set_default_error ();
6881 case AARCH64_OPND_ADDR_ADRP
:
6882 po_misc_or_fail (parse_adrp (&str
));
6883 /* Clear the value as operand needs to be relocated. */
6884 info
->imm
.value
= 0;
6887 case AARCH64_OPND_ADDR_PCREL14
:
6888 case AARCH64_OPND_ADDR_PCREL19
:
6889 case AARCH64_OPND_ADDR_PCREL21
:
6890 case AARCH64_OPND_ADDR_PCREL26
:
6891 po_misc_or_fail (parse_address (&str
, info
));
6892 if (!info
->addr
.pcrel
)
6894 set_syntax_error (_("invalid pc-relative address"));
6897 if (inst
.gen_lit_pool
6898 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6900 /* Only permit "=value" in the literal load instructions.
6901 The literal will be generated by programmer_friendly_fixup. */
6902 set_syntax_error (_("invalid use of \"=immediate\""));
6905 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6907 set_syntax_error (_("unrecognized relocation suffix"));
6910 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6912 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6913 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6917 info
->imm
.value
= 0;
6918 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6919 switch (opcode
->iclass
)
6923 /* e.g. CBZ or B.COND */
6924 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6925 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6929 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6930 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6934 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6936 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6937 : BFD_RELOC_AARCH64_JUMP26
;
6940 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6941 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6944 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6945 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6951 inst
.reloc
.pc_rel
= 1;
6955 case AARCH64_OPND_ADDR_SIMPLE
:
6956 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6958 /* [<Xn|SP>{, #<simm>}] */
6960 /* First use the normal address-parsing routines, to get
6961 the usual syntax errors. */
6962 po_misc_or_fail (parse_address (&str
, info
));
6963 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6964 || !info
->addr
.preind
|| info
->addr
.postind
6965 || info
->addr
.writeback
)
6967 set_syntax_error (_("invalid addressing mode"));
6971 /* Then retry, matching the specific syntax of these addresses. */
6973 po_char_or_fail ('[');
6974 po_reg_or_fail (REG_TYPE_R64_SP
);
6975 /* Accept optional ", #0". */
6976 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6977 && skip_past_char (&str
, ','))
6979 skip_past_char (&str
, '#');
6980 if (! skip_past_char (&str
, '0'))
6982 set_fatal_syntax_error
6983 (_("the optional immediate offset can only be 0"));
6987 po_char_or_fail (']');
6991 case AARCH64_OPND_ADDR_REGOFF
:
6992 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6993 po_misc_or_fail (parse_address (&str
, info
));
6995 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6996 || !info
->addr
.preind
|| info
->addr
.postind
6997 || info
->addr
.writeback
)
6999 set_syntax_error (_("invalid addressing mode"));
7002 if (!info
->shifter
.operator_present
)
7004 /* Default to LSL if not present. Libopcodes prefers shifter
7005 kind to be explicit. */
7006 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7007 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7009 /* Qualifier to be deduced by libopcodes. */
7012 case AARCH64_OPND_ADDR_SIMM7
:
7013 po_misc_or_fail (parse_address (&str
, info
));
7014 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7015 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7017 set_syntax_error (_("invalid addressing mode"));
7020 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7022 set_syntax_error (_("relocation not allowed"));
7025 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7027 /* need_libopcodes_p */ 1,
7031 case AARCH64_OPND_ADDR_SIMM9
:
7032 case AARCH64_OPND_ADDR_SIMM9_2
:
7033 case AARCH64_OPND_ADDR_SIMM11
:
7034 case AARCH64_OPND_ADDR_SIMM13
:
7035 po_misc_or_fail (parse_address (&str
, info
));
7036 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7037 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7038 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7039 && info
->addr
.writeback
))
7041 set_syntax_error (_("invalid addressing mode"));
7044 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7046 set_syntax_error (_("relocation not allowed"));
7049 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7051 /* need_libopcodes_p */ 1,
7055 case AARCH64_OPND_ADDR_SIMM10
:
7056 case AARCH64_OPND_ADDR_OFFSET
:
7057 po_misc_or_fail (parse_address (&str
, info
));
7058 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7059 || !info
->addr
.preind
|| info
->addr
.postind
)
7061 set_syntax_error (_("invalid addressing mode"));
7064 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7066 set_syntax_error (_("relocation not allowed"));
7069 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7071 /* need_libopcodes_p */ 1,
7075 case AARCH64_OPND_ADDR_UIMM12
:
7076 po_misc_or_fail (parse_address (&str
, info
));
7077 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7078 || !info
->addr
.preind
|| info
->addr
.writeback
)
7080 set_syntax_error (_("invalid addressing mode"));
7083 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7084 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7085 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7087 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7089 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7091 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7093 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7094 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7095 /* Leave qualifier to be determined by libopcodes. */
7098 case AARCH64_OPND_SIMD_ADDR_POST
:
7099 /* [<Xn|SP>], <Xm|#<amount>> */
7100 po_misc_or_fail (parse_address (&str
, info
));
7101 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7103 set_syntax_error (_("invalid addressing mode"));
7106 if (!info
->addr
.offset
.is_reg
)
7108 if (inst
.reloc
.exp
.X_op
== O_constant
)
7109 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7112 set_fatal_syntax_error
7113 (_("writeback value must be an immediate constant"));
7120 case AARCH64_OPND_SME_SM_ZA
:
7122 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7124 set_syntax_error (_("unknown or missing PSTATE field name"));
7127 info
->reg
.regno
= val
;
7130 case AARCH64_OPND_SME_PnT_Wm_imm
:
7131 /* <Pn>.<T>[<Wm>, #<imm>] */
7135 val
= parse_sme_pred_reg_with_index (&str
,
7139 if (val
== PARSE_FAIL
)
7142 info
->za_tile_vector
.regno
= val
;
7143 info
->za_tile_vector
.index
.regno
= index_base_reg
;
7144 info
->za_tile_vector
.index
.imm
= imm
;
7145 info
->qualifier
= qualifier
;
7149 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7150 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7151 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7152 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7153 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7154 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7155 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7156 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7157 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7158 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7159 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7160 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7161 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7162 /* [X<n>{, #imm, MUL VL}]
7164 but recognizing SVE registers. */
7165 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7166 &offset_qualifier
));
7167 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7169 set_syntax_error (_("invalid addressing mode"));
7173 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7174 || !info
->addr
.preind
|| info
->addr
.writeback
)
7176 set_syntax_error (_("invalid addressing mode"));
7179 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7180 || inst
.reloc
.exp
.X_op
!= O_constant
)
7182 /* Make sure this has priority over
7183 "invalid addressing mode". */
7184 set_fatal_syntax_error (_("constant offset required"));
7187 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7190 case AARCH64_OPND_SVE_ADDR_R
:
7191 /* [<Xn|SP>{, <R><m>}]
7192 but recognizing SVE registers. */
7193 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7194 &offset_qualifier
));
7195 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7197 offset_qualifier
= AARCH64_OPND_QLF_X
;
7198 info
->addr
.offset
.is_reg
= 1;
7199 info
->addr
.offset
.regno
= 31;
7201 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7202 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7204 set_syntax_error (_("invalid addressing mode"));
7209 case AARCH64_OPND_SVE_ADDR_RR
:
7210 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7211 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7212 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7213 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7214 case AARCH64_OPND_SVE_ADDR_RX
:
7215 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7216 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7217 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7218 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7219 but recognizing SVE registers. */
7220 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7221 &offset_qualifier
));
7222 if (base_qualifier
!= AARCH64_OPND_QLF_X
7223 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7225 set_syntax_error (_("invalid addressing mode"));
7230 case AARCH64_OPND_SVE_ADDR_RZ
:
7231 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7232 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7233 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7234 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7235 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7236 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7237 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7238 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7239 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7240 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7241 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7242 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7243 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7244 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7245 &offset_qualifier
));
7246 if (base_qualifier
!= AARCH64_OPND_QLF_X
7247 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7248 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7250 set_syntax_error (_("invalid addressing mode"));
7253 info
->qualifier
= offset_qualifier
;
7256 case AARCH64_OPND_SVE_ADDR_ZX
:
7257 /* [Zn.<T>{, <Xm>}]. */
7258 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7259 &offset_qualifier
));
7261 base_qualifier either S_S or S_D
7262 offset_qualifier must be X
7264 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7265 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7266 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7268 set_syntax_error (_("invalid addressing mode"));
7271 info
->qualifier
= base_qualifier
;
7272 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7273 || !info
->addr
.preind
|| info
->addr
.writeback
7274 || info
->shifter
.operator_present
!= 0)
7276 set_syntax_error (_("invalid addressing mode"));
7279 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7283 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7284 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7285 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7286 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7287 /* [Z<n>.<T>{, #imm}] */
7288 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7289 &offset_qualifier
));
7290 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7291 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7293 set_syntax_error (_("invalid addressing mode"));
7296 info
->qualifier
= base_qualifier
;
7299 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7300 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7301 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7302 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7303 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7307 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7309 here since we get better error messages by leaving it to
7310 the qualifier checking routines. */
7311 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7312 &offset_qualifier
));
7313 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7314 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7315 || offset_qualifier
!= base_qualifier
)
7317 set_syntax_error (_("invalid addressing mode"));
7320 info
->qualifier
= base_qualifier
;
7323 case AARCH64_OPND_SYSREG
:
7325 uint32_t sysreg_flags
;
7326 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7327 &sysreg_flags
)) == PARSE_FAIL
)
7329 set_syntax_error (_("unknown or missing system register name"));
7332 inst
.base
.operands
[i
].sysreg
.value
= val
;
7333 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7337 case AARCH64_OPND_PSTATEFIELD
:
7339 uint32_t sysreg_flags
;
7340 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7341 &sysreg_flags
)) == PARSE_FAIL
)
7343 set_syntax_error (_("unknown or missing PSTATE field name"));
7346 inst
.base
.operands
[i
].pstatefield
= val
;
7347 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7351 case AARCH64_OPND_SYSREG_IC
:
7352 inst
.base
.operands
[i
].sysins_op
=
7353 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7356 case AARCH64_OPND_SYSREG_DC
:
7357 inst
.base
.operands
[i
].sysins_op
=
7358 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7361 case AARCH64_OPND_SYSREG_AT
:
7362 inst
.base
.operands
[i
].sysins_op
=
7363 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7366 case AARCH64_OPND_SYSREG_SR
:
7367 inst
.base
.operands
[i
].sysins_op
=
7368 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7371 case AARCH64_OPND_SYSREG_TLBI
:
7372 inst
.base
.operands
[i
].sysins_op
=
7373 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7375 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7377 set_fatal_syntax_error ( _("unknown or missing operation name"));
7382 case AARCH64_OPND_BARRIER
:
7383 case AARCH64_OPND_BARRIER_ISB
:
7384 val
= parse_barrier (&str
);
7385 if (val
!= PARSE_FAIL
7386 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7388 /* ISB only accepts options name 'sy'. */
7390 (_("the specified option is not accepted in ISB"));
7391 /* Turn off backtrack as this optional operand is present. */
7395 if (val
!= PARSE_FAIL
7396 && operands
[i
] == AARCH64_OPND_BARRIER
)
7398 /* Regular barriers accept options CRm (C0-C15).
7399 DSB nXS barrier variant accepts values > 15. */
7400 if (val
< 0 || val
> 15)
7402 set_syntax_error (_("the specified option is not accepted in DSB"));
7406 /* This is an extension to accept a 0..15 immediate. */
7407 if (val
== PARSE_FAIL
)
7408 po_imm_or_fail (0, 15);
7409 info
->barrier
= aarch64_barrier_options
+ val
;
7412 case AARCH64_OPND_BARRIER_DSB_NXS
:
7413 val
= parse_barrier (&str
);
7414 if (val
!= PARSE_FAIL
)
7416 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7417 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7419 set_syntax_error (_("the specified option is not accepted in DSB"));
7420 /* Turn off backtrack as this optional operand is present. */
7427 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7428 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7429 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7431 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7433 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7437 /* Option index is encoded as 2-bit value in val<3:2>. */
7438 val
= (val
>> 2) - 4;
7439 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7442 case AARCH64_OPND_PRFOP
:
7443 val
= parse_pldop (&str
);
7444 /* This is an extension to accept a 0..31 immediate. */
7445 if (val
== PARSE_FAIL
)
7446 po_imm_or_fail (0, 31);
7447 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7450 case AARCH64_OPND_BARRIER_PSB
:
7451 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7452 if (val
== PARSE_FAIL
)
7456 case AARCH64_OPND_BTI_TARGET
:
7457 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7458 if (val
== PARSE_FAIL
)
7462 case AARCH64_OPND_SME_ZAda_2b
:
7463 case AARCH64_OPND_SME_ZAda_3b
:
7464 val
= parse_sme_zada_operand (&str
, &qualifier
);
7465 if (val
== PARSE_FAIL
)
7467 info
->reg
.regno
= val
;
7468 info
->qualifier
= qualifier
;
7471 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7472 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7473 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7475 enum sme_hv_slice slice_indicator
;
7476 int vector_select_register
;
7479 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
)
7480 val
= parse_sme_za_hv_tiles_operand_with_braces (&str
,
7482 &vector_select_register
,
7486 val
= parse_sme_za_hv_tiles_operand (&str
, &slice_indicator
,
7487 &vector_select_register
,
7490 if (val
== PARSE_FAIL
)
7492 info
->za_tile_vector
.regno
= val
;
7493 info
->za_tile_vector
.index
.regno
= vector_select_register
;
7494 info
->za_tile_vector
.index
.imm
= imm
;
7495 info
->za_tile_vector
.v
= slice_indicator
;
7496 info
->qualifier
= qualifier
;
7500 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7501 val
= parse_sme_list_of_64bit_tiles (&str
);
7502 if (val
== PARSE_FAIL
)
7504 info
->imm
.value
= val
;
7507 case AARCH64_OPND_SME_ZA_array
:
7510 val
= parse_sme_za_array (&str
, &imm
);
7511 if (val
== PARSE_FAIL
)
7513 info
->za_tile_vector
.index
.regno
= val
;
7514 info
->za_tile_vector
.index
.imm
= imm
;
7519 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7522 /* If we get here, this operand was successfully parsed. */
7523 inst
.base
.operands
[i
].present
= 1;
7527 /* The parse routine should already have set the error, but in case
7528 not, set a default one here. */
7530 set_default_error ();
7532 if (! backtrack_pos
)
7533 goto parse_operands_return
;
7536 /* We reach here because this operand is marked as optional, and
7537 either no operand was supplied or the operand was supplied but it
7538 was syntactically incorrect. In the latter case we report an
7539 error. In the former case we perform a few more checks before
7540 dropping through to the code to insert the default operand. */
7542 char *tmp
= backtrack_pos
;
7543 char endchar
= END_OF_INSN
;
7545 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7547 skip_past_char (&tmp
, ',');
7549 if (*tmp
!= endchar
)
7550 /* The user has supplied an operand in the wrong format. */
7551 goto parse_operands_return
;
7553 /* Make sure there is not a comma before the optional operand.
7554 For example the fifth operand of 'sys' is optional:
7556 sys #0,c0,c0,#0, <--- wrong
7557 sys #0,c0,c0,#0 <--- correct. */
7558 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7560 set_fatal_syntax_error
7561 (_("unexpected comma before the omitted optional operand"));
7562 goto parse_operands_return
;
7566 /* Reaching here means we are dealing with an optional operand that is
7567 omitted from the assembly line. */
7568 gas_assert (optional_operand_p (opcode
, i
));
7570 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7572 /* Try again, skipping the optional operand at backtrack_pos. */
7573 str
= backtrack_pos
;
7576 /* Clear any error record after the omitted optional operand has been
7577 successfully handled. */
7581 /* Check if we have parsed all the operands. */
7582 if (*str
!= '\0' && ! error_p ())
7584 /* Set I to the index of the last present operand; this is
7585 for the purpose of diagnostics. */
7586 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7588 set_fatal_syntax_error
7589 (_("unexpected characters following instruction"));
7592 parse_operands_return
:
7596 DEBUG_TRACE ("parsing FAIL: %s - %s",
7597 operand_mismatch_kind_names
[get_error_kind ()],
7598 get_error_message ());
7599 /* Record the operand error properly; this is useful when there
7600 are multiple instruction templates for a mnemonic name, so that
7601 later on, we can select the error that most closely describes
7603 record_operand_error (opcode
, i
, get_error_kind (),
7604 get_error_message ());
7609 DEBUG_TRACE ("parsing SUCCESS");
7614 /* It does some fix-up to provide some programmer friendly feature while
7615 keeping the libopcodes happy, i.e. libopcodes only accepts
7616 the preferred architectural syntax.
7617 Return FALSE if there is any failure; otherwise return TRUE. */
7620 programmer_friendly_fixup (aarch64_instruction
*instr
)
7622 aarch64_inst
*base
= &instr
->base
;
7623 const aarch64_opcode
*opcode
= base
->opcode
;
7624 enum aarch64_op op
= opcode
->op
;
7625 aarch64_opnd_info
*operands
= base
->operands
;
7627 DEBUG_TRACE ("enter");
7629 switch (opcode
->iclass
)
7632 /* TBNZ Xn|Wn, #uimm6, label
7633 Test and Branch Not Zero: conditionally jumps to label if bit number
7634 uimm6 in register Xn is not zero. The bit number implies the width of
7635 the register, which may be written and should be disassembled as Wn if
7636 uimm is less than 32. */
7637 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7639 if (operands
[1].imm
.value
>= 32)
7641 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7645 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7649 /* LDR Wt, label | =value
7650 As a convenience assemblers will typically permit the notation
7651 "=value" in conjunction with the pc-relative literal load instructions
7652 to automatically place an immediate value or symbolic address in a
7653 nearby literal pool and generate a hidden label which references it.
7654 ISREG has been set to 0 in the case of =value. */
7655 if (instr
->gen_lit_pool
7656 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7658 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7659 if (op
== OP_LDRSW_LIT
)
7661 if (instr
->reloc
.exp
.X_op
!= O_constant
7662 && instr
->reloc
.exp
.X_op
!= O_big
7663 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7665 record_operand_error (opcode
, 1,
7666 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7667 _("constant expression expected"));
7670 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7672 record_operand_error (opcode
, 1,
7673 AARCH64_OPDE_OTHER_ERROR
,
7674 _("literal pool insertion failed"));
7682 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7683 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7684 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7685 A programmer-friendly assembler should accept a destination Xd in
7686 place of Wd, however that is not the preferred form for disassembly.
7688 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7689 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7690 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7691 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7696 /* In the 64-bit form, the final register operand is written as Wm
7697 for all but the (possibly omitted) UXTX/LSL and SXTX
7699 As a programmer-friendly assembler, we accept e.g.
7700 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7701 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7702 int idx
= aarch64_operand_index (opcode
->operands
,
7703 AARCH64_OPND_Rm_EXT
);
7704 gas_assert (idx
== 1 || idx
== 2);
7705 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7706 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7707 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7708 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7709 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7710 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7718 DEBUG_TRACE ("exit with SUCCESS");
7722 /* Check for loads and stores that will cause unpredictable behavior. */
7725 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7727 aarch64_inst
*base
= &instr
->base
;
7728 const aarch64_opcode
*opcode
= base
->opcode
;
7729 const aarch64_opnd_info
*opnds
= base
->operands
;
7730 switch (opcode
->iclass
)
7737 /* Loading/storing the base register is unpredictable if writeback. */
7738 if ((aarch64_get_operand_class (opnds
[0].type
)
7739 == AARCH64_OPND_CLASS_INT_REG
)
7740 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7741 && opnds
[1].addr
.base_regno
!= REG_SP
7742 /* Exempt STG/STZG/ST2G/STZ2G. */
7743 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7744 && opnds
[1].addr
.writeback
)
7745 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7749 case ldstnapair_offs
:
7750 case ldstpair_indexed
:
7751 /* Loading/storing the base register is unpredictable if writeback. */
7752 if ((aarch64_get_operand_class (opnds
[0].type
)
7753 == AARCH64_OPND_CLASS_INT_REG
)
7754 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7755 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7756 && opnds
[2].addr
.base_regno
!= REG_SP
7758 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7759 && opnds
[2].addr
.writeback
)
7760 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7761 /* Load operations must load different registers. */
7762 if ((opcode
->opcode
& (1 << 22))
7763 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7764 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7768 if ((aarch64_get_operand_class (opnds
[0].type
)
7769 == AARCH64_OPND_CLASS_INT_REG
)
7770 && (aarch64_get_operand_class (opnds
[1].type
)
7771 == AARCH64_OPND_CLASS_INT_REG
))
7773 if ((opcode
->opcode
& (1 << 22)))
7775 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
7776 if ((opcode
->opcode
& (1 << 21))
7777 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7778 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7782 /* Store-Exclusive is unpredictable if Rt == Rs. */
7783 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7785 (_("unpredictable: identical transfer and status registers"
7788 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
7790 if (!(opcode
->opcode
& (1 << 21)))
7791 /* Store-Exclusive is unpredictable if Rn == Rs. */
7793 (_("unpredictable: identical base and status registers"
7796 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
7798 (_("unpredictable: "
7799 "identical transfer and status registers"
7803 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
7804 if ((opcode
->opcode
& (1 << 21))
7805 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
7806 && opnds
[3].reg
.regno
!= REG_SP
)
7807 as_warn (_("unpredictable: identical base and status registers"
7819 force_automatic_sequence_close (void)
7821 if (now_instr_sequence
.instr
)
7823 as_warn (_("previous `%s' sequence has not been closed"),
7824 now_instr_sequence
.instr
->opcode
->name
);
7825 init_insn_sequence (NULL
, &now_instr_sequence
);
7829 /* A wrapper function to interface with libopcodes on encoding and
7830 record the error message if there is any.
7832 Return TRUE on success; otherwise return FALSE. */
7835 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7838 aarch64_operand_error error_info
;
7839 memset (&error_info
, '\0', sizeof (error_info
));
7840 error_info
.kind
= AARCH64_OPDE_NIL
;
7841 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7842 && !error_info
.non_fatal
)
7845 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7846 record_operand_error_info (opcode
, &error_info
);
7847 return error_info
.non_fatal
;
7850 #ifdef DEBUG_AARCH64
7852 dump_opcode_operands (const aarch64_opcode
*opcode
)
7855 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7857 aarch64_verbose ("\t\t opnd%d: %s", i
,
7858 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7859 ? aarch64_get_operand_name (opcode
->operands
[i
])
7860 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7864 #endif /* DEBUG_AARCH64 */
7866 /* This is the guts of the machine-dependent assembler. STR points to a
7867 machine dependent instruction. This function is supposed to emit
7868 the frags/bytes it assembles to. */
7871 md_assemble (char *str
)
7874 templates
*template;
7875 const aarch64_opcode
*opcode
;
7876 aarch64_inst
*inst_base
;
7877 unsigned saved_cond
;
7879 /* Align the previous label if needed. */
7880 if (last_label_seen
!= NULL
)
7882 symbol_set_frag (last_label_seen
, frag_now
);
7883 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7884 S_SET_SEGMENT (last_label_seen
, now_seg
);
7887 /* Update the current insn_sequence from the segment. */
7888 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
7890 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7892 DEBUG_TRACE ("\n\n");
7893 DEBUG_TRACE ("==============================");
7894 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7896 template = opcode_lookup (&p
);
7899 /* It wasn't an instruction, but it might be a register alias of
7900 the form alias .req reg directive. */
7901 if (!create_register_alias (str
, p
))
7902 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7907 skip_whitespace (p
);
7910 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7911 get_mnemonic_name (str
), str
);
7915 init_operand_error_report ();
7917 /* Sections are assumed to start aligned. In executable section, there is no
7918 MAP_DATA symbol pending. So we only align the address during
7919 MAP_DATA --> MAP_INSN transition.
7920 For other sections, this is not guaranteed. */
7921 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7922 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7923 frag_align_code (2, 0);
7925 saved_cond
= inst
.cond
;
7926 reset_aarch64_instruction (&inst
);
7927 inst
.cond
= saved_cond
;
7929 /* Iterate through all opcode entries with the same mnemonic name. */
7932 opcode
= template->opcode
;
7934 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7935 #ifdef DEBUG_AARCH64
7937 dump_opcode_operands (opcode
);
7938 #endif /* DEBUG_AARCH64 */
7940 mapping_state (MAP_INSN
);
7942 inst_base
= &inst
.base
;
7943 inst_base
->opcode
= opcode
;
7945 /* Truly conditionally executed instructions, e.g. b.cond. */
7946 if (opcode
->flags
& F_COND
)
7948 gas_assert (inst
.cond
!= COND_ALWAYS
);
7949 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7950 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7952 else if (inst
.cond
!= COND_ALWAYS
)
7954 /* It shouldn't arrive here, where the assembly looks like a
7955 conditional instruction but the found opcode is unconditional. */
7960 if (parse_operands (p
, opcode
)
7961 && programmer_friendly_fixup (&inst
)
7962 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7964 /* Check that this instruction is supported for this CPU. */
7965 if (!opcode
->avariant
7966 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7968 as_bad (_("selected processor does not support `%s'"), str
);
7972 warn_unpredictable_ldst (&inst
, str
);
7974 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7975 || !inst
.reloc
.need_libopcodes_p
)
7979 /* If there is relocation generated for the instruction,
7980 store the instruction information for the future fix-up. */
7981 struct aarch64_inst
*copy
;
7982 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7983 copy
= XNEW (struct aarch64_inst
);
7984 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7988 /* Issue non-fatal messages if any. */
7989 output_operand_error_report (str
, true);
7993 template = template->next
;
7994 if (template != NULL
)
7996 reset_aarch64_instruction (&inst
);
7997 inst
.cond
= saved_cond
;
8000 while (template != NULL
);
8002 /* Issue the error messages if any. */
8003 output_operand_error_report (str
, false);
8006 /* Various frobbings of labels and their addresses. */
8009 aarch64_start_line_hook (void)
8011 last_label_seen
= NULL
;
8015 aarch64_frob_label (symbolS
* sym
)
8017 last_label_seen
= sym
;
8019 dwarf2_emit_label (sym
);
8023 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8025 /* Check to see if we have a block to close. */
8026 force_automatic_sequence_close ();
8030 aarch64_data_in_code (void)
8032 if (startswith (input_line_pointer
+ 1, "data:"))
8034 *input_line_pointer
= '/';
8035 input_line_pointer
+= 5;
8036 *input_line_pointer
= 0;
8044 aarch64_canonicalize_symbol_name (char *name
)
8048 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8049 *(name
+ len
- 5) = 0;
8054 /* Table of all register names defined by default. The user can
8055 define additional names with .req. Note that all register names
8056 should appear in both upper and lowercase variants. Some registers
8057 also have mixed-case names. */
8059 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8060 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8061 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8062 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8063 #define REGSET16(p,t) \
8064 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8065 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8066 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8067 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8068 #define REGSET16S(p,s,t) \
8069 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8070 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8071 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8072 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8073 #define REGSET31(p,t) \
8075 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8076 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8077 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8078 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8079 #define REGSET(p,t) \
8080 REGSET31(p,t), REGNUM(p,31,t)
8082 /* These go into aarch64_reg_hsh hash-table. */
8083 static const reg_entry reg_names
[] = {
8084 /* Integer registers. */
8085 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8086 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8088 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8089 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8090 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8091 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8092 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8093 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8095 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
8096 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
8098 /* Floating-point single precision registers. */
8099 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8101 /* Floating-point double precision registers. */
8102 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8104 /* Floating-point half precision registers. */
8105 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8107 /* Floating-point byte precision registers. */
8108 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8110 /* Floating-point quad precision registers. */
8111 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8113 /* FP/SIMD registers. */
8114 REGSET (v
, VN
), REGSET (V
, VN
),
8116 /* SVE vector registers. */
8117 REGSET (z
, ZN
), REGSET (Z
, ZN
),
8119 /* SVE predicate registers. */
8120 REGSET16 (p
, PN
), REGSET16 (P
, PN
),
8122 /* SME ZA tile registers. */
8123 REGSET16 (za
, ZA
), REGSET16 (ZA
, ZA
),
8125 /* SME ZA tile registers (horizontal slice). */
8126 REGSET16S (za
, h
, ZAH
), REGSET16S (ZA
, H
, ZAH
),
8128 /* SME ZA tile registers (vertical slice). */
8129 REGSET16S (za
, v
, ZAV
), REGSET16S (ZA
, V
, ZAV
)
8147 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8148 static const asm_nzcv nzcv_names
[] = {
8149 {"nzcv", B (n
, z
, c
, v
)},
8150 {"nzcV", B (n
, z
, c
, V
)},
8151 {"nzCv", B (n
, z
, C
, v
)},
8152 {"nzCV", B (n
, z
, C
, V
)},
8153 {"nZcv", B (n
, Z
, c
, v
)},
8154 {"nZcV", B (n
, Z
, c
, V
)},
8155 {"nZCv", B (n
, Z
, C
, v
)},
8156 {"nZCV", B (n
, Z
, C
, V
)},
8157 {"Nzcv", B (N
, z
, c
, v
)},
8158 {"NzcV", B (N
, z
, c
, V
)},
8159 {"NzCv", B (N
, z
, C
, v
)},
8160 {"NzCV", B (N
, z
, C
, V
)},
8161 {"NZcv", B (N
, Z
, c
, v
)},
8162 {"NZcV", B (N
, Z
, c
, V
)},
8163 {"NZCv", B (N
, Z
, C
, v
)},
8164 {"NZCV", B (N
, Z
, C
, V
)}
8177 /* MD interface: bits in the object file. */
8179 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8180 for use in the a.out file, and stores them in the array pointed to by buf.
8181 This knows about the endian-ness of the target machine and does
8182 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8183 2 (short) and 4 (long) Floating numbers are put out as a series of
8184 LITTLENUMS (shorts, here at least). */
8187 md_number_to_chars (char *buf
, valueT val
, int n
)
8189 if (target_big_endian
)
8190 number_to_chars_bigendian (buf
, val
, n
);
8192 number_to_chars_littleendian (buf
, val
, n
);
8195 /* MD interface: Sections. */
8197 /* Estimate the size of a frag before relaxing. Assume everything fits in
8201 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8207 /* Round up a section size to the appropriate boundary. */
8210 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8215 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8216 of an rs_align_code fragment.
8218 Here we fill the frag with the appropriate info for padding the
8219 output stream. The resulting frag will consist of a fixed (fr_fix)
8220 and of a repeating (fr_var) part.
8222 The fixed content is always emitted before the repeating content and
8223 these two parts are used as follows in constructing the output:
8224 - the fixed part will be used to align to a valid instruction word
8225 boundary, in case that we start at a misaligned address; as no
8226 executable instruction can live at the misaligned location, we
8227 simply fill with zeros;
8228 - the variable part will be used to cover the remaining padding and
8229 we fill using the AArch64 NOP instruction.
8231 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8232 enough storage space for up to 3 bytes for padding the back to a valid
8233 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8236 aarch64_handle_align (fragS
* fragP
)
8238 /* NOP = d503201f */
8239 /* AArch64 instructions are always little-endian. */
8240 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8242 int bytes
, fix
, noop_size
;
8245 if (fragP
->fr_type
!= rs_align_code
)
8248 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8249 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8252 gas_assert (fragP
->tc_frag_data
.recorded
);
8255 noop_size
= sizeof (aarch64_noop
);
8257 fix
= bytes
& (noop_size
- 1);
8261 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8265 fragP
->fr_fix
+= fix
;
8269 memcpy (p
, aarch64_noop
, noop_size
);
8270 fragP
->fr_var
= noop_size
;
8273 /* Perform target specific initialisation of a frag.
8274 Note - despite the name this initialisation is not done when the frag
8275 is created, but only when its type is assigned. A frag can be created
8276 and used a long time before its type is set, so beware of assuming that
8277 this initialisation is performed first. */
8281 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8282 int max_chars ATTRIBUTE_UNUSED
)
8286 #else /* OBJ_ELF is defined. */
8288 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8290 /* Record a mapping symbol for alignment frags. We will delete this
8291 later if the alignment ends up empty. */
8292 if (!fragP
->tc_frag_data
.recorded
)
8293 fragP
->tc_frag_data
.recorded
= 1;
8295 /* PR 21809: Do not set a mapping state for debug sections
8296 - it just confuses other tools. */
8297 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8300 switch (fragP
->fr_type
)
8304 mapping_state_2 (MAP_DATA
, max_chars
);
8307 /* PR 20364: We can get alignment frags in code sections,
8308 so do not just assume that we should use the MAP_DATA state. */
8309 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8312 mapping_state_2 (MAP_INSN
, max_chars
);
8319 /* Initialize the DWARF-2 unwind information for this procedure. */
8322 tc_aarch64_frame_initial_instructions (void)
8324 cfi_add_CFA_def_cfa (REG_SP
, 0);
8326 #endif /* OBJ_ELF */
8328 /* Convert REGNAME to a DWARF-2 register number. */
8331 tc_aarch64_regname_to_dw2regnum (char *regname
)
8333 const reg_entry
*reg
= parse_reg (®name
);
8339 case REG_TYPE_SP_32
:
8340 case REG_TYPE_SP_64
:
8350 return reg
->number
+ 64;
8358 /* Implement DWARF2_ADDR_SIZE. */
8361 aarch64_dwarf2_addr_size (void)
8363 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8367 return bfd_arch_bits_per_address (stdoutput
) / 8;
8370 /* MD interface: Symbol and relocation handling. */
8372 /* Return the address within the segment that a PC-relative fixup is
8373 relative to. For AArch64 PC-relative fixups applied to instructions
8374 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8377 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8379 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8381 /* If this is pc-relative and we are going to emit a relocation
8382 then we just want to put out any pipeline compensation that the linker
8383 will need. Otherwise we want to use the calculated base. */
8385 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8386 || aarch64_force_relocation (fixP
)))
8389 /* AArch64 should be consistent for all pc-relative relocations. */
8390 return base
+ AARCH64_PCREL_OFFSET
;
8393 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8394 Otherwise we have no need to default values of symbols. */
8397 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8400 if (name
[0] == '_' && name
[1] == 'G'
8401 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8405 if (symbol_find (name
))
8406 as_bad (_("GOT already in the symbol table"));
8408 GOT_symbol
= symbol_new (name
, undefined_section
,
8409 &zero_address_frag
, 0);
8419 /* Return non-zero if the indicated VALUE has overflowed the maximum
8420 range expressible by a unsigned number with the indicated number of
8424 unsigned_overflow (valueT value
, unsigned bits
)
8427 if (bits
>= sizeof (valueT
) * 8)
8429 lim
= (valueT
) 1 << bits
;
8430 return (value
>= lim
);
8434 /* Return non-zero if the indicated VALUE has overflowed the maximum
8435 range expressible by an signed number with the indicated number of
8439 signed_overflow (offsetT value
, unsigned bits
)
8442 if (bits
>= sizeof (offsetT
) * 8)
8444 lim
= (offsetT
) 1 << (bits
- 1);
8445 return (value
< -lim
|| value
>= lim
);
8448 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8449 unsigned immediate offset load/store instruction, try to encode it as
8450 an unscaled, 9-bit, signed immediate offset load/store instruction.
8451 Return TRUE if it is successful; otherwise return FALSE.
8453 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8454 in response to the standard LDR/STR mnemonics when the immediate offset is
8455 unambiguous, i.e. when it is negative or unaligned. */
8458 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8461 enum aarch64_op new_op
;
8462 const aarch64_opcode
*new_opcode
;
8464 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8466 switch (instr
->opcode
->op
)
8468 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8469 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8470 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8471 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8472 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8473 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8474 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8475 case OP_STR_POS
: new_op
= OP_STUR
; break;
8476 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8477 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8478 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8479 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8480 default: new_op
= OP_NIL
; break;
8483 if (new_op
== OP_NIL
)
8486 new_opcode
= aarch64_get_opcode (new_op
);
8487 gas_assert (new_opcode
!= NULL
);
8489 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8490 instr
->opcode
->op
, new_opcode
->op
);
8492 aarch64_replace_opcode (instr
, new_opcode
);
8494 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8495 qualifier matching may fail because the out-of-date qualifier will
8496 prevent the operand being updated with a new and correct qualifier. */
8497 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8498 AARCH64_OPND_ADDR_SIMM9
);
8499 gas_assert (idx
== 1);
8500 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8502 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8504 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8511 /* Called by fix_insn to fix a MOV immediate alias instruction.
8513 Operand for a generic move immediate instruction, which is an alias
8514 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8515 a 32-bit/64-bit immediate value into general register. An assembler error
8516 shall result if the immediate cannot be created by a single one of these
8517 instructions. If there is a choice, then to ensure reversability an
8518 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8521 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8523 const aarch64_opcode
*opcode
;
8525 /* Need to check if the destination is SP/ZR. The check has to be done
8526 before any aarch64_replace_opcode. */
8527 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8528 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8530 instr
->operands
[1].imm
.value
= value
;
8531 instr
->operands
[1].skip
= 0;
8535 /* Try the MOVZ alias. */
8536 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8537 aarch64_replace_opcode (instr
, opcode
);
8538 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8539 &instr
->value
, NULL
, NULL
, insn_sequence
))
8541 put_aarch64_insn (buf
, instr
->value
);
8544 /* Try the MOVK alias. */
8545 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8546 aarch64_replace_opcode (instr
, opcode
);
8547 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8548 &instr
->value
, NULL
, NULL
, insn_sequence
))
8550 put_aarch64_insn (buf
, instr
->value
);
8555 if (try_mov_bitmask_p
)
8557 /* Try the ORR alias. */
8558 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8559 aarch64_replace_opcode (instr
, opcode
);
8560 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8561 &instr
->value
, NULL
, NULL
, insn_sequence
))
8563 put_aarch64_insn (buf
, instr
->value
);
8568 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8569 _("immediate cannot be moved by a single instruction"));
8572 /* An instruction operand which is immediate related may have symbol used
8573 in the assembly, e.g.
8576 .set u32, 0x00ffff00
8578 At the time when the assembly instruction is parsed, a referenced symbol,
8579 like 'u32' in the above example may not have been seen; a fixS is created
8580 in such a case and is handled here after symbols have been resolved.
8581 Instruction is fixed up with VALUE using the information in *FIXP plus
8582 extra information in FLAGS.
8584 This function is called by md_apply_fix to fix up instructions that need
8585 a fix-up described above but does not involve any linker-time relocation. */
8588 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8592 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8593 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8594 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8598 /* Now the instruction is about to be fixed-up, so the operand that
8599 was previously marked as 'ignored' needs to be unmarked in order
8600 to get the encoding done properly. */
8601 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8602 new_inst
->operands
[idx
].skip
= 0;
8605 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8609 case AARCH64_OPND_EXCEPTION
:
8610 case AARCH64_OPND_UNDEFINED
:
8611 if (unsigned_overflow (value
, 16))
8612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8613 _("immediate out of range"));
8614 insn
= get_aarch64_insn (buf
);
8615 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8616 put_aarch64_insn (buf
, insn
);
8619 case AARCH64_OPND_AIMM
:
8620 /* ADD or SUB with immediate.
8621 NOTE this assumes we come here with a add/sub shifted reg encoding
8622 3 322|2222|2 2 2 21111 111111
8623 1 098|7654|3 2 1 09876 543210 98765 43210
8624 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8625 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8626 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8627 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8629 3 322|2222|2 2 221111111111
8630 1 098|7654|3 2 109876543210 98765 43210
8631 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8632 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8633 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8634 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8635 Fields sf Rn Rd are already set. */
8636 insn
= get_aarch64_insn (buf
);
8640 insn
= reencode_addsub_switch_add_sub (insn
);
8644 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8645 && unsigned_overflow (value
, 12))
8647 /* Try to shift the value by 12 to make it fit. */
8648 if (((value
>> 12) << 12) == value
8649 && ! unsigned_overflow (value
, 12 + 12))
8652 insn
|= encode_addsub_imm_shift_amount (1);
8656 if (unsigned_overflow (value
, 12))
8657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8658 _("immediate out of range"));
8660 insn
|= encode_addsub_imm (value
);
8662 put_aarch64_insn (buf
, insn
);
8665 case AARCH64_OPND_SIMD_IMM
:
8666 case AARCH64_OPND_SIMD_IMM_SFT
:
8667 case AARCH64_OPND_LIMM
:
8668 /* Bit mask immediate. */
8669 gas_assert (new_inst
!= NULL
);
8670 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8671 new_inst
->operands
[idx
].imm
.value
= value
;
8672 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8673 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8674 put_aarch64_insn (buf
, new_inst
->value
);
8676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8677 _("invalid immediate"));
8680 case AARCH64_OPND_HALF
:
8681 /* 16-bit unsigned immediate. */
8682 if (unsigned_overflow (value
, 16))
8683 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8684 _("immediate out of range"));
8685 insn
= get_aarch64_insn (buf
);
8686 insn
|= encode_movw_imm (value
& 0xffff);
8687 put_aarch64_insn (buf
, insn
);
8690 case AARCH64_OPND_IMM_MOV
:
8691 /* Operand for a generic move immediate instruction, which is
8692 an alias instruction that generates a single MOVZ, MOVN or ORR
8693 instruction to loads a 32-bit/64-bit immediate value into general
8694 register. An assembler error shall result if the immediate cannot be
8695 created by a single one of these instructions. If there is a choice,
8696 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8697 and MOVZ or MOVN to ORR. */
8698 gas_assert (new_inst
!= NULL
);
8699 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8702 case AARCH64_OPND_ADDR_SIMM7
:
8703 case AARCH64_OPND_ADDR_SIMM9
:
8704 case AARCH64_OPND_ADDR_SIMM9_2
:
8705 case AARCH64_OPND_ADDR_SIMM10
:
8706 case AARCH64_OPND_ADDR_UIMM12
:
8707 case AARCH64_OPND_ADDR_SIMM11
:
8708 case AARCH64_OPND_ADDR_SIMM13
:
8709 /* Immediate offset in an address. */
8710 insn
= get_aarch64_insn (buf
);
8712 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8713 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8714 || new_inst
->opcode
->operands
[2] == opnd
);
8716 /* Get the index of the address operand. */
8717 if (new_inst
->opcode
->operands
[1] == opnd
)
8718 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8721 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8724 /* Update the resolved offset value. */
8725 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8727 /* Encode/fix-up. */
8728 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8729 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8731 put_aarch64_insn (buf
, new_inst
->value
);
8734 else if (new_inst
->opcode
->iclass
== ldst_pos
8735 && try_to_encode_as_unscaled_ldst (new_inst
))
8737 put_aarch64_insn (buf
, new_inst
->value
);
8741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8742 _("immediate offset out of range"));
8747 as_fatal (_("unhandled operand code %d"), opnd
);
8751 /* Apply a fixup (fixP) to segment data, once it has been determined
8752 by our caller that we have all the info we need to fix it up.
8754 Parameter valP is the pointer to the value of the bits. */
8757 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8759 offsetT value
= *valP
;
8761 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8763 unsigned flags
= fixP
->fx_addnumber
;
8765 DEBUG_TRACE ("\n\n");
8766 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8767 DEBUG_TRACE ("Enter md_apply_fix");
8769 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8771 /* Note whether this will delete the relocation. */
8773 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
8776 /* Process the relocations. */
8777 switch (fixP
->fx_r_type
)
8779 case BFD_RELOC_NONE
:
8780 /* This will need to go in the object file. */
8785 case BFD_RELOC_8_PCREL
:
8786 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8787 md_number_to_chars (buf
, value
, 1);
8791 case BFD_RELOC_16_PCREL
:
8792 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8793 md_number_to_chars (buf
, value
, 2);
8797 case BFD_RELOC_32_PCREL
:
8798 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8799 md_number_to_chars (buf
, value
, 4);
8803 case BFD_RELOC_64_PCREL
:
8804 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8805 md_number_to_chars (buf
, value
, 8);
8808 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8809 /* We claim that these fixups have been processed here, even if
8810 in fact we generate an error because we do not have a reloc
8811 for them, so tc_gen_reloc() will reject them. */
8813 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8816 _("undefined symbol %s used as an immediate value"),
8817 S_GET_NAME (fixP
->fx_addsy
));
8818 goto apply_fix_return
;
8820 fix_insn (fixP
, flags
, value
);
8823 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8824 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8828 _("pc-relative load offset not word aligned"));
8829 if (signed_overflow (value
, 21))
8830 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8831 _("pc-relative load offset out of range"));
8832 insn
= get_aarch64_insn (buf
);
8833 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8834 put_aarch64_insn (buf
, insn
);
8838 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8839 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8841 if (signed_overflow (value
, 21))
8842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8843 _("pc-relative address offset out of range"));
8844 insn
= get_aarch64_insn (buf
);
8845 insn
|= encode_adr_imm (value
);
8846 put_aarch64_insn (buf
, insn
);
8850 case BFD_RELOC_AARCH64_BRANCH19
:
8851 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8854 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8855 _("conditional branch target not word aligned"));
8856 if (signed_overflow (value
, 21))
8857 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8858 _("conditional branch out of range"));
8859 insn
= get_aarch64_insn (buf
);
8860 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8861 put_aarch64_insn (buf
, insn
);
8865 case BFD_RELOC_AARCH64_TSTBR14
:
8866 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8869 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8870 _("conditional branch target not word aligned"));
8871 if (signed_overflow (value
, 16))
8872 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8873 _("conditional branch out of range"));
8874 insn
= get_aarch64_insn (buf
);
8875 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8876 put_aarch64_insn (buf
, insn
);
8880 case BFD_RELOC_AARCH64_CALL26
:
8881 case BFD_RELOC_AARCH64_JUMP26
:
8882 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8886 _("branch target not word aligned"));
8887 if (signed_overflow (value
, 28))
8888 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8889 _("branch out of range"));
8890 insn
= get_aarch64_insn (buf
);
8891 insn
|= encode_branch_ofs_26 (value
>> 2);
8892 put_aarch64_insn (buf
, insn
);
8896 case BFD_RELOC_AARCH64_MOVW_G0
:
8897 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8898 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8899 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8900 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8901 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8904 case BFD_RELOC_AARCH64_MOVW_G1
:
8905 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8906 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8907 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8908 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8909 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8912 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8914 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8915 /* Should always be exported to object file, see
8916 aarch64_force_relocation(). */
8917 gas_assert (!fixP
->fx_done
);
8918 gas_assert (seg
->use_rela_p
);
8920 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8922 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8923 /* Should always be exported to object file, see
8924 aarch64_force_relocation(). */
8925 gas_assert (!fixP
->fx_done
);
8926 gas_assert (seg
->use_rela_p
);
8928 case BFD_RELOC_AARCH64_MOVW_G2
:
8929 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8930 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8931 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8932 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8935 case BFD_RELOC_AARCH64_MOVW_G3
:
8936 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8939 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8941 insn
= get_aarch64_insn (buf
);
8945 /* REL signed addend must fit in 16 bits */
8946 if (signed_overflow (value
, 16))
8947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8948 _("offset out of range"));
8952 /* Check for overflow and scale. */
8953 switch (fixP
->fx_r_type
)
8955 case BFD_RELOC_AARCH64_MOVW_G0
:
8956 case BFD_RELOC_AARCH64_MOVW_G1
:
8957 case BFD_RELOC_AARCH64_MOVW_G2
:
8958 case BFD_RELOC_AARCH64_MOVW_G3
:
8959 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8960 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8961 if (unsigned_overflow (value
, scale
+ 16))
8962 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8963 _("unsigned value out of range"));
8965 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8966 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8967 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8968 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8969 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8970 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8971 /* NOTE: We can only come here with movz or movn. */
8972 if (signed_overflow (value
, scale
+ 16))
8973 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8974 _("signed value out of range"));
8977 /* Force use of MOVN. */
8979 insn
= reencode_movzn_to_movn (insn
);
8983 /* Force use of MOVZ. */
8984 insn
= reencode_movzn_to_movz (insn
);
8988 /* Unchecked relocations. */
8994 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8995 insn
|= encode_movw_imm (value
& 0xffff);
8997 put_aarch64_insn (buf
, insn
);
9001 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9002 fixP
->fx_r_type
= (ilp32_p
9003 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9004 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9005 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9006 /* Should always be exported to object file, see
9007 aarch64_force_relocation(). */
9008 gas_assert (!fixP
->fx_done
);
9009 gas_assert (seg
->use_rela_p
);
9012 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9013 fixP
->fx_r_type
= (ilp32_p
9014 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9015 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9016 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9017 /* Should always be exported to object file, see
9018 aarch64_force_relocation(). */
9019 gas_assert (!fixP
->fx_done
);
9020 gas_assert (seg
->use_rela_p
);
9023 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9024 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9025 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9026 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9027 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9028 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9029 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9030 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9031 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9032 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9033 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9034 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9035 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9036 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9037 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9038 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9039 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9040 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9041 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9042 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9043 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9044 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9045 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9046 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9047 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9048 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9049 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9050 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9051 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9052 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9053 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9054 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9055 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9056 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9057 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9058 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9059 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9060 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9061 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9062 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9063 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9064 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9065 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9066 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9067 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9068 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9069 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9070 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9071 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9072 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9073 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9074 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9075 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9076 /* Should always be exported to object file, see
9077 aarch64_force_relocation(). */
9078 gas_assert (!fixP
->fx_done
);
9079 gas_assert (seg
->use_rela_p
);
9082 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9083 /* Should always be exported to object file, see
9084 aarch64_force_relocation(). */
9085 fixP
->fx_r_type
= (ilp32_p
9086 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9087 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9088 gas_assert (!fixP
->fx_done
);
9089 gas_assert (seg
->use_rela_p
);
9092 case BFD_RELOC_AARCH64_ADD_LO12
:
9093 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9094 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9095 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9096 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9097 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9098 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9099 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9100 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9101 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9102 case BFD_RELOC_AARCH64_LDST128_LO12
:
9103 case BFD_RELOC_AARCH64_LDST16_LO12
:
9104 case BFD_RELOC_AARCH64_LDST32_LO12
:
9105 case BFD_RELOC_AARCH64_LDST64_LO12
:
9106 case BFD_RELOC_AARCH64_LDST8_LO12
:
9107 /* Should always be exported to object file, see
9108 aarch64_force_relocation(). */
9109 gas_assert (!fixP
->fx_done
);
9110 gas_assert (seg
->use_rela_p
);
9113 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9114 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9115 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9118 case BFD_RELOC_UNUSED
:
9119 /* An error will already have been reported. */
9123 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9124 _("unexpected %s fixup"),
9125 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9130 /* Free the allocated the struct aarch64_inst.
9131 N.B. currently there are very limited number of fix-up types actually use
9132 this field, so the impact on the performance should be minimal . */
9133 free (fixP
->tc_fix_data
.inst
);
9138 /* Translate internal representation of relocation info to BFD target
9142 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9145 bfd_reloc_code_real_type code
;
9147 reloc
= XNEW (arelent
);
9149 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9150 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9151 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9155 if (section
->use_rela_p
)
9156 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9158 fixp
->fx_offset
= reloc
->address
;
9160 reloc
->addend
= fixp
->fx_offset
;
9162 code
= fixp
->fx_r_type
;
9167 code
= BFD_RELOC_16_PCREL
;
9172 code
= BFD_RELOC_32_PCREL
;
9177 code
= BFD_RELOC_64_PCREL
;
9184 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9185 if (reloc
->howto
== NULL
)
9187 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9189 ("cannot represent %s relocation in this object file format"),
9190 bfd_get_reloc_code_name (code
));
9197 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9200 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9202 bfd_reloc_code_real_type type
;
9206 FIXME: @@ Should look at CPU word size. */
9213 type
= BFD_RELOC_16
;
9216 type
= BFD_RELOC_32
;
9219 type
= BFD_RELOC_64
;
9222 as_bad (_("cannot do %u-byte relocation"), size
);
9223 type
= BFD_RELOC_UNUSED
;
9227 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9232 /* Implement md_after_parse_args. This is the earliest time we need to decide
9233 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9236 aarch64_after_parse_args (void)
9238 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9241 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9242 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9243 aarch64_abi
= AARCH64_ABI_ILP32
;
9245 aarch64_abi
= AARCH64_ABI_LP64
;
9249 elf64_aarch64_target_format (void)
9252 /* FIXME: What to do for ilp32_p ? */
9253 if (target_big_endian
)
9254 return "elf64-bigaarch64-cloudabi";
9256 return "elf64-littleaarch64-cloudabi";
9258 if (target_big_endian
)
9259 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9261 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9266 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9268 elf_frob_symbol (symp
, puntp
);
9272 /* MD interface: Finalization. */
9274 /* A good place to do this, although this was probably not intended
9275 for this kind of use. We need to dump the literal pool before
9276 references are made to a null symbol pointer. */
9279 aarch64_cleanup (void)
9283 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9285 /* Put it at the end of the relevant section. */
9286 subseg_set (pool
->section
, pool
->sub_section
);
9292 /* Remove any excess mapping symbols generated for alignment frags in
9293 SEC. We may have created a mapping symbol before a zero byte
9294 alignment; remove it if there's a mapping symbol after the
9297 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9298 void *dummy ATTRIBUTE_UNUSED
)
9300 segment_info_type
*seginfo
= seg_info (sec
);
9303 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9306 for (fragp
= seginfo
->frchainP
->frch_root
;
9307 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9309 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9310 fragS
*next
= fragp
->fr_next
;
9312 /* Variable-sized frags have been converted to fixed size by
9313 this point. But if this was variable-sized to start with,
9314 there will be a fixed-size frag after it. So don't handle
9316 if (sym
== NULL
|| next
== NULL
)
9319 if (S_GET_VALUE (sym
) < next
->fr_address
)
9320 /* Not at the end of this frag. */
9322 know (S_GET_VALUE (sym
) == next
->fr_address
);
9326 if (next
->tc_frag_data
.first_map
!= NULL
)
9328 /* Next frag starts with a mapping symbol. Discard this
9330 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9334 if (next
->fr_next
== NULL
)
9336 /* This mapping symbol is at the end of the section. Discard
9338 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9339 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9343 /* As long as we have empty frags without any mapping symbols,
9345 /* If the next frag is non-empty and does not start with a
9346 mapping symbol, then this mapping symbol is required. */
9347 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9350 next
= next
->fr_next
;
9352 while (next
!= NULL
);
9357 /* Adjust the symbol table. */
9360 aarch64_adjust_symtab (void)
9363 /* Remove any overlapping mapping symbols generated by alignment frags. */
9364 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9365 /* Now do generic ELF adjustments. */
9366 elf_adjust_symtab ();
9371 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9373 str_hash_insert (table
, key
, value
, 0);
9377 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9379 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9380 checked_hash_insert (table
, key
, value
);
9384 fill_instruction_hash_table (void)
9386 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9388 while (opcode
->name
!= NULL
)
9390 templates
*templ
, *new_templ
;
9391 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9393 new_templ
= XNEW (templates
);
9394 new_templ
->opcode
= opcode
;
9395 new_templ
->next
= NULL
;
9398 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9401 new_templ
->next
= templ
->next
;
9402 templ
->next
= new_templ
;
9409 convert_to_upper (char *dst
, const char *src
, size_t num
)
9412 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9413 *dst
= TOUPPER (*src
);
9417 /* Assume STR point to a lower-case string, allocate, convert and return
9418 the corresponding upper-case string. */
9419 static inline const char*
9420 get_upper_str (const char *str
)
9423 size_t len
= strlen (str
);
9424 ret
= XNEWVEC (char, len
+ 1);
9425 convert_to_upper (ret
, str
, len
);
9429 /* MD interface: Initialization. */
9437 aarch64_ops_hsh
= str_htab_create ();
9438 aarch64_cond_hsh
= str_htab_create ();
9439 aarch64_shift_hsh
= str_htab_create ();
9440 aarch64_sys_regs_hsh
= str_htab_create ();
9441 aarch64_pstatefield_hsh
= str_htab_create ();
9442 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9443 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9444 aarch64_sys_regs_at_hsh
= str_htab_create ();
9445 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9446 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9447 aarch64_reg_hsh
= str_htab_create ();
9448 aarch64_barrier_opt_hsh
= str_htab_create ();
9449 aarch64_nzcv_hsh
= str_htab_create ();
9450 aarch64_pldop_hsh
= str_htab_create ();
9451 aarch64_hint_opt_hsh
= str_htab_create ();
9453 fill_instruction_hash_table ();
9455 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9456 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9457 (void *) (aarch64_sys_regs
+ i
));
9459 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9460 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9461 aarch64_pstatefields
[i
].name
,
9462 (void *) (aarch64_pstatefields
+ i
));
9464 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9465 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9466 aarch64_sys_regs_ic
[i
].name
,
9467 (void *) (aarch64_sys_regs_ic
+ i
));
9469 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9470 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9471 aarch64_sys_regs_dc
[i
].name
,
9472 (void *) (aarch64_sys_regs_dc
+ i
));
9474 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9475 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9476 aarch64_sys_regs_at
[i
].name
,
9477 (void *) (aarch64_sys_regs_at
+ i
));
9479 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9480 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9481 aarch64_sys_regs_tlbi
[i
].name
,
9482 (void *) (aarch64_sys_regs_tlbi
+ i
));
9484 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9485 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9486 aarch64_sys_regs_sr
[i
].name
,
9487 (void *) (aarch64_sys_regs_sr
+ i
));
9489 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9490 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9491 (void *) (reg_names
+ i
));
9493 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9494 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9495 (void *) (nzcv_names
+ i
));
9497 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9499 const char *name
= aarch64_operand_modifiers
[i
].name
;
9500 checked_hash_insert (aarch64_shift_hsh
, name
,
9501 (void *) (aarch64_operand_modifiers
+ i
));
9502 /* Also hash the name in the upper case. */
9503 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9504 (void *) (aarch64_operand_modifiers
+ i
));
9507 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9510 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9511 the same condition code. */
9512 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9514 const char *name
= aarch64_conds
[i
].names
[j
];
9517 checked_hash_insert (aarch64_cond_hsh
, name
,
9518 (void *) (aarch64_conds
+ i
));
9519 /* Also hash the name in the upper case. */
9520 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9521 (void *) (aarch64_conds
+ i
));
9525 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9527 const char *name
= aarch64_barrier_options
[i
].name
;
9528 /* Skip xx00 - the unallocated values of option. */
9531 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9532 (void *) (aarch64_barrier_options
+ i
));
9533 /* Also hash the name in the upper case. */
9534 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9535 (void *) (aarch64_barrier_options
+ i
));
9538 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
9540 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
9541 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9542 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9543 /* Also hash the name in the upper case. */
9544 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9545 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9548 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9550 const char* name
= aarch64_prfops
[i
].name
;
9551 /* Skip the unallocated hint encodings. */
9554 checked_hash_insert (aarch64_pldop_hsh
, name
,
9555 (void *) (aarch64_prfops
+ i
));
9556 /* Also hash the name in the upper case. */
9557 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9558 (void *) (aarch64_prfops
+ i
));
9561 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9563 const char* name
= aarch64_hint_options
[i
].name
;
9564 const char* upper_name
= get_upper_str(name
);
9566 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9567 (void *) (aarch64_hint_options
+ i
));
9569 /* Also hash the name in the upper case if not the same. */
9570 if (strcmp (name
, upper_name
) != 0)
9571 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9572 (void *) (aarch64_hint_options
+ i
));
9575 /* Set the cpu variant based on the command-line options. */
9577 mcpu_cpu_opt
= march_cpu_opt
;
9580 mcpu_cpu_opt
= &cpu_default
;
9582 cpu_variant
= *mcpu_cpu_opt
;
9584 /* Record the CPU type. */
9585 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
9587 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9590 /* Command line processing. */
9592 const char *md_shortopts
= "m:";
9594 #ifdef AARCH64_BI_ENDIAN
9595 #define OPTION_EB (OPTION_MD_BASE + 0)
9596 #define OPTION_EL (OPTION_MD_BASE + 1)
9598 #if TARGET_BYTES_BIG_ENDIAN
9599 #define OPTION_EB (OPTION_MD_BASE + 0)
9601 #define OPTION_EL (OPTION_MD_BASE + 1)
9605 struct option md_longopts
[] = {
9607 {"EB", no_argument
, NULL
, OPTION_EB
},
9610 {"EL", no_argument
, NULL
, OPTION_EL
},
9612 {NULL
, no_argument
, NULL
, 0}
9615 size_t md_longopts_size
= sizeof (md_longopts
);
9617 struct aarch64_option_table
9619 const char *option
; /* Option name to match. */
9620 const char *help
; /* Help information. */
9621 int *var
; /* Variable to change. */
9622 int value
; /* What to change it to. */
9623 char *deprecated
; /* If non-null, print this message. */
9626 static struct aarch64_option_table aarch64_opts
[] = {
9627 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9628 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9630 #ifdef DEBUG_AARCH64
9631 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9632 #endif /* DEBUG_AARCH64 */
9633 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9635 {"mno-verbose-error", N_("do not output verbose error messages"),
9636 &verbose_error_p
, 0, NULL
},
9637 {NULL
, NULL
, NULL
, 0, NULL
}
9640 struct aarch64_cpu_option_table
9643 const aarch64_feature_set value
;
9644 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9646 const char *canonical_name
;
9649 /* This list should, at a minimum, contain all the cpu names
9650 recognized by GCC. */
9651 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9652 {"all", AARCH64_ANY
, NULL
},
9653 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9654 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9655 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9656 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9657 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9658 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9659 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9660 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9661 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9662 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9663 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9664 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9665 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9666 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9668 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9669 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9671 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9672 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9674 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9675 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9676 | AARCH64_FEATURE_DOTPROD
9677 | AARCH64_FEATURE_SSBS
),
9679 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9680 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9681 | AARCH64_FEATURE_DOTPROD
9682 | AARCH64_FEATURE_SSBS
),
9684 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9685 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9686 | AARCH64_FEATURE_DOTPROD
9687 | AARCH64_FEATURE_SSBS
),
9689 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9690 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9691 | AARCH64_FEATURE_DOTPROD
9692 | AARCH64_FEATURE_SSBS
),
9694 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9696 | AARCH64_FEATURE_RCPC
9697 | AARCH64_FEATURE_DOTPROD
9698 | AARCH64_FEATURE_SSBS
9699 | AARCH64_FEATURE_PROFILE
),
9701 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9703 | AARCH64_FEATURE_RCPC
9704 | AARCH64_FEATURE_DOTPROD
9705 | AARCH64_FEATURE_SSBS
9706 | AARCH64_FEATURE_PROFILE
),
9708 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9709 AARCH64_FEATURE_DOTPROD
9710 | AARCH64_FEATURE_F16
9711 | AARCH64_FEATURE_FLAGM
9712 | AARCH64_FEATURE_PAC
9713 | AARCH64_FEATURE_PROFILE
9714 | AARCH64_FEATURE_RCPC
9715 | AARCH64_FEATURE_SSBS
),
9717 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9718 AARCH64_FEATURE_BFLOAT16
9719 | AARCH64_FEATURE_I8MM
9720 | AARCH64_FEATURE_MEMTAG
9721 | AARCH64_FEATURE_SVE2_BITPERM
),
9723 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9724 AARCH64_FEATURE_BFLOAT16
9725 | AARCH64_FEATURE_I8MM
9726 | AARCH64_FEATURE_MEMTAG
9727 | AARCH64_FEATURE_SVE2_BITPERM
),
9729 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9730 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9731 | AARCH64_FEATURE_DOTPROD
9732 | AARCH64_FEATURE_PROFILE
),
9734 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9735 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9736 "Samsung Exynos M1"},
9737 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9738 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9739 | AARCH64_FEATURE_RDMA
),
9741 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9742 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9743 | AARCH64_FEATURE_DOTPROD
9744 | AARCH64_FEATURE_SSBS
),
9746 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9747 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9748 | AARCH64_FEATURE_DOTPROD
9749 | AARCH64_FEATURE_PROFILE
),
9751 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9752 AARCH64_FEATURE_BFLOAT16
9753 | AARCH64_FEATURE_I8MM
9754 | AARCH64_FEATURE_F16
9755 | AARCH64_FEATURE_SVE
9756 | AARCH64_FEATURE_SVE2
9757 | AARCH64_FEATURE_SVE2_BITPERM
9758 | AARCH64_FEATURE_MEMTAG
9759 | AARCH64_FEATURE_RNG
),
9761 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9762 AARCH64_FEATURE_PROFILE
9763 | AARCH64_FEATURE_CVADP
9764 | AARCH64_FEATURE_SVE
9765 | AARCH64_FEATURE_SSBS
9766 | AARCH64_FEATURE_RNG
9767 | AARCH64_FEATURE_F16
9768 | AARCH64_FEATURE_BFLOAT16
9769 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9770 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9771 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9772 | AARCH64_FEATURE_RDMA
),
9773 "Qualcomm QDF24XX"},
9774 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9775 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9776 "Qualcomm Saphira"},
9777 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9778 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9780 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9781 AARCH64_FEATURE_CRYPTO
),
9783 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9784 in earlier releases and is superseded by 'xgene1' in all
9786 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9787 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9788 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9789 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9790 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9791 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9793 | AARCH64_FEATURE_RCPC
9794 | AARCH64_FEATURE_DOTPROD
9795 | AARCH64_FEATURE_SSBS
9796 | AARCH64_FEATURE_PROFILE
),
9798 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9799 AARCH64_FEATURE_BFLOAT16
9800 | AARCH64_FEATURE_I8MM
9801 | AARCH64_FEATURE_MEMTAG
9802 | AARCH64_FEATURE_SVE2_BITPERM
),
9804 {"generic", AARCH64_ARCH_V8
, NULL
},
9806 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9809 struct aarch64_arch_option_table
9812 const aarch64_feature_set value
;
9815 /* This list should, at a minimum, contain all the architecture names
9816 recognized by GCC. */
9817 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9818 {"all", AARCH64_ANY
},
9819 {"armv8-a", AARCH64_ARCH_V8
},
9820 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9821 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9822 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9823 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9824 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9825 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9826 {"armv8.7-a", AARCH64_ARCH_V8_7
},
9827 {"armv8-r", AARCH64_ARCH_V8_R
},
9828 {"armv9-a", AARCH64_ARCH_V9
},
9829 {NULL
, AARCH64_ARCH_NONE
}
9832 /* ISA extensions. */
9833 struct aarch64_option_cpu_value_table
9836 const aarch64_feature_set value
;
9837 const aarch64_feature_set require
; /* Feature dependencies. */
9840 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9841 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9843 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9844 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9845 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
9847 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
9849 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9850 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9851 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9853 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9855 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9857 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9858 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9859 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9860 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9861 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9862 AARCH64_FEATURE (AARCH64_FEATURE_FP
9863 | AARCH64_FEATURE_F16
, 0)},
9864 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9866 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9867 AARCH64_FEATURE (AARCH64_FEATURE_F16
9868 | AARCH64_FEATURE_SIMD
9869 | AARCH64_FEATURE_COMPNUM
, 0)},
9870 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9872 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9873 AARCH64_FEATURE (AARCH64_FEATURE_F16
9874 | AARCH64_FEATURE_SIMD
, 0)},
9875 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9877 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9879 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9881 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9883 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9885 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9887 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9889 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9890 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9891 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9893 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
9895 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
9897 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
9898 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9899 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9900 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9901 | AARCH64_FEATURE_SM4
, 0)},
9902 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
9903 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9904 | AARCH64_FEATURE_AES
, 0)},
9905 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
9906 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9907 | AARCH64_FEATURE_SHA3
, 0)},
9908 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
9909 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
9910 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
9911 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9912 | AARCH64_FEATURE_BFLOAT16
, 0)},
9913 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64
, 0),
9914 AARCH64_FEATURE (AARCH64_FEATURE_SME
9915 | AARCH64_FEATURE_SVE2
9916 | AARCH64_FEATURE_BFLOAT16
, 0)},
9917 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I64
, 0),
9918 AARCH64_FEATURE (AARCH64_FEATURE_SME
9919 | AARCH64_FEATURE_SVE2
9920 | AARCH64_FEATURE_BFLOAT16
, 0)},
9921 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
9923 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
9925 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
9926 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9927 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
9928 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9929 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
9931 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
9933 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
9935 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
9938 struct aarch64_long_option_table
9940 const char *option
; /* Substring to match. */
9941 const char *help
; /* Help information. */
9942 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
9943 char *deprecated
; /* If non-null, print this message. */
9946 /* Transitive closure of features depending on set. */
9947 static aarch64_feature_set
9948 aarch64_feature_disable_set (aarch64_feature_set set
)
9950 const struct aarch64_option_cpu_value_table
*opt
;
9951 aarch64_feature_set prev
= 0;
9953 while (prev
!= set
) {
9955 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9956 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
9957 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
9962 /* Transitive closure of dependencies of set. */
9963 static aarch64_feature_set
9964 aarch64_feature_enable_set (aarch64_feature_set set
)
9966 const struct aarch64_option_cpu_value_table
*opt
;
9967 aarch64_feature_set prev
= 0;
9969 while (prev
!= set
) {
9971 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9972 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
9973 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
9979 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
9982 /* We insist on extensions being added before being removed. We achieve
9983 this by using the ADDING_VALUE variable to indicate whether we are
9984 adding an extension (1) or removing it (0) and only allowing it to
9985 change in the order -1 -> 1 -> 0. */
9986 int adding_value
= -1;
9987 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
9989 /* Copy the feature set, so that we can modify it. */
9993 while (str
!= NULL
&& *str
!= 0)
9995 const struct aarch64_option_cpu_value_table
*opt
;
9996 const char *ext
= NULL
;
10003 as_bad (_("invalid architectural extension"));
10007 ext
= strchr (++str
, '+');
10011 optlen
= ext
- str
;
10013 optlen
= strlen (str
);
10015 if (optlen
>= 2 && startswith (str
, "no"))
10017 if (adding_value
!= 0)
10022 else if (optlen
> 0)
10024 if (adding_value
== -1)
10026 else if (adding_value
!= 1)
10028 as_bad (_("must specify extensions to add before specifying "
10029 "those to remove"));
10036 as_bad (_("missing architectural extension"));
10040 gas_assert (adding_value
!= -1);
10042 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10043 if (strncmp (opt
->name
, str
, optlen
) == 0)
10045 aarch64_feature_set set
;
10047 /* Add or remove the extension. */
10050 set
= aarch64_feature_enable_set (opt
->value
);
10051 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10055 set
= aarch64_feature_disable_set (opt
->value
);
10056 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10061 if (opt
->name
== NULL
)
10063 as_bad (_("unknown architectural extension `%s'"), str
);
10074 aarch64_parse_cpu (const char *str
)
10076 const struct aarch64_cpu_option_table
*opt
;
10077 const char *ext
= strchr (str
, '+');
10081 optlen
= ext
- str
;
10083 optlen
= strlen (str
);
10087 as_bad (_("missing cpu name `%s'"), str
);
10091 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10092 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10094 mcpu_cpu_opt
= &opt
->value
;
10096 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10101 as_bad (_("unknown cpu `%s'"), str
);
10106 aarch64_parse_arch (const char *str
)
10108 const struct aarch64_arch_option_table
*opt
;
10109 const char *ext
= strchr (str
, '+');
10113 optlen
= ext
- str
;
10115 optlen
= strlen (str
);
10119 as_bad (_("missing architecture name `%s'"), str
);
10123 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10124 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10126 march_cpu_opt
= &opt
->value
;
10128 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10133 as_bad (_("unknown architecture `%s'\n"), str
);
10138 struct aarch64_option_abi_value_table
10141 enum aarch64_abi_type value
;
10144 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10145 {"ilp32", AARCH64_ABI_ILP32
},
10146 {"lp64", AARCH64_ABI_LP64
},
10150 aarch64_parse_abi (const char *str
)
10154 if (str
[0] == '\0')
10156 as_bad (_("missing abi name `%s'"), str
);
10160 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10161 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10163 aarch64_abi
= aarch64_abis
[i
].value
;
10167 as_bad (_("unknown abi `%s'\n"), str
);
10171 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10173 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10174 aarch64_parse_abi
, NULL
},
10175 #endif /* OBJ_ELF */
10176 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10177 aarch64_parse_cpu
, NULL
},
10178 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10179 aarch64_parse_arch
, NULL
},
10180 {NULL
, NULL
, 0, NULL
}
10184 md_parse_option (int c
, const char *arg
)
10186 struct aarch64_option_table
*opt
;
10187 struct aarch64_long_option_table
*lopt
;
10193 target_big_endian
= 1;
10199 target_big_endian
= 0;
10204 /* Listing option. Just ignore these, we don't support additional
10209 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10211 if (c
== opt
->option
[0]
10212 && ((arg
== NULL
&& opt
->option
[1] == 0)
10213 || streq (arg
, opt
->option
+ 1)))
10215 /* If the option is deprecated, tell the user. */
10216 if (opt
->deprecated
!= NULL
)
10217 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10218 arg
? arg
: "", _(opt
->deprecated
));
10220 if (opt
->var
!= NULL
)
10221 *opt
->var
= opt
->value
;
10227 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10229 /* These options are expected to have an argument. */
10230 if (c
== lopt
->option
[0]
10232 && startswith (arg
, lopt
->option
+ 1))
10234 /* If the option is deprecated, tell the user. */
10235 if (lopt
->deprecated
!= NULL
)
10236 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10237 _(lopt
->deprecated
));
10239 /* Call the sup-option parser. */
10240 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10251 md_show_usage (FILE * fp
)
10253 struct aarch64_option_table
*opt
;
10254 struct aarch64_long_option_table
*lopt
;
10256 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10258 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10259 if (opt
->help
!= NULL
)
10260 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10262 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10263 if (lopt
->help
!= NULL
)
10264 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10268 -EB assemble code for a big-endian cpu\n"));
10273 -EL assemble code for a little-endian cpu\n"));
10277 /* Parse a .cpu directive. */
10280 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10282 const struct aarch64_cpu_option_table
*opt
;
10288 name
= input_line_pointer
;
10289 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10290 input_line_pointer
++;
10291 saved_char
= *input_line_pointer
;
10292 *input_line_pointer
= 0;
10294 ext
= strchr (name
, '+');
10297 optlen
= ext
- name
;
10299 optlen
= strlen (name
);
10301 /* Skip the first "all" entry. */
10302 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10303 if (strlen (opt
->name
) == optlen
10304 && strncmp (name
, opt
->name
, optlen
) == 0)
10306 mcpu_cpu_opt
= &opt
->value
;
10308 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10311 cpu_variant
= *mcpu_cpu_opt
;
10313 *input_line_pointer
= saved_char
;
10314 demand_empty_rest_of_line ();
10317 as_bad (_("unknown cpu `%s'"), name
);
10318 *input_line_pointer
= saved_char
;
10319 ignore_rest_of_line ();
10323 /* Parse a .arch directive. */
10326 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10328 const struct aarch64_arch_option_table
*opt
;
10334 name
= input_line_pointer
;
10335 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10336 input_line_pointer
++;
10337 saved_char
= *input_line_pointer
;
10338 *input_line_pointer
= 0;
10340 ext
= strchr (name
, '+');
10343 optlen
= ext
- name
;
10345 optlen
= strlen (name
);
10347 /* Skip the first "all" entry. */
10348 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10349 if (strlen (opt
->name
) == optlen
10350 && strncmp (name
, opt
->name
, optlen
) == 0)
10352 mcpu_cpu_opt
= &opt
->value
;
10354 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10357 cpu_variant
= *mcpu_cpu_opt
;
10359 *input_line_pointer
= saved_char
;
10360 demand_empty_rest_of_line ();
10364 as_bad (_("unknown architecture `%s'\n"), name
);
10365 *input_line_pointer
= saved_char
;
10366 ignore_rest_of_line ();
10369 /* Parse a .arch_extension directive. */
10372 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10375 char *ext
= input_line_pointer
;;
10377 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10378 input_line_pointer
++;
10379 saved_char
= *input_line_pointer
;
10380 *input_line_pointer
= 0;
10382 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10385 cpu_variant
= *mcpu_cpu_opt
;
10387 *input_line_pointer
= saved_char
;
10388 demand_empty_rest_of_line ();
10391 /* Copy symbol information. */
10394 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10396 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10400 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10401 This is needed so AArch64 specific st_other values can be independently
10402 specified for an IFUNC resolver (that is called by the dynamic linker)
10403 and the symbol it resolves (aliased to the resolver). In particular,
10404 if a function symbol has special st_other value set via directives,
10405 then attaching an IFUNC resolver to that symbol should not override
10406 the st_other setting. Requiring the directive on the IFUNC resolver
10407 symbol would be unexpected and problematic in C code, where the two
10408 symbols appear as two independent function declarations. */
10411 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10413 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10414 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10417 if (destelf
->size
== NULL
)
10418 destelf
->size
= XNEW (expressionS
);
10419 *destelf
->size
= *srcelf
->size
;
10423 free (destelf
->size
);
10424 destelf
->size
= NULL
;
10426 S_SET_SIZE (dest
, S_GET_SIZE (src
));