1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2023 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
35 #include "gen-sframe.h"
38 #include "dw2gencfi.h"
39 #include "dwarf2dbg.h"
41 /* Types of processor to assemble for. */
43 #define CPU_DEFAULT AARCH64_ARCH_V8
46 #define streq(a, b) (strcmp (a, b) == 0)
48 #define END_OF_INSN '\0'
50 static aarch64_feature_set cpu_variant
;
52 /* Variables that we set while parsing command-line options. Once all
53 options have been read we re-process these values to set the real
55 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
56 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
58 /* Constants for known architecture features. */
59 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
61 /* Currently active instruction sequence. */
62 static aarch64_instr_sequence
*insn_sequence
= NULL
;
65 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
66 static symbolS
*GOT_symbol
;
69 /* Which ABI to use. */
74 AARCH64_ABI_ILP32
= 2,
78 unsigned int aarch64_sframe_cfa_sp_reg
;
79 /* The other CFA base register for SFrame stack trace info. */
80 unsigned int aarch64_sframe_cfa_fp_reg
;
81 unsigned int aarch64_sframe_cfa_ra_reg
;
84 #define DEFAULT_ARCH "aarch64"
88 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
89 static const char *default_arch
= DEFAULT_ARCH
;
92 /* AArch64 ABI for the output file. */
93 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
95 /* When non-zero, program to a 32-bit model, in which the C data types
96 int, long and all pointer types are 32-bit objects (ILP32); or to a
97 64-bit model, in which the C int type is 32-bits but the C long type
98 and all pointer types are 64-bit objects (LP64). */
99 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
101 /* When non zero, C types int and long are 32 bit,
102 pointers, however are 64 bit */
103 #define llp64_p (aarch64_abi == AARCH64_ABI_LLP64)
117 /* Bits for DEFINED field in vector_type_el. */
118 #define NTA_HASTYPE 1
119 #define NTA_HASINDEX 2
120 #define NTA_HASVARWIDTH 4
122 struct vector_type_el
124 enum vector_el_type type
;
125 unsigned char defined
;
126 unsigned element_size
;
131 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
135 bfd_reloc_code_real_type type
;
138 enum aarch64_opnd opnd
;
140 unsigned need_libopcodes_p
: 1;
143 struct aarch64_instruction
145 /* libopcodes structure for instruction intermediate representation. */
147 /* Record assembly errors found during the parsing. */
148 aarch64_operand_error parsing_error
;
149 /* The condition that appears in the assembly line. */
151 /* Relocation information (including the GAS internal fixup). */
153 /* Need to generate an immediate in the literal pool. */
154 unsigned gen_lit_pool
: 1;
157 typedef struct aarch64_instruction aarch64_instruction
;
159 static aarch64_instruction inst
;
161 static bool parse_operands (char *, const aarch64_opcode
*);
162 static bool programmer_friendly_fixup (aarch64_instruction
*);
164 /* If an AARCH64_OPDE_SYNTAX_ERROR has no error string, its first three
165 data fields contain the following information:
168 A mask of register types that would have been acceptable as bare
169 operands, outside of a register list. In addition, SEF_DEFAULT_ERROR
170 is set if a general parsing error occured for an operand (that is,
171 an error not related to registers, and having no error string).
174 A mask of register types that would have been acceptable inside
175 a register list. In addition, SEF_IN_REGLIST is set if the
176 operand contained a '{' and if we got to the point of trying
177 to parse a register inside a list.
180 The mask associated with the register that was actually seen, or 0
181 if none. A nonzero value describes a register inside a register
182 list if data[1].i & SEF_IN_REGLIST, otherwise it describes a bare
185 The idea is that stringless errors from multiple opcode templates can
186 be ORed together to give a summary of the available alternatives. */
187 #define SEF_DEFAULT_ERROR (1U << 31)
188 #define SEF_IN_REGLIST (1U << 31)
190 /* Diagnostics inline function utilities.
192 These are lightweight utilities which should only be called by parse_operands
193 and other parsers. GAS processes each assembly line by parsing it against
194 instruction template(s), in the case of multiple templates (for the same
195 mnemonic name), those templates are tried one by one until one succeeds or
196 all fail. An assembly line may fail a few templates before being
197 successfully parsed; an error saved here in most cases is not a user error
198 but an error indicating the current template is not the right template.
199 Therefore it is very important that errors can be saved at a low cost during
200 the parsing; we don't want to slow down the whole parsing by recording
201 non-user errors in detail.
203 Remember that the objective is to help GAS pick up the most appropriate
204 error message in the case of multiple templates, e.g. FMOV which has 8
210 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
211 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
217 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
221 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
223 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
224 inst
.parsing_error
.index
= -1;
225 inst
.parsing_error
.kind
= kind
;
226 inst
.parsing_error
.error
= error
;
230 set_recoverable_error (const char *error
)
232 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
235 /* Use the DESC field of the corresponding aarch64_operand entry to compose
236 the error message. */
238 set_default_error (void)
240 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
241 inst
.parsing_error
.data
[0].i
= SEF_DEFAULT_ERROR
;
245 set_expected_error (unsigned int flags
)
247 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
248 inst
.parsing_error
.data
[0].i
= flags
;
252 set_syntax_error (const char *error
)
254 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
258 set_first_syntax_error (const char *error
)
261 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
265 set_fatal_syntax_error (const char *error
)
267 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
270 /* Return value for certain parsers when the parsing fails; those parsers
271 return the information of the parsed result, e.g. register number, on
273 #define PARSE_FAIL -1
275 /* This is an invalid condition code that means no conditional field is
277 #define COND_ALWAYS 0x10
281 const char *template;
288 bfd_reloc_code_real_type reloc
;
291 /* Macros to define the register types and masks for the purpose
294 #undef AARCH64_REG_TYPES
295 #define AARCH64_REG_TYPES \
296 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
297 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
298 BASIC_REG_TYPE(SP_32) /* wsp */ \
299 BASIC_REG_TYPE(SP_64) /* sp */ \
300 BASIC_REG_TYPE(ZR_32) /* wzr */ \
301 BASIC_REG_TYPE(ZR_64) /* xzr */ \
302 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
303 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
304 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
305 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
306 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
307 BASIC_REG_TYPE(V) /* v[0-31] */ \
308 BASIC_REG_TYPE(Z) /* z[0-31] */ \
309 BASIC_REG_TYPE(P) /* p[0-15] */ \
310 BASIC_REG_TYPE(ZA) /* za */ \
311 BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
312 BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
313 BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
314 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
315 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
316 /* Typecheck: same, plus SVE registers. */ \
317 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
319 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
320 MULTI_REG_TYPE(R_ZR, REG_TYPE(R_32) | REG_TYPE(R_64) \
321 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
322 /* Typecheck: same, plus SVE registers. */ \
323 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
324 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) \
326 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
327 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
328 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
329 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
330 MULTI_REG_TYPE(R_ZR_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
331 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
332 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
333 /* Typecheck: any [BHSDQ]P FP. */ \
334 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
335 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
336 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
337 MULTI_REG_TYPE(R_ZR_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
338 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \
339 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
340 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
341 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
342 be used for SVE instructions, since Zn and Pn are valid symbols \
343 in other contexts. */ \
344 MULTI_REG_TYPE(R_ZR_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
345 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
346 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \
347 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
348 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
349 | REG_TYPE(Z) | REG_TYPE(P)) \
350 /* Any integer register; used for error messages only. */ \
351 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
352 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
353 | REG_TYPE(ZR_32) | REG_TYPE(ZR_64)) \
354 /* Any vector register. */ \
355 MULTI_REG_TYPE(VZ, REG_TYPE(V) | REG_TYPE(Z)) \
356 /* An SVE vector or predicate register. */ \
357 MULTI_REG_TYPE(ZP, REG_TYPE(Z) | REG_TYPE(P)) \
358 /* Any vector or predicate register. */ \
359 MULTI_REG_TYPE(VZP, REG_TYPE(V) | REG_TYPE(Z) | REG_TYPE(P)) \
360 /* The whole of ZA or a single tile. */ \
361 MULTI_REG_TYPE(ZA_ZAT, REG_TYPE(ZA) | REG_TYPE(ZAT)) \
362 /* A horizontal or vertical slice of a ZA tile. */ \
363 MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV)) \
364 /* Pseudo type to mark the end of the enumerator sequence. */ \
367 #undef BASIC_REG_TYPE
368 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
369 #undef MULTI_REG_TYPE
370 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
372 #define END_REG_TYPE(T) BASIC_REG_TYPE(T)
374 /* Register type enumerators. */
375 typedef enum aarch64_reg_type_
377 /* A list of REG_TYPE_*. */
381 #undef BASIC_REG_TYPE
382 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
384 #define REG_TYPE(T) (1 << REG_TYPE_##T)
385 #undef MULTI_REG_TYPE
386 #define MULTI_REG_TYPE(T,V) V,
388 #define END_REG_TYPE(T) 0
390 /* Structure for a hash table entry for a register. */
394 unsigned char number
;
395 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
396 unsigned char builtin
;
399 /* Values indexed by aarch64_reg_type to assist the type checking. */
400 static const unsigned reg_type_masks
[] =
405 #undef BASIC_REG_TYPE
407 #undef MULTI_REG_TYPE
409 #undef AARCH64_REG_TYPES
411 /* We expected one of the registers in MASK to be specified. If a register
412 of some kind was specified, SEEN is a mask that contains that register,
413 otherwise it is zero.
415 If it is possible to provide a relatively pithy message that describes
416 the error exactly, return a string that does so, reporting the error
417 against "operand %d". Return null otherwise.
419 From a QoI perspective, any REG_TYPE_* that is passed as the first
420 argument to set_expected_reg_error should generally have its own message.
421 Providing messages for combinations of such REG_TYPE_*s can be useful if
422 it is possible to summarize the combination in a relatively natural way.
423 On the other hand, it seems better to avoid long lists of unrelated
427 get_reg_expected_msg (unsigned int mask
, unsigned int seen
)
429 /* First handle messages that use SEEN. */
430 if ((mask
& reg_type_masks
[REG_TYPE_ZAT
])
431 && (seen
& reg_type_masks
[REG_TYPE_ZATHV
]))
432 return N_("expected an unsuffixed ZA tile at operand %d");
434 if ((mask
& reg_type_masks
[REG_TYPE_ZATHV
])
435 && (seen
& reg_type_masks
[REG_TYPE_ZAT
]))
436 return N_("missing horizontal or vertical suffix at operand %d");
438 if ((mask
& reg_type_masks
[REG_TYPE_ZA
])
439 && (seen
& (reg_type_masks
[REG_TYPE_ZAT
]
440 | reg_type_masks
[REG_TYPE_ZATHV
])))
441 return N_("expected 'za' rather than a ZA tile at operand %d");
443 /* Integer, zero and stack registers. */
444 if (mask
== reg_type_masks
[REG_TYPE_R_64
])
445 return N_("expected a 64-bit integer register at operand %d");
446 if (mask
== reg_type_masks
[REG_TYPE_R_ZR
])
447 return N_("expected an integer or zero register at operand %d");
448 if (mask
== reg_type_masks
[REG_TYPE_R_SP
])
449 return N_("expected an integer or stack pointer register at operand %d");
451 /* Floating-point and SIMD registers. */
452 if (mask
== reg_type_masks
[REG_TYPE_BHSDQ
])
453 return N_("expected a scalar SIMD or floating-point register"
455 if (mask
== reg_type_masks
[REG_TYPE_V
])
456 return N_("expected an Advanced SIMD vector register at operand %d");
457 if (mask
== reg_type_masks
[REG_TYPE_Z
])
458 return N_("expected an SVE vector register at operand %d");
459 if (mask
== reg_type_masks
[REG_TYPE_P
])
460 return N_("expected an SVE predicate register at operand %d");
461 if (mask
== reg_type_masks
[REG_TYPE_VZ
])
462 return N_("expected a vector register at operand %d");
463 if (mask
== reg_type_masks
[REG_TYPE_ZP
])
464 return N_("expected an SVE vector or predicate register at operand %d");
465 if (mask
== reg_type_masks
[REG_TYPE_VZP
])
466 return N_("expected a vector or predicate register at operand %d");
468 /* ZA-related registers. */
469 if (mask
== reg_type_masks
[REG_TYPE_ZA
])
470 return N_("expected a ZA array vector at operand %d");
471 if (mask
== reg_type_masks
[REG_TYPE_ZA_ZAT
])
472 return N_("expected 'za' or a ZA tile at operand %d");
473 if (mask
== reg_type_masks
[REG_TYPE_ZAT
])
474 return N_("expected a ZA tile at operand %d");
475 if (mask
== reg_type_masks
[REG_TYPE_ZATHV
])
476 return N_("expected a ZA tile slice at operand %d");
478 /* Integer and vector combos. */
479 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_V
]))
480 return N_("expected an integer register or Advanced SIMD vector register"
482 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_Z
]))
483 return N_("expected an integer register or SVE vector register"
485 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_VZ
]))
486 return N_("expected an integer or vector register at operand %d");
487 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_P
]))
488 return N_("expected an integer or predicate register at operand %d");
489 if (mask
== (reg_type_masks
[REG_TYPE_R_ZR
] | reg_type_masks
[REG_TYPE_VZP
]))
490 return N_("expected an integer, vector or predicate register"
493 /* SVE and SME combos. */
494 if (mask
== (reg_type_masks
[REG_TYPE_Z
] | reg_type_masks
[REG_TYPE_ZATHV
]))
495 return N_("expected an SVE vector register or ZA tile slice"
501 /* Record that we expected a register of type TYPE but didn't see one.
502 REG is the register that we actually saw, or null if we didn't see a
503 recognized register. FLAGS is SEF_IN_REGLIST if we are parsing the
504 contents of a register list, otherwise it is zero. */
507 set_expected_reg_error (aarch64_reg_type type
, const reg_entry
*reg
,
510 assert (flags
== 0 || flags
== SEF_IN_REGLIST
);
511 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
512 if (flags
& SEF_IN_REGLIST
)
513 inst
.parsing_error
.data
[1].i
= reg_type_masks
[type
] | flags
;
515 inst
.parsing_error
.data
[0].i
= reg_type_masks
[type
];
517 inst
.parsing_error
.data
[2].i
= reg_type_masks
[reg
->type
];
520 /* Record that we expected a register list containing registers of type TYPE,
521 but didn't see the opening '{'. If we saw a register instead, REG is the
522 register that we saw, otherwise it is null. */
525 set_expected_reglist_error (aarch64_reg_type type
, const reg_entry
*reg
)
527 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
528 inst
.parsing_error
.data
[1].i
= reg_type_masks
[type
];
530 inst
.parsing_error
.data
[2].i
= reg_type_masks
[reg
->type
];
533 /* Some well known registers that we refer to directly elsewhere. */
537 /* Instructions take 4 bytes in the object file. */
540 static htab_t aarch64_ops_hsh
;
541 static htab_t aarch64_cond_hsh
;
542 static htab_t aarch64_shift_hsh
;
543 static htab_t aarch64_sys_regs_hsh
;
544 static htab_t aarch64_pstatefield_hsh
;
545 static htab_t aarch64_sys_regs_ic_hsh
;
546 static htab_t aarch64_sys_regs_dc_hsh
;
547 static htab_t aarch64_sys_regs_at_hsh
;
548 static htab_t aarch64_sys_regs_tlbi_hsh
;
549 static htab_t aarch64_sys_regs_sr_hsh
;
550 static htab_t aarch64_reg_hsh
;
551 static htab_t aarch64_barrier_opt_hsh
;
552 static htab_t aarch64_nzcv_hsh
;
553 static htab_t aarch64_pldop_hsh
;
554 static htab_t aarch64_hint_opt_hsh
;
556 /* Stuff needed to resolve the label ambiguity
565 static symbolS
*last_label_seen
;
567 /* Literal pool structure. Held on a per-section
568 and per-sub-section basis. */
570 #define MAX_LITERAL_POOL_SIZE 1024
571 typedef struct literal_expression
574 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
575 LITTLENUM_TYPE
* bignum
;
576 } literal_expression
;
578 typedef struct literal_pool
580 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
581 unsigned int next_free_entry
;
587 struct literal_pool
*next
;
590 /* Pointer to a linked list of literal pools. */
591 static literal_pool
*list_of_pools
= NULL
;
595 /* This array holds the chars that always start a comment. If the
596 pre-processor is disabled, these aren't very useful. */
597 const char comment_chars
[] = "";
599 /* This array holds the chars that only start a comment at the beginning of
600 a line. If the line seems to have the form '# 123 filename'
601 .line and .file directives will appear in the pre-processed output. */
602 /* Note that input_file.c hand checks for '#' at the beginning of the
603 first line of the input file. This is because the compiler outputs
604 #NO_APP at the beginning of its output. */
605 /* Also note that comments like this one will always work. */
606 const char line_comment_chars
[] = "#";
608 const char line_separator_chars
[] = ";";
610 /* Chars that can be used to separate mant
611 from exp in floating point numbers. */
612 const char EXP_CHARS
[] = "eE";
614 /* Chars that mean this number is a floating point constant. */
618 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
620 /* Prefix character that indicates the start of an immediate value. */
621 #define is_immediate_prefix(C) ((C) == '#')
623 /* Separator character handling. */
625 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
628 skip_past_char (char **str
, char c
)
639 #define skip_past_comma(str) skip_past_char (str, ',')
641 /* Arithmetic expressions (possibly involving symbols). */
643 static bool in_aarch64_get_expression
= false;
645 /* Third argument to aarch64_get_expression. */
646 #define GE_NO_PREFIX false
647 #define GE_OPT_PREFIX true
649 /* Fourth argument to aarch64_get_expression. */
650 #define ALLOW_ABSENT false
651 #define REJECT_ABSENT true
653 /* Return TRUE if the string pointed by *STR is successfully parsed
654 as an valid expression; *EP will be filled with the information of
655 such an expression. Otherwise return FALSE.
657 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
658 If REJECT_ABSENT is true then trat missing expressions as an error. */
661 aarch64_get_expression (expressionS
* ep
,
663 bool allow_immediate_prefix
,
668 bool prefix_present
= false;
670 if (allow_immediate_prefix
)
672 if (is_immediate_prefix (**str
))
675 prefix_present
= true;
679 memset (ep
, 0, sizeof (expressionS
));
681 save_in
= input_line_pointer
;
682 input_line_pointer
= *str
;
683 in_aarch64_get_expression
= true;
684 seg
= expression (ep
);
685 in_aarch64_get_expression
= false;
687 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
689 /* We found a bad expression in md_operand(). */
690 *str
= input_line_pointer
;
691 input_line_pointer
= save_in
;
692 if (prefix_present
&& ! error_p ())
693 set_fatal_syntax_error (_("bad expression"));
695 set_first_syntax_error (_("bad expression"));
700 if (seg
!= absolute_section
701 && seg
!= text_section
702 && seg
!= data_section
703 && seg
!= bss_section
704 && seg
!= undefined_section
)
706 set_syntax_error (_("bad segment"));
707 *str
= input_line_pointer
;
708 input_line_pointer
= save_in
;
715 *str
= input_line_pointer
;
716 input_line_pointer
= save_in
;
720 /* Turn a string in input_line_pointer into a floating point constant
721 of type TYPE, and store the appropriate bytes in *LITP. The number
722 of LITTLENUMS emitted is stored in *SIZEP. An error message is
723 returned, or NULL on OK. */
726 md_atof (int type
, char *litP
, int *sizeP
)
728 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
731 /* We handle all bad expressions here, so that we can report the faulty
732 instruction in the error message. */
734 md_operand (expressionS
* exp
)
736 if (in_aarch64_get_expression
)
737 exp
->X_op
= O_illegal
;
740 /* Immediate values. */
742 /* Errors may be set multiple times during parsing or bit encoding
743 (particularly in the Neon bits), but usually the earliest error which is set
744 will be the most meaningful. Avoid overwriting it with later (cascading)
745 errors by calling this function. */
748 first_error (const char *error
)
751 set_syntax_error (error
);
754 /* Similar to first_error, but this function accepts formatted error
757 first_error_fmt (const char *format
, ...)
762 /* N.B. this single buffer will not cause error messages for different
763 instructions to pollute each other; this is because at the end of
764 processing of each assembly line, error message if any will be
765 collected by as_bad. */
766 static char buffer
[size
];
770 int ret ATTRIBUTE_UNUSED
;
771 va_start (args
, format
);
772 ret
= vsnprintf (buffer
, size
, format
, args
);
773 know (ret
<= size
- 1 && ret
>= 0);
775 set_syntax_error (buffer
);
779 /* Internal helper routine converting a vector_type_el structure *VECTYPE
780 to a corresponding operand qualifier. */
782 static inline aarch64_opnd_qualifier_t
783 vectype_to_qualifier (const struct vector_type_el
*vectype
)
785 /* Element size in bytes indexed by vector_el_type. */
786 const unsigned char ele_size
[5]
788 const unsigned int ele_base
[5] =
790 AARCH64_OPND_QLF_V_4B
,
791 AARCH64_OPND_QLF_V_2H
,
792 AARCH64_OPND_QLF_V_2S
,
793 AARCH64_OPND_QLF_V_1D
,
794 AARCH64_OPND_QLF_V_1Q
797 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
798 goto vectype_conversion_fail
;
800 if (vectype
->type
== NT_zero
)
801 return AARCH64_OPND_QLF_P_Z
;
802 if (vectype
->type
== NT_merge
)
803 return AARCH64_OPND_QLF_P_M
;
805 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
807 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
809 /* Special case S_4B. */
810 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
811 return AARCH64_OPND_QLF_S_4B
;
813 /* Special case S_2H. */
814 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
815 return AARCH64_OPND_QLF_S_2H
;
817 /* Vector element register. */
818 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
822 /* Vector register. */
823 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
826 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
827 goto vectype_conversion_fail
;
829 /* The conversion is by calculating the offset from the base operand
830 qualifier for the vector type. The operand qualifiers are regular
831 enough that the offset can established by shifting the vector width by
832 a vector-type dependent amount. */
834 if (vectype
->type
== NT_b
)
836 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
838 else if (vectype
->type
>= NT_d
)
843 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
844 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
845 && offset
<= AARCH64_OPND_QLF_V_1Q
);
849 vectype_conversion_fail
:
850 first_error (_("bad vector arrangement type"));
851 return AARCH64_OPND_QLF_NIL
;
854 /* Register parsing. */
856 /* Generic register parser which is called by other specialized
858 CCP points to what should be the beginning of a register name.
859 If it is indeed a valid register name, advance CCP over it and
860 return the reg_entry structure; otherwise return NULL.
861 It does not issue diagnostics. */
864 parse_reg (char **ccp
)
870 #ifdef REGISTER_PREFIX
871 if (*start
!= REGISTER_PREFIX
)
877 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
882 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
884 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
893 /* Return the operand qualifier associated with all uses of REG, or
894 AARCH64_OPND_QLF_NIL if none. AARCH64_OPND_QLF_NIL means either
895 that qualifiers don't apply to REG or that qualifiers are added
898 static aarch64_opnd_qualifier_t
899 inherent_reg_qualifier (const reg_entry
*reg
)
906 return AARCH64_OPND_QLF_W
;
911 return AARCH64_OPND_QLF_X
;
918 return AARCH64_OPND_QLF_S_B
+ (reg
->type
- REG_TYPE_FP_B
);
921 return AARCH64_OPND_QLF_NIL
;
925 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
928 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
930 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
933 /* Try to parse a base or offset register. Allow SVE base and offset
934 registers if REG_TYPE includes SVE registers. Return the register
935 entry on success, setting *QUALIFIER to the register qualifier.
936 Return null otherwise.
938 Note that this function does not issue any diagnostics. */
940 static const reg_entry
*
941 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
942 aarch64_opnd_qualifier_t
*qualifier
)
945 const reg_entry
*reg
= parse_reg (&str
);
953 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_Z
)) == 0
956 switch (TOLOWER (str
[1]))
959 *qualifier
= AARCH64_OPND_QLF_S_S
;
962 *qualifier
= AARCH64_OPND_QLF_S_D
;
971 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_ZR_SP
))
973 *qualifier
= inherent_reg_qualifier (reg
);
982 /* Try to parse a base or offset register. Return the register entry
983 on success, setting *QUALIFIER to the register qualifier. Return null
986 Note that this function does not issue any diagnostics. */
988 static const reg_entry
*
989 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
991 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_ZR_SP
, qualifier
);
994 /* Parse the qualifier of a vector register or vector element of type
995 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
996 succeeds; otherwise return FALSE.
998 Accept only one occurrence of:
999 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
1002 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
1003 struct vector_type_el
*parsed_type
, char **str
)
1007 unsigned element_size
;
1008 enum vector_el_type type
;
1011 gas_assert (*ptr
== '.');
1014 if (reg_type
!= REG_TYPE_V
|| !ISDIGIT (*ptr
))
1019 width
= strtoul (ptr
, &ptr
, 10);
1020 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
1022 first_error_fmt (_("bad size %d in vector width specifier"), width
);
1027 switch (TOLOWER (*ptr
))
1046 if (reg_type
!= REG_TYPE_V
|| width
== 1)
1055 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
1057 first_error (_("missing element size"));
1060 if (width
!= 0 && width
* element_size
!= 64
1061 && width
* element_size
!= 128
1062 && !(width
== 2 && element_size
== 16)
1063 && !(width
== 4 && element_size
== 8))
1066 ("invalid element size %d and vector size combination %c"),
1072 parsed_type
->type
= type
;
1073 parsed_type
->width
= width
;
1074 parsed_type
->element_size
= element_size
;
1081 /* *STR contains an SVE zero/merge predication suffix. Parse it into
1082 *PARSED_TYPE and point *STR at the end of the suffix. */
1085 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
1090 gas_assert (*ptr
== '/');
1092 switch (TOLOWER (*ptr
))
1095 parsed_type
->type
= NT_zero
;
1098 parsed_type
->type
= NT_merge
;
1101 if (*ptr
!= '\0' && *ptr
!= ',')
1102 first_error_fmt (_("unexpected character `%c' in predication type"),
1105 first_error (_("missing predication type"));
1108 parsed_type
->width
= 0;
1113 /* Return true if CH is a valid suffix character for registers of
1117 aarch64_valid_suffix_char_p (aarch64_reg_type type
, char ch
)
1130 return ch
== '.' || ch
== '/';
1137 /* Parse an index expression at *STR, storing it in *IMM on success. */
1140 parse_index_expression (char **str
, int64_t *imm
)
1144 aarch64_get_expression (&exp
, str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1145 if (exp
.X_op
!= O_constant
)
1147 first_error (_("constant expression required"));
1150 *imm
= exp
.X_add_number
;
1154 /* Parse a register of the type TYPE.
1156 Return null if the string pointed to by *CCP is not a valid register
1157 name or the parsed register is not of TYPE.
1159 Otherwise return the register, and optionally return the register
1160 shape and element index information in *TYPEINFO.
1162 FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.
1164 FLAGS includes PTR_FULL_REG if the function should ignore any potential
1167 FLAGS includes PTR_GOOD_MATCH if we are sufficiently far into parsing
1168 an operand that we can be confident that it is a good match. */
1170 #define PTR_IN_REGLIST (1U << 0)
1171 #define PTR_FULL_REG (1U << 1)
1172 #define PTR_GOOD_MATCH (1U << 2)
1174 static const reg_entry
*
1175 parse_typed_reg (char **ccp
, aarch64_reg_type type
,
1176 struct vector_type_el
*typeinfo
, unsigned int flags
)
1179 bool isalpha
= ISALPHA (*str
);
1180 const reg_entry
*reg
= parse_reg (&str
);
1181 struct vector_type_el atype
;
1182 struct vector_type_el parsetype
;
1183 bool is_typed_vecreg
= false;
1184 unsigned int err_flags
= (flags
& PTR_IN_REGLIST
) ? SEF_IN_REGLIST
: 0;
1187 atype
.type
= NT_invtype
;
1189 atype
.element_size
= 0;
1196 if (!isalpha
&& (flags
& PTR_IN_REGLIST
))
1197 set_fatal_syntax_error (_("syntax error in register list"));
1198 else if (flags
& PTR_GOOD_MATCH
)
1199 set_fatal_syntax_error (NULL
);
1201 set_expected_reg_error (type
, reg
, err_flags
);
1205 if (! aarch64_check_reg_type (reg
, type
))
1207 DEBUG_TRACE ("reg type check failed");
1208 if (flags
& PTR_GOOD_MATCH
)
1209 set_fatal_syntax_error (NULL
);
1211 set_expected_reg_error (type
, reg
, err_flags
);
1216 if (aarch64_valid_suffix_char_p (reg
->type
, *str
))
1220 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1222 if ((reg
->type
== REG_TYPE_ZAT
1223 || reg
->type
== REG_TYPE_ZATH
1224 || reg
->type
== REG_TYPE_ZATV
)
1225 && reg
->number
* 8 >= parsetype
.element_size
)
1227 set_syntax_error (_("ZA tile number out of range"));
1233 if (!parse_predication_for_operand (&parsetype
, &str
))
1237 /* Register if of the form Vn.[bhsdq]. */
1238 is_typed_vecreg
= true;
1240 if (type
!= REG_TYPE_V
)
1242 /* The width is always variable; we don't allow an integer width
1244 gas_assert (parsetype
.width
== 0);
1245 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1247 else if (parsetype
.width
== 0)
1248 /* Expect index. In the new scheme we cannot have
1249 Vn.[bhsdq] represent a scalar. Therefore any
1250 Vn.[bhsdq] should have an index following it.
1251 Except in reglists of course. */
1252 atype
.defined
|= NTA_HASINDEX
;
1254 atype
.defined
|= NTA_HASTYPE
;
1256 atype
.type
= parsetype
.type
;
1257 atype
.width
= parsetype
.width
;
1260 if (!(flags
& PTR_FULL_REG
) && skip_past_char (&str
, '['))
1262 /* Reject Sn[index] syntax. */
1263 if (!is_typed_vecreg
)
1265 first_error (_("this type of register can't be indexed"));
1269 if (flags
& PTR_IN_REGLIST
)
1271 first_error (_("index not allowed inside register list"));
1275 atype
.defined
|= NTA_HASINDEX
;
1277 if (!parse_index_expression (&str
, &atype
.index
))
1280 if (! skip_past_char (&str
, ']'))
1283 else if (!(flags
& PTR_IN_REGLIST
) && (atype
.defined
& NTA_HASINDEX
) != 0)
1285 /* Indexed vector register expected. */
1286 first_error (_("indexed vector register expected"));
1290 /* A vector reg Vn should be typed or indexed. */
1291 if (type
== REG_TYPE_V
&& atype
.defined
== 0)
1293 first_error (_("invalid use of vector register"));
1306 Return the register on success; return null otherwise.
1308 If this is a NEON vector register with additional type information, fill
1309 in the struct pointed to by VECTYPE (if non-NULL).
1311 This parser does not handle register lists. */
1313 static const reg_entry
*
1314 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1315 struct vector_type_el
*vectype
)
1317 return parse_typed_reg (ccp
, type
, vectype
, 0);
1321 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1323 return (e1
.type
== e2
.type
1324 && e1
.defined
== e2
.defined
1325 && e1
.width
== e2
.width
1326 && e1
.element_size
== e2
.element_size
1327 && e1
.index
== e2
.index
);
1330 /* This function parses a list of vector registers of type TYPE.
1331 On success, it returns the parsed register list information in the
1332 following encoded format:
1334 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1335 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1337 The information of the register shape and/or index is returned in
1340 It returns PARSE_FAIL if the register list is invalid.
1342 The list contains one to four registers.
1343 Each register can be one of:
1346 All <T> should be identical.
1347 All <index> should be identical.
1348 There are restrictions on <Vt> numbers which are checked later
1349 (by reg_list_valid_p). */
1352 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1353 struct vector_type_el
*vectype
)
1357 struct vector_type_el typeinfo
, typeinfo_first
;
1363 bool expect_index
= false;
1364 unsigned int ptr_flags
= PTR_IN_REGLIST
;
1368 set_expected_reglist_error (type
, parse_reg (&str
));
1374 typeinfo_first
.defined
= 0;
1375 typeinfo_first
.type
= NT_invtype
;
1376 typeinfo_first
.width
= -1;
1377 typeinfo_first
.element_size
= 0;
1378 typeinfo_first
.index
= 0;
1387 str
++; /* skip over '-' */
1390 const reg_entry
*reg
= parse_typed_reg (&str
, type
, &typeinfo
,
1394 set_first_syntax_error (_("invalid vector register in list"));
1399 /* reject [bhsd]n */
1400 if (type
== REG_TYPE_V
&& typeinfo
.defined
== 0)
1402 set_first_syntax_error (_("invalid scalar register in list"));
1407 if (typeinfo
.defined
& NTA_HASINDEX
)
1408 expect_index
= true;
1412 if (val
< val_range
)
1414 set_first_syntax_error
1415 (_("invalid range in vector register list"));
1424 typeinfo_first
= typeinfo
;
1425 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1427 set_first_syntax_error
1428 (_("type mismatch in vector register list"));
1433 for (i
= val_range
; i
<= val
; i
++)
1435 ret_val
|= i
<< (5 * nb_regs
);
1439 ptr_flags
|= PTR_GOOD_MATCH
;
1441 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1443 skip_whitespace (str
);
1446 set_first_syntax_error (_("end of vector register list not found"));
1451 skip_whitespace (str
);
1455 if (skip_past_char (&str
, '['))
1457 if (!parse_index_expression (&str
, &typeinfo_first
.index
))
1459 if (! skip_past_char (&str
, ']'))
1464 set_first_syntax_error (_("expected index"));
1471 set_first_syntax_error (_("too many registers in vector register list"));
1474 else if (nb_regs
== 0)
1476 set_first_syntax_error (_("empty vector register list"));
1482 *vectype
= typeinfo_first
;
1484 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1487 /* Directives: register aliases. */
1490 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1495 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1498 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1501 /* Only warn about a redefinition if it's not defined as the
1503 else if (new->number
!= number
|| new->type
!= type
)
1504 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1509 name
= xstrdup (str
);
1510 new = XNEW (reg_entry
);
1513 new->number
= number
;
1515 new->builtin
= false;
1517 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1522 /* Look for the .req directive. This is of the form:
1524 new_register_name .req existing_register_name
1526 If we find one, or if it looks sufficiently like one that we want to
1527 handle any error here, return TRUE. Otherwise return FALSE. */
1530 create_register_alias (char *newname
, char *p
)
1532 const reg_entry
*old
;
1533 char *oldname
, *nbuf
;
1536 /* The input scrubber ensures that whitespace after the mnemonic is
1537 collapsed to single spaces. */
1539 if (!startswith (oldname
, " .req "))
1543 if (*oldname
== '\0')
1546 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1549 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1553 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1554 the desired alias name, and p points to its end. If not, then
1555 the desired alias name is in the global original_case_string. */
1556 #ifdef TC_CASE_SENSITIVE
1559 newname
= original_case_string
;
1560 nlen
= strlen (newname
);
1563 nbuf
= xmemdup0 (newname
, nlen
);
1565 /* Create aliases under the new name as stated; an all-lowercase
1566 version of the new name; and an all-uppercase version of the new
1568 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1570 for (p
= nbuf
; *p
; p
++)
1573 if (strncmp (nbuf
, newname
, nlen
))
1575 /* If this attempt to create an additional alias fails, do not bother
1576 trying to create the all-lower case alias. We will fail and issue
1577 a second, duplicate error message. This situation arises when the
1578 programmer does something like:
1581 The second .req creates the "Foo" alias but then fails to create
1582 the artificial FOO alias because it has already been created by the
1584 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1591 for (p
= nbuf
; *p
; p
++)
1594 if (strncmp (nbuf
, newname
, nlen
))
1595 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1602 /* Should never be called, as .req goes between the alias and the
1603 register name, not at the beginning of the line. */
1605 s_req (int a ATTRIBUTE_UNUSED
)
1607 as_bad (_("invalid syntax for .req directive"));
1610 /* The .unreq directive deletes an alias which was previously defined
1611 by .req. For example:
1617 s_unreq (int a ATTRIBUTE_UNUSED
)
1622 name
= input_line_pointer
;
1623 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
1624 saved_char
= *input_line_pointer
;
1625 *input_line_pointer
= 0;
1628 as_bad (_("invalid syntax for .unreq directive"));
1631 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1634 as_bad (_("unknown register alias '%s'"), name
);
1635 else if (reg
->builtin
)
1636 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1643 str_hash_delete (aarch64_reg_hsh
, name
);
1644 free ((char *) reg
->name
);
1647 /* Also locate the all upper case and all lower case versions.
1648 Do not complain if we cannot find one or the other as it
1649 was probably deleted above. */
1651 nbuf
= strdup (name
);
1652 for (p
= nbuf
; *p
; p
++)
1654 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1657 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1658 free ((char *) reg
->name
);
1662 for (p
= nbuf
; *p
; p
++)
1664 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1667 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1668 free ((char *) reg
->name
);
1676 *input_line_pointer
= saved_char
;
1677 demand_empty_rest_of_line ();
1680 /* Directives: Instruction set selection. */
1682 #if defined OBJ_ELF || defined OBJ_COFF
1683 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1684 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1685 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1686 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1688 /* Create a new mapping symbol for the transition to STATE. */
1691 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1694 const char *symname
;
1701 type
= BSF_NO_FLAGS
;
1705 type
= BSF_NO_FLAGS
;
1711 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1712 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1714 /* Save the mapping symbols for future reference. Also check that
1715 we do not place two mapping symbols at the same offset within a
1716 frag. We'll handle overlap between frags in
1717 check_mapping_symbols.
1719 If .fill or other data filling directive generates zero sized data,
1720 the mapping symbol for the following code will have the same value
1721 as the one generated for the data filling directive. In this case,
1722 we replace the old symbol with the new one at the same address. */
1725 if (frag
->tc_frag_data
.first_map
!= NULL
)
1727 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1728 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1731 frag
->tc_frag_data
.first_map
= symbolP
;
1733 if (frag
->tc_frag_data
.last_map
!= NULL
)
1735 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1736 S_GET_VALUE (symbolP
));
1737 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1738 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1741 frag
->tc_frag_data
.last_map
= symbolP
;
1744 /* We must sometimes convert a region marked as code to data during
1745 code alignment, if an odd number of bytes have to be padded. The
1746 code mapping symbol is pushed to an aligned address. */
1749 insert_data_mapping_symbol (enum mstate state
,
1750 valueT value
, fragS
* frag
, offsetT bytes
)
1752 /* If there was already a mapping symbol, remove it. */
1753 if (frag
->tc_frag_data
.last_map
!= NULL
1754 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1755 frag
->fr_address
+ value
)
1757 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1761 know (frag
->tc_frag_data
.first_map
== symp
);
1762 frag
->tc_frag_data
.first_map
= NULL
;
1764 frag
->tc_frag_data
.last_map
= NULL
;
1765 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1768 make_mapping_symbol (MAP_DATA
, value
, frag
);
1769 make_mapping_symbol (state
, value
+ bytes
, frag
);
1772 static void mapping_state_2 (enum mstate state
, int max_chars
);
1774 /* Set the mapping state to STATE. Only call this when about to
1775 emit some STATE bytes to the file. */
1778 mapping_state (enum mstate state
)
1780 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1782 if (state
== MAP_INSN
)
1783 /* AArch64 instructions require 4-byte alignment. When emitting
1784 instructions into any section, record the appropriate section
1786 record_alignment (now_seg
, 2);
1788 if (mapstate
== state
)
1789 /* The mapping symbol has already been emitted.
1790 There is nothing else to do. */
1793 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1794 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1795 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1796 evaluated later in the next else. */
1798 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1800 /* Only add the symbol if the offset is > 0:
1801 if we're at the first frag, check it's size > 0;
1802 if we're not at the first frag, then for sure
1803 the offset is > 0. */
1804 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1805 const int add_symbol
= (frag_now
!= frag_first
)
1806 || (frag_now_fix () > 0);
1809 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1813 mapping_state_2 (state
, 0);
1816 /* Same as mapping_state, but MAX_CHARS bytes have already been
1817 allocated. Put the mapping symbol that far back. */
1820 mapping_state_2 (enum mstate state
, int max_chars
)
1822 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1824 if (!SEG_NORMAL (now_seg
))
1827 if (mapstate
== state
)
1828 /* The mapping symbol has already been emitted.
1829 There is nothing else to do. */
1832 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1833 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1836 #define mapping_state(x) /* nothing */
1837 #define mapping_state_2(x, y) /* nothing */
1840 /* Directives: sectioning and alignment. */
1843 s_bss (int ignore ATTRIBUTE_UNUSED
)
1845 /* We don't support putting frags in the BSS segment, we fake it by
1846 marking in_bss, then looking at s_skip for clues. */
1847 subseg_set (bss_section
, 0);
1848 demand_empty_rest_of_line ();
1849 mapping_state (MAP_DATA
);
1853 s_even (int ignore ATTRIBUTE_UNUSED
)
1855 /* Never make frag if expect extra pass. */
1857 frag_align (1, 0, 0);
1859 record_alignment (now_seg
, 1);
1861 demand_empty_rest_of_line ();
1864 /* Directives: Literal pools. */
1866 static literal_pool
*
1867 find_literal_pool (int size
)
1871 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1873 if (pool
->section
== now_seg
1874 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1881 static literal_pool
*
1882 find_or_make_literal_pool (int size
)
1884 /* Next literal pool ID number. */
1885 static unsigned int latest_pool_num
= 1;
1888 pool
= find_literal_pool (size
);
1892 /* Create a new pool. */
1893 pool
= XNEW (literal_pool
);
1897 /* Currently we always put the literal pool in the current text
1898 section. If we were generating "small" model code where we
1899 knew that all code and initialised data was within 1MB then
1900 we could output literals to mergeable, read-only data
1903 pool
->next_free_entry
= 0;
1904 pool
->section
= now_seg
;
1905 pool
->sub_section
= now_subseg
;
1907 pool
->next
= list_of_pools
;
1908 pool
->symbol
= NULL
;
1910 /* Add it to the list. */
1911 list_of_pools
= pool
;
1914 /* New pools, and emptied pools, will have a NULL symbol. */
1915 if (pool
->symbol
== NULL
)
1917 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1918 &zero_address_frag
, 0);
1919 pool
->id
= latest_pool_num
++;
1926 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1927 Return TRUE on success, otherwise return FALSE. */
1929 add_to_lit_pool (expressionS
*exp
, int size
)
1934 pool
= find_or_make_literal_pool (size
);
1936 /* Check if this literal value is already in the pool. */
1937 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1939 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1941 if ((litexp
->X_op
== exp
->X_op
)
1942 && (exp
->X_op
== O_constant
)
1943 && (litexp
->X_add_number
== exp
->X_add_number
)
1944 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1947 if ((litexp
->X_op
== exp
->X_op
)
1948 && (exp
->X_op
== O_symbol
)
1949 && (litexp
->X_add_number
== exp
->X_add_number
)
1950 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1951 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1955 /* Do we need to create a new entry? */
1956 if (entry
== pool
->next_free_entry
)
1958 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1960 set_syntax_error (_("literal pool overflow"));
1964 pool
->literals
[entry
].exp
= *exp
;
1965 pool
->next_free_entry
+= 1;
1966 if (exp
->X_op
== O_big
)
1968 /* PR 16688: Bignums are held in a single global array. We must
1969 copy and preserve that value now, before it is overwritten. */
1970 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1972 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1973 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1976 pool
->literals
[entry
].bignum
= NULL
;
1979 exp
->X_op
= O_symbol
;
1980 exp
->X_add_number
= ((int) entry
) * size
;
1981 exp
->X_add_symbol
= pool
->symbol
;
1986 /* Can't use symbol_new here, so have to create a symbol and then at
1987 a later date assign it a value. That's what these functions do. */
1990 symbol_locate (symbolS
* symbolP
,
1991 const char *name
,/* It is copied, the caller can modify. */
1992 segT segment
, /* Segment identifier (SEG_<something>). */
1993 valueT valu
, /* Symbol value. */
1994 fragS
* frag
) /* Associated fragment. */
1997 char *preserved_copy_of_name
;
1999 name_length
= strlen (name
) + 1; /* +1 for \0. */
2000 obstack_grow (¬es
, name
, name_length
);
2001 preserved_copy_of_name
= obstack_finish (¬es
);
2003 #ifdef tc_canonicalize_symbol_name
2004 preserved_copy_of_name
=
2005 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2008 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2010 S_SET_SEGMENT (symbolP
, segment
);
2011 S_SET_VALUE (symbolP
, valu
);
2012 symbol_clear_list_pointers (symbolP
);
2014 symbol_set_frag (symbolP
, frag
);
2016 /* Link to end of symbol chain. */
2018 extern int symbol_table_frozen
;
2020 if (symbol_table_frozen
)
2024 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
2026 obj_symbol_new_hook (symbolP
);
2028 #ifdef tc_symbol_new_hook
2029 tc_symbol_new_hook (symbolP
);
2033 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2034 #endif /* DEBUG_SYMS */
2039 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2046 for (align
= 2; align
<= 4; align
++)
2048 int size
= 1 << align
;
2050 pool
= find_literal_pool (size
);
2051 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
2054 /* Align pool as you have word accesses.
2055 Only make a frag if we have to. */
2057 frag_align (align
, 0, 0);
2059 mapping_state (MAP_DATA
);
2061 record_alignment (now_seg
, align
);
2063 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2065 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2066 (valueT
) frag_now_fix (), frag_now
);
2067 symbol_table_insert (pool
->symbol
);
2069 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2071 expressionS
* exp
= & pool
->literals
[entry
].exp
;
2073 if (exp
->X_op
== O_big
)
2075 /* PR 16688: Restore the global bignum value. */
2076 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
2077 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
2078 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
2081 /* First output the expression in the instruction to the pool. */
2082 emit_expr (exp
, size
); /* .word|.xword */
2084 if (exp
->X_op
== O_big
)
2086 free (pool
->literals
[entry
].bignum
);
2087 pool
->literals
[entry
].bignum
= NULL
;
2091 /* Mark the pool as empty. */
2092 pool
->next_free_entry
= 0;
2093 pool
->symbol
= NULL
;
2097 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2098 /* Forward declarations for functions below, in the MD interface
2100 static struct reloc_table_entry
* find_reloc_table_entry (char **);
2102 /* Directives: Data. */
2103 /* N.B. the support for relocation suffix in this directive needs to be
2104 implemented properly. */
2107 s_aarch64_cons (int nbytes
)
2111 #ifdef md_flush_pending_output
2112 md_flush_pending_output ();
2115 if (is_it_end_of_statement ())
2117 demand_empty_rest_of_line ();
2121 #ifdef md_cons_align
2122 md_cons_align (nbytes
);
2125 mapping_state (MAP_DATA
);
2128 struct reloc_table_entry
*reloc
;
2132 if (exp
.X_op
!= O_symbol
)
2133 emit_expr (&exp
, (unsigned int) nbytes
);
2136 skip_past_char (&input_line_pointer
, '#');
2137 if (skip_past_char (&input_line_pointer
, ':'))
2139 reloc
= find_reloc_table_entry (&input_line_pointer
);
2141 as_bad (_("unrecognized relocation suffix"));
2143 as_bad (_("unimplemented relocation suffix"));
2144 ignore_rest_of_line ();
2148 emit_expr (&exp
, (unsigned int) nbytes
);
2151 while (*input_line_pointer
++ == ',');
2153 /* Put terminator back into stream. */
2154 input_line_pointer
--;
2155 demand_empty_rest_of_line ();
2160 /* Forward declarations for functions below, in the MD interface
2162 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
2164 /* Mark symbol that it follows a variant PCS convention. */
2167 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
2173 elf_symbol_type
*elfsym
;
2175 c
= get_symbol_name (&name
);
2177 as_bad (_("Missing symbol name in directive"));
2178 sym
= symbol_find_or_make (name
);
2179 restore_line_pointer (c
);
2180 demand_empty_rest_of_line ();
2181 bfdsym
= symbol_get_bfdsym (sym
);
2182 elfsym
= elf_symbol_from (bfdsym
);
2183 gas_assert (elfsym
);
2184 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2186 #endif /* OBJ_ELF */
2188 /* Output a 32-bit word, but mark as an instruction. */
2191 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2196 #ifdef md_flush_pending_output
2197 md_flush_pending_output ();
2200 if (is_it_end_of_statement ())
2202 demand_empty_rest_of_line ();
2206 /* Sections are assumed to start aligned. In executable section, there is no
2207 MAP_DATA symbol pending. So we only align the address during
2208 MAP_DATA --> MAP_INSN transition.
2209 For other sections, this is not guaranteed. */
2210 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2211 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2212 frag_align_code (2, 0);
2215 mapping_state (MAP_INSN
);
2221 if (exp
.X_op
!= O_constant
)
2223 as_bad (_("constant expression required"));
2224 ignore_rest_of_line ();
2228 if (target_big_endian
)
2230 unsigned int val
= exp
.X_add_number
;
2231 exp
.X_add_number
= SWAP_32 (val
);
2233 emit_expr (&exp
, INSN_SIZE
);
2236 while (*input_line_pointer
++ == ',');
2238 dwarf2_emit_insn (n
* INSN_SIZE
);
2240 /* Put terminator back into stream. */
2241 input_line_pointer
--;
2242 demand_empty_rest_of_line ();
2246 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2248 demand_empty_rest_of_line ();
2249 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2250 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2254 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2257 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2263 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2264 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2266 demand_empty_rest_of_line ();
2269 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2272 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2276 /* Since we're just labelling the code, there's no need to define a
2279 /* Make sure there is enough room in this frag for the following
2280 blr. This trick only works if the blr follows immediately after
2281 the .tlsdesc directive. */
2283 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2284 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2286 demand_empty_rest_of_line ();
2289 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2292 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2298 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2299 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2301 demand_empty_rest_of_line ();
2303 #endif /* OBJ_ELF */
2307 s_secrel (int dummy ATTRIBUTE_UNUSED
)
2314 if (exp
.X_op
== O_symbol
)
2315 exp
.X_op
= O_secrel
;
2317 emit_expr (&exp
, 4);
2319 while (*input_line_pointer
++ == ',');
2321 input_line_pointer
--;
2322 demand_empty_rest_of_line ();
2326 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
2330 exp
.X_op
= O_secrel
;
2331 exp
.X_add_symbol
= symbol
;
2332 exp
.X_add_number
= 0;
2333 emit_expr (&exp
, size
);
2337 s_secidx (int dummy ATTRIBUTE_UNUSED
)
2344 if (exp
.X_op
== O_symbol
)
2345 exp
.X_op
= O_secidx
;
2347 emit_expr (&exp
, 2);
2349 while (*input_line_pointer
++ == ',');
2351 input_line_pointer
--;
2352 demand_empty_rest_of_line ();
2356 static void s_aarch64_arch (int);
2357 static void s_aarch64_cpu (int);
2358 static void s_aarch64_arch_extension (int);
2360 /* This table describes all the machine specific pseudo-ops the assembler
2361 has to support. The fields are:
2362 pseudo-op name without dot
2363 function to call to execute this pseudo-op
2364 Integer arg to pass to the function. */
2366 const pseudo_typeS md_pseudo_table
[] = {
2367 /* Never called because '.req' does not start a line. */
2369 {"unreq", s_unreq
, 0},
2371 {"even", s_even
, 0},
2372 {"ltorg", s_ltorg
, 0},
2373 {"pool", s_ltorg
, 0},
2374 {"cpu", s_aarch64_cpu
, 0},
2375 {"arch", s_aarch64_arch
, 0},
2376 {"arch_extension", s_aarch64_arch_extension
, 0},
2377 {"inst", s_aarch64_inst
, 0},
2378 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2380 {"tlsdescadd", s_tlsdescadd
, 0},
2381 {"tlsdesccall", s_tlsdesccall
, 0},
2382 {"tlsdescldr", s_tlsdescldr
, 0},
2383 {"variant_pcs", s_variant_pcs
, 0},
2385 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2386 {"word", s_aarch64_cons
, 4},
2387 {"long", s_aarch64_cons
, 4},
2388 {"xword", s_aarch64_cons
, 8},
2389 {"dword", s_aarch64_cons
, 8},
2392 {"secrel32", s_secrel
, 0},
2393 {"secidx", s_secidx
, 0},
2395 {"float16", float_cons
, 'h'},
2396 {"bfloat16", float_cons
, 'b'},
2401 /* Check whether STR points to a register name followed by a comma or the
2402 end of line; REG_TYPE indicates which register types are checked
2403 against. Return TRUE if STR is such a register name; otherwise return
2404 FALSE. The function does not intend to produce any diagnostics, but since
2405 the register parser aarch64_reg_parse, which is called by this function,
2406 does produce diagnostics, we call clear_error to clear any diagnostics
2407 that may be generated by aarch64_reg_parse.
2408 Also, the function returns FALSE directly if there is any user error
2409 present at the function entry. This prevents the existing diagnostics
2410 state from being spoiled.
2411 The function currently serves parse_constant_immediate and
2412 parse_big_immediate only. */
2414 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2416 const reg_entry
*reg
;
2418 /* Prevent the diagnostics state from being spoiled. */
2422 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
);
2424 /* Clear the parsing error that may be set by the reg parser. */
2430 skip_whitespace (str
);
2431 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2437 /* Parser functions used exclusively in instruction operands. */
2439 /* Parse an immediate expression which may not be constant.
2441 To prevent the expression parser from pushing a register name
2442 into the symbol table as an undefined symbol, firstly a check is
2443 done to find out whether STR is a register of type REG_TYPE followed
2444 by a comma or the end of line. Return FALSE if STR is such a string. */
2447 parse_immediate_expression (char **str
, expressionS
*exp
,
2448 aarch64_reg_type reg_type
)
2450 if (reg_name_p (*str
, reg_type
))
2452 set_recoverable_error (_("immediate operand required"));
2456 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2458 if (exp
->X_op
== O_absent
)
2460 set_fatal_syntax_error (_("missing immediate expression"));
2467 /* Constant immediate-value read function for use in insn parsing.
2468 STR points to the beginning of the immediate (with the optional
2469 leading #); *VAL receives the value. REG_TYPE says which register
2470 names should be treated as registers rather than as symbolic immediates.
2472 Return TRUE on success; otherwise return FALSE. */
2475 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2479 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2482 if (exp
.X_op
!= O_constant
)
2484 set_syntax_error (_("constant expression required"));
2488 *val
= exp
.X_add_number
;
2493 encode_imm_float_bits (uint32_t imm
)
2495 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2496 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2499 /* Return TRUE if the single-precision floating-point value encoded in IMM
2500 can be expressed in the AArch64 8-bit signed floating-point format with
2501 3-bit exponent and normalized 4 bits of precision; in other words, the
2502 floating-point value must be expressable as
2503 (+/-) n / 16 * power (2, r)
2504 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2507 aarch64_imm_float_p (uint32_t imm
)
2509 /* If a single-precision floating-point value has the following bit
2510 pattern, it can be expressed in the AArch64 8-bit floating-point
2513 3 32222222 2221111111111
2514 1 09876543 21098765432109876543210
2515 n Eeeeeexx xxxx0000000000000000000
2517 where n, e and each x are either 0 or 1 independently, with
2522 /* Prepare the pattern for 'Eeeeee'. */
2523 if (((imm
>> 30) & 0x1) == 0)
2524 pattern
= 0x3e000000;
2526 pattern
= 0x40000000;
2528 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2529 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2532 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2533 as an IEEE float without any loss of precision. Store the value in
2537 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2539 /* If a double-precision floating-point value has the following bit
2540 pattern, it can be expressed in a float:
2542 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2543 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2544 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2546 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2547 if Eeee_eeee != 1111_1111
2549 where n, e, s and S are either 0 or 1 independently and where ~ is the
2553 uint32_t high32
= imm
>> 32;
2554 uint32_t low32
= imm
;
2556 /* Lower 29 bits need to be 0s. */
2557 if ((imm
& 0x1fffffff) != 0)
2560 /* Prepare the pattern for 'Eeeeeeeee'. */
2561 if (((high32
>> 30) & 0x1) == 0)
2562 pattern
= 0x38000000;
2564 pattern
= 0x40000000;
2567 if ((high32
& 0x78000000) != pattern
)
2570 /* Check Eeee_eeee != 1111_1111. */
2571 if ((high32
& 0x7ff00000) == 0x47f00000)
2574 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2575 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2576 | (low32
>> 29)); /* 3 S bits. */
2580 /* Return true if we should treat OPERAND as a double-precision
2581 floating-point operand rather than a single-precision one. */
2583 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2585 /* Check for unsuffixed SVE registers, which are allowed
2586 for LDR and STR but not in instructions that require an
2587 immediate. We get better error messages if we arbitrarily
2588 pick one size, parse the immediate normally, and then
2589 report the match failure in the normal way. */
2590 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2591 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2594 /* Parse a floating-point immediate. Return TRUE on success and return the
2595 value in *IMMED in the format of IEEE754 single-precision encoding.
2596 *CCP points to the start of the string; DP_P is TRUE when the immediate
2597 is expected to be in double-precision (N.B. this only matters when
2598 hexadecimal representation is involved). REG_TYPE says which register
2599 names should be treated as registers rather than as symbolic immediates.
2601 This routine accepts any IEEE float; it is up to the callers to reject
2605 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2606 aarch64_reg_type reg_type
)
2610 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2612 unsigned fpword
= 0;
2615 skip_past_char (&str
, '#');
2618 skip_whitespace (fpnum
);
2620 if (startswith (fpnum
, "0x"))
2622 /* Support the hexadecimal representation of the IEEE754 encoding.
2623 Double-precision is expected when DP_P is TRUE, otherwise the
2624 representation should be in single-precision. */
2625 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2630 if (!can_convert_double_to_float (val
, &fpword
))
2633 else if ((uint64_t) val
> 0xffffffff)
2640 else if (reg_name_p (str
, reg_type
))
2642 set_recoverable_error (_("immediate operand required"));
2650 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2653 /* Our FP word must be 32 bits (single-precision FP). */
2654 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2656 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2666 set_fatal_syntax_error (_("invalid floating-point constant"));
2670 /* Less-generic immediate-value read function with the possibility of loading
2671 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2674 To prevent the expression parser from pushing a register name into the
2675 symbol table as an undefined symbol, a check is firstly done to find
2676 out whether STR is a register of type REG_TYPE followed by a comma or
2677 the end of line. Return FALSE if STR is such a register. */
2680 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2684 if (reg_name_p (ptr
, reg_type
))
2686 set_syntax_error (_("immediate operand required"));
2690 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2692 if (inst
.reloc
.exp
.X_op
== O_constant
)
2693 *imm
= inst
.reloc
.exp
.X_add_number
;
2700 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2701 if NEED_LIBOPCODES is non-zero, the fixup will need
2702 assistance from the libopcodes. */
2705 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2706 const aarch64_opnd_info
*operand
,
2707 int need_libopcodes_p
)
2709 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2710 reloc
->opnd
= operand
->type
;
2711 if (need_libopcodes_p
)
2712 reloc
->need_libopcodes_p
= 1;
2715 /* Return TRUE if the instruction needs to be fixed up later internally by
2716 the GAS; otherwise return FALSE. */
2719 aarch64_gas_internal_fixup_p (void)
2721 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2724 /* Assign the immediate value to the relevant field in *OPERAND if
2725 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2726 needs an internal fixup in a later stage.
2727 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2728 IMM.VALUE that may get assigned with the constant. */
2730 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2731 aarch64_opnd_info
*operand
,
2733 int need_libopcodes_p
,
2736 if (reloc
->exp
.X_op
== O_constant
)
2739 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2741 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2742 reloc
->type
= BFD_RELOC_UNUSED
;
2746 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2747 /* Tell libopcodes to ignore this operand or not. This is helpful
2748 when one of the operands needs to be fixed up later but we need
2749 libopcodes to check the other operands. */
2750 operand
->skip
= skip_p
;
2754 /* Relocation modifiers. Each entry in the table contains the textual
2755 name for the relocation which may be placed before a symbol used as
2756 a load/store offset, or add immediate. It must be surrounded by a
2757 leading and trailing colon, for example:
2759 ldr x0, [x1, #:rello:varsym]
2760 add x0, x1, #:rello:varsym */
2762 struct reloc_table_entry
2766 bfd_reloc_code_real_type adr_type
;
2767 bfd_reloc_code_real_type adrp_type
;
2768 bfd_reloc_code_real_type movw_type
;
2769 bfd_reloc_code_real_type add_type
;
2770 bfd_reloc_code_real_type ldst_type
;
2771 bfd_reloc_code_real_type ld_literal_type
;
2774 static struct reloc_table_entry reloc_table
[] =
2776 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2781 BFD_RELOC_AARCH64_ADD_LO12
,
2782 BFD_RELOC_AARCH64_LDST_LO12
,
2785 /* Higher 21 bits of pc-relative page offset: ADRP */
2788 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2794 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2797 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2803 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2807 BFD_RELOC_AARCH64_MOVW_G0
,
2812 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2816 BFD_RELOC_AARCH64_MOVW_G0_S
,
2821 /* Less significant bits 0-15 of address/value: MOVK, no check */
2825 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2830 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2834 BFD_RELOC_AARCH64_MOVW_G1
,
2839 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2843 BFD_RELOC_AARCH64_MOVW_G1_S
,
2848 /* Less significant bits 16-31 of address/value: MOVK, no check */
2852 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2857 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2861 BFD_RELOC_AARCH64_MOVW_G2
,
2866 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2870 BFD_RELOC_AARCH64_MOVW_G2_S
,
2875 /* Less significant bits 32-47 of address/value: MOVK, no check */
2879 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2884 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2888 BFD_RELOC_AARCH64_MOVW_G3
,
2893 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2897 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2902 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2906 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2911 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2915 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2920 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2924 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2929 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2933 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2938 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2942 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2947 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2951 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2956 /* Get to the page containing GOT entry for a symbol. */
2959 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2963 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2965 /* 12 bit offset into the page containing GOT entry for that symbol. */
2971 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2974 /* 0-15 bits of address/value: MOVk, no check. */
2978 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2983 /* Most significant bits 16-31 of address/value: MOVZ. */
2987 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2992 /* 15 bit offset into the page containing GOT entry for that symbol. */
2998 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
3001 /* Get to the page containing GOT TLS entry for a symbol */
3002 {"gottprel_g0_nc", 0,
3005 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
3010 /* Get to the page containing GOT TLS entry for a symbol */
3014 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
3019 /* Get to the page containing GOT TLS entry for a symbol */
3021 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
3022 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
3028 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3033 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
3037 /* Lower 16 bits address/value: MOVk. */
3041 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
3046 /* Most significant bits 16-31 of address/value: MOVZ. */
3050 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
3055 /* Get to the page containing GOT TLS entry for a symbol */
3057 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
3058 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
3062 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
3064 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3069 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
3070 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
3073 /* Get to the page containing GOT TLS entry for a symbol.
3074 The same as GD, we allocate two consecutive GOT slots
3075 for module index and module offset, the only difference
3076 with GD is the module offset should be initialized to
3077 zero without any outstanding runtime relocation. */
3079 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
3080 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
3086 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3087 {"tlsldm_lo12_nc", 0,
3091 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
3095 /* 12 bit offset into the module TLS base address. */
3100 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
3101 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
3104 /* Same as dtprel_lo12, no overflow check. */
3105 {"dtprel_lo12_nc", 0,
3109 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
3110 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
3113 /* bits[23:12] of offset to the module TLS base address. */
3118 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
3122 /* bits[15:0] of offset to the module TLS base address. */
3126 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
3131 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
3135 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
3140 /* bits[31:16] of offset to the module TLS base address. */
3144 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
3149 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
3153 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
3158 /* bits[47:32] of offset to the module TLS base address. */
3162 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
3167 /* Lower 16 bit offset into GOT entry for a symbol */
3168 {"tlsdesc_off_g0_nc", 0,
3171 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
3176 /* Higher 16 bit offset into GOT entry for a symbol */
3177 {"tlsdesc_off_g1", 0,
3180 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
3185 /* Get to the page containing GOT TLS entry for a symbol */
3188 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
3192 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
3194 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3195 {"gottprel_lo12", 0,
3200 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
3203 /* Get tp offset for a symbol. */
3208 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3212 /* Get tp offset for a symbol. */
3217 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3218 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
3221 /* Get tp offset for a symbol. */
3226 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
3230 /* Get tp offset for a symbol. */
3231 {"tprel_lo12_nc", 0,
3235 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
3236 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
3239 /* Most significant bits 32-47 of address/value: MOVZ. */
3243 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3248 /* Most significant bits 16-31 of address/value: MOVZ. */
3252 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3257 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3261 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3266 /* Most significant bits 0-15 of address/value: MOVZ. */
3270 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3275 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3279 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3284 /* 15bit offset from got entry to base address of GOT table. */
3290 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3293 /* 14bit offset from got entry to base address of GOT table. */
3299 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3303 /* Given the address of a pointer pointing to the textual name of a
3304 relocation as may appear in assembler source, attempt to find its
3305 details in reloc_table. The pointer will be updated to the character
3306 after the trailing colon. On failure, NULL will be returned;
3307 otherwise return the reloc_table_entry. */
3309 static struct reloc_table_entry
*
3310 find_reloc_table_entry (char **str
)
3313 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3315 int length
= strlen (reloc_table
[i
].name
);
3317 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3318 && (*str
)[length
] == ':')
3320 *str
+= (length
+ 1);
3321 return &reloc_table
[i
];
3328 /* Returns 0 if the relocation should never be forced,
3329 1 if the relocation must be forced, and -1 if either
3333 aarch64_force_reloc (unsigned int type
)
3337 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3338 /* Perform these "immediate" internal relocations
3339 even if the symbol is extern or weak. */
3342 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3343 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3344 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3345 /* Pseudo relocs that need to be fixed up according to
3349 case BFD_RELOC_AARCH64_ADD_LO12
:
3350 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3351 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3352 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3353 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3354 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3355 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3356 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3357 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3358 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3359 case BFD_RELOC_AARCH64_LDST128_LO12
:
3360 case BFD_RELOC_AARCH64_LDST16_LO12
:
3361 case BFD_RELOC_AARCH64_LDST32_LO12
:
3362 case BFD_RELOC_AARCH64_LDST64_LO12
:
3363 case BFD_RELOC_AARCH64_LDST8_LO12
:
3364 case BFD_RELOC_AARCH64_LDST_LO12
:
3365 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3366 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3367 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3368 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3369 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3370 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3371 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3372 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3373 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3374 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3375 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3376 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3377 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3378 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3379 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3380 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3381 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3382 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3383 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3384 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3385 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3386 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3387 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3388 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3389 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3390 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3391 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3392 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3393 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3394 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3395 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3396 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3397 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3398 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
:
3399 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
:
3400 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3401 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3402 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3403 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3404 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3405 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3406 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3407 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3408 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3409 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3410 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3411 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3412 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3413 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
:
3414 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
:
3415 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3416 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3417 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3418 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3419 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3420 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3421 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3422 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3423 /* Always leave these relocations for the linker. */
3432 aarch64_force_relocation (struct fix
*fixp
)
3434 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3437 return generic_force_reloc (fixp
);
3441 /* Mode argument to parse_shift and parser_shifter_operand. */
3442 enum parse_shift_mode
3444 SHIFTED_NONE
, /* no shifter allowed */
3445 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3447 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3449 SHIFTED_LSL
, /* bare "lsl #n" */
3450 SHIFTED_MUL
, /* bare "mul #n" */
3451 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3452 SHIFTED_MUL_VL
, /* "mul vl" */
3453 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3456 /* Parse a <shift> operator on an AArch64 data processing instruction.
3457 Return TRUE on success; otherwise return FALSE. */
3459 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3461 const struct aarch64_name_value_pair
*shift_op
;
3462 enum aarch64_modifier_kind kind
;
3468 for (p
= *str
; ISALPHA (*p
); p
++)
3473 set_syntax_error (_("shift expression expected"));
3477 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3479 if (shift_op
== NULL
)
3481 set_syntax_error (_("shift operator expected"));
3485 kind
= aarch64_get_operand_modifier (shift_op
);
3487 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3489 set_syntax_error (_("invalid use of 'MSL'"));
3493 if (kind
== AARCH64_MOD_MUL
3494 && mode
!= SHIFTED_MUL
3495 && mode
!= SHIFTED_MUL_VL
)
3497 set_syntax_error (_("invalid use of 'MUL'"));
3503 case SHIFTED_LOGIC_IMM
:
3504 if (aarch64_extend_operator_p (kind
))
3506 set_syntax_error (_("extending shift is not permitted"));
3511 case SHIFTED_ARITH_IMM
:
3512 if (kind
== AARCH64_MOD_ROR
)
3514 set_syntax_error (_("'ROR' shift is not permitted"));
3520 if (kind
!= AARCH64_MOD_LSL
)
3522 set_syntax_error (_("only 'LSL' shift is permitted"));
3528 if (kind
!= AARCH64_MOD_MUL
)
3530 set_syntax_error (_("only 'MUL' is permitted"));
3535 case SHIFTED_MUL_VL
:
3536 /* "MUL VL" consists of two separate tokens. Require the first
3537 token to be "MUL" and look for a following "VL". */
3538 if (kind
== AARCH64_MOD_MUL
)
3540 skip_whitespace (p
);
3541 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3544 kind
= AARCH64_MOD_MUL_VL
;
3548 set_syntax_error (_("only 'MUL VL' is permitted"));
3551 case SHIFTED_REG_OFFSET
:
3552 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3553 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3555 set_fatal_syntax_error
3556 (_("invalid shift for the register offset addressing mode"));
3561 case SHIFTED_LSL_MSL
:
3562 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3564 set_syntax_error (_("invalid shift operator"));
3573 /* Whitespace can appear here if the next thing is a bare digit. */
3574 skip_whitespace (p
);
3576 /* Parse shift amount. */
3578 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3579 exp
.X_op
= O_absent
;
3582 if (is_immediate_prefix (*p
))
3587 aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
);
3589 if (kind
== AARCH64_MOD_MUL_VL
)
3590 /* For consistency, give MUL VL the same shift amount as an implicit
3592 operand
->shifter
.amount
= 1;
3593 else if (exp
.X_op
== O_absent
)
3595 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3597 set_syntax_error (_("missing shift amount"));
3600 operand
->shifter
.amount
= 0;
3602 else if (exp
.X_op
!= O_constant
)
3604 set_syntax_error (_("constant shift amount required"));
3607 /* For parsing purposes, MUL #n has no inherent range. The range
3608 depends on the operand and will be checked by operand-specific
3610 else if (kind
!= AARCH64_MOD_MUL
3611 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3613 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3618 operand
->shifter
.amount
= exp
.X_add_number
;
3619 operand
->shifter
.amount_present
= 1;
3622 operand
->shifter
.operator_present
= 1;
3623 operand
->shifter
.kind
= kind
;
3629 /* Parse a <shifter_operand> for a data processing instruction:
3632 #<immediate>, LSL #imm
3634 Validation of immediate operands is deferred to md_apply_fix.
3636 Return TRUE on success; otherwise return FALSE. */
3639 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3640 enum parse_shift_mode mode
)
3644 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3649 /* Accept an immediate expression. */
3650 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3654 /* Accept optional LSL for arithmetic immediate values. */
3655 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3656 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3659 /* Not accept any shifter for logical immediate values. */
3660 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3661 && parse_shift (&p
, operand
, mode
))
3663 set_syntax_error (_("unexpected shift operator"));
3671 /* Parse a <shifter_operand> for a data processing instruction:
3676 #<immediate>, LSL #imm
3678 where <shift> is handled by parse_shift above, and the last two
3679 cases are handled by the function above.
3681 Validation of immediate operands is deferred to md_apply_fix.
3683 Return TRUE on success; otherwise return FALSE. */
3686 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3687 enum parse_shift_mode mode
)
3689 const reg_entry
*reg
;
3690 aarch64_opnd_qualifier_t qualifier
;
3691 enum aarch64_operand_class opd_class
3692 = aarch64_get_operand_class (operand
->type
);
3694 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3697 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3699 set_syntax_error (_("unexpected register in the immediate operand"));
3703 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_ZR
))
3705 set_expected_reg_error (REG_TYPE_R_ZR
, reg
, 0);
3709 operand
->reg
.regno
= reg
->number
;
3710 operand
->qualifier
= qualifier
;
3712 /* Accept optional shift operation on register. */
3713 if (! skip_past_comma (str
))
3716 if (! parse_shift (str
, operand
, mode
))
3721 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3724 (_("integer register expected in the extended/shifted operand "
3729 /* We have a shifted immediate variable. */
3730 return parse_shifter_operand_imm (str
, operand
, mode
);
3733 /* Return TRUE on success; return FALSE otherwise. */
3736 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3737 enum parse_shift_mode mode
)
3741 /* Determine if we have the sequence of characters #: or just :
3742 coming next. If we do, then we check for a :rello: relocation
3743 modifier. If we don't, punt the whole lot to
3744 parse_shifter_operand. */
3746 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3748 struct reloc_table_entry
*entry
;
3756 /* Try to parse a relocation. Anything else is an error. */
3757 if (!(entry
= find_reloc_table_entry (str
)))
3759 set_syntax_error (_("unknown relocation modifier"));
3763 if (entry
->add_type
== 0)
3766 (_("this relocation modifier is not allowed on this instruction"));
3770 /* Save str before we decompose it. */
3773 /* Next, we parse the expression. */
3774 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3778 /* Record the relocation type (use the ADD variant here). */
3779 inst
.reloc
.type
= entry
->add_type
;
3780 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3782 /* If str is empty, we've reached the end, stop here. */
3786 /* Otherwise, we have a shifted reloc modifier, so rewind to
3787 recover the variable name and continue parsing for the shifter. */
3789 return parse_shifter_operand_imm (str
, operand
, mode
);
3792 return parse_shifter_operand (str
, operand
, mode
);
3795 /* Parse all forms of an address expression. Information is written
3796 to *OPERAND and/or inst.reloc.
3798 The A64 instruction set has the following addressing modes:
3801 [base] // in SIMD ld/st structure
3802 [base{,#0}] // in ld/st exclusive
3804 [base,Xm{,LSL #imm}]
3805 [base,Xm,SXTX {#imm}]
3806 [base,Wm,(S|U)XTW {#imm}]
3808 [base]! // in ldraa/ldrab exclusive
3812 [base],Xm // in SIMD ld/st structure
3813 PC-relative (literal)
3817 [base,Zm.D{,LSL #imm}]
3818 [base,Zm.S,(S|U)XTW {#imm}]
3819 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3823 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3824 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3825 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3827 (As a convenience, the notation "=immediate" is permitted in conjunction
3828 with the pc-relative literal load instructions to automatically place an
3829 immediate value or symbolic address in a nearby literal pool and generate
3830 a hidden label which references it.)
3832 Upon a successful parsing, the address structure in *OPERAND will be
3833 filled in the following way:
3835 .base_regno = <base>
3836 .offset.is_reg // 1 if the offset is a register
3838 .offset.regno = <Rm>
3840 For different addressing modes defined in the A64 ISA:
3843 .pcrel=0; .preind=1; .postind=0; .writeback=0
3845 .pcrel=0; .preind=1; .postind=0; .writeback=1
3847 .pcrel=0; .preind=0; .postind=1; .writeback=1
3848 PC-relative (literal)
3849 .pcrel=1; .preind=1; .postind=0; .writeback=0
3851 The shift/extension information, if any, will be stored in .shifter.
3852 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3853 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3854 corresponding register.
3856 BASE_TYPE says which types of base register should be accepted and
3857 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3858 is the type of shifter that is allowed for immediate offsets,
3859 or SHIFTED_NONE if none.
3861 In all other respects, it is the caller's responsibility to check
3862 for addressing modes not supported by the instruction, and to set
3866 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3867 aarch64_opnd_qualifier_t
*base_qualifier
,
3868 aarch64_opnd_qualifier_t
*offset_qualifier
,
3869 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3870 enum parse_shift_mode imm_shift_mode
)
3873 const reg_entry
*reg
;
3874 expressionS
*exp
= &inst
.reloc
.exp
;
3876 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3877 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3878 if (! skip_past_char (&p
, '['))
3880 /* =immediate or label. */
3881 operand
->addr
.pcrel
= 1;
3882 operand
->addr
.preind
= 1;
3884 /* #:<reloc_op>:<symbol> */
3885 skip_past_char (&p
, '#');
3886 if (skip_past_char (&p
, ':'))
3888 bfd_reloc_code_real_type ty
;
3889 struct reloc_table_entry
*entry
;
3891 /* Try to parse a relocation modifier. Anything else is
3893 entry
= find_reloc_table_entry (&p
);
3896 set_syntax_error (_("unknown relocation modifier"));
3900 switch (operand
->type
)
3902 case AARCH64_OPND_ADDR_PCREL21
:
3904 ty
= entry
->adr_type
;
3908 ty
= entry
->ld_literal_type
;
3915 (_("this relocation modifier is not allowed on this "
3921 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3923 set_syntax_error (_("invalid relocation expression"));
3926 /* #:<reloc_op>:<expr> */
3927 /* Record the relocation type. */
3928 inst
.reloc
.type
= ty
;
3929 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3933 if (skip_past_char (&p
, '='))
3934 /* =immediate; need to generate the literal in the literal pool. */
3935 inst
.gen_lit_pool
= 1;
3937 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3939 set_syntax_error (_("invalid address"));
3950 bool alpha_base_p
= ISALPHA (*p
);
3951 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3952 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3955 && aarch64_check_reg_type (reg
, REG_TYPE_R_SP
)
3956 && *base_qualifier
== AARCH64_OPND_QLF_W
)
3957 set_syntax_error (_("expected a 64-bit base register"));
3958 else if (alpha_base_p
)
3959 set_syntax_error (_("invalid base register"));
3961 set_syntax_error (_("expected a base register"));
3964 operand
->addr
.base_regno
= reg
->number
;
3967 if (skip_past_comma (&p
))
3970 operand
->addr
.preind
= 1;
3972 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3975 if (!aarch64_check_reg_type (reg
, offset_type
))
3977 set_syntax_error (_("invalid offset register"));
3982 operand
->addr
.offset
.regno
= reg
->number
;
3983 operand
->addr
.offset
.is_reg
= 1;
3984 /* Shifted index. */
3985 if (skip_past_comma (&p
))
3988 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3989 /* Use the diagnostics set in parse_shift, so not set new
3990 error message here. */
3994 [base,Xm] # For vector plus scalar SVE2 indexing.
3995 [base,Xm{,LSL #imm}]
3996 [base,Xm,SXTX {#imm}]
3997 [base,Wm,(S|U)XTW {#imm}] */
3998 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3999 || operand
->shifter
.kind
== AARCH64_MOD_LSL
4000 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
4002 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
4004 set_syntax_error (_("invalid use of 32-bit register offset"));
4007 if (aarch64_get_qualifier_esize (*base_qualifier
)
4008 != aarch64_get_qualifier_esize (*offset_qualifier
)
4009 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
4010 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
4011 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
4013 set_syntax_error (_("offset has different size from base"));
4017 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
4019 set_syntax_error (_("invalid use of 64-bit register offset"));
4025 /* [Xn,#:<reloc_op>:<symbol> */
4026 skip_past_char (&p
, '#');
4027 if (skip_past_char (&p
, ':'))
4029 struct reloc_table_entry
*entry
;
4031 /* Try to parse a relocation modifier. Anything else is
4033 if (!(entry
= find_reloc_table_entry (&p
)))
4035 set_syntax_error (_("unknown relocation modifier"));
4039 if (entry
->ldst_type
== 0)
4042 (_("this relocation modifier is not allowed on this "
4047 /* [Xn,#:<reloc_op>: */
4048 /* We now have the group relocation table entry corresponding to
4049 the name in the assembler source. Next, we parse the
4051 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4053 set_syntax_error (_("invalid relocation expression"));
4057 /* [Xn,#:<reloc_op>:<expr> */
4058 /* Record the load/store relocation type. */
4059 inst
.reloc
.type
= entry
->ldst_type
;
4060 inst
.reloc
.pc_rel
= entry
->pc_rel
;
4064 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
4066 set_syntax_error (_("invalid expression in the address"));
4070 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
4071 /* [Xn,<expr>,<shifter> */
4072 if (! parse_shift (&p
, operand
, imm_shift_mode
))
4078 if (! skip_past_char (&p
, ']'))
4080 set_syntax_error (_("']' expected"));
4084 if (skip_past_char (&p
, '!'))
4086 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
4088 set_syntax_error (_("register offset not allowed in pre-indexed "
4089 "addressing mode"));
4093 operand
->addr
.writeback
= 1;
4095 else if (skip_past_comma (&p
))
4098 operand
->addr
.postind
= 1;
4099 operand
->addr
.writeback
= 1;
4101 if (operand
->addr
.preind
)
4103 set_syntax_error (_("cannot combine pre- and post-indexing"));
4107 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
4111 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4113 set_syntax_error (_("invalid offset register"));
4117 operand
->addr
.offset
.regno
= reg
->number
;
4118 operand
->addr
.offset
.is_reg
= 1;
4120 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
4123 set_syntax_error (_("invalid expression in the address"));
4128 /* If at this point neither .preind nor .postind is set, we have a
4129 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
4130 ldrab, accept [Rn] as a shorthand for [Rn,#0].
4131 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
4133 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
4135 if (operand
->addr
.writeback
)
4137 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
4139 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
4140 operand
->addr
.offset
.is_reg
= 0;
4141 operand
->addr
.offset
.imm
= 0;
4142 operand
->addr
.preind
= 1;
4147 set_syntax_error (_("missing offset in the pre-indexed address"));
4153 operand
->addr
.preind
= 1;
4154 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
4156 operand
->addr
.offset
.is_reg
= 1;
4157 operand
->addr
.offset
.regno
= REG_ZR
;
4158 *offset_qualifier
= AARCH64_OPND_QLF_X
;
4162 inst
.reloc
.exp
.X_op
= O_constant
;
4163 inst
.reloc
.exp
.X_add_number
= 0;
4172 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
4175 parse_address (char **str
, aarch64_opnd_info
*operand
)
4177 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
4178 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
4179 REG_TYPE_R64_SP
, REG_TYPE_R_ZR
, SHIFTED_NONE
);
4182 /* Parse an address in which SVE vector registers and MUL VL are allowed.
4183 The arguments have the same meaning as for parse_address_main.
4184 Return TRUE on success. */
4186 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
4187 aarch64_opnd_qualifier_t
*base_qualifier
,
4188 aarch64_opnd_qualifier_t
*offset_qualifier
)
4190 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
4191 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
4195 /* Parse a register X0-X30. The register must be 64-bit and register 31
4198 parse_x0_to_x30 (char **str
, aarch64_opnd_info
*operand
)
4200 const reg_entry
*reg
= parse_reg (str
);
4201 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4203 set_expected_reg_error (REG_TYPE_R_64
, reg
, 0);
4206 operand
->reg
.regno
= reg
->number
;
4207 operand
->qualifier
= AARCH64_OPND_QLF_X
;
4211 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
4212 Return TRUE on success; otherwise return FALSE. */
4214 parse_half (char **str
, int *internal_fixup_p
)
4218 skip_past_char (&p
, '#');
4220 gas_assert (internal_fixup_p
);
4221 *internal_fixup_p
= 0;
4225 struct reloc_table_entry
*entry
;
4227 /* Try to parse a relocation. Anything else is an error. */
4230 if (!(entry
= find_reloc_table_entry (&p
)))
4232 set_syntax_error (_("unknown relocation modifier"));
4236 if (entry
->movw_type
== 0)
4239 (_("this relocation modifier is not allowed on this instruction"));
4243 inst
.reloc
.type
= entry
->movw_type
;
4246 *internal_fixup_p
= 1;
4248 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4255 /* Parse an operand for an ADRP instruction:
4257 Return TRUE on success; otherwise return FALSE. */
4260 parse_adrp (char **str
)
4267 struct reloc_table_entry
*entry
;
4269 /* Try to parse a relocation. Anything else is an error. */
4271 if (!(entry
= find_reloc_table_entry (&p
)))
4273 set_syntax_error (_("unknown relocation modifier"));
4277 if (entry
->adrp_type
== 0)
4280 (_("this relocation modifier is not allowed on this instruction"));
4284 inst
.reloc
.type
= entry
->adrp_type
;
4287 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4289 inst
.reloc
.pc_rel
= 1;
4290 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4296 /* Miscellaneous. */
4298 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4299 of SIZE tokens in which index I gives the token for field value I,
4300 or is null if field value I is invalid. REG_TYPE says which register
4301 names should be treated as registers rather than as symbolic immediates.
4303 Return true on success, moving *STR past the operand and storing the
4304 field value in *VAL. */
4307 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4308 size_t size
, aarch64_reg_type reg_type
)
4314 /* Match C-like tokens. */
4316 while (ISALNUM (*q
))
4319 for (i
= 0; i
< size
; ++i
)
4321 && strncasecmp (array
[i
], p
, q
- p
) == 0
4322 && array
[i
][q
- p
] == 0)
4329 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4332 if (exp
.X_op
== O_constant
4333 && (uint64_t) exp
.X_add_number
< size
)
4335 *val
= exp
.X_add_number
;
4340 /* Use the default error for this operand. */
4344 /* Parse an option for a preload instruction. Returns the encoding for the
4345 option, or PARSE_FAIL. */
4348 parse_pldop (char **str
)
4351 const struct aarch64_name_value_pair
*o
;
4354 while (ISALNUM (*q
))
4357 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4365 /* Parse an option for a barrier instruction. Returns the encoding for the
4366 option, or PARSE_FAIL. */
4369 parse_barrier (char **str
)
4372 const struct aarch64_name_value_pair
*o
;
4375 while (ISALPHA (*q
))
4378 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4386 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4387 return 0 if successful. Otherwise return PARSE_FAIL. */
4390 parse_barrier_psb (char **str
,
4391 const struct aarch64_name_value_pair
** hint_opt
)
4394 const struct aarch64_name_value_pair
*o
;
4397 while (ISALPHA (*q
))
4400 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4403 set_fatal_syntax_error
4404 ( _("unknown or missing option to PSB/TSB"));
4408 if (o
->value
!= 0x11)
4410 /* PSB only accepts option name 'CSYNC'. */
4412 (_("the specified option is not accepted for PSB/TSB"));
4421 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4422 return 0 if successful. Otherwise return PARSE_FAIL. */
4425 parse_bti_operand (char **str
,
4426 const struct aarch64_name_value_pair
** hint_opt
)
4429 const struct aarch64_name_value_pair
*o
;
4432 while (ISALPHA (*q
))
4435 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4438 set_fatal_syntax_error
4439 ( _("unknown option to BTI"));
4445 /* Valid BTI operands. */
4453 (_("unknown option to BTI"));
4462 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4463 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4468 Side effect: Update STR with current parse position of success.
4470 FLAGS is as for parse_typed_reg. */
4472 static const reg_entry
*
4473 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4474 aarch64_opnd_qualifier_t
*qualifier
, unsigned int flags
)
4476 struct vector_type_el vectype
;
4477 const reg_entry
*reg
= parse_typed_reg (str
, reg_type
, &vectype
,
4478 PTR_FULL_REG
| flags
);
4482 if (vectype
.type
== NT_invtype
)
4483 *qualifier
= AARCH64_OPND_QLF_NIL
;
4486 *qualifier
= vectype_to_qualifier (&vectype
);
4487 if (*qualifier
== AARCH64_OPND_QLF_NIL
)
4494 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4499 Function return TRUE if immediate was found, or FALSE.
4502 parse_sme_immediate (char **str
, int64_t *imm
)
4505 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4512 /* Parse index with selection register and immediate offset:
4517 Return true on success, populating OPND with the parsed index. */
4520 parse_sme_za_index (char **str
, struct aarch64_indexed_za
*opnd
)
4522 const reg_entry
*reg
;
4524 if (!skip_past_char (str
, '['))
4526 set_syntax_error (_("expected '['"));
4530 /* The selection register, encoded in the 2-bit Rv field. */
4531 reg
= parse_reg (str
);
4532 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
)
4534 set_syntax_error (_("expected a 32-bit selection register"));
4537 opnd
->index
.regno
= reg
->number
;
4539 if (!skip_past_char (str
, ','))
4541 set_syntax_error (_("missing immediate offset"));
4545 if (!parse_sme_immediate (str
, &opnd
->index
.imm
))
4547 set_syntax_error (_("expected a constant immediate offset"));
4551 if (!skip_past_char (str
, ']'))
4553 set_syntax_error (_("expected ']'"));
4560 /* Parse a register of type REG_TYPE that might have an element type
4561 qualifier and that is indexed by two values: a 32-bit register,
4562 followed by an immediate. The ranges of the register and the
4563 immediate vary by opcode and are checked in libopcodes.
4565 Return true on success, populating OPND with information about
4566 the operand and setting QUALIFIER to the register qualifier.
4568 Field format examples:
4570 <Pm>.<T>[<Wv>< #<imm>]
4572 <ZAn><HV>.<T>[<Wv>, #<imm>]
4574 FLAGS is as for parse_typed_reg. */
4577 parse_dual_indexed_reg (char **str
, aarch64_reg_type reg_type
,
4578 struct aarch64_indexed_za
*opnd
,
4579 aarch64_opnd_qualifier_t
*qualifier
,
4582 const reg_entry
*reg
= parse_reg_with_qual (str
, reg_type
, qualifier
, flags
);
4586 opnd
->v
= aarch64_check_reg_type (reg
, REG_TYPE_ZATV
);
4587 opnd
->regno
= reg
->number
;
4589 return parse_sme_za_index (str
, opnd
);
4592 /* Like parse_sme_za_hv_tiles_operand, but expect braces around the
4596 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4597 struct aarch64_indexed_za
*opnd
,
4598 aarch64_opnd_qualifier_t
*qualifier
)
4600 if (!skip_past_char (str
, '{'))
4602 set_expected_reglist_error (REG_TYPE_ZATHV
, parse_reg (str
));
4606 if (!parse_dual_indexed_reg (str
, REG_TYPE_ZATHV
, opnd
, qualifier
,
4610 if (!skip_past_char (str
, '}'))
4612 set_syntax_error (_("expected '}'"));
4619 /* Parse list of up to eight 64-bit element tile names separated by commas in
4620 SME's ZERO instruction:
4624 Function returns <mask>:
4626 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4629 parse_sme_zero_mask(char **str
)
4633 aarch64_opnd_qualifier_t qualifier
;
4634 unsigned int ptr_flags
= PTR_IN_REGLIST
;
4640 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZA_ZAT
,
4641 &qualifier
, ptr_flags
);
4645 if (reg
->type
== REG_TYPE_ZA
)
4647 if (qualifier
!= AARCH64_OPND_QLF_NIL
)
4649 set_syntax_error ("ZA should not have a size suffix");
4652 /* { ZA } is assembled as all-ones immediate. */
4657 int regno
= reg
->number
;
4658 if (qualifier
== AARCH64_OPND_QLF_S_B
)
4660 /* { ZA0.B } is assembled as all-ones immediate. */
4663 else if (qualifier
== AARCH64_OPND_QLF_S_H
)
4664 mask
|= 0x55 << regno
;
4665 else if (qualifier
== AARCH64_OPND_QLF_S_S
)
4666 mask
|= 0x11 << regno
;
4667 else if (qualifier
== AARCH64_OPND_QLF_S_D
)
4668 mask
|= 0x01 << regno
;
4669 else if (qualifier
== AARCH64_OPND_QLF_S_Q
)
4671 set_syntax_error (_("ZA tile masks do not operate at .Q"
4675 else if (qualifier
== AARCH64_OPND_QLF_NIL
)
4677 set_syntax_error (_("missing ZA tile size"));
4682 set_syntax_error (_("invalid ZA tile"));
4686 ptr_flags
|= PTR_GOOD_MATCH
;
4688 while (skip_past_char (&q
, ','));
4694 /* Wraps in curly braces <mask> operand ZERO instruction:
4698 Function returns value of <mask> bit-field.
4701 parse_sme_list_of_64bit_tiles (char **str
)
4705 if (!skip_past_char (str
, '{'))
4707 set_syntax_error (_("expected '{'"));
4711 /* Empty <mask> list is an all-zeros immediate. */
4712 if (!skip_past_char (str
, '}'))
4714 regno
= parse_sme_zero_mask (str
);
4715 if (regno
== PARSE_FAIL
)
4718 if (!skip_past_char (str
, '}'))
4720 set_syntax_error (_("expected '}'"));
4730 /* Parse streaming mode operand for SMSTART and SMSTOP.
4734 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4737 parse_sme_sm_za (char **str
)
4742 while (ISALPHA (*q
))
4746 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4748 set_syntax_error (_("expected SM or ZA operand"));
4753 return TOLOWER (p
[0]);
4756 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4757 Returns the encoding for the option, or PARSE_FAIL.
4759 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4760 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4762 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4763 field, otherwise as a system register.
4767 parse_sys_reg (char **str
, htab_t sys_regs
,
4768 int imple_defined_p
, int pstatefield_p
,
4772 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4773 const aarch64_sys_reg
*o
;
4777 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4778 if (p
< buf
+ (sizeof (buf
) - 1))
4779 *p
++ = TOLOWER (*q
);
4782 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4783 valid system register. This is enforced by construction of the hash
4785 if (p
- buf
!= q
- *str
)
4788 o
= str_hash_find (sys_regs
, buf
);
4791 if (!imple_defined_p
)
4795 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4796 unsigned int op0
, op1
, cn
, cm
, op2
;
4798 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4801 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4803 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4810 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4811 as_bad (_("selected processor does not support PSTATE field "
4814 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4815 o
->value
, o
->flags
, o
->features
))
4816 as_bad (_("selected processor does not support system register "
4818 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4819 as_warn (_("system register name '%s' is deprecated and may be "
4820 "removed in a future release"), buf
);
4830 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4831 for the option, or NULL. */
4833 static const aarch64_sys_ins_reg
*
4834 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4837 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4838 const aarch64_sys_ins_reg
*o
;
4841 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4842 if (p
< buf
+ (sizeof (buf
) - 1))
4843 *p
++ = TOLOWER (*q
);
4846 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4847 valid system register. This is enforced by construction of the hash
4849 if (p
- buf
!= q
- *str
)
4852 o
= str_hash_find (sys_ins_regs
, buf
);
4856 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4857 o
->name
, o
->value
, o
->flags
, 0))
4858 as_bad (_("selected processor does not support system register "
4860 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4861 as_warn (_("system register name '%s' is deprecated and may be "
4862 "removed in a future release"), buf
);
4868 #define po_char_or_fail(chr) do { \
4869 if (! skip_past_char (&str, chr)) \
4873 #define po_reg_or_fail(regtype) do { \
4874 reg = aarch64_reg_parse (&str, regtype, NULL); \
4879 #define po_int_fp_reg_or_fail(reg_type) do { \
4880 reg = parse_reg (&str); \
4881 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4883 set_expected_reg_error (reg_type, reg, 0); \
4886 info->reg.regno = reg->number; \
4887 info->qualifier = inherent_reg_qualifier (reg); \
4890 #define po_imm_nc_or_fail() do { \
4891 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4895 #define po_imm_or_fail(min, max) do { \
4896 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4898 if (val < min || val > max) \
4900 set_fatal_syntax_error (_("immediate value out of range "\
4901 #min " to "#max)); \
4906 #define po_enum_or_fail(array) do { \
4907 if (!parse_enum_string (&str, &val, array, \
4908 ARRAY_SIZE (array), imm_reg_type)) \
4912 #define po_misc_or_fail(expr) do { \
4917 /* A primitive log calculator. */
4919 static inline unsigned int
4920 get_log2 (unsigned int n
)
4922 unsigned int count
= 0;
4931 /* encode the 12-bit imm field of Add/sub immediate */
4932 static inline uint32_t
4933 encode_addsub_imm (uint32_t imm
)
4938 /* encode the shift amount field of Add/sub immediate */
4939 static inline uint32_t
4940 encode_addsub_imm_shift_amount (uint32_t cnt
)
4946 /* encode the imm field of Adr instruction */
4947 static inline uint32_t
4948 encode_adr_imm (uint32_t imm
)
4950 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4951 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4954 /* encode the immediate field of Move wide immediate */
4955 static inline uint32_t
4956 encode_movw_imm (uint32_t imm
)
4961 /* encode the 26-bit offset of unconditional branch */
4962 static inline uint32_t
4963 encode_branch_ofs_26 (uint32_t ofs
)
4965 return ofs
& ((1 << 26) - 1);
4968 /* encode the 19-bit offset of conditional branch and compare & branch */
4969 static inline uint32_t
4970 encode_cond_branch_ofs_19 (uint32_t ofs
)
4972 return (ofs
& ((1 << 19) - 1)) << 5;
4975 /* encode the 19-bit offset of ld literal */
4976 static inline uint32_t
4977 encode_ld_lit_ofs_19 (uint32_t ofs
)
4979 return (ofs
& ((1 << 19) - 1)) << 5;
4982 /* Encode the 14-bit offset of test & branch. */
4983 static inline uint32_t
4984 encode_tst_branch_ofs_14 (uint32_t ofs
)
4986 return (ofs
& ((1 << 14) - 1)) << 5;
4989 /* Encode the 16-bit imm field of svc/hvc/smc. */
4990 static inline uint32_t
4991 encode_svc_imm (uint32_t imm
)
4996 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4997 static inline uint32_t
4998 reencode_addsub_switch_add_sub (uint32_t opcode
)
5000 return opcode
^ (1 << 30);
5003 static inline uint32_t
5004 reencode_movzn_to_movz (uint32_t opcode
)
5006 return opcode
| (1 << 30);
5009 static inline uint32_t
5010 reencode_movzn_to_movn (uint32_t opcode
)
5012 return opcode
& ~(1 << 30);
5015 /* Overall per-instruction processing. */
5017 /* We need to be able to fix up arbitrary expressions in some statements.
5018 This is so that we can handle symbols that are an arbitrary distance from
5019 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
5020 which returns part of an address in a form which will be valid for
5021 a data instruction. We do this by pushing the expression into a symbol
5022 in the expr_section, and creating a fix for that. */
5025 fix_new_aarch64 (fragS
* frag
,
5040 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
5044 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
5051 /* Diagnostics on operands errors. */
5053 /* By default, output verbose error message.
5054 Disable the verbose error message by -mno-verbose-error. */
5055 static int verbose_error_p
= 1;
5057 #ifdef DEBUG_AARCH64
5058 /* N.B. this is only for the purpose of debugging. */
5059 const char* operand_mismatch_kind_names
[] =
5062 "AARCH64_OPDE_RECOVERABLE",
5063 "AARCH64_OPDE_A_SHOULD_FOLLOW_B",
5064 "AARCH64_OPDE_EXPECTED_A_AFTER_B",
5065 "AARCH64_OPDE_SYNTAX_ERROR",
5066 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5067 "AARCH64_OPDE_INVALID_VARIANT",
5068 "AARCH64_OPDE_REG_LIST",
5069 "AARCH64_OPDE_UNTIED_IMMS",
5070 "AARCH64_OPDE_UNTIED_OPERAND",
5071 "AARCH64_OPDE_OUT_OF_RANGE",
5072 "AARCH64_OPDE_UNALIGNED",
5073 "AARCH64_OPDE_OTHER_ERROR",
5074 "AARCH64_OPDE_INVALID_REGNO",
5076 #endif /* DEBUG_AARCH64 */
5078 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5080 When multiple errors of different kinds are found in the same assembly
5081 line, only the error of the highest severity will be picked up for
5082 issuing the diagnostics. */
5085 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5086 enum aarch64_operand_error_kind rhs
)
5088 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5089 gas_assert (AARCH64_OPDE_A_SHOULD_FOLLOW_B
> AARCH64_OPDE_RECOVERABLE
);
5090 gas_assert (AARCH64_OPDE_EXPECTED_A_AFTER_B
> AARCH64_OPDE_RECOVERABLE
);
5091 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_A_SHOULD_FOLLOW_B
);
5092 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_EXPECTED_A_AFTER_B
);
5093 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5094 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5095 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_INVALID_VARIANT
);
5096 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_REG_LIST
);
5097 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5098 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
5099 gas_assert (AARCH64_OPDE_INVALID_REGNO
> AARCH64_OPDE_OTHER_ERROR
);
5103 /* Helper routine to get the mnemonic name from the assembly instruction
5104 line; should only be called for the diagnosis purpose, as there is
5105 string copy operation involved, which may affect the runtime
5106 performance if used in elsewhere. */
5109 get_mnemonic_name (const char *str
)
5111 static char mnemonic
[32];
5114 /* Get the first 15 bytes and assume that the full name is included. */
5115 strncpy (mnemonic
, str
, 31);
5116 mnemonic
[31] = '\0';
5118 /* Scan up to the end of the mnemonic, which must end in white space,
5119 '.', or end of string. */
5120 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5125 /* Append '...' to the truncated long name. */
5126 if (ptr
- mnemonic
== 31)
5127 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5133 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5135 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5136 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5139 /* Data structures storing one user error in the assembly code related to
5142 struct operand_error_record
5144 const aarch64_opcode
*opcode
;
5145 aarch64_operand_error detail
;
5146 struct operand_error_record
*next
;
5149 typedef struct operand_error_record operand_error_record
;
5151 struct operand_errors
5153 operand_error_record
*head
;
5154 operand_error_record
*tail
;
5157 typedef struct operand_errors operand_errors
;
5159 /* Top-level data structure reporting user errors for the current line of
5161 The way md_assemble works is that all opcodes sharing the same mnemonic
5162 name are iterated to find a match to the assembly line. In this data
5163 structure, each of the such opcodes will have one operand_error_record
5164 allocated and inserted. In other words, excessive errors related with
5165 a single opcode are disregarded. */
5166 operand_errors operand_error_report
;
5168 /* Free record nodes. */
5169 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5171 /* Initialize the data structure that stores the operand mismatch
5172 information on assembling one line of the assembly code. */
5174 init_operand_error_report (void)
5176 if (operand_error_report
.head
!= NULL
)
5178 gas_assert (operand_error_report
.tail
!= NULL
);
5179 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5180 free_opnd_error_record_nodes
= operand_error_report
.head
;
5181 operand_error_report
.head
= NULL
;
5182 operand_error_report
.tail
= NULL
;
5185 gas_assert (operand_error_report
.tail
== NULL
);
5188 /* Return TRUE if some operand error has been recorded during the
5189 parsing of the current assembly line using the opcode *OPCODE;
5190 otherwise return FALSE. */
5192 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5194 operand_error_record
*record
= operand_error_report
.head
;
5195 return record
&& record
->opcode
== opcode
;
5198 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5199 OPCODE field is initialized with OPCODE.
5200 N.B. only one record for each opcode, i.e. the maximum of one error is
5201 recorded for each instruction template. */
5204 add_operand_error_record (const operand_error_record
* new_record
)
5206 const aarch64_opcode
*opcode
= new_record
->opcode
;
5207 operand_error_record
* record
= operand_error_report
.head
;
5209 /* The record may have been created for this opcode. If not, we need
5211 if (! opcode_has_operand_error_p (opcode
))
5213 /* Get one empty record. */
5214 if (free_opnd_error_record_nodes
== NULL
)
5216 record
= XNEW (operand_error_record
);
5220 record
= free_opnd_error_record_nodes
;
5221 free_opnd_error_record_nodes
= record
->next
;
5223 record
->opcode
= opcode
;
5224 /* Insert at the head. */
5225 record
->next
= operand_error_report
.head
;
5226 operand_error_report
.head
= record
;
5227 if (operand_error_report
.tail
== NULL
)
5228 operand_error_report
.tail
= record
;
5230 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5231 && record
->detail
.index
<= new_record
->detail
.index
5232 && operand_error_higher_severity_p (record
->detail
.kind
,
5233 new_record
->detail
.kind
))
5235 /* In the case of multiple errors found on operands related with a
5236 single opcode, only record the error of the leftmost operand and
5237 only if the error is of higher severity. */
5238 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5239 " the existing error %s on operand %d",
5240 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5241 new_record
->detail
.index
,
5242 operand_mismatch_kind_names
[record
->detail
.kind
],
5243 record
->detail
.index
);
5247 record
->detail
= new_record
->detail
;
5251 record_operand_error_info (const aarch64_opcode
*opcode
,
5252 aarch64_operand_error
*error_info
)
5254 operand_error_record record
;
5255 record
.opcode
= opcode
;
5256 record
.detail
= *error_info
;
5257 add_operand_error_record (&record
);
5260 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5261 error message *ERROR, for operand IDX (count from 0). */
5264 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5265 enum aarch64_operand_error_kind kind
,
5268 aarch64_operand_error info
;
5269 memset(&info
, 0, sizeof (info
));
5273 info
.non_fatal
= false;
5274 record_operand_error_info (opcode
, &info
);
5278 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5279 enum aarch64_operand_error_kind kind
,
5280 const char* error
, const int *extra_data
)
5282 aarch64_operand_error info
;
5286 info
.data
[0].i
= extra_data
[0];
5287 info
.data
[1].i
= extra_data
[1];
5288 info
.data
[2].i
= extra_data
[2];
5289 info
.non_fatal
= false;
5290 record_operand_error_info (opcode
, &info
);
5294 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5295 const char* error
, int lower_bound
,
5298 int data
[3] = {lower_bound
, upper_bound
, 0};
5299 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5303 /* Remove the operand error record for *OPCODE. */
5304 static void ATTRIBUTE_UNUSED
5305 remove_operand_error_record (const aarch64_opcode
*opcode
)
5307 if (opcode_has_operand_error_p (opcode
))
5309 operand_error_record
* record
= operand_error_report
.head
;
5310 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5311 operand_error_report
.head
= record
->next
;
5312 record
->next
= free_opnd_error_record_nodes
;
5313 free_opnd_error_record_nodes
= record
;
5314 if (operand_error_report
.head
== NULL
)
5316 gas_assert (operand_error_report
.tail
== record
);
5317 operand_error_report
.tail
= NULL
;
5322 /* Given the instruction in *INSTR, return the index of the best matched
5323 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5325 Return -1 if there is no qualifier sequence; return the first match
5326 if there is multiple matches found. */
5329 find_best_match (const aarch64_inst
*instr
,
5330 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5332 int i
, num_opnds
, max_num_matched
, idx
;
5334 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5337 DEBUG_TRACE ("no operand");
5341 max_num_matched
= 0;
5344 /* For each pattern. */
5345 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5348 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5350 /* Most opcodes has much fewer patterns in the list. */
5351 if (empty_qualifier_sequence_p (qualifiers
))
5353 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5357 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5358 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5361 if (num_matched
> max_num_matched
)
5363 max_num_matched
= num_matched
;
5368 DEBUG_TRACE ("return with %d", idx
);
5372 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5373 corresponding operands in *INSTR. */
5376 assign_qualifier_sequence (aarch64_inst
*instr
,
5377 const aarch64_opnd_qualifier_t
*qualifiers
)
5380 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5381 gas_assert (num_opnds
);
5382 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5383 instr
->operands
[i
].qualifier
= *qualifiers
;
5386 /* Callback used by aarch64_print_operand to apply STYLE to the
5387 disassembler output created from FMT and ARGS. The STYLER object holds
5388 any required state. Must return a pointer to a string (created from FMT
5389 and ARGS) that will continue to be valid until the complete disassembled
5390 instruction has been printed.
5392 We don't currently add any styling to the output of the disassembler as
5393 used within assembler error messages, and so STYLE is ignored here. A
5394 new string is allocated on the obstack help within STYLER and returned
5397 static const char *aarch64_apply_style
5398 (struct aarch64_styler
*styler
,
5399 enum disassembler_style style ATTRIBUTE_UNUSED
,
5400 const char *fmt
, va_list args
)
5404 struct obstack
*stack
= (struct obstack
*) styler
->state
;
5407 /* Calculate the required space. */
5409 res
= vsnprintf (NULL
, 0, fmt
, ap
);
5411 gas_assert (res
>= 0);
5413 /* Allocate space on the obstack and format the result. */
5414 ptr
= (char *) obstack_alloc (stack
, res
+ 1);
5415 res
= vsnprintf (ptr
, (res
+ 1), fmt
, args
);
5416 gas_assert (res
>= 0);
5421 /* Print operands for the diagnosis purpose. */
5424 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5425 const aarch64_opnd_info
*opnds
)
5428 struct aarch64_styler styler
;
5429 struct obstack content
;
5430 obstack_init (&content
);
5432 styler
.apply_style
= aarch64_apply_style
;
5433 styler
.state
= (void *) &content
;
5435 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5440 /* We regard the opcode operand info more, however we also look into
5441 the inst->operands to support the disassembling of the optional
5443 The two operand code should be the same in all cases, apart from
5444 when the operand can be optional. */
5445 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5446 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5449 /* Generate the operand string in STR. */
5450 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5451 NULL
, cmt
, sizeof (cmt
), cpu_variant
, &styler
);
5455 strcat (buf
, i
== 0 ? " " : ", ");
5457 /* Append the operand string. */
5460 /* Append a comment. This works because only the last operand ever
5461 adds a comment. If that ever changes then we'll need to be
5465 strcat (buf
, "\t// ");
5470 obstack_free (&content
, NULL
);
5473 /* Send to stderr a string as information. */
5476 output_info (const char *format
, ...)
5482 file
= as_where (&line
);
5486 fprintf (stderr
, "%s:%u: ", file
, line
);
5488 fprintf (stderr
, "%s: ", file
);
5490 fprintf (stderr
, _("Info: "));
5491 va_start (args
, format
);
5492 vfprintf (stderr
, format
, args
);
5494 (void) putc ('\n', stderr
);
5497 /* See if the AARCH64_OPDE_SYNTAX_ERROR error described by DETAIL
5498 relates to registers or register lists. If so, return a string that
5499 reports the error against "operand %d", otherwise return null. */
5502 get_reg_error_message (const aarch64_operand_error
*detail
)
5504 /* Handle the case where we found a register that was expected
5505 to be in a register list outside of a register list. */
5506 if ((detail
->data
[1].i
& detail
->data
[2].i
) != 0
5507 && (detail
->data
[1].i
& SEF_IN_REGLIST
) == 0)
5508 return _("missing braces at operand %d");
5510 /* If some opcodes expected a register, and we found a register,
5511 complain about the difference. */
5512 if (detail
->data
[2].i
)
5514 unsigned int expected
= (detail
->data
[1].i
& SEF_IN_REGLIST
5515 ? detail
->data
[1].i
& ~SEF_IN_REGLIST
5516 : detail
->data
[0].i
& ~SEF_DEFAULT_ERROR
);
5517 const char *msg
= get_reg_expected_msg (expected
, detail
->data
[2].i
);
5519 msg
= N_("unexpected register type at operand %d");
5523 /* Handle the case where we got to the point of trying to parse a
5524 register within a register list, but didn't find a known register. */
5525 if (detail
->data
[1].i
& SEF_IN_REGLIST
)
5527 unsigned int expected
= detail
->data
[1].i
& ~SEF_IN_REGLIST
;
5528 const char *msg
= get_reg_expected_msg (expected
, 0);
5530 msg
= _("invalid register list at operand %d");
5534 /* Punt if register-related problems weren't the only errors. */
5535 if (detail
->data
[0].i
& SEF_DEFAULT_ERROR
)
5538 /* Handle the case where the only acceptable things are registers. */
5539 if (detail
->data
[1].i
== 0)
5541 const char *msg
= get_reg_expected_msg (detail
->data
[0].i
, 0);
5543 msg
= _("expected a register at operand %d");
5547 /* Handle the case where the only acceptable things are register lists,
5548 and there was no opening '{'. */
5549 if (detail
->data
[0].i
== 0)
5550 return _("expected '{' at operand %d");
5552 return _("expected a register or register list at operand %d");
5555 /* Output one operand error record. */
5558 output_operand_error_record (const operand_error_record
*record
, char *str
)
5560 const aarch64_operand_error
*detail
= &record
->detail
;
5561 int idx
= detail
->index
;
5562 const aarch64_opcode
*opcode
= record
->opcode
;
5563 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5564 : AARCH64_OPND_NIL
);
5566 typedef void (*handler_t
)(const char *format
, ...);
5567 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5568 const char *msg
= detail
->error
;
5570 switch (detail
->kind
)
5572 case AARCH64_OPDE_NIL
:
5576 case AARCH64_OPDE_A_SHOULD_FOLLOW_B
:
5577 handler (_("this `%s' should have an immediately preceding `%s'"
5579 detail
->data
[0].s
, detail
->data
[1].s
, str
);
5582 case AARCH64_OPDE_EXPECTED_A_AFTER_B
:
5583 handler (_("the preceding `%s' should be followed by `%s` rather"
5584 " than `%s` -- `%s'"),
5585 detail
->data
[1].s
, detail
->data
[0].s
, opcode
->name
, str
);
5588 case AARCH64_OPDE_SYNTAX_ERROR
:
5589 if (!msg
&& idx
>= 0)
5591 msg
= get_reg_error_message (detail
);
5594 char *full_msg
= xasprintf (msg
, idx
+ 1);
5595 handler (_("%s -- `%s'"), full_msg
, str
);
5602 case AARCH64_OPDE_RECOVERABLE
:
5603 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5604 case AARCH64_OPDE_OTHER_ERROR
:
5605 /* Use the prepared error message if there is, otherwise use the
5606 operand description string to describe the error. */
5610 handler (_("%s -- `%s'"), msg
, str
);
5612 handler (_("%s at operand %d -- `%s'"),
5617 gas_assert (idx
>= 0);
5618 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5619 aarch64_get_operand_desc (opd_code
), str
);
5623 case AARCH64_OPDE_INVALID_VARIANT
:
5624 handler (_("operand mismatch -- `%s'"), str
);
5625 if (verbose_error_p
)
5627 /* We will try to correct the erroneous instruction and also provide
5628 more information e.g. all other valid variants.
5630 The string representation of the corrected instruction and other
5631 valid variants are generated by
5633 1) obtaining the intermediate representation of the erroneous
5635 2) manipulating the IR, e.g. replacing the operand qualifier;
5636 3) printing out the instruction by calling the printer functions
5637 shared with the disassembler.
5639 The limitation of this method is that the exact input assembly
5640 line cannot be accurately reproduced in some cases, for example an
5641 optional operand present in the actual assembly line will be
5642 omitted in the output; likewise for the optional syntax rules,
5643 e.g. the # before the immediate. Another limitation is that the
5644 assembly symbols and relocation operations in the assembly line
5645 currently cannot be printed out in the error report. Last but not
5646 least, when there is other error(s) co-exist with this error, the
5647 'corrected' instruction may be still incorrect, e.g. given
5648 'ldnp h0,h1,[x0,#6]!'
5649 this diagnosis will provide the version:
5650 'ldnp s0,s1,[x0,#6]!'
5651 which is still not right. */
5652 size_t len
= strlen (get_mnemonic_name (str
));
5656 aarch64_inst
*inst_base
= &inst
.base
;
5657 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5660 reset_aarch64_instruction (&inst
);
5661 inst_base
->opcode
= opcode
;
5663 /* Reset the error report so that there is no side effect on the
5664 following operand parsing. */
5665 init_operand_error_report ();
5668 result
= parse_operands (str
+ len
, opcode
)
5669 && programmer_friendly_fixup (&inst
);
5670 gas_assert (result
);
5671 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5672 NULL
, NULL
, insn_sequence
);
5673 gas_assert (!result
);
5675 /* Find the most matched qualifier sequence. */
5676 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5677 gas_assert (qlf_idx
> -1);
5679 /* Assign the qualifiers. */
5680 assign_qualifier_sequence (inst_base
,
5681 opcode
->qualifiers_list
[qlf_idx
]);
5683 /* Print the hint. */
5684 output_info (_(" did you mean this?"));
5685 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5686 print_operands (buf
, opcode
, inst_base
->operands
);
5687 output_info (_(" %s"), buf
);
5689 /* Print out other variant(s) if there is any. */
5691 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5692 output_info (_(" other valid variant(s):"));
5694 /* For each pattern. */
5695 qualifiers_list
= opcode
->qualifiers_list
;
5696 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5698 /* Most opcodes has much fewer patterns in the list.
5699 First NIL qualifier indicates the end in the list. */
5700 if (empty_qualifier_sequence_p (*qualifiers_list
))
5705 /* Mnemonics name. */
5706 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5708 /* Assign the qualifiers. */
5709 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5711 /* Print instruction. */
5712 print_operands (buf
, opcode
, inst_base
->operands
);
5714 output_info (_(" %s"), buf
);
5720 case AARCH64_OPDE_UNTIED_IMMS
:
5721 handler (_("operand %d must have the same immediate value "
5722 "as operand 1 -- `%s'"),
5723 detail
->index
+ 1, str
);
5726 case AARCH64_OPDE_UNTIED_OPERAND
:
5727 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5728 detail
->index
+ 1, str
);
5731 case AARCH64_OPDE_INVALID_REGNO
:
5732 handler (_("%s%d-%s%d expected at operand %d -- `%s'"),
5733 detail
->data
[0].s
, detail
->data
[1].i
,
5734 detail
->data
[0].s
, detail
->data
[2].i
, idx
+ 1, str
);
5737 case AARCH64_OPDE_OUT_OF_RANGE
:
5738 if (detail
->data
[0].i
!= detail
->data
[1].i
)
5739 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5740 msg
? msg
: _("immediate value"),
5741 detail
->data
[0].i
, detail
->data
[1].i
, idx
+ 1, str
);
5743 handler (_("%s must be %d at operand %d -- `%s'"),
5744 msg
? msg
: _("immediate value"),
5745 detail
->data
[0].i
, idx
+ 1, str
);
5748 case AARCH64_OPDE_REG_LIST
:
5749 if (detail
->data
[0].i
== (1 << 1))
5750 handler (_("expected a single-register list at operand %d -- `%s'"),
5752 else if ((detail
->data
[0].i
& -detail
->data
[0].i
) == detail
->data
[0].i
)
5753 handler (_("expected a list of %d registers at operand %d -- `%s'"),
5754 get_log2 (detail
->data
[0].i
), idx
+ 1, str
);
5756 handler (_("invalid number of registers in the list"
5757 " at operand %d -- `%s'"), idx
+ 1, str
);
5760 case AARCH64_OPDE_UNALIGNED
:
5761 handler (_("immediate value must be a multiple of "
5762 "%d at operand %d -- `%s'"),
5763 detail
->data
[0].i
, idx
+ 1, str
);
5772 /* Return true if the presence of error A against an instruction means
5773 that error B should not be reported. This is only used as a first pass,
5774 to pick the kind of error that we should report. */
5777 better_error_p (operand_error_record
*a
, operand_error_record
*b
)
5779 /* For errors reported during parsing, prefer errors that relate to
5780 later operands, since that implies that the earlier operands were
5781 syntactically valid.
5783 For example, if we see a register R instead of an immediate in
5784 operand N, we'll report that as a recoverable "immediate operand
5785 required" error. This is because there is often another opcode
5786 entry that accepts a register operand N, and any errors about R
5787 should be reported against the register forms of the instruction.
5788 But if no such register form exists, the recoverable error should
5789 still win over a syntax error against operand N-1.
5791 For these purposes, count an error reported at the end of the
5792 assembly string as equivalent to an error reported against the
5793 final operand. This means that opcode entries that expect more
5794 operands win over "unexpected characters following instruction". */
5795 if (a
->detail
.kind
<= AARCH64_OPDE_FATAL_SYNTAX_ERROR
5796 && b
->detail
.kind
<= AARCH64_OPDE_FATAL_SYNTAX_ERROR
)
5798 int a_index
= (a
->detail
.index
< 0
5799 ? aarch64_num_of_operands (a
->opcode
) - 1
5801 int b_index
= (b
->detail
.index
< 0
5802 ? aarch64_num_of_operands (b
->opcode
) - 1
5804 if (a_index
!= b_index
)
5805 return a_index
> b_index
;
5807 return operand_error_higher_severity_p (a
->detail
.kind
, b
->detail
.kind
);
5810 /* Process and output the error message about the operand mismatching.
5812 When this function is called, the operand error information had
5813 been collected for an assembly line and there will be multiple
5814 errors in the case of multiple instruction templates; output the
5815 error message that most closely describes the problem.
5817 The errors to be printed can be filtered on printing all errors
5818 or only non-fatal errors. This distinction has to be made because
5819 the error buffer may already be filled with fatal errors we don't want to
5820 print due to the different instruction templates. */
5823 output_operand_error_report (char *str
, bool non_fatal_only
)
5825 enum aarch64_operand_error_kind kind
;
5826 operand_error_record
*curr
;
5827 operand_error_record
*head
= operand_error_report
.head
;
5828 operand_error_record
*record
;
5830 /* No error to report. */
5834 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5836 /* Only one error. */
5837 if (head
== operand_error_report
.tail
)
5839 /* If the only error is a non-fatal one and we don't want to print it,
5841 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5843 DEBUG_TRACE ("single opcode entry with error kind: %s",
5844 operand_mismatch_kind_names
[head
->detail
.kind
]);
5845 output_operand_error_record (head
, str
);
5850 /* Find the error kind of the highest severity. */
5851 DEBUG_TRACE ("multiple opcode entries with error kind");
5853 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5855 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5856 if (curr
->detail
.kind
== AARCH64_OPDE_SYNTAX_ERROR
)
5858 DEBUG_TRACE ("\t%s [%x, %x, %x]",
5859 operand_mismatch_kind_names
[curr
->detail
.kind
],
5860 curr
->detail
.data
[0].i
, curr
->detail
.data
[1].i
,
5861 curr
->detail
.data
[2].i
);
5863 else if (curr
->detail
.kind
== AARCH64_OPDE_REG_LIST
)
5865 DEBUG_TRACE ("\t%s [%x]",
5866 operand_mismatch_kind_names
[curr
->detail
.kind
],
5867 curr
->detail
.data
[0].i
);
5871 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5873 if ((!non_fatal_only
|| curr
->detail
.non_fatal
)
5874 && (!record
|| better_error_p (curr
, record
)))
5878 kind
= (record
? record
->detail
.kind
: AARCH64_OPDE_NIL
);
5879 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5881 /* Pick up one of errors of KIND to report. */
5883 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5885 /* If we don't want to print non-fatal errors then don't consider them
5887 if (curr
->detail
.kind
!= kind
5888 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5890 /* If there are multiple errors, pick up the one with the highest
5891 mismatching operand index. In the case of multiple errors with
5892 the equally highest operand index, pick up the first one or the
5893 first one with non-NULL error message. */
5894 if (!record
|| curr
->detail
.index
> record
->detail
.index
)
5896 else if (curr
->detail
.index
== record
->detail
.index
5897 && !record
->detail
.error
)
5899 if (curr
->detail
.error
)
5901 else if (kind
== AARCH64_OPDE_SYNTAX_ERROR
)
5903 record
->detail
.data
[0].i
|= curr
->detail
.data
[0].i
;
5904 record
->detail
.data
[1].i
|= curr
->detail
.data
[1].i
;
5905 record
->detail
.data
[2].i
|= curr
->detail
.data
[2].i
;
5906 DEBUG_TRACE ("\t--> %s [%x, %x, %x]",
5907 operand_mismatch_kind_names
[kind
],
5908 curr
->detail
.data
[0].i
, curr
->detail
.data
[1].i
,
5909 curr
->detail
.data
[2].i
);
5911 else if (kind
== AARCH64_OPDE_REG_LIST
)
5913 record
->detail
.data
[0].i
|= curr
->detail
.data
[0].i
;
5914 DEBUG_TRACE ("\t--> %s [%x]",
5915 operand_mismatch_kind_names
[kind
],
5916 curr
->detail
.data
[0].i
);
5918 /* Pick the variant with the cloest match. */
5919 else if (kind
== AARCH64_OPDE_INVALID_VARIANT
5920 && record
->detail
.data
[0].i
> curr
->detail
.data
[0].i
)
5925 /* The way errors are collected in the back-end is a bit non-intuitive. But
5926 essentially, because each operand template is tried recursively you may
5927 always have errors collected from the previous tried OPND. These are
5928 usually skipped if there is one successful match. However now with the
5929 non-fatal errors we have to ignore those previously collected hard errors
5930 when we're only interested in printing the non-fatal ones. This condition
5931 prevents us from printing errors that are not appropriate, since we did
5932 match a condition, but it also has warnings that it wants to print. */
5933 if (non_fatal_only
&& !record
)
5936 gas_assert (record
);
5937 DEBUG_TRACE ("Pick up error kind %s to report",
5938 operand_mismatch_kind_names
[kind
]);
5941 output_operand_error_record (record
, str
);
5944 /* Write an AARCH64 instruction to buf - always little-endian. */
5946 put_aarch64_insn (char *buf
, uint32_t insn
)
5948 unsigned char *where
= (unsigned char *) buf
;
5950 where
[1] = insn
>> 8;
5951 where
[2] = insn
>> 16;
5952 where
[3] = insn
>> 24;
5956 get_aarch64_insn (char *buf
)
5958 unsigned char *where
= (unsigned char *) buf
;
5960 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5961 | ((uint32_t) where
[3] << 24)));
5966 output_inst (struct aarch64_inst
*new_inst
)
5970 to
= frag_more (INSN_SIZE
);
5972 frag_now
->tc_frag_data
.recorded
= 1;
5974 put_aarch64_insn (to
, inst
.base
.value
);
5976 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5978 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5979 INSN_SIZE
, &inst
.reloc
.exp
,
5982 DEBUG_TRACE ("Prepared relocation fix up");
5983 /* Don't check the addend value against the instruction size,
5984 that's the job of our code in md_apply_fix(). */
5985 fixp
->fx_no_overflow
= 1;
5986 if (new_inst
!= NULL
)
5987 fixp
->tc_fix_data
.inst
= new_inst
;
5988 if (aarch64_gas_internal_fixup_p ())
5990 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5991 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5992 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5996 dwarf2_emit_insn (INSN_SIZE
);
5999 /* Link together opcodes of the same name. */
6003 const aarch64_opcode
*opcode
;
6004 struct templates
*next
;
6007 typedef struct templates templates
;
6010 lookup_mnemonic (const char *start
, int len
)
6012 templates
*templ
= NULL
;
6014 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
6018 /* Subroutine of md_assemble, responsible for looking up the primary
6019 opcode from the mnemonic the user wrote. BASE points to the beginning
6020 of the mnemonic, DOT points to the first '.' within the mnemonic
6021 (if any) and END points to the end of the mnemonic. */
6024 opcode_lookup (char *base
, char *dot
, char *end
)
6026 const aarch64_cond
*cond
;
6033 inst
.cond
= COND_ALWAYS
;
6035 /* Handle a possible condition. */
6038 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
6041 inst
.cond
= cond
->value
;
6047 if (inst
.cond
== COND_ALWAYS
)
6049 /* Look for unaffixed mnemonic. */
6050 return lookup_mnemonic (base
, len
);
6054 /* append ".c" to mnemonic if conditional */
6055 memcpy (condname
, base
, len
);
6056 memcpy (condname
+ len
, ".c", 2);
6059 return lookup_mnemonic (base
, len
);
6065 /* Process an optional operand that is found omitted from the assembly line.
6066 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
6067 instruction's opcode entry while IDX is the index of this omitted operand.
6071 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
6072 int idx
, aarch64_opnd_info
*operand
)
6074 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
6075 gas_assert (optional_operand_p (opcode
, idx
));
6076 gas_assert (!operand
->present
);
6080 case AARCH64_OPND_Rd
:
6081 case AARCH64_OPND_Rn
:
6082 case AARCH64_OPND_Rm
:
6083 case AARCH64_OPND_Rt
:
6084 case AARCH64_OPND_Rt2
:
6085 case AARCH64_OPND_Rt_LS64
:
6086 case AARCH64_OPND_Rt_SP
:
6087 case AARCH64_OPND_Rs
:
6088 case AARCH64_OPND_Ra
:
6089 case AARCH64_OPND_Rt_SYS
:
6090 case AARCH64_OPND_Rd_SP
:
6091 case AARCH64_OPND_Rn_SP
:
6092 case AARCH64_OPND_Rm_SP
:
6093 case AARCH64_OPND_Fd
:
6094 case AARCH64_OPND_Fn
:
6095 case AARCH64_OPND_Fm
:
6096 case AARCH64_OPND_Fa
:
6097 case AARCH64_OPND_Ft
:
6098 case AARCH64_OPND_Ft2
:
6099 case AARCH64_OPND_Sd
:
6100 case AARCH64_OPND_Sn
:
6101 case AARCH64_OPND_Sm
:
6102 case AARCH64_OPND_Va
:
6103 case AARCH64_OPND_Vd
:
6104 case AARCH64_OPND_Vn
:
6105 case AARCH64_OPND_Vm
:
6106 case AARCH64_OPND_VdD1
:
6107 case AARCH64_OPND_VnD1
:
6108 operand
->reg
.regno
= default_value
;
6111 case AARCH64_OPND_Ed
:
6112 case AARCH64_OPND_En
:
6113 case AARCH64_OPND_Em
:
6114 case AARCH64_OPND_Em16
:
6115 case AARCH64_OPND_SM3_IMM2
:
6116 operand
->reglane
.regno
= default_value
;
6119 case AARCH64_OPND_IDX
:
6120 case AARCH64_OPND_BIT_NUM
:
6121 case AARCH64_OPND_IMMR
:
6122 case AARCH64_OPND_IMMS
:
6123 case AARCH64_OPND_SHLL_IMM
:
6124 case AARCH64_OPND_IMM_VLSL
:
6125 case AARCH64_OPND_IMM_VLSR
:
6126 case AARCH64_OPND_CCMP_IMM
:
6127 case AARCH64_OPND_FBITS
:
6128 case AARCH64_OPND_UIMM4
:
6129 case AARCH64_OPND_UIMM3_OP1
:
6130 case AARCH64_OPND_UIMM3_OP2
:
6131 case AARCH64_OPND_IMM
:
6132 case AARCH64_OPND_IMM_2
:
6133 case AARCH64_OPND_WIDTH
:
6134 case AARCH64_OPND_UIMM7
:
6135 case AARCH64_OPND_NZCV
:
6136 case AARCH64_OPND_SVE_PATTERN
:
6137 case AARCH64_OPND_SVE_PRFOP
:
6138 operand
->imm
.value
= default_value
;
6141 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6142 operand
->imm
.value
= default_value
;
6143 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
6144 operand
->shifter
.amount
= 1;
6147 case AARCH64_OPND_EXCEPTION
:
6148 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6151 case AARCH64_OPND_BARRIER_ISB
:
6152 operand
->barrier
= aarch64_barrier_options
+ default_value
;
6155 case AARCH64_OPND_BTI_TARGET
:
6156 operand
->hint_option
= aarch64_hint_options
+ default_value
;
6164 /* Process the relocation type for move wide instructions.
6165 Return TRUE on success; otherwise return FALSE. */
6168 process_movw_reloc_info (void)
6173 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
6175 if (inst
.base
.opcode
->op
== OP_MOVK
)
6176 switch (inst
.reloc
.type
)
6178 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6179 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6180 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6181 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6182 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6183 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6184 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6185 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6186 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6187 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6188 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6190 (_("the specified relocation type is not allowed for MOVK"));
6196 switch (inst
.reloc
.type
)
6198 case BFD_RELOC_AARCH64_MOVW_G0
:
6199 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6200 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6201 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6202 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6203 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6204 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6205 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6206 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6207 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6208 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6209 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6210 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6213 case BFD_RELOC_AARCH64_MOVW_G1
:
6214 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6215 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6216 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6217 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6218 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6219 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6220 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6221 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6222 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6223 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6224 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6225 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6228 case BFD_RELOC_AARCH64_MOVW_G2
:
6229 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6230 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6231 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6232 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6233 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6234 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6237 set_fatal_syntax_error
6238 (_("the specified relocation type is not allowed for 32-bit "
6244 case BFD_RELOC_AARCH64_MOVW_G3
:
6245 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6248 set_fatal_syntax_error
6249 (_("the specified relocation type is not allowed for 32-bit "
6256 /* More cases should be added when more MOVW-related relocation types
6257 are supported in GAS. */
6258 gas_assert (aarch64_gas_internal_fixup_p ());
6259 /* The shift amount should have already been set by the parser. */
6262 inst
.base
.operands
[1].shifter
.amount
= shift
;
6266 /* Determine and return the real reloc type code for an instruction
6267 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6269 static inline bfd_reloc_code_real_type
6270 ldst_lo12_determine_real_reloc_type (void)
6272 unsigned logsz
, max_logsz
;
6273 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6274 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6276 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6278 BFD_RELOC_AARCH64_LDST8_LO12
,
6279 BFD_RELOC_AARCH64_LDST16_LO12
,
6280 BFD_RELOC_AARCH64_LDST32_LO12
,
6281 BFD_RELOC_AARCH64_LDST64_LO12
,
6282 BFD_RELOC_AARCH64_LDST128_LO12
6285 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6286 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6287 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6288 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6289 BFD_RELOC_AARCH64_NONE
6292 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6293 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6294 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6295 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6296 BFD_RELOC_AARCH64_NONE
6299 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6300 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6301 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6302 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6303 BFD_RELOC_AARCH64_NONE
6306 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6307 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6308 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6309 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6310 BFD_RELOC_AARCH64_NONE
6314 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6315 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6317 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6319 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6321 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6322 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6324 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6326 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6328 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6330 logsz
= get_log2 (aarch64_get_qualifier_esize (opd1_qlf
));
6332 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6333 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6334 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6335 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6340 if (logsz
> max_logsz
)
6342 /* SEE PR 27904 for an example of this. */
6343 set_fatal_syntax_error
6344 (_("relocation qualifier does not match instruction size"));
6345 return BFD_RELOC_AARCH64_NONE
;
6348 /* In reloc.c, these pseudo relocation types should be defined in similar
6349 order as above reloc_ldst_lo12 array. Because the array index calculation
6350 below relies on this. */
6351 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6354 /* Check whether a register list REGINFO is valid. The registers must be
6355 numbered in increasing order (modulo 32), in increments of one or two.
6357 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
6360 Return FALSE if such a register list is invalid, otherwise return TRUE. */
6363 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
6365 uint32_t i
, nb_regs
, prev_regno
, incr
;
6367 nb_regs
= 1 + (reginfo
& 0x3);
6369 prev_regno
= reginfo
& 0x1f;
6370 incr
= accept_alternate
? 2 : 1;
6372 for (i
= 1; i
< nb_regs
; ++i
)
6374 uint32_t curr_regno
;
6376 curr_regno
= reginfo
& 0x1f;
6377 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
6379 prev_regno
= curr_regno
;
6385 /* Generic instruction operand parser. This does no encoding and no
6386 semantic validation; it merely squirrels values away in the inst
6387 structure. Returns TRUE or FALSE depending on whether the
6388 specified grammar matched. */
6391 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6394 char *backtrack_pos
= 0;
6395 const enum aarch64_opnd
*operands
= opcode
->operands
;
6396 aarch64_reg_type imm_reg_type
;
6399 skip_whitespace (str
);
6401 if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode
->avariant
,
6403 | AARCH64_FEATURE_SVE2
))
6404 imm_reg_type
= REG_TYPE_R_ZR_SP_BHSDQ_VZP
;
6406 imm_reg_type
= REG_TYPE_R_ZR_BHSDQ_V
;
6408 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6411 const reg_entry
*reg
;
6412 int comma_skipped_p
= 0;
6413 struct vector_type_el vectype
;
6414 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6415 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6416 aarch64_reg_type reg_type
;
6418 DEBUG_TRACE ("parse operand %d", i
);
6420 /* Assign the operand code. */
6421 info
->type
= operands
[i
];
6423 if (optional_operand_p (opcode
, i
))
6425 /* Remember where we are in case we need to backtrack. */
6426 gas_assert (!backtrack_pos
);
6427 backtrack_pos
= str
;
6430 /* Expect comma between operands; the backtrack mechanism will take
6431 care of cases of omitted optional operand. */
6432 if (i
> 0 && ! skip_past_char (&str
, ','))
6434 set_syntax_error (_("comma expected between operands"));
6438 comma_skipped_p
= 1;
6440 switch (operands
[i
])
6442 case AARCH64_OPND_Rd
:
6443 case AARCH64_OPND_Rn
:
6444 case AARCH64_OPND_Rm
:
6445 case AARCH64_OPND_Rt
:
6446 case AARCH64_OPND_Rt2
:
6447 case AARCH64_OPND_Rs
:
6448 case AARCH64_OPND_Ra
:
6449 case AARCH64_OPND_Rt_LS64
:
6450 case AARCH64_OPND_Rt_SYS
:
6451 case AARCH64_OPND_PAIRREG
:
6452 case AARCH64_OPND_SVE_Rm
:
6453 po_int_fp_reg_or_fail (REG_TYPE_R_ZR
);
6455 /* In LS64 load/store instructions Rt register number must be even
6457 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6459 /* We've already checked if this is valid register.
6460 This will check if register number (Rt) is not undefined for LS64
6462 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6463 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6465 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6471 case AARCH64_OPND_Rd_SP
:
6472 case AARCH64_OPND_Rn_SP
:
6473 case AARCH64_OPND_Rt_SP
:
6474 case AARCH64_OPND_SVE_Rn_SP
:
6475 case AARCH64_OPND_Rm_SP
:
6476 po_int_fp_reg_or_fail (REG_TYPE_R_SP
);
6479 case AARCH64_OPND_Rm_EXT
:
6480 case AARCH64_OPND_Rm_SFT
:
6481 po_misc_or_fail (parse_shifter_operand
6482 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6484 : SHIFTED_LOGIC_IMM
)));
6485 if (!info
->shifter
.operator_present
)
6487 /* Default to LSL if not present. Libopcodes prefers shifter
6488 kind to be explicit. */
6489 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6490 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6491 /* For Rm_EXT, libopcodes will carry out further check on whether
6492 or not stack pointer is used in the instruction (Recall that
6493 "the extend operator is not optional unless at least one of
6494 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6498 case AARCH64_OPND_Fd
:
6499 case AARCH64_OPND_Fn
:
6500 case AARCH64_OPND_Fm
:
6501 case AARCH64_OPND_Fa
:
6502 case AARCH64_OPND_Ft
:
6503 case AARCH64_OPND_Ft2
:
6504 case AARCH64_OPND_Sd
:
6505 case AARCH64_OPND_Sn
:
6506 case AARCH64_OPND_Sm
:
6507 case AARCH64_OPND_SVE_VZn
:
6508 case AARCH64_OPND_SVE_Vd
:
6509 case AARCH64_OPND_SVE_Vm
:
6510 case AARCH64_OPND_SVE_Vn
:
6511 po_int_fp_reg_or_fail (REG_TYPE_BHSDQ
);
6514 case AARCH64_OPND_SVE_Pd
:
6515 case AARCH64_OPND_SVE_Pg3
:
6516 case AARCH64_OPND_SVE_Pg4_5
:
6517 case AARCH64_OPND_SVE_Pg4_10
:
6518 case AARCH64_OPND_SVE_Pg4_16
:
6519 case AARCH64_OPND_SVE_Pm
:
6520 case AARCH64_OPND_SVE_Pn
:
6521 case AARCH64_OPND_SVE_Pt
:
6522 case AARCH64_OPND_SME_Pm
:
6523 reg_type
= REG_TYPE_P
;
6526 case AARCH64_OPND_SVE_Za_5
:
6527 case AARCH64_OPND_SVE_Za_16
:
6528 case AARCH64_OPND_SVE_Zd
:
6529 case AARCH64_OPND_SVE_Zm_5
:
6530 case AARCH64_OPND_SVE_Zm_16
:
6531 case AARCH64_OPND_SVE_Zn
:
6532 case AARCH64_OPND_SVE_Zt
:
6533 reg_type
= REG_TYPE_Z
;
6536 case AARCH64_OPND_Va
:
6537 case AARCH64_OPND_Vd
:
6538 case AARCH64_OPND_Vn
:
6539 case AARCH64_OPND_Vm
:
6540 reg_type
= REG_TYPE_V
;
6542 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6545 if (vectype
.defined
& NTA_HASINDEX
)
6548 info
->reg
.regno
= reg
->number
;
6549 if ((reg_type
== REG_TYPE_P
|| reg_type
== REG_TYPE_Z
)
6550 && vectype
.type
== NT_invtype
)
6551 /* Unqualified P and Z registers are allowed in certain
6552 contexts. Rely on F_STRICT qualifier checking to catch
6554 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6557 info
->qualifier
= vectype_to_qualifier (&vectype
);
6558 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6563 case AARCH64_OPND_VdD1
:
6564 case AARCH64_OPND_VnD1
:
6565 reg
= aarch64_reg_parse (&str
, REG_TYPE_V
, &vectype
);
6568 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6570 set_fatal_syntax_error
6571 (_("the top half of a 128-bit FP/SIMD register is expected"));
6574 info
->reg
.regno
= reg
->number
;
6575 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6576 here; it is correct for the purpose of encoding/decoding since
6577 only the register number is explicitly encoded in the related
6578 instructions, although this appears a bit hacky. */
6579 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6582 case AARCH64_OPND_SVE_Zm3_INDEX
:
6583 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6584 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6585 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6586 case AARCH64_OPND_SVE_Zm4_INDEX
:
6587 case AARCH64_OPND_SVE_Zn_INDEX
:
6588 reg_type
= REG_TYPE_Z
;
6589 goto vector_reg_index
;
6591 case AARCH64_OPND_Ed
:
6592 case AARCH64_OPND_En
:
6593 case AARCH64_OPND_Em
:
6594 case AARCH64_OPND_Em16
:
6595 case AARCH64_OPND_SM3_IMM2
:
6596 reg_type
= REG_TYPE_V
;
6598 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6601 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6604 info
->reglane
.regno
= reg
->number
;
6605 info
->reglane
.index
= vectype
.index
;
6606 info
->qualifier
= vectype_to_qualifier (&vectype
);
6607 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6611 case AARCH64_OPND_SVE_ZnxN
:
6612 case AARCH64_OPND_SVE_ZtxN
:
6613 reg_type
= REG_TYPE_Z
;
6614 goto vector_reg_list
;
6616 case AARCH64_OPND_LVn
:
6617 case AARCH64_OPND_LVt
:
6618 case AARCH64_OPND_LVt_AL
:
6619 case AARCH64_OPND_LEt
:
6620 reg_type
= REG_TYPE_V
;
6622 if (reg_type
== REG_TYPE_Z
6623 && get_opcode_dependent_value (opcode
) == 1
6626 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6629 info
->reglist
.first_regno
= reg
->number
;
6630 info
->reglist
.num_regs
= 1;
6634 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6635 if (val
== PARSE_FAIL
)
6638 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6640 set_fatal_syntax_error (_("invalid register list"));
6644 if (vectype
.width
!= 0 && *str
!= ',')
6646 set_fatal_syntax_error
6647 (_("expected element type rather than vector type"));
6651 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6652 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6654 if (operands
[i
] == AARCH64_OPND_LEt
)
6656 if (!(vectype
.defined
& NTA_HASINDEX
))
6658 info
->reglist
.has_index
= 1;
6659 info
->reglist
.index
= vectype
.index
;
6663 if (vectype
.defined
& NTA_HASINDEX
)
6665 if (!(vectype
.defined
& NTA_HASTYPE
))
6667 if (reg_type
== REG_TYPE_Z
)
6668 set_fatal_syntax_error (_("missing type suffix"));
6672 info
->qualifier
= vectype_to_qualifier (&vectype
);
6673 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6677 case AARCH64_OPND_CRn
:
6678 case AARCH64_OPND_CRm
:
6680 char prefix
= *(str
++);
6681 if (prefix
!= 'c' && prefix
!= 'C')
6684 po_imm_nc_or_fail ();
6687 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6690 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6691 info
->imm
.value
= val
;
6695 case AARCH64_OPND_SHLL_IMM
:
6696 case AARCH64_OPND_IMM_VLSR
:
6697 po_imm_or_fail (1, 64);
6698 info
->imm
.value
= val
;
6701 case AARCH64_OPND_CCMP_IMM
:
6702 case AARCH64_OPND_SIMM5
:
6703 case AARCH64_OPND_FBITS
:
6704 case AARCH64_OPND_TME_UIMM16
:
6705 case AARCH64_OPND_UIMM4
:
6706 case AARCH64_OPND_UIMM4_ADDG
:
6707 case AARCH64_OPND_UIMM10
:
6708 case AARCH64_OPND_UIMM3_OP1
:
6709 case AARCH64_OPND_UIMM3_OP2
:
6710 case AARCH64_OPND_IMM_VLSL
:
6711 case AARCH64_OPND_IMM
:
6712 case AARCH64_OPND_IMM_2
:
6713 case AARCH64_OPND_WIDTH
:
6714 case AARCH64_OPND_SVE_INV_LIMM
:
6715 case AARCH64_OPND_SVE_LIMM
:
6716 case AARCH64_OPND_SVE_LIMM_MOV
:
6717 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6718 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6719 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6720 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6721 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6722 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6723 case AARCH64_OPND_SVE_SIMM5
:
6724 case AARCH64_OPND_SVE_SIMM5B
:
6725 case AARCH64_OPND_SVE_SIMM6
:
6726 case AARCH64_OPND_SVE_SIMM8
:
6727 case AARCH64_OPND_SVE_UIMM3
:
6728 case AARCH64_OPND_SVE_UIMM7
:
6729 case AARCH64_OPND_SVE_UIMM8
:
6730 case AARCH64_OPND_SVE_UIMM8_53
:
6731 case AARCH64_OPND_IMM_ROT1
:
6732 case AARCH64_OPND_IMM_ROT2
:
6733 case AARCH64_OPND_IMM_ROT3
:
6734 case AARCH64_OPND_SVE_IMM_ROT1
:
6735 case AARCH64_OPND_SVE_IMM_ROT2
:
6736 case AARCH64_OPND_SVE_IMM_ROT3
:
6737 case AARCH64_OPND_CSSC_SIMM8
:
6738 case AARCH64_OPND_CSSC_UIMM8
:
6739 po_imm_nc_or_fail ();
6740 info
->imm
.value
= val
;
6743 case AARCH64_OPND_SVE_AIMM
:
6744 case AARCH64_OPND_SVE_ASIMM
:
6745 po_imm_nc_or_fail ();
6746 info
->imm
.value
= val
;
6747 skip_whitespace (str
);
6748 if (skip_past_comma (&str
))
6749 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6751 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6754 case AARCH64_OPND_SVE_PATTERN
:
6755 po_enum_or_fail (aarch64_sve_pattern_array
);
6756 info
->imm
.value
= val
;
6759 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6760 po_enum_or_fail (aarch64_sve_pattern_array
);
6761 info
->imm
.value
= val
;
6762 if (skip_past_comma (&str
)
6763 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6765 if (!info
->shifter
.operator_present
)
6767 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6768 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6769 info
->shifter
.amount
= 1;
6773 case AARCH64_OPND_SVE_PRFOP
:
6774 po_enum_or_fail (aarch64_sve_prfop_array
);
6775 info
->imm
.value
= val
;
6778 case AARCH64_OPND_UIMM7
:
6779 po_imm_or_fail (0, 127);
6780 info
->imm
.value
= val
;
6783 case AARCH64_OPND_IDX
:
6784 case AARCH64_OPND_MASK
:
6785 case AARCH64_OPND_BIT_NUM
:
6786 case AARCH64_OPND_IMMR
:
6787 case AARCH64_OPND_IMMS
:
6788 po_imm_or_fail (0, 63);
6789 info
->imm
.value
= val
;
6792 case AARCH64_OPND_IMM0
:
6793 po_imm_nc_or_fail ();
6796 set_fatal_syntax_error (_("immediate zero expected"));
6799 info
->imm
.value
= 0;
6802 case AARCH64_OPND_FPIMM0
:
6805 bool res1
= false, res2
= false;
6806 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6807 it is probably not worth the effort to support it. */
6808 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6811 || !(res2
= parse_constant_immediate (&str
, &val
,
6814 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6816 info
->imm
.value
= 0;
6817 info
->imm
.is_fp
= 1;
6820 set_fatal_syntax_error (_("immediate zero expected"));
6824 case AARCH64_OPND_IMM_MOV
:
6827 if (reg_name_p (str
, REG_TYPE_R_ZR_SP
)
6828 || reg_name_p (str
, REG_TYPE_V
))
6831 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6832 GE_OPT_PREFIX
, REJECT_ABSENT
));
6833 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6834 later. fix_mov_imm_insn will try to determine a machine
6835 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6836 message if the immediate cannot be moved by a single
6838 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6839 inst
.base
.operands
[i
].skip
= 1;
6843 case AARCH64_OPND_SIMD_IMM
:
6844 case AARCH64_OPND_SIMD_IMM_SFT
:
6845 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6847 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6849 /* need_libopcodes_p */ 1,
6852 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6853 shift, we don't check it here; we leave the checking to
6854 the libopcodes (operand_general_constraint_met_p). By
6855 doing this, we achieve better diagnostics. */
6856 if (skip_past_comma (&str
)
6857 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6859 if (!info
->shifter
.operator_present
6860 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6862 /* Default to LSL if not present. Libopcodes prefers shifter
6863 kind to be explicit. */
6864 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6865 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6869 case AARCH64_OPND_FPIMM
:
6870 case AARCH64_OPND_SIMD_FPIMM
:
6871 case AARCH64_OPND_SVE_FPIMM8
:
6876 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6877 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6878 || !aarch64_imm_float_p (qfloat
))
6881 set_fatal_syntax_error (_("invalid floating-point"
6885 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6886 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6890 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6891 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6892 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6897 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6898 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6901 set_fatal_syntax_error (_("invalid floating-point"
6905 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6906 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6910 case AARCH64_OPND_LIMM
:
6911 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6912 SHIFTED_LOGIC_IMM
));
6913 if (info
->shifter
.operator_present
)
6915 set_fatal_syntax_error
6916 (_("shift not allowed for bitmask immediate"));
6919 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6921 /* need_libopcodes_p */ 1,
6925 case AARCH64_OPND_AIMM
:
6926 if (opcode
->op
== OP_ADD
)
6927 /* ADD may have relocation types. */
6928 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6929 SHIFTED_ARITH_IMM
));
6931 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6932 SHIFTED_ARITH_IMM
));
6933 switch (inst
.reloc
.type
)
6935 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6936 info
->shifter
.amount
= 12;
6938 case BFD_RELOC_UNUSED
:
6939 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6940 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6941 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6942 inst
.reloc
.pc_rel
= 0;
6947 info
->imm
.value
= 0;
6948 if (!info
->shifter
.operator_present
)
6950 /* Default to LSL if not present. Libopcodes prefers shifter
6951 kind to be explicit. */
6952 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6953 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6957 case AARCH64_OPND_HALF
:
6959 /* #<imm16> or relocation. */
6960 int internal_fixup_p
;
6961 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6962 if (internal_fixup_p
)
6963 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6964 skip_whitespace (str
);
6965 if (skip_past_comma (&str
))
6967 /* {, LSL #<shift>} */
6968 if (! aarch64_gas_internal_fixup_p ())
6970 set_fatal_syntax_error (_("can't mix relocation modifier "
6971 "with explicit shift"));
6974 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6977 inst
.base
.operands
[i
].shifter
.amount
= 0;
6978 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6979 inst
.base
.operands
[i
].imm
.value
= 0;
6980 if (! process_movw_reloc_info ())
6985 case AARCH64_OPND_EXCEPTION
:
6986 case AARCH64_OPND_UNDEFINED
:
6987 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6989 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6991 /* need_libopcodes_p */ 0,
6995 case AARCH64_OPND_NZCV
:
6997 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
7001 info
->imm
.value
= nzcv
->value
;
7004 po_imm_or_fail (0, 15);
7005 info
->imm
.value
= val
;
7009 case AARCH64_OPND_COND
:
7010 case AARCH64_OPND_COND1
:
7015 while (ISALPHA (*str
));
7016 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
7017 if (info
->cond
== NULL
)
7019 set_syntax_error (_("invalid condition"));
7022 else if (operands
[i
] == AARCH64_OPND_COND1
7023 && (info
->cond
->value
& 0xe) == 0xe)
7025 /* Do not allow AL or NV. */
7026 set_default_error ();
7032 case AARCH64_OPND_ADDR_ADRP
:
7033 po_misc_or_fail (parse_adrp (&str
));
7034 /* Clear the value as operand needs to be relocated. */
7035 info
->imm
.value
= 0;
7038 case AARCH64_OPND_ADDR_PCREL14
:
7039 case AARCH64_OPND_ADDR_PCREL19
:
7040 case AARCH64_OPND_ADDR_PCREL21
:
7041 case AARCH64_OPND_ADDR_PCREL26
:
7042 po_misc_or_fail (parse_address (&str
, info
));
7043 if (!info
->addr
.pcrel
)
7045 set_syntax_error (_("invalid pc-relative address"));
7048 if (inst
.gen_lit_pool
7049 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
7051 /* Only permit "=value" in the literal load instructions.
7052 The literal will be generated by programmer_friendly_fixup. */
7053 set_syntax_error (_("invalid use of \"=immediate\""));
7056 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
7058 set_syntax_error (_("unrecognized relocation suffix"));
7061 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
7063 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
7064 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7068 info
->imm
.value
= 0;
7069 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7070 switch (opcode
->iclass
)
7074 /* e.g. CBZ or B.COND */
7075 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7076 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
7080 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
7081 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
7085 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
7087 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
7088 : BFD_RELOC_AARCH64_JUMP26
;
7091 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7092 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
7095 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
7096 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
7102 inst
.reloc
.pc_rel
= 1;
7106 case AARCH64_OPND_ADDR_SIMPLE
:
7107 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
7109 /* [<Xn|SP>{, #<simm>}] */
7111 /* First use the normal address-parsing routines, to get
7112 the usual syntax errors. */
7113 po_misc_or_fail (parse_address (&str
, info
));
7114 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7115 || !info
->addr
.preind
|| info
->addr
.postind
7116 || info
->addr
.writeback
)
7118 set_syntax_error (_("invalid addressing mode"));
7122 /* Then retry, matching the specific syntax of these addresses. */
7124 po_char_or_fail ('[');
7125 po_reg_or_fail (REG_TYPE_R64_SP
);
7126 /* Accept optional ", #0". */
7127 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
7128 && skip_past_char (&str
, ','))
7130 skip_past_char (&str
, '#');
7131 if (! skip_past_char (&str
, '0'))
7133 set_fatal_syntax_error
7134 (_("the optional immediate offset can only be 0"));
7138 po_char_or_fail (']');
7142 case AARCH64_OPND_ADDR_REGOFF
:
7143 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
7144 po_misc_or_fail (parse_address (&str
, info
));
7146 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
7147 || !info
->addr
.preind
|| info
->addr
.postind
7148 || info
->addr
.writeback
)
7150 set_syntax_error (_("invalid addressing mode"));
7153 if (!info
->shifter
.operator_present
)
7155 /* Default to LSL if not present. Libopcodes prefers shifter
7156 kind to be explicit. */
7157 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7158 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7160 /* Qualifier to be deduced by libopcodes. */
7163 case AARCH64_OPND_ADDR_SIMM7
:
7164 po_misc_or_fail (parse_address (&str
, info
));
7165 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7166 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7168 set_syntax_error (_("invalid addressing mode"));
7171 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7173 set_syntax_error (_("relocation not allowed"));
7176 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7178 /* need_libopcodes_p */ 1,
7182 case AARCH64_OPND_ADDR_SIMM9
:
7183 case AARCH64_OPND_ADDR_SIMM9_2
:
7184 case AARCH64_OPND_ADDR_SIMM11
:
7185 case AARCH64_OPND_ADDR_SIMM13
:
7186 po_misc_or_fail (parse_address (&str
, info
));
7187 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7188 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7189 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7190 && info
->addr
.writeback
))
7192 set_syntax_error (_("invalid addressing mode"));
7195 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7197 set_syntax_error (_("relocation not allowed"));
7200 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7202 /* need_libopcodes_p */ 1,
7206 case AARCH64_OPND_ADDR_SIMM10
:
7207 case AARCH64_OPND_ADDR_OFFSET
:
7208 po_misc_or_fail (parse_address (&str
, info
));
7209 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7210 || !info
->addr
.preind
|| info
->addr
.postind
)
7212 set_syntax_error (_("invalid addressing mode"));
7215 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7217 set_syntax_error (_("relocation not allowed"));
7220 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7222 /* need_libopcodes_p */ 1,
7226 case AARCH64_OPND_ADDR_UIMM12
:
7227 po_misc_or_fail (parse_address (&str
, info
));
7228 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7229 || !info
->addr
.preind
|| info
->addr
.writeback
)
7231 set_syntax_error (_("invalid addressing mode"));
7234 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7235 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7236 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7238 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7240 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7242 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7244 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7245 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7246 /* Leave qualifier to be determined by libopcodes. */
7249 case AARCH64_OPND_SIMD_ADDR_POST
:
7250 /* [<Xn|SP>], <Xm|#<amount>> */
7251 po_misc_or_fail (parse_address (&str
, info
));
7252 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7254 set_syntax_error (_("invalid addressing mode"));
7257 if (!info
->addr
.offset
.is_reg
)
7259 if (inst
.reloc
.exp
.X_op
== O_constant
)
7260 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7263 set_fatal_syntax_error
7264 (_("writeback value must be an immediate constant"));
7271 case AARCH64_OPND_SME_SM_ZA
:
7273 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7275 set_syntax_error (_("unknown or missing PSTATE field name"));
7278 info
->reg
.regno
= val
;
7281 case AARCH64_OPND_SME_PnT_Wm_imm
:
7282 if (!parse_dual_indexed_reg (&str
, REG_TYPE_P
,
7283 &info
->indexed_za
, &qualifier
, 0))
7285 info
->qualifier
= qualifier
;
7288 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7289 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7290 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7291 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7292 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7293 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7294 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7295 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7296 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7297 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7298 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7299 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7300 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7301 /* [X<n>{, #imm, MUL VL}]
7303 but recognizing SVE registers. */
7304 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7305 &offset_qualifier
));
7306 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7308 set_syntax_error (_("invalid addressing mode"));
7312 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7313 || !info
->addr
.preind
|| info
->addr
.writeback
)
7315 set_syntax_error (_("invalid addressing mode"));
7318 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7319 || inst
.reloc
.exp
.X_op
!= O_constant
)
7321 /* Make sure this has priority over
7322 "invalid addressing mode". */
7323 set_fatal_syntax_error (_("constant offset required"));
7326 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7329 case AARCH64_OPND_SVE_ADDR_R
:
7330 /* [<Xn|SP>{, <R><m>}]
7331 but recognizing SVE registers. */
7332 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7333 &offset_qualifier
));
7334 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7336 offset_qualifier
= AARCH64_OPND_QLF_X
;
7337 info
->addr
.offset
.is_reg
= 1;
7338 info
->addr
.offset
.regno
= 31;
7340 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7341 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7343 set_syntax_error (_("invalid addressing mode"));
7348 case AARCH64_OPND_SVE_ADDR_RR
:
7349 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7350 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7351 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7352 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7353 case AARCH64_OPND_SVE_ADDR_RX
:
7354 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7355 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7356 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7357 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7358 but recognizing SVE registers. */
7359 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7360 &offset_qualifier
));
7361 if (base_qualifier
!= AARCH64_OPND_QLF_X
7362 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7364 set_syntax_error (_("invalid addressing mode"));
7369 case AARCH64_OPND_SVE_ADDR_RZ
:
7370 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7371 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7372 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7373 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7374 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7375 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7376 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7377 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7378 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7379 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7380 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7381 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7382 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7383 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7384 &offset_qualifier
));
7385 if (base_qualifier
!= AARCH64_OPND_QLF_X
7386 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7387 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7389 set_syntax_error (_("invalid addressing mode"));
7392 info
->qualifier
= offset_qualifier
;
7395 case AARCH64_OPND_SVE_ADDR_ZX
:
7396 /* [Zn.<T>{, <Xm>}]. */
7397 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7398 &offset_qualifier
));
7400 base_qualifier either S_S or S_D
7401 offset_qualifier must be X
7403 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7404 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7405 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7407 set_syntax_error (_("invalid addressing mode"));
7410 info
->qualifier
= base_qualifier
;
7411 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7412 || !info
->addr
.preind
|| info
->addr
.writeback
7413 || info
->shifter
.operator_present
!= 0)
7415 set_syntax_error (_("invalid addressing mode"));
7418 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7422 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7423 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7424 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7425 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7426 /* [Z<n>.<T>{, #imm}] */
7427 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7428 &offset_qualifier
));
7429 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7430 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7432 set_syntax_error (_("invalid addressing mode"));
7435 info
->qualifier
= base_qualifier
;
7438 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7439 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7440 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7441 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7442 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7446 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7448 here since we get better error messages by leaving it to
7449 the qualifier checking routines. */
7450 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7451 &offset_qualifier
));
7452 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7453 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7454 || offset_qualifier
!= base_qualifier
)
7456 set_syntax_error (_("invalid addressing mode"));
7459 info
->qualifier
= base_qualifier
;
7462 case AARCH64_OPND_SYSREG
:
7464 uint32_t sysreg_flags
;
7465 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7466 &sysreg_flags
)) == PARSE_FAIL
)
7468 set_syntax_error (_("unknown or missing system register name"));
7471 inst
.base
.operands
[i
].sysreg
.value
= val
;
7472 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7476 case AARCH64_OPND_PSTATEFIELD
:
7478 uint32_t sysreg_flags
;
7479 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7480 &sysreg_flags
)) == PARSE_FAIL
)
7482 set_syntax_error (_("unknown or missing PSTATE field name"));
7485 inst
.base
.operands
[i
].pstatefield
= val
;
7486 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7490 case AARCH64_OPND_SYSREG_IC
:
7491 inst
.base
.operands
[i
].sysins_op
=
7492 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7495 case AARCH64_OPND_SYSREG_DC
:
7496 inst
.base
.operands
[i
].sysins_op
=
7497 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7500 case AARCH64_OPND_SYSREG_AT
:
7501 inst
.base
.operands
[i
].sysins_op
=
7502 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7505 case AARCH64_OPND_SYSREG_SR
:
7506 inst
.base
.operands
[i
].sysins_op
=
7507 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7510 case AARCH64_OPND_SYSREG_TLBI
:
7511 inst
.base
.operands
[i
].sysins_op
=
7512 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7514 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7516 set_fatal_syntax_error ( _("unknown or missing operation name"));
7521 case AARCH64_OPND_BARRIER
:
7522 case AARCH64_OPND_BARRIER_ISB
:
7523 val
= parse_barrier (&str
);
7524 if (val
!= PARSE_FAIL
7525 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7527 /* ISB only accepts options name 'sy'. */
7529 (_("the specified option is not accepted in ISB"));
7530 /* Turn off backtrack as this optional operand is present. */
7534 if (val
!= PARSE_FAIL
7535 && operands
[i
] == AARCH64_OPND_BARRIER
)
7537 /* Regular barriers accept options CRm (C0-C15).
7538 DSB nXS barrier variant accepts values > 15. */
7539 if (val
< 0 || val
> 15)
7541 set_syntax_error (_("the specified option is not accepted in DSB"));
7545 /* This is an extension to accept a 0..15 immediate. */
7546 if (val
== PARSE_FAIL
)
7547 po_imm_or_fail (0, 15);
7548 info
->barrier
= aarch64_barrier_options
+ val
;
7551 case AARCH64_OPND_BARRIER_DSB_NXS
:
7552 val
= parse_barrier (&str
);
7553 if (val
!= PARSE_FAIL
)
7555 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7556 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7558 set_syntax_error (_("the specified option is not accepted in DSB"));
7559 /* Turn off backtrack as this optional operand is present. */
7566 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7567 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7568 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7570 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7572 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7576 /* Option index is encoded as 2-bit value in val<3:2>. */
7577 val
= (val
>> 2) - 4;
7578 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7581 case AARCH64_OPND_PRFOP
:
7582 val
= parse_pldop (&str
);
7583 /* This is an extension to accept a 0..31 immediate. */
7584 if (val
== PARSE_FAIL
)
7585 po_imm_or_fail (0, 31);
7586 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7589 case AARCH64_OPND_BARRIER_PSB
:
7590 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7591 if (val
== PARSE_FAIL
)
7595 case AARCH64_OPND_BTI_TARGET
:
7596 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7597 if (val
== PARSE_FAIL
)
7601 case AARCH64_OPND_SME_ZAda_2b
:
7602 case AARCH64_OPND_SME_ZAda_3b
:
7603 reg
= parse_reg_with_qual (&str
, REG_TYPE_ZAT
, &qualifier
, 0);
7606 info
->reg
.regno
= reg
->number
;
7607 info
->qualifier
= qualifier
;
7610 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7611 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7612 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7613 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
7614 ? !parse_sme_za_hv_tiles_operand_with_braces (&str
,
7617 : !parse_dual_indexed_reg (&str
, REG_TYPE_ZATHV
,
7618 &info
->indexed_za
, &qualifier
, 0))
7620 info
->qualifier
= qualifier
;
7623 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7624 val
= parse_sme_list_of_64bit_tiles (&str
);
7625 if (val
== PARSE_FAIL
)
7627 info
->imm
.value
= val
;
7630 case AARCH64_OPND_SME_ZA_array
:
7631 if (!parse_dual_indexed_reg (&str
, REG_TYPE_ZA
,
7632 &info
->indexed_za
, &qualifier
, 0))
7634 info
->qualifier
= qualifier
;
7637 case AARCH64_OPND_MOPS_ADDR_Rd
:
7638 case AARCH64_OPND_MOPS_ADDR_Rs
:
7639 po_char_or_fail ('[');
7640 if (!parse_x0_to_x30 (&str
, info
))
7642 po_char_or_fail (']');
7643 po_char_or_fail ('!');
7646 case AARCH64_OPND_MOPS_WB_Rn
:
7647 if (!parse_x0_to_x30 (&str
, info
))
7649 po_char_or_fail ('!');
7653 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7656 /* If we get here, this operand was successfully parsed. */
7657 inst
.base
.operands
[i
].present
= 1;
7661 /* The parse routine should already have set the error, but in case
7662 not, set a default one here. */
7664 set_default_error ();
7666 if (! backtrack_pos
)
7667 goto parse_operands_return
;
7670 /* We reach here because this operand is marked as optional, and
7671 either no operand was supplied or the operand was supplied but it
7672 was syntactically incorrect. In the latter case we report an
7673 error. In the former case we perform a few more checks before
7674 dropping through to the code to insert the default operand. */
7676 char *tmp
= backtrack_pos
;
7677 char endchar
= END_OF_INSN
;
7679 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7681 skip_past_char (&tmp
, ',');
7683 if (*tmp
!= endchar
)
7684 /* The user has supplied an operand in the wrong format. */
7685 goto parse_operands_return
;
7687 /* Make sure there is not a comma before the optional operand.
7688 For example the fifth operand of 'sys' is optional:
7690 sys #0,c0,c0,#0, <--- wrong
7691 sys #0,c0,c0,#0 <--- correct. */
7692 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7694 set_fatal_syntax_error
7695 (_("unexpected comma before the omitted optional operand"));
7696 goto parse_operands_return
;
7700 /* Reaching here means we are dealing with an optional operand that is
7701 omitted from the assembly line. */
7702 gas_assert (optional_operand_p (opcode
, i
));
7704 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7706 /* Try again, skipping the optional operand at backtrack_pos. */
7707 str
= backtrack_pos
;
7710 /* Clear any error record after the omitted optional operand has been
7711 successfully handled. */
7715 /* Check if we have parsed all the operands. */
7716 if (*str
!= '\0' && ! error_p ())
7718 /* Set I to the index of the last present operand; this is
7719 for the purpose of diagnostics. */
7720 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7722 set_fatal_syntax_error
7723 (_("unexpected characters following instruction"));
7726 parse_operands_return
:
7730 inst
.parsing_error
.index
= i
;
7731 DEBUG_TRACE ("parsing FAIL: %s - %s",
7732 operand_mismatch_kind_names
[inst
.parsing_error
.kind
],
7733 inst
.parsing_error
.error
);
7734 /* Record the operand error properly; this is useful when there
7735 are multiple instruction templates for a mnemonic name, so that
7736 later on, we can select the error that most closely describes
7738 record_operand_error_info (opcode
, &inst
.parsing_error
);
7743 DEBUG_TRACE ("parsing SUCCESS");
7748 /* It does some fix-up to provide some programmer friendly feature while
7749 keeping the libopcodes happy, i.e. libopcodes only accepts
7750 the preferred architectural syntax.
7751 Return FALSE if there is any failure; otherwise return TRUE. */
7754 programmer_friendly_fixup (aarch64_instruction
*instr
)
7756 aarch64_inst
*base
= &instr
->base
;
7757 const aarch64_opcode
*opcode
= base
->opcode
;
7758 enum aarch64_op op
= opcode
->op
;
7759 aarch64_opnd_info
*operands
= base
->operands
;
7761 DEBUG_TRACE ("enter");
7763 switch (opcode
->iclass
)
7766 /* TBNZ Xn|Wn, #uimm6, label
7767 Test and Branch Not Zero: conditionally jumps to label if bit number
7768 uimm6 in register Xn is not zero. The bit number implies the width of
7769 the register, which may be written and should be disassembled as Wn if
7770 uimm is less than 32. */
7771 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7773 if (operands
[1].imm
.value
>= 32)
7775 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7779 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7783 /* LDR Wt, label | =value
7784 As a convenience assemblers will typically permit the notation
7785 "=value" in conjunction with the pc-relative literal load instructions
7786 to automatically place an immediate value or symbolic address in a
7787 nearby literal pool and generate a hidden label which references it.
7788 ISREG has been set to 0 in the case of =value. */
7789 if (instr
->gen_lit_pool
7790 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7792 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7793 if (op
== OP_LDRSW_LIT
)
7795 if (instr
->reloc
.exp
.X_op
!= O_constant
7796 && instr
->reloc
.exp
.X_op
!= O_big
7797 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7799 record_operand_error (opcode
, 1,
7800 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7801 _("constant expression expected"));
7804 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7806 record_operand_error (opcode
, 1,
7807 AARCH64_OPDE_OTHER_ERROR
,
7808 _("literal pool insertion failed"));
7816 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7817 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7818 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7819 A programmer-friendly assembler should accept a destination Xd in
7820 place of Wd, however that is not the preferred form for disassembly.
7822 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7823 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7824 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7825 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7830 /* In the 64-bit form, the final register operand is written as Wm
7831 for all but the (possibly omitted) UXTX/LSL and SXTX
7833 As a programmer-friendly assembler, we accept e.g.
7834 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7835 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7836 int idx
= aarch64_operand_index (opcode
->operands
,
7837 AARCH64_OPND_Rm_EXT
);
7838 gas_assert (idx
== 1 || idx
== 2);
7839 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7840 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7841 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7842 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7843 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7844 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7852 DEBUG_TRACE ("exit with SUCCESS");
7856 /* Check for loads and stores that will cause unpredictable behavior. */
7859 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7861 aarch64_inst
*base
= &instr
->base
;
7862 const aarch64_opcode
*opcode
= base
->opcode
;
7863 const aarch64_opnd_info
*opnds
= base
->operands
;
7864 switch (opcode
->iclass
)
7871 /* Loading/storing the base register is unpredictable if writeback. */
7872 if ((aarch64_get_operand_class (opnds
[0].type
)
7873 == AARCH64_OPND_CLASS_INT_REG
)
7874 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7875 && opnds
[1].addr
.base_regno
!= REG_SP
7876 /* Exempt STG/STZG/ST2G/STZ2G. */
7877 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7878 && opnds
[1].addr
.writeback
)
7879 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7883 case ldstnapair_offs
:
7884 case ldstpair_indexed
:
7885 /* Loading/storing the base register is unpredictable if writeback. */
7886 if ((aarch64_get_operand_class (opnds
[0].type
)
7887 == AARCH64_OPND_CLASS_INT_REG
)
7888 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7889 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7890 && opnds
[2].addr
.base_regno
!= REG_SP
7892 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7893 && opnds
[2].addr
.writeback
)
7894 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7895 /* Load operations must load different registers. */
7896 if ((opcode
->opcode
& (1 << 22))
7897 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7898 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7902 if ((aarch64_get_operand_class (opnds
[0].type
)
7903 == AARCH64_OPND_CLASS_INT_REG
)
7904 && (aarch64_get_operand_class (opnds
[1].type
)
7905 == AARCH64_OPND_CLASS_INT_REG
))
7907 if ((opcode
->opcode
& (1 << 22)))
7909 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
7910 if ((opcode
->opcode
& (1 << 21))
7911 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7912 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7916 /* Store-Exclusive is unpredictable if Rt == Rs. */
7917 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7919 (_("unpredictable: identical transfer and status registers"
7922 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
7924 if (!(opcode
->opcode
& (1 << 21)))
7925 /* Store-Exclusive is unpredictable if Rn == Rs. */
7927 (_("unpredictable: identical base and status registers"
7930 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
7932 (_("unpredictable: "
7933 "identical transfer and status registers"
7937 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
7938 if ((opcode
->opcode
& (1 << 21))
7939 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
7940 && opnds
[3].reg
.regno
!= REG_SP
)
7941 as_warn (_("unpredictable: identical base and status registers"
7953 force_automatic_sequence_close (void)
7955 struct aarch64_segment_info_type
*tc_seg_info
;
7957 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7958 if (tc_seg_info
->insn_sequence
.instr
)
7960 as_warn_where (tc_seg_info
->last_file
, tc_seg_info
->last_line
,
7961 _("previous `%s' sequence has not been closed"),
7962 tc_seg_info
->insn_sequence
.instr
->opcode
->name
);
7963 init_insn_sequence (NULL
, &tc_seg_info
->insn_sequence
);
7967 /* A wrapper function to interface with libopcodes on encoding and
7968 record the error message if there is any.
7970 Return TRUE on success; otherwise return FALSE. */
7973 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7976 aarch64_operand_error error_info
;
7977 memset (&error_info
, '\0', sizeof (error_info
));
7978 error_info
.kind
= AARCH64_OPDE_NIL
;
7979 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7980 && !error_info
.non_fatal
)
7983 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7984 record_operand_error_info (opcode
, &error_info
);
7985 return error_info
.non_fatal
;
7988 #ifdef DEBUG_AARCH64
7990 dump_opcode_operands (const aarch64_opcode
*opcode
)
7993 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7995 aarch64_verbose ("\t\t opnd%d: %s", i
,
7996 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7997 ? aarch64_get_operand_name (opcode
->operands
[i
])
7998 : aarch64_get_operand_desc (opcode
->operands
[i
]));
8002 #endif /* DEBUG_AARCH64 */
8004 /* This is the guts of the machine-dependent assembler. STR points to a
8005 machine dependent instruction. This function is supposed to emit
8006 the frags/bytes it assembles to. */
8009 md_assemble (char *str
)
8011 templates
*template;
8012 const aarch64_opcode
*opcode
;
8013 struct aarch64_segment_info_type
*tc_seg_info
;
8014 aarch64_inst
*inst_base
;
8015 unsigned saved_cond
;
8017 /* Align the previous label if needed. */
8018 if (last_label_seen
!= NULL
)
8020 symbol_set_frag (last_label_seen
, frag_now
);
8021 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
8022 S_SET_SEGMENT (last_label_seen
, now_seg
);
8025 /* Update the current insn_sequence from the segment. */
8026 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
8027 insn_sequence
= &tc_seg_info
->insn_sequence
;
8028 tc_seg_info
->last_file
= as_where (&tc_seg_info
->last_line
);
8030 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8032 DEBUG_TRACE ("\n\n");
8033 DEBUG_TRACE ("==============================");
8034 DEBUG_TRACE ("Enter md_assemble with %s", str
);
8036 /* Scan up to the end of the mnemonic, which must end in whitespace,
8037 '.', or end of string. */
8040 for (; is_part_of_name (*p
); p
++)
8041 if (*p
== '.' && !dot
)
8046 as_bad (_("unknown mnemonic -- `%s'"), str
);
8050 if (!dot
&& create_register_alias (str
, p
))
8053 template = opcode_lookup (str
, dot
, p
);
8056 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
8061 skip_whitespace (p
);
8064 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
8065 get_mnemonic_name (str
), str
);
8069 init_operand_error_report ();
8071 /* Sections are assumed to start aligned. In executable section, there is no
8072 MAP_DATA symbol pending. So we only align the address during
8073 MAP_DATA --> MAP_INSN transition.
8074 For other sections, this is not guaranteed. */
8075 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
8076 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
8077 frag_align_code (2, 0);
8079 saved_cond
= inst
.cond
;
8080 reset_aarch64_instruction (&inst
);
8081 inst
.cond
= saved_cond
;
8083 /* Iterate through all opcode entries with the same mnemonic name. */
8086 opcode
= template->opcode
;
8088 DEBUG_TRACE ("opcode %s found", opcode
->name
);
8089 #ifdef DEBUG_AARCH64
8091 dump_opcode_operands (opcode
);
8092 #endif /* DEBUG_AARCH64 */
8094 mapping_state (MAP_INSN
);
8096 inst_base
= &inst
.base
;
8097 inst_base
->opcode
= opcode
;
8099 /* Truly conditionally executed instructions, e.g. b.cond. */
8100 if (opcode
->flags
& F_COND
)
8102 gas_assert (inst
.cond
!= COND_ALWAYS
);
8103 inst_base
->cond
= get_cond_from_value (inst
.cond
);
8104 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
8106 else if (inst
.cond
!= COND_ALWAYS
)
8108 /* It shouldn't arrive here, where the assembly looks like a
8109 conditional instruction but the found opcode is unconditional. */
8114 if (parse_operands (p
, opcode
)
8115 && programmer_friendly_fixup (&inst
)
8116 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
8118 /* Check that this instruction is supported for this CPU. */
8119 if (!aarch64_cpu_supports_inst_p (cpu_variant
, inst_base
))
8121 as_bad (_("selected processor does not support `%s'"), str
);
8125 warn_unpredictable_ldst (&inst
, str
);
8127 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
8128 || !inst
.reloc
.need_libopcodes_p
)
8132 /* If there is relocation generated for the instruction,
8133 store the instruction information for the future fix-up. */
8134 struct aarch64_inst
*copy
;
8135 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
8136 copy
= XNEW (struct aarch64_inst
);
8137 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
8141 /* Issue non-fatal messages if any. */
8142 output_operand_error_report (str
, true);
8146 template = template->next
;
8147 if (template != NULL
)
8149 reset_aarch64_instruction (&inst
);
8150 inst
.cond
= saved_cond
;
8153 while (template != NULL
);
8155 /* Issue the error messages if any. */
8156 output_operand_error_report (str
, false);
8159 /* Various frobbings of labels and their addresses. */
8162 aarch64_start_line_hook (void)
8164 last_label_seen
= NULL
;
8168 aarch64_frob_label (symbolS
* sym
)
8170 last_label_seen
= sym
;
8172 dwarf2_emit_label (sym
);
8176 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8178 /* Check to see if we have a block to close. */
8179 force_automatic_sequence_close ();
8183 aarch64_data_in_code (void)
8185 if (startswith (input_line_pointer
+ 1, "data:"))
8187 *input_line_pointer
= '/';
8188 input_line_pointer
+= 5;
8189 *input_line_pointer
= 0;
8197 aarch64_canonicalize_symbol_name (char *name
)
8201 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8202 *(name
+ len
- 5) = 0;
8207 /* Table of all register names defined by default. The user can
8208 define additional names with .req. Note that all register names
8209 should appear in both upper and lowercase variants. Some registers
8210 also have mixed-case names. */
8212 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8213 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8214 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8215 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8216 #define REGSET16(p,t) \
8217 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8218 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8219 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8220 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8221 #define REGSET16S(p,s,t) \
8222 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8223 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8224 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8225 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8226 #define REGSET31(p,t) \
8228 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8229 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8230 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8231 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8232 #define REGSET(p,t) \
8233 REGSET31(p,t), REGNUM(p,31,t)
8235 /* These go into aarch64_reg_hsh hash-table. */
8236 static const reg_entry reg_names
[] = {
8237 /* Integer registers. */
8238 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8239 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8241 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8242 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8243 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8244 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8245 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8246 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8248 REGDEF (wzr
, 31, ZR_32
), REGDEF (WZR
, 31, ZR_32
),
8249 REGDEF (xzr
, 31, ZR_64
), REGDEF (XZR
, 31, ZR_64
),
8251 /* Floating-point single precision registers. */
8252 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8254 /* Floating-point double precision registers. */
8255 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8257 /* Floating-point half precision registers. */
8258 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8260 /* Floating-point byte precision registers. */
8261 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8263 /* Floating-point quad precision registers. */
8264 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8266 /* FP/SIMD registers. */
8267 REGSET (v
, V
), REGSET (V
, V
),
8269 /* SVE vector registers. */
8270 REGSET (z
, Z
), REGSET (Z
, Z
),
8272 /* SVE predicate registers. */
8273 REGSET16 (p
, P
), REGSET16 (P
, P
),
8275 /* SME ZA. We model this as a register because it acts syntactically
8276 like ZA0H, supporting qualifier suffixes and indexing. */
8277 REGDEF (za
, 0, ZA
), REGDEF (ZA
, 0, ZA
),
8279 /* SME ZA tile registers. */
8280 REGSET16 (za
, ZAT
), REGSET16 (ZA
, ZAT
),
8282 /* SME ZA tile registers (horizontal slice). */
8283 REGSET16S (za
, h
, ZATH
), REGSET16S (ZA
, H
, ZATH
),
8285 /* SME ZA tile registers (vertical slice). */
8286 REGSET16S (za
, v
, ZATV
), REGSET16S (ZA
, V
, ZATV
)
8304 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8305 static const asm_nzcv nzcv_names
[] = {
8306 {"nzcv", B (n
, z
, c
, v
)},
8307 {"nzcV", B (n
, z
, c
, V
)},
8308 {"nzCv", B (n
, z
, C
, v
)},
8309 {"nzCV", B (n
, z
, C
, V
)},
8310 {"nZcv", B (n
, Z
, c
, v
)},
8311 {"nZcV", B (n
, Z
, c
, V
)},
8312 {"nZCv", B (n
, Z
, C
, v
)},
8313 {"nZCV", B (n
, Z
, C
, V
)},
8314 {"Nzcv", B (N
, z
, c
, v
)},
8315 {"NzcV", B (N
, z
, c
, V
)},
8316 {"NzCv", B (N
, z
, C
, v
)},
8317 {"NzCV", B (N
, z
, C
, V
)},
8318 {"NZcv", B (N
, Z
, c
, v
)},
8319 {"NZcV", B (N
, Z
, c
, V
)},
8320 {"NZCv", B (N
, Z
, C
, v
)},
8321 {"NZCV", B (N
, Z
, C
, V
)}
8334 /* MD interface: bits in the object file. */
8336 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8337 for use in the a.out file, and stores them in the array pointed to by buf.
8338 This knows about the endian-ness of the target machine and does
8339 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8340 2 (short) and 4 (long) Floating numbers are put out as a series of
8341 LITTLENUMS (shorts, here at least). */
8344 md_number_to_chars (char *buf
, valueT val
, int n
)
8346 if (target_big_endian
)
8347 number_to_chars_bigendian (buf
, val
, n
);
8349 number_to_chars_littleendian (buf
, val
, n
);
8352 /* MD interface: Sections. */
8354 /* Estimate the size of a frag before relaxing. Assume everything fits in
8358 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8364 /* Round up a section size to the appropriate boundary. */
8367 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8372 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8373 of an rs_align_code fragment.
8375 Here we fill the frag with the appropriate info for padding the
8376 output stream. The resulting frag will consist of a fixed (fr_fix)
8377 and of a repeating (fr_var) part.
8379 The fixed content is always emitted before the repeating content and
8380 these two parts are used as follows in constructing the output:
8381 - the fixed part will be used to align to a valid instruction word
8382 boundary, in case that we start at a misaligned address; as no
8383 executable instruction can live at the misaligned location, we
8384 simply fill with zeros;
8385 - the variable part will be used to cover the remaining padding and
8386 we fill using the AArch64 NOP instruction.
8388 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8389 enough storage space for up to 3 bytes for padding the back to a valid
8390 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8393 aarch64_handle_align (fragS
* fragP
)
8395 /* NOP = d503201f */
8396 /* AArch64 instructions are always little-endian. */
8397 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8399 int bytes
, fix
, noop_size
;
8402 if (fragP
->fr_type
!= rs_align_code
)
8405 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8406 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8409 gas_assert (fragP
->tc_frag_data
.recorded
);
8412 noop_size
= sizeof (aarch64_noop
);
8414 fix
= bytes
& (noop_size
- 1);
8417 #if defined OBJ_ELF || defined OBJ_COFF
8418 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8422 fragP
->fr_fix
+= fix
;
8426 memcpy (p
, aarch64_noop
, noop_size
);
8427 fragP
->fr_var
= noop_size
;
8430 /* Perform target specific initialisation of a frag.
8431 Note - despite the name this initialisation is not done when the frag
8432 is created, but only when its type is assigned. A frag can be created
8433 and used a long time before its type is set, so beware of assuming that
8434 this initialisation is performed first. */
8438 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8439 int max_chars ATTRIBUTE_UNUSED
)
8443 #else /* OBJ_ELF is defined. */
8445 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8447 /* Record a mapping symbol for alignment frags. We will delete this
8448 later if the alignment ends up empty. */
8449 if (!fragP
->tc_frag_data
.recorded
)
8450 fragP
->tc_frag_data
.recorded
= 1;
8452 /* PR 21809: Do not set a mapping state for debug sections
8453 - it just confuses other tools. */
8454 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8457 switch (fragP
->fr_type
)
8461 mapping_state_2 (MAP_DATA
, max_chars
);
8464 /* PR 20364: We can get alignment frags in code sections,
8465 so do not just assume that we should use the MAP_DATA state. */
8466 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8469 mapping_state_2 (MAP_INSN
, max_chars
);
8476 /* Whether SFrame stack trace info is supported. */
8479 aarch64_support_sframe_p (void)
8481 /* At this time, SFrame is supported for aarch64 only. */
8482 return (aarch64_abi
== AARCH64_ABI_LP64
);
8485 /* Specify if RA tracking is needed. */
8488 aarch64_sframe_ra_tracking_p (void)
8493 /* Specify the fixed offset to recover RA from CFA.
8494 (useful only when RA tracking is not needed). */
8497 aarch64_sframe_cfa_ra_offset (void)
8499 return (offsetT
) SFRAME_CFA_FIXED_RA_INVALID
;
8502 /* Get the abi/arch indentifier for SFrame. */
8505 aarch64_sframe_get_abi_arch (void)
8507 unsigned char sframe_abi_arch
= 0;
8509 if (aarch64_support_sframe_p ())
8511 sframe_abi_arch
= target_big_endian
8512 ? SFRAME_ABI_AARCH64_ENDIAN_BIG
8513 : SFRAME_ABI_AARCH64_ENDIAN_LITTLE
;
8516 return sframe_abi_arch
;
8519 #endif /* OBJ_ELF */
8521 /* Initialize the DWARF-2 unwind information for this procedure. */
8524 tc_aarch64_frame_initial_instructions (void)
8526 cfi_add_CFA_def_cfa (REG_SP
, 0);
8529 /* Convert REGNAME to a DWARF-2 register number. */
8532 tc_aarch64_regname_to_dw2regnum (char *regname
)
8534 const reg_entry
*reg
= parse_reg (®name
);
8540 case REG_TYPE_SP_32
:
8541 case REG_TYPE_SP_64
:
8551 return reg
->number
+ 64;
8559 /* Implement DWARF2_ADDR_SIZE. */
8562 aarch64_dwarf2_addr_size (void)
8568 return bfd_arch_bits_per_address (stdoutput
) / 8;
8571 /* MD interface: Symbol and relocation handling. */
8573 /* Return the address within the segment that a PC-relative fixup is
8574 relative to. For AArch64 PC-relative fixups applied to instructions
8575 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8578 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8580 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8582 /* If this is pc-relative and we are going to emit a relocation
8583 then we just want to put out any pipeline compensation that the linker
8584 will need. Otherwise we want to use the calculated base. */
8586 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8587 || aarch64_force_relocation (fixP
)))
8590 /* AArch64 should be consistent for all pc-relative relocations. */
8591 return base
+ AARCH64_PCREL_OFFSET
;
8594 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8595 Otherwise we have no need to default values of symbols. */
8598 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8601 if (name
[0] == '_' && name
[1] == 'G'
8602 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8606 if (symbol_find (name
))
8607 as_bad (_("GOT already in the symbol table"));
8609 GOT_symbol
= symbol_new (name
, undefined_section
,
8610 &zero_address_frag
, 0);
8620 /* Return non-zero if the indicated VALUE has overflowed the maximum
8621 range expressible by a unsigned number with the indicated number of
8625 unsigned_overflow (valueT value
, unsigned bits
)
8628 if (bits
>= sizeof (valueT
) * 8)
8630 lim
= (valueT
) 1 << bits
;
8631 return (value
>= lim
);
8635 /* Return non-zero if the indicated VALUE has overflowed the maximum
8636 range expressible by an signed number with the indicated number of
8640 signed_overflow (offsetT value
, unsigned bits
)
8643 if (bits
>= sizeof (offsetT
) * 8)
8645 lim
= (offsetT
) 1 << (bits
- 1);
8646 return (value
< -lim
|| value
>= lim
);
8649 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8650 unsigned immediate offset load/store instruction, try to encode it as
8651 an unscaled, 9-bit, signed immediate offset load/store instruction.
8652 Return TRUE if it is successful; otherwise return FALSE.
8654 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8655 in response to the standard LDR/STR mnemonics when the immediate offset is
8656 unambiguous, i.e. when it is negative or unaligned. */
8659 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8662 enum aarch64_op new_op
;
8663 const aarch64_opcode
*new_opcode
;
8665 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8667 switch (instr
->opcode
->op
)
8669 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8670 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8671 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8672 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8673 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8674 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8675 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8676 case OP_STR_POS
: new_op
= OP_STUR
; break;
8677 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8678 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8679 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8680 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8681 default: new_op
= OP_NIL
; break;
8684 if (new_op
== OP_NIL
)
8687 new_opcode
= aarch64_get_opcode (new_op
);
8688 gas_assert (new_opcode
!= NULL
);
8690 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8691 instr
->opcode
->op
, new_opcode
->op
);
8693 aarch64_replace_opcode (instr
, new_opcode
);
8695 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8696 qualifier matching may fail because the out-of-date qualifier will
8697 prevent the operand being updated with a new and correct qualifier. */
8698 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8699 AARCH64_OPND_ADDR_SIMM9
);
8700 gas_assert (idx
== 1);
8701 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8703 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8705 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8712 /* Called by fix_insn to fix a MOV immediate alias instruction.
8714 Operand for a generic move immediate instruction, which is an alias
8715 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8716 a 32-bit/64-bit immediate value into general register. An assembler error
8717 shall result if the immediate cannot be created by a single one of these
8718 instructions. If there is a choice, then to ensure reversability an
8719 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8722 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8724 const aarch64_opcode
*opcode
;
8726 /* Need to check if the destination is SP/ZR. The check has to be done
8727 before any aarch64_replace_opcode. */
8728 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8729 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8731 instr
->operands
[1].imm
.value
= value
;
8732 instr
->operands
[1].skip
= 0;
8736 /* Try the MOVZ alias. */
8737 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8738 aarch64_replace_opcode (instr
, opcode
);
8739 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8740 &instr
->value
, NULL
, NULL
, insn_sequence
))
8742 put_aarch64_insn (buf
, instr
->value
);
8745 /* Try the MOVK alias. */
8746 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8747 aarch64_replace_opcode (instr
, opcode
);
8748 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8749 &instr
->value
, NULL
, NULL
, insn_sequence
))
8751 put_aarch64_insn (buf
, instr
->value
);
8756 if (try_mov_bitmask_p
)
8758 /* Try the ORR alias. */
8759 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8760 aarch64_replace_opcode (instr
, opcode
);
8761 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8762 &instr
->value
, NULL
, NULL
, insn_sequence
))
8764 put_aarch64_insn (buf
, instr
->value
);
8769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8770 _("immediate cannot be moved by a single instruction"));
8773 /* An instruction operand which is immediate related may have symbol used
8774 in the assembly, e.g.
8777 .set u32, 0x00ffff00
8779 At the time when the assembly instruction is parsed, a referenced symbol,
8780 like 'u32' in the above example may not have been seen; a fixS is created
8781 in such a case and is handled here after symbols have been resolved.
8782 Instruction is fixed up with VALUE using the information in *FIXP plus
8783 extra information in FLAGS.
8785 This function is called by md_apply_fix to fix up instructions that need
8786 a fix-up described above but does not involve any linker-time relocation. */
8789 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8793 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8794 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8795 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8799 /* Now the instruction is about to be fixed-up, so the operand that
8800 was previously marked as 'ignored' needs to be unmarked in order
8801 to get the encoding done properly. */
8802 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8803 new_inst
->operands
[idx
].skip
= 0;
8806 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8810 case AARCH64_OPND_EXCEPTION
:
8811 case AARCH64_OPND_UNDEFINED
:
8812 if (unsigned_overflow (value
, 16))
8813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8814 _("immediate out of range"));
8815 insn
= get_aarch64_insn (buf
);
8816 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8817 put_aarch64_insn (buf
, insn
);
8820 case AARCH64_OPND_AIMM
:
8821 /* ADD or SUB with immediate.
8822 NOTE this assumes we come here with a add/sub shifted reg encoding
8823 3 322|2222|2 2 2 21111 111111
8824 1 098|7654|3 2 1 09876 543210 98765 43210
8825 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8826 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8827 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8828 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8830 3 322|2222|2 2 221111111111
8831 1 098|7654|3 2 109876543210 98765 43210
8832 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8833 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8834 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8835 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8836 Fields sf Rn Rd are already set. */
8837 insn
= get_aarch64_insn (buf
);
8841 insn
= reencode_addsub_switch_add_sub (insn
);
8845 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8846 && unsigned_overflow (value
, 12))
8848 /* Try to shift the value by 12 to make it fit. */
8849 if (((value
>> 12) << 12) == value
8850 && ! unsigned_overflow (value
, 12 + 12))
8853 insn
|= encode_addsub_imm_shift_amount (1);
8857 if (unsigned_overflow (value
, 12))
8858 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8859 _("immediate out of range"));
8861 insn
|= encode_addsub_imm (value
);
8863 put_aarch64_insn (buf
, insn
);
8866 case AARCH64_OPND_SIMD_IMM
:
8867 case AARCH64_OPND_SIMD_IMM_SFT
:
8868 case AARCH64_OPND_LIMM
:
8869 /* Bit mask immediate. */
8870 gas_assert (new_inst
!= NULL
);
8871 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8872 new_inst
->operands
[idx
].imm
.value
= value
;
8873 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8874 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8875 put_aarch64_insn (buf
, new_inst
->value
);
8877 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8878 _("invalid immediate"));
8881 case AARCH64_OPND_HALF
:
8882 /* 16-bit unsigned immediate. */
8883 if (unsigned_overflow (value
, 16))
8884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8885 _("immediate out of range"));
8886 insn
= get_aarch64_insn (buf
);
8887 insn
|= encode_movw_imm (value
& 0xffff);
8888 put_aarch64_insn (buf
, insn
);
8891 case AARCH64_OPND_IMM_MOV
:
8892 /* Operand for a generic move immediate instruction, which is
8893 an alias instruction that generates a single MOVZ, MOVN or ORR
8894 instruction to loads a 32-bit/64-bit immediate value into general
8895 register. An assembler error shall result if the immediate cannot be
8896 created by a single one of these instructions. If there is a choice,
8897 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8898 and MOVZ or MOVN to ORR. */
8899 gas_assert (new_inst
!= NULL
);
8900 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8903 case AARCH64_OPND_ADDR_SIMM7
:
8904 case AARCH64_OPND_ADDR_SIMM9
:
8905 case AARCH64_OPND_ADDR_SIMM9_2
:
8906 case AARCH64_OPND_ADDR_SIMM10
:
8907 case AARCH64_OPND_ADDR_UIMM12
:
8908 case AARCH64_OPND_ADDR_SIMM11
:
8909 case AARCH64_OPND_ADDR_SIMM13
:
8910 /* Immediate offset in an address. */
8911 insn
= get_aarch64_insn (buf
);
8913 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8914 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8915 || new_inst
->opcode
->operands
[2] == opnd
);
8917 /* Get the index of the address operand. */
8918 if (new_inst
->opcode
->operands
[1] == opnd
)
8919 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8922 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8925 /* Update the resolved offset value. */
8926 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8928 /* Encode/fix-up. */
8929 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8930 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8932 put_aarch64_insn (buf
, new_inst
->value
);
8935 else if (new_inst
->opcode
->iclass
== ldst_pos
8936 && try_to_encode_as_unscaled_ldst (new_inst
))
8938 put_aarch64_insn (buf
, new_inst
->value
);
8942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8943 _("immediate offset out of range"));
8948 as_fatal (_("unhandled operand code %d"), opnd
);
8952 /* Apply a fixup (fixP) to segment data, once it has been determined
8953 by our caller that we have all the info we need to fix it up.
8955 Parameter valP is the pointer to the value of the bits. */
8958 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8960 offsetT value
= *valP
;
8962 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8964 unsigned flags
= fixP
->fx_addnumber
;
8966 DEBUG_TRACE ("\n\n");
8967 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8968 DEBUG_TRACE ("Enter md_apply_fix");
8970 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8972 /* Note whether this will delete the relocation. */
8974 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
8975 && aarch64_force_reloc (fixP
->fx_r_type
) <= 0)
8978 /* Process the relocations. */
8979 switch (fixP
->fx_r_type
)
8981 case BFD_RELOC_NONE
:
8982 /* This will need to go in the object file. */
8987 case BFD_RELOC_8_PCREL
:
8988 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8989 md_number_to_chars (buf
, value
, 1);
8993 case BFD_RELOC_16_PCREL
:
8994 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8995 md_number_to_chars (buf
, value
, 2);
8999 case BFD_RELOC_32_PCREL
:
9000 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9001 md_number_to_chars (buf
, value
, 4);
9005 case BFD_RELOC_64_PCREL
:
9006 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9007 md_number_to_chars (buf
, value
, 8);
9010 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
9011 /* We claim that these fixups have been processed here, even if
9012 in fact we generate an error because we do not have a reloc
9013 for them, so tc_gen_reloc() will reject them. */
9015 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
9017 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9018 _("undefined symbol %s used as an immediate value"),
9019 S_GET_NAME (fixP
->fx_addsy
));
9020 goto apply_fix_return
;
9022 fix_insn (fixP
, flags
, value
);
9025 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
9026 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9029 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9030 _("pc-relative load offset not word aligned"));
9031 if (signed_overflow (value
, 21))
9032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9033 _("pc-relative load offset out of range"));
9034 insn
= get_aarch64_insn (buf
);
9035 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
9036 put_aarch64_insn (buf
, insn
);
9040 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
9041 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9043 if (signed_overflow (value
, 21))
9044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9045 _("pc-relative address offset out of range"));
9046 insn
= get_aarch64_insn (buf
);
9047 insn
|= encode_adr_imm (value
);
9048 put_aarch64_insn (buf
, insn
);
9052 case BFD_RELOC_AARCH64_BRANCH19
:
9053 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9056 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9057 _("conditional branch target not word aligned"));
9058 if (signed_overflow (value
, 21))
9059 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9060 _("conditional branch out of range"));
9061 insn
= get_aarch64_insn (buf
);
9062 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
9063 put_aarch64_insn (buf
, insn
);
9067 case BFD_RELOC_AARCH64_TSTBR14
:
9068 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9071 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9072 _("conditional branch target not word aligned"));
9073 if (signed_overflow (value
, 16))
9074 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9075 _("conditional branch out of range"));
9076 insn
= get_aarch64_insn (buf
);
9077 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
9078 put_aarch64_insn (buf
, insn
);
9082 case BFD_RELOC_AARCH64_CALL26
:
9083 case BFD_RELOC_AARCH64_JUMP26
:
9084 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9087 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9088 _("branch target not word aligned"));
9089 if (signed_overflow (value
, 28))
9090 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9091 _("branch out of range"));
9092 insn
= get_aarch64_insn (buf
);
9093 insn
|= encode_branch_ofs_26 (value
>> 2);
9094 put_aarch64_insn (buf
, insn
);
9098 case BFD_RELOC_AARCH64_MOVW_G0
:
9099 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
9100 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9101 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
9102 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9103 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
9106 case BFD_RELOC_AARCH64_MOVW_G1
:
9107 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
9108 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9109 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9110 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9111 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
9114 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
9116 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9117 /* Should always be exported to object file, see
9118 aarch64_force_relocation(). */
9119 gas_assert (!fixP
->fx_done
);
9120 gas_assert (seg
->use_rela_p
);
9122 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9124 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9125 /* Should always be exported to object file, see
9126 aarch64_force_relocation(). */
9127 gas_assert (!fixP
->fx_done
);
9128 gas_assert (seg
->use_rela_p
);
9130 case BFD_RELOC_AARCH64_MOVW_G2
:
9131 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
9132 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9133 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9134 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
9137 case BFD_RELOC_AARCH64_MOVW_G3
:
9138 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
9141 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9143 insn
= get_aarch64_insn (buf
);
9147 /* REL signed addend must fit in 16 bits */
9148 if (signed_overflow (value
, 16))
9149 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9150 _("offset out of range"));
9154 /* Check for overflow and scale. */
9155 switch (fixP
->fx_r_type
)
9157 case BFD_RELOC_AARCH64_MOVW_G0
:
9158 case BFD_RELOC_AARCH64_MOVW_G1
:
9159 case BFD_RELOC_AARCH64_MOVW_G2
:
9160 case BFD_RELOC_AARCH64_MOVW_G3
:
9161 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9162 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9163 if (unsigned_overflow (value
, scale
+ 16))
9164 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9165 _("unsigned value out of range"));
9167 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9168 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9169 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9170 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9171 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9172 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9173 /* NOTE: We can only come here with movz or movn. */
9174 if (signed_overflow (value
, scale
+ 16))
9175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9176 _("signed value out of range"));
9179 /* Force use of MOVN. */
9181 insn
= reencode_movzn_to_movn (insn
);
9185 /* Force use of MOVZ. */
9186 insn
= reencode_movzn_to_movz (insn
);
9190 /* Unchecked relocations. */
9196 /* Insert value into MOVN/MOVZ/MOVK instruction. */
9197 insn
|= encode_movw_imm (value
& 0xffff);
9199 put_aarch64_insn (buf
, insn
);
9203 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9204 fixP
->fx_r_type
= (ilp32_p
9205 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9206 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9207 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9208 /* Should always be exported to object file, see
9209 aarch64_force_relocation(). */
9210 gas_assert (!fixP
->fx_done
);
9211 gas_assert (seg
->use_rela_p
);
9214 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9215 fixP
->fx_r_type
= (ilp32_p
9216 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9217 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9218 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9219 /* Should always be exported to object file, see
9220 aarch64_force_relocation(). */
9221 gas_assert (!fixP
->fx_done
);
9222 gas_assert (seg
->use_rela_p
);
9225 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9226 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9227 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9228 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9229 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9230 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9231 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9232 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9233 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9234 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9235 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9236 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9237 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9238 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9239 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9240 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9241 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9242 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9243 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9244 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9245 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9246 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9247 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9248 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9249 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9250 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9251 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9252 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9253 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9254 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9255 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9256 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9257 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9258 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9259 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9260 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9261 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9262 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9263 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9264 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9265 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9266 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9267 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9268 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9269 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9270 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9271 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9272 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9273 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9274 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9275 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9276 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9277 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9278 /* Should always be exported to object file, see
9279 aarch64_force_relocation(). */
9280 gas_assert (!fixP
->fx_done
);
9281 gas_assert (seg
->use_rela_p
);
9284 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9285 /* Should always be exported to object file, see
9286 aarch64_force_relocation(). */
9287 fixP
->fx_r_type
= (ilp32_p
9288 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9289 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9290 gas_assert (!fixP
->fx_done
);
9291 gas_assert (seg
->use_rela_p
);
9294 case BFD_RELOC_AARCH64_ADD_LO12
:
9295 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9296 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9297 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9298 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9299 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9300 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9301 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9302 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9303 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9304 case BFD_RELOC_AARCH64_LDST128_LO12
:
9305 case BFD_RELOC_AARCH64_LDST16_LO12
:
9306 case BFD_RELOC_AARCH64_LDST32_LO12
:
9307 case BFD_RELOC_AARCH64_LDST64_LO12
:
9308 case BFD_RELOC_AARCH64_LDST8_LO12
:
9309 /* Should always be exported to object file, see
9310 aarch64_force_relocation(). */
9311 gas_assert (!fixP
->fx_done
);
9312 gas_assert (seg
->use_rela_p
);
9315 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9316 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9317 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9320 case BFD_RELOC_UNUSED
:
9321 /* An error will already have been reported. */
9325 case BFD_RELOC_32_SECREL
:
9326 case BFD_RELOC_16_SECIDX
:
9330 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9331 _("unexpected %s fixup"),
9332 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9337 /* Free the allocated the struct aarch64_inst.
9338 N.B. currently there are very limited number of fix-up types actually use
9339 this field, so the impact on the performance should be minimal . */
9340 free (fixP
->tc_fix_data
.inst
);
9345 /* Translate internal representation of relocation info to BFD target
9349 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9352 bfd_reloc_code_real_type code
;
9354 reloc
= XNEW (arelent
);
9356 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9357 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9358 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9362 if (section
->use_rela_p
)
9363 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9365 fixp
->fx_offset
= reloc
->address
;
9367 reloc
->addend
= fixp
->fx_offset
;
9369 code
= fixp
->fx_r_type
;
9374 code
= BFD_RELOC_16_PCREL
;
9379 code
= BFD_RELOC_32_PCREL
;
9384 code
= BFD_RELOC_64_PCREL
;
9391 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9392 if (reloc
->howto
== NULL
)
9394 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9396 ("cannot represent %s relocation in this object file format"),
9397 bfd_get_reloc_code_name (code
));
9404 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9407 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9409 bfd_reloc_code_real_type type
;
9413 if (exp
->X_op
== O_secrel
)
9415 exp
->X_op
= O_symbol
;
9416 type
= BFD_RELOC_32_SECREL
;
9418 else if (exp
->X_op
== O_secidx
)
9420 exp
->X_op
= O_symbol
;
9421 type
= BFD_RELOC_16_SECIDX
;
9427 FIXME: @@ Should look at CPU word size. */
9434 type
= BFD_RELOC_16
;
9437 type
= BFD_RELOC_32
;
9440 type
= BFD_RELOC_64
;
9443 as_bad (_("cannot do %u-byte relocation"), size
);
9444 type
= BFD_RELOC_UNUSED
;
9451 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9454 /* Implement md_after_parse_args. This is the earliest time we need to decide
9455 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9458 aarch64_after_parse_args (void)
9460 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9464 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9465 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9466 aarch64_abi
= AARCH64_ABI_ILP32
;
9468 aarch64_abi
= AARCH64_ABI_LP64
;
9470 aarch64_abi
= AARCH64_ABI_LLP64
;
9476 elf64_aarch64_target_format (void)
9479 /* FIXME: What to do for ilp32_p ? */
9480 if (target_big_endian
)
9481 return "elf64-bigaarch64-cloudabi";
9483 return "elf64-littleaarch64-cloudabi";
9485 if (target_big_endian
)
9486 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9488 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9493 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9495 elf_frob_symbol (symp
, puntp
);
9497 #elif defined OBJ_COFF
9499 coff_aarch64_target_format (void)
9501 return "pe-aarch64-little";
9505 /* MD interface: Finalization. */
9507 /* A good place to do this, although this was probably not intended
9508 for this kind of use. We need to dump the literal pool before
9509 references are made to a null symbol pointer. */
9512 aarch64_cleanup (void)
9516 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9518 /* Put it at the end of the relevant section. */
9519 subseg_set (pool
->section
, pool
->sub_section
);
9525 /* Remove any excess mapping symbols generated for alignment frags in
9526 SEC. We may have created a mapping symbol before a zero byte
9527 alignment; remove it if there's a mapping symbol after the
9530 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9531 void *dummy ATTRIBUTE_UNUSED
)
9533 segment_info_type
*seginfo
= seg_info (sec
);
9536 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9539 for (fragp
= seginfo
->frchainP
->frch_root
;
9540 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9542 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9543 fragS
*next
= fragp
->fr_next
;
9545 /* Variable-sized frags have been converted to fixed size by
9546 this point. But if this was variable-sized to start with,
9547 there will be a fixed-size frag after it. So don't handle
9549 if (sym
== NULL
|| next
== NULL
)
9552 if (S_GET_VALUE (sym
) < next
->fr_address
)
9553 /* Not at the end of this frag. */
9555 know (S_GET_VALUE (sym
) == next
->fr_address
);
9559 if (next
->tc_frag_data
.first_map
!= NULL
)
9561 /* Next frag starts with a mapping symbol. Discard this
9563 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9567 if (next
->fr_next
== NULL
)
9569 /* This mapping symbol is at the end of the section. Discard
9571 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9572 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9576 /* As long as we have empty frags without any mapping symbols,
9578 /* If the next frag is non-empty and does not start with a
9579 mapping symbol, then this mapping symbol is required. */
9580 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9583 next
= next
->fr_next
;
9585 while (next
!= NULL
);
9590 /* Adjust the symbol table. */
9593 aarch64_adjust_symtab (void)
9596 /* Remove any overlapping mapping symbols generated by alignment frags. */
9597 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9598 /* Now do generic ELF adjustments. */
9599 elf_adjust_symtab ();
9604 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9606 str_hash_insert (table
, key
, value
, 0);
9610 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9612 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9613 checked_hash_insert (table
, key
, value
);
9617 fill_instruction_hash_table (void)
9619 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9621 while (opcode
->name
!= NULL
)
9623 templates
*templ
, *new_templ
;
9624 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9626 new_templ
= XNEW (templates
);
9627 new_templ
->opcode
= opcode
;
9628 new_templ
->next
= NULL
;
9631 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9634 new_templ
->next
= templ
->next
;
9635 templ
->next
= new_templ
;
9642 convert_to_upper (char *dst
, const char *src
, size_t num
)
9645 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9646 *dst
= TOUPPER (*src
);
9650 /* Assume STR point to a lower-case string, allocate, convert and return
9651 the corresponding upper-case string. */
9652 static inline const char*
9653 get_upper_str (const char *str
)
9656 size_t len
= strlen (str
);
9657 ret
= XNEWVEC (char, len
+ 1);
9658 convert_to_upper (ret
, str
, len
);
9662 /* MD interface: Initialization. */
9670 aarch64_ops_hsh
= str_htab_create ();
9671 aarch64_cond_hsh
= str_htab_create ();
9672 aarch64_shift_hsh
= str_htab_create ();
9673 aarch64_sys_regs_hsh
= str_htab_create ();
9674 aarch64_pstatefield_hsh
= str_htab_create ();
9675 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9676 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9677 aarch64_sys_regs_at_hsh
= str_htab_create ();
9678 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9679 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9680 aarch64_reg_hsh
= str_htab_create ();
9681 aarch64_barrier_opt_hsh
= str_htab_create ();
9682 aarch64_nzcv_hsh
= str_htab_create ();
9683 aarch64_pldop_hsh
= str_htab_create ();
9684 aarch64_hint_opt_hsh
= str_htab_create ();
9686 fill_instruction_hash_table ();
9688 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9689 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9690 (void *) (aarch64_sys_regs
+ i
));
9692 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9693 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9694 aarch64_pstatefields
[i
].name
,
9695 (void *) (aarch64_pstatefields
+ i
));
9697 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9698 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9699 aarch64_sys_regs_ic
[i
].name
,
9700 (void *) (aarch64_sys_regs_ic
+ i
));
9702 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9703 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9704 aarch64_sys_regs_dc
[i
].name
,
9705 (void *) (aarch64_sys_regs_dc
+ i
));
9707 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9708 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9709 aarch64_sys_regs_at
[i
].name
,
9710 (void *) (aarch64_sys_regs_at
+ i
));
9712 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9713 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9714 aarch64_sys_regs_tlbi
[i
].name
,
9715 (void *) (aarch64_sys_regs_tlbi
+ i
));
9717 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9718 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9719 aarch64_sys_regs_sr
[i
].name
,
9720 (void *) (aarch64_sys_regs_sr
+ i
));
9722 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9723 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9724 (void *) (reg_names
+ i
));
9726 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9727 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9728 (void *) (nzcv_names
+ i
));
9730 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9732 const char *name
= aarch64_operand_modifiers
[i
].name
;
9733 checked_hash_insert (aarch64_shift_hsh
, name
,
9734 (void *) (aarch64_operand_modifiers
+ i
));
9735 /* Also hash the name in the upper case. */
9736 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9737 (void *) (aarch64_operand_modifiers
+ i
));
9740 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9743 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9744 the same condition code. */
9745 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9747 const char *name
= aarch64_conds
[i
].names
[j
];
9750 checked_hash_insert (aarch64_cond_hsh
, name
,
9751 (void *) (aarch64_conds
+ i
));
9752 /* Also hash the name in the upper case. */
9753 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9754 (void *) (aarch64_conds
+ i
));
9758 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9760 const char *name
= aarch64_barrier_options
[i
].name
;
9761 /* Skip xx00 - the unallocated values of option. */
9764 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9765 (void *) (aarch64_barrier_options
+ i
));
9766 /* Also hash the name in the upper case. */
9767 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9768 (void *) (aarch64_barrier_options
+ i
));
9771 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
9773 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
9774 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9775 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9776 /* Also hash the name in the upper case. */
9777 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9778 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9781 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9783 const char* name
= aarch64_prfops
[i
].name
;
9784 /* Skip the unallocated hint encodings. */
9787 checked_hash_insert (aarch64_pldop_hsh
, name
,
9788 (void *) (aarch64_prfops
+ i
));
9789 /* Also hash the name in the upper case. */
9790 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9791 (void *) (aarch64_prfops
+ i
));
9794 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9796 const char* name
= aarch64_hint_options
[i
].name
;
9797 const char* upper_name
= get_upper_str(name
);
9799 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9800 (void *) (aarch64_hint_options
+ i
));
9802 /* Also hash the name in the upper case if not the same. */
9803 if (strcmp (name
, upper_name
) != 0)
9804 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9805 (void *) (aarch64_hint_options
+ i
));
9808 /* Set the cpu variant based on the command-line options. */
9810 mcpu_cpu_opt
= march_cpu_opt
;
9813 mcpu_cpu_opt
= &cpu_default
;
9815 cpu_variant
= *mcpu_cpu_opt
;
9817 /* Record the CPU type. */
9819 mach
= bfd_mach_aarch64_ilp32
;
9821 mach
= bfd_mach_aarch64_llp64
;
9823 mach
= bfd_mach_aarch64
;
9825 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9827 /* FIXME - is there a better way to do it ? */
9828 aarch64_sframe_cfa_sp_reg
= 31;
9829 aarch64_sframe_cfa_fp_reg
= 29; /* x29. */
9830 aarch64_sframe_cfa_ra_reg
= 30;
9834 /* Command line processing. */
9836 const char *md_shortopts
= "m:";
9838 #ifdef AARCH64_BI_ENDIAN
9839 #define OPTION_EB (OPTION_MD_BASE + 0)
9840 #define OPTION_EL (OPTION_MD_BASE + 1)
9842 #if TARGET_BYTES_BIG_ENDIAN
9843 #define OPTION_EB (OPTION_MD_BASE + 0)
9845 #define OPTION_EL (OPTION_MD_BASE + 1)
9849 struct option md_longopts
[] = {
9851 {"EB", no_argument
, NULL
, OPTION_EB
},
9854 {"EL", no_argument
, NULL
, OPTION_EL
},
9856 {NULL
, no_argument
, NULL
, 0}
9859 size_t md_longopts_size
= sizeof (md_longopts
);
9861 struct aarch64_option_table
9863 const char *option
; /* Option name to match. */
9864 const char *help
; /* Help information. */
9865 int *var
; /* Variable to change. */
9866 int value
; /* What to change it to. */
9867 char *deprecated
; /* If non-null, print this message. */
9870 static struct aarch64_option_table aarch64_opts
[] = {
9871 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9872 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9874 #ifdef DEBUG_AARCH64
9875 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9876 #endif /* DEBUG_AARCH64 */
9877 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9879 {"mno-verbose-error", N_("do not output verbose error messages"),
9880 &verbose_error_p
, 0, NULL
},
9881 {NULL
, NULL
, NULL
, 0, NULL
}
9884 struct aarch64_cpu_option_table
9887 const aarch64_feature_set value
;
9888 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9890 const char *canonical_name
;
9893 /* This list should, at a minimum, contain all the cpu names
9894 recognized by GCC. */
9895 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9896 {"all", AARCH64_ANY
, NULL
},
9897 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9898 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9899 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9900 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9901 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9902 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9903 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9904 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9905 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9906 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9907 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9908 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9909 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9910 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9912 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9913 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9915 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9916 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9918 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9919 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9920 | AARCH64_FEATURE_DOTPROD
9921 | AARCH64_FEATURE_SSBS
),
9923 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9924 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9925 | AARCH64_FEATURE_DOTPROD
9926 | AARCH64_FEATURE_SSBS
),
9928 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9929 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9930 | AARCH64_FEATURE_DOTPROD
9931 | AARCH64_FEATURE_SSBS
),
9933 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9934 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9935 | AARCH64_FEATURE_DOTPROD
9936 | AARCH64_FEATURE_SSBS
),
9938 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9940 | AARCH64_FEATURE_RCPC
9941 | AARCH64_FEATURE_DOTPROD
9942 | AARCH64_FEATURE_SSBS
9943 | AARCH64_FEATURE_PROFILE
),
9945 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9947 | AARCH64_FEATURE_RCPC
9948 | AARCH64_FEATURE_DOTPROD
9949 | AARCH64_FEATURE_SSBS
9950 | AARCH64_FEATURE_PROFILE
),
9952 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9953 AARCH64_FEATURE_DOTPROD
9954 | AARCH64_FEATURE_F16
9955 | AARCH64_FEATURE_FLAGM
9956 | AARCH64_FEATURE_PAC
9957 | AARCH64_FEATURE_PROFILE
9958 | AARCH64_FEATURE_RCPC
9959 | AARCH64_FEATURE_SSBS
),
9961 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9962 AARCH64_FEATURE_BFLOAT16
9963 | AARCH64_FEATURE_I8MM
9964 | AARCH64_FEATURE_MEMTAG
9965 | AARCH64_FEATURE_SVE2_BITPERM
),
9967 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9968 AARCH64_FEATURE_BFLOAT16
9969 | AARCH64_FEATURE_I8MM
9970 | AARCH64_FEATURE_MEMTAG
9971 | AARCH64_FEATURE_SVE2_BITPERM
),
9973 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9974 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9975 | AARCH64_FEATURE_DOTPROD
9976 | AARCH64_FEATURE_PROFILE
),
9978 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9979 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9980 "Samsung Exynos M1"},
9981 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9982 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9983 | AARCH64_FEATURE_RDMA
),
9985 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9986 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9987 | AARCH64_FEATURE_DOTPROD
9988 | AARCH64_FEATURE_SSBS
),
9990 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9991 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9992 | AARCH64_FEATURE_DOTPROD
9993 | AARCH64_FEATURE_PROFILE
),
9995 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9996 AARCH64_FEATURE_BFLOAT16
9997 | AARCH64_FEATURE_I8MM
9998 | AARCH64_FEATURE_F16
9999 | AARCH64_FEATURE_SVE
10000 | AARCH64_FEATURE_SVE2
10001 | AARCH64_FEATURE_SVE2_BITPERM
10002 | AARCH64_FEATURE_MEMTAG
10003 | AARCH64_FEATURE_RNG
),
10005 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
10006 AARCH64_FEATURE_PROFILE
10007 | AARCH64_FEATURE_CVADP
10008 | AARCH64_FEATURE_SVE
10009 | AARCH64_FEATURE_SSBS
10010 | AARCH64_FEATURE_RNG
10011 | AARCH64_FEATURE_F16
10012 | AARCH64_FEATURE_BFLOAT16
10013 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
10014 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10015 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
10016 | AARCH64_FEATURE_RDMA
),
10017 "Qualcomm QDF24XX"},
10018 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
10019 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
10020 "Qualcomm Saphira"},
10021 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10022 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
10023 "Cavium ThunderX"},
10024 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
10025 AARCH64_FEATURE_CRYPTO
),
10026 "Broadcom Vulcan"},
10027 /* The 'xgene-1' name is an older name for 'xgene1', which was used
10028 in earlier releases and is superseded by 'xgene1' in all
10030 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
10031 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
10032 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10033 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
10034 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
10035 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10036 AARCH64_FEATURE_F16
10037 | AARCH64_FEATURE_RCPC
10038 | AARCH64_FEATURE_DOTPROD
10039 | AARCH64_FEATURE_SSBS
10040 | AARCH64_FEATURE_PROFILE
),
10042 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
10043 AARCH64_FEATURE_BFLOAT16
10044 | AARCH64_FEATURE_I8MM
10045 | AARCH64_FEATURE_MEMTAG
10046 | AARCH64_FEATURE_SVE2_BITPERM
),
10048 {"generic", AARCH64_ARCH_V8
, NULL
},
10050 {NULL
, AARCH64_ARCH_NONE
, NULL
}
10053 struct aarch64_arch_option_table
10056 const aarch64_feature_set value
;
10059 /* This list should, at a minimum, contain all the architecture names
10060 recognized by GCC. */
10061 static const struct aarch64_arch_option_table aarch64_archs
[] = {
10062 {"all", AARCH64_ANY
},
10063 {"armv8-a", AARCH64_ARCH_V8
},
10064 {"armv8.1-a", AARCH64_ARCH_V8_1
},
10065 {"armv8.2-a", AARCH64_ARCH_V8_2
},
10066 {"armv8.3-a", AARCH64_ARCH_V8_3
},
10067 {"armv8.4-a", AARCH64_ARCH_V8_4
},
10068 {"armv8.5-a", AARCH64_ARCH_V8_5
},
10069 {"armv8.6-a", AARCH64_ARCH_V8_6
},
10070 {"armv8.7-a", AARCH64_ARCH_V8_7
},
10071 {"armv8.8-a", AARCH64_ARCH_V8_8
},
10072 {"armv8-r", AARCH64_ARCH_V8_R
},
10073 {"armv9-a", AARCH64_ARCH_V9
},
10074 {"armv9.1-a", AARCH64_ARCH_V9_1
},
10075 {"armv9.2-a", AARCH64_ARCH_V9_2
},
10076 {"armv9.3-a", AARCH64_ARCH_V9_3
},
10077 {NULL
, AARCH64_ARCH_NONE
}
10080 /* ISA extensions. */
10081 struct aarch64_option_cpu_value_table
10084 const aarch64_feature_set value
;
10085 const aarch64_feature_set require
; /* Feature dependencies. */
10088 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
10089 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
10090 AARCH64_ARCH_NONE
},
10091 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
10092 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10093 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
10094 AARCH64_ARCH_NONE
},
10095 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
10096 AARCH64_ARCH_NONE
},
10097 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
10098 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10099 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
10100 AARCH64_ARCH_NONE
},
10101 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
10102 AARCH64_ARCH_NONE
},
10103 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
10104 AARCH64_ARCH_NONE
},
10105 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
10106 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10107 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
10108 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10109 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
10110 AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0)},
10111 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
10112 AARCH64_ARCH_NONE
},
10113 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
10114 AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0)},
10115 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
10116 AARCH64_ARCH_NONE
},
10117 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
10118 AARCH64_FEATURE (AARCH64_FEATURE_F16
10119 | AARCH64_FEATURE_SIMD
, 0)},
10120 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
10121 AARCH64_ARCH_NONE
},
10122 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
10123 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10124 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
10125 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10126 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
10127 AARCH64_ARCH_NONE
},
10128 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
10129 AARCH64_ARCH_NONE
},
10130 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
10131 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10132 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
10133 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10134 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
10135 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
10136 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
10137 AARCH64_ARCH_NONE
},
10138 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
10139 AARCH64_ARCH_NONE
},
10140 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
10141 AARCH64_ARCH_NONE
},
10142 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
10143 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10144 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
10145 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10146 | AARCH64_FEATURE_SM4
, 0)},
10147 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
10148 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10149 | AARCH64_FEATURE_AES
, 0)},
10150 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
10151 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10152 | AARCH64_FEATURE_SHA3
, 0)},
10153 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
10154 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
10155 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
10156 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10157 | AARCH64_FEATURE_BFLOAT16
, 0)},
10158 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10159 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10160 {"sme-f64f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10161 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10162 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10163 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10164 {"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10165 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10166 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
10167 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10168 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
10169 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10170 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
10171 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10172 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
10173 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10174 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
10175 AARCH64_ARCH_NONE
},
10176 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
10177 AARCH64_ARCH_NONE
},
10178 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
10179 AARCH64_ARCH_NONE
},
10180 {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS
, 0),
10181 AARCH64_ARCH_NONE
},
10182 {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC
, 0),
10183 AARCH64_ARCH_NONE
},
10184 {"cssc", AARCH64_FEATURE (AARCH64_FEATURE_CSSC
, 0),
10185 AARCH64_ARCH_NONE
},
10186 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
10189 struct aarch64_long_option_table
10191 const char *option
; /* Substring to match. */
10192 const char *help
; /* Help information. */
10193 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
10194 char *deprecated
; /* If non-null, print this message. */
10197 /* Transitive closure of features depending on set. */
10198 static aarch64_feature_set
10199 aarch64_feature_disable_set (aarch64_feature_set set
)
10201 const struct aarch64_option_cpu_value_table
*opt
;
10202 aarch64_feature_set prev
= 0;
10204 while (prev
!= set
) {
10206 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10207 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10208 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10213 /* Transitive closure of dependencies of set. */
10214 static aarch64_feature_set
10215 aarch64_feature_enable_set (aarch64_feature_set set
)
10217 const struct aarch64_option_cpu_value_table
*opt
;
10218 aarch64_feature_set prev
= 0;
10220 while (prev
!= set
) {
10222 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10223 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10224 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10230 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10233 /* We insist on extensions being added before being removed. We achieve
10234 this by using the ADDING_VALUE variable to indicate whether we are
10235 adding an extension (1) or removing it (0) and only allowing it to
10236 change in the order -1 -> 1 -> 0. */
10237 int adding_value
= -1;
10238 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10240 /* Copy the feature set, so that we can modify it. */
10241 *ext_set
= **opt_p
;
10244 while (str
!= NULL
&& *str
!= 0)
10246 const struct aarch64_option_cpu_value_table
*opt
;
10247 const char *ext
= NULL
;
10254 as_bad (_("invalid architectural extension"));
10258 ext
= strchr (++str
, '+');
10262 optlen
= ext
- str
;
10264 optlen
= strlen (str
);
10266 if (optlen
>= 2 && startswith (str
, "no"))
10268 if (adding_value
!= 0)
10273 else if (optlen
> 0)
10275 if (adding_value
== -1)
10277 else if (adding_value
!= 1)
10279 as_bad (_("must specify extensions to add before specifying "
10280 "those to remove"));
10287 as_bad (_("missing architectural extension"));
10291 gas_assert (adding_value
!= -1);
10293 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10294 if (strncmp (opt
->name
, str
, optlen
) == 0)
10296 aarch64_feature_set set
;
10298 /* Add or remove the extension. */
10301 set
= aarch64_feature_enable_set (opt
->value
);
10302 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10306 set
= aarch64_feature_disable_set (opt
->value
);
10307 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10312 if (opt
->name
== NULL
)
10314 as_bad (_("unknown architectural extension `%s'"), str
);
10325 aarch64_parse_cpu (const char *str
)
10327 const struct aarch64_cpu_option_table
*opt
;
10328 const char *ext
= strchr (str
, '+');
10332 optlen
= ext
- str
;
10334 optlen
= strlen (str
);
10338 as_bad (_("missing cpu name `%s'"), str
);
10342 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10343 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10345 mcpu_cpu_opt
= &opt
->value
;
10347 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10352 as_bad (_("unknown cpu `%s'"), str
);
10357 aarch64_parse_arch (const char *str
)
10359 const struct aarch64_arch_option_table
*opt
;
10360 const char *ext
= strchr (str
, '+');
10364 optlen
= ext
- str
;
10366 optlen
= strlen (str
);
10370 as_bad (_("missing architecture name `%s'"), str
);
10374 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10375 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10377 march_cpu_opt
= &opt
->value
;
10379 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10384 as_bad (_("unknown architecture `%s'\n"), str
);
10389 struct aarch64_option_abi_value_table
10392 enum aarch64_abi_type value
;
10395 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10397 {"ilp32", AARCH64_ABI_ILP32
},
10398 {"lp64", AARCH64_ABI_LP64
},
10400 {"llp64", AARCH64_ABI_LLP64
},
10405 aarch64_parse_abi (const char *str
)
10409 if (str
[0] == '\0')
10411 as_bad (_("missing abi name `%s'"), str
);
10415 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10416 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10418 aarch64_abi
= aarch64_abis
[i
].value
;
10422 as_bad (_("unknown abi `%s'\n"), str
);
10426 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10427 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10428 aarch64_parse_abi
, NULL
},
10429 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10430 aarch64_parse_cpu
, NULL
},
10431 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10432 aarch64_parse_arch
, NULL
},
10433 {NULL
, NULL
, 0, NULL
}
10437 md_parse_option (int c
, const char *arg
)
10439 struct aarch64_option_table
*opt
;
10440 struct aarch64_long_option_table
*lopt
;
10446 target_big_endian
= 1;
10452 target_big_endian
= 0;
10457 /* Listing option. Just ignore these, we don't support additional
10462 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10464 if (c
== opt
->option
[0]
10465 && ((arg
== NULL
&& opt
->option
[1] == 0)
10466 || streq (arg
, opt
->option
+ 1)))
10468 /* If the option is deprecated, tell the user. */
10469 if (opt
->deprecated
!= NULL
)
10470 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10471 arg
? arg
: "", _(opt
->deprecated
));
10473 if (opt
->var
!= NULL
)
10474 *opt
->var
= opt
->value
;
10480 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10482 /* These options are expected to have an argument. */
10483 if (c
== lopt
->option
[0]
10485 && startswith (arg
, lopt
->option
+ 1))
10487 /* If the option is deprecated, tell the user. */
10488 if (lopt
->deprecated
!= NULL
)
10489 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10490 _(lopt
->deprecated
));
10492 /* Call the sup-option parser. */
10493 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10504 md_show_usage (FILE * fp
)
10506 struct aarch64_option_table
*opt
;
10507 struct aarch64_long_option_table
*lopt
;
10509 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10511 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10512 if (opt
->help
!= NULL
)
10513 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10515 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10516 if (lopt
->help
!= NULL
)
10517 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10521 -EB assemble code for a big-endian cpu\n"));
10526 -EL assemble code for a little-endian cpu\n"));
10530 /* Parse a .cpu directive. */
10533 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10535 const struct aarch64_cpu_option_table
*opt
;
10541 name
= input_line_pointer
;
10542 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10543 saved_char
= *input_line_pointer
;
10544 *input_line_pointer
= 0;
10546 ext
= strchr (name
, '+');
10549 optlen
= ext
- name
;
10551 optlen
= strlen (name
);
10553 /* Skip the first "all" entry. */
10554 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10555 if (strlen (opt
->name
) == optlen
10556 && strncmp (name
, opt
->name
, optlen
) == 0)
10558 mcpu_cpu_opt
= &opt
->value
;
10560 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10563 cpu_variant
= *mcpu_cpu_opt
;
10565 *input_line_pointer
= saved_char
;
10566 demand_empty_rest_of_line ();
10569 as_bad (_("unknown cpu `%s'"), name
);
10570 *input_line_pointer
= saved_char
;
10571 ignore_rest_of_line ();
10575 /* Parse a .arch directive. */
10578 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10580 const struct aarch64_arch_option_table
*opt
;
10586 name
= input_line_pointer
;
10587 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10588 saved_char
= *input_line_pointer
;
10589 *input_line_pointer
= 0;
10591 ext
= strchr (name
, '+');
10594 optlen
= ext
- name
;
10596 optlen
= strlen (name
);
10598 /* Skip the first "all" entry. */
10599 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10600 if (strlen (opt
->name
) == optlen
10601 && strncmp (name
, opt
->name
, optlen
) == 0)
10603 mcpu_cpu_opt
= &opt
->value
;
10605 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10608 cpu_variant
= *mcpu_cpu_opt
;
10610 *input_line_pointer
= saved_char
;
10611 demand_empty_rest_of_line ();
10615 as_bad (_("unknown architecture `%s'\n"), name
);
10616 *input_line_pointer
= saved_char
;
10617 ignore_rest_of_line ();
10620 /* Parse a .arch_extension directive. */
10623 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10626 char *ext
= input_line_pointer
;
10628 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10629 saved_char
= *input_line_pointer
;
10630 *input_line_pointer
= 0;
10632 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10635 cpu_variant
= *mcpu_cpu_opt
;
10637 *input_line_pointer
= saved_char
;
10638 demand_empty_rest_of_line ();
10641 /* Copy symbol information. */
10644 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10646 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10650 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10651 This is needed so AArch64 specific st_other values can be independently
10652 specified for an IFUNC resolver (that is called by the dynamic linker)
10653 and the symbol it resolves (aliased to the resolver). In particular,
10654 if a function symbol has special st_other value set via directives,
10655 then attaching an IFUNC resolver to that symbol should not override
10656 the st_other setting. Requiring the directive on the IFUNC resolver
10657 symbol would be unexpected and problematic in C code, where the two
10658 symbols appear as two independent function declarations. */
10661 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10663 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10664 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10665 /* If size is unset, copy size from src. Because we don't track whether
10666 .size has been used, we can't differentiate .size dest, 0 from the case
10667 where dest's size is unset. */
10668 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
10672 destelf
->size
= XNEW (expressionS
);
10673 *destelf
->size
= *srcelf
->size
;
10675 S_SET_SIZE (dest
, S_GET_SIZE (src
));