1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in vector_type_el. */
91 #define NTA_HASINDEX 2
95 enum vector_el_type type
;
96 unsigned char defined
;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type
;
108 enum aarch64_opnd opnd
;
110 unsigned need_libopcodes_p
: 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind
;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool
: 1;
131 typedef struct aarch64_instruction aarch64_instruction
;
133 static aarch64_instruction inst
;
135 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
136 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
159 inst
.parsing_error
.error
= NULL
;
162 static inline bfd_boolean
165 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
168 static inline const char *
169 get_error_message (void)
171 return inst
.parsing_error
.error
;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst
.parsing_error
.kind
;
181 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
183 inst
.parsing_error
.kind
= kind
;
184 inst
.parsing_error
.error
= error
;
188 set_recoverable_error (const char *error
)
190 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
202 set_syntax_error (const char *error
)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
208 set_first_syntax_error (const char *error
)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
215 set_fatal_syntax_error (const char *error
)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc
;
250 /* Macros to define the register types and masks for the purpose
253 #undef AARCH64_REG_TYPES
254 #define AARCH64_REG_TYPES \
255 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
256 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
257 BASIC_REG_TYPE(SP_32) /* wsp */ \
258 BASIC_REG_TYPE(SP_64) /* sp */ \
259 BASIC_REG_TYPE(Z_32) /* wzr */ \
260 BASIC_REG_TYPE(Z_64) /* xzr */ \
261 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
262 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
263 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
264 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
265 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
266 BASIC_REG_TYPE(CN) /* c[0-7] */ \
267 BASIC_REG_TYPE(VN) /* v[0-31] */ \
268 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
269 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
270 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
271 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
272 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
273 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
274 /* Typecheck: any [BHSDQ]P FP. */ \
275 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
276 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
277 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
278 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
279 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
280 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
281 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
282 /* Any integer register; used for error messages only. */ \
283 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
284 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
285 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
286 /* Pseudo type to mark the end of the enumerator sequence. */ \
289 #undef BASIC_REG_TYPE
290 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
291 #undef MULTI_REG_TYPE
292 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
294 /* Register type enumerators. */
295 typedef enum aarch64_reg_type_
297 /* A list of REG_TYPE_*. */
301 #undef BASIC_REG_TYPE
302 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
304 #define REG_TYPE(T) (1 << REG_TYPE_##T)
305 #undef MULTI_REG_TYPE
306 #define MULTI_REG_TYPE(T,V) V,
308 /* Structure for a hash table entry for a register. */
312 unsigned char number
;
313 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
314 unsigned char builtin
;
317 /* Values indexed by aarch64_reg_type to assist the type checking. */
318 static const unsigned reg_type_masks
[] =
323 #undef BASIC_REG_TYPE
325 #undef MULTI_REG_TYPE
326 #undef AARCH64_REG_TYPES
328 /* Diagnostics used when we don't get a register of the expected type.
329 Note: this has to synchronized with aarch64_reg_type definitions
332 get_reg_expected_msg (aarch64_reg_type reg_type
)
339 msg
= N_("integer 32-bit register expected");
342 msg
= N_("integer 64-bit register expected");
345 msg
= N_("integer register expected");
347 case REG_TYPE_R_Z_SP
:
348 msg
= N_("integer, zero or SP register expected");
351 msg
= N_("8-bit SIMD scalar register expected");
354 msg
= N_("16-bit SIMD scalar or floating-point half precision "
355 "register expected");
358 msg
= N_("32-bit SIMD scalar or floating-point single precision "
359 "register expected");
362 msg
= N_("64-bit SIMD scalar or floating-point double precision "
363 "register expected");
366 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
367 "register expected");
370 msg
= N_("C0 - C15 expected");
372 case REG_TYPE_R_Z_BHSDQ_V
:
373 msg
= N_("register expected");
375 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
376 msg
= N_("SIMD scalar or floating-point register expected");
378 case REG_TYPE_VN
: /* any V reg */
379 msg
= N_("vector register expected");
382 as_fatal (_("invalid register type %d"), reg_type
);
387 /* Some well known registers that we refer to directly elsewhere. */
390 /* Instructions take 4 bytes in the object file. */
393 /* Define some common error messages. */
394 #define BAD_SP _("SP not allowed here")
396 static struct hash_control
*aarch64_ops_hsh
;
397 static struct hash_control
*aarch64_cond_hsh
;
398 static struct hash_control
*aarch64_shift_hsh
;
399 static struct hash_control
*aarch64_sys_regs_hsh
;
400 static struct hash_control
*aarch64_pstatefield_hsh
;
401 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
402 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
403 static struct hash_control
*aarch64_sys_regs_at_hsh
;
404 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
405 static struct hash_control
*aarch64_reg_hsh
;
406 static struct hash_control
*aarch64_barrier_opt_hsh
;
407 static struct hash_control
*aarch64_nzcv_hsh
;
408 static struct hash_control
*aarch64_pldop_hsh
;
409 static struct hash_control
*aarch64_hint_opt_hsh
;
411 /* Stuff needed to resolve the label ambiguity
420 static symbolS
*last_label_seen
;
422 /* Literal pool structure. Held on a per-section
423 and per-sub-section basis. */
425 #define MAX_LITERAL_POOL_SIZE 1024
426 typedef struct literal_expression
429 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
430 LITTLENUM_TYPE
* bignum
;
431 } literal_expression
;
433 typedef struct literal_pool
435 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
436 unsigned int next_free_entry
;
442 struct literal_pool
*next
;
445 /* Pointer to a linked list of literal pools. */
446 static literal_pool
*list_of_pools
= NULL
;
450 /* This array holds the chars that always start a comment. If the
451 pre-processor is disabled, these aren't very useful. */
452 const char comment_chars
[] = "";
454 /* This array holds the chars that only start a comment at the beginning of
455 a line. If the line seems to have the form '# 123 filename'
456 .line and .file directives will appear in the pre-processed output. */
457 /* Note that input_file.c hand checks for '#' at the beginning of the
458 first line of the input file. This is because the compiler outputs
459 #NO_APP at the beginning of its output. */
460 /* Also note that comments like this one will always work. */
461 const char line_comment_chars
[] = "#";
463 const char line_separator_chars
[] = ";";
465 /* Chars that can be used to separate mant
466 from exp in floating point numbers. */
467 const char EXP_CHARS
[] = "eE";
469 /* Chars that mean this number is a floating point constant. */
473 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
475 /* Prefix character that indicates the start of an immediate value. */
476 #define is_immediate_prefix(C) ((C) == '#')
478 /* Separator character handling. */
480 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
482 static inline bfd_boolean
483 skip_past_char (char **str
, char c
)
494 #define skip_past_comma(str) skip_past_char (str, ',')
496 /* Arithmetic expressions (possibly involving symbols). */
498 static bfd_boolean in_my_get_expression_p
= FALSE
;
500 /* Third argument to my_get_expression. */
501 #define GE_NO_PREFIX 0
502 #define GE_OPT_PREFIX 1
504 /* Return TRUE if the string pointed by *STR is successfully parsed
505 as an valid expression; *EP will be filled with the information of
506 such an expression. Otherwise return FALSE. */
509 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
514 int prefix_present_p
= 0;
521 if (is_immediate_prefix (**str
))
524 prefix_present_p
= 1;
531 memset (ep
, 0, sizeof (expressionS
));
533 save_in
= input_line_pointer
;
534 input_line_pointer
= *str
;
535 in_my_get_expression_p
= TRUE
;
536 seg
= expression (ep
);
537 in_my_get_expression_p
= FALSE
;
539 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
541 /* We found a bad expression in md_operand(). */
542 *str
= input_line_pointer
;
543 input_line_pointer
= save_in
;
544 if (prefix_present_p
&& ! error_p ())
545 set_fatal_syntax_error (_("bad expression"));
547 set_first_syntax_error (_("bad expression"));
552 if (seg
!= absolute_section
553 && seg
!= text_section
554 && seg
!= data_section
555 && seg
!= bss_section
&& seg
!= undefined_section
)
557 set_syntax_error (_("bad segment"));
558 *str
= input_line_pointer
;
559 input_line_pointer
= save_in
;
566 *str
= input_line_pointer
;
567 input_line_pointer
= save_in
;
571 /* Turn a string in input_line_pointer into a floating point constant
572 of type TYPE, and store the appropriate bytes in *LITP. The number
573 of LITTLENUMS emitted is stored in *SIZEP. An error message is
574 returned, or NULL on OK. */
577 md_atof (int type
, char *litP
, int *sizeP
)
579 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
582 /* We handle all bad expressions here, so that we can report the faulty
583 instruction in the error message. */
585 md_operand (expressionS
* exp
)
587 if (in_my_get_expression_p
)
588 exp
->X_op
= O_illegal
;
591 /* Immediate values. */
593 /* Errors may be set multiple times during parsing or bit encoding
594 (particularly in the Neon bits), but usually the earliest error which is set
595 will be the most meaningful. Avoid overwriting it with later (cascading)
596 errors by calling this function. */
599 first_error (const char *error
)
602 set_syntax_error (error
);
605 /* Similiar to first_error, but this function accepts formatted error
608 first_error_fmt (const char *format
, ...)
613 /* N.B. this single buffer will not cause error messages for different
614 instructions to pollute each other; this is because at the end of
615 processing of each assembly line, error message if any will be
616 collected by as_bad. */
617 static char buffer
[size
];
621 int ret ATTRIBUTE_UNUSED
;
622 va_start (args
, format
);
623 ret
= vsnprintf (buffer
, size
, format
, args
);
624 know (ret
<= size
- 1 && ret
>= 0);
626 set_syntax_error (buffer
);
630 /* Register parsing. */
632 /* Generic register parser which is called by other specialized
634 CCP points to what should be the beginning of a register name.
635 If it is indeed a valid register name, advance CCP over it and
636 return the reg_entry structure; otherwise return NULL.
637 It does not issue diagnostics. */
640 parse_reg (char **ccp
)
646 #ifdef REGISTER_PREFIX
647 if (*start
!= REGISTER_PREFIX
)
653 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
658 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
660 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
669 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
672 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
674 if (reg
->type
== type
)
679 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
680 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
681 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
682 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
683 case REG_TYPE_VN
: /* Vector register. */
684 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
685 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
686 == reg_type_masks
[reg
->type
]);
688 as_fatal ("unhandled type %d", type
);
693 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
694 Return the register number otherwise. *ISREG32 is set to one if the
695 register is 32-bit wide; *ISREGZERO is set to one if the register is
696 of type Z_32 or Z_64.
697 Note that this function does not issue any diagnostics. */
700 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
701 int *isreg32
, int *isregzero
)
704 const reg_entry
*reg
= parse_reg (&str
);
709 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
718 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
723 *isreg32
= reg
->type
== REG_TYPE_R_32
;
730 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
742 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
743 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
744 otherwise return FALSE.
746 Accept only one occurrence of:
747 8b 16b 2h 4h 8h 2s 4s 1d 2d
750 parse_vector_type_for_operand (struct vector_type_el
*parsed_type
, char **str
)
754 unsigned element_size
;
755 enum vector_el_type type
;
765 width
= strtoul (ptr
, &ptr
, 10);
766 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
768 first_error_fmt (_("bad size %d in vector width specifier"), width
);
773 switch (TOLOWER (*ptr
))
801 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
803 first_error (_("missing element size"));
806 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128
807 && !(width
== 2 && element_size
== 16))
810 ("invalid element size %d and vector size combination %c"),
816 parsed_type
->type
= type
;
817 parsed_type
->width
= width
;
824 /* Parse a register of the type TYPE.
826 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
827 name or the parsed register is not of TYPE.
829 Otherwise return the register number, and optionally fill in the actual
830 type of the register in *RTYPE when multiple alternatives were given, and
831 return the register shape and element index information in *TYPEINFO.
833 IN_REG_LIST should be set with TRUE if the caller is parsing a register
837 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
838 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
841 const reg_entry
*reg
= parse_reg (&str
);
842 struct vector_type_el atype
;
843 struct vector_type_el parsetype
;
844 bfd_boolean is_typed_vecreg
= FALSE
;
847 atype
.type
= NT_invtype
;
855 set_default_error ();
859 if (! aarch64_check_reg_type (reg
, type
))
861 DEBUG_TRACE ("reg type check failed");
862 set_default_error ();
867 if (type
== REG_TYPE_VN
&& *str
== '.')
869 if (!parse_vector_type_for_operand (&parsetype
, &str
))
872 /* Register if of the form Vn.[bhsdq]. */
873 is_typed_vecreg
= TRUE
;
875 if (parsetype
.width
== 0)
876 /* Expect index. In the new scheme we cannot have
877 Vn.[bhsdq] represent a scalar. Therefore any
878 Vn.[bhsdq] should have an index following it.
879 Except in reglists ofcourse. */
880 atype
.defined
|= NTA_HASINDEX
;
882 atype
.defined
|= NTA_HASTYPE
;
884 atype
.type
= parsetype
.type
;
885 atype
.width
= parsetype
.width
;
888 if (skip_past_char (&str
, '['))
892 /* Reject Sn[index] syntax. */
893 if (!is_typed_vecreg
)
895 first_error (_("this type of register can't be indexed"));
899 if (in_reg_list
== TRUE
)
901 first_error (_("index not allowed inside register list"));
905 atype
.defined
|= NTA_HASINDEX
;
907 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
909 if (exp
.X_op
!= O_constant
)
911 first_error (_("constant expression required"));
915 if (! skip_past_char (&str
, ']'))
918 atype
.index
= exp
.X_add_number
;
920 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
922 /* Indexed vector register expected. */
923 first_error (_("indexed vector register expected"));
927 /* A vector reg Vn should be typed or indexed. */
928 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
930 first_error (_("invalid use of vector register"));
946 Return the register number on success; return PARSE_FAIL otherwise.
948 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
949 the register (e.g. NEON double or quad reg when either has been requested).
951 If this is a NEON vector register with additional type information, fill
952 in the struct pointed to by VECTYPE (if non-NULL).
954 This parser does not handle register list. */
957 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
958 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
960 struct vector_type_el atype
;
962 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
963 /*in_reg_list= */ FALSE
);
965 if (reg
== PARSE_FAIL
)
976 static inline bfd_boolean
977 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
981 && e1
.defined
== e2
.defined
982 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
985 /* This function parses a list of vector registers of type TYPE.
986 On success, it returns the parsed register list information in the
987 following encoded format:
989 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
990 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
992 The information of the register shape and/or index is returned in
995 It returns PARSE_FAIL if the register list is invalid.
997 The list contains one to four registers.
998 Each register can be one of:
1001 All <T> should be identical.
1002 All <index> should be identical.
1003 There are restrictions on <Vt> numbers which are checked later
1004 (by reg_list_valid_p). */
1007 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1008 struct vector_type_el
*vectype
)
1012 struct vector_type_el typeinfo
, typeinfo_first
;
1017 bfd_boolean error
= FALSE
;
1018 bfd_boolean expect_index
= FALSE
;
1022 set_syntax_error (_("expecting {"));
1028 typeinfo_first
.defined
= 0;
1029 typeinfo_first
.type
= NT_invtype
;
1030 typeinfo_first
.width
= -1;
1031 typeinfo_first
.index
= 0;
1040 str
++; /* skip over '-' */
1043 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1044 /*in_reg_list= */ TRUE
);
1045 if (val
== PARSE_FAIL
)
1047 set_first_syntax_error (_("invalid vector register in list"));
1051 /* reject [bhsd]n */
1052 if (typeinfo
.defined
== 0)
1054 set_first_syntax_error (_("invalid scalar register in list"));
1059 if (typeinfo
.defined
& NTA_HASINDEX
)
1060 expect_index
= TRUE
;
1064 if (val
< val_range
)
1066 set_first_syntax_error
1067 (_("invalid range in vector register list"));
1076 typeinfo_first
= typeinfo
;
1077 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1079 set_first_syntax_error
1080 (_("type mismatch in vector register list"));
1085 for (i
= val_range
; i
<= val
; i
++)
1087 ret_val
|= i
<< (5 * nb_regs
);
1092 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1094 skip_whitespace (str
);
1097 set_first_syntax_error (_("end of vector register list not found"));
1102 skip_whitespace (str
);
1106 if (skip_past_char (&str
, '['))
1110 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1111 if (exp
.X_op
!= O_constant
)
1113 set_first_syntax_error (_("constant expression required."));
1116 if (! skip_past_char (&str
, ']'))
1119 typeinfo_first
.index
= exp
.X_add_number
;
1123 set_first_syntax_error (_("expected index"));
1130 set_first_syntax_error (_("too many registers in vector register list"));
1133 else if (nb_regs
== 0)
1135 set_first_syntax_error (_("empty vector register list"));
1141 *vectype
= typeinfo_first
;
1143 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1146 /* Directives: register aliases. */
1149 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1154 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1157 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1160 /* Only warn about a redefinition if it's not defined as the
1162 else if (new->number
!= number
|| new->type
!= type
)
1163 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1168 name
= xstrdup (str
);
1169 new = XNEW (reg_entry
);
1172 new->number
= number
;
1174 new->builtin
= FALSE
;
1176 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1182 /* Look for the .req directive. This is of the form:
1184 new_register_name .req existing_register_name
1186 If we find one, or if it looks sufficiently like one that we want to
1187 handle any error here, return TRUE. Otherwise return FALSE. */
1190 create_register_alias (char *newname
, char *p
)
1192 const reg_entry
*old
;
1193 char *oldname
, *nbuf
;
1196 /* The input scrubber ensures that whitespace after the mnemonic is
1197 collapsed to single spaces. */
1199 if (strncmp (oldname
, " .req ", 6) != 0)
1203 if (*oldname
== '\0')
1206 old
= hash_find (aarch64_reg_hsh
, oldname
);
1209 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1213 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1214 the desired alias name, and p points to its end. If not, then
1215 the desired alias name is in the global original_case_string. */
1216 #ifdef TC_CASE_SENSITIVE
1219 newname
= original_case_string
;
1220 nlen
= strlen (newname
);
1223 nbuf
= xmemdup0 (newname
, nlen
);
1225 /* Create aliases under the new name as stated; an all-lowercase
1226 version of the new name; and an all-uppercase version of the new
1228 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1230 for (p
= nbuf
; *p
; p
++)
1233 if (strncmp (nbuf
, newname
, nlen
))
1235 /* If this attempt to create an additional alias fails, do not bother
1236 trying to create the all-lower case alias. We will fail and issue
1237 a second, duplicate error message. This situation arises when the
1238 programmer does something like:
1241 The second .req creates the "Foo" alias but then fails to create
1242 the artificial FOO alias because it has already been created by the
1244 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1251 for (p
= nbuf
; *p
; p
++)
1254 if (strncmp (nbuf
, newname
, nlen
))
1255 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1262 /* Should never be called, as .req goes between the alias and the
1263 register name, not at the beginning of the line. */
1265 s_req (int a ATTRIBUTE_UNUSED
)
1267 as_bad (_("invalid syntax for .req directive"));
1270 /* The .unreq directive deletes an alias which was previously defined
1271 by .req. For example:
1277 s_unreq (int a ATTRIBUTE_UNUSED
)
1282 name
= input_line_pointer
;
1284 while (*input_line_pointer
!= 0
1285 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1286 ++input_line_pointer
;
1288 saved_char
= *input_line_pointer
;
1289 *input_line_pointer
= 0;
1292 as_bad (_("invalid syntax for .unreq directive"));
1295 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1298 as_bad (_("unknown register alias '%s'"), name
);
1299 else if (reg
->builtin
)
1300 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1307 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1308 free ((char *) reg
->name
);
1311 /* Also locate the all upper case and all lower case versions.
1312 Do not complain if we cannot find one or the other as it
1313 was probably deleted above. */
1315 nbuf
= strdup (name
);
1316 for (p
= nbuf
; *p
; p
++)
1318 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1321 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1322 free ((char *) reg
->name
);
1326 for (p
= nbuf
; *p
; p
++)
1328 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1331 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1332 free ((char *) reg
->name
);
1340 *input_line_pointer
= saved_char
;
1341 demand_empty_rest_of_line ();
1344 /* Directives: Instruction set selection. */
1347 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1348 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1349 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1350 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1352 /* Create a new mapping symbol for the transition to STATE. */
1355 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1358 const char *symname
;
1365 type
= BSF_NO_FLAGS
;
1369 type
= BSF_NO_FLAGS
;
1375 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1376 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1378 /* Save the mapping symbols for future reference. Also check that
1379 we do not place two mapping symbols at the same offset within a
1380 frag. We'll handle overlap between frags in
1381 check_mapping_symbols.
1383 If .fill or other data filling directive generates zero sized data,
1384 the mapping symbol for the following code will have the same value
1385 as the one generated for the data filling directive. In this case,
1386 we replace the old symbol with the new one at the same address. */
1389 if (frag
->tc_frag_data
.first_map
!= NULL
)
1391 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1392 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1395 frag
->tc_frag_data
.first_map
= symbolP
;
1397 if (frag
->tc_frag_data
.last_map
!= NULL
)
1399 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1400 S_GET_VALUE (symbolP
));
1401 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1402 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1405 frag
->tc_frag_data
.last_map
= symbolP
;
1408 /* We must sometimes convert a region marked as code to data during
1409 code alignment, if an odd number of bytes have to be padded. The
1410 code mapping symbol is pushed to an aligned address. */
1413 insert_data_mapping_symbol (enum mstate state
,
1414 valueT value
, fragS
* frag
, offsetT bytes
)
1416 /* If there was already a mapping symbol, remove it. */
1417 if (frag
->tc_frag_data
.last_map
!= NULL
1418 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1419 frag
->fr_address
+ value
)
1421 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1425 know (frag
->tc_frag_data
.first_map
== symp
);
1426 frag
->tc_frag_data
.first_map
= NULL
;
1428 frag
->tc_frag_data
.last_map
= NULL
;
1429 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1432 make_mapping_symbol (MAP_DATA
, value
, frag
);
1433 make_mapping_symbol (state
, value
+ bytes
, frag
);
1436 static void mapping_state_2 (enum mstate state
, int max_chars
);
1438 /* Set the mapping state to STATE. Only call this when about to
1439 emit some STATE bytes to the file. */
1442 mapping_state (enum mstate state
)
1444 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1446 if (state
== MAP_INSN
)
1447 /* AArch64 instructions require 4-byte alignment. When emitting
1448 instructions into any section, record the appropriate section
1450 record_alignment (now_seg
, 2);
1452 if (mapstate
== state
)
1453 /* The mapping symbol has already been emitted.
1454 There is nothing else to do. */
1457 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1458 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1459 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1460 evaluated later in the next else. */
1462 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1464 /* Only add the symbol if the offset is > 0:
1465 if we're at the first frag, check it's size > 0;
1466 if we're not at the first frag, then for sure
1467 the offset is > 0. */
1468 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1469 const int add_symbol
= (frag_now
!= frag_first
)
1470 || (frag_now_fix () > 0);
1473 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1477 mapping_state_2 (state
, 0);
1480 /* Same as mapping_state, but MAX_CHARS bytes have already been
1481 allocated. Put the mapping symbol that far back. */
1484 mapping_state_2 (enum mstate state
, int max_chars
)
1486 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1488 if (!SEG_NORMAL (now_seg
))
1491 if (mapstate
== state
)
1492 /* The mapping symbol has already been emitted.
1493 There is nothing else to do. */
1496 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1497 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1500 #define mapping_state(x) /* nothing */
1501 #define mapping_state_2(x, y) /* nothing */
1504 /* Directives: sectioning and alignment. */
1507 s_bss (int ignore ATTRIBUTE_UNUSED
)
1509 /* We don't support putting frags in the BSS segment, we fake it by
1510 marking in_bss, then looking at s_skip for clues. */
1511 subseg_set (bss_section
, 0);
1512 demand_empty_rest_of_line ();
1513 mapping_state (MAP_DATA
);
1517 s_even (int ignore ATTRIBUTE_UNUSED
)
1519 /* Never make frag if expect extra pass. */
1521 frag_align (1, 0, 0);
1523 record_alignment (now_seg
, 1);
1525 demand_empty_rest_of_line ();
1528 /* Directives: Literal pools. */
1530 static literal_pool
*
1531 find_literal_pool (int size
)
1535 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1537 if (pool
->section
== now_seg
1538 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1545 static literal_pool
*
1546 find_or_make_literal_pool (int size
)
1548 /* Next literal pool ID number. */
1549 static unsigned int latest_pool_num
= 1;
1552 pool
= find_literal_pool (size
);
1556 /* Create a new pool. */
1557 pool
= XNEW (literal_pool
);
1561 /* Currently we always put the literal pool in the current text
1562 section. If we were generating "small" model code where we
1563 knew that all code and initialised data was within 1MB then
1564 we could output literals to mergeable, read-only data
1567 pool
->next_free_entry
= 0;
1568 pool
->section
= now_seg
;
1569 pool
->sub_section
= now_subseg
;
1571 pool
->next
= list_of_pools
;
1572 pool
->symbol
= NULL
;
1574 /* Add it to the list. */
1575 list_of_pools
= pool
;
1578 /* New pools, and emptied pools, will have a NULL symbol. */
1579 if (pool
->symbol
== NULL
)
1581 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1582 (valueT
) 0, &zero_address_frag
);
1583 pool
->id
= latest_pool_num
++;
1590 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1591 Return TRUE on success, otherwise return FALSE. */
1593 add_to_lit_pool (expressionS
*exp
, int size
)
1598 pool
= find_or_make_literal_pool (size
);
1600 /* Check if this literal value is already in the pool. */
1601 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1603 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1605 if ((litexp
->X_op
== exp
->X_op
)
1606 && (exp
->X_op
== O_constant
)
1607 && (litexp
->X_add_number
== exp
->X_add_number
)
1608 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1611 if ((litexp
->X_op
== exp
->X_op
)
1612 && (exp
->X_op
== O_symbol
)
1613 && (litexp
->X_add_number
== exp
->X_add_number
)
1614 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1615 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1619 /* Do we need to create a new entry? */
1620 if (entry
== pool
->next_free_entry
)
1622 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1624 set_syntax_error (_("literal pool overflow"));
1628 pool
->literals
[entry
].exp
= *exp
;
1629 pool
->next_free_entry
+= 1;
1630 if (exp
->X_op
== O_big
)
1632 /* PR 16688: Bignums are held in a single global array. We must
1633 copy and preserve that value now, before it is overwritten. */
1634 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1636 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1637 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1640 pool
->literals
[entry
].bignum
= NULL
;
1643 exp
->X_op
= O_symbol
;
1644 exp
->X_add_number
= ((int) entry
) * size
;
1645 exp
->X_add_symbol
= pool
->symbol
;
1650 /* Can't use symbol_new here, so have to create a symbol and then at
1651 a later date assign it a value. Thats what these functions do. */
1654 symbol_locate (symbolS
* symbolP
,
1655 const char *name
,/* It is copied, the caller can modify. */
1656 segT segment
, /* Segment identifier (SEG_<something>). */
1657 valueT valu
, /* Symbol value. */
1658 fragS
* frag
) /* Associated fragment. */
1661 char *preserved_copy_of_name
;
1663 name_length
= strlen (name
) + 1; /* +1 for \0. */
1664 obstack_grow (¬es
, name
, name_length
);
1665 preserved_copy_of_name
= obstack_finish (¬es
);
1667 #ifdef tc_canonicalize_symbol_name
1668 preserved_copy_of_name
=
1669 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1672 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1674 S_SET_SEGMENT (symbolP
, segment
);
1675 S_SET_VALUE (symbolP
, valu
);
1676 symbol_clear_list_pointers (symbolP
);
1678 symbol_set_frag (symbolP
, frag
);
1680 /* Link to end of symbol chain. */
1682 extern int symbol_table_frozen
;
1684 if (symbol_table_frozen
)
1688 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1690 obj_symbol_new_hook (symbolP
);
1692 #ifdef tc_symbol_new_hook
1693 tc_symbol_new_hook (symbolP
);
1697 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1698 #endif /* DEBUG_SYMS */
1703 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1710 for (align
= 2; align
<= 4; align
++)
1712 int size
= 1 << align
;
1714 pool
= find_literal_pool (size
);
1715 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1718 /* Align pool as you have word accesses.
1719 Only make a frag if we have to. */
1721 frag_align (align
, 0, 0);
1723 mapping_state (MAP_DATA
);
1725 record_alignment (now_seg
, align
);
1727 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1729 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1730 (valueT
) frag_now_fix (), frag_now
);
1731 symbol_table_insert (pool
->symbol
);
1733 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1735 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1737 if (exp
->X_op
== O_big
)
1739 /* PR 16688: Restore the global bignum value. */
1740 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1741 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1742 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1745 /* First output the expression in the instruction to the pool. */
1746 emit_expr (exp
, size
); /* .word|.xword */
1748 if (exp
->X_op
== O_big
)
1750 free (pool
->literals
[entry
].bignum
);
1751 pool
->literals
[entry
].bignum
= NULL
;
1755 /* Mark the pool as empty. */
1756 pool
->next_free_entry
= 0;
1757 pool
->symbol
= NULL
;
1762 /* Forward declarations for functions below, in the MD interface
1764 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1765 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1767 /* Directives: Data. */
1768 /* N.B. the support for relocation suffix in this directive needs to be
1769 implemented properly. */
1772 s_aarch64_elf_cons (int nbytes
)
1776 #ifdef md_flush_pending_output
1777 md_flush_pending_output ();
1780 if (is_it_end_of_statement ())
1782 demand_empty_rest_of_line ();
1786 #ifdef md_cons_align
1787 md_cons_align (nbytes
);
1790 mapping_state (MAP_DATA
);
1793 struct reloc_table_entry
*reloc
;
1797 if (exp
.X_op
!= O_symbol
)
1798 emit_expr (&exp
, (unsigned int) nbytes
);
1801 skip_past_char (&input_line_pointer
, '#');
1802 if (skip_past_char (&input_line_pointer
, ':'))
1804 reloc
= find_reloc_table_entry (&input_line_pointer
);
1806 as_bad (_("unrecognized relocation suffix"));
1808 as_bad (_("unimplemented relocation suffix"));
1809 ignore_rest_of_line ();
1813 emit_expr (&exp
, (unsigned int) nbytes
);
1816 while (*input_line_pointer
++ == ',');
1818 /* Put terminator back into stream. */
1819 input_line_pointer
--;
1820 demand_empty_rest_of_line ();
1823 #endif /* OBJ_ELF */
1825 /* Output a 32-bit word, but mark as an instruction. */
1828 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1832 #ifdef md_flush_pending_output
1833 md_flush_pending_output ();
1836 if (is_it_end_of_statement ())
1838 demand_empty_rest_of_line ();
1842 /* Sections are assumed to start aligned. In executable section, there is no
1843 MAP_DATA symbol pending. So we only align the address during
1844 MAP_DATA --> MAP_INSN transition.
1845 For other sections, this is not guaranteed. */
1846 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1847 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1848 frag_align_code (2, 0);
1851 mapping_state (MAP_INSN
);
1857 if (exp
.X_op
!= O_constant
)
1859 as_bad (_("constant expression required"));
1860 ignore_rest_of_line ();
1864 if (target_big_endian
)
1866 unsigned int val
= exp
.X_add_number
;
1867 exp
.X_add_number
= SWAP_32 (val
);
1869 emit_expr (&exp
, 4);
1871 while (*input_line_pointer
++ == ',');
1873 /* Put terminator back into stream. */
1874 input_line_pointer
--;
1875 demand_empty_rest_of_line ();
1879 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1882 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1888 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1889 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1891 demand_empty_rest_of_line ();
1894 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1897 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1901 /* Since we're just labelling the code, there's no need to define a
1904 /* Make sure there is enough room in this frag for the following
1905 blr. This trick only works if the blr follows immediately after
1906 the .tlsdesc directive. */
1908 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1909 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1911 demand_empty_rest_of_line ();
1914 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
1917 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
1923 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1924 BFD_RELOC_AARCH64_TLSDESC_LDR
);
1926 demand_empty_rest_of_line ();
1928 #endif /* OBJ_ELF */
1930 static void s_aarch64_arch (int);
1931 static void s_aarch64_cpu (int);
1932 static void s_aarch64_arch_extension (int);
1934 /* This table describes all the machine specific pseudo-ops the assembler
1935 has to support. The fields are:
1936 pseudo-op name without dot
1937 function to call to execute this pseudo-op
1938 Integer arg to pass to the function. */
1940 const pseudo_typeS md_pseudo_table
[] = {
1941 /* Never called because '.req' does not start a line. */
1943 {"unreq", s_unreq
, 0},
1945 {"even", s_even
, 0},
1946 {"ltorg", s_ltorg
, 0},
1947 {"pool", s_ltorg
, 0},
1948 {"cpu", s_aarch64_cpu
, 0},
1949 {"arch", s_aarch64_arch
, 0},
1950 {"arch_extension", s_aarch64_arch_extension
, 0},
1951 {"inst", s_aarch64_inst
, 0},
1953 {"tlsdescadd", s_tlsdescadd
, 0},
1954 {"tlsdesccall", s_tlsdesccall
, 0},
1955 {"tlsdescldr", s_tlsdescldr
, 0},
1956 {"word", s_aarch64_elf_cons
, 4},
1957 {"long", s_aarch64_elf_cons
, 4},
1958 {"xword", s_aarch64_elf_cons
, 8},
1959 {"dword", s_aarch64_elf_cons
, 8},
1965 /* Check whether STR points to a register name followed by a comma or the
1966 end of line; REG_TYPE indicates which register types are checked
1967 against. Return TRUE if STR is such a register name; otherwise return
1968 FALSE. The function does not intend to produce any diagnostics, but since
1969 the register parser aarch64_reg_parse, which is called by this function,
1970 does produce diagnostics, we call clear_error to clear any diagnostics
1971 that may be generated by aarch64_reg_parse.
1972 Also, the function returns FALSE directly if there is any user error
1973 present at the function entry. This prevents the existing diagnostics
1974 state from being spoiled.
1975 The function currently serves parse_constant_immediate and
1976 parse_big_immediate only. */
1978 reg_name_p (char *str
, aarch64_reg_type reg_type
)
1982 /* Prevent the diagnostics state from being spoiled. */
1986 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
1988 /* Clear the parsing error that may be set by the reg parser. */
1991 if (reg
== PARSE_FAIL
)
1994 skip_whitespace (str
);
1995 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2001 /* Parser functions used exclusively in instruction operands. */
2003 /* Parse an immediate expression which may not be constant.
2005 To prevent the expression parser from pushing a register name
2006 into the symbol table as an undefined symbol, firstly a check is
2007 done to find out whether STR is a valid register name followed
2008 by a comma or the end of line. Return FALSE if STR is such a
2012 parse_immediate_expression (char **str
, expressionS
*exp
)
2014 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
2016 set_recoverable_error (_("immediate operand required"));
2020 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2022 if (exp
->X_op
== O_absent
)
2024 set_fatal_syntax_error (_("missing immediate expression"));
2031 /* Constant immediate-value read function for use in insn parsing.
2032 STR points to the beginning of the immediate (with the optional
2033 leading #); *VAL receives the value.
2035 Return TRUE on success; otherwise return FALSE. */
2038 parse_constant_immediate (char **str
, int64_t * val
)
2042 if (! parse_immediate_expression (str
, &exp
))
2045 if (exp
.X_op
!= O_constant
)
2047 set_syntax_error (_("constant expression required"));
2051 *val
= exp
.X_add_number
;
2056 encode_imm_float_bits (uint32_t imm
)
2058 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2059 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2062 /* Return TRUE if the single-precision floating-point value encoded in IMM
2063 can be expressed in the AArch64 8-bit signed floating-point format with
2064 3-bit exponent and normalized 4 bits of precision; in other words, the
2065 floating-point value must be expressable as
2066 (+/-) n / 16 * power (2, r)
2067 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2070 aarch64_imm_float_p (uint32_t imm
)
2072 /* If a single-precision floating-point value has the following bit
2073 pattern, it can be expressed in the AArch64 8-bit floating-point
2076 3 32222222 2221111111111
2077 1 09876543 21098765432109876543210
2078 n Eeeeeexx xxxx0000000000000000000
2080 where n, e and each x are either 0 or 1 independently, with
2085 /* Prepare the pattern for 'Eeeeee'. */
2086 if (((imm
>> 30) & 0x1) == 0)
2087 pattern
= 0x3e000000;
2089 pattern
= 0x40000000;
2091 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2092 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2095 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2097 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2098 8-bit signed floating-point format with 3-bit exponent and normalized 4
2099 bits of precision (i.e. can be used in an FMOV instruction); return the
2100 equivalent single-precision encoding in *FPWORD.
2102 Otherwise return FALSE. */
2105 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2107 /* If a double-precision floating-point value has the following bit
2108 pattern, it can be expressed in the AArch64 8-bit floating-point
2111 6 66655555555 554444444...21111111111
2112 3 21098765432 109876543...098765432109876543210
2113 n Eeeeeeeeexx xxxx00000...000000000000000000000
2115 where n, e and each x are either 0 or 1 independently, with
2119 uint32_t high32
= imm
>> 32;
2121 /* Lower 32 bits need to be 0s. */
2122 if ((imm
& 0xffffffff) != 0)
2125 /* Prepare the pattern for 'Eeeeeeeee'. */
2126 if (((high32
>> 30) & 0x1) == 0)
2127 pattern
= 0x3fc00000;
2129 pattern
= 0x40000000;
2131 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2132 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2134 /* Convert to the single-precision encoding.
2136 n Eeeeeeeeexx xxxx00000...000000000000000000000
2138 n Eeeeeexx xxxx0000000000000000000. */
2139 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2140 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2147 /* Parse a floating-point immediate. Return TRUE on success and return the
2148 value in *IMMED in the format of IEEE754 single-precision encoding.
2149 *CCP points to the start of the string; DP_P is TRUE when the immediate
2150 is expected to be in double-precision (N.B. this only matters when
2151 hexadecimal representation is involved).
2153 N.B. 0.0 is accepted by this function. */
2156 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2160 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2161 int found_fpchar
= 0;
2163 unsigned fpword
= 0;
2164 bfd_boolean hex_p
= FALSE
;
2166 skip_past_char (&str
, '#');
2169 skip_whitespace (fpnum
);
2171 if (strncmp (fpnum
, "0x", 2) == 0)
2173 /* Support the hexadecimal representation of the IEEE754 encoding.
2174 Double-precision is expected when DP_P is TRUE, otherwise the
2175 representation should be in single-precision. */
2176 if (! parse_constant_immediate (&str
, &val
))
2181 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2184 else if ((uint64_t) val
> 0xffffffff)
2193 /* We must not accidentally parse an integer as a floating-point number.
2194 Make sure that the value we parse is not an integer by checking for
2195 special characters '.' or 'e'. */
2196 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2197 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2211 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2214 /* Our FP word must be 32 bits (single-precision FP). */
2215 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2217 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2222 if (aarch64_imm_float_p (fpword
) || fpword
== 0)
2230 set_fatal_syntax_error (_("invalid floating-point constant"));
2234 /* Less-generic immediate-value read function with the possibility of loading
2235 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2238 To prevent the expression parser from pushing a register name into the
2239 symbol table as an undefined symbol, a check is firstly done to find
2240 out whether STR is a valid register name followed by a comma or the end
2241 of line. Return FALSE if STR is such a register. */
2244 parse_big_immediate (char **str
, int64_t *imm
)
2248 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2250 set_syntax_error (_("immediate operand required"));
2254 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2256 if (inst
.reloc
.exp
.X_op
== O_constant
)
2257 *imm
= inst
.reloc
.exp
.X_add_number
;
2264 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2265 if NEED_LIBOPCODES is non-zero, the fixup will need
2266 assistance from the libopcodes. */
2269 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2270 const aarch64_opnd_info
*operand
,
2271 int need_libopcodes_p
)
2273 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2274 reloc
->opnd
= operand
->type
;
2275 if (need_libopcodes_p
)
2276 reloc
->need_libopcodes_p
= 1;
2279 /* Return TRUE if the instruction needs to be fixed up later internally by
2280 the GAS; otherwise return FALSE. */
2282 static inline bfd_boolean
2283 aarch64_gas_internal_fixup_p (void)
2285 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2288 /* Assign the immediate value to the relavant field in *OPERAND if
2289 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2290 needs an internal fixup in a later stage.
2291 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2292 IMM.VALUE that may get assigned with the constant. */
2294 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2295 aarch64_opnd_info
*operand
,
2297 int need_libopcodes_p
,
2300 if (reloc
->exp
.X_op
== O_constant
)
2303 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2305 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2306 reloc
->type
= BFD_RELOC_UNUSED
;
2310 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2311 /* Tell libopcodes to ignore this operand or not. This is helpful
2312 when one of the operands needs to be fixed up later but we need
2313 libopcodes to check the other operands. */
2314 operand
->skip
= skip_p
;
2318 /* Relocation modifiers. Each entry in the table contains the textual
2319 name for the relocation which may be placed before a symbol used as
2320 a load/store offset, or add immediate. It must be surrounded by a
2321 leading and trailing colon, for example:
2323 ldr x0, [x1, #:rello:varsym]
2324 add x0, x1, #:rello:varsym */
2326 struct reloc_table_entry
2330 bfd_reloc_code_real_type adr_type
;
2331 bfd_reloc_code_real_type adrp_type
;
2332 bfd_reloc_code_real_type movw_type
;
2333 bfd_reloc_code_real_type add_type
;
2334 bfd_reloc_code_real_type ldst_type
;
2335 bfd_reloc_code_real_type ld_literal_type
;
2338 static struct reloc_table_entry reloc_table
[] = {
2339 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2344 BFD_RELOC_AARCH64_ADD_LO12
,
2345 BFD_RELOC_AARCH64_LDST_LO12
,
2348 /* Higher 21 bits of pc-relative page offset: ADRP */
2351 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2357 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2360 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2366 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2370 BFD_RELOC_AARCH64_MOVW_G0
,
2375 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2379 BFD_RELOC_AARCH64_MOVW_G0_S
,
2384 /* Less significant bits 0-15 of address/value: MOVK, no check */
2388 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2393 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2397 BFD_RELOC_AARCH64_MOVW_G1
,
2402 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2406 BFD_RELOC_AARCH64_MOVW_G1_S
,
2411 /* Less significant bits 16-31 of address/value: MOVK, no check */
2415 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2420 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2424 BFD_RELOC_AARCH64_MOVW_G2
,
2429 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2433 BFD_RELOC_AARCH64_MOVW_G2_S
,
2438 /* Less significant bits 32-47 of address/value: MOVK, no check */
2442 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2447 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2451 BFD_RELOC_AARCH64_MOVW_G3
,
2456 /* Get to the page containing GOT entry for a symbol. */
2459 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2463 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2465 /* 12 bit offset into the page containing GOT entry for that symbol. */
2471 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2474 /* 0-15 bits of address/value: MOVk, no check. */
2478 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2483 /* Most significant bits 16-31 of address/value: MOVZ. */
2487 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2492 /* 15 bit offset into the page containing GOT entry for that symbol. */
2498 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2501 /* Get to the page containing GOT TLS entry for a symbol */
2502 {"gottprel_g0_nc", 0,
2505 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2510 /* Get to the page containing GOT TLS entry for a symbol */
2514 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2519 /* Get to the page containing GOT TLS entry for a symbol */
2521 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2522 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2528 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2533 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2537 /* Lower 16 bits address/value: MOVk. */
2541 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2546 /* Most significant bits 16-31 of address/value: MOVZ. */
2550 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2555 /* Get to the page containing GOT TLS entry for a symbol */
2557 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2558 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2562 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2564 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2569 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2570 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2573 /* Get to the page containing GOT TLS entry for a symbol.
2574 The same as GD, we allocate two consecutive GOT slots
2575 for module index and module offset, the only difference
2576 with GD is the module offset should be intialized to
2577 zero without any outstanding runtime relocation. */
2579 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2580 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2586 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2587 {"tlsldm_lo12_nc", 0,
2591 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2595 /* 12 bit offset into the module TLS base address. */
2600 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2601 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2604 /* Same as dtprel_lo12, no overflow check. */
2605 {"dtprel_lo12_nc", 0,
2609 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2610 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2613 /* bits[23:12] of offset to the module TLS base address. */
2618 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2622 /* bits[15:0] of offset to the module TLS base address. */
2626 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2631 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2635 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2640 /* bits[31:16] of offset to the module TLS base address. */
2644 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2649 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2653 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2658 /* bits[47:32] of offset to the module TLS base address. */
2662 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2667 /* Lower 16 bit offset into GOT entry for a symbol */
2668 {"tlsdesc_off_g0_nc", 0,
2671 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2676 /* Higher 16 bit offset into GOT entry for a symbol */
2677 {"tlsdesc_off_g1", 0,
2680 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2685 /* Get to the page containing GOT TLS entry for a symbol */
2688 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2692 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2694 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2695 {"gottprel_lo12", 0,
2700 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2703 /* Get tp offset for a symbol. */
2708 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2712 /* Get tp offset for a symbol. */
2717 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2721 /* Get tp offset for a symbol. */
2726 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2730 /* Get tp offset for a symbol. */
2731 {"tprel_lo12_nc", 0,
2735 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2739 /* Most significant bits 32-47 of address/value: MOVZ. */
2743 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2748 /* Most significant bits 16-31 of address/value: MOVZ. */
2752 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2757 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2761 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2766 /* Most significant bits 0-15 of address/value: MOVZ. */
2770 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2775 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2779 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2784 /* 15bit offset from got entry to base address of GOT table. */
2790 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2793 /* 14bit offset from got entry to base address of GOT table. */
2799 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2803 /* Given the address of a pointer pointing to the textual name of a
2804 relocation as may appear in assembler source, attempt to find its
2805 details in reloc_table. The pointer will be updated to the character
2806 after the trailing colon. On failure, NULL will be returned;
2807 otherwise return the reloc_table_entry. */
2809 static struct reloc_table_entry
*
2810 find_reloc_table_entry (char **str
)
2813 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2815 int length
= strlen (reloc_table
[i
].name
);
2817 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2818 && (*str
)[length
] == ':')
2820 *str
+= (length
+ 1);
2821 return &reloc_table
[i
];
2828 /* Mode argument to parse_shift and parser_shifter_operand. */
2829 enum parse_shift_mode
2831 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2833 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2835 SHIFTED_LSL
, /* bare "lsl #n" */
2836 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2837 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2840 /* Parse a <shift> operator on an AArch64 data processing instruction.
2841 Return TRUE on success; otherwise return FALSE. */
2843 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2845 const struct aarch64_name_value_pair
*shift_op
;
2846 enum aarch64_modifier_kind kind
;
2852 for (p
= *str
; ISALPHA (*p
); p
++)
2857 set_syntax_error (_("shift expression expected"));
2861 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2863 if (shift_op
== NULL
)
2865 set_syntax_error (_("shift operator expected"));
2869 kind
= aarch64_get_operand_modifier (shift_op
);
2871 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2873 set_syntax_error (_("invalid use of 'MSL'"));
2879 case SHIFTED_LOGIC_IMM
:
2880 if (aarch64_extend_operator_p (kind
) == TRUE
)
2882 set_syntax_error (_("extending shift is not permitted"));
2887 case SHIFTED_ARITH_IMM
:
2888 if (kind
== AARCH64_MOD_ROR
)
2890 set_syntax_error (_("'ROR' shift is not permitted"));
2896 if (kind
!= AARCH64_MOD_LSL
)
2898 set_syntax_error (_("only 'LSL' shift is permitted"));
2903 case SHIFTED_REG_OFFSET
:
2904 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2905 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2907 set_fatal_syntax_error
2908 (_("invalid shift for the register offset addressing mode"));
2913 case SHIFTED_LSL_MSL
:
2914 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2916 set_syntax_error (_("invalid shift operator"));
2925 /* Whitespace can appear here if the next thing is a bare digit. */
2926 skip_whitespace (p
);
2928 /* Parse shift amount. */
2930 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2931 exp
.X_op
= O_absent
;
2934 if (is_immediate_prefix (*p
))
2939 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2941 if (exp
.X_op
== O_absent
)
2943 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2945 set_syntax_error (_("missing shift amount"));
2948 operand
->shifter
.amount
= 0;
2950 else if (exp
.X_op
!= O_constant
)
2952 set_syntax_error (_("constant shift amount required"));
2955 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2957 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2962 operand
->shifter
.amount
= exp
.X_add_number
;
2963 operand
->shifter
.amount_present
= 1;
2966 operand
->shifter
.operator_present
= 1;
2967 operand
->shifter
.kind
= kind
;
2973 /* Parse a <shifter_operand> for a data processing instruction:
2976 #<immediate>, LSL #imm
2978 Validation of immediate operands is deferred to md_apply_fix.
2980 Return TRUE on success; otherwise return FALSE. */
2983 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
2984 enum parse_shift_mode mode
)
2988 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
2993 /* Accept an immediate expression. */
2994 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
2997 /* Accept optional LSL for arithmetic immediate values. */
2998 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
2999 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3002 /* Not accept any shifter for logical immediate values. */
3003 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3004 && parse_shift (&p
, operand
, mode
))
3006 set_syntax_error (_("unexpected shift operator"));
3014 /* Parse a <shifter_operand> for a data processing instruction:
3019 #<immediate>, LSL #imm
3021 where <shift> is handled by parse_shift above, and the last two
3022 cases are handled by the function above.
3024 Validation of immediate operands is deferred to md_apply_fix.
3026 Return TRUE on success; otherwise return FALSE. */
3029 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3030 enum parse_shift_mode mode
)
3033 int isreg32
, isregzero
;
3034 enum aarch64_operand_class opd_class
3035 = aarch64_get_operand_class (operand
->type
);
3038 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
3040 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3042 set_syntax_error (_("unexpected register in the immediate operand"));
3046 if (!isregzero
&& reg
== REG_SP
)
3048 set_syntax_error (BAD_SP
);
3052 operand
->reg
.regno
= reg
;
3053 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
3055 /* Accept optional shift operation on register. */
3056 if (! skip_past_comma (str
))
3059 if (! parse_shift (str
, operand
, mode
))
3064 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3067 (_("integer register expected in the extended/shifted operand "
3072 /* We have a shifted immediate variable. */
3073 return parse_shifter_operand_imm (str
, operand
, mode
);
3076 /* Return TRUE on success; return FALSE otherwise. */
3079 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3080 enum parse_shift_mode mode
)
3084 /* Determine if we have the sequence of characters #: or just :
3085 coming next. If we do, then we check for a :rello: relocation
3086 modifier. If we don't, punt the whole lot to
3087 parse_shifter_operand. */
3089 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3091 struct reloc_table_entry
*entry
;
3099 /* Try to parse a relocation. Anything else is an error. */
3100 if (!(entry
= find_reloc_table_entry (str
)))
3102 set_syntax_error (_("unknown relocation modifier"));
3106 if (entry
->add_type
== 0)
3109 (_("this relocation modifier is not allowed on this instruction"));
3113 /* Save str before we decompose it. */
3116 /* Next, we parse the expression. */
3117 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3120 /* Record the relocation type (use the ADD variant here). */
3121 inst
.reloc
.type
= entry
->add_type
;
3122 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3124 /* If str is empty, we've reached the end, stop here. */
3128 /* Otherwise, we have a shifted reloc modifier, so rewind to
3129 recover the variable name and continue parsing for the shifter. */
3131 return parse_shifter_operand_imm (str
, operand
, mode
);
3134 return parse_shifter_operand (str
, operand
, mode
);
3137 /* Parse all forms of an address expression. Information is written
3138 to *OPERAND and/or inst.reloc.
3140 The A64 instruction set has the following addressing modes:
3143 [base] // in SIMD ld/st structure
3144 [base{,#0}] // in ld/st exclusive
3146 [base,Xm{,LSL #imm}]
3147 [base,Xm,SXTX {#imm}]
3148 [base,Wm,(S|U)XTW {#imm}]
3153 [base],Xm // in SIMD ld/st structure
3154 PC-relative (literal)
3158 (As a convenience, the notation "=immediate" is permitted in conjunction
3159 with the pc-relative literal load instructions to automatically place an
3160 immediate value or symbolic address in a nearby literal pool and generate
3161 a hidden label which references it.)
3163 Upon a successful parsing, the address structure in *OPERAND will be
3164 filled in the following way:
3166 .base_regno = <base>
3167 .offset.is_reg // 1 if the offset is a register
3169 .offset.regno = <Rm>
3171 For different addressing modes defined in the A64 ISA:
3174 .pcrel=0; .preind=1; .postind=0; .writeback=0
3176 .pcrel=0; .preind=1; .postind=0; .writeback=1
3178 .pcrel=0; .preind=0; .postind=1; .writeback=1
3179 PC-relative (literal)
3180 .pcrel=1; .preind=1; .postind=0; .writeback=0
3182 The shift/extension information, if any, will be stored in .shifter.
3184 It is the caller's responsibility to check for addressing modes not
3185 supported by the instruction, and to set inst.reloc.type. */
3188 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
3189 int accept_reg_post_index
)
3193 int isreg32
, isregzero
;
3194 expressionS
*exp
= &inst
.reloc
.exp
;
3196 if (! skip_past_char (&p
, '['))
3198 /* =immediate or label. */
3199 operand
->addr
.pcrel
= 1;
3200 operand
->addr
.preind
= 1;
3202 /* #:<reloc_op>:<symbol> */
3203 skip_past_char (&p
, '#');
3204 if (reloc
&& skip_past_char (&p
, ':'))
3206 bfd_reloc_code_real_type ty
;
3207 struct reloc_table_entry
*entry
;
3209 /* Try to parse a relocation modifier. Anything else is
3211 entry
= find_reloc_table_entry (&p
);
3214 set_syntax_error (_("unknown relocation modifier"));
3218 switch (operand
->type
)
3220 case AARCH64_OPND_ADDR_PCREL21
:
3222 ty
= entry
->adr_type
;
3226 ty
= entry
->ld_literal_type
;
3233 (_("this relocation modifier is not allowed on this "
3239 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3241 set_syntax_error (_("invalid relocation expression"));
3245 /* #:<reloc_op>:<expr> */
3246 /* Record the relocation type. */
3247 inst
.reloc
.type
= ty
;
3248 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3253 if (skip_past_char (&p
, '='))
3254 /* =immediate; need to generate the literal in the literal pool. */
3255 inst
.gen_lit_pool
= 1;
3257 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3259 set_syntax_error (_("invalid address"));
3270 /* Accept SP and reject ZR */
3271 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
3272 if (reg
== PARSE_FAIL
|| isreg32
)
3274 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3277 operand
->addr
.base_regno
= reg
;
3280 if (skip_past_comma (&p
))
3283 operand
->addr
.preind
= 1;
3285 /* Reject SP and accept ZR */
3286 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3287 if (reg
!= PARSE_FAIL
)
3290 operand
->addr
.offset
.regno
= reg
;
3291 operand
->addr
.offset
.is_reg
= 1;
3292 /* Shifted index. */
3293 if (skip_past_comma (&p
))
3296 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3297 /* Use the diagnostics set in parse_shift, so not set new
3298 error message here. */
3302 [base,Xm{,LSL #imm}]
3303 [base,Xm,SXTX {#imm}]
3304 [base,Wm,(S|U)XTW {#imm}] */
3305 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3306 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3307 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3311 set_syntax_error (_("invalid use of 32-bit register offset"));
3317 set_syntax_error (_("invalid use of 64-bit register offset"));
3323 /* [Xn,#:<reloc_op>:<symbol> */
3324 skip_past_char (&p
, '#');
3325 if (reloc
&& skip_past_char (&p
, ':'))
3327 struct reloc_table_entry
*entry
;
3329 /* Try to parse a relocation modifier. Anything else is
3331 if (!(entry
= find_reloc_table_entry (&p
)))
3333 set_syntax_error (_("unknown relocation modifier"));
3337 if (entry
->ldst_type
== 0)
3340 (_("this relocation modifier is not allowed on this "
3345 /* [Xn,#:<reloc_op>: */
3346 /* We now have the group relocation table entry corresponding to
3347 the name in the assembler source. Next, we parse the
3349 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3351 set_syntax_error (_("invalid relocation expression"));
3355 /* [Xn,#:<reloc_op>:<expr> */
3356 /* Record the load/store relocation type. */
3357 inst
.reloc
.type
= entry
->ldst_type
;
3358 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3360 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3362 set_syntax_error (_("invalid expression in the address"));
3369 if (! skip_past_char (&p
, ']'))
3371 set_syntax_error (_("']' expected"));
3375 if (skip_past_char (&p
, '!'))
3377 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3379 set_syntax_error (_("register offset not allowed in pre-indexed "
3380 "addressing mode"));
3384 operand
->addr
.writeback
= 1;
3386 else if (skip_past_comma (&p
))
3389 operand
->addr
.postind
= 1;
3390 operand
->addr
.writeback
= 1;
3392 if (operand
->addr
.preind
)
3394 set_syntax_error (_("cannot combine pre- and post-indexing"));
3398 if (accept_reg_post_index
3399 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3400 &isregzero
)) != PARSE_FAIL
)
3405 set_syntax_error (_("invalid 32-bit register offset"));
3408 operand
->addr
.offset
.regno
= reg
;
3409 operand
->addr
.offset
.is_reg
= 1;
3411 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3414 set_syntax_error (_("invalid expression in the address"));
3419 /* If at this point neither .preind nor .postind is set, we have a
3420 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3421 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3423 if (operand
->addr
.writeback
)
3426 set_syntax_error (_("missing offset in the pre-indexed address"));
3429 operand
->addr
.preind
= 1;
3430 inst
.reloc
.exp
.X_op
= O_constant
;
3431 inst
.reloc
.exp
.X_add_number
= 0;
3438 /* Return TRUE on success; otherwise return FALSE. */
3440 parse_address (char **str
, aarch64_opnd_info
*operand
,
3441 int accept_reg_post_index
)
3443 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3446 /* Return TRUE on success; otherwise return FALSE. */
3448 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3450 return parse_address_main (str
, operand
, 1, 0);
3453 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3454 Return TRUE on success; otherwise return FALSE. */
3456 parse_half (char **str
, int *internal_fixup_p
)
3460 skip_past_char (&p
, '#');
3462 gas_assert (internal_fixup_p
);
3463 *internal_fixup_p
= 0;
3467 struct reloc_table_entry
*entry
;
3469 /* Try to parse a relocation. Anything else is an error. */
3471 if (!(entry
= find_reloc_table_entry (&p
)))
3473 set_syntax_error (_("unknown relocation modifier"));
3477 if (entry
->movw_type
== 0)
3480 (_("this relocation modifier is not allowed on this instruction"));
3484 inst
.reloc
.type
= entry
->movw_type
;
3487 *internal_fixup_p
= 1;
3489 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3496 /* Parse an operand for an ADRP instruction:
3498 Return TRUE on success; otherwise return FALSE. */
3501 parse_adrp (char **str
)
3508 struct reloc_table_entry
*entry
;
3510 /* Try to parse a relocation. Anything else is an error. */
3512 if (!(entry
= find_reloc_table_entry (&p
)))
3514 set_syntax_error (_("unknown relocation modifier"));
3518 if (entry
->adrp_type
== 0)
3521 (_("this relocation modifier is not allowed on this instruction"));
3525 inst
.reloc
.type
= entry
->adrp_type
;
3528 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3530 inst
.reloc
.pc_rel
= 1;
3532 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3539 /* Miscellaneous. */
3541 /* Parse an option for a preload instruction. Returns the encoding for the
3542 option, or PARSE_FAIL. */
3545 parse_pldop (char **str
)
3548 const struct aarch64_name_value_pair
*o
;
3551 while (ISALNUM (*q
))
3554 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3562 /* Parse an option for a barrier instruction. Returns the encoding for the
3563 option, or PARSE_FAIL. */
3566 parse_barrier (char **str
)
3569 const asm_barrier_opt
*o
;
3572 while (ISALPHA (*q
))
3575 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3583 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3584 return 0 if successful. Otherwise return PARSE_FAIL. */
3587 parse_barrier_psb (char **str
,
3588 const struct aarch64_name_value_pair
** hint_opt
)
3591 const struct aarch64_name_value_pair
*o
;
3594 while (ISALPHA (*q
))
3597 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3600 set_fatal_syntax_error
3601 ( _("unknown or missing option to PSB"));
3605 if (o
->value
!= 0x11)
3607 /* PSB only accepts option name 'CSYNC'. */
3609 (_("the specified option is not accepted for PSB"));
3618 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3619 Returns the encoding for the option, or PARSE_FAIL.
3621 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3622 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3624 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3625 field, otherwise as a system register.
3629 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3630 int imple_defined_p
, int pstatefield_p
)
3634 const aarch64_sys_reg
*o
;
3638 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3640 *p
++ = TOLOWER (*q
);
3642 /* Assert that BUF be large enough. */
3643 gas_assert (p
- buf
== q
- *str
);
3645 o
= hash_find (sys_regs
, buf
);
3648 if (!imple_defined_p
)
3652 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3653 unsigned int op0
, op1
, cn
, cm
, op2
;
3655 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3658 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3660 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3665 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3666 as_bad (_("selected processor does not support PSTATE field "
3668 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3669 as_bad (_("selected processor does not support system register "
3671 if (aarch64_sys_reg_deprecated_p (o
))
3672 as_warn (_("system register name '%s' is deprecated and may be "
3673 "removed in a future release"), buf
);
3681 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3682 for the option, or NULL. */
3684 static const aarch64_sys_ins_reg
*
3685 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3689 const aarch64_sys_ins_reg
*o
;
3692 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3694 *p
++ = TOLOWER (*q
);
3697 o
= hash_find (sys_ins_regs
, buf
);
3701 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
3702 as_bad (_("selected processor does not support system register "
3709 #define po_char_or_fail(chr) do { \
3710 if (! skip_past_char (&str, chr)) \
3714 #define po_reg_or_fail(regtype) do { \
3715 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3716 if (val == PARSE_FAIL) \
3718 set_default_error (); \
3723 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3724 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3725 &isreg32, &isregzero); \
3726 if (val == PARSE_FAIL) \
3728 set_default_error (); \
3731 info->reg.regno = val; \
3733 info->qualifier = AARCH64_OPND_QLF_W; \
3735 info->qualifier = AARCH64_OPND_QLF_X; \
3738 #define po_imm_nc_or_fail() do { \
3739 if (! parse_constant_immediate (&str, &val)) \
3743 #define po_imm_or_fail(min, max) do { \
3744 if (! parse_constant_immediate (&str, &val)) \
3746 if (val < min || val > max) \
3748 set_fatal_syntax_error (_("immediate value out of range "\
3749 #min " to "#max)); \
3754 #define po_misc_or_fail(expr) do { \
3759 /* encode the 12-bit imm field of Add/sub immediate */
3760 static inline uint32_t
3761 encode_addsub_imm (uint32_t imm
)
3766 /* encode the shift amount field of Add/sub immediate */
3767 static inline uint32_t
3768 encode_addsub_imm_shift_amount (uint32_t cnt
)
3774 /* encode the imm field of Adr instruction */
3775 static inline uint32_t
3776 encode_adr_imm (uint32_t imm
)
3778 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3779 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3782 /* encode the immediate field of Move wide immediate */
3783 static inline uint32_t
3784 encode_movw_imm (uint32_t imm
)
3789 /* encode the 26-bit offset of unconditional branch */
3790 static inline uint32_t
3791 encode_branch_ofs_26 (uint32_t ofs
)
3793 return ofs
& ((1 << 26) - 1);
3796 /* encode the 19-bit offset of conditional branch and compare & branch */
3797 static inline uint32_t
3798 encode_cond_branch_ofs_19 (uint32_t ofs
)
3800 return (ofs
& ((1 << 19) - 1)) << 5;
3803 /* encode the 19-bit offset of ld literal */
3804 static inline uint32_t
3805 encode_ld_lit_ofs_19 (uint32_t ofs
)
3807 return (ofs
& ((1 << 19) - 1)) << 5;
3810 /* Encode the 14-bit offset of test & branch. */
3811 static inline uint32_t
3812 encode_tst_branch_ofs_14 (uint32_t ofs
)
3814 return (ofs
& ((1 << 14) - 1)) << 5;
3817 /* Encode the 16-bit imm field of svc/hvc/smc. */
3818 static inline uint32_t
3819 encode_svc_imm (uint32_t imm
)
3824 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3825 static inline uint32_t
3826 reencode_addsub_switch_add_sub (uint32_t opcode
)
3828 return opcode
^ (1 << 30);
3831 static inline uint32_t
3832 reencode_movzn_to_movz (uint32_t opcode
)
3834 return opcode
| (1 << 30);
3837 static inline uint32_t
3838 reencode_movzn_to_movn (uint32_t opcode
)
3840 return opcode
& ~(1 << 30);
3843 /* Overall per-instruction processing. */
3845 /* We need to be able to fix up arbitrary expressions in some statements.
3846 This is so that we can handle symbols that are an arbitrary distance from
3847 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3848 which returns part of an address in a form which will be valid for
3849 a data instruction. We do this by pushing the expression into a symbol
3850 in the expr_section, and creating a fix for that. */
3853 fix_new_aarch64 (fragS
* frag
,
3855 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3865 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3869 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3876 /* Diagnostics on operands errors. */
3878 /* By default, output verbose error message.
3879 Disable the verbose error message by -mno-verbose-error. */
3880 static int verbose_error_p
= 1;
3882 #ifdef DEBUG_AARCH64
3883 /* N.B. this is only for the purpose of debugging. */
3884 const char* operand_mismatch_kind_names
[] =
3887 "AARCH64_OPDE_RECOVERABLE",
3888 "AARCH64_OPDE_SYNTAX_ERROR",
3889 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3890 "AARCH64_OPDE_INVALID_VARIANT",
3891 "AARCH64_OPDE_OUT_OF_RANGE",
3892 "AARCH64_OPDE_UNALIGNED",
3893 "AARCH64_OPDE_REG_LIST",
3894 "AARCH64_OPDE_OTHER_ERROR",
3896 #endif /* DEBUG_AARCH64 */
3898 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3900 When multiple errors of different kinds are found in the same assembly
3901 line, only the error of the highest severity will be picked up for
3902 issuing the diagnostics. */
3904 static inline bfd_boolean
3905 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3906 enum aarch64_operand_error_kind rhs
)
3908 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3909 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3910 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3911 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3912 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3913 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3914 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3915 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3919 /* Helper routine to get the mnemonic name from the assembly instruction
3920 line; should only be called for the diagnosis purpose, as there is
3921 string copy operation involved, which may affect the runtime
3922 performance if used in elsewhere. */
3925 get_mnemonic_name (const char *str
)
3927 static char mnemonic
[32];
3930 /* Get the first 15 bytes and assume that the full name is included. */
3931 strncpy (mnemonic
, str
, 31);
3932 mnemonic
[31] = '\0';
3934 /* Scan up to the end of the mnemonic, which must end in white space,
3935 '.', or end of string. */
3936 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3941 /* Append '...' to the truncated long name. */
3942 if (ptr
- mnemonic
== 31)
3943 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3949 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3951 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3952 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3955 /* Data strutures storing one user error in the assembly code related to
3958 struct operand_error_record
3960 const aarch64_opcode
*opcode
;
3961 aarch64_operand_error detail
;
3962 struct operand_error_record
*next
;
3965 typedef struct operand_error_record operand_error_record
;
3967 struct operand_errors
3969 operand_error_record
*head
;
3970 operand_error_record
*tail
;
3973 typedef struct operand_errors operand_errors
;
3975 /* Top-level data structure reporting user errors for the current line of
3977 The way md_assemble works is that all opcodes sharing the same mnemonic
3978 name are iterated to find a match to the assembly line. In this data
3979 structure, each of the such opcodes will have one operand_error_record
3980 allocated and inserted. In other words, excessive errors related with
3981 a single opcode are disregarded. */
3982 operand_errors operand_error_report
;
3984 /* Free record nodes. */
3985 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
3987 /* Initialize the data structure that stores the operand mismatch
3988 information on assembling one line of the assembly code. */
3990 init_operand_error_report (void)
3992 if (operand_error_report
.head
!= NULL
)
3994 gas_assert (operand_error_report
.tail
!= NULL
);
3995 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
3996 free_opnd_error_record_nodes
= operand_error_report
.head
;
3997 operand_error_report
.head
= NULL
;
3998 operand_error_report
.tail
= NULL
;
4001 gas_assert (operand_error_report
.tail
== NULL
);
4004 /* Return TRUE if some operand error has been recorded during the
4005 parsing of the current assembly line using the opcode *OPCODE;
4006 otherwise return FALSE. */
4007 static inline bfd_boolean
4008 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4010 operand_error_record
*record
= operand_error_report
.head
;
4011 return record
&& record
->opcode
== opcode
;
4014 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4015 OPCODE field is initialized with OPCODE.
4016 N.B. only one record for each opcode, i.e. the maximum of one error is
4017 recorded for each instruction template. */
4020 add_operand_error_record (const operand_error_record
* new_record
)
4022 const aarch64_opcode
*opcode
= new_record
->opcode
;
4023 operand_error_record
* record
= operand_error_report
.head
;
4025 /* The record may have been created for this opcode. If not, we need
4027 if (! opcode_has_operand_error_p (opcode
))
4029 /* Get one empty record. */
4030 if (free_opnd_error_record_nodes
== NULL
)
4032 record
= XNEW (operand_error_record
);
4036 record
= free_opnd_error_record_nodes
;
4037 free_opnd_error_record_nodes
= record
->next
;
4039 record
->opcode
= opcode
;
4040 /* Insert at the head. */
4041 record
->next
= operand_error_report
.head
;
4042 operand_error_report
.head
= record
;
4043 if (operand_error_report
.tail
== NULL
)
4044 operand_error_report
.tail
= record
;
4046 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4047 && record
->detail
.index
<= new_record
->detail
.index
4048 && operand_error_higher_severity_p (record
->detail
.kind
,
4049 new_record
->detail
.kind
))
4051 /* In the case of multiple errors found on operands related with a
4052 single opcode, only record the error of the leftmost operand and
4053 only if the error is of higher severity. */
4054 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4055 " the existing error %s on operand %d",
4056 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4057 new_record
->detail
.index
,
4058 operand_mismatch_kind_names
[record
->detail
.kind
],
4059 record
->detail
.index
);
4063 record
->detail
= new_record
->detail
;
4067 record_operand_error_info (const aarch64_opcode
*opcode
,
4068 aarch64_operand_error
*error_info
)
4070 operand_error_record record
;
4071 record
.opcode
= opcode
;
4072 record
.detail
= *error_info
;
4073 add_operand_error_record (&record
);
4076 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4077 error message *ERROR, for operand IDX (count from 0). */
4080 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4081 enum aarch64_operand_error_kind kind
,
4084 aarch64_operand_error info
;
4085 memset(&info
, 0, sizeof (info
));
4089 record_operand_error_info (opcode
, &info
);
4093 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4094 enum aarch64_operand_error_kind kind
,
4095 const char* error
, const int *extra_data
)
4097 aarch64_operand_error info
;
4101 info
.data
[0] = extra_data
[0];
4102 info
.data
[1] = extra_data
[1];
4103 info
.data
[2] = extra_data
[2];
4104 record_operand_error_info (opcode
, &info
);
4108 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4109 const char* error
, int lower_bound
,
4112 int data
[3] = {lower_bound
, upper_bound
, 0};
4113 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4117 /* Remove the operand error record for *OPCODE. */
4118 static void ATTRIBUTE_UNUSED
4119 remove_operand_error_record (const aarch64_opcode
*opcode
)
4121 if (opcode_has_operand_error_p (opcode
))
4123 operand_error_record
* record
= operand_error_report
.head
;
4124 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4125 operand_error_report
.head
= record
->next
;
4126 record
->next
= free_opnd_error_record_nodes
;
4127 free_opnd_error_record_nodes
= record
;
4128 if (operand_error_report
.head
== NULL
)
4130 gas_assert (operand_error_report
.tail
== record
);
4131 operand_error_report
.tail
= NULL
;
4136 /* Given the instruction in *INSTR, return the index of the best matched
4137 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4139 Return -1 if there is no qualifier sequence; return the first match
4140 if there is multiple matches found. */
4143 find_best_match (const aarch64_inst
*instr
,
4144 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4146 int i
, num_opnds
, max_num_matched
, idx
;
4148 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4151 DEBUG_TRACE ("no operand");
4155 max_num_matched
= 0;
4158 /* For each pattern. */
4159 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4162 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4164 /* Most opcodes has much fewer patterns in the list. */
4165 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
4167 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4168 if (i
!= 0 && idx
== -1)
4169 /* If nothing has been matched, return the 1st sequence. */
4174 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4175 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4178 if (num_matched
> max_num_matched
)
4180 max_num_matched
= num_matched
;
4185 DEBUG_TRACE ("return with %d", idx
);
4189 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4190 corresponding operands in *INSTR. */
4193 assign_qualifier_sequence (aarch64_inst
*instr
,
4194 const aarch64_opnd_qualifier_t
*qualifiers
)
4197 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4198 gas_assert (num_opnds
);
4199 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4200 instr
->operands
[i
].qualifier
= *qualifiers
;
4203 /* Print operands for the diagnosis purpose. */
4206 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4207 const aarch64_opnd_info
*opnds
)
4211 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4215 /* We regard the opcode operand info more, however we also look into
4216 the inst->operands to support the disassembling of the optional
4218 The two operand code should be the same in all cases, apart from
4219 when the operand can be optional. */
4220 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4221 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4224 /* Generate the operand string in STR. */
4225 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
);
4229 strcat (buf
, i
== 0 ? " " : ",");
4231 /* Append the operand string. */
4236 /* Send to stderr a string as information. */
4239 output_info (const char *format
, ...)
4245 file
= as_where (&line
);
4249 fprintf (stderr
, "%s:%u: ", file
, line
);
4251 fprintf (stderr
, "%s: ", file
);
4253 fprintf (stderr
, _("Info: "));
4254 va_start (args
, format
);
4255 vfprintf (stderr
, format
, args
);
4257 (void) putc ('\n', stderr
);
4260 /* Output one operand error record. */
4263 output_operand_error_record (const operand_error_record
*record
, char *str
)
4265 const aarch64_operand_error
*detail
= &record
->detail
;
4266 int idx
= detail
->index
;
4267 const aarch64_opcode
*opcode
= record
->opcode
;
4268 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4269 : AARCH64_OPND_NIL
);
4271 switch (detail
->kind
)
4273 case AARCH64_OPDE_NIL
:
4277 case AARCH64_OPDE_SYNTAX_ERROR
:
4278 case AARCH64_OPDE_RECOVERABLE
:
4279 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4280 case AARCH64_OPDE_OTHER_ERROR
:
4281 /* Use the prepared error message if there is, otherwise use the
4282 operand description string to describe the error. */
4283 if (detail
->error
!= NULL
)
4286 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4288 as_bad (_("%s at operand %d -- `%s'"),
4289 detail
->error
, idx
+ 1, str
);
4293 gas_assert (idx
>= 0);
4294 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4295 aarch64_get_operand_desc (opd_code
), str
);
4299 case AARCH64_OPDE_INVALID_VARIANT
:
4300 as_bad (_("operand mismatch -- `%s'"), str
);
4301 if (verbose_error_p
)
4303 /* We will try to correct the erroneous instruction and also provide
4304 more information e.g. all other valid variants.
4306 The string representation of the corrected instruction and other
4307 valid variants are generated by
4309 1) obtaining the intermediate representation of the erroneous
4311 2) manipulating the IR, e.g. replacing the operand qualifier;
4312 3) printing out the instruction by calling the printer functions
4313 shared with the disassembler.
4315 The limitation of this method is that the exact input assembly
4316 line cannot be accurately reproduced in some cases, for example an
4317 optional operand present in the actual assembly line will be
4318 omitted in the output; likewise for the optional syntax rules,
4319 e.g. the # before the immediate. Another limitation is that the
4320 assembly symbols and relocation operations in the assembly line
4321 currently cannot be printed out in the error report. Last but not
4322 least, when there is other error(s) co-exist with this error, the
4323 'corrected' instruction may be still incorrect, e.g. given
4324 'ldnp h0,h1,[x0,#6]!'
4325 this diagnosis will provide the version:
4326 'ldnp s0,s1,[x0,#6]!'
4327 which is still not right. */
4328 size_t len
= strlen (get_mnemonic_name (str
));
4332 aarch64_inst
*inst_base
= &inst
.base
;
4333 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4336 reset_aarch64_instruction (&inst
);
4337 inst_base
->opcode
= opcode
;
4339 /* Reset the error report so that there is no side effect on the
4340 following operand parsing. */
4341 init_operand_error_report ();
4344 result
= parse_operands (str
+ len
, opcode
)
4345 && programmer_friendly_fixup (&inst
);
4346 gas_assert (result
);
4347 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4349 gas_assert (!result
);
4351 /* Find the most matched qualifier sequence. */
4352 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4353 gas_assert (qlf_idx
> -1);
4355 /* Assign the qualifiers. */
4356 assign_qualifier_sequence (inst_base
,
4357 opcode
->qualifiers_list
[qlf_idx
]);
4359 /* Print the hint. */
4360 output_info (_(" did you mean this?"));
4361 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4362 print_operands (buf
, opcode
, inst_base
->operands
);
4363 output_info (_(" %s"), buf
);
4365 /* Print out other variant(s) if there is any. */
4367 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4368 output_info (_(" other valid variant(s):"));
4370 /* For each pattern. */
4371 qualifiers_list
= opcode
->qualifiers_list
;
4372 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4374 /* Most opcodes has much fewer patterns in the list.
4375 First NIL qualifier indicates the end in the list. */
4376 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4381 /* Mnemonics name. */
4382 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4384 /* Assign the qualifiers. */
4385 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4387 /* Print instruction. */
4388 print_operands (buf
, opcode
, inst_base
->operands
);
4390 output_info (_(" %s"), buf
);
4396 case AARCH64_OPDE_OUT_OF_RANGE
:
4397 if (detail
->data
[0] != detail
->data
[1])
4398 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4399 detail
->error
? detail
->error
: _("immediate value"),
4400 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4402 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4403 detail
->error
? detail
->error
: _("immediate value"),
4404 detail
->data
[0], idx
+ 1, str
);
4407 case AARCH64_OPDE_REG_LIST
:
4408 if (detail
->data
[0] == 1)
4409 as_bad (_("invalid number of registers in the list; "
4410 "only 1 register is expected at operand %d -- `%s'"),
4413 as_bad (_("invalid number of registers in the list; "
4414 "%d registers are expected at operand %d -- `%s'"),
4415 detail
->data
[0], idx
+ 1, str
);
4418 case AARCH64_OPDE_UNALIGNED
:
4419 as_bad (_("immediate value should be a multiple of "
4420 "%d at operand %d -- `%s'"),
4421 detail
->data
[0], idx
+ 1, str
);
4430 /* Process and output the error message about the operand mismatching.
4432 When this function is called, the operand error information had
4433 been collected for an assembly line and there will be multiple
4434 errors in the case of mulitple instruction templates; output the
4435 error message that most closely describes the problem. */
4438 output_operand_error_report (char *str
)
4440 int largest_error_pos
;
4441 const char *msg
= NULL
;
4442 enum aarch64_operand_error_kind kind
;
4443 operand_error_record
*curr
;
4444 operand_error_record
*head
= operand_error_report
.head
;
4445 operand_error_record
*record
= NULL
;
4447 /* No error to report. */
4451 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4453 /* Only one error. */
4454 if (head
== operand_error_report
.tail
)
4456 DEBUG_TRACE ("single opcode entry with error kind: %s",
4457 operand_mismatch_kind_names
[head
->detail
.kind
]);
4458 output_operand_error_record (head
, str
);
4462 /* Find the error kind of the highest severity. */
4463 DEBUG_TRACE ("multiple opcode entres with error kind");
4464 kind
= AARCH64_OPDE_NIL
;
4465 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4467 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4468 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4469 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4470 kind
= curr
->detail
.kind
;
4472 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4474 /* Pick up one of errors of KIND to report. */
4475 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4476 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4478 if (curr
->detail
.kind
!= kind
)
4480 /* If there are multiple errors, pick up the one with the highest
4481 mismatching operand index. In the case of multiple errors with
4482 the equally highest operand index, pick up the first one or the
4483 first one with non-NULL error message. */
4484 if (curr
->detail
.index
> largest_error_pos
4485 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4486 && curr
->detail
.error
!= NULL
))
4488 largest_error_pos
= curr
->detail
.index
;
4490 msg
= record
->detail
.error
;
4494 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4495 DEBUG_TRACE ("Pick up error kind %s to report",
4496 operand_mismatch_kind_names
[record
->detail
.kind
]);
4499 output_operand_error_record (record
, str
);
4502 /* Write an AARCH64 instruction to buf - always little-endian. */
4504 put_aarch64_insn (char *buf
, uint32_t insn
)
4506 unsigned char *where
= (unsigned char *) buf
;
4508 where
[1] = insn
>> 8;
4509 where
[2] = insn
>> 16;
4510 where
[3] = insn
>> 24;
4514 get_aarch64_insn (char *buf
)
4516 unsigned char *where
= (unsigned char *) buf
;
4518 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4523 output_inst (struct aarch64_inst
*new_inst
)
4527 to
= frag_more (INSN_SIZE
);
4529 frag_now
->tc_frag_data
.recorded
= 1;
4531 put_aarch64_insn (to
, inst
.base
.value
);
4533 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4535 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4536 INSN_SIZE
, &inst
.reloc
.exp
,
4539 DEBUG_TRACE ("Prepared relocation fix up");
4540 /* Don't check the addend value against the instruction size,
4541 that's the job of our code in md_apply_fix(). */
4542 fixp
->fx_no_overflow
= 1;
4543 if (new_inst
!= NULL
)
4544 fixp
->tc_fix_data
.inst
= new_inst
;
4545 if (aarch64_gas_internal_fixup_p ())
4547 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4548 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4549 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4553 dwarf2_emit_insn (INSN_SIZE
);
4556 /* Link together opcodes of the same name. */
4560 aarch64_opcode
*opcode
;
4561 struct templates
*next
;
4564 typedef struct templates templates
;
4567 lookup_mnemonic (const char *start
, int len
)
4569 templates
*templ
= NULL
;
4571 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4575 /* Subroutine of md_assemble, responsible for looking up the primary
4576 opcode from the mnemonic the user wrote. STR points to the
4577 beginning of the mnemonic. */
4580 opcode_lookup (char **str
)
4583 const aarch64_cond
*cond
;
4587 /* Scan up to the end of the mnemonic, which must end in white space,
4588 '.', or end of string. */
4589 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4596 inst
.cond
= COND_ALWAYS
;
4598 /* Handle a possible condition. */
4601 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4604 inst
.cond
= cond
->value
;
4618 if (inst
.cond
== COND_ALWAYS
)
4620 /* Look for unaffixed mnemonic. */
4621 return lookup_mnemonic (base
, len
);
4625 /* append ".c" to mnemonic if conditional */
4626 memcpy (condname
, base
, len
);
4627 memcpy (condname
+ len
, ".c", 2);
4630 return lookup_mnemonic (base
, len
);
4636 /* Internal helper routine converting a vector_type_el structure *VECTYPE
4637 to a corresponding operand qualifier. */
4639 static inline aarch64_opnd_qualifier_t
4640 vectype_to_qualifier (const struct vector_type_el
*vectype
)
4642 /* Element size in bytes indexed by vector_el_type. */
4643 const unsigned char ele_size
[5]
4645 const unsigned int ele_base
[5] =
4647 AARCH64_OPND_QLF_V_8B
,
4648 AARCH64_OPND_QLF_V_2H
,
4649 AARCH64_OPND_QLF_V_2S
,
4650 AARCH64_OPND_QLF_V_1D
,
4651 AARCH64_OPND_QLF_V_1Q
4654 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4655 goto vectype_conversion_fail
;
4657 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4659 if (vectype
->defined
& NTA_HASINDEX
)
4660 /* Vector element register. */
4661 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4664 /* Vector register. */
4665 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4668 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
4669 goto vectype_conversion_fail
;
4671 /* The conversion is by calculating the offset from the base operand
4672 qualifier for the vector type. The operand qualifiers are regular
4673 enough that the offset can established by shifting the vector width by
4674 a vector-type dependent amount. */
4676 if (vectype
->type
== NT_b
)
4678 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
4680 else if (vectype
->type
>= NT_d
)
4685 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
4686 gas_assert (AARCH64_OPND_QLF_V_8B
<= offset
4687 && offset
<= AARCH64_OPND_QLF_V_1Q
);
4691 vectype_conversion_fail
:
4692 first_error (_("bad vector arrangement type"));
4693 return AARCH64_OPND_QLF_NIL
;
4696 /* Process an optional operand that is found omitted from the assembly line.
4697 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4698 instruction's opcode entry while IDX is the index of this omitted operand.
4702 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4703 int idx
, aarch64_opnd_info
*operand
)
4705 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4706 gas_assert (optional_operand_p (opcode
, idx
));
4707 gas_assert (!operand
->present
);
4711 case AARCH64_OPND_Rd
:
4712 case AARCH64_OPND_Rn
:
4713 case AARCH64_OPND_Rm
:
4714 case AARCH64_OPND_Rt
:
4715 case AARCH64_OPND_Rt2
:
4716 case AARCH64_OPND_Rs
:
4717 case AARCH64_OPND_Ra
:
4718 case AARCH64_OPND_Rt_SYS
:
4719 case AARCH64_OPND_Rd_SP
:
4720 case AARCH64_OPND_Rn_SP
:
4721 case AARCH64_OPND_Fd
:
4722 case AARCH64_OPND_Fn
:
4723 case AARCH64_OPND_Fm
:
4724 case AARCH64_OPND_Fa
:
4725 case AARCH64_OPND_Ft
:
4726 case AARCH64_OPND_Ft2
:
4727 case AARCH64_OPND_Sd
:
4728 case AARCH64_OPND_Sn
:
4729 case AARCH64_OPND_Sm
:
4730 case AARCH64_OPND_Vd
:
4731 case AARCH64_OPND_Vn
:
4732 case AARCH64_OPND_Vm
:
4733 case AARCH64_OPND_VdD1
:
4734 case AARCH64_OPND_VnD1
:
4735 operand
->reg
.regno
= default_value
;
4738 case AARCH64_OPND_Ed
:
4739 case AARCH64_OPND_En
:
4740 case AARCH64_OPND_Em
:
4741 operand
->reglane
.regno
= default_value
;
4744 case AARCH64_OPND_IDX
:
4745 case AARCH64_OPND_BIT_NUM
:
4746 case AARCH64_OPND_IMMR
:
4747 case AARCH64_OPND_IMMS
:
4748 case AARCH64_OPND_SHLL_IMM
:
4749 case AARCH64_OPND_IMM_VLSL
:
4750 case AARCH64_OPND_IMM_VLSR
:
4751 case AARCH64_OPND_CCMP_IMM
:
4752 case AARCH64_OPND_FBITS
:
4753 case AARCH64_OPND_UIMM4
:
4754 case AARCH64_OPND_UIMM3_OP1
:
4755 case AARCH64_OPND_UIMM3_OP2
:
4756 case AARCH64_OPND_IMM
:
4757 case AARCH64_OPND_WIDTH
:
4758 case AARCH64_OPND_UIMM7
:
4759 case AARCH64_OPND_NZCV
:
4760 operand
->imm
.value
= default_value
;
4763 case AARCH64_OPND_EXCEPTION
:
4764 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4767 case AARCH64_OPND_BARRIER_ISB
:
4768 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4775 /* Process the relocation type for move wide instructions.
4776 Return TRUE on success; otherwise return FALSE. */
4779 process_movw_reloc_info (void)
4784 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4786 if (inst
.base
.opcode
->op
== OP_MOVK
)
4787 switch (inst
.reloc
.type
)
4789 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4790 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4791 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4792 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4793 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4794 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4795 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4797 (_("the specified relocation type is not allowed for MOVK"));
4803 switch (inst
.reloc
.type
)
4805 case BFD_RELOC_AARCH64_MOVW_G0
:
4806 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4807 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4808 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
4809 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
4810 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
4811 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
4812 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
4813 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
4814 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4815 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4818 case BFD_RELOC_AARCH64_MOVW_G1
:
4819 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4820 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4821 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
4822 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
4823 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4824 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
4825 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
4826 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
4827 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4828 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4831 case BFD_RELOC_AARCH64_MOVW_G2
:
4832 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4833 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4834 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
4835 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4838 set_fatal_syntax_error
4839 (_("the specified relocation type is not allowed for 32-bit "
4845 case BFD_RELOC_AARCH64_MOVW_G3
:
4848 set_fatal_syntax_error
4849 (_("the specified relocation type is not allowed for 32-bit "
4856 /* More cases should be added when more MOVW-related relocation types
4857 are supported in GAS. */
4858 gas_assert (aarch64_gas_internal_fixup_p ());
4859 /* The shift amount should have already been set by the parser. */
4862 inst
.base
.operands
[1].shifter
.amount
= shift
;
4866 /* A primitive log caculator. */
4868 static inline unsigned int
4869 get_logsz (unsigned int size
)
4871 const unsigned char ls
[16] =
4872 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4878 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4879 return ls
[size
- 1];
4882 /* Determine and return the real reloc type code for an instruction
4883 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4885 static inline bfd_reloc_code_real_type
4886 ldst_lo12_determine_real_reloc_type (void)
4889 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4890 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4892 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
4894 BFD_RELOC_AARCH64_LDST8_LO12
,
4895 BFD_RELOC_AARCH64_LDST16_LO12
,
4896 BFD_RELOC_AARCH64_LDST32_LO12
,
4897 BFD_RELOC_AARCH64_LDST64_LO12
,
4898 BFD_RELOC_AARCH64_LDST128_LO12
4901 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
4902 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
4903 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
4904 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
4905 BFD_RELOC_AARCH64_NONE
4908 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
4909 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
4910 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
4911 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
4912 BFD_RELOC_AARCH64_NONE
4916 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
4917 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4919 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
4920 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4922 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4924 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4926 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4928 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4929 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4930 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
4931 gas_assert (logsz
<= 3);
4933 gas_assert (logsz
<= 4);
4935 /* In reloc.c, these pseudo relocation types should be defined in similar
4936 order as above reloc_ldst_lo12 array. Because the array index calcuation
4937 below relies on this. */
4938 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
4941 /* Check whether a register list REGINFO is valid. The registers must be
4942 numbered in increasing order (modulo 32), in increments of one or two.
4944 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4947 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4950 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4952 uint32_t i
, nb_regs
, prev_regno
, incr
;
4954 nb_regs
= 1 + (reginfo
& 0x3);
4956 prev_regno
= reginfo
& 0x1f;
4957 incr
= accept_alternate
? 2 : 1;
4959 for (i
= 1; i
< nb_regs
; ++i
)
4961 uint32_t curr_regno
;
4963 curr_regno
= reginfo
& 0x1f;
4964 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4966 prev_regno
= curr_regno
;
4972 /* Generic instruction operand parser. This does no encoding and no
4973 semantic validation; it merely squirrels values away in the inst
4974 structure. Returns TRUE or FALSE depending on whether the
4975 specified grammar matched. */
4978 parse_operands (char *str
, const aarch64_opcode
*opcode
)
4981 char *backtrack_pos
= 0;
4982 const enum aarch64_opnd
*operands
= opcode
->operands
;
4985 skip_whitespace (str
);
4987 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
4990 int isreg32
, isregzero
;
4991 int comma_skipped_p
= 0;
4992 aarch64_reg_type rtype
;
4993 struct vector_type_el vectype
;
4994 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
4996 DEBUG_TRACE ("parse operand %d", i
);
4998 /* Assign the operand code. */
4999 info
->type
= operands
[i
];
5001 if (optional_operand_p (opcode
, i
))
5003 /* Remember where we are in case we need to backtrack. */
5004 gas_assert (!backtrack_pos
);
5005 backtrack_pos
= str
;
5008 /* Expect comma between operands; the backtrack mechanizm will take
5009 care of cases of omitted optional operand. */
5010 if (i
> 0 && ! skip_past_char (&str
, ','))
5012 set_syntax_error (_("comma expected between operands"));
5016 comma_skipped_p
= 1;
5018 switch (operands
[i
])
5020 case AARCH64_OPND_Rd
:
5021 case AARCH64_OPND_Rn
:
5022 case AARCH64_OPND_Rm
:
5023 case AARCH64_OPND_Rt
:
5024 case AARCH64_OPND_Rt2
:
5025 case AARCH64_OPND_Rs
:
5026 case AARCH64_OPND_Ra
:
5027 case AARCH64_OPND_Rt_SYS
:
5028 case AARCH64_OPND_PAIRREG
:
5029 po_int_reg_or_fail (1, 0);
5032 case AARCH64_OPND_Rd_SP
:
5033 case AARCH64_OPND_Rn_SP
:
5034 po_int_reg_or_fail (0, 1);
5037 case AARCH64_OPND_Rm_EXT
:
5038 case AARCH64_OPND_Rm_SFT
:
5039 po_misc_or_fail (parse_shifter_operand
5040 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5042 : SHIFTED_LOGIC_IMM
)));
5043 if (!info
->shifter
.operator_present
)
5045 /* Default to LSL if not present. Libopcodes prefers shifter
5046 kind to be explicit. */
5047 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5048 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5049 /* For Rm_EXT, libopcodes will carry out further check on whether
5050 or not stack pointer is used in the instruction (Recall that
5051 "the extend operator is not optional unless at least one of
5052 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5056 case AARCH64_OPND_Fd
:
5057 case AARCH64_OPND_Fn
:
5058 case AARCH64_OPND_Fm
:
5059 case AARCH64_OPND_Fa
:
5060 case AARCH64_OPND_Ft
:
5061 case AARCH64_OPND_Ft2
:
5062 case AARCH64_OPND_Sd
:
5063 case AARCH64_OPND_Sn
:
5064 case AARCH64_OPND_Sm
:
5065 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5066 if (val
== PARSE_FAIL
)
5068 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5071 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5073 info
->reg
.regno
= val
;
5074 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5077 case AARCH64_OPND_Vd
:
5078 case AARCH64_OPND_Vn
:
5079 case AARCH64_OPND_Vm
:
5080 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5081 if (val
== PARSE_FAIL
)
5083 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5086 if (vectype
.defined
& NTA_HASINDEX
)
5089 info
->reg
.regno
= val
;
5090 info
->qualifier
= vectype_to_qualifier (&vectype
);
5091 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5095 case AARCH64_OPND_VdD1
:
5096 case AARCH64_OPND_VnD1
:
5097 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5098 if (val
== PARSE_FAIL
)
5100 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5103 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5105 set_fatal_syntax_error
5106 (_("the top half of a 128-bit FP/SIMD register is expected"));
5109 info
->reg
.regno
= val
;
5110 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5111 here; it is correct for the purpose of encoding/decoding since
5112 only the register number is explicitly encoded in the related
5113 instructions, although this appears a bit hacky. */
5114 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5117 case AARCH64_OPND_Ed
:
5118 case AARCH64_OPND_En
:
5119 case AARCH64_OPND_Em
:
5120 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5121 if (val
== PARSE_FAIL
)
5123 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5126 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5129 info
->reglane
.regno
= val
;
5130 info
->reglane
.index
= vectype
.index
;
5131 info
->qualifier
= vectype_to_qualifier (&vectype
);
5132 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5136 case AARCH64_OPND_LVn
:
5137 case AARCH64_OPND_LVt
:
5138 case AARCH64_OPND_LVt_AL
:
5139 case AARCH64_OPND_LEt
:
5140 if ((val
= parse_vector_reg_list (&str
, REG_TYPE_VN
,
5141 &vectype
)) == PARSE_FAIL
)
5143 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5145 set_fatal_syntax_error (_("invalid register list"));
5148 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5149 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5150 if (operands
[i
] == AARCH64_OPND_LEt
)
5152 if (!(vectype
.defined
& NTA_HASINDEX
))
5154 info
->reglist
.has_index
= 1;
5155 info
->reglist
.index
= vectype
.index
;
5157 else if (!(vectype
.defined
& NTA_HASTYPE
))
5159 info
->qualifier
= vectype_to_qualifier (&vectype
);
5160 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5164 case AARCH64_OPND_Cn
:
5165 case AARCH64_OPND_Cm
:
5166 po_reg_or_fail (REG_TYPE_CN
);
5169 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
5172 inst
.base
.operands
[i
].reg
.regno
= val
;
5175 case AARCH64_OPND_SHLL_IMM
:
5176 case AARCH64_OPND_IMM_VLSR
:
5177 po_imm_or_fail (1, 64);
5178 info
->imm
.value
= val
;
5181 case AARCH64_OPND_CCMP_IMM
:
5182 case AARCH64_OPND_FBITS
:
5183 case AARCH64_OPND_UIMM4
:
5184 case AARCH64_OPND_UIMM3_OP1
:
5185 case AARCH64_OPND_UIMM3_OP2
:
5186 case AARCH64_OPND_IMM_VLSL
:
5187 case AARCH64_OPND_IMM
:
5188 case AARCH64_OPND_WIDTH
:
5189 po_imm_nc_or_fail ();
5190 info
->imm
.value
= val
;
5193 case AARCH64_OPND_UIMM7
:
5194 po_imm_or_fail (0, 127);
5195 info
->imm
.value
= val
;
5198 case AARCH64_OPND_IDX
:
5199 case AARCH64_OPND_BIT_NUM
:
5200 case AARCH64_OPND_IMMR
:
5201 case AARCH64_OPND_IMMS
:
5202 po_imm_or_fail (0, 63);
5203 info
->imm
.value
= val
;
5206 case AARCH64_OPND_IMM0
:
5207 po_imm_nc_or_fail ();
5210 set_fatal_syntax_error (_("immediate zero expected"));
5213 info
->imm
.value
= 0;
5216 case AARCH64_OPND_FPIMM0
:
5219 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5220 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5221 it is probably not worth the effort to support it. */
5222 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
5223 && !(res2
= parse_constant_immediate (&str
, &val
)))
5225 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5227 info
->imm
.value
= 0;
5228 info
->imm
.is_fp
= 1;
5231 set_fatal_syntax_error (_("immediate zero expected"));
5235 case AARCH64_OPND_IMM_MOV
:
5238 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5239 reg_name_p (str
, REG_TYPE_VN
))
5242 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5244 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5245 later. fix_mov_imm_insn will try to determine a machine
5246 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5247 message if the immediate cannot be moved by a single
5249 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5250 inst
.base
.operands
[i
].skip
= 1;
5254 case AARCH64_OPND_SIMD_IMM
:
5255 case AARCH64_OPND_SIMD_IMM_SFT
:
5256 if (! parse_big_immediate (&str
, &val
))
5258 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5260 /* need_libopcodes_p */ 1,
5263 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5264 shift, we don't check it here; we leave the checking to
5265 the libopcodes (operand_general_constraint_met_p). By
5266 doing this, we achieve better diagnostics. */
5267 if (skip_past_comma (&str
)
5268 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5270 if (!info
->shifter
.operator_present
5271 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5273 /* Default to LSL if not present. Libopcodes prefers shifter
5274 kind to be explicit. */
5275 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5276 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5280 case AARCH64_OPND_FPIMM
:
5281 case AARCH64_OPND_SIMD_FPIMM
:
5285 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
5287 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
5291 set_fatal_syntax_error (_("invalid floating-point constant"));
5294 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5295 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5299 case AARCH64_OPND_LIMM
:
5300 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5301 SHIFTED_LOGIC_IMM
));
5302 if (info
->shifter
.operator_present
)
5304 set_fatal_syntax_error
5305 (_("shift not allowed for bitmask immediate"));
5308 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5310 /* need_libopcodes_p */ 1,
5314 case AARCH64_OPND_AIMM
:
5315 if (opcode
->op
== OP_ADD
)
5316 /* ADD may have relocation types. */
5317 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5318 SHIFTED_ARITH_IMM
));
5320 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5321 SHIFTED_ARITH_IMM
));
5322 switch (inst
.reloc
.type
)
5324 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5325 info
->shifter
.amount
= 12;
5327 case BFD_RELOC_UNUSED
:
5328 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5329 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5330 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5331 inst
.reloc
.pc_rel
= 0;
5336 info
->imm
.value
= 0;
5337 if (!info
->shifter
.operator_present
)
5339 /* Default to LSL if not present. Libopcodes prefers shifter
5340 kind to be explicit. */
5341 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5342 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5346 case AARCH64_OPND_HALF
:
5348 /* #<imm16> or relocation. */
5349 int internal_fixup_p
;
5350 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5351 if (internal_fixup_p
)
5352 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5353 skip_whitespace (str
);
5354 if (skip_past_comma (&str
))
5356 /* {, LSL #<shift>} */
5357 if (! aarch64_gas_internal_fixup_p ())
5359 set_fatal_syntax_error (_("can't mix relocation modifier "
5360 "with explicit shift"));
5363 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5366 inst
.base
.operands
[i
].shifter
.amount
= 0;
5367 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5368 inst
.base
.operands
[i
].imm
.value
= 0;
5369 if (! process_movw_reloc_info ())
5374 case AARCH64_OPND_EXCEPTION
:
5375 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
5376 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5378 /* need_libopcodes_p */ 0,
5382 case AARCH64_OPND_NZCV
:
5384 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5388 info
->imm
.value
= nzcv
->value
;
5391 po_imm_or_fail (0, 15);
5392 info
->imm
.value
= val
;
5396 case AARCH64_OPND_COND
:
5397 case AARCH64_OPND_COND1
:
5398 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5400 if (info
->cond
== NULL
)
5402 set_syntax_error (_("invalid condition"));
5405 else if (operands
[i
] == AARCH64_OPND_COND1
5406 && (info
->cond
->value
& 0xe) == 0xe)
5408 /* Not allow AL or NV. */
5409 set_default_error ();
5414 case AARCH64_OPND_ADDR_ADRP
:
5415 po_misc_or_fail (parse_adrp (&str
));
5416 /* Clear the value as operand needs to be relocated. */
5417 info
->imm
.value
= 0;
5420 case AARCH64_OPND_ADDR_PCREL14
:
5421 case AARCH64_OPND_ADDR_PCREL19
:
5422 case AARCH64_OPND_ADDR_PCREL21
:
5423 case AARCH64_OPND_ADDR_PCREL26
:
5424 po_misc_or_fail (parse_address_reloc (&str
, info
));
5425 if (!info
->addr
.pcrel
)
5427 set_syntax_error (_("invalid pc-relative address"));
5430 if (inst
.gen_lit_pool
5431 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5433 /* Only permit "=value" in the literal load instructions.
5434 The literal will be generated by programmer_friendly_fixup. */
5435 set_syntax_error (_("invalid use of \"=immediate\""));
5438 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5440 set_syntax_error (_("unrecognized relocation suffix"));
5443 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5445 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5446 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5450 info
->imm
.value
= 0;
5451 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5452 switch (opcode
->iclass
)
5456 /* e.g. CBZ or B.COND */
5457 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5458 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5462 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5463 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5467 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5469 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5470 : BFD_RELOC_AARCH64_JUMP26
;
5473 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5474 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5477 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5478 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5484 inst
.reloc
.pc_rel
= 1;
5488 case AARCH64_OPND_ADDR_SIMPLE
:
5489 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5490 /* [<Xn|SP>{, #<simm>}] */
5491 po_char_or_fail ('[');
5492 po_reg_or_fail (REG_TYPE_R64_SP
);
5493 /* Accept optional ", #0". */
5494 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5495 && skip_past_char (&str
, ','))
5497 skip_past_char (&str
, '#');
5498 if (! skip_past_char (&str
, '0'))
5500 set_fatal_syntax_error
5501 (_("the optional immediate offset can only be 0"));
5505 po_char_or_fail (']');
5506 info
->addr
.base_regno
= val
;
5509 case AARCH64_OPND_ADDR_REGOFF
:
5510 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5511 po_misc_or_fail (parse_address (&str
, info
, 0));
5512 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5513 || !info
->addr
.preind
|| info
->addr
.postind
5514 || info
->addr
.writeback
)
5516 set_syntax_error (_("invalid addressing mode"));
5519 if (!info
->shifter
.operator_present
)
5521 /* Default to LSL if not present. Libopcodes prefers shifter
5522 kind to be explicit. */
5523 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5524 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5526 /* Qualifier to be deduced by libopcodes. */
5529 case AARCH64_OPND_ADDR_SIMM7
:
5530 po_misc_or_fail (parse_address (&str
, info
, 0));
5531 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5532 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5534 set_syntax_error (_("invalid addressing mode"));
5537 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5539 /* need_libopcodes_p */ 1,
5543 case AARCH64_OPND_ADDR_SIMM9
:
5544 case AARCH64_OPND_ADDR_SIMM9_2
:
5545 po_misc_or_fail (parse_address_reloc (&str
, info
));
5546 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5547 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5548 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5549 && info
->addr
.writeback
))
5551 set_syntax_error (_("invalid addressing mode"));
5554 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5556 set_syntax_error (_("relocation not allowed"));
5559 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5561 /* need_libopcodes_p */ 1,
5565 case AARCH64_OPND_ADDR_UIMM12
:
5566 po_misc_or_fail (parse_address_reloc (&str
, info
));
5567 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5568 || !info
->addr
.preind
|| info
->addr
.writeback
)
5570 set_syntax_error (_("invalid addressing mode"));
5573 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5574 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5575 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5577 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
5579 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
5580 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5581 /* Leave qualifier to be determined by libopcodes. */
5584 case AARCH64_OPND_SIMD_ADDR_POST
:
5585 /* [<Xn|SP>], <Xm|#<amount>> */
5586 po_misc_or_fail (parse_address (&str
, info
, 1));
5587 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5589 set_syntax_error (_("invalid addressing mode"));
5592 if (!info
->addr
.offset
.is_reg
)
5594 if (inst
.reloc
.exp
.X_op
== O_constant
)
5595 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5598 set_fatal_syntax_error
5599 (_("writeback value should be an immediate constant"));
5606 case AARCH64_OPND_SYSREG
:
5607 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
5610 set_syntax_error (_("unknown or missing system register name"));
5613 inst
.base
.operands
[i
].sysreg
= val
;
5616 case AARCH64_OPND_PSTATEFIELD
:
5617 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
5620 set_syntax_error (_("unknown or missing PSTATE field name"));
5623 inst
.base
.operands
[i
].pstatefield
= val
;
5626 case AARCH64_OPND_SYSREG_IC
:
5627 inst
.base
.operands
[i
].sysins_op
=
5628 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5630 case AARCH64_OPND_SYSREG_DC
:
5631 inst
.base
.operands
[i
].sysins_op
=
5632 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5634 case AARCH64_OPND_SYSREG_AT
:
5635 inst
.base
.operands
[i
].sysins_op
=
5636 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5638 case AARCH64_OPND_SYSREG_TLBI
:
5639 inst
.base
.operands
[i
].sysins_op
=
5640 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5642 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5644 set_fatal_syntax_error ( _("unknown or missing operation name"));
5649 case AARCH64_OPND_BARRIER
:
5650 case AARCH64_OPND_BARRIER_ISB
:
5651 val
= parse_barrier (&str
);
5652 if (val
!= PARSE_FAIL
5653 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5655 /* ISB only accepts options name 'sy'. */
5657 (_("the specified option is not accepted in ISB"));
5658 /* Turn off backtrack as this optional operand is present. */
5662 /* This is an extension to accept a 0..15 immediate. */
5663 if (val
== PARSE_FAIL
)
5664 po_imm_or_fail (0, 15);
5665 info
->barrier
= aarch64_barrier_options
+ val
;
5668 case AARCH64_OPND_PRFOP
:
5669 val
= parse_pldop (&str
);
5670 /* This is an extension to accept a 0..31 immediate. */
5671 if (val
== PARSE_FAIL
)
5672 po_imm_or_fail (0, 31);
5673 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5676 case AARCH64_OPND_BARRIER_PSB
:
5677 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
5678 if (val
== PARSE_FAIL
)
5683 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5686 /* If we get here, this operand was successfully parsed. */
5687 inst
.base
.operands
[i
].present
= 1;
5691 /* The parse routine should already have set the error, but in case
5692 not, set a default one here. */
5694 set_default_error ();
5696 if (! backtrack_pos
)
5697 goto parse_operands_return
;
5700 /* We reach here because this operand is marked as optional, and
5701 either no operand was supplied or the operand was supplied but it
5702 was syntactically incorrect. In the latter case we report an
5703 error. In the former case we perform a few more checks before
5704 dropping through to the code to insert the default operand. */
5706 char *tmp
= backtrack_pos
;
5707 char endchar
= END_OF_INSN
;
5709 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5711 skip_past_char (&tmp
, ',');
5713 if (*tmp
!= endchar
)
5714 /* The user has supplied an operand in the wrong format. */
5715 goto parse_operands_return
;
5717 /* Make sure there is not a comma before the optional operand.
5718 For example the fifth operand of 'sys' is optional:
5720 sys #0,c0,c0,#0, <--- wrong
5721 sys #0,c0,c0,#0 <--- correct. */
5722 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5724 set_fatal_syntax_error
5725 (_("unexpected comma before the omitted optional operand"));
5726 goto parse_operands_return
;
5730 /* Reaching here means we are dealing with an optional operand that is
5731 omitted from the assembly line. */
5732 gas_assert (optional_operand_p (opcode
, i
));
5734 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5736 /* Try again, skipping the optional operand at backtrack_pos. */
5737 str
= backtrack_pos
;
5740 /* Clear any error record after the omitted optional operand has been
5741 successfully handled. */
5745 /* Check if we have parsed all the operands. */
5746 if (*str
!= '\0' && ! error_p ())
5748 /* Set I to the index of the last present operand; this is
5749 for the purpose of diagnostics. */
5750 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5752 set_fatal_syntax_error
5753 (_("unexpected characters following instruction"));
5756 parse_operands_return
:
5760 DEBUG_TRACE ("parsing FAIL: %s - %s",
5761 operand_mismatch_kind_names
[get_error_kind ()],
5762 get_error_message ());
5763 /* Record the operand error properly; this is useful when there
5764 are multiple instruction templates for a mnemonic name, so that
5765 later on, we can select the error that most closely describes
5767 record_operand_error (opcode
, i
, get_error_kind (),
5768 get_error_message ());
5773 DEBUG_TRACE ("parsing SUCCESS");
5778 /* It does some fix-up to provide some programmer friendly feature while
5779 keeping the libopcodes happy, i.e. libopcodes only accepts
5780 the preferred architectural syntax.
5781 Return FALSE if there is any failure; otherwise return TRUE. */
5784 programmer_friendly_fixup (aarch64_instruction
*instr
)
5786 aarch64_inst
*base
= &instr
->base
;
5787 const aarch64_opcode
*opcode
= base
->opcode
;
5788 enum aarch64_op op
= opcode
->op
;
5789 aarch64_opnd_info
*operands
= base
->operands
;
5791 DEBUG_TRACE ("enter");
5793 switch (opcode
->iclass
)
5796 /* TBNZ Xn|Wn, #uimm6, label
5797 Test and Branch Not Zero: conditionally jumps to label if bit number
5798 uimm6 in register Xn is not zero. The bit number implies the width of
5799 the register, which may be written and should be disassembled as Wn if
5800 uimm is less than 32. */
5801 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5803 if (operands
[1].imm
.value
>= 32)
5805 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5809 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5813 /* LDR Wt, label | =value
5814 As a convenience assemblers will typically permit the notation
5815 "=value" in conjunction with the pc-relative literal load instructions
5816 to automatically place an immediate value or symbolic address in a
5817 nearby literal pool and generate a hidden label which references it.
5818 ISREG has been set to 0 in the case of =value. */
5819 if (instr
->gen_lit_pool
5820 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5822 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5823 if (op
== OP_LDRSW_LIT
)
5825 if (instr
->reloc
.exp
.X_op
!= O_constant
5826 && instr
->reloc
.exp
.X_op
!= O_big
5827 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5829 record_operand_error (opcode
, 1,
5830 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5831 _("constant expression expected"));
5834 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5836 record_operand_error (opcode
, 1,
5837 AARCH64_OPDE_OTHER_ERROR
,
5838 _("literal pool insertion failed"));
5846 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5847 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5848 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5849 A programmer-friendly assembler should accept a destination Xd in
5850 place of Wd, however that is not the preferred form for disassembly.
5852 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5853 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5854 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5855 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5860 /* In the 64-bit form, the final register operand is written as Wm
5861 for all but the (possibly omitted) UXTX/LSL and SXTX
5863 As a programmer-friendly assembler, we accept e.g.
5864 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5865 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5866 int idx
= aarch64_operand_index (opcode
->operands
,
5867 AARCH64_OPND_Rm_EXT
);
5868 gas_assert (idx
== 1 || idx
== 2);
5869 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5870 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5871 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5872 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5873 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5874 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5882 DEBUG_TRACE ("exit with SUCCESS");
5886 /* Check for loads and stores that will cause unpredictable behavior. */
5889 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5891 aarch64_inst
*base
= &instr
->base
;
5892 const aarch64_opcode
*opcode
= base
->opcode
;
5893 const aarch64_opnd_info
*opnds
= base
->operands
;
5894 switch (opcode
->iclass
)
5900 /* Loading/storing the base register is unpredictable if writeback. */
5901 if ((aarch64_get_operand_class (opnds
[0].type
)
5902 == AARCH64_OPND_CLASS_INT_REG
)
5903 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5904 && opnds
[1].addr
.base_regno
!= REG_SP
5905 && opnds
[1].addr
.writeback
)
5906 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5909 case ldstnapair_offs
:
5910 case ldstpair_indexed
:
5911 /* Loading/storing the base register is unpredictable if writeback. */
5912 if ((aarch64_get_operand_class (opnds
[0].type
)
5913 == AARCH64_OPND_CLASS_INT_REG
)
5914 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5915 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5916 && opnds
[2].addr
.base_regno
!= REG_SP
5917 && opnds
[2].addr
.writeback
)
5918 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5919 /* Load operations must load different registers. */
5920 if ((opcode
->opcode
& (1 << 22))
5921 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5922 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5929 /* A wrapper function to interface with libopcodes on encoding and
5930 record the error message if there is any.
5932 Return TRUE on success; otherwise return FALSE. */
5935 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5938 aarch64_operand_error error_info
;
5939 error_info
.kind
= AARCH64_OPDE_NIL
;
5940 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5944 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5945 record_operand_error_info (opcode
, &error_info
);
5950 #ifdef DEBUG_AARCH64
5952 dump_opcode_operands (const aarch64_opcode
*opcode
)
5955 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5957 aarch64_verbose ("\t\t opnd%d: %s", i
,
5958 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5959 ? aarch64_get_operand_name (opcode
->operands
[i
])
5960 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5964 #endif /* DEBUG_AARCH64 */
5966 /* This is the guts of the machine-dependent assembler. STR points to a
5967 machine dependent instruction. This function is supposed to emit
5968 the frags/bytes it assembles to. */
5971 md_assemble (char *str
)
5974 templates
*template;
5975 aarch64_opcode
*opcode
;
5976 aarch64_inst
*inst_base
;
5977 unsigned saved_cond
;
5979 /* Align the previous label if needed. */
5980 if (last_label_seen
!= NULL
)
5982 symbol_set_frag (last_label_seen
, frag_now
);
5983 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
5984 S_SET_SEGMENT (last_label_seen
, now_seg
);
5987 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5989 DEBUG_TRACE ("\n\n");
5990 DEBUG_TRACE ("==============================");
5991 DEBUG_TRACE ("Enter md_assemble with %s", str
);
5993 template = opcode_lookup (&p
);
5996 /* It wasn't an instruction, but it might be a register alias of
5997 the form alias .req reg directive. */
5998 if (!create_register_alias (str
, p
))
5999 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6004 skip_whitespace (p
);
6007 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6008 get_mnemonic_name (str
), str
);
6012 init_operand_error_report ();
6014 /* Sections are assumed to start aligned. In executable section, there is no
6015 MAP_DATA symbol pending. So we only align the address during
6016 MAP_DATA --> MAP_INSN transition.
6017 For other sections, this is not guaranteed. */
6018 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6019 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6020 frag_align_code (2, 0);
6022 saved_cond
= inst
.cond
;
6023 reset_aarch64_instruction (&inst
);
6024 inst
.cond
= saved_cond
;
6026 /* Iterate through all opcode entries with the same mnemonic name. */
6029 opcode
= template->opcode
;
6031 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6032 #ifdef DEBUG_AARCH64
6034 dump_opcode_operands (opcode
);
6035 #endif /* DEBUG_AARCH64 */
6037 mapping_state (MAP_INSN
);
6039 inst_base
= &inst
.base
;
6040 inst_base
->opcode
= opcode
;
6042 /* Truly conditionally executed instructions, e.g. b.cond. */
6043 if (opcode
->flags
& F_COND
)
6045 gas_assert (inst
.cond
!= COND_ALWAYS
);
6046 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6047 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6049 else if (inst
.cond
!= COND_ALWAYS
)
6051 /* It shouldn't arrive here, where the assembly looks like a
6052 conditional instruction but the found opcode is unconditional. */
6057 if (parse_operands (p
, opcode
)
6058 && programmer_friendly_fixup (&inst
)
6059 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6061 /* Check that this instruction is supported for this CPU. */
6062 if (!opcode
->avariant
6063 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
6065 as_bad (_("selected processor does not support `%s'"), str
);
6069 warn_unpredictable_ldst (&inst
, str
);
6071 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6072 || !inst
.reloc
.need_libopcodes_p
)
6076 /* If there is relocation generated for the instruction,
6077 store the instruction information for the future fix-up. */
6078 struct aarch64_inst
*copy
;
6079 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6080 copy
= XNEW (struct aarch64_inst
);
6081 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6087 template = template->next
;
6088 if (template != NULL
)
6090 reset_aarch64_instruction (&inst
);
6091 inst
.cond
= saved_cond
;
6094 while (template != NULL
);
6096 /* Issue the error messages if any. */
6097 output_operand_error_report (str
);
6100 /* Various frobbings of labels and their addresses. */
6103 aarch64_start_line_hook (void)
6105 last_label_seen
= NULL
;
6109 aarch64_frob_label (symbolS
* sym
)
6111 last_label_seen
= sym
;
6113 dwarf2_emit_label (sym
);
6117 aarch64_data_in_code (void)
6119 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6121 *input_line_pointer
= '/';
6122 input_line_pointer
+= 5;
6123 *input_line_pointer
= 0;
6131 aarch64_canonicalize_symbol_name (char *name
)
6135 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6136 *(name
+ len
- 5) = 0;
6141 /* Table of all register names defined by default. The user can
6142 define additional names with .req. Note that all register names
6143 should appear in both upper and lowercase variants. Some registers
6144 also have mixed-case names. */
6146 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6147 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6148 #define REGSET31(p,t) \
6149 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6150 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6151 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6152 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
6153 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6154 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6155 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6156 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6157 #define REGSET(p,t) \
6158 REGSET31(p,t), REGNUM(p,31,t)
6160 /* These go into aarch64_reg_hsh hash-table. */
6161 static const reg_entry reg_names
[] = {
6162 /* Integer registers. */
6163 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6164 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6166 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6167 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6169 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6170 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6172 /* Coprocessor register numbers. */
6173 REGSET (c
, CN
), REGSET (C
, CN
),
6175 /* Floating-point single precision registers. */
6176 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6178 /* Floating-point double precision registers. */
6179 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6181 /* Floating-point half precision registers. */
6182 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6184 /* Floating-point byte precision registers. */
6185 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6187 /* Floating-point quad precision registers. */
6188 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6190 /* FP/SIMD registers. */
6191 REGSET (v
, VN
), REGSET (V
, VN
),
6206 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6207 static const asm_nzcv nzcv_names
[] = {
6208 {"nzcv", B (n
, z
, c
, v
)},
6209 {"nzcV", B (n
, z
, c
, V
)},
6210 {"nzCv", B (n
, z
, C
, v
)},
6211 {"nzCV", B (n
, z
, C
, V
)},
6212 {"nZcv", B (n
, Z
, c
, v
)},
6213 {"nZcV", B (n
, Z
, c
, V
)},
6214 {"nZCv", B (n
, Z
, C
, v
)},
6215 {"nZCV", B (n
, Z
, C
, V
)},
6216 {"Nzcv", B (N
, z
, c
, v
)},
6217 {"NzcV", B (N
, z
, c
, V
)},
6218 {"NzCv", B (N
, z
, C
, v
)},
6219 {"NzCV", B (N
, z
, C
, V
)},
6220 {"NZcv", B (N
, Z
, c
, v
)},
6221 {"NZcV", B (N
, Z
, c
, V
)},
6222 {"NZCv", B (N
, Z
, C
, v
)},
6223 {"NZCV", B (N
, Z
, C
, V
)}
6236 /* MD interface: bits in the object file. */
6238 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6239 for use in the a.out file, and stores them in the array pointed to by buf.
6240 This knows about the endian-ness of the target machine and does
6241 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6242 2 (short) and 4 (long) Floating numbers are put out as a series of
6243 LITTLENUMS (shorts, here at least). */
6246 md_number_to_chars (char *buf
, valueT val
, int n
)
6248 if (target_big_endian
)
6249 number_to_chars_bigendian (buf
, val
, n
);
6251 number_to_chars_littleendian (buf
, val
, n
);
6254 /* MD interface: Sections. */
6256 /* Estimate the size of a frag before relaxing. Assume everything fits in
6260 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6266 /* Round up a section size to the appropriate boundary. */
6269 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
6274 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6275 of an rs_align_code fragment.
6277 Here we fill the frag with the appropriate info for padding the
6278 output stream. The resulting frag will consist of a fixed (fr_fix)
6279 and of a repeating (fr_var) part.
6281 The fixed content is always emitted before the repeating content and
6282 these two parts are used as follows in constructing the output:
6283 - the fixed part will be used to align to a valid instruction word
6284 boundary, in case that we start at a misaligned address; as no
6285 executable instruction can live at the misaligned location, we
6286 simply fill with zeros;
6287 - the variable part will be used to cover the remaining padding and
6288 we fill using the AArch64 NOP instruction.
6290 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6291 enough storage space for up to 3 bytes for padding the back to a valid
6292 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6295 aarch64_handle_align (fragS
* fragP
)
6297 /* NOP = d503201f */
6298 /* AArch64 instructions are always little-endian. */
6299 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6301 int bytes
, fix
, noop_size
;
6304 if (fragP
->fr_type
!= rs_align_code
)
6307 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6308 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6311 gas_assert (fragP
->tc_frag_data
.recorded
);
6314 noop_size
= sizeof (aarch64_noop
);
6316 fix
= bytes
& (noop_size
- 1);
6320 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6324 fragP
->fr_fix
+= fix
;
6328 memcpy (p
, aarch64_noop
, noop_size
);
6329 fragP
->fr_var
= noop_size
;
6332 /* Perform target specific initialisation of a frag.
6333 Note - despite the name this initialisation is not done when the frag
6334 is created, but only when its type is assigned. A frag can be created
6335 and used a long time before its type is set, so beware of assuming that
6336 this initialisationis performed first. */
6340 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6341 int max_chars ATTRIBUTE_UNUSED
)
6345 #else /* OBJ_ELF is defined. */
6347 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6349 /* Record a mapping symbol for alignment frags. We will delete this
6350 later if the alignment ends up empty. */
6351 if (!fragP
->tc_frag_data
.recorded
)
6352 fragP
->tc_frag_data
.recorded
= 1;
6354 switch (fragP
->fr_type
)
6358 mapping_state_2 (MAP_DATA
, max_chars
);
6361 /* PR 20364: We can get alignment frags in code sections,
6362 so do not just assume that we should use the MAP_DATA state. */
6363 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
6366 mapping_state_2 (MAP_INSN
, max_chars
);
6373 /* Initialize the DWARF-2 unwind information for this procedure. */
6376 tc_aarch64_frame_initial_instructions (void)
6378 cfi_add_CFA_def_cfa (REG_SP
, 0);
6380 #endif /* OBJ_ELF */
6382 /* Convert REGNAME to a DWARF-2 register number. */
6385 tc_aarch64_regname_to_dw2regnum (char *regname
)
6387 const reg_entry
*reg
= parse_reg (®name
);
6393 case REG_TYPE_SP_32
:
6394 case REG_TYPE_SP_64
:
6404 return reg
->number
+ 64;
6412 /* Implement DWARF2_ADDR_SIZE. */
6415 aarch64_dwarf2_addr_size (void)
6417 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6421 return bfd_arch_bits_per_address (stdoutput
) / 8;
6424 /* MD interface: Symbol and relocation handling. */
6426 /* Return the address within the segment that a PC-relative fixup is
6427 relative to. For AArch64 PC-relative fixups applied to instructions
6428 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6431 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6433 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6435 /* If this is pc-relative and we are going to emit a relocation
6436 then we just want to put out any pipeline compensation that the linker
6437 will need. Otherwise we want to use the calculated base. */
6439 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6440 || aarch64_force_relocation (fixP
)))
6443 /* AArch64 should be consistent for all pc-relative relocations. */
6444 return base
+ AARCH64_PCREL_OFFSET
;
6447 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6448 Otherwise we have no need to default values of symbols. */
6451 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6454 if (name
[0] == '_' && name
[1] == 'G'
6455 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6459 if (symbol_find (name
))
6460 as_bad (_("GOT already in the symbol table"));
6462 GOT_symbol
= symbol_new (name
, undefined_section
,
6463 (valueT
) 0, &zero_address_frag
);
6473 /* Return non-zero if the indicated VALUE has overflowed the maximum
6474 range expressible by a unsigned number with the indicated number of
6478 unsigned_overflow (valueT value
, unsigned bits
)
6481 if (bits
>= sizeof (valueT
) * 8)
6483 lim
= (valueT
) 1 << bits
;
6484 return (value
>= lim
);
6488 /* Return non-zero if the indicated VALUE has overflowed the maximum
6489 range expressible by an signed number with the indicated number of
6493 signed_overflow (offsetT value
, unsigned bits
)
6496 if (bits
>= sizeof (offsetT
) * 8)
6498 lim
= (offsetT
) 1 << (bits
- 1);
6499 return (value
< -lim
|| value
>= lim
);
6502 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6503 unsigned immediate offset load/store instruction, try to encode it as
6504 an unscaled, 9-bit, signed immediate offset load/store instruction.
6505 Return TRUE if it is successful; otherwise return FALSE.
6507 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6508 in response to the standard LDR/STR mnemonics when the immediate offset is
6509 unambiguous, i.e. when it is negative or unaligned. */
6512 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6515 enum aarch64_op new_op
;
6516 const aarch64_opcode
*new_opcode
;
6518 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6520 switch (instr
->opcode
->op
)
6522 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6523 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6524 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6525 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6526 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6527 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6528 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6529 case OP_STR_POS
: new_op
= OP_STUR
; break;
6530 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6531 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6532 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6533 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6534 default: new_op
= OP_NIL
; break;
6537 if (new_op
== OP_NIL
)
6540 new_opcode
= aarch64_get_opcode (new_op
);
6541 gas_assert (new_opcode
!= NULL
);
6543 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6544 instr
->opcode
->op
, new_opcode
->op
);
6546 aarch64_replace_opcode (instr
, new_opcode
);
6548 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6549 qualifier matching may fail because the out-of-date qualifier will
6550 prevent the operand being updated with a new and correct qualifier. */
6551 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6552 AARCH64_OPND_ADDR_SIMM9
);
6553 gas_assert (idx
== 1);
6554 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6556 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6558 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6564 /* Called by fix_insn to fix a MOV immediate alias instruction.
6566 Operand for a generic move immediate instruction, which is an alias
6567 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6568 a 32-bit/64-bit immediate value into general register. An assembler error
6569 shall result if the immediate cannot be created by a single one of these
6570 instructions. If there is a choice, then to ensure reversability an
6571 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6574 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6576 const aarch64_opcode
*opcode
;
6578 /* Need to check if the destination is SP/ZR. The check has to be done
6579 before any aarch64_replace_opcode. */
6580 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6581 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6583 instr
->operands
[1].imm
.value
= value
;
6584 instr
->operands
[1].skip
= 0;
6588 /* Try the MOVZ alias. */
6589 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6590 aarch64_replace_opcode (instr
, opcode
);
6591 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6592 &instr
->value
, NULL
, NULL
))
6594 put_aarch64_insn (buf
, instr
->value
);
6597 /* Try the MOVK alias. */
6598 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6599 aarch64_replace_opcode (instr
, opcode
);
6600 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6601 &instr
->value
, NULL
, NULL
))
6603 put_aarch64_insn (buf
, instr
->value
);
6608 if (try_mov_bitmask_p
)
6610 /* Try the ORR alias. */
6611 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6612 aarch64_replace_opcode (instr
, opcode
);
6613 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6614 &instr
->value
, NULL
, NULL
))
6616 put_aarch64_insn (buf
, instr
->value
);
6621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6622 _("immediate cannot be moved by a single instruction"));
6625 /* An instruction operand which is immediate related may have symbol used
6626 in the assembly, e.g.
6629 .set u32, 0x00ffff00
6631 At the time when the assembly instruction is parsed, a referenced symbol,
6632 like 'u32' in the above example may not have been seen; a fixS is created
6633 in such a case and is handled here after symbols have been resolved.
6634 Instruction is fixed up with VALUE using the information in *FIXP plus
6635 extra information in FLAGS.
6637 This function is called by md_apply_fix to fix up instructions that need
6638 a fix-up described above but does not involve any linker-time relocation. */
6641 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6645 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6646 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6647 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6651 /* Now the instruction is about to be fixed-up, so the operand that
6652 was previously marked as 'ignored' needs to be unmarked in order
6653 to get the encoding done properly. */
6654 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6655 new_inst
->operands
[idx
].skip
= 0;
6658 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6662 case AARCH64_OPND_EXCEPTION
:
6663 if (unsigned_overflow (value
, 16))
6664 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6665 _("immediate out of range"));
6666 insn
= get_aarch64_insn (buf
);
6667 insn
|= encode_svc_imm (value
);
6668 put_aarch64_insn (buf
, insn
);
6671 case AARCH64_OPND_AIMM
:
6672 /* ADD or SUB with immediate.
6673 NOTE this assumes we come here with a add/sub shifted reg encoding
6674 3 322|2222|2 2 2 21111 111111
6675 1 098|7654|3 2 1 09876 543210 98765 43210
6676 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6677 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6678 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6679 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6681 3 322|2222|2 2 221111111111
6682 1 098|7654|3 2 109876543210 98765 43210
6683 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6684 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6685 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6686 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6687 Fields sf Rn Rd are already set. */
6688 insn
= get_aarch64_insn (buf
);
6692 insn
= reencode_addsub_switch_add_sub (insn
);
6696 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6697 && unsigned_overflow (value
, 12))
6699 /* Try to shift the value by 12 to make it fit. */
6700 if (((value
>> 12) << 12) == value
6701 && ! unsigned_overflow (value
, 12 + 12))
6704 insn
|= encode_addsub_imm_shift_amount (1);
6708 if (unsigned_overflow (value
, 12))
6709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6710 _("immediate out of range"));
6712 insn
|= encode_addsub_imm (value
);
6714 put_aarch64_insn (buf
, insn
);
6717 case AARCH64_OPND_SIMD_IMM
:
6718 case AARCH64_OPND_SIMD_IMM_SFT
:
6719 case AARCH64_OPND_LIMM
:
6720 /* Bit mask immediate. */
6721 gas_assert (new_inst
!= NULL
);
6722 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6723 new_inst
->operands
[idx
].imm
.value
= value
;
6724 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6725 &new_inst
->value
, NULL
, NULL
))
6726 put_aarch64_insn (buf
, new_inst
->value
);
6728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6729 _("invalid immediate"));
6732 case AARCH64_OPND_HALF
:
6733 /* 16-bit unsigned immediate. */
6734 if (unsigned_overflow (value
, 16))
6735 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6736 _("immediate out of range"));
6737 insn
= get_aarch64_insn (buf
);
6738 insn
|= encode_movw_imm (value
& 0xffff);
6739 put_aarch64_insn (buf
, insn
);
6742 case AARCH64_OPND_IMM_MOV
:
6743 /* Operand for a generic move immediate instruction, which is
6744 an alias instruction that generates a single MOVZ, MOVN or ORR
6745 instruction to loads a 32-bit/64-bit immediate value into general
6746 register. An assembler error shall result if the immediate cannot be
6747 created by a single one of these instructions. If there is a choice,
6748 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6749 and MOVZ or MOVN to ORR. */
6750 gas_assert (new_inst
!= NULL
);
6751 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6754 case AARCH64_OPND_ADDR_SIMM7
:
6755 case AARCH64_OPND_ADDR_SIMM9
:
6756 case AARCH64_OPND_ADDR_SIMM9_2
:
6757 case AARCH64_OPND_ADDR_UIMM12
:
6758 /* Immediate offset in an address. */
6759 insn
= get_aarch64_insn (buf
);
6761 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6762 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6763 || new_inst
->opcode
->operands
[2] == opnd
);
6765 /* Get the index of the address operand. */
6766 if (new_inst
->opcode
->operands
[1] == opnd
)
6767 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6770 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6773 /* Update the resolved offset value. */
6774 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6776 /* Encode/fix-up. */
6777 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6778 &new_inst
->value
, NULL
, NULL
))
6780 put_aarch64_insn (buf
, new_inst
->value
);
6783 else if (new_inst
->opcode
->iclass
== ldst_pos
6784 && try_to_encode_as_unscaled_ldst (new_inst
))
6786 put_aarch64_insn (buf
, new_inst
->value
);
6790 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6791 _("immediate offset out of range"));
6796 as_fatal (_("unhandled operand code %d"), opnd
);
6800 /* Apply a fixup (fixP) to segment data, once it has been determined
6801 by our caller that we have all the info we need to fix it up.
6803 Parameter valP is the pointer to the value of the bits. */
6806 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6808 offsetT value
= *valP
;
6810 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6812 unsigned flags
= fixP
->fx_addnumber
;
6814 DEBUG_TRACE ("\n\n");
6815 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6816 DEBUG_TRACE ("Enter md_apply_fix");
6818 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6820 /* Note whether this will delete the relocation. */
6822 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6825 /* Process the relocations. */
6826 switch (fixP
->fx_r_type
)
6828 case BFD_RELOC_NONE
:
6829 /* This will need to go in the object file. */
6834 case BFD_RELOC_8_PCREL
:
6835 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6836 md_number_to_chars (buf
, value
, 1);
6840 case BFD_RELOC_16_PCREL
:
6841 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6842 md_number_to_chars (buf
, value
, 2);
6846 case BFD_RELOC_32_PCREL
:
6847 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6848 md_number_to_chars (buf
, value
, 4);
6852 case BFD_RELOC_64_PCREL
:
6853 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6854 md_number_to_chars (buf
, value
, 8);
6857 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6858 /* We claim that these fixups have been processed here, even if
6859 in fact we generate an error because we do not have a reloc
6860 for them, so tc_gen_reloc() will reject them. */
6862 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6864 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6865 _("undefined symbol %s used as an immediate value"),
6866 S_GET_NAME (fixP
->fx_addsy
));
6867 goto apply_fix_return
;
6869 fix_insn (fixP
, flags
, value
);
6872 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6873 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6877 _("pc-relative load offset not word aligned"));
6878 if (signed_overflow (value
, 21))
6879 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6880 _("pc-relative load offset out of range"));
6881 insn
= get_aarch64_insn (buf
);
6882 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6883 put_aarch64_insn (buf
, insn
);
6887 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6888 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6890 if (signed_overflow (value
, 21))
6891 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6892 _("pc-relative address offset out of range"));
6893 insn
= get_aarch64_insn (buf
);
6894 insn
|= encode_adr_imm (value
);
6895 put_aarch64_insn (buf
, insn
);
6899 case BFD_RELOC_AARCH64_BRANCH19
:
6900 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6903 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6904 _("conditional branch target not word aligned"));
6905 if (signed_overflow (value
, 21))
6906 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6907 _("conditional branch out of range"));
6908 insn
= get_aarch64_insn (buf
);
6909 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6910 put_aarch64_insn (buf
, insn
);
6914 case BFD_RELOC_AARCH64_TSTBR14
:
6915 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6918 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6919 _("conditional branch target not word aligned"));
6920 if (signed_overflow (value
, 16))
6921 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6922 _("conditional branch out of range"));
6923 insn
= get_aarch64_insn (buf
);
6924 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6925 put_aarch64_insn (buf
, insn
);
6929 case BFD_RELOC_AARCH64_CALL26
:
6930 case BFD_RELOC_AARCH64_JUMP26
:
6931 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6935 _("branch target not word aligned"));
6936 if (signed_overflow (value
, 28))
6937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6938 _("branch out of range"));
6939 insn
= get_aarch64_insn (buf
);
6940 insn
|= encode_branch_ofs_26 (value
>> 2);
6941 put_aarch64_insn (buf
, insn
);
6945 case BFD_RELOC_AARCH64_MOVW_G0
:
6946 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6947 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6948 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6951 case BFD_RELOC_AARCH64_MOVW_G1
:
6952 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6953 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6954 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6957 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6959 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6960 /* Should always be exported to object file, see
6961 aarch64_force_relocation(). */
6962 gas_assert (!fixP
->fx_done
);
6963 gas_assert (seg
->use_rela_p
);
6965 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6967 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6968 /* Should always be exported to object file, see
6969 aarch64_force_relocation(). */
6970 gas_assert (!fixP
->fx_done
);
6971 gas_assert (seg
->use_rela_p
);
6973 case BFD_RELOC_AARCH64_MOVW_G2
:
6974 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6975 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6978 case BFD_RELOC_AARCH64_MOVW_G3
:
6981 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6983 insn
= get_aarch64_insn (buf
);
6987 /* REL signed addend must fit in 16 bits */
6988 if (signed_overflow (value
, 16))
6989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6990 _("offset out of range"));
6994 /* Check for overflow and scale. */
6995 switch (fixP
->fx_r_type
)
6997 case BFD_RELOC_AARCH64_MOVW_G0
:
6998 case BFD_RELOC_AARCH64_MOVW_G1
:
6999 case BFD_RELOC_AARCH64_MOVW_G2
:
7000 case BFD_RELOC_AARCH64_MOVW_G3
:
7001 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7002 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7003 if (unsigned_overflow (value
, scale
+ 16))
7004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7005 _("unsigned value out of range"));
7007 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7008 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7009 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7010 /* NOTE: We can only come here with movz or movn. */
7011 if (signed_overflow (value
, scale
+ 16))
7012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7013 _("signed value out of range"));
7016 /* Force use of MOVN. */
7018 insn
= reencode_movzn_to_movn (insn
);
7022 /* Force use of MOVZ. */
7023 insn
= reencode_movzn_to_movz (insn
);
7027 /* Unchecked relocations. */
7033 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7034 insn
|= encode_movw_imm (value
& 0xffff);
7036 put_aarch64_insn (buf
, insn
);
7040 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7041 fixP
->fx_r_type
= (ilp32_p
7042 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7043 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7044 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7045 /* Should always be exported to object file, see
7046 aarch64_force_relocation(). */
7047 gas_assert (!fixP
->fx_done
);
7048 gas_assert (seg
->use_rela_p
);
7051 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7052 fixP
->fx_r_type
= (ilp32_p
7053 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7054 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
7055 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7056 /* Should always be exported to object file, see
7057 aarch64_force_relocation(). */
7058 gas_assert (!fixP
->fx_done
);
7059 gas_assert (seg
->use_rela_p
);
7062 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7063 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7064 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7065 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7066 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7067 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7068 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7069 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7070 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7071 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7072 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7073 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7074 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7075 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7076 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7077 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7078 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7079 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7080 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7081 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7082 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7083 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7084 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7085 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7086 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7087 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7088 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7089 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7090 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7091 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7092 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7093 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7094 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7095 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7096 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7097 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7098 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7099 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7100 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7101 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7102 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7103 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7104 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7105 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7106 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7107 /* Should always be exported to object file, see
7108 aarch64_force_relocation(). */
7109 gas_assert (!fixP
->fx_done
);
7110 gas_assert (seg
->use_rela_p
);
7113 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7114 /* Should always be exported to object file, see
7115 aarch64_force_relocation(). */
7116 fixP
->fx_r_type
= (ilp32_p
7117 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7118 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7119 gas_assert (!fixP
->fx_done
);
7120 gas_assert (seg
->use_rela_p
);
7123 case BFD_RELOC_AARCH64_ADD_LO12
:
7124 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7125 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7126 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7127 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7128 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7129 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7130 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7131 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7132 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7133 case BFD_RELOC_AARCH64_LDST128_LO12
:
7134 case BFD_RELOC_AARCH64_LDST16_LO12
:
7135 case BFD_RELOC_AARCH64_LDST32_LO12
:
7136 case BFD_RELOC_AARCH64_LDST64_LO12
:
7137 case BFD_RELOC_AARCH64_LDST8_LO12
:
7138 /* Should always be exported to object file, see
7139 aarch64_force_relocation(). */
7140 gas_assert (!fixP
->fx_done
);
7141 gas_assert (seg
->use_rela_p
);
7144 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7145 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7146 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7149 case BFD_RELOC_UNUSED
:
7150 /* An error will already have been reported. */
7154 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7155 _("unexpected %s fixup"),
7156 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7161 /* Free the allocated the struct aarch64_inst.
7162 N.B. currently there are very limited number of fix-up types actually use
7163 this field, so the impact on the performance should be minimal . */
7164 if (fixP
->tc_fix_data
.inst
!= NULL
)
7165 free (fixP
->tc_fix_data
.inst
);
7170 /* Translate internal representation of relocation info to BFD target
7174 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7177 bfd_reloc_code_real_type code
;
7179 reloc
= XNEW (arelent
);
7181 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7182 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7183 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7187 if (section
->use_rela_p
)
7188 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7190 fixp
->fx_offset
= reloc
->address
;
7192 reloc
->addend
= fixp
->fx_offset
;
7194 code
= fixp
->fx_r_type
;
7199 code
= BFD_RELOC_16_PCREL
;
7204 code
= BFD_RELOC_32_PCREL
;
7209 code
= BFD_RELOC_64_PCREL
;
7216 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7217 if (reloc
->howto
== NULL
)
7219 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7221 ("cannot represent %s relocation in this object file format"),
7222 bfd_get_reloc_code_name (code
));
7229 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7232 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7234 bfd_reloc_code_real_type type
;
7238 FIXME: @@ Should look at CPU word size. */
7245 type
= BFD_RELOC_16
;
7248 type
= BFD_RELOC_32
;
7251 type
= BFD_RELOC_64
;
7254 as_bad (_("cannot do %u-byte relocation"), size
);
7255 type
= BFD_RELOC_UNUSED
;
7259 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7263 aarch64_force_relocation (struct fix
*fixp
)
7265 switch (fixp
->fx_r_type
)
7267 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7268 /* Perform these "immediate" internal relocations
7269 even if the symbol is extern or weak. */
7272 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7273 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7274 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7275 /* Pseudo relocs that need to be fixed up according to
7279 case BFD_RELOC_AARCH64_ADD_LO12
:
7280 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7281 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7282 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7283 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7284 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7285 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7286 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7287 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7288 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7289 case BFD_RELOC_AARCH64_LDST128_LO12
:
7290 case BFD_RELOC_AARCH64_LDST16_LO12
:
7291 case BFD_RELOC_AARCH64_LDST32_LO12
:
7292 case BFD_RELOC_AARCH64_LDST64_LO12
:
7293 case BFD_RELOC_AARCH64_LDST8_LO12
:
7294 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7295 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7296 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7297 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7298 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7299 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7300 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7301 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7302 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7303 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7304 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7305 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7306 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7307 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7308 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7309 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7310 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7311 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7312 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7313 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7314 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7315 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7316 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7317 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7318 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7319 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7320 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7321 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7322 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7323 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7324 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7325 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7326 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7327 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7328 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7329 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7330 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7331 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7332 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7333 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7334 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7335 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7336 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7337 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7338 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7339 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7340 /* Always leave these relocations for the linker. */
7347 return generic_force_reloc (fixp
);
7353 elf64_aarch64_target_format (void)
7355 if (strcmp (TARGET_OS
, "cloudabi") == 0)
7357 /* FIXME: What to do for ilp32_p ? */
7358 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7360 if (target_big_endian
)
7361 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7363 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7367 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7369 elf_frob_symbol (symp
, puntp
);
7373 /* MD interface: Finalization. */
7375 /* A good place to do this, although this was probably not intended
7376 for this kind of use. We need to dump the literal pool before
7377 references are made to a null symbol pointer. */
7380 aarch64_cleanup (void)
7384 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7386 /* Put it at the end of the relevant section. */
7387 subseg_set (pool
->section
, pool
->sub_section
);
7393 /* Remove any excess mapping symbols generated for alignment frags in
7394 SEC. We may have created a mapping symbol before a zero byte
7395 alignment; remove it if there's a mapping symbol after the
7398 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7399 void *dummy ATTRIBUTE_UNUSED
)
7401 segment_info_type
*seginfo
= seg_info (sec
);
7404 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7407 for (fragp
= seginfo
->frchainP
->frch_root
;
7408 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7410 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7411 fragS
*next
= fragp
->fr_next
;
7413 /* Variable-sized frags have been converted to fixed size by
7414 this point. But if this was variable-sized to start with,
7415 there will be a fixed-size frag after it. So don't handle
7417 if (sym
== NULL
|| next
== NULL
)
7420 if (S_GET_VALUE (sym
) < next
->fr_address
)
7421 /* Not at the end of this frag. */
7423 know (S_GET_VALUE (sym
) == next
->fr_address
);
7427 if (next
->tc_frag_data
.first_map
!= NULL
)
7429 /* Next frag starts with a mapping symbol. Discard this
7431 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7435 if (next
->fr_next
== NULL
)
7437 /* This mapping symbol is at the end of the section. Discard
7439 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7440 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7444 /* As long as we have empty frags without any mapping symbols,
7446 /* If the next frag is non-empty and does not start with a
7447 mapping symbol, then this mapping symbol is required. */
7448 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7451 next
= next
->fr_next
;
7453 while (next
!= NULL
);
7458 /* Adjust the symbol table. */
7461 aarch64_adjust_symtab (void)
7464 /* Remove any overlapping mapping symbols generated by alignment frags. */
7465 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7466 /* Now do generic ELF adjustments. */
7467 elf_adjust_symtab ();
7472 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7474 const char *hash_err
;
7476 hash_err
= hash_insert (table
, key
, value
);
7478 printf ("Internal Error: Can't hash %s\n", key
);
7482 fill_instruction_hash_table (void)
7484 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7486 while (opcode
->name
!= NULL
)
7488 templates
*templ
, *new_templ
;
7489 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7491 new_templ
= XNEW (templates
);
7492 new_templ
->opcode
= opcode
;
7493 new_templ
->next
= NULL
;
7496 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7499 new_templ
->next
= templ
->next
;
7500 templ
->next
= new_templ
;
7507 convert_to_upper (char *dst
, const char *src
, size_t num
)
7510 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7511 *dst
= TOUPPER (*src
);
7515 /* Assume STR point to a lower-case string, allocate, convert and return
7516 the corresponding upper-case string. */
7517 static inline const char*
7518 get_upper_str (const char *str
)
7521 size_t len
= strlen (str
);
7522 ret
= XNEWVEC (char, len
+ 1);
7523 convert_to_upper (ret
, str
, len
);
7527 /* MD interface: Initialization. */
7535 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7536 || (aarch64_cond_hsh
= hash_new ()) == NULL
7537 || (aarch64_shift_hsh
= hash_new ()) == NULL
7538 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7539 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7540 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7541 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7542 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7543 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7544 || (aarch64_reg_hsh
= hash_new ()) == NULL
7545 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7546 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7547 || (aarch64_pldop_hsh
= hash_new ()) == NULL
7548 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
7549 as_fatal (_("virtual memory exhausted"));
7551 fill_instruction_hash_table ();
7553 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7554 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7555 (void *) (aarch64_sys_regs
+ i
));
7557 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7558 checked_hash_insert (aarch64_pstatefield_hsh
,
7559 aarch64_pstatefields
[i
].name
,
7560 (void *) (aarch64_pstatefields
+ i
));
7562 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
7563 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7564 aarch64_sys_regs_ic
[i
].name
,
7565 (void *) (aarch64_sys_regs_ic
+ i
));
7567 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
7568 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7569 aarch64_sys_regs_dc
[i
].name
,
7570 (void *) (aarch64_sys_regs_dc
+ i
));
7572 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
7573 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7574 aarch64_sys_regs_at
[i
].name
,
7575 (void *) (aarch64_sys_regs_at
+ i
));
7577 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
7578 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7579 aarch64_sys_regs_tlbi
[i
].name
,
7580 (void *) (aarch64_sys_regs_tlbi
+ i
));
7582 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7583 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7584 (void *) (reg_names
+ i
));
7586 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7587 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7588 (void *) (nzcv_names
+ i
));
7590 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7592 const char *name
= aarch64_operand_modifiers
[i
].name
;
7593 checked_hash_insert (aarch64_shift_hsh
, name
,
7594 (void *) (aarch64_operand_modifiers
+ i
));
7595 /* Also hash the name in the upper case. */
7596 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7597 (void *) (aarch64_operand_modifiers
+ i
));
7600 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7603 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7604 the same condition code. */
7605 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7607 const char *name
= aarch64_conds
[i
].names
[j
];
7610 checked_hash_insert (aarch64_cond_hsh
, name
,
7611 (void *) (aarch64_conds
+ i
));
7612 /* Also hash the name in the upper case. */
7613 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7614 (void *) (aarch64_conds
+ i
));
7618 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7620 const char *name
= aarch64_barrier_options
[i
].name
;
7621 /* Skip xx00 - the unallocated values of option. */
7624 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7625 (void *) (aarch64_barrier_options
+ i
));
7626 /* Also hash the name in the upper case. */
7627 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7628 (void *) (aarch64_barrier_options
+ i
));
7631 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7633 const char* name
= aarch64_prfops
[i
].name
;
7634 /* Skip the unallocated hint encodings. */
7637 checked_hash_insert (aarch64_pldop_hsh
, name
,
7638 (void *) (aarch64_prfops
+ i
));
7639 /* Also hash the name in the upper case. */
7640 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7641 (void *) (aarch64_prfops
+ i
));
7644 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
7646 const char* name
= aarch64_hint_options
[i
].name
;
7648 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
7649 (void *) (aarch64_hint_options
+ i
));
7650 /* Also hash the name in the upper case. */
7651 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7652 (void *) (aarch64_hint_options
+ i
));
7655 /* Set the cpu variant based on the command-line options. */
7657 mcpu_cpu_opt
= march_cpu_opt
;
7660 mcpu_cpu_opt
= &cpu_default
;
7662 cpu_variant
= *mcpu_cpu_opt
;
7664 /* Record the CPU type. */
7665 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7667 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7670 /* Command line processing. */
7672 const char *md_shortopts
= "m:";
7674 #ifdef AARCH64_BI_ENDIAN
7675 #define OPTION_EB (OPTION_MD_BASE + 0)
7676 #define OPTION_EL (OPTION_MD_BASE + 1)
7678 #if TARGET_BYTES_BIG_ENDIAN
7679 #define OPTION_EB (OPTION_MD_BASE + 0)
7681 #define OPTION_EL (OPTION_MD_BASE + 1)
7685 struct option md_longopts
[] = {
7687 {"EB", no_argument
, NULL
, OPTION_EB
},
7690 {"EL", no_argument
, NULL
, OPTION_EL
},
7692 {NULL
, no_argument
, NULL
, 0}
7695 size_t md_longopts_size
= sizeof (md_longopts
);
7697 struct aarch64_option_table
7699 const char *option
; /* Option name to match. */
7700 const char *help
; /* Help information. */
7701 int *var
; /* Variable to change. */
7702 int value
; /* What to change it to. */
7703 char *deprecated
; /* If non-null, print this message. */
7706 static struct aarch64_option_table aarch64_opts
[] = {
7707 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7708 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7710 #ifdef DEBUG_AARCH64
7711 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7712 #endif /* DEBUG_AARCH64 */
7713 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7715 {"mno-verbose-error", N_("do not output verbose error messages"),
7716 &verbose_error_p
, 0, NULL
},
7717 {NULL
, NULL
, NULL
, 0, NULL
}
7720 struct aarch64_cpu_option_table
7723 const aarch64_feature_set value
;
7724 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7726 const char *canonical_name
;
7729 /* This list should, at a minimum, contain all the cpu names
7730 recognized by GCC. */
7731 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7732 {"all", AARCH64_ANY
, NULL
},
7733 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7734 AARCH64_FEATURE_CRC
), "Cortex-A35"},
7735 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7736 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7737 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7738 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7739 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7740 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7741 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7742 AARCH64_FEATURE_CRC
), "Cortex-A73"},
7743 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7744 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7745 "Samsung Exynos M1"},
7746 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7747 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7748 "Qualcomm QDF24XX"},
7749 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7750 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7752 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
7753 AARCH64_FEATURE_CRYPTO
),
7755 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7756 in earlier releases and is superseded by 'xgene1' in all
7758 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7759 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7760 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7761 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7762 {"generic", AARCH64_ARCH_V8
, NULL
},
7764 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7767 struct aarch64_arch_option_table
7770 const aarch64_feature_set value
;
7773 /* This list should, at a minimum, contain all the architecture names
7774 recognized by GCC. */
7775 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7776 {"all", AARCH64_ANY
},
7777 {"armv8-a", AARCH64_ARCH_V8
},
7778 {"armv8.1-a", AARCH64_ARCH_V8_1
},
7779 {"armv8.2-a", AARCH64_ARCH_V8_2
},
7780 {NULL
, AARCH64_ARCH_NONE
}
7783 /* ISA extensions. */
7784 struct aarch64_option_cpu_value_table
7787 const aarch64_feature_set value
;
7788 const aarch64_feature_set require
; /* Feature dependencies. */
7791 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7792 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
7794 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
7796 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
7798 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
7800 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
7802 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
7804 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
7806 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
7808 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
7809 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7810 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
7811 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7812 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
7814 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
7817 struct aarch64_long_option_table
7819 const char *option
; /* Substring to match. */
7820 const char *help
; /* Help information. */
7821 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
7822 char *deprecated
; /* If non-null, print this message. */
7825 /* Transitive closure of features depending on set. */
7826 static aarch64_feature_set
7827 aarch64_feature_disable_set (aarch64_feature_set set
)
7829 const struct aarch64_option_cpu_value_table
*opt
;
7830 aarch64_feature_set prev
= 0;
7832 while (prev
!= set
) {
7834 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7835 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
7836 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
7841 /* Transitive closure of dependencies of set. */
7842 static aarch64_feature_set
7843 aarch64_feature_enable_set (aarch64_feature_set set
)
7845 const struct aarch64_option_cpu_value_table
*opt
;
7846 aarch64_feature_set prev
= 0;
7848 while (prev
!= set
) {
7850 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7851 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
7852 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
7858 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
7859 bfd_boolean ext_only
)
7861 /* We insist on extensions being added before being removed. We achieve
7862 this by using the ADDING_VALUE variable to indicate whether we are
7863 adding an extension (1) or removing it (0) and only allowing it to
7864 change in the order -1 -> 1 -> 0. */
7865 int adding_value
= -1;
7866 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
7868 /* Copy the feature set, so that we can modify it. */
7872 while (str
!= NULL
&& *str
!= 0)
7874 const struct aarch64_option_cpu_value_table
*opt
;
7875 const char *ext
= NULL
;
7882 as_bad (_("invalid architectural extension"));
7886 ext
= strchr (++str
, '+');
7892 optlen
= strlen (str
);
7894 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7896 if (adding_value
!= 0)
7901 else if (optlen
> 0)
7903 if (adding_value
== -1)
7905 else if (adding_value
!= 1)
7907 as_bad (_("must specify extensions to add before specifying "
7908 "those to remove"));
7915 as_bad (_("missing architectural extension"));
7919 gas_assert (adding_value
!= -1);
7921 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7922 if (strncmp (opt
->name
, str
, optlen
) == 0)
7924 aarch64_feature_set set
;
7926 /* Add or remove the extension. */
7929 set
= aarch64_feature_enable_set (opt
->value
);
7930 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
7934 set
= aarch64_feature_disable_set (opt
->value
);
7935 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
7940 if (opt
->name
== NULL
)
7942 as_bad (_("unknown architectural extension `%s'"), str
);
7953 aarch64_parse_cpu (const char *str
)
7955 const struct aarch64_cpu_option_table
*opt
;
7956 const char *ext
= strchr (str
, '+');
7962 optlen
= strlen (str
);
7966 as_bad (_("missing cpu name `%s'"), str
);
7970 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7971 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7973 mcpu_cpu_opt
= &opt
->value
;
7975 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7980 as_bad (_("unknown cpu `%s'"), str
);
7985 aarch64_parse_arch (const char *str
)
7987 const struct aarch64_arch_option_table
*opt
;
7988 const char *ext
= strchr (str
, '+');
7994 optlen
= strlen (str
);
7998 as_bad (_("missing architecture name `%s'"), str
);
8002 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
8003 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8005 march_cpu_opt
= &opt
->value
;
8007 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
8012 as_bad (_("unknown architecture `%s'\n"), str
);
8017 struct aarch64_option_abi_value_table
8020 enum aarch64_abi_type value
;
8023 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
8024 {"ilp32", AARCH64_ABI_ILP32
},
8025 {"lp64", AARCH64_ABI_LP64
},
8029 aarch64_parse_abi (const char *str
)
8035 as_bad (_("missing abi name `%s'"), str
);
8039 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
8040 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
8042 aarch64_abi
= aarch64_abis
[i
].value
;
8046 as_bad (_("unknown abi `%s'\n"), str
);
8050 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8052 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8053 aarch64_parse_abi
, NULL
},
8054 #endif /* OBJ_ELF */
8055 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8056 aarch64_parse_cpu
, NULL
},
8057 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8058 aarch64_parse_arch
, NULL
},
8059 {NULL
, NULL
, 0, NULL
}
8063 md_parse_option (int c
, const char *arg
)
8065 struct aarch64_option_table
*opt
;
8066 struct aarch64_long_option_table
*lopt
;
8072 target_big_endian
= 1;
8078 target_big_endian
= 0;
8083 /* Listing option. Just ignore these, we don't support additional
8088 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8090 if (c
== opt
->option
[0]
8091 && ((arg
== NULL
&& opt
->option
[1] == 0)
8092 || streq (arg
, opt
->option
+ 1)))
8094 /* If the option is deprecated, tell the user. */
8095 if (opt
->deprecated
!= NULL
)
8096 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8097 arg
? arg
: "", _(opt
->deprecated
));
8099 if (opt
->var
!= NULL
)
8100 *opt
->var
= opt
->value
;
8106 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8108 /* These options are expected to have an argument. */
8109 if (c
== lopt
->option
[0]
8111 && strncmp (arg
, lopt
->option
+ 1,
8112 strlen (lopt
->option
+ 1)) == 0)
8114 /* If the option is deprecated, tell the user. */
8115 if (lopt
->deprecated
!= NULL
)
8116 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8117 _(lopt
->deprecated
));
8119 /* Call the sup-option parser. */
8120 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8131 md_show_usage (FILE * fp
)
8133 struct aarch64_option_table
*opt
;
8134 struct aarch64_long_option_table
*lopt
;
8136 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8138 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8139 if (opt
->help
!= NULL
)
8140 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8142 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8143 if (lopt
->help
!= NULL
)
8144 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
8148 -EB assemble code for a big-endian cpu\n"));
8153 -EL assemble code for a little-endian cpu\n"));
8157 /* Parse a .cpu directive. */
8160 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
8162 const struct aarch64_cpu_option_table
*opt
;
8168 name
= input_line_pointer
;
8169 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8170 input_line_pointer
++;
8171 saved_char
= *input_line_pointer
;
8172 *input_line_pointer
= 0;
8174 ext
= strchr (name
, '+');
8177 optlen
= ext
- name
;
8179 optlen
= strlen (name
);
8181 /* Skip the first "all" entry. */
8182 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
8183 if (strlen (opt
->name
) == optlen
8184 && strncmp (name
, opt
->name
, optlen
) == 0)
8186 mcpu_cpu_opt
= &opt
->value
;
8188 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8191 cpu_variant
= *mcpu_cpu_opt
;
8193 *input_line_pointer
= saved_char
;
8194 demand_empty_rest_of_line ();
8197 as_bad (_("unknown cpu `%s'"), name
);
8198 *input_line_pointer
= saved_char
;
8199 ignore_rest_of_line ();
8203 /* Parse a .arch directive. */
8206 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
8208 const struct aarch64_arch_option_table
*opt
;
8214 name
= input_line_pointer
;
8215 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8216 input_line_pointer
++;
8217 saved_char
= *input_line_pointer
;
8218 *input_line_pointer
= 0;
8220 ext
= strchr (name
, '+');
8223 optlen
= ext
- name
;
8225 optlen
= strlen (name
);
8227 /* Skip the first "all" entry. */
8228 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
8229 if (strlen (opt
->name
) == optlen
8230 && strncmp (name
, opt
->name
, optlen
) == 0)
8232 mcpu_cpu_opt
= &opt
->value
;
8234 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8237 cpu_variant
= *mcpu_cpu_opt
;
8239 *input_line_pointer
= saved_char
;
8240 demand_empty_rest_of_line ();
8244 as_bad (_("unknown architecture `%s'\n"), name
);
8245 *input_line_pointer
= saved_char
;
8246 ignore_rest_of_line ();
8249 /* Parse a .arch_extension directive. */
8252 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
8255 char *ext
= input_line_pointer
;;
8257 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8258 input_line_pointer
++;
8259 saved_char
= *input_line_pointer
;
8260 *input_line_pointer
= 0;
8262 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
8265 cpu_variant
= *mcpu_cpu_opt
;
8267 *input_line_pointer
= saved_char
;
8268 demand_empty_rest_of_line ();
8271 /* Copy symbol information. */
8274 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
8276 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);