1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2023 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
35 #include "gen-sframe.h"
38 #include "dw2gencfi.h"
39 #include "dwarf2dbg.h"
41 /* Types of processor to assemble for. */
43 #define CPU_DEFAULT AARCH64_ARCH_V8
46 #define streq(a, b) (strcmp (a, b) == 0)
48 #define END_OF_INSN '\0'
50 static aarch64_feature_set cpu_variant
;
52 /* Variables that we set while parsing command-line options. Once all
53 options have been read we re-process these values to set the real
55 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
56 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
58 /* Constants for known architecture features. */
59 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
61 /* Currently active instruction sequence. */
62 static aarch64_instr_sequence
*insn_sequence
= NULL
;
65 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
66 static symbolS
*GOT_symbol
;
69 /* Which ABI to use. */
74 AARCH64_ABI_ILP32
= 2,
78 unsigned int aarch64_sframe_cfa_sp_reg
;
79 /* The other CFA base register for SFrame stack trace info. */
80 unsigned int aarch64_sframe_cfa_fp_reg
;
81 unsigned int aarch64_sframe_cfa_ra_reg
;
84 #define DEFAULT_ARCH "aarch64"
88 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
89 static const char *default_arch
= DEFAULT_ARCH
;
92 /* AArch64 ABI for the output file. */
93 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
95 /* When non-zero, program to a 32-bit model, in which the C data types
96 int, long and all pointer types are 32-bit objects (ILP32); or to a
97 64-bit model, in which the C int type is 32-bits but the C long type
98 and all pointer types are 64-bit objects (LP64). */
99 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
101 /* When non zero, C types int and long are 32 bit,
102 pointers, however are 64 bit */
103 #define llp64_p (aarch64_abi == AARCH64_ABI_LLP64)
117 /* SME horizontal or vertical slice indicator, encoded in "V".
128 /* Bits for DEFINED field in vector_type_el. */
129 #define NTA_HASTYPE 1
130 #define NTA_HASINDEX 2
131 #define NTA_HASVARWIDTH 4
133 struct vector_type_el
135 enum vector_el_type type
;
136 unsigned char defined
;
141 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
145 bfd_reloc_code_real_type type
;
148 enum aarch64_opnd opnd
;
150 unsigned need_libopcodes_p
: 1;
153 struct aarch64_instruction
155 /* libopcodes structure for instruction intermediate representation. */
157 /* Record assembly errors found during the parsing. */
158 aarch64_operand_error parsing_error
;
159 /* The condition that appears in the assembly line. */
161 /* Relocation information (including the GAS internal fixup). */
163 /* Need to generate an immediate in the literal pool. */
164 unsigned gen_lit_pool
: 1;
167 typedef struct aarch64_instruction aarch64_instruction
;
169 static aarch64_instruction inst
;
171 static bool parse_operands (char *, const aarch64_opcode
*);
172 static bool programmer_friendly_fixup (aarch64_instruction
*);
174 /* Diagnostics inline function utilities.
176 These are lightweight utilities which should only be called by parse_operands
177 and other parsers. GAS processes each assembly line by parsing it against
178 instruction template(s), in the case of multiple templates (for the same
179 mnemonic name), those templates are tried one by one until one succeeds or
180 all fail. An assembly line may fail a few templates before being
181 successfully parsed; an error saved here in most cases is not a user error
182 but an error indicating the current template is not the right template.
183 Therefore it is very important that errors can be saved at a low cost during
184 the parsing; we don't want to slow down the whole parsing by recording
185 non-user errors in detail.
187 Remember that the objective is to help GAS pick up the most appropriate
188 error message in the case of multiple templates, e.g. FMOV which has 8
194 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
195 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
201 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
205 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
207 memset (&inst
.parsing_error
, 0, sizeof (inst
.parsing_error
));
208 inst
.parsing_error
.index
= -1;
209 inst
.parsing_error
.kind
= kind
;
210 inst
.parsing_error
.error
= error
;
214 set_recoverable_error (const char *error
)
216 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
219 /* Use the DESC field of the corresponding aarch64_operand entry to compose
220 the error message. */
222 set_default_error (void)
224 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
228 set_syntax_error (const char *error
)
230 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
234 set_first_syntax_error (const char *error
)
237 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
241 set_fatal_syntax_error (const char *error
)
243 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
246 /* Return value for certain parsers when the parsing fails; those parsers
247 return the information of the parsed result, e.g. register number, on
249 #define PARSE_FAIL -1
251 /* This is an invalid condition code that means no conditional field is
253 #define COND_ALWAYS 0x10
257 const char *template;
264 bfd_reloc_code_real_type reloc
;
267 /* Macros to define the register types and masks for the purpose
270 #undef AARCH64_REG_TYPES
271 #define AARCH64_REG_TYPES \
272 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
273 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
274 BASIC_REG_TYPE(SP_32) /* wsp */ \
275 BASIC_REG_TYPE(SP_64) /* sp */ \
276 BASIC_REG_TYPE(Z_32) /* wzr */ \
277 BASIC_REG_TYPE(Z_64) /* xzr */ \
278 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
279 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
280 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
281 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
282 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
283 BASIC_REG_TYPE(VN) /* v[0-31] */ \
284 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
285 BASIC_REG_TYPE(PN) /* p[0-15] */ \
286 BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
287 BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
288 BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
289 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
290 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
291 /* Typecheck: same, plus SVE registers. */ \
292 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
294 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
295 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
296 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
297 /* Typecheck: same, plus SVE registers. */ \
298 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
299 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
301 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
302 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
303 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
304 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
305 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
306 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
307 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
308 /* Typecheck: any [BHSDQ]P FP. */ \
309 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
310 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
311 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
312 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
313 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
314 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
315 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
316 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
317 be used for SVE instructions, since Zn and Pn are valid symbols \
318 in other contexts. */ \
319 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
320 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
321 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
322 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
323 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
324 | REG_TYPE(ZN) | REG_TYPE(PN)) \
325 /* Any integer register; used for error messages only. */ \
326 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
327 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
328 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
329 /* A horizontal or vertical slice of a ZA tile. */ \
330 MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV)) \
331 /* Pseudo type to mark the end of the enumerator sequence. */ \
334 #undef BASIC_REG_TYPE
335 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
336 #undef MULTI_REG_TYPE
337 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
339 /* Register type enumerators. */
340 typedef enum aarch64_reg_type_
342 /* A list of REG_TYPE_*. */
346 #undef BASIC_REG_TYPE
347 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
349 #define REG_TYPE(T) (1 << REG_TYPE_##T)
350 #undef MULTI_REG_TYPE
351 #define MULTI_REG_TYPE(T,V) V,
353 /* Structure for a hash table entry for a register. */
357 unsigned char number
;
358 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
359 unsigned char builtin
;
362 /* Values indexed by aarch64_reg_type to assist the type checking. */
363 static const unsigned reg_type_masks
[] =
368 #undef BASIC_REG_TYPE
370 #undef MULTI_REG_TYPE
371 #undef AARCH64_REG_TYPES
373 /* Diagnostics used when we don't get a register of the expected type.
374 Note: this has to synchronized with aarch64_reg_type definitions
377 get_reg_expected_msg (aarch64_reg_type reg_type
)
384 msg
= N_("integer 32-bit register expected");
387 msg
= N_("integer 64-bit register expected");
390 msg
= N_("integer register expected");
392 case REG_TYPE_R64_SP
:
393 msg
= N_("64-bit integer or SP register expected");
395 case REG_TYPE_SVE_BASE
:
396 msg
= N_("base register expected");
399 msg
= N_("integer or zero register expected");
401 case REG_TYPE_SVE_OFFSET
:
402 msg
= N_("offset register expected");
405 msg
= N_("integer or SP register expected");
407 case REG_TYPE_R_Z_SP
:
408 msg
= N_("integer, zero or SP register expected");
411 msg
= N_("8-bit SIMD scalar register expected");
414 msg
= N_("16-bit SIMD scalar or floating-point half precision "
415 "register expected");
418 msg
= N_("32-bit SIMD scalar or floating-point single precision "
419 "register expected");
422 msg
= N_("64-bit SIMD scalar or floating-point double precision "
423 "register expected");
426 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
427 "register expected");
429 case REG_TYPE_R_Z_BHSDQ_V
:
430 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
431 msg
= N_("register expected");
433 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
434 msg
= N_("SIMD scalar or floating-point register expected");
436 case REG_TYPE_VN
: /* any V reg */
437 msg
= N_("vector register expected");
440 msg
= N_("SVE vector register expected");
443 msg
= N_("SVE predicate register expected");
446 as_fatal (_("invalid register type %d"), reg_type
);
451 /* Some well known registers that we refer to directly elsewhere. */
455 /* Instructions take 4 bytes in the object file. */
458 static htab_t aarch64_ops_hsh
;
459 static htab_t aarch64_cond_hsh
;
460 static htab_t aarch64_shift_hsh
;
461 static htab_t aarch64_sys_regs_hsh
;
462 static htab_t aarch64_pstatefield_hsh
;
463 static htab_t aarch64_sys_regs_ic_hsh
;
464 static htab_t aarch64_sys_regs_dc_hsh
;
465 static htab_t aarch64_sys_regs_at_hsh
;
466 static htab_t aarch64_sys_regs_tlbi_hsh
;
467 static htab_t aarch64_sys_regs_sr_hsh
;
468 static htab_t aarch64_reg_hsh
;
469 static htab_t aarch64_barrier_opt_hsh
;
470 static htab_t aarch64_nzcv_hsh
;
471 static htab_t aarch64_pldop_hsh
;
472 static htab_t aarch64_hint_opt_hsh
;
474 /* Stuff needed to resolve the label ambiguity
483 static symbolS
*last_label_seen
;
485 /* Literal pool structure. Held on a per-section
486 and per-sub-section basis. */
488 #define MAX_LITERAL_POOL_SIZE 1024
489 typedef struct literal_expression
492 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
493 LITTLENUM_TYPE
* bignum
;
494 } literal_expression
;
496 typedef struct literal_pool
498 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
499 unsigned int next_free_entry
;
505 struct literal_pool
*next
;
508 /* Pointer to a linked list of literal pools. */
509 static literal_pool
*list_of_pools
= NULL
;
513 /* This array holds the chars that always start a comment. If the
514 pre-processor is disabled, these aren't very useful. */
515 const char comment_chars
[] = "";
517 /* This array holds the chars that only start a comment at the beginning of
518 a line. If the line seems to have the form '# 123 filename'
519 .line and .file directives will appear in the pre-processed output. */
520 /* Note that input_file.c hand checks for '#' at the beginning of the
521 first line of the input file. This is because the compiler outputs
522 #NO_APP at the beginning of its output. */
523 /* Also note that comments like this one will always work. */
524 const char line_comment_chars
[] = "#";
526 const char line_separator_chars
[] = ";";
528 /* Chars that can be used to separate mant
529 from exp in floating point numbers. */
530 const char EXP_CHARS
[] = "eE";
532 /* Chars that mean this number is a floating point constant. */
536 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
538 /* Prefix character that indicates the start of an immediate value. */
539 #define is_immediate_prefix(C) ((C) == '#')
541 /* Separator character handling. */
543 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
546 skip_past_char (char **str
, char c
)
557 #define skip_past_comma(str) skip_past_char (str, ',')
559 /* Arithmetic expressions (possibly involving symbols). */
561 static bool in_aarch64_get_expression
= false;
563 /* Third argument to aarch64_get_expression. */
564 #define GE_NO_PREFIX false
565 #define GE_OPT_PREFIX true
567 /* Fourth argument to aarch64_get_expression. */
568 #define ALLOW_ABSENT false
569 #define REJECT_ABSENT true
571 /* Return TRUE if the string pointed by *STR is successfully parsed
572 as an valid expression; *EP will be filled with the information of
573 such an expression. Otherwise return FALSE.
575 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
576 If REJECT_ABSENT is true then trat missing expressions as an error. */
579 aarch64_get_expression (expressionS
* ep
,
581 bool allow_immediate_prefix
,
586 bool prefix_present
= false;
588 if (allow_immediate_prefix
)
590 if (is_immediate_prefix (**str
))
593 prefix_present
= true;
597 memset (ep
, 0, sizeof (expressionS
));
599 save_in
= input_line_pointer
;
600 input_line_pointer
= *str
;
601 in_aarch64_get_expression
= true;
602 seg
= expression (ep
);
603 in_aarch64_get_expression
= false;
605 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
607 /* We found a bad expression in md_operand(). */
608 *str
= input_line_pointer
;
609 input_line_pointer
= save_in
;
610 if (prefix_present
&& ! error_p ())
611 set_fatal_syntax_error (_("bad expression"));
613 set_first_syntax_error (_("bad expression"));
618 if (seg
!= absolute_section
619 && seg
!= text_section
620 && seg
!= data_section
621 && seg
!= bss_section
622 && seg
!= undefined_section
)
624 set_syntax_error (_("bad segment"));
625 *str
= input_line_pointer
;
626 input_line_pointer
= save_in
;
633 *str
= input_line_pointer
;
634 input_line_pointer
= save_in
;
638 /* Turn a string in input_line_pointer into a floating point constant
639 of type TYPE, and store the appropriate bytes in *LITP. The number
640 of LITTLENUMS emitted is stored in *SIZEP. An error message is
641 returned, or NULL on OK. */
644 md_atof (int type
, char *litP
, int *sizeP
)
646 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
649 /* We handle all bad expressions here, so that we can report the faulty
650 instruction in the error message. */
652 md_operand (expressionS
* exp
)
654 if (in_aarch64_get_expression
)
655 exp
->X_op
= O_illegal
;
658 /* Immediate values. */
660 /* Errors may be set multiple times during parsing or bit encoding
661 (particularly in the Neon bits), but usually the earliest error which is set
662 will be the most meaningful. Avoid overwriting it with later (cascading)
663 errors by calling this function. */
666 first_error (const char *error
)
669 set_syntax_error (error
);
672 /* Similar to first_error, but this function accepts formatted error
675 first_error_fmt (const char *format
, ...)
680 /* N.B. this single buffer will not cause error messages for different
681 instructions to pollute each other; this is because at the end of
682 processing of each assembly line, error message if any will be
683 collected by as_bad. */
684 static char buffer
[size
];
688 int ret ATTRIBUTE_UNUSED
;
689 va_start (args
, format
);
690 ret
= vsnprintf (buffer
, size
, format
, args
);
691 know (ret
<= size
- 1 && ret
>= 0);
693 set_syntax_error (buffer
);
697 /* Internal helper routine converting a vector_type_el structure *VECTYPE
698 to a corresponding operand qualifier. */
700 static inline aarch64_opnd_qualifier_t
701 vectype_to_qualifier (const struct vector_type_el
*vectype
)
703 /* Element size in bytes indexed by vector_el_type. */
704 const unsigned char ele_size
[5]
706 const unsigned int ele_base
[5] =
708 AARCH64_OPND_QLF_V_4B
,
709 AARCH64_OPND_QLF_V_2H
,
710 AARCH64_OPND_QLF_V_2S
,
711 AARCH64_OPND_QLF_V_1D
,
712 AARCH64_OPND_QLF_V_1Q
715 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
716 goto vectype_conversion_fail
;
718 if (vectype
->type
== NT_zero
)
719 return AARCH64_OPND_QLF_P_Z
;
720 if (vectype
->type
== NT_merge
)
721 return AARCH64_OPND_QLF_P_M
;
723 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
725 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
727 /* Special case S_4B. */
728 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
729 return AARCH64_OPND_QLF_S_4B
;
731 /* Special case S_2H. */
732 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
733 return AARCH64_OPND_QLF_S_2H
;
735 /* Vector element register. */
736 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
740 /* Vector register. */
741 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
744 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
745 goto vectype_conversion_fail
;
747 /* The conversion is by calculating the offset from the base operand
748 qualifier for the vector type. The operand qualifiers are regular
749 enough that the offset can established by shifting the vector width by
750 a vector-type dependent amount. */
752 if (vectype
->type
== NT_b
)
754 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
756 else if (vectype
->type
>= NT_d
)
761 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
762 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
763 && offset
<= AARCH64_OPND_QLF_V_1Q
);
767 vectype_conversion_fail
:
768 first_error (_("bad vector arrangement type"));
769 return AARCH64_OPND_QLF_NIL
;
772 /* Register parsing. */
774 /* Generic register parser which is called by other specialized
776 CCP points to what should be the beginning of a register name.
777 If it is indeed a valid register name, advance CCP over it and
778 return the reg_entry structure; otherwise return NULL.
779 It does not issue diagnostics. */
782 parse_reg (char **ccp
)
788 #ifdef REGISTER_PREFIX
789 if (*start
!= REGISTER_PREFIX
)
795 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
800 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
802 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
811 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
814 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
816 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
819 /* Try to parse a base or offset register. Allow SVE base and offset
820 registers if REG_TYPE includes SVE registers. Return the register
821 entry on success, setting *QUALIFIER to the register qualifier.
822 Return null otherwise.
824 Note that this function does not issue any diagnostics. */
826 static const reg_entry
*
827 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
828 aarch64_opnd_qualifier_t
*qualifier
)
831 const reg_entry
*reg
= parse_reg (&str
);
841 *qualifier
= AARCH64_OPND_QLF_W
;
847 *qualifier
= AARCH64_OPND_QLF_X
;
851 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
854 switch (TOLOWER (str
[1]))
857 *qualifier
= AARCH64_OPND_QLF_S_S
;
860 *qualifier
= AARCH64_OPND_QLF_S_D
;
877 /* Try to parse a base or offset register. Return the register entry
878 on success, setting *QUALIFIER to the register qualifier. Return null
881 Note that this function does not issue any diagnostics. */
883 static const reg_entry
*
884 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
886 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
889 /* Parse the qualifier of a vector register or vector element of type
890 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
891 succeeds; otherwise return FALSE.
893 Accept only one occurrence of:
894 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
897 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
898 struct vector_type_el
*parsed_type
, char **str
)
902 unsigned element_size
;
903 enum vector_el_type type
;
906 gas_assert (*ptr
== '.');
909 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
914 width
= strtoul (ptr
, &ptr
, 10);
915 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
917 first_error_fmt (_("bad size %d in vector width specifier"), width
);
922 switch (TOLOWER (*ptr
))
941 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
950 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
952 first_error (_("missing element size"));
955 if (width
!= 0 && width
* element_size
!= 64
956 && width
* element_size
!= 128
957 && !(width
== 2 && element_size
== 16)
958 && !(width
== 4 && element_size
== 8))
961 ("invalid element size %d and vector size combination %c"),
967 parsed_type
->type
= type
;
968 parsed_type
->width
= width
;
975 /* *STR contains an SVE zero/merge predication suffix. Parse it into
976 *PARSED_TYPE and point *STR at the end of the suffix. */
979 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
984 gas_assert (*ptr
== '/');
986 switch (TOLOWER (*ptr
))
989 parsed_type
->type
= NT_zero
;
992 parsed_type
->type
= NT_merge
;
995 if (*ptr
!= '\0' && *ptr
!= ',')
996 first_error_fmt (_("unexpected character `%c' in predication type"),
999 first_error (_("missing predication type"));
1002 parsed_type
->width
= 0;
1007 /* Parse a register of the type TYPE.
1009 Return null if the string pointed to by *CCP is not a valid register
1010 name or the parsed register is not of TYPE.
1012 Otherwise return the register, and optionally return the register
1013 shape and element index information in *TYPEINFO.
1015 FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list. */
1017 #define PTR_IN_REGLIST (1U << 0)
1019 static const reg_entry
*
1020 parse_typed_reg (char **ccp
, aarch64_reg_type type
,
1021 struct vector_type_el
*typeinfo
, unsigned int flags
)
1024 const reg_entry
*reg
= parse_reg (&str
);
1025 struct vector_type_el atype
;
1026 struct vector_type_el parsetype
;
1027 bool is_typed_vecreg
= false;
1030 atype
.type
= NT_invtype
;
1038 set_default_error ();
1042 if (! aarch64_check_reg_type (reg
, type
))
1044 DEBUG_TRACE ("reg type check failed");
1045 set_default_error ();
1050 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1051 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
1055 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
1060 if (!parse_predication_for_operand (&parsetype
, &str
))
1064 /* Register if of the form Vn.[bhsdq]. */
1065 is_typed_vecreg
= true;
1067 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1069 /* The width is always variable; we don't allow an integer width
1071 gas_assert (parsetype
.width
== 0);
1072 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1074 else if (parsetype
.width
== 0)
1075 /* Expect index. In the new scheme we cannot have
1076 Vn.[bhsdq] represent a scalar. Therefore any
1077 Vn.[bhsdq] should have an index following it.
1078 Except in reglists of course. */
1079 atype
.defined
|= NTA_HASINDEX
;
1081 atype
.defined
|= NTA_HASTYPE
;
1083 atype
.type
= parsetype
.type
;
1084 atype
.width
= parsetype
.width
;
1087 if (skip_past_char (&str
, '['))
1091 /* Reject Sn[index] syntax. */
1092 if (!is_typed_vecreg
)
1094 first_error (_("this type of register can't be indexed"));
1098 if (flags
& PTR_IN_REGLIST
)
1100 first_error (_("index not allowed inside register list"));
1104 atype
.defined
|= NTA_HASINDEX
;
1106 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1108 if (exp
.X_op
!= O_constant
)
1110 first_error (_("constant expression required"));
1114 if (! skip_past_char (&str
, ']'))
1117 atype
.index
= exp
.X_add_number
;
1119 else if (!(flags
& PTR_IN_REGLIST
) && (atype
.defined
& NTA_HASINDEX
) != 0)
1121 /* Indexed vector register expected. */
1122 first_error (_("indexed vector register expected"));
1126 /* A vector reg Vn should be typed or indexed. */
1127 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1129 first_error (_("invalid use of vector register"));
1142 Return the register on success; return null otherwise.
1144 If this is a NEON vector register with additional type information, fill
1145 in the struct pointed to by VECTYPE (if non-NULL).
1147 This parser does not handle register lists. */
1149 static const reg_entry
*
1150 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1151 struct vector_type_el
*vectype
)
1153 return parse_typed_reg (ccp
, type
, vectype
, 0);
1157 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1161 && e1
.defined
== e2
.defined
1162 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1165 /* This function parses a list of vector registers of type TYPE.
1166 On success, it returns the parsed register list information in the
1167 following encoded format:
1169 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1170 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1172 The information of the register shape and/or index is returned in
1175 It returns PARSE_FAIL if the register list is invalid.
1177 The list contains one to four registers.
1178 Each register can be one of:
1181 All <T> should be identical.
1182 All <index> should be identical.
1183 There are restrictions on <Vt> numbers which are checked later
1184 (by reg_list_valid_p). */
1187 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1188 struct vector_type_el
*vectype
)
1192 struct vector_type_el typeinfo
, typeinfo_first
;
1198 bool expect_index
= false;
1202 set_syntax_error (_("expecting {"));
1208 typeinfo_first
.defined
= 0;
1209 typeinfo_first
.type
= NT_invtype
;
1210 typeinfo_first
.width
= -1;
1211 typeinfo_first
.index
= 0;
1220 str
++; /* skip over '-' */
1223 const reg_entry
*reg
= parse_typed_reg (&str
, type
, &typeinfo
,
1227 set_first_syntax_error (_("invalid vector register in list"));
1232 /* reject [bhsd]n */
1233 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1235 set_first_syntax_error (_("invalid scalar register in list"));
1240 if (typeinfo
.defined
& NTA_HASINDEX
)
1241 expect_index
= true;
1245 if (val
< val_range
)
1247 set_first_syntax_error
1248 (_("invalid range in vector register list"));
1257 typeinfo_first
= typeinfo
;
1258 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1260 set_first_syntax_error
1261 (_("type mismatch in vector register list"));
1266 for (i
= val_range
; i
<= val
; i
++)
1268 ret_val
|= i
<< (5 * nb_regs
);
1273 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1275 skip_whitespace (str
);
1278 set_first_syntax_error (_("end of vector register list not found"));
1283 skip_whitespace (str
);
1287 if (skip_past_char (&str
, '['))
1291 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1292 if (exp
.X_op
!= O_constant
)
1294 set_first_syntax_error (_("constant expression required."));
1297 if (! skip_past_char (&str
, ']'))
1300 typeinfo_first
.index
= exp
.X_add_number
;
1304 set_first_syntax_error (_("expected index"));
1311 set_first_syntax_error (_("too many registers in vector register list"));
1314 else if (nb_regs
== 0)
1316 set_first_syntax_error (_("empty vector register list"));
1322 *vectype
= typeinfo_first
;
1324 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1327 /* Directives: register aliases. */
1330 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1335 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1338 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1341 /* Only warn about a redefinition if it's not defined as the
1343 else if (new->number
!= number
|| new->type
!= type
)
1344 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1349 name
= xstrdup (str
);
1350 new = XNEW (reg_entry
);
1353 new->number
= number
;
1355 new->builtin
= false;
1357 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1362 /* Look for the .req directive. This is of the form:
1364 new_register_name .req existing_register_name
1366 If we find one, or if it looks sufficiently like one that we want to
1367 handle any error here, return TRUE. Otherwise return FALSE. */
1370 create_register_alias (char *newname
, char *p
)
1372 const reg_entry
*old
;
1373 char *oldname
, *nbuf
;
1376 /* The input scrubber ensures that whitespace after the mnemonic is
1377 collapsed to single spaces. */
1379 if (!startswith (oldname
, " .req "))
1383 if (*oldname
== '\0')
1386 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1389 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1393 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1394 the desired alias name, and p points to its end. If not, then
1395 the desired alias name is in the global original_case_string. */
1396 #ifdef TC_CASE_SENSITIVE
1399 newname
= original_case_string
;
1400 nlen
= strlen (newname
);
1403 nbuf
= xmemdup0 (newname
, nlen
);
1405 /* Create aliases under the new name as stated; an all-lowercase
1406 version of the new name; and an all-uppercase version of the new
1408 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1410 for (p
= nbuf
; *p
; p
++)
1413 if (strncmp (nbuf
, newname
, nlen
))
1415 /* If this attempt to create an additional alias fails, do not bother
1416 trying to create the all-lower case alias. We will fail and issue
1417 a second, duplicate error message. This situation arises when the
1418 programmer does something like:
1421 The second .req creates the "Foo" alias but then fails to create
1422 the artificial FOO alias because it has already been created by the
1424 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1431 for (p
= nbuf
; *p
; p
++)
1434 if (strncmp (nbuf
, newname
, nlen
))
1435 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1442 /* Should never be called, as .req goes between the alias and the
1443 register name, not at the beginning of the line. */
1445 s_req (int a ATTRIBUTE_UNUSED
)
1447 as_bad (_("invalid syntax for .req directive"));
1450 /* The .unreq directive deletes an alias which was previously defined
1451 by .req. For example:
1457 s_unreq (int a ATTRIBUTE_UNUSED
)
1462 name
= input_line_pointer
;
1463 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
1464 saved_char
= *input_line_pointer
;
1465 *input_line_pointer
= 0;
1468 as_bad (_("invalid syntax for .unreq directive"));
1471 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1474 as_bad (_("unknown register alias '%s'"), name
);
1475 else if (reg
->builtin
)
1476 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1483 str_hash_delete (aarch64_reg_hsh
, name
);
1484 free ((char *) reg
->name
);
1487 /* Also locate the all upper case and all lower case versions.
1488 Do not complain if we cannot find one or the other as it
1489 was probably deleted above. */
1491 nbuf
= strdup (name
);
1492 for (p
= nbuf
; *p
; p
++)
1494 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1497 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1498 free ((char *) reg
->name
);
1502 for (p
= nbuf
; *p
; p
++)
1504 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1507 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1508 free ((char *) reg
->name
);
1516 *input_line_pointer
= saved_char
;
1517 demand_empty_rest_of_line ();
1520 /* Directives: Instruction set selection. */
1522 #if defined OBJ_ELF || defined OBJ_COFF
1523 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1524 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1525 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1526 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1528 /* Create a new mapping symbol for the transition to STATE. */
1531 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1534 const char *symname
;
1541 type
= BSF_NO_FLAGS
;
1545 type
= BSF_NO_FLAGS
;
1551 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1552 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1554 /* Save the mapping symbols for future reference. Also check that
1555 we do not place two mapping symbols at the same offset within a
1556 frag. We'll handle overlap between frags in
1557 check_mapping_symbols.
1559 If .fill or other data filling directive generates zero sized data,
1560 the mapping symbol for the following code will have the same value
1561 as the one generated for the data filling directive. In this case,
1562 we replace the old symbol with the new one at the same address. */
1565 if (frag
->tc_frag_data
.first_map
!= NULL
)
1567 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1568 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1571 frag
->tc_frag_data
.first_map
= symbolP
;
1573 if (frag
->tc_frag_data
.last_map
!= NULL
)
1575 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1576 S_GET_VALUE (symbolP
));
1577 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1578 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1581 frag
->tc_frag_data
.last_map
= symbolP
;
1584 /* We must sometimes convert a region marked as code to data during
1585 code alignment, if an odd number of bytes have to be padded. The
1586 code mapping symbol is pushed to an aligned address. */
1589 insert_data_mapping_symbol (enum mstate state
,
1590 valueT value
, fragS
* frag
, offsetT bytes
)
1592 /* If there was already a mapping symbol, remove it. */
1593 if (frag
->tc_frag_data
.last_map
!= NULL
1594 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1595 frag
->fr_address
+ value
)
1597 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1601 know (frag
->tc_frag_data
.first_map
== symp
);
1602 frag
->tc_frag_data
.first_map
= NULL
;
1604 frag
->tc_frag_data
.last_map
= NULL
;
1605 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1608 make_mapping_symbol (MAP_DATA
, value
, frag
);
1609 make_mapping_symbol (state
, value
+ bytes
, frag
);
1612 static void mapping_state_2 (enum mstate state
, int max_chars
);
1614 /* Set the mapping state to STATE. Only call this when about to
1615 emit some STATE bytes to the file. */
1618 mapping_state (enum mstate state
)
1620 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1622 if (state
== MAP_INSN
)
1623 /* AArch64 instructions require 4-byte alignment. When emitting
1624 instructions into any section, record the appropriate section
1626 record_alignment (now_seg
, 2);
1628 if (mapstate
== state
)
1629 /* The mapping symbol has already been emitted.
1630 There is nothing else to do. */
1633 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1634 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1635 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1636 evaluated later in the next else. */
1638 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1640 /* Only add the symbol if the offset is > 0:
1641 if we're at the first frag, check it's size > 0;
1642 if we're not at the first frag, then for sure
1643 the offset is > 0. */
1644 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1645 const int add_symbol
= (frag_now
!= frag_first
)
1646 || (frag_now_fix () > 0);
1649 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1653 mapping_state_2 (state
, 0);
1656 /* Same as mapping_state, but MAX_CHARS bytes have already been
1657 allocated. Put the mapping symbol that far back. */
1660 mapping_state_2 (enum mstate state
, int max_chars
)
1662 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1664 if (!SEG_NORMAL (now_seg
))
1667 if (mapstate
== state
)
1668 /* The mapping symbol has already been emitted.
1669 There is nothing else to do. */
1672 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1673 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1676 #define mapping_state(x) /* nothing */
1677 #define mapping_state_2(x, y) /* nothing */
1680 /* Directives: sectioning and alignment. */
1683 s_bss (int ignore ATTRIBUTE_UNUSED
)
1685 /* We don't support putting frags in the BSS segment, we fake it by
1686 marking in_bss, then looking at s_skip for clues. */
1687 subseg_set (bss_section
, 0);
1688 demand_empty_rest_of_line ();
1689 mapping_state (MAP_DATA
);
1693 s_even (int ignore ATTRIBUTE_UNUSED
)
1695 /* Never make frag if expect extra pass. */
1697 frag_align (1, 0, 0);
1699 record_alignment (now_seg
, 1);
1701 demand_empty_rest_of_line ();
1704 /* Directives: Literal pools. */
1706 static literal_pool
*
1707 find_literal_pool (int size
)
1711 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1713 if (pool
->section
== now_seg
1714 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1721 static literal_pool
*
1722 find_or_make_literal_pool (int size
)
1724 /* Next literal pool ID number. */
1725 static unsigned int latest_pool_num
= 1;
1728 pool
= find_literal_pool (size
);
1732 /* Create a new pool. */
1733 pool
= XNEW (literal_pool
);
1737 /* Currently we always put the literal pool in the current text
1738 section. If we were generating "small" model code where we
1739 knew that all code and initialised data was within 1MB then
1740 we could output literals to mergeable, read-only data
1743 pool
->next_free_entry
= 0;
1744 pool
->section
= now_seg
;
1745 pool
->sub_section
= now_subseg
;
1747 pool
->next
= list_of_pools
;
1748 pool
->symbol
= NULL
;
1750 /* Add it to the list. */
1751 list_of_pools
= pool
;
1754 /* New pools, and emptied pools, will have a NULL symbol. */
1755 if (pool
->symbol
== NULL
)
1757 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1758 &zero_address_frag
, 0);
1759 pool
->id
= latest_pool_num
++;
1766 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1767 Return TRUE on success, otherwise return FALSE. */
1769 add_to_lit_pool (expressionS
*exp
, int size
)
1774 pool
= find_or_make_literal_pool (size
);
1776 /* Check if this literal value is already in the pool. */
1777 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1779 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1781 if ((litexp
->X_op
== exp
->X_op
)
1782 && (exp
->X_op
== O_constant
)
1783 && (litexp
->X_add_number
== exp
->X_add_number
)
1784 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1787 if ((litexp
->X_op
== exp
->X_op
)
1788 && (exp
->X_op
== O_symbol
)
1789 && (litexp
->X_add_number
== exp
->X_add_number
)
1790 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1791 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1795 /* Do we need to create a new entry? */
1796 if (entry
== pool
->next_free_entry
)
1798 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1800 set_syntax_error (_("literal pool overflow"));
1804 pool
->literals
[entry
].exp
= *exp
;
1805 pool
->next_free_entry
+= 1;
1806 if (exp
->X_op
== O_big
)
1808 /* PR 16688: Bignums are held in a single global array. We must
1809 copy and preserve that value now, before it is overwritten. */
1810 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1812 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1813 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1816 pool
->literals
[entry
].bignum
= NULL
;
1819 exp
->X_op
= O_symbol
;
1820 exp
->X_add_number
= ((int) entry
) * size
;
1821 exp
->X_add_symbol
= pool
->symbol
;
1826 /* Can't use symbol_new here, so have to create a symbol and then at
1827 a later date assign it a value. That's what these functions do. */
1830 symbol_locate (symbolS
* symbolP
,
1831 const char *name
,/* It is copied, the caller can modify. */
1832 segT segment
, /* Segment identifier (SEG_<something>). */
1833 valueT valu
, /* Symbol value. */
1834 fragS
* frag
) /* Associated fragment. */
1837 char *preserved_copy_of_name
;
1839 name_length
= strlen (name
) + 1; /* +1 for \0. */
1840 obstack_grow (¬es
, name
, name_length
);
1841 preserved_copy_of_name
= obstack_finish (¬es
);
1843 #ifdef tc_canonicalize_symbol_name
1844 preserved_copy_of_name
=
1845 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1848 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1850 S_SET_SEGMENT (symbolP
, segment
);
1851 S_SET_VALUE (symbolP
, valu
);
1852 symbol_clear_list_pointers (symbolP
);
1854 symbol_set_frag (symbolP
, frag
);
1856 /* Link to end of symbol chain. */
1858 extern int symbol_table_frozen
;
1860 if (symbol_table_frozen
)
1864 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1866 obj_symbol_new_hook (symbolP
);
1868 #ifdef tc_symbol_new_hook
1869 tc_symbol_new_hook (symbolP
);
1873 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1874 #endif /* DEBUG_SYMS */
1879 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1886 for (align
= 2; align
<= 4; align
++)
1888 int size
= 1 << align
;
1890 pool
= find_literal_pool (size
);
1891 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1894 /* Align pool as you have word accesses.
1895 Only make a frag if we have to. */
1897 frag_align (align
, 0, 0);
1899 mapping_state (MAP_DATA
);
1901 record_alignment (now_seg
, align
);
1903 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1905 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1906 (valueT
) frag_now_fix (), frag_now
);
1907 symbol_table_insert (pool
->symbol
);
1909 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1911 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1913 if (exp
->X_op
== O_big
)
1915 /* PR 16688: Restore the global bignum value. */
1916 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1917 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1918 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1921 /* First output the expression in the instruction to the pool. */
1922 emit_expr (exp
, size
); /* .word|.xword */
1924 if (exp
->X_op
== O_big
)
1926 free (pool
->literals
[entry
].bignum
);
1927 pool
->literals
[entry
].bignum
= NULL
;
1931 /* Mark the pool as empty. */
1932 pool
->next_free_entry
= 0;
1933 pool
->symbol
= NULL
;
1937 #if defined(OBJ_ELF) || defined(OBJ_COFF)
1938 /* Forward declarations for functions below, in the MD interface
1940 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1942 /* Directives: Data. */
1943 /* N.B. the support for relocation suffix in this directive needs to be
1944 implemented properly. */
1947 s_aarch64_cons (int nbytes
)
1951 #ifdef md_flush_pending_output
1952 md_flush_pending_output ();
1955 if (is_it_end_of_statement ())
1957 demand_empty_rest_of_line ();
1961 #ifdef md_cons_align
1962 md_cons_align (nbytes
);
1965 mapping_state (MAP_DATA
);
1968 struct reloc_table_entry
*reloc
;
1972 if (exp
.X_op
!= O_symbol
)
1973 emit_expr (&exp
, (unsigned int) nbytes
);
1976 skip_past_char (&input_line_pointer
, '#');
1977 if (skip_past_char (&input_line_pointer
, ':'))
1979 reloc
= find_reloc_table_entry (&input_line_pointer
);
1981 as_bad (_("unrecognized relocation suffix"));
1983 as_bad (_("unimplemented relocation suffix"));
1984 ignore_rest_of_line ();
1988 emit_expr (&exp
, (unsigned int) nbytes
);
1991 while (*input_line_pointer
++ == ',');
1993 /* Put terminator back into stream. */
1994 input_line_pointer
--;
1995 demand_empty_rest_of_line ();
2000 /* Forward declarations for functions below, in the MD interface
2002 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
2004 /* Mark symbol that it follows a variant PCS convention. */
2007 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
2013 elf_symbol_type
*elfsym
;
2015 c
= get_symbol_name (&name
);
2017 as_bad (_("Missing symbol name in directive"));
2018 sym
= symbol_find_or_make (name
);
2019 restore_line_pointer (c
);
2020 demand_empty_rest_of_line ();
2021 bfdsym
= symbol_get_bfdsym (sym
);
2022 elfsym
= elf_symbol_from (bfdsym
);
2023 gas_assert (elfsym
);
2024 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
2026 #endif /* OBJ_ELF */
2028 /* Output a 32-bit word, but mark as an instruction. */
2031 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
2036 #ifdef md_flush_pending_output
2037 md_flush_pending_output ();
2040 if (is_it_end_of_statement ())
2042 demand_empty_rest_of_line ();
2046 /* Sections are assumed to start aligned. In executable section, there is no
2047 MAP_DATA symbol pending. So we only align the address during
2048 MAP_DATA --> MAP_INSN transition.
2049 For other sections, this is not guaranteed. */
2050 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2051 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2052 frag_align_code (2, 0);
2055 mapping_state (MAP_INSN
);
2061 if (exp
.X_op
!= O_constant
)
2063 as_bad (_("constant expression required"));
2064 ignore_rest_of_line ();
2068 if (target_big_endian
)
2070 unsigned int val
= exp
.X_add_number
;
2071 exp
.X_add_number
= SWAP_32 (val
);
2073 emit_expr (&exp
, INSN_SIZE
);
2076 while (*input_line_pointer
++ == ',');
2078 dwarf2_emit_insn (n
* INSN_SIZE
);
2080 /* Put terminator back into stream. */
2081 input_line_pointer
--;
2082 demand_empty_rest_of_line ();
2086 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2088 demand_empty_rest_of_line ();
2089 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2090 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2094 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2097 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2103 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2104 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2106 demand_empty_rest_of_line ();
2109 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2112 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2116 /* Since we're just labelling the code, there's no need to define a
2119 /* Make sure there is enough room in this frag for the following
2120 blr. This trick only works if the blr follows immediately after
2121 the .tlsdesc directive. */
2123 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2124 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2126 demand_empty_rest_of_line ();
2129 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2132 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2138 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2139 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2141 demand_empty_rest_of_line ();
2143 #endif /* OBJ_ELF */
2147 s_secrel (int dummy ATTRIBUTE_UNUSED
)
2154 if (exp
.X_op
== O_symbol
)
2155 exp
.X_op
= O_secrel
;
2157 emit_expr (&exp
, 4);
2159 while (*input_line_pointer
++ == ',');
2161 input_line_pointer
--;
2162 demand_empty_rest_of_line ();
2166 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
2170 exp
.X_op
= O_secrel
;
2171 exp
.X_add_symbol
= symbol
;
2172 exp
.X_add_number
= 0;
2173 emit_expr (&exp
, size
);
2177 s_secidx (int dummy ATTRIBUTE_UNUSED
)
2184 if (exp
.X_op
== O_symbol
)
2185 exp
.X_op
= O_secidx
;
2187 emit_expr (&exp
, 2);
2189 while (*input_line_pointer
++ == ',');
2191 input_line_pointer
--;
2192 demand_empty_rest_of_line ();
2196 static void s_aarch64_arch (int);
2197 static void s_aarch64_cpu (int);
2198 static void s_aarch64_arch_extension (int);
2200 /* This table describes all the machine specific pseudo-ops the assembler
2201 has to support. The fields are:
2202 pseudo-op name without dot
2203 function to call to execute this pseudo-op
2204 Integer arg to pass to the function. */
2206 const pseudo_typeS md_pseudo_table
[] = {
2207 /* Never called because '.req' does not start a line. */
2209 {"unreq", s_unreq
, 0},
2211 {"even", s_even
, 0},
2212 {"ltorg", s_ltorg
, 0},
2213 {"pool", s_ltorg
, 0},
2214 {"cpu", s_aarch64_cpu
, 0},
2215 {"arch", s_aarch64_arch
, 0},
2216 {"arch_extension", s_aarch64_arch_extension
, 0},
2217 {"inst", s_aarch64_inst
, 0},
2218 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2220 {"tlsdescadd", s_tlsdescadd
, 0},
2221 {"tlsdesccall", s_tlsdesccall
, 0},
2222 {"tlsdescldr", s_tlsdescldr
, 0},
2223 {"variant_pcs", s_variant_pcs
, 0},
2225 #if defined(OBJ_ELF) || defined(OBJ_COFF)
2226 {"word", s_aarch64_cons
, 4},
2227 {"long", s_aarch64_cons
, 4},
2228 {"xword", s_aarch64_cons
, 8},
2229 {"dword", s_aarch64_cons
, 8},
2232 {"secrel32", s_secrel
, 0},
2233 {"secidx", s_secidx
, 0},
2235 {"float16", float_cons
, 'h'},
2236 {"bfloat16", float_cons
, 'b'},
2241 /* Check whether STR points to a register name followed by a comma or the
2242 end of line; REG_TYPE indicates which register types are checked
2243 against. Return TRUE if STR is such a register name; otherwise return
2244 FALSE. The function does not intend to produce any diagnostics, but since
2245 the register parser aarch64_reg_parse, which is called by this function,
2246 does produce diagnostics, we call clear_error to clear any diagnostics
2247 that may be generated by aarch64_reg_parse.
2248 Also, the function returns FALSE directly if there is any user error
2249 present at the function entry. This prevents the existing diagnostics
2250 state from being spoiled.
2251 The function currently serves parse_constant_immediate and
2252 parse_big_immediate only. */
2254 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2256 const reg_entry
*reg
;
2258 /* Prevent the diagnostics state from being spoiled. */
2262 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
);
2264 /* Clear the parsing error that may be set by the reg parser. */
2270 skip_whitespace (str
);
2271 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2277 /* Parser functions used exclusively in instruction operands. */
2279 /* Parse an immediate expression which may not be constant.
2281 To prevent the expression parser from pushing a register name
2282 into the symbol table as an undefined symbol, firstly a check is
2283 done to find out whether STR is a register of type REG_TYPE followed
2284 by a comma or the end of line. Return FALSE if STR is such a string. */
2287 parse_immediate_expression (char **str
, expressionS
*exp
,
2288 aarch64_reg_type reg_type
)
2290 if (reg_name_p (*str
, reg_type
))
2292 set_recoverable_error (_("immediate operand required"));
2296 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2298 if (exp
->X_op
== O_absent
)
2300 set_fatal_syntax_error (_("missing immediate expression"));
2307 /* Constant immediate-value read function for use in insn parsing.
2308 STR points to the beginning of the immediate (with the optional
2309 leading #); *VAL receives the value. REG_TYPE says which register
2310 names should be treated as registers rather than as symbolic immediates.
2312 Return TRUE on success; otherwise return FALSE. */
2315 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2319 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2322 if (exp
.X_op
!= O_constant
)
2324 set_syntax_error (_("constant expression required"));
2328 *val
= exp
.X_add_number
;
2333 encode_imm_float_bits (uint32_t imm
)
2335 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2336 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2339 /* Return TRUE if the single-precision floating-point value encoded in IMM
2340 can be expressed in the AArch64 8-bit signed floating-point format with
2341 3-bit exponent and normalized 4 bits of precision; in other words, the
2342 floating-point value must be expressable as
2343 (+/-) n / 16 * power (2, r)
2344 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2347 aarch64_imm_float_p (uint32_t imm
)
2349 /* If a single-precision floating-point value has the following bit
2350 pattern, it can be expressed in the AArch64 8-bit floating-point
2353 3 32222222 2221111111111
2354 1 09876543 21098765432109876543210
2355 n Eeeeeexx xxxx0000000000000000000
2357 where n, e and each x are either 0 or 1 independently, with
2362 /* Prepare the pattern for 'Eeeeee'. */
2363 if (((imm
>> 30) & 0x1) == 0)
2364 pattern
= 0x3e000000;
2366 pattern
= 0x40000000;
2368 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2369 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2372 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2373 as an IEEE float without any loss of precision. Store the value in
2377 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2379 /* If a double-precision floating-point value has the following bit
2380 pattern, it can be expressed in a float:
2382 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2383 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2384 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2386 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2387 if Eeee_eeee != 1111_1111
2389 where n, e, s and S are either 0 or 1 independently and where ~ is the
2393 uint32_t high32
= imm
>> 32;
2394 uint32_t low32
= imm
;
2396 /* Lower 29 bits need to be 0s. */
2397 if ((imm
& 0x1fffffff) != 0)
2400 /* Prepare the pattern for 'Eeeeeeeee'. */
2401 if (((high32
>> 30) & 0x1) == 0)
2402 pattern
= 0x38000000;
2404 pattern
= 0x40000000;
2407 if ((high32
& 0x78000000) != pattern
)
2410 /* Check Eeee_eeee != 1111_1111. */
2411 if ((high32
& 0x7ff00000) == 0x47f00000)
2414 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2415 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2416 | (low32
>> 29)); /* 3 S bits. */
2420 /* Return true if we should treat OPERAND as a double-precision
2421 floating-point operand rather than a single-precision one. */
2423 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2425 /* Check for unsuffixed SVE registers, which are allowed
2426 for LDR and STR but not in instructions that require an
2427 immediate. We get better error messages if we arbitrarily
2428 pick one size, parse the immediate normally, and then
2429 report the match failure in the normal way. */
2430 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2431 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2434 /* Parse a floating-point immediate. Return TRUE on success and return the
2435 value in *IMMED in the format of IEEE754 single-precision encoding.
2436 *CCP points to the start of the string; DP_P is TRUE when the immediate
2437 is expected to be in double-precision (N.B. this only matters when
2438 hexadecimal representation is involved). REG_TYPE says which register
2439 names should be treated as registers rather than as symbolic immediates.
2441 This routine accepts any IEEE float; it is up to the callers to reject
2445 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2446 aarch64_reg_type reg_type
)
2450 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2452 unsigned fpword
= 0;
2455 skip_past_char (&str
, '#');
2458 skip_whitespace (fpnum
);
2460 if (startswith (fpnum
, "0x"))
2462 /* Support the hexadecimal representation of the IEEE754 encoding.
2463 Double-precision is expected when DP_P is TRUE, otherwise the
2464 representation should be in single-precision. */
2465 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2470 if (!can_convert_double_to_float (val
, &fpword
))
2473 else if ((uint64_t) val
> 0xffffffff)
2480 else if (reg_name_p (str
, reg_type
))
2482 set_recoverable_error (_("immediate operand required"));
2490 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2493 /* Our FP word must be 32 bits (single-precision FP). */
2494 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2496 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2506 set_fatal_syntax_error (_("invalid floating-point constant"));
2510 /* Less-generic immediate-value read function with the possibility of loading
2511 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2514 To prevent the expression parser from pushing a register name into the
2515 symbol table as an undefined symbol, a check is firstly done to find
2516 out whether STR is a register of type REG_TYPE followed by a comma or
2517 the end of line. Return FALSE if STR is such a register. */
2520 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2524 if (reg_name_p (ptr
, reg_type
))
2526 set_syntax_error (_("immediate operand required"));
2530 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2532 if (inst
.reloc
.exp
.X_op
== O_constant
)
2533 *imm
= inst
.reloc
.exp
.X_add_number
;
2540 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2541 if NEED_LIBOPCODES is non-zero, the fixup will need
2542 assistance from the libopcodes. */
2545 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2546 const aarch64_opnd_info
*operand
,
2547 int need_libopcodes_p
)
2549 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2550 reloc
->opnd
= operand
->type
;
2551 if (need_libopcodes_p
)
2552 reloc
->need_libopcodes_p
= 1;
2555 /* Return TRUE if the instruction needs to be fixed up later internally by
2556 the GAS; otherwise return FALSE. */
2559 aarch64_gas_internal_fixup_p (void)
2561 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2564 /* Assign the immediate value to the relevant field in *OPERAND if
2565 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2566 needs an internal fixup in a later stage.
2567 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2568 IMM.VALUE that may get assigned with the constant. */
2570 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2571 aarch64_opnd_info
*operand
,
2573 int need_libopcodes_p
,
2576 if (reloc
->exp
.X_op
== O_constant
)
2579 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2581 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2582 reloc
->type
= BFD_RELOC_UNUSED
;
2586 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2587 /* Tell libopcodes to ignore this operand or not. This is helpful
2588 when one of the operands needs to be fixed up later but we need
2589 libopcodes to check the other operands. */
2590 operand
->skip
= skip_p
;
2594 /* Relocation modifiers. Each entry in the table contains the textual
2595 name for the relocation which may be placed before a symbol used as
2596 a load/store offset, or add immediate. It must be surrounded by a
2597 leading and trailing colon, for example:
2599 ldr x0, [x1, #:rello:varsym]
2600 add x0, x1, #:rello:varsym */
2602 struct reloc_table_entry
2606 bfd_reloc_code_real_type adr_type
;
2607 bfd_reloc_code_real_type adrp_type
;
2608 bfd_reloc_code_real_type movw_type
;
2609 bfd_reloc_code_real_type add_type
;
2610 bfd_reloc_code_real_type ldst_type
;
2611 bfd_reloc_code_real_type ld_literal_type
;
2614 static struct reloc_table_entry reloc_table
[] =
2616 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2621 BFD_RELOC_AARCH64_ADD_LO12
,
2622 BFD_RELOC_AARCH64_LDST_LO12
,
2625 /* Higher 21 bits of pc-relative page offset: ADRP */
2628 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2634 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2637 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2643 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2647 BFD_RELOC_AARCH64_MOVW_G0
,
2652 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2656 BFD_RELOC_AARCH64_MOVW_G0_S
,
2661 /* Less significant bits 0-15 of address/value: MOVK, no check */
2665 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2670 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2674 BFD_RELOC_AARCH64_MOVW_G1
,
2679 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2683 BFD_RELOC_AARCH64_MOVW_G1_S
,
2688 /* Less significant bits 16-31 of address/value: MOVK, no check */
2692 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2697 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2701 BFD_RELOC_AARCH64_MOVW_G2
,
2706 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2710 BFD_RELOC_AARCH64_MOVW_G2_S
,
2715 /* Less significant bits 32-47 of address/value: MOVK, no check */
2719 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2724 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2728 BFD_RELOC_AARCH64_MOVW_G3
,
2733 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2737 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2742 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2746 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2751 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2755 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2760 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2764 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2769 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2773 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2778 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2782 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2787 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2791 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2796 /* Get to the page containing GOT entry for a symbol. */
2799 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2803 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2805 /* 12 bit offset into the page containing GOT entry for that symbol. */
2811 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2814 /* 0-15 bits of address/value: MOVk, no check. */
2818 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2823 /* Most significant bits 16-31 of address/value: MOVZ. */
2827 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2832 /* 15 bit offset into the page containing GOT entry for that symbol. */
2838 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2841 /* Get to the page containing GOT TLS entry for a symbol */
2842 {"gottprel_g0_nc", 0,
2845 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2850 /* Get to the page containing GOT TLS entry for a symbol */
2854 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2859 /* Get to the page containing GOT TLS entry for a symbol */
2861 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2862 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2868 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2873 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2877 /* Lower 16 bits address/value: MOVk. */
2881 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2886 /* Most significant bits 16-31 of address/value: MOVZ. */
2890 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2895 /* Get to the page containing GOT TLS entry for a symbol */
2897 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2898 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2902 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2904 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2909 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2910 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2913 /* Get to the page containing GOT TLS entry for a symbol.
2914 The same as GD, we allocate two consecutive GOT slots
2915 for module index and module offset, the only difference
2916 with GD is the module offset should be initialized to
2917 zero without any outstanding runtime relocation. */
2919 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2920 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2926 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2927 {"tlsldm_lo12_nc", 0,
2931 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2935 /* 12 bit offset into the module TLS base address. */
2940 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2941 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2944 /* Same as dtprel_lo12, no overflow check. */
2945 {"dtprel_lo12_nc", 0,
2949 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2950 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2953 /* bits[23:12] of offset to the module TLS base address. */
2958 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2962 /* bits[15:0] of offset to the module TLS base address. */
2966 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2971 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2975 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2980 /* bits[31:16] of offset to the module TLS base address. */
2984 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2989 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2993 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2998 /* bits[47:32] of offset to the module TLS base address. */
3002 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
3007 /* Lower 16 bit offset into GOT entry for a symbol */
3008 {"tlsdesc_off_g0_nc", 0,
3011 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
3016 /* Higher 16 bit offset into GOT entry for a symbol */
3017 {"tlsdesc_off_g1", 0,
3020 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
3025 /* Get to the page containing GOT TLS entry for a symbol */
3028 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
3032 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
3034 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
3035 {"gottprel_lo12", 0,
3040 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
3043 /* Get tp offset for a symbol. */
3048 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3052 /* Get tp offset for a symbol. */
3057 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
3058 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
3061 /* Get tp offset for a symbol. */
3066 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
3070 /* Get tp offset for a symbol. */
3071 {"tprel_lo12_nc", 0,
3075 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
3076 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
3079 /* Most significant bits 32-47 of address/value: MOVZ. */
3083 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
3088 /* Most significant bits 16-31 of address/value: MOVZ. */
3092 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
3097 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
3101 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
3106 /* Most significant bits 0-15 of address/value: MOVZ. */
3110 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3115 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3119 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3124 /* 15bit offset from got entry to base address of GOT table. */
3130 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3133 /* 14bit offset from got entry to base address of GOT table. */
3139 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3143 /* Given the address of a pointer pointing to the textual name of a
3144 relocation as may appear in assembler source, attempt to find its
3145 details in reloc_table. The pointer will be updated to the character
3146 after the trailing colon. On failure, NULL will be returned;
3147 otherwise return the reloc_table_entry. */
3149 static struct reloc_table_entry
*
3150 find_reloc_table_entry (char **str
)
3153 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3155 int length
= strlen (reloc_table
[i
].name
);
3157 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3158 && (*str
)[length
] == ':')
3160 *str
+= (length
+ 1);
3161 return &reloc_table
[i
];
3168 /* Returns 0 if the relocation should never be forced,
3169 1 if the relocation must be forced, and -1 if either
3173 aarch64_force_reloc (unsigned int type
)
3177 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3178 /* Perform these "immediate" internal relocations
3179 even if the symbol is extern or weak. */
3182 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3183 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3184 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3185 /* Pseudo relocs that need to be fixed up according to
3189 case BFD_RELOC_AARCH64_ADD_LO12
:
3190 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3191 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3192 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3193 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3194 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3195 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3196 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3197 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3198 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3199 case BFD_RELOC_AARCH64_LDST128_LO12
:
3200 case BFD_RELOC_AARCH64_LDST16_LO12
:
3201 case BFD_RELOC_AARCH64_LDST32_LO12
:
3202 case BFD_RELOC_AARCH64_LDST64_LO12
:
3203 case BFD_RELOC_AARCH64_LDST8_LO12
:
3204 case BFD_RELOC_AARCH64_LDST_LO12
:
3205 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3206 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3207 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3208 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3209 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3210 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3211 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3212 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3213 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3214 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3215 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3216 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3217 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3218 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3219 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3220 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3221 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3222 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3223 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3224 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3225 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3226 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3227 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3228 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3229 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3230 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3231 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3232 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3233 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3234 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3235 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3236 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3237 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3238 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
:
3239 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
:
3240 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3241 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3242 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3243 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3244 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3245 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3246 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3247 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3248 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3249 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3250 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3251 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3252 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3253 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
:
3254 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
:
3255 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3256 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3257 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3258 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3259 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3260 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3261 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3262 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3263 /* Always leave these relocations for the linker. */
3272 aarch64_force_relocation (struct fix
*fixp
)
3274 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3277 return generic_force_reloc (fixp
);
3281 /* Mode argument to parse_shift and parser_shifter_operand. */
3282 enum parse_shift_mode
3284 SHIFTED_NONE
, /* no shifter allowed */
3285 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3287 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3289 SHIFTED_LSL
, /* bare "lsl #n" */
3290 SHIFTED_MUL
, /* bare "mul #n" */
3291 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3292 SHIFTED_MUL_VL
, /* "mul vl" */
3293 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3296 /* Parse a <shift> operator on an AArch64 data processing instruction.
3297 Return TRUE on success; otherwise return FALSE. */
3299 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3301 const struct aarch64_name_value_pair
*shift_op
;
3302 enum aarch64_modifier_kind kind
;
3308 for (p
= *str
; ISALPHA (*p
); p
++)
3313 set_syntax_error (_("shift expression expected"));
3317 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3319 if (shift_op
== NULL
)
3321 set_syntax_error (_("shift operator expected"));
3325 kind
= aarch64_get_operand_modifier (shift_op
);
3327 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3329 set_syntax_error (_("invalid use of 'MSL'"));
3333 if (kind
== AARCH64_MOD_MUL
3334 && mode
!= SHIFTED_MUL
3335 && mode
!= SHIFTED_MUL_VL
)
3337 set_syntax_error (_("invalid use of 'MUL'"));
3343 case SHIFTED_LOGIC_IMM
:
3344 if (aarch64_extend_operator_p (kind
))
3346 set_syntax_error (_("extending shift is not permitted"));
3351 case SHIFTED_ARITH_IMM
:
3352 if (kind
== AARCH64_MOD_ROR
)
3354 set_syntax_error (_("'ROR' shift is not permitted"));
3360 if (kind
!= AARCH64_MOD_LSL
)
3362 set_syntax_error (_("only 'LSL' shift is permitted"));
3368 if (kind
!= AARCH64_MOD_MUL
)
3370 set_syntax_error (_("only 'MUL' is permitted"));
3375 case SHIFTED_MUL_VL
:
3376 /* "MUL VL" consists of two separate tokens. Require the first
3377 token to be "MUL" and look for a following "VL". */
3378 if (kind
== AARCH64_MOD_MUL
)
3380 skip_whitespace (p
);
3381 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3384 kind
= AARCH64_MOD_MUL_VL
;
3388 set_syntax_error (_("only 'MUL VL' is permitted"));
3391 case SHIFTED_REG_OFFSET
:
3392 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3393 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3395 set_fatal_syntax_error
3396 (_("invalid shift for the register offset addressing mode"));
3401 case SHIFTED_LSL_MSL
:
3402 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3404 set_syntax_error (_("invalid shift operator"));
3413 /* Whitespace can appear here if the next thing is a bare digit. */
3414 skip_whitespace (p
);
3416 /* Parse shift amount. */
3418 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3419 exp
.X_op
= O_absent
;
3422 if (is_immediate_prefix (*p
))
3427 aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
);
3429 if (kind
== AARCH64_MOD_MUL_VL
)
3430 /* For consistency, give MUL VL the same shift amount as an implicit
3432 operand
->shifter
.amount
= 1;
3433 else if (exp
.X_op
== O_absent
)
3435 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3437 set_syntax_error (_("missing shift amount"));
3440 operand
->shifter
.amount
= 0;
3442 else if (exp
.X_op
!= O_constant
)
3444 set_syntax_error (_("constant shift amount required"));
3447 /* For parsing purposes, MUL #n has no inherent range. The range
3448 depends on the operand and will be checked by operand-specific
3450 else if (kind
!= AARCH64_MOD_MUL
3451 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3453 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3458 operand
->shifter
.amount
= exp
.X_add_number
;
3459 operand
->shifter
.amount_present
= 1;
3462 operand
->shifter
.operator_present
= 1;
3463 operand
->shifter
.kind
= kind
;
3469 /* Parse a <shifter_operand> for a data processing instruction:
3472 #<immediate>, LSL #imm
3474 Validation of immediate operands is deferred to md_apply_fix.
3476 Return TRUE on success; otherwise return FALSE. */
3479 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3480 enum parse_shift_mode mode
)
3484 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3489 /* Accept an immediate expression. */
3490 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3494 /* Accept optional LSL for arithmetic immediate values. */
3495 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3496 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3499 /* Not accept any shifter for logical immediate values. */
3500 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3501 && parse_shift (&p
, operand
, mode
))
3503 set_syntax_error (_("unexpected shift operator"));
3511 /* Parse a <shifter_operand> for a data processing instruction:
3516 #<immediate>, LSL #imm
3518 where <shift> is handled by parse_shift above, and the last two
3519 cases are handled by the function above.
3521 Validation of immediate operands is deferred to md_apply_fix.
3523 Return TRUE on success; otherwise return FALSE. */
3526 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3527 enum parse_shift_mode mode
)
3529 const reg_entry
*reg
;
3530 aarch64_opnd_qualifier_t qualifier
;
3531 enum aarch64_operand_class opd_class
3532 = aarch64_get_operand_class (operand
->type
);
3534 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3537 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3539 set_syntax_error (_("unexpected register in the immediate operand"));
3543 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3545 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3549 operand
->reg
.regno
= reg
->number
;
3550 operand
->qualifier
= qualifier
;
3552 /* Accept optional shift operation on register. */
3553 if (! skip_past_comma (str
))
3556 if (! parse_shift (str
, operand
, mode
))
3561 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3564 (_("integer register expected in the extended/shifted operand "
3569 /* We have a shifted immediate variable. */
3570 return parse_shifter_operand_imm (str
, operand
, mode
);
3573 /* Return TRUE on success; return FALSE otherwise. */
3576 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3577 enum parse_shift_mode mode
)
3581 /* Determine if we have the sequence of characters #: or just :
3582 coming next. If we do, then we check for a :rello: relocation
3583 modifier. If we don't, punt the whole lot to
3584 parse_shifter_operand. */
3586 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3588 struct reloc_table_entry
*entry
;
3596 /* Try to parse a relocation. Anything else is an error. */
3597 if (!(entry
= find_reloc_table_entry (str
)))
3599 set_syntax_error (_("unknown relocation modifier"));
3603 if (entry
->add_type
== 0)
3606 (_("this relocation modifier is not allowed on this instruction"));
3610 /* Save str before we decompose it. */
3613 /* Next, we parse the expression. */
3614 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3618 /* Record the relocation type (use the ADD variant here). */
3619 inst
.reloc
.type
= entry
->add_type
;
3620 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3622 /* If str is empty, we've reached the end, stop here. */
3626 /* Otherwise, we have a shifted reloc modifier, so rewind to
3627 recover the variable name and continue parsing for the shifter. */
3629 return parse_shifter_operand_imm (str
, operand
, mode
);
3632 return parse_shifter_operand (str
, operand
, mode
);
3635 /* Parse all forms of an address expression. Information is written
3636 to *OPERAND and/or inst.reloc.
3638 The A64 instruction set has the following addressing modes:
3641 [base] // in SIMD ld/st structure
3642 [base{,#0}] // in ld/st exclusive
3644 [base,Xm{,LSL #imm}]
3645 [base,Xm,SXTX {#imm}]
3646 [base,Wm,(S|U)XTW {#imm}]
3648 [base]! // in ldraa/ldrab exclusive
3652 [base],Xm // in SIMD ld/st structure
3653 PC-relative (literal)
3657 [base,Zm.D{,LSL #imm}]
3658 [base,Zm.S,(S|U)XTW {#imm}]
3659 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3663 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3664 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3665 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3667 (As a convenience, the notation "=immediate" is permitted in conjunction
3668 with the pc-relative literal load instructions to automatically place an
3669 immediate value or symbolic address in a nearby literal pool and generate
3670 a hidden label which references it.)
3672 Upon a successful parsing, the address structure in *OPERAND will be
3673 filled in the following way:
3675 .base_regno = <base>
3676 .offset.is_reg // 1 if the offset is a register
3678 .offset.regno = <Rm>
3680 For different addressing modes defined in the A64 ISA:
3683 .pcrel=0; .preind=1; .postind=0; .writeback=0
3685 .pcrel=0; .preind=1; .postind=0; .writeback=1
3687 .pcrel=0; .preind=0; .postind=1; .writeback=1
3688 PC-relative (literal)
3689 .pcrel=1; .preind=1; .postind=0; .writeback=0
3691 The shift/extension information, if any, will be stored in .shifter.
3692 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3693 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3694 corresponding register.
3696 BASE_TYPE says which types of base register should be accepted and
3697 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3698 is the type of shifter that is allowed for immediate offsets,
3699 or SHIFTED_NONE if none.
3701 In all other respects, it is the caller's responsibility to check
3702 for addressing modes not supported by the instruction, and to set
3706 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3707 aarch64_opnd_qualifier_t
*base_qualifier
,
3708 aarch64_opnd_qualifier_t
*offset_qualifier
,
3709 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3710 enum parse_shift_mode imm_shift_mode
)
3713 const reg_entry
*reg
;
3714 expressionS
*exp
= &inst
.reloc
.exp
;
3716 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3717 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3718 if (! skip_past_char (&p
, '['))
3720 /* =immediate or label. */
3721 operand
->addr
.pcrel
= 1;
3722 operand
->addr
.preind
= 1;
3724 /* #:<reloc_op>:<symbol> */
3725 skip_past_char (&p
, '#');
3726 if (skip_past_char (&p
, ':'))
3728 bfd_reloc_code_real_type ty
;
3729 struct reloc_table_entry
*entry
;
3731 /* Try to parse a relocation modifier. Anything else is
3733 entry
= find_reloc_table_entry (&p
);
3736 set_syntax_error (_("unknown relocation modifier"));
3740 switch (operand
->type
)
3742 case AARCH64_OPND_ADDR_PCREL21
:
3744 ty
= entry
->adr_type
;
3748 ty
= entry
->ld_literal_type
;
3755 (_("this relocation modifier is not allowed on this "
3761 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3763 set_syntax_error (_("invalid relocation expression"));
3766 /* #:<reloc_op>:<expr> */
3767 /* Record the relocation type. */
3768 inst
.reloc
.type
= ty
;
3769 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3773 if (skip_past_char (&p
, '='))
3774 /* =immediate; need to generate the literal in the literal pool. */
3775 inst
.gen_lit_pool
= 1;
3777 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3779 set_syntax_error (_("invalid address"));
3790 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3791 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3793 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3796 operand
->addr
.base_regno
= reg
->number
;
3799 if (skip_past_comma (&p
))
3802 operand
->addr
.preind
= 1;
3804 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3807 if (!aarch64_check_reg_type (reg
, offset_type
))
3809 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3814 operand
->addr
.offset
.regno
= reg
->number
;
3815 operand
->addr
.offset
.is_reg
= 1;
3816 /* Shifted index. */
3817 if (skip_past_comma (&p
))
3820 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3821 /* Use the diagnostics set in parse_shift, so not set new
3822 error message here. */
3826 [base,Xm] # For vector plus scalar SVE2 indexing.
3827 [base,Xm{,LSL #imm}]
3828 [base,Xm,SXTX {#imm}]
3829 [base,Wm,(S|U)XTW {#imm}] */
3830 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3831 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3832 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3834 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3836 set_syntax_error (_("invalid use of 32-bit register offset"));
3839 if (aarch64_get_qualifier_esize (*base_qualifier
)
3840 != aarch64_get_qualifier_esize (*offset_qualifier
)
3841 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3842 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3843 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3845 set_syntax_error (_("offset has different size from base"));
3849 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3851 set_syntax_error (_("invalid use of 64-bit register offset"));
3857 /* [Xn,#:<reloc_op>:<symbol> */
3858 skip_past_char (&p
, '#');
3859 if (skip_past_char (&p
, ':'))
3861 struct reloc_table_entry
*entry
;
3863 /* Try to parse a relocation modifier. Anything else is
3865 if (!(entry
= find_reloc_table_entry (&p
)))
3867 set_syntax_error (_("unknown relocation modifier"));
3871 if (entry
->ldst_type
== 0)
3874 (_("this relocation modifier is not allowed on this "
3879 /* [Xn,#:<reloc_op>: */
3880 /* We now have the group relocation table entry corresponding to
3881 the name in the assembler source. Next, we parse the
3883 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3885 set_syntax_error (_("invalid relocation expression"));
3889 /* [Xn,#:<reloc_op>:<expr> */
3890 /* Record the load/store relocation type. */
3891 inst
.reloc
.type
= entry
->ldst_type
;
3892 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3896 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
3898 set_syntax_error (_("invalid expression in the address"));
3902 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3903 /* [Xn,<expr>,<shifter> */
3904 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3910 if (! skip_past_char (&p
, ']'))
3912 set_syntax_error (_("']' expected"));
3916 if (skip_past_char (&p
, '!'))
3918 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3920 set_syntax_error (_("register offset not allowed in pre-indexed "
3921 "addressing mode"));
3925 operand
->addr
.writeback
= 1;
3927 else if (skip_past_comma (&p
))
3930 operand
->addr
.postind
= 1;
3931 operand
->addr
.writeback
= 1;
3933 if (operand
->addr
.preind
)
3935 set_syntax_error (_("cannot combine pre- and post-indexing"));
3939 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3943 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3945 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3949 operand
->addr
.offset
.regno
= reg
->number
;
3950 operand
->addr
.offset
.is_reg
= 1;
3952 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
3955 set_syntax_error (_("invalid expression in the address"));
3960 /* If at this point neither .preind nor .postind is set, we have a
3961 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3962 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3963 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3965 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3967 if (operand
->addr
.writeback
)
3969 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3971 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3972 operand
->addr
.offset
.is_reg
= 0;
3973 operand
->addr
.offset
.imm
= 0;
3974 operand
->addr
.preind
= 1;
3979 set_syntax_error (_("missing offset in the pre-indexed address"));
3985 operand
->addr
.preind
= 1;
3986 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3988 operand
->addr
.offset
.is_reg
= 1;
3989 operand
->addr
.offset
.regno
= REG_ZR
;
3990 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3994 inst
.reloc
.exp
.X_op
= O_constant
;
3995 inst
.reloc
.exp
.X_add_number
= 0;
4004 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
4007 parse_address (char **str
, aarch64_opnd_info
*operand
)
4009 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
4010 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
4011 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
4014 /* Parse an address in which SVE vector registers and MUL VL are allowed.
4015 The arguments have the same meaning as for parse_address_main.
4016 Return TRUE on success. */
4018 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
4019 aarch64_opnd_qualifier_t
*base_qualifier
,
4020 aarch64_opnd_qualifier_t
*offset_qualifier
)
4022 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
4023 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
4027 /* Parse a register X0-X30. The register must be 64-bit and register 31
4030 parse_x0_to_x30 (char **str
, aarch64_opnd_info
*operand
)
4032 const reg_entry
*reg
= parse_reg (str
);
4033 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
4035 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
4038 operand
->reg
.regno
= reg
->number
;
4039 operand
->qualifier
= AARCH64_OPND_QLF_X
;
4043 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
4044 Return TRUE on success; otherwise return FALSE. */
4046 parse_half (char **str
, int *internal_fixup_p
)
4050 skip_past_char (&p
, '#');
4052 gas_assert (internal_fixup_p
);
4053 *internal_fixup_p
= 0;
4057 struct reloc_table_entry
*entry
;
4059 /* Try to parse a relocation. Anything else is an error. */
4062 if (!(entry
= find_reloc_table_entry (&p
)))
4064 set_syntax_error (_("unknown relocation modifier"));
4068 if (entry
->movw_type
== 0)
4071 (_("this relocation modifier is not allowed on this instruction"));
4075 inst
.reloc
.type
= entry
->movw_type
;
4078 *internal_fixup_p
= 1;
4080 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4087 /* Parse an operand for an ADRP instruction:
4089 Return TRUE on success; otherwise return FALSE. */
4092 parse_adrp (char **str
)
4099 struct reloc_table_entry
*entry
;
4101 /* Try to parse a relocation. Anything else is an error. */
4103 if (!(entry
= find_reloc_table_entry (&p
)))
4105 set_syntax_error (_("unknown relocation modifier"));
4109 if (entry
->adrp_type
== 0)
4112 (_("this relocation modifier is not allowed on this instruction"));
4116 inst
.reloc
.type
= entry
->adrp_type
;
4119 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4121 inst
.reloc
.pc_rel
= 1;
4122 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4128 /* Miscellaneous. */
4130 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4131 of SIZE tokens in which index I gives the token for field value I,
4132 or is null if field value I is invalid. REG_TYPE says which register
4133 names should be treated as registers rather than as symbolic immediates.
4135 Return true on success, moving *STR past the operand and storing the
4136 field value in *VAL. */
4139 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4140 size_t size
, aarch64_reg_type reg_type
)
4146 /* Match C-like tokens. */
4148 while (ISALNUM (*q
))
4151 for (i
= 0; i
< size
; ++i
)
4153 && strncasecmp (array
[i
], p
, q
- p
) == 0
4154 && array
[i
][q
- p
] == 0)
4161 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4164 if (exp
.X_op
== O_constant
4165 && (uint64_t) exp
.X_add_number
< size
)
4167 *val
= exp
.X_add_number
;
4172 /* Use the default error for this operand. */
4176 /* Parse an option for a preload instruction. Returns the encoding for the
4177 option, or PARSE_FAIL. */
4180 parse_pldop (char **str
)
4183 const struct aarch64_name_value_pair
*o
;
4186 while (ISALNUM (*q
))
4189 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4197 /* Parse an option for a barrier instruction. Returns the encoding for the
4198 option, or PARSE_FAIL. */
4201 parse_barrier (char **str
)
4204 const struct aarch64_name_value_pair
*o
;
4207 while (ISALPHA (*q
))
4210 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4218 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4219 return 0 if successful. Otherwise return PARSE_FAIL. */
4222 parse_barrier_psb (char **str
,
4223 const struct aarch64_name_value_pair
** hint_opt
)
4226 const struct aarch64_name_value_pair
*o
;
4229 while (ISALPHA (*q
))
4232 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4235 set_fatal_syntax_error
4236 ( _("unknown or missing option to PSB/TSB"));
4240 if (o
->value
!= 0x11)
4242 /* PSB only accepts option name 'CSYNC'. */
4244 (_("the specified option is not accepted for PSB/TSB"));
4253 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4254 return 0 if successful. Otherwise return PARSE_FAIL. */
4257 parse_bti_operand (char **str
,
4258 const struct aarch64_name_value_pair
** hint_opt
)
4261 const struct aarch64_name_value_pair
*o
;
4264 while (ISALPHA (*q
))
4267 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4270 set_fatal_syntax_error
4271 ( _("unknown option to BTI"));
4277 /* Valid BTI operands. */
4285 (_("unknown option to BTI"));
4294 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4295 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4300 Side effect: Update STR with current parse position of success.
4303 static const reg_entry
*
4304 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4305 aarch64_opnd_qualifier_t
*qualifier
)
4309 reg_entry
*reg
= parse_reg (str
);
4310 if (reg
!= NULL
&& aarch64_check_reg_type (reg
, reg_type
))
4312 if (!skip_past_char (str
, '.'))
4314 set_syntax_error (_("missing ZA tile element size separator"));
4319 switch (TOLOWER (*q
))
4322 *qualifier
= AARCH64_OPND_QLF_S_B
;
4325 *qualifier
= AARCH64_OPND_QLF_S_H
;
4328 *qualifier
= AARCH64_OPND_QLF_S_S
;
4331 *qualifier
= AARCH64_OPND_QLF_S_D
;
4334 *qualifier
= AARCH64_OPND_QLF_S_Q
;
4348 /* Parse SME ZA tile encoded in <ZAda> assembler symbol.
4349 Function return tile QUALIFIER on success.
4351 Tiles are in example format: za[0-9]\.[bhsd]
4353 Function returns <ZAda> register number or PARSE_FAIL.
4356 parse_sme_zada_operand (char **str
, aarch64_opnd_qualifier_t
*qualifier
)
4359 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_ZAT
, qualifier
);
4363 regno
= reg
->number
;
4367 case AARCH64_OPND_QLF_S_B
:
4370 set_syntax_error (_("invalid ZA tile register number, expected za0"));
4374 case AARCH64_OPND_QLF_S_H
:
4377 set_syntax_error (_("invalid ZA tile register number, expected za0-za1"));
4381 case AARCH64_OPND_QLF_S_S
:
4384 /* For the 32-bit variant: is the name of the ZA tile ZA0-ZA3. */
4385 set_syntax_error (_("invalid ZA tile register number, expected za0-za3"));
4389 case AARCH64_OPND_QLF_S_D
:
4392 /* For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 */
4393 set_syntax_error (_("invalid ZA tile register number, expected za0-za7"));
4398 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s and d"));
4405 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4410 Function return TRUE if immediate was found, or FALSE.
4413 parse_sme_immediate (char **str
, int64_t *imm
)
4416 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4423 /* Parse index with vector select register and immediate:
4427 where <Wv> is in W12-W15 range and # is optional for immediate.
4429 Function performs extra check for mandatory immediate value if REQUIRE_IMM
4432 On success function returns TRUE and populated VECTOR_SELECT_REGISTER and
4436 parse_sme_za_hv_tiles_operand_index (char **str
,
4437 int *vector_select_register
,
4440 const reg_entry
*reg
;
4442 if (!skip_past_char (str
, '['))
4444 set_syntax_error (_("expected '['"));
4448 /* Vector select register W12-W15 encoded in the 2-bit Rv field. */
4449 reg
= parse_reg (str
);
4450 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
4451 || reg
->number
< 12 || reg
->number
> 15)
4453 set_syntax_error (_("expected vector select register W12-W15"));
4456 *vector_select_register
= reg
->number
;
4458 if (!skip_past_char (str
, ',')) /* Optional index offset immediate. */
4460 set_syntax_error (_("expected ','"));
4464 if (!parse_sme_immediate (str
, imm
))
4466 set_syntax_error (_("index offset immediate expected"));
4470 if (!skip_past_char (str
, ']'))
4472 set_syntax_error (_("expected ']'"));
4479 /* Parse SME ZA horizontal or vertical vector access to tiles.
4480 Function extracts from STR to SLICE_INDICATOR <HV> horizontal (0) or
4481 vertical (1) ZA tile vector orientation. VECTOR_SELECT_REGISTER
4482 contains <Wv> select register and corresponding optional IMMEDIATE.
4483 In addition QUALIFIER is extracted.
4485 Field format examples:
4487 ZA0<HV>.B[<Wv>, #<imm>]
4488 <ZAn><HV>.H[<Wv>, #<imm>]
4489 <ZAn><HV>.S[<Wv>, #<imm>]
4490 <ZAn><HV>.D[<Wv>, #<imm>]
4491 <ZAn><HV>.Q[<Wv>, #<imm>]
4493 Function returns <ZAda> register number or PARSE_FAIL.
4496 parse_sme_za_hv_tiles_operand (char **str
,
4497 enum sme_hv_slice
*slice_indicator
,
4498 int *vector_select_register
,
4500 aarch64_opnd_qualifier_t
*qualifier
)
4506 const reg_entry
*reg
;
4508 reg
= parse_reg_with_qual (str
, REG_TYPE_ZATHV
, qualifier
);
4512 *slice_indicator
= (aarch64_check_reg_type (reg
, REG_TYPE_ZATH
)
4515 regno
= reg
->number
;
4519 case AARCH64_OPND_QLF_S_B
:
4523 case AARCH64_OPND_QLF_S_H
:
4527 case AARCH64_OPND_QLF_S_S
:
4531 case AARCH64_OPND_QLF_S_D
:
4535 case AARCH64_OPND_QLF_S_Q
:
4540 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q"));
4544 /* Check if destination register ZA tile vector is in range for given
4545 instruction variant. */
4546 if (regno
< 0 || regno
> regno_limit
)
4548 set_syntax_error (_("ZA tile vector out of range"));
4552 if (!parse_sme_za_hv_tiles_operand_index (str
, vector_select_register
,
4556 /* Check if optional index offset is in the range for instruction
4558 if (imm_value
< 0 || imm_value
> imm_limit
)
4560 set_syntax_error (_("index offset out of range"));
4571 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4572 enum sme_hv_slice
*slice_indicator
,
4573 int *vector_select_register
,
4575 aarch64_opnd_qualifier_t
*qualifier
)
4579 if (!skip_past_char (str
, '{'))
4581 set_syntax_error (_("expected '{'"));
4585 regno
= parse_sme_za_hv_tiles_operand (str
, slice_indicator
,
4586 vector_select_register
, imm
,
4589 if (regno
== PARSE_FAIL
)
4592 if (!skip_past_char (str
, '}'))
4594 set_syntax_error (_("expected '}'"));
4601 /* Parse list of up to eight 64-bit element tile names separated by commas in
4602 SME's ZERO instruction:
4606 Function returns <mask>:
4608 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4611 parse_sme_zero_mask(char **str
)
4615 aarch64_opnd_qualifier_t qualifier
;
4621 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZAT
,
4625 int regno
= reg
->number
;
4626 if (qualifier
== AARCH64_OPND_QLF_S_B
&& regno
== 0)
4628 /* { ZA0.B } is assembled as all-ones immediate. */
4631 else if (qualifier
== AARCH64_OPND_QLF_S_H
&& regno
< 2)
4632 mask
|= 0x55 << regno
;
4633 else if (qualifier
== AARCH64_OPND_QLF_S_S
&& regno
< 4)
4634 mask
|= 0x11 << regno
;
4635 else if (qualifier
== AARCH64_OPND_QLF_S_D
&& regno
< 8)
4636 mask
|= 0x01 << regno
;
4639 set_syntax_error (_("wrong ZA tile element format"));
4644 else if (strncasecmp (q
, "za", 2) == 0
4647 /* { ZA } is assembled as all-ones immediate. */
4654 set_syntax_error (_("wrong ZA tile element format"));
4658 while (skip_past_char (&q
, ','));
4664 /* Wraps in curly braces <mask> operand ZERO instruction:
4668 Function returns value of <mask> bit-field.
4671 parse_sme_list_of_64bit_tiles (char **str
)
4675 if (!skip_past_char (str
, '{'))
4677 set_syntax_error (_("expected '{'"));
4681 /* Empty <mask> list is an all-zeros immediate. */
4682 if (!skip_past_char (str
, '}'))
4684 regno
= parse_sme_zero_mask (str
);
4685 if (regno
== PARSE_FAIL
)
4688 if (!skip_past_char (str
, '}'))
4690 set_syntax_error (_("expected '}'"));
4700 /* Parse ZA array operand used in e.g. STR and LDR instruction.
4706 Function returns <Wv> or PARSE_FAIL.
4709 parse_sme_za_array (char **str
, int *imm
)
4716 while (ISALPHA (*q
))
4719 if ((q
- p
!= 2) || strncasecmp ("za", p
, q
- p
) != 0)
4721 set_syntax_error (_("expected ZA array"));
4725 if (! parse_sme_za_hv_tiles_operand_index (&q
, ®no
, &imm_value
))
4728 if (imm_value
< 0 || imm_value
> 15)
4730 set_syntax_error (_("offset out of range"));
4739 /* Parse streaming mode operand for SMSTART and SMSTOP.
4743 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4746 parse_sme_sm_za (char **str
)
4751 while (ISALPHA (*q
))
4755 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4757 set_syntax_error (_("expected SM or ZA operand"));
4762 return TOLOWER (p
[0]);
4765 /* Parse the name of the source scalable predicate register, the index base
4766 register W12-W15 and the element index. Function performs element index
4767 limit checks as well as qualifier type checks.
4769 <Pn>.<T>[<Wv>, <imm>]
4770 <Pn>.<T>[<Wv>, #<imm>]
4772 On success function sets <Wv> to INDEX_BASE_REG, <T> to QUALIFIER and
4774 Function returns <Pn>, or PARSE_FAIL.
4777 parse_sme_pred_reg_with_index(char **str
,
4778 int *index_base_reg
,
4780 aarch64_opnd_qualifier_t
*qualifier
)
4785 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_PN
, qualifier
);
4789 regno
= reg
->number
;
4793 case AARCH64_OPND_QLF_S_B
:
4796 case AARCH64_OPND_QLF_S_H
:
4799 case AARCH64_OPND_QLF_S_S
:
4802 case AARCH64_OPND_QLF_S_D
:
4806 set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d"));
4810 if (! parse_sme_za_hv_tiles_operand_index (str
, index_base_reg
, &imm_value
))
4813 if (imm_value
< 0 || imm_value
> imm_limit
)
4815 set_syntax_error (_("element index out of range for given variant"));
4824 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4825 Returns the encoding for the option, or PARSE_FAIL.
4827 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4828 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4830 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4831 field, otherwise as a system register.
4835 parse_sys_reg (char **str
, htab_t sys_regs
,
4836 int imple_defined_p
, int pstatefield_p
,
4840 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4841 const aarch64_sys_reg
*o
;
4845 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4846 if (p
< buf
+ (sizeof (buf
) - 1))
4847 *p
++ = TOLOWER (*q
);
4850 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4851 valid system register. This is enforced by construction of the hash
4853 if (p
- buf
!= q
- *str
)
4856 o
= str_hash_find (sys_regs
, buf
);
4859 if (!imple_defined_p
)
4863 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4864 unsigned int op0
, op1
, cn
, cm
, op2
;
4866 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4869 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4871 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4878 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4879 as_bad (_("selected processor does not support PSTATE field "
4882 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4883 o
->value
, o
->flags
, o
->features
))
4884 as_bad (_("selected processor does not support system register "
4886 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4887 as_warn (_("system register name '%s' is deprecated and may be "
4888 "removed in a future release"), buf
);
4898 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4899 for the option, or NULL. */
4901 static const aarch64_sys_ins_reg
*
4902 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4905 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4906 const aarch64_sys_ins_reg
*o
;
4909 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4910 if (p
< buf
+ (sizeof (buf
) - 1))
4911 *p
++ = TOLOWER (*q
);
4914 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4915 valid system register. This is enforced by construction of the hash
4917 if (p
- buf
!= q
- *str
)
4920 o
= str_hash_find (sys_ins_regs
, buf
);
4924 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4925 o
->name
, o
->value
, o
->flags
, 0))
4926 as_bad (_("selected processor does not support system register "
4928 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4929 as_warn (_("system register name '%s' is deprecated and may be "
4930 "removed in a future release"), buf
);
4936 #define po_char_or_fail(chr) do { \
4937 if (! skip_past_char (&str, chr)) \
4941 #define po_reg_or_fail(regtype) do { \
4942 reg = aarch64_reg_parse (&str, regtype, NULL); \
4945 set_default_error (); \
4950 #define po_int_reg_or_fail(reg_type) do { \
4951 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4952 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4954 set_default_error (); \
4957 info->reg.regno = reg->number; \
4958 info->qualifier = qualifier; \
4961 #define po_imm_nc_or_fail() do { \
4962 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4966 #define po_imm_or_fail(min, max) do { \
4967 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4969 if (val < min || val > max) \
4971 set_fatal_syntax_error (_("immediate value out of range "\
4972 #min " to "#max)); \
4977 #define po_enum_or_fail(array) do { \
4978 if (!parse_enum_string (&str, &val, array, \
4979 ARRAY_SIZE (array), imm_reg_type)) \
4983 #define po_misc_or_fail(expr) do { \
4988 /* encode the 12-bit imm field of Add/sub immediate */
4989 static inline uint32_t
4990 encode_addsub_imm (uint32_t imm
)
4995 /* encode the shift amount field of Add/sub immediate */
4996 static inline uint32_t
4997 encode_addsub_imm_shift_amount (uint32_t cnt
)
5003 /* encode the imm field of Adr instruction */
5004 static inline uint32_t
5005 encode_adr_imm (uint32_t imm
)
5007 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
5008 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
5011 /* encode the immediate field of Move wide immediate */
5012 static inline uint32_t
5013 encode_movw_imm (uint32_t imm
)
5018 /* encode the 26-bit offset of unconditional branch */
5019 static inline uint32_t
5020 encode_branch_ofs_26 (uint32_t ofs
)
5022 return ofs
& ((1 << 26) - 1);
5025 /* encode the 19-bit offset of conditional branch and compare & branch */
5026 static inline uint32_t
5027 encode_cond_branch_ofs_19 (uint32_t ofs
)
5029 return (ofs
& ((1 << 19) - 1)) << 5;
5032 /* encode the 19-bit offset of ld literal */
5033 static inline uint32_t
5034 encode_ld_lit_ofs_19 (uint32_t ofs
)
5036 return (ofs
& ((1 << 19) - 1)) << 5;
5039 /* Encode the 14-bit offset of test & branch. */
5040 static inline uint32_t
5041 encode_tst_branch_ofs_14 (uint32_t ofs
)
5043 return (ofs
& ((1 << 14) - 1)) << 5;
5046 /* Encode the 16-bit imm field of svc/hvc/smc. */
5047 static inline uint32_t
5048 encode_svc_imm (uint32_t imm
)
5053 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
5054 static inline uint32_t
5055 reencode_addsub_switch_add_sub (uint32_t opcode
)
5057 return opcode
^ (1 << 30);
5060 static inline uint32_t
5061 reencode_movzn_to_movz (uint32_t opcode
)
5063 return opcode
| (1 << 30);
5066 static inline uint32_t
5067 reencode_movzn_to_movn (uint32_t opcode
)
5069 return opcode
& ~(1 << 30);
5072 /* Overall per-instruction processing. */
5074 /* We need to be able to fix up arbitrary expressions in some statements.
5075 This is so that we can handle symbols that are an arbitrary distance from
5076 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
5077 which returns part of an address in a form which will be valid for
5078 a data instruction. We do this by pushing the expression into a symbol
5079 in the expr_section, and creating a fix for that. */
5082 fix_new_aarch64 (fragS
* frag
,
5097 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
5101 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
5108 /* Diagnostics on operands errors. */
5110 /* By default, output verbose error message.
5111 Disable the verbose error message by -mno-verbose-error. */
5112 static int verbose_error_p
= 1;
5114 #ifdef DEBUG_AARCH64
5115 /* N.B. this is only for the purpose of debugging. */
5116 const char* operand_mismatch_kind_names
[] =
5119 "AARCH64_OPDE_RECOVERABLE",
5120 "AARCH64_OPDE_A_SHOULD_FOLLOW_B",
5121 "AARCH64_OPDE_EXPECTED_A_AFTER_B",
5122 "AARCH64_OPDE_SYNTAX_ERROR",
5123 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5124 "AARCH64_OPDE_INVALID_VARIANT",
5125 "AARCH64_OPDE_OUT_OF_RANGE",
5126 "AARCH64_OPDE_UNALIGNED",
5127 "AARCH64_OPDE_REG_LIST",
5128 "AARCH64_OPDE_OTHER_ERROR",
5130 #endif /* DEBUG_AARCH64 */
5132 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5134 When multiple errors of different kinds are found in the same assembly
5135 line, only the error of the highest severity will be picked up for
5136 issuing the diagnostics. */
5139 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5140 enum aarch64_operand_error_kind rhs
)
5142 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5143 gas_assert (AARCH64_OPDE_A_SHOULD_FOLLOW_B
> AARCH64_OPDE_RECOVERABLE
);
5144 gas_assert (AARCH64_OPDE_EXPECTED_A_AFTER_B
> AARCH64_OPDE_RECOVERABLE
);
5145 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_A_SHOULD_FOLLOW_B
);
5146 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_EXPECTED_A_AFTER_B
);
5147 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5148 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5149 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
5150 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5151 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
5152 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
5156 /* Helper routine to get the mnemonic name from the assembly instruction
5157 line; should only be called for the diagnosis purpose, as there is
5158 string copy operation involved, which may affect the runtime
5159 performance if used in elsewhere. */
5162 get_mnemonic_name (const char *str
)
5164 static char mnemonic
[32];
5167 /* Get the first 15 bytes and assume that the full name is included. */
5168 strncpy (mnemonic
, str
, 31);
5169 mnemonic
[31] = '\0';
5171 /* Scan up to the end of the mnemonic, which must end in white space,
5172 '.', or end of string. */
5173 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5178 /* Append '...' to the truncated long name. */
5179 if (ptr
- mnemonic
== 31)
5180 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5186 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5188 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5189 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5192 /* Data structures storing one user error in the assembly code related to
5195 struct operand_error_record
5197 const aarch64_opcode
*opcode
;
5198 aarch64_operand_error detail
;
5199 struct operand_error_record
*next
;
5202 typedef struct operand_error_record operand_error_record
;
5204 struct operand_errors
5206 operand_error_record
*head
;
5207 operand_error_record
*tail
;
5210 typedef struct operand_errors operand_errors
;
5212 /* Top-level data structure reporting user errors for the current line of
5214 The way md_assemble works is that all opcodes sharing the same mnemonic
5215 name are iterated to find a match to the assembly line. In this data
5216 structure, each of the such opcodes will have one operand_error_record
5217 allocated and inserted. In other words, excessive errors related with
5218 a single opcode are disregarded. */
5219 operand_errors operand_error_report
;
5221 /* Free record nodes. */
5222 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5224 /* Initialize the data structure that stores the operand mismatch
5225 information on assembling one line of the assembly code. */
5227 init_operand_error_report (void)
5229 if (operand_error_report
.head
!= NULL
)
5231 gas_assert (operand_error_report
.tail
!= NULL
);
5232 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5233 free_opnd_error_record_nodes
= operand_error_report
.head
;
5234 operand_error_report
.head
= NULL
;
5235 operand_error_report
.tail
= NULL
;
5238 gas_assert (operand_error_report
.tail
== NULL
);
5241 /* Return TRUE if some operand error has been recorded during the
5242 parsing of the current assembly line using the opcode *OPCODE;
5243 otherwise return FALSE. */
5245 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5247 operand_error_record
*record
= operand_error_report
.head
;
5248 return record
&& record
->opcode
== opcode
;
5251 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5252 OPCODE field is initialized with OPCODE.
5253 N.B. only one record for each opcode, i.e. the maximum of one error is
5254 recorded for each instruction template. */
5257 add_operand_error_record (const operand_error_record
* new_record
)
5259 const aarch64_opcode
*opcode
= new_record
->opcode
;
5260 operand_error_record
* record
= operand_error_report
.head
;
5262 /* The record may have been created for this opcode. If not, we need
5264 if (! opcode_has_operand_error_p (opcode
))
5266 /* Get one empty record. */
5267 if (free_opnd_error_record_nodes
== NULL
)
5269 record
= XNEW (operand_error_record
);
5273 record
= free_opnd_error_record_nodes
;
5274 free_opnd_error_record_nodes
= record
->next
;
5276 record
->opcode
= opcode
;
5277 /* Insert at the head. */
5278 record
->next
= operand_error_report
.head
;
5279 operand_error_report
.head
= record
;
5280 if (operand_error_report
.tail
== NULL
)
5281 operand_error_report
.tail
= record
;
5283 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5284 && record
->detail
.index
<= new_record
->detail
.index
5285 && operand_error_higher_severity_p (record
->detail
.kind
,
5286 new_record
->detail
.kind
))
5288 /* In the case of multiple errors found on operands related with a
5289 single opcode, only record the error of the leftmost operand and
5290 only if the error is of higher severity. */
5291 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5292 " the existing error %s on operand %d",
5293 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5294 new_record
->detail
.index
,
5295 operand_mismatch_kind_names
[record
->detail
.kind
],
5296 record
->detail
.index
);
5300 record
->detail
= new_record
->detail
;
5304 record_operand_error_info (const aarch64_opcode
*opcode
,
5305 aarch64_operand_error
*error_info
)
5307 operand_error_record record
;
5308 record
.opcode
= opcode
;
5309 record
.detail
= *error_info
;
5310 add_operand_error_record (&record
);
5313 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5314 error message *ERROR, for operand IDX (count from 0). */
5317 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5318 enum aarch64_operand_error_kind kind
,
5321 aarch64_operand_error info
;
5322 memset(&info
, 0, sizeof (info
));
5326 info
.non_fatal
= false;
5327 record_operand_error_info (opcode
, &info
);
5331 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5332 enum aarch64_operand_error_kind kind
,
5333 const char* error
, const int *extra_data
)
5335 aarch64_operand_error info
;
5339 info
.data
[0].i
= extra_data
[0];
5340 info
.data
[1].i
= extra_data
[1];
5341 info
.data
[2].i
= extra_data
[2];
5342 info
.non_fatal
= false;
5343 record_operand_error_info (opcode
, &info
);
5347 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5348 const char* error
, int lower_bound
,
5351 int data
[3] = {lower_bound
, upper_bound
, 0};
5352 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5356 /* Remove the operand error record for *OPCODE. */
5357 static void ATTRIBUTE_UNUSED
5358 remove_operand_error_record (const aarch64_opcode
*opcode
)
5360 if (opcode_has_operand_error_p (opcode
))
5362 operand_error_record
* record
= operand_error_report
.head
;
5363 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5364 operand_error_report
.head
= record
->next
;
5365 record
->next
= free_opnd_error_record_nodes
;
5366 free_opnd_error_record_nodes
= record
;
5367 if (operand_error_report
.head
== NULL
)
5369 gas_assert (operand_error_report
.tail
== record
);
5370 operand_error_report
.tail
= NULL
;
5375 /* Given the instruction in *INSTR, return the index of the best matched
5376 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5378 Return -1 if there is no qualifier sequence; return the first match
5379 if there is multiple matches found. */
5382 find_best_match (const aarch64_inst
*instr
,
5383 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5385 int i
, num_opnds
, max_num_matched
, idx
;
5387 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5390 DEBUG_TRACE ("no operand");
5394 max_num_matched
= 0;
5397 /* For each pattern. */
5398 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5401 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5403 /* Most opcodes has much fewer patterns in the list. */
5404 if (empty_qualifier_sequence_p (qualifiers
))
5406 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5410 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5411 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5414 if (num_matched
> max_num_matched
)
5416 max_num_matched
= num_matched
;
5421 DEBUG_TRACE ("return with %d", idx
);
5425 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5426 corresponding operands in *INSTR. */
5429 assign_qualifier_sequence (aarch64_inst
*instr
,
5430 const aarch64_opnd_qualifier_t
*qualifiers
)
5433 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5434 gas_assert (num_opnds
);
5435 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5436 instr
->operands
[i
].qualifier
= *qualifiers
;
5439 /* Callback used by aarch64_print_operand to apply STYLE to the
5440 disassembler output created from FMT and ARGS. The STYLER object holds
5441 any required state. Must return a pointer to a string (created from FMT
5442 and ARGS) that will continue to be valid until the complete disassembled
5443 instruction has been printed.
5445 We don't currently add any styling to the output of the disassembler as
5446 used within assembler error messages, and so STYLE is ignored here. A
5447 new string is allocated on the obstack help within STYLER and returned
5450 static const char *aarch64_apply_style
5451 (struct aarch64_styler
*styler
,
5452 enum disassembler_style style ATTRIBUTE_UNUSED
,
5453 const char *fmt
, va_list args
)
5457 struct obstack
*stack
= (struct obstack
*) styler
->state
;
5460 /* Calculate the required space. */
5462 res
= vsnprintf (NULL
, 0, fmt
, ap
);
5464 gas_assert (res
>= 0);
5466 /* Allocate space on the obstack and format the result. */
5467 ptr
= (char *) obstack_alloc (stack
, res
+ 1);
5468 res
= vsnprintf (ptr
, (res
+ 1), fmt
, args
);
5469 gas_assert (res
>= 0);
5474 /* Print operands for the diagnosis purpose. */
5477 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5478 const aarch64_opnd_info
*opnds
)
5481 struct aarch64_styler styler
;
5482 struct obstack content
;
5483 obstack_init (&content
);
5485 styler
.apply_style
= aarch64_apply_style
;
5486 styler
.state
= (void *) &content
;
5488 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5493 /* We regard the opcode operand info more, however we also look into
5494 the inst->operands to support the disassembling of the optional
5496 The two operand code should be the same in all cases, apart from
5497 when the operand can be optional. */
5498 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5499 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5502 /* Generate the operand string in STR. */
5503 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5504 NULL
, cmt
, sizeof (cmt
), cpu_variant
, &styler
);
5508 strcat (buf
, i
== 0 ? " " : ", ");
5510 /* Append the operand string. */
5513 /* Append a comment. This works because only the last operand ever
5514 adds a comment. If that ever changes then we'll need to be
5518 strcat (buf
, "\t// ");
5523 obstack_free (&content
, NULL
);
5526 /* Send to stderr a string as information. */
5529 output_info (const char *format
, ...)
5535 file
= as_where (&line
);
5539 fprintf (stderr
, "%s:%u: ", file
, line
);
5541 fprintf (stderr
, "%s: ", file
);
5543 fprintf (stderr
, _("Info: "));
5544 va_start (args
, format
);
5545 vfprintf (stderr
, format
, args
);
5547 (void) putc ('\n', stderr
);
5550 /* Output one operand error record. */
5553 output_operand_error_record (const operand_error_record
*record
, char *str
)
5555 const aarch64_operand_error
*detail
= &record
->detail
;
5556 int idx
= detail
->index
;
5557 const aarch64_opcode
*opcode
= record
->opcode
;
5558 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5559 : AARCH64_OPND_NIL
);
5561 typedef void (*handler_t
)(const char *format
, ...);
5562 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5564 switch (detail
->kind
)
5566 case AARCH64_OPDE_NIL
:
5570 case AARCH64_OPDE_A_SHOULD_FOLLOW_B
:
5571 handler (_("this `%s' should have an immediately preceding `%s'"
5573 detail
->data
[0].s
, detail
->data
[1].s
, str
);
5576 case AARCH64_OPDE_EXPECTED_A_AFTER_B
:
5577 handler (_("the preceding `%s' should be followed by `%s` rather"
5578 " than `%s` -- `%s'"),
5579 detail
->data
[1].s
, detail
->data
[0].s
, opcode
->name
, str
);
5582 case AARCH64_OPDE_SYNTAX_ERROR
:
5583 case AARCH64_OPDE_RECOVERABLE
:
5584 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5585 case AARCH64_OPDE_OTHER_ERROR
:
5586 /* Use the prepared error message if there is, otherwise use the
5587 operand description string to describe the error. */
5588 if (detail
->error
!= NULL
)
5591 handler (_("%s -- `%s'"), detail
->error
, str
);
5593 handler (_("%s at operand %d -- `%s'"),
5594 detail
->error
, idx
+ 1, str
);
5598 gas_assert (idx
>= 0);
5599 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5600 aarch64_get_operand_desc (opd_code
), str
);
5604 case AARCH64_OPDE_INVALID_VARIANT
:
5605 handler (_("operand mismatch -- `%s'"), str
);
5606 if (verbose_error_p
)
5608 /* We will try to correct the erroneous instruction and also provide
5609 more information e.g. all other valid variants.
5611 The string representation of the corrected instruction and other
5612 valid variants are generated by
5614 1) obtaining the intermediate representation of the erroneous
5616 2) manipulating the IR, e.g. replacing the operand qualifier;
5617 3) printing out the instruction by calling the printer functions
5618 shared with the disassembler.
5620 The limitation of this method is that the exact input assembly
5621 line cannot be accurately reproduced in some cases, for example an
5622 optional operand present in the actual assembly line will be
5623 omitted in the output; likewise for the optional syntax rules,
5624 e.g. the # before the immediate. Another limitation is that the
5625 assembly symbols and relocation operations in the assembly line
5626 currently cannot be printed out in the error report. Last but not
5627 least, when there is other error(s) co-exist with this error, the
5628 'corrected' instruction may be still incorrect, e.g. given
5629 'ldnp h0,h1,[x0,#6]!'
5630 this diagnosis will provide the version:
5631 'ldnp s0,s1,[x0,#6]!'
5632 which is still not right. */
5633 size_t len
= strlen (get_mnemonic_name (str
));
5637 aarch64_inst
*inst_base
= &inst
.base
;
5638 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5641 reset_aarch64_instruction (&inst
);
5642 inst_base
->opcode
= opcode
;
5644 /* Reset the error report so that there is no side effect on the
5645 following operand parsing. */
5646 init_operand_error_report ();
5649 result
= parse_operands (str
+ len
, opcode
)
5650 && programmer_friendly_fixup (&inst
);
5651 gas_assert (result
);
5652 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5653 NULL
, NULL
, insn_sequence
);
5654 gas_assert (!result
);
5656 /* Find the most matched qualifier sequence. */
5657 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5658 gas_assert (qlf_idx
> -1);
5660 /* Assign the qualifiers. */
5661 assign_qualifier_sequence (inst_base
,
5662 opcode
->qualifiers_list
[qlf_idx
]);
5664 /* Print the hint. */
5665 output_info (_(" did you mean this?"));
5666 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5667 print_operands (buf
, opcode
, inst_base
->operands
);
5668 output_info (_(" %s"), buf
);
5670 /* Print out other variant(s) if there is any. */
5672 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5673 output_info (_(" other valid variant(s):"));
5675 /* For each pattern. */
5676 qualifiers_list
= opcode
->qualifiers_list
;
5677 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5679 /* Most opcodes has much fewer patterns in the list.
5680 First NIL qualifier indicates the end in the list. */
5681 if (empty_qualifier_sequence_p (*qualifiers_list
))
5686 /* Mnemonics name. */
5687 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5689 /* Assign the qualifiers. */
5690 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5692 /* Print instruction. */
5693 print_operands (buf
, opcode
, inst_base
->operands
);
5695 output_info (_(" %s"), buf
);
5701 case AARCH64_OPDE_UNTIED_IMMS
:
5702 handler (_("operand %d must have the same immediate value "
5703 "as operand 1 -- `%s'"),
5704 detail
->index
+ 1, str
);
5707 case AARCH64_OPDE_UNTIED_OPERAND
:
5708 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5709 detail
->index
+ 1, str
);
5712 case AARCH64_OPDE_OUT_OF_RANGE
:
5713 if (detail
->data
[0].i
!= detail
->data
[1].i
)
5714 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5715 detail
->error
? detail
->error
: _("immediate value"),
5716 detail
->data
[0].i
, detail
->data
[1].i
, idx
+ 1, str
);
5718 handler (_("%s must be %d at operand %d -- `%s'"),
5719 detail
->error
? detail
->error
: _("immediate value"),
5720 detail
->data
[0].i
, idx
+ 1, str
);
5723 case AARCH64_OPDE_REG_LIST
:
5724 if (detail
->data
[0].i
== 1)
5725 handler (_("invalid number of registers in the list; "
5726 "only 1 register is expected at operand %d -- `%s'"),
5729 handler (_("invalid number of registers in the list; "
5730 "%d registers are expected at operand %d -- `%s'"),
5731 detail
->data
[0].i
, idx
+ 1, str
);
5734 case AARCH64_OPDE_UNALIGNED
:
5735 handler (_("immediate value must be a multiple of "
5736 "%d at operand %d -- `%s'"),
5737 detail
->data
[0].i
, idx
+ 1, str
);
5746 /* Process and output the error message about the operand mismatching.
5748 When this function is called, the operand error information had
5749 been collected for an assembly line and there will be multiple
5750 errors in the case of multiple instruction templates; output the
5751 error message that most closely describes the problem.
5753 The errors to be printed can be filtered on printing all errors
5754 or only non-fatal errors. This distinction has to be made because
5755 the error buffer may already be filled with fatal errors we don't want to
5756 print due to the different instruction templates. */
5759 output_operand_error_report (char *str
, bool non_fatal_only
)
5761 int largest_error_pos
;
5762 const char *msg
= NULL
;
5763 enum aarch64_operand_error_kind kind
;
5764 operand_error_record
*curr
;
5765 operand_error_record
*head
= operand_error_report
.head
;
5766 operand_error_record
*record
= NULL
;
5768 /* No error to report. */
5772 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5774 /* Only one error. */
5775 if (head
== operand_error_report
.tail
)
5777 /* If the only error is a non-fatal one and we don't want to print it,
5779 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5781 DEBUG_TRACE ("single opcode entry with error kind: %s",
5782 operand_mismatch_kind_names
[head
->detail
.kind
]);
5783 output_operand_error_record (head
, str
);
5788 /* Find the error kind of the highest severity. */
5789 DEBUG_TRACE ("multiple opcode entries with error kind");
5790 kind
= AARCH64_OPDE_NIL
;
5791 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5793 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5794 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5795 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5796 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5797 kind
= curr
->detail
.kind
;
5800 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5802 /* Pick up one of errors of KIND to report. */
5803 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5804 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5806 /* If we don't want to print non-fatal errors then don't consider them
5808 if (curr
->detail
.kind
!= kind
5809 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5811 /* If there are multiple errors, pick up the one with the highest
5812 mismatching operand index. In the case of multiple errors with
5813 the equally highest operand index, pick up the first one or the
5814 first one with non-NULL error message. */
5815 if (curr
->detail
.index
> largest_error_pos
5816 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5817 && curr
->detail
.error
!= NULL
))
5819 largest_error_pos
= curr
->detail
.index
;
5821 msg
= record
->detail
.error
;
5825 /* The way errors are collected in the back-end is a bit non-intuitive. But
5826 essentially, because each operand template is tried recursively you may
5827 always have errors collected from the previous tried OPND. These are
5828 usually skipped if there is one successful match. However now with the
5829 non-fatal errors we have to ignore those previously collected hard errors
5830 when we're only interested in printing the non-fatal ones. This condition
5831 prevents us from printing errors that are not appropriate, since we did
5832 match a condition, but it also has warnings that it wants to print. */
5833 if (non_fatal_only
&& !record
)
5836 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5837 DEBUG_TRACE ("Pick up error kind %s to report",
5838 operand_mismatch_kind_names
[record
->detail
.kind
]);
5841 output_operand_error_record (record
, str
);
5844 /* Write an AARCH64 instruction to buf - always little-endian. */
5846 put_aarch64_insn (char *buf
, uint32_t insn
)
5848 unsigned char *where
= (unsigned char *) buf
;
5850 where
[1] = insn
>> 8;
5851 where
[2] = insn
>> 16;
5852 where
[3] = insn
>> 24;
5856 get_aarch64_insn (char *buf
)
5858 unsigned char *where
= (unsigned char *) buf
;
5860 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5861 | ((uint32_t) where
[3] << 24)));
5866 output_inst (struct aarch64_inst
*new_inst
)
5870 to
= frag_more (INSN_SIZE
);
5872 frag_now
->tc_frag_data
.recorded
= 1;
5874 put_aarch64_insn (to
, inst
.base
.value
);
5876 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5878 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5879 INSN_SIZE
, &inst
.reloc
.exp
,
5882 DEBUG_TRACE ("Prepared relocation fix up");
5883 /* Don't check the addend value against the instruction size,
5884 that's the job of our code in md_apply_fix(). */
5885 fixp
->fx_no_overflow
= 1;
5886 if (new_inst
!= NULL
)
5887 fixp
->tc_fix_data
.inst
= new_inst
;
5888 if (aarch64_gas_internal_fixup_p ())
5890 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5891 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5892 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5896 dwarf2_emit_insn (INSN_SIZE
);
5899 /* Link together opcodes of the same name. */
5903 const aarch64_opcode
*opcode
;
5904 struct templates
*next
;
5907 typedef struct templates templates
;
5910 lookup_mnemonic (const char *start
, int len
)
5912 templates
*templ
= NULL
;
5914 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5918 /* Subroutine of md_assemble, responsible for looking up the primary
5919 opcode from the mnemonic the user wrote. BASE points to the beginning
5920 of the mnemonic, DOT points to the first '.' within the mnemonic
5921 (if any) and END points to the end of the mnemonic. */
5924 opcode_lookup (char *base
, char *dot
, char *end
)
5926 const aarch64_cond
*cond
;
5933 inst
.cond
= COND_ALWAYS
;
5935 /* Handle a possible condition. */
5938 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5941 inst
.cond
= cond
->value
;
5947 if (inst
.cond
== COND_ALWAYS
)
5949 /* Look for unaffixed mnemonic. */
5950 return lookup_mnemonic (base
, len
);
5954 /* append ".c" to mnemonic if conditional */
5955 memcpy (condname
, base
, len
);
5956 memcpy (condname
+ len
, ".c", 2);
5959 return lookup_mnemonic (base
, len
);
5965 /* Process an optional operand that is found omitted from the assembly line.
5966 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5967 instruction's opcode entry while IDX is the index of this omitted operand.
5971 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5972 int idx
, aarch64_opnd_info
*operand
)
5974 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5975 gas_assert (optional_operand_p (opcode
, idx
));
5976 gas_assert (!operand
->present
);
5980 case AARCH64_OPND_Rd
:
5981 case AARCH64_OPND_Rn
:
5982 case AARCH64_OPND_Rm
:
5983 case AARCH64_OPND_Rt
:
5984 case AARCH64_OPND_Rt2
:
5985 case AARCH64_OPND_Rt_LS64
:
5986 case AARCH64_OPND_Rt_SP
:
5987 case AARCH64_OPND_Rs
:
5988 case AARCH64_OPND_Ra
:
5989 case AARCH64_OPND_Rt_SYS
:
5990 case AARCH64_OPND_Rd_SP
:
5991 case AARCH64_OPND_Rn_SP
:
5992 case AARCH64_OPND_Rm_SP
:
5993 case AARCH64_OPND_Fd
:
5994 case AARCH64_OPND_Fn
:
5995 case AARCH64_OPND_Fm
:
5996 case AARCH64_OPND_Fa
:
5997 case AARCH64_OPND_Ft
:
5998 case AARCH64_OPND_Ft2
:
5999 case AARCH64_OPND_Sd
:
6000 case AARCH64_OPND_Sn
:
6001 case AARCH64_OPND_Sm
:
6002 case AARCH64_OPND_Va
:
6003 case AARCH64_OPND_Vd
:
6004 case AARCH64_OPND_Vn
:
6005 case AARCH64_OPND_Vm
:
6006 case AARCH64_OPND_VdD1
:
6007 case AARCH64_OPND_VnD1
:
6008 operand
->reg
.regno
= default_value
;
6011 case AARCH64_OPND_Ed
:
6012 case AARCH64_OPND_En
:
6013 case AARCH64_OPND_Em
:
6014 case AARCH64_OPND_Em16
:
6015 case AARCH64_OPND_SM3_IMM2
:
6016 operand
->reglane
.regno
= default_value
;
6019 case AARCH64_OPND_IDX
:
6020 case AARCH64_OPND_BIT_NUM
:
6021 case AARCH64_OPND_IMMR
:
6022 case AARCH64_OPND_IMMS
:
6023 case AARCH64_OPND_SHLL_IMM
:
6024 case AARCH64_OPND_IMM_VLSL
:
6025 case AARCH64_OPND_IMM_VLSR
:
6026 case AARCH64_OPND_CCMP_IMM
:
6027 case AARCH64_OPND_FBITS
:
6028 case AARCH64_OPND_UIMM4
:
6029 case AARCH64_OPND_UIMM3_OP1
:
6030 case AARCH64_OPND_UIMM3_OP2
:
6031 case AARCH64_OPND_IMM
:
6032 case AARCH64_OPND_IMM_2
:
6033 case AARCH64_OPND_WIDTH
:
6034 case AARCH64_OPND_UIMM7
:
6035 case AARCH64_OPND_NZCV
:
6036 case AARCH64_OPND_SVE_PATTERN
:
6037 case AARCH64_OPND_SVE_PRFOP
:
6038 operand
->imm
.value
= default_value
;
6041 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6042 operand
->imm
.value
= default_value
;
6043 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
6044 operand
->shifter
.amount
= 1;
6047 case AARCH64_OPND_EXCEPTION
:
6048 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6051 case AARCH64_OPND_BARRIER_ISB
:
6052 operand
->barrier
= aarch64_barrier_options
+ default_value
;
6055 case AARCH64_OPND_BTI_TARGET
:
6056 operand
->hint_option
= aarch64_hint_options
+ default_value
;
6064 /* Process the relocation type for move wide instructions.
6065 Return TRUE on success; otherwise return FALSE. */
6068 process_movw_reloc_info (void)
6073 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
6075 if (inst
.base
.opcode
->op
== OP_MOVK
)
6076 switch (inst
.reloc
.type
)
6078 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6079 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6080 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6081 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6082 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6083 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6084 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6085 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6086 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6087 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6088 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6090 (_("the specified relocation type is not allowed for MOVK"));
6096 switch (inst
.reloc
.type
)
6098 case BFD_RELOC_AARCH64_MOVW_G0
:
6099 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6100 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6101 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6102 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6103 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6104 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6105 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6106 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6107 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6108 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6109 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6110 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6113 case BFD_RELOC_AARCH64_MOVW_G1
:
6114 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6115 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6116 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6117 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6118 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6119 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6120 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6121 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6122 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6123 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6124 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6125 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6128 case BFD_RELOC_AARCH64_MOVW_G2
:
6129 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6130 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6131 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6132 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6133 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6134 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6137 set_fatal_syntax_error
6138 (_("the specified relocation type is not allowed for 32-bit "
6144 case BFD_RELOC_AARCH64_MOVW_G3
:
6145 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6148 set_fatal_syntax_error
6149 (_("the specified relocation type is not allowed for 32-bit "
6156 /* More cases should be added when more MOVW-related relocation types
6157 are supported in GAS. */
6158 gas_assert (aarch64_gas_internal_fixup_p ());
6159 /* The shift amount should have already been set by the parser. */
6162 inst
.base
.operands
[1].shifter
.amount
= shift
;
6166 /* A primitive log calculator. */
6168 static inline unsigned int
6169 get_logsz (unsigned int size
)
6171 const unsigned char ls
[16] =
6172 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
6178 gas_assert (ls
[size
- 1] != (unsigned char)-1);
6179 return ls
[size
- 1];
6182 /* Determine and return the real reloc type code for an instruction
6183 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6185 static inline bfd_reloc_code_real_type
6186 ldst_lo12_determine_real_reloc_type (void)
6188 unsigned logsz
, max_logsz
;
6189 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6190 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6192 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6194 BFD_RELOC_AARCH64_LDST8_LO12
,
6195 BFD_RELOC_AARCH64_LDST16_LO12
,
6196 BFD_RELOC_AARCH64_LDST32_LO12
,
6197 BFD_RELOC_AARCH64_LDST64_LO12
,
6198 BFD_RELOC_AARCH64_LDST128_LO12
6201 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6202 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6203 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6204 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6205 BFD_RELOC_AARCH64_NONE
6208 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6209 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6210 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6211 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6212 BFD_RELOC_AARCH64_NONE
6215 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6216 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6217 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6218 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6219 BFD_RELOC_AARCH64_NONE
6222 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6223 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6224 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6225 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6226 BFD_RELOC_AARCH64_NONE
6230 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6231 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6233 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6235 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6237 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6238 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6240 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6242 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6244 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6246 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
6248 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6249 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6250 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6251 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6256 if (logsz
> max_logsz
)
6258 /* SEE PR 27904 for an example of this. */
6259 set_fatal_syntax_error
6260 (_("relocation qualifier does not match instruction size"));
6261 return BFD_RELOC_AARCH64_NONE
;
6264 /* In reloc.c, these pseudo relocation types should be defined in similar
6265 order as above reloc_ldst_lo12 array. Because the array index calculation
6266 below relies on this. */
6267 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6270 /* Check whether a register list REGINFO is valid. The registers must be
6271 numbered in increasing order (modulo 32), in increments of one or two.
6273 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
6276 Return FALSE if such a register list is invalid, otherwise return TRUE. */
6279 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
6281 uint32_t i
, nb_regs
, prev_regno
, incr
;
6283 nb_regs
= 1 + (reginfo
& 0x3);
6285 prev_regno
= reginfo
& 0x1f;
6286 incr
= accept_alternate
? 2 : 1;
6288 for (i
= 1; i
< nb_regs
; ++i
)
6290 uint32_t curr_regno
;
6292 curr_regno
= reginfo
& 0x1f;
6293 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
6295 prev_regno
= curr_regno
;
6301 /* Generic instruction operand parser. This does no encoding and no
6302 semantic validation; it merely squirrels values away in the inst
6303 structure. Returns TRUE or FALSE depending on whether the
6304 specified grammar matched. */
6307 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6310 char *backtrack_pos
= 0;
6311 const enum aarch64_opnd
*operands
= opcode
->operands
;
6312 aarch64_reg_type imm_reg_type
;
6315 skip_whitespace (str
);
6317 if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode
->avariant
,
6319 | AARCH64_FEATURE_SVE2
))
6320 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
6322 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
6324 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6327 const reg_entry
*reg
;
6328 int comma_skipped_p
= 0;
6329 struct vector_type_el vectype
;
6330 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6331 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6332 aarch64_reg_type reg_type
;
6334 DEBUG_TRACE ("parse operand %d", i
);
6336 /* Assign the operand code. */
6337 info
->type
= operands
[i
];
6339 if (optional_operand_p (opcode
, i
))
6341 /* Remember where we are in case we need to backtrack. */
6342 gas_assert (!backtrack_pos
);
6343 backtrack_pos
= str
;
6346 /* Expect comma between operands; the backtrack mechanism will take
6347 care of cases of omitted optional operand. */
6348 if (i
> 0 && ! skip_past_char (&str
, ','))
6350 set_syntax_error (_("comma expected between operands"));
6354 comma_skipped_p
= 1;
6356 switch (operands
[i
])
6358 case AARCH64_OPND_Rd
:
6359 case AARCH64_OPND_Rn
:
6360 case AARCH64_OPND_Rm
:
6361 case AARCH64_OPND_Rt
:
6362 case AARCH64_OPND_Rt2
:
6363 case AARCH64_OPND_Rs
:
6364 case AARCH64_OPND_Ra
:
6365 case AARCH64_OPND_Rt_LS64
:
6366 case AARCH64_OPND_Rt_SYS
:
6367 case AARCH64_OPND_PAIRREG
:
6368 case AARCH64_OPND_SVE_Rm
:
6369 po_int_reg_or_fail (REG_TYPE_R_Z
);
6371 /* In LS64 load/store instructions Rt register number must be even
6373 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6375 /* We've already checked if this is valid register.
6376 This will check if register number (Rt) is not undefined for LS64
6378 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6379 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6381 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6387 case AARCH64_OPND_Rd_SP
:
6388 case AARCH64_OPND_Rn_SP
:
6389 case AARCH64_OPND_Rt_SP
:
6390 case AARCH64_OPND_SVE_Rn_SP
:
6391 case AARCH64_OPND_Rm_SP
:
6392 po_int_reg_or_fail (REG_TYPE_R_SP
);
6395 case AARCH64_OPND_Rm_EXT
:
6396 case AARCH64_OPND_Rm_SFT
:
6397 po_misc_or_fail (parse_shifter_operand
6398 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6400 : SHIFTED_LOGIC_IMM
)));
6401 if (!info
->shifter
.operator_present
)
6403 /* Default to LSL if not present. Libopcodes prefers shifter
6404 kind to be explicit. */
6405 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6406 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6407 /* For Rm_EXT, libopcodes will carry out further check on whether
6408 or not stack pointer is used in the instruction (Recall that
6409 "the extend operator is not optional unless at least one of
6410 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6414 case AARCH64_OPND_Fd
:
6415 case AARCH64_OPND_Fn
:
6416 case AARCH64_OPND_Fm
:
6417 case AARCH64_OPND_Fa
:
6418 case AARCH64_OPND_Ft
:
6419 case AARCH64_OPND_Ft2
:
6420 case AARCH64_OPND_Sd
:
6421 case AARCH64_OPND_Sn
:
6422 case AARCH64_OPND_Sm
:
6423 case AARCH64_OPND_SVE_VZn
:
6424 case AARCH64_OPND_SVE_Vd
:
6425 case AARCH64_OPND_SVE_Vm
:
6426 case AARCH64_OPND_SVE_Vn
:
6427 reg
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, NULL
);
6430 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
6433 gas_assert (reg
->type
>= REG_TYPE_FP_B
6434 && reg
->type
<= REG_TYPE_FP_Q
);
6436 info
->reg
.regno
= reg
->number
;
6437 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (reg
->type
- REG_TYPE_FP_B
);
6440 case AARCH64_OPND_SVE_Pd
:
6441 case AARCH64_OPND_SVE_Pg3
:
6442 case AARCH64_OPND_SVE_Pg4_5
:
6443 case AARCH64_OPND_SVE_Pg4_10
:
6444 case AARCH64_OPND_SVE_Pg4_16
:
6445 case AARCH64_OPND_SVE_Pm
:
6446 case AARCH64_OPND_SVE_Pn
:
6447 case AARCH64_OPND_SVE_Pt
:
6448 case AARCH64_OPND_SME_Pm
:
6449 reg_type
= REG_TYPE_PN
;
6452 case AARCH64_OPND_SVE_Za_5
:
6453 case AARCH64_OPND_SVE_Za_16
:
6454 case AARCH64_OPND_SVE_Zd
:
6455 case AARCH64_OPND_SVE_Zm_5
:
6456 case AARCH64_OPND_SVE_Zm_16
:
6457 case AARCH64_OPND_SVE_Zn
:
6458 case AARCH64_OPND_SVE_Zt
:
6459 reg_type
= REG_TYPE_ZN
;
6462 case AARCH64_OPND_Va
:
6463 case AARCH64_OPND_Vd
:
6464 case AARCH64_OPND_Vn
:
6465 case AARCH64_OPND_Vm
:
6466 reg_type
= REG_TYPE_VN
;
6468 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6471 first_error (_(get_reg_expected_msg (reg_type
)));
6474 if (vectype
.defined
& NTA_HASINDEX
)
6477 info
->reg
.regno
= reg
->number
;
6478 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
6479 && vectype
.type
== NT_invtype
)
6480 /* Unqualified Pn and Zn registers are allowed in certain
6481 contexts. Rely on F_STRICT qualifier checking to catch
6483 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6486 info
->qualifier
= vectype_to_qualifier (&vectype
);
6487 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6492 case AARCH64_OPND_VdD1
:
6493 case AARCH64_OPND_VnD1
:
6494 reg
= aarch64_reg_parse (&str
, REG_TYPE_VN
, &vectype
);
6497 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
6500 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6502 set_fatal_syntax_error
6503 (_("the top half of a 128-bit FP/SIMD register is expected"));
6506 info
->reg
.regno
= reg
->number
;
6507 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6508 here; it is correct for the purpose of encoding/decoding since
6509 only the register number is explicitly encoded in the related
6510 instructions, although this appears a bit hacky. */
6511 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6514 case AARCH64_OPND_SVE_Zm3_INDEX
:
6515 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6516 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6517 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6518 case AARCH64_OPND_SVE_Zm4_INDEX
:
6519 case AARCH64_OPND_SVE_Zn_INDEX
:
6520 reg_type
= REG_TYPE_ZN
;
6521 goto vector_reg_index
;
6523 case AARCH64_OPND_Ed
:
6524 case AARCH64_OPND_En
:
6525 case AARCH64_OPND_Em
:
6526 case AARCH64_OPND_Em16
:
6527 case AARCH64_OPND_SM3_IMM2
:
6528 reg_type
= REG_TYPE_VN
;
6530 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6533 first_error (_(get_reg_expected_msg (reg_type
)));
6536 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6539 info
->reglane
.regno
= reg
->number
;
6540 info
->reglane
.index
= vectype
.index
;
6541 info
->qualifier
= vectype_to_qualifier (&vectype
);
6542 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6546 case AARCH64_OPND_SVE_ZnxN
:
6547 case AARCH64_OPND_SVE_ZtxN
:
6548 reg_type
= REG_TYPE_ZN
;
6549 goto vector_reg_list
;
6551 case AARCH64_OPND_LVn
:
6552 case AARCH64_OPND_LVt
:
6553 case AARCH64_OPND_LVt_AL
:
6554 case AARCH64_OPND_LEt
:
6555 reg_type
= REG_TYPE_VN
;
6557 if (reg_type
== REG_TYPE_ZN
6558 && get_opcode_dependent_value (opcode
) == 1
6561 reg
= aarch64_reg_parse (&str
, reg_type
, &vectype
);
6564 first_error (_(get_reg_expected_msg (reg_type
)));
6567 info
->reglist
.first_regno
= reg
->number
;
6568 info
->reglist
.num_regs
= 1;
6572 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6573 if (val
== PARSE_FAIL
)
6576 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6578 set_fatal_syntax_error (_("invalid register list"));
6582 if (vectype
.width
!= 0 && *str
!= ',')
6584 set_fatal_syntax_error
6585 (_("expected element type rather than vector type"));
6589 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6590 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6592 if (operands
[i
] == AARCH64_OPND_LEt
)
6594 if (!(vectype
.defined
& NTA_HASINDEX
))
6596 info
->reglist
.has_index
= 1;
6597 info
->reglist
.index
= vectype
.index
;
6601 if (vectype
.defined
& NTA_HASINDEX
)
6603 if (!(vectype
.defined
& NTA_HASTYPE
))
6605 if (reg_type
== REG_TYPE_ZN
)
6606 set_fatal_syntax_error (_("missing type suffix"));
6610 info
->qualifier
= vectype_to_qualifier (&vectype
);
6611 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6615 case AARCH64_OPND_CRn
:
6616 case AARCH64_OPND_CRm
:
6618 char prefix
= *(str
++);
6619 if (prefix
!= 'c' && prefix
!= 'C')
6622 po_imm_nc_or_fail ();
6625 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6628 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6629 info
->imm
.value
= val
;
6633 case AARCH64_OPND_SHLL_IMM
:
6634 case AARCH64_OPND_IMM_VLSR
:
6635 po_imm_or_fail (1, 64);
6636 info
->imm
.value
= val
;
6639 case AARCH64_OPND_CCMP_IMM
:
6640 case AARCH64_OPND_SIMM5
:
6641 case AARCH64_OPND_FBITS
:
6642 case AARCH64_OPND_TME_UIMM16
:
6643 case AARCH64_OPND_UIMM4
:
6644 case AARCH64_OPND_UIMM4_ADDG
:
6645 case AARCH64_OPND_UIMM10
:
6646 case AARCH64_OPND_UIMM3_OP1
:
6647 case AARCH64_OPND_UIMM3_OP2
:
6648 case AARCH64_OPND_IMM_VLSL
:
6649 case AARCH64_OPND_IMM
:
6650 case AARCH64_OPND_IMM_2
:
6651 case AARCH64_OPND_WIDTH
:
6652 case AARCH64_OPND_SVE_INV_LIMM
:
6653 case AARCH64_OPND_SVE_LIMM
:
6654 case AARCH64_OPND_SVE_LIMM_MOV
:
6655 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6656 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6657 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6658 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6659 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6660 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6661 case AARCH64_OPND_SVE_SIMM5
:
6662 case AARCH64_OPND_SVE_SIMM5B
:
6663 case AARCH64_OPND_SVE_SIMM6
:
6664 case AARCH64_OPND_SVE_SIMM8
:
6665 case AARCH64_OPND_SVE_UIMM3
:
6666 case AARCH64_OPND_SVE_UIMM7
:
6667 case AARCH64_OPND_SVE_UIMM8
:
6668 case AARCH64_OPND_SVE_UIMM8_53
:
6669 case AARCH64_OPND_IMM_ROT1
:
6670 case AARCH64_OPND_IMM_ROT2
:
6671 case AARCH64_OPND_IMM_ROT3
:
6672 case AARCH64_OPND_SVE_IMM_ROT1
:
6673 case AARCH64_OPND_SVE_IMM_ROT2
:
6674 case AARCH64_OPND_SVE_IMM_ROT3
:
6675 case AARCH64_OPND_CSSC_SIMM8
:
6676 case AARCH64_OPND_CSSC_UIMM8
:
6677 po_imm_nc_or_fail ();
6678 info
->imm
.value
= val
;
6681 case AARCH64_OPND_SVE_AIMM
:
6682 case AARCH64_OPND_SVE_ASIMM
:
6683 po_imm_nc_or_fail ();
6684 info
->imm
.value
= val
;
6685 skip_whitespace (str
);
6686 if (skip_past_comma (&str
))
6687 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6689 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6692 case AARCH64_OPND_SVE_PATTERN
:
6693 po_enum_or_fail (aarch64_sve_pattern_array
);
6694 info
->imm
.value
= val
;
6697 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6698 po_enum_or_fail (aarch64_sve_pattern_array
);
6699 info
->imm
.value
= val
;
6700 if (skip_past_comma (&str
)
6701 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6703 if (!info
->shifter
.operator_present
)
6705 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6706 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6707 info
->shifter
.amount
= 1;
6711 case AARCH64_OPND_SVE_PRFOP
:
6712 po_enum_or_fail (aarch64_sve_prfop_array
);
6713 info
->imm
.value
= val
;
6716 case AARCH64_OPND_UIMM7
:
6717 po_imm_or_fail (0, 127);
6718 info
->imm
.value
= val
;
6721 case AARCH64_OPND_IDX
:
6722 case AARCH64_OPND_MASK
:
6723 case AARCH64_OPND_BIT_NUM
:
6724 case AARCH64_OPND_IMMR
:
6725 case AARCH64_OPND_IMMS
:
6726 po_imm_or_fail (0, 63);
6727 info
->imm
.value
= val
;
6730 case AARCH64_OPND_IMM0
:
6731 po_imm_nc_or_fail ();
6734 set_fatal_syntax_error (_("immediate zero expected"));
6737 info
->imm
.value
= 0;
6740 case AARCH64_OPND_FPIMM0
:
6743 bool res1
= false, res2
= false;
6744 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6745 it is probably not worth the effort to support it. */
6746 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6749 || !(res2
= parse_constant_immediate (&str
, &val
,
6752 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6754 info
->imm
.value
= 0;
6755 info
->imm
.is_fp
= 1;
6758 set_fatal_syntax_error (_("immediate zero expected"));
6762 case AARCH64_OPND_IMM_MOV
:
6765 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6766 reg_name_p (str
, REG_TYPE_VN
))
6769 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6770 GE_OPT_PREFIX
, REJECT_ABSENT
));
6771 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6772 later. fix_mov_imm_insn will try to determine a machine
6773 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6774 message if the immediate cannot be moved by a single
6776 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6777 inst
.base
.operands
[i
].skip
= 1;
6781 case AARCH64_OPND_SIMD_IMM
:
6782 case AARCH64_OPND_SIMD_IMM_SFT
:
6783 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6785 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6787 /* need_libopcodes_p */ 1,
6790 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6791 shift, we don't check it here; we leave the checking to
6792 the libopcodes (operand_general_constraint_met_p). By
6793 doing this, we achieve better diagnostics. */
6794 if (skip_past_comma (&str
)
6795 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6797 if (!info
->shifter
.operator_present
6798 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6800 /* Default to LSL if not present. Libopcodes prefers shifter
6801 kind to be explicit. */
6802 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6803 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6807 case AARCH64_OPND_FPIMM
:
6808 case AARCH64_OPND_SIMD_FPIMM
:
6809 case AARCH64_OPND_SVE_FPIMM8
:
6814 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6815 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6816 || !aarch64_imm_float_p (qfloat
))
6819 set_fatal_syntax_error (_("invalid floating-point"
6823 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6824 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6828 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6829 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6830 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6835 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6836 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6839 set_fatal_syntax_error (_("invalid floating-point"
6843 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6844 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6848 case AARCH64_OPND_LIMM
:
6849 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6850 SHIFTED_LOGIC_IMM
));
6851 if (info
->shifter
.operator_present
)
6853 set_fatal_syntax_error
6854 (_("shift not allowed for bitmask immediate"));
6857 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6859 /* need_libopcodes_p */ 1,
6863 case AARCH64_OPND_AIMM
:
6864 if (opcode
->op
== OP_ADD
)
6865 /* ADD may have relocation types. */
6866 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6867 SHIFTED_ARITH_IMM
));
6869 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6870 SHIFTED_ARITH_IMM
));
6871 switch (inst
.reloc
.type
)
6873 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6874 info
->shifter
.amount
= 12;
6876 case BFD_RELOC_UNUSED
:
6877 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6878 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6879 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6880 inst
.reloc
.pc_rel
= 0;
6885 info
->imm
.value
= 0;
6886 if (!info
->shifter
.operator_present
)
6888 /* Default to LSL if not present. Libopcodes prefers shifter
6889 kind to be explicit. */
6890 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6891 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6895 case AARCH64_OPND_HALF
:
6897 /* #<imm16> or relocation. */
6898 int internal_fixup_p
;
6899 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6900 if (internal_fixup_p
)
6901 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6902 skip_whitespace (str
);
6903 if (skip_past_comma (&str
))
6905 /* {, LSL #<shift>} */
6906 if (! aarch64_gas_internal_fixup_p ())
6908 set_fatal_syntax_error (_("can't mix relocation modifier "
6909 "with explicit shift"));
6912 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6915 inst
.base
.operands
[i
].shifter
.amount
= 0;
6916 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6917 inst
.base
.operands
[i
].imm
.value
= 0;
6918 if (! process_movw_reloc_info ())
6923 case AARCH64_OPND_EXCEPTION
:
6924 case AARCH64_OPND_UNDEFINED
:
6925 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6927 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6929 /* need_libopcodes_p */ 0,
6933 case AARCH64_OPND_NZCV
:
6935 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6939 info
->imm
.value
= nzcv
->value
;
6942 po_imm_or_fail (0, 15);
6943 info
->imm
.value
= val
;
6947 case AARCH64_OPND_COND
:
6948 case AARCH64_OPND_COND1
:
6953 while (ISALPHA (*str
));
6954 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6955 if (info
->cond
== NULL
)
6957 set_syntax_error (_("invalid condition"));
6960 else if (operands
[i
] == AARCH64_OPND_COND1
6961 && (info
->cond
->value
& 0xe) == 0xe)
6963 /* Do not allow AL or NV. */
6964 set_default_error ();
6970 case AARCH64_OPND_ADDR_ADRP
:
6971 po_misc_or_fail (parse_adrp (&str
));
6972 /* Clear the value as operand needs to be relocated. */
6973 info
->imm
.value
= 0;
6976 case AARCH64_OPND_ADDR_PCREL14
:
6977 case AARCH64_OPND_ADDR_PCREL19
:
6978 case AARCH64_OPND_ADDR_PCREL21
:
6979 case AARCH64_OPND_ADDR_PCREL26
:
6980 po_misc_or_fail (parse_address (&str
, info
));
6981 if (!info
->addr
.pcrel
)
6983 set_syntax_error (_("invalid pc-relative address"));
6986 if (inst
.gen_lit_pool
6987 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6989 /* Only permit "=value" in the literal load instructions.
6990 The literal will be generated by programmer_friendly_fixup. */
6991 set_syntax_error (_("invalid use of \"=immediate\""));
6994 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6996 set_syntax_error (_("unrecognized relocation suffix"));
6999 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
7001 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
7002 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7006 info
->imm
.value
= 0;
7007 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7008 switch (opcode
->iclass
)
7012 /* e.g. CBZ or B.COND */
7013 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7014 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
7018 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
7019 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
7023 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
7025 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
7026 : BFD_RELOC_AARCH64_JUMP26
;
7029 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
7030 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
7033 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
7034 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
7040 inst
.reloc
.pc_rel
= 1;
7044 case AARCH64_OPND_ADDR_SIMPLE
:
7045 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
7047 /* [<Xn|SP>{, #<simm>}] */
7049 /* First use the normal address-parsing routines, to get
7050 the usual syntax errors. */
7051 po_misc_or_fail (parse_address (&str
, info
));
7052 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7053 || !info
->addr
.preind
|| info
->addr
.postind
7054 || info
->addr
.writeback
)
7056 set_syntax_error (_("invalid addressing mode"));
7060 /* Then retry, matching the specific syntax of these addresses. */
7062 po_char_or_fail ('[');
7063 po_reg_or_fail (REG_TYPE_R64_SP
);
7064 /* Accept optional ", #0". */
7065 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
7066 && skip_past_char (&str
, ','))
7068 skip_past_char (&str
, '#');
7069 if (! skip_past_char (&str
, '0'))
7071 set_fatal_syntax_error
7072 (_("the optional immediate offset can only be 0"));
7076 po_char_or_fail (']');
7080 case AARCH64_OPND_ADDR_REGOFF
:
7081 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
7082 po_misc_or_fail (parse_address (&str
, info
));
7084 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
7085 || !info
->addr
.preind
|| info
->addr
.postind
7086 || info
->addr
.writeback
)
7088 set_syntax_error (_("invalid addressing mode"));
7091 if (!info
->shifter
.operator_present
)
7093 /* Default to LSL if not present. Libopcodes prefers shifter
7094 kind to be explicit. */
7095 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7096 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7098 /* Qualifier to be deduced by libopcodes. */
7101 case AARCH64_OPND_ADDR_SIMM7
:
7102 po_misc_or_fail (parse_address (&str
, info
));
7103 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7104 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7106 set_syntax_error (_("invalid addressing mode"));
7109 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7111 set_syntax_error (_("relocation not allowed"));
7114 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7116 /* need_libopcodes_p */ 1,
7120 case AARCH64_OPND_ADDR_SIMM9
:
7121 case AARCH64_OPND_ADDR_SIMM9_2
:
7122 case AARCH64_OPND_ADDR_SIMM11
:
7123 case AARCH64_OPND_ADDR_SIMM13
:
7124 po_misc_or_fail (parse_address (&str
, info
));
7125 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7126 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7127 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7128 && info
->addr
.writeback
))
7130 set_syntax_error (_("invalid addressing mode"));
7133 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7135 set_syntax_error (_("relocation not allowed"));
7138 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7140 /* need_libopcodes_p */ 1,
7144 case AARCH64_OPND_ADDR_SIMM10
:
7145 case AARCH64_OPND_ADDR_OFFSET
:
7146 po_misc_or_fail (parse_address (&str
, info
));
7147 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7148 || !info
->addr
.preind
|| info
->addr
.postind
)
7150 set_syntax_error (_("invalid addressing mode"));
7153 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7155 set_syntax_error (_("relocation not allowed"));
7158 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7160 /* need_libopcodes_p */ 1,
7164 case AARCH64_OPND_ADDR_UIMM12
:
7165 po_misc_or_fail (parse_address (&str
, info
));
7166 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7167 || !info
->addr
.preind
|| info
->addr
.writeback
)
7169 set_syntax_error (_("invalid addressing mode"));
7172 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7173 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7174 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7176 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7178 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7180 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7182 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7183 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7184 /* Leave qualifier to be determined by libopcodes. */
7187 case AARCH64_OPND_SIMD_ADDR_POST
:
7188 /* [<Xn|SP>], <Xm|#<amount>> */
7189 po_misc_or_fail (parse_address (&str
, info
));
7190 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7192 set_syntax_error (_("invalid addressing mode"));
7195 if (!info
->addr
.offset
.is_reg
)
7197 if (inst
.reloc
.exp
.X_op
== O_constant
)
7198 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7201 set_fatal_syntax_error
7202 (_("writeback value must be an immediate constant"));
7209 case AARCH64_OPND_SME_SM_ZA
:
7211 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7213 set_syntax_error (_("unknown or missing PSTATE field name"));
7216 info
->reg
.regno
= val
;
7219 case AARCH64_OPND_SME_PnT_Wm_imm
:
7220 /* <Pn>.<T>[<Wm>, #<imm>] */
7224 val
= parse_sme_pred_reg_with_index (&str
,
7228 if (val
== PARSE_FAIL
)
7231 info
->za_tile_vector
.regno
= val
;
7232 info
->za_tile_vector
.index
.regno
= index_base_reg
;
7233 info
->za_tile_vector
.index
.imm
= imm
;
7234 info
->qualifier
= qualifier
;
7238 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7239 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7240 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7241 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7242 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7243 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7244 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7245 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7246 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7247 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7248 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7249 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7250 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7251 /* [X<n>{, #imm, MUL VL}]
7253 but recognizing SVE registers. */
7254 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7255 &offset_qualifier
));
7256 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7258 set_syntax_error (_("invalid addressing mode"));
7262 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7263 || !info
->addr
.preind
|| info
->addr
.writeback
)
7265 set_syntax_error (_("invalid addressing mode"));
7268 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7269 || inst
.reloc
.exp
.X_op
!= O_constant
)
7271 /* Make sure this has priority over
7272 "invalid addressing mode". */
7273 set_fatal_syntax_error (_("constant offset required"));
7276 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7279 case AARCH64_OPND_SVE_ADDR_R
:
7280 /* [<Xn|SP>{, <R><m>}]
7281 but recognizing SVE registers. */
7282 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7283 &offset_qualifier
));
7284 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7286 offset_qualifier
= AARCH64_OPND_QLF_X
;
7287 info
->addr
.offset
.is_reg
= 1;
7288 info
->addr
.offset
.regno
= 31;
7290 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7291 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7293 set_syntax_error (_("invalid addressing mode"));
7298 case AARCH64_OPND_SVE_ADDR_RR
:
7299 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7300 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7301 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7302 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7303 case AARCH64_OPND_SVE_ADDR_RX
:
7304 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7305 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7306 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7307 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7308 but recognizing SVE registers. */
7309 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7310 &offset_qualifier
));
7311 if (base_qualifier
!= AARCH64_OPND_QLF_X
7312 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7314 set_syntax_error (_("invalid addressing mode"));
7319 case AARCH64_OPND_SVE_ADDR_RZ
:
7320 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7321 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7322 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7323 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7324 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7325 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7326 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7327 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7328 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7329 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7330 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7331 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7332 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7333 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7334 &offset_qualifier
));
7335 if (base_qualifier
!= AARCH64_OPND_QLF_X
7336 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7337 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7339 set_syntax_error (_("invalid addressing mode"));
7342 info
->qualifier
= offset_qualifier
;
7345 case AARCH64_OPND_SVE_ADDR_ZX
:
7346 /* [Zn.<T>{, <Xm>}]. */
7347 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7348 &offset_qualifier
));
7350 base_qualifier either S_S or S_D
7351 offset_qualifier must be X
7353 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7354 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7355 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7357 set_syntax_error (_("invalid addressing mode"));
7360 info
->qualifier
= base_qualifier
;
7361 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7362 || !info
->addr
.preind
|| info
->addr
.writeback
7363 || info
->shifter
.operator_present
!= 0)
7365 set_syntax_error (_("invalid addressing mode"));
7368 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7372 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7373 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7374 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7375 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7376 /* [Z<n>.<T>{, #imm}] */
7377 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7378 &offset_qualifier
));
7379 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7380 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7382 set_syntax_error (_("invalid addressing mode"));
7385 info
->qualifier
= base_qualifier
;
7388 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7389 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7390 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7391 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7392 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7396 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7398 here since we get better error messages by leaving it to
7399 the qualifier checking routines. */
7400 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7401 &offset_qualifier
));
7402 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7403 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7404 || offset_qualifier
!= base_qualifier
)
7406 set_syntax_error (_("invalid addressing mode"));
7409 info
->qualifier
= base_qualifier
;
7412 case AARCH64_OPND_SYSREG
:
7414 uint32_t sysreg_flags
;
7415 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7416 &sysreg_flags
)) == PARSE_FAIL
)
7418 set_syntax_error (_("unknown or missing system register name"));
7421 inst
.base
.operands
[i
].sysreg
.value
= val
;
7422 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7426 case AARCH64_OPND_PSTATEFIELD
:
7428 uint32_t sysreg_flags
;
7429 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7430 &sysreg_flags
)) == PARSE_FAIL
)
7432 set_syntax_error (_("unknown or missing PSTATE field name"));
7435 inst
.base
.operands
[i
].pstatefield
= val
;
7436 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7440 case AARCH64_OPND_SYSREG_IC
:
7441 inst
.base
.operands
[i
].sysins_op
=
7442 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7445 case AARCH64_OPND_SYSREG_DC
:
7446 inst
.base
.operands
[i
].sysins_op
=
7447 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7450 case AARCH64_OPND_SYSREG_AT
:
7451 inst
.base
.operands
[i
].sysins_op
=
7452 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7455 case AARCH64_OPND_SYSREG_SR
:
7456 inst
.base
.operands
[i
].sysins_op
=
7457 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7460 case AARCH64_OPND_SYSREG_TLBI
:
7461 inst
.base
.operands
[i
].sysins_op
=
7462 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7464 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7466 set_fatal_syntax_error ( _("unknown or missing operation name"));
7471 case AARCH64_OPND_BARRIER
:
7472 case AARCH64_OPND_BARRIER_ISB
:
7473 val
= parse_barrier (&str
);
7474 if (val
!= PARSE_FAIL
7475 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7477 /* ISB only accepts options name 'sy'. */
7479 (_("the specified option is not accepted in ISB"));
7480 /* Turn off backtrack as this optional operand is present. */
7484 if (val
!= PARSE_FAIL
7485 && operands
[i
] == AARCH64_OPND_BARRIER
)
7487 /* Regular barriers accept options CRm (C0-C15).
7488 DSB nXS barrier variant accepts values > 15. */
7489 if (val
< 0 || val
> 15)
7491 set_syntax_error (_("the specified option is not accepted in DSB"));
7495 /* This is an extension to accept a 0..15 immediate. */
7496 if (val
== PARSE_FAIL
)
7497 po_imm_or_fail (0, 15);
7498 info
->barrier
= aarch64_barrier_options
+ val
;
7501 case AARCH64_OPND_BARRIER_DSB_NXS
:
7502 val
= parse_barrier (&str
);
7503 if (val
!= PARSE_FAIL
)
7505 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7506 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7508 set_syntax_error (_("the specified option is not accepted in DSB"));
7509 /* Turn off backtrack as this optional operand is present. */
7516 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7517 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7518 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7520 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7522 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7526 /* Option index is encoded as 2-bit value in val<3:2>. */
7527 val
= (val
>> 2) - 4;
7528 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7531 case AARCH64_OPND_PRFOP
:
7532 val
= parse_pldop (&str
);
7533 /* This is an extension to accept a 0..31 immediate. */
7534 if (val
== PARSE_FAIL
)
7535 po_imm_or_fail (0, 31);
7536 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7539 case AARCH64_OPND_BARRIER_PSB
:
7540 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7541 if (val
== PARSE_FAIL
)
7545 case AARCH64_OPND_BTI_TARGET
:
7546 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7547 if (val
== PARSE_FAIL
)
7551 case AARCH64_OPND_SME_ZAda_2b
:
7552 case AARCH64_OPND_SME_ZAda_3b
:
7553 val
= parse_sme_zada_operand (&str
, &qualifier
);
7554 if (val
== PARSE_FAIL
)
7556 info
->reg
.regno
= val
;
7557 info
->qualifier
= qualifier
;
7560 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7561 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7562 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7564 enum sme_hv_slice slice_indicator
;
7565 int vector_select_register
;
7568 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
)
7569 val
= parse_sme_za_hv_tiles_operand_with_braces (&str
,
7571 &vector_select_register
,
7575 val
= parse_sme_za_hv_tiles_operand (&str
, &slice_indicator
,
7576 &vector_select_register
,
7579 if (val
== PARSE_FAIL
)
7581 info
->za_tile_vector
.regno
= val
;
7582 info
->za_tile_vector
.index
.regno
= vector_select_register
;
7583 info
->za_tile_vector
.index
.imm
= imm
;
7584 info
->za_tile_vector
.v
= slice_indicator
;
7585 info
->qualifier
= qualifier
;
7589 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7590 val
= parse_sme_list_of_64bit_tiles (&str
);
7591 if (val
== PARSE_FAIL
)
7593 info
->imm
.value
= val
;
7596 case AARCH64_OPND_SME_ZA_array
:
7599 val
= parse_sme_za_array (&str
, &imm
);
7600 if (val
== PARSE_FAIL
)
7602 info
->za_tile_vector
.index
.regno
= val
;
7603 info
->za_tile_vector
.index
.imm
= imm
;
7607 case AARCH64_OPND_MOPS_ADDR_Rd
:
7608 case AARCH64_OPND_MOPS_ADDR_Rs
:
7609 po_char_or_fail ('[');
7610 if (!parse_x0_to_x30 (&str
, info
))
7612 po_char_or_fail (']');
7613 po_char_or_fail ('!');
7616 case AARCH64_OPND_MOPS_WB_Rn
:
7617 if (!parse_x0_to_x30 (&str
, info
))
7619 po_char_or_fail ('!');
7623 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7626 /* If we get here, this operand was successfully parsed. */
7627 inst
.base
.operands
[i
].present
= 1;
7631 /* The parse routine should already have set the error, but in case
7632 not, set a default one here. */
7634 set_default_error ();
7636 if (! backtrack_pos
)
7637 goto parse_operands_return
;
7640 /* We reach here because this operand is marked as optional, and
7641 either no operand was supplied or the operand was supplied but it
7642 was syntactically incorrect. In the latter case we report an
7643 error. In the former case we perform a few more checks before
7644 dropping through to the code to insert the default operand. */
7646 char *tmp
= backtrack_pos
;
7647 char endchar
= END_OF_INSN
;
7649 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7651 skip_past_char (&tmp
, ',');
7653 if (*tmp
!= endchar
)
7654 /* The user has supplied an operand in the wrong format. */
7655 goto parse_operands_return
;
7657 /* Make sure there is not a comma before the optional operand.
7658 For example the fifth operand of 'sys' is optional:
7660 sys #0,c0,c0,#0, <--- wrong
7661 sys #0,c0,c0,#0 <--- correct. */
7662 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7664 set_fatal_syntax_error
7665 (_("unexpected comma before the omitted optional operand"));
7666 goto parse_operands_return
;
7670 /* Reaching here means we are dealing with an optional operand that is
7671 omitted from the assembly line. */
7672 gas_assert (optional_operand_p (opcode
, i
));
7674 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7676 /* Try again, skipping the optional operand at backtrack_pos. */
7677 str
= backtrack_pos
;
7680 /* Clear any error record after the omitted optional operand has been
7681 successfully handled. */
7685 /* Check if we have parsed all the operands. */
7686 if (*str
!= '\0' && ! error_p ())
7688 /* Set I to the index of the last present operand; this is
7689 for the purpose of diagnostics. */
7690 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7692 set_fatal_syntax_error
7693 (_("unexpected characters following instruction"));
7696 parse_operands_return
:
7700 inst
.parsing_error
.index
= i
;
7701 DEBUG_TRACE ("parsing FAIL: %s - %s",
7702 operand_mismatch_kind_names
[inst
.parsing_error
.kind
],
7703 inst
.parsing_error
.error
);
7704 /* Record the operand error properly; this is useful when there
7705 are multiple instruction templates for a mnemonic name, so that
7706 later on, we can select the error that most closely describes
7708 record_operand_error_info (opcode
, &inst
.parsing_error
);
7713 DEBUG_TRACE ("parsing SUCCESS");
7718 /* It does some fix-up to provide some programmer friendly feature while
7719 keeping the libopcodes happy, i.e. libopcodes only accepts
7720 the preferred architectural syntax.
7721 Return FALSE if there is any failure; otherwise return TRUE. */
7724 programmer_friendly_fixup (aarch64_instruction
*instr
)
7726 aarch64_inst
*base
= &instr
->base
;
7727 const aarch64_opcode
*opcode
= base
->opcode
;
7728 enum aarch64_op op
= opcode
->op
;
7729 aarch64_opnd_info
*operands
= base
->operands
;
7731 DEBUG_TRACE ("enter");
7733 switch (opcode
->iclass
)
7736 /* TBNZ Xn|Wn, #uimm6, label
7737 Test and Branch Not Zero: conditionally jumps to label if bit number
7738 uimm6 in register Xn is not zero. The bit number implies the width of
7739 the register, which may be written and should be disassembled as Wn if
7740 uimm is less than 32. */
7741 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7743 if (operands
[1].imm
.value
>= 32)
7745 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7749 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7753 /* LDR Wt, label | =value
7754 As a convenience assemblers will typically permit the notation
7755 "=value" in conjunction with the pc-relative literal load instructions
7756 to automatically place an immediate value or symbolic address in a
7757 nearby literal pool and generate a hidden label which references it.
7758 ISREG has been set to 0 in the case of =value. */
7759 if (instr
->gen_lit_pool
7760 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7762 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7763 if (op
== OP_LDRSW_LIT
)
7765 if (instr
->reloc
.exp
.X_op
!= O_constant
7766 && instr
->reloc
.exp
.X_op
!= O_big
7767 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7769 record_operand_error (opcode
, 1,
7770 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7771 _("constant expression expected"));
7774 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7776 record_operand_error (opcode
, 1,
7777 AARCH64_OPDE_OTHER_ERROR
,
7778 _("literal pool insertion failed"));
7786 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7787 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7788 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7789 A programmer-friendly assembler should accept a destination Xd in
7790 place of Wd, however that is not the preferred form for disassembly.
7792 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7793 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7794 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7795 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7800 /* In the 64-bit form, the final register operand is written as Wm
7801 for all but the (possibly omitted) UXTX/LSL and SXTX
7803 As a programmer-friendly assembler, we accept e.g.
7804 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7805 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7806 int idx
= aarch64_operand_index (opcode
->operands
,
7807 AARCH64_OPND_Rm_EXT
);
7808 gas_assert (idx
== 1 || idx
== 2);
7809 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7810 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7811 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7812 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7813 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7814 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7822 DEBUG_TRACE ("exit with SUCCESS");
7826 /* Check for loads and stores that will cause unpredictable behavior. */
7829 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7831 aarch64_inst
*base
= &instr
->base
;
7832 const aarch64_opcode
*opcode
= base
->opcode
;
7833 const aarch64_opnd_info
*opnds
= base
->operands
;
7834 switch (opcode
->iclass
)
7841 /* Loading/storing the base register is unpredictable if writeback. */
7842 if ((aarch64_get_operand_class (opnds
[0].type
)
7843 == AARCH64_OPND_CLASS_INT_REG
)
7844 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7845 && opnds
[1].addr
.base_regno
!= REG_SP
7846 /* Exempt STG/STZG/ST2G/STZ2G. */
7847 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7848 && opnds
[1].addr
.writeback
)
7849 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7853 case ldstnapair_offs
:
7854 case ldstpair_indexed
:
7855 /* Loading/storing the base register is unpredictable if writeback. */
7856 if ((aarch64_get_operand_class (opnds
[0].type
)
7857 == AARCH64_OPND_CLASS_INT_REG
)
7858 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7859 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7860 && opnds
[2].addr
.base_regno
!= REG_SP
7862 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7863 && opnds
[2].addr
.writeback
)
7864 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7865 /* Load operations must load different registers. */
7866 if ((opcode
->opcode
& (1 << 22))
7867 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7868 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7872 if ((aarch64_get_operand_class (opnds
[0].type
)
7873 == AARCH64_OPND_CLASS_INT_REG
)
7874 && (aarch64_get_operand_class (opnds
[1].type
)
7875 == AARCH64_OPND_CLASS_INT_REG
))
7877 if ((opcode
->opcode
& (1 << 22)))
7879 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
7880 if ((opcode
->opcode
& (1 << 21))
7881 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7882 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7886 /* Store-Exclusive is unpredictable if Rt == Rs. */
7887 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7889 (_("unpredictable: identical transfer and status registers"
7892 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
7894 if (!(opcode
->opcode
& (1 << 21)))
7895 /* Store-Exclusive is unpredictable if Rn == Rs. */
7897 (_("unpredictable: identical base and status registers"
7900 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
7902 (_("unpredictable: "
7903 "identical transfer and status registers"
7907 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
7908 if ((opcode
->opcode
& (1 << 21))
7909 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
7910 && opnds
[3].reg
.regno
!= REG_SP
)
7911 as_warn (_("unpredictable: identical base and status registers"
7923 force_automatic_sequence_close (void)
7925 struct aarch64_segment_info_type
*tc_seg_info
;
7927 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7928 if (tc_seg_info
->insn_sequence
.instr
)
7930 as_warn_where (tc_seg_info
->last_file
, tc_seg_info
->last_line
,
7931 _("previous `%s' sequence has not been closed"),
7932 tc_seg_info
->insn_sequence
.instr
->opcode
->name
);
7933 init_insn_sequence (NULL
, &tc_seg_info
->insn_sequence
);
7937 /* A wrapper function to interface with libopcodes on encoding and
7938 record the error message if there is any.
7940 Return TRUE on success; otherwise return FALSE. */
7943 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7946 aarch64_operand_error error_info
;
7947 memset (&error_info
, '\0', sizeof (error_info
));
7948 error_info
.kind
= AARCH64_OPDE_NIL
;
7949 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7950 && !error_info
.non_fatal
)
7953 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7954 record_operand_error_info (opcode
, &error_info
);
7955 return error_info
.non_fatal
;
7958 #ifdef DEBUG_AARCH64
7960 dump_opcode_operands (const aarch64_opcode
*opcode
)
7963 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7965 aarch64_verbose ("\t\t opnd%d: %s", i
,
7966 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7967 ? aarch64_get_operand_name (opcode
->operands
[i
])
7968 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7972 #endif /* DEBUG_AARCH64 */
7974 /* This is the guts of the machine-dependent assembler. STR points to a
7975 machine dependent instruction. This function is supposed to emit
7976 the frags/bytes it assembles to. */
7979 md_assemble (char *str
)
7981 templates
*template;
7982 const aarch64_opcode
*opcode
;
7983 struct aarch64_segment_info_type
*tc_seg_info
;
7984 aarch64_inst
*inst_base
;
7985 unsigned saved_cond
;
7987 /* Align the previous label if needed. */
7988 if (last_label_seen
!= NULL
)
7990 symbol_set_frag (last_label_seen
, frag_now
);
7991 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7992 S_SET_SEGMENT (last_label_seen
, now_seg
);
7995 /* Update the current insn_sequence from the segment. */
7996 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7997 insn_sequence
= &tc_seg_info
->insn_sequence
;
7998 tc_seg_info
->last_file
= as_where (&tc_seg_info
->last_line
);
8000 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8002 DEBUG_TRACE ("\n\n");
8003 DEBUG_TRACE ("==============================");
8004 DEBUG_TRACE ("Enter md_assemble with %s", str
);
8006 /* Scan up to the end of the mnemonic, which must end in whitespace,
8007 '.', or end of string. */
8010 for (; is_part_of_name (*p
); p
++)
8011 if (*p
== '.' && !dot
)
8016 as_bad (_("unknown mnemonic -- `%s'"), str
);
8020 if (!dot
&& create_register_alias (str
, p
))
8023 template = opcode_lookup (str
, dot
, p
);
8026 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
8031 skip_whitespace (p
);
8034 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
8035 get_mnemonic_name (str
), str
);
8039 init_operand_error_report ();
8041 /* Sections are assumed to start aligned. In executable section, there is no
8042 MAP_DATA symbol pending. So we only align the address during
8043 MAP_DATA --> MAP_INSN transition.
8044 For other sections, this is not guaranteed. */
8045 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
8046 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
8047 frag_align_code (2, 0);
8049 saved_cond
= inst
.cond
;
8050 reset_aarch64_instruction (&inst
);
8051 inst
.cond
= saved_cond
;
8053 /* Iterate through all opcode entries with the same mnemonic name. */
8056 opcode
= template->opcode
;
8058 DEBUG_TRACE ("opcode %s found", opcode
->name
);
8059 #ifdef DEBUG_AARCH64
8061 dump_opcode_operands (opcode
);
8062 #endif /* DEBUG_AARCH64 */
8064 mapping_state (MAP_INSN
);
8066 inst_base
= &inst
.base
;
8067 inst_base
->opcode
= opcode
;
8069 /* Truly conditionally executed instructions, e.g. b.cond. */
8070 if (opcode
->flags
& F_COND
)
8072 gas_assert (inst
.cond
!= COND_ALWAYS
);
8073 inst_base
->cond
= get_cond_from_value (inst
.cond
);
8074 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
8076 else if (inst
.cond
!= COND_ALWAYS
)
8078 /* It shouldn't arrive here, where the assembly looks like a
8079 conditional instruction but the found opcode is unconditional. */
8084 if (parse_operands (p
, opcode
)
8085 && programmer_friendly_fixup (&inst
)
8086 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
8088 /* Check that this instruction is supported for this CPU. */
8089 if (!opcode
->avariant
8090 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
8092 as_bad (_("selected processor does not support `%s'"), str
);
8096 warn_unpredictable_ldst (&inst
, str
);
8098 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
8099 || !inst
.reloc
.need_libopcodes_p
)
8103 /* If there is relocation generated for the instruction,
8104 store the instruction information for the future fix-up. */
8105 struct aarch64_inst
*copy
;
8106 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
8107 copy
= XNEW (struct aarch64_inst
);
8108 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
8112 /* Issue non-fatal messages if any. */
8113 output_operand_error_report (str
, true);
8117 template = template->next
;
8118 if (template != NULL
)
8120 reset_aarch64_instruction (&inst
);
8121 inst
.cond
= saved_cond
;
8124 while (template != NULL
);
8126 /* Issue the error messages if any. */
8127 output_operand_error_report (str
, false);
8130 /* Various frobbings of labels and their addresses. */
8133 aarch64_start_line_hook (void)
8135 last_label_seen
= NULL
;
8139 aarch64_frob_label (symbolS
* sym
)
8141 last_label_seen
= sym
;
8143 dwarf2_emit_label (sym
);
8147 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8149 /* Check to see if we have a block to close. */
8150 force_automatic_sequence_close ();
8154 aarch64_data_in_code (void)
8156 if (startswith (input_line_pointer
+ 1, "data:"))
8158 *input_line_pointer
= '/';
8159 input_line_pointer
+= 5;
8160 *input_line_pointer
= 0;
8168 aarch64_canonicalize_symbol_name (char *name
)
8172 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8173 *(name
+ len
- 5) = 0;
8178 /* Table of all register names defined by default. The user can
8179 define additional names with .req. Note that all register names
8180 should appear in both upper and lowercase variants. Some registers
8181 also have mixed-case names. */
8183 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8184 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8185 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8186 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8187 #define REGSET16(p,t) \
8188 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8189 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8190 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8191 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8192 #define REGSET16S(p,s,t) \
8193 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8194 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8195 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8196 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8197 #define REGSET31(p,t) \
8199 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8200 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8201 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8202 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8203 #define REGSET(p,t) \
8204 REGSET31(p,t), REGNUM(p,31,t)
8206 /* These go into aarch64_reg_hsh hash-table. */
8207 static const reg_entry reg_names
[] = {
8208 /* Integer registers. */
8209 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8210 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8212 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8213 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8214 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8215 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8216 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8217 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8219 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
8220 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
8222 /* Floating-point single precision registers. */
8223 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8225 /* Floating-point double precision registers. */
8226 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8228 /* Floating-point half precision registers. */
8229 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8231 /* Floating-point byte precision registers. */
8232 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8234 /* Floating-point quad precision registers. */
8235 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8237 /* FP/SIMD registers. */
8238 REGSET (v
, VN
), REGSET (V
, VN
),
8240 /* SVE vector registers. */
8241 REGSET (z
, ZN
), REGSET (Z
, ZN
),
8243 /* SVE predicate registers. */
8244 REGSET16 (p
, PN
), REGSET16 (P
, PN
),
8246 /* SME ZA tile registers. */
8247 REGSET16 (za
, ZAT
), REGSET16 (ZA
, ZAT
),
8249 /* SME ZA tile registers (horizontal slice). */
8250 REGSET16S (za
, h
, ZATH
), REGSET16S (ZA
, H
, ZATH
),
8252 /* SME ZA tile registers (vertical slice). */
8253 REGSET16S (za
, v
, ZATV
), REGSET16S (ZA
, V
, ZATV
)
8271 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8272 static const asm_nzcv nzcv_names
[] = {
8273 {"nzcv", B (n
, z
, c
, v
)},
8274 {"nzcV", B (n
, z
, c
, V
)},
8275 {"nzCv", B (n
, z
, C
, v
)},
8276 {"nzCV", B (n
, z
, C
, V
)},
8277 {"nZcv", B (n
, Z
, c
, v
)},
8278 {"nZcV", B (n
, Z
, c
, V
)},
8279 {"nZCv", B (n
, Z
, C
, v
)},
8280 {"nZCV", B (n
, Z
, C
, V
)},
8281 {"Nzcv", B (N
, z
, c
, v
)},
8282 {"NzcV", B (N
, z
, c
, V
)},
8283 {"NzCv", B (N
, z
, C
, v
)},
8284 {"NzCV", B (N
, z
, C
, V
)},
8285 {"NZcv", B (N
, Z
, c
, v
)},
8286 {"NZcV", B (N
, Z
, c
, V
)},
8287 {"NZCv", B (N
, Z
, C
, v
)},
8288 {"NZCV", B (N
, Z
, C
, V
)}
8301 /* MD interface: bits in the object file. */
8303 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8304 for use in the a.out file, and stores them in the array pointed to by buf.
8305 This knows about the endian-ness of the target machine and does
8306 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8307 2 (short) and 4 (long) Floating numbers are put out as a series of
8308 LITTLENUMS (shorts, here at least). */
8311 md_number_to_chars (char *buf
, valueT val
, int n
)
8313 if (target_big_endian
)
8314 number_to_chars_bigendian (buf
, val
, n
);
8316 number_to_chars_littleendian (buf
, val
, n
);
8319 /* MD interface: Sections. */
8321 /* Estimate the size of a frag before relaxing. Assume everything fits in
8325 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8331 /* Round up a section size to the appropriate boundary. */
8334 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8339 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8340 of an rs_align_code fragment.
8342 Here we fill the frag with the appropriate info for padding the
8343 output stream. The resulting frag will consist of a fixed (fr_fix)
8344 and of a repeating (fr_var) part.
8346 The fixed content is always emitted before the repeating content and
8347 these two parts are used as follows in constructing the output:
8348 - the fixed part will be used to align to a valid instruction word
8349 boundary, in case that we start at a misaligned address; as no
8350 executable instruction can live at the misaligned location, we
8351 simply fill with zeros;
8352 - the variable part will be used to cover the remaining padding and
8353 we fill using the AArch64 NOP instruction.
8355 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8356 enough storage space for up to 3 bytes for padding the back to a valid
8357 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8360 aarch64_handle_align (fragS
* fragP
)
8362 /* NOP = d503201f */
8363 /* AArch64 instructions are always little-endian. */
8364 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8366 int bytes
, fix
, noop_size
;
8369 if (fragP
->fr_type
!= rs_align_code
)
8372 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8373 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8376 gas_assert (fragP
->tc_frag_data
.recorded
);
8379 noop_size
= sizeof (aarch64_noop
);
8381 fix
= bytes
& (noop_size
- 1);
8384 #if defined OBJ_ELF || defined OBJ_COFF
8385 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8389 fragP
->fr_fix
+= fix
;
8393 memcpy (p
, aarch64_noop
, noop_size
);
8394 fragP
->fr_var
= noop_size
;
8397 /* Perform target specific initialisation of a frag.
8398 Note - despite the name this initialisation is not done when the frag
8399 is created, but only when its type is assigned. A frag can be created
8400 and used a long time before its type is set, so beware of assuming that
8401 this initialisation is performed first. */
8405 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8406 int max_chars ATTRIBUTE_UNUSED
)
8410 #else /* OBJ_ELF is defined. */
8412 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8414 /* Record a mapping symbol for alignment frags. We will delete this
8415 later if the alignment ends up empty. */
8416 if (!fragP
->tc_frag_data
.recorded
)
8417 fragP
->tc_frag_data
.recorded
= 1;
8419 /* PR 21809: Do not set a mapping state for debug sections
8420 - it just confuses other tools. */
8421 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8424 switch (fragP
->fr_type
)
8428 mapping_state_2 (MAP_DATA
, max_chars
);
8431 /* PR 20364: We can get alignment frags in code sections,
8432 so do not just assume that we should use the MAP_DATA state. */
8433 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8436 mapping_state_2 (MAP_INSN
, max_chars
);
8443 /* Whether SFrame stack trace info is supported. */
8446 aarch64_support_sframe_p (void)
8448 /* At this time, SFrame is supported for aarch64 only. */
8449 return (aarch64_abi
== AARCH64_ABI_LP64
);
8452 /* Specify if RA tracking is needed. */
8455 aarch64_sframe_ra_tracking_p (void)
8460 /* Specify the fixed offset to recover RA from CFA.
8461 (useful only when RA tracking is not needed). */
8464 aarch64_sframe_cfa_ra_offset (void)
8466 return (offsetT
) SFRAME_CFA_FIXED_RA_INVALID
;
8469 /* Get the abi/arch indentifier for SFrame. */
8472 aarch64_sframe_get_abi_arch (void)
8474 unsigned char sframe_abi_arch
= 0;
8476 if (aarch64_support_sframe_p ())
8478 sframe_abi_arch
= target_big_endian
8479 ? SFRAME_ABI_AARCH64_ENDIAN_BIG
8480 : SFRAME_ABI_AARCH64_ENDIAN_LITTLE
;
8483 return sframe_abi_arch
;
8486 #endif /* OBJ_ELF */
8488 /* Initialize the DWARF-2 unwind information for this procedure. */
8491 tc_aarch64_frame_initial_instructions (void)
8493 cfi_add_CFA_def_cfa (REG_SP
, 0);
8496 /* Convert REGNAME to a DWARF-2 register number. */
8499 tc_aarch64_regname_to_dw2regnum (char *regname
)
8501 const reg_entry
*reg
= parse_reg (®name
);
8507 case REG_TYPE_SP_32
:
8508 case REG_TYPE_SP_64
:
8518 return reg
->number
+ 64;
8526 /* Implement DWARF2_ADDR_SIZE. */
8529 aarch64_dwarf2_addr_size (void)
8535 return bfd_arch_bits_per_address (stdoutput
) / 8;
8538 /* MD interface: Symbol and relocation handling. */
8540 /* Return the address within the segment that a PC-relative fixup is
8541 relative to. For AArch64 PC-relative fixups applied to instructions
8542 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8545 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8547 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8549 /* If this is pc-relative and we are going to emit a relocation
8550 then we just want to put out any pipeline compensation that the linker
8551 will need. Otherwise we want to use the calculated base. */
8553 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8554 || aarch64_force_relocation (fixP
)))
8557 /* AArch64 should be consistent for all pc-relative relocations. */
8558 return base
+ AARCH64_PCREL_OFFSET
;
8561 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8562 Otherwise we have no need to default values of symbols. */
8565 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8568 if (name
[0] == '_' && name
[1] == 'G'
8569 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8573 if (symbol_find (name
))
8574 as_bad (_("GOT already in the symbol table"));
8576 GOT_symbol
= symbol_new (name
, undefined_section
,
8577 &zero_address_frag
, 0);
8587 /* Return non-zero if the indicated VALUE has overflowed the maximum
8588 range expressible by a unsigned number with the indicated number of
8592 unsigned_overflow (valueT value
, unsigned bits
)
8595 if (bits
>= sizeof (valueT
) * 8)
8597 lim
= (valueT
) 1 << bits
;
8598 return (value
>= lim
);
8602 /* Return non-zero if the indicated VALUE has overflowed the maximum
8603 range expressible by an signed number with the indicated number of
8607 signed_overflow (offsetT value
, unsigned bits
)
8610 if (bits
>= sizeof (offsetT
) * 8)
8612 lim
= (offsetT
) 1 << (bits
- 1);
8613 return (value
< -lim
|| value
>= lim
);
8616 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8617 unsigned immediate offset load/store instruction, try to encode it as
8618 an unscaled, 9-bit, signed immediate offset load/store instruction.
8619 Return TRUE if it is successful; otherwise return FALSE.
8621 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8622 in response to the standard LDR/STR mnemonics when the immediate offset is
8623 unambiguous, i.e. when it is negative or unaligned. */
8626 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8629 enum aarch64_op new_op
;
8630 const aarch64_opcode
*new_opcode
;
8632 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8634 switch (instr
->opcode
->op
)
8636 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8637 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8638 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8639 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8640 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8641 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8642 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8643 case OP_STR_POS
: new_op
= OP_STUR
; break;
8644 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8645 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8646 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8647 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8648 default: new_op
= OP_NIL
; break;
8651 if (new_op
== OP_NIL
)
8654 new_opcode
= aarch64_get_opcode (new_op
);
8655 gas_assert (new_opcode
!= NULL
);
8657 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8658 instr
->opcode
->op
, new_opcode
->op
);
8660 aarch64_replace_opcode (instr
, new_opcode
);
8662 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8663 qualifier matching may fail because the out-of-date qualifier will
8664 prevent the operand being updated with a new and correct qualifier. */
8665 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8666 AARCH64_OPND_ADDR_SIMM9
);
8667 gas_assert (idx
== 1);
8668 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8670 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8672 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8679 /* Called by fix_insn to fix a MOV immediate alias instruction.
8681 Operand for a generic move immediate instruction, which is an alias
8682 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8683 a 32-bit/64-bit immediate value into general register. An assembler error
8684 shall result if the immediate cannot be created by a single one of these
8685 instructions. If there is a choice, then to ensure reversability an
8686 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8689 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8691 const aarch64_opcode
*opcode
;
8693 /* Need to check if the destination is SP/ZR. The check has to be done
8694 before any aarch64_replace_opcode. */
8695 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8696 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8698 instr
->operands
[1].imm
.value
= value
;
8699 instr
->operands
[1].skip
= 0;
8703 /* Try the MOVZ alias. */
8704 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8705 aarch64_replace_opcode (instr
, opcode
);
8706 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8707 &instr
->value
, NULL
, NULL
, insn_sequence
))
8709 put_aarch64_insn (buf
, instr
->value
);
8712 /* Try the MOVK alias. */
8713 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8714 aarch64_replace_opcode (instr
, opcode
);
8715 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8716 &instr
->value
, NULL
, NULL
, insn_sequence
))
8718 put_aarch64_insn (buf
, instr
->value
);
8723 if (try_mov_bitmask_p
)
8725 /* Try the ORR alias. */
8726 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8727 aarch64_replace_opcode (instr
, opcode
);
8728 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8729 &instr
->value
, NULL
, NULL
, insn_sequence
))
8731 put_aarch64_insn (buf
, instr
->value
);
8736 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8737 _("immediate cannot be moved by a single instruction"));
8740 /* An instruction operand which is immediate related may have symbol used
8741 in the assembly, e.g.
8744 .set u32, 0x00ffff00
8746 At the time when the assembly instruction is parsed, a referenced symbol,
8747 like 'u32' in the above example may not have been seen; a fixS is created
8748 in such a case and is handled here after symbols have been resolved.
8749 Instruction is fixed up with VALUE using the information in *FIXP plus
8750 extra information in FLAGS.
8752 This function is called by md_apply_fix to fix up instructions that need
8753 a fix-up described above but does not involve any linker-time relocation. */
8756 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8760 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8761 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8762 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8766 /* Now the instruction is about to be fixed-up, so the operand that
8767 was previously marked as 'ignored' needs to be unmarked in order
8768 to get the encoding done properly. */
8769 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8770 new_inst
->operands
[idx
].skip
= 0;
8773 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8777 case AARCH64_OPND_EXCEPTION
:
8778 case AARCH64_OPND_UNDEFINED
:
8779 if (unsigned_overflow (value
, 16))
8780 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8781 _("immediate out of range"));
8782 insn
= get_aarch64_insn (buf
);
8783 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8784 put_aarch64_insn (buf
, insn
);
8787 case AARCH64_OPND_AIMM
:
8788 /* ADD or SUB with immediate.
8789 NOTE this assumes we come here with a add/sub shifted reg encoding
8790 3 322|2222|2 2 2 21111 111111
8791 1 098|7654|3 2 1 09876 543210 98765 43210
8792 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8793 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8794 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8795 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8797 3 322|2222|2 2 221111111111
8798 1 098|7654|3 2 109876543210 98765 43210
8799 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8800 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8801 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8802 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8803 Fields sf Rn Rd are already set. */
8804 insn
= get_aarch64_insn (buf
);
8808 insn
= reencode_addsub_switch_add_sub (insn
);
8812 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8813 && unsigned_overflow (value
, 12))
8815 /* Try to shift the value by 12 to make it fit. */
8816 if (((value
>> 12) << 12) == value
8817 && ! unsigned_overflow (value
, 12 + 12))
8820 insn
|= encode_addsub_imm_shift_amount (1);
8824 if (unsigned_overflow (value
, 12))
8825 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8826 _("immediate out of range"));
8828 insn
|= encode_addsub_imm (value
);
8830 put_aarch64_insn (buf
, insn
);
8833 case AARCH64_OPND_SIMD_IMM
:
8834 case AARCH64_OPND_SIMD_IMM_SFT
:
8835 case AARCH64_OPND_LIMM
:
8836 /* Bit mask immediate. */
8837 gas_assert (new_inst
!= NULL
);
8838 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8839 new_inst
->operands
[idx
].imm
.value
= value
;
8840 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8841 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8842 put_aarch64_insn (buf
, new_inst
->value
);
8844 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8845 _("invalid immediate"));
8848 case AARCH64_OPND_HALF
:
8849 /* 16-bit unsigned immediate. */
8850 if (unsigned_overflow (value
, 16))
8851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8852 _("immediate out of range"));
8853 insn
= get_aarch64_insn (buf
);
8854 insn
|= encode_movw_imm (value
& 0xffff);
8855 put_aarch64_insn (buf
, insn
);
8858 case AARCH64_OPND_IMM_MOV
:
8859 /* Operand for a generic move immediate instruction, which is
8860 an alias instruction that generates a single MOVZ, MOVN or ORR
8861 instruction to loads a 32-bit/64-bit immediate value into general
8862 register. An assembler error shall result if the immediate cannot be
8863 created by a single one of these instructions. If there is a choice,
8864 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8865 and MOVZ or MOVN to ORR. */
8866 gas_assert (new_inst
!= NULL
);
8867 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8870 case AARCH64_OPND_ADDR_SIMM7
:
8871 case AARCH64_OPND_ADDR_SIMM9
:
8872 case AARCH64_OPND_ADDR_SIMM9_2
:
8873 case AARCH64_OPND_ADDR_SIMM10
:
8874 case AARCH64_OPND_ADDR_UIMM12
:
8875 case AARCH64_OPND_ADDR_SIMM11
:
8876 case AARCH64_OPND_ADDR_SIMM13
:
8877 /* Immediate offset in an address. */
8878 insn
= get_aarch64_insn (buf
);
8880 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8881 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8882 || new_inst
->opcode
->operands
[2] == opnd
);
8884 /* Get the index of the address operand. */
8885 if (new_inst
->opcode
->operands
[1] == opnd
)
8886 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8889 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8892 /* Update the resolved offset value. */
8893 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8895 /* Encode/fix-up. */
8896 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8897 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8899 put_aarch64_insn (buf
, new_inst
->value
);
8902 else if (new_inst
->opcode
->iclass
== ldst_pos
8903 && try_to_encode_as_unscaled_ldst (new_inst
))
8905 put_aarch64_insn (buf
, new_inst
->value
);
8909 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8910 _("immediate offset out of range"));
8915 as_fatal (_("unhandled operand code %d"), opnd
);
8919 /* Apply a fixup (fixP) to segment data, once it has been determined
8920 by our caller that we have all the info we need to fix it up.
8922 Parameter valP is the pointer to the value of the bits. */
8925 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8927 offsetT value
= *valP
;
8929 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8931 unsigned flags
= fixP
->fx_addnumber
;
8933 DEBUG_TRACE ("\n\n");
8934 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8935 DEBUG_TRACE ("Enter md_apply_fix");
8937 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8939 /* Note whether this will delete the relocation. */
8941 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
8942 && aarch64_force_reloc (fixP
->fx_r_type
) <= 0)
8945 /* Process the relocations. */
8946 switch (fixP
->fx_r_type
)
8948 case BFD_RELOC_NONE
:
8949 /* This will need to go in the object file. */
8954 case BFD_RELOC_8_PCREL
:
8955 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8956 md_number_to_chars (buf
, value
, 1);
8960 case BFD_RELOC_16_PCREL
:
8961 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8962 md_number_to_chars (buf
, value
, 2);
8966 case BFD_RELOC_32_PCREL
:
8967 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8968 md_number_to_chars (buf
, value
, 4);
8972 case BFD_RELOC_64_PCREL
:
8973 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8974 md_number_to_chars (buf
, value
, 8);
8977 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8978 /* We claim that these fixups have been processed here, even if
8979 in fact we generate an error because we do not have a reloc
8980 for them, so tc_gen_reloc() will reject them. */
8982 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8985 _("undefined symbol %s used as an immediate value"),
8986 S_GET_NAME (fixP
->fx_addsy
));
8987 goto apply_fix_return
;
8989 fix_insn (fixP
, flags
, value
);
8992 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8993 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8996 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8997 _("pc-relative load offset not word aligned"));
8998 if (signed_overflow (value
, 21))
8999 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9000 _("pc-relative load offset out of range"));
9001 insn
= get_aarch64_insn (buf
);
9002 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
9003 put_aarch64_insn (buf
, insn
);
9007 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
9008 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9010 if (signed_overflow (value
, 21))
9011 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9012 _("pc-relative address offset out of range"));
9013 insn
= get_aarch64_insn (buf
);
9014 insn
|= encode_adr_imm (value
);
9015 put_aarch64_insn (buf
, insn
);
9019 case BFD_RELOC_AARCH64_BRANCH19
:
9020 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9023 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9024 _("conditional branch target not word aligned"));
9025 if (signed_overflow (value
, 21))
9026 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9027 _("conditional branch out of range"));
9028 insn
= get_aarch64_insn (buf
);
9029 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
9030 put_aarch64_insn (buf
, insn
);
9034 case BFD_RELOC_AARCH64_TSTBR14
:
9035 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9038 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9039 _("conditional branch target not word aligned"));
9040 if (signed_overflow (value
, 16))
9041 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9042 _("conditional branch out of range"));
9043 insn
= get_aarch64_insn (buf
);
9044 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
9045 put_aarch64_insn (buf
, insn
);
9049 case BFD_RELOC_AARCH64_CALL26
:
9050 case BFD_RELOC_AARCH64_JUMP26
:
9051 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9054 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9055 _("branch target not word aligned"));
9056 if (signed_overflow (value
, 28))
9057 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9058 _("branch out of range"));
9059 insn
= get_aarch64_insn (buf
);
9060 insn
|= encode_branch_ofs_26 (value
>> 2);
9061 put_aarch64_insn (buf
, insn
);
9065 case BFD_RELOC_AARCH64_MOVW_G0
:
9066 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
9067 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9068 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
9069 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9070 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
9073 case BFD_RELOC_AARCH64_MOVW_G1
:
9074 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
9075 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9076 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9077 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9078 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
9081 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
9083 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9084 /* Should always be exported to object file, see
9085 aarch64_force_relocation(). */
9086 gas_assert (!fixP
->fx_done
);
9087 gas_assert (seg
->use_rela_p
);
9089 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9091 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9092 /* Should always be exported to object file, see
9093 aarch64_force_relocation(). */
9094 gas_assert (!fixP
->fx_done
);
9095 gas_assert (seg
->use_rela_p
);
9097 case BFD_RELOC_AARCH64_MOVW_G2
:
9098 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
9099 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9100 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9101 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
9104 case BFD_RELOC_AARCH64_MOVW_G3
:
9105 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
9108 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9110 insn
= get_aarch64_insn (buf
);
9114 /* REL signed addend must fit in 16 bits */
9115 if (signed_overflow (value
, 16))
9116 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9117 _("offset out of range"));
9121 /* Check for overflow and scale. */
9122 switch (fixP
->fx_r_type
)
9124 case BFD_RELOC_AARCH64_MOVW_G0
:
9125 case BFD_RELOC_AARCH64_MOVW_G1
:
9126 case BFD_RELOC_AARCH64_MOVW_G2
:
9127 case BFD_RELOC_AARCH64_MOVW_G3
:
9128 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9129 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9130 if (unsigned_overflow (value
, scale
+ 16))
9131 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9132 _("unsigned value out of range"));
9134 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9135 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9136 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9137 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9138 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9139 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9140 /* NOTE: We can only come here with movz or movn. */
9141 if (signed_overflow (value
, scale
+ 16))
9142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9143 _("signed value out of range"));
9146 /* Force use of MOVN. */
9148 insn
= reencode_movzn_to_movn (insn
);
9152 /* Force use of MOVZ. */
9153 insn
= reencode_movzn_to_movz (insn
);
9157 /* Unchecked relocations. */
9163 /* Insert value into MOVN/MOVZ/MOVK instruction. */
9164 insn
|= encode_movw_imm (value
& 0xffff);
9166 put_aarch64_insn (buf
, insn
);
9170 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9171 fixP
->fx_r_type
= (ilp32_p
9172 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9173 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9174 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9175 /* Should always be exported to object file, see
9176 aarch64_force_relocation(). */
9177 gas_assert (!fixP
->fx_done
);
9178 gas_assert (seg
->use_rela_p
);
9181 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9182 fixP
->fx_r_type
= (ilp32_p
9183 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9184 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9185 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9186 /* Should always be exported to object file, see
9187 aarch64_force_relocation(). */
9188 gas_assert (!fixP
->fx_done
);
9189 gas_assert (seg
->use_rela_p
);
9192 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9193 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9194 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9195 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9196 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9197 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9198 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9199 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9200 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9201 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9202 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9203 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9204 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9205 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9206 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9207 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9208 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9209 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9210 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9211 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9212 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9213 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9214 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9215 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9216 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9217 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9218 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9219 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9220 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9221 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9222 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9223 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9224 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9225 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9226 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9227 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9228 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9229 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9230 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9231 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9232 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9233 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9234 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9235 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9236 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9237 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9238 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9239 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9240 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9241 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9242 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9243 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9244 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9245 /* Should always be exported to object file, see
9246 aarch64_force_relocation(). */
9247 gas_assert (!fixP
->fx_done
);
9248 gas_assert (seg
->use_rela_p
);
9251 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9252 /* Should always be exported to object file, see
9253 aarch64_force_relocation(). */
9254 fixP
->fx_r_type
= (ilp32_p
9255 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9256 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9257 gas_assert (!fixP
->fx_done
);
9258 gas_assert (seg
->use_rela_p
);
9261 case BFD_RELOC_AARCH64_ADD_LO12
:
9262 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9263 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9264 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9265 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9266 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9267 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9268 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9269 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9270 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9271 case BFD_RELOC_AARCH64_LDST128_LO12
:
9272 case BFD_RELOC_AARCH64_LDST16_LO12
:
9273 case BFD_RELOC_AARCH64_LDST32_LO12
:
9274 case BFD_RELOC_AARCH64_LDST64_LO12
:
9275 case BFD_RELOC_AARCH64_LDST8_LO12
:
9276 /* Should always be exported to object file, see
9277 aarch64_force_relocation(). */
9278 gas_assert (!fixP
->fx_done
);
9279 gas_assert (seg
->use_rela_p
);
9282 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9283 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9284 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9287 case BFD_RELOC_UNUSED
:
9288 /* An error will already have been reported. */
9292 case BFD_RELOC_32_SECREL
:
9293 case BFD_RELOC_16_SECIDX
:
9297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9298 _("unexpected %s fixup"),
9299 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9304 /* Free the allocated the struct aarch64_inst.
9305 N.B. currently there are very limited number of fix-up types actually use
9306 this field, so the impact on the performance should be minimal . */
9307 free (fixP
->tc_fix_data
.inst
);
9312 /* Translate internal representation of relocation info to BFD target
9316 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9319 bfd_reloc_code_real_type code
;
9321 reloc
= XNEW (arelent
);
9323 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9324 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9325 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9329 if (section
->use_rela_p
)
9330 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9332 fixp
->fx_offset
= reloc
->address
;
9334 reloc
->addend
= fixp
->fx_offset
;
9336 code
= fixp
->fx_r_type
;
9341 code
= BFD_RELOC_16_PCREL
;
9346 code
= BFD_RELOC_32_PCREL
;
9351 code
= BFD_RELOC_64_PCREL
;
9358 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9359 if (reloc
->howto
== NULL
)
9361 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9363 ("cannot represent %s relocation in this object file format"),
9364 bfd_get_reloc_code_name (code
));
9371 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9374 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9376 bfd_reloc_code_real_type type
;
9380 if (exp
->X_op
== O_secrel
)
9382 exp
->X_op
= O_symbol
;
9383 type
= BFD_RELOC_32_SECREL
;
9385 else if (exp
->X_op
== O_secidx
)
9387 exp
->X_op
= O_symbol
;
9388 type
= BFD_RELOC_16_SECIDX
;
9394 FIXME: @@ Should look at CPU word size. */
9401 type
= BFD_RELOC_16
;
9404 type
= BFD_RELOC_32
;
9407 type
= BFD_RELOC_64
;
9410 as_bad (_("cannot do %u-byte relocation"), size
);
9411 type
= BFD_RELOC_UNUSED
;
9418 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9421 /* Implement md_after_parse_args. This is the earliest time we need to decide
9422 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9425 aarch64_after_parse_args (void)
9427 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9431 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9432 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9433 aarch64_abi
= AARCH64_ABI_ILP32
;
9435 aarch64_abi
= AARCH64_ABI_LP64
;
9437 aarch64_abi
= AARCH64_ABI_LLP64
;
9443 elf64_aarch64_target_format (void)
9446 /* FIXME: What to do for ilp32_p ? */
9447 if (target_big_endian
)
9448 return "elf64-bigaarch64-cloudabi";
9450 return "elf64-littleaarch64-cloudabi";
9452 if (target_big_endian
)
9453 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9455 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9460 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9462 elf_frob_symbol (symp
, puntp
);
9464 #elif defined OBJ_COFF
9466 coff_aarch64_target_format (void)
9468 return "pe-aarch64-little";
9472 /* MD interface: Finalization. */
9474 /* A good place to do this, although this was probably not intended
9475 for this kind of use. We need to dump the literal pool before
9476 references are made to a null symbol pointer. */
9479 aarch64_cleanup (void)
9483 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9485 /* Put it at the end of the relevant section. */
9486 subseg_set (pool
->section
, pool
->sub_section
);
9492 /* Remove any excess mapping symbols generated for alignment frags in
9493 SEC. We may have created a mapping symbol before a zero byte
9494 alignment; remove it if there's a mapping symbol after the
9497 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9498 void *dummy ATTRIBUTE_UNUSED
)
9500 segment_info_type
*seginfo
= seg_info (sec
);
9503 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9506 for (fragp
= seginfo
->frchainP
->frch_root
;
9507 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9509 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9510 fragS
*next
= fragp
->fr_next
;
9512 /* Variable-sized frags have been converted to fixed size by
9513 this point. But if this was variable-sized to start with,
9514 there will be a fixed-size frag after it. So don't handle
9516 if (sym
== NULL
|| next
== NULL
)
9519 if (S_GET_VALUE (sym
) < next
->fr_address
)
9520 /* Not at the end of this frag. */
9522 know (S_GET_VALUE (sym
) == next
->fr_address
);
9526 if (next
->tc_frag_data
.first_map
!= NULL
)
9528 /* Next frag starts with a mapping symbol. Discard this
9530 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9534 if (next
->fr_next
== NULL
)
9536 /* This mapping symbol is at the end of the section. Discard
9538 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9539 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9543 /* As long as we have empty frags without any mapping symbols,
9545 /* If the next frag is non-empty and does not start with a
9546 mapping symbol, then this mapping symbol is required. */
9547 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9550 next
= next
->fr_next
;
9552 while (next
!= NULL
);
9557 /* Adjust the symbol table. */
9560 aarch64_adjust_symtab (void)
9563 /* Remove any overlapping mapping symbols generated by alignment frags. */
9564 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9565 /* Now do generic ELF adjustments. */
9566 elf_adjust_symtab ();
9571 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9573 str_hash_insert (table
, key
, value
, 0);
9577 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9579 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9580 checked_hash_insert (table
, key
, value
);
9584 fill_instruction_hash_table (void)
9586 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9588 while (opcode
->name
!= NULL
)
9590 templates
*templ
, *new_templ
;
9591 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9593 new_templ
= XNEW (templates
);
9594 new_templ
->opcode
= opcode
;
9595 new_templ
->next
= NULL
;
9598 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9601 new_templ
->next
= templ
->next
;
9602 templ
->next
= new_templ
;
9609 convert_to_upper (char *dst
, const char *src
, size_t num
)
9612 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9613 *dst
= TOUPPER (*src
);
9617 /* Assume STR point to a lower-case string, allocate, convert and return
9618 the corresponding upper-case string. */
9619 static inline const char*
9620 get_upper_str (const char *str
)
9623 size_t len
= strlen (str
);
9624 ret
= XNEWVEC (char, len
+ 1);
9625 convert_to_upper (ret
, str
, len
);
9629 /* MD interface: Initialization. */
9637 aarch64_ops_hsh
= str_htab_create ();
9638 aarch64_cond_hsh
= str_htab_create ();
9639 aarch64_shift_hsh
= str_htab_create ();
9640 aarch64_sys_regs_hsh
= str_htab_create ();
9641 aarch64_pstatefield_hsh
= str_htab_create ();
9642 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9643 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9644 aarch64_sys_regs_at_hsh
= str_htab_create ();
9645 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9646 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9647 aarch64_reg_hsh
= str_htab_create ();
9648 aarch64_barrier_opt_hsh
= str_htab_create ();
9649 aarch64_nzcv_hsh
= str_htab_create ();
9650 aarch64_pldop_hsh
= str_htab_create ();
9651 aarch64_hint_opt_hsh
= str_htab_create ();
9653 fill_instruction_hash_table ();
9655 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9656 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9657 (void *) (aarch64_sys_regs
+ i
));
9659 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9660 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9661 aarch64_pstatefields
[i
].name
,
9662 (void *) (aarch64_pstatefields
+ i
));
9664 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9665 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9666 aarch64_sys_regs_ic
[i
].name
,
9667 (void *) (aarch64_sys_regs_ic
+ i
));
9669 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9670 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9671 aarch64_sys_regs_dc
[i
].name
,
9672 (void *) (aarch64_sys_regs_dc
+ i
));
9674 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9675 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9676 aarch64_sys_regs_at
[i
].name
,
9677 (void *) (aarch64_sys_regs_at
+ i
));
9679 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9680 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9681 aarch64_sys_regs_tlbi
[i
].name
,
9682 (void *) (aarch64_sys_regs_tlbi
+ i
));
9684 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9685 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9686 aarch64_sys_regs_sr
[i
].name
,
9687 (void *) (aarch64_sys_regs_sr
+ i
));
9689 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9690 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9691 (void *) (reg_names
+ i
));
9693 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9694 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9695 (void *) (nzcv_names
+ i
));
9697 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9699 const char *name
= aarch64_operand_modifiers
[i
].name
;
9700 checked_hash_insert (aarch64_shift_hsh
, name
,
9701 (void *) (aarch64_operand_modifiers
+ i
));
9702 /* Also hash the name in the upper case. */
9703 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9704 (void *) (aarch64_operand_modifiers
+ i
));
9707 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9710 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9711 the same condition code. */
9712 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9714 const char *name
= aarch64_conds
[i
].names
[j
];
9717 checked_hash_insert (aarch64_cond_hsh
, name
,
9718 (void *) (aarch64_conds
+ i
));
9719 /* Also hash the name in the upper case. */
9720 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9721 (void *) (aarch64_conds
+ i
));
9725 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9727 const char *name
= aarch64_barrier_options
[i
].name
;
9728 /* Skip xx00 - the unallocated values of option. */
9731 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9732 (void *) (aarch64_barrier_options
+ i
));
9733 /* Also hash the name in the upper case. */
9734 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9735 (void *) (aarch64_barrier_options
+ i
));
9738 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
9740 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
9741 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9742 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9743 /* Also hash the name in the upper case. */
9744 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9745 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9748 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9750 const char* name
= aarch64_prfops
[i
].name
;
9751 /* Skip the unallocated hint encodings. */
9754 checked_hash_insert (aarch64_pldop_hsh
, name
,
9755 (void *) (aarch64_prfops
+ i
));
9756 /* Also hash the name in the upper case. */
9757 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9758 (void *) (aarch64_prfops
+ i
));
9761 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9763 const char* name
= aarch64_hint_options
[i
].name
;
9764 const char* upper_name
= get_upper_str(name
);
9766 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9767 (void *) (aarch64_hint_options
+ i
));
9769 /* Also hash the name in the upper case if not the same. */
9770 if (strcmp (name
, upper_name
) != 0)
9771 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9772 (void *) (aarch64_hint_options
+ i
));
9775 /* Set the cpu variant based on the command-line options. */
9777 mcpu_cpu_opt
= march_cpu_opt
;
9780 mcpu_cpu_opt
= &cpu_default
;
9782 cpu_variant
= *mcpu_cpu_opt
;
9784 /* Record the CPU type. */
9786 mach
= bfd_mach_aarch64_ilp32
;
9788 mach
= bfd_mach_aarch64_llp64
;
9790 mach
= bfd_mach_aarch64
;
9792 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9794 /* FIXME - is there a better way to do it ? */
9795 aarch64_sframe_cfa_sp_reg
= 31;
9796 aarch64_sframe_cfa_fp_reg
= 29; /* x29. */
9797 aarch64_sframe_cfa_ra_reg
= 30;
9801 /* Command line processing. */
9803 const char *md_shortopts
= "m:";
9805 #ifdef AARCH64_BI_ENDIAN
9806 #define OPTION_EB (OPTION_MD_BASE + 0)
9807 #define OPTION_EL (OPTION_MD_BASE + 1)
9809 #if TARGET_BYTES_BIG_ENDIAN
9810 #define OPTION_EB (OPTION_MD_BASE + 0)
9812 #define OPTION_EL (OPTION_MD_BASE + 1)
9816 struct option md_longopts
[] = {
9818 {"EB", no_argument
, NULL
, OPTION_EB
},
9821 {"EL", no_argument
, NULL
, OPTION_EL
},
9823 {NULL
, no_argument
, NULL
, 0}
9826 size_t md_longopts_size
= sizeof (md_longopts
);
9828 struct aarch64_option_table
9830 const char *option
; /* Option name to match. */
9831 const char *help
; /* Help information. */
9832 int *var
; /* Variable to change. */
9833 int value
; /* What to change it to. */
9834 char *deprecated
; /* If non-null, print this message. */
9837 static struct aarch64_option_table aarch64_opts
[] = {
9838 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9839 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9841 #ifdef DEBUG_AARCH64
9842 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9843 #endif /* DEBUG_AARCH64 */
9844 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9846 {"mno-verbose-error", N_("do not output verbose error messages"),
9847 &verbose_error_p
, 0, NULL
},
9848 {NULL
, NULL
, NULL
, 0, NULL
}
9851 struct aarch64_cpu_option_table
9854 const aarch64_feature_set value
;
9855 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9857 const char *canonical_name
;
9860 /* This list should, at a minimum, contain all the cpu names
9861 recognized by GCC. */
9862 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9863 {"all", AARCH64_ANY
, NULL
},
9864 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9865 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9866 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9867 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9868 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9869 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9870 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9871 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9872 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9873 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9874 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9875 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9876 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9877 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9879 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9880 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9882 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9883 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9885 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9886 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9887 | AARCH64_FEATURE_DOTPROD
9888 | AARCH64_FEATURE_SSBS
),
9890 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9891 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9892 | AARCH64_FEATURE_DOTPROD
9893 | AARCH64_FEATURE_SSBS
),
9895 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9896 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9897 | AARCH64_FEATURE_DOTPROD
9898 | AARCH64_FEATURE_SSBS
),
9900 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9901 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9902 | AARCH64_FEATURE_DOTPROD
9903 | AARCH64_FEATURE_SSBS
),
9905 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9907 | AARCH64_FEATURE_RCPC
9908 | AARCH64_FEATURE_DOTPROD
9909 | AARCH64_FEATURE_SSBS
9910 | AARCH64_FEATURE_PROFILE
),
9912 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9914 | AARCH64_FEATURE_RCPC
9915 | AARCH64_FEATURE_DOTPROD
9916 | AARCH64_FEATURE_SSBS
9917 | AARCH64_FEATURE_PROFILE
),
9919 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9920 AARCH64_FEATURE_DOTPROD
9921 | AARCH64_FEATURE_F16
9922 | AARCH64_FEATURE_FLAGM
9923 | AARCH64_FEATURE_PAC
9924 | AARCH64_FEATURE_PROFILE
9925 | AARCH64_FEATURE_RCPC
9926 | AARCH64_FEATURE_SSBS
),
9928 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9929 AARCH64_FEATURE_BFLOAT16
9930 | AARCH64_FEATURE_I8MM
9931 | AARCH64_FEATURE_MEMTAG
9932 | AARCH64_FEATURE_SVE2_BITPERM
),
9934 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9935 AARCH64_FEATURE_BFLOAT16
9936 | AARCH64_FEATURE_I8MM
9937 | AARCH64_FEATURE_MEMTAG
9938 | AARCH64_FEATURE_SVE2_BITPERM
),
9940 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9941 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9942 | AARCH64_FEATURE_DOTPROD
9943 | AARCH64_FEATURE_PROFILE
),
9945 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9946 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9947 "Samsung Exynos M1"},
9948 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9949 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9950 | AARCH64_FEATURE_RDMA
),
9952 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9953 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9954 | AARCH64_FEATURE_DOTPROD
9955 | AARCH64_FEATURE_SSBS
),
9957 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9958 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9959 | AARCH64_FEATURE_DOTPROD
9960 | AARCH64_FEATURE_PROFILE
),
9962 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9963 AARCH64_FEATURE_BFLOAT16
9964 | AARCH64_FEATURE_I8MM
9965 | AARCH64_FEATURE_F16
9966 | AARCH64_FEATURE_SVE
9967 | AARCH64_FEATURE_SVE2
9968 | AARCH64_FEATURE_SVE2_BITPERM
9969 | AARCH64_FEATURE_MEMTAG
9970 | AARCH64_FEATURE_RNG
),
9972 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9973 AARCH64_FEATURE_PROFILE
9974 | AARCH64_FEATURE_CVADP
9975 | AARCH64_FEATURE_SVE
9976 | AARCH64_FEATURE_SSBS
9977 | AARCH64_FEATURE_RNG
9978 | AARCH64_FEATURE_F16
9979 | AARCH64_FEATURE_BFLOAT16
9980 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9981 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9982 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9983 | AARCH64_FEATURE_RDMA
),
9984 "Qualcomm QDF24XX"},
9985 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9986 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9987 "Qualcomm Saphira"},
9988 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9989 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9991 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9992 AARCH64_FEATURE_CRYPTO
),
9994 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9995 in earlier releases and is superseded by 'xgene1' in all
9997 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9998 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9999 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
10000 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
10001 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
10002 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
10003 AARCH64_FEATURE_F16
10004 | AARCH64_FEATURE_RCPC
10005 | AARCH64_FEATURE_DOTPROD
10006 | AARCH64_FEATURE_SSBS
10007 | AARCH64_FEATURE_PROFILE
),
10009 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
10010 AARCH64_FEATURE_BFLOAT16
10011 | AARCH64_FEATURE_I8MM
10012 | AARCH64_FEATURE_MEMTAG
10013 | AARCH64_FEATURE_SVE2_BITPERM
),
10015 {"generic", AARCH64_ARCH_V8
, NULL
},
10017 {NULL
, AARCH64_ARCH_NONE
, NULL
}
10020 struct aarch64_arch_option_table
10023 const aarch64_feature_set value
;
10026 /* This list should, at a minimum, contain all the architecture names
10027 recognized by GCC. */
10028 static const struct aarch64_arch_option_table aarch64_archs
[] = {
10029 {"all", AARCH64_ANY
},
10030 {"armv8-a", AARCH64_ARCH_V8
},
10031 {"armv8.1-a", AARCH64_ARCH_V8_1
},
10032 {"armv8.2-a", AARCH64_ARCH_V8_2
},
10033 {"armv8.3-a", AARCH64_ARCH_V8_3
},
10034 {"armv8.4-a", AARCH64_ARCH_V8_4
},
10035 {"armv8.5-a", AARCH64_ARCH_V8_5
},
10036 {"armv8.6-a", AARCH64_ARCH_V8_6
},
10037 {"armv8.7-a", AARCH64_ARCH_V8_7
},
10038 {"armv8.8-a", AARCH64_ARCH_V8_8
},
10039 {"armv8-r", AARCH64_ARCH_V8_R
},
10040 {"armv9-a", AARCH64_ARCH_V9
},
10041 {"armv9.1-a", AARCH64_ARCH_V9_1
},
10042 {"armv9.2-a", AARCH64_ARCH_V9_2
},
10043 {"armv9.3-a", AARCH64_ARCH_V9_3
},
10044 {NULL
, AARCH64_ARCH_NONE
}
10047 /* ISA extensions. */
10048 struct aarch64_option_cpu_value_table
10051 const aarch64_feature_set value
;
10052 const aarch64_feature_set require
; /* Feature dependencies. */
10055 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
10056 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
10057 AARCH64_ARCH_NONE
},
10058 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
10059 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10060 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
10061 AARCH64_ARCH_NONE
},
10062 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
10063 AARCH64_ARCH_NONE
},
10064 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
10065 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10066 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
10067 AARCH64_ARCH_NONE
},
10068 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
10069 AARCH64_ARCH_NONE
},
10070 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
10071 AARCH64_ARCH_NONE
},
10072 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
10073 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10074 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
10075 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10076 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
10077 AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0)},
10078 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
10079 AARCH64_ARCH_NONE
},
10080 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
10081 AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0)},
10082 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
10083 AARCH64_ARCH_NONE
},
10084 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
10085 AARCH64_FEATURE (AARCH64_FEATURE_F16
10086 | AARCH64_FEATURE_SIMD
, 0)},
10087 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
10088 AARCH64_ARCH_NONE
},
10089 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
10090 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10091 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
10092 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10093 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
10094 AARCH64_ARCH_NONE
},
10095 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
10096 AARCH64_ARCH_NONE
},
10097 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
10098 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10099 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
10100 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10101 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
10102 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
10103 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
10104 AARCH64_ARCH_NONE
},
10105 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
10106 AARCH64_ARCH_NONE
},
10107 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
10108 AARCH64_ARCH_NONE
},
10109 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
10110 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10111 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
10112 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10113 | AARCH64_FEATURE_SM4
, 0)},
10114 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
10115 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10116 | AARCH64_FEATURE_AES
, 0)},
10117 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
10118 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10119 | AARCH64_FEATURE_SHA3
, 0)},
10120 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
10121 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
10122 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
10123 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10124 | AARCH64_FEATURE_BFLOAT16
, 0)},
10125 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10126 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10127 {"sme-f64f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64
, 0),
10128 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10129 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10130 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10131 {"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64
, 0),
10132 AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0)},
10133 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
10134 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
10135 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
10136 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
10137 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
10138 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10139 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
10140 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10141 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
10142 AARCH64_ARCH_NONE
},
10143 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
10144 AARCH64_ARCH_NONE
},
10145 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
10146 AARCH64_ARCH_NONE
},
10147 {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS
, 0),
10148 AARCH64_ARCH_NONE
},
10149 {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC
, 0),
10150 AARCH64_ARCH_NONE
},
10151 {"cssc", AARCH64_FEATURE (AARCH64_FEATURE_CSSC
, 0),
10152 AARCH64_ARCH_NONE
},
10153 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
10156 struct aarch64_long_option_table
10158 const char *option
; /* Substring to match. */
10159 const char *help
; /* Help information. */
10160 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
10161 char *deprecated
; /* If non-null, print this message. */
10164 /* Transitive closure of features depending on set. */
10165 static aarch64_feature_set
10166 aarch64_feature_disable_set (aarch64_feature_set set
)
10168 const struct aarch64_option_cpu_value_table
*opt
;
10169 aarch64_feature_set prev
= 0;
10171 while (prev
!= set
) {
10173 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10174 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10175 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10180 /* Transitive closure of dependencies of set. */
10181 static aarch64_feature_set
10182 aarch64_feature_enable_set (aarch64_feature_set set
)
10184 const struct aarch64_option_cpu_value_table
*opt
;
10185 aarch64_feature_set prev
= 0;
10187 while (prev
!= set
) {
10189 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10190 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10191 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10197 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10200 /* We insist on extensions being added before being removed. We achieve
10201 this by using the ADDING_VALUE variable to indicate whether we are
10202 adding an extension (1) or removing it (0) and only allowing it to
10203 change in the order -1 -> 1 -> 0. */
10204 int adding_value
= -1;
10205 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10207 /* Copy the feature set, so that we can modify it. */
10208 *ext_set
= **opt_p
;
10211 while (str
!= NULL
&& *str
!= 0)
10213 const struct aarch64_option_cpu_value_table
*opt
;
10214 const char *ext
= NULL
;
10221 as_bad (_("invalid architectural extension"));
10225 ext
= strchr (++str
, '+');
10229 optlen
= ext
- str
;
10231 optlen
= strlen (str
);
10233 if (optlen
>= 2 && startswith (str
, "no"))
10235 if (adding_value
!= 0)
10240 else if (optlen
> 0)
10242 if (adding_value
== -1)
10244 else if (adding_value
!= 1)
10246 as_bad (_("must specify extensions to add before specifying "
10247 "those to remove"));
10254 as_bad (_("missing architectural extension"));
10258 gas_assert (adding_value
!= -1);
10260 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10261 if (strncmp (opt
->name
, str
, optlen
) == 0)
10263 aarch64_feature_set set
;
10265 /* Add or remove the extension. */
10268 set
= aarch64_feature_enable_set (opt
->value
);
10269 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10273 set
= aarch64_feature_disable_set (opt
->value
);
10274 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10279 if (opt
->name
== NULL
)
10281 as_bad (_("unknown architectural extension `%s'"), str
);
10292 aarch64_parse_cpu (const char *str
)
10294 const struct aarch64_cpu_option_table
*opt
;
10295 const char *ext
= strchr (str
, '+');
10299 optlen
= ext
- str
;
10301 optlen
= strlen (str
);
10305 as_bad (_("missing cpu name `%s'"), str
);
10309 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10310 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10312 mcpu_cpu_opt
= &opt
->value
;
10314 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10319 as_bad (_("unknown cpu `%s'"), str
);
10324 aarch64_parse_arch (const char *str
)
10326 const struct aarch64_arch_option_table
*opt
;
10327 const char *ext
= strchr (str
, '+');
10331 optlen
= ext
- str
;
10333 optlen
= strlen (str
);
10337 as_bad (_("missing architecture name `%s'"), str
);
10341 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10342 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10344 march_cpu_opt
= &opt
->value
;
10346 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10351 as_bad (_("unknown architecture `%s'\n"), str
);
10356 struct aarch64_option_abi_value_table
10359 enum aarch64_abi_type value
;
10362 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10364 {"ilp32", AARCH64_ABI_ILP32
},
10365 {"lp64", AARCH64_ABI_LP64
},
10367 {"llp64", AARCH64_ABI_LLP64
},
10372 aarch64_parse_abi (const char *str
)
10376 if (str
[0] == '\0')
10378 as_bad (_("missing abi name `%s'"), str
);
10382 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10383 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10385 aarch64_abi
= aarch64_abis
[i
].value
;
10389 as_bad (_("unknown abi `%s'\n"), str
);
10393 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10394 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10395 aarch64_parse_abi
, NULL
},
10396 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10397 aarch64_parse_cpu
, NULL
},
10398 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10399 aarch64_parse_arch
, NULL
},
10400 {NULL
, NULL
, 0, NULL
}
10404 md_parse_option (int c
, const char *arg
)
10406 struct aarch64_option_table
*opt
;
10407 struct aarch64_long_option_table
*lopt
;
10413 target_big_endian
= 1;
10419 target_big_endian
= 0;
10424 /* Listing option. Just ignore these, we don't support additional
10429 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10431 if (c
== opt
->option
[0]
10432 && ((arg
== NULL
&& opt
->option
[1] == 0)
10433 || streq (arg
, opt
->option
+ 1)))
10435 /* If the option is deprecated, tell the user. */
10436 if (opt
->deprecated
!= NULL
)
10437 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10438 arg
? arg
: "", _(opt
->deprecated
));
10440 if (opt
->var
!= NULL
)
10441 *opt
->var
= opt
->value
;
10447 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10449 /* These options are expected to have an argument. */
10450 if (c
== lopt
->option
[0]
10452 && startswith (arg
, lopt
->option
+ 1))
10454 /* If the option is deprecated, tell the user. */
10455 if (lopt
->deprecated
!= NULL
)
10456 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10457 _(lopt
->deprecated
));
10459 /* Call the sup-option parser. */
10460 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10471 md_show_usage (FILE * fp
)
10473 struct aarch64_option_table
*opt
;
10474 struct aarch64_long_option_table
*lopt
;
10476 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10478 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10479 if (opt
->help
!= NULL
)
10480 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10482 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10483 if (lopt
->help
!= NULL
)
10484 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10488 -EB assemble code for a big-endian cpu\n"));
10493 -EL assemble code for a little-endian cpu\n"));
10497 /* Parse a .cpu directive. */
10500 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10502 const struct aarch64_cpu_option_table
*opt
;
10508 name
= input_line_pointer
;
10509 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10510 saved_char
= *input_line_pointer
;
10511 *input_line_pointer
= 0;
10513 ext
= strchr (name
, '+');
10516 optlen
= ext
- name
;
10518 optlen
= strlen (name
);
10520 /* Skip the first "all" entry. */
10521 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10522 if (strlen (opt
->name
) == optlen
10523 && strncmp (name
, opt
->name
, optlen
) == 0)
10525 mcpu_cpu_opt
= &opt
->value
;
10527 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10530 cpu_variant
= *mcpu_cpu_opt
;
10532 *input_line_pointer
= saved_char
;
10533 demand_empty_rest_of_line ();
10536 as_bad (_("unknown cpu `%s'"), name
);
10537 *input_line_pointer
= saved_char
;
10538 ignore_rest_of_line ();
10542 /* Parse a .arch directive. */
10545 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10547 const struct aarch64_arch_option_table
*opt
;
10553 name
= input_line_pointer
;
10554 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10555 saved_char
= *input_line_pointer
;
10556 *input_line_pointer
= 0;
10558 ext
= strchr (name
, '+');
10561 optlen
= ext
- name
;
10563 optlen
= strlen (name
);
10565 /* Skip the first "all" entry. */
10566 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10567 if (strlen (opt
->name
) == optlen
10568 && strncmp (name
, opt
->name
, optlen
) == 0)
10570 mcpu_cpu_opt
= &opt
->value
;
10572 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10575 cpu_variant
= *mcpu_cpu_opt
;
10577 *input_line_pointer
= saved_char
;
10578 demand_empty_rest_of_line ();
10582 as_bad (_("unknown architecture `%s'\n"), name
);
10583 *input_line_pointer
= saved_char
;
10584 ignore_rest_of_line ();
10587 /* Parse a .arch_extension directive. */
10590 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10593 char *ext
= input_line_pointer
;
10595 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10596 saved_char
= *input_line_pointer
;
10597 *input_line_pointer
= 0;
10599 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10602 cpu_variant
= *mcpu_cpu_opt
;
10604 *input_line_pointer
= saved_char
;
10605 demand_empty_rest_of_line ();
10608 /* Copy symbol information. */
10611 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10613 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10617 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10618 This is needed so AArch64 specific st_other values can be independently
10619 specified for an IFUNC resolver (that is called by the dynamic linker)
10620 and the symbol it resolves (aliased to the resolver). In particular,
10621 if a function symbol has special st_other value set via directives,
10622 then attaching an IFUNC resolver to that symbol should not override
10623 the st_other setting. Requiring the directive on the IFUNC resolver
10624 symbol would be unexpected and problematic in C code, where the two
10625 symbols appear as two independent function declarations. */
10628 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10630 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10631 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10632 /* If size is unset, copy size from src. Because we don't track whether
10633 .size has been used, we can't differentiate .size dest, 0 from the case
10634 where dest's size is unset. */
10635 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
10639 destelf
->size
= XNEW (expressionS
);
10640 *destelf
->size
= *srcelf
->size
;
10642 S_SET_SIZE (dest
, S_GET_SIZE (src
));