1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2022 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
35 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
66 /* Which ABI to use. */
71 AARCH64_ABI_ILP32
= 2,
76 #define DEFAULT_ARCH "aarch64"
80 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
81 static const char *default_arch
= DEFAULT_ARCH
;
84 /* AArch64 ABI for the output file. */
85 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
87 /* When non-zero, program to a 32-bit model, in which the C data types
88 int, long and all pointer types are 32-bit objects (ILP32); or to a
89 64-bit model, in which the C int type is 32-bits but the C long type
90 and all pointer types are 64-bit objects (LP64). */
91 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
93 /* When non zero, C types int and long are 32 bit,
94 pointers, however are 64 bit */
95 #define llp64_p (aarch64_abi == AARCH64_ABI_LLP64)
109 /* SME horizontal or vertical slice indicator, encoded in "V".
120 /* Bits for DEFINED field in vector_type_el. */
121 #define NTA_HASTYPE 1
122 #define NTA_HASINDEX 2
123 #define NTA_HASVARWIDTH 4
125 struct vector_type_el
127 enum vector_el_type type
;
128 unsigned char defined
;
133 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
137 bfd_reloc_code_real_type type
;
140 enum aarch64_opnd opnd
;
142 unsigned need_libopcodes_p
: 1;
145 struct aarch64_instruction
147 /* libopcodes structure for instruction intermediate representation. */
149 /* Record assembly errors found during the parsing. */
152 enum aarch64_operand_error_kind kind
;
155 /* The condition that appears in the assembly line. */
157 /* Relocation information (including the GAS internal fixup). */
159 /* Need to generate an immediate in the literal pool. */
160 unsigned gen_lit_pool
: 1;
163 typedef struct aarch64_instruction aarch64_instruction
;
165 static aarch64_instruction inst
;
167 static bool parse_operands (char *, const aarch64_opcode
*);
168 static bool programmer_friendly_fixup (aarch64_instruction
*);
170 /* Diagnostics inline function utilities.
172 These are lightweight utilities which should only be called by parse_operands
173 and other parsers. GAS processes each assembly line by parsing it against
174 instruction template(s), in the case of multiple templates (for the same
175 mnemonic name), those templates are tried one by one until one succeeds or
176 all fail. An assembly line may fail a few templates before being
177 successfully parsed; an error saved here in most cases is not a user error
178 but an error indicating the current template is not the right template.
179 Therefore it is very important that errors can be saved at a low cost during
180 the parsing; we don't want to slow down the whole parsing by recording
181 non-user errors in detail.
183 Remember that the objective is to help GAS pick up the most appropriate
184 error message in the case of multiple templates, e.g. FMOV which has 8
190 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
191 inst
.parsing_error
.error
= NULL
;
197 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
200 static inline const char *
201 get_error_message (void)
203 return inst
.parsing_error
.error
;
206 static inline enum aarch64_operand_error_kind
207 get_error_kind (void)
209 return inst
.parsing_error
.kind
;
213 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
215 inst
.parsing_error
.kind
= kind
;
216 inst
.parsing_error
.error
= error
;
220 set_recoverable_error (const char *error
)
222 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
225 /* Use the DESC field of the corresponding aarch64_operand entry to compose
226 the error message. */
228 set_default_error (void)
230 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
234 set_syntax_error (const char *error
)
236 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
240 set_first_syntax_error (const char *error
)
243 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
247 set_fatal_syntax_error (const char *error
)
249 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
252 /* Return value for certain parsers when the parsing fails; those parsers
253 return the information of the parsed result, e.g. register number, on
255 #define PARSE_FAIL -1
257 /* This is an invalid condition code that means no conditional field is
259 #define COND_ALWAYS 0x10
263 const char *template;
270 bfd_reloc_code_real_type reloc
;
273 /* Macros to define the register types and masks for the purpose
276 #undef AARCH64_REG_TYPES
277 #define AARCH64_REG_TYPES \
278 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
279 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
280 BASIC_REG_TYPE(SP_32) /* wsp */ \
281 BASIC_REG_TYPE(SP_64) /* sp */ \
282 BASIC_REG_TYPE(Z_32) /* wzr */ \
283 BASIC_REG_TYPE(Z_64) /* xzr */ \
284 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
285 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
286 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
287 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
288 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
289 BASIC_REG_TYPE(VN) /* v[0-31] */ \
290 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
291 BASIC_REG_TYPE(PN) /* p[0-15] */ \
292 BASIC_REG_TYPE(ZA) /* za[0-15] */ \
293 BASIC_REG_TYPE(ZAH) /* za[0-15]h */ \
294 BASIC_REG_TYPE(ZAV) /* za[0-15]v */ \
295 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
296 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
297 /* Typecheck: same, plus SVE registers. */ \
298 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
300 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
301 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
302 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
303 /* Typecheck: same, plus SVE registers. */ \
304 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
305 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
307 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
308 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
309 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
310 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
311 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
312 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
313 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
314 /* Typecheck: any [BHSDQ]P FP. */ \
315 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
316 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
317 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
318 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
319 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
320 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
321 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
322 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
323 be used for SVE instructions, since Zn and Pn are valid symbols \
324 in other contexts. */ \
325 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
326 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
327 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
328 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
329 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
330 | REG_TYPE(ZN) | REG_TYPE(PN)) \
331 /* Any integer register; used for error messages only. */ \
332 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
333 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
334 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
335 /* Pseudo type to mark the end of the enumerator sequence. */ \
338 #undef BASIC_REG_TYPE
339 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
340 #undef MULTI_REG_TYPE
341 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
343 /* Register type enumerators. */
344 typedef enum aarch64_reg_type_
346 /* A list of REG_TYPE_*. */
350 #undef BASIC_REG_TYPE
351 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
353 #define REG_TYPE(T) (1 << REG_TYPE_##T)
354 #undef MULTI_REG_TYPE
355 #define MULTI_REG_TYPE(T,V) V,
357 /* Structure for a hash table entry for a register. */
361 unsigned char number
;
362 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
363 unsigned char builtin
;
366 /* Values indexed by aarch64_reg_type to assist the type checking. */
367 static const unsigned reg_type_masks
[] =
372 #undef BASIC_REG_TYPE
374 #undef MULTI_REG_TYPE
375 #undef AARCH64_REG_TYPES
377 /* Diagnostics used when we don't get a register of the expected type.
378 Note: this has to synchronized with aarch64_reg_type definitions
381 get_reg_expected_msg (aarch64_reg_type reg_type
)
388 msg
= N_("integer 32-bit register expected");
391 msg
= N_("integer 64-bit register expected");
394 msg
= N_("integer register expected");
396 case REG_TYPE_R64_SP
:
397 msg
= N_("64-bit integer or SP register expected");
399 case REG_TYPE_SVE_BASE
:
400 msg
= N_("base register expected");
403 msg
= N_("integer or zero register expected");
405 case REG_TYPE_SVE_OFFSET
:
406 msg
= N_("offset register expected");
409 msg
= N_("integer or SP register expected");
411 case REG_TYPE_R_Z_SP
:
412 msg
= N_("integer, zero or SP register expected");
415 msg
= N_("8-bit SIMD scalar register expected");
418 msg
= N_("16-bit SIMD scalar or floating-point half precision "
419 "register expected");
422 msg
= N_("32-bit SIMD scalar or floating-point single precision "
423 "register expected");
426 msg
= N_("64-bit SIMD scalar or floating-point double precision "
427 "register expected");
430 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
431 "register expected");
433 case REG_TYPE_R_Z_BHSDQ_V
:
434 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
435 msg
= N_("register expected");
437 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
438 msg
= N_("SIMD scalar or floating-point register expected");
440 case REG_TYPE_VN
: /* any V reg */
441 msg
= N_("vector register expected");
444 msg
= N_("SVE vector register expected");
447 msg
= N_("SVE predicate register expected");
450 as_fatal (_("invalid register type %d"), reg_type
);
455 /* Some well known registers that we refer to directly elsewhere. */
459 /* Instructions take 4 bytes in the object file. */
462 static htab_t aarch64_ops_hsh
;
463 static htab_t aarch64_cond_hsh
;
464 static htab_t aarch64_shift_hsh
;
465 static htab_t aarch64_sys_regs_hsh
;
466 static htab_t aarch64_pstatefield_hsh
;
467 static htab_t aarch64_sys_regs_ic_hsh
;
468 static htab_t aarch64_sys_regs_dc_hsh
;
469 static htab_t aarch64_sys_regs_at_hsh
;
470 static htab_t aarch64_sys_regs_tlbi_hsh
;
471 static htab_t aarch64_sys_regs_sr_hsh
;
472 static htab_t aarch64_reg_hsh
;
473 static htab_t aarch64_barrier_opt_hsh
;
474 static htab_t aarch64_nzcv_hsh
;
475 static htab_t aarch64_pldop_hsh
;
476 static htab_t aarch64_hint_opt_hsh
;
478 /* Stuff needed to resolve the label ambiguity
487 static symbolS
*last_label_seen
;
489 /* Literal pool structure. Held on a per-section
490 and per-sub-section basis. */
492 #define MAX_LITERAL_POOL_SIZE 1024
493 typedef struct literal_expression
496 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
497 LITTLENUM_TYPE
* bignum
;
498 } literal_expression
;
500 typedef struct literal_pool
502 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
503 unsigned int next_free_entry
;
509 struct literal_pool
*next
;
512 /* Pointer to a linked list of literal pools. */
513 static literal_pool
*list_of_pools
= NULL
;
517 /* This array holds the chars that always start a comment. If the
518 pre-processor is disabled, these aren't very useful. */
519 const char comment_chars
[] = "";
521 /* This array holds the chars that only start a comment at the beginning of
522 a line. If the line seems to have the form '# 123 filename'
523 .line and .file directives will appear in the pre-processed output. */
524 /* Note that input_file.c hand checks for '#' at the beginning of the
525 first line of the input file. This is because the compiler outputs
526 #NO_APP at the beginning of its output. */
527 /* Also note that comments like this one will always work. */
528 const char line_comment_chars
[] = "#";
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant
533 from exp in floating point numbers. */
534 const char EXP_CHARS
[] = "eE";
536 /* Chars that mean this number is a floating point constant. */
540 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
542 /* Prefix character that indicates the start of an immediate value. */
543 #define is_immediate_prefix(C) ((C) == '#')
545 /* Separator character handling. */
547 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
550 skip_past_char (char **str
, char c
)
561 #define skip_past_comma(str) skip_past_char (str, ',')
563 /* Arithmetic expressions (possibly involving symbols). */
565 static bool in_aarch64_get_expression
= false;
567 /* Third argument to aarch64_get_expression. */
568 #define GE_NO_PREFIX false
569 #define GE_OPT_PREFIX true
571 /* Fourth argument to aarch64_get_expression. */
572 #define ALLOW_ABSENT false
573 #define REJECT_ABSENT true
575 /* Return TRUE if the string pointed by *STR is successfully parsed
576 as an valid expression; *EP will be filled with the information of
577 such an expression. Otherwise return FALSE.
579 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
580 If REJECT_ABSENT is true then trat missing expressions as an error. */
583 aarch64_get_expression (expressionS
* ep
,
585 bool allow_immediate_prefix
,
590 bool prefix_present
= false;
592 if (allow_immediate_prefix
)
594 if (is_immediate_prefix (**str
))
597 prefix_present
= true;
601 memset (ep
, 0, sizeof (expressionS
));
603 save_in
= input_line_pointer
;
604 input_line_pointer
= *str
;
605 in_aarch64_get_expression
= true;
606 seg
= expression (ep
);
607 in_aarch64_get_expression
= false;
609 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
611 /* We found a bad expression in md_operand(). */
612 *str
= input_line_pointer
;
613 input_line_pointer
= save_in
;
614 if (prefix_present
&& ! error_p ())
615 set_fatal_syntax_error (_("bad expression"));
617 set_first_syntax_error (_("bad expression"));
622 if (seg
!= absolute_section
623 && seg
!= text_section
624 && seg
!= data_section
625 && seg
!= bss_section
626 && seg
!= undefined_section
)
628 set_syntax_error (_("bad segment"));
629 *str
= input_line_pointer
;
630 input_line_pointer
= save_in
;
637 *str
= input_line_pointer
;
638 input_line_pointer
= save_in
;
642 /* Turn a string in input_line_pointer into a floating point constant
643 of type TYPE, and store the appropriate bytes in *LITP. The number
644 of LITTLENUMS emitted is stored in *SIZEP. An error message is
645 returned, or NULL on OK. */
648 md_atof (int type
, char *litP
, int *sizeP
)
650 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
653 /* We handle all bad expressions here, so that we can report the faulty
654 instruction in the error message. */
656 md_operand (expressionS
* exp
)
658 if (in_aarch64_get_expression
)
659 exp
->X_op
= O_illegal
;
662 /* Immediate values. */
664 /* Errors may be set multiple times during parsing or bit encoding
665 (particularly in the Neon bits), but usually the earliest error which is set
666 will be the most meaningful. Avoid overwriting it with later (cascading)
667 errors by calling this function. */
670 first_error (const char *error
)
673 set_syntax_error (error
);
676 /* Similar to first_error, but this function accepts formatted error
679 first_error_fmt (const char *format
, ...)
684 /* N.B. this single buffer will not cause error messages for different
685 instructions to pollute each other; this is because at the end of
686 processing of each assembly line, error message if any will be
687 collected by as_bad. */
688 static char buffer
[size
];
692 int ret ATTRIBUTE_UNUSED
;
693 va_start (args
, format
);
694 ret
= vsnprintf (buffer
, size
, format
, args
);
695 know (ret
<= size
- 1 && ret
>= 0);
697 set_syntax_error (buffer
);
701 /* Register parsing. */
703 /* Generic register parser which is called by other specialized
705 CCP points to what should be the beginning of a register name.
706 If it is indeed a valid register name, advance CCP over it and
707 return the reg_entry structure; otherwise return NULL.
708 It does not issue diagnostics. */
711 parse_reg (char **ccp
)
717 #ifdef REGISTER_PREFIX
718 if (*start
!= REGISTER_PREFIX
)
724 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
729 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
731 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
740 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
743 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
745 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
748 /* Try to parse a base or offset register. Allow SVE base and offset
749 registers if REG_TYPE includes SVE registers. Return the register
750 entry on success, setting *QUALIFIER to the register qualifier.
751 Return null otherwise.
753 Note that this function does not issue any diagnostics. */
755 static const reg_entry
*
756 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
757 aarch64_opnd_qualifier_t
*qualifier
)
760 const reg_entry
*reg
= parse_reg (&str
);
770 *qualifier
= AARCH64_OPND_QLF_W
;
776 *qualifier
= AARCH64_OPND_QLF_X
;
780 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
783 switch (TOLOWER (str
[1]))
786 *qualifier
= AARCH64_OPND_QLF_S_S
;
789 *qualifier
= AARCH64_OPND_QLF_S_D
;
806 /* Try to parse a base or offset register. Return the register entry
807 on success, setting *QUALIFIER to the register qualifier. Return null
810 Note that this function does not issue any diagnostics. */
812 static const reg_entry
*
813 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
815 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
818 /* Parse the qualifier of a vector register or vector element of type
819 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
820 succeeds; otherwise return FALSE.
822 Accept only one occurrence of:
823 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
826 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
827 struct vector_type_el
*parsed_type
, char **str
)
831 unsigned element_size
;
832 enum vector_el_type type
;
835 gas_assert (*ptr
== '.');
838 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
843 width
= strtoul (ptr
, &ptr
, 10);
844 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
846 first_error_fmt (_("bad size %d in vector width specifier"), width
);
851 switch (TOLOWER (*ptr
))
870 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
879 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
881 first_error (_("missing element size"));
884 if (width
!= 0 && width
* element_size
!= 64
885 && width
* element_size
!= 128
886 && !(width
== 2 && element_size
== 16)
887 && !(width
== 4 && element_size
== 8))
890 ("invalid element size %d and vector size combination %c"),
896 parsed_type
->type
= type
;
897 parsed_type
->width
= width
;
904 /* *STR contains an SVE zero/merge predication suffix. Parse it into
905 *PARSED_TYPE and point *STR at the end of the suffix. */
908 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
913 gas_assert (*ptr
== '/');
915 switch (TOLOWER (*ptr
))
918 parsed_type
->type
= NT_zero
;
921 parsed_type
->type
= NT_merge
;
924 if (*ptr
!= '\0' && *ptr
!= ',')
925 first_error_fmt (_("unexpected character `%c' in predication type"),
928 first_error (_("missing predication type"));
931 parsed_type
->width
= 0;
936 /* Parse a register of the type TYPE.
938 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
939 name or the parsed register is not of TYPE.
941 Otherwise return the register number, and optionally fill in the actual
942 type of the register in *RTYPE when multiple alternatives were given, and
943 return the register shape and element index information in *TYPEINFO.
945 IN_REG_LIST should be set with TRUE if the caller is parsing a register
949 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
950 struct vector_type_el
*typeinfo
, bool in_reg_list
)
953 const reg_entry
*reg
= parse_reg (&str
);
954 struct vector_type_el atype
;
955 struct vector_type_el parsetype
;
956 bool is_typed_vecreg
= false;
959 atype
.type
= NT_invtype
;
967 set_default_error ();
971 if (! aarch64_check_reg_type (reg
, type
))
973 DEBUG_TRACE ("reg type check failed");
974 set_default_error ();
979 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
980 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
984 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
989 if (!parse_predication_for_operand (&parsetype
, &str
))
993 /* Register if of the form Vn.[bhsdq]. */
994 is_typed_vecreg
= true;
996 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
998 /* The width is always variable; we don't allow an integer width
1000 gas_assert (parsetype
.width
== 0);
1001 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1003 else if (parsetype
.width
== 0)
1004 /* Expect index. In the new scheme we cannot have
1005 Vn.[bhsdq] represent a scalar. Therefore any
1006 Vn.[bhsdq] should have an index following it.
1007 Except in reglists of course. */
1008 atype
.defined
|= NTA_HASINDEX
;
1010 atype
.defined
|= NTA_HASTYPE
;
1012 atype
.type
= parsetype
.type
;
1013 atype
.width
= parsetype
.width
;
1016 if (skip_past_char (&str
, '['))
1020 /* Reject Sn[index] syntax. */
1021 if (!is_typed_vecreg
)
1023 first_error (_("this type of register can't be indexed"));
1029 first_error (_("index not allowed inside register list"));
1033 atype
.defined
|= NTA_HASINDEX
;
1035 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1037 if (exp
.X_op
!= O_constant
)
1039 first_error (_("constant expression required"));
1043 if (! skip_past_char (&str
, ']'))
1046 atype
.index
= exp
.X_add_number
;
1048 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1050 /* Indexed vector register expected. */
1051 first_error (_("indexed vector register expected"));
1055 /* A vector reg Vn should be typed or indexed. */
1056 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1058 first_error (_("invalid use of vector register"));
1074 Return the register number on success; return PARSE_FAIL otherwise.
1076 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1077 the register (e.g. NEON double or quad reg when either has been requested).
1079 If this is a NEON vector register with additional type information, fill
1080 in the struct pointed to by VECTYPE (if non-NULL).
1082 This parser does not handle register list. */
1085 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1086 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1088 struct vector_type_el atype
;
1090 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1091 /*in_reg_list= */ false);
1093 if (reg
== PARSE_FAIL
)
1105 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1109 && e1
.defined
== e2
.defined
1110 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1113 /* This function parses a list of vector registers of type TYPE.
1114 On success, it returns the parsed register list information in the
1115 following encoded format:
1117 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1118 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1120 The information of the register shape and/or index is returned in
1123 It returns PARSE_FAIL if the register list is invalid.
1125 The list contains one to four registers.
1126 Each register can be one of:
1129 All <T> should be identical.
1130 All <index> should be identical.
1131 There are restrictions on <Vt> numbers which are checked later
1132 (by reg_list_valid_p). */
1135 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1136 struct vector_type_el
*vectype
)
1140 struct vector_type_el typeinfo
, typeinfo_first
;
1146 bool expect_index
= false;
1150 set_syntax_error (_("expecting {"));
1156 typeinfo_first
.defined
= 0;
1157 typeinfo_first
.type
= NT_invtype
;
1158 typeinfo_first
.width
= -1;
1159 typeinfo_first
.index
= 0;
1168 str
++; /* skip over '-' */
1171 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1172 /*in_reg_list= */ true);
1173 if (val
== PARSE_FAIL
)
1175 set_first_syntax_error (_("invalid vector register in list"));
1179 /* reject [bhsd]n */
1180 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1182 set_first_syntax_error (_("invalid scalar register in list"));
1187 if (typeinfo
.defined
& NTA_HASINDEX
)
1188 expect_index
= true;
1192 if (val
< val_range
)
1194 set_first_syntax_error
1195 (_("invalid range in vector register list"));
1204 typeinfo_first
= typeinfo
;
1205 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1207 set_first_syntax_error
1208 (_("type mismatch in vector register list"));
1213 for (i
= val_range
; i
<= val
; i
++)
1215 ret_val
|= i
<< (5 * nb_regs
);
1220 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1222 skip_whitespace (str
);
1225 set_first_syntax_error (_("end of vector register list not found"));
1230 skip_whitespace (str
);
1234 if (skip_past_char (&str
, '['))
1238 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
);
1239 if (exp
.X_op
!= O_constant
)
1241 set_first_syntax_error (_("constant expression required."));
1244 if (! skip_past_char (&str
, ']'))
1247 typeinfo_first
.index
= exp
.X_add_number
;
1251 set_first_syntax_error (_("expected index"));
1258 set_first_syntax_error (_("too many registers in vector register list"));
1261 else if (nb_regs
== 0)
1263 set_first_syntax_error (_("empty vector register list"));
1269 *vectype
= typeinfo_first
;
1271 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1274 /* Directives: register aliases. */
1277 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1282 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1285 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1288 /* Only warn about a redefinition if it's not defined as the
1290 else if (new->number
!= number
|| new->type
!= type
)
1291 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1296 name
= xstrdup (str
);
1297 new = XNEW (reg_entry
);
1300 new->number
= number
;
1302 new->builtin
= false;
1304 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1309 /* Look for the .req directive. This is of the form:
1311 new_register_name .req existing_register_name
1313 If we find one, or if it looks sufficiently like one that we want to
1314 handle any error here, return TRUE. Otherwise return FALSE. */
1317 create_register_alias (char *newname
, char *p
)
1319 const reg_entry
*old
;
1320 char *oldname
, *nbuf
;
1323 /* The input scrubber ensures that whitespace after the mnemonic is
1324 collapsed to single spaces. */
1326 if (!startswith (oldname
, " .req "))
1330 if (*oldname
== '\0')
1333 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1336 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1340 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1341 the desired alias name, and p points to its end. If not, then
1342 the desired alias name is in the global original_case_string. */
1343 #ifdef TC_CASE_SENSITIVE
1346 newname
= original_case_string
;
1347 nlen
= strlen (newname
);
1350 nbuf
= xmemdup0 (newname
, nlen
);
1352 /* Create aliases under the new name as stated; an all-lowercase
1353 version of the new name; and an all-uppercase version of the new
1355 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1357 for (p
= nbuf
; *p
; p
++)
1360 if (strncmp (nbuf
, newname
, nlen
))
1362 /* If this attempt to create an additional alias fails, do not bother
1363 trying to create the all-lower case alias. We will fail and issue
1364 a second, duplicate error message. This situation arises when the
1365 programmer does something like:
1368 The second .req creates the "Foo" alias but then fails to create
1369 the artificial FOO alias because it has already been created by the
1371 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1378 for (p
= nbuf
; *p
; p
++)
1381 if (strncmp (nbuf
, newname
, nlen
))
1382 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1389 /* Should never be called, as .req goes between the alias and the
1390 register name, not at the beginning of the line. */
1392 s_req (int a ATTRIBUTE_UNUSED
)
1394 as_bad (_("invalid syntax for .req directive"));
1397 /* The .unreq directive deletes an alias which was previously defined
1398 by .req. For example:
1404 s_unreq (int a ATTRIBUTE_UNUSED
)
1409 name
= input_line_pointer
;
1410 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
1411 saved_char
= *input_line_pointer
;
1412 *input_line_pointer
= 0;
1415 as_bad (_("invalid syntax for .unreq directive"));
1418 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1421 as_bad (_("unknown register alias '%s'"), name
);
1422 else if (reg
->builtin
)
1423 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1430 str_hash_delete (aarch64_reg_hsh
, name
);
1431 free ((char *) reg
->name
);
1434 /* Also locate the all upper case and all lower case versions.
1435 Do not complain if we cannot find one or the other as it
1436 was probably deleted above. */
1438 nbuf
= strdup (name
);
1439 for (p
= nbuf
; *p
; p
++)
1441 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1444 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1445 free ((char *) reg
->name
);
1449 for (p
= nbuf
; *p
; p
++)
1451 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1454 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1455 free ((char *) reg
->name
);
1463 *input_line_pointer
= saved_char
;
1464 demand_empty_rest_of_line ();
1467 /* Directives: Instruction set selection. */
1469 #if defined OBJ_ELF || defined OBJ_COFF
1470 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1471 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1472 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1473 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1475 /* Create a new mapping symbol for the transition to STATE. */
1478 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1481 const char *symname
;
1488 type
= BSF_NO_FLAGS
;
1492 type
= BSF_NO_FLAGS
;
1498 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1499 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1501 /* Save the mapping symbols for future reference. Also check that
1502 we do not place two mapping symbols at the same offset within a
1503 frag. We'll handle overlap between frags in
1504 check_mapping_symbols.
1506 If .fill or other data filling directive generates zero sized data,
1507 the mapping symbol for the following code will have the same value
1508 as the one generated for the data filling directive. In this case,
1509 we replace the old symbol with the new one at the same address. */
1512 if (frag
->tc_frag_data
.first_map
!= NULL
)
1514 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1515 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1518 frag
->tc_frag_data
.first_map
= symbolP
;
1520 if (frag
->tc_frag_data
.last_map
!= NULL
)
1522 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1523 S_GET_VALUE (symbolP
));
1524 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1525 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1528 frag
->tc_frag_data
.last_map
= symbolP
;
1531 /* We must sometimes convert a region marked as code to data during
1532 code alignment, if an odd number of bytes have to be padded. The
1533 code mapping symbol is pushed to an aligned address. */
1536 insert_data_mapping_symbol (enum mstate state
,
1537 valueT value
, fragS
* frag
, offsetT bytes
)
1539 /* If there was already a mapping symbol, remove it. */
1540 if (frag
->tc_frag_data
.last_map
!= NULL
1541 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1542 frag
->fr_address
+ value
)
1544 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1548 know (frag
->tc_frag_data
.first_map
== symp
);
1549 frag
->tc_frag_data
.first_map
= NULL
;
1551 frag
->tc_frag_data
.last_map
= NULL
;
1552 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1555 make_mapping_symbol (MAP_DATA
, value
, frag
);
1556 make_mapping_symbol (state
, value
+ bytes
, frag
);
1559 static void mapping_state_2 (enum mstate state
, int max_chars
);
1561 /* Set the mapping state to STATE. Only call this when about to
1562 emit some STATE bytes to the file. */
1565 mapping_state (enum mstate state
)
1567 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1569 if (state
== MAP_INSN
)
1570 /* AArch64 instructions require 4-byte alignment. When emitting
1571 instructions into any section, record the appropriate section
1573 record_alignment (now_seg
, 2);
1575 if (mapstate
== state
)
1576 /* The mapping symbol has already been emitted.
1577 There is nothing else to do. */
1580 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1581 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1582 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1583 evaluated later in the next else. */
1585 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1587 /* Only add the symbol if the offset is > 0:
1588 if we're at the first frag, check it's size > 0;
1589 if we're not at the first frag, then for sure
1590 the offset is > 0. */
1591 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1592 const int add_symbol
= (frag_now
!= frag_first
)
1593 || (frag_now_fix () > 0);
1596 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1600 mapping_state_2 (state
, 0);
1603 /* Same as mapping_state, but MAX_CHARS bytes have already been
1604 allocated. Put the mapping symbol that far back. */
1607 mapping_state_2 (enum mstate state
, int max_chars
)
1609 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1611 if (!SEG_NORMAL (now_seg
))
1614 if (mapstate
== state
)
1615 /* The mapping symbol has already been emitted.
1616 There is nothing else to do. */
1619 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1620 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1623 #define mapping_state(x) /* nothing */
1624 #define mapping_state_2(x, y) /* nothing */
1627 /* Directives: sectioning and alignment. */
1630 s_bss (int ignore ATTRIBUTE_UNUSED
)
1632 /* We don't support putting frags in the BSS segment, we fake it by
1633 marking in_bss, then looking at s_skip for clues. */
1634 subseg_set (bss_section
, 0);
1635 demand_empty_rest_of_line ();
1636 mapping_state (MAP_DATA
);
1640 s_even (int ignore ATTRIBUTE_UNUSED
)
1642 /* Never make frag if expect extra pass. */
1644 frag_align (1, 0, 0);
1646 record_alignment (now_seg
, 1);
1648 demand_empty_rest_of_line ();
1651 /* Directives: Literal pools. */
1653 static literal_pool
*
1654 find_literal_pool (int size
)
1658 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1660 if (pool
->section
== now_seg
1661 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1668 static literal_pool
*
1669 find_or_make_literal_pool (int size
)
1671 /* Next literal pool ID number. */
1672 static unsigned int latest_pool_num
= 1;
1675 pool
= find_literal_pool (size
);
1679 /* Create a new pool. */
1680 pool
= XNEW (literal_pool
);
1684 /* Currently we always put the literal pool in the current text
1685 section. If we were generating "small" model code where we
1686 knew that all code and initialised data was within 1MB then
1687 we could output literals to mergeable, read-only data
1690 pool
->next_free_entry
= 0;
1691 pool
->section
= now_seg
;
1692 pool
->sub_section
= now_subseg
;
1694 pool
->next
= list_of_pools
;
1695 pool
->symbol
= NULL
;
1697 /* Add it to the list. */
1698 list_of_pools
= pool
;
1701 /* New pools, and emptied pools, will have a NULL symbol. */
1702 if (pool
->symbol
== NULL
)
1704 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1705 &zero_address_frag
, 0);
1706 pool
->id
= latest_pool_num
++;
1713 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1714 Return TRUE on success, otherwise return FALSE. */
1716 add_to_lit_pool (expressionS
*exp
, int size
)
1721 pool
= find_or_make_literal_pool (size
);
1723 /* Check if this literal value is already in the pool. */
1724 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1726 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1728 if ((litexp
->X_op
== exp
->X_op
)
1729 && (exp
->X_op
== O_constant
)
1730 && (litexp
->X_add_number
== exp
->X_add_number
)
1731 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1734 if ((litexp
->X_op
== exp
->X_op
)
1735 && (exp
->X_op
== O_symbol
)
1736 && (litexp
->X_add_number
== exp
->X_add_number
)
1737 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1738 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1742 /* Do we need to create a new entry? */
1743 if (entry
== pool
->next_free_entry
)
1745 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1747 set_syntax_error (_("literal pool overflow"));
1751 pool
->literals
[entry
].exp
= *exp
;
1752 pool
->next_free_entry
+= 1;
1753 if (exp
->X_op
== O_big
)
1755 /* PR 16688: Bignums are held in a single global array. We must
1756 copy and preserve that value now, before it is overwritten. */
1757 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1759 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1760 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1763 pool
->literals
[entry
].bignum
= NULL
;
1766 exp
->X_op
= O_symbol
;
1767 exp
->X_add_number
= ((int) entry
) * size
;
1768 exp
->X_add_symbol
= pool
->symbol
;
1773 /* Can't use symbol_new here, so have to create a symbol and then at
1774 a later date assign it a value. That's what these functions do. */
1777 symbol_locate (symbolS
* symbolP
,
1778 const char *name
,/* It is copied, the caller can modify. */
1779 segT segment
, /* Segment identifier (SEG_<something>). */
1780 valueT valu
, /* Symbol value. */
1781 fragS
* frag
) /* Associated fragment. */
1784 char *preserved_copy_of_name
;
1786 name_length
= strlen (name
) + 1; /* +1 for \0. */
1787 obstack_grow (¬es
, name
, name_length
);
1788 preserved_copy_of_name
= obstack_finish (¬es
);
1790 #ifdef tc_canonicalize_symbol_name
1791 preserved_copy_of_name
=
1792 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1795 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1797 S_SET_SEGMENT (symbolP
, segment
);
1798 S_SET_VALUE (symbolP
, valu
);
1799 symbol_clear_list_pointers (symbolP
);
1801 symbol_set_frag (symbolP
, frag
);
1803 /* Link to end of symbol chain. */
1805 extern int symbol_table_frozen
;
1807 if (symbol_table_frozen
)
1811 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1813 obj_symbol_new_hook (symbolP
);
1815 #ifdef tc_symbol_new_hook
1816 tc_symbol_new_hook (symbolP
);
1820 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1821 #endif /* DEBUG_SYMS */
1826 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1833 for (align
= 2; align
<= 4; align
++)
1835 int size
= 1 << align
;
1837 pool
= find_literal_pool (size
);
1838 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1841 /* Align pool as you have word accesses.
1842 Only make a frag if we have to. */
1844 frag_align (align
, 0, 0);
1846 mapping_state (MAP_DATA
);
1848 record_alignment (now_seg
, align
);
1850 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1852 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1853 (valueT
) frag_now_fix (), frag_now
);
1854 symbol_table_insert (pool
->symbol
);
1856 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1858 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1860 if (exp
->X_op
== O_big
)
1862 /* PR 16688: Restore the global bignum value. */
1863 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1864 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1865 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1868 /* First output the expression in the instruction to the pool. */
1869 emit_expr (exp
, size
); /* .word|.xword */
1871 if (exp
->X_op
== O_big
)
1873 free (pool
->literals
[entry
].bignum
);
1874 pool
->literals
[entry
].bignum
= NULL
;
1878 /* Mark the pool as empty. */
1879 pool
->next_free_entry
= 0;
1880 pool
->symbol
= NULL
;
1885 /* Forward declarations for functions below, in the MD interface
1887 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1888 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1890 /* Directives: Data. */
1891 /* N.B. the support for relocation suffix in this directive needs to be
1892 implemented properly. */
1895 s_aarch64_elf_cons (int nbytes
)
1899 #ifdef md_flush_pending_output
1900 md_flush_pending_output ();
1903 if (is_it_end_of_statement ())
1905 demand_empty_rest_of_line ();
1909 #ifdef md_cons_align
1910 md_cons_align (nbytes
);
1913 mapping_state (MAP_DATA
);
1916 struct reloc_table_entry
*reloc
;
1920 if (exp
.X_op
!= O_symbol
)
1921 emit_expr (&exp
, (unsigned int) nbytes
);
1924 skip_past_char (&input_line_pointer
, '#');
1925 if (skip_past_char (&input_line_pointer
, ':'))
1927 reloc
= find_reloc_table_entry (&input_line_pointer
);
1929 as_bad (_("unrecognized relocation suffix"));
1931 as_bad (_("unimplemented relocation suffix"));
1932 ignore_rest_of_line ();
1936 emit_expr (&exp
, (unsigned int) nbytes
);
1939 while (*input_line_pointer
++ == ',');
1941 /* Put terminator back into stream. */
1942 input_line_pointer
--;
1943 demand_empty_rest_of_line ();
1946 /* Mark symbol that it follows a variant PCS convention. */
1949 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1955 elf_symbol_type
*elfsym
;
1957 c
= get_symbol_name (&name
);
1959 as_bad (_("Missing symbol name in directive"));
1960 sym
= symbol_find_or_make (name
);
1961 restore_line_pointer (c
);
1962 demand_empty_rest_of_line ();
1963 bfdsym
= symbol_get_bfdsym (sym
);
1964 elfsym
= elf_symbol_from (bfdsym
);
1965 gas_assert (elfsym
);
1966 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
1968 #endif /* OBJ_ELF */
1970 /* Output a 32-bit word, but mark as an instruction. */
1973 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1978 #ifdef md_flush_pending_output
1979 md_flush_pending_output ();
1982 if (is_it_end_of_statement ())
1984 demand_empty_rest_of_line ();
1988 /* Sections are assumed to start aligned. In executable section, there is no
1989 MAP_DATA symbol pending. So we only align the address during
1990 MAP_DATA --> MAP_INSN transition.
1991 For other sections, this is not guaranteed. */
1992 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1993 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1994 frag_align_code (2, 0);
1997 mapping_state (MAP_INSN
);
2003 if (exp
.X_op
!= O_constant
)
2005 as_bad (_("constant expression required"));
2006 ignore_rest_of_line ();
2010 if (target_big_endian
)
2012 unsigned int val
= exp
.X_add_number
;
2013 exp
.X_add_number
= SWAP_32 (val
);
2015 emit_expr (&exp
, INSN_SIZE
);
2018 while (*input_line_pointer
++ == ',');
2020 dwarf2_emit_insn (n
* INSN_SIZE
);
2022 /* Put terminator back into stream. */
2023 input_line_pointer
--;
2024 demand_empty_rest_of_line ();
2028 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2030 demand_empty_rest_of_line ();
2031 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2032 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2036 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2039 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2045 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2046 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2048 demand_empty_rest_of_line ();
2051 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2054 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2058 /* Since we're just labelling the code, there's no need to define a
2061 /* Make sure there is enough room in this frag for the following
2062 blr. This trick only works if the blr follows immediately after
2063 the .tlsdesc directive. */
2065 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2066 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2068 demand_empty_rest_of_line ();
2071 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2074 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2080 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2081 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2083 demand_empty_rest_of_line ();
2085 #endif /* OBJ_ELF */
2087 static void s_aarch64_arch (int);
2088 static void s_aarch64_cpu (int);
2089 static void s_aarch64_arch_extension (int);
2091 /* This table describes all the machine specific pseudo-ops the assembler
2092 has to support. The fields are:
2093 pseudo-op name without dot
2094 function to call to execute this pseudo-op
2095 Integer arg to pass to the function. */
2097 const pseudo_typeS md_pseudo_table
[] = {
2098 /* Never called because '.req' does not start a line. */
2100 {"unreq", s_unreq
, 0},
2102 {"even", s_even
, 0},
2103 {"ltorg", s_ltorg
, 0},
2104 {"pool", s_ltorg
, 0},
2105 {"cpu", s_aarch64_cpu
, 0},
2106 {"arch", s_aarch64_arch
, 0},
2107 {"arch_extension", s_aarch64_arch_extension
, 0},
2108 {"inst", s_aarch64_inst
, 0},
2109 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2111 {"tlsdescadd", s_tlsdescadd
, 0},
2112 {"tlsdesccall", s_tlsdesccall
, 0},
2113 {"tlsdescldr", s_tlsdescldr
, 0},
2114 {"word", s_aarch64_elf_cons
, 4},
2115 {"long", s_aarch64_elf_cons
, 4},
2116 {"xword", s_aarch64_elf_cons
, 8},
2117 {"dword", s_aarch64_elf_cons
, 8},
2118 {"variant_pcs", s_variant_pcs
, 0},
2120 {"float16", float_cons
, 'h'},
2121 {"bfloat16", float_cons
, 'b'},
2126 /* Check whether STR points to a register name followed by a comma or the
2127 end of line; REG_TYPE indicates which register types are checked
2128 against. Return TRUE if STR is such a register name; otherwise return
2129 FALSE. The function does not intend to produce any diagnostics, but since
2130 the register parser aarch64_reg_parse, which is called by this function,
2131 does produce diagnostics, we call clear_error to clear any diagnostics
2132 that may be generated by aarch64_reg_parse.
2133 Also, the function returns FALSE directly if there is any user error
2134 present at the function entry. This prevents the existing diagnostics
2135 state from being spoiled.
2136 The function currently serves parse_constant_immediate and
2137 parse_big_immediate only. */
2139 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2143 /* Prevent the diagnostics state from being spoiled. */
2147 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2149 /* Clear the parsing error that may be set by the reg parser. */
2152 if (reg
== PARSE_FAIL
)
2155 skip_whitespace (str
);
2156 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2162 /* Parser functions used exclusively in instruction operands. */
2164 /* Parse an immediate expression which may not be constant.
2166 To prevent the expression parser from pushing a register name
2167 into the symbol table as an undefined symbol, firstly a check is
2168 done to find out whether STR is a register of type REG_TYPE followed
2169 by a comma or the end of line. Return FALSE if STR is such a string. */
2172 parse_immediate_expression (char **str
, expressionS
*exp
,
2173 aarch64_reg_type reg_type
)
2175 if (reg_name_p (*str
, reg_type
))
2177 set_recoverable_error (_("immediate operand required"));
2181 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2183 if (exp
->X_op
== O_absent
)
2185 set_fatal_syntax_error (_("missing immediate expression"));
2192 /* Constant immediate-value read function for use in insn parsing.
2193 STR points to the beginning of the immediate (with the optional
2194 leading #); *VAL receives the value. REG_TYPE says which register
2195 names should be treated as registers rather than as symbolic immediates.
2197 Return TRUE on success; otherwise return FALSE. */
2200 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2204 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2207 if (exp
.X_op
!= O_constant
)
2209 set_syntax_error (_("constant expression required"));
2213 *val
= exp
.X_add_number
;
2218 encode_imm_float_bits (uint32_t imm
)
2220 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2221 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2224 /* Return TRUE if the single-precision floating-point value encoded in IMM
2225 can be expressed in the AArch64 8-bit signed floating-point format with
2226 3-bit exponent and normalized 4 bits of precision; in other words, the
2227 floating-point value must be expressable as
2228 (+/-) n / 16 * power (2, r)
2229 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2232 aarch64_imm_float_p (uint32_t imm
)
2234 /* If a single-precision floating-point value has the following bit
2235 pattern, it can be expressed in the AArch64 8-bit floating-point
2238 3 32222222 2221111111111
2239 1 09876543 21098765432109876543210
2240 n Eeeeeexx xxxx0000000000000000000
2242 where n, e and each x are either 0 or 1 independently, with
2247 /* Prepare the pattern for 'Eeeeee'. */
2248 if (((imm
>> 30) & 0x1) == 0)
2249 pattern
= 0x3e000000;
2251 pattern
= 0x40000000;
2253 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2254 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2257 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2258 as an IEEE float without any loss of precision. Store the value in
2262 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2264 /* If a double-precision floating-point value has the following bit
2265 pattern, it can be expressed in a float:
2267 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2268 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2269 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2271 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2272 if Eeee_eeee != 1111_1111
2274 where n, e, s and S are either 0 or 1 independently and where ~ is the
2278 uint32_t high32
= imm
>> 32;
2279 uint32_t low32
= imm
;
2281 /* Lower 29 bits need to be 0s. */
2282 if ((imm
& 0x1fffffff) != 0)
2285 /* Prepare the pattern for 'Eeeeeeeee'. */
2286 if (((high32
>> 30) & 0x1) == 0)
2287 pattern
= 0x38000000;
2289 pattern
= 0x40000000;
2292 if ((high32
& 0x78000000) != pattern
)
2295 /* Check Eeee_eeee != 1111_1111. */
2296 if ((high32
& 0x7ff00000) == 0x47f00000)
2299 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2300 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2301 | (low32
>> 29)); /* 3 S bits. */
2305 /* Return true if we should treat OPERAND as a double-precision
2306 floating-point operand rather than a single-precision one. */
2308 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2310 /* Check for unsuffixed SVE registers, which are allowed
2311 for LDR and STR but not in instructions that require an
2312 immediate. We get better error messages if we arbitrarily
2313 pick one size, parse the immediate normally, and then
2314 report the match failure in the normal way. */
2315 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2316 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2319 /* Parse a floating-point immediate. Return TRUE on success and return the
2320 value in *IMMED in the format of IEEE754 single-precision encoding.
2321 *CCP points to the start of the string; DP_P is TRUE when the immediate
2322 is expected to be in double-precision (N.B. this only matters when
2323 hexadecimal representation is involved). REG_TYPE says which register
2324 names should be treated as registers rather than as symbolic immediates.
2326 This routine accepts any IEEE float; it is up to the callers to reject
2330 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2331 aarch64_reg_type reg_type
)
2335 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2337 unsigned fpword
= 0;
2340 skip_past_char (&str
, '#');
2343 skip_whitespace (fpnum
);
2345 if (startswith (fpnum
, "0x"))
2347 /* Support the hexadecimal representation of the IEEE754 encoding.
2348 Double-precision is expected when DP_P is TRUE, otherwise the
2349 representation should be in single-precision. */
2350 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2355 if (!can_convert_double_to_float (val
, &fpword
))
2358 else if ((uint64_t) val
> 0xffffffff)
2365 else if (reg_name_p (str
, reg_type
))
2367 set_recoverable_error (_("immediate operand required"));
2375 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2378 /* Our FP word must be 32 bits (single-precision FP). */
2379 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2381 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2391 set_fatal_syntax_error (_("invalid floating-point constant"));
2395 /* Less-generic immediate-value read function with the possibility of loading
2396 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2399 To prevent the expression parser from pushing a register name into the
2400 symbol table as an undefined symbol, a check is firstly done to find
2401 out whether STR is a register of type REG_TYPE followed by a comma or
2402 the end of line. Return FALSE if STR is such a register. */
2405 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2409 if (reg_name_p (ptr
, reg_type
))
2411 set_syntax_error (_("immediate operand required"));
2415 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
);
2417 if (inst
.reloc
.exp
.X_op
== O_constant
)
2418 *imm
= inst
.reloc
.exp
.X_add_number
;
2425 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2426 if NEED_LIBOPCODES is non-zero, the fixup will need
2427 assistance from the libopcodes. */
2430 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2431 const aarch64_opnd_info
*operand
,
2432 int need_libopcodes_p
)
2434 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2435 reloc
->opnd
= operand
->type
;
2436 if (need_libopcodes_p
)
2437 reloc
->need_libopcodes_p
= 1;
2440 /* Return TRUE if the instruction needs to be fixed up later internally by
2441 the GAS; otherwise return FALSE. */
2444 aarch64_gas_internal_fixup_p (void)
2446 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2449 /* Assign the immediate value to the relevant field in *OPERAND if
2450 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2451 needs an internal fixup in a later stage.
2452 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2453 IMM.VALUE that may get assigned with the constant. */
2455 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2456 aarch64_opnd_info
*operand
,
2458 int need_libopcodes_p
,
2461 if (reloc
->exp
.X_op
== O_constant
)
2464 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2466 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2467 reloc
->type
= BFD_RELOC_UNUSED
;
2471 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2472 /* Tell libopcodes to ignore this operand or not. This is helpful
2473 when one of the operands needs to be fixed up later but we need
2474 libopcodes to check the other operands. */
2475 operand
->skip
= skip_p
;
2479 /* Relocation modifiers. Each entry in the table contains the textual
2480 name for the relocation which may be placed before a symbol used as
2481 a load/store offset, or add immediate. It must be surrounded by a
2482 leading and trailing colon, for example:
2484 ldr x0, [x1, #:rello:varsym]
2485 add x0, x1, #:rello:varsym */
2487 struct reloc_table_entry
2491 bfd_reloc_code_real_type adr_type
;
2492 bfd_reloc_code_real_type adrp_type
;
2493 bfd_reloc_code_real_type movw_type
;
2494 bfd_reloc_code_real_type add_type
;
2495 bfd_reloc_code_real_type ldst_type
;
2496 bfd_reloc_code_real_type ld_literal_type
;
2499 static struct reloc_table_entry reloc_table
[] =
2501 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2506 BFD_RELOC_AARCH64_ADD_LO12
,
2507 BFD_RELOC_AARCH64_LDST_LO12
,
2510 /* Higher 21 bits of pc-relative page offset: ADRP */
2513 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2519 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2522 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2528 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2532 BFD_RELOC_AARCH64_MOVW_G0
,
2537 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2541 BFD_RELOC_AARCH64_MOVW_G0_S
,
2546 /* Less significant bits 0-15 of address/value: MOVK, no check */
2550 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2555 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2559 BFD_RELOC_AARCH64_MOVW_G1
,
2564 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2568 BFD_RELOC_AARCH64_MOVW_G1_S
,
2573 /* Less significant bits 16-31 of address/value: MOVK, no check */
2577 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2582 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2586 BFD_RELOC_AARCH64_MOVW_G2
,
2591 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2595 BFD_RELOC_AARCH64_MOVW_G2_S
,
2600 /* Less significant bits 32-47 of address/value: MOVK, no check */
2604 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2609 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2613 BFD_RELOC_AARCH64_MOVW_G3
,
2618 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2622 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2627 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2631 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2636 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2640 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2645 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2649 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2654 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2658 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2663 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2667 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2672 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2676 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2681 /* Get to the page containing GOT entry for a symbol. */
2684 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2688 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2690 /* 12 bit offset into the page containing GOT entry for that symbol. */
2696 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2699 /* 0-15 bits of address/value: MOVk, no check. */
2703 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2708 /* Most significant bits 16-31 of address/value: MOVZ. */
2712 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2717 /* 15 bit offset into the page containing GOT entry for that symbol. */
2723 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2726 /* Get to the page containing GOT TLS entry for a symbol */
2727 {"gottprel_g0_nc", 0,
2730 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2735 /* Get to the page containing GOT TLS entry for a symbol */
2739 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2744 /* Get to the page containing GOT TLS entry for a symbol */
2746 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2747 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2753 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2758 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2762 /* Lower 16 bits address/value: MOVk. */
2766 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2771 /* Most significant bits 16-31 of address/value: MOVZ. */
2775 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2780 /* Get to the page containing GOT TLS entry for a symbol */
2782 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2783 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2787 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2789 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2794 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2795 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2798 /* Get to the page containing GOT TLS entry for a symbol.
2799 The same as GD, we allocate two consecutive GOT slots
2800 for module index and module offset, the only difference
2801 with GD is the module offset should be initialized to
2802 zero without any outstanding runtime relocation. */
2804 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2805 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2811 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2812 {"tlsldm_lo12_nc", 0,
2816 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2820 /* 12 bit offset into the module TLS base address. */
2825 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2826 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2829 /* Same as dtprel_lo12, no overflow check. */
2830 {"dtprel_lo12_nc", 0,
2834 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2835 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2838 /* bits[23:12] of offset to the module TLS base address. */
2843 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2847 /* bits[15:0] of offset to the module TLS base address. */
2851 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2856 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2860 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2865 /* bits[31:16] of offset to the module TLS base address. */
2869 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2874 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2878 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2883 /* bits[47:32] of offset to the module TLS base address. */
2887 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2892 /* Lower 16 bit offset into GOT entry for a symbol */
2893 {"tlsdesc_off_g0_nc", 0,
2896 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2901 /* Higher 16 bit offset into GOT entry for a symbol */
2902 {"tlsdesc_off_g1", 0,
2905 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2910 /* Get to the page containing GOT TLS entry for a symbol */
2913 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2917 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2919 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2920 {"gottprel_lo12", 0,
2925 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2928 /* Get tp offset for a symbol. */
2933 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2937 /* Get tp offset for a symbol. */
2942 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2943 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2946 /* Get tp offset for a symbol. */
2951 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2955 /* Get tp offset for a symbol. */
2956 {"tprel_lo12_nc", 0,
2960 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2961 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2964 /* Most significant bits 32-47 of address/value: MOVZ. */
2968 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2973 /* Most significant bits 16-31 of address/value: MOVZ. */
2977 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2982 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2986 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2991 /* Most significant bits 0-15 of address/value: MOVZ. */
2995 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3000 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3004 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3009 /* 15bit offset from got entry to base address of GOT table. */
3015 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3018 /* 14bit offset from got entry to base address of GOT table. */
3024 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3028 /* Given the address of a pointer pointing to the textual name of a
3029 relocation as may appear in assembler source, attempt to find its
3030 details in reloc_table. The pointer will be updated to the character
3031 after the trailing colon. On failure, NULL will be returned;
3032 otherwise return the reloc_table_entry. */
3034 static struct reloc_table_entry
*
3035 find_reloc_table_entry (char **str
)
3038 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3040 int length
= strlen (reloc_table
[i
].name
);
3042 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3043 && (*str
)[length
] == ':')
3045 *str
+= (length
+ 1);
3046 return &reloc_table
[i
];
3053 /* Returns 0 if the relocation should never be forced,
3054 1 if the relocation must be forced, and -1 if either
3058 aarch64_force_reloc (unsigned int type
)
3062 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3063 /* Perform these "immediate" internal relocations
3064 even if the symbol is extern or weak. */
3067 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3068 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3069 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3070 /* Pseudo relocs that need to be fixed up according to
3074 case BFD_RELOC_AARCH64_ADD_LO12
:
3075 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3076 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3077 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3078 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3079 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3080 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3081 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3082 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3083 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3084 case BFD_RELOC_AARCH64_LDST128_LO12
:
3085 case BFD_RELOC_AARCH64_LDST16_LO12
:
3086 case BFD_RELOC_AARCH64_LDST32_LO12
:
3087 case BFD_RELOC_AARCH64_LDST64_LO12
:
3088 case BFD_RELOC_AARCH64_LDST8_LO12
:
3089 case BFD_RELOC_AARCH64_LDST_LO12
:
3090 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3091 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3092 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3093 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3094 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3095 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3096 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3097 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3098 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3099 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3100 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3101 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3102 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3103 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3104 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3105 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3106 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3107 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3108 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3109 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3110 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3111 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3112 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3113 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3114 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3115 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3116 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3117 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3118 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3119 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3120 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3121 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3122 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3123 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
:
3124 case BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
:
3125 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3126 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3127 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3128 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3129 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3130 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3131 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3132 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3133 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3134 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3135 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3136 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3137 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3138 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
:
3139 case BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
:
3140 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3141 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3142 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3143 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3144 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3145 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3146 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3147 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3148 /* Always leave these relocations for the linker. */
3157 aarch64_force_relocation (struct fix
*fixp
)
3159 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3162 return generic_force_reloc (fixp
);
3166 /* Mode argument to parse_shift and parser_shifter_operand. */
3167 enum parse_shift_mode
3169 SHIFTED_NONE
, /* no shifter allowed */
3170 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3172 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3174 SHIFTED_LSL
, /* bare "lsl #n" */
3175 SHIFTED_MUL
, /* bare "mul #n" */
3176 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3177 SHIFTED_MUL_VL
, /* "mul vl" */
3178 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3181 /* Parse a <shift> operator on an AArch64 data processing instruction.
3182 Return TRUE on success; otherwise return FALSE. */
3184 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3186 const struct aarch64_name_value_pair
*shift_op
;
3187 enum aarch64_modifier_kind kind
;
3193 for (p
= *str
; ISALPHA (*p
); p
++)
3198 set_syntax_error (_("shift expression expected"));
3202 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3204 if (shift_op
== NULL
)
3206 set_syntax_error (_("shift operator expected"));
3210 kind
= aarch64_get_operand_modifier (shift_op
);
3212 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3214 set_syntax_error (_("invalid use of 'MSL'"));
3218 if (kind
== AARCH64_MOD_MUL
3219 && mode
!= SHIFTED_MUL
3220 && mode
!= SHIFTED_MUL_VL
)
3222 set_syntax_error (_("invalid use of 'MUL'"));
3228 case SHIFTED_LOGIC_IMM
:
3229 if (aarch64_extend_operator_p (kind
))
3231 set_syntax_error (_("extending shift is not permitted"));
3236 case SHIFTED_ARITH_IMM
:
3237 if (kind
== AARCH64_MOD_ROR
)
3239 set_syntax_error (_("'ROR' shift is not permitted"));
3245 if (kind
!= AARCH64_MOD_LSL
)
3247 set_syntax_error (_("only 'LSL' shift is permitted"));
3253 if (kind
!= AARCH64_MOD_MUL
)
3255 set_syntax_error (_("only 'MUL' is permitted"));
3260 case SHIFTED_MUL_VL
:
3261 /* "MUL VL" consists of two separate tokens. Require the first
3262 token to be "MUL" and look for a following "VL". */
3263 if (kind
== AARCH64_MOD_MUL
)
3265 skip_whitespace (p
);
3266 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3269 kind
= AARCH64_MOD_MUL_VL
;
3273 set_syntax_error (_("only 'MUL VL' is permitted"));
3276 case SHIFTED_REG_OFFSET
:
3277 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3278 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3280 set_fatal_syntax_error
3281 (_("invalid shift for the register offset addressing mode"));
3286 case SHIFTED_LSL_MSL
:
3287 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3289 set_syntax_error (_("invalid shift operator"));
3298 /* Whitespace can appear here if the next thing is a bare digit. */
3299 skip_whitespace (p
);
3301 /* Parse shift amount. */
3303 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3304 exp
.X_op
= O_absent
;
3307 if (is_immediate_prefix (*p
))
3312 aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
);
3314 if (kind
== AARCH64_MOD_MUL_VL
)
3315 /* For consistency, give MUL VL the same shift amount as an implicit
3317 operand
->shifter
.amount
= 1;
3318 else if (exp
.X_op
== O_absent
)
3320 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3322 set_syntax_error (_("missing shift amount"));
3325 operand
->shifter
.amount
= 0;
3327 else if (exp
.X_op
!= O_constant
)
3329 set_syntax_error (_("constant shift amount required"));
3332 /* For parsing purposes, MUL #n has no inherent range. The range
3333 depends on the operand and will be checked by operand-specific
3335 else if (kind
!= AARCH64_MOD_MUL
3336 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3338 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3343 operand
->shifter
.amount
= exp
.X_add_number
;
3344 operand
->shifter
.amount_present
= 1;
3347 operand
->shifter
.operator_present
= 1;
3348 operand
->shifter
.kind
= kind
;
3354 /* Parse a <shifter_operand> for a data processing instruction:
3357 #<immediate>, LSL #imm
3359 Validation of immediate operands is deferred to md_apply_fix.
3361 Return TRUE on success; otherwise return FALSE. */
3364 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3365 enum parse_shift_mode mode
)
3369 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3374 /* Accept an immediate expression. */
3375 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3379 /* Accept optional LSL for arithmetic immediate values. */
3380 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3381 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3384 /* Not accept any shifter for logical immediate values. */
3385 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3386 && parse_shift (&p
, operand
, mode
))
3388 set_syntax_error (_("unexpected shift operator"));
3396 /* Parse a <shifter_operand> for a data processing instruction:
3401 #<immediate>, LSL #imm
3403 where <shift> is handled by parse_shift above, and the last two
3404 cases are handled by the function above.
3406 Validation of immediate operands is deferred to md_apply_fix.
3408 Return TRUE on success; otherwise return FALSE. */
3411 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3412 enum parse_shift_mode mode
)
3414 const reg_entry
*reg
;
3415 aarch64_opnd_qualifier_t qualifier
;
3416 enum aarch64_operand_class opd_class
3417 = aarch64_get_operand_class (operand
->type
);
3419 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3422 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3424 set_syntax_error (_("unexpected register in the immediate operand"));
3428 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3430 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3434 operand
->reg
.regno
= reg
->number
;
3435 operand
->qualifier
= qualifier
;
3437 /* Accept optional shift operation on register. */
3438 if (! skip_past_comma (str
))
3441 if (! parse_shift (str
, operand
, mode
))
3446 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3449 (_("integer register expected in the extended/shifted operand "
3454 /* We have a shifted immediate variable. */
3455 return parse_shifter_operand_imm (str
, operand
, mode
);
3458 /* Return TRUE on success; return FALSE otherwise. */
3461 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3462 enum parse_shift_mode mode
)
3466 /* Determine if we have the sequence of characters #: or just :
3467 coming next. If we do, then we check for a :rello: relocation
3468 modifier. If we don't, punt the whole lot to
3469 parse_shifter_operand. */
3471 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3473 struct reloc_table_entry
*entry
;
3481 /* Try to parse a relocation. Anything else is an error. */
3482 if (!(entry
= find_reloc_table_entry (str
)))
3484 set_syntax_error (_("unknown relocation modifier"));
3488 if (entry
->add_type
== 0)
3491 (_("this relocation modifier is not allowed on this instruction"));
3495 /* Save str before we decompose it. */
3498 /* Next, we parse the expression. */
3499 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3503 /* Record the relocation type (use the ADD variant here). */
3504 inst
.reloc
.type
= entry
->add_type
;
3505 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3507 /* If str is empty, we've reached the end, stop here. */
3511 /* Otherwise, we have a shifted reloc modifier, so rewind to
3512 recover the variable name and continue parsing for the shifter. */
3514 return parse_shifter_operand_imm (str
, operand
, mode
);
3517 return parse_shifter_operand (str
, operand
, mode
);
3520 /* Parse all forms of an address expression. Information is written
3521 to *OPERAND and/or inst.reloc.
3523 The A64 instruction set has the following addressing modes:
3526 [base] // in SIMD ld/st structure
3527 [base{,#0}] // in ld/st exclusive
3529 [base,Xm{,LSL #imm}]
3530 [base,Xm,SXTX {#imm}]
3531 [base,Wm,(S|U)XTW {#imm}]
3533 [base]! // in ldraa/ldrab exclusive
3537 [base],Xm // in SIMD ld/st structure
3538 PC-relative (literal)
3542 [base,Zm.D{,LSL #imm}]
3543 [base,Zm.S,(S|U)XTW {#imm}]
3544 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3548 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3549 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3550 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3552 (As a convenience, the notation "=immediate" is permitted in conjunction
3553 with the pc-relative literal load instructions to automatically place an
3554 immediate value or symbolic address in a nearby literal pool and generate
3555 a hidden label which references it.)
3557 Upon a successful parsing, the address structure in *OPERAND will be
3558 filled in the following way:
3560 .base_regno = <base>
3561 .offset.is_reg // 1 if the offset is a register
3563 .offset.regno = <Rm>
3565 For different addressing modes defined in the A64 ISA:
3568 .pcrel=0; .preind=1; .postind=0; .writeback=0
3570 .pcrel=0; .preind=1; .postind=0; .writeback=1
3572 .pcrel=0; .preind=0; .postind=1; .writeback=1
3573 PC-relative (literal)
3574 .pcrel=1; .preind=1; .postind=0; .writeback=0
3576 The shift/extension information, if any, will be stored in .shifter.
3577 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3578 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3579 corresponding register.
3581 BASE_TYPE says which types of base register should be accepted and
3582 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3583 is the type of shifter that is allowed for immediate offsets,
3584 or SHIFTED_NONE if none.
3586 In all other respects, it is the caller's responsibility to check
3587 for addressing modes not supported by the instruction, and to set
3591 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3592 aarch64_opnd_qualifier_t
*base_qualifier
,
3593 aarch64_opnd_qualifier_t
*offset_qualifier
,
3594 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3595 enum parse_shift_mode imm_shift_mode
)
3598 const reg_entry
*reg
;
3599 expressionS
*exp
= &inst
.reloc
.exp
;
3601 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3602 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3603 if (! skip_past_char (&p
, '['))
3605 /* =immediate or label. */
3606 operand
->addr
.pcrel
= 1;
3607 operand
->addr
.preind
= 1;
3609 /* #:<reloc_op>:<symbol> */
3610 skip_past_char (&p
, '#');
3611 if (skip_past_char (&p
, ':'))
3613 bfd_reloc_code_real_type ty
;
3614 struct reloc_table_entry
*entry
;
3616 /* Try to parse a relocation modifier. Anything else is
3618 entry
= find_reloc_table_entry (&p
);
3621 set_syntax_error (_("unknown relocation modifier"));
3625 switch (operand
->type
)
3627 case AARCH64_OPND_ADDR_PCREL21
:
3629 ty
= entry
->adr_type
;
3633 ty
= entry
->ld_literal_type
;
3640 (_("this relocation modifier is not allowed on this "
3646 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3648 set_syntax_error (_("invalid relocation expression"));
3651 /* #:<reloc_op>:<expr> */
3652 /* Record the relocation type. */
3653 inst
.reloc
.type
= ty
;
3654 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3658 if (skip_past_char (&p
, '='))
3659 /* =immediate; need to generate the literal in the literal pool. */
3660 inst
.gen_lit_pool
= 1;
3662 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3664 set_syntax_error (_("invalid address"));
3675 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3676 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3678 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3681 operand
->addr
.base_regno
= reg
->number
;
3684 if (skip_past_comma (&p
))
3687 operand
->addr
.preind
= 1;
3689 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3692 if (!aarch64_check_reg_type (reg
, offset_type
))
3694 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3699 operand
->addr
.offset
.regno
= reg
->number
;
3700 operand
->addr
.offset
.is_reg
= 1;
3701 /* Shifted index. */
3702 if (skip_past_comma (&p
))
3705 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3706 /* Use the diagnostics set in parse_shift, so not set new
3707 error message here. */
3711 [base,Xm] # For vector plus scalar SVE2 indexing.
3712 [base,Xm{,LSL #imm}]
3713 [base,Xm,SXTX {#imm}]
3714 [base,Wm,(S|U)XTW {#imm}] */
3715 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3716 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3717 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3719 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3721 set_syntax_error (_("invalid use of 32-bit register offset"));
3724 if (aarch64_get_qualifier_esize (*base_qualifier
)
3725 != aarch64_get_qualifier_esize (*offset_qualifier
)
3726 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3727 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3728 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3730 set_syntax_error (_("offset has different size from base"));
3734 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3736 set_syntax_error (_("invalid use of 64-bit register offset"));
3742 /* [Xn,#:<reloc_op>:<symbol> */
3743 skip_past_char (&p
, '#');
3744 if (skip_past_char (&p
, ':'))
3746 struct reloc_table_entry
*entry
;
3748 /* Try to parse a relocation modifier. Anything else is
3750 if (!(entry
= find_reloc_table_entry (&p
)))
3752 set_syntax_error (_("unknown relocation modifier"));
3756 if (entry
->ldst_type
== 0)
3759 (_("this relocation modifier is not allowed on this "
3764 /* [Xn,#:<reloc_op>: */
3765 /* We now have the group relocation table entry corresponding to
3766 the name in the assembler source. Next, we parse the
3768 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3770 set_syntax_error (_("invalid relocation expression"));
3774 /* [Xn,#:<reloc_op>:<expr> */
3775 /* Record the load/store relocation type. */
3776 inst
.reloc
.type
= entry
->ldst_type
;
3777 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3781 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
3783 set_syntax_error (_("invalid expression in the address"));
3787 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3788 /* [Xn,<expr>,<shifter> */
3789 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3795 if (! skip_past_char (&p
, ']'))
3797 set_syntax_error (_("']' expected"));
3801 if (skip_past_char (&p
, '!'))
3803 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3805 set_syntax_error (_("register offset not allowed in pre-indexed "
3806 "addressing mode"));
3810 operand
->addr
.writeback
= 1;
3812 else if (skip_past_comma (&p
))
3815 operand
->addr
.postind
= 1;
3816 operand
->addr
.writeback
= 1;
3818 if (operand
->addr
.preind
)
3820 set_syntax_error (_("cannot combine pre- and post-indexing"));
3824 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3828 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3830 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3834 operand
->addr
.offset
.regno
= reg
->number
;
3835 operand
->addr
.offset
.is_reg
= 1;
3837 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
))
3840 set_syntax_error (_("invalid expression in the address"));
3845 /* If at this point neither .preind nor .postind is set, we have a
3846 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3847 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3848 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3850 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3852 if (operand
->addr
.writeback
)
3854 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3856 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3857 operand
->addr
.offset
.is_reg
= 0;
3858 operand
->addr
.offset
.imm
= 0;
3859 operand
->addr
.preind
= 1;
3864 set_syntax_error (_("missing offset in the pre-indexed address"));
3870 operand
->addr
.preind
= 1;
3871 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3873 operand
->addr
.offset
.is_reg
= 1;
3874 operand
->addr
.offset
.regno
= REG_ZR
;
3875 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3879 inst
.reloc
.exp
.X_op
= O_constant
;
3880 inst
.reloc
.exp
.X_add_number
= 0;
3889 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3892 parse_address (char **str
, aarch64_opnd_info
*operand
)
3894 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3895 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3896 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3899 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3900 The arguments have the same meaning as for parse_address_main.
3901 Return TRUE on success. */
3903 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3904 aarch64_opnd_qualifier_t
*base_qualifier
,
3905 aarch64_opnd_qualifier_t
*offset_qualifier
)
3907 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3908 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3912 /* Parse a register X0-X30. The register must be 64-bit and register 31
3915 parse_x0_to_x30 (char **str
, aarch64_opnd_info
*operand
)
3917 const reg_entry
*reg
= parse_reg (str
);
3918 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3920 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3923 operand
->reg
.regno
= reg
->number
;
3924 operand
->qualifier
= AARCH64_OPND_QLF_X
;
3928 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3929 Return TRUE on success; otherwise return FALSE. */
3931 parse_half (char **str
, int *internal_fixup_p
)
3935 skip_past_char (&p
, '#');
3937 gas_assert (internal_fixup_p
);
3938 *internal_fixup_p
= 0;
3942 struct reloc_table_entry
*entry
;
3944 /* Try to parse a relocation. Anything else is an error. */
3947 if (!(entry
= find_reloc_table_entry (&p
)))
3949 set_syntax_error (_("unknown relocation modifier"));
3953 if (entry
->movw_type
== 0)
3956 (_("this relocation modifier is not allowed on this instruction"));
3960 inst
.reloc
.type
= entry
->movw_type
;
3963 *internal_fixup_p
= 1;
3965 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
3972 /* Parse an operand for an ADRP instruction:
3974 Return TRUE on success; otherwise return FALSE. */
3977 parse_adrp (char **str
)
3984 struct reloc_table_entry
*entry
;
3986 /* Try to parse a relocation. Anything else is an error. */
3988 if (!(entry
= find_reloc_table_entry (&p
)))
3990 set_syntax_error (_("unknown relocation modifier"));
3994 if (entry
->adrp_type
== 0)
3997 (_("this relocation modifier is not allowed on this instruction"));
4001 inst
.reloc
.type
= entry
->adrp_type
;
4004 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4006 inst
.reloc
.pc_rel
= 1;
4007 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
))
4013 /* Miscellaneous. */
4015 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4016 of SIZE tokens in which index I gives the token for field value I,
4017 or is null if field value I is invalid. REG_TYPE says which register
4018 names should be treated as registers rather than as symbolic immediates.
4020 Return true on success, moving *STR past the operand and storing the
4021 field value in *VAL. */
4024 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4025 size_t size
, aarch64_reg_type reg_type
)
4031 /* Match C-like tokens. */
4033 while (ISALNUM (*q
))
4036 for (i
= 0; i
< size
; ++i
)
4038 && strncasecmp (array
[i
], p
, q
- p
) == 0
4039 && array
[i
][q
- p
] == 0)
4046 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4049 if (exp
.X_op
== O_constant
4050 && (uint64_t) exp
.X_add_number
< size
)
4052 *val
= exp
.X_add_number
;
4057 /* Use the default error for this operand. */
4061 /* Parse an option for a preload instruction. Returns the encoding for the
4062 option, or PARSE_FAIL. */
4065 parse_pldop (char **str
)
4068 const struct aarch64_name_value_pair
*o
;
4071 while (ISALNUM (*q
))
4074 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4082 /* Parse an option for a barrier instruction. Returns the encoding for the
4083 option, or PARSE_FAIL. */
4086 parse_barrier (char **str
)
4089 const struct aarch64_name_value_pair
*o
;
4092 while (ISALPHA (*q
))
4095 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4103 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4104 return 0 if successful. Otherwise return PARSE_FAIL. */
4107 parse_barrier_psb (char **str
,
4108 const struct aarch64_name_value_pair
** hint_opt
)
4111 const struct aarch64_name_value_pair
*o
;
4114 while (ISALPHA (*q
))
4117 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4120 set_fatal_syntax_error
4121 ( _("unknown or missing option to PSB/TSB"));
4125 if (o
->value
!= 0x11)
4127 /* PSB only accepts option name 'CSYNC'. */
4129 (_("the specified option is not accepted for PSB/TSB"));
4138 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4139 return 0 if successful. Otherwise return PARSE_FAIL. */
4142 parse_bti_operand (char **str
,
4143 const struct aarch64_name_value_pair
** hint_opt
)
4146 const struct aarch64_name_value_pair
*o
;
4149 while (ISALPHA (*q
))
4152 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4155 set_fatal_syntax_error
4156 ( _("unknown option to BTI"));
4162 /* Valid BTI operands. */
4170 (_("unknown option to BTI"));
4179 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4180 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4185 Side effect: Update STR with current parse position of success.
4188 static const reg_entry
*
4189 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4190 aarch64_opnd_qualifier_t
*qualifier
)
4194 reg_entry
*reg
= parse_reg (str
);
4195 if (reg
!= NULL
&& reg
->type
== reg_type
)
4197 if (!skip_past_char (str
, '.'))
4199 set_syntax_error (_("missing ZA tile element size separator"));
4204 switch (TOLOWER (*q
))
4207 *qualifier
= AARCH64_OPND_QLF_S_B
;
4210 *qualifier
= AARCH64_OPND_QLF_S_H
;
4213 *qualifier
= AARCH64_OPND_QLF_S_S
;
4216 *qualifier
= AARCH64_OPND_QLF_S_D
;
4219 *qualifier
= AARCH64_OPND_QLF_S_Q
;
4233 /* Parse SME ZA tile encoded in <ZAda> assembler symbol.
4234 Function return tile QUALIFIER on success.
4236 Tiles are in example format: za[0-9]\.[bhsd]
4238 Function returns <ZAda> register number or PARSE_FAIL.
4241 parse_sme_zada_operand (char **str
, aarch64_opnd_qualifier_t
*qualifier
)
4244 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_ZA
, qualifier
);
4248 regno
= reg
->number
;
4252 case AARCH64_OPND_QLF_S_B
:
4255 set_syntax_error (_("invalid ZA tile register number, expected za0"));
4259 case AARCH64_OPND_QLF_S_H
:
4262 set_syntax_error (_("invalid ZA tile register number, expected za0-za1"));
4266 case AARCH64_OPND_QLF_S_S
:
4269 /* For the 32-bit variant: is the name of the ZA tile ZA0-ZA3. */
4270 set_syntax_error (_("invalid ZA tile register number, expected za0-za3"));
4274 case AARCH64_OPND_QLF_S_D
:
4277 /* For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 */
4278 set_syntax_error (_("invalid ZA tile register number, expected za0-za7"));
4283 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s and d"));
4290 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4295 Function return TRUE if immediate was found, or FALSE.
4298 parse_sme_immediate (char **str
, int64_t *imm
)
4301 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4308 /* Parse index with vector select register and immediate:
4312 where <Wv> is in W12-W15 range and # is optional for immediate.
4314 Function performs extra check for mandatory immediate value if REQUIRE_IMM
4317 On success function returns TRUE and populated VECTOR_SELECT_REGISTER and
4321 parse_sme_za_hv_tiles_operand_index (char **str
,
4322 int *vector_select_register
,
4325 const reg_entry
*reg
;
4327 if (!skip_past_char (str
, '['))
4329 set_syntax_error (_("expected '['"));
4333 /* Vector select register W12-W15 encoded in the 2-bit Rv field. */
4334 reg
= parse_reg (str
);
4335 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
4336 || reg
->number
< 12 || reg
->number
> 15)
4338 set_syntax_error (_("expected vector select register W12-W15"));
4341 *vector_select_register
= reg
->number
;
4343 if (!skip_past_char (str
, ',')) /* Optional index offset immediate. */
4345 set_syntax_error (_("expected ','"));
4349 if (!parse_sme_immediate (str
, imm
))
4351 set_syntax_error (_("index offset immediate expected"));
4355 if (!skip_past_char (str
, ']'))
4357 set_syntax_error (_("expected ']'"));
4364 /* Parse SME ZA horizontal or vertical vector access to tiles.
4365 Function extracts from STR to SLICE_INDICATOR <HV> horizontal (0) or
4366 vertical (1) ZA tile vector orientation. VECTOR_SELECT_REGISTER
4367 contains <Wv> select register and corresponding optional IMMEDIATE.
4368 In addition QUALIFIER is extracted.
4370 Field format examples:
4372 ZA0<HV>.B[<Wv>, #<imm>]
4373 <ZAn><HV>.H[<Wv>, #<imm>]
4374 <ZAn><HV>.S[<Wv>, #<imm>]
4375 <ZAn><HV>.D[<Wv>, #<imm>]
4376 <ZAn><HV>.Q[<Wv>, #<imm>]
4378 Function returns <ZAda> register number or PARSE_FAIL.
4381 parse_sme_za_hv_tiles_operand (char **str
,
4382 enum sme_hv_slice
*slice_indicator
,
4383 int *vector_select_register
,
4385 aarch64_opnd_qualifier_t
*qualifier
)
4392 const reg_entry
*reg
;
4395 if ((reg
= parse_reg_with_qual (&qh
, REG_TYPE_ZAH
, qualifier
)) != NULL
)
4397 *slice_indicator
= HV_horizontal
;
4400 else if ((reg
= parse_reg_with_qual (&qv
, REG_TYPE_ZAV
, qualifier
)) != NULL
)
4402 *slice_indicator
= HV_vertical
;
4407 regno
= reg
->number
;
4411 case AARCH64_OPND_QLF_S_B
:
4415 case AARCH64_OPND_QLF_S_H
:
4419 case AARCH64_OPND_QLF_S_S
:
4423 case AARCH64_OPND_QLF_S_D
:
4427 case AARCH64_OPND_QLF_S_Q
:
4432 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q"));
4436 /* Check if destination register ZA tile vector is in range for given
4437 instruction variant. */
4438 if (regno
< 0 || regno
> regno_limit
)
4440 set_syntax_error (_("ZA tile vector out of range"));
4444 if (!parse_sme_za_hv_tiles_operand_index (str
, vector_select_register
,
4448 /* Check if optional index offset is in the range for instruction
4450 if (imm_value
< 0 || imm_value
> imm_limit
)
4452 set_syntax_error (_("index offset out of range"));
4463 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4464 enum sme_hv_slice
*slice_indicator
,
4465 int *vector_select_register
,
4467 aarch64_opnd_qualifier_t
*qualifier
)
4471 if (!skip_past_char (str
, '{'))
4473 set_syntax_error (_("expected '{'"));
4477 regno
= parse_sme_za_hv_tiles_operand (str
, slice_indicator
,
4478 vector_select_register
, imm
,
4481 if (regno
== PARSE_FAIL
)
4484 if (!skip_past_char (str
, '}'))
4486 set_syntax_error (_("expected '}'"));
4493 /* Parse list of up to eight 64-bit element tile names separated by commas in
4494 SME's ZERO instruction:
4498 Function returns <mask>:
4500 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4503 parse_sme_zero_mask(char **str
)
4507 aarch64_opnd_qualifier_t qualifier
;
4513 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZA
, &qualifier
);
4516 int regno
= reg
->number
;
4517 if (qualifier
== AARCH64_OPND_QLF_S_B
&& regno
== 0)
4519 /* { ZA0.B } is assembled as all-ones immediate. */
4522 else if (qualifier
== AARCH64_OPND_QLF_S_H
&& regno
< 2)
4523 mask
|= 0x55 << regno
;
4524 else if (qualifier
== AARCH64_OPND_QLF_S_S
&& regno
< 4)
4525 mask
|= 0x11 << regno
;
4526 else if (qualifier
== AARCH64_OPND_QLF_S_D
&& regno
< 8)
4527 mask
|= 0x01 << regno
;
4530 set_syntax_error (_("wrong ZA tile element format"));
4535 else if (strncasecmp (q
, "za", 2) == 0
4538 /* { ZA } is assembled as all-ones immediate. */
4545 set_syntax_error (_("wrong ZA tile element format"));
4549 while (skip_past_char (&q
, ','));
4555 /* Wraps in curly braces <mask> operand ZERO instruction:
4559 Function returns value of <mask> bit-field.
4562 parse_sme_list_of_64bit_tiles (char **str
)
4566 if (!skip_past_char (str
, '{'))
4568 set_syntax_error (_("expected '{'"));
4572 /* Empty <mask> list is an all-zeros immediate. */
4573 if (!skip_past_char (str
, '}'))
4575 regno
= parse_sme_zero_mask (str
);
4576 if (regno
== PARSE_FAIL
)
4579 if (!skip_past_char (str
, '}'))
4581 set_syntax_error (_("expected '}'"));
4591 /* Parse ZA array operand used in e.g. STR and LDR instruction.
4597 Function returns <Wv> or PARSE_FAIL.
4600 parse_sme_za_array (char **str
, int *imm
)
4607 while (ISALPHA (*q
))
4610 if ((q
- p
!= 2) || strncasecmp ("za", p
, q
- p
) != 0)
4612 set_syntax_error (_("expected ZA array"));
4616 if (! parse_sme_za_hv_tiles_operand_index (&q
, ®no
, &imm_value
))
4619 if (imm_value
< 0 || imm_value
> 15)
4621 set_syntax_error (_("offset out of range"));
4630 /* Parse streaming mode operand for SMSTART and SMSTOP.
4634 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4637 parse_sme_sm_za (char **str
)
4642 while (ISALPHA (*q
))
4646 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4648 set_syntax_error (_("expected SM or ZA operand"));
4653 return TOLOWER (p
[0]);
4656 /* Parse the name of the source scalable predicate register, the index base
4657 register W12-W15 and the element index. Function performs element index
4658 limit checks as well as qualifier type checks.
4660 <Pn>.<T>[<Wv>, <imm>]
4661 <Pn>.<T>[<Wv>, #<imm>]
4663 On success function sets <Wv> to INDEX_BASE_REG, <T> to QUALIFIER and
4665 Function returns <Pn>, or PARSE_FAIL.
4668 parse_sme_pred_reg_with_index(char **str
,
4669 int *index_base_reg
,
4671 aarch64_opnd_qualifier_t
*qualifier
)
4676 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_PN
, qualifier
);
4680 regno
= reg
->number
;
4684 case AARCH64_OPND_QLF_S_B
:
4687 case AARCH64_OPND_QLF_S_H
:
4690 case AARCH64_OPND_QLF_S_S
:
4693 case AARCH64_OPND_QLF_S_D
:
4697 set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d"));
4701 if (! parse_sme_za_hv_tiles_operand_index (str
, index_base_reg
, &imm_value
))
4704 if (imm_value
< 0 || imm_value
> imm_limit
)
4706 set_syntax_error (_("element index out of range for given variant"));
4715 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4716 Returns the encoding for the option, or PARSE_FAIL.
4718 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4719 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4721 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4722 field, otherwise as a system register.
4726 parse_sys_reg (char **str
, htab_t sys_regs
,
4727 int imple_defined_p
, int pstatefield_p
,
4731 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4732 const aarch64_sys_reg
*o
;
4736 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4737 if (p
< buf
+ (sizeof (buf
) - 1))
4738 *p
++ = TOLOWER (*q
);
4741 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4742 valid system register. This is enforced by construction of the hash
4744 if (p
- buf
!= q
- *str
)
4747 o
= str_hash_find (sys_regs
, buf
);
4750 if (!imple_defined_p
)
4754 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4755 unsigned int op0
, op1
, cn
, cm
, op2
;
4757 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4760 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4762 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4769 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4770 as_bad (_("selected processor does not support PSTATE field "
4773 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4774 o
->value
, o
->flags
, o
->features
))
4775 as_bad (_("selected processor does not support system register "
4777 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4778 as_warn (_("system register name '%s' is deprecated and may be "
4779 "removed in a future release"), buf
);
4789 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4790 for the option, or NULL. */
4792 static const aarch64_sys_ins_reg
*
4793 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4796 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4797 const aarch64_sys_ins_reg
*o
;
4800 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4801 if (p
< buf
+ (sizeof (buf
) - 1))
4802 *p
++ = TOLOWER (*q
);
4805 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4806 valid system register. This is enforced by construction of the hash
4808 if (p
- buf
!= q
- *str
)
4811 o
= str_hash_find (sys_ins_regs
, buf
);
4815 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4816 o
->name
, o
->value
, o
->flags
, 0))
4817 as_bad (_("selected processor does not support system register "
4819 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4820 as_warn (_("system register name '%s' is deprecated and may be "
4821 "removed in a future release"), buf
);
4827 #define po_char_or_fail(chr) do { \
4828 if (! skip_past_char (&str, chr)) \
4832 #define po_reg_or_fail(regtype) do { \
4833 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4834 if (val == PARSE_FAIL) \
4836 set_default_error (); \
4841 #define po_int_reg_or_fail(reg_type) do { \
4842 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4843 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4845 set_default_error (); \
4848 info->reg.regno = reg->number; \
4849 info->qualifier = qualifier; \
4852 #define po_imm_nc_or_fail() do { \
4853 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4857 #define po_imm_or_fail(min, max) do { \
4858 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4860 if (val < min || val > max) \
4862 set_fatal_syntax_error (_("immediate value out of range "\
4863 #min " to "#max)); \
4868 #define po_enum_or_fail(array) do { \
4869 if (!parse_enum_string (&str, &val, array, \
4870 ARRAY_SIZE (array), imm_reg_type)) \
4874 #define po_misc_or_fail(expr) do { \
4879 /* encode the 12-bit imm field of Add/sub immediate */
4880 static inline uint32_t
4881 encode_addsub_imm (uint32_t imm
)
4886 /* encode the shift amount field of Add/sub immediate */
4887 static inline uint32_t
4888 encode_addsub_imm_shift_amount (uint32_t cnt
)
4894 /* encode the imm field of Adr instruction */
4895 static inline uint32_t
4896 encode_adr_imm (uint32_t imm
)
4898 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4899 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4902 /* encode the immediate field of Move wide immediate */
4903 static inline uint32_t
4904 encode_movw_imm (uint32_t imm
)
4909 /* encode the 26-bit offset of unconditional branch */
4910 static inline uint32_t
4911 encode_branch_ofs_26 (uint32_t ofs
)
4913 return ofs
& ((1 << 26) - 1);
4916 /* encode the 19-bit offset of conditional branch and compare & branch */
4917 static inline uint32_t
4918 encode_cond_branch_ofs_19 (uint32_t ofs
)
4920 return (ofs
& ((1 << 19) - 1)) << 5;
4923 /* encode the 19-bit offset of ld literal */
4924 static inline uint32_t
4925 encode_ld_lit_ofs_19 (uint32_t ofs
)
4927 return (ofs
& ((1 << 19) - 1)) << 5;
4930 /* Encode the 14-bit offset of test & branch. */
4931 static inline uint32_t
4932 encode_tst_branch_ofs_14 (uint32_t ofs
)
4934 return (ofs
& ((1 << 14) - 1)) << 5;
4937 /* Encode the 16-bit imm field of svc/hvc/smc. */
4938 static inline uint32_t
4939 encode_svc_imm (uint32_t imm
)
4944 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4945 static inline uint32_t
4946 reencode_addsub_switch_add_sub (uint32_t opcode
)
4948 return opcode
^ (1 << 30);
4951 static inline uint32_t
4952 reencode_movzn_to_movz (uint32_t opcode
)
4954 return opcode
| (1 << 30);
4957 static inline uint32_t
4958 reencode_movzn_to_movn (uint32_t opcode
)
4960 return opcode
& ~(1 << 30);
4963 /* Overall per-instruction processing. */
4965 /* We need to be able to fix up arbitrary expressions in some statements.
4966 This is so that we can handle symbols that are an arbitrary distance from
4967 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4968 which returns part of an address in a form which will be valid for
4969 a data instruction. We do this by pushing the expression into a symbol
4970 in the expr_section, and creating a fix for that. */
4973 fix_new_aarch64 (fragS
* frag
,
4988 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4992 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4999 /* Diagnostics on operands errors. */
5001 /* By default, output verbose error message.
5002 Disable the verbose error message by -mno-verbose-error. */
5003 static int verbose_error_p
= 1;
5005 #ifdef DEBUG_AARCH64
5006 /* N.B. this is only for the purpose of debugging. */
5007 const char* operand_mismatch_kind_names
[] =
5010 "AARCH64_OPDE_RECOVERABLE",
5011 "AARCH64_OPDE_A_SHOULD_FOLLOW_B",
5012 "AARCH64_OPDE_EXPECTED_A_AFTER_B",
5013 "AARCH64_OPDE_SYNTAX_ERROR",
5014 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5015 "AARCH64_OPDE_INVALID_VARIANT",
5016 "AARCH64_OPDE_OUT_OF_RANGE",
5017 "AARCH64_OPDE_UNALIGNED",
5018 "AARCH64_OPDE_REG_LIST",
5019 "AARCH64_OPDE_OTHER_ERROR",
5021 #endif /* DEBUG_AARCH64 */
5023 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5025 When multiple errors of different kinds are found in the same assembly
5026 line, only the error of the highest severity will be picked up for
5027 issuing the diagnostics. */
5030 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5031 enum aarch64_operand_error_kind rhs
)
5033 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5034 gas_assert (AARCH64_OPDE_A_SHOULD_FOLLOW_B
> AARCH64_OPDE_RECOVERABLE
);
5035 gas_assert (AARCH64_OPDE_EXPECTED_A_AFTER_B
> AARCH64_OPDE_RECOVERABLE
);
5036 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_A_SHOULD_FOLLOW_B
);
5037 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_EXPECTED_A_AFTER_B
);
5038 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5039 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5040 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
5041 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5042 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
5043 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
5047 /* Helper routine to get the mnemonic name from the assembly instruction
5048 line; should only be called for the diagnosis purpose, as there is
5049 string copy operation involved, which may affect the runtime
5050 performance if used in elsewhere. */
5053 get_mnemonic_name (const char *str
)
5055 static char mnemonic
[32];
5058 /* Get the first 15 bytes and assume that the full name is included. */
5059 strncpy (mnemonic
, str
, 31);
5060 mnemonic
[31] = '\0';
5062 /* Scan up to the end of the mnemonic, which must end in white space,
5063 '.', or end of string. */
5064 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5069 /* Append '...' to the truncated long name. */
5070 if (ptr
- mnemonic
== 31)
5071 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5077 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5079 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5080 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5083 /* Data structures storing one user error in the assembly code related to
5086 struct operand_error_record
5088 const aarch64_opcode
*opcode
;
5089 aarch64_operand_error detail
;
5090 struct operand_error_record
*next
;
5093 typedef struct operand_error_record operand_error_record
;
5095 struct operand_errors
5097 operand_error_record
*head
;
5098 operand_error_record
*tail
;
5101 typedef struct operand_errors operand_errors
;
5103 /* Top-level data structure reporting user errors for the current line of
5105 The way md_assemble works is that all opcodes sharing the same mnemonic
5106 name are iterated to find a match to the assembly line. In this data
5107 structure, each of the such opcodes will have one operand_error_record
5108 allocated and inserted. In other words, excessive errors related with
5109 a single opcode are disregarded. */
5110 operand_errors operand_error_report
;
5112 /* Free record nodes. */
5113 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5115 /* Initialize the data structure that stores the operand mismatch
5116 information on assembling one line of the assembly code. */
5118 init_operand_error_report (void)
5120 if (operand_error_report
.head
!= NULL
)
5122 gas_assert (operand_error_report
.tail
!= NULL
);
5123 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5124 free_opnd_error_record_nodes
= operand_error_report
.head
;
5125 operand_error_report
.head
= NULL
;
5126 operand_error_report
.tail
= NULL
;
5129 gas_assert (operand_error_report
.tail
== NULL
);
5132 /* Return TRUE if some operand error has been recorded during the
5133 parsing of the current assembly line using the opcode *OPCODE;
5134 otherwise return FALSE. */
5136 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5138 operand_error_record
*record
= operand_error_report
.head
;
5139 return record
&& record
->opcode
== opcode
;
5142 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5143 OPCODE field is initialized with OPCODE.
5144 N.B. only one record for each opcode, i.e. the maximum of one error is
5145 recorded for each instruction template. */
5148 add_operand_error_record (const operand_error_record
* new_record
)
5150 const aarch64_opcode
*opcode
= new_record
->opcode
;
5151 operand_error_record
* record
= operand_error_report
.head
;
5153 /* The record may have been created for this opcode. If not, we need
5155 if (! opcode_has_operand_error_p (opcode
))
5157 /* Get one empty record. */
5158 if (free_opnd_error_record_nodes
== NULL
)
5160 record
= XNEW (operand_error_record
);
5164 record
= free_opnd_error_record_nodes
;
5165 free_opnd_error_record_nodes
= record
->next
;
5167 record
->opcode
= opcode
;
5168 /* Insert at the head. */
5169 record
->next
= operand_error_report
.head
;
5170 operand_error_report
.head
= record
;
5171 if (operand_error_report
.tail
== NULL
)
5172 operand_error_report
.tail
= record
;
5174 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5175 && record
->detail
.index
<= new_record
->detail
.index
5176 && operand_error_higher_severity_p (record
->detail
.kind
,
5177 new_record
->detail
.kind
))
5179 /* In the case of multiple errors found on operands related with a
5180 single opcode, only record the error of the leftmost operand and
5181 only if the error is of higher severity. */
5182 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5183 " the existing error %s on operand %d",
5184 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5185 new_record
->detail
.index
,
5186 operand_mismatch_kind_names
[record
->detail
.kind
],
5187 record
->detail
.index
);
5191 record
->detail
= new_record
->detail
;
5195 record_operand_error_info (const aarch64_opcode
*opcode
,
5196 aarch64_operand_error
*error_info
)
5198 operand_error_record record
;
5199 record
.opcode
= opcode
;
5200 record
.detail
= *error_info
;
5201 add_operand_error_record (&record
);
5204 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5205 error message *ERROR, for operand IDX (count from 0). */
5208 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5209 enum aarch64_operand_error_kind kind
,
5212 aarch64_operand_error info
;
5213 memset(&info
, 0, sizeof (info
));
5217 info
.non_fatal
= false;
5218 record_operand_error_info (opcode
, &info
);
5222 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5223 enum aarch64_operand_error_kind kind
,
5224 const char* error
, const int *extra_data
)
5226 aarch64_operand_error info
;
5230 info
.data
[0].i
= extra_data
[0];
5231 info
.data
[1].i
= extra_data
[1];
5232 info
.data
[2].i
= extra_data
[2];
5233 info
.non_fatal
= false;
5234 record_operand_error_info (opcode
, &info
);
5238 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5239 const char* error
, int lower_bound
,
5242 int data
[3] = {lower_bound
, upper_bound
, 0};
5243 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5247 /* Remove the operand error record for *OPCODE. */
5248 static void ATTRIBUTE_UNUSED
5249 remove_operand_error_record (const aarch64_opcode
*opcode
)
5251 if (opcode_has_operand_error_p (opcode
))
5253 operand_error_record
* record
= operand_error_report
.head
;
5254 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5255 operand_error_report
.head
= record
->next
;
5256 record
->next
= free_opnd_error_record_nodes
;
5257 free_opnd_error_record_nodes
= record
;
5258 if (operand_error_report
.head
== NULL
)
5260 gas_assert (operand_error_report
.tail
== record
);
5261 operand_error_report
.tail
= NULL
;
5266 /* Given the instruction in *INSTR, return the index of the best matched
5267 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5269 Return -1 if there is no qualifier sequence; return the first match
5270 if there is multiple matches found. */
5273 find_best_match (const aarch64_inst
*instr
,
5274 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5276 int i
, num_opnds
, max_num_matched
, idx
;
5278 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5281 DEBUG_TRACE ("no operand");
5285 max_num_matched
= 0;
5288 /* For each pattern. */
5289 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5292 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5294 /* Most opcodes has much fewer patterns in the list. */
5295 if (empty_qualifier_sequence_p (qualifiers
))
5297 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5301 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5302 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5305 if (num_matched
> max_num_matched
)
5307 max_num_matched
= num_matched
;
5312 DEBUG_TRACE ("return with %d", idx
);
5316 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5317 corresponding operands in *INSTR. */
5320 assign_qualifier_sequence (aarch64_inst
*instr
,
5321 const aarch64_opnd_qualifier_t
*qualifiers
)
5324 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5325 gas_assert (num_opnds
);
5326 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5327 instr
->operands
[i
].qualifier
= *qualifiers
;
5330 /* Callback used by aarch64_print_operand to apply STYLE to the
5331 disassembler output created from FMT and ARGS. The STYLER object holds
5332 any required state. Must return a pointer to a string (created from FMT
5333 and ARGS) that will continue to be valid until the complete disassembled
5334 instruction has been printed.
5336 We don't currently add any styling to the output of the disassembler as
5337 used within assembler error messages, and so STYLE is ignored here. A
5338 new string is allocated on the obstack help within STYLER and returned
5341 static const char *aarch64_apply_style
5342 (struct aarch64_styler
*styler
,
5343 enum disassembler_style style ATTRIBUTE_UNUSED
,
5344 const char *fmt
, va_list args
)
5348 struct obstack
*stack
= (struct obstack
*) styler
->state
;
5351 /* Calculate the required space. */
5353 res
= vsnprintf (NULL
, 0, fmt
, ap
);
5355 gas_assert (res
>= 0);
5357 /* Allocate space on the obstack and format the result. */
5358 ptr
= (char *) obstack_alloc (stack
, res
+ 1);
5359 res
= vsnprintf (ptr
, (res
+ 1), fmt
, args
);
5360 gas_assert (res
>= 0);
5365 /* Print operands for the diagnosis purpose. */
5368 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5369 const aarch64_opnd_info
*opnds
)
5372 struct aarch64_styler styler
;
5373 struct obstack content
;
5374 obstack_init (&content
);
5376 styler
.apply_style
= aarch64_apply_style
;
5377 styler
.state
= (void *) &content
;
5379 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5384 /* We regard the opcode operand info more, however we also look into
5385 the inst->operands to support the disassembling of the optional
5387 The two operand code should be the same in all cases, apart from
5388 when the operand can be optional. */
5389 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5390 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5393 /* Generate the operand string in STR. */
5394 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5395 NULL
, cmt
, sizeof (cmt
), cpu_variant
, &styler
);
5399 strcat (buf
, i
== 0 ? " " : ", ");
5401 /* Append the operand string. */
5404 /* Append a comment. This works because only the last operand ever
5405 adds a comment. If that ever changes then we'll need to be
5409 strcat (buf
, "\t// ");
5414 obstack_free (&content
, NULL
);
5417 /* Send to stderr a string as information. */
5420 output_info (const char *format
, ...)
5426 file
= as_where (&line
);
5430 fprintf (stderr
, "%s:%u: ", file
, line
);
5432 fprintf (stderr
, "%s: ", file
);
5434 fprintf (stderr
, _("Info: "));
5435 va_start (args
, format
);
5436 vfprintf (stderr
, format
, args
);
5438 (void) putc ('\n', stderr
);
5441 /* Output one operand error record. */
5444 output_operand_error_record (const operand_error_record
*record
, char *str
)
5446 const aarch64_operand_error
*detail
= &record
->detail
;
5447 int idx
= detail
->index
;
5448 const aarch64_opcode
*opcode
= record
->opcode
;
5449 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5450 : AARCH64_OPND_NIL
);
5452 typedef void (*handler_t
)(const char *format
, ...);
5453 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5455 switch (detail
->kind
)
5457 case AARCH64_OPDE_NIL
:
5461 case AARCH64_OPDE_A_SHOULD_FOLLOW_B
:
5462 handler (_("this `%s' should have an immediately preceding `%s'"
5464 detail
->data
[0].s
, detail
->data
[1].s
, str
);
5467 case AARCH64_OPDE_EXPECTED_A_AFTER_B
:
5468 handler (_("the preceding `%s' should be followed by `%s` rather"
5469 " than `%s` -- `%s'"),
5470 detail
->data
[1].s
, detail
->data
[0].s
, opcode
->name
, str
);
5473 case AARCH64_OPDE_SYNTAX_ERROR
:
5474 case AARCH64_OPDE_RECOVERABLE
:
5475 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5476 case AARCH64_OPDE_OTHER_ERROR
:
5477 /* Use the prepared error message if there is, otherwise use the
5478 operand description string to describe the error. */
5479 if (detail
->error
!= NULL
)
5482 handler (_("%s -- `%s'"), detail
->error
, str
);
5484 handler (_("%s at operand %d -- `%s'"),
5485 detail
->error
, idx
+ 1, str
);
5489 gas_assert (idx
>= 0);
5490 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5491 aarch64_get_operand_desc (opd_code
), str
);
5495 case AARCH64_OPDE_INVALID_VARIANT
:
5496 handler (_("operand mismatch -- `%s'"), str
);
5497 if (verbose_error_p
)
5499 /* We will try to correct the erroneous instruction and also provide
5500 more information e.g. all other valid variants.
5502 The string representation of the corrected instruction and other
5503 valid variants are generated by
5505 1) obtaining the intermediate representation of the erroneous
5507 2) manipulating the IR, e.g. replacing the operand qualifier;
5508 3) printing out the instruction by calling the printer functions
5509 shared with the disassembler.
5511 The limitation of this method is that the exact input assembly
5512 line cannot be accurately reproduced in some cases, for example an
5513 optional operand present in the actual assembly line will be
5514 omitted in the output; likewise for the optional syntax rules,
5515 e.g. the # before the immediate. Another limitation is that the
5516 assembly symbols and relocation operations in the assembly line
5517 currently cannot be printed out in the error report. Last but not
5518 least, when there is other error(s) co-exist with this error, the
5519 'corrected' instruction may be still incorrect, e.g. given
5520 'ldnp h0,h1,[x0,#6]!'
5521 this diagnosis will provide the version:
5522 'ldnp s0,s1,[x0,#6]!'
5523 which is still not right. */
5524 size_t len
= strlen (get_mnemonic_name (str
));
5528 aarch64_inst
*inst_base
= &inst
.base
;
5529 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5532 reset_aarch64_instruction (&inst
);
5533 inst_base
->opcode
= opcode
;
5535 /* Reset the error report so that there is no side effect on the
5536 following operand parsing. */
5537 init_operand_error_report ();
5540 result
= parse_operands (str
+ len
, opcode
)
5541 && programmer_friendly_fixup (&inst
);
5542 gas_assert (result
);
5543 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5544 NULL
, NULL
, insn_sequence
);
5545 gas_assert (!result
);
5547 /* Find the most matched qualifier sequence. */
5548 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5549 gas_assert (qlf_idx
> -1);
5551 /* Assign the qualifiers. */
5552 assign_qualifier_sequence (inst_base
,
5553 opcode
->qualifiers_list
[qlf_idx
]);
5555 /* Print the hint. */
5556 output_info (_(" did you mean this?"));
5557 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5558 print_operands (buf
, opcode
, inst_base
->operands
);
5559 output_info (_(" %s"), buf
);
5561 /* Print out other variant(s) if there is any. */
5563 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5564 output_info (_(" other valid variant(s):"));
5566 /* For each pattern. */
5567 qualifiers_list
= opcode
->qualifiers_list
;
5568 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5570 /* Most opcodes has much fewer patterns in the list.
5571 First NIL qualifier indicates the end in the list. */
5572 if (empty_qualifier_sequence_p (*qualifiers_list
))
5577 /* Mnemonics name. */
5578 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5580 /* Assign the qualifiers. */
5581 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5583 /* Print instruction. */
5584 print_operands (buf
, opcode
, inst_base
->operands
);
5586 output_info (_(" %s"), buf
);
5592 case AARCH64_OPDE_UNTIED_IMMS
:
5593 handler (_("operand %d must have the same immediate value "
5594 "as operand 1 -- `%s'"),
5595 detail
->index
+ 1, str
);
5598 case AARCH64_OPDE_UNTIED_OPERAND
:
5599 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5600 detail
->index
+ 1, str
);
5603 case AARCH64_OPDE_OUT_OF_RANGE
:
5604 if (detail
->data
[0].i
!= detail
->data
[1].i
)
5605 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5606 detail
->error
? detail
->error
: _("immediate value"),
5607 detail
->data
[0].i
, detail
->data
[1].i
, idx
+ 1, str
);
5609 handler (_("%s must be %d at operand %d -- `%s'"),
5610 detail
->error
? detail
->error
: _("immediate value"),
5611 detail
->data
[0].i
, idx
+ 1, str
);
5614 case AARCH64_OPDE_REG_LIST
:
5615 if (detail
->data
[0].i
== 1)
5616 handler (_("invalid number of registers in the list; "
5617 "only 1 register is expected at operand %d -- `%s'"),
5620 handler (_("invalid number of registers in the list; "
5621 "%d registers are expected at operand %d -- `%s'"),
5622 detail
->data
[0].i
, idx
+ 1, str
);
5625 case AARCH64_OPDE_UNALIGNED
:
5626 handler (_("immediate value must be a multiple of "
5627 "%d at operand %d -- `%s'"),
5628 detail
->data
[0].i
, idx
+ 1, str
);
5637 /* Process and output the error message about the operand mismatching.
5639 When this function is called, the operand error information had
5640 been collected for an assembly line and there will be multiple
5641 errors in the case of multiple instruction templates; output the
5642 error message that most closely describes the problem.
5644 The errors to be printed can be filtered on printing all errors
5645 or only non-fatal errors. This distinction has to be made because
5646 the error buffer may already be filled with fatal errors we don't want to
5647 print due to the different instruction templates. */
5650 output_operand_error_report (char *str
, bool non_fatal_only
)
5652 int largest_error_pos
;
5653 const char *msg
= NULL
;
5654 enum aarch64_operand_error_kind kind
;
5655 operand_error_record
*curr
;
5656 operand_error_record
*head
= operand_error_report
.head
;
5657 operand_error_record
*record
= NULL
;
5659 /* No error to report. */
5663 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5665 /* Only one error. */
5666 if (head
== operand_error_report
.tail
)
5668 /* If the only error is a non-fatal one and we don't want to print it,
5670 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5672 DEBUG_TRACE ("single opcode entry with error kind: %s",
5673 operand_mismatch_kind_names
[head
->detail
.kind
]);
5674 output_operand_error_record (head
, str
);
5679 /* Find the error kind of the highest severity. */
5680 DEBUG_TRACE ("multiple opcode entries with error kind");
5681 kind
= AARCH64_OPDE_NIL
;
5682 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5684 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5685 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5686 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5687 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5688 kind
= curr
->detail
.kind
;
5691 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5693 /* Pick up one of errors of KIND to report. */
5694 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5695 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5697 /* If we don't want to print non-fatal errors then don't consider them
5699 if (curr
->detail
.kind
!= kind
5700 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5702 /* If there are multiple errors, pick up the one with the highest
5703 mismatching operand index. In the case of multiple errors with
5704 the equally highest operand index, pick up the first one or the
5705 first one with non-NULL error message. */
5706 if (curr
->detail
.index
> largest_error_pos
5707 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5708 && curr
->detail
.error
!= NULL
))
5710 largest_error_pos
= curr
->detail
.index
;
5712 msg
= record
->detail
.error
;
5716 /* The way errors are collected in the back-end is a bit non-intuitive. But
5717 essentially, because each operand template is tried recursively you may
5718 always have errors collected from the previous tried OPND. These are
5719 usually skipped if there is one successful match. However now with the
5720 non-fatal errors we have to ignore those previously collected hard errors
5721 when we're only interested in printing the non-fatal ones. This condition
5722 prevents us from printing errors that are not appropriate, since we did
5723 match a condition, but it also has warnings that it wants to print. */
5724 if (non_fatal_only
&& !record
)
5727 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5728 DEBUG_TRACE ("Pick up error kind %s to report",
5729 operand_mismatch_kind_names
[record
->detail
.kind
]);
5732 output_operand_error_record (record
, str
);
5735 /* Write an AARCH64 instruction to buf - always little-endian. */
5737 put_aarch64_insn (char *buf
, uint32_t insn
)
5739 unsigned char *where
= (unsigned char *) buf
;
5741 where
[1] = insn
>> 8;
5742 where
[2] = insn
>> 16;
5743 where
[3] = insn
>> 24;
5747 get_aarch64_insn (char *buf
)
5749 unsigned char *where
= (unsigned char *) buf
;
5751 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5752 | ((uint32_t) where
[3] << 24)));
5757 output_inst (struct aarch64_inst
*new_inst
)
5761 to
= frag_more (INSN_SIZE
);
5763 frag_now
->tc_frag_data
.recorded
= 1;
5765 put_aarch64_insn (to
, inst
.base
.value
);
5767 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5769 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5770 INSN_SIZE
, &inst
.reloc
.exp
,
5773 DEBUG_TRACE ("Prepared relocation fix up");
5774 /* Don't check the addend value against the instruction size,
5775 that's the job of our code in md_apply_fix(). */
5776 fixp
->fx_no_overflow
= 1;
5777 if (new_inst
!= NULL
)
5778 fixp
->tc_fix_data
.inst
= new_inst
;
5779 if (aarch64_gas_internal_fixup_p ())
5781 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5782 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5783 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5787 dwarf2_emit_insn (INSN_SIZE
);
5790 /* Link together opcodes of the same name. */
5794 const aarch64_opcode
*opcode
;
5795 struct templates
*next
;
5798 typedef struct templates templates
;
5801 lookup_mnemonic (const char *start
, int len
)
5803 templates
*templ
= NULL
;
5805 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5809 /* Subroutine of md_assemble, responsible for looking up the primary
5810 opcode from the mnemonic the user wrote. BASE points to the beginning
5811 of the mnemonic, DOT points to the first '.' within the mnemonic
5812 (if any) and END points to the end of the mnemonic. */
5815 opcode_lookup (char *base
, char *dot
, char *end
)
5817 const aarch64_cond
*cond
;
5824 inst
.cond
= COND_ALWAYS
;
5826 /* Handle a possible condition. */
5829 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5832 inst
.cond
= cond
->value
;
5838 if (inst
.cond
== COND_ALWAYS
)
5840 /* Look for unaffixed mnemonic. */
5841 return lookup_mnemonic (base
, len
);
5845 /* append ".c" to mnemonic if conditional */
5846 memcpy (condname
, base
, len
);
5847 memcpy (condname
+ len
, ".c", 2);
5850 return lookup_mnemonic (base
, len
);
5856 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5857 to a corresponding operand qualifier. */
5859 static inline aarch64_opnd_qualifier_t
5860 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5862 /* Element size in bytes indexed by vector_el_type. */
5863 const unsigned char ele_size
[5]
5865 const unsigned int ele_base
[5] =
5867 AARCH64_OPND_QLF_V_4B
,
5868 AARCH64_OPND_QLF_V_2H
,
5869 AARCH64_OPND_QLF_V_2S
,
5870 AARCH64_OPND_QLF_V_1D
,
5871 AARCH64_OPND_QLF_V_1Q
5874 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5875 goto vectype_conversion_fail
;
5877 if (vectype
->type
== NT_zero
)
5878 return AARCH64_OPND_QLF_P_Z
;
5879 if (vectype
->type
== NT_merge
)
5880 return AARCH64_OPND_QLF_P_M
;
5882 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5884 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5886 /* Special case S_4B. */
5887 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5888 return AARCH64_OPND_QLF_S_4B
;
5890 /* Special case S_2H. */
5891 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5892 return AARCH64_OPND_QLF_S_2H
;
5894 /* Vector element register. */
5895 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5899 /* Vector register. */
5900 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5903 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5904 goto vectype_conversion_fail
;
5906 /* The conversion is by calculating the offset from the base operand
5907 qualifier for the vector type. The operand qualifiers are regular
5908 enough that the offset can established by shifting the vector width by
5909 a vector-type dependent amount. */
5911 if (vectype
->type
== NT_b
)
5913 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5915 else if (vectype
->type
>= NT_d
)
5920 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5921 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5922 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5926 vectype_conversion_fail
:
5927 first_error (_("bad vector arrangement type"));
5928 return AARCH64_OPND_QLF_NIL
;
5931 /* Process an optional operand that is found omitted from the assembly line.
5932 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5933 instruction's opcode entry while IDX is the index of this omitted operand.
5937 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5938 int idx
, aarch64_opnd_info
*operand
)
5940 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5941 gas_assert (optional_operand_p (opcode
, idx
));
5942 gas_assert (!operand
->present
);
5946 case AARCH64_OPND_Rd
:
5947 case AARCH64_OPND_Rn
:
5948 case AARCH64_OPND_Rm
:
5949 case AARCH64_OPND_Rt
:
5950 case AARCH64_OPND_Rt2
:
5951 case AARCH64_OPND_Rt_LS64
:
5952 case AARCH64_OPND_Rt_SP
:
5953 case AARCH64_OPND_Rs
:
5954 case AARCH64_OPND_Ra
:
5955 case AARCH64_OPND_Rt_SYS
:
5956 case AARCH64_OPND_Rd_SP
:
5957 case AARCH64_OPND_Rn_SP
:
5958 case AARCH64_OPND_Rm_SP
:
5959 case AARCH64_OPND_Fd
:
5960 case AARCH64_OPND_Fn
:
5961 case AARCH64_OPND_Fm
:
5962 case AARCH64_OPND_Fa
:
5963 case AARCH64_OPND_Ft
:
5964 case AARCH64_OPND_Ft2
:
5965 case AARCH64_OPND_Sd
:
5966 case AARCH64_OPND_Sn
:
5967 case AARCH64_OPND_Sm
:
5968 case AARCH64_OPND_Va
:
5969 case AARCH64_OPND_Vd
:
5970 case AARCH64_OPND_Vn
:
5971 case AARCH64_OPND_Vm
:
5972 case AARCH64_OPND_VdD1
:
5973 case AARCH64_OPND_VnD1
:
5974 operand
->reg
.regno
= default_value
;
5977 case AARCH64_OPND_Ed
:
5978 case AARCH64_OPND_En
:
5979 case AARCH64_OPND_Em
:
5980 case AARCH64_OPND_Em16
:
5981 case AARCH64_OPND_SM3_IMM2
:
5982 operand
->reglane
.regno
= default_value
;
5985 case AARCH64_OPND_IDX
:
5986 case AARCH64_OPND_BIT_NUM
:
5987 case AARCH64_OPND_IMMR
:
5988 case AARCH64_OPND_IMMS
:
5989 case AARCH64_OPND_SHLL_IMM
:
5990 case AARCH64_OPND_IMM_VLSL
:
5991 case AARCH64_OPND_IMM_VLSR
:
5992 case AARCH64_OPND_CCMP_IMM
:
5993 case AARCH64_OPND_FBITS
:
5994 case AARCH64_OPND_UIMM4
:
5995 case AARCH64_OPND_UIMM3_OP1
:
5996 case AARCH64_OPND_UIMM3_OP2
:
5997 case AARCH64_OPND_IMM
:
5998 case AARCH64_OPND_IMM_2
:
5999 case AARCH64_OPND_WIDTH
:
6000 case AARCH64_OPND_UIMM7
:
6001 case AARCH64_OPND_NZCV
:
6002 case AARCH64_OPND_SVE_PATTERN
:
6003 case AARCH64_OPND_SVE_PRFOP
:
6004 operand
->imm
.value
= default_value
;
6007 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6008 operand
->imm
.value
= default_value
;
6009 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
6010 operand
->shifter
.amount
= 1;
6013 case AARCH64_OPND_EXCEPTION
:
6014 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6017 case AARCH64_OPND_BARRIER_ISB
:
6018 operand
->barrier
= aarch64_barrier_options
+ default_value
;
6021 case AARCH64_OPND_BTI_TARGET
:
6022 operand
->hint_option
= aarch64_hint_options
+ default_value
;
6030 /* Process the relocation type for move wide instructions.
6031 Return TRUE on success; otherwise return FALSE. */
6034 process_movw_reloc_info (void)
6039 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
6041 if (inst
.base
.opcode
->op
== OP_MOVK
)
6042 switch (inst
.reloc
.type
)
6044 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6045 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6046 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6047 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6048 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6049 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6050 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6051 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6052 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6053 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6054 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6056 (_("the specified relocation type is not allowed for MOVK"));
6062 switch (inst
.reloc
.type
)
6064 case BFD_RELOC_AARCH64_MOVW_G0
:
6065 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6066 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6067 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6068 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6069 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6070 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6071 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6072 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6073 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6074 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6075 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6076 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6079 case BFD_RELOC_AARCH64_MOVW_G1
:
6080 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6081 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6082 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6083 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6084 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6085 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6086 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6087 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6088 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6089 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6090 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6091 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6094 case BFD_RELOC_AARCH64_MOVW_G2
:
6095 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6096 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6097 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6098 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6099 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6100 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6103 set_fatal_syntax_error
6104 (_("the specified relocation type is not allowed for 32-bit "
6110 case BFD_RELOC_AARCH64_MOVW_G3
:
6111 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6114 set_fatal_syntax_error
6115 (_("the specified relocation type is not allowed for 32-bit "
6122 /* More cases should be added when more MOVW-related relocation types
6123 are supported in GAS. */
6124 gas_assert (aarch64_gas_internal_fixup_p ());
6125 /* The shift amount should have already been set by the parser. */
6128 inst
.base
.operands
[1].shifter
.amount
= shift
;
6132 /* A primitive log calculator. */
6134 static inline unsigned int
6135 get_logsz (unsigned int size
)
6137 const unsigned char ls
[16] =
6138 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
6144 gas_assert (ls
[size
- 1] != (unsigned char)-1);
6145 return ls
[size
- 1];
6148 /* Determine and return the real reloc type code for an instruction
6149 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6151 static inline bfd_reloc_code_real_type
6152 ldst_lo12_determine_real_reloc_type (void)
6154 unsigned logsz
, max_logsz
;
6155 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6156 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6158 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6160 BFD_RELOC_AARCH64_LDST8_LO12
,
6161 BFD_RELOC_AARCH64_LDST16_LO12
,
6162 BFD_RELOC_AARCH64_LDST32_LO12
,
6163 BFD_RELOC_AARCH64_LDST64_LO12
,
6164 BFD_RELOC_AARCH64_LDST128_LO12
6167 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6168 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6169 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6170 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6171 BFD_RELOC_AARCH64_NONE
6174 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6175 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6176 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6177 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6178 BFD_RELOC_AARCH64_NONE
6181 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6182 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6183 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6184 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6185 BFD_RELOC_AARCH64_NONE
6188 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6189 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6190 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6191 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6192 BFD_RELOC_AARCH64_NONE
6196 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6197 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6199 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6201 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6203 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6204 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6206 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6208 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6210 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6212 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
6214 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6215 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6216 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6217 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6222 if (logsz
> max_logsz
)
6224 /* SEE PR 27904 for an example of this. */
6225 set_fatal_syntax_error
6226 (_("relocation qualifier does not match instruction size"));
6227 return BFD_RELOC_AARCH64_NONE
;
6230 /* In reloc.c, these pseudo relocation types should be defined in similar
6231 order as above reloc_ldst_lo12 array. Because the array index calculation
6232 below relies on this. */
6233 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6236 /* Check whether a register list REGINFO is valid. The registers must be
6237 numbered in increasing order (modulo 32), in increments of one or two.
6239 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
6242 Return FALSE if such a register list is invalid, otherwise return TRUE. */
6245 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
6247 uint32_t i
, nb_regs
, prev_regno
, incr
;
6249 nb_regs
= 1 + (reginfo
& 0x3);
6251 prev_regno
= reginfo
& 0x1f;
6252 incr
= accept_alternate
? 2 : 1;
6254 for (i
= 1; i
< nb_regs
; ++i
)
6256 uint32_t curr_regno
;
6258 curr_regno
= reginfo
& 0x1f;
6259 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
6261 prev_regno
= curr_regno
;
6267 /* Generic instruction operand parser. This does no encoding and no
6268 semantic validation; it merely squirrels values away in the inst
6269 structure. Returns TRUE or FALSE depending on whether the
6270 specified grammar matched. */
6273 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6276 char *backtrack_pos
= 0;
6277 const enum aarch64_opnd
*operands
= opcode
->operands
;
6278 aarch64_reg_type imm_reg_type
;
6281 skip_whitespace (str
);
6283 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
6284 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
6286 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
6288 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6291 const reg_entry
*reg
;
6292 int comma_skipped_p
= 0;
6293 aarch64_reg_type rtype
;
6294 struct vector_type_el vectype
;
6295 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6296 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6297 aarch64_reg_type reg_type
;
6299 DEBUG_TRACE ("parse operand %d", i
);
6301 /* Assign the operand code. */
6302 info
->type
= operands
[i
];
6304 if (optional_operand_p (opcode
, i
))
6306 /* Remember where we are in case we need to backtrack. */
6307 gas_assert (!backtrack_pos
);
6308 backtrack_pos
= str
;
6311 /* Expect comma between operands; the backtrack mechanism will take
6312 care of cases of omitted optional operand. */
6313 if (i
> 0 && ! skip_past_char (&str
, ','))
6315 set_syntax_error (_("comma expected between operands"));
6319 comma_skipped_p
= 1;
6321 switch (operands
[i
])
6323 case AARCH64_OPND_Rd
:
6324 case AARCH64_OPND_Rn
:
6325 case AARCH64_OPND_Rm
:
6326 case AARCH64_OPND_Rt
:
6327 case AARCH64_OPND_Rt2
:
6328 case AARCH64_OPND_Rs
:
6329 case AARCH64_OPND_Ra
:
6330 case AARCH64_OPND_Rt_LS64
:
6331 case AARCH64_OPND_Rt_SYS
:
6332 case AARCH64_OPND_PAIRREG
:
6333 case AARCH64_OPND_SVE_Rm
:
6334 po_int_reg_or_fail (REG_TYPE_R_Z
);
6336 /* In LS64 load/store instructions Rt register number must be even
6338 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6340 /* We've already checked if this is valid register.
6341 This will check if register number (Rt) is not undefined for LS64
6343 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6344 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6346 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6352 case AARCH64_OPND_Rd_SP
:
6353 case AARCH64_OPND_Rn_SP
:
6354 case AARCH64_OPND_Rt_SP
:
6355 case AARCH64_OPND_SVE_Rn_SP
:
6356 case AARCH64_OPND_Rm_SP
:
6357 po_int_reg_or_fail (REG_TYPE_R_SP
);
6360 case AARCH64_OPND_Rm_EXT
:
6361 case AARCH64_OPND_Rm_SFT
:
6362 po_misc_or_fail (parse_shifter_operand
6363 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6365 : SHIFTED_LOGIC_IMM
)));
6366 if (!info
->shifter
.operator_present
)
6368 /* Default to LSL if not present. Libopcodes prefers shifter
6369 kind to be explicit. */
6370 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6371 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6372 /* For Rm_EXT, libopcodes will carry out further check on whether
6373 or not stack pointer is used in the instruction (Recall that
6374 "the extend operator is not optional unless at least one of
6375 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6379 case AARCH64_OPND_Fd
:
6380 case AARCH64_OPND_Fn
:
6381 case AARCH64_OPND_Fm
:
6382 case AARCH64_OPND_Fa
:
6383 case AARCH64_OPND_Ft
:
6384 case AARCH64_OPND_Ft2
:
6385 case AARCH64_OPND_Sd
:
6386 case AARCH64_OPND_Sn
:
6387 case AARCH64_OPND_Sm
:
6388 case AARCH64_OPND_SVE_VZn
:
6389 case AARCH64_OPND_SVE_Vd
:
6390 case AARCH64_OPND_SVE_Vm
:
6391 case AARCH64_OPND_SVE_Vn
:
6392 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
6393 if (val
== PARSE_FAIL
)
6395 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
6398 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
6400 info
->reg
.regno
= val
;
6401 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
6404 case AARCH64_OPND_SVE_Pd
:
6405 case AARCH64_OPND_SVE_Pg3
:
6406 case AARCH64_OPND_SVE_Pg4_5
:
6407 case AARCH64_OPND_SVE_Pg4_10
:
6408 case AARCH64_OPND_SVE_Pg4_16
:
6409 case AARCH64_OPND_SVE_Pm
:
6410 case AARCH64_OPND_SVE_Pn
:
6411 case AARCH64_OPND_SVE_Pt
:
6412 case AARCH64_OPND_SME_Pm
:
6413 reg_type
= REG_TYPE_PN
;
6416 case AARCH64_OPND_SVE_Za_5
:
6417 case AARCH64_OPND_SVE_Za_16
:
6418 case AARCH64_OPND_SVE_Zd
:
6419 case AARCH64_OPND_SVE_Zm_5
:
6420 case AARCH64_OPND_SVE_Zm_16
:
6421 case AARCH64_OPND_SVE_Zn
:
6422 case AARCH64_OPND_SVE_Zt
:
6423 reg_type
= REG_TYPE_ZN
;
6426 case AARCH64_OPND_Va
:
6427 case AARCH64_OPND_Vd
:
6428 case AARCH64_OPND_Vn
:
6429 case AARCH64_OPND_Vm
:
6430 reg_type
= REG_TYPE_VN
;
6432 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6433 if (val
== PARSE_FAIL
)
6435 first_error (_(get_reg_expected_msg (reg_type
)));
6438 if (vectype
.defined
& NTA_HASINDEX
)
6441 info
->reg
.regno
= val
;
6442 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
6443 && vectype
.type
== NT_invtype
)
6444 /* Unqualified Pn and Zn registers are allowed in certain
6445 contexts. Rely on F_STRICT qualifier checking to catch
6447 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6450 info
->qualifier
= vectype_to_qualifier (&vectype
);
6451 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6456 case AARCH64_OPND_VdD1
:
6457 case AARCH64_OPND_VnD1
:
6458 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
6459 if (val
== PARSE_FAIL
)
6461 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
6464 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6466 set_fatal_syntax_error
6467 (_("the top half of a 128-bit FP/SIMD register is expected"));
6470 info
->reg
.regno
= val
;
6471 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6472 here; it is correct for the purpose of encoding/decoding since
6473 only the register number is explicitly encoded in the related
6474 instructions, although this appears a bit hacky. */
6475 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6478 case AARCH64_OPND_SVE_Zm3_INDEX
:
6479 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6480 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6481 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6482 case AARCH64_OPND_SVE_Zm4_INDEX
:
6483 case AARCH64_OPND_SVE_Zn_INDEX
:
6484 reg_type
= REG_TYPE_ZN
;
6485 goto vector_reg_index
;
6487 case AARCH64_OPND_Ed
:
6488 case AARCH64_OPND_En
:
6489 case AARCH64_OPND_Em
:
6490 case AARCH64_OPND_Em16
:
6491 case AARCH64_OPND_SM3_IMM2
:
6492 reg_type
= REG_TYPE_VN
;
6494 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6495 if (val
== PARSE_FAIL
)
6497 first_error (_(get_reg_expected_msg (reg_type
)));
6500 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6503 info
->reglane
.regno
= val
;
6504 info
->reglane
.index
= vectype
.index
;
6505 info
->qualifier
= vectype_to_qualifier (&vectype
);
6506 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6510 case AARCH64_OPND_SVE_ZnxN
:
6511 case AARCH64_OPND_SVE_ZtxN
:
6512 reg_type
= REG_TYPE_ZN
;
6513 goto vector_reg_list
;
6515 case AARCH64_OPND_LVn
:
6516 case AARCH64_OPND_LVt
:
6517 case AARCH64_OPND_LVt_AL
:
6518 case AARCH64_OPND_LEt
:
6519 reg_type
= REG_TYPE_VN
;
6521 if (reg_type
== REG_TYPE_ZN
6522 && get_opcode_dependent_value (opcode
) == 1
6525 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6526 if (val
== PARSE_FAIL
)
6528 first_error (_(get_reg_expected_msg (reg_type
)));
6531 info
->reglist
.first_regno
= val
;
6532 info
->reglist
.num_regs
= 1;
6536 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6537 if (val
== PARSE_FAIL
)
6540 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6542 set_fatal_syntax_error (_("invalid register list"));
6546 if (vectype
.width
!= 0 && *str
!= ',')
6548 set_fatal_syntax_error
6549 (_("expected element type rather than vector type"));
6553 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6554 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6556 if (operands
[i
] == AARCH64_OPND_LEt
)
6558 if (!(vectype
.defined
& NTA_HASINDEX
))
6560 info
->reglist
.has_index
= 1;
6561 info
->reglist
.index
= vectype
.index
;
6565 if (vectype
.defined
& NTA_HASINDEX
)
6567 if (!(vectype
.defined
& NTA_HASTYPE
))
6569 if (reg_type
== REG_TYPE_ZN
)
6570 set_fatal_syntax_error (_("missing type suffix"));
6574 info
->qualifier
= vectype_to_qualifier (&vectype
);
6575 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6579 case AARCH64_OPND_CRn
:
6580 case AARCH64_OPND_CRm
:
6582 char prefix
= *(str
++);
6583 if (prefix
!= 'c' && prefix
!= 'C')
6586 po_imm_nc_or_fail ();
6589 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6592 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6593 info
->imm
.value
= val
;
6597 case AARCH64_OPND_SHLL_IMM
:
6598 case AARCH64_OPND_IMM_VLSR
:
6599 po_imm_or_fail (1, 64);
6600 info
->imm
.value
= val
;
6603 case AARCH64_OPND_CCMP_IMM
:
6604 case AARCH64_OPND_SIMM5
:
6605 case AARCH64_OPND_FBITS
:
6606 case AARCH64_OPND_TME_UIMM16
:
6607 case AARCH64_OPND_UIMM4
:
6608 case AARCH64_OPND_UIMM4_ADDG
:
6609 case AARCH64_OPND_UIMM10
:
6610 case AARCH64_OPND_UIMM3_OP1
:
6611 case AARCH64_OPND_UIMM3_OP2
:
6612 case AARCH64_OPND_IMM_VLSL
:
6613 case AARCH64_OPND_IMM
:
6614 case AARCH64_OPND_IMM_2
:
6615 case AARCH64_OPND_WIDTH
:
6616 case AARCH64_OPND_SVE_INV_LIMM
:
6617 case AARCH64_OPND_SVE_LIMM
:
6618 case AARCH64_OPND_SVE_LIMM_MOV
:
6619 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6620 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6621 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6622 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6623 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6624 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6625 case AARCH64_OPND_SVE_SIMM5
:
6626 case AARCH64_OPND_SVE_SIMM5B
:
6627 case AARCH64_OPND_SVE_SIMM6
:
6628 case AARCH64_OPND_SVE_SIMM8
:
6629 case AARCH64_OPND_SVE_UIMM3
:
6630 case AARCH64_OPND_SVE_UIMM7
:
6631 case AARCH64_OPND_SVE_UIMM8
:
6632 case AARCH64_OPND_SVE_UIMM8_53
:
6633 case AARCH64_OPND_IMM_ROT1
:
6634 case AARCH64_OPND_IMM_ROT2
:
6635 case AARCH64_OPND_IMM_ROT3
:
6636 case AARCH64_OPND_SVE_IMM_ROT1
:
6637 case AARCH64_OPND_SVE_IMM_ROT2
:
6638 case AARCH64_OPND_SVE_IMM_ROT3
:
6639 po_imm_nc_or_fail ();
6640 info
->imm
.value
= val
;
6643 case AARCH64_OPND_SVE_AIMM
:
6644 case AARCH64_OPND_SVE_ASIMM
:
6645 po_imm_nc_or_fail ();
6646 info
->imm
.value
= val
;
6647 skip_whitespace (str
);
6648 if (skip_past_comma (&str
))
6649 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6651 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6654 case AARCH64_OPND_SVE_PATTERN
:
6655 po_enum_or_fail (aarch64_sve_pattern_array
);
6656 info
->imm
.value
= val
;
6659 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6660 po_enum_or_fail (aarch64_sve_pattern_array
);
6661 info
->imm
.value
= val
;
6662 if (skip_past_comma (&str
)
6663 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6665 if (!info
->shifter
.operator_present
)
6667 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6668 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6669 info
->shifter
.amount
= 1;
6673 case AARCH64_OPND_SVE_PRFOP
:
6674 po_enum_or_fail (aarch64_sve_prfop_array
);
6675 info
->imm
.value
= val
;
6678 case AARCH64_OPND_UIMM7
:
6679 po_imm_or_fail (0, 127);
6680 info
->imm
.value
= val
;
6683 case AARCH64_OPND_IDX
:
6684 case AARCH64_OPND_MASK
:
6685 case AARCH64_OPND_BIT_NUM
:
6686 case AARCH64_OPND_IMMR
:
6687 case AARCH64_OPND_IMMS
:
6688 po_imm_or_fail (0, 63);
6689 info
->imm
.value
= val
;
6692 case AARCH64_OPND_IMM0
:
6693 po_imm_nc_or_fail ();
6696 set_fatal_syntax_error (_("immediate zero expected"));
6699 info
->imm
.value
= 0;
6702 case AARCH64_OPND_FPIMM0
:
6705 bool res1
= false, res2
= false;
6706 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6707 it is probably not worth the effort to support it. */
6708 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6711 || !(res2
= parse_constant_immediate (&str
, &val
,
6714 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6716 info
->imm
.value
= 0;
6717 info
->imm
.is_fp
= 1;
6720 set_fatal_syntax_error (_("immediate zero expected"));
6724 case AARCH64_OPND_IMM_MOV
:
6727 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6728 reg_name_p (str
, REG_TYPE_VN
))
6731 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6732 GE_OPT_PREFIX
, REJECT_ABSENT
));
6733 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6734 later. fix_mov_imm_insn will try to determine a machine
6735 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6736 message if the immediate cannot be moved by a single
6738 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6739 inst
.base
.operands
[i
].skip
= 1;
6743 case AARCH64_OPND_SIMD_IMM
:
6744 case AARCH64_OPND_SIMD_IMM_SFT
:
6745 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6747 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6749 /* need_libopcodes_p */ 1,
6752 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6753 shift, we don't check it here; we leave the checking to
6754 the libopcodes (operand_general_constraint_met_p). By
6755 doing this, we achieve better diagnostics. */
6756 if (skip_past_comma (&str
)
6757 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6759 if (!info
->shifter
.operator_present
6760 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6762 /* Default to LSL if not present. Libopcodes prefers shifter
6763 kind to be explicit. */
6764 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6765 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6769 case AARCH64_OPND_FPIMM
:
6770 case AARCH64_OPND_SIMD_FPIMM
:
6771 case AARCH64_OPND_SVE_FPIMM8
:
6776 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6777 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6778 || !aarch64_imm_float_p (qfloat
))
6781 set_fatal_syntax_error (_("invalid floating-point"
6785 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6786 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6790 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6791 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6792 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6797 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6798 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6801 set_fatal_syntax_error (_("invalid floating-point"
6805 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6806 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6810 case AARCH64_OPND_LIMM
:
6811 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6812 SHIFTED_LOGIC_IMM
));
6813 if (info
->shifter
.operator_present
)
6815 set_fatal_syntax_error
6816 (_("shift not allowed for bitmask immediate"));
6819 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6821 /* need_libopcodes_p */ 1,
6825 case AARCH64_OPND_AIMM
:
6826 if (opcode
->op
== OP_ADD
)
6827 /* ADD may have relocation types. */
6828 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6829 SHIFTED_ARITH_IMM
));
6831 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6832 SHIFTED_ARITH_IMM
));
6833 switch (inst
.reloc
.type
)
6835 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6836 info
->shifter
.amount
= 12;
6838 case BFD_RELOC_UNUSED
:
6839 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6840 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6841 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6842 inst
.reloc
.pc_rel
= 0;
6847 info
->imm
.value
= 0;
6848 if (!info
->shifter
.operator_present
)
6850 /* Default to LSL if not present. Libopcodes prefers shifter
6851 kind to be explicit. */
6852 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6853 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6857 case AARCH64_OPND_HALF
:
6859 /* #<imm16> or relocation. */
6860 int internal_fixup_p
;
6861 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6862 if (internal_fixup_p
)
6863 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6864 skip_whitespace (str
);
6865 if (skip_past_comma (&str
))
6867 /* {, LSL #<shift>} */
6868 if (! aarch64_gas_internal_fixup_p ())
6870 set_fatal_syntax_error (_("can't mix relocation modifier "
6871 "with explicit shift"));
6874 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6877 inst
.base
.operands
[i
].shifter
.amount
= 0;
6878 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6879 inst
.base
.operands
[i
].imm
.value
= 0;
6880 if (! process_movw_reloc_info ())
6885 case AARCH64_OPND_EXCEPTION
:
6886 case AARCH64_OPND_UNDEFINED
:
6887 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6889 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6891 /* need_libopcodes_p */ 0,
6895 case AARCH64_OPND_NZCV
:
6897 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6901 info
->imm
.value
= nzcv
->value
;
6904 po_imm_or_fail (0, 15);
6905 info
->imm
.value
= val
;
6909 case AARCH64_OPND_COND
:
6910 case AARCH64_OPND_COND1
:
6915 while (ISALPHA (*str
));
6916 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6917 if (info
->cond
== NULL
)
6919 set_syntax_error (_("invalid condition"));
6922 else if (operands
[i
] == AARCH64_OPND_COND1
6923 && (info
->cond
->value
& 0xe) == 0xe)
6925 /* Do not allow AL or NV. */
6926 set_default_error ();
6932 case AARCH64_OPND_ADDR_ADRP
:
6933 po_misc_or_fail (parse_adrp (&str
));
6934 /* Clear the value as operand needs to be relocated. */
6935 info
->imm
.value
= 0;
6938 case AARCH64_OPND_ADDR_PCREL14
:
6939 case AARCH64_OPND_ADDR_PCREL19
:
6940 case AARCH64_OPND_ADDR_PCREL21
:
6941 case AARCH64_OPND_ADDR_PCREL26
:
6942 po_misc_or_fail (parse_address (&str
, info
));
6943 if (!info
->addr
.pcrel
)
6945 set_syntax_error (_("invalid pc-relative address"));
6948 if (inst
.gen_lit_pool
6949 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6951 /* Only permit "=value" in the literal load instructions.
6952 The literal will be generated by programmer_friendly_fixup. */
6953 set_syntax_error (_("invalid use of \"=immediate\""));
6956 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6958 set_syntax_error (_("unrecognized relocation suffix"));
6961 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6963 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6964 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6968 info
->imm
.value
= 0;
6969 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6970 switch (opcode
->iclass
)
6974 /* e.g. CBZ or B.COND */
6975 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6976 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6980 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6981 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6985 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6987 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6988 : BFD_RELOC_AARCH64_JUMP26
;
6991 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6992 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6995 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6996 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
7002 inst
.reloc
.pc_rel
= 1;
7006 case AARCH64_OPND_ADDR_SIMPLE
:
7007 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
7009 /* [<Xn|SP>{, #<simm>}] */
7011 /* First use the normal address-parsing routines, to get
7012 the usual syntax errors. */
7013 po_misc_or_fail (parse_address (&str
, info
));
7014 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7015 || !info
->addr
.preind
|| info
->addr
.postind
7016 || info
->addr
.writeback
)
7018 set_syntax_error (_("invalid addressing mode"));
7022 /* Then retry, matching the specific syntax of these addresses. */
7024 po_char_or_fail ('[');
7025 po_reg_or_fail (REG_TYPE_R64_SP
);
7026 /* Accept optional ", #0". */
7027 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
7028 && skip_past_char (&str
, ','))
7030 skip_past_char (&str
, '#');
7031 if (! skip_past_char (&str
, '0'))
7033 set_fatal_syntax_error
7034 (_("the optional immediate offset can only be 0"));
7038 po_char_or_fail (']');
7042 case AARCH64_OPND_ADDR_REGOFF
:
7043 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
7044 po_misc_or_fail (parse_address (&str
, info
));
7046 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
7047 || !info
->addr
.preind
|| info
->addr
.postind
7048 || info
->addr
.writeback
)
7050 set_syntax_error (_("invalid addressing mode"));
7053 if (!info
->shifter
.operator_present
)
7055 /* Default to LSL if not present. Libopcodes prefers shifter
7056 kind to be explicit. */
7057 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7058 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7060 /* Qualifier to be deduced by libopcodes. */
7063 case AARCH64_OPND_ADDR_SIMM7
:
7064 po_misc_or_fail (parse_address (&str
, info
));
7065 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7066 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7068 set_syntax_error (_("invalid addressing mode"));
7071 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7073 set_syntax_error (_("relocation not allowed"));
7076 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7078 /* need_libopcodes_p */ 1,
7082 case AARCH64_OPND_ADDR_SIMM9
:
7083 case AARCH64_OPND_ADDR_SIMM9_2
:
7084 case AARCH64_OPND_ADDR_SIMM11
:
7085 case AARCH64_OPND_ADDR_SIMM13
:
7086 po_misc_or_fail (parse_address (&str
, info
));
7087 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7088 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7089 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7090 && info
->addr
.writeback
))
7092 set_syntax_error (_("invalid addressing mode"));
7095 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7097 set_syntax_error (_("relocation not allowed"));
7100 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7102 /* need_libopcodes_p */ 1,
7106 case AARCH64_OPND_ADDR_SIMM10
:
7107 case AARCH64_OPND_ADDR_OFFSET
:
7108 po_misc_or_fail (parse_address (&str
, info
));
7109 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7110 || !info
->addr
.preind
|| info
->addr
.postind
)
7112 set_syntax_error (_("invalid addressing mode"));
7115 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7117 set_syntax_error (_("relocation not allowed"));
7120 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7122 /* need_libopcodes_p */ 1,
7126 case AARCH64_OPND_ADDR_UIMM12
:
7127 po_misc_or_fail (parse_address (&str
, info
));
7128 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7129 || !info
->addr
.preind
|| info
->addr
.writeback
)
7131 set_syntax_error (_("invalid addressing mode"));
7134 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7135 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7136 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7138 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7140 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7142 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7144 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7145 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7146 /* Leave qualifier to be determined by libopcodes. */
7149 case AARCH64_OPND_SIMD_ADDR_POST
:
7150 /* [<Xn|SP>], <Xm|#<amount>> */
7151 po_misc_or_fail (parse_address (&str
, info
));
7152 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7154 set_syntax_error (_("invalid addressing mode"));
7157 if (!info
->addr
.offset
.is_reg
)
7159 if (inst
.reloc
.exp
.X_op
== O_constant
)
7160 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7163 set_fatal_syntax_error
7164 (_("writeback value must be an immediate constant"));
7171 case AARCH64_OPND_SME_SM_ZA
:
7173 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7175 set_syntax_error (_("unknown or missing PSTATE field name"));
7178 info
->reg
.regno
= val
;
7181 case AARCH64_OPND_SME_PnT_Wm_imm
:
7182 /* <Pn>.<T>[<Wm>, #<imm>] */
7186 val
= parse_sme_pred_reg_with_index (&str
,
7190 if (val
== PARSE_FAIL
)
7193 info
->za_tile_vector
.regno
= val
;
7194 info
->za_tile_vector
.index
.regno
= index_base_reg
;
7195 info
->za_tile_vector
.index
.imm
= imm
;
7196 info
->qualifier
= qualifier
;
7200 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7201 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7202 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7203 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7204 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7205 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7206 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7207 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7208 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7209 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7210 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7211 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7212 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7213 /* [X<n>{, #imm, MUL VL}]
7215 but recognizing SVE registers. */
7216 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7217 &offset_qualifier
));
7218 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7220 set_syntax_error (_("invalid addressing mode"));
7224 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7225 || !info
->addr
.preind
|| info
->addr
.writeback
)
7227 set_syntax_error (_("invalid addressing mode"));
7230 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7231 || inst
.reloc
.exp
.X_op
!= O_constant
)
7233 /* Make sure this has priority over
7234 "invalid addressing mode". */
7235 set_fatal_syntax_error (_("constant offset required"));
7238 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7241 case AARCH64_OPND_SVE_ADDR_R
:
7242 /* [<Xn|SP>{, <R><m>}]
7243 but recognizing SVE registers. */
7244 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7245 &offset_qualifier
));
7246 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7248 offset_qualifier
= AARCH64_OPND_QLF_X
;
7249 info
->addr
.offset
.is_reg
= 1;
7250 info
->addr
.offset
.regno
= 31;
7252 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7253 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7255 set_syntax_error (_("invalid addressing mode"));
7260 case AARCH64_OPND_SVE_ADDR_RR
:
7261 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7262 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7263 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7264 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7265 case AARCH64_OPND_SVE_ADDR_RX
:
7266 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7267 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7268 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7269 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7270 but recognizing SVE registers. */
7271 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7272 &offset_qualifier
));
7273 if (base_qualifier
!= AARCH64_OPND_QLF_X
7274 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7276 set_syntax_error (_("invalid addressing mode"));
7281 case AARCH64_OPND_SVE_ADDR_RZ
:
7282 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7283 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7284 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7285 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7286 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7287 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7288 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7289 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7290 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7291 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7292 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7293 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7294 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7295 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7296 &offset_qualifier
));
7297 if (base_qualifier
!= AARCH64_OPND_QLF_X
7298 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7299 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7301 set_syntax_error (_("invalid addressing mode"));
7304 info
->qualifier
= offset_qualifier
;
7307 case AARCH64_OPND_SVE_ADDR_ZX
:
7308 /* [Zn.<T>{, <Xm>}]. */
7309 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7310 &offset_qualifier
));
7312 base_qualifier either S_S or S_D
7313 offset_qualifier must be X
7315 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7316 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7317 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7319 set_syntax_error (_("invalid addressing mode"));
7322 info
->qualifier
= base_qualifier
;
7323 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7324 || !info
->addr
.preind
|| info
->addr
.writeback
7325 || info
->shifter
.operator_present
!= 0)
7327 set_syntax_error (_("invalid addressing mode"));
7330 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7334 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7335 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7336 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7337 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7338 /* [Z<n>.<T>{, #imm}] */
7339 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7340 &offset_qualifier
));
7341 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7342 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7344 set_syntax_error (_("invalid addressing mode"));
7347 info
->qualifier
= base_qualifier
;
7350 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7351 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7352 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7353 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7354 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7358 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7360 here since we get better error messages by leaving it to
7361 the qualifier checking routines. */
7362 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7363 &offset_qualifier
));
7364 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7365 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7366 || offset_qualifier
!= base_qualifier
)
7368 set_syntax_error (_("invalid addressing mode"));
7371 info
->qualifier
= base_qualifier
;
7374 case AARCH64_OPND_SYSREG
:
7376 uint32_t sysreg_flags
;
7377 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7378 &sysreg_flags
)) == PARSE_FAIL
)
7380 set_syntax_error (_("unknown or missing system register name"));
7383 inst
.base
.operands
[i
].sysreg
.value
= val
;
7384 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7388 case AARCH64_OPND_PSTATEFIELD
:
7390 uint32_t sysreg_flags
;
7391 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7392 &sysreg_flags
)) == PARSE_FAIL
)
7394 set_syntax_error (_("unknown or missing PSTATE field name"));
7397 inst
.base
.operands
[i
].pstatefield
= val
;
7398 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7402 case AARCH64_OPND_SYSREG_IC
:
7403 inst
.base
.operands
[i
].sysins_op
=
7404 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7407 case AARCH64_OPND_SYSREG_DC
:
7408 inst
.base
.operands
[i
].sysins_op
=
7409 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7412 case AARCH64_OPND_SYSREG_AT
:
7413 inst
.base
.operands
[i
].sysins_op
=
7414 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7417 case AARCH64_OPND_SYSREG_SR
:
7418 inst
.base
.operands
[i
].sysins_op
=
7419 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7422 case AARCH64_OPND_SYSREG_TLBI
:
7423 inst
.base
.operands
[i
].sysins_op
=
7424 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7426 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7428 set_fatal_syntax_error ( _("unknown or missing operation name"));
7433 case AARCH64_OPND_BARRIER
:
7434 case AARCH64_OPND_BARRIER_ISB
:
7435 val
= parse_barrier (&str
);
7436 if (val
!= PARSE_FAIL
7437 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7439 /* ISB only accepts options name 'sy'. */
7441 (_("the specified option is not accepted in ISB"));
7442 /* Turn off backtrack as this optional operand is present. */
7446 if (val
!= PARSE_FAIL
7447 && operands
[i
] == AARCH64_OPND_BARRIER
)
7449 /* Regular barriers accept options CRm (C0-C15).
7450 DSB nXS barrier variant accepts values > 15. */
7451 if (val
< 0 || val
> 15)
7453 set_syntax_error (_("the specified option is not accepted in DSB"));
7457 /* This is an extension to accept a 0..15 immediate. */
7458 if (val
== PARSE_FAIL
)
7459 po_imm_or_fail (0, 15);
7460 info
->barrier
= aarch64_barrier_options
+ val
;
7463 case AARCH64_OPND_BARRIER_DSB_NXS
:
7464 val
= parse_barrier (&str
);
7465 if (val
!= PARSE_FAIL
)
7467 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7468 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7470 set_syntax_error (_("the specified option is not accepted in DSB"));
7471 /* Turn off backtrack as this optional operand is present. */
7478 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7479 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7480 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7482 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7484 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7488 /* Option index is encoded as 2-bit value in val<3:2>. */
7489 val
= (val
>> 2) - 4;
7490 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7493 case AARCH64_OPND_PRFOP
:
7494 val
= parse_pldop (&str
);
7495 /* This is an extension to accept a 0..31 immediate. */
7496 if (val
== PARSE_FAIL
)
7497 po_imm_or_fail (0, 31);
7498 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7501 case AARCH64_OPND_BARRIER_PSB
:
7502 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7503 if (val
== PARSE_FAIL
)
7507 case AARCH64_OPND_BTI_TARGET
:
7508 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7509 if (val
== PARSE_FAIL
)
7513 case AARCH64_OPND_SME_ZAda_2b
:
7514 case AARCH64_OPND_SME_ZAda_3b
:
7515 val
= parse_sme_zada_operand (&str
, &qualifier
);
7516 if (val
== PARSE_FAIL
)
7518 info
->reg
.regno
= val
;
7519 info
->qualifier
= qualifier
;
7522 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7523 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7524 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7526 enum sme_hv_slice slice_indicator
;
7527 int vector_select_register
;
7530 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
)
7531 val
= parse_sme_za_hv_tiles_operand_with_braces (&str
,
7533 &vector_select_register
,
7537 val
= parse_sme_za_hv_tiles_operand (&str
, &slice_indicator
,
7538 &vector_select_register
,
7541 if (val
== PARSE_FAIL
)
7543 info
->za_tile_vector
.regno
= val
;
7544 info
->za_tile_vector
.index
.regno
= vector_select_register
;
7545 info
->za_tile_vector
.index
.imm
= imm
;
7546 info
->za_tile_vector
.v
= slice_indicator
;
7547 info
->qualifier
= qualifier
;
7551 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7552 val
= parse_sme_list_of_64bit_tiles (&str
);
7553 if (val
== PARSE_FAIL
)
7555 info
->imm
.value
= val
;
7558 case AARCH64_OPND_SME_ZA_array
:
7561 val
= parse_sme_za_array (&str
, &imm
);
7562 if (val
== PARSE_FAIL
)
7564 info
->za_tile_vector
.index
.regno
= val
;
7565 info
->za_tile_vector
.index
.imm
= imm
;
7569 case AARCH64_OPND_MOPS_ADDR_Rd
:
7570 case AARCH64_OPND_MOPS_ADDR_Rs
:
7571 po_char_or_fail ('[');
7572 if (!parse_x0_to_x30 (&str
, info
))
7574 po_char_or_fail (']');
7575 po_char_or_fail ('!');
7578 case AARCH64_OPND_MOPS_WB_Rn
:
7579 if (!parse_x0_to_x30 (&str
, info
))
7581 po_char_or_fail ('!');
7585 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7588 /* If we get here, this operand was successfully parsed. */
7589 inst
.base
.operands
[i
].present
= 1;
7593 /* The parse routine should already have set the error, but in case
7594 not, set a default one here. */
7596 set_default_error ();
7598 if (! backtrack_pos
)
7599 goto parse_operands_return
;
7602 /* We reach here because this operand is marked as optional, and
7603 either no operand was supplied or the operand was supplied but it
7604 was syntactically incorrect. In the latter case we report an
7605 error. In the former case we perform a few more checks before
7606 dropping through to the code to insert the default operand. */
7608 char *tmp
= backtrack_pos
;
7609 char endchar
= END_OF_INSN
;
7611 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7613 skip_past_char (&tmp
, ',');
7615 if (*tmp
!= endchar
)
7616 /* The user has supplied an operand in the wrong format. */
7617 goto parse_operands_return
;
7619 /* Make sure there is not a comma before the optional operand.
7620 For example the fifth operand of 'sys' is optional:
7622 sys #0,c0,c0,#0, <--- wrong
7623 sys #0,c0,c0,#0 <--- correct. */
7624 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7626 set_fatal_syntax_error
7627 (_("unexpected comma before the omitted optional operand"));
7628 goto parse_operands_return
;
7632 /* Reaching here means we are dealing with an optional operand that is
7633 omitted from the assembly line. */
7634 gas_assert (optional_operand_p (opcode
, i
));
7636 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7638 /* Try again, skipping the optional operand at backtrack_pos. */
7639 str
= backtrack_pos
;
7642 /* Clear any error record after the omitted optional operand has been
7643 successfully handled. */
7647 /* Check if we have parsed all the operands. */
7648 if (*str
!= '\0' && ! error_p ())
7650 /* Set I to the index of the last present operand; this is
7651 for the purpose of diagnostics. */
7652 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7654 set_fatal_syntax_error
7655 (_("unexpected characters following instruction"));
7658 parse_operands_return
:
7662 DEBUG_TRACE ("parsing FAIL: %s - %s",
7663 operand_mismatch_kind_names
[get_error_kind ()],
7664 get_error_message ());
7665 /* Record the operand error properly; this is useful when there
7666 are multiple instruction templates for a mnemonic name, so that
7667 later on, we can select the error that most closely describes
7669 record_operand_error (opcode
, i
, get_error_kind (),
7670 get_error_message ());
7675 DEBUG_TRACE ("parsing SUCCESS");
7680 /* It does some fix-up to provide some programmer friendly feature while
7681 keeping the libopcodes happy, i.e. libopcodes only accepts
7682 the preferred architectural syntax.
7683 Return FALSE if there is any failure; otherwise return TRUE. */
7686 programmer_friendly_fixup (aarch64_instruction
*instr
)
7688 aarch64_inst
*base
= &instr
->base
;
7689 const aarch64_opcode
*opcode
= base
->opcode
;
7690 enum aarch64_op op
= opcode
->op
;
7691 aarch64_opnd_info
*operands
= base
->operands
;
7693 DEBUG_TRACE ("enter");
7695 switch (opcode
->iclass
)
7698 /* TBNZ Xn|Wn, #uimm6, label
7699 Test and Branch Not Zero: conditionally jumps to label if bit number
7700 uimm6 in register Xn is not zero. The bit number implies the width of
7701 the register, which may be written and should be disassembled as Wn if
7702 uimm is less than 32. */
7703 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7705 if (operands
[1].imm
.value
>= 32)
7707 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7711 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7715 /* LDR Wt, label | =value
7716 As a convenience assemblers will typically permit the notation
7717 "=value" in conjunction with the pc-relative literal load instructions
7718 to automatically place an immediate value or symbolic address in a
7719 nearby literal pool and generate a hidden label which references it.
7720 ISREG has been set to 0 in the case of =value. */
7721 if (instr
->gen_lit_pool
7722 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7724 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7725 if (op
== OP_LDRSW_LIT
)
7727 if (instr
->reloc
.exp
.X_op
!= O_constant
7728 && instr
->reloc
.exp
.X_op
!= O_big
7729 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7731 record_operand_error (opcode
, 1,
7732 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7733 _("constant expression expected"));
7736 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7738 record_operand_error (opcode
, 1,
7739 AARCH64_OPDE_OTHER_ERROR
,
7740 _("literal pool insertion failed"));
7748 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7749 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7750 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7751 A programmer-friendly assembler should accept a destination Xd in
7752 place of Wd, however that is not the preferred form for disassembly.
7754 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7755 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7756 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7757 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7762 /* In the 64-bit form, the final register operand is written as Wm
7763 for all but the (possibly omitted) UXTX/LSL and SXTX
7765 As a programmer-friendly assembler, we accept e.g.
7766 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7767 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7768 int idx
= aarch64_operand_index (opcode
->operands
,
7769 AARCH64_OPND_Rm_EXT
);
7770 gas_assert (idx
== 1 || idx
== 2);
7771 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7772 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7773 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7774 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7775 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7776 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7784 DEBUG_TRACE ("exit with SUCCESS");
7788 /* Check for loads and stores that will cause unpredictable behavior. */
7791 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7793 aarch64_inst
*base
= &instr
->base
;
7794 const aarch64_opcode
*opcode
= base
->opcode
;
7795 const aarch64_opnd_info
*opnds
= base
->operands
;
7796 switch (opcode
->iclass
)
7803 /* Loading/storing the base register is unpredictable if writeback. */
7804 if ((aarch64_get_operand_class (opnds
[0].type
)
7805 == AARCH64_OPND_CLASS_INT_REG
)
7806 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7807 && opnds
[1].addr
.base_regno
!= REG_SP
7808 /* Exempt STG/STZG/ST2G/STZ2G. */
7809 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7810 && opnds
[1].addr
.writeback
)
7811 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7815 case ldstnapair_offs
:
7816 case ldstpair_indexed
:
7817 /* Loading/storing the base register is unpredictable if writeback. */
7818 if ((aarch64_get_operand_class (opnds
[0].type
)
7819 == AARCH64_OPND_CLASS_INT_REG
)
7820 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7821 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7822 && opnds
[2].addr
.base_regno
!= REG_SP
7824 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7825 && opnds
[2].addr
.writeback
)
7826 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7827 /* Load operations must load different registers. */
7828 if ((opcode
->opcode
& (1 << 22))
7829 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7830 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7834 if ((aarch64_get_operand_class (opnds
[0].type
)
7835 == AARCH64_OPND_CLASS_INT_REG
)
7836 && (aarch64_get_operand_class (opnds
[1].type
)
7837 == AARCH64_OPND_CLASS_INT_REG
))
7839 if ((opcode
->opcode
& (1 << 22)))
7841 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
7842 if ((opcode
->opcode
& (1 << 21))
7843 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7844 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7848 /* Store-Exclusive is unpredictable if Rt == Rs. */
7849 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7851 (_("unpredictable: identical transfer and status registers"
7854 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
7856 if (!(opcode
->opcode
& (1 << 21)))
7857 /* Store-Exclusive is unpredictable if Rn == Rs. */
7859 (_("unpredictable: identical base and status registers"
7862 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
7864 (_("unpredictable: "
7865 "identical transfer and status registers"
7869 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
7870 if ((opcode
->opcode
& (1 << 21))
7871 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
7872 && opnds
[3].reg
.regno
!= REG_SP
)
7873 as_warn (_("unpredictable: identical base and status registers"
7885 force_automatic_sequence_close (void)
7887 struct aarch64_segment_info_type
*tc_seg_info
;
7889 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7890 if (tc_seg_info
->insn_sequence
.instr
)
7892 as_warn_where (tc_seg_info
->last_file
, tc_seg_info
->last_line
,
7893 _("previous `%s' sequence has not been closed"),
7894 tc_seg_info
->insn_sequence
.instr
->opcode
->name
);
7895 init_insn_sequence (NULL
, &tc_seg_info
->insn_sequence
);
7899 /* A wrapper function to interface with libopcodes on encoding and
7900 record the error message if there is any.
7902 Return TRUE on success; otherwise return FALSE. */
7905 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7908 aarch64_operand_error error_info
;
7909 memset (&error_info
, '\0', sizeof (error_info
));
7910 error_info
.kind
= AARCH64_OPDE_NIL
;
7911 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7912 && !error_info
.non_fatal
)
7915 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7916 record_operand_error_info (opcode
, &error_info
);
7917 return error_info
.non_fatal
;
7920 #ifdef DEBUG_AARCH64
7922 dump_opcode_operands (const aarch64_opcode
*opcode
)
7925 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7927 aarch64_verbose ("\t\t opnd%d: %s", i
,
7928 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7929 ? aarch64_get_operand_name (opcode
->operands
[i
])
7930 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7934 #endif /* DEBUG_AARCH64 */
7936 /* This is the guts of the machine-dependent assembler. STR points to a
7937 machine dependent instruction. This function is supposed to emit
7938 the frags/bytes it assembles to. */
7941 md_assemble (char *str
)
7943 templates
*template;
7944 const aarch64_opcode
*opcode
;
7945 struct aarch64_segment_info_type
*tc_seg_info
;
7946 aarch64_inst
*inst_base
;
7947 unsigned saved_cond
;
7949 /* Align the previous label if needed. */
7950 if (last_label_seen
!= NULL
)
7952 symbol_set_frag (last_label_seen
, frag_now
);
7953 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7954 S_SET_SEGMENT (last_label_seen
, now_seg
);
7957 /* Update the current insn_sequence from the segment. */
7958 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7959 insn_sequence
= &tc_seg_info
->insn_sequence
;
7960 tc_seg_info
->last_file
= as_where (&tc_seg_info
->last_line
);
7962 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7964 DEBUG_TRACE ("\n\n");
7965 DEBUG_TRACE ("==============================");
7966 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7968 /* Scan up to the end of the mnemonic, which must end in whitespace,
7969 '.', or end of string. */
7972 for (; is_part_of_name (*p
); p
++)
7973 if (*p
== '.' && !dot
)
7978 as_bad (_("unknown mnemonic -- `%s'"), str
);
7982 if (!dot
&& create_register_alias (str
, p
))
7985 template = opcode_lookup (str
, dot
, p
);
7988 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7993 skip_whitespace (p
);
7996 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7997 get_mnemonic_name (str
), str
);
8001 init_operand_error_report ();
8003 /* Sections are assumed to start aligned. In executable section, there is no
8004 MAP_DATA symbol pending. So we only align the address during
8005 MAP_DATA --> MAP_INSN transition.
8006 For other sections, this is not guaranteed. */
8007 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
8008 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
8009 frag_align_code (2, 0);
8011 saved_cond
= inst
.cond
;
8012 reset_aarch64_instruction (&inst
);
8013 inst
.cond
= saved_cond
;
8015 /* Iterate through all opcode entries with the same mnemonic name. */
8018 opcode
= template->opcode
;
8020 DEBUG_TRACE ("opcode %s found", opcode
->name
);
8021 #ifdef DEBUG_AARCH64
8023 dump_opcode_operands (opcode
);
8024 #endif /* DEBUG_AARCH64 */
8026 mapping_state (MAP_INSN
);
8028 inst_base
= &inst
.base
;
8029 inst_base
->opcode
= opcode
;
8031 /* Truly conditionally executed instructions, e.g. b.cond. */
8032 if (opcode
->flags
& F_COND
)
8034 gas_assert (inst
.cond
!= COND_ALWAYS
);
8035 inst_base
->cond
= get_cond_from_value (inst
.cond
);
8036 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
8038 else if (inst
.cond
!= COND_ALWAYS
)
8040 /* It shouldn't arrive here, where the assembly looks like a
8041 conditional instruction but the found opcode is unconditional. */
8046 if (parse_operands (p
, opcode
)
8047 && programmer_friendly_fixup (&inst
)
8048 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
8050 /* Check that this instruction is supported for this CPU. */
8051 if (!opcode
->avariant
8052 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
8054 as_bad (_("selected processor does not support `%s'"), str
);
8058 warn_unpredictable_ldst (&inst
, str
);
8060 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
8061 || !inst
.reloc
.need_libopcodes_p
)
8065 /* If there is relocation generated for the instruction,
8066 store the instruction information for the future fix-up. */
8067 struct aarch64_inst
*copy
;
8068 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
8069 copy
= XNEW (struct aarch64_inst
);
8070 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
8074 /* Issue non-fatal messages if any. */
8075 output_operand_error_report (str
, true);
8079 template = template->next
;
8080 if (template != NULL
)
8082 reset_aarch64_instruction (&inst
);
8083 inst
.cond
= saved_cond
;
8086 while (template != NULL
);
8088 /* Issue the error messages if any. */
8089 output_operand_error_report (str
, false);
8092 /* Various frobbings of labels and their addresses. */
8095 aarch64_start_line_hook (void)
8097 last_label_seen
= NULL
;
8101 aarch64_frob_label (symbolS
* sym
)
8103 last_label_seen
= sym
;
8105 dwarf2_emit_label (sym
);
8109 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8111 /* Check to see if we have a block to close. */
8112 force_automatic_sequence_close ();
8116 aarch64_data_in_code (void)
8118 if (startswith (input_line_pointer
+ 1, "data:"))
8120 *input_line_pointer
= '/';
8121 input_line_pointer
+= 5;
8122 *input_line_pointer
= 0;
8130 aarch64_canonicalize_symbol_name (char *name
)
8134 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8135 *(name
+ len
- 5) = 0;
8140 /* Table of all register names defined by default. The user can
8141 define additional names with .req. Note that all register names
8142 should appear in both upper and lowercase variants. Some registers
8143 also have mixed-case names. */
8145 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8146 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8147 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8148 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8149 #define REGSET16(p,t) \
8150 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8151 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8152 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8153 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8154 #define REGSET16S(p,s,t) \
8155 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8156 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8157 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8158 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8159 #define REGSET31(p,t) \
8161 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8162 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8163 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8164 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8165 #define REGSET(p,t) \
8166 REGSET31(p,t), REGNUM(p,31,t)
8168 /* These go into aarch64_reg_hsh hash-table. */
8169 static const reg_entry reg_names
[] = {
8170 /* Integer registers. */
8171 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8172 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8174 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8175 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8176 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8177 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8178 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8179 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8181 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
8182 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
8184 /* Floating-point single precision registers. */
8185 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8187 /* Floating-point double precision registers. */
8188 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8190 /* Floating-point half precision registers. */
8191 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8193 /* Floating-point byte precision registers. */
8194 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8196 /* Floating-point quad precision registers. */
8197 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8199 /* FP/SIMD registers. */
8200 REGSET (v
, VN
), REGSET (V
, VN
),
8202 /* SVE vector registers. */
8203 REGSET (z
, ZN
), REGSET (Z
, ZN
),
8205 /* SVE predicate registers. */
8206 REGSET16 (p
, PN
), REGSET16 (P
, PN
),
8208 /* SME ZA tile registers. */
8209 REGSET16 (za
, ZA
), REGSET16 (ZA
, ZA
),
8211 /* SME ZA tile registers (horizontal slice). */
8212 REGSET16S (za
, h
, ZAH
), REGSET16S (ZA
, H
, ZAH
),
8214 /* SME ZA tile registers (vertical slice). */
8215 REGSET16S (za
, v
, ZAV
), REGSET16S (ZA
, V
, ZAV
)
8233 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8234 static const asm_nzcv nzcv_names
[] = {
8235 {"nzcv", B (n
, z
, c
, v
)},
8236 {"nzcV", B (n
, z
, c
, V
)},
8237 {"nzCv", B (n
, z
, C
, v
)},
8238 {"nzCV", B (n
, z
, C
, V
)},
8239 {"nZcv", B (n
, Z
, c
, v
)},
8240 {"nZcV", B (n
, Z
, c
, V
)},
8241 {"nZCv", B (n
, Z
, C
, v
)},
8242 {"nZCV", B (n
, Z
, C
, V
)},
8243 {"Nzcv", B (N
, z
, c
, v
)},
8244 {"NzcV", B (N
, z
, c
, V
)},
8245 {"NzCv", B (N
, z
, C
, v
)},
8246 {"NzCV", B (N
, z
, C
, V
)},
8247 {"NZcv", B (N
, Z
, c
, v
)},
8248 {"NZcV", B (N
, Z
, c
, V
)},
8249 {"NZCv", B (N
, Z
, C
, v
)},
8250 {"NZCV", B (N
, Z
, C
, V
)}
8263 /* MD interface: bits in the object file. */
8265 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8266 for use in the a.out file, and stores them in the array pointed to by buf.
8267 This knows about the endian-ness of the target machine and does
8268 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8269 2 (short) and 4 (long) Floating numbers are put out as a series of
8270 LITTLENUMS (shorts, here at least). */
8273 md_number_to_chars (char *buf
, valueT val
, int n
)
8275 if (target_big_endian
)
8276 number_to_chars_bigendian (buf
, val
, n
);
8278 number_to_chars_littleendian (buf
, val
, n
);
8281 /* MD interface: Sections. */
8283 /* Estimate the size of a frag before relaxing. Assume everything fits in
8287 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8293 /* Round up a section size to the appropriate boundary. */
8296 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8301 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8302 of an rs_align_code fragment.
8304 Here we fill the frag with the appropriate info for padding the
8305 output stream. The resulting frag will consist of a fixed (fr_fix)
8306 and of a repeating (fr_var) part.
8308 The fixed content is always emitted before the repeating content and
8309 these two parts are used as follows in constructing the output:
8310 - the fixed part will be used to align to a valid instruction word
8311 boundary, in case that we start at a misaligned address; as no
8312 executable instruction can live at the misaligned location, we
8313 simply fill with zeros;
8314 - the variable part will be used to cover the remaining padding and
8315 we fill using the AArch64 NOP instruction.
8317 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8318 enough storage space for up to 3 bytes for padding the back to a valid
8319 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8322 aarch64_handle_align (fragS
* fragP
)
8324 /* NOP = d503201f */
8325 /* AArch64 instructions are always little-endian. */
8326 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8328 int bytes
, fix
, noop_size
;
8331 if (fragP
->fr_type
!= rs_align_code
)
8334 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8335 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8338 gas_assert (fragP
->tc_frag_data
.recorded
);
8341 noop_size
= sizeof (aarch64_noop
);
8343 fix
= bytes
& (noop_size
- 1);
8346 #if defined OBJ_ELF || defined OBJ_COFF
8347 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8351 fragP
->fr_fix
+= fix
;
8355 memcpy (p
, aarch64_noop
, noop_size
);
8356 fragP
->fr_var
= noop_size
;
8359 /* Perform target specific initialisation of a frag.
8360 Note - despite the name this initialisation is not done when the frag
8361 is created, but only when its type is assigned. A frag can be created
8362 and used a long time before its type is set, so beware of assuming that
8363 this initialisation is performed first. */
8367 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8368 int max_chars ATTRIBUTE_UNUSED
)
8372 #else /* OBJ_ELF is defined. */
8374 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8376 /* Record a mapping symbol for alignment frags. We will delete this
8377 later if the alignment ends up empty. */
8378 if (!fragP
->tc_frag_data
.recorded
)
8379 fragP
->tc_frag_data
.recorded
= 1;
8381 /* PR 21809: Do not set a mapping state for debug sections
8382 - it just confuses other tools. */
8383 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8386 switch (fragP
->fr_type
)
8390 mapping_state_2 (MAP_DATA
, max_chars
);
8393 /* PR 20364: We can get alignment frags in code sections,
8394 so do not just assume that we should use the MAP_DATA state. */
8395 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8398 mapping_state_2 (MAP_INSN
, max_chars
);
8404 #endif /* OBJ_ELF */
8406 /* Initialize the DWARF-2 unwind information for this procedure. */
8409 tc_aarch64_frame_initial_instructions (void)
8411 cfi_add_CFA_def_cfa (REG_SP
, 0);
8414 /* Convert REGNAME to a DWARF-2 register number. */
8417 tc_aarch64_regname_to_dw2regnum (char *regname
)
8419 const reg_entry
*reg
= parse_reg (®name
);
8425 case REG_TYPE_SP_32
:
8426 case REG_TYPE_SP_64
:
8436 return reg
->number
+ 64;
8444 /* Implement DWARF2_ADDR_SIZE. */
8447 aarch64_dwarf2_addr_size (void)
8453 return bfd_arch_bits_per_address (stdoutput
) / 8;
8456 /* MD interface: Symbol and relocation handling. */
8458 /* Return the address within the segment that a PC-relative fixup is
8459 relative to. For AArch64 PC-relative fixups applied to instructions
8460 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8463 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8465 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8467 /* If this is pc-relative and we are going to emit a relocation
8468 then we just want to put out any pipeline compensation that the linker
8469 will need. Otherwise we want to use the calculated base. */
8471 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8472 || aarch64_force_relocation (fixP
)))
8475 /* AArch64 should be consistent for all pc-relative relocations. */
8476 return base
+ AARCH64_PCREL_OFFSET
;
8479 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8480 Otherwise we have no need to default values of symbols. */
8483 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8486 if (name
[0] == '_' && name
[1] == 'G'
8487 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8491 if (symbol_find (name
))
8492 as_bad (_("GOT already in the symbol table"));
8494 GOT_symbol
= symbol_new (name
, undefined_section
,
8495 &zero_address_frag
, 0);
8505 /* Return non-zero if the indicated VALUE has overflowed the maximum
8506 range expressible by a unsigned number with the indicated number of
8510 unsigned_overflow (valueT value
, unsigned bits
)
8513 if (bits
>= sizeof (valueT
) * 8)
8515 lim
= (valueT
) 1 << bits
;
8516 return (value
>= lim
);
8520 /* Return non-zero if the indicated VALUE has overflowed the maximum
8521 range expressible by an signed number with the indicated number of
8525 signed_overflow (offsetT value
, unsigned bits
)
8528 if (bits
>= sizeof (offsetT
) * 8)
8530 lim
= (offsetT
) 1 << (bits
- 1);
8531 return (value
< -lim
|| value
>= lim
);
8534 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8535 unsigned immediate offset load/store instruction, try to encode it as
8536 an unscaled, 9-bit, signed immediate offset load/store instruction.
8537 Return TRUE if it is successful; otherwise return FALSE.
8539 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8540 in response to the standard LDR/STR mnemonics when the immediate offset is
8541 unambiguous, i.e. when it is negative or unaligned. */
8544 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8547 enum aarch64_op new_op
;
8548 const aarch64_opcode
*new_opcode
;
8550 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8552 switch (instr
->opcode
->op
)
8554 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8555 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8556 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8557 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8558 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8559 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8560 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8561 case OP_STR_POS
: new_op
= OP_STUR
; break;
8562 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8563 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8564 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8565 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8566 default: new_op
= OP_NIL
; break;
8569 if (new_op
== OP_NIL
)
8572 new_opcode
= aarch64_get_opcode (new_op
);
8573 gas_assert (new_opcode
!= NULL
);
8575 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8576 instr
->opcode
->op
, new_opcode
->op
);
8578 aarch64_replace_opcode (instr
, new_opcode
);
8580 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8581 qualifier matching may fail because the out-of-date qualifier will
8582 prevent the operand being updated with a new and correct qualifier. */
8583 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8584 AARCH64_OPND_ADDR_SIMM9
);
8585 gas_assert (idx
== 1);
8586 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8588 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8590 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8597 /* Called by fix_insn to fix a MOV immediate alias instruction.
8599 Operand for a generic move immediate instruction, which is an alias
8600 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8601 a 32-bit/64-bit immediate value into general register. An assembler error
8602 shall result if the immediate cannot be created by a single one of these
8603 instructions. If there is a choice, then to ensure reversability an
8604 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8607 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8609 const aarch64_opcode
*opcode
;
8611 /* Need to check if the destination is SP/ZR. The check has to be done
8612 before any aarch64_replace_opcode. */
8613 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8614 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8616 instr
->operands
[1].imm
.value
= value
;
8617 instr
->operands
[1].skip
= 0;
8621 /* Try the MOVZ alias. */
8622 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8623 aarch64_replace_opcode (instr
, opcode
);
8624 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8625 &instr
->value
, NULL
, NULL
, insn_sequence
))
8627 put_aarch64_insn (buf
, instr
->value
);
8630 /* Try the MOVK alias. */
8631 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8632 aarch64_replace_opcode (instr
, opcode
);
8633 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8634 &instr
->value
, NULL
, NULL
, insn_sequence
))
8636 put_aarch64_insn (buf
, instr
->value
);
8641 if (try_mov_bitmask_p
)
8643 /* Try the ORR alias. */
8644 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8645 aarch64_replace_opcode (instr
, opcode
);
8646 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8647 &instr
->value
, NULL
, NULL
, insn_sequence
))
8649 put_aarch64_insn (buf
, instr
->value
);
8654 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8655 _("immediate cannot be moved by a single instruction"));
8658 /* An instruction operand which is immediate related may have symbol used
8659 in the assembly, e.g.
8662 .set u32, 0x00ffff00
8664 At the time when the assembly instruction is parsed, a referenced symbol,
8665 like 'u32' in the above example may not have been seen; a fixS is created
8666 in such a case and is handled here after symbols have been resolved.
8667 Instruction is fixed up with VALUE using the information in *FIXP plus
8668 extra information in FLAGS.
8670 This function is called by md_apply_fix to fix up instructions that need
8671 a fix-up described above but does not involve any linker-time relocation. */
8674 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8678 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8679 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8680 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8684 /* Now the instruction is about to be fixed-up, so the operand that
8685 was previously marked as 'ignored' needs to be unmarked in order
8686 to get the encoding done properly. */
8687 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8688 new_inst
->operands
[idx
].skip
= 0;
8691 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8695 case AARCH64_OPND_EXCEPTION
:
8696 case AARCH64_OPND_UNDEFINED
:
8697 if (unsigned_overflow (value
, 16))
8698 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8699 _("immediate out of range"));
8700 insn
= get_aarch64_insn (buf
);
8701 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8702 put_aarch64_insn (buf
, insn
);
8705 case AARCH64_OPND_AIMM
:
8706 /* ADD or SUB with immediate.
8707 NOTE this assumes we come here with a add/sub shifted reg encoding
8708 3 322|2222|2 2 2 21111 111111
8709 1 098|7654|3 2 1 09876 543210 98765 43210
8710 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8711 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8712 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8713 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8715 3 322|2222|2 2 221111111111
8716 1 098|7654|3 2 109876543210 98765 43210
8717 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8718 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8719 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8720 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8721 Fields sf Rn Rd are already set. */
8722 insn
= get_aarch64_insn (buf
);
8726 insn
= reencode_addsub_switch_add_sub (insn
);
8730 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8731 && unsigned_overflow (value
, 12))
8733 /* Try to shift the value by 12 to make it fit. */
8734 if (((value
>> 12) << 12) == value
8735 && ! unsigned_overflow (value
, 12 + 12))
8738 insn
|= encode_addsub_imm_shift_amount (1);
8742 if (unsigned_overflow (value
, 12))
8743 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8744 _("immediate out of range"));
8746 insn
|= encode_addsub_imm (value
);
8748 put_aarch64_insn (buf
, insn
);
8751 case AARCH64_OPND_SIMD_IMM
:
8752 case AARCH64_OPND_SIMD_IMM_SFT
:
8753 case AARCH64_OPND_LIMM
:
8754 /* Bit mask immediate. */
8755 gas_assert (new_inst
!= NULL
);
8756 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8757 new_inst
->operands
[idx
].imm
.value
= value
;
8758 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8759 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8760 put_aarch64_insn (buf
, new_inst
->value
);
8762 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8763 _("invalid immediate"));
8766 case AARCH64_OPND_HALF
:
8767 /* 16-bit unsigned immediate. */
8768 if (unsigned_overflow (value
, 16))
8769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8770 _("immediate out of range"));
8771 insn
= get_aarch64_insn (buf
);
8772 insn
|= encode_movw_imm (value
& 0xffff);
8773 put_aarch64_insn (buf
, insn
);
8776 case AARCH64_OPND_IMM_MOV
:
8777 /* Operand for a generic move immediate instruction, which is
8778 an alias instruction that generates a single MOVZ, MOVN or ORR
8779 instruction to loads a 32-bit/64-bit immediate value into general
8780 register. An assembler error shall result if the immediate cannot be
8781 created by a single one of these instructions. If there is a choice,
8782 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8783 and MOVZ or MOVN to ORR. */
8784 gas_assert (new_inst
!= NULL
);
8785 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8788 case AARCH64_OPND_ADDR_SIMM7
:
8789 case AARCH64_OPND_ADDR_SIMM9
:
8790 case AARCH64_OPND_ADDR_SIMM9_2
:
8791 case AARCH64_OPND_ADDR_SIMM10
:
8792 case AARCH64_OPND_ADDR_UIMM12
:
8793 case AARCH64_OPND_ADDR_SIMM11
:
8794 case AARCH64_OPND_ADDR_SIMM13
:
8795 /* Immediate offset in an address. */
8796 insn
= get_aarch64_insn (buf
);
8798 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8799 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8800 || new_inst
->opcode
->operands
[2] == opnd
);
8802 /* Get the index of the address operand. */
8803 if (new_inst
->opcode
->operands
[1] == opnd
)
8804 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8807 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8810 /* Update the resolved offset value. */
8811 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8813 /* Encode/fix-up. */
8814 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8815 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8817 put_aarch64_insn (buf
, new_inst
->value
);
8820 else if (new_inst
->opcode
->iclass
== ldst_pos
8821 && try_to_encode_as_unscaled_ldst (new_inst
))
8823 put_aarch64_insn (buf
, new_inst
->value
);
8827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8828 _("immediate offset out of range"));
8833 as_fatal (_("unhandled operand code %d"), opnd
);
8837 /* Apply a fixup (fixP) to segment data, once it has been determined
8838 by our caller that we have all the info we need to fix it up.
8840 Parameter valP is the pointer to the value of the bits. */
8843 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8845 offsetT value
= *valP
;
8847 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8849 unsigned flags
= fixP
->fx_addnumber
;
8851 DEBUG_TRACE ("\n\n");
8852 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8853 DEBUG_TRACE ("Enter md_apply_fix");
8855 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8857 /* Note whether this will delete the relocation. */
8859 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
8860 && aarch64_force_reloc (fixP
->fx_r_type
) <= 0)
8863 /* Process the relocations. */
8864 switch (fixP
->fx_r_type
)
8866 case BFD_RELOC_NONE
:
8867 /* This will need to go in the object file. */
8872 case BFD_RELOC_8_PCREL
:
8873 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8874 md_number_to_chars (buf
, value
, 1);
8878 case BFD_RELOC_16_PCREL
:
8879 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8880 md_number_to_chars (buf
, value
, 2);
8884 case BFD_RELOC_32_PCREL
:
8885 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8886 md_number_to_chars (buf
, value
, 4);
8890 case BFD_RELOC_64_PCREL
:
8891 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8892 md_number_to_chars (buf
, value
, 8);
8895 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8896 /* We claim that these fixups have been processed here, even if
8897 in fact we generate an error because we do not have a reloc
8898 for them, so tc_gen_reloc() will reject them. */
8900 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8903 _("undefined symbol %s used as an immediate value"),
8904 S_GET_NAME (fixP
->fx_addsy
));
8905 goto apply_fix_return
;
8907 fix_insn (fixP
, flags
, value
);
8910 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8911 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8915 _("pc-relative load offset not word aligned"));
8916 if (signed_overflow (value
, 21))
8917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8918 _("pc-relative load offset out of range"));
8919 insn
= get_aarch64_insn (buf
);
8920 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8921 put_aarch64_insn (buf
, insn
);
8925 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8926 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8928 if (signed_overflow (value
, 21))
8929 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8930 _("pc-relative address offset out of range"));
8931 insn
= get_aarch64_insn (buf
);
8932 insn
|= encode_adr_imm (value
);
8933 put_aarch64_insn (buf
, insn
);
8937 case BFD_RELOC_AARCH64_BRANCH19
:
8938 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8942 _("conditional branch target not word aligned"));
8943 if (signed_overflow (value
, 21))
8944 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8945 _("conditional branch out of range"));
8946 insn
= get_aarch64_insn (buf
);
8947 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8948 put_aarch64_insn (buf
, insn
);
8952 case BFD_RELOC_AARCH64_TSTBR14
:
8953 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8957 _("conditional branch target not word aligned"));
8958 if (signed_overflow (value
, 16))
8959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8960 _("conditional branch out of range"));
8961 insn
= get_aarch64_insn (buf
);
8962 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8963 put_aarch64_insn (buf
, insn
);
8967 case BFD_RELOC_AARCH64_CALL26
:
8968 case BFD_RELOC_AARCH64_JUMP26
:
8969 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8973 _("branch target not word aligned"));
8974 if (signed_overflow (value
, 28))
8975 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8976 _("branch out of range"));
8977 insn
= get_aarch64_insn (buf
);
8978 insn
|= encode_branch_ofs_26 (value
>> 2);
8979 put_aarch64_insn (buf
, insn
);
8983 case BFD_RELOC_AARCH64_MOVW_G0
:
8984 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8985 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8986 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8987 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8988 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8991 case BFD_RELOC_AARCH64_MOVW_G1
:
8992 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8993 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8994 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8995 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8996 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8999 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
9001 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9002 /* Should always be exported to object file, see
9003 aarch64_force_relocation(). */
9004 gas_assert (!fixP
->fx_done
);
9005 gas_assert (seg
->use_rela_p
);
9007 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9009 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9010 /* Should always be exported to object file, see
9011 aarch64_force_relocation(). */
9012 gas_assert (!fixP
->fx_done
);
9013 gas_assert (seg
->use_rela_p
);
9015 case BFD_RELOC_AARCH64_MOVW_G2
:
9016 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
9017 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9018 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9019 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
9022 case BFD_RELOC_AARCH64_MOVW_G3
:
9023 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
9026 if (fixP
->fx_done
|| !seg
->use_rela_p
)
9028 insn
= get_aarch64_insn (buf
);
9032 /* REL signed addend must fit in 16 bits */
9033 if (signed_overflow (value
, 16))
9034 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9035 _("offset out of range"));
9039 /* Check for overflow and scale. */
9040 switch (fixP
->fx_r_type
)
9042 case BFD_RELOC_AARCH64_MOVW_G0
:
9043 case BFD_RELOC_AARCH64_MOVW_G1
:
9044 case BFD_RELOC_AARCH64_MOVW_G2
:
9045 case BFD_RELOC_AARCH64_MOVW_G3
:
9046 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9047 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9048 if (unsigned_overflow (value
, scale
+ 16))
9049 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9050 _("unsigned value out of range"));
9052 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9053 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9054 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9055 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9056 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9057 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9058 /* NOTE: We can only come here with movz or movn. */
9059 if (signed_overflow (value
, scale
+ 16))
9060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9061 _("signed value out of range"));
9064 /* Force use of MOVN. */
9066 insn
= reencode_movzn_to_movn (insn
);
9070 /* Force use of MOVZ. */
9071 insn
= reencode_movzn_to_movz (insn
);
9075 /* Unchecked relocations. */
9081 /* Insert value into MOVN/MOVZ/MOVK instruction. */
9082 insn
|= encode_movw_imm (value
& 0xffff);
9084 put_aarch64_insn (buf
, insn
);
9088 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9089 fixP
->fx_r_type
= (ilp32_p
9090 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9091 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9092 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9093 /* Should always be exported to object file, see
9094 aarch64_force_relocation(). */
9095 gas_assert (!fixP
->fx_done
);
9096 gas_assert (seg
->use_rela_p
);
9099 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9100 fixP
->fx_r_type
= (ilp32_p
9101 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9102 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9103 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9104 /* Should always be exported to object file, see
9105 aarch64_force_relocation(). */
9106 gas_assert (!fixP
->fx_done
);
9107 gas_assert (seg
->use_rela_p
);
9110 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9111 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9112 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9113 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9114 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9115 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9116 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9117 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9118 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9119 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9120 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9121 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9122 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9123 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9124 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9125 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9126 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9127 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9128 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9129 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9130 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9131 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9132 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9133 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9134 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9135 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9136 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9137 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9138 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9139 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9140 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9141 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9142 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9143 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9144 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9145 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9146 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9147 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9148 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9149 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9150 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9151 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9152 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9153 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9154 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9155 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9156 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9157 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9158 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9159 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9160 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9161 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9162 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9163 /* Should always be exported to object file, see
9164 aarch64_force_relocation(). */
9165 gas_assert (!fixP
->fx_done
);
9166 gas_assert (seg
->use_rela_p
);
9169 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9170 /* Should always be exported to object file, see
9171 aarch64_force_relocation(). */
9172 fixP
->fx_r_type
= (ilp32_p
9173 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9174 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9175 gas_assert (!fixP
->fx_done
);
9176 gas_assert (seg
->use_rela_p
);
9179 case BFD_RELOC_AARCH64_ADD_LO12
:
9180 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9181 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9182 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9183 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9184 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9185 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9186 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9187 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9188 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9189 case BFD_RELOC_AARCH64_LDST128_LO12
:
9190 case BFD_RELOC_AARCH64_LDST16_LO12
:
9191 case BFD_RELOC_AARCH64_LDST32_LO12
:
9192 case BFD_RELOC_AARCH64_LDST64_LO12
:
9193 case BFD_RELOC_AARCH64_LDST8_LO12
:
9194 /* Should always be exported to object file, see
9195 aarch64_force_relocation(). */
9196 gas_assert (!fixP
->fx_done
);
9197 gas_assert (seg
->use_rela_p
);
9200 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9201 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9202 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9205 case BFD_RELOC_UNUSED
:
9206 /* An error will already have been reported. */
9210 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9211 _("unexpected %s fixup"),
9212 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9217 /* Free the allocated the struct aarch64_inst.
9218 N.B. currently there are very limited number of fix-up types actually use
9219 this field, so the impact on the performance should be minimal . */
9220 free (fixP
->tc_fix_data
.inst
);
9225 /* Translate internal representation of relocation info to BFD target
9229 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9232 bfd_reloc_code_real_type code
;
9234 reloc
= XNEW (arelent
);
9236 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9237 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9238 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9242 if (section
->use_rela_p
)
9243 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9245 fixp
->fx_offset
= reloc
->address
;
9247 reloc
->addend
= fixp
->fx_offset
;
9249 code
= fixp
->fx_r_type
;
9254 code
= BFD_RELOC_16_PCREL
;
9259 code
= BFD_RELOC_32_PCREL
;
9264 code
= BFD_RELOC_64_PCREL
;
9271 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9272 if (reloc
->howto
== NULL
)
9274 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9276 ("cannot represent %s relocation in this object file format"),
9277 bfd_get_reloc_code_name (code
));
9284 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9287 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9289 bfd_reloc_code_real_type type
;
9293 FIXME: @@ Should look at CPU word size. */
9300 type
= BFD_RELOC_16
;
9303 type
= BFD_RELOC_32
;
9306 type
= BFD_RELOC_64
;
9309 as_bad (_("cannot do %u-byte relocation"), size
);
9310 type
= BFD_RELOC_UNUSED
;
9314 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9317 /* Implement md_after_parse_args. This is the earliest time we need to decide
9318 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9321 aarch64_after_parse_args (void)
9323 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9327 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9328 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9329 aarch64_abi
= AARCH64_ABI_ILP32
;
9331 aarch64_abi
= AARCH64_ABI_LP64
;
9333 aarch64_abi
= AARCH64_ABI_LLP64
;
9339 elf64_aarch64_target_format (void)
9342 /* FIXME: What to do for ilp32_p ? */
9343 if (target_big_endian
)
9344 return "elf64-bigaarch64-cloudabi";
9346 return "elf64-littleaarch64-cloudabi";
9348 if (target_big_endian
)
9349 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9351 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9356 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9358 elf_frob_symbol (symp
, puntp
);
9360 #elif defined OBJ_COFF
9362 coff_aarch64_target_format (void)
9364 return "pe-aarch64-little";
9368 /* MD interface: Finalization. */
9370 /* A good place to do this, although this was probably not intended
9371 for this kind of use. We need to dump the literal pool before
9372 references are made to a null symbol pointer. */
9375 aarch64_cleanup (void)
9379 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9381 /* Put it at the end of the relevant section. */
9382 subseg_set (pool
->section
, pool
->sub_section
);
9388 /* Remove any excess mapping symbols generated for alignment frags in
9389 SEC. We may have created a mapping symbol before a zero byte
9390 alignment; remove it if there's a mapping symbol after the
9393 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9394 void *dummy ATTRIBUTE_UNUSED
)
9396 segment_info_type
*seginfo
= seg_info (sec
);
9399 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9402 for (fragp
= seginfo
->frchainP
->frch_root
;
9403 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9405 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9406 fragS
*next
= fragp
->fr_next
;
9408 /* Variable-sized frags have been converted to fixed size by
9409 this point. But if this was variable-sized to start with,
9410 there will be a fixed-size frag after it. So don't handle
9412 if (sym
== NULL
|| next
== NULL
)
9415 if (S_GET_VALUE (sym
) < next
->fr_address
)
9416 /* Not at the end of this frag. */
9418 know (S_GET_VALUE (sym
) == next
->fr_address
);
9422 if (next
->tc_frag_data
.first_map
!= NULL
)
9424 /* Next frag starts with a mapping symbol. Discard this
9426 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9430 if (next
->fr_next
== NULL
)
9432 /* This mapping symbol is at the end of the section. Discard
9434 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9435 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9439 /* As long as we have empty frags without any mapping symbols,
9441 /* If the next frag is non-empty and does not start with a
9442 mapping symbol, then this mapping symbol is required. */
9443 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9446 next
= next
->fr_next
;
9448 while (next
!= NULL
);
9453 /* Adjust the symbol table. */
9456 aarch64_adjust_symtab (void)
9459 /* Remove any overlapping mapping symbols generated by alignment frags. */
9460 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9461 /* Now do generic ELF adjustments. */
9462 elf_adjust_symtab ();
9467 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9469 str_hash_insert (table
, key
, value
, 0);
9473 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9475 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9476 checked_hash_insert (table
, key
, value
);
9480 fill_instruction_hash_table (void)
9482 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9484 while (opcode
->name
!= NULL
)
9486 templates
*templ
, *new_templ
;
9487 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9489 new_templ
= XNEW (templates
);
9490 new_templ
->opcode
= opcode
;
9491 new_templ
->next
= NULL
;
9494 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9497 new_templ
->next
= templ
->next
;
9498 templ
->next
= new_templ
;
9505 convert_to_upper (char *dst
, const char *src
, size_t num
)
9508 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9509 *dst
= TOUPPER (*src
);
9513 /* Assume STR point to a lower-case string, allocate, convert and return
9514 the corresponding upper-case string. */
9515 static inline const char*
9516 get_upper_str (const char *str
)
9519 size_t len
= strlen (str
);
9520 ret
= XNEWVEC (char, len
+ 1);
9521 convert_to_upper (ret
, str
, len
);
9525 /* MD interface: Initialization. */
9533 aarch64_ops_hsh
= str_htab_create ();
9534 aarch64_cond_hsh
= str_htab_create ();
9535 aarch64_shift_hsh
= str_htab_create ();
9536 aarch64_sys_regs_hsh
= str_htab_create ();
9537 aarch64_pstatefield_hsh
= str_htab_create ();
9538 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9539 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9540 aarch64_sys_regs_at_hsh
= str_htab_create ();
9541 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9542 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9543 aarch64_reg_hsh
= str_htab_create ();
9544 aarch64_barrier_opt_hsh
= str_htab_create ();
9545 aarch64_nzcv_hsh
= str_htab_create ();
9546 aarch64_pldop_hsh
= str_htab_create ();
9547 aarch64_hint_opt_hsh
= str_htab_create ();
9549 fill_instruction_hash_table ();
9551 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9552 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9553 (void *) (aarch64_sys_regs
+ i
));
9555 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9556 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9557 aarch64_pstatefields
[i
].name
,
9558 (void *) (aarch64_pstatefields
+ i
));
9560 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9561 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9562 aarch64_sys_regs_ic
[i
].name
,
9563 (void *) (aarch64_sys_regs_ic
+ i
));
9565 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9566 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9567 aarch64_sys_regs_dc
[i
].name
,
9568 (void *) (aarch64_sys_regs_dc
+ i
));
9570 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9571 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9572 aarch64_sys_regs_at
[i
].name
,
9573 (void *) (aarch64_sys_regs_at
+ i
));
9575 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9576 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9577 aarch64_sys_regs_tlbi
[i
].name
,
9578 (void *) (aarch64_sys_regs_tlbi
+ i
));
9580 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9581 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9582 aarch64_sys_regs_sr
[i
].name
,
9583 (void *) (aarch64_sys_regs_sr
+ i
));
9585 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9586 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9587 (void *) (reg_names
+ i
));
9589 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9590 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9591 (void *) (nzcv_names
+ i
));
9593 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9595 const char *name
= aarch64_operand_modifiers
[i
].name
;
9596 checked_hash_insert (aarch64_shift_hsh
, name
,
9597 (void *) (aarch64_operand_modifiers
+ i
));
9598 /* Also hash the name in the upper case. */
9599 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9600 (void *) (aarch64_operand_modifiers
+ i
));
9603 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9606 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9607 the same condition code. */
9608 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9610 const char *name
= aarch64_conds
[i
].names
[j
];
9613 checked_hash_insert (aarch64_cond_hsh
, name
,
9614 (void *) (aarch64_conds
+ i
));
9615 /* Also hash the name in the upper case. */
9616 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9617 (void *) (aarch64_conds
+ i
));
9621 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9623 const char *name
= aarch64_barrier_options
[i
].name
;
9624 /* Skip xx00 - the unallocated values of option. */
9627 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9628 (void *) (aarch64_barrier_options
+ i
));
9629 /* Also hash the name in the upper case. */
9630 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9631 (void *) (aarch64_barrier_options
+ i
));
9634 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
9636 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
9637 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9638 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9639 /* Also hash the name in the upper case. */
9640 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9641 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9644 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9646 const char* name
= aarch64_prfops
[i
].name
;
9647 /* Skip the unallocated hint encodings. */
9650 checked_hash_insert (aarch64_pldop_hsh
, name
,
9651 (void *) (aarch64_prfops
+ i
));
9652 /* Also hash the name in the upper case. */
9653 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9654 (void *) (aarch64_prfops
+ i
));
9657 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9659 const char* name
= aarch64_hint_options
[i
].name
;
9660 const char* upper_name
= get_upper_str(name
);
9662 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9663 (void *) (aarch64_hint_options
+ i
));
9665 /* Also hash the name in the upper case if not the same. */
9666 if (strcmp (name
, upper_name
) != 0)
9667 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9668 (void *) (aarch64_hint_options
+ i
));
9671 /* Set the cpu variant based on the command-line options. */
9673 mcpu_cpu_opt
= march_cpu_opt
;
9676 mcpu_cpu_opt
= &cpu_default
;
9678 cpu_variant
= *mcpu_cpu_opt
;
9680 /* Record the CPU type. */
9682 mach
= bfd_mach_aarch64_ilp32
;
9684 mach
= bfd_mach_aarch64_llp64
;
9686 mach
= bfd_mach_aarch64
;
9688 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9691 /* Command line processing. */
9693 const char *md_shortopts
= "m:";
9695 #ifdef AARCH64_BI_ENDIAN
9696 #define OPTION_EB (OPTION_MD_BASE + 0)
9697 #define OPTION_EL (OPTION_MD_BASE + 1)
9699 #if TARGET_BYTES_BIG_ENDIAN
9700 #define OPTION_EB (OPTION_MD_BASE + 0)
9702 #define OPTION_EL (OPTION_MD_BASE + 1)
9706 struct option md_longopts
[] = {
9708 {"EB", no_argument
, NULL
, OPTION_EB
},
9711 {"EL", no_argument
, NULL
, OPTION_EL
},
9713 {NULL
, no_argument
, NULL
, 0}
9716 size_t md_longopts_size
= sizeof (md_longopts
);
9718 struct aarch64_option_table
9720 const char *option
; /* Option name to match. */
9721 const char *help
; /* Help information. */
9722 int *var
; /* Variable to change. */
9723 int value
; /* What to change it to. */
9724 char *deprecated
; /* If non-null, print this message. */
9727 static struct aarch64_option_table aarch64_opts
[] = {
9728 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9729 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9731 #ifdef DEBUG_AARCH64
9732 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9733 #endif /* DEBUG_AARCH64 */
9734 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9736 {"mno-verbose-error", N_("do not output verbose error messages"),
9737 &verbose_error_p
, 0, NULL
},
9738 {NULL
, NULL
, NULL
, 0, NULL
}
9741 struct aarch64_cpu_option_table
9744 const aarch64_feature_set value
;
9745 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9747 const char *canonical_name
;
9750 /* This list should, at a minimum, contain all the cpu names
9751 recognized by GCC. */
9752 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9753 {"all", AARCH64_ANY
, NULL
},
9754 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9755 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9756 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9757 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9758 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9759 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9760 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9761 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9762 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9763 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9764 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9765 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9766 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9767 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9769 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9770 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9772 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9773 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9775 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9776 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9777 | AARCH64_FEATURE_DOTPROD
9778 | AARCH64_FEATURE_SSBS
),
9780 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9781 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9782 | AARCH64_FEATURE_DOTPROD
9783 | AARCH64_FEATURE_SSBS
),
9785 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9786 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9787 | AARCH64_FEATURE_DOTPROD
9788 | AARCH64_FEATURE_SSBS
),
9790 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9791 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9792 | AARCH64_FEATURE_DOTPROD
9793 | AARCH64_FEATURE_SSBS
),
9795 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9797 | AARCH64_FEATURE_RCPC
9798 | AARCH64_FEATURE_DOTPROD
9799 | AARCH64_FEATURE_SSBS
9800 | AARCH64_FEATURE_PROFILE
),
9802 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9804 | AARCH64_FEATURE_RCPC
9805 | AARCH64_FEATURE_DOTPROD
9806 | AARCH64_FEATURE_SSBS
9807 | AARCH64_FEATURE_PROFILE
),
9809 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9810 AARCH64_FEATURE_DOTPROD
9811 | AARCH64_FEATURE_F16
9812 | AARCH64_FEATURE_FLAGM
9813 | AARCH64_FEATURE_PAC
9814 | AARCH64_FEATURE_PROFILE
9815 | AARCH64_FEATURE_RCPC
9816 | AARCH64_FEATURE_SSBS
),
9818 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9819 AARCH64_FEATURE_BFLOAT16
9820 | AARCH64_FEATURE_I8MM
9821 | AARCH64_FEATURE_MEMTAG
9822 | AARCH64_FEATURE_SVE2_BITPERM
),
9824 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9825 AARCH64_FEATURE_BFLOAT16
9826 | AARCH64_FEATURE_I8MM
9827 | AARCH64_FEATURE_MEMTAG
9828 | AARCH64_FEATURE_SVE2_BITPERM
),
9830 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9831 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9832 | AARCH64_FEATURE_DOTPROD
9833 | AARCH64_FEATURE_PROFILE
),
9835 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9836 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9837 "Samsung Exynos M1"},
9838 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9839 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9840 | AARCH64_FEATURE_RDMA
),
9842 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9843 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9844 | AARCH64_FEATURE_DOTPROD
9845 | AARCH64_FEATURE_SSBS
),
9847 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9848 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9849 | AARCH64_FEATURE_DOTPROD
9850 | AARCH64_FEATURE_PROFILE
),
9852 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9853 AARCH64_FEATURE_BFLOAT16
9854 | AARCH64_FEATURE_I8MM
9855 | AARCH64_FEATURE_F16
9856 | AARCH64_FEATURE_SVE
9857 | AARCH64_FEATURE_SVE2
9858 | AARCH64_FEATURE_SVE2_BITPERM
9859 | AARCH64_FEATURE_MEMTAG
9860 | AARCH64_FEATURE_RNG
),
9862 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9863 AARCH64_FEATURE_PROFILE
9864 | AARCH64_FEATURE_CVADP
9865 | AARCH64_FEATURE_SVE
9866 | AARCH64_FEATURE_SSBS
9867 | AARCH64_FEATURE_RNG
9868 | AARCH64_FEATURE_F16
9869 | AARCH64_FEATURE_BFLOAT16
9870 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9871 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9872 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9873 | AARCH64_FEATURE_RDMA
),
9874 "Qualcomm QDF24XX"},
9875 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9876 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9877 "Qualcomm Saphira"},
9878 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9879 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9881 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9882 AARCH64_FEATURE_CRYPTO
),
9884 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9885 in earlier releases and is superseded by 'xgene1' in all
9887 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9888 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9889 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9890 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9891 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9892 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9894 | AARCH64_FEATURE_RCPC
9895 | AARCH64_FEATURE_DOTPROD
9896 | AARCH64_FEATURE_SSBS
9897 | AARCH64_FEATURE_PROFILE
),
9899 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9900 AARCH64_FEATURE_BFLOAT16
9901 | AARCH64_FEATURE_I8MM
9902 | AARCH64_FEATURE_MEMTAG
9903 | AARCH64_FEATURE_SVE2_BITPERM
),
9905 {"generic", AARCH64_ARCH_V8
, NULL
},
9907 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9910 struct aarch64_arch_option_table
9913 const aarch64_feature_set value
;
9916 /* This list should, at a minimum, contain all the architecture names
9917 recognized by GCC. */
9918 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9919 {"all", AARCH64_ANY
},
9920 {"armv8-a", AARCH64_ARCH_V8
},
9921 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9922 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9923 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9924 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9925 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9926 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9927 {"armv8.7-a", AARCH64_ARCH_V8_7
},
9928 {"armv8.8-a", AARCH64_ARCH_V8_8
},
9929 {"armv8-r", AARCH64_ARCH_V8_R
},
9930 {"armv9-a", AARCH64_ARCH_V9
},
9931 {"armv9.1-a", AARCH64_ARCH_V9_1
},
9932 {"armv9.2-a", AARCH64_ARCH_V9_2
},
9933 {"armv9.3-a", AARCH64_ARCH_V9_3
},
9934 {NULL
, AARCH64_ARCH_NONE
}
9937 /* ISA extensions. */
9938 struct aarch64_option_cpu_value_table
9941 const aarch64_feature_set value
;
9942 const aarch64_feature_set require
; /* Feature dependencies. */
9945 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9946 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9948 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9949 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9950 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
9952 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
9954 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9955 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9956 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9958 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9960 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9962 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9963 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9964 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9965 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9966 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9967 AARCH64_FEATURE (AARCH64_FEATURE_FP
9968 | AARCH64_FEATURE_F16
, 0)},
9969 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9971 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9972 AARCH64_FEATURE (AARCH64_FEATURE_F16
9973 | AARCH64_FEATURE_SIMD
9974 | AARCH64_FEATURE_COMPNUM
, 0)},
9975 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9977 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9978 AARCH64_FEATURE (AARCH64_FEATURE_F16
9979 | AARCH64_FEATURE_SIMD
, 0)},
9980 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9982 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9984 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9986 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9988 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9990 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9992 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9994 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9995 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9996 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9998 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
10000 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
10001 AARCH64_ARCH_NONE
},
10002 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
10003 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10004 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
10005 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10006 | AARCH64_FEATURE_SM4
, 0)},
10007 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
10008 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10009 | AARCH64_FEATURE_AES
, 0)},
10010 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
10011 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10012 | AARCH64_FEATURE_SHA3
, 0)},
10013 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
10014 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
10015 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
10016 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
10017 | AARCH64_FEATURE_BFLOAT16
, 0)},
10018 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64
, 0),
10019 AARCH64_FEATURE (AARCH64_FEATURE_SME
10020 | AARCH64_FEATURE_SVE2
10021 | AARCH64_FEATURE_BFLOAT16
, 0)},
10022 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I64
, 0),
10023 AARCH64_FEATURE (AARCH64_FEATURE_SME
10024 | AARCH64_FEATURE_SVE2
10025 | AARCH64_FEATURE_BFLOAT16
, 0)},
10026 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
10027 AARCH64_ARCH_NONE
},
10028 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
10029 AARCH64_ARCH_NONE
},
10030 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
10031 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10032 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
10033 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
10034 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
10035 AARCH64_ARCH_NONE
},
10036 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
10037 AARCH64_ARCH_NONE
},
10038 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
10039 AARCH64_ARCH_NONE
},
10040 {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS
, 0),
10041 AARCH64_ARCH_NONE
},
10042 {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC
, 0),
10043 AARCH64_ARCH_NONE
},
10044 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
10047 struct aarch64_long_option_table
10049 const char *option
; /* Substring to match. */
10050 const char *help
; /* Help information. */
10051 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
10052 char *deprecated
; /* If non-null, print this message. */
10055 /* Transitive closure of features depending on set. */
10056 static aarch64_feature_set
10057 aarch64_feature_disable_set (aarch64_feature_set set
)
10059 const struct aarch64_option_cpu_value_table
*opt
;
10060 aarch64_feature_set prev
= 0;
10062 while (prev
!= set
) {
10064 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10065 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10066 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10071 /* Transitive closure of dependencies of set. */
10072 static aarch64_feature_set
10073 aarch64_feature_enable_set (aarch64_feature_set set
)
10075 const struct aarch64_option_cpu_value_table
*opt
;
10076 aarch64_feature_set prev
= 0;
10078 while (prev
!= set
) {
10080 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10081 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10082 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10088 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10091 /* We insist on extensions being added before being removed. We achieve
10092 this by using the ADDING_VALUE variable to indicate whether we are
10093 adding an extension (1) or removing it (0) and only allowing it to
10094 change in the order -1 -> 1 -> 0. */
10095 int adding_value
= -1;
10096 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10098 /* Copy the feature set, so that we can modify it. */
10099 *ext_set
= **opt_p
;
10102 while (str
!= NULL
&& *str
!= 0)
10104 const struct aarch64_option_cpu_value_table
*opt
;
10105 const char *ext
= NULL
;
10112 as_bad (_("invalid architectural extension"));
10116 ext
= strchr (++str
, '+');
10120 optlen
= ext
- str
;
10122 optlen
= strlen (str
);
10124 if (optlen
>= 2 && startswith (str
, "no"))
10126 if (adding_value
!= 0)
10131 else if (optlen
> 0)
10133 if (adding_value
== -1)
10135 else if (adding_value
!= 1)
10137 as_bad (_("must specify extensions to add before specifying "
10138 "those to remove"));
10145 as_bad (_("missing architectural extension"));
10149 gas_assert (adding_value
!= -1);
10151 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10152 if (strncmp (opt
->name
, str
, optlen
) == 0)
10154 aarch64_feature_set set
;
10156 /* Add or remove the extension. */
10159 set
= aarch64_feature_enable_set (opt
->value
);
10160 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10164 set
= aarch64_feature_disable_set (opt
->value
);
10165 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10170 if (opt
->name
== NULL
)
10172 as_bad (_("unknown architectural extension `%s'"), str
);
10183 aarch64_parse_cpu (const char *str
)
10185 const struct aarch64_cpu_option_table
*opt
;
10186 const char *ext
= strchr (str
, '+');
10190 optlen
= ext
- str
;
10192 optlen
= strlen (str
);
10196 as_bad (_("missing cpu name `%s'"), str
);
10200 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10201 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10203 mcpu_cpu_opt
= &opt
->value
;
10205 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10210 as_bad (_("unknown cpu `%s'"), str
);
10215 aarch64_parse_arch (const char *str
)
10217 const struct aarch64_arch_option_table
*opt
;
10218 const char *ext
= strchr (str
, '+');
10222 optlen
= ext
- str
;
10224 optlen
= strlen (str
);
10228 as_bad (_("missing architecture name `%s'"), str
);
10232 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10233 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10235 march_cpu_opt
= &opt
->value
;
10237 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10242 as_bad (_("unknown architecture `%s'\n"), str
);
10247 struct aarch64_option_abi_value_table
10250 enum aarch64_abi_type value
;
10253 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10255 {"ilp32", AARCH64_ABI_ILP32
},
10256 {"lp64", AARCH64_ABI_LP64
},
10258 {"llp64", AARCH64_ABI_LLP64
},
10263 aarch64_parse_abi (const char *str
)
10267 if (str
[0] == '\0')
10269 as_bad (_("missing abi name `%s'"), str
);
10273 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10274 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10276 aarch64_abi
= aarch64_abis
[i
].value
;
10280 as_bad (_("unknown abi `%s'\n"), str
);
10284 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10285 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10286 aarch64_parse_abi
, NULL
},
10287 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10288 aarch64_parse_cpu
, NULL
},
10289 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10290 aarch64_parse_arch
, NULL
},
10291 {NULL
, NULL
, 0, NULL
}
10295 md_parse_option (int c
, const char *arg
)
10297 struct aarch64_option_table
*opt
;
10298 struct aarch64_long_option_table
*lopt
;
10304 target_big_endian
= 1;
10310 target_big_endian
= 0;
10315 /* Listing option. Just ignore these, we don't support additional
10320 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10322 if (c
== opt
->option
[0]
10323 && ((arg
== NULL
&& opt
->option
[1] == 0)
10324 || streq (arg
, opt
->option
+ 1)))
10326 /* If the option is deprecated, tell the user. */
10327 if (opt
->deprecated
!= NULL
)
10328 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10329 arg
? arg
: "", _(opt
->deprecated
));
10331 if (opt
->var
!= NULL
)
10332 *opt
->var
= opt
->value
;
10338 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10340 /* These options are expected to have an argument. */
10341 if (c
== lopt
->option
[0]
10343 && startswith (arg
, lopt
->option
+ 1))
10345 /* If the option is deprecated, tell the user. */
10346 if (lopt
->deprecated
!= NULL
)
10347 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10348 _(lopt
->deprecated
));
10350 /* Call the sup-option parser. */
10351 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10362 md_show_usage (FILE * fp
)
10364 struct aarch64_option_table
*opt
;
10365 struct aarch64_long_option_table
*lopt
;
10367 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10369 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10370 if (opt
->help
!= NULL
)
10371 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10373 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10374 if (lopt
->help
!= NULL
)
10375 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10379 -EB assemble code for a big-endian cpu\n"));
10384 -EL assemble code for a little-endian cpu\n"));
10388 /* Parse a .cpu directive. */
10391 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10393 const struct aarch64_cpu_option_table
*opt
;
10399 name
= input_line_pointer
;
10400 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10401 saved_char
= *input_line_pointer
;
10402 *input_line_pointer
= 0;
10404 ext
= strchr (name
, '+');
10407 optlen
= ext
- name
;
10409 optlen
= strlen (name
);
10411 /* Skip the first "all" entry. */
10412 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10413 if (strlen (opt
->name
) == optlen
10414 && strncmp (name
, opt
->name
, optlen
) == 0)
10416 mcpu_cpu_opt
= &opt
->value
;
10418 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10421 cpu_variant
= *mcpu_cpu_opt
;
10423 *input_line_pointer
= saved_char
;
10424 demand_empty_rest_of_line ();
10427 as_bad (_("unknown cpu `%s'"), name
);
10428 *input_line_pointer
= saved_char
;
10429 ignore_rest_of_line ();
10433 /* Parse a .arch directive. */
10436 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10438 const struct aarch64_arch_option_table
*opt
;
10444 name
= input_line_pointer
;
10445 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10446 saved_char
= *input_line_pointer
;
10447 *input_line_pointer
= 0;
10449 ext
= strchr (name
, '+');
10452 optlen
= ext
- name
;
10454 optlen
= strlen (name
);
10456 /* Skip the first "all" entry. */
10457 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10458 if (strlen (opt
->name
) == optlen
10459 && strncmp (name
, opt
->name
, optlen
) == 0)
10461 mcpu_cpu_opt
= &opt
->value
;
10463 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10466 cpu_variant
= *mcpu_cpu_opt
;
10468 *input_line_pointer
= saved_char
;
10469 demand_empty_rest_of_line ();
10473 as_bad (_("unknown architecture `%s'\n"), name
);
10474 *input_line_pointer
= saved_char
;
10475 ignore_rest_of_line ();
10478 /* Parse a .arch_extension directive. */
10481 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10484 char *ext
= input_line_pointer
;
10486 input_line_pointer
= find_end_of_line (input_line_pointer
, flag_m68k_mri
);
10487 saved_char
= *input_line_pointer
;
10488 *input_line_pointer
= 0;
10490 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10493 cpu_variant
= *mcpu_cpu_opt
;
10495 *input_line_pointer
= saved_char
;
10496 demand_empty_rest_of_line ();
10499 /* Copy symbol information. */
10502 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10504 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10508 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10509 This is needed so AArch64 specific st_other values can be independently
10510 specified for an IFUNC resolver (that is called by the dynamic linker)
10511 and the symbol it resolves (aliased to the resolver). In particular,
10512 if a function symbol has special st_other value set via directives,
10513 then attaching an IFUNC resolver to that symbol should not override
10514 the st_other setting. Requiring the directive on the IFUNC resolver
10515 symbol would be unexpected and problematic in C code, where the two
10516 symbols appear as two independent function declarations. */
10519 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10521 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10522 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10523 /* If size is unset, copy size from src. Because we don't track whether
10524 .size has been used, we can't differentiate .size dest, 0 from the case
10525 where dest's size is unset. */
10526 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
10530 destelf
->size
= XNEW (expressionS
);
10531 *destelf
->size
= *srcelf
->size
;
10533 S_SET_SIZE (dest
, S_GET_SIZE (src
));