projects / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
x86: permit parenthesized expressions again as addressing scale factor
[binutils-gdb.git] / gas / config / tc-arc.c
1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2021 Free Software Foundation, Inc.
3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include "as.h"
24 #include "subsegs.h"
25 #include "dwarf2dbg.h"
26 #include "dw2gencfi.h"
27 #include "safe-ctype.h"
28
29 #include "opcode/arc.h"
30 #include "opcode/arc-attrs.h"
31 #include "elf/arc.h"
32 #include "../opcodes/arc-ext.h"
33
34 /* Defines section. */
35
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
39
40 #ifdef DEBUG
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
42 #else
43 # define pr_debug(fmt, args...)
44 #endif
45
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
50
51 #ifndef TARGET_WITH_CPU
52 #define TARGET_WITH_CPU "arc700"
53 #endif /* TARGET_WITH_CPU */
54
55 #define ARC_GET_FLAG(s) (*symbol_get_tc (s))
56 #define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
57 #define streq(a, b) (strcmp (a, b) == 0)
58
59 /* Enum used to enumerate the relaxable ins operands. */
60 enum rlx_operand_type
61 {
62 EMPTY = 0,
63 REGISTER,
64 REGISTER_S, /* Register for short instruction(s). */
65 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
66 REGISTER_DUP, /* Duplication of previous operand of type register. */
67 IMMEDIATE,
68 BRACKET
69 };
70
71 enum arc_rlx_types
72 {
73 ARC_RLX_NONE = 0,
74 ARC_RLX_BL_S,
75 ARC_RLX_BL,
76 ARC_RLX_B_S,
77 ARC_RLX_B,
78 ARC_RLX_ADD_U3,
79 ARC_RLX_ADD_U6,
80 ARC_RLX_ADD_LIMM,
81 ARC_RLX_LD_U7,
82 ARC_RLX_LD_S9,
83 ARC_RLX_LD_LIMM,
84 ARC_RLX_MOV_U8,
85 ARC_RLX_MOV_S12,
86 ARC_RLX_MOV_LIMM,
87 ARC_RLX_SUB_U3,
88 ARC_RLX_SUB_U6,
89 ARC_RLX_SUB_LIMM,
90 ARC_RLX_MPY_U6,
91 ARC_RLX_MPY_LIMM,
92 ARC_RLX_MOV_RU6,
93 ARC_RLX_MOV_RLIMM,
94 ARC_RLX_ADD_RRU6,
95 ARC_RLX_ADD_RRLIMM,
96 };
97
98 /* Macros section. */
99
100 #define regno(x) ((x) & 0x3F)
101 #define is_ir_num(x) (((x) & ~0x3F) == 0)
102 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
103 #define is_spfp_p(op) (((sc) == SPX))
104 #define is_dpfp_p(op) (((sc) == DPX))
105 #define is_fpuda_p(op) (((sc) == DPA))
106 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
107 || (op)->insn_class == JUMP \
108 || (op)->insn_class == BRCC \
109 || (op)->insn_class == BBIT0 \
110 || (op)->insn_class == BBIT1 \
111 || (op)->insn_class == BI \
112 || (op)->insn_class == EI \
113 || (op)->insn_class == ENTER \
114 || (op)->insn_class == JLI \
115 || (op)->insn_class == LOOP \
116 || (op)->insn_class == LEAVE \
117 ))
118 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
119 #define is_nps400_p(op) (((sc) == NPS400))
120
121 /* Generic assembler global variables which must be defined by all
122 targets. */
123
124 /* Characters which always start a comment. */
125 const char comment_chars[] = "#;";
126
127 /* Characters which start a comment at the beginning of a line. */
128 const char line_comment_chars[] = "#";
129
130 /* Characters which may be used to separate multiple commands on a
131 single line. */
132 const char line_separator_chars[] = "`";
133
134 /* Characters which are used to indicate an exponent in a floating
135 point number. */
136 const char EXP_CHARS[] = "eE";
137
138 /* Chars that mean this number is a floating point constant
139 As in 0f12.456 or 0d1.2345e12. */
140 const char FLT_CHARS[] = "rRsSfFdD";
141
142 /* Byte order. */
143 extern int target_big_endian;
144 const char *arc_target_format = DEFAULT_TARGET_FORMAT;
145 static int byte_order = DEFAULT_BYTE_ORDER;
146
147 /* Arc extension section. */
148 static segT arcext_section;
149
150 /* By default relaxation is disabled. */
151 static int relaxation_state = 0;
152
153 extern int arc_get_mach (char *);
154
155 /* Forward declarations. */
156 static void arc_lcomm (int);
157 static void arc_option (int);
158 static void arc_extra_reloc (int);
159 static void arc_extinsn (int);
160 static void arc_extcorereg (int);
161 static void arc_attribute (int);
162
163 const pseudo_typeS md_pseudo_table[] =
164 {
165 /* Make sure that .word is 32 bits. */
166 { "word", cons, 4 },
167
168 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
169 { "lcomm", arc_lcomm, 0 },
170 { "lcommon", arc_lcomm, 0 },
171 { "cpu", arc_option, 0 },
172
173 { "arc_attribute", arc_attribute, 0 },
174 { "extinstruction", arc_extinsn, 0 },
175 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
176 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
177 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
178
179 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
180 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
181
182 { NULL, NULL, 0 }
183 };
184
185 const char *md_shortopts = "";
186
187 enum options
188 {
189 OPTION_EB = OPTION_MD_BASE,
190 OPTION_EL,
191
192 OPTION_ARC600,
193 OPTION_ARC601,
194 OPTION_ARC700,
195 OPTION_ARCEM,
196 OPTION_ARCHS,
197
198 OPTION_MCPU,
199 OPTION_CD,
200 OPTION_RELAX,
201 OPTION_NPS400,
202
203 OPTION_SPFP,
204 OPTION_DPFP,
205 OPTION_FPUDA,
206
207 /* The following options are deprecated and provided here only for
208 compatibility reasons. */
209 OPTION_USER_MODE,
210 OPTION_LD_EXT_MASK,
211 OPTION_SWAP,
212 OPTION_NORM,
213 OPTION_BARREL_SHIFT,
214 OPTION_MIN_MAX,
215 OPTION_NO_MPY,
216 OPTION_EA,
217 OPTION_MUL64,
218 OPTION_SIMD,
219 OPTION_XMAC_D16,
220 OPTION_XMAC_24,
221 OPTION_DSP_PACKA,
222 OPTION_CRC,
223 OPTION_DVBF,
224 OPTION_TELEPHONY,
225 OPTION_XYMEMORY,
226 OPTION_LOCK,
227 OPTION_SWAPE,
228 OPTION_RTSC
229 };
230
231 struct option md_longopts[] =
232 {
233 { "EB", no_argument, NULL, OPTION_EB },
234 { "EL", no_argument, NULL, OPTION_EL },
235 { "mcpu", required_argument, NULL, OPTION_MCPU },
236 { "mA6", no_argument, NULL, OPTION_ARC600 },
237 { "mARC600", no_argument, NULL, OPTION_ARC600 },
238 { "mARC601", no_argument, NULL, OPTION_ARC601 },
239 { "mARC700", no_argument, NULL, OPTION_ARC700 },
240 { "mA7", no_argument, NULL, OPTION_ARC700 },
241 { "mEM", no_argument, NULL, OPTION_ARCEM },
242 { "mHS", no_argument, NULL, OPTION_ARCHS },
243 { "mcode-density", no_argument, NULL, OPTION_CD },
244 { "mrelax", no_argument, NULL, OPTION_RELAX },
245 { "mnps400", no_argument, NULL, OPTION_NPS400 },
246
247 /* Floating point options */
248 { "mspfp", no_argument, NULL, OPTION_SPFP},
249 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
250 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
251 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
252 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
253 { "mdpfp", no_argument, NULL, OPTION_DPFP},
254 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
255 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
256 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
257 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
258 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
259
260 /* The following options are deprecated and provided here only for
261 compatibility reasons. */
262 { "mav2em", no_argument, NULL, OPTION_ARCEM },
263 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
264 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
265 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
266 { "mswap", no_argument, NULL, OPTION_SWAP },
267 { "mnorm", no_argument, NULL, OPTION_NORM },
268 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
269 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
270 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
271 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
272 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
273 { "mea", no_argument, NULL, OPTION_EA },
274 { "mEA", no_argument, NULL, OPTION_EA },
275 { "mmul64", no_argument, NULL, OPTION_MUL64 },
276 { "msimd", no_argument, NULL, OPTION_SIMD},
277 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
278 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
279 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
280 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
281 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
282 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
283 { "mcrc", no_argument, NULL, OPTION_CRC},
284 { "mdvbf", no_argument, NULL, OPTION_DVBF},
285 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
286 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
287 { "mlock", no_argument, NULL, OPTION_LOCK},
288 { "mswape", no_argument, NULL, OPTION_SWAPE},
289 { "mrtsc", no_argument, NULL, OPTION_RTSC},
290
291 { NULL, no_argument, NULL, 0 }
292 };
293
294 size_t md_longopts_size = sizeof (md_longopts);
295
296 /* Local data and data types. */
297
298 /* Used since new relocation types are introduced in this
299 file (DUMMY_RELOC_LITUSE_*). */
300 typedef int extended_bfd_reloc_code_real_type;
301
302 struct arc_fixup
303 {
304 expressionS exp;
305
306 extended_bfd_reloc_code_real_type reloc;
307
308 /* index into arc_operands. */
309 unsigned int opindex;
310
311 /* PC-relative, used by internals fixups. */
312 unsigned char pcrel;
313
314 /* TRUE if this fixup is for LIMM operand. */
315 bool islong;
316 };
317
318 struct arc_insn
319 {
320 unsigned long long int insn;
321 int nfixups;
322 struct arc_fixup fixups[MAX_INSN_FIXUPS];
323 long limm;
324 unsigned int len; /* Length of instruction in bytes. */
325 bool has_limm; /* Boolean value: TRUE if limm field is valid. */
326 bool relax; /* Boolean value: TRUE if needs relaxation. */
327 };
328
329 /* Structure to hold any last two instructions. */
330 static struct arc_last_insn
331 {
332 /* Saved instruction opcode. */
333 const struct arc_opcode *opcode;
334
335 /* Boolean value: TRUE if current insn is short. */
336 bool has_limm;
337
338 /* Boolean value: TRUE if current insn has delay slot. */
339 bool has_delay_slot;
340 } arc_last_insns[2];
341
342 /* Extension instruction suffix classes. */
343 typedef struct
344 {
345 const char *name;
346 int len;
347 int attr_class;
348 } attributes_t;
349
350 static const attributes_t suffixclass[] =
351 {
352 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
353 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
354 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
355 };
356
357 /* Extension instruction syntax classes. */
358 static const attributes_t syntaxclass[] =
359 {
360 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
361 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
362 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
363 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
364 };
365
366 /* Extension instruction syntax classes modifiers. */
367 static const attributes_t syntaxclassmod[] =
368 {
369 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
370 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
371 };
372
373 /* Extension register type. */
374 typedef struct
375 {
376 char *name;
377 int number;
378 int imode;
379 } extRegister_t;
380
381 /* A structure to hold the additional conditional codes. */
382 static struct
383 {
384 struct arc_flag_operand *arc_ext_condcode;
385 int size;
386 } ext_condcode = { NULL, 0 };
387
388 /* Structure to hold an entry in ARC_OPCODE_HASH. */
389 struct arc_opcode_hash_entry
390 {
391 /* The number of pointers in the OPCODE list. */
392 size_t count;
393
394 /* Points to a list of opcode pointers. */
395 const struct arc_opcode **opcode;
396 };
397
398 /* Structure used for iterating through an arc_opcode_hash_entry. */
399 struct arc_opcode_hash_entry_iterator
400 {
401 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
402 size_t index;
403
404 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
405 returned by this iterator. */
406 const struct arc_opcode *opcode;
407 };
408
409 /* Forward declaration. */
410 static void assemble_insn
411 (const struct arc_opcode *, const expressionS *, int,
412 const struct arc_flags *, int, struct arc_insn *);
413
414 /* The selection of the machine type can come from different sources. This
415 enum is used to track how the selection was made in order to perform
416 error checks. */
417 enum mach_selection_type
418 {
419 MACH_SELECTION_NONE,
420 MACH_SELECTION_FROM_DEFAULT,
421 MACH_SELECTION_FROM_CPU_DIRECTIVE,
422 MACH_SELECTION_FROM_COMMAND_LINE
423 };
424
425 /* How the current machine type was selected. */
426 static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
427
428 /* The hash table of instruction opcodes. */
429 static htab_t arc_opcode_hash;
430
431 /* The hash table of register symbols. */
432 static htab_t arc_reg_hash;
433
434 /* The hash table of aux register symbols. */
435 static htab_t arc_aux_hash;
436
437 /* The hash table of address types. */
438 static htab_t arc_addrtype_hash;
439
440 #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
441 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
442 E_ARC_MACH_ARC600, EXTRA}
443 #define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
444 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
445 E_ARC_MACH_ARC700, EXTRA}
446 #define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
447 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
448 EF_ARC_CPU_ARCV2EM, EXTRA}
449 #define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
450 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
451 EF_ARC_CPU_ARCV2HS, EXTRA}
452 #define ARC_CPU_TYPE_NONE \
453 { 0, 0, 0, 0, 0 }
454
455 /* A table of CPU names and opcode sets. */
456 static const struct cpu_type
457 {
458 const char *name;
459 unsigned flags;
460 int mach;
461 unsigned eflags;
462 unsigned features;
463 }
464 cpu_types[] =
465 {
466 #include "elf/arc-cpu.def"
467 };
468
469 /* Information about the cpu/variant we're assembling for. */
470 static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
471
472 /* TRUE if current assembly code uses RF16 only registers. */
473 static bool rf16_only = true;
474
475 /* MPY option. */
476 static unsigned mpy_option = 0;
477
478 /* Use PIC. */
479 static unsigned pic_option = 0;
480
481 /* Use small data. */
482 static unsigned sda_option = 0;
483
484 /* Use TLS. */
485 static unsigned tls_option = 0;
486
487 /* Command line given features. */
488 static unsigned cl_features = 0;
489
490 /* Used by the arc_reloc_op table. Order is important. */
491 #define O_gotoff O_md1 /* @gotoff relocation. */
492 #define O_gotpc O_md2 /* @gotpc relocation. */
493 #define O_plt O_md3 /* @plt relocation. */
494 #define O_sda O_md4 /* @sda relocation. */
495 #define O_pcl O_md5 /* @pcl relocation. */
496 #define O_tlsgd O_md6 /* @tlsgd relocation. */
497 #define O_tlsie O_md7 /* @tlsie relocation. */
498 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
499 #define O_tpoff O_md9 /* @tpoff relocation. */
500 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
501 #define O_dtpoff O_md11 /* @dtpoff relocation. */
502 #define O_last O_dtpoff
503
504 /* Used to define a bracket as operand in tokens. */
505 #define O_bracket O_md32
506
507 /* Used to define a colon as an operand in tokens. */
508 #define O_colon O_md31
509
510 /* Used to define address types in nps400. */
511 #define O_addrtype O_md30
512
513 /* Dummy relocation, to be sorted out. */
514 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
515
516 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
517
518 /* A table to map the spelling of a relocation operand into an appropriate
519 bfd_reloc_code_real_type type. The table is assumed to be ordered such
520 that op-O_literal indexes into it. */
521 #define ARC_RELOC_TABLE(op) \
522 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
523 ? (abort (), 0) \
524 : (int) (op) - (int) O_gotoff) ])
525
526 #define DEF(NAME, RELOC, REQ) \
527 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
528
529 static const struct arc_reloc_op_tag
530 {
531 /* String to lookup. */
532 const char *name;
533 /* Size of the string. */
534 size_t length;
535 /* Which operator to use. */
536 operatorT op;
537 extended_bfd_reloc_code_real_type reloc;
538 /* Allows complex relocation expression like identifier@reloc +
539 const. */
540 unsigned int complex_expr : 1;
541 }
542 arc_reloc_op[] =
543 {
544 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
545 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
546 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
547 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
548 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
549 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
550 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
551 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
552 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
553 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
554 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
555 };
556
557 static const int arc_num_reloc_op
558 = sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
559
560 /* Structure for relaxable instruction that have to be swapped with a
561 smaller alternative instruction. */
562 struct arc_relaxable_ins
563 {
564 /* Mnemonic that should be checked. */
565 const char *mnemonic_r;
566
567 /* Operands that should be checked.
568 Indexes of operands from operand array. */
569 enum rlx_operand_type operands[6];
570
571 /* Flags that should be checked. */
572 unsigned flag_classes[5];
573
574 /* Mnemonic (smaller) alternative to be used later for relaxation. */
575 const char *mnemonic_alt;
576
577 /* Index of operand that generic relaxation has to check. */
578 unsigned opcheckidx;
579
580 /* Base subtype index used. */
581 enum arc_rlx_types subtype;
582 };
583
584 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
585 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
586 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
587 (SIZE), \
588 (NEXT) } \
589
590 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
591 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
592 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
593 (SIZE), \
594 (NEXT) } \
595
596
597 /* ARC relaxation table. */
598 const relax_typeS md_relax_table[] =
599 {
600 /* Fake entry. */
601 {0, 0, 0, 0},
602
603 /* BL_S s13 ->
604 BL s25. */
605 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
606 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
607
608 /* B_S s10 ->
609 B s25. */
610 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
611 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
612
613 /* ADD_S c,b, u3 ->
614 ADD<.f> a,b,u6 ->
615 ADD<.f> a,b,limm. */
616 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
617 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
618 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
619
620 /* LD_S a, [b, u7] ->
621 LD<zz><.x><.aa><.di> a, [b, s9] ->
622 LD<zz><.x><.aa><.di> a, [b, limm] */
623 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
624 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
625 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
626
627 /* MOV_S b, u8 ->
628 MOV<.f> b, s12 ->
629 MOV<.f> b, limm. */
630 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
631 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
632 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
633
634 /* SUB_S c, b, u3 ->
635 SUB<.f> a, b, u6 ->
636 SUB<.f> a, b, limm. */
637 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
638 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
639 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
640
641 /* MPY<.f> a, b, u6 ->
642 MPY<.f> a, b, limm. */
643 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
644 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
645
646 /* MOV<.f><.cc> b, u6 ->
647 MOV<.f><.cc> b, limm. */
648 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
649 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
650
651 /* ADD<.f><.cc> b, b, u6 ->
652 ADD<.f><.cc> b, b, limm. */
653 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
654 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
655 };
656
657 /* Order of this table's entries matters! */
658 const struct arc_relaxable_ins arc_relaxable_insns[] =
659 {
660 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
661 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
662 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
663 2, ARC_RLX_ADD_RRU6},
664 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
665 ARC_RLX_ADD_U3 },
666 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
667 ARC_RLX_ADD_U6 },
668 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
669 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
670 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
671 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
672 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
673 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
674 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
675 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
676 ARC_RLX_SUB_U3 },
677 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
678 ARC_RLX_SUB_U6 },
679 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
680 ARC_RLX_MPY_U6 },
681 };
682
683 const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
684
685 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
686 symbolS * GOT_symbol = 0;
687
688 /* Set to TRUE when we assemble instructions. */
689 static bool assembling_insn = false;
690
691 /* List with attributes set explicitly. */
692 static bool attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
693
694 /* Functions implementation. */
695
696 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
697 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
698 are no matching entries in ARC_OPCODE_HASH. */
699
700 static const struct arc_opcode_hash_entry *
701 arc_find_opcode (const char *name)
702 {
703 const struct arc_opcode_hash_entry *entry;
704
705 entry = str_hash_find (arc_opcode_hash, name);
706 return entry;
707 }
708
709 /* Initialise the iterator ITER. */
710
711 static void
712 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
713 {
714 iter->index = 0;
715 iter->opcode = NULL;
716 }
717
718 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
719 calls to this function. Return NULL when all ARC_OPCODE entries have
720 been returned. */
721
722 static const struct arc_opcode *
723 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
724 struct arc_opcode_hash_entry_iterator *iter)
725 {
726 if (iter->opcode == NULL && iter->index == 0)
727 {
728 gas_assert (entry->count > 0);
729 iter->opcode = entry->opcode[iter->index];
730 }
731 else if (iter->opcode != NULL)
732 {
733 const char *old_name = iter->opcode->name;
734
735 iter->opcode++;
736 if (iter->opcode->name == NULL
737 || strcmp (old_name, iter->opcode->name) != 0)
738 {
739 iter->index++;
740 if (iter->index == entry->count)
741 iter->opcode = NULL;
742 else
743 iter->opcode = entry->opcode[iter->index];
744 }
745 }
746
747 return iter->opcode;
748 }
749
750 /* Insert an opcode into opcode hash structure. */
751
752 static void
753 arc_insert_opcode (const struct arc_opcode *opcode)
754 {
755 const char *name;
756 struct arc_opcode_hash_entry *entry;
757 name = opcode->name;
758
759 entry = str_hash_find (arc_opcode_hash, name);
760 if (entry == NULL)
761 {
762 entry = XNEW (struct arc_opcode_hash_entry);
763 entry->count = 0;
764 entry->opcode = NULL;
765
766 if (str_hash_insert (arc_opcode_hash, name, entry, 0) != NULL)
767 as_fatal (_("duplicate %s"), name);
768 }
769
770 entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode,
771 entry->count + 1);
772
773 entry->opcode[entry->count] = opcode;
774 entry->count++;
775 }
776
777
778 /* Like md_number_to_chars but for middle-endian values. The 4-byte limm
779 value, is encoded as 'middle-endian' for a little-endian target. This
780 function is used for regular 4, 6, and 8 byte instructions as well. */
781
782 static void
783 md_number_to_chars_midend (char *buf, unsigned long long val, int n)
784 {
785 switch (n)
786 {
787 case 2:
788 md_number_to_chars (buf, val, n);
789 break;
790 case 6:
791 md_number_to_chars (buf, (val & 0xffff00000000ull) >> 32, 2);
792 md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
793 break;
794 case 4:
795 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
796 md_number_to_chars (buf + 2, (val & 0xffff), 2);
797 break;
798 case 8:
799 md_number_to_chars_midend (buf, (val & 0xffffffff00000000ull) >> 32, 4);
800 md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
801 break;
802 default:
803 abort ();
804 }
805 }
806
807 /* Check if a feature is allowed for a specific CPU. */
808
809 static void
810 arc_check_feature (void)
811 {
812 unsigned i;
813
814 if (!selected_cpu.features
815 || !selected_cpu.name)
816 return;
817
818 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
819 if ((selected_cpu.features & feature_list[i].feature)
820 && !(selected_cpu.flags & feature_list[i].cpus))
821 as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
822 selected_cpu.name);
823
824 for (i = 0; i < ARRAY_SIZE (conflict_list); i++)
825 if ((selected_cpu.features & conflict_list[i]) == conflict_list[i])
826 as_bad(_("conflicting ISA extension attributes."));
827 }
828
829 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
830 the relevant static global variables. Parameter SEL describes where
831 this selection originated from. */
832
833 static void
834 arc_select_cpu (const char *arg, enum mach_selection_type sel)
835 {
836 int i;
837 static struct cpu_type old_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
838
839 /* We should only set a default if we've not made a selection from some
840 other source. */
841 gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
842 || mach_selection_mode == MACH_SELECTION_NONE);
843
844 if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
845 && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
846 as_bad (_("Multiple .cpu directives found"));
847
848 /* Look for a matching entry in CPU_TYPES array. */
849 for (i = 0; cpu_types[i].name; ++i)
850 {
851 if (!strcasecmp (cpu_types[i].name, arg))
852 {
853 /* If a previous selection was made on the command line, then we
854 allow later selections on the command line to override earlier
855 ones. However, a selection from a '.cpu NAME' directive must
856 match the command line selection, or we give a warning. */
857 if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
858 {
859 gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
860 || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
861 if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
862 && selected_cpu.mach != cpu_types[i].mach)
863 {
864 as_warn (_("Command-line value overrides \".cpu\" directive"));
865 }
866 return;
867 }
868 /* Initialise static global data about selected machine type. */
869 selected_cpu.flags = cpu_types[i].flags;
870 selected_cpu.name = cpu_types[i].name;
871 selected_cpu.features = cpu_types[i].features | cl_features;
872 selected_cpu.mach = cpu_types[i].mach;
873 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_MACH_MSK)
874 | cpu_types[i].eflags);
875 break;
876 }
877 }
878
879 if (!cpu_types[i].name)
880 as_fatal (_("unknown architecture: %s\n"), arg);
881
882 /* Check if set features are compatible with the chosen CPU. */
883 arc_check_feature ();
884
885 /* If we change the CPU, we need to re-init the bfd. */
886 if (mach_selection_mode != MACH_SELECTION_NONE
887 && (old_cpu.mach != selected_cpu.mach))
888 {
889 bfd_find_target (arc_target_format, stdoutput);
890 if (! bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
891 as_warn (_("Could not set architecture and machine"));
892 }
893
894 mach_selection_mode = sel;
895 old_cpu = selected_cpu;
896 }
897
898 /* Here ends all the ARCompact extension instruction assembling
899 stuff. */
900
901 static void
902 arc_extra_reloc (int r_type)
903 {
904 char *sym_name, c;
905 symbolS *sym, *lab = NULL;
906
907 if (*input_line_pointer == '@')
908 input_line_pointer++;
909 c = get_symbol_name (&sym_name);
910 sym = symbol_find_or_make (sym_name);
911 restore_line_pointer (c);
912 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
913 {
914 ++input_line_pointer;
915 char *lab_name;
916 c = get_symbol_name (&lab_name);
917 lab = symbol_find_or_make (lab_name);
918 restore_line_pointer (c);
919 }
920
921 /* These relocations exist as a mechanism for the compiler to tell the
922 linker how to patch the code if the tls model is optimised. However,
923 the relocation itself does not require any space within the assembler
924 fragment, and so we pass a size of 0.
925
926 The lines that generate these relocations look like this:
927
928 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
929
930 The '.tls_gd_ld @.tdata' is processed first and generates the
931 additional relocation, while the 'bl __tls_get_addr@plt' is processed
932 second and generates the additional branch.
933
934 It is possible that the additional relocation generated by the
935 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
936 while the 'bl __tls_get_addr@plt' will be generated as the first thing
937 in the next fragment. This will be fine; both relocations will still
938 appear to be at the same address in the generated object file.
939 However, this only works as the additional relocation is generated
940 with size of 0 bytes. */
941 fixS *fixP
942 = fix_new (frag_now, /* Which frag? */
943 frag_now_fix (), /* Where in that frag? */
944 0, /* size: 1, 2, or 4 usually. */
945 sym, /* X_add_symbol. */
946 0, /* X_add_number. */
947 false, /* TRUE if PC-relative relocation. */
948 r_type /* Relocation type. */);
949 fixP->fx_subsy = lab;
950 }
951
952 static symbolS *
953 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
954 symbolS *symbolP, addressT size)
955 {
956 addressT align = 0;
957 SKIP_WHITESPACE ();
958
959 if (*input_line_pointer == ',')
960 {
961 align = parse_align (1);
962
963 if (align == (addressT) -1)
964 return NULL;
965 }
966 else
967 {
968 if (size >= 8)
969 align = 3;
970 else if (size >= 4)
971 align = 2;
972 else if (size >= 2)
973 align = 1;
974 else
975 align = 0;
976 }
977
978 bss_alloc (symbolP, size, align);
979 S_CLEAR_EXTERNAL (symbolP);
980
981 return symbolP;
982 }
983
984 static void
985 arc_lcomm (int ignore)
986 {
987 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
988
989 if (symbolP)
990 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
991 }
992
993 /* Select the cpu we're assembling for. */
994
995 static void
996 arc_option (int ignore ATTRIBUTE_UNUSED)
997 {
998 char c;
999 char *cpu;
1000 const char *cpu_name;
1001
1002 c = get_symbol_name (&cpu);
1003
1004 cpu_name = cpu;
1005 if ((!strcmp ("ARC600", cpu))
1006 || (!strcmp ("ARC601", cpu))
1007 || (!strcmp ("A6", cpu)))
1008 cpu_name = "arc600";
1009 else if ((!strcmp ("ARC700", cpu))
1010 || (!strcmp ("A7", cpu)))
1011 cpu_name = "arc700";
1012 else if (!strcmp ("EM", cpu))
1013 cpu_name = "arcem";
1014 else if (!strcmp ("HS", cpu))
1015 cpu_name = "archs";
1016 else if (!strcmp ("NPS400", cpu))
1017 cpu_name = "nps400";
1018
1019 arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
1020
1021 restore_line_pointer (c);
1022 demand_empty_rest_of_line ();
1023 }
1024
1025 /* Smartly print an expression. */
1026
1027 static void
1028 debug_exp (expressionS *t)
1029 {
1030 const char *name ATTRIBUTE_UNUSED;
1031 const char *namemd ATTRIBUTE_UNUSED;
1032
1033 pr_debug ("debug_exp: ");
1034
1035 switch (t->X_op)
1036 {
1037 default: name = "unknown"; break;
1038 case O_illegal: name = "O_illegal"; break;
1039 case O_absent: name = "O_absent"; break;
1040 case O_constant: name = "O_constant"; break;
1041 case O_symbol: name = "O_symbol"; break;
1042 case O_symbol_rva: name = "O_symbol_rva"; break;
1043 case O_register: name = "O_register"; break;
1044 case O_big: name = "O_big"; break;
1045 case O_uminus: name = "O_uminus"; break;
1046 case O_bit_not: name = "O_bit_not"; break;
1047 case O_logical_not: name = "O_logical_not"; break;
1048 case O_multiply: name = "O_multiply"; break;
1049 case O_divide: name = "O_divide"; break;
1050 case O_modulus: name = "O_modulus"; break;
1051 case O_left_shift: name = "O_left_shift"; break;
1052 case O_right_shift: name = "O_right_shift"; break;
1053 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
1054 case O_bit_or_not: name = "O_bit_or_not"; break;
1055 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
1056 case O_bit_and: name = "O_bit_and"; break;
1057 case O_add: name = "O_add"; break;
1058 case O_subtract: name = "O_subtract"; break;
1059 case O_eq: name = "O_eq"; break;
1060 case O_ne: name = "O_ne"; break;
1061 case O_lt: name = "O_lt"; break;
1062 case O_le: name = "O_le"; break;
1063 case O_ge: name = "O_ge"; break;
1064 case O_gt: name = "O_gt"; break;
1065 case O_logical_and: name = "O_logical_and"; break;
1066 case O_logical_or: name = "O_logical_or"; break;
1067 case O_index: name = "O_index"; break;
1068 case O_bracket: name = "O_bracket"; break;
1069 case O_colon: name = "O_colon"; break;
1070 case O_addrtype: name = "O_addrtype"; break;
1071 }
1072
1073 switch (t->X_md)
1074 {
1075 default: namemd = "unknown"; break;
1076 case O_gotoff: namemd = "O_gotoff"; break;
1077 case O_gotpc: namemd = "O_gotpc"; break;
1078 case O_plt: namemd = "O_plt"; break;
1079 case O_sda: namemd = "O_sda"; break;
1080 case O_pcl: namemd = "O_pcl"; break;
1081 case O_tlsgd: namemd = "O_tlsgd"; break;
1082 case O_tlsie: namemd = "O_tlsie"; break;
1083 case O_tpoff9: namemd = "O_tpoff9"; break;
1084 case O_tpoff: namemd = "O_tpoff"; break;
1085 case O_dtpoff9: namemd = "O_dtpoff9"; break;
1086 case O_dtpoff: namemd = "O_dtpoff"; break;
1087 }
1088
1089 pr_debug ("%s (%s, %s, %d, %s)", name,
1090 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
1091 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
1092 (int) t->X_add_number,
1093 (t->X_md) ? namemd : "--");
1094 pr_debug ("\n");
1095 fflush (stderr);
1096 }
1097
1098 /* Helper for parsing an argument, used for sorting out the relocation
1099 type. */
1100
1101 static void
1102 parse_reloc_symbol (expressionS *resultP)
1103 {
1104 char *reloc_name, c, *sym_name;
1105 size_t len;
1106 int i;
1107 const struct arc_reloc_op_tag *r;
1108 expressionS right;
1109 symbolS *base;
1110
1111 /* A relocation operand has the following form
1112 @identifier@relocation_type. The identifier is already in
1113 tok! */
1114 if (resultP->X_op != O_symbol)
1115 {
1116 as_bad (_("No valid label relocation operand"));
1117 resultP->X_op = O_illegal;
1118 return;
1119 }
1120
1121 /* Parse @relocation_type. */
1122 input_line_pointer++;
1123 c = get_symbol_name (&reloc_name);
1124 len = input_line_pointer - reloc_name;
1125 if (len == 0)
1126 {
1127 as_bad (_("No relocation operand"));
1128 resultP->X_op = O_illegal;
1129 return;
1130 }
1131
1132 /* Go through known relocation and try to find a match. */
1133 r = &arc_reloc_op[0];
1134 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
1135 if (len == r->length
1136 && memcmp (reloc_name, r->name, len) == 0)
1137 break;
1138 if (i < 0)
1139 {
1140 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
1141 resultP->X_op = O_illegal;
1142 return;
1143 }
1144
1145 *input_line_pointer = c;
1146 SKIP_WHITESPACE_AFTER_NAME ();
1147 /* Extra check for TLS: base. */
1148 if (*input_line_pointer == '@')
1149 {
1150 if (resultP->X_op_symbol != NULL
1151 || resultP->X_op != O_symbol)
1152 {
1153 as_bad (_("Unable to parse TLS base: %s"),
1154 input_line_pointer);
1155 resultP->X_op = O_illegal;
1156 return;
1157 }
1158 input_line_pointer++;
1159 c = get_symbol_name (&sym_name);
1160 base = symbol_find_or_make (sym_name);
1161 resultP->X_op = O_subtract;
1162 resultP->X_op_symbol = base;
1163 restore_line_pointer (c);
1164 right.X_add_number = 0;
1165 }
1166
1167 if ((*input_line_pointer != '+')
1168 && (*input_line_pointer != '-'))
1169 right.X_add_number = 0;
1170 else
1171 {
1172 /* Parse the constant of a complex relocation expression
1173 like @identifier@reloc +/- const. */
1174 if (! r->complex_expr)
1175 {
1176 as_bad (_("@%s is not a complex relocation."), r->name);
1177 resultP->X_op = O_illegal;
1178 return;
1179 }
1180 expression (&right);
1181 if (right.X_op != O_constant)
1182 {
1183 as_bad (_("Bad expression: @%s + %s."),
1184 r->name, input_line_pointer);
1185 resultP->X_op = O_illegal;
1186 return;
1187 }
1188 }
1189
1190 resultP->X_md = r->op;
1191 resultP->X_add_number = right.X_add_number;
1192 }
1193
1194 /* Parse the arguments to an opcode. */
1195
1196 static int
1197 tokenize_arguments (char *str,
1198 expressionS *tok,
1199 int ntok)
1200 {
1201 char *old_input_line_pointer;
1202 bool saw_comma = false;
1203 bool saw_arg = false;
1204 int brk_lvl = 0;
1205 int num_args = 0;
1206
1207 memset (tok, 0, sizeof (*tok) * ntok);
1208
1209 /* Save and restore input_line_pointer around this function. */
1210 old_input_line_pointer = input_line_pointer;
1211 input_line_pointer = str;
1212
1213 while (*input_line_pointer)
1214 {
1215 SKIP_WHITESPACE ();
1216 switch (*input_line_pointer)
1217 {
1218 case '\0':
1219 goto fini;
1220
1221 case ',':
1222 input_line_pointer++;
1223 if (saw_comma || !saw_arg)
1224 goto err;
1225 saw_comma = true;
1226 break;
1227
1228 case '}':
1229 case ']':
1230 ++input_line_pointer;
1231 --brk_lvl;
1232 if (!saw_arg || num_args == ntok)
1233 goto err;
1234 tok->X_op = O_bracket;
1235 ++tok;
1236 ++num_args;
1237 break;
1238
1239 case '{':
1240 case '[':
1241 input_line_pointer++;
1242 if (brk_lvl || num_args == ntok)
1243 goto err;
1244 ++brk_lvl;
1245 tok->X_op = O_bracket;
1246 ++tok;
1247 ++num_args;
1248 break;
1249
1250 case ':':
1251 input_line_pointer++;
1252 if (!saw_arg || num_args == ntok)
1253 goto err;
1254 tok->X_op = O_colon;
1255 saw_arg = false;
1256 ++tok;
1257 ++num_args;
1258 break;
1259
1260 case '@':
1261 /* We have labels, function names and relocations, all
1262 starting with @ symbol. Sort them out. */
1263 if ((saw_arg && !saw_comma) || num_args == ntok)
1264 goto err;
1265
1266 /* Parse @label. */
1267 input_line_pointer++;
1268 tok->X_op = O_symbol;
1269 tok->X_md = O_absent;
1270 expression (tok);
1271
1272 if (*input_line_pointer == '@')
1273 parse_reloc_symbol (tok);
1274
1275 debug_exp (tok);
1276
1277 if (tok->X_op == O_illegal
1278 || tok->X_op == O_absent
1279 || num_args == ntok)
1280 goto err;
1281
1282 saw_comma = false;
1283 saw_arg = true;
1284 tok++;
1285 num_args++;
1286 break;
1287
1288 case '%':
1289 /* Can be a register. */
1290 ++input_line_pointer;
1291 /* Fall through. */
1292 default:
1293
1294 if ((saw_arg && !saw_comma) || num_args == ntok)
1295 goto err;
1296
1297 tok->X_op = O_absent;
1298 tok->X_md = O_absent;
1299 expression (tok);
1300
1301 /* Legacy: There are cases when we have
1302 identifier@relocation_type, if it is the case parse the
1303 relocation type as well. */
1304 if (*input_line_pointer == '@')
1305 parse_reloc_symbol (tok);
1306
1307 debug_exp (tok);
1308
1309 if (tok->X_op == O_illegal
1310 || tok->X_op == O_absent
1311 || num_args == ntok)
1312 goto err;
1313
1314 saw_comma = false;
1315 saw_arg = true;
1316 tok++;
1317 num_args++;
1318 break;
1319 }
1320 }
1321
1322 fini:
1323 if (saw_comma || brk_lvl)
1324 goto err;
1325 input_line_pointer = old_input_line_pointer;
1326
1327 return num_args;
1328
1329 err:
1330 if (brk_lvl)
1331 as_bad (_("Brackets in operand field incorrect"));
1332 else if (saw_comma)
1333 as_bad (_("extra comma"));
1334 else if (!saw_arg)
1335 as_bad (_("missing argument"));
1336 else
1337 as_bad (_("missing comma or colon"));
1338 input_line_pointer = old_input_line_pointer;
1339 return -1;
1340 }
1341
1342 /* Parse the flags to a structure. */
1343
1344 static int
1345 tokenize_flags (const char *str,
1346 struct arc_flags flags[],
1347 int nflg)
1348 {
1349 char *old_input_line_pointer;
1350 bool saw_flg = false;
1351 bool saw_dot = false;
1352 int num_flags = 0;
1353 size_t flgnamelen;
1354
1355 memset (flags, 0, sizeof (*flags) * nflg);
1356
1357 /* Save and restore input_line_pointer around this function. */
1358 old_input_line_pointer = input_line_pointer;
1359 input_line_pointer = (char *) str;
1360
1361 while (*input_line_pointer)
1362 {
1363 switch (*input_line_pointer)
1364 {
1365 case ' ':
1366 case '\0':
1367 goto fini;
1368
1369 case '.':
1370 input_line_pointer++;
1371 if (saw_dot)
1372 goto err;
1373 saw_dot = true;
1374 saw_flg = false;
1375 break;
1376
1377 default:
1378 if (saw_flg && !saw_dot)
1379 goto err;
1380
1381 if (num_flags >= nflg)
1382 goto err;
1383
1384 flgnamelen = strspn (input_line_pointer,
1385 "abcdefghijklmnopqrstuvwxyz0123456789");
1386 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
1387 goto err;
1388
1389 memcpy (flags->name, input_line_pointer, flgnamelen);
1390
1391 input_line_pointer += flgnamelen;
1392 flags++;
1393 saw_dot = false;
1394 saw_flg = true;
1395 num_flags++;
1396 break;
1397 }
1398 }
1399
1400 fini:
1401 input_line_pointer = old_input_line_pointer;
1402 return num_flags;
1403
1404 err:
1405 if (saw_dot)
1406 as_bad (_("extra dot"));
1407 else if (!saw_flg)
1408 as_bad (_("unrecognized flag"));
1409 else
1410 as_bad (_("failed to parse flags"));
1411 input_line_pointer = old_input_line_pointer;
1412 return -1;
1413 }
1414
1415 /* Apply the fixups in order. */
1416
1417 static void
1418 apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
1419 {
1420 int i;
1421
1422 for (i = 0; i < insn->nfixups; i++)
1423 {
1424 struct arc_fixup *fixup = &insn->fixups[i];
1425 int size, pcrel, offset = 0;
1426
1427 /* FIXME! the reloc size is wrong in the BFD file.
1428 When it is fixed please delete me. */
1429 size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
1430
1431 if (fixup->islong)
1432 offset = insn->len;
1433
1434 /* Some fixups are only used internally, thus no howto. */
1435 if ((int) fixup->reloc == 0)
1436 as_fatal (_("Unhandled reloc type"));
1437
1438 if ((int) fixup->reloc < 0)
1439 {
1440 /* FIXME! the reloc size is wrong in the BFD file.
1441 When it is fixed please enable me.
1442 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
1443 pcrel = fixup->pcrel;
1444 }
1445 else
1446 {
1447 reloc_howto_type *reloc_howto =
1448 bfd_reloc_type_lookup (stdoutput,
1449 (bfd_reloc_code_real_type) fixup->reloc);
1450 gas_assert (reloc_howto);
1451
1452 /* FIXME! the reloc size is wrong in the BFD file.
1453 When it is fixed please enable me.
1454 size = bfd_get_reloc_size (reloc_howto); */
1455 pcrel = reloc_howto->pc_relative;
1456 }
1457
1458 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1459 offset %d + %d\n",
1460 fragP->fr_file, fragP->fr_line,
1461 (fixup->reloc < 0) ? "Internal" :
1462 bfd_get_reloc_code_name (fixup->reloc),
1463 pcrel ? "Y" : "N",
1464 size, fix, offset);
1465 fix_new_exp (fragP, fix + offset,
1466 size, &fixup->exp, pcrel, fixup->reloc);
1467
1468 /* Check for ZOLs, and update symbol info if any. */
1469 if (LP_INSN (insn->insn))
1470 {
1471 gas_assert (fixup->exp.X_add_symbol);
1472 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
1473 }
1474 }
1475 }
1476
1477 /* Actually output an instruction with its fixup. */
1478
1479 static void
1480 emit_insn0 (struct arc_insn *insn, char *where, bool relax)
1481 {
1482 char *f = where;
1483 size_t total_len;
1484
1485 pr_debug ("Emit insn : 0x%llx\n", insn->insn);
1486 pr_debug ("\tLength : %d\n", insn->len);
1487 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
1488
1489 /* Write out the instruction. */
1490 total_len = insn->len + (insn->has_limm ? 4 : 0);
1491 if (!relax)
1492 f = frag_more (total_len);
1493
1494 md_number_to_chars_midend(f, insn->insn, insn->len);
1495
1496 if (insn->has_limm)
1497 md_number_to_chars_midend (f + insn->len, insn->limm, 4);
1498 dwarf2_emit_insn (total_len);
1499
1500 if (!relax)
1501 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1502 }
1503
1504 static void
1505 emit_insn1 (struct arc_insn *insn)
1506 {
1507 /* How frag_var's args are currently configured:
1508 - rs_machine_dependent, to dictate it's a relaxation frag.
1509 - FRAG_MAX_GROWTH, maximum size of instruction
1510 - 0, variable size that might grow...unused by generic relaxation.
1511 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1512 - s, opand expression.
1513 - 0, offset but it's unused.
1514 - 0, opcode but it's unused. */
1515 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1516 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1517
1518 if (frag_room () < FRAG_MAX_GROWTH)
1519 {
1520 /* Handle differently when frag literal memory is exhausted.
1521 This is used because when there's not enough memory left in
1522 the current frag, a new frag is created and the information
1523 we put into frag_now->tc_frag_data is disregarded. */
1524
1525 struct arc_relax_type relax_info_copy;
1526 relax_substateT subtype = frag_now->fr_subtype;
1527
1528 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1529 sizeof (struct arc_relax_type));
1530
1531 frag_wane (frag_now);
1532 frag_grow (FRAG_MAX_GROWTH);
1533
1534 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1535 sizeof (struct arc_relax_type));
1536
1537 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1538 subtype, s, 0, 0);
1539 }
1540 else
1541 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1542 frag_now->fr_subtype, s, 0, 0);
1543 }
1544
1545 static void
1546 emit_insn (struct arc_insn *insn)
1547 {
1548 if (insn->relax)
1549 emit_insn1 (insn);
1550 else
1551 emit_insn0 (insn, NULL, false);
1552 }
1553
1554 /* Check whether a symbol involves a register. */
1555
1556 static bool
1557 contains_register (symbolS *sym)
1558 {
1559 if (sym)
1560 {
1561 expressionS *ex = symbol_get_value_expression (sym);
1562
1563 return ((O_register == ex->X_op)
1564 && !contains_register (ex->X_add_symbol)
1565 && !contains_register (ex->X_op_symbol));
1566 }
1567
1568 return false;
1569 }
1570
1571 /* Returns the register number within a symbol. */
1572
1573 static int
1574 get_register (symbolS *sym)
1575 {
1576 if (!contains_register (sym))
1577 return -1;
1578
1579 expressionS *ex = symbol_get_value_expression (sym);
1580 return regno (ex->X_add_number);
1581 }
1582
1583 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1584 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1585
1586 static bool
1587 generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1588 {
1589 if (!reloc)
1590 return false;
1591
1592 switch (reloc)
1593 {
1594 case BFD_RELOC_ARC_SDA_LDST:
1595 case BFD_RELOC_ARC_SDA_LDST1:
1596 case BFD_RELOC_ARC_SDA_LDST2:
1597 case BFD_RELOC_ARC_SDA16_LD:
1598 case BFD_RELOC_ARC_SDA16_LD1:
1599 case BFD_RELOC_ARC_SDA16_LD2:
1600 case BFD_RELOC_ARC_SDA16_ST2:
1601 case BFD_RELOC_ARC_SDA32_ME:
1602 return false;
1603 default:
1604 return true;
1605 }
1606 }
1607
1608 /* Allocates a tok entry. */
1609
1610 static int
1611 allocate_tok (expressionS *tok, int ntok, int cidx)
1612 {
1613 if (ntok > MAX_INSN_ARGS - 2)
1614 return 0; /* No space left. */
1615
1616 if (cidx > ntok)
1617 return 0; /* Incorrect args. */
1618
1619 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
1620
1621 if (cidx == ntok)
1622 return 1; /* Success. */
1623 return allocate_tok (tok, ntok - 1, cidx);
1624 }
1625
1626 /* Check if an particular ARC feature is enabled. */
1627
1628 static bool
1629 check_cpu_feature (insn_subclass_t sc)
1630 {
1631 if (is_code_density_p (sc) && !(selected_cpu.features & CD))
1632 return false;
1633
1634 if (is_spfp_p (sc) && !(selected_cpu.features & SPX))
1635 return false;
1636
1637 if (is_dpfp_p (sc) && !(selected_cpu.features & DPX))
1638 return false;
1639
1640 if (is_fpuda_p (sc) && !(selected_cpu.features & DPA))
1641 return false;
1642
1643 if (is_nps400_p (sc) && !(selected_cpu.features & NPS400))
1644 return false;
1645
1646 return true;
1647 }
1648
1649 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1650 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1651 array and returns TRUE if the flag operands all match, otherwise,
1652 returns FALSE, in which case the FIRST_PFLAG array may have been
1653 modified. */
1654
1655 static bool
1656 parse_opcode_flags (const struct arc_opcode *opcode,
1657 int nflgs,
1658 struct arc_flags *first_pflag)
1659 {
1660 int lnflg, i;
1661 const unsigned char *flgidx;
1662
1663 lnflg = nflgs;
1664 for (i = 0; i < nflgs; i++)
1665 first_pflag[i].flgp = NULL;
1666
1667 /* Check the flags. Iterate over the valid flag classes. */
1668 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1669 {
1670 /* Get a valid flag class. */
1671 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1672 const unsigned *flgopridx;
1673 int cl_matches = 0;
1674 struct arc_flags *pflag = NULL;
1675
1676 /* Check if opcode has implicit flag classes. */
1677 if (cl_flags->flag_class & F_CLASS_IMPLICIT)
1678 continue;
1679
1680 /* Check for extension conditional codes. */
1681 if (ext_condcode.arc_ext_condcode
1682 && cl_flags->flag_class & F_CLASS_EXTEND)
1683 {
1684 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1685 while (pf->name)
1686 {
1687 pflag = first_pflag;
1688 for (i = 0; i < nflgs; i++, pflag++)
1689 {
1690 if (!strcmp (pf->name, pflag->name))
1691 {
1692 if (pflag->flgp != NULL)
1693 return false;
1694 /* Found it. */
1695 cl_matches++;
1696 pflag->flgp = pf;
1697 lnflg--;
1698 break;
1699 }
1700 }
1701 pf++;
1702 }
1703 }
1704
1705 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1706 {
1707 const struct arc_flag_operand *flg_operand;
1708
1709 pflag = first_pflag;
1710 flg_operand = &arc_flag_operands[*flgopridx];
1711 for (i = 0; i < nflgs; i++, pflag++)
1712 {
1713 /* Match against the parsed flags. */
1714 if (!strcmp (flg_operand->name, pflag->name))
1715 {
1716 if (pflag->flgp != NULL)
1717 return false;
1718 cl_matches++;
1719 pflag->flgp = flg_operand;
1720 lnflg--;
1721 break; /* goto next flag class and parsed flag. */
1722 }
1723 }
1724 }
1725
1726 if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
1727 return false;
1728 if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
1729 return false;
1730 }
1731
1732 /* Did I check all the parsed flags? */
1733 return lnflg == 0;
1734 }
1735
1736
1737 /* Search forward through all variants of an opcode looking for a
1738 syntax match. */
1739
1740 static const struct arc_opcode *
1741 find_opcode_match (const struct arc_opcode_hash_entry *entry,
1742 expressionS *tok,
1743 int *pntok,
1744 struct arc_flags *first_pflag,
1745 int nflgs,
1746 int *pcpumatch,
1747 const char **errmsg)
1748 {
1749 const struct arc_opcode *opcode;
1750 struct arc_opcode_hash_entry_iterator iter;
1751 int ntok = *pntok;
1752 int got_cpu_match = 0;
1753 expressionS bktok[MAX_INSN_ARGS];
1754 int bkntok, maxerridx = 0;
1755 expressionS emptyE;
1756 const char *tmpmsg = NULL;
1757
1758 arc_opcode_hash_entry_iterator_init (&iter);
1759 memset (&emptyE, 0, sizeof (emptyE));
1760 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1761 bkntok = ntok;
1762
1763 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1764 opcode != NULL;
1765 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
1766 {
1767 const unsigned char *opidx;
1768 int tokidx = 0;
1769 const expressionS *t = &emptyE;
1770
1771 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
1772 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
1773
1774 /* Don't match opcodes that don't exist on this
1775 architecture. */
1776 if (!(opcode->cpu & selected_cpu.flags))
1777 goto match_failed;
1778
1779 if (!check_cpu_feature (opcode->subclass))
1780 goto match_failed;
1781
1782 got_cpu_match = 1;
1783 pr_debug ("cpu ");
1784
1785 /* Check the operands. */
1786 for (opidx = opcode->operands; *opidx; ++opidx)
1787 {
1788 const struct arc_operand *operand = &arc_operands[*opidx];
1789
1790 /* Only take input from real operands. */
1791 if (ARC_OPERAND_IS_FAKE (operand))
1792 continue;
1793
1794 /* When we expect input, make sure we have it. */
1795 if (tokidx >= ntok)
1796 goto match_failed;
1797
1798 /* Match operand type with expression type. */
1799 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1800 {
1801 case ARC_OPERAND_ADDRTYPE:
1802 {
1803 tmpmsg = NULL;
1804
1805 /* Check to be an address type. */
1806 if (tok[tokidx].X_op != O_addrtype)
1807 goto match_failed;
1808
1809 /* All address type operands need to have an insert
1810 method in order to check that we have the correct
1811 address type. */
1812 gas_assert (operand->insert != NULL);
1813 (*operand->insert) (0, tok[tokidx].X_add_number,
1814 &tmpmsg);
1815 if (tmpmsg != NULL)
1816 goto match_failed;
1817 }
1818 break;
1819
1820 case ARC_OPERAND_IR:
1821 /* Check to be a register. */
1822 if ((tok[tokidx].X_op != O_register
1823 || !is_ir_num (tok[tokidx].X_add_number))
1824 && !(operand->flags & ARC_OPERAND_IGNORE))
1825 goto match_failed;
1826
1827 /* If expect duplicate, make sure it is duplicate. */
1828 if (operand->flags & ARC_OPERAND_DUPLICATE)
1829 {
1830 /* Check for duplicate. */
1831 if (t->X_op != O_register
1832 || !is_ir_num (t->X_add_number)
1833 || (regno (t->X_add_number) !=
1834 regno (tok[tokidx].X_add_number)))
1835 goto match_failed;
1836 }
1837
1838 /* Special handling? */
1839 if (operand->insert)
1840 {
1841 tmpmsg = NULL;
1842 (*operand->insert)(0,
1843 regno (tok[tokidx].X_add_number),
1844 &tmpmsg);
1845 if (tmpmsg)
1846 {
1847 if (operand->flags & ARC_OPERAND_IGNORE)
1848 {
1849 /* Missing argument, create one. */
1850 if (!allocate_tok (tok, ntok - 1, tokidx))
1851 goto match_failed;
1852
1853 tok[tokidx].X_op = O_absent;
1854 ++ntok;
1855 }
1856 else
1857 goto match_failed;
1858 }
1859 }
1860
1861 t = &tok[tokidx];
1862 break;
1863
1864 case ARC_OPERAND_BRAKET:
1865 /* Check if bracket is also in opcode table as
1866 operand. */
1867 if (tok[tokidx].X_op != O_bracket)
1868 goto match_failed;
1869 break;
1870
1871 case ARC_OPERAND_COLON:
1872 /* Check if colon is also in opcode table as operand. */
1873 if (tok[tokidx].X_op != O_colon)
1874 goto match_failed;
1875 break;
1876
1877 case ARC_OPERAND_LIMM:
1878 case ARC_OPERAND_SIGNED:
1879 case ARC_OPERAND_UNSIGNED:
1880 switch (tok[tokidx].X_op)
1881 {
1882 case O_illegal:
1883 case O_absent:
1884 case O_register:
1885 goto match_failed;
1886
1887 case O_bracket:
1888 /* Got an (too) early bracket, check if it is an
1889 ignored operand. N.B. This procedure works only
1890 when bracket is the last operand! */
1891 if (!(operand->flags & ARC_OPERAND_IGNORE))
1892 goto match_failed;
1893 /* Insert the missing operand. */
1894 if (!allocate_tok (tok, ntok - 1, tokidx))
1895 goto match_failed;
1896
1897 tok[tokidx].X_op = O_absent;
1898 ++ntok;
1899 break;
1900
1901 case O_symbol:
1902 {
1903 const char *p;
1904 char *tmpp, *pp;
1905 const struct arc_aux_reg *auxr;
1906
1907 if (opcode->insn_class != AUXREG)
1908 goto de_fault;
1909 p = S_GET_NAME (tok[tokidx].X_add_symbol);
1910
1911 /* For compatibility reasons, an aux register can
1912 be spelled with upper or lower case
1913 letters. */
1914 tmpp = strdup (p);
1915 for (pp = tmpp; *pp; ++pp) *pp = TOLOWER (*pp);
1916
1917 auxr = str_hash_find (arc_aux_hash, tmpp);
1918 if (auxr)
1919 {
1920 /* We modify the token array here, safe in the
1921 knowledge, that if this was the wrong
1922 choice then the original contents will be
1923 restored from BKTOK. */
1924 tok[tokidx].X_op = O_constant;
1925 tok[tokidx].X_add_number = auxr->address;
1926 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1927 }
1928 free (tmpp);
1929
1930 if (tok[tokidx].X_op != O_constant)
1931 goto de_fault;
1932 }
1933 /* Fall through. */
1934 case O_constant:
1935 /* Check the range. */
1936 if (operand->bits != 32
1937 && !(operand->flags & ARC_OPERAND_NCHK))
1938 {
1939 offsetT min, max, val;
1940 val = tok[tokidx].X_add_number;
1941
1942 if (operand->flags & ARC_OPERAND_SIGNED)
1943 {
1944 max = (1 << (operand->bits - 1)) - 1;
1945 min = -(1 << (operand->bits - 1));
1946 }
1947 else
1948 {
1949 max = (1 << operand->bits) - 1;
1950 min = 0;
1951 }
1952
1953 if (val < min || val > max)
1954 {
1955 tmpmsg = _("immediate is out of bounds");
1956 goto match_failed;
1957 }
1958
1959 /* Check alignments. */
1960 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1961 && (val & 0x03))
1962 {
1963 tmpmsg = _("immediate is not 32bit aligned");
1964 goto match_failed;
1965 }
1966
1967 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1968 && (val & 0x01))
1969 {
1970 tmpmsg = _("immediate is not 16bit aligned");
1971 goto match_failed;
1972 }
1973 }
1974 else if (operand->flags & ARC_OPERAND_NCHK)
1975 {
1976 if (operand->insert)
1977 {
1978 tmpmsg = NULL;
1979 (*operand->insert)(0,
1980 tok[tokidx].X_add_number,
1981 &tmpmsg);
1982 if (tmpmsg)
1983 goto match_failed;
1984 }
1985 else if (!(operand->flags & ARC_OPERAND_IGNORE))
1986 goto match_failed;
1987 }
1988 break;
1989
1990 case O_subtract:
1991 /* Check if it is register range. */
1992 if ((tok[tokidx].X_add_number == 0)
1993 && contains_register (tok[tokidx].X_add_symbol)
1994 && contains_register (tok[tokidx].X_op_symbol))
1995 {
1996 int regs;
1997
1998 regs = get_register (tok[tokidx].X_add_symbol);
1999 regs <<= 16;
2000 regs |= get_register (tok[tokidx].X_op_symbol);
2001 if (operand->insert)
2002 {
2003 tmpmsg = NULL;
2004 (*operand->insert)(0,
2005 regs,
2006 &tmpmsg);
2007 if (tmpmsg)
2008 goto match_failed;
2009 }
2010 else
2011 goto match_failed;
2012 break;
2013 }
2014 /* Fall through. */
2015 default:
2016 de_fault:
2017 if (operand->default_reloc == 0)
2018 goto match_failed; /* The operand needs relocation. */
2019
2020 /* Relocs requiring long immediate. FIXME! make it
2021 generic and move it to a function. */
2022 switch (tok[tokidx].X_md)
2023 {
2024 case O_gotoff:
2025 case O_gotpc:
2026 case O_pcl:
2027 case O_tpoff:
2028 case O_dtpoff:
2029 case O_tlsgd:
2030 case O_tlsie:
2031 if (!(operand->flags & ARC_OPERAND_LIMM))
2032 goto match_failed;
2033 /* Fall through. */
2034 case O_absent:
2035 if (!generic_reloc_p (operand->default_reloc))
2036 goto match_failed;
2037 break;
2038 default:
2039 break;
2040 }
2041 break;
2042 }
2043 /* If expect duplicate, make sure it is duplicate. */
2044 if (operand->flags & ARC_OPERAND_DUPLICATE)
2045 {
2046 if (t->X_op == O_illegal
2047 || t->X_op == O_absent
2048 || t->X_op == O_register
2049 || (t->X_add_number != tok[tokidx].X_add_number))
2050 {
2051 tmpmsg = _("operand is not duplicate of the "
2052 "previous one");
2053 goto match_failed;
2054 }
2055 }
2056 t = &tok[tokidx];
2057 break;
2058
2059 default:
2060 /* Everything else should have been fake. */
2061 abort ();
2062 }
2063
2064 ++tokidx;
2065 }
2066 pr_debug ("opr ");
2067
2068 /* Setup ready for flag parsing. */
2069 if (!parse_opcode_flags (opcode, nflgs, first_pflag))
2070 {
2071 tmpmsg = _("flag mismatch");
2072 goto match_failed;
2073 }
2074
2075 pr_debug ("flg");
2076 /* Possible match -- did we use all of our input? */
2077 if (tokidx == ntok)
2078 {
2079 *pntok = ntok;
2080 pr_debug ("\n");
2081 return opcode;
2082 }
2083 tmpmsg = _("too many arguments");
2084
2085 match_failed:;
2086 pr_debug ("\n");
2087 /* Restore the original parameters. */
2088 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
2089 ntok = bkntok;
2090 if (tokidx >= maxerridx
2091 && tmpmsg)
2092 {
2093 maxerridx = tokidx;
2094 *errmsg = tmpmsg;
2095 }
2096 }
2097
2098 if (*pcpumatch)
2099 *pcpumatch = got_cpu_match;
2100
2101 return NULL;
2102 }
2103
2104 /* Swap operand tokens. */
2105
2106 static void
2107 swap_operand (expressionS *operand_array,
2108 unsigned source,
2109 unsigned destination)
2110 {
2111 expressionS cpy_operand;
2112 expressionS *src_operand;
2113 expressionS *dst_operand;
2114 size_t size;
2115
2116 if (source == destination)
2117 return;
2118
2119 src_operand = &operand_array[source];
2120 dst_operand = &operand_array[destination];
2121 size = sizeof (expressionS);
2122
2123 /* Make copy of operand to swap with and swap. */
2124 memcpy (&cpy_operand, dst_operand, size);
2125 memcpy (dst_operand, src_operand, size);
2126 memcpy (src_operand, &cpy_operand, size);
2127 }
2128
2129 /* Check if *op matches *tok type.
2130 Returns FALSE if they don't match, TRUE if they match. */
2131
2132 static bool
2133 pseudo_operand_match (const expressionS *tok,
2134 const struct arc_operand_operation *op)
2135 {
2136 offsetT min, max, val;
2137 bool ret;
2138 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
2139
2140 ret = false;
2141 switch (tok->X_op)
2142 {
2143 case O_constant:
2144 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
2145 ret = 1;
2146 else if (!(operand_real->flags & ARC_OPERAND_IR))
2147 {
2148 val = tok->X_add_number + op->count;
2149 if (operand_real->flags & ARC_OPERAND_SIGNED)
2150 {
2151 max = (1 << (operand_real->bits - 1)) - 1;
2152 min = -(1 << (operand_real->bits - 1));
2153 }
2154 else
2155 {
2156 max = (1 << operand_real->bits) - 1;
2157 min = 0;
2158 }
2159 if (min <= val && val <= max)
2160 ret = true;
2161 }
2162 break;
2163
2164 case O_symbol:
2165 /* Handle all symbols as long immediates or signed 9. */
2166 if (operand_real->flags & ARC_OPERAND_LIMM
2167 || ((operand_real->flags & ARC_OPERAND_SIGNED)
2168 && operand_real->bits == 9))
2169 ret = true;
2170 break;
2171
2172 case O_register:
2173 if (operand_real->flags & ARC_OPERAND_IR)
2174 ret = true;
2175 break;
2176
2177 case O_bracket:
2178 if (operand_real->flags & ARC_OPERAND_BRAKET)
2179 ret = true;
2180 break;
2181
2182 default:
2183 /* Unknown. */
2184 break;
2185 }
2186 return ret;
2187 }
2188
2189 /* Find pseudo instruction in array. */
2190
2191 static const struct arc_pseudo_insn *
2192 find_pseudo_insn (const char *opname,
2193 int ntok,
2194 const expressionS *tok)
2195 {
2196 const struct arc_pseudo_insn *pseudo_insn = NULL;
2197 const struct arc_operand_operation *op;
2198 unsigned int i;
2199 int j;
2200
2201 for (i = 0; i < arc_num_pseudo_insn; ++i)
2202 {
2203 pseudo_insn = &arc_pseudo_insns[i];
2204 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2205 {
2206 op = pseudo_insn->operand;
2207 for (j = 0; j < ntok; ++j)
2208 if (!pseudo_operand_match (&tok[j], &op[j]))
2209 break;
2210
2211 /* Found the right instruction. */
2212 if (j == ntok)
2213 return pseudo_insn;
2214 }
2215 }
2216 return NULL;
2217 }
2218
2219 /* Assumes the expressionS *tok is of sufficient size. */
2220
2221 static const struct arc_opcode_hash_entry *
2222 find_special_case_pseudo (const char *opname,
2223 int *ntok,
2224 expressionS *tok,
2225 int *nflgs,
2226 struct arc_flags *pflags)
2227 {
2228 const struct arc_pseudo_insn *pseudo_insn = NULL;
2229 const struct arc_operand_operation *operand_pseudo;
2230 const struct arc_operand *operand_real;
2231 unsigned i;
2232 char construct_operand[MAX_CONSTR_STR];
2233
2234 /* Find whether opname is in pseudo instruction array. */
2235 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2236
2237 if (pseudo_insn == NULL)
2238 return NULL;
2239
2240 /* Handle flag, Limited to one flag at the moment. */
2241 if (pseudo_insn->flag_r != NULL)
2242 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2243 MAX_INSN_FLGS - *nflgs);
2244
2245 /* Handle operand operations. */
2246 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2247 {
2248 operand_pseudo = &pseudo_insn->operand[i];
2249 operand_real = &arc_operands[operand_pseudo->operand_idx];
2250
2251 if (operand_real->flags & ARC_OPERAND_BRAKET
2252 && !operand_pseudo->needs_insert)
2253 continue;
2254
2255 /* Has to be inserted (i.e. this token does not exist yet). */
2256 if (operand_pseudo->needs_insert)
2257 {
2258 if (operand_real->flags & ARC_OPERAND_BRAKET)
2259 {
2260 tok[i].X_op = O_bracket;
2261 ++(*ntok);
2262 continue;
2263 }
2264
2265 /* Check if operand is a register or constant and handle it
2266 by type. */
2267 if (operand_real->flags & ARC_OPERAND_IR)
2268 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2269 operand_pseudo->count);
2270 else
2271 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2272 operand_pseudo->count);
2273
2274 tokenize_arguments (construct_operand, &tok[i], 1);
2275 ++(*ntok);
2276 }
2277
2278 else if (operand_pseudo->count)
2279 {
2280 /* Operand number has to be adjusted accordingly (by operand
2281 type). */
2282 switch (tok[i].X_op)
2283 {
2284 case O_constant:
2285 tok[i].X_add_number += operand_pseudo->count;
2286 break;
2287
2288 case O_symbol:
2289 break;
2290
2291 default:
2292 /* Ignored. */
2293 break;
2294 }
2295 }
2296 }
2297
2298 /* Swap operands if necessary. Only supports one swap at the
2299 moment. */
2300 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2301 {
2302 operand_pseudo = &pseudo_insn->operand[i];
2303
2304 if (operand_pseudo->swap_operand_idx == i)
2305 continue;
2306
2307 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2308
2309 /* Prevent a swap back later by breaking out. */
2310 break;
2311 }
2312
2313 return arc_find_opcode (pseudo_insn->mnemonic_r);
2314 }
2315
2316 static const struct arc_opcode_hash_entry *
2317 find_special_case_flag (const char *opname,
2318 int *nflgs,
2319 struct arc_flags *pflags)
2320 {
2321 unsigned int i;
2322 const char *flagnm;
2323 unsigned flag_idx, flag_arr_idx;
2324 size_t flaglen, oplen;
2325 const struct arc_flag_special *arc_flag_special_opcode;
2326 const struct arc_opcode_hash_entry *entry;
2327
2328 /* Search for special case instruction. */
2329 for (i = 0; i < arc_num_flag_special; i++)
2330 {
2331 arc_flag_special_opcode = &arc_flag_special_cases[i];
2332 oplen = strlen (arc_flag_special_opcode->name);
2333
2334 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2335 continue;
2336
2337 /* Found a potential special case instruction, now test for
2338 flags. */
2339 for (flag_arr_idx = 0;; ++flag_arr_idx)
2340 {
2341 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2342 if (flag_idx == 0)
2343 break; /* End of array, nothing found. */
2344
2345 flagnm = arc_flag_operands[flag_idx].name;
2346 flaglen = strlen (flagnm);
2347 if (strcmp (opname + oplen, flagnm) == 0)
2348 {
2349 entry = arc_find_opcode (arc_flag_special_opcode->name);
2350
2351 if (*nflgs + 1 > MAX_INSN_FLGS)
2352 break;
2353 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2354 pflags[*nflgs].name[flaglen] = '\0';
2355 (*nflgs)++;
2356 return entry;
2357 }
2358 }
2359 }
2360 return NULL;
2361 }
2362
2363 /* Used to find special case opcode. */
2364
2365 static const struct arc_opcode_hash_entry *
2366 find_special_case (const char *opname,
2367 int *nflgs,
2368 struct arc_flags *pflags,
2369 expressionS *tok,
2370 int *ntok)
2371 {
2372 const struct arc_opcode_hash_entry *entry;
2373
2374 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
2375
2376 if (entry == NULL)
2377 entry = find_special_case_flag (opname, nflgs, pflags);
2378
2379 return entry;
2380 }
2381
2382 /* Autodetect cpu attribute list. */
2383
2384 static void
2385 autodetect_attributes (const struct arc_opcode *opcode,
2386 const expressionS *tok,
2387 int ntok)
2388 {
2389 unsigned i;
2390 struct mpy_type
2391 {
2392 unsigned feature;
2393 unsigned encoding;
2394 } mpy_list[] = {{ MPY1E, 1 }, { MPY6E, 6 }, { MPY7E, 7 }, { MPY8E, 8 },
2395 { MPY9E, 9 }};
2396
2397 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
2398 if (opcode->subclass == feature_list[i].feature)
2399 selected_cpu.features |= feature_list[i].feature;
2400
2401 for (i = 0; i < ARRAY_SIZE (mpy_list); i++)
2402 if (opcode->subclass == mpy_list[i].feature)
2403 mpy_option = mpy_list[i].encoding;
2404
2405 for (i = 0; i < (unsigned) ntok; i++)
2406 {
2407 switch (tok[i].X_md)
2408 {
2409 case O_gotoff:
2410 case O_gotpc:
2411 case O_plt:
2412 pic_option = 2;
2413 break;
2414 case O_sda:
2415 sda_option = 2;
2416 break;
2417 case O_tlsgd:
2418 case O_tlsie:
2419 case O_tpoff9:
2420 case O_tpoff:
2421 case O_dtpoff9:
2422 case O_dtpoff:
2423 tls_option = 1;
2424 break;
2425 default:
2426 break;
2427 }
2428
2429 switch (tok[i].X_op)
2430 {
2431 case O_register:
2432 if ((tok[i].X_add_number >= 4 && tok[i].X_add_number <= 9)
2433 || (tok[i].X_add_number >= 16 && tok[i].X_add_number <= 25))
2434 rf16_only = false;
2435 break;
2436 default:
2437 break;
2438 }
2439 }
2440 }
2441
2442 /* Given an opcode name, pre-tockenized set of argumenst and the
2443 opcode flags, take it all the way through emission. */
2444
2445 static void
2446 assemble_tokens (const char *opname,
2447 expressionS *tok,
2448 int ntok,
2449 struct arc_flags *pflags,
2450 int nflgs)
2451 {
2452 bool found_something = false;
2453 const struct arc_opcode_hash_entry *entry;
2454 int cpumatch = 1;
2455 const char *errmsg = NULL;
2456
2457 /* Search opcodes. */
2458 entry = arc_find_opcode (opname);
2459
2460 /* Couldn't find opcode conventional way, try special cases. */
2461 if (entry == NULL)
2462 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
2463
2464 if (entry != NULL)
2465 {
2466 const struct arc_opcode *opcode;
2467
2468 pr_debug ("%s:%d: assemble_tokens: %s\n",
2469 frag_now->fr_file, frag_now->fr_line, opname);
2470 found_something = true;
2471 opcode = find_opcode_match (entry, tok, &ntok, pflags,
2472 nflgs, &cpumatch, &errmsg);
2473 if (opcode != NULL)
2474 {
2475 struct arc_insn insn;
2476
2477 autodetect_attributes (opcode, tok, ntok);
2478 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2479 emit_insn (&insn);
2480 return;
2481 }
2482 }
2483
2484 if (found_something)
2485 {
2486 if (cpumatch)
2487 if (errmsg)
2488 as_bad (_("%s for instruction '%s'"), errmsg, opname);
2489 else
2490 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
2491 else
2492 as_bad (_("opcode '%s' not supported for target %s"), opname,
2493 selected_cpu.name);
2494 }
2495 else
2496 as_bad (_("unknown opcode '%s'"), opname);
2497 }
2498
2499 /* The public interface to the instruction assembler. */
2500
2501 void
2502 md_assemble (char *str)
2503 {
2504 char *opname;
2505 expressionS tok[MAX_INSN_ARGS];
2506 int ntok, nflg;
2507 size_t opnamelen;
2508 struct arc_flags flags[MAX_INSN_FLGS];
2509
2510 /* Split off the opcode. */
2511 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
2512 opname = xmemdup0 (str, opnamelen);
2513
2514 /* Signalize we are assembling the instructions. */
2515 assembling_insn = true;
2516
2517 /* Tokenize the flags. */
2518 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2519 {
2520 as_bad (_("syntax error"));
2521 return;
2522 }
2523
2524 /* Scan up to the end of the mnemonic which must end in space or end
2525 of string. */
2526 str += opnamelen;
2527 for (; *str != '\0'; str++)
2528 if (*str == ' ')
2529 break;
2530
2531 /* Tokenize the rest of the line. */
2532 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
2533 {
2534 as_bad (_("syntax error"));
2535 return;
2536 }
2537
2538 /* Finish it off. */
2539 assemble_tokens (opname, tok, ntok, flags, nflg);
2540 assembling_insn = false;
2541 }
2542
2543 /* Callback to insert a register into the hash table. */
2544
2545 static void
2546 declare_register (const char *name, int number)
2547 {
2548 symbolS *regS = symbol_create (name, reg_section,
2549 &zero_address_frag, number);
2550
2551 if (str_hash_insert (arc_reg_hash, S_GET_NAME (regS), regS, 0) != NULL)
2552 as_fatal (_("duplicate %s"), name);
2553 }
2554
2555 /* Construct symbols for each of the general registers. */
2556
2557 static void
2558 declare_register_set (void)
2559 {
2560 int i;
2561 for (i = 0; i < 64; ++i)
2562 {
2563 char name[32];
2564
2565 sprintf (name, "r%d", i);
2566 declare_register (name, i);
2567 if ((i & 0x01) == 0)
2568 {
2569 sprintf (name, "r%dr%d", i, i+1);
2570 declare_register (name, i);
2571 }
2572 }
2573 }
2574
2575 /* Construct a symbol for an address type. */
2576
2577 static void
2578 declare_addrtype (const char *name, int number)
2579 {
2580 symbolS *addrtypeS = symbol_create (name, undefined_section,
2581 &zero_address_frag, number);
2582
2583 if (str_hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS), addrtypeS, 0))
2584 as_fatal (_("duplicate %s"), name);
2585 }
2586
2587 /* Port-specific assembler initialization. This function is called
2588 once, at assembler startup time. */
2589
2590 void
2591 md_begin (void)
2592 {
2593 const struct arc_opcode *opcode = arc_opcodes;
2594
2595 if (mach_selection_mode == MACH_SELECTION_NONE)
2596 arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
2597
2598 /* The endianness can be chosen "at the factory". */
2599 target_big_endian = byte_order == BIG_ENDIAN;
2600
2601 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
2602 as_warn (_("could not set architecture and machine"));
2603
2604 /* Set elf header flags. */
2605 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
2606
2607 /* Set up a hash table for the instructions. */
2608 arc_opcode_hash = str_htab_create ();
2609
2610 /* Initialize the hash table with the insns. */
2611 do
2612 {
2613 const char *name = opcode->name;
2614
2615 arc_insert_opcode (opcode);
2616
2617 while (++opcode && opcode->name
2618 && (opcode->name == name
2619 || !strcmp (opcode->name, name)))
2620 continue;
2621 }while (opcode->name);
2622
2623 /* Register declaration. */
2624 arc_reg_hash = str_htab_create ();
2625
2626 declare_register_set ();
2627 declare_register ("gp", 26);
2628 declare_register ("fp", 27);
2629 declare_register ("sp", 28);
2630 declare_register ("ilink", 29);
2631 declare_register ("ilink1", 29);
2632 declare_register ("ilink2", 30);
2633 declare_register ("blink", 31);
2634
2635 /* XY memory registers. */
2636 declare_register ("x0_u0", 32);
2637 declare_register ("x0_u1", 33);
2638 declare_register ("x1_u0", 34);
2639 declare_register ("x1_u1", 35);
2640 declare_register ("x2_u0", 36);
2641 declare_register ("x2_u1", 37);
2642 declare_register ("x3_u0", 38);
2643 declare_register ("x3_u1", 39);
2644 declare_register ("y0_u0", 40);
2645 declare_register ("y0_u1", 41);
2646 declare_register ("y1_u0", 42);
2647 declare_register ("y1_u1", 43);
2648 declare_register ("y2_u0", 44);
2649 declare_register ("y2_u1", 45);
2650 declare_register ("y3_u0", 46);
2651 declare_register ("y3_u1", 47);
2652 declare_register ("x0_nu", 48);
2653 declare_register ("x1_nu", 49);
2654 declare_register ("x2_nu", 50);
2655 declare_register ("x3_nu", 51);
2656 declare_register ("y0_nu", 52);
2657 declare_register ("y1_nu", 53);
2658 declare_register ("y2_nu", 54);
2659 declare_register ("y3_nu", 55);
2660
2661 declare_register ("mlo", 57);
2662 declare_register ("mmid", 58);
2663 declare_register ("mhi", 59);
2664
2665 declare_register ("acc1", 56);
2666 declare_register ("acc2", 57);
2667
2668 declare_register ("lp_count", 60);
2669 declare_register ("pcl", 63);
2670
2671 /* Initialize the last instructions. */
2672 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
2673
2674 /* Aux register declaration. */
2675 arc_aux_hash = str_htab_create ();
2676
2677 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2678 unsigned int i;
2679 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2680 {
2681 if (!(auxr->cpu & selected_cpu.flags))
2682 continue;
2683
2684 if ((auxr->subclass != NONE)
2685 && !check_cpu_feature (auxr->subclass))
2686 continue;
2687
2688 if (str_hash_insert (arc_aux_hash, auxr->name, auxr, 0) != 0)
2689 as_fatal (_("duplicate %s"), auxr->name);
2690 }
2691
2692 /* Address type declaration. */
2693 arc_addrtype_hash = str_htab_create ();
2694
2695 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
2696 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
2697 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
2698 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
2699 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
2700 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
2701 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
2702 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
2703 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
2704 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
2705 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
2706 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
2707 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
2708 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
2709 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
2710 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
2711 }
2712
2713 /* Write a value out to the object file, using the appropriate
2714 endianness. */
2715
2716 void
2717 md_number_to_chars (char *buf,
2718 valueT val,
2719 int n)
2720 {
2721 if (target_big_endian)
2722 number_to_chars_bigendian (buf, val, n);
2723 else
2724 number_to_chars_littleendian (buf, val, n);
2725 }
2726
2727 /* Round up a section size to the appropriate boundary. */
2728
2729 valueT
2730 md_section_align (segT segment,
2731 valueT size)
2732 {
2733 int align = bfd_section_alignment (segment);
2734
2735 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
2736 }
2737
2738 /* The location from which a PC relative jump should be calculated,
2739 given a PC relative reloc. */
2740
2741 long
2742 md_pcrel_from_section (fixS *fixP,
2743 segT sec)
2744 {
2745 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
2746
2747 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
2748
2749 if (fixP->fx_addsy != (symbolS *) NULL
2750 && (!S_IS_DEFINED (fixP->fx_addsy)
2751 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2752 {
2753 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
2754
2755 /* The symbol is undefined (or is defined but not in this section).
2756 Let the linker figure it out. */
2757 return 0;
2758 }
2759
2760 if ((int) fixP->fx_r_type < 0)
2761 {
2762 /* These are the "internal" relocations. Align them to
2763 32 bit boundary (PCL), for the moment. */
2764 base &= ~3;
2765 }
2766 else
2767 {
2768 switch (fixP->fx_r_type)
2769 {
2770 case BFD_RELOC_ARC_PC32:
2771 /* The hardware calculates relative to the start of the
2772 insn, but this relocation is relative to location of the
2773 LIMM, compensate. The base always needs to be
2774 subtracted by 4 as we do not support this type of PCrel
2775 relocation for short instructions. */
2776 base -= 4;
2777 /* Fall through. */
2778 case BFD_RELOC_ARC_PLT32:
2779 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2780 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2781 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2782 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2783
2784 case BFD_RELOC_ARC_S21H_PCREL:
2785 case BFD_RELOC_ARC_S25H_PCREL:
2786 case BFD_RELOC_ARC_S13_PCREL:
2787 case BFD_RELOC_ARC_S21W_PCREL:
2788 case BFD_RELOC_ARC_S25W_PCREL:
2789 base &= ~3;
2790 break;
2791 default:
2792 as_bad_where (fixP->fx_file, fixP->fx_line,
2793 _("unhandled reloc %s in md_pcrel_from_section"),
2794 bfd_get_reloc_code_name (fixP->fx_r_type));
2795 break;
2796 }
2797 }
2798
2799 pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, "
2800 "symbol: %s (%"BFD_VMA_FMT"x)\n",
2801 fixP->fx_frag->fr_address, fixP->fx_where, base,
2802 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2803 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2804
2805 return base;
2806 }
2807
2808 /* Given a BFD relocation find the corresponding operand. */
2809
2810 static const struct arc_operand *
2811 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2812 {
2813 unsigned i;
2814
2815 for (i = 0; i < arc_num_operands; i++)
2816 if (arc_operands[i].default_reloc == reloc)
2817 return &arc_operands[i];
2818 return NULL;
2819 }
2820
2821 /* Insert an operand value into an instruction. */
2822
2823 static unsigned long long
2824 insert_operand (unsigned long long insn,
2825 const struct arc_operand *operand,
2826 long long val,
2827 const char *file,
2828 unsigned line)
2829 {
2830 offsetT min = 0, max = 0;
2831
2832 if (operand->bits != 32
2833 && !(operand->flags & ARC_OPERAND_NCHK)
2834 && !(operand->flags & ARC_OPERAND_FAKE))
2835 {
2836 if (operand->flags & ARC_OPERAND_SIGNED)
2837 {
2838 max = (1 << (operand->bits - 1)) - 1;
2839 min = -(1 << (operand->bits - 1));
2840 }
2841 else
2842 {
2843 max = (1 << operand->bits) - 1;
2844 min = 0;
2845 }
2846
2847 if (val < min || val > max)
2848 as_bad_value_out_of_range (_("operand"),
2849 val, min, max, file, line);
2850 }
2851
2852 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
2853 min, val, max, insn);
2854
2855 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2856 && (val & 0x03))
2857 as_bad_where (file, line,
2858 _("Unaligned operand. Needs to be 32bit aligned"));
2859
2860 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2861 && (val & 0x01))
2862 as_bad_where (file, line,
2863 _("Unaligned operand. Needs to be 16bit aligned"));
2864
2865 if (operand->insert)
2866 {
2867 const char *errmsg = NULL;
2868
2869 insn = (*operand->insert) (insn, val, &errmsg);
2870 if (errmsg)
2871 as_warn_where (file, line, "%s", errmsg);
2872 }
2873 else
2874 {
2875 if (operand->flags & ARC_OPERAND_TRUNCATE)
2876 {
2877 if (operand->flags & ARC_OPERAND_ALIGNED32)
2878 val >>= 2;
2879 if (operand->flags & ARC_OPERAND_ALIGNED16)
2880 val >>= 1;
2881 }
2882 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2883 }
2884 return insn;
2885 }
2886
2887 /* Apply a fixup to the object code. At this point all symbol values
2888 should be fully resolved, and we attempt to completely resolve the
2889 reloc. If we can not do that, we determine the correct reloc code
2890 and put it back in the fixup. To indicate that a fixup has been
2891 eliminated, set fixP->fx_done. */
2892
2893 void
2894 md_apply_fix (fixS *fixP,
2895 valueT *valP,
2896 segT seg)
2897 {
2898 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2899 valueT value = *valP;
2900 unsigned insn = 0;
2901 symbolS *fx_addsy, *fx_subsy;
2902 offsetT fx_offset;
2903 segT add_symbol_segment = absolute_section;
2904 segT sub_symbol_segment = absolute_section;
2905 const struct arc_operand *operand = NULL;
2906 extended_bfd_reloc_code_real_type reloc;
2907
2908 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2909 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2910 ((int) fixP->fx_r_type < 0) ? "Internal":
2911 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2912 fixP->fx_offset);
2913
2914 fx_addsy = fixP->fx_addsy;
2915 fx_subsy = fixP->fx_subsy;
2916 fx_offset = 0;
2917
2918 if (fx_addsy)
2919 {
2920 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
2921 }
2922
2923 if (fx_subsy
2924 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2925 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2926 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2927 {
2928 resolve_symbol_value (fx_subsy);
2929 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
2930
2931 if (sub_symbol_segment == absolute_section)
2932 {
2933 /* The symbol is really a constant. */
2934 fx_offset -= S_GET_VALUE (fx_subsy);
2935 fx_subsy = NULL;
2936 }
2937 else
2938 {
2939 as_bad_where (fixP->fx_file, fixP->fx_line,
2940 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2941 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2942 segment_name (add_symbol_segment),
2943 S_GET_NAME (fx_subsy),
2944 segment_name (sub_symbol_segment));
2945 return;
2946 }
2947 }
2948
2949 if (fx_addsy
2950 && !S_IS_WEAK (fx_addsy))
2951 {
2952 if (add_symbol_segment == seg
2953 && fixP->fx_pcrel)
2954 {
2955 value += S_GET_VALUE (fx_addsy);
2956 value -= md_pcrel_from_section (fixP, seg);
2957 fx_addsy = NULL;
2958 fixP->fx_pcrel = false;
2959 }
2960 else if (add_symbol_segment == absolute_section)
2961 {
2962 value = fixP->fx_offset;
2963 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2964 fx_addsy = NULL;
2965 fixP->fx_pcrel = false;
2966 }
2967 }
2968
2969 if (!fx_addsy)
2970 fixP->fx_done = true;
2971
2972 if (fixP->fx_pcrel)
2973 {
2974 if (fx_addsy
2975 && ((S_IS_DEFINED (fx_addsy)
2976 && S_GET_SEGMENT (fx_addsy) != seg)
2977 || S_IS_WEAK (fx_addsy)))
2978 value += md_pcrel_from_section (fixP, seg);
2979
2980 switch (fixP->fx_r_type)
2981 {
2982 case BFD_RELOC_ARC_32_ME:
2983 /* This is a pc-relative value in a LIMM. Adjust it to the
2984 address of the instruction not to the address of the
2985 LIMM. Note: it is not any longer valid this affirmation as
2986 the linker consider ARC_PC32 a fixup to entire 64 bit
2987 insn. */
2988 fixP->fx_offset += fixP->fx_frag->fr_address;
2989 /* Fall through. */
2990 case BFD_RELOC_32:
2991 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2992 /* Fall through. */
2993 case BFD_RELOC_ARC_PC32:
2994 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2995 break;
2996 default:
2997 if ((int) fixP->fx_r_type < 0)
2998 as_bad_where (fixP->fx_file, fixP->fx_line,
2999 _("PC relative relocation not allowed for (internal)"
3000 " type %d"),
3001 fixP->fx_r_type);
3002 break;
3003 }
3004 }
3005
3006 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
3007 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
3008 ((int) fixP->fx_r_type < 0) ? "Internal":
3009 bfd_get_reloc_code_name (fixP->fx_r_type), value,
3010 fixP->fx_offset);
3011
3012
3013 /* Now check for TLS relocations. */
3014 reloc = fixP->fx_r_type;
3015 switch (reloc)
3016 {
3017 case BFD_RELOC_ARC_TLS_DTPOFF:
3018 case BFD_RELOC_ARC_TLS_LE_32:
3019 if (fixP->fx_done)
3020 break;
3021 /* Fall through. */
3022 case BFD_RELOC_ARC_TLS_GD_GOT:
3023 case BFD_RELOC_ARC_TLS_IE_GOT:
3024 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3025 break;
3026
3027 case BFD_RELOC_ARC_TLS_GD_LD:
3028 gas_assert (!fixP->fx_offset);
3029 if (fixP->fx_subsy)
3030 fixP->fx_offset
3031 = (S_GET_VALUE (fixP->fx_subsy)
3032 - fixP->fx_frag->fr_address- fixP->fx_where);
3033 fixP->fx_subsy = NULL;
3034 /* Fall through. */
3035 case BFD_RELOC_ARC_TLS_GD_CALL:
3036 /* These two relocs are there just to allow ld to change the tls
3037 model for this symbol, by patching the code. The offset -
3038 and scale, if any - will be installed by the linker. */
3039 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3040 break;
3041
3042 case BFD_RELOC_ARC_TLS_LE_S9:
3043 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
3044 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3045 break;
3046
3047 default:
3048 break;
3049 }
3050
3051 if (!fixP->fx_done)
3052 {
3053 return;
3054 }
3055
3056 /* Adjust the value if we have a constant. */
3057 value += fx_offset;
3058
3059 /* For hosts with longs bigger than 32-bits make sure that the top
3060 bits of a 32-bit negative value read in by the parser are set,
3061 so that the correct comparisons are made. */
3062 if (value & 0x80000000)
3063 value |= (-1UL << 31);
3064
3065 reloc = fixP->fx_r_type;
3066 switch (reloc)
3067 {
3068 case BFD_RELOC_8:
3069 case BFD_RELOC_16:
3070 case BFD_RELOC_24:
3071 case BFD_RELOC_32:
3072 case BFD_RELOC_64:
3073 case BFD_RELOC_ARC_32_PCREL:
3074 md_number_to_chars (fixpos, value, fixP->fx_size);
3075 return;
3076
3077 case BFD_RELOC_ARC_GOTPC32:
3078 /* I cannot fix an GOTPC relocation because I need to relax it
3079 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3080 as_bad (_("Unsupported operation on reloc"));
3081 return;
3082
3083 case BFD_RELOC_ARC_TLS_DTPOFF:
3084 case BFD_RELOC_ARC_TLS_LE_32:
3085 gas_assert (!fixP->fx_addsy);
3086 gas_assert (!fixP->fx_subsy);
3087 /* Fall through. */
3088
3089 case BFD_RELOC_ARC_GOTOFF:
3090 case BFD_RELOC_ARC_32_ME:
3091 case BFD_RELOC_ARC_PC32:
3092 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3093 return;
3094
3095 case BFD_RELOC_ARC_PLT32:
3096 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3097 return;
3098
3099 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3100 reloc = BFD_RELOC_ARC_S25W_PCREL;
3101 goto solve_plt;
3102
3103 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3104 reloc = BFD_RELOC_ARC_S21H_PCREL;
3105 goto solve_plt;
3106
3107 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3108 reloc = BFD_RELOC_ARC_S25W_PCREL;
3109 goto solve_plt;
3110
3111 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3112 reloc = BFD_RELOC_ARC_S21W_PCREL;
3113 /* Fall through. */
3114
3115 case BFD_RELOC_ARC_S25W_PCREL:
3116 case BFD_RELOC_ARC_S21W_PCREL:
3117 case BFD_RELOC_ARC_S21H_PCREL:
3118 case BFD_RELOC_ARC_S25H_PCREL:
3119 case BFD_RELOC_ARC_S13_PCREL:
3120 solve_plt:
3121 operand = find_operand_for_reloc (reloc);
3122 gas_assert (operand);
3123 break;
3124
3125 default:
3126 {
3127 if ((int) fixP->fx_r_type >= 0)
3128 as_fatal (_("unhandled relocation type %s"),
3129 bfd_get_reloc_code_name (fixP->fx_r_type));
3130
3131 /* The rest of these fixups needs to be completely resolved as
3132 constants. */
3133 if (fixP->fx_addsy != 0
3134 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
3135 as_bad_where (fixP->fx_file, fixP->fx_line,
3136 _("non-absolute expression in constant field"));
3137
3138 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
3139 operand = &arc_operands[-(int) fixP->fx_r_type];
3140 break;
3141 }
3142 }
3143
3144 if (target_big_endian)
3145 {
3146 switch (fixP->fx_size)
3147 {
3148 case 4:
3149 insn = bfd_getb32 (fixpos);
3150 break;
3151 case 2:
3152 insn = bfd_getb16 (fixpos);
3153 break;
3154 default:
3155 as_bad_where (fixP->fx_file, fixP->fx_line,
3156 _("unknown fixup size"));
3157 }
3158 }
3159 else
3160 {
3161 insn = 0;
3162 switch (fixP->fx_size)
3163 {
3164 case 4:
3165 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
3166 break;
3167 case 2:
3168 insn = bfd_getl16 (fixpos);
3169 break;
3170 default:
3171 as_bad_where (fixP->fx_file, fixP->fx_line,
3172 _("unknown fixup size"));
3173 }
3174 }
3175
3176 insn = insert_operand (insn, operand, (offsetT) value,
3177 fixP->fx_file, fixP->fx_line);
3178
3179 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
3180 }
3181
3182 /* Prepare machine-dependent frags for relaxation.
3183
3184 Called just before relaxation starts. Any symbol that is now undefined
3185 will not become defined.
3186
3187 Return the correct fr_subtype in the frag.
3188
3189 Return the initial "guess for fr_var" to caller. The guess for fr_var
3190 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3191 or fr_var contributes to our returned value.
3192
3193 Although it may not be explicit in the frag, pretend
3194 fr_var starts with a value. */
3195
3196 int
3197 md_estimate_size_before_relax (fragS *fragP,
3198 segT segment)
3199 {
3200 int growth;
3201
3202 /* If the symbol is not located within the same section AND it's not
3203 an absolute section, use the maximum. OR if the symbol is a
3204 constant AND the insn is by nature not pc-rel, use the maximum.
3205 OR if the symbol is being equated against another symbol, use the
3206 maximum. OR if the symbol is weak use the maximum. */
3207 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
3208 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
3209 || (symbol_constant_p (fragP->fr_symbol)
3210 && !fragP->tc_frag_data.pcrel)
3211 || symbol_equated_p (fragP->fr_symbol)
3212 || S_IS_WEAK (fragP->fr_symbol))
3213 {
3214 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
3215 ++fragP->fr_subtype;
3216 }
3217
3218 growth = md_relax_table[fragP->fr_subtype].rlx_length;
3219 fragP->fr_var = growth;
3220
3221 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3222 fragP->fr_file, fragP->fr_line, growth);
3223
3224 return growth;
3225 }
3226
3227 /* Translate internal representation of relocation info to BFD target
3228 format. */
3229
3230 arelent *
3231 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
3232 fixS *fixP)
3233 {
3234 arelent *reloc;
3235 bfd_reloc_code_real_type code;
3236
3237 reloc = XNEW (arelent);
3238 reloc->sym_ptr_ptr = XNEW (asymbol *);
3239 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3240 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
3241
3242 /* Make sure none of our internal relocations make it this far.
3243 They'd better have been fully resolved by this point. */
3244 gas_assert ((int) fixP->fx_r_type > 0);
3245
3246 code = fixP->fx_r_type;
3247
3248 /* if we have something like add gp, pcl,
3249 _GLOBAL_OFFSET_TABLE_@gotpc. */
3250 if (code == BFD_RELOC_ARC_GOTPC32
3251 && GOT_symbol
3252 && fixP->fx_addsy == GOT_symbol)
3253 code = BFD_RELOC_ARC_GOTPC;
3254
3255 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3256 if (reloc->howto == NULL)
3257 {
3258 as_bad_where (fixP->fx_file, fixP->fx_line,
3259 _("cannot represent `%s' relocation in object file"),
3260 bfd_get_reloc_code_name (code));
3261 return NULL;
3262 }
3263
3264 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
3265 as_fatal (_("internal error? cannot generate `%s' relocation"),
3266 bfd_get_reloc_code_name (code));
3267
3268 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
3269
3270 reloc->addend = fixP->fx_offset;
3271
3272 return reloc;
3273 }
3274
3275 /* Perform post-processing of machine-dependent frags after relaxation.
3276 Called after relaxation is finished.
3277 In: Address of frag.
3278 fr_type == rs_machine_dependent.
3279 fr_subtype is what the address relaxed to.
3280
3281 Out: Any fixS:s and constants are set up. */
3282
3283 void
3284 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3285 segT segment ATTRIBUTE_UNUSED,
3286 fragS *fragP)
3287 {
3288 const relax_typeS *table_entry;
3289 char *dest;
3290 const struct arc_opcode *opcode;
3291 struct arc_insn insn;
3292 int size, fix;
3293 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
3294
3295 fix = fragP->fr_fix;
3296 dest = fragP->fr_literal + fix;
3297 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
3298
3299 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3300 "var: %"BFD_VMA_FMT"d\n",
3301 fragP->fr_file, fragP->fr_line,
3302 fragP->fr_subtype, fix, fragP->fr_var);
3303
3304 if (fragP->fr_subtype <= 0
3305 && fragP->fr_subtype >= arc_num_relax_opcodes)
3306 as_fatal (_("no relaxation found for this instruction."));
3307
3308 opcode = &arc_relax_opcodes[fragP->fr_subtype];
3309
3310 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3311 relax_arg->nflg, &insn);
3312
3313 apply_fixups (&insn, fragP, fix);
3314
3315 size = insn.len + (insn.has_limm ? 4 : 0);
3316 gas_assert (table_entry->rlx_length == size);
3317 emit_insn0 (&insn, dest, true);
3318
3319 fragP->fr_fix += table_entry->rlx_length;
3320 fragP->fr_var = 0;
3321 }
3322
3323 /* We have no need to default values of symbols. We could catch
3324 register names here, but that is handled by inserting them all in
3325 the symbol table to begin with. */
3326
3327 symbolS *
3328 md_undefined_symbol (char *name)
3329 {
3330 /* The arc abi demands that a GOT[0] should be referencible as
3331 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3332 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3333 if (((*name == '_')
3334 && (*(name+1) == 'G')
3335 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)))
3336 {
3337 if (!GOT_symbol)
3338 {
3339 if (symbol_find (name))
3340 as_bad ("GOT already in symbol table");
3341
3342 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
3343 &zero_address_frag, 0);
3344 };
3345 return GOT_symbol;
3346 }
3347 return NULL;
3348 }
3349
3350 /* Turn a string in input_line_pointer into a floating point constant
3351 of type type, and store the appropriate bytes in *litP. The number
3352 of LITTLENUMS emitted is stored in *sizeP. An error message is
3353 returned, or NULL on OK. */
3354
3355 const char *
3356 md_atof (int type, char *litP, int *sizeP)
3357 {
3358 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3359 }
3360
3361 /* Called for any expression that can not be recognized. When the
3362 function is called, `input_line_pointer' will point to the start of
3363 the expression. We use it when we have complex operations like
3364 @label1 - @label2. */
3365
3366 void
3367 md_operand (expressionS *expressionP)
3368 {
3369 char *p = input_line_pointer;
3370 if (*p == '@')
3371 {
3372 input_line_pointer++;
3373 expressionP->X_op = O_symbol;
3374 expressionP->X_md = O_absent;
3375 expression (expressionP);
3376 }
3377 }
3378
3379 /* This function is called from the function 'expression', it attempts
3380 to parse special names (in our case register names). It fills in
3381 the expression with the identified register. It returns TRUE if
3382 it is a register and FALSE otherwise. */
3383
3384 bool
3385 arc_parse_name (const char *name,
3386 struct expressionS *e)
3387 {
3388 struct symbol *sym;
3389
3390 if (!assembling_insn)
3391 return false;
3392
3393 if (e->X_op == O_symbol
3394 && e->X_md == O_absent)
3395 return false;
3396
3397 sym = str_hash_find (arc_reg_hash, name);
3398 if (sym)
3399 {
3400 e->X_op = O_register;
3401 e->X_add_number = S_GET_VALUE (sym);
3402 return true;
3403 }
3404
3405 sym = str_hash_find (arc_addrtype_hash, name);
3406 if (sym)
3407 {
3408 e->X_op = O_addrtype;
3409 e->X_add_number = S_GET_VALUE (sym);
3410 return true;
3411 }
3412
3413 return false;
3414 }
3415
3416 /* md_parse_option
3417 Invocation line includes a switch not recognized by the base assembler.
3418 See if it's a processor-specific option.
3419
3420 New options (supported) are:
3421
3422 -mcpu=<cpu name> Assemble for selected processor
3423 -EB/-mbig-endian Big-endian
3424 -EL/-mlittle-endian Little-endian
3425 -mrelax Enable relaxation
3426
3427 The following CPU names are recognized:
3428 arc600, arc700, arcem, archs, nps400. */
3429
3430 int
3431 md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
3432 {
3433 switch (c)
3434 {
3435 case OPTION_ARC600:
3436 case OPTION_ARC601:
3437 return md_parse_option (OPTION_MCPU, "arc600");
3438
3439 case OPTION_ARC700:
3440 return md_parse_option (OPTION_MCPU, "arc700");
3441
3442 case OPTION_ARCEM:
3443 return md_parse_option (OPTION_MCPU, "arcem");
3444
3445 case OPTION_ARCHS:
3446 return md_parse_option (OPTION_MCPU, "archs");
3447
3448 case OPTION_MCPU:
3449 {
3450 arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
3451 break;
3452 }
3453
3454 case OPTION_EB:
3455 arc_target_format = "elf32-bigarc";
3456 byte_order = BIG_ENDIAN;
3457 break;
3458
3459 case OPTION_EL:
3460 arc_target_format = "elf32-littlearc";
3461 byte_order = LITTLE_ENDIAN;
3462 break;
3463
3464 case OPTION_CD:
3465 selected_cpu.features |= CD;
3466 cl_features |= CD;
3467 arc_check_feature ();
3468 break;
3469
3470 case OPTION_RELAX:
3471 relaxation_state = 1;
3472 break;
3473
3474 case OPTION_NPS400:
3475 selected_cpu.features |= NPS400;
3476 cl_features |= NPS400;
3477 arc_check_feature ();
3478 break;
3479
3480 case OPTION_SPFP:
3481 selected_cpu.features |= SPX;
3482 cl_features |= SPX;
3483 arc_check_feature ();
3484 break;
3485
3486 case OPTION_DPFP:
3487 selected_cpu.features |= DPX;
3488 cl_features |= DPX;
3489 arc_check_feature ();
3490 break;
3491
3492 case OPTION_FPUDA:
3493 selected_cpu.features |= DPA;
3494 cl_features |= DPA;
3495 arc_check_feature ();
3496 break;
3497
3498 /* Dummy options are accepted but have no effect. */
3499 case OPTION_USER_MODE:
3500 case OPTION_LD_EXT_MASK:
3501 case OPTION_SWAP:
3502 case OPTION_NORM:
3503 case OPTION_BARREL_SHIFT:
3504 case OPTION_MIN_MAX:
3505 case OPTION_NO_MPY:
3506 case OPTION_EA:
3507 case OPTION_MUL64:
3508 case OPTION_SIMD:
3509 case OPTION_XMAC_D16:
3510 case OPTION_XMAC_24:
3511 case OPTION_DSP_PACKA:
3512 case OPTION_CRC:
3513 case OPTION_DVBF:
3514 case OPTION_TELEPHONY:
3515 case OPTION_XYMEMORY:
3516 case OPTION_LOCK:
3517 case OPTION_SWAPE:
3518 case OPTION_RTSC:
3519 break;
3520
3521 default:
3522 return 0;
3523 }
3524
3525 return 1;
3526 }
3527
3528 /* Display the list of cpu names for use in the help text. */
3529
3530 static void
3531 arc_show_cpu_list (FILE *stream)
3532 {
3533 int i, offset;
3534 static const char *space_buf = " ";
3535
3536 fprintf (stream, "%s", space_buf);
3537 offset = strlen (space_buf);
3538 for (i = 0; cpu_types[i].name != NULL; ++i)
3539 {
3540 bool last = (cpu_types[i + 1].name == NULL);
3541
3542 /* If displaying the new cpu name string, and the ', ' (for all
3543 but the last one) will take us past a target width of 80
3544 characters, then it's time for a new line. */
3545 if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80)
3546 {
3547 fprintf (stream, "\n%s", space_buf);
3548 offset = strlen (space_buf);
3549 }
3550
3551 fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", "));
3552 offset += strlen (cpu_types [i].name) + (last ? 0 : 2);
3553 }
3554 }
3555
3556 void
3557 md_show_usage (FILE *stream)
3558 {
3559 fprintf (stream, _("ARC-specific assembler options:\n"));
3560
3561 fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for"
3562 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU);
3563 arc_show_cpu_list (stream);
3564 fprintf (stream, "\n");
3565 fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3566 fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3567 fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
3568 fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
3569
3570 fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
3571 fprintf (stream, " -mspfp\t\t enable single-precision floating point"
3572 " instructions\n");
3573 fprintf (stream, " -mdpfp\t\t enable double-precision floating point"
3574 " instructions\n");
3575 fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
3576 "point\n\t\t\t instructions for ARC EM\n");
3577
3578 fprintf (stream,
3579 " -mcode-density\t enable code density option for ARC EM\n");
3580
3581 fprintf (stream, _("\
3582 -EB assemble code for a big-endian cpu\n"));
3583 fprintf (stream, _("\
3584 -EL assemble code for a little-endian cpu\n"));
3585 fprintf (stream, _("\
3586 -mrelax enable relaxation\n"));
3587
3588 fprintf (stream, _("The following ARC-specific assembler options are "
3589 "deprecated and are accepted\nfor compatibility only:\n"));
3590
3591 fprintf (stream, _(" -mEA\n"
3592 " -mbarrel-shifter\n"
3593 " -mbarrel_shifter\n"
3594 " -mcrc\n"
3595 " -mdsp-packa\n"
3596 " -mdsp_packa\n"
3597 " -mdvbf\n"
3598 " -mld-extension-reg-mask\n"
3599 " -mlock\n"
3600 " -mmac-24\n"
3601 " -mmac-d16\n"
3602 " -mmac_24\n"
3603 " -mmac_d16\n"
3604 " -mmin-max\n"
3605 " -mmin_max\n"
3606 " -mmul64\n"
3607 " -mno-mpy\n"
3608 " -mnorm\n"
3609 " -mrtsc\n"
3610 " -msimd\n"
3611 " -mswap\n"
3612 " -mswape\n"
3613 " -mtelephony\n"
3614 " -muser-mode-only\n"
3615 " -mxy\n"));
3616 }
3617
3618 /* Find the proper relocation for the given opcode. */
3619
3620 static extended_bfd_reloc_code_real_type
3621 find_reloc (const char *name,
3622 const char *opcodename,
3623 const struct arc_flags *pflags,
3624 int nflg,
3625 extended_bfd_reloc_code_real_type reloc)
3626 {
3627 unsigned int i;
3628 int j;
3629 bool found_flag, tmp;
3630 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3631
3632 for (i = 0; i < arc_num_equiv_tab; i++)
3633 {
3634 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3635
3636 /* Find the entry. */
3637 if (strcmp (name, r->name))
3638 continue;
3639 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3640 continue;
3641 if (r->flags[0])
3642 {
3643 if (!nflg)
3644 continue;
3645 found_flag = false;
3646 unsigned * psflg = (unsigned *)r->flags;
3647 do
3648 {
3649 tmp = false;
3650 for (j = 0; j < nflg; j++)
3651 if (!strcmp (pflags[j].name,
3652 arc_flag_operands[*psflg].name))
3653 {
3654 tmp = true;
3655 break;
3656 }
3657 if (!tmp)
3658 {
3659 found_flag = false;
3660 break;
3661 }
3662 else
3663 {
3664 found_flag = true;
3665 }
3666 ++ psflg;
3667 } while (*psflg);
3668
3669 if (!found_flag)
3670 continue;
3671 }
3672
3673 if (reloc != r->oldreloc)
3674 continue;
3675 /* Found it. */
3676 ret = r->newreloc;
3677 break;
3678 }
3679
3680 if (ret == BFD_RELOC_UNUSED)
3681 as_bad (_("Unable to find %s relocation for instruction %s"),
3682 name, opcodename);
3683 return ret;
3684 }
3685
3686 /* All the symbol types that are allowed to be used for
3687 relaxation. */
3688
3689 static bool
3690 may_relax_expr (expressionS tok)
3691 {
3692 /* Check if we have unrelaxable relocs. */
3693 switch (tok.X_md)
3694 {
3695 default:
3696 break;
3697 case O_plt:
3698 return false;
3699 }
3700
3701 switch (tok.X_op)
3702 {
3703 case O_symbol:
3704 case O_multiply:
3705 case O_divide:
3706 case O_modulus:
3707 case O_add:
3708 case O_subtract:
3709 break;
3710
3711 default:
3712 return false;
3713 }
3714 return true;
3715 }
3716
3717 /* Checks if flags are in line with relaxable insn. */
3718
3719 static bool
3720 relaxable_flag (const struct arc_relaxable_ins *ins,
3721 const struct arc_flags *pflags,
3722 int nflgs)
3723 {
3724 unsigned flag_class,
3725 flag,
3726 flag_class_idx = 0,
3727 flag_idx = 0;
3728
3729 const struct arc_flag_operand *flag_opand;
3730 int i, counttrue = 0;
3731
3732 /* Iterate through flags classes. */
3733 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3734 {
3735 /* Iterate through flags in flag class. */
3736 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3737 != 0)
3738 {
3739 flag_opand = &arc_flag_operands[flag];
3740 /* Iterate through flags in ins to compare. */
3741 for (i = 0; i < nflgs; ++i)
3742 {
3743 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3744 ++counttrue;
3745 }
3746
3747 ++flag_idx;
3748 }
3749
3750 ++flag_class_idx;
3751 flag_idx = 0;
3752 }
3753
3754 /* If counttrue == nflgs, then all flags have been found. */
3755 return counttrue == nflgs;
3756 }
3757
3758 /* Checks if operands are in line with relaxable insn. */
3759
3760 static bool
3761 relaxable_operand (const struct arc_relaxable_ins *ins,
3762 const expressionS *tok,
3763 int ntok)
3764 {
3765 const enum rlx_operand_type *operand = &ins->operands[0];
3766 int i = 0;
3767
3768 while (*operand != EMPTY)
3769 {
3770 const expressionS *epr = &tok[i];
3771
3772 if (i != 0 && i >= ntok)
3773 return false;
3774
3775 switch (*operand)
3776 {
3777 case IMMEDIATE:
3778 if (!(epr->X_op == O_multiply
3779 || epr->X_op == O_divide
3780 || epr->X_op == O_modulus
3781 || epr->X_op == O_add
3782 || epr->X_op == O_subtract
3783 || epr->X_op == O_symbol))
3784 return false;
3785 break;
3786
3787 case REGISTER_DUP:
3788 if ((i <= 0)
3789 || (epr->X_add_number != tok[i - 1].X_add_number))
3790 return false;
3791 /* Fall through. */
3792 case REGISTER:
3793 if (epr->X_op != O_register)
3794 return false;
3795 break;
3796
3797 case REGISTER_S:
3798 if (epr->X_op != O_register)
3799 return false;
3800
3801 switch (epr->X_add_number)
3802 {
3803 case 0: case 1: case 2: case 3:
3804 case 12: case 13: case 14: case 15:
3805 break;
3806 default:
3807 return false;
3808 }
3809 break;
3810
3811 case REGISTER_NO_GP:
3812 if ((epr->X_op != O_register)
3813 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3814 return false;
3815 break;
3816
3817 case BRACKET:
3818 if (epr->X_op != O_bracket)
3819 return false;
3820 break;
3821
3822 default:
3823 /* Don't understand, bail out. */
3824 return false;
3825 break;
3826 }
3827
3828 ++i;
3829 operand = &ins->operands[i];
3830 }
3831
3832 return i == ntok;
3833 }
3834
3835 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3836
3837 static bool
3838 relax_insn_p (const struct arc_opcode *opcode,
3839 const expressionS *tok,
3840 int ntok,
3841 const struct arc_flags *pflags,
3842 int nflg)
3843 {
3844 unsigned i;
3845 bool rv = false;
3846
3847 /* Check the relaxation table. */
3848 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3849 {
3850 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3851
3852 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3853 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3854 && relaxable_operand (arc_rlx_ins, tok, ntok)
3855 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3856 {
3857 rv = true;
3858 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3859 memcpy (&frag_now->tc_frag_data.tok, tok,
3860 sizeof (expressionS) * ntok);
3861 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3862 sizeof (struct arc_flags) * nflg);
3863 frag_now->tc_frag_data.nflg = nflg;
3864 frag_now->tc_frag_data.ntok = ntok;
3865 break;
3866 }
3867 }
3868
3869 return rv;
3870 }
3871
3872 /* Turn an opcode description and a set of arguments into
3873 an instruction and a fixup. */
3874
3875 static void
3876 assemble_insn (const struct arc_opcode *opcode,
3877 const expressionS *tok,
3878 int ntok,
3879 const struct arc_flags *pflags,
3880 int nflg,
3881 struct arc_insn *insn)
3882 {
3883 const expressionS *reloc_exp = NULL;
3884 unsigned long long image;
3885 const unsigned char *argidx;
3886 int i;
3887 int tokidx = 0;
3888 unsigned char pcrel = 0;
3889 bool needGOTSymbol;
3890 bool has_delay_slot = false;
3891 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3892
3893 memset (insn, 0, sizeof (*insn));
3894 image = opcode->opcode;
3895
3896 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
3897 frag_now->fr_file, frag_now->fr_line, opcode->name,
3898 opcode->opcode);
3899
3900 /* Handle operands. */
3901 for (argidx = opcode->operands; *argidx; ++argidx)
3902 {
3903 const struct arc_operand *operand = &arc_operands[*argidx];
3904 const expressionS *t = (const expressionS *) 0;
3905
3906 if (ARC_OPERAND_IS_FAKE (operand))
3907 continue;
3908
3909 if (operand->flags & ARC_OPERAND_DUPLICATE)
3910 {
3911 /* Duplicate operand, already inserted. */
3912 tokidx ++;
3913 continue;
3914 }
3915
3916 if (tokidx >= ntok)
3917 {
3918 abort ();
3919 }
3920 else
3921 t = &tok[tokidx++];
3922
3923 /* Regardless if we have a reloc or not mark the instruction
3924 limm if it is the case. */
3925 if (operand->flags & ARC_OPERAND_LIMM)
3926 insn->has_limm = true;
3927
3928 switch (t->X_op)
3929 {
3930 case O_register:
3931 image = insert_operand (image, operand, regno (t->X_add_number),
3932 NULL, 0);
3933 break;
3934
3935 case O_constant:
3936 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3937 reloc_exp = t;
3938 if (operand->flags & ARC_OPERAND_LIMM)
3939 insn->limm = t->X_add_number;
3940 break;
3941
3942 case O_bracket:
3943 case O_colon:
3944 case O_addrtype:
3945 /* Ignore brackets, colons, and address types. */
3946 break;
3947
3948 case O_absent:
3949 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3950 break;
3951
3952 case O_subtract:
3953 /* Maybe register range. */
3954 if ((t->X_add_number == 0)
3955 && contains_register (t->X_add_symbol)
3956 && contains_register (t->X_op_symbol))
3957 {
3958 int regs;
3959
3960 regs = get_register (t->X_add_symbol);
3961 regs <<= 16;
3962 regs |= get_register (t->X_op_symbol);
3963 image = insert_operand (image, operand, regs, NULL, 0);
3964 break;
3965 }
3966 /* Fall through. */
3967
3968 default:
3969 /* This operand needs a relocation. */
3970 needGOTSymbol = false;
3971
3972 switch (t->X_md)
3973 {
3974 case O_plt:
3975 if (opcode->insn_class == JUMP)
3976 as_bad (_("Unable to use @plt relocation for insn %s"),
3977 opcode->name);
3978 needGOTSymbol = true;
3979 reloc = find_reloc ("plt", opcode->name,
3980 pflags, nflg,
3981 operand->default_reloc);
3982 break;
3983
3984 case O_gotoff:
3985 case O_gotpc:
3986 needGOTSymbol = true;
3987 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3988 break;
3989 case O_pcl:
3990 if (operand->flags & ARC_OPERAND_LIMM)
3991 {
3992 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3993 if (arc_opcode_len (opcode) == 2
3994 || opcode->insn_class == JUMP)
3995 as_bad (_("Unable to use @pcl relocation for insn %s"),
3996 opcode->name);
3997 }
3998 else
3999 {
4000 /* This is a relaxed operand which initially was
4001 limm, choose whatever we have defined in the
4002 opcode as reloc. */
4003 reloc = operand->default_reloc;
4004 }
4005 break;
4006 case O_sda:
4007 reloc = find_reloc ("sda", opcode->name,
4008 pflags, nflg,
4009 operand->default_reloc);
4010 break;
4011 case O_tlsgd:
4012 case O_tlsie:
4013 needGOTSymbol = true;
4014 /* Fall-through. */
4015
4016 case O_tpoff:
4017 case O_dtpoff:
4018 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
4019 break;
4020
4021 case O_tpoff9: /*FIXME! Check for the conditionality of
4022 the insn. */
4023 case O_dtpoff9: /*FIXME! Check for the conditionality of
4024 the insn. */
4025 as_bad (_("TLS_*_S9 relocs are not supported yet"));
4026 break;
4027
4028 default:
4029 /* Just consider the default relocation. */
4030 reloc = operand->default_reloc;
4031 break;
4032 }
4033
4034 if (needGOTSymbol && (GOT_symbol == NULL))
4035 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4036
4037 reloc_exp = t;
4038
4039 #if 0
4040 if (reloc > 0)
4041 {
4042 /* sanity checks. */
4043 reloc_howto_type *reloc_howto
4044 = bfd_reloc_type_lookup (stdoutput,
4045 (bfd_reloc_code_real_type) reloc);
4046 unsigned reloc_bitsize = reloc_howto->bitsize;
4047 if (reloc_howto->rightshift)
4048 reloc_bitsize -= reloc_howto->rightshift;
4049 if (reloc_bitsize != operand->bits)
4050 {
4051 as_bad (_("invalid relocation %s for field"),
4052 bfd_get_reloc_code_name (reloc));
4053 return;
4054 }
4055 }
4056 #endif
4057 if (insn->nfixups >= MAX_INSN_FIXUPS)
4058 as_fatal (_("too many fixups"));
4059
4060 struct arc_fixup *fixup;
4061 fixup = &insn->fixups[insn->nfixups++];
4062 fixup->exp = *t;
4063 fixup->reloc = reloc;
4064 if ((int) reloc < 0)
4065 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
4066 else
4067 {
4068 reloc_howto_type *reloc_howto =
4069 bfd_reloc_type_lookup (stdoutput,
4070 (bfd_reloc_code_real_type) fixup->reloc);
4071 pcrel = reloc_howto->pc_relative;
4072 }
4073 fixup->pcrel = pcrel;
4074 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) != 0;
4075 break;
4076 }
4077 }
4078
4079 /* Handle flags. */
4080 for (i = 0; i < nflg; i++)
4081 {
4082 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
4083
4084 /* Check if the instruction has a delay slot. */
4085 if (!strcmp (flg_operand->name, "d"))
4086 has_delay_slot = true;
4087
4088 /* There is an exceptional case when we cannot insert a flag just as
4089 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4090 relation with the relative address. Unfortunately, some of the
4091 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4092 handled in the normal way.
4093
4094 Flag operands don't have an architecture field, so we can't
4095 directly validate that FLAG_OPERAND is valid for the current
4096 architecture, what we do instead is just validate that we're
4097 assembling for an ARCv2 architecture. */
4098 if ((selected_cpu.flags & ARC_OPCODE_ARCV2)
4099 && (!strcmp (flg_operand->name, "t")
4100 || !strcmp (flg_operand->name, "nt")))
4101 {
4102 unsigned bitYoperand = 0;
4103 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4104 if (!strcmp (flg_operand->name, "t"))
4105 if (!strcmp (opcode->name, "bbit0")
4106 || !strcmp (opcode->name, "bbit1"))
4107 bitYoperand = arc_NToperand;
4108 else
4109 bitYoperand = arc_Toperand;
4110 else
4111 if (!strcmp (opcode->name, "bbit0")
4112 || !strcmp (opcode->name, "bbit1"))
4113 bitYoperand = arc_Toperand;
4114 else
4115 bitYoperand = arc_NToperand;
4116
4117 gas_assert (reloc_exp != NULL);
4118 if (reloc_exp->X_op == O_constant)
4119 {
4120 /* Check if we have a constant and solved it
4121 immediately. */
4122 offsetT val = reloc_exp->X_add_number;
4123 image |= insert_operand (image, &arc_operands[bitYoperand],
4124 val, NULL, 0);
4125 }
4126 else
4127 {
4128 struct arc_fixup *fixup;
4129
4130 if (insn->nfixups >= MAX_INSN_FIXUPS)
4131 as_fatal (_("too many fixups"));
4132
4133 fixup = &insn->fixups[insn->nfixups++];
4134 fixup->exp = *reloc_exp;
4135 fixup->reloc = -bitYoperand;
4136 fixup->pcrel = pcrel;
4137 fixup->islong = false;
4138 }
4139 }
4140 else
4141 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
4142 << flg_operand->shift;
4143 }
4144
4145 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
4146
4147 /* Instruction length. */
4148 insn->len = arc_opcode_len (opcode);
4149
4150 insn->insn = image;
4151
4152 /* Update last insn status. */
4153 arc_last_insns[1] = arc_last_insns[0];
4154 arc_last_insns[0].opcode = opcode;
4155 arc_last_insns[0].has_limm = insn->has_limm;
4156 arc_last_insns[0].has_delay_slot = has_delay_slot;
4157
4158 /* Check if the current instruction is legally used. */
4159 if (arc_last_insns[1].has_delay_slot
4160 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4161 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4162 arc_last_insns[1].opcode->name,
4163 arc_last_insns[0].opcode->name);
4164 if (arc_last_insns[1].has_delay_slot
4165 && arc_last_insns[0].has_limm)
4166 as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
4167 arc_last_insns[1].opcode->name,
4168 arc_last_insns[0].opcode->name);
4169 }
4170
4171 void
4172 arc_handle_align (fragS* fragP)
4173 {
4174 if ((fragP)->fr_type == rs_align_code)
4175 {
4176 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
4177 valueT count = ((fragP)->fr_next->fr_address
4178 - (fragP)->fr_address - (fragP)->fr_fix);
4179
4180 (fragP)->fr_var = 2;
4181
4182 if (count & 1)/* Padding in the gap till the next 2-byte
4183 boundary with 0s. */
4184 {
4185 (fragP)->fr_fix++;
4186 *dest++ = 0;
4187 }
4188 /* Writing nop_s. */
4189 md_number_to_chars (dest, NOP_OPCODE_S, 2);
4190 }
4191 }
4192
4193 /* Here we decide which fixups can be adjusted to make them relative
4194 to the beginning of the section instead of the symbol. Basically
4195 we need to make sure that the dynamic relocations are done
4196 correctly, so in some cases we force the original symbol to be
4197 used. */
4198
4199 int
4200 tc_arc_fix_adjustable (fixS *fixP)
4201 {
4202
4203 /* Prevent all adjustments to global symbols. */
4204 if (S_IS_EXTERNAL (fixP->fx_addsy))
4205 return 0;
4206 if (S_IS_WEAK (fixP->fx_addsy))
4207 return 0;
4208
4209 /* Adjust_reloc_syms doesn't know about the GOT. */
4210 switch (fixP->fx_r_type)
4211 {
4212 case BFD_RELOC_ARC_GOTPC32:
4213 case BFD_RELOC_ARC_PLT32:
4214 case BFD_RELOC_ARC_S25H_PCREL_PLT:
4215 case BFD_RELOC_ARC_S21H_PCREL_PLT:
4216 case BFD_RELOC_ARC_S25W_PCREL_PLT:
4217 case BFD_RELOC_ARC_S21W_PCREL_PLT:
4218 return 0;
4219
4220 default:
4221 break;
4222 }
4223
4224 return 1;
4225 }
4226
4227 /* Compute the reloc type of an expression EXP. */
4228
4229 static void
4230 arc_check_reloc (expressionS *exp,
4231 bfd_reloc_code_real_type *r_type_p)
4232 {
4233 if (*r_type_p == BFD_RELOC_32
4234 && exp->X_op == O_subtract
4235 && exp->X_op_symbol != NULL
4236 && S_GET_SEGMENT (exp->X_op_symbol) == now_seg)
4237 *r_type_p = BFD_RELOC_ARC_32_PCREL;
4238 }
4239
4240
4241 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4242
4243 void
4244 arc_cons_fix_new (fragS *frag,
4245 int off,
4246 int size,
4247 expressionS *exp,
4248 bfd_reloc_code_real_type r_type)
4249 {
4250 r_type = BFD_RELOC_UNUSED;
4251
4252 switch (size)
4253 {
4254 case 1:
4255 r_type = BFD_RELOC_8;
4256 break;
4257
4258 case 2:
4259 r_type = BFD_RELOC_16;
4260 break;
4261
4262 case 3:
4263 r_type = BFD_RELOC_24;
4264 break;
4265
4266 case 4:
4267 r_type = BFD_RELOC_32;
4268 arc_check_reloc (exp, &r_type);
4269 break;
4270
4271 case 8:
4272 r_type = BFD_RELOC_64;
4273 break;
4274
4275 default:
4276 as_bad (_("unsupported BFD relocation size %u"), size);
4277 r_type = BFD_RELOC_UNUSED;
4278 }
4279
4280 fix_new_exp (frag, off, size, exp, 0, r_type);
4281 }
4282
4283 /* The actual routine that checks the ZOL conditions. */
4284
4285 static void
4286 check_zol (symbolS *s)
4287 {
4288 switch (selected_cpu.mach)
4289 {
4290 case bfd_mach_arc_arcv2:
4291 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
4292 return;
4293
4294 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
4295 || arc_last_insns[1].has_delay_slot)
4296 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4297 S_GET_NAME (s));
4298
4299 break;
4300 case bfd_mach_arc_arc600:
4301
4302 if (is_kernel_insn_p (arc_last_insns[0].opcode))
4303 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4304 S_GET_NAME (s));
4305
4306 if (arc_last_insns[0].has_limm
4307 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4308 as_bad (_("A jump instruction with long immediate detected at the \
4309 end of the ZOL label @%s"), S_GET_NAME (s));
4310
4311 /* Fall through. */
4312 case bfd_mach_arc_arc700:
4313 if (arc_last_insns[0].has_delay_slot)
4314 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4315 S_GET_NAME (s));
4316
4317 break;
4318 default:
4319 break;
4320 }
4321 }
4322
4323 /* If ZOL end check the last two instruction for illegals. */
4324 void
4325 arc_frob_label (symbolS * sym)
4326 {
4327 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
4328 check_zol (sym);
4329
4330 dwarf2_emit_label (sym);
4331 }
4332
4333 /* Used because generic relaxation assumes a pc-rel value whilst we
4334 also relax instructions that use an absolute value resolved out of
4335 relative values (if that makes any sense). An example: 'add r1,
4336 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4337 but if they're in the same section we can subtract the section
4338 offset relocation which ends up in a resolved value. So if @.L2 is
4339 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4340 .text + 0x40 = 0x10. */
4341 int
4342 arc_pcrel_adjust (fragS *fragP)
4343 {
4344 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4345 fragP->fr_address, fragP->fr_fix,
4346 fragP->tc_frag_data.pcrel ? "Y" : "N");
4347
4348 if (!fragP->tc_frag_data.pcrel)
4349 return fragP->fr_address + fragP->fr_fix;
4350
4351 /* Take into account the PCL rounding. */
4352 return (fragP->fr_address + fragP->fr_fix) & 0x03;
4353 }
4354
4355 /* Initialize the DWARF-2 unwind information for this procedure. */
4356
4357 void
4358 tc_arc_frame_initial_instructions (void)
4359 {
4360 /* Stack pointer is register 28. */
4361 cfi_add_CFA_def_cfa (28, 0);
4362 }
4363
4364 int
4365 tc_arc_regname_to_dw2regnum (char *regname)
4366 {
4367 struct symbol *sym;
4368
4369 sym = str_hash_find (arc_reg_hash, regname);
4370 if (sym)
4371 return S_GET_VALUE (sym);
4372
4373 return -1;
4374 }
4375
4376 /* Adjust the symbol table. Delete found AUX register symbols. */
4377
4378 void
4379 arc_adjust_symtab (void)
4380 {
4381 symbolS * sym;
4382
4383 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4384 {
4385 /* I've created a symbol during parsing process. Now, remove
4386 the symbol as it is found to be an AUX register. */
4387 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
4388 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4389 }
4390
4391 /* Now do generic ELF adjustments. */
4392 elf_adjust_symtab ();
4393 }
4394
4395 static void
4396 tokenize_extinsn (extInstruction_t *einsn)
4397 {
4398 char *p, c;
4399 char *insn_name;
4400 unsigned char major_opcode;
4401 unsigned char sub_opcode;
4402 unsigned char syntax_class = 0;
4403 unsigned char syntax_class_modifiers = 0;
4404 unsigned char suffix_class = 0;
4405 unsigned int i;
4406
4407 SKIP_WHITESPACE ();
4408
4409 /* 1st: get instruction name. */
4410 p = input_line_pointer;
4411 c = get_symbol_name (&p);
4412
4413 insn_name = xstrdup (p);
4414 restore_line_pointer (c);
4415
4416 /* Convert to lower case. */
4417 for (p = insn_name; *p; ++p)
4418 *p = TOLOWER (*p);
4419
4420 /* 2nd: get major opcode. */
4421 if (*input_line_pointer != ',')
4422 {
4423 as_bad (_("expected comma after instruction name"));
4424 ignore_rest_of_line ();
4425 return;
4426 }
4427 input_line_pointer++;
4428 major_opcode = get_absolute_expression ();
4429
4430 /* 3rd: get sub-opcode. */
4431 SKIP_WHITESPACE ();
4432
4433 if (*input_line_pointer != ',')
4434 {
4435 as_bad (_("expected comma after major opcode"));
4436 ignore_rest_of_line ();
4437 return;
4438 }
4439 input_line_pointer++;
4440 sub_opcode = get_absolute_expression ();
4441
4442 /* 4th: get suffix class. */
4443 SKIP_WHITESPACE ();
4444
4445 if (*input_line_pointer != ',')
4446 {
4447 as_bad ("expected comma after sub opcode");
4448 ignore_rest_of_line ();
4449 return;
4450 }
4451 input_line_pointer++;
4452
4453 while (1)
4454 {
4455 SKIP_WHITESPACE ();
4456
4457 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4458 {
4459 if (!strncmp (suffixclass[i].name, input_line_pointer,
4460 suffixclass[i].len))
4461 {
4462 suffix_class |= suffixclass[i].attr_class;
4463 input_line_pointer += suffixclass[i].len;
4464 break;
4465 }
4466 }
4467
4468 if (i == ARRAY_SIZE (suffixclass))
4469 {
4470 as_bad ("invalid suffix class");
4471 ignore_rest_of_line ();
4472 return;
4473 }
4474
4475 SKIP_WHITESPACE ();
4476
4477 if (*input_line_pointer == '|')
4478 input_line_pointer++;
4479 else
4480 break;
4481 }
4482
4483 /* 5th: get syntax class and syntax class modifiers. */
4484 if (*input_line_pointer != ',')
4485 {
4486 as_bad ("expected comma after suffix class");
4487 ignore_rest_of_line ();
4488 return;
4489 }
4490 input_line_pointer++;
4491
4492 while (1)
4493 {
4494 SKIP_WHITESPACE ();
4495
4496 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4497 {
4498 if (!strncmp (syntaxclassmod[i].name,
4499 input_line_pointer,
4500 syntaxclassmod[i].len))
4501 {
4502 syntax_class_modifiers |= syntaxclassmod[i].attr_class;
4503 input_line_pointer += syntaxclassmod[i].len;
4504 break;
4505 }
4506 }
4507
4508 if (i == ARRAY_SIZE (syntaxclassmod))
4509 {
4510 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4511 {
4512 if (!strncmp (syntaxclass[i].name,
4513 input_line_pointer,
4514 syntaxclass[i].len))
4515 {
4516 syntax_class |= syntaxclass[i].attr_class;
4517 input_line_pointer += syntaxclass[i].len;
4518 break;
4519 }
4520 }
4521
4522 if (i == ARRAY_SIZE (syntaxclass))
4523 {
4524 as_bad ("missing syntax class");
4525 ignore_rest_of_line ();
4526 return;
4527 }
4528 }
4529
4530 SKIP_WHITESPACE ();
4531
4532 if (*input_line_pointer == '|')
4533 input_line_pointer++;
4534 else
4535 break;
4536 }
4537
4538 demand_empty_rest_of_line ();
4539
4540 einsn->name = insn_name;
4541 einsn->major = major_opcode;
4542 einsn->minor = sub_opcode;
4543 einsn->syntax = syntax_class;
4544 einsn->modsyn = syntax_class_modifiers;
4545 einsn->suffix = suffix_class;
4546 einsn->flags = syntax_class
4547 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4548 }
4549
4550 /* Generate an extension section. */
4551
4552 static int
4553 arc_set_ext_seg (void)
4554 {
4555 if (!arcext_section)
4556 {
4557 arcext_section = subseg_new (".arcextmap", 0);
4558 bfd_set_section_flags (arcext_section, SEC_READONLY | SEC_HAS_CONTENTS);
4559 }
4560 else
4561 subseg_set (arcext_section, 0);
4562 return 1;
4563 }
4564
4565 /* Create an extension instruction description in the arc extension
4566 section of the output file.
4567 The structure for an instruction is like this:
4568 [0]: Length of the record.
4569 [1]: Type of the record.
4570
4571 [2]: Major opcode.
4572 [3]: Sub-opcode.
4573 [4]: Syntax (flags).
4574 [5]+ Name instruction.
4575
4576 The sequence is terminated by an empty entry. */
4577
4578 static void
4579 create_extinst_section (extInstruction_t *einsn)
4580 {
4581
4582 segT old_sec = now_seg;
4583 int old_subsec = now_subseg;
4584 char *p;
4585 int name_len = strlen (einsn->name);
4586
4587 arc_set_ext_seg ();
4588
4589 p = frag_more (1);
4590 *p = 5 + name_len + 1;
4591 p = frag_more (1);
4592 *p = EXT_INSTRUCTION;
4593 p = frag_more (1);
4594 *p = einsn->major;
4595 p = frag_more (1);
4596 *p = einsn->minor;
4597 p = frag_more (1);
4598 *p = einsn->flags;
4599 p = frag_more (name_len + 1);
4600 strcpy (p, einsn->name);
4601
4602 subseg_set (old_sec, old_subsec);
4603 }
4604
4605 /* Handler .extinstruction pseudo-op. */
4606
4607 static void
4608 arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4609 {
4610 extInstruction_t einsn;
4611 struct arc_opcode *arc_ext_opcodes;
4612 const char *errmsg = NULL;
4613 unsigned char moplow, mophigh;
4614
4615 memset (&einsn, 0, sizeof (einsn));
4616 tokenize_extinsn (&einsn);
4617
4618 /* Check if the name is already used. */
4619 if (arc_find_opcode (einsn.name))
4620 as_warn (_("Pseudocode already used %s"), einsn.name);
4621
4622 /* Check the opcode ranges. */
4623 moplow = 0x05;
4624 mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
4625 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
4626
4627 if ((einsn.major > mophigh) || (einsn.major < moplow))
4628 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4629
4630 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4631 && (einsn.major != 5) && (einsn.major != 9))
4632 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4633
4634 switch (einsn.syntax & ARC_SYNTAX_MASK)
4635 {
4636 case ARC_SYNTAX_3OP:
4637 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4638 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4639 break;
4640 case ARC_SYNTAX_2OP:
4641 case ARC_SYNTAX_1OP:
4642 case ARC_SYNTAX_NOP:
4643 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4644 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4645 break;
4646 default:
4647 break;
4648 }
4649
4650 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
4651 if (arc_ext_opcodes == NULL)
4652 {
4653 if (errmsg)
4654 as_fatal ("%s", errmsg);
4655 else
4656 as_fatal (_("Couldn't generate extension instruction opcodes"));
4657 }
4658 else if (errmsg)
4659 as_warn ("%s", errmsg);
4660
4661 /* Insert the extension instruction. */
4662 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4663
4664 create_extinst_section (&einsn);
4665 }
4666
4667 static bool
4668 tokenize_extregister (extRegister_t *ereg, int opertype)
4669 {
4670 char *name;
4671 char *mode;
4672 char c;
4673 char *p;
4674 int number, imode = 0;
4675 bool isCore_p = opertype == EXT_CORE_REGISTER;
4676 bool isReg_p = opertype == EXT_CORE_REGISTER || opertype == EXT_AUX_REGISTER;
4677
4678 /* 1st: get register name. */
4679 SKIP_WHITESPACE ();
4680 p = input_line_pointer;
4681 c = get_symbol_name (&p);
4682
4683 name = xstrdup (p);
4684 restore_line_pointer (c);
4685
4686 /* 2nd: get register number. */
4687 SKIP_WHITESPACE ();
4688
4689 if (*input_line_pointer != ',')
4690 {
4691 as_bad (_("expected comma after name"));
4692 ignore_rest_of_line ();
4693 free (name);
4694 return false;
4695 }
4696 input_line_pointer++;
4697 number = get_absolute_expression ();
4698
4699 if ((number < 0)
4700 && (opertype != EXT_AUX_REGISTER))
4701 {
4702 as_bad (_("%s second argument cannot be a negative number %d"),
4703 isCore_p ? "extCoreRegister's" : "extCondCode's",
4704 number);
4705 ignore_rest_of_line ();
4706 free (name);
4707 return false;
4708 }
4709
4710 if (isReg_p)
4711 {
4712 /* 3rd: get register mode. */
4713 SKIP_WHITESPACE ();
4714
4715 if (*input_line_pointer != ',')
4716 {
4717 as_bad (_("expected comma after register number"));
4718 ignore_rest_of_line ();
4719 free (name);
4720 return false;
4721 }
4722
4723 input_line_pointer++;
4724 mode = input_line_pointer;
4725
4726 if (startswith (mode, "r|w"))
4727 {
4728 imode = 0;
4729 input_line_pointer += 3;
4730 }
4731 else if (startswith (mode, "r"))
4732 {
4733 imode = ARC_REGISTER_READONLY;
4734 input_line_pointer += 1;
4735 }
4736 else if (!startswith (mode, "w"))
4737 {
4738 as_bad (_("invalid mode"));
4739 ignore_rest_of_line ();
4740 free (name);
4741 return false;
4742 }
4743 else
4744 {
4745 imode = ARC_REGISTER_WRITEONLY;
4746 input_line_pointer += 1;
4747 }
4748 }
4749
4750 if (isCore_p)
4751 {
4752 /* 4th: get core register shortcut. */
4753 SKIP_WHITESPACE ();
4754 if (*input_line_pointer != ',')
4755 {
4756 as_bad (_("expected comma after register mode"));
4757 ignore_rest_of_line ();
4758 free (name);
4759 return false;
4760 }
4761
4762 input_line_pointer++;
4763
4764 if (startswith (input_line_pointer, "cannot_shortcut"))
4765 {
4766 imode |= ARC_REGISTER_NOSHORT_CUT;
4767 input_line_pointer += 15;
4768 }
4769 else if (!startswith (input_line_pointer, "can_shortcut"))
4770 {
4771 as_bad (_("shortcut designator invalid"));
4772 ignore_rest_of_line ();
4773 free (name);
4774 return false;
4775 }
4776 else
4777 {
4778 input_line_pointer += 12;
4779 }
4780 }
4781 demand_empty_rest_of_line ();
4782
4783 ereg->name = name;
4784 ereg->number = number;
4785 ereg->imode = imode;
4786 return true;
4787 }
4788
4789 /* Create an extension register/condition description in the arc
4790 extension section of the output file.
4791
4792 The structure for an instruction is like this:
4793 [0]: Length of the record.
4794 [1]: Type of the record.
4795
4796 For core regs and condition codes:
4797 [2]: Value.
4798 [3]+ Name.
4799
4800 For auxiliary registers:
4801 [2..5]: Value.
4802 [6]+ Name
4803
4804 The sequence is terminated by an empty entry. */
4805
4806 static void
4807 create_extcore_section (extRegister_t *ereg, int opertype)
4808 {
4809 segT old_sec = now_seg;
4810 int old_subsec = now_subseg;
4811 char *p;
4812 int name_len = strlen (ereg->name);
4813
4814 arc_set_ext_seg ();
4815
4816 switch (opertype)
4817 {
4818 case EXT_COND_CODE:
4819 case EXT_CORE_REGISTER:
4820 p = frag_more (1);
4821 *p = 3 + name_len + 1;
4822 p = frag_more (1);
4823 *p = opertype;
4824 p = frag_more (1);
4825 *p = ereg->number;
4826 break;
4827 case EXT_AUX_REGISTER:
4828 p = frag_more (1);
4829 *p = 6 + name_len + 1;
4830 p = frag_more (1);
4831 *p = EXT_AUX_REGISTER;
4832 p = frag_more (1);
4833 *p = (ereg->number >> 24) & 0xff;
4834 p = frag_more (1);
4835 *p = (ereg->number >> 16) & 0xff;
4836 p = frag_more (1);
4837 *p = (ereg->number >> 8) & 0xff;
4838 p = frag_more (1);
4839 *p = (ereg->number) & 0xff;
4840 break;
4841 default:
4842 break;
4843 }
4844
4845 p = frag_more (name_len + 1);
4846 strcpy (p, ereg->name);
4847
4848 subseg_set (old_sec, old_subsec);
4849 }
4850
4851 /* Handler .extCoreRegister pseudo-op. */
4852
4853 static void
4854 arc_extcorereg (int opertype)
4855 {
4856 extRegister_t ereg;
4857 struct arc_aux_reg *auxr;
4858 struct arc_flag_operand *ccode;
4859
4860 memset (&ereg, 0, sizeof (ereg));
4861 if (!tokenize_extregister (&ereg, opertype))
4862 return;
4863
4864 switch (opertype)
4865 {
4866 case EXT_CORE_REGISTER:
4867 /* Core register. */
4868 if (ereg.number > 60)
4869 as_bad (_("core register %s value (%d) too large"), ereg.name,
4870 ereg.number);
4871 declare_register (ereg.name, ereg.number);
4872 break;
4873 case EXT_AUX_REGISTER:
4874 /* Auxiliary register. */
4875 auxr = XNEW (struct arc_aux_reg);
4876 auxr->name = ereg.name;
4877 auxr->cpu = selected_cpu.flags;
4878 auxr->subclass = NONE;
4879 auxr->address = ereg.number;
4880 if (str_hash_insert (arc_aux_hash, auxr->name, auxr, 0) != NULL)
4881 as_bad (_("duplicate aux register %s"), auxr->name);
4882 break;
4883 case EXT_COND_CODE:
4884 /* Condition code. */
4885 if (ereg.number > 31)
4886 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4887 ereg.number);
4888 ext_condcode.size ++;
4889 ext_condcode.arc_ext_condcode =
4890 XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode,
4891 ext_condcode.size + 1);
4892
4893 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4894 ccode->name = ereg.name;
4895 ccode->code = ereg.number;
4896 ccode->bits = 5;
4897 ccode->shift = 0;
4898 ccode->favail = 0; /* not used. */
4899 ccode++;
4900 memset (ccode, 0, sizeof (struct arc_flag_operand));
4901 break;
4902 default:
4903 as_bad (_("Unknown extension"));
4904 break;
4905 }
4906 create_extcore_section (&ereg, opertype);
4907 }
4908
4909 /* Parse a .arc_attribute directive. */
4910
4911 static void
4912 arc_attribute (int ignored ATTRIBUTE_UNUSED)
4913 {
4914 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4915
4916 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4917 attributes_set_explicitly[tag] = true;
4918 }
4919
4920 /* Set an attribute if it has not already been set by the user. */
4921
4922 static void
4923 arc_set_attribute_int (int tag, int value)
4924 {
4925 if (tag < 1
4926 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4927 || !attributes_set_explicitly[tag])
4928 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
4929 }
4930
4931 static void
4932 arc_set_attribute_string (int tag, const char *value)
4933 {
4934 if (tag < 1
4935 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4936 || !attributes_set_explicitly[tag])
4937 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
4938 }
4939
4940 /* Allocate and concatenate two strings. s1 can be NULL but not
4941 s2. s1 pointer is freed at end of this procedure. */
4942
4943 static char *
4944 arc_stralloc (char * s1, const char * s2)
4945 {
4946 char * p;
4947 int len = 0;
4948
4949 if (s1)
4950 len = strlen (s1) + 1;
4951
4952 /* Only s1 can be null. */
4953 gas_assert (s2);
4954 len += strlen (s2) + 1;
4955
4956 p = (char *) xmalloc (len);
4957
4958 if (s1)
4959 {
4960 strcpy (p, s1);
4961 strcat (p, ",");
4962 strcat (p, s2);
4963 free (s1);
4964 }
4965 else
4966 strcpy (p, s2);
4967
4968 return p;
4969 }
4970
4971 /* Set the public ARC object attributes. */
4972
4973 static void
4974 arc_set_public_attributes (void)
4975 {
4976 int base = 0;
4977 char *s = NULL;
4978 unsigned int i;
4979
4980 /* Tag_ARC_CPU_name. */
4981 arc_set_attribute_string (Tag_ARC_CPU_name, selected_cpu.name);
4982
4983 /* Tag_ARC_CPU_base. */
4984 switch (selected_cpu.eflags & EF_ARC_MACH_MSK)
4985 {
4986 case E_ARC_MACH_ARC600:
4987 case E_ARC_MACH_ARC601:
4988 base = TAG_CPU_ARC6xx;
4989 break;
4990 case E_ARC_MACH_ARC700:
4991 base = TAG_CPU_ARC7xx;
4992 break;
4993 case EF_ARC_CPU_ARCV2EM:
4994 base = TAG_CPU_ARCEM;
4995 break;
4996 case EF_ARC_CPU_ARCV2HS:
4997 base = TAG_CPU_ARCHS;
4998 break;
4999 default:
5000 base = 0;
5001 break;
5002 }
5003 if (attributes_set_explicitly[Tag_ARC_CPU_base]
5004 && (base != bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5005 Tag_ARC_CPU_base)))
5006 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
5007 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_CPU_base, base);
5008
5009 /* Tag_ARC_ABI_osver. */
5010 if (attributes_set_explicitly[Tag_ARC_ABI_osver])
5011 {
5012 int val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5013 Tag_ARC_ABI_osver);
5014
5015 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_OSABI_MSK)
5016 | (val & 0x0f << 8));
5017 }
5018 else
5019 {
5020 arc_set_attribute_int (Tag_ARC_ABI_osver, E_ARC_OSABI_CURRENT >> 8);
5021 }
5022
5023 /* Tag_ARC_ISA_config. */
5024 arc_check_feature();
5025
5026 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
5027 if (selected_cpu.features & feature_list[i].feature)
5028 s = arc_stralloc (s, feature_list[i].attr);
5029
5030 if (s)
5031 arc_set_attribute_string (Tag_ARC_ISA_config, s);
5032
5033 /* Tag_ARC_ISA_mpy_option. */
5034 arc_set_attribute_int (Tag_ARC_ISA_mpy_option, mpy_option);
5035
5036 /* Tag_ARC_ABI_pic. */
5037 arc_set_attribute_int (Tag_ARC_ABI_pic, pic_option);
5038
5039 /* Tag_ARC_ABI_sda. */
5040 arc_set_attribute_int (Tag_ARC_ABI_sda, sda_option);
5041
5042 /* Tag_ARC_ABI_tls. */
5043 arc_set_attribute_int (Tag_ARC_ABI_tls, tls_option);
5044
5045 /* Tag_ARC_ATR_version. */
5046 arc_set_attribute_int (Tag_ARC_ATR_version, 1);
5047
5048 /* Tag_ARC_ABI_rf16. */
5049 if (attributes_set_explicitly[Tag_ARC_ABI_rf16]
5050 && bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5051 Tag_ARC_ABI_rf16)
5052 && !rf16_only)
5053 {
5054 as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full "
5055 "register file"));
5056 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_ABI_rf16, 0);
5057 }
5058 }
5059
5060 /* Add the default contents for the .ARC.attributes section. */
5061
5062 void
5063 arc_md_end (void)
5064 {
5065 arc_set_public_attributes ();
5066
5067 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
5068 as_fatal (_("could not set architecture and machine"));
5069
5070 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
5071 }
5072
5073 void arc_copy_symbol_attributes (symbolS *dest, symbolS *src)
5074 {
5075 ARC_GET_FLAG (dest) = ARC_GET_FLAG (src);
5076 }
5077
5078 int arc_convert_symbolic_attribute (const char *name)
5079 {
5080 static const struct
5081 {
5082 const char * name;
5083 const int tag;
5084 }
5085 attribute_table[] =
5086 {
5087 #define T(tag) {#tag, tag}
5088 T (Tag_ARC_PCS_config),
5089 T (Tag_ARC_CPU_base),
5090 T (Tag_ARC_CPU_variation),
5091 T (Tag_ARC_CPU_name),
5092 T (Tag_ARC_ABI_rf16),
5093 T (Tag_ARC_ABI_osver),
5094 T (Tag_ARC_ABI_sda),
5095 T (Tag_ARC_ABI_pic),
5096 T (Tag_ARC_ABI_tls),
5097 T (Tag_ARC_ABI_enumsize),
5098 T (Tag_ARC_ABI_exceptions),
5099 T (Tag_ARC_ABI_double_size),
5100 T (Tag_ARC_ISA_config),
5101 T (Tag_ARC_ISA_apex),
5102 T (Tag_ARC_ISA_mpy_option),
5103 T (Tag_ARC_ATR_version)
5104 #undef T
5105 };
5106 unsigned int i;
5107
5108 if (name == NULL)
5109 return -1;
5110
5111 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
5112 if (streq (name, attribute_table[i].name))
5113 return attribute_table[i].tag;
5114
5115 return -1;
5116 }
5117
5118 /* Local variables:
5119 eval: (c-set-style "gnu")
5120 indent-tabs-mode: t
5121 End: */