1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
51 /* Equal to MAX_PRECISION in atof-ieee.c. */
52 #define MAX_LITTLENUMS 6
54 #ifndef TARGET_WITH_CPU
55 #define TARGET_WITH_CPU "arc700"
56 #endif /* TARGET_WITH_CPU */
58 /* Enum used to enumerate the relaxable ins operands. */
63 REGISTER_S
, /* Register for short instruction(s). */
64 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
65 REGISTER_DUP
, /* Duplication of previous operand of type register. */
99 #define regno(x) ((x) & 0x3F)
100 #define is_ir_num(x) (((x) & ~0x3F) == 0)
101 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
102 #define is_spfp_p(op) (((sc) == SPX))
103 #define is_dpfp_p(op) (((sc) == DPX))
104 #define is_fpuda_p(op) (((sc) == DPA))
105 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
106 || (op)->insn_class == JUMP))
107 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
108 #define is_nps400_p(op) (((sc) == NPS400))
110 /* Generic assembler global variables which must be defined by all
113 /* Characters which always start a comment. */
114 const char comment_chars
[] = "#;";
116 /* Characters which start a comment at the beginning of a line. */
117 const char line_comment_chars
[] = "#";
119 /* Characters which may be used to separate multiple commands on a
121 const char line_separator_chars
[] = "`";
123 /* Characters which are used to indicate an exponent in a floating
125 const char EXP_CHARS
[] = "eE";
127 /* Chars that mean this number is a floating point constant
128 As in 0f12.456 or 0d1.2345e12. */
129 const char FLT_CHARS
[] = "rRsSfFdD";
132 extern int target_big_endian
;
133 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
134 static int byte_order
= DEFAULT_BYTE_ORDER
;
136 /* Arc extension section. */
137 static segT arcext_section
;
139 /* By default relaxation is disabled. */
140 static int relaxation_state
= 0;
142 extern int arc_get_mach (char *);
144 /* Forward declarations. */
145 static void arc_lcomm (int);
146 static void arc_option (int);
147 static void arc_extra_reloc (int);
148 static void arc_extinsn (int);
149 static void arc_extcorereg (int);
151 const pseudo_typeS md_pseudo_table
[] =
153 /* Make sure that .word is 32 bits. */
156 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
157 { "lcomm", arc_lcomm
, 0 },
158 { "lcommon", arc_lcomm
, 0 },
159 { "cpu", arc_option
, 0 },
161 { "extinstruction", arc_extinsn
, 0 },
162 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
163 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
164 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
166 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
167 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
172 const char *md_shortopts
= "";
176 OPTION_EB
= OPTION_MD_BASE
,
194 /* The following options are deprecated and provided here only for
195 compatibility reasons. */
218 struct option md_longopts
[] =
220 { "EB", no_argument
, NULL
, OPTION_EB
},
221 { "EL", no_argument
, NULL
, OPTION_EL
},
222 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
223 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
224 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
225 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
226 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
227 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
228 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
229 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
230 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
231 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
232 { "mnps400", no_argument
, NULL
, OPTION_NPS400
},
234 /* Floating point options */
235 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
236 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
237 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
238 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
239 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
240 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
241 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
242 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
243 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
244 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
245 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
247 /* The following options are deprecated and provided here only for
248 compatibility reasons. */
249 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
250 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
251 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
252 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
253 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
254 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
255 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
256 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
257 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
258 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
259 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
260 { "mea", no_argument
, NULL
, OPTION_EA
},
261 { "mEA", no_argument
, NULL
, OPTION_EA
},
262 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
263 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
264 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
265 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
266 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
267 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
268 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
269 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
270 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
271 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
272 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
273 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
274 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
275 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
276 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
278 { NULL
, no_argument
, NULL
, 0 }
281 size_t md_longopts_size
= sizeof (md_longopts
);
283 /* Local data and data types. */
285 /* Used since new relocation types are introduced in this
286 file (DUMMY_RELOC_LITUSE_*). */
287 typedef int extended_bfd_reloc_code_real_type
;
293 extended_bfd_reloc_code_real_type reloc
;
295 /* index into arc_operands. */
296 unsigned int opindex
;
298 /* PC-relative, used by internals fixups. */
301 /* TRUE if this fixup is for LIMM operand. */
309 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
311 bfd_boolean short_insn
; /* Boolean value: TRUE if current insn is
313 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
315 bfd_boolean relax
; /* Boolean value: TRUE if needs
319 /* Structure to hold any last two instructions. */
320 static struct arc_last_insn
322 /* Saved instruction opcode. */
323 const struct arc_opcode
*opcode
;
325 /* Boolean value: TRUE if current insn is short. */
326 bfd_boolean has_limm
;
328 /* Boolean value: TRUE if current insn has delay slot. */
329 bfd_boolean has_delay_slot
;
332 /* Extension instruction suffix classes. */
340 static const attributes_t suffixclass
[] =
342 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
343 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
344 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
347 /* Extension instruction syntax classes. */
348 static const attributes_t syntaxclass
[] =
350 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
351 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
352 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
353 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
356 /* Extension instruction syntax classes modifiers. */
357 static const attributes_t syntaxclassmod
[] =
359 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
360 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
363 /* Extension register type. */
371 /* A structure to hold the additional conditional codes. */
374 struct arc_flag_operand
*arc_ext_condcode
;
376 } ext_condcode
= { NULL
, 0 };
378 /* Structure to hold an entry in ARC_OPCODE_HASH. */
379 struct arc_opcode_hash_entry
381 /* The number of pointers in the OPCODE list. */
384 /* Points to a list of opcode pointers. */
385 const struct arc_opcode
**opcode
;
388 /* Structure used for iterating through an arc_opcode_hash_entry. */
389 struct arc_opcode_hash_entry_iterator
391 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
394 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
395 returned by this iterator. */
396 const struct arc_opcode
*opcode
;
399 /* Forward declaration. */
400 static void assemble_insn
401 (const struct arc_opcode
*, const expressionS
*, int,
402 const struct arc_flags
*, int, struct arc_insn
*);
404 /* The cpu for which we are generating code. */
405 static unsigned arc_target
;
406 static const char *arc_target_name
;
407 static unsigned arc_features
;
409 /* The default architecture. */
410 static int arc_mach_type
;
412 /* TRUE if the cpu type has been explicitly specified. */
413 static bfd_boolean mach_type_specified_p
= FALSE
;
415 /* The hash table of instruction opcodes. */
416 static struct hash_control
*arc_opcode_hash
;
418 /* The hash table of register symbols. */
419 static struct hash_control
*arc_reg_hash
;
421 /* The hash table of aux register symbols. */
422 static struct hash_control
*arc_aux_hash
;
424 /* The hash table of address types. */
425 static struct hash_control
*arc_addrtype_hash
;
427 /* A table of CPU names and opcode sets. */
428 static const struct cpu_type
438 { "arc600", ARC_OPCODE_ARC600
, bfd_mach_arc_arc600
,
439 E_ARC_MACH_ARC600
, 0x00},
440 { "arc700", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
441 E_ARC_MACH_ARC700
, 0x00},
442 { "nps400", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
443 E_ARC_MACH_ARC700
, ARC_NPS400
},
444 { "arcem", ARC_OPCODE_ARCv2EM
, bfd_mach_arc_arcv2
,
445 EF_ARC_CPU_ARCV2EM
, 0x00},
446 { "archs", ARC_OPCODE_ARCv2HS
, bfd_mach_arc_arcv2
,
447 EF_ARC_CPU_ARCV2HS
, ARC_CD
},
451 /* Used by the arc_reloc_op table. Order is important. */
452 #define O_gotoff O_md1 /* @gotoff relocation. */
453 #define O_gotpc O_md2 /* @gotpc relocation. */
454 #define O_plt O_md3 /* @plt relocation. */
455 #define O_sda O_md4 /* @sda relocation. */
456 #define O_pcl O_md5 /* @pcl relocation. */
457 #define O_tlsgd O_md6 /* @tlsgd relocation. */
458 #define O_tlsie O_md7 /* @tlsie relocation. */
459 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
460 #define O_tpoff O_md9 /* @tpoff relocation. */
461 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
462 #define O_dtpoff O_md11 /* @dtpoff relocation. */
463 #define O_last O_dtpoff
465 /* Used to define a bracket as operand in tokens. */
466 #define O_bracket O_md32
468 /* Used to define a colon as an operand in tokens. */
469 #define O_colon O_md31
471 /* Used to define address types in nps400. */
472 #define O_addrtype O_md30
474 /* Dummy relocation, to be sorted out. */
475 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
477 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
479 /* A table to map the spelling of a relocation operand into an appropriate
480 bfd_reloc_code_real_type type. The table is assumed to be ordered such
481 that op-O_literal indexes into it. */
482 #define ARC_RELOC_TABLE(op) \
483 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
485 : (int) (op) - (int) O_gotoff) ])
487 #define DEF(NAME, RELOC, REQ) \
488 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
490 static const struct arc_reloc_op_tag
492 /* String to lookup. */
494 /* Size of the string. */
496 /* Which operator to use. */
498 extended_bfd_reloc_code_real_type reloc
;
499 /* Allows complex relocation expression like identifier@reloc +
501 unsigned int complex_expr
: 1;
505 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
506 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
507 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
508 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
509 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
510 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
511 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
512 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
513 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
514 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
515 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 1),
518 static const int arc_num_reloc_op
519 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
521 /* Structure for relaxable instruction that have to be swapped with a
522 smaller alternative instruction. */
523 struct arc_relaxable_ins
525 /* Mnemonic that should be checked. */
526 const char *mnemonic_r
;
528 /* Operands that should be checked.
529 Indexes of operands from operand array. */
530 enum rlx_operand_type operands
[6];
532 /* Flags that should be checked. */
533 unsigned flag_classes
[5];
535 /* Mnemonic (smaller) alternative to be used later for relaxation. */
536 const char *mnemonic_alt
;
538 /* Index of operand that generic relaxation has to check. */
541 /* Base subtype index used. */
542 enum arc_rlx_types subtype
;
545 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
546 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
547 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
551 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
552 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
553 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
558 /* ARC relaxation table. */
559 const relax_typeS md_relax_table
[] =
566 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL
),
567 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
571 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B
),
572 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
577 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6
),
578 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM
),
579 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
581 /* LD_S a, [b, u7] ->
582 LD<zz><.x><.aa><.di> a, [b, s9] ->
583 LD<zz><.x><.aa><.di> a, [b, limm] */
584 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9
),
585 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM
),
586 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE
),
591 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12
),
592 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM
),
593 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
597 SUB<.f> a, b, limm. */
598 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6
),
599 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM
),
600 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
602 /* MPY<.f> a, b, u6 ->
603 MPY<.f> a, b, limm. */
604 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM
),
605 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
607 /* MOV<.f><.cc> b, u6 ->
608 MOV<.f><.cc> b, limm. */
609 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM
),
610 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
612 /* ADD<.f><.cc> b, b, u6 ->
613 ADD<.f><.cc> b, b, limm. */
614 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM
),
615 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
618 /* Order of this table's entries matters! */
619 const struct arc_relaxable_ins arc_relaxable_insns
[] =
621 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
622 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
623 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
624 2, ARC_RLX_ADD_RRU6
},
625 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
627 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
629 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
630 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
631 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
632 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
633 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
634 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
635 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
636 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
638 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
640 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
644 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
646 /* Flags to set in the elf header. */
647 static flagword arc_eflag
= 0x00;
649 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
650 symbolS
* GOT_symbol
= 0;
652 /* Set to TRUE when we assemble instructions. */
653 static bfd_boolean assembling_insn
= FALSE
;
655 /* Functions implementation. */
657 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
658 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
659 are no matching entries in ARC_OPCODE_HASH. */
661 static const struct arc_opcode_hash_entry
*
662 arc_find_opcode (const char *name
)
664 const struct arc_opcode_hash_entry
*entry
;
666 entry
= hash_find (arc_opcode_hash
, name
);
670 /* Initialise the iterator ITER. */
673 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
679 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
680 calls to this function. Return NULL when all ARC_OPCODE entries have
683 static const struct arc_opcode
*
684 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
685 struct arc_opcode_hash_entry_iterator
*iter
)
687 if (iter
->opcode
== NULL
&& iter
->index
== 0)
689 gas_assert (entry
->count
> 0);
690 iter
->opcode
= entry
->opcode
[iter
->index
];
692 else if (iter
->opcode
!= NULL
)
694 const char *old_name
= iter
->opcode
->name
;
697 if (iter
->opcode
->name
== NULL
698 || strcmp (old_name
, iter
->opcode
->name
) != 0)
701 if (iter
->index
== entry
->count
)
704 iter
->opcode
= entry
->opcode
[iter
->index
];
711 /* Insert an opcode into opcode hash structure. */
714 arc_insert_opcode (const struct arc_opcode
*opcode
)
716 const char *name
, *retval
;
717 struct arc_opcode_hash_entry
*entry
;
720 entry
= hash_find (arc_opcode_hash
, name
);
723 entry
= XNEW (struct arc_opcode_hash_entry
);
725 entry
->opcode
= NULL
;
727 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
729 as_fatal (_("internal error: can't hash opcode '%s': %s"),
733 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
736 if (entry
->opcode
== NULL
)
737 as_fatal (_("Virtual memory exhausted"));
739 entry
->opcode
[entry
->count
] = opcode
;
744 /* Like md_number_to_chars but used for limms. The 4-byte limm value,
745 is encoded as 'middle-endian' for a little-endian target. FIXME!
746 this function is used for regular 4 byte instructions as well. */
749 md_number_to_chars_midend (char *buf
, valueT val
, int n
)
753 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
754 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
758 md_number_to_chars (buf
, val
, n
);
762 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
763 the relevant static global variables. */
766 arc_select_cpu (const char *arg
)
771 for (i
= 0; cpu_types
[i
].name
; ++i
)
773 if (!strcasecmp (cpu_types
[i
].name
, arg
))
775 arc_target
= cpu_types
[i
].flags
;
776 arc_target_name
= cpu_types
[i
].name
;
777 arc_features
= cpu_types
[i
].features
;
778 arc_mach_type
= cpu_types
[i
].mach
;
779 cpu_flags
= cpu_types
[i
].eflags
;
784 if (!cpu_types
[i
].name
)
785 as_fatal (_("unknown architecture: %s\n"), arg
);
786 gas_assert (cpu_flags
!= 0);
787 arc_eflag
= (arc_eflag
& ~EF_ARC_MACH_MSK
) | cpu_flags
;
790 /* Here ends all the ARCompact extension instruction assembling
794 arc_extra_reloc (int r_type
)
797 symbolS
*sym
, *lab
= NULL
;
799 if (*input_line_pointer
== '@')
800 input_line_pointer
++;
801 c
= get_symbol_name (&sym_name
);
802 sym
= symbol_find_or_make (sym_name
);
803 restore_line_pointer (c
);
804 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
806 ++input_line_pointer
;
808 c
= get_symbol_name (&lab_name
);
809 lab
= symbol_find_or_make (lab_name
);
810 restore_line_pointer (c
);
813 /* These relocations exist as a mechanism for the compiler to tell the
814 linker how to patch the code if the tls model is optimised. However,
815 the relocation itself does not require any space within the assembler
816 fragment, and so we pass a size of 0.
818 The lines that generate these relocations look like this:
820 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
822 The '.tls_gd_ld @.tdata' is processed first and generates the
823 additional relocation, while the 'bl __tls_get_addr@plt' is processed
824 second and generates the additional branch.
826 It is possible that the additional relocation generated by the
827 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
828 while the 'bl __tls_get_addr@plt' will be generated as the first thing
829 in the next fragment. This will be fine; both relocations will still
830 appear to be at the same address in the generated object file.
831 However, this only works as the additional relocation is generated
832 with size of 0 bytes. */
834 = fix_new (frag_now
, /* Which frag? */
835 frag_now_fix (), /* Where in that frag? */
836 0, /* size: 1, 2, or 4 usually. */
837 sym
, /* X_add_symbol. */
838 0, /* X_add_number. */
839 FALSE
, /* TRUE if PC-relative relocation. */
840 r_type
/* Relocation type. */);
841 fixP
->fx_subsy
= lab
;
845 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
846 symbolS
*symbolP
, addressT size
)
851 if (*input_line_pointer
== ',')
853 align
= parse_align (1);
855 if (align
== (addressT
) -1)
870 bss_alloc (symbolP
, size
, align
);
871 S_CLEAR_EXTERNAL (symbolP
);
877 arc_lcomm (int ignore
)
879 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
882 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
885 /* Select the cpu we're assembling for. */
888 arc_option (int ignore ATTRIBUTE_UNUSED
)
894 c
= get_symbol_name (&cpu
);
895 mach
= arc_get_mach (cpu
);
900 if (!mach_type_specified_p
)
902 if ((!strcmp ("ARC600", cpu
))
903 || (!strcmp ("ARC601", cpu
))
904 || (!strcmp ("A6", cpu
)))
906 md_parse_option (OPTION_MCPU
, "arc600");
908 else if ((!strcmp ("ARC700", cpu
))
909 || (!strcmp ("A7", cpu
)))
911 md_parse_option (OPTION_MCPU
, "arc700");
913 else if (!strcmp ("EM", cpu
))
915 md_parse_option (OPTION_MCPU
, "arcem");
917 else if (!strcmp ("HS", cpu
))
919 md_parse_option (OPTION_MCPU
, "archs");
921 else if (!strcmp ("NPS400", cpu
))
923 md_parse_option (OPTION_MCPU
, "nps400");
926 as_fatal (_("could not find the architecture"));
928 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, mach
))
929 as_fatal (_("could not set architecture and machine"));
931 /* Set elf header flags. */
932 bfd_set_private_flags (stdoutput
, arc_eflag
);
935 if (arc_mach_type
!= mach
)
936 as_warn (_("Command-line value overrides \".cpu\" directive"));
938 restore_line_pointer (c
);
939 demand_empty_rest_of_line ();
943 restore_line_pointer (c
);
944 as_bad (_("invalid identifier for \".cpu\""));
945 ignore_rest_of_line ();
948 /* Smartly print an expression. */
951 debug_exp (expressionS
*t
)
953 const char *name ATTRIBUTE_UNUSED
;
954 const char *namemd ATTRIBUTE_UNUSED
;
956 pr_debug ("debug_exp: ");
960 default: name
= "unknown"; break;
961 case O_illegal
: name
= "O_illegal"; break;
962 case O_absent
: name
= "O_absent"; break;
963 case O_constant
: name
= "O_constant"; break;
964 case O_symbol
: name
= "O_symbol"; break;
965 case O_symbol_rva
: name
= "O_symbol_rva"; break;
966 case O_register
: name
= "O_register"; break;
967 case O_big
: name
= "O_big"; break;
968 case O_uminus
: name
= "O_uminus"; break;
969 case O_bit_not
: name
= "O_bit_not"; break;
970 case O_logical_not
: name
= "O_logical_not"; break;
971 case O_multiply
: name
= "O_multiply"; break;
972 case O_divide
: name
= "O_divide"; break;
973 case O_modulus
: name
= "O_modulus"; break;
974 case O_left_shift
: name
= "O_left_shift"; break;
975 case O_right_shift
: name
= "O_right_shift"; break;
976 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
977 case O_bit_or_not
: name
= "O_bit_or_not"; break;
978 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
979 case O_bit_and
: name
= "O_bit_and"; break;
980 case O_add
: name
= "O_add"; break;
981 case O_subtract
: name
= "O_subtract"; break;
982 case O_eq
: name
= "O_eq"; break;
983 case O_ne
: name
= "O_ne"; break;
984 case O_lt
: name
= "O_lt"; break;
985 case O_le
: name
= "O_le"; break;
986 case O_ge
: name
= "O_ge"; break;
987 case O_gt
: name
= "O_gt"; break;
988 case O_logical_and
: name
= "O_logical_and"; break;
989 case O_logical_or
: name
= "O_logical_or"; break;
990 case O_index
: name
= "O_index"; break;
991 case O_bracket
: name
= "O_bracket"; break;
992 case O_colon
: name
= "O_colon"; break;
993 case O_addrtype
: name
= "O_addrtype"; break;
998 default: namemd
= "unknown"; break;
999 case O_gotoff
: namemd
= "O_gotoff"; break;
1000 case O_gotpc
: namemd
= "O_gotpc"; break;
1001 case O_plt
: namemd
= "O_plt"; break;
1002 case O_sda
: namemd
= "O_sda"; break;
1003 case O_pcl
: namemd
= "O_pcl"; break;
1004 case O_tlsgd
: namemd
= "O_tlsgd"; break;
1005 case O_tlsie
: namemd
= "O_tlsie"; break;
1006 case O_tpoff9
: namemd
= "O_tpoff9"; break;
1007 case O_tpoff
: namemd
= "O_tpoff"; break;
1008 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
1009 case O_dtpoff
: namemd
= "O_dtpoff"; break;
1012 pr_debug ("%s (%s, %s, %d, %s)", name
,
1013 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
1014 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
1015 (int) t
->X_add_number
,
1016 (t
->X_md
) ? namemd
: "--");
1021 /* Parse the arguments to an opcode. */
1024 tokenize_arguments (char *str
,
1028 char *old_input_line_pointer
;
1029 bfd_boolean saw_comma
= FALSE
;
1030 bfd_boolean saw_arg
= FALSE
;
1035 const struct arc_reloc_op_tag
*r
;
1037 char *reloc_name
, c
;
1039 memset (tok
, 0, sizeof (*tok
) * ntok
);
1041 /* Save and restore input_line_pointer around this function. */
1042 old_input_line_pointer
= input_line_pointer
;
1043 input_line_pointer
= str
;
1045 while (*input_line_pointer
)
1048 switch (*input_line_pointer
)
1054 input_line_pointer
++;
1055 if (saw_comma
|| !saw_arg
)
1062 ++input_line_pointer
;
1064 if (!saw_arg
|| num_args
== ntok
)
1066 tok
->X_op
= O_bracket
;
1073 input_line_pointer
++;
1074 if (brk_lvl
|| num_args
== ntok
)
1077 tok
->X_op
= O_bracket
;
1083 input_line_pointer
++;
1084 if (!saw_arg
|| num_args
== ntok
)
1086 tok
->X_op
= O_colon
;
1093 /* We have labels, function names and relocations, all
1094 starting with @ symbol. Sort them out. */
1095 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1099 tok
->X_op
= O_symbol
;
1100 tok
->X_md
= O_absent
;
1102 if (*input_line_pointer
!= '@')
1103 goto normalsymbol
; /* This is not a relocation. */
1107 /* A relocation opernad has the following form
1108 @identifier@relocation_type. The identifier is already
1110 if (tok
->X_op
!= O_symbol
)
1112 as_bad (_("No valid label relocation operand"));
1116 /* Parse @relocation_type. */
1117 input_line_pointer
++;
1118 c
= get_symbol_name (&reloc_name
);
1119 len
= input_line_pointer
- reloc_name
;
1122 as_bad (_("No relocation operand"));
1126 /* Go through known relocation and try to find a match. */
1127 r
= &arc_reloc_op
[0];
1128 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1129 if (len
== r
->length
1130 && memcmp (reloc_name
, r
->name
, len
) == 0)
1134 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1138 *input_line_pointer
= c
;
1139 SKIP_WHITESPACE_AFTER_NAME ();
1140 /* Extra check for TLS: base. */
1141 if (*input_line_pointer
== '@')
1144 if (tok
->X_op_symbol
!= NULL
1145 || tok
->X_op
!= O_symbol
)
1147 as_bad (_("Unable to parse TLS base: %s"),
1148 input_line_pointer
);
1151 input_line_pointer
++;
1153 c
= get_symbol_name (&sym_name
);
1154 base
= symbol_find_or_make (sym_name
);
1155 tok
->X_op
= O_subtract
;
1156 tok
->X_op_symbol
= base
;
1157 restore_line_pointer (c
);
1158 tmpE
.X_add_number
= 0;
1160 if ((*input_line_pointer
!= '+')
1161 && (*input_line_pointer
!= '-'))
1163 tmpE
.X_add_number
= 0;
1167 /* Parse the constant of a complex relocation expression
1168 like @identifier@reloc +/- const. */
1169 if (! r
->complex_expr
)
1171 as_bad (_("@%s is not a complex relocation."), r
->name
);
1175 if (tmpE
.X_op
!= O_constant
)
1177 as_bad (_("Bad expression: @%s + %s."),
1178 r
->name
, input_line_pointer
);
1184 tok
->X_add_number
= tmpE
.X_add_number
;
1195 /* Can be a register. */
1196 ++input_line_pointer
;
1200 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1203 tok
->X_op
= O_absent
;
1204 tok
->X_md
= O_absent
;
1207 /* Legacy: There are cases when we have
1208 identifier@relocation_type, if it is the case parse the
1209 relocation type as well. */
1210 if (*input_line_pointer
== '@')
1216 if (tok
->X_op
== O_illegal
1217 || tok
->X_op
== O_absent
1218 || num_args
== ntok
)
1230 if (saw_comma
|| brk_lvl
)
1232 input_line_pointer
= old_input_line_pointer
;
1238 as_bad (_("Brackets in operand field incorrect"));
1240 as_bad (_("extra comma"));
1242 as_bad (_("missing argument"));
1244 as_bad (_("missing comma or colon"));
1245 input_line_pointer
= old_input_line_pointer
;
1249 /* Parse the flags to a structure. */
1252 tokenize_flags (const char *str
,
1253 struct arc_flags flags
[],
1256 char *old_input_line_pointer
;
1257 bfd_boolean saw_flg
= FALSE
;
1258 bfd_boolean saw_dot
= FALSE
;
1262 memset (flags
, 0, sizeof (*flags
) * nflg
);
1264 /* Save and restore input_line_pointer around this function. */
1265 old_input_line_pointer
= input_line_pointer
;
1266 input_line_pointer
= (char *) str
;
1268 while (*input_line_pointer
)
1270 switch (*input_line_pointer
)
1277 input_line_pointer
++;
1285 if (saw_flg
&& !saw_dot
)
1288 if (num_flags
>= nflg
)
1291 flgnamelen
= strspn (input_line_pointer
,
1292 "abcdefghijklmnopqrstuvwxyz0123456789");
1293 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1296 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1298 input_line_pointer
+= flgnamelen
;
1308 input_line_pointer
= old_input_line_pointer
;
1313 as_bad (_("extra dot"));
1315 as_bad (_("unrecognized flag"));
1317 as_bad (_("failed to parse flags"));
1318 input_line_pointer
= old_input_line_pointer
;
1322 /* Apply the fixups in order. */
1325 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1329 for (i
= 0; i
< insn
->nfixups
; i
++)
1331 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1332 int size
, pcrel
, offset
= 0;
1334 /* FIXME! the reloc size is wrong in the BFD file.
1335 When it is fixed please delete me. */
1336 size
= (insn
->short_insn
&& !fixup
->islong
) ? 2 : 4;
1339 offset
= (insn
->short_insn
) ? 2 : 4;
1341 /* Some fixups are only used internally, thus no howto. */
1342 if ((int) fixup
->reloc
== 0)
1343 as_fatal (_("Unhandled reloc type"));
1345 if ((int) fixup
->reloc
< 0)
1347 /* FIXME! the reloc size is wrong in the BFD file.
1348 When it is fixed please enable me.
1349 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1350 pcrel
= fixup
->pcrel
;
1354 reloc_howto_type
*reloc_howto
=
1355 bfd_reloc_type_lookup (stdoutput
,
1356 (bfd_reloc_code_real_type
) fixup
->reloc
);
1357 gas_assert (reloc_howto
);
1359 /* FIXME! the reloc size is wrong in the BFD file.
1360 When it is fixed please enable me.
1361 size = bfd_get_reloc_size (reloc_howto); */
1362 pcrel
= reloc_howto
->pc_relative
;
1365 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1367 fragP
->fr_file
, fragP
->fr_line
,
1368 (fixup
->reloc
< 0) ? "Internal" :
1369 bfd_get_reloc_code_name (fixup
->reloc
),
1372 fix_new_exp (fragP
, fix
+ offset
,
1373 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1375 /* Check for ZOLs, and update symbol info if any. */
1376 if (LP_INSN (insn
->insn
))
1378 gas_assert (fixup
->exp
.X_add_symbol
);
1379 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1384 /* Actually output an instruction with its fixup. */
1387 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1391 pr_debug ("Emit insn : 0x%x\n", insn
->insn
);
1392 pr_debug ("\tShort : 0x%d\n", insn
->short_insn
);
1393 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1395 /* Write out the instruction. */
1396 if (insn
->short_insn
)
1402 md_number_to_chars (f
, insn
->insn
, 2);
1403 md_number_to_chars_midend (f
+ 2, insn
->limm
, 4);
1404 dwarf2_emit_insn (6);
1410 md_number_to_chars (f
, insn
->insn
, 2);
1411 dwarf2_emit_insn (2);
1420 md_number_to_chars_midend (f
, insn
->insn
, 4);
1421 md_number_to_chars_midend (f
+ 4, insn
->limm
, 4);
1422 dwarf2_emit_insn (8);
1428 md_number_to_chars_midend (f
, insn
->insn
, 4);
1429 dwarf2_emit_insn (4);
1434 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1438 emit_insn1 (struct arc_insn
*insn
)
1440 /* How frag_var's args are currently configured:
1441 - rs_machine_dependent, to dictate it's a relaxation frag.
1442 - FRAG_MAX_GROWTH, maximum size of instruction
1443 - 0, variable size that might grow...unused by generic relaxation.
1444 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1445 - s, opand expression.
1446 - 0, offset but it's unused.
1447 - 0, opcode but it's unused. */
1448 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1449 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1451 if (frag_room () < FRAG_MAX_GROWTH
)
1453 /* Handle differently when frag literal memory is exhausted.
1454 This is used because when there's not enough memory left in
1455 the current frag, a new frag is created and the information
1456 we put into frag_now->tc_frag_data is disregarded. */
1458 struct arc_relax_type relax_info_copy
;
1459 relax_substateT subtype
= frag_now
->fr_subtype
;
1461 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1462 sizeof (struct arc_relax_type
));
1464 frag_wane (frag_now
);
1465 frag_grow (FRAG_MAX_GROWTH
);
1467 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1468 sizeof (struct arc_relax_type
));
1470 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1474 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1475 frag_now
->fr_subtype
, s
, 0, 0);
1479 emit_insn (struct arc_insn
*insn
)
1484 emit_insn0 (insn
, NULL
, FALSE
);
1487 /* Check whether a symbol involves a register. */
1490 contains_register (symbolS
*sym
)
1494 expressionS
*ex
= symbol_get_value_expression (sym
);
1496 return ((O_register
== ex
->X_op
)
1497 && !contains_register (ex
->X_add_symbol
)
1498 && !contains_register (ex
->X_op_symbol
));
1504 /* Returns the register number within a symbol. */
1507 get_register (symbolS
*sym
)
1509 if (!contains_register (sym
))
1512 expressionS
*ex
= symbol_get_value_expression (sym
);
1513 return regno (ex
->X_add_number
);
1516 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1517 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1520 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1527 case BFD_RELOC_ARC_SDA_LDST
:
1528 case BFD_RELOC_ARC_SDA_LDST1
:
1529 case BFD_RELOC_ARC_SDA_LDST2
:
1530 case BFD_RELOC_ARC_SDA16_LD
:
1531 case BFD_RELOC_ARC_SDA16_LD1
:
1532 case BFD_RELOC_ARC_SDA16_LD2
:
1533 case BFD_RELOC_ARC_SDA16_ST2
:
1534 case BFD_RELOC_ARC_SDA32_ME
:
1541 /* Allocates a tok entry. */
1544 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1546 if (ntok
> MAX_INSN_ARGS
- 2)
1547 return 0; /* No space left. */
1550 return 0; /* Incorect args. */
1552 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1555 return 1; /* Success. */
1556 return allocate_tok (tok
, ntok
- 1, cidx
);
1559 /* Check if an particular ARC feature is enabled. */
1562 check_cpu_feature (insn_subclass_t sc
)
1564 if (is_code_density_p (sc
) && !(arc_features
& ARC_CD
))
1567 if (is_spfp_p (sc
) && !(arc_features
& ARC_SPFP
))
1570 if (is_dpfp_p (sc
) && !(arc_features
& ARC_DPFP
))
1573 if (is_fpuda_p (sc
) && !(arc_features
& ARC_FPUDA
))
1576 if (is_nps400_p (sc
) && !(arc_features
& ARC_NPS400
))
1582 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1583 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1584 array and returns TRUE if the flag operands all match, otherwise,
1585 returns FALSE, in which case the FIRST_PFLAG array may have been
1589 parse_opcode_flags (const struct arc_opcode
*opcode
,
1591 struct arc_flags
*first_pflag
)
1594 const unsigned char *flgidx
;
1597 for (i
= 0; i
< nflgs
; i
++)
1598 first_pflag
[i
].flgp
= NULL
;
1600 /* Check the flags. Iterate over the valid flag classes. */
1601 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1603 /* Get a valid flag class. */
1604 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1605 const unsigned *flgopridx
;
1607 struct arc_flags
*pflag
= NULL
;
1609 /* Check for extension conditional codes. */
1610 if (ext_condcode
.arc_ext_condcode
1611 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1613 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1616 pflag
= first_pflag
;
1617 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1619 if (!strcmp (pf
->name
, pflag
->name
))
1621 if (pflag
->flgp
!= NULL
)
1634 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1636 const struct arc_flag_operand
*flg_operand
;
1638 pflag
= first_pflag
;
1639 flg_operand
= &arc_flag_operands
[*flgopridx
];
1640 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1642 /* Match against the parsed flags. */
1643 if (!strcmp (flg_operand
->name
, pflag
->name
))
1645 if (pflag
->flgp
!= NULL
)
1648 pflag
->flgp
= flg_operand
;
1650 break; /* goto next flag class and parsed flag. */
1655 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1657 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1661 /* Did I check all the parsed flags? */
1662 return lnflg
? FALSE
: TRUE
;
1666 /* Search forward through all variants of an opcode looking for a
1669 static const struct arc_opcode
*
1670 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1673 struct arc_flags
*first_pflag
,
1677 const struct arc_opcode
*opcode
;
1678 struct arc_opcode_hash_entry_iterator iter
;
1680 int got_cpu_match
= 0;
1681 expressionS bktok
[MAX_INSN_ARGS
];
1685 arc_opcode_hash_entry_iterator_init (&iter
);
1686 memset (&emptyE
, 0, sizeof (emptyE
));
1687 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1690 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1692 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1694 const unsigned char *opidx
;
1696 const expressionS
*t
= &emptyE
;
1698 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1699 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1701 /* Don't match opcodes that don't exist on this
1703 if (!(opcode
->cpu
& arc_target
))
1706 if (!check_cpu_feature (opcode
->subclass
))
1712 /* Check the operands. */
1713 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1715 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1717 /* Only take input from real operands. */
1718 if (ARC_OPERAND_IS_FAKE (operand
))
1721 /* When we expect input, make sure we have it. */
1725 /* Match operand type with expression type. */
1726 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1728 case ARC_OPERAND_ADDRTYPE
:
1729 /* Check to be an address type. */
1730 if (tok
[tokidx
].X_op
!= O_addrtype
)
1734 case ARC_OPERAND_IR
:
1735 /* Check to be a register. */
1736 if ((tok
[tokidx
].X_op
!= O_register
1737 || !is_ir_num (tok
[tokidx
].X_add_number
))
1738 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1741 /* If expect duplicate, make sure it is duplicate. */
1742 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1744 /* Check for duplicate. */
1745 if (t
->X_op
!= O_register
1746 || !is_ir_num (t
->X_add_number
)
1747 || (regno (t
->X_add_number
) !=
1748 regno (tok
[tokidx
].X_add_number
)))
1752 /* Special handling? */
1753 if (operand
->insert
)
1755 const char *errmsg
= NULL
;
1756 (*operand
->insert
)(0,
1757 regno (tok
[tokidx
].X_add_number
),
1761 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1763 /* Missing argument, create one. */
1764 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1767 tok
[tokidx
].X_op
= O_absent
;
1778 case ARC_OPERAND_BRAKET
:
1779 /* Check if bracket is also in opcode table as
1781 if (tok
[tokidx
].X_op
!= O_bracket
)
1785 case ARC_OPERAND_COLON
:
1786 /* Check if colon is also in opcode table as operand. */
1787 if (tok
[tokidx
].X_op
!= O_colon
)
1791 case ARC_OPERAND_LIMM
:
1792 case ARC_OPERAND_SIGNED
:
1793 case ARC_OPERAND_UNSIGNED
:
1794 switch (tok
[tokidx
].X_op
)
1802 /* Got an (too) early bracket, check if it is an
1803 ignored operand. N.B. This procedure works only
1804 when bracket is the last operand! */
1805 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1807 /* Insert the missing operand. */
1808 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1811 tok
[tokidx
].X_op
= O_absent
;
1818 const struct arc_aux_reg
*auxr
;
1820 if (opcode
->insn_class
!= AUXREG
)
1822 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1824 auxr
= hash_find (arc_aux_hash
, p
);
1827 /* We modify the token array here, safe in the
1828 knowledge, that if this was the wrong
1829 choice then the original contents will be
1830 restored from BKTOK. */
1831 tok
[tokidx
].X_op
= O_constant
;
1832 tok
[tokidx
].X_add_number
= auxr
->address
;
1833 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1836 if (tok
[tokidx
].X_op
!= O_constant
)
1841 /* Check the range. */
1842 if (operand
->bits
!= 32
1843 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1845 offsetT min
, max
, val
;
1846 val
= tok
[tokidx
].X_add_number
;
1848 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1850 max
= (1 << (operand
->bits
- 1)) - 1;
1851 min
= -(1 << (operand
->bits
- 1));
1855 max
= (1 << operand
->bits
) - 1;
1859 if (val
< min
|| val
> max
)
1862 /* Check alignmets. */
1863 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1867 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1871 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1873 if (operand
->insert
)
1875 const char *errmsg
= NULL
;
1876 (*operand
->insert
)(0,
1877 tok
[tokidx
].X_add_number
,
1882 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1888 /* Check if it is register range. */
1889 if ((tok
[tokidx
].X_add_number
== 0)
1890 && contains_register (tok
[tokidx
].X_add_symbol
)
1891 && contains_register (tok
[tokidx
].X_op_symbol
))
1895 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1897 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1898 if (operand
->insert
)
1900 const char *errmsg
= NULL
;
1901 (*operand
->insert
)(0,
1914 if (operand
->default_reloc
== 0)
1915 goto match_failed
; /* The operand needs relocation. */
1917 /* Relocs requiring long immediate. FIXME! make it
1918 generic and move it to a function. */
1919 switch (tok
[tokidx
].X_md
)
1928 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
1932 if (!generic_reloc_p (operand
->default_reloc
))
1940 /* If expect duplicate, make sure it is duplicate. */
1941 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1943 if (t
->X_op
== O_illegal
1944 || t
->X_op
== O_absent
1945 || t
->X_op
== O_register
1946 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
1953 /* Everything else should have been fake. */
1961 /* Setup ready for flag parsing. */
1962 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
1966 /* Possible match -- did we use all of our input? */
1976 /* Restore the original parameters. */
1977 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
1982 *pcpumatch
= got_cpu_match
;
1987 /* Swap operand tokens. */
1990 swap_operand (expressionS
*operand_array
,
1992 unsigned destination
)
1994 expressionS cpy_operand
;
1995 expressionS
*src_operand
;
1996 expressionS
*dst_operand
;
1999 if (source
== destination
)
2002 src_operand
= &operand_array
[source
];
2003 dst_operand
= &operand_array
[destination
];
2004 size
= sizeof (expressionS
);
2006 /* Make copy of operand to swap with and swap. */
2007 memcpy (&cpy_operand
, dst_operand
, size
);
2008 memcpy (dst_operand
, src_operand
, size
);
2009 memcpy (src_operand
, &cpy_operand
, size
);
2012 /* Check if *op matches *tok type.
2013 Returns FALSE if they don't match, TRUE if they match. */
2016 pseudo_operand_match (const expressionS
*tok
,
2017 const struct arc_operand_operation
*op
)
2019 offsetT min
, max
, val
;
2021 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
2027 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
2029 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
2031 val
= tok
->X_add_number
+ op
->count
;
2032 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
2034 max
= (1 << (operand_real
->bits
- 1)) - 1;
2035 min
= -(1 << (operand_real
->bits
- 1));
2039 max
= (1 << operand_real
->bits
) - 1;
2042 if (min
<= val
&& val
<= max
)
2048 /* Handle all symbols as long immediates or signed 9. */
2049 if (operand_real
->flags
& ARC_OPERAND_LIMM
2050 || ((operand_real
->flags
& ARC_OPERAND_SIGNED
)
2051 && operand_real
->bits
== 9))
2056 if (operand_real
->flags
& ARC_OPERAND_IR
)
2061 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2072 /* Find pseudo instruction in array. */
2074 static const struct arc_pseudo_insn
*
2075 find_pseudo_insn (const char *opname
,
2077 const expressionS
*tok
)
2079 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2080 const struct arc_operand_operation
*op
;
2084 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2086 pseudo_insn
= &arc_pseudo_insns
[i
];
2087 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2089 op
= pseudo_insn
->operand
;
2090 for (j
= 0; j
< ntok
; ++j
)
2091 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2094 /* Found the right instruction. */
2102 /* Assumes the expressionS *tok is of sufficient size. */
2104 static const struct arc_opcode_hash_entry
*
2105 find_special_case_pseudo (const char *opname
,
2109 struct arc_flags
*pflags
)
2111 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2112 const struct arc_operand_operation
*operand_pseudo
;
2113 const struct arc_operand
*operand_real
;
2115 char construct_operand
[MAX_CONSTR_STR
];
2117 /* Find whether opname is in pseudo instruction array. */
2118 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2120 if (pseudo_insn
== NULL
)
2123 /* Handle flag, Limited to one flag at the moment. */
2124 if (pseudo_insn
->flag_r
!= NULL
)
2125 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2126 MAX_INSN_FLGS
- *nflgs
);
2128 /* Handle operand operations. */
2129 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2131 operand_pseudo
= &pseudo_insn
->operand
[i
];
2132 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2134 if (operand_real
->flags
& ARC_OPERAND_BRAKET
2135 && !operand_pseudo
->needs_insert
)
2138 /* Has to be inserted (i.e. this token does not exist yet). */
2139 if (operand_pseudo
->needs_insert
)
2141 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2143 tok
[i
].X_op
= O_bracket
;
2148 /* Check if operand is a register or constant and handle it
2150 if (operand_real
->flags
& ARC_OPERAND_IR
)
2151 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2152 operand_pseudo
->count
);
2154 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2155 operand_pseudo
->count
);
2157 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2161 else if (operand_pseudo
->count
)
2163 /* Operand number has to be adjusted accordingly (by operand
2165 switch (tok
[i
].X_op
)
2168 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2181 /* Swap operands if necessary. Only supports one swap at the
2183 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2185 operand_pseudo
= &pseudo_insn
->operand
[i
];
2187 if (operand_pseudo
->swap_operand_idx
== i
)
2190 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2192 /* Prevent a swap back later by breaking out. */
2196 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2199 static const struct arc_opcode_hash_entry
*
2200 find_special_case_flag (const char *opname
,
2202 struct arc_flags
*pflags
)
2206 unsigned flag_idx
, flag_arr_idx
;
2207 size_t flaglen
, oplen
;
2208 const struct arc_flag_special
*arc_flag_special_opcode
;
2209 const struct arc_opcode_hash_entry
*entry
;
2211 /* Search for special case instruction. */
2212 for (i
= 0; i
< arc_num_flag_special
; i
++)
2214 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2215 oplen
= strlen (arc_flag_special_opcode
->name
);
2217 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2220 /* Found a potential special case instruction, now test for
2222 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2224 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2226 break; /* End of array, nothing found. */
2228 flagnm
= arc_flag_operands
[flag_idx
].name
;
2229 flaglen
= strlen (flagnm
);
2230 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2232 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2234 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2236 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2237 pflags
[*nflgs
].name
[flaglen
] = '\0';
2246 /* The long instructions are not stored in a hash (there's not many of
2247 them) and so there's no arc_opcode_hash_entry structure to return. This
2248 helper function for find_special_case_long_opcode takes an arc_opcode
2249 result and places it into a fake arc_opcode_hash_entry that points to
2250 the single arc_opcode OPCODE, which is then returned. */
2252 static const struct arc_opcode_hash_entry
*
2253 build_fake_opcode_hash_entry (const struct arc_opcode
*opcode
)
2255 static struct arc_opcode_hash_entry entry
;
2256 static struct arc_opcode tmp
[2];
2257 static const struct arc_opcode
*ptr
[2];
2259 memcpy (&tmp
[0], opcode
, sizeof (struct arc_opcode
));
2260 memset (&tmp
[1], 0, sizeof (struct arc_opcode
));
2269 /* Used by the assembler to match the list of tokens against a long (48 or
2270 64 bits) instruction. If a matching long instruction is found, then
2271 some of the tokens are consumed in this function and converted into a
2272 single LIMM value, which is then added to the end of the token list,
2273 where it will be consumed by a LIMM operand that exists in the base
2274 opcode of the long instruction. */
2276 static const struct arc_opcode_hash_entry
*
2277 find_special_case_long_opcode (const char *opname
,
2278 int *ntok ATTRIBUTE_UNUSED
,
2279 expressionS
*tok ATTRIBUTE_UNUSED
,
2281 struct arc_flags
*pflags
)
2285 if (*ntok
== MAX_INSN_ARGS
)
2288 for (i
= 0; i
< arc_num_long_opcodes
; ++i
)
2290 struct arc_opcode fake_opcode
;
2291 const struct arc_opcode
*opcode
;
2292 struct arc_insn insn
;
2293 expressionS
*limm_token
;
2295 opcode
= &arc_long_opcodes
[i
].base_opcode
;
2297 if (!(opcode
->cpu
& arc_target
))
2300 if (!check_cpu_feature (opcode
->subclass
))
2303 if (strcmp (opname
, opcode
->name
) != 0)
2306 /* Check that the flags are a match. */
2307 if (!parse_opcode_flags (opcode
, *nflgs
, pflags
))
2310 /* Parse the LIMM operands into the LIMM template. */
2311 memset (&fake_opcode
, 0, sizeof (fake_opcode
));
2312 fake_opcode
.name
= "fake limm";
2313 fake_opcode
.opcode
= arc_long_opcodes
[i
].limm_template
;
2314 fake_opcode
.mask
= arc_long_opcodes
[i
].limm_mask
;
2315 fake_opcode
.cpu
= opcode
->cpu
;
2316 fake_opcode
.insn_class
= opcode
->insn_class
;
2317 fake_opcode
.subclass
= opcode
->subclass
;
2318 memcpy (&fake_opcode
.operands
[0],
2319 &arc_long_opcodes
[i
].operands
,
2321 /* Leave fake_opcode.flags as zero. */
2323 pr_debug ("Calling assemble_insn to build fake limm value\n");
2324 assemble_insn (&fake_opcode
, tok
, *ntok
,
2326 pr_debug (" got limm value: 0x%x\n", insn
.insn
);
2328 /* Now create a new token at the end of the token array (We know this
2329 is safe as the token array is always created with enough space for
2330 MAX_INSN_ARGS, and we check at the start at the start of this
2331 function that we're not there yet). This new token will
2332 correspond to a LIMM operand that will be contained in the
2333 base_opcode of the arc_long_opcode. */
2334 limm_token
= &tok
[(*ntok
)];
2337 /* Modify the LIMM token to hold the constant. */
2338 limm_token
->X_op
= O_constant
;
2339 limm_token
->X_add_number
= insn
.insn
;
2341 /* Return the base opcode. */
2342 return build_fake_opcode_hash_entry (opcode
);
2348 /* Used to find special case opcode. */
2350 static const struct arc_opcode_hash_entry
*
2351 find_special_case (const char *opname
,
2353 struct arc_flags
*pflags
,
2357 const struct arc_opcode_hash_entry
*entry
;
2359 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2362 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2365 entry
= find_special_case_long_opcode (opname
, ntok
, tok
, nflgs
, pflags
);
2370 /* Given an opcode name, pre-tockenized set of argumenst and the
2371 opcode flags, take it all the way through emission. */
2374 assemble_tokens (const char *opname
,
2377 struct arc_flags
*pflags
,
2380 bfd_boolean found_something
= FALSE
;
2381 const struct arc_opcode_hash_entry
*entry
;
2384 /* Search opcodes. */
2385 entry
= arc_find_opcode (opname
);
2387 /* Couldn't find opcode conventional way, try special cases. */
2389 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2393 const struct arc_opcode
*opcode
;
2395 pr_debug ("%s:%d: assemble_tokens: %s\n",
2396 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2397 found_something
= TRUE
;
2398 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2402 struct arc_insn insn
;
2404 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2410 if (found_something
)
2413 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2415 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2419 as_bad (_("unknown opcode '%s'"), opname
);
2422 /* The public interface to the instruction assembler. */
2425 md_assemble (char *str
)
2428 expressionS tok
[MAX_INSN_ARGS
];
2431 struct arc_flags flags
[MAX_INSN_FLGS
];
2433 /* Split off the opcode. */
2434 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2435 opname
= xmemdup0 (str
, opnamelen
);
2437 /* Signalize we are assmbling the instructions. */
2438 assembling_insn
= TRUE
;
2440 /* Tokenize the flags. */
2441 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2443 as_bad (_("syntax error"));
2447 /* Scan up to the end of the mnemonic which must end in space or end
2450 for (; *str
!= '\0'; str
++)
2454 /* Tokenize the rest of the line. */
2455 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2457 as_bad (_("syntax error"));
2461 /* Finish it off. */
2462 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2463 assembling_insn
= FALSE
;
2466 /* Callback to insert a register into the hash table. */
2469 declare_register (const char *name
, int number
)
2472 symbolS
*regS
= symbol_create (name
, reg_section
,
2473 number
, &zero_address_frag
);
2475 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2477 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2481 /* Construct symbols for each of the general registers. */
2484 declare_register_set (void)
2487 for (i
= 0; i
< 64; ++i
)
2491 sprintf (name
, "r%d", i
);
2492 declare_register (name
, i
);
2493 if ((i
& 0x01) == 0)
2495 sprintf (name
, "r%dr%d", i
, i
+1);
2496 declare_register (name
, i
);
2501 /* Construct a symbol for an address type. */
2504 declare_addrtype (const char *name
, int number
)
2507 symbolS
*addrtypeS
= symbol_create (name
, undefined_section
,
2508 number
, &zero_address_frag
);
2510 err
= hash_insert (arc_addrtype_hash
, S_GET_NAME (addrtypeS
),
2511 (void *) addrtypeS
);
2513 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2517 /* Port-specific assembler initialization. This function is called
2518 once, at assembler startup time. */
2523 const struct arc_opcode
*opcode
= arc_opcodes
;
2525 if (!mach_type_specified_p
)
2526 arc_select_cpu (TARGET_WITH_CPU
);
2528 /* The endianness can be chosen "at the factory". */
2529 target_big_endian
= byte_order
== BIG_ENDIAN
;
2531 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, arc_mach_type
))
2532 as_warn (_("could not set architecture and machine"));
2534 /* Set elf header flags. */
2535 bfd_set_private_flags (stdoutput
, arc_eflag
);
2537 /* Set up a hash table for the instructions. */
2538 arc_opcode_hash
= hash_new ();
2539 if (arc_opcode_hash
== NULL
)
2540 as_fatal (_("Virtual memory exhausted"));
2542 /* Initialize the hash table with the insns. */
2545 const char *name
= opcode
->name
;
2547 arc_insert_opcode (opcode
);
2549 while (++opcode
&& opcode
->name
2550 && (opcode
->name
== name
2551 || !strcmp (opcode
->name
, name
)))
2553 }while (opcode
->name
);
2555 /* Register declaration. */
2556 arc_reg_hash
= hash_new ();
2557 if (arc_reg_hash
== NULL
)
2558 as_fatal (_("Virtual memory exhausted"));
2560 declare_register_set ();
2561 declare_register ("gp", 26);
2562 declare_register ("fp", 27);
2563 declare_register ("sp", 28);
2564 declare_register ("ilink", 29);
2565 declare_register ("ilink1", 29);
2566 declare_register ("ilink2", 30);
2567 declare_register ("blink", 31);
2569 /* XY memory registers. */
2570 declare_register ("x0_u0", 32);
2571 declare_register ("x0_u1", 33);
2572 declare_register ("x1_u0", 34);
2573 declare_register ("x1_u1", 35);
2574 declare_register ("x2_u0", 36);
2575 declare_register ("x2_u1", 37);
2576 declare_register ("x3_u0", 38);
2577 declare_register ("x3_u1", 39);
2578 declare_register ("y0_u0", 40);
2579 declare_register ("y0_u1", 41);
2580 declare_register ("y1_u0", 42);
2581 declare_register ("y1_u1", 43);
2582 declare_register ("y2_u0", 44);
2583 declare_register ("y2_u1", 45);
2584 declare_register ("y3_u0", 46);
2585 declare_register ("y3_u1", 47);
2586 declare_register ("x0_nu", 48);
2587 declare_register ("x1_nu", 49);
2588 declare_register ("x2_nu", 50);
2589 declare_register ("x3_nu", 51);
2590 declare_register ("y0_nu", 52);
2591 declare_register ("y1_nu", 53);
2592 declare_register ("y2_nu", 54);
2593 declare_register ("y3_nu", 55);
2595 declare_register ("mlo", 57);
2596 declare_register ("mmid", 58);
2597 declare_register ("mhi", 59);
2599 declare_register ("acc1", 56);
2600 declare_register ("acc2", 57);
2602 declare_register ("lp_count", 60);
2603 declare_register ("pcl", 63);
2605 /* Initialize the last instructions. */
2606 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2608 /* Aux register declaration. */
2609 arc_aux_hash
= hash_new ();
2610 if (arc_aux_hash
== NULL
)
2611 as_fatal (_("Virtual memory exhausted"));
2613 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2615 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2619 if (!(auxr
->cpu
& arc_target
))
2622 if ((auxr
->subclass
!= NONE
)
2623 && !check_cpu_feature (auxr
->subclass
))
2626 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2628 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2629 auxr
->name
, retval
);
2632 /* Address type declaration. */
2633 arc_addrtype_hash
= hash_new ();
2634 if (arc_addrtype_hash
== NULL
)
2635 as_fatal (_("Virtual memory exhausted"));
2637 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD
);
2638 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID
);
2639 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD
);
2640 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD
);
2641 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD
);
2642 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM
);
2643 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA
);
2644 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD
);
2645 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD
);
2646 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD
);
2647 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID
);
2648 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD
);
2649 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM
);
2650 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD
);
2651 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA
);
2652 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD
);
2655 /* Write a value out to the object file, using the appropriate
2659 md_number_to_chars (char *buf
,
2663 if (target_big_endian
)
2664 number_to_chars_bigendian (buf
, val
, n
);
2666 number_to_chars_littleendian (buf
, val
, n
);
2669 /* Round up a section size to the appropriate boundary. */
2672 md_section_align (segT segment
,
2675 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2677 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2680 /* The location from which a PC relative jump should be calculated,
2681 given a PC relative reloc. */
2684 md_pcrel_from_section (fixS
*fixP
,
2687 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2689 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2691 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2692 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2693 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2695 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2697 /* The symbol is undefined (or is defined but not in this section).
2698 Let the linker figure it out. */
2702 if ((int) fixP
->fx_r_type
< 0)
2704 /* These are the "internal" relocations. Align them to
2705 32 bit boundary (PCL), for the moment. */
2710 switch (fixP
->fx_r_type
)
2712 case BFD_RELOC_ARC_PC32
:
2713 /* The hardware calculates relative to the start of the
2714 insn, but this relocation is relative to location of the
2715 LIMM, compensate. The base always needs to be
2716 substracted by 4 as we do not support this type of PCrel
2717 relocation for short instructions. */
2720 case BFD_RELOC_ARC_PLT32
:
2721 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2722 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2723 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2724 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2726 case BFD_RELOC_ARC_S21H_PCREL
:
2727 case BFD_RELOC_ARC_S25H_PCREL
:
2728 case BFD_RELOC_ARC_S13_PCREL
:
2729 case BFD_RELOC_ARC_S21W_PCREL
:
2730 case BFD_RELOC_ARC_S25W_PCREL
:
2734 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2735 _("unhandled reloc %s in md_pcrel_from_section"),
2736 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2741 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2742 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2743 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2744 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2745 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2750 /* Given a BFD relocation find the coresponding operand. */
2752 static const struct arc_operand
*
2753 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2757 for (i
= 0; i
< arc_num_operands
; i
++)
2758 if (arc_operands
[i
].default_reloc
== reloc
)
2759 return &arc_operands
[i
];
2763 /* Insert an operand value into an instruction. */
2766 insert_operand (unsigned insn
,
2767 const struct arc_operand
*operand
,
2772 offsetT min
= 0, max
= 0;
2774 if (operand
->bits
!= 32
2775 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2776 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2778 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2780 max
= (1 << (operand
->bits
- 1)) - 1;
2781 min
= -(1 << (operand
->bits
- 1));
2785 max
= (1 << operand
->bits
) - 1;
2789 if (val
< min
|| val
> max
)
2790 as_bad_value_out_of_range (_("operand"),
2791 val
, min
, max
, file
, line
);
2794 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2795 min
, val
, max
, insn
);
2797 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2799 as_bad_where (file
, line
,
2800 _("Unaligned operand. Needs to be 32bit aligned"));
2802 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2804 as_bad_where (file
, line
,
2805 _("Unaligned operand. Needs to be 16bit aligned"));
2807 if (operand
->insert
)
2809 const char *errmsg
= NULL
;
2811 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2813 as_warn_where (file
, line
, "%s", errmsg
);
2817 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2819 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2821 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2824 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2829 /* Apply a fixup to the object code. At this point all symbol values
2830 should be fully resolved, and we attempt to completely resolve the
2831 reloc. If we can not do that, we determine the correct reloc code
2832 and put it back in the fixup. To indicate that a fixup has been
2833 eliminated, set fixP->fx_done. */
2836 md_apply_fix (fixS
*fixP
,
2840 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2841 valueT value
= *valP
;
2843 symbolS
*fx_addsy
, *fx_subsy
;
2845 segT add_symbol_segment
= absolute_section
;
2846 segT sub_symbol_segment
= absolute_section
;
2847 const struct arc_operand
*operand
= NULL
;
2848 extended_bfd_reloc_code_real_type reloc
;
2850 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2851 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2852 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2853 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2856 fx_addsy
= fixP
->fx_addsy
;
2857 fx_subsy
= fixP
->fx_subsy
;
2862 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2866 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2867 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2868 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2870 resolve_symbol_value (fx_subsy
);
2871 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2873 if (sub_symbol_segment
== absolute_section
)
2875 /* The symbol is really a constant. */
2876 fx_offset
-= S_GET_VALUE (fx_subsy
);
2881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2882 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2883 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2884 segment_name (add_symbol_segment
),
2885 S_GET_NAME (fx_subsy
),
2886 segment_name (sub_symbol_segment
));
2892 && !S_IS_WEAK (fx_addsy
))
2894 if (add_symbol_segment
== seg
2897 value
+= S_GET_VALUE (fx_addsy
);
2898 value
-= md_pcrel_from_section (fixP
, seg
);
2900 fixP
->fx_pcrel
= FALSE
;
2902 else if (add_symbol_segment
== absolute_section
)
2904 value
= fixP
->fx_offset
;
2905 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2907 fixP
->fx_pcrel
= FALSE
;
2912 fixP
->fx_done
= TRUE
;
2917 && ((S_IS_DEFINED (fx_addsy
)
2918 && S_GET_SEGMENT (fx_addsy
) != seg
)
2919 || S_IS_WEAK (fx_addsy
)))
2920 value
+= md_pcrel_from_section (fixP
, seg
);
2922 switch (fixP
->fx_r_type
)
2924 case BFD_RELOC_ARC_32_ME
:
2925 /* This is a pc-relative value in a LIMM. Adjust it to the
2926 address of the instruction not to the address of the
2927 LIMM. Note: it is not anylonger valid this afirmation as
2928 the linker consider ARC_PC32 a fixup to entire 64 bit
2930 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2933 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2935 case BFD_RELOC_ARC_PC32
:
2936 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2939 if ((int) fixP
->fx_r_type
< 0)
2940 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2946 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2947 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2948 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2949 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2953 /* Now check for TLS relocations. */
2954 reloc
= fixP
->fx_r_type
;
2957 case BFD_RELOC_ARC_TLS_DTPOFF
:
2958 case BFD_RELOC_ARC_TLS_LE_32
:
2962 case BFD_RELOC_ARC_TLS_GD_GOT
:
2963 case BFD_RELOC_ARC_TLS_IE_GOT
:
2964 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2967 case BFD_RELOC_ARC_TLS_GD_LD
:
2968 gas_assert (!fixP
->fx_offset
);
2971 = (S_GET_VALUE (fixP
->fx_subsy
)
2972 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2973 fixP
->fx_subsy
= NULL
;
2975 case BFD_RELOC_ARC_TLS_GD_CALL
:
2976 /* These two relocs are there just to allow ld to change the tls
2977 model for this symbol, by patching the code. The offset -
2978 and scale, if any - will be installed by the linker. */
2979 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2982 case BFD_RELOC_ARC_TLS_LE_S9
:
2983 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
2984 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2996 /* Addjust the value if we have a constant. */
2999 /* For hosts with longs bigger than 32-bits make sure that the top
3000 bits of a 32-bit negative value read in by the parser are set,
3001 so that the correct comparisons are made. */
3002 if (value
& 0x80000000)
3003 value
|= (-1UL << 31);
3005 reloc
= fixP
->fx_r_type
;
3013 case BFD_RELOC_ARC_32_PCREL
:
3014 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
3017 case BFD_RELOC_ARC_GOTPC32
:
3018 /* I cannot fix an GOTPC relocation because I need to relax it
3019 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3020 as_bad (_("Unsupported operation on reloc"));
3023 case BFD_RELOC_ARC_TLS_DTPOFF
:
3024 case BFD_RELOC_ARC_TLS_LE_32
:
3025 gas_assert (!fixP
->fx_addsy
);
3026 gas_assert (!fixP
->fx_subsy
);
3029 case BFD_RELOC_ARC_GOTOFF
:
3030 case BFD_RELOC_ARC_32_ME
:
3031 case BFD_RELOC_ARC_PC32
:
3032 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3035 case BFD_RELOC_ARC_PLT32
:
3036 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3039 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3040 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3043 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3044 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
3047 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3048 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3051 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3052 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
3055 case BFD_RELOC_ARC_S25W_PCREL
:
3056 case BFD_RELOC_ARC_S21W_PCREL
:
3057 case BFD_RELOC_ARC_S21H_PCREL
:
3058 case BFD_RELOC_ARC_S25H_PCREL
:
3059 case BFD_RELOC_ARC_S13_PCREL
:
3061 operand
= find_operand_for_reloc (reloc
);
3062 gas_assert (operand
);
3067 if ((int) fixP
->fx_r_type
>= 0)
3068 as_fatal (_("unhandled relocation type %s"),
3069 bfd_get_reloc_code_name (fixP
->fx_r_type
));
3071 /* The rest of these fixups needs to be completely resolved as
3073 if (fixP
->fx_addsy
!= 0
3074 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
3075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3076 _("non-absolute expression in constant field"));
3078 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
3079 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
3084 if (target_big_endian
)
3086 switch (fixP
->fx_size
)
3089 insn
= bfd_getb32 (fixpos
);
3092 insn
= bfd_getb16 (fixpos
);
3095 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3096 _("unknown fixup size"));
3102 switch (fixP
->fx_size
)
3105 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
3108 insn
= bfd_getl16 (fixpos
);
3111 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3112 _("unknown fixup size"));
3116 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3117 fixP
->fx_file
, fixP
->fx_line
);
3119 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3122 /* Prepare machine-dependent frags for relaxation.
3124 Called just before relaxation starts. Any symbol that is now undefined
3125 will not become defined.
3127 Return the correct fr_subtype in the frag.
3129 Return the initial "guess for fr_var" to caller. The guess for fr_var
3130 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3131 or fr_var contributes to our returned value.
3133 Although it may not be explicit in the frag, pretend
3134 fr_var starts with a value. */
3137 md_estimate_size_before_relax (fragS
*fragP
,
3142 /* If the symbol is not located within the same section AND it's not
3143 an absolute section, use the maximum. OR if the symbol is a
3144 constant AND the insn is by nature not pc-rel, use the maximum.
3145 OR if the symbol is being equated against another symbol, use the
3146 maximum. OR if the symbol is weak use the maximum. */
3147 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3148 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3149 || (symbol_constant_p (fragP
->fr_symbol
)
3150 && !fragP
->tc_frag_data
.pcrel
)
3151 || symbol_equated_p (fragP
->fr_symbol
)
3152 || S_IS_WEAK (fragP
->fr_symbol
))
3154 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3155 ++fragP
->fr_subtype
;
3158 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3159 fragP
->fr_var
= growth
;
3161 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3162 fragP
->fr_file
, fragP
->fr_line
, growth
);
3167 /* Translate internal representation of relocation info to BFD target
3171 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3175 bfd_reloc_code_real_type code
;
3177 reloc
= XNEW (arelent
);
3178 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3179 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3180 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3182 /* Make sure none of our internal relocations make it this far.
3183 They'd better have been fully resolved by this point. */
3184 gas_assert ((int) fixP
->fx_r_type
> 0);
3186 code
= fixP
->fx_r_type
;
3188 /* if we have something like add gp, pcl,
3189 _GLOBAL_OFFSET_TABLE_@gotpc. */
3190 if (code
== BFD_RELOC_ARC_GOTPC32
3192 && fixP
->fx_addsy
== GOT_symbol
)
3193 code
= BFD_RELOC_ARC_GOTPC
;
3195 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3196 if (reloc
->howto
== NULL
)
3198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3199 _("cannot represent `%s' relocation in object file"),
3200 bfd_get_reloc_code_name (code
));
3204 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3205 as_fatal (_("internal error? cannot generate `%s' relocation"),
3206 bfd_get_reloc_code_name (code
));
3208 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3210 reloc
->addend
= fixP
->fx_offset
;
3215 /* Perform post-processing of machine-dependent frags after relaxation.
3216 Called after relaxation is finished.
3217 In: Address of frag.
3218 fr_type == rs_machine_dependent.
3219 fr_subtype is what the address relaxed to.
3221 Out: Any fixS:s and constants are set up. */
3224 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3225 segT segment ATTRIBUTE_UNUSED
,
3228 const relax_typeS
*table_entry
;
3230 const struct arc_opcode
*opcode
;
3231 struct arc_insn insn
;
3233 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3235 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
3236 dest
= fragP
->fr_literal
+ fix
;
3237 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3239 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3240 "var: %"BFD_VMA_FMT
"d\n",
3241 fragP
->fr_file
, fragP
->fr_line
,
3242 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3244 if (fragP
->fr_subtype
<= 0
3245 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3246 as_fatal (_("no relaxation found for this instruction."));
3248 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3250 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3251 relax_arg
->nflg
, &insn
);
3253 apply_fixups (&insn
, fragP
, fix
);
3255 size
= insn
.short_insn
? (insn
.has_limm
? 6 : 2) : (insn
.has_limm
? 8 : 4);
3256 gas_assert (table_entry
->rlx_length
== size
);
3257 emit_insn0 (&insn
, dest
, TRUE
);
3259 fragP
->fr_fix
+= table_entry
->rlx_length
;
3263 /* We have no need to default values of symbols. We could catch
3264 register names here, but that is handled by inserting them all in
3265 the symbol table to begin with. */
3268 md_undefined_symbol (char *name
)
3270 /* The arc abi demands that a GOT[0] should be referencible as
3271 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3272 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3274 && (*(name
+1) == 'G')
3275 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
3277 && (*(name
+1) == 'D')
3278 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
3282 if (symbol_find (name
))
3283 as_bad ("GOT already in symbol table");
3285 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3286 (valueT
) 0, &zero_address_frag
);
3293 /* Turn a string in input_line_pointer into a floating point constant
3294 of type type, and store the appropriate bytes in *litP. The number
3295 of LITTLENUMS emitted is stored in *sizeP. An error message is
3296 returned, or NULL on OK. */
3299 md_atof (int type
, char *litP
, int *sizeP
)
3301 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3304 /* Called for any expression that can not be recognized. When the
3305 function is called, `input_line_pointer' will point to the start of
3309 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3311 char *p
= input_line_pointer
;
3314 input_line_pointer
++;
3315 expressionP
->X_op
= O_symbol
;
3316 expression (expressionP
);
3320 /* This function is called from the function 'expression', it attempts
3321 to parse special names (in our case register names). It fills in
3322 the expression with the identified register. It returns TRUE if
3323 it is a register and FALSE otherwise. */
3326 arc_parse_name (const char *name
,
3327 struct expressionS
*e
)
3331 if (!assembling_insn
)
3334 /* Handle only registers and address types. */
3335 if (e
->X_op
!= O_absent
)
3338 sym
= hash_find (arc_reg_hash
, name
);
3341 e
->X_op
= O_register
;
3342 e
->X_add_number
= S_GET_VALUE (sym
);
3346 sym
= hash_find (arc_addrtype_hash
, name
);
3349 e
->X_op
= O_addrtype
;
3350 e
->X_add_number
= S_GET_VALUE (sym
);
3358 Invocation line includes a switch not recognized by the base assembler.
3359 See if it's a processor-specific option.
3361 New options (supported) are:
3363 -mcpu=<cpu name> Assemble for selected processor
3364 -EB/-mbig-endian Big-endian
3365 -EL/-mlittle-endian Little-endian
3366 -mrelax Enable relaxation
3368 The following CPU names are recognized:
3369 arc600, arc700, arcem, archs, nps400. */
3372 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3378 return md_parse_option (OPTION_MCPU
, "arc600");
3381 return md_parse_option (OPTION_MCPU
, "arc700");
3384 return md_parse_option (OPTION_MCPU
, "arcem");
3387 return md_parse_option (OPTION_MCPU
, "archs");
3391 arc_select_cpu (arg
);
3392 mach_type_specified_p
= TRUE
;
3397 arc_target_format
= "elf32-bigarc";
3398 byte_order
= BIG_ENDIAN
;
3402 arc_target_format
= "elf32-littlearc";
3403 byte_order
= LITTLE_ENDIAN
;
3407 /* This option has an effect only on ARC EM. */
3408 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3409 arc_features
|= ARC_CD
;
3411 as_warn (_("Code density option invalid for selected CPU"));
3415 relaxation_state
= 1;
3419 arc_features
|= ARC_NPS400
;
3423 arc_features
|= ARC_SPFP
;
3427 arc_features
|= ARC_DPFP
;
3431 /* This option has an effect only on ARC EM. */
3432 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3433 arc_features
|= ARC_FPUDA
;
3435 as_warn (_("FPUDA invalid for selected CPU"));
3438 /* Dummy options are accepted but have no effect. */
3439 case OPTION_USER_MODE
:
3440 case OPTION_LD_EXT_MASK
:
3443 case OPTION_BARREL_SHIFT
:
3444 case OPTION_MIN_MAX
:
3449 case OPTION_XMAC_D16
:
3450 case OPTION_XMAC_24
:
3451 case OPTION_DSP_PACKA
:
3454 case OPTION_TELEPHONY
:
3455 case OPTION_XYMEMORY
:
3469 md_show_usage (FILE *stream
)
3471 fprintf (stream
, _("ARC-specific assembler options:\n"));
3473 fprintf (stream
, " -mcpu=<cpu name>\t assemble for CPU <cpu name> "
3474 "(default: %s)\n", TARGET_WITH_CPU
);
3475 fprintf (stream
, " -mcpu=nps400\t\t same as -mcpu=arc700 -mnps400\n");
3476 fprintf (stream
, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3477 fprintf (stream
, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3478 fprintf (stream
, " -mEM\t\t\t same as -mcpu=arcem\n");
3479 fprintf (stream
, " -mHS\t\t\t same as -mcpu=archs\n");
3481 fprintf (stream
, " -mnps400\t\t enable NPS-400 extended instructions\n");
3482 fprintf (stream
, " -mspfp\t\t enable single-precision floating point instructions\n");
3483 fprintf (stream
, " -mdpfp\t\t enable double-precision floating point instructions\n");
3484 fprintf (stream
, " -mfpuda\t\t enable double-precision assist floating "
3485 "point\n\t\t\t instructions for ARC EM\n");
3488 " -mcode-density\t enable code density option for ARC EM\n");
3490 fprintf (stream
, _("\
3491 -EB assemble code for a big-endian cpu\n"));
3492 fprintf (stream
, _("\
3493 -EL assemble code for a little-endian cpu\n"));
3494 fprintf (stream
, _("\
3495 -mrelax enable relaxation\n"));
3497 fprintf (stream
, _("The following ARC-specific assembler options are "
3498 "deprecated and are accepted\nfor compatibility only:\n"));
3500 fprintf (stream
, _(" -mEA\n"
3501 " -mbarrel-shifter\n"
3502 " -mbarrel_shifter\n"
3507 " -mld-extension-reg-mask\n"
3523 " -muser-mode-only\n"
3527 /* Find the proper relocation for the given opcode. */
3529 static extended_bfd_reloc_code_real_type
3530 find_reloc (const char *name
,
3531 const char *opcodename
,
3532 const struct arc_flags
*pflags
,
3534 extended_bfd_reloc_code_real_type reloc
)
3538 bfd_boolean found_flag
, tmp
;
3539 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3541 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3543 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3545 /* Find the entry. */
3546 if (strcmp (name
, r
->name
))
3548 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3555 unsigned * psflg
= (unsigned *)r
->flags
;
3559 for (j
= 0; j
< nflg
; j
++)
3560 if (!strcmp (pflags
[j
].name
,
3561 arc_flag_operands
[*psflg
].name
))
3582 if (reloc
!= r
->oldreloc
)
3589 if (ret
== BFD_RELOC_UNUSED
)
3590 as_bad (_("Unable to find %s relocation for instruction %s"),
3595 /* All the symbol types that are allowed to be used for
3599 may_relax_expr (expressionS tok
)
3601 /* Check if we have unrelaxable relocs. */
3626 /* Checks if flags are in line with relaxable insn. */
3629 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3630 const struct arc_flags
*pflags
,
3633 unsigned flag_class
,
3638 const struct arc_flag_operand
*flag_opand
;
3639 int i
, counttrue
= 0;
3641 /* Iterate through flags classes. */
3642 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3644 /* Iterate through flags in flag class. */
3645 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3648 flag_opand
= &arc_flag_operands
[flag
];
3649 /* Iterate through flags in ins to compare. */
3650 for (i
= 0; i
< nflgs
; ++i
)
3652 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3663 /* If counttrue == nflgs, then all flags have been found. */
3664 return (counttrue
== nflgs
? TRUE
: FALSE
);
3667 /* Checks if operands are in line with relaxable insn. */
3670 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3671 const expressionS
*tok
,
3674 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3677 while (*operand
!= EMPTY
)
3679 const expressionS
*epr
= &tok
[i
];
3681 if (i
!= 0 && i
>= ntok
)
3687 if (!(epr
->X_op
== O_multiply
3688 || epr
->X_op
== O_divide
3689 || epr
->X_op
== O_modulus
3690 || epr
->X_op
== O_add
3691 || epr
->X_op
== O_subtract
3692 || epr
->X_op
== O_symbol
))
3698 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3702 if (epr
->X_op
!= O_register
)
3707 if (epr
->X_op
!= O_register
)
3710 switch (epr
->X_add_number
)
3712 case 0: case 1: case 2: case 3:
3713 case 12: case 13: case 14: case 15:
3720 case REGISTER_NO_GP
:
3721 if ((epr
->X_op
!= O_register
)
3722 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3727 if (epr
->X_op
!= O_bracket
)
3732 /* Don't understand, bail out. */
3738 operand
= &ins
->operands
[i
];
3741 return (i
== ntok
? TRUE
: FALSE
);
3744 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3747 relax_insn_p (const struct arc_opcode
*opcode
,
3748 const expressionS
*tok
,
3750 const struct arc_flags
*pflags
,
3754 bfd_boolean rv
= FALSE
;
3756 /* Check the relaxation table. */
3757 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3759 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3761 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3762 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3763 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3764 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3767 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3768 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3769 sizeof (expressionS
) * ntok
);
3770 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3771 sizeof (struct arc_flags
) * nflg
);
3772 frag_now
->tc_frag_data
.nflg
= nflg
;
3773 frag_now
->tc_frag_data
.ntok
= ntok
;
3781 /* Turn an opcode description and a set of arguments into
3782 an instruction and a fixup. */
3785 assemble_insn (const struct arc_opcode
*opcode
,
3786 const expressionS
*tok
,
3788 const struct arc_flags
*pflags
,
3790 struct arc_insn
*insn
)
3792 const expressionS
*reloc_exp
= NULL
;
3794 const unsigned char *argidx
;
3797 unsigned char pcrel
= 0;
3798 bfd_boolean needGOTSymbol
;
3799 bfd_boolean has_delay_slot
= FALSE
;
3800 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3802 memset (insn
, 0, sizeof (*insn
));
3803 image
= opcode
->opcode
;
3805 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3806 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3809 /* Handle operands. */
3810 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3812 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3813 const expressionS
*t
= (const expressionS
*) 0;
3815 if (ARC_OPERAND_IS_FAKE (operand
))
3818 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3820 /* Duplicate operand, already inserted. */
3832 /* Regardless if we have a reloc or not mark the instruction
3833 limm if it is the case. */
3834 if (operand
->flags
& ARC_OPERAND_LIMM
)
3835 insn
->has_limm
= TRUE
;
3840 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3845 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3847 if (operand
->flags
& ARC_OPERAND_LIMM
)
3848 insn
->limm
= t
->X_add_number
;
3854 /* Ignore brackets, colons, and address types. */
3858 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3862 /* Maybe register range. */
3863 if ((t
->X_add_number
== 0)
3864 && contains_register (t
->X_add_symbol
)
3865 && contains_register (t
->X_op_symbol
))
3869 regs
= get_register (t
->X_add_symbol
);
3871 regs
|= get_register (t
->X_op_symbol
);
3872 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3878 /* This operand needs a relocation. */
3879 needGOTSymbol
= FALSE
;
3884 if (opcode
->insn_class
== JUMP
)
3885 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3886 _("Unable to use @plt relocatio for insn %s"),
3888 needGOTSymbol
= TRUE
;
3889 reloc
= find_reloc ("plt", opcode
->name
,
3891 operand
->default_reloc
);
3896 needGOTSymbol
= TRUE
;
3897 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3900 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3901 if (ARC_SHORT (opcode
->mask
) || opcode
->insn_class
== JUMP
)
3902 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3903 _("Unable to use @pcl relocation for insn %s"),
3907 reloc
= find_reloc ("sda", opcode
->name
,
3909 operand
->default_reloc
);
3913 needGOTSymbol
= TRUE
;
3918 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3921 case O_tpoff9
: /*FIXME! Check for the conditionality of
3923 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3925 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3929 /* Just consider the default relocation. */
3930 reloc
= operand
->default_reloc
;
3934 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3935 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3942 /* sanity checks. */
3943 reloc_howto_type
*reloc_howto
3944 = bfd_reloc_type_lookup (stdoutput
,
3945 (bfd_reloc_code_real_type
) reloc
);
3946 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
3947 if (reloc_howto
->rightshift
)
3948 reloc_bitsize
-= reloc_howto
->rightshift
;
3949 if (reloc_bitsize
!= operand
->bits
)
3951 as_bad (_("invalid relocation %s for field"),
3952 bfd_get_reloc_code_name (reloc
));
3957 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3958 as_fatal (_("too many fixups"));
3960 struct arc_fixup
*fixup
;
3961 fixup
= &insn
->fixups
[insn
->nfixups
++];
3963 fixup
->reloc
= reloc
;
3964 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
3965 fixup
->pcrel
= pcrel
;
3966 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
3973 for (i
= 0; i
< nflg
; i
++)
3975 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
3977 /* Check if the instruction has a delay slot. */
3978 if (!strcmp (flg_operand
->name
, "d"))
3979 has_delay_slot
= TRUE
;
3981 /* There is an exceptional case when we cannot insert a flag
3982 just as it is. The .T flag must be handled in relation with
3983 the relative address. */
3984 if (!strcmp (flg_operand
->name
, "t")
3985 || !strcmp (flg_operand
->name
, "nt"))
3987 unsigned bitYoperand
= 0;
3988 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3989 if (!strcmp (flg_operand
->name
, "t"))
3990 if (!strcmp (opcode
->name
, "bbit0")
3991 || !strcmp (opcode
->name
, "bbit1"))
3992 bitYoperand
= arc_NToperand
;
3994 bitYoperand
= arc_Toperand
;
3996 if (!strcmp (opcode
->name
, "bbit0")
3997 || !strcmp (opcode
->name
, "bbit1"))
3998 bitYoperand
= arc_Toperand
;
4000 bitYoperand
= arc_NToperand
;
4002 gas_assert (reloc_exp
!= NULL
);
4003 if (reloc_exp
->X_op
== O_constant
)
4005 /* Check if we have a constant and solved it
4007 offsetT val
= reloc_exp
->X_add_number
;
4008 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
4013 struct arc_fixup
*fixup
;
4015 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4016 as_fatal (_("too many fixups"));
4018 fixup
= &insn
->fixups
[insn
->nfixups
++];
4019 fixup
->exp
= *reloc_exp
;
4020 fixup
->reloc
= -bitYoperand
;
4021 fixup
->pcrel
= pcrel
;
4022 fixup
->islong
= FALSE
;
4026 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
4027 << flg_operand
->shift
;
4030 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
4032 /* Short instruction? */
4033 insn
->short_insn
= ARC_SHORT (opcode
->mask
) ? TRUE
: FALSE
;
4037 /* Update last insn status. */
4038 arc_last_insns
[1] = arc_last_insns
[0];
4039 arc_last_insns
[0].opcode
= opcode
;
4040 arc_last_insns
[0].has_limm
= insn
->has_limm
;
4041 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
4043 /* Check if the current instruction is legally used. */
4044 if (arc_last_insns
[1].has_delay_slot
4045 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4046 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4047 _("A jump/branch instruction in delay slot."));
4051 arc_handle_align (fragS
* fragP
)
4053 if ((fragP
)->fr_type
== rs_align_code
)
4055 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
4056 valueT count
= ((fragP
)->fr_next
->fr_address
4057 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
4059 (fragP
)->fr_var
= 2;
4061 if (count
& 1)/* Padding in the gap till the next 2-byte
4062 boundary with 0s. */
4067 /* Writing nop_s. */
4068 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
4072 /* Here we decide which fixups can be adjusted to make them relative
4073 to the beginning of the section instead of the symbol. Basically
4074 we need to make sure that the dynamic relocations are done
4075 correctly, so in some cases we force the original symbol to be
4079 tc_arc_fix_adjustable (fixS
*fixP
)
4082 /* Prevent all adjustments to global symbols. */
4083 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
4085 if (S_IS_WEAK (fixP
->fx_addsy
))
4088 /* Adjust_reloc_syms doesn't know about the GOT. */
4089 switch (fixP
->fx_r_type
)
4091 case BFD_RELOC_ARC_GOTPC32
:
4092 case BFD_RELOC_ARC_PLT32
:
4093 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
4094 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
4095 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
4096 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
4106 /* Compute the reloc type of an expression EXP. */
4109 arc_check_reloc (expressionS
*exp
,
4110 bfd_reloc_code_real_type
*r_type_p
)
4112 if (*r_type_p
== BFD_RELOC_32
4113 && exp
->X_op
== O_subtract
4114 && exp
->X_op_symbol
!= NULL
4115 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
4116 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4120 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4123 arc_cons_fix_new (fragS
*frag
,
4127 bfd_reloc_code_real_type r_type
)
4129 r_type
= BFD_RELOC_UNUSED
;
4134 r_type
= BFD_RELOC_8
;
4138 r_type
= BFD_RELOC_16
;
4142 r_type
= BFD_RELOC_24
;
4146 r_type
= BFD_RELOC_32
;
4147 arc_check_reloc (exp
, &r_type
);
4151 r_type
= BFD_RELOC_64
;
4155 as_bad (_("unsupported BFD relocation size %u"), size
);
4156 r_type
= BFD_RELOC_UNUSED
;
4159 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4162 /* The actual routine that checks the ZOL conditions. */
4165 check_zol (symbolS
*s
)
4167 switch (arc_mach_type
)
4169 case bfd_mach_arc_arcv2
:
4170 if (arc_target
& ARC_OPCODE_ARCv2EM
)
4173 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4174 || arc_last_insns
[1].has_delay_slot
)
4175 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4179 case bfd_mach_arc_arc600
:
4181 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4182 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4185 if (arc_last_insns
[0].has_limm
4186 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4187 as_bad (_("A jump instruction with long immediate detected at the \
4188 end of the ZOL label @%s"), S_GET_NAME (s
));
4191 case bfd_mach_arc_arc700
:
4192 if (arc_last_insns
[0].has_delay_slot
)
4193 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4202 /* If ZOL end check the last two instruction for illegals. */
4204 arc_frob_label (symbolS
* sym
)
4206 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4209 dwarf2_emit_label (sym
);
4212 /* Used because generic relaxation assumes a pc-rel value whilst we
4213 also relax instructions that use an absolute value resolved out of
4214 relative values (if that makes any sense). An example: 'add r1,
4215 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4216 but if they're in the same section we can subtract the section
4217 offset relocation which ends up in a resolved value. So if @.L2 is
4218 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4219 .text + 0x40 = 0x10. */
4221 arc_pcrel_adjust (fragS
*fragP
)
4223 if (!fragP
->tc_frag_data
.pcrel
)
4224 return fragP
->fr_address
+ fragP
->fr_fix
;
4229 /* Initialize the DWARF-2 unwind information for this procedure. */
4232 tc_arc_frame_initial_instructions (void)
4234 /* Stack pointer is register 28. */
4235 cfi_add_CFA_def_cfa (28, 0);
4239 tc_arc_regname_to_dw2regnum (char *regname
)
4243 sym
= hash_find (arc_reg_hash
, regname
);
4245 return S_GET_VALUE (sym
);
4250 /* Adjust the symbol table. Delete found AUX register symbols. */
4253 arc_adjust_symtab (void)
4257 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4259 /* I've created a symbol during parsing process. Now, remove
4260 the symbol as it is found to be an AUX register. */
4261 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4262 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4265 /* Now do generic ELF adjustments. */
4266 elf_adjust_symtab ();
4270 tokenize_extinsn (extInstruction_t
*einsn
)
4274 unsigned char major_opcode
;
4275 unsigned char sub_opcode
;
4276 unsigned char syntax_class
= 0;
4277 unsigned char syntax_class_modifiers
= 0;
4278 unsigned char suffix_class
= 0;
4283 /* 1st: get instruction name. */
4284 p
= input_line_pointer
;
4285 c
= get_symbol_name (&p
);
4287 insn_name
= xstrdup (p
);
4288 restore_line_pointer (c
);
4290 /* 2nd: get major opcode. */
4291 if (*input_line_pointer
!= ',')
4293 as_bad (_("expected comma after instruction name"));
4294 ignore_rest_of_line ();
4297 input_line_pointer
++;
4298 major_opcode
= get_absolute_expression ();
4300 /* 3rd: get sub-opcode. */
4303 if (*input_line_pointer
!= ',')
4305 as_bad (_("expected comma after major opcode"));
4306 ignore_rest_of_line ();
4309 input_line_pointer
++;
4310 sub_opcode
= get_absolute_expression ();
4312 /* 4th: get suffix class. */
4315 if (*input_line_pointer
!= ',')
4317 as_bad ("expected comma after sub opcode");
4318 ignore_rest_of_line ();
4321 input_line_pointer
++;
4327 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4329 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4330 suffixclass
[i
].len
))
4332 suffix_class
|= suffixclass
[i
].attr_class
;
4333 input_line_pointer
+= suffixclass
[i
].len
;
4338 if (i
== ARRAY_SIZE (suffixclass
))
4340 as_bad ("invalid suffix class");
4341 ignore_rest_of_line ();
4347 if (*input_line_pointer
== '|')
4348 input_line_pointer
++;
4353 /* 5th: get syntax class and syntax class modifiers. */
4354 if (*input_line_pointer
!= ',')
4356 as_bad ("expected comma after suffix class");
4357 ignore_rest_of_line ();
4360 input_line_pointer
++;
4366 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4368 if (!strncmp (syntaxclassmod
[i
].name
,
4370 syntaxclassmod
[i
].len
))
4372 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4373 input_line_pointer
+= syntaxclassmod
[i
].len
;
4378 if (i
== ARRAY_SIZE (syntaxclassmod
))
4380 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4382 if (!strncmp (syntaxclass
[i
].name
,
4384 syntaxclass
[i
].len
))
4386 syntax_class
|= syntaxclass
[i
].attr_class
;
4387 input_line_pointer
+= syntaxclass
[i
].len
;
4392 if (i
== ARRAY_SIZE (syntaxclass
))
4394 as_bad ("missing syntax class");
4395 ignore_rest_of_line ();
4402 if (*input_line_pointer
== '|')
4403 input_line_pointer
++;
4408 demand_empty_rest_of_line ();
4410 einsn
->name
= insn_name
;
4411 einsn
->major
= major_opcode
;
4412 einsn
->minor
= sub_opcode
;
4413 einsn
->syntax
= syntax_class
;
4414 einsn
->modsyn
= syntax_class_modifiers
;
4415 einsn
->suffix
= suffix_class
;
4416 einsn
->flags
= syntax_class
4417 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4420 /* Generate an extension section. */
4423 arc_set_ext_seg (void)
4425 if (!arcext_section
)
4427 arcext_section
= subseg_new (".arcextmap", 0);
4428 bfd_set_section_flags (stdoutput
, arcext_section
,
4429 SEC_READONLY
| SEC_HAS_CONTENTS
);
4432 subseg_set (arcext_section
, 0);
4436 /* Create an extension instruction description in the arc extension
4437 section of the output file.
4438 The structure for an instruction is like this:
4439 [0]: Length of the record.
4440 [1]: Type of the record.
4444 [4]: Syntax (flags).
4445 [5]+ Name instruction.
4447 The sequence is terminated by an empty entry. */
4450 create_extinst_section (extInstruction_t
*einsn
)
4453 segT old_sec
= now_seg
;
4454 int old_subsec
= now_subseg
;
4456 int name_len
= strlen (einsn
->name
);
4461 *p
= 5 + name_len
+ 1;
4463 *p
= EXT_INSTRUCTION
;
4470 p
= frag_more (name_len
+ 1);
4471 strcpy (p
, einsn
->name
);
4473 subseg_set (old_sec
, old_subsec
);
4476 /* Handler .extinstruction pseudo-op. */
4479 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4481 extInstruction_t einsn
;
4482 struct arc_opcode
*arc_ext_opcodes
;
4483 const char *errmsg
= NULL
;
4484 unsigned char moplow
, mophigh
;
4486 memset (&einsn
, 0, sizeof (einsn
));
4487 tokenize_extinsn (&einsn
);
4489 /* Check if the name is already used. */
4490 if (arc_find_opcode (einsn
.name
))
4491 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4493 /* Check the opcode ranges. */
4495 mophigh
= (arc_target
& (ARC_OPCODE_ARCv2EM
4496 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4498 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4499 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4501 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4502 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4503 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4505 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4507 case ARC_SYNTAX_3OP
:
4508 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4509 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4511 case ARC_SYNTAX_2OP
:
4512 case ARC_SYNTAX_1OP
:
4513 case ARC_SYNTAX_NOP
:
4514 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4515 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4521 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, arc_target
, &errmsg
);
4522 if (arc_ext_opcodes
== NULL
)
4525 as_fatal ("%s", errmsg
);
4527 as_fatal (_("Couldn't generate extension instruction opcodes"));
4530 as_warn ("%s", errmsg
);
4532 /* Insert the extension instruction. */
4533 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4535 create_extinst_section (&einsn
);
4539 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4545 int number
, imode
= 0;
4546 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4547 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4548 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4550 /* 1st: get register name. */
4552 p
= input_line_pointer
;
4553 c
= get_symbol_name (&p
);
4556 restore_line_pointer (c
);
4558 /* 2nd: get register number. */
4561 if (*input_line_pointer
!= ',')
4563 as_bad (_("expected comma after register name"));
4564 ignore_rest_of_line ();
4568 input_line_pointer
++;
4569 number
= get_absolute_expression ();
4573 as_bad (_("negative operand number %d"), number
);
4574 ignore_rest_of_line ();
4581 /* 3rd: get register mode. */
4584 if (*input_line_pointer
!= ',')
4586 as_bad (_("expected comma after register number"));
4587 ignore_rest_of_line ();
4592 input_line_pointer
++;
4593 mode
= input_line_pointer
;
4595 if (!strncmp (mode
, "r|w", 3))
4598 input_line_pointer
+= 3;
4600 else if (!strncmp (mode
, "r", 1))
4602 imode
= ARC_REGISTER_READONLY
;
4603 input_line_pointer
+= 1;
4605 else if (strncmp (mode
, "w", 1))
4607 as_bad (_("invalid mode"));
4608 ignore_rest_of_line ();
4614 imode
= ARC_REGISTER_WRITEONLY
;
4615 input_line_pointer
+= 1;
4621 /* 4th: get core register shortcut. */
4623 if (*input_line_pointer
!= ',')
4625 as_bad (_("expected comma after register mode"));
4626 ignore_rest_of_line ();
4631 input_line_pointer
++;
4633 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4635 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4636 input_line_pointer
+= 15;
4638 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4640 as_bad (_("shortcut designator invalid"));
4641 ignore_rest_of_line ();
4647 input_line_pointer
+= 12;
4650 demand_empty_rest_of_line ();
4653 ereg
->number
= number
;
4654 ereg
->imode
= imode
;
4657 /* Create an extension register/condition description in the arc
4658 extension section of the output file.
4660 The structure for an instruction is like this:
4661 [0]: Length of the record.
4662 [1]: Type of the record.
4664 For core regs and condition codes:
4668 For auxilirary registers:
4672 The sequence is terminated by an empty entry. */
4675 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4677 segT old_sec
= now_seg
;
4678 int old_subsec
= now_subseg
;
4680 int name_len
= strlen (ereg
->name
);
4687 case EXT_CORE_REGISTER
:
4689 *p
= 3 + name_len
+ 1;
4695 case EXT_AUX_REGISTER
:
4697 *p
= 6 + name_len
+ 1;
4699 *p
= EXT_AUX_REGISTER
;
4701 *p
= (ereg
->number
>> 24) & 0xff;
4703 *p
= (ereg
->number
>> 16) & 0xff;
4705 *p
= (ereg
->number
>> 8) & 0xff;
4707 *p
= (ereg
->number
) & 0xff;
4713 p
= frag_more (name_len
+ 1);
4714 strcpy (p
, ereg
->name
);
4716 subseg_set (old_sec
, old_subsec
);
4719 /* Handler .extCoreRegister pseudo-op. */
4722 arc_extcorereg (int opertype
)
4725 struct arc_aux_reg
*auxr
;
4727 struct arc_flag_operand
*ccode
;
4729 memset (&ereg
, 0, sizeof (ereg
));
4730 tokenize_extregister (&ereg
, opertype
);
4734 case EXT_CORE_REGISTER
:
4735 /* Core register. */
4736 if (ereg
.number
> 60)
4737 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4739 declare_register (ereg
.name
, ereg
.number
);
4741 case EXT_AUX_REGISTER
:
4742 /* Auxiliary register. */
4743 auxr
= XNEW (struct arc_aux_reg
);
4744 auxr
->name
= ereg
.name
;
4745 auxr
->cpu
= arc_target
;
4746 auxr
->subclass
= NONE
;
4747 auxr
->address
= ereg
.number
;
4748 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4750 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4751 auxr
->name
, retval
);
4754 /* Condition code. */
4755 if (ereg
.number
> 31)
4756 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4758 ext_condcode
.size
++;
4759 ext_condcode
.arc_ext_condcode
=
4760 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4761 ext_condcode
.size
+ 1);
4762 if (ext_condcode
.arc_ext_condcode
== NULL
)
4763 as_fatal (_("Virtual memory exhausted"));
4765 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4766 ccode
->name
= ereg
.name
;
4767 ccode
->code
= ereg
.number
;
4770 ccode
->favail
= 0; /* not used. */
4772 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4775 as_bad (_("Unknown extension"));
4778 create_extcore_section (&ereg
, opertype
);
4782 eval: (c-set-style "gnu")