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Fix spelling in comments in C source files (gas)
[binutils-gdb.git] / gas / config / tc-arc.c
1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include "as.h"
24 #include "subsegs.h"
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
29
30 #include "opcode/arc.h"
31 #include "elf/arc.h"
32 #include "../opcodes/arc-ext.h"
33
34 /* Defines section. */
35
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
39
40 #ifdef DEBUG
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
42 #else
43 # define pr_debug(fmt, args...)
44 #endif
45
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
50
51 /* Equal to MAX_PRECISION in atof-ieee.c. */
52 #define MAX_LITTLENUMS 6
53
54 #ifndef TARGET_WITH_CPU
55 #define TARGET_WITH_CPU "arc700"
56 #endif /* TARGET_WITH_CPU */
57
58 /* Enum used to enumerate the relaxable ins operands. */
59 enum rlx_operand_type
60 {
61 EMPTY = 0,
62 REGISTER,
63 REGISTER_S, /* Register for short instruction(s). */
64 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
65 REGISTER_DUP, /* Duplication of previous operand of type register. */
66 IMMEDIATE,
67 BRACKET
68 };
69
70 enum arc_rlx_types
71 {
72 ARC_RLX_NONE = 0,
73 ARC_RLX_BL_S,
74 ARC_RLX_BL,
75 ARC_RLX_B_S,
76 ARC_RLX_B,
77 ARC_RLX_ADD_U3,
78 ARC_RLX_ADD_U6,
79 ARC_RLX_ADD_LIMM,
80 ARC_RLX_LD_U7,
81 ARC_RLX_LD_S9,
82 ARC_RLX_LD_LIMM,
83 ARC_RLX_MOV_U8,
84 ARC_RLX_MOV_S12,
85 ARC_RLX_MOV_LIMM,
86 ARC_RLX_SUB_U3,
87 ARC_RLX_SUB_U6,
88 ARC_RLX_SUB_LIMM,
89 ARC_RLX_MPY_U6,
90 ARC_RLX_MPY_LIMM,
91 ARC_RLX_MOV_RU6,
92 ARC_RLX_MOV_RLIMM,
93 ARC_RLX_ADD_RRU6,
94 ARC_RLX_ADD_RRLIMM,
95 };
96
97 /* Macros section. */
98
99 #define regno(x) ((x) & 0x3F)
100 #define is_ir_num(x) (((x) & ~0x3F) == 0)
101 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
102 #define is_spfp_p(op) (((sc) == SPX))
103 #define is_dpfp_p(op) (((sc) == DPX))
104 #define is_fpuda_p(op) (((sc) == DPA))
105 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
106 || (op)->insn_class == JUMP))
107 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
108 #define is_nps400_p(op) (((sc) == NPS400))
109
110 /* Generic assembler global variables which must be defined by all
111 targets. */
112
113 /* Characters which always start a comment. */
114 const char comment_chars[] = "#;";
115
116 /* Characters which start a comment at the beginning of a line. */
117 const char line_comment_chars[] = "#";
118
119 /* Characters which may be used to separate multiple commands on a
120 single line. */
121 const char line_separator_chars[] = "`";
122
123 /* Characters which are used to indicate an exponent in a floating
124 point number. */
125 const char EXP_CHARS[] = "eE";
126
127 /* Chars that mean this number is a floating point constant
128 As in 0f12.456 or 0d1.2345e12. */
129 const char FLT_CHARS[] = "rRsSfFdD";
130
131 /* Byte order. */
132 extern int target_big_endian;
133 const char *arc_target_format = DEFAULT_TARGET_FORMAT;
134 static int byte_order = DEFAULT_BYTE_ORDER;
135
136 /* Arc extension section. */
137 static segT arcext_section;
138
139 /* By default relaxation is disabled. */
140 static int relaxation_state = 0;
141
142 extern int arc_get_mach (char *);
143
144 /* Forward declarations. */
145 static void arc_lcomm (int);
146 static void arc_option (int);
147 static void arc_extra_reloc (int);
148 static void arc_extinsn (int);
149 static void arc_extcorereg (int);
150
151 const pseudo_typeS md_pseudo_table[] =
152 {
153 /* Make sure that .word is 32 bits. */
154 { "word", cons, 4 },
155
156 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
157 { "lcomm", arc_lcomm, 0 },
158 { "lcommon", arc_lcomm, 0 },
159 { "cpu", arc_option, 0 },
160
161 { "extinstruction", arc_extinsn, 0 },
162 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
163 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
164 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
165
166 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
167 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
168
169 { NULL, NULL, 0 }
170 };
171
172 const char *md_shortopts = "";
173
174 enum options
175 {
176 OPTION_EB = OPTION_MD_BASE,
177 OPTION_EL,
178
179 OPTION_ARC600,
180 OPTION_ARC601,
181 OPTION_ARC700,
182 OPTION_ARCEM,
183 OPTION_ARCHS,
184
185 OPTION_MCPU,
186 OPTION_CD,
187 OPTION_RELAX,
188 OPTION_NPS400,
189
190 OPTION_SPFP,
191 OPTION_DPFP,
192 OPTION_FPUDA,
193
194 /* The following options are deprecated and provided here only for
195 compatibility reasons. */
196 OPTION_USER_MODE,
197 OPTION_LD_EXT_MASK,
198 OPTION_SWAP,
199 OPTION_NORM,
200 OPTION_BARREL_SHIFT,
201 OPTION_MIN_MAX,
202 OPTION_NO_MPY,
203 OPTION_EA,
204 OPTION_MUL64,
205 OPTION_SIMD,
206 OPTION_XMAC_D16,
207 OPTION_XMAC_24,
208 OPTION_DSP_PACKA,
209 OPTION_CRC,
210 OPTION_DVBF,
211 OPTION_TELEPHONY,
212 OPTION_XYMEMORY,
213 OPTION_LOCK,
214 OPTION_SWAPE,
215 OPTION_RTSC
216 };
217
218 struct option md_longopts[] =
219 {
220 { "EB", no_argument, NULL, OPTION_EB },
221 { "EL", no_argument, NULL, OPTION_EL },
222 { "mcpu", required_argument, NULL, OPTION_MCPU },
223 { "mA6", no_argument, NULL, OPTION_ARC600 },
224 { "mARC600", no_argument, NULL, OPTION_ARC600 },
225 { "mARC601", no_argument, NULL, OPTION_ARC601 },
226 { "mARC700", no_argument, NULL, OPTION_ARC700 },
227 { "mA7", no_argument, NULL, OPTION_ARC700 },
228 { "mEM", no_argument, NULL, OPTION_ARCEM },
229 { "mHS", no_argument, NULL, OPTION_ARCHS },
230 { "mcode-density", no_argument, NULL, OPTION_CD },
231 { "mrelax", no_argument, NULL, OPTION_RELAX },
232 { "mnps400", no_argument, NULL, OPTION_NPS400 },
233
234 /* Floating point options */
235 { "mspfp", no_argument, NULL, OPTION_SPFP},
236 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
237 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
238 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
239 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
240 { "mdpfp", no_argument, NULL, OPTION_DPFP},
241 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
242 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
243 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
244 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
245 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
246
247 /* The following options are deprecated and provided here only for
248 compatibility reasons. */
249 { "mav2em", no_argument, NULL, OPTION_ARCEM },
250 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
251 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
252 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
253 { "mswap", no_argument, NULL, OPTION_SWAP },
254 { "mnorm", no_argument, NULL, OPTION_NORM },
255 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
256 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
257 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
258 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
259 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
260 { "mea", no_argument, NULL, OPTION_EA },
261 { "mEA", no_argument, NULL, OPTION_EA },
262 { "mmul64", no_argument, NULL, OPTION_MUL64 },
263 { "msimd", no_argument, NULL, OPTION_SIMD},
264 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
265 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
266 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
267 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
268 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
269 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
270 { "mcrc", no_argument, NULL, OPTION_CRC},
271 { "mdvbf", no_argument, NULL, OPTION_DVBF},
272 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
273 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
274 { "mlock", no_argument, NULL, OPTION_LOCK},
275 { "mswape", no_argument, NULL, OPTION_SWAPE},
276 { "mrtsc", no_argument, NULL, OPTION_RTSC},
277
278 { NULL, no_argument, NULL, 0 }
279 };
280
281 size_t md_longopts_size = sizeof (md_longopts);
282
283 /* Local data and data types. */
284
285 /* Used since new relocation types are introduced in this
286 file (DUMMY_RELOC_LITUSE_*). */
287 typedef int extended_bfd_reloc_code_real_type;
288
289 struct arc_fixup
290 {
291 expressionS exp;
292
293 extended_bfd_reloc_code_real_type reloc;
294
295 /* index into arc_operands. */
296 unsigned int opindex;
297
298 /* PC-relative, used by internals fixups. */
299 unsigned char pcrel;
300
301 /* TRUE if this fixup is for LIMM operand. */
302 bfd_boolean islong;
303 };
304
305 struct arc_insn
306 {
307 unsigned long long int insn;
308 int nfixups;
309 struct arc_fixup fixups[MAX_INSN_FIXUPS];
310 long limm;
311 unsigned int len; /* Length of instruction in bytes. */
312 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
313 valid. */
314 bfd_boolean relax; /* Boolean value: TRUE if needs
315 relaxation. */
316 };
317
318 /* Structure to hold any last two instructions. */
319 static struct arc_last_insn
320 {
321 /* Saved instruction opcode. */
322 const struct arc_opcode *opcode;
323
324 /* Boolean value: TRUE if current insn is short. */
325 bfd_boolean has_limm;
326
327 /* Boolean value: TRUE if current insn has delay slot. */
328 bfd_boolean has_delay_slot;
329 } arc_last_insns[2];
330
331 /* Extension instruction suffix classes. */
332 typedef struct
333 {
334 const char *name;
335 int len;
336 int attr_class;
337 } attributes_t;
338
339 static const attributes_t suffixclass[] =
340 {
341 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
342 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
343 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
344 };
345
346 /* Extension instruction syntax classes. */
347 static const attributes_t syntaxclass[] =
348 {
349 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
350 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
351 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
352 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
353 };
354
355 /* Extension instruction syntax classes modifiers. */
356 static const attributes_t syntaxclassmod[] =
357 {
358 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
359 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
360 };
361
362 /* Extension register type. */
363 typedef struct
364 {
365 char *name;
366 int number;
367 int imode;
368 } extRegister_t;
369
370 /* A structure to hold the additional conditional codes. */
371 static struct
372 {
373 struct arc_flag_operand *arc_ext_condcode;
374 int size;
375 } ext_condcode = { NULL, 0 };
376
377 /* Structure to hold an entry in ARC_OPCODE_HASH. */
378 struct arc_opcode_hash_entry
379 {
380 /* The number of pointers in the OPCODE list. */
381 size_t count;
382
383 /* Points to a list of opcode pointers. */
384 const struct arc_opcode **opcode;
385 };
386
387 /* Structure used for iterating through an arc_opcode_hash_entry. */
388 struct arc_opcode_hash_entry_iterator
389 {
390 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
391 size_t index;
392
393 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
394 returned by this iterator. */
395 const struct arc_opcode *opcode;
396 };
397
398 /* Forward declaration. */
399 static void assemble_insn
400 (const struct arc_opcode *, const expressionS *, int,
401 const struct arc_flags *, int, struct arc_insn *);
402
403 /* The selection of the machine type can come from different sources. This
404 enum is used to track how the selection was made in order to perform
405 error checks. */
406 enum mach_selection_type
407 {
408 MACH_SELECTION_NONE,
409 MACH_SELECTION_FROM_DEFAULT,
410 MACH_SELECTION_FROM_CPU_DIRECTIVE,
411 MACH_SELECTION_FROM_COMMAND_LINE
412 };
413
414 /* How the current machine type was selected. */
415 static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
416
417 /* The hash table of instruction opcodes. */
418 static struct hash_control *arc_opcode_hash;
419
420 /* The hash table of register symbols. */
421 static struct hash_control *arc_reg_hash;
422
423 /* The hash table of aux register symbols. */
424 static struct hash_control *arc_aux_hash;
425
426 /* The hash table of address types. */
427 static struct hash_control *arc_addrtype_hash;
428
429 /* A table of CPU names and opcode sets. */
430 static const struct cpu_type
431 {
432 const char *name;
433 unsigned flags;
434 int mach;
435 unsigned eflags;
436 unsigned features;
437 }
438 cpu_types[] =
439 {
440 { "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600,
441 E_ARC_MACH_ARC600, 0x00},
442 { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
443 E_ARC_MACH_ARC700, 0x00},
444 { "nps400", ARC_OPCODE_ARC700 , bfd_mach_arc_arc700,
445 E_ARC_MACH_ARC700, ARC_NPS400},
446 { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
447 EF_ARC_CPU_ARCV2EM, 0x00},
448 { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
449 EF_ARC_CPU_ARCV2HS, ARC_CD},
450 { 0, 0, 0, 0, 0 }
451 };
452
453 /* Information about the cpu/variant we're assembling for. */
454 static struct cpu_type selected_cpu = { 0, 0, 0, 0, 0 };
455
456 /* A table with options. */
457 static const struct feature_type
458 {
459 unsigned feature;
460 unsigned cpus;
461 const char *name;
462 }
463 feature_list[] =
464 {
465 { ARC_CD, ARC_OPCODE_ARCV2, "code-density" },
466 { ARC_NPS400, ARC_OPCODE_ARC700, "nps400" },
467 { ARC_SPFP, ARC_OPCODE_ARCFPX, "single-precision FPX" },
468 { ARC_DPFP, ARC_OPCODE_ARCFPX, "double-precision FPX" },
469 { ARC_FPUDA, ARC_OPCODE_ARCv2EM, "double assist FP" }
470 };
471
472 /* Used by the arc_reloc_op table. Order is important. */
473 #define O_gotoff O_md1 /* @gotoff relocation. */
474 #define O_gotpc O_md2 /* @gotpc relocation. */
475 #define O_plt O_md3 /* @plt relocation. */
476 #define O_sda O_md4 /* @sda relocation. */
477 #define O_pcl O_md5 /* @pcl relocation. */
478 #define O_tlsgd O_md6 /* @tlsgd relocation. */
479 #define O_tlsie O_md7 /* @tlsie relocation. */
480 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
481 #define O_tpoff O_md9 /* @tpoff relocation. */
482 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
483 #define O_dtpoff O_md11 /* @dtpoff relocation. */
484 #define O_last O_dtpoff
485
486 /* Used to define a bracket as operand in tokens. */
487 #define O_bracket O_md32
488
489 /* Used to define a colon as an operand in tokens. */
490 #define O_colon O_md31
491
492 /* Used to define address types in nps400. */
493 #define O_addrtype O_md30
494
495 /* Dummy relocation, to be sorted out. */
496 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
497
498 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
499
500 /* A table to map the spelling of a relocation operand into an appropriate
501 bfd_reloc_code_real_type type. The table is assumed to be ordered such
502 that op-O_literal indexes into it. */
503 #define ARC_RELOC_TABLE(op) \
504 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
505 ? (abort (), 0) \
506 : (int) (op) - (int) O_gotoff) ])
507
508 #define DEF(NAME, RELOC, REQ) \
509 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
510
511 static const struct arc_reloc_op_tag
512 {
513 /* String to lookup. */
514 const char *name;
515 /* Size of the string. */
516 size_t length;
517 /* Which operator to use. */
518 operatorT op;
519 extended_bfd_reloc_code_real_type reloc;
520 /* Allows complex relocation expression like identifier@reloc +
521 const. */
522 unsigned int complex_expr : 1;
523 }
524 arc_reloc_op[] =
525 {
526 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
527 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
528 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
529 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
530 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
531 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
532 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
533 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
534 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
535 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
536 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
537 };
538
539 static const int arc_num_reloc_op
540 = sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
541
542 /* Structure for relaxable instruction that have to be swapped with a
543 smaller alternative instruction. */
544 struct arc_relaxable_ins
545 {
546 /* Mnemonic that should be checked. */
547 const char *mnemonic_r;
548
549 /* Operands that should be checked.
550 Indexes of operands from operand array. */
551 enum rlx_operand_type operands[6];
552
553 /* Flags that should be checked. */
554 unsigned flag_classes[5];
555
556 /* Mnemonic (smaller) alternative to be used later for relaxation. */
557 const char *mnemonic_alt;
558
559 /* Index of operand that generic relaxation has to check. */
560 unsigned opcheckidx;
561
562 /* Base subtype index used. */
563 enum arc_rlx_types subtype;
564 };
565
566 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
567 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
568 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
569 (SIZE), \
570 (NEXT) } \
571
572 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
573 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
574 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
575 (SIZE), \
576 (NEXT) } \
577
578
579 /* ARC relaxation table. */
580 const relax_typeS md_relax_table[] =
581 {
582 /* Fake entry. */
583 {0, 0, 0, 0},
584
585 /* BL_S s13 ->
586 BL s25. */
587 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
588 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
589
590 /* B_S s10 ->
591 B s25. */
592 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
593 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
594
595 /* ADD_S c,b, u3 ->
596 ADD<.f> a,b,u6 ->
597 ADD<.f> a,b,limm. */
598 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
599 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
600 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
601
602 /* LD_S a, [b, u7] ->
603 LD<zz><.x><.aa><.di> a, [b, s9] ->
604 LD<zz><.x><.aa><.di> a, [b, limm] */
605 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
606 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
607 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
608
609 /* MOV_S b, u8 ->
610 MOV<.f> b, s12 ->
611 MOV<.f> b, limm. */
612 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
613 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
614 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
615
616 /* SUB_S c, b, u3 ->
617 SUB<.f> a, b, u6 ->
618 SUB<.f> a, b, limm. */
619 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
620 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
621 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
622
623 /* MPY<.f> a, b, u6 ->
624 MPY<.f> a, b, limm. */
625 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
626 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
627
628 /* MOV<.f><.cc> b, u6 ->
629 MOV<.f><.cc> b, limm. */
630 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
631 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
632
633 /* ADD<.f><.cc> b, b, u6 ->
634 ADD<.f><.cc> b, b, limm. */
635 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
636 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
637 };
638
639 /* Order of this table's entries matters! */
640 const struct arc_relaxable_ins arc_relaxable_insns[] =
641 {
642 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
643 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
644 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
645 2, ARC_RLX_ADD_RRU6},
646 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
647 ARC_RLX_ADD_U3 },
648 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
649 ARC_RLX_ADD_U6 },
650 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
651 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
652 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
653 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
654 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
655 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
656 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
657 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
658 ARC_RLX_SUB_U3 },
659 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
660 ARC_RLX_SUB_U6 },
661 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
662 ARC_RLX_MPY_U6 },
663 };
664
665 const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
666
667 /* Flags to set in the elf header. */
668 static const flagword arc_initial_eflag = 0x00;
669
670 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
671 symbolS * GOT_symbol = 0;
672
673 /* Set to TRUE when we assemble instructions. */
674 static bfd_boolean assembling_insn = FALSE;
675
676 /* Functions implementation. */
677
678 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
679 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
680 are no matching entries in ARC_OPCODE_HASH. */
681
682 static const struct arc_opcode_hash_entry *
683 arc_find_opcode (const char *name)
684 {
685 const struct arc_opcode_hash_entry *entry;
686
687 entry = hash_find (arc_opcode_hash, name);
688 return entry;
689 }
690
691 /* Initialise the iterator ITER. */
692
693 static void
694 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
695 {
696 iter->index = 0;
697 iter->opcode = NULL;
698 }
699
700 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
701 calls to this function. Return NULL when all ARC_OPCODE entries have
702 been returned. */
703
704 static const struct arc_opcode *
705 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
706 struct arc_opcode_hash_entry_iterator *iter)
707 {
708 if (iter->opcode == NULL && iter->index == 0)
709 {
710 gas_assert (entry->count > 0);
711 iter->opcode = entry->opcode[iter->index];
712 }
713 else if (iter->opcode != NULL)
714 {
715 const char *old_name = iter->opcode->name;
716
717 iter->opcode++;
718 if (iter->opcode->name == NULL
719 || strcmp (old_name, iter->opcode->name) != 0)
720 {
721 iter->index++;
722 if (iter->index == entry->count)
723 iter->opcode = NULL;
724 else
725 iter->opcode = entry->opcode[iter->index];
726 }
727 }
728
729 return iter->opcode;
730 }
731
732 /* Insert an opcode into opcode hash structure. */
733
734 static void
735 arc_insert_opcode (const struct arc_opcode *opcode)
736 {
737 const char *name, *retval;
738 struct arc_opcode_hash_entry *entry;
739 name = opcode->name;
740
741 entry = hash_find (arc_opcode_hash, name);
742 if (entry == NULL)
743 {
744 entry = XNEW (struct arc_opcode_hash_entry);
745 entry->count = 0;
746 entry->opcode = NULL;
747
748 retval = hash_insert (arc_opcode_hash, name, (void *) entry);
749 if (retval)
750 as_fatal (_("internal error: can't hash opcode '%s': %s"),
751 name, retval);
752 }
753
754 entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode,
755 entry->count + 1);
756
757 if (entry->opcode == NULL)
758 as_fatal (_("Virtual memory exhausted"));
759
760 entry->opcode[entry->count] = opcode;
761 entry->count++;
762 }
763
764
765 /* Like md_number_to_chars but for middle-endian values. The 4-byte limm
766 value, is encoded as 'middle-endian' for a little-endian target. This
767 function is used for regular 4, 6, and 8 byte instructions as well. */
768
769 static void
770 md_number_to_chars_midend (char *buf, unsigned long long val, int n)
771 {
772 switch (n)
773 {
774 case 2:
775 md_number_to_chars (buf, val, n);
776 break;
777 case 6:
778 md_number_to_chars (buf, (val & 0xffff00000000) >> 32, 2);
779 md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
780 break;
781 case 4:
782 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
783 md_number_to_chars (buf + 2, (val & 0xffff), 2);
784 break;
785 case 8:
786 md_number_to_chars_midend (buf, (val & 0xffffffff00000000) >> 32, 4);
787 md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
788 break;
789 default:
790 abort ();
791 }
792 }
793
794 /* Check if a feature is allowed for a specific CPU. */
795
796 static void
797 arc_check_feature (void)
798 {
799 unsigned i;
800
801 if (!selected_cpu.features
802 || !selected_cpu.name)
803 return;
804 for (i = 0; (i < ARRAY_SIZE (feature_list)); i++)
805 {
806 if ((selected_cpu.features & feature_list[i].feature)
807 && !(selected_cpu.flags & feature_list[i].cpus))
808 {
809 as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
810 selected_cpu.name);
811 }
812 }
813 }
814
815 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
816 the relevant static global variables. Parameter SEL describes where
817 this selection originated from. */
818
819 static void
820 arc_select_cpu (const char *arg, enum mach_selection_type sel)
821 {
822 int cpu_flags = 0;
823 int i;
824
825 /* We should only set a default if we've not made a selection from some
826 other source. */
827 gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
828 || mach_selection_mode == MACH_SELECTION_NONE);
829
830 if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
831 && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
832 as_bad (_("Multiple .cpu directives found"));
833
834 /* Look for a matching entry in CPU_TYPES array. */
835 for (i = 0; cpu_types[i].name; ++i)
836 {
837 if (!strcasecmp (cpu_types[i].name, arg))
838 {
839 /* If a previous selection was made on the command line, then we
840 allow later selections on the command line to override earlier
841 ones. However, a selection from a '.cpu NAME' directive must
842 match the command line selection, or we give a warning. */
843 if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
844 {
845 gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
846 || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
847 if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
848 && selected_cpu.mach != cpu_types[i].mach)
849 {
850 as_warn (_("Command-line value overrides \".cpu\" directive"));
851 }
852 return;
853 }
854
855 /* Initialise static global data about selected machine type. */
856 selected_cpu.flags = cpu_types[i].flags;
857 selected_cpu.name = cpu_types[i].name;
858 selected_cpu.features |= cpu_types[i].features;
859 selected_cpu.mach = cpu_types[i].mach;
860 cpu_flags = cpu_types[i].eflags;
861 break;
862 }
863 }
864
865 if (!cpu_types[i].name)
866 as_fatal (_("unknown architecture: %s\n"), arg);
867
868 /* Check if set features are compatible with the chosen CPU. */
869 arc_check_feature ();
870 gas_assert (cpu_flags != 0);
871 selected_cpu.eflags = (arc_initial_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
872 mach_selection_mode = sel;
873 }
874
875 /* Here ends all the ARCompact extension instruction assembling
876 stuff. */
877
878 static void
879 arc_extra_reloc (int r_type)
880 {
881 char *sym_name, c;
882 symbolS *sym, *lab = NULL;
883
884 if (*input_line_pointer == '@')
885 input_line_pointer++;
886 c = get_symbol_name (&sym_name);
887 sym = symbol_find_or_make (sym_name);
888 restore_line_pointer (c);
889 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
890 {
891 ++input_line_pointer;
892 char *lab_name;
893 c = get_symbol_name (&lab_name);
894 lab = symbol_find_or_make (lab_name);
895 restore_line_pointer (c);
896 }
897
898 /* These relocations exist as a mechanism for the compiler to tell the
899 linker how to patch the code if the tls model is optimised. However,
900 the relocation itself does not require any space within the assembler
901 fragment, and so we pass a size of 0.
902
903 The lines that generate these relocations look like this:
904
905 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
906
907 The '.tls_gd_ld @.tdata' is processed first and generates the
908 additional relocation, while the 'bl __tls_get_addr@plt' is processed
909 second and generates the additional branch.
910
911 It is possible that the additional relocation generated by the
912 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
913 while the 'bl __tls_get_addr@plt' will be generated as the first thing
914 in the next fragment. This will be fine; both relocations will still
915 appear to be at the same address in the generated object file.
916 However, this only works as the additional relocation is generated
917 with size of 0 bytes. */
918 fixS *fixP
919 = fix_new (frag_now, /* Which frag? */
920 frag_now_fix (), /* Where in that frag? */
921 0, /* size: 1, 2, or 4 usually. */
922 sym, /* X_add_symbol. */
923 0, /* X_add_number. */
924 FALSE, /* TRUE if PC-relative relocation. */
925 r_type /* Relocation type. */);
926 fixP->fx_subsy = lab;
927 }
928
929 static symbolS *
930 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
931 symbolS *symbolP, addressT size)
932 {
933 addressT align = 0;
934 SKIP_WHITESPACE ();
935
936 if (*input_line_pointer == ',')
937 {
938 align = parse_align (1);
939
940 if (align == (addressT) -1)
941 return NULL;
942 }
943 else
944 {
945 if (size >= 8)
946 align = 3;
947 else if (size >= 4)
948 align = 2;
949 else if (size >= 2)
950 align = 1;
951 else
952 align = 0;
953 }
954
955 bss_alloc (symbolP, size, align);
956 S_CLEAR_EXTERNAL (symbolP);
957
958 return symbolP;
959 }
960
961 static void
962 arc_lcomm (int ignore)
963 {
964 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
965
966 if (symbolP)
967 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
968 }
969
970 /* Select the cpu we're assembling for. */
971
972 static void
973 arc_option (int ignore ATTRIBUTE_UNUSED)
974 {
975 char c;
976 char *cpu;
977 const char *cpu_name;
978
979 c = get_symbol_name (&cpu);
980
981 if ((!strcmp ("ARC600", cpu))
982 || (!strcmp ("ARC601", cpu))
983 || (!strcmp ("A6", cpu)))
984 cpu_name = "arc600";
985 else if ((!strcmp ("ARC700", cpu))
986 || (!strcmp ("A7", cpu)))
987 cpu_name = "arc700";
988 else if (!strcmp ("EM", cpu))
989 cpu_name = "arcem";
990 else if (!strcmp ("HS", cpu))
991 cpu_name = "archs";
992 else if (!strcmp ("NPS400", cpu))
993 cpu_name = "nps400";
994 else
995 cpu_name = NULL;
996
997 if (cpu_name != NULL)
998 arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
999 else
1000 as_fatal (_("invalid architecture `%s' in .cpu directive"), cpu);
1001
1002 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
1003 as_fatal (_("could not set architecture and machine"));
1004
1005 /* Set elf header flags. */
1006 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
1007
1008 restore_line_pointer (c);
1009 demand_empty_rest_of_line ();
1010 }
1011
1012 /* Smartly print an expression. */
1013
1014 static void
1015 debug_exp (expressionS *t)
1016 {
1017 const char *name ATTRIBUTE_UNUSED;
1018 const char *namemd ATTRIBUTE_UNUSED;
1019
1020 pr_debug ("debug_exp: ");
1021
1022 switch (t->X_op)
1023 {
1024 default: name = "unknown"; break;
1025 case O_illegal: name = "O_illegal"; break;
1026 case O_absent: name = "O_absent"; break;
1027 case O_constant: name = "O_constant"; break;
1028 case O_symbol: name = "O_symbol"; break;
1029 case O_symbol_rva: name = "O_symbol_rva"; break;
1030 case O_register: name = "O_register"; break;
1031 case O_big: name = "O_big"; break;
1032 case O_uminus: name = "O_uminus"; break;
1033 case O_bit_not: name = "O_bit_not"; break;
1034 case O_logical_not: name = "O_logical_not"; break;
1035 case O_multiply: name = "O_multiply"; break;
1036 case O_divide: name = "O_divide"; break;
1037 case O_modulus: name = "O_modulus"; break;
1038 case O_left_shift: name = "O_left_shift"; break;
1039 case O_right_shift: name = "O_right_shift"; break;
1040 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
1041 case O_bit_or_not: name = "O_bit_or_not"; break;
1042 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
1043 case O_bit_and: name = "O_bit_and"; break;
1044 case O_add: name = "O_add"; break;
1045 case O_subtract: name = "O_subtract"; break;
1046 case O_eq: name = "O_eq"; break;
1047 case O_ne: name = "O_ne"; break;
1048 case O_lt: name = "O_lt"; break;
1049 case O_le: name = "O_le"; break;
1050 case O_ge: name = "O_ge"; break;
1051 case O_gt: name = "O_gt"; break;
1052 case O_logical_and: name = "O_logical_and"; break;
1053 case O_logical_or: name = "O_logical_or"; break;
1054 case O_index: name = "O_index"; break;
1055 case O_bracket: name = "O_bracket"; break;
1056 case O_colon: name = "O_colon"; break;
1057 case O_addrtype: name = "O_addrtype"; break;
1058 }
1059
1060 switch (t->X_md)
1061 {
1062 default: namemd = "unknown"; break;
1063 case O_gotoff: namemd = "O_gotoff"; break;
1064 case O_gotpc: namemd = "O_gotpc"; break;
1065 case O_plt: namemd = "O_plt"; break;
1066 case O_sda: namemd = "O_sda"; break;
1067 case O_pcl: namemd = "O_pcl"; break;
1068 case O_tlsgd: namemd = "O_tlsgd"; break;
1069 case O_tlsie: namemd = "O_tlsie"; break;
1070 case O_tpoff9: namemd = "O_tpoff9"; break;
1071 case O_tpoff: namemd = "O_tpoff"; break;
1072 case O_dtpoff9: namemd = "O_dtpoff9"; break;
1073 case O_dtpoff: namemd = "O_dtpoff"; break;
1074 }
1075
1076 pr_debug ("%s (%s, %s, %d, %s)", name,
1077 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
1078 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
1079 (int) t->X_add_number,
1080 (t->X_md) ? namemd : "--");
1081 pr_debug ("\n");
1082 fflush (stderr);
1083 }
1084
1085 /* Parse the arguments to an opcode. */
1086
1087 static int
1088 tokenize_arguments (char *str,
1089 expressionS *tok,
1090 int ntok)
1091 {
1092 char *old_input_line_pointer;
1093 bfd_boolean saw_comma = FALSE;
1094 bfd_boolean saw_arg = FALSE;
1095 int brk_lvl = 0;
1096 int num_args = 0;
1097 int i;
1098 size_t len;
1099 const struct arc_reloc_op_tag *r;
1100 expressionS tmpE;
1101 char *reloc_name, c;
1102
1103 memset (tok, 0, sizeof (*tok) * ntok);
1104
1105 /* Save and restore input_line_pointer around this function. */
1106 old_input_line_pointer = input_line_pointer;
1107 input_line_pointer = str;
1108
1109 while (*input_line_pointer)
1110 {
1111 SKIP_WHITESPACE ();
1112 switch (*input_line_pointer)
1113 {
1114 case '\0':
1115 goto fini;
1116
1117 case ',':
1118 input_line_pointer++;
1119 if (saw_comma || !saw_arg)
1120 goto err;
1121 saw_comma = TRUE;
1122 break;
1123
1124 case '}':
1125 case ']':
1126 ++input_line_pointer;
1127 --brk_lvl;
1128 if (!saw_arg || num_args == ntok)
1129 goto err;
1130 tok->X_op = O_bracket;
1131 ++tok;
1132 ++num_args;
1133 break;
1134
1135 case '{':
1136 case '[':
1137 input_line_pointer++;
1138 if (brk_lvl || num_args == ntok)
1139 goto err;
1140 ++brk_lvl;
1141 tok->X_op = O_bracket;
1142 ++tok;
1143 ++num_args;
1144 break;
1145
1146 case ':':
1147 input_line_pointer++;
1148 if (!saw_arg || num_args == ntok)
1149 goto err;
1150 tok->X_op = O_colon;
1151 saw_arg = FALSE;
1152 ++tok;
1153 ++num_args;
1154 break;
1155
1156 case '@':
1157 /* We have labels, function names and relocations, all
1158 starting with @ symbol. Sort them out. */
1159 if ((saw_arg && !saw_comma) || num_args == ntok)
1160 goto err;
1161
1162 /* Parse @label. */
1163 tok->X_op = O_symbol;
1164 tok->X_md = O_absent;
1165 expression (tok);
1166 if (*input_line_pointer != '@')
1167 goto normalsymbol; /* This is not a relocation. */
1168
1169 relocationsym:
1170
1171 /* A relocation opernad has the following form
1172 @identifier@relocation_type. The identifier is already
1173 in tok! */
1174 if (tok->X_op != O_symbol)
1175 {
1176 as_bad (_("No valid label relocation operand"));
1177 goto err;
1178 }
1179
1180 /* Parse @relocation_type. */
1181 input_line_pointer++;
1182 c = get_symbol_name (&reloc_name);
1183 len = input_line_pointer - reloc_name;
1184 if (len == 0)
1185 {
1186 as_bad (_("No relocation operand"));
1187 goto err;
1188 }
1189
1190 /* Go through known relocation and try to find a match. */
1191 r = &arc_reloc_op[0];
1192 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
1193 if (len == r->length
1194 && memcmp (reloc_name, r->name, len) == 0)
1195 break;
1196 if (i < 0)
1197 {
1198 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
1199 goto err;
1200 }
1201
1202 *input_line_pointer = c;
1203 SKIP_WHITESPACE_AFTER_NAME ();
1204 /* Extra check for TLS: base. */
1205 if (*input_line_pointer == '@')
1206 {
1207 symbolS *base;
1208 if (tok->X_op_symbol != NULL
1209 || tok->X_op != O_symbol)
1210 {
1211 as_bad (_("Unable to parse TLS base: %s"),
1212 input_line_pointer);
1213 goto err;
1214 }
1215 input_line_pointer++;
1216 char *sym_name;
1217 c = get_symbol_name (&sym_name);
1218 base = symbol_find_or_make (sym_name);
1219 tok->X_op = O_subtract;
1220 tok->X_op_symbol = base;
1221 restore_line_pointer (c);
1222 tmpE.X_add_number = 0;
1223 }
1224 if ((*input_line_pointer != '+')
1225 && (*input_line_pointer != '-'))
1226 {
1227 tmpE.X_add_number = 0;
1228 }
1229 else
1230 {
1231 /* Parse the constant of a complex relocation expression
1232 like @identifier@reloc +/- const. */
1233 if (! r->complex_expr)
1234 {
1235 as_bad (_("@%s is not a complex relocation."), r->name);
1236 goto err;
1237 }
1238 expression (&tmpE);
1239 if (tmpE.X_op != O_constant)
1240 {
1241 as_bad (_("Bad expression: @%s + %s."),
1242 r->name, input_line_pointer);
1243 goto err;
1244 }
1245 }
1246
1247 tok->X_md = r->op;
1248 tok->X_add_number = tmpE.X_add_number;
1249
1250 debug_exp (tok);
1251
1252 saw_comma = FALSE;
1253 saw_arg = TRUE;
1254 tok++;
1255 num_args++;
1256 break;
1257
1258 case '%':
1259 /* Can be a register. */
1260 ++input_line_pointer;
1261 /* Fall through. */
1262 default:
1263
1264 if ((saw_arg && !saw_comma) || num_args == ntok)
1265 goto err;
1266
1267 tok->X_op = O_absent;
1268 tok->X_md = O_absent;
1269 expression (tok);
1270
1271 /* Legacy: There are cases when we have
1272 identifier@relocation_type, if it is the case parse the
1273 relocation type as well. */
1274 if (*input_line_pointer == '@')
1275 goto relocationsym;
1276
1277 normalsymbol:
1278 debug_exp (tok);
1279
1280 if (tok->X_op == O_illegal
1281 || tok->X_op == O_absent
1282 || num_args == ntok)
1283 goto err;
1284
1285 saw_comma = FALSE;
1286 saw_arg = TRUE;
1287 tok++;
1288 num_args++;
1289 break;
1290 }
1291 }
1292
1293 fini:
1294 if (saw_comma || brk_lvl)
1295 goto err;
1296 input_line_pointer = old_input_line_pointer;
1297
1298 return num_args;
1299
1300 err:
1301 if (brk_lvl)
1302 as_bad (_("Brackets in operand field incorrect"));
1303 else if (saw_comma)
1304 as_bad (_("extra comma"));
1305 else if (!saw_arg)
1306 as_bad (_("missing argument"));
1307 else
1308 as_bad (_("missing comma or colon"));
1309 input_line_pointer = old_input_line_pointer;
1310 return -1;
1311 }
1312
1313 /* Parse the flags to a structure. */
1314
1315 static int
1316 tokenize_flags (const char *str,
1317 struct arc_flags flags[],
1318 int nflg)
1319 {
1320 char *old_input_line_pointer;
1321 bfd_boolean saw_flg = FALSE;
1322 bfd_boolean saw_dot = FALSE;
1323 int num_flags = 0;
1324 size_t flgnamelen;
1325
1326 memset (flags, 0, sizeof (*flags) * nflg);
1327
1328 /* Save and restore input_line_pointer around this function. */
1329 old_input_line_pointer = input_line_pointer;
1330 input_line_pointer = (char *) str;
1331
1332 while (*input_line_pointer)
1333 {
1334 switch (*input_line_pointer)
1335 {
1336 case ' ':
1337 case '\0':
1338 goto fini;
1339
1340 case '.':
1341 input_line_pointer++;
1342 if (saw_dot)
1343 goto err;
1344 saw_dot = TRUE;
1345 saw_flg = FALSE;
1346 break;
1347
1348 default:
1349 if (saw_flg && !saw_dot)
1350 goto err;
1351
1352 if (num_flags >= nflg)
1353 goto err;
1354
1355 flgnamelen = strspn (input_line_pointer,
1356 "abcdefghijklmnopqrstuvwxyz0123456789");
1357 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
1358 goto err;
1359
1360 memcpy (flags->name, input_line_pointer, flgnamelen);
1361
1362 input_line_pointer += flgnamelen;
1363 flags++;
1364 saw_dot = FALSE;
1365 saw_flg = TRUE;
1366 num_flags++;
1367 break;
1368 }
1369 }
1370
1371 fini:
1372 input_line_pointer = old_input_line_pointer;
1373 return num_flags;
1374
1375 err:
1376 if (saw_dot)
1377 as_bad (_("extra dot"));
1378 else if (!saw_flg)
1379 as_bad (_("unrecognized flag"));
1380 else
1381 as_bad (_("failed to parse flags"));
1382 input_line_pointer = old_input_line_pointer;
1383 return -1;
1384 }
1385
1386 /* Apply the fixups in order. */
1387
1388 static void
1389 apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
1390 {
1391 int i;
1392
1393 for (i = 0; i < insn->nfixups; i++)
1394 {
1395 struct arc_fixup *fixup = &insn->fixups[i];
1396 int size, pcrel, offset = 0;
1397
1398 /* FIXME! the reloc size is wrong in the BFD file.
1399 When it is fixed please delete me. */
1400 size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
1401
1402 if (fixup->islong)
1403 offset = insn->len;
1404
1405 /* Some fixups are only used internally, thus no howto. */
1406 if ((int) fixup->reloc == 0)
1407 as_fatal (_("Unhandled reloc type"));
1408
1409 if ((int) fixup->reloc < 0)
1410 {
1411 /* FIXME! the reloc size is wrong in the BFD file.
1412 When it is fixed please enable me.
1413 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
1414 pcrel = fixup->pcrel;
1415 }
1416 else
1417 {
1418 reloc_howto_type *reloc_howto =
1419 bfd_reloc_type_lookup (stdoutput,
1420 (bfd_reloc_code_real_type) fixup->reloc);
1421 gas_assert (reloc_howto);
1422
1423 /* FIXME! the reloc size is wrong in the BFD file.
1424 When it is fixed please enable me.
1425 size = bfd_get_reloc_size (reloc_howto); */
1426 pcrel = reloc_howto->pc_relative;
1427 }
1428
1429 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1430 offset %d + %d\n",
1431 fragP->fr_file, fragP->fr_line,
1432 (fixup->reloc < 0) ? "Internal" :
1433 bfd_get_reloc_code_name (fixup->reloc),
1434 pcrel ? "Y" : "N",
1435 size, fix, offset);
1436 fix_new_exp (fragP, fix + offset,
1437 size, &fixup->exp, pcrel, fixup->reloc);
1438
1439 /* Check for ZOLs, and update symbol info if any. */
1440 if (LP_INSN (insn->insn))
1441 {
1442 gas_assert (fixup->exp.X_add_symbol);
1443 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
1444 }
1445 }
1446 }
1447
1448 /* Actually output an instruction with its fixup. */
1449
1450 static void
1451 emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
1452 {
1453 char *f = where;
1454 size_t total_len;
1455
1456 pr_debug ("Emit insn : 0x%llx\n", insn->insn);
1457 pr_debug ("\tLength : 0x%d\n", insn->len);
1458 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
1459
1460 /* Write out the instruction. */
1461 total_len = insn->len + (insn->has_limm ? 4 : 0);
1462 if (!relax)
1463 f = frag_more (total_len);
1464
1465 md_number_to_chars_midend(f, insn->insn, insn->len);
1466
1467 if (insn->has_limm)
1468 md_number_to_chars_midend (f + insn->len, insn->limm, 4);
1469 dwarf2_emit_insn (total_len);
1470
1471 if (!relax)
1472 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1473 }
1474
1475 static void
1476 emit_insn1 (struct arc_insn *insn)
1477 {
1478 /* How frag_var's args are currently configured:
1479 - rs_machine_dependent, to dictate it's a relaxation frag.
1480 - FRAG_MAX_GROWTH, maximum size of instruction
1481 - 0, variable size that might grow...unused by generic relaxation.
1482 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1483 - s, opand expression.
1484 - 0, offset but it's unused.
1485 - 0, opcode but it's unused. */
1486 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1487 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1488
1489 if (frag_room () < FRAG_MAX_GROWTH)
1490 {
1491 /* Handle differently when frag literal memory is exhausted.
1492 This is used because when there's not enough memory left in
1493 the current frag, a new frag is created and the information
1494 we put into frag_now->tc_frag_data is disregarded. */
1495
1496 struct arc_relax_type relax_info_copy;
1497 relax_substateT subtype = frag_now->fr_subtype;
1498
1499 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1500 sizeof (struct arc_relax_type));
1501
1502 frag_wane (frag_now);
1503 frag_grow (FRAG_MAX_GROWTH);
1504
1505 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1506 sizeof (struct arc_relax_type));
1507
1508 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1509 subtype, s, 0, 0);
1510 }
1511 else
1512 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1513 frag_now->fr_subtype, s, 0, 0);
1514 }
1515
1516 static void
1517 emit_insn (struct arc_insn *insn)
1518 {
1519 if (insn->relax)
1520 emit_insn1 (insn);
1521 else
1522 emit_insn0 (insn, NULL, FALSE);
1523 }
1524
1525 /* Check whether a symbol involves a register. */
1526
1527 static bfd_boolean
1528 contains_register (symbolS *sym)
1529 {
1530 if (sym)
1531 {
1532 expressionS *ex = symbol_get_value_expression (sym);
1533
1534 return ((O_register == ex->X_op)
1535 && !contains_register (ex->X_add_symbol)
1536 && !contains_register (ex->X_op_symbol));
1537 }
1538
1539 return FALSE;
1540 }
1541
1542 /* Returns the register number within a symbol. */
1543
1544 static int
1545 get_register (symbolS *sym)
1546 {
1547 if (!contains_register (sym))
1548 return -1;
1549
1550 expressionS *ex = symbol_get_value_expression (sym);
1551 return regno (ex->X_add_number);
1552 }
1553
1554 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1555 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1556
1557 static bfd_boolean
1558 generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1559 {
1560 if (!reloc)
1561 return FALSE;
1562
1563 switch (reloc)
1564 {
1565 case BFD_RELOC_ARC_SDA_LDST:
1566 case BFD_RELOC_ARC_SDA_LDST1:
1567 case BFD_RELOC_ARC_SDA_LDST2:
1568 case BFD_RELOC_ARC_SDA16_LD:
1569 case BFD_RELOC_ARC_SDA16_LD1:
1570 case BFD_RELOC_ARC_SDA16_LD2:
1571 case BFD_RELOC_ARC_SDA16_ST2:
1572 case BFD_RELOC_ARC_SDA32_ME:
1573 return FALSE;
1574 default:
1575 return TRUE;
1576 }
1577 }
1578
1579 /* Allocates a tok entry. */
1580
1581 static int
1582 allocate_tok (expressionS *tok, int ntok, int cidx)
1583 {
1584 if (ntok > MAX_INSN_ARGS - 2)
1585 return 0; /* No space left. */
1586
1587 if (cidx > ntok)
1588 return 0; /* Incorect args. */
1589
1590 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
1591
1592 if (cidx == ntok)
1593 return 1; /* Success. */
1594 return allocate_tok (tok, ntok - 1, cidx);
1595 }
1596
1597 /* Check if an particular ARC feature is enabled. */
1598
1599 static bfd_boolean
1600 check_cpu_feature (insn_subclass_t sc)
1601 {
1602 if (is_code_density_p (sc) && !(selected_cpu.features & ARC_CD))
1603 return FALSE;
1604
1605 if (is_spfp_p (sc) && !(selected_cpu.features & ARC_SPFP))
1606 return FALSE;
1607
1608 if (is_dpfp_p (sc) && !(selected_cpu.features & ARC_DPFP))
1609 return FALSE;
1610
1611 if (is_fpuda_p (sc) && !(selected_cpu.features & ARC_FPUDA))
1612 return FALSE;
1613
1614 if (is_nps400_p (sc) && !(selected_cpu.features & ARC_NPS400))
1615 return FALSE;
1616
1617 return TRUE;
1618 }
1619
1620 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1621 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1622 array and returns TRUE if the flag operands all match, otherwise,
1623 returns FALSE, in which case the FIRST_PFLAG array may have been
1624 modified. */
1625
1626 static bfd_boolean
1627 parse_opcode_flags (const struct arc_opcode *opcode,
1628 int nflgs,
1629 struct arc_flags *first_pflag)
1630 {
1631 int lnflg, i;
1632 const unsigned char *flgidx;
1633
1634 lnflg = nflgs;
1635 for (i = 0; i < nflgs; i++)
1636 first_pflag[i].flgp = NULL;
1637
1638 /* Check the flags. Iterate over the valid flag classes. */
1639 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1640 {
1641 /* Get a valid flag class. */
1642 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1643 const unsigned *flgopridx;
1644 int cl_matches = 0;
1645 struct arc_flags *pflag = NULL;
1646
1647 /* Check for extension conditional codes. */
1648 if (ext_condcode.arc_ext_condcode
1649 && cl_flags->flag_class & F_CLASS_EXTEND)
1650 {
1651 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1652 while (pf->name)
1653 {
1654 pflag = first_pflag;
1655 for (i = 0; i < nflgs; i++, pflag++)
1656 {
1657 if (!strcmp (pf->name, pflag->name))
1658 {
1659 if (pflag->flgp != NULL)
1660 return FALSE;
1661 /* Found it. */
1662 cl_matches++;
1663 pflag->flgp = pf;
1664 lnflg--;
1665 break;
1666 }
1667 }
1668 pf++;
1669 }
1670 }
1671
1672 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1673 {
1674 const struct arc_flag_operand *flg_operand;
1675
1676 pflag = first_pflag;
1677 flg_operand = &arc_flag_operands[*flgopridx];
1678 for (i = 0; i < nflgs; i++, pflag++)
1679 {
1680 /* Match against the parsed flags. */
1681 if (!strcmp (flg_operand->name, pflag->name))
1682 {
1683 if (pflag->flgp != NULL)
1684 return FALSE;
1685 cl_matches++;
1686 pflag->flgp = flg_operand;
1687 lnflg--;
1688 break; /* goto next flag class and parsed flag. */
1689 }
1690 }
1691 }
1692
1693 if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
1694 return FALSE;
1695 if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
1696 return FALSE;
1697 }
1698
1699 /* Did I check all the parsed flags? */
1700 return lnflg ? FALSE : TRUE;
1701 }
1702
1703
1704 /* Search forward through all variants of an opcode looking for a
1705 syntax match. */
1706
1707 static const struct arc_opcode *
1708 find_opcode_match (const struct arc_opcode_hash_entry *entry,
1709 expressionS *tok,
1710 int *pntok,
1711 struct arc_flags *first_pflag,
1712 int nflgs,
1713 int *pcpumatch)
1714 {
1715 const struct arc_opcode *opcode;
1716 struct arc_opcode_hash_entry_iterator iter;
1717 int ntok = *pntok;
1718 int got_cpu_match = 0;
1719 expressionS bktok[MAX_INSN_ARGS];
1720 int bkntok;
1721 expressionS emptyE;
1722
1723 arc_opcode_hash_entry_iterator_init (&iter);
1724 memset (&emptyE, 0, sizeof (emptyE));
1725 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1726 bkntok = ntok;
1727
1728 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1729 opcode != NULL;
1730 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
1731 {
1732 const unsigned char *opidx;
1733 int tokidx = 0;
1734 const expressionS *t = &emptyE;
1735
1736 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
1737 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
1738
1739 /* Don't match opcodes that don't exist on this
1740 architecture. */
1741 if (!(opcode->cpu & selected_cpu.flags))
1742 goto match_failed;
1743
1744 if (!check_cpu_feature (opcode->subclass))
1745 goto match_failed;
1746
1747 got_cpu_match = 1;
1748 pr_debug ("cpu ");
1749
1750 /* Check the operands. */
1751 for (opidx = opcode->operands; *opidx; ++opidx)
1752 {
1753 const struct arc_operand *operand = &arc_operands[*opidx];
1754
1755 /* Only take input from real operands. */
1756 if (ARC_OPERAND_IS_FAKE (operand))
1757 continue;
1758
1759 /* When we expect input, make sure we have it. */
1760 if (tokidx >= ntok)
1761 goto match_failed;
1762
1763 /* Match operand type with expression type. */
1764 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1765 {
1766 case ARC_OPERAND_ADDRTYPE:
1767 {
1768 const char *errmsg = NULL;
1769
1770 /* Check to be an address type. */
1771 if (tok[tokidx].X_op != O_addrtype)
1772 goto match_failed;
1773
1774 /* All address type operands need to have an insert
1775 method in order to check that we have the correct
1776 address type. */
1777 gas_assert (operand->insert != NULL);
1778 (*operand->insert) (0, tok[tokidx].X_add_number,
1779 &errmsg);
1780 if (errmsg != NULL)
1781 goto match_failed;
1782 }
1783 break;
1784
1785 case ARC_OPERAND_IR:
1786 /* Check to be a register. */
1787 if ((tok[tokidx].X_op != O_register
1788 || !is_ir_num (tok[tokidx].X_add_number))
1789 && !(operand->flags & ARC_OPERAND_IGNORE))
1790 goto match_failed;
1791
1792 /* If expect duplicate, make sure it is duplicate. */
1793 if (operand->flags & ARC_OPERAND_DUPLICATE)
1794 {
1795 /* Check for duplicate. */
1796 if (t->X_op != O_register
1797 || !is_ir_num (t->X_add_number)
1798 || (regno (t->X_add_number) !=
1799 regno (tok[tokidx].X_add_number)))
1800 goto match_failed;
1801 }
1802
1803 /* Special handling? */
1804 if (operand->insert)
1805 {
1806 const char *errmsg = NULL;
1807 (*operand->insert)(0,
1808 regno (tok[tokidx].X_add_number),
1809 &errmsg);
1810 if (errmsg)
1811 {
1812 if (operand->flags & ARC_OPERAND_IGNORE)
1813 {
1814 /* Missing argument, create one. */
1815 if (!allocate_tok (tok, ntok - 1, tokidx))
1816 goto match_failed;
1817
1818 tok[tokidx].X_op = O_absent;
1819 ++ntok;
1820 }
1821 else
1822 goto match_failed;
1823 }
1824 }
1825
1826 t = &tok[tokidx];
1827 break;
1828
1829 case ARC_OPERAND_BRAKET:
1830 /* Check if bracket is also in opcode table as
1831 operand. */
1832 if (tok[tokidx].X_op != O_bracket)
1833 goto match_failed;
1834 break;
1835
1836 case ARC_OPERAND_COLON:
1837 /* Check if colon is also in opcode table as operand. */
1838 if (tok[tokidx].X_op != O_colon)
1839 goto match_failed;
1840 break;
1841
1842 case ARC_OPERAND_LIMM:
1843 case ARC_OPERAND_SIGNED:
1844 case ARC_OPERAND_UNSIGNED:
1845 switch (tok[tokidx].X_op)
1846 {
1847 case O_illegal:
1848 case O_absent:
1849 case O_register:
1850 goto match_failed;
1851
1852 case O_bracket:
1853 /* Got an (too) early bracket, check if it is an
1854 ignored operand. N.B. This procedure works only
1855 when bracket is the last operand! */
1856 if (!(operand->flags & ARC_OPERAND_IGNORE))
1857 goto match_failed;
1858 /* Insert the missing operand. */
1859 if (!allocate_tok (tok, ntok - 1, tokidx))
1860 goto match_failed;
1861
1862 tok[tokidx].X_op = O_absent;
1863 ++ntok;
1864 break;
1865
1866 case O_symbol:
1867 {
1868 const char *p;
1869 const struct arc_aux_reg *auxr;
1870
1871 if (opcode->insn_class != AUXREG)
1872 goto de_fault;
1873 p = S_GET_NAME (tok[tokidx].X_add_symbol);
1874
1875 auxr = hash_find (arc_aux_hash, p);
1876 if (auxr)
1877 {
1878 /* We modify the token array here, safe in the
1879 knowledge, that if this was the wrong
1880 choice then the original contents will be
1881 restored from BKTOK. */
1882 tok[tokidx].X_op = O_constant;
1883 tok[tokidx].X_add_number = auxr->address;
1884 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1885 }
1886
1887 if (tok[tokidx].X_op != O_constant)
1888 goto de_fault;
1889 }
1890 /* Fall through. */
1891 case O_constant:
1892 /* Check the range. */
1893 if (operand->bits != 32
1894 && !(operand->flags & ARC_OPERAND_NCHK))
1895 {
1896 offsetT min, max, val;
1897 val = tok[tokidx].X_add_number;
1898
1899 if (operand->flags & ARC_OPERAND_SIGNED)
1900 {
1901 max = (1 << (operand->bits - 1)) - 1;
1902 min = -(1 << (operand->bits - 1));
1903 }
1904 else
1905 {
1906 max = (1 << operand->bits) - 1;
1907 min = 0;
1908 }
1909
1910 if (val < min || val > max)
1911 goto match_failed;
1912
1913 /* Check alignmets. */
1914 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1915 && (val & 0x03))
1916 goto match_failed;
1917
1918 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1919 && (val & 0x01))
1920 goto match_failed;
1921 }
1922 else if (operand->flags & ARC_OPERAND_NCHK)
1923 {
1924 if (operand->insert)
1925 {
1926 const char *errmsg = NULL;
1927 (*operand->insert)(0,
1928 tok[tokidx].X_add_number,
1929 &errmsg);
1930 if (errmsg)
1931 goto match_failed;
1932 }
1933 else if (!(operand->flags & ARC_OPERAND_IGNORE))
1934 goto match_failed;
1935 }
1936 break;
1937
1938 case O_subtract:
1939 /* Check if it is register range. */
1940 if ((tok[tokidx].X_add_number == 0)
1941 && contains_register (tok[tokidx].X_add_symbol)
1942 && contains_register (tok[tokidx].X_op_symbol))
1943 {
1944 int regs;
1945
1946 regs = get_register (tok[tokidx].X_add_symbol);
1947 regs <<= 16;
1948 regs |= get_register (tok[tokidx].X_op_symbol);
1949 if (operand->insert)
1950 {
1951 const char *errmsg = NULL;
1952 (*operand->insert)(0,
1953 regs,
1954 &errmsg);
1955 if (errmsg)
1956 goto match_failed;
1957 }
1958 else
1959 goto match_failed;
1960 break;
1961 }
1962 /* Fall through. */
1963 default:
1964 de_fault:
1965 if (operand->default_reloc == 0)
1966 goto match_failed; /* The operand needs relocation. */
1967
1968 /* Relocs requiring long immediate. FIXME! make it
1969 generic and move it to a function. */
1970 switch (tok[tokidx].X_md)
1971 {
1972 case O_gotoff:
1973 case O_gotpc:
1974 case O_pcl:
1975 case O_tpoff:
1976 case O_dtpoff:
1977 case O_tlsgd:
1978 case O_tlsie:
1979 if (!(operand->flags & ARC_OPERAND_LIMM))
1980 goto match_failed;
1981 /* Fall through. */
1982 case O_absent:
1983 if (!generic_reloc_p (operand->default_reloc))
1984 goto match_failed;
1985 break;
1986 default:
1987 break;
1988 }
1989 break;
1990 }
1991 /* If expect duplicate, make sure it is duplicate. */
1992 if (operand->flags & ARC_OPERAND_DUPLICATE)
1993 {
1994 if (t->X_op == O_illegal
1995 || t->X_op == O_absent
1996 || t->X_op == O_register
1997 || (t->X_add_number != tok[tokidx].X_add_number))
1998 goto match_failed;
1999 }
2000 t = &tok[tokidx];
2001 break;
2002
2003 default:
2004 /* Everything else should have been fake. */
2005 abort ();
2006 }
2007
2008 ++tokidx;
2009 }
2010 pr_debug ("opr ");
2011
2012 /* Setup ready for flag parsing. */
2013 if (!parse_opcode_flags (opcode, nflgs, first_pflag))
2014 goto match_failed;
2015
2016 pr_debug ("flg");
2017 /* Possible match -- did we use all of our input? */
2018 if (tokidx == ntok)
2019 {
2020 *pntok = ntok;
2021 pr_debug ("\n");
2022 return opcode;
2023 }
2024
2025 match_failed:;
2026 pr_debug ("\n");
2027 /* Restore the original parameters. */
2028 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
2029 ntok = bkntok;
2030 }
2031
2032 if (*pcpumatch)
2033 *pcpumatch = got_cpu_match;
2034
2035 return NULL;
2036 }
2037
2038 /* Swap operand tokens. */
2039
2040 static void
2041 swap_operand (expressionS *operand_array,
2042 unsigned source,
2043 unsigned destination)
2044 {
2045 expressionS cpy_operand;
2046 expressionS *src_operand;
2047 expressionS *dst_operand;
2048 size_t size;
2049
2050 if (source == destination)
2051 return;
2052
2053 src_operand = &operand_array[source];
2054 dst_operand = &operand_array[destination];
2055 size = sizeof (expressionS);
2056
2057 /* Make copy of operand to swap with and swap. */
2058 memcpy (&cpy_operand, dst_operand, size);
2059 memcpy (dst_operand, src_operand, size);
2060 memcpy (src_operand, &cpy_operand, size);
2061 }
2062
2063 /* Check if *op matches *tok type.
2064 Returns FALSE if they don't match, TRUE if they match. */
2065
2066 static bfd_boolean
2067 pseudo_operand_match (const expressionS *tok,
2068 const struct arc_operand_operation *op)
2069 {
2070 offsetT min, max, val;
2071 bfd_boolean ret;
2072 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
2073
2074 ret = FALSE;
2075 switch (tok->X_op)
2076 {
2077 case O_constant:
2078 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
2079 ret = 1;
2080 else if (!(operand_real->flags & ARC_OPERAND_IR))
2081 {
2082 val = tok->X_add_number + op->count;
2083 if (operand_real->flags & ARC_OPERAND_SIGNED)
2084 {
2085 max = (1 << (operand_real->bits - 1)) - 1;
2086 min = -(1 << (operand_real->bits - 1));
2087 }
2088 else
2089 {
2090 max = (1 << operand_real->bits) - 1;
2091 min = 0;
2092 }
2093 if (min <= val && val <= max)
2094 ret = TRUE;
2095 }
2096 break;
2097
2098 case O_symbol:
2099 /* Handle all symbols as long immediates or signed 9. */
2100 if (operand_real->flags & ARC_OPERAND_LIMM
2101 || ((operand_real->flags & ARC_OPERAND_SIGNED)
2102 && operand_real->bits == 9))
2103 ret = TRUE;
2104 break;
2105
2106 case O_register:
2107 if (operand_real->flags & ARC_OPERAND_IR)
2108 ret = TRUE;
2109 break;
2110
2111 case O_bracket:
2112 if (operand_real->flags & ARC_OPERAND_BRAKET)
2113 ret = TRUE;
2114 break;
2115
2116 default:
2117 /* Unknown. */
2118 break;
2119 }
2120 return ret;
2121 }
2122
2123 /* Find pseudo instruction in array. */
2124
2125 static const struct arc_pseudo_insn *
2126 find_pseudo_insn (const char *opname,
2127 int ntok,
2128 const expressionS *tok)
2129 {
2130 const struct arc_pseudo_insn *pseudo_insn = NULL;
2131 const struct arc_operand_operation *op;
2132 unsigned int i;
2133 int j;
2134
2135 for (i = 0; i < arc_num_pseudo_insn; ++i)
2136 {
2137 pseudo_insn = &arc_pseudo_insns[i];
2138 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2139 {
2140 op = pseudo_insn->operand;
2141 for (j = 0; j < ntok; ++j)
2142 if (!pseudo_operand_match (&tok[j], &op[j]))
2143 break;
2144
2145 /* Found the right instruction. */
2146 if (j == ntok)
2147 return pseudo_insn;
2148 }
2149 }
2150 return NULL;
2151 }
2152
2153 /* Assumes the expressionS *tok is of sufficient size. */
2154
2155 static const struct arc_opcode_hash_entry *
2156 find_special_case_pseudo (const char *opname,
2157 int *ntok,
2158 expressionS *tok,
2159 int *nflgs,
2160 struct arc_flags *pflags)
2161 {
2162 const struct arc_pseudo_insn *pseudo_insn = NULL;
2163 const struct arc_operand_operation *operand_pseudo;
2164 const struct arc_operand *operand_real;
2165 unsigned i;
2166 char construct_operand[MAX_CONSTR_STR];
2167
2168 /* Find whether opname is in pseudo instruction array. */
2169 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2170
2171 if (pseudo_insn == NULL)
2172 return NULL;
2173
2174 /* Handle flag, Limited to one flag at the moment. */
2175 if (pseudo_insn->flag_r != NULL)
2176 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2177 MAX_INSN_FLGS - *nflgs);
2178
2179 /* Handle operand operations. */
2180 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2181 {
2182 operand_pseudo = &pseudo_insn->operand[i];
2183 operand_real = &arc_operands[operand_pseudo->operand_idx];
2184
2185 if (operand_real->flags & ARC_OPERAND_BRAKET
2186 && !operand_pseudo->needs_insert)
2187 continue;
2188
2189 /* Has to be inserted (i.e. this token does not exist yet). */
2190 if (operand_pseudo->needs_insert)
2191 {
2192 if (operand_real->flags & ARC_OPERAND_BRAKET)
2193 {
2194 tok[i].X_op = O_bracket;
2195 ++(*ntok);
2196 continue;
2197 }
2198
2199 /* Check if operand is a register or constant and handle it
2200 by type. */
2201 if (operand_real->flags & ARC_OPERAND_IR)
2202 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2203 operand_pseudo->count);
2204 else
2205 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2206 operand_pseudo->count);
2207
2208 tokenize_arguments (construct_operand, &tok[i], 1);
2209 ++(*ntok);
2210 }
2211
2212 else if (operand_pseudo->count)
2213 {
2214 /* Operand number has to be adjusted accordingly (by operand
2215 type). */
2216 switch (tok[i].X_op)
2217 {
2218 case O_constant:
2219 tok[i].X_add_number += operand_pseudo->count;
2220 break;
2221
2222 case O_symbol:
2223 break;
2224
2225 default:
2226 /* Ignored. */
2227 break;
2228 }
2229 }
2230 }
2231
2232 /* Swap operands if necessary. Only supports one swap at the
2233 moment. */
2234 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2235 {
2236 operand_pseudo = &pseudo_insn->operand[i];
2237
2238 if (operand_pseudo->swap_operand_idx == i)
2239 continue;
2240
2241 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2242
2243 /* Prevent a swap back later by breaking out. */
2244 break;
2245 }
2246
2247 return arc_find_opcode (pseudo_insn->mnemonic_r);
2248 }
2249
2250 static const struct arc_opcode_hash_entry *
2251 find_special_case_flag (const char *opname,
2252 int *nflgs,
2253 struct arc_flags *pflags)
2254 {
2255 unsigned int i;
2256 const char *flagnm;
2257 unsigned flag_idx, flag_arr_idx;
2258 size_t flaglen, oplen;
2259 const struct arc_flag_special *arc_flag_special_opcode;
2260 const struct arc_opcode_hash_entry *entry;
2261
2262 /* Search for special case instruction. */
2263 for (i = 0; i < arc_num_flag_special; i++)
2264 {
2265 arc_flag_special_opcode = &arc_flag_special_cases[i];
2266 oplen = strlen (arc_flag_special_opcode->name);
2267
2268 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2269 continue;
2270
2271 /* Found a potential special case instruction, now test for
2272 flags. */
2273 for (flag_arr_idx = 0;; ++flag_arr_idx)
2274 {
2275 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2276 if (flag_idx == 0)
2277 break; /* End of array, nothing found. */
2278
2279 flagnm = arc_flag_operands[flag_idx].name;
2280 flaglen = strlen (flagnm);
2281 if (strcmp (opname + oplen, flagnm) == 0)
2282 {
2283 entry = arc_find_opcode (arc_flag_special_opcode->name);
2284
2285 if (*nflgs + 1 > MAX_INSN_FLGS)
2286 break;
2287 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2288 pflags[*nflgs].name[flaglen] = '\0';
2289 (*nflgs)++;
2290 return entry;
2291 }
2292 }
2293 }
2294 return NULL;
2295 }
2296
2297 /* Used to find special case opcode. */
2298
2299 static const struct arc_opcode_hash_entry *
2300 find_special_case (const char *opname,
2301 int *nflgs,
2302 struct arc_flags *pflags,
2303 expressionS *tok,
2304 int *ntok)
2305 {
2306 const struct arc_opcode_hash_entry *entry;
2307
2308 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
2309
2310 if (entry == NULL)
2311 entry = find_special_case_flag (opname, nflgs, pflags);
2312
2313 return entry;
2314 }
2315
2316 /* Given an opcode name, pre-tockenized set of argumenst and the
2317 opcode flags, take it all the way through emission. */
2318
2319 static void
2320 assemble_tokens (const char *opname,
2321 expressionS *tok,
2322 int ntok,
2323 struct arc_flags *pflags,
2324 int nflgs)
2325 {
2326 bfd_boolean found_something = FALSE;
2327 const struct arc_opcode_hash_entry *entry;
2328 int cpumatch = 1;
2329
2330 /* Search opcodes. */
2331 entry = arc_find_opcode (opname);
2332
2333 /* Couldn't find opcode conventional way, try special cases. */
2334 if (entry == NULL)
2335 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
2336
2337 if (entry != NULL)
2338 {
2339 const struct arc_opcode *opcode;
2340
2341 pr_debug ("%s:%d: assemble_tokens: %s\n",
2342 frag_now->fr_file, frag_now->fr_line, opname);
2343 found_something = TRUE;
2344 opcode = find_opcode_match (entry, tok, &ntok, pflags,
2345 nflgs, &cpumatch);
2346 if (opcode != NULL)
2347 {
2348 struct arc_insn insn;
2349
2350 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2351 emit_insn (&insn);
2352 return;
2353 }
2354 }
2355
2356 if (found_something)
2357 {
2358 if (cpumatch)
2359 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
2360 else
2361 as_bad (_("opcode '%s' not supported for target %s"), opname,
2362 selected_cpu.name);
2363 }
2364 else
2365 as_bad (_("unknown opcode '%s'"), opname);
2366 }
2367
2368 /* The public interface to the instruction assembler. */
2369
2370 void
2371 md_assemble (char *str)
2372 {
2373 char *opname;
2374 expressionS tok[MAX_INSN_ARGS];
2375 int ntok, nflg;
2376 size_t opnamelen;
2377 struct arc_flags flags[MAX_INSN_FLGS];
2378
2379 /* Split off the opcode. */
2380 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
2381 opname = xmemdup0 (str, opnamelen);
2382
2383 /* Signalize we are assmbling the instructions. */
2384 assembling_insn = TRUE;
2385
2386 /* Tokenize the flags. */
2387 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2388 {
2389 as_bad (_("syntax error"));
2390 return;
2391 }
2392
2393 /* Scan up to the end of the mnemonic which must end in space or end
2394 of string. */
2395 str += opnamelen;
2396 for (; *str != '\0'; str++)
2397 if (*str == ' ')
2398 break;
2399
2400 /* Tokenize the rest of the line. */
2401 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
2402 {
2403 as_bad (_("syntax error"));
2404 return;
2405 }
2406
2407 /* Finish it off. */
2408 assemble_tokens (opname, tok, ntok, flags, nflg);
2409 assembling_insn = FALSE;
2410 }
2411
2412 /* Callback to insert a register into the hash table. */
2413
2414 static void
2415 declare_register (const char *name, int number)
2416 {
2417 const char *err;
2418 symbolS *regS = symbol_create (name, reg_section,
2419 number, &zero_address_frag);
2420
2421 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
2422 if (err)
2423 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2424 name, err);
2425 }
2426
2427 /* Construct symbols for each of the general registers. */
2428
2429 static void
2430 declare_register_set (void)
2431 {
2432 int i;
2433 for (i = 0; i < 64; ++i)
2434 {
2435 char name[7];
2436
2437 sprintf (name, "r%d", i);
2438 declare_register (name, i);
2439 if ((i & 0x01) == 0)
2440 {
2441 sprintf (name, "r%dr%d", i, i+1);
2442 declare_register (name, i);
2443 }
2444 }
2445 }
2446
2447 /* Construct a symbol for an address type. */
2448
2449 static void
2450 declare_addrtype (const char *name, int number)
2451 {
2452 const char *err;
2453 symbolS *addrtypeS = symbol_create (name, undefined_section,
2454 number, &zero_address_frag);
2455
2456 err = hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS),
2457 (void *) addrtypeS);
2458 if (err)
2459 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2460 name, err);
2461 }
2462
2463 /* Port-specific assembler initialization. This function is called
2464 once, at assembler startup time. */
2465
2466 void
2467 md_begin (void)
2468 {
2469 const struct arc_opcode *opcode = arc_opcodes;
2470
2471 if (mach_selection_mode == MACH_SELECTION_NONE)
2472 arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
2473
2474 /* The endianness can be chosen "at the factory". */
2475 target_big_endian = byte_order == BIG_ENDIAN;
2476
2477 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
2478 as_warn (_("could not set architecture and machine"));
2479
2480 /* Set elf header flags. */
2481 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
2482
2483 /* Set up a hash table for the instructions. */
2484 arc_opcode_hash = hash_new ();
2485 if (arc_opcode_hash == NULL)
2486 as_fatal (_("Virtual memory exhausted"));
2487
2488 /* Initialize the hash table with the insns. */
2489 do
2490 {
2491 const char *name = opcode->name;
2492
2493 arc_insert_opcode (opcode);
2494
2495 while (++opcode && opcode->name
2496 && (opcode->name == name
2497 || !strcmp (opcode->name, name)))
2498 continue;
2499 }while (opcode->name);
2500
2501 /* Register declaration. */
2502 arc_reg_hash = hash_new ();
2503 if (arc_reg_hash == NULL)
2504 as_fatal (_("Virtual memory exhausted"));
2505
2506 declare_register_set ();
2507 declare_register ("gp", 26);
2508 declare_register ("fp", 27);
2509 declare_register ("sp", 28);
2510 declare_register ("ilink", 29);
2511 declare_register ("ilink1", 29);
2512 declare_register ("ilink2", 30);
2513 declare_register ("blink", 31);
2514
2515 /* XY memory registers. */
2516 declare_register ("x0_u0", 32);
2517 declare_register ("x0_u1", 33);
2518 declare_register ("x1_u0", 34);
2519 declare_register ("x1_u1", 35);
2520 declare_register ("x2_u0", 36);
2521 declare_register ("x2_u1", 37);
2522 declare_register ("x3_u0", 38);
2523 declare_register ("x3_u1", 39);
2524 declare_register ("y0_u0", 40);
2525 declare_register ("y0_u1", 41);
2526 declare_register ("y1_u0", 42);
2527 declare_register ("y1_u1", 43);
2528 declare_register ("y2_u0", 44);
2529 declare_register ("y2_u1", 45);
2530 declare_register ("y3_u0", 46);
2531 declare_register ("y3_u1", 47);
2532 declare_register ("x0_nu", 48);
2533 declare_register ("x1_nu", 49);
2534 declare_register ("x2_nu", 50);
2535 declare_register ("x3_nu", 51);
2536 declare_register ("y0_nu", 52);
2537 declare_register ("y1_nu", 53);
2538 declare_register ("y2_nu", 54);
2539 declare_register ("y3_nu", 55);
2540
2541 declare_register ("mlo", 57);
2542 declare_register ("mmid", 58);
2543 declare_register ("mhi", 59);
2544
2545 declare_register ("acc1", 56);
2546 declare_register ("acc2", 57);
2547
2548 declare_register ("lp_count", 60);
2549 declare_register ("pcl", 63);
2550
2551 /* Initialize the last instructions. */
2552 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
2553
2554 /* Aux register declaration. */
2555 arc_aux_hash = hash_new ();
2556 if (arc_aux_hash == NULL)
2557 as_fatal (_("Virtual memory exhausted"));
2558
2559 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2560 unsigned int i;
2561 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2562 {
2563 const char *retval;
2564
2565 if (!(auxr->cpu & selected_cpu.flags))
2566 continue;
2567
2568 if ((auxr->subclass != NONE)
2569 && !check_cpu_feature (auxr->subclass))
2570 continue;
2571
2572 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
2573 if (retval)
2574 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2575 auxr->name, retval);
2576 }
2577
2578 /* Address type declaration. */
2579 arc_addrtype_hash = hash_new ();
2580 if (arc_addrtype_hash == NULL)
2581 as_fatal (_("Virtual memory exhausted"));
2582
2583 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
2584 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
2585 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
2586 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
2587 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
2588 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
2589 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
2590 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
2591 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
2592 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
2593 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
2594 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
2595 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
2596 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
2597 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
2598 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
2599 }
2600
2601 /* Write a value out to the object file, using the appropriate
2602 endianness. */
2603
2604 void
2605 md_number_to_chars (char *buf,
2606 valueT val,
2607 int n)
2608 {
2609 if (target_big_endian)
2610 number_to_chars_bigendian (buf, val, n);
2611 else
2612 number_to_chars_littleendian (buf, val, n);
2613 }
2614
2615 /* Round up a section size to the appropriate boundary. */
2616
2617 valueT
2618 md_section_align (segT segment,
2619 valueT size)
2620 {
2621 int align = bfd_get_section_alignment (stdoutput, segment);
2622
2623 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
2624 }
2625
2626 /* The location from which a PC relative jump should be calculated,
2627 given a PC relative reloc. */
2628
2629 long
2630 md_pcrel_from_section (fixS *fixP,
2631 segT sec)
2632 {
2633 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
2634
2635 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
2636
2637 if (fixP->fx_addsy != (symbolS *) NULL
2638 && (!S_IS_DEFINED (fixP->fx_addsy)
2639 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2640 {
2641 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
2642
2643 /* The symbol is undefined (or is defined but not in this section).
2644 Let the linker figure it out. */
2645 return 0;
2646 }
2647
2648 if ((int) fixP->fx_r_type < 0)
2649 {
2650 /* These are the "internal" relocations. Align them to
2651 32 bit boundary (PCL), for the moment. */
2652 base &= ~3;
2653 }
2654 else
2655 {
2656 switch (fixP->fx_r_type)
2657 {
2658 case BFD_RELOC_ARC_PC32:
2659 /* The hardware calculates relative to the start of the
2660 insn, but this relocation is relative to location of the
2661 LIMM, compensate. The base always needs to be
2662 subtracted by 4 as we do not support this type of PCrel
2663 relocation for short instructions. */
2664 base -= 4;
2665 /* Fall through. */
2666 case BFD_RELOC_ARC_PLT32:
2667 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2668 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2669 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2670 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2671
2672 case BFD_RELOC_ARC_S21H_PCREL:
2673 case BFD_RELOC_ARC_S25H_PCREL:
2674 case BFD_RELOC_ARC_S13_PCREL:
2675 case BFD_RELOC_ARC_S21W_PCREL:
2676 case BFD_RELOC_ARC_S25W_PCREL:
2677 base &= ~3;
2678 break;
2679 default:
2680 as_bad_where (fixP->fx_file, fixP->fx_line,
2681 _("unhandled reloc %s in md_pcrel_from_section"),
2682 bfd_get_reloc_code_name (fixP->fx_r_type));
2683 break;
2684 }
2685 }
2686
2687 pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, "
2688 "symbol: %s (%"BFD_VMA_FMT"x)\n",
2689 fixP->fx_frag->fr_address, fixP->fx_where, base,
2690 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2691 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2692
2693 return base;
2694 }
2695
2696 /* Given a BFD relocation find the coresponding operand. */
2697
2698 static const struct arc_operand *
2699 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2700 {
2701 unsigned i;
2702
2703 for (i = 0; i < arc_num_operands; i++)
2704 if (arc_operands[i].default_reloc == reloc)
2705 return &arc_operands[i];
2706 return NULL;
2707 }
2708
2709 /* Insert an operand value into an instruction. */
2710
2711 static unsigned long long
2712 insert_operand (unsigned long long insn,
2713 const struct arc_operand *operand,
2714 long long val,
2715 const char *file,
2716 unsigned line)
2717 {
2718 offsetT min = 0, max = 0;
2719
2720 if (operand->bits != 32
2721 && !(operand->flags & ARC_OPERAND_NCHK)
2722 && !(operand->flags & ARC_OPERAND_FAKE))
2723 {
2724 if (operand->flags & ARC_OPERAND_SIGNED)
2725 {
2726 max = (1 << (operand->bits - 1)) - 1;
2727 min = -(1 << (operand->bits - 1));
2728 }
2729 else
2730 {
2731 max = (1 << operand->bits) - 1;
2732 min = 0;
2733 }
2734
2735 if (val < min || val > max)
2736 as_bad_value_out_of_range (_("operand"),
2737 val, min, max, file, line);
2738 }
2739
2740 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08llx\n",
2741 min, val, max, insn);
2742
2743 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2744 && (val & 0x03))
2745 as_bad_where (file, line,
2746 _("Unaligned operand. Needs to be 32bit aligned"));
2747
2748 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2749 && (val & 0x01))
2750 as_bad_where (file, line,
2751 _("Unaligned operand. Needs to be 16bit aligned"));
2752
2753 if (operand->insert)
2754 {
2755 const char *errmsg = NULL;
2756
2757 insn = (*operand->insert) (insn, val, &errmsg);
2758 if (errmsg)
2759 as_warn_where (file, line, "%s", errmsg);
2760 }
2761 else
2762 {
2763 if (operand->flags & ARC_OPERAND_TRUNCATE)
2764 {
2765 if (operand->flags & ARC_OPERAND_ALIGNED32)
2766 val >>= 2;
2767 if (operand->flags & ARC_OPERAND_ALIGNED16)
2768 val >>= 1;
2769 }
2770 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2771 }
2772 return insn;
2773 }
2774
2775 /* Apply a fixup to the object code. At this point all symbol values
2776 should be fully resolved, and we attempt to completely resolve the
2777 reloc. If we can not do that, we determine the correct reloc code
2778 and put it back in the fixup. To indicate that a fixup has been
2779 eliminated, set fixP->fx_done. */
2780
2781 void
2782 md_apply_fix (fixS *fixP,
2783 valueT *valP,
2784 segT seg)
2785 {
2786 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2787 valueT value = *valP;
2788 unsigned insn = 0;
2789 symbolS *fx_addsy, *fx_subsy;
2790 offsetT fx_offset;
2791 segT add_symbol_segment = absolute_section;
2792 segT sub_symbol_segment = absolute_section;
2793 const struct arc_operand *operand = NULL;
2794 extended_bfd_reloc_code_real_type reloc;
2795
2796 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2797 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2798 ((int) fixP->fx_r_type < 0) ? "Internal":
2799 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2800 fixP->fx_offset);
2801
2802 fx_addsy = fixP->fx_addsy;
2803 fx_subsy = fixP->fx_subsy;
2804 fx_offset = 0;
2805
2806 if (fx_addsy)
2807 {
2808 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
2809 }
2810
2811 if (fx_subsy
2812 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2813 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2814 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2815 {
2816 resolve_symbol_value (fx_subsy);
2817 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
2818
2819 if (sub_symbol_segment == absolute_section)
2820 {
2821 /* The symbol is really a constant. */
2822 fx_offset -= S_GET_VALUE (fx_subsy);
2823 fx_subsy = NULL;
2824 }
2825 else
2826 {
2827 as_bad_where (fixP->fx_file, fixP->fx_line,
2828 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2829 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2830 segment_name (add_symbol_segment),
2831 S_GET_NAME (fx_subsy),
2832 segment_name (sub_symbol_segment));
2833 return;
2834 }
2835 }
2836
2837 if (fx_addsy
2838 && !S_IS_WEAK (fx_addsy))
2839 {
2840 if (add_symbol_segment == seg
2841 && fixP->fx_pcrel)
2842 {
2843 value += S_GET_VALUE (fx_addsy);
2844 value -= md_pcrel_from_section (fixP, seg);
2845 fx_addsy = NULL;
2846 fixP->fx_pcrel = FALSE;
2847 }
2848 else if (add_symbol_segment == absolute_section)
2849 {
2850 value = fixP->fx_offset;
2851 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2852 fx_addsy = NULL;
2853 fixP->fx_pcrel = FALSE;
2854 }
2855 }
2856
2857 if (!fx_addsy)
2858 fixP->fx_done = TRUE;
2859
2860 if (fixP->fx_pcrel)
2861 {
2862 if (fx_addsy
2863 && ((S_IS_DEFINED (fx_addsy)
2864 && S_GET_SEGMENT (fx_addsy) != seg)
2865 || S_IS_WEAK (fx_addsy)))
2866 value += md_pcrel_from_section (fixP, seg);
2867
2868 switch (fixP->fx_r_type)
2869 {
2870 case BFD_RELOC_ARC_32_ME:
2871 /* This is a pc-relative value in a LIMM. Adjust it to the
2872 address of the instruction not to the address of the
2873 LIMM. Note: it is not anylonger valid this afirmation as
2874 the linker consider ARC_PC32 a fixup to entire 64 bit
2875 insn. */
2876 fixP->fx_offset += fixP->fx_frag->fr_address;
2877 /* Fall through. */
2878 case BFD_RELOC_32:
2879 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2880 /* Fall through. */
2881 case BFD_RELOC_ARC_PC32:
2882 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2883 break;
2884 default:
2885 if ((int) fixP->fx_r_type < 0)
2886 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2887 fixP->fx_r_type);
2888 break;
2889 }
2890 }
2891
2892 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2893 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2894 ((int) fixP->fx_r_type < 0) ? "Internal":
2895 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2896 fixP->fx_offset);
2897
2898
2899 /* Now check for TLS relocations. */
2900 reloc = fixP->fx_r_type;
2901 switch (reloc)
2902 {
2903 case BFD_RELOC_ARC_TLS_DTPOFF:
2904 case BFD_RELOC_ARC_TLS_LE_32:
2905 if (fixP->fx_done)
2906 break;
2907 /* Fall through. */
2908 case BFD_RELOC_ARC_TLS_GD_GOT:
2909 case BFD_RELOC_ARC_TLS_IE_GOT:
2910 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2911 break;
2912
2913 case BFD_RELOC_ARC_TLS_GD_LD:
2914 gas_assert (!fixP->fx_offset);
2915 if (fixP->fx_subsy)
2916 fixP->fx_offset
2917 = (S_GET_VALUE (fixP->fx_subsy)
2918 - fixP->fx_frag->fr_address- fixP->fx_where);
2919 fixP->fx_subsy = NULL;
2920 /* Fall through. */
2921 case BFD_RELOC_ARC_TLS_GD_CALL:
2922 /* These two relocs are there just to allow ld to change the tls
2923 model for this symbol, by patching the code. The offset -
2924 and scale, if any - will be installed by the linker. */
2925 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2926 break;
2927
2928 case BFD_RELOC_ARC_TLS_LE_S9:
2929 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
2930 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2931 break;
2932
2933 default:
2934 break;
2935 }
2936
2937 if (!fixP->fx_done)
2938 {
2939 return;
2940 }
2941
2942 /* Addjust the value if we have a constant. */
2943 value += fx_offset;
2944
2945 /* For hosts with longs bigger than 32-bits make sure that the top
2946 bits of a 32-bit negative value read in by the parser are set,
2947 so that the correct comparisons are made. */
2948 if (value & 0x80000000)
2949 value |= (-1UL << 31);
2950
2951 reloc = fixP->fx_r_type;
2952 switch (reloc)
2953 {
2954 case BFD_RELOC_8:
2955 case BFD_RELOC_16:
2956 case BFD_RELOC_24:
2957 case BFD_RELOC_32:
2958 case BFD_RELOC_64:
2959 case BFD_RELOC_ARC_32_PCREL:
2960 md_number_to_chars (fixpos, value, fixP->fx_size);
2961 return;
2962
2963 case BFD_RELOC_ARC_GOTPC32:
2964 /* I cannot fix an GOTPC relocation because I need to relax it
2965 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2966 as_bad (_("Unsupported operation on reloc"));
2967 return;
2968
2969 case BFD_RELOC_ARC_TLS_DTPOFF:
2970 case BFD_RELOC_ARC_TLS_LE_32:
2971 gas_assert (!fixP->fx_addsy);
2972 gas_assert (!fixP->fx_subsy);
2973 /* Fall through. */
2974
2975 case BFD_RELOC_ARC_GOTOFF:
2976 case BFD_RELOC_ARC_32_ME:
2977 case BFD_RELOC_ARC_PC32:
2978 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
2979 return;
2980
2981 case BFD_RELOC_ARC_PLT32:
2982 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
2983 return;
2984
2985 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2986 reloc = BFD_RELOC_ARC_S25W_PCREL;
2987 goto solve_plt;
2988
2989 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2990 reloc = BFD_RELOC_ARC_S21H_PCREL;
2991 goto solve_plt;
2992
2993 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2994 reloc = BFD_RELOC_ARC_S25W_PCREL;
2995 goto solve_plt;
2996
2997 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2998 reloc = BFD_RELOC_ARC_S21W_PCREL;
2999 /* Fall through. */
3000
3001 case BFD_RELOC_ARC_S25W_PCREL:
3002 case BFD_RELOC_ARC_S21W_PCREL:
3003 case BFD_RELOC_ARC_S21H_PCREL:
3004 case BFD_RELOC_ARC_S25H_PCREL:
3005 case BFD_RELOC_ARC_S13_PCREL:
3006 solve_plt:
3007 operand = find_operand_for_reloc (reloc);
3008 gas_assert (operand);
3009 break;
3010
3011 default:
3012 {
3013 if ((int) fixP->fx_r_type >= 0)
3014 as_fatal (_("unhandled relocation type %s"),
3015 bfd_get_reloc_code_name (fixP->fx_r_type));
3016
3017 /* The rest of these fixups needs to be completely resolved as
3018 constants. */
3019 if (fixP->fx_addsy != 0
3020 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
3021 as_bad_where (fixP->fx_file, fixP->fx_line,
3022 _("non-absolute expression in constant field"));
3023
3024 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
3025 operand = &arc_operands[-(int) fixP->fx_r_type];
3026 break;
3027 }
3028 }
3029
3030 if (target_big_endian)
3031 {
3032 switch (fixP->fx_size)
3033 {
3034 case 4:
3035 insn = bfd_getb32 (fixpos);
3036 break;
3037 case 2:
3038 insn = bfd_getb16 (fixpos);
3039 break;
3040 default:
3041 as_bad_where (fixP->fx_file, fixP->fx_line,
3042 _("unknown fixup size"));
3043 }
3044 }
3045 else
3046 {
3047 insn = 0;
3048 switch (fixP->fx_size)
3049 {
3050 case 4:
3051 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
3052 break;
3053 case 2:
3054 insn = bfd_getl16 (fixpos);
3055 break;
3056 default:
3057 as_bad_where (fixP->fx_file, fixP->fx_line,
3058 _("unknown fixup size"));
3059 }
3060 }
3061
3062 insn = insert_operand (insn, operand, (offsetT) value,
3063 fixP->fx_file, fixP->fx_line);
3064
3065 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
3066 }
3067
3068 /* Prepare machine-dependent frags for relaxation.
3069
3070 Called just before relaxation starts. Any symbol that is now undefined
3071 will not become defined.
3072
3073 Return the correct fr_subtype in the frag.
3074
3075 Return the initial "guess for fr_var" to caller. The guess for fr_var
3076 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3077 or fr_var contributes to our returned value.
3078
3079 Although it may not be explicit in the frag, pretend
3080 fr_var starts with a value. */
3081
3082 int
3083 md_estimate_size_before_relax (fragS *fragP,
3084 segT segment)
3085 {
3086 int growth;
3087
3088 /* If the symbol is not located within the same section AND it's not
3089 an absolute section, use the maximum. OR if the symbol is a
3090 constant AND the insn is by nature not pc-rel, use the maximum.
3091 OR if the symbol is being equated against another symbol, use the
3092 maximum. OR if the symbol is weak use the maximum. */
3093 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
3094 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
3095 || (symbol_constant_p (fragP->fr_symbol)
3096 && !fragP->tc_frag_data.pcrel)
3097 || symbol_equated_p (fragP->fr_symbol)
3098 || S_IS_WEAK (fragP->fr_symbol))
3099 {
3100 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
3101 ++fragP->fr_subtype;
3102 }
3103
3104 growth = md_relax_table[fragP->fr_subtype].rlx_length;
3105 fragP->fr_var = growth;
3106
3107 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3108 fragP->fr_file, fragP->fr_line, growth);
3109
3110 return growth;
3111 }
3112
3113 /* Translate internal representation of relocation info to BFD target
3114 format. */
3115
3116 arelent *
3117 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
3118 fixS *fixP)
3119 {
3120 arelent *reloc;
3121 bfd_reloc_code_real_type code;
3122
3123 reloc = XNEW (arelent);
3124 reloc->sym_ptr_ptr = XNEW (asymbol *);
3125 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3126 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
3127
3128 /* Make sure none of our internal relocations make it this far.
3129 They'd better have been fully resolved by this point. */
3130 gas_assert ((int) fixP->fx_r_type > 0);
3131
3132 code = fixP->fx_r_type;
3133
3134 /* if we have something like add gp, pcl,
3135 _GLOBAL_OFFSET_TABLE_@gotpc. */
3136 if (code == BFD_RELOC_ARC_GOTPC32
3137 && GOT_symbol
3138 && fixP->fx_addsy == GOT_symbol)
3139 code = BFD_RELOC_ARC_GOTPC;
3140
3141 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3142 if (reloc->howto == NULL)
3143 {
3144 as_bad_where (fixP->fx_file, fixP->fx_line,
3145 _("cannot represent `%s' relocation in object file"),
3146 bfd_get_reloc_code_name (code));
3147 return NULL;
3148 }
3149
3150 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
3151 as_fatal (_("internal error? cannot generate `%s' relocation"),
3152 bfd_get_reloc_code_name (code));
3153
3154 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
3155
3156 reloc->addend = fixP->fx_offset;
3157
3158 return reloc;
3159 }
3160
3161 /* Perform post-processing of machine-dependent frags after relaxation.
3162 Called after relaxation is finished.
3163 In: Address of frag.
3164 fr_type == rs_machine_dependent.
3165 fr_subtype is what the address relaxed to.
3166
3167 Out: Any fixS:s and constants are set up. */
3168
3169 void
3170 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3171 segT segment ATTRIBUTE_UNUSED,
3172 fragS *fragP)
3173 {
3174 const relax_typeS *table_entry;
3175 char *dest;
3176 const struct arc_opcode *opcode;
3177 struct arc_insn insn;
3178 int size, fix;
3179 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
3180
3181 fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
3182 dest = fragP->fr_literal + fix;
3183 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
3184
3185 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3186 "var: %"BFD_VMA_FMT"d\n",
3187 fragP->fr_file, fragP->fr_line,
3188 fragP->fr_subtype, fix, fragP->fr_var);
3189
3190 if (fragP->fr_subtype <= 0
3191 && fragP->fr_subtype >= arc_num_relax_opcodes)
3192 as_fatal (_("no relaxation found for this instruction."));
3193
3194 opcode = &arc_relax_opcodes[fragP->fr_subtype];
3195
3196 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3197 relax_arg->nflg, &insn);
3198
3199 apply_fixups (&insn, fragP, fix);
3200
3201 size = insn.len + (insn.has_limm ? 4 : 0);
3202 gas_assert (table_entry->rlx_length == size);
3203 emit_insn0 (&insn, dest, TRUE);
3204
3205 fragP->fr_fix += table_entry->rlx_length;
3206 fragP->fr_var = 0;
3207 }
3208
3209 /* We have no need to default values of symbols. We could catch
3210 register names here, but that is handled by inserting them all in
3211 the symbol table to begin with. */
3212
3213 symbolS *
3214 md_undefined_symbol (char *name)
3215 {
3216 /* The arc abi demands that a GOT[0] should be referencible as
3217 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3218 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3219 if (((*name == '_')
3220 && (*(name+1) == 'G')
3221 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0))
3222 || ((*name == '_')
3223 && (*(name+1) == 'D')
3224 && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0)))
3225 {
3226 if (!GOT_symbol)
3227 {
3228 if (symbol_find (name))
3229 as_bad ("GOT already in symbol table");
3230
3231 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
3232 (valueT) 0, &zero_address_frag);
3233 };
3234 return GOT_symbol;
3235 }
3236 return NULL;
3237 }
3238
3239 /* Turn a string in input_line_pointer into a floating point constant
3240 of type type, and store the appropriate bytes in *litP. The number
3241 of LITTLENUMS emitted is stored in *sizeP. An error message is
3242 returned, or NULL on OK. */
3243
3244 const char *
3245 md_atof (int type, char *litP, int *sizeP)
3246 {
3247 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3248 }
3249
3250 /* Called for any expression that can not be recognized. When the
3251 function is called, `input_line_pointer' will point to the start of
3252 the expression. */
3253
3254 void
3255 md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
3256 {
3257 char *p = input_line_pointer;
3258 if (*p == '@')
3259 {
3260 input_line_pointer++;
3261 expressionP->X_op = O_symbol;
3262 expression (expressionP);
3263 }
3264 }
3265
3266 /* This function is called from the function 'expression', it attempts
3267 to parse special names (in our case register names). It fills in
3268 the expression with the identified register. It returns TRUE if
3269 it is a register and FALSE otherwise. */
3270
3271 bfd_boolean
3272 arc_parse_name (const char *name,
3273 struct expressionS *e)
3274 {
3275 struct symbol *sym;
3276
3277 if (!assembling_insn)
3278 return FALSE;
3279
3280 if (e->X_op == O_symbol)
3281 return FALSE;
3282
3283 sym = hash_find (arc_reg_hash, name);
3284 if (sym)
3285 {
3286 e->X_op = O_register;
3287 e->X_add_number = S_GET_VALUE (sym);
3288 return TRUE;
3289 }
3290
3291 sym = hash_find (arc_addrtype_hash, name);
3292 if (sym)
3293 {
3294 e->X_op = O_addrtype;
3295 e->X_add_number = S_GET_VALUE (sym);
3296 return TRUE;
3297 }
3298
3299 return FALSE;
3300 }
3301
3302 /* md_parse_option
3303 Invocation line includes a switch not recognized by the base assembler.
3304 See if it's a processor-specific option.
3305
3306 New options (supported) are:
3307
3308 -mcpu=<cpu name> Assemble for selected processor
3309 -EB/-mbig-endian Big-endian
3310 -EL/-mlittle-endian Little-endian
3311 -mrelax Enable relaxation
3312
3313 The following CPU names are recognized:
3314 arc600, arc700, arcem, archs, nps400. */
3315
3316 int
3317 md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
3318 {
3319 switch (c)
3320 {
3321 case OPTION_ARC600:
3322 case OPTION_ARC601:
3323 return md_parse_option (OPTION_MCPU, "arc600");
3324
3325 case OPTION_ARC700:
3326 return md_parse_option (OPTION_MCPU, "arc700");
3327
3328 case OPTION_ARCEM:
3329 return md_parse_option (OPTION_MCPU, "arcem");
3330
3331 case OPTION_ARCHS:
3332 return md_parse_option (OPTION_MCPU, "archs");
3333
3334 case OPTION_MCPU:
3335 {
3336 arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
3337 break;
3338 }
3339
3340 case OPTION_EB:
3341 arc_target_format = "elf32-bigarc";
3342 byte_order = BIG_ENDIAN;
3343 break;
3344
3345 case OPTION_EL:
3346 arc_target_format = "elf32-littlearc";
3347 byte_order = LITTLE_ENDIAN;
3348 break;
3349
3350 case OPTION_CD:
3351 selected_cpu.features |= ARC_CD;
3352 arc_check_feature ();
3353 break;
3354
3355 case OPTION_RELAX:
3356 relaxation_state = 1;
3357 break;
3358
3359 case OPTION_NPS400:
3360 selected_cpu.features |= ARC_NPS400;
3361 arc_check_feature ();
3362 break;
3363
3364 case OPTION_SPFP:
3365 selected_cpu.features |= ARC_SPFP;
3366 arc_check_feature ();
3367 break;
3368
3369 case OPTION_DPFP:
3370 selected_cpu.features |= ARC_DPFP;
3371 arc_check_feature ();
3372 break;
3373
3374 case OPTION_FPUDA:
3375 selected_cpu.features |= ARC_FPUDA;
3376 arc_check_feature ();
3377 break;
3378
3379 /* Dummy options are accepted but have no effect. */
3380 case OPTION_USER_MODE:
3381 case OPTION_LD_EXT_MASK:
3382 case OPTION_SWAP:
3383 case OPTION_NORM:
3384 case OPTION_BARREL_SHIFT:
3385 case OPTION_MIN_MAX:
3386 case OPTION_NO_MPY:
3387 case OPTION_EA:
3388 case OPTION_MUL64:
3389 case OPTION_SIMD:
3390 case OPTION_XMAC_D16:
3391 case OPTION_XMAC_24:
3392 case OPTION_DSP_PACKA:
3393 case OPTION_CRC:
3394 case OPTION_DVBF:
3395 case OPTION_TELEPHONY:
3396 case OPTION_XYMEMORY:
3397 case OPTION_LOCK:
3398 case OPTION_SWAPE:
3399 case OPTION_RTSC:
3400 break;
3401
3402 default:
3403 return 0;
3404 }
3405
3406 return 1;
3407 }
3408
3409 void
3410 md_show_usage (FILE *stream)
3411 {
3412 fprintf (stream, _("ARC-specific assembler options:\n"));
3413
3414 fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name> "
3415 "(default: %s)\n", TARGET_WITH_CPU);
3416 fprintf (stream, " -mcpu=nps400\t\t same as -mcpu=arc700 -mnps400\n");
3417 fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3418 fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3419 fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
3420 fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
3421
3422 fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
3423 fprintf (stream, " -mspfp\t\t enable single-precision floating point instructions\n");
3424 fprintf (stream, " -mdpfp\t\t enable double-precision floating point instructions\n");
3425 fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
3426 "point\n\t\t\t instructions for ARC EM\n");
3427
3428 fprintf (stream,
3429 " -mcode-density\t enable code density option for ARC EM\n");
3430
3431 fprintf (stream, _("\
3432 -EB assemble code for a big-endian cpu\n"));
3433 fprintf (stream, _("\
3434 -EL assemble code for a little-endian cpu\n"));
3435 fprintf (stream, _("\
3436 -mrelax enable relaxation\n"));
3437
3438 fprintf (stream, _("The following ARC-specific assembler options are "
3439 "deprecated and are accepted\nfor compatibility only:\n"));
3440
3441 fprintf (stream, _(" -mEA\n"
3442 " -mbarrel-shifter\n"
3443 " -mbarrel_shifter\n"
3444 " -mcrc\n"
3445 " -mdsp-packa\n"
3446 " -mdsp_packa\n"
3447 " -mdvbf\n"
3448 " -mld-extension-reg-mask\n"
3449 " -mlock\n"
3450 " -mmac-24\n"
3451 " -mmac-d16\n"
3452 " -mmac_24\n"
3453 " -mmac_d16\n"
3454 " -mmin-max\n"
3455 " -mmin_max\n"
3456 " -mmul64\n"
3457 " -mno-mpy\n"
3458 " -mnorm\n"
3459 " -mrtsc\n"
3460 " -msimd\n"
3461 " -mswap\n"
3462 " -mswape\n"
3463 " -mtelephony\n"
3464 " -muser-mode-only\n"
3465 " -mxy\n"));
3466 }
3467
3468 /* Find the proper relocation for the given opcode. */
3469
3470 static extended_bfd_reloc_code_real_type
3471 find_reloc (const char *name,
3472 const char *opcodename,
3473 const struct arc_flags *pflags,
3474 int nflg,
3475 extended_bfd_reloc_code_real_type reloc)
3476 {
3477 unsigned int i;
3478 int j;
3479 bfd_boolean found_flag, tmp;
3480 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3481
3482 for (i = 0; i < arc_num_equiv_tab; i++)
3483 {
3484 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3485
3486 /* Find the entry. */
3487 if (strcmp (name, r->name))
3488 continue;
3489 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3490 continue;
3491 if (r->flags[0])
3492 {
3493 if (!nflg)
3494 continue;
3495 found_flag = FALSE;
3496 unsigned * psflg = (unsigned *)r->flags;
3497 do
3498 {
3499 tmp = FALSE;
3500 for (j = 0; j < nflg; j++)
3501 if (!strcmp (pflags[j].name,
3502 arc_flag_operands[*psflg].name))
3503 {
3504 tmp = TRUE;
3505 break;
3506 }
3507 if (!tmp)
3508 {
3509 found_flag = FALSE;
3510 break;
3511 }
3512 else
3513 {
3514 found_flag = TRUE;
3515 }
3516 ++ psflg;
3517 } while (*psflg);
3518
3519 if (!found_flag)
3520 continue;
3521 }
3522
3523 if (reloc != r->oldreloc)
3524 continue;
3525 /* Found it. */
3526 ret = r->newreloc;
3527 break;
3528 }
3529
3530 if (ret == BFD_RELOC_UNUSED)
3531 as_bad (_("Unable to find %s relocation for instruction %s"),
3532 name, opcodename);
3533 return ret;
3534 }
3535
3536 /* All the symbol types that are allowed to be used for
3537 relaxation. */
3538
3539 static bfd_boolean
3540 may_relax_expr (expressionS tok)
3541 {
3542 /* Check if we have unrelaxable relocs. */
3543 switch (tok.X_md)
3544 {
3545 default:
3546 break;
3547 case O_plt:
3548 return FALSE;
3549 }
3550
3551 switch (tok.X_op)
3552 {
3553 case O_symbol:
3554 case O_multiply:
3555 case O_divide:
3556 case O_modulus:
3557 case O_add:
3558 case O_subtract:
3559 break;
3560
3561 default:
3562 return FALSE;
3563 }
3564 return TRUE;
3565 }
3566
3567 /* Checks if flags are in line with relaxable insn. */
3568
3569 static bfd_boolean
3570 relaxable_flag (const struct arc_relaxable_ins *ins,
3571 const struct arc_flags *pflags,
3572 int nflgs)
3573 {
3574 unsigned flag_class,
3575 flag,
3576 flag_class_idx = 0,
3577 flag_idx = 0;
3578
3579 const struct arc_flag_operand *flag_opand;
3580 int i, counttrue = 0;
3581
3582 /* Iterate through flags classes. */
3583 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3584 {
3585 /* Iterate through flags in flag class. */
3586 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3587 != 0)
3588 {
3589 flag_opand = &arc_flag_operands[flag];
3590 /* Iterate through flags in ins to compare. */
3591 for (i = 0; i < nflgs; ++i)
3592 {
3593 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3594 ++counttrue;
3595 }
3596
3597 ++flag_idx;
3598 }
3599
3600 ++flag_class_idx;
3601 flag_idx = 0;
3602 }
3603
3604 /* If counttrue == nflgs, then all flags have been found. */
3605 return (counttrue == nflgs ? TRUE : FALSE);
3606 }
3607
3608 /* Checks if operands are in line with relaxable insn. */
3609
3610 static bfd_boolean
3611 relaxable_operand (const struct arc_relaxable_ins *ins,
3612 const expressionS *tok,
3613 int ntok)
3614 {
3615 const enum rlx_operand_type *operand = &ins->operands[0];
3616 int i = 0;
3617
3618 while (*operand != EMPTY)
3619 {
3620 const expressionS *epr = &tok[i];
3621
3622 if (i != 0 && i >= ntok)
3623 return FALSE;
3624
3625 switch (*operand)
3626 {
3627 case IMMEDIATE:
3628 if (!(epr->X_op == O_multiply
3629 || epr->X_op == O_divide
3630 || epr->X_op == O_modulus
3631 || epr->X_op == O_add
3632 || epr->X_op == O_subtract
3633 || epr->X_op == O_symbol))
3634 return FALSE;
3635 break;
3636
3637 case REGISTER_DUP:
3638 if ((i <= 0)
3639 || (epr->X_add_number != tok[i - 1].X_add_number))
3640 return FALSE;
3641 /* Fall through. */
3642 case REGISTER:
3643 if (epr->X_op != O_register)
3644 return FALSE;
3645 break;
3646
3647 case REGISTER_S:
3648 if (epr->X_op != O_register)
3649 return FALSE;
3650
3651 switch (epr->X_add_number)
3652 {
3653 case 0: case 1: case 2: case 3:
3654 case 12: case 13: case 14: case 15:
3655 break;
3656 default:
3657 return FALSE;
3658 }
3659 break;
3660
3661 case REGISTER_NO_GP:
3662 if ((epr->X_op != O_register)
3663 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3664 return FALSE;
3665 break;
3666
3667 case BRACKET:
3668 if (epr->X_op != O_bracket)
3669 return FALSE;
3670 break;
3671
3672 default:
3673 /* Don't understand, bail out. */
3674 return FALSE;
3675 break;
3676 }
3677
3678 ++i;
3679 operand = &ins->operands[i];
3680 }
3681
3682 return (i == ntok ? TRUE : FALSE);
3683 }
3684
3685 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3686
3687 static bfd_boolean
3688 relax_insn_p (const struct arc_opcode *opcode,
3689 const expressionS *tok,
3690 int ntok,
3691 const struct arc_flags *pflags,
3692 int nflg)
3693 {
3694 unsigned i;
3695 bfd_boolean rv = FALSE;
3696
3697 /* Check the relaxation table. */
3698 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3699 {
3700 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3701
3702 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3703 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3704 && relaxable_operand (arc_rlx_ins, tok, ntok)
3705 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3706 {
3707 rv = TRUE;
3708 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3709 memcpy (&frag_now->tc_frag_data.tok, tok,
3710 sizeof (expressionS) * ntok);
3711 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3712 sizeof (struct arc_flags) * nflg);
3713 frag_now->tc_frag_data.nflg = nflg;
3714 frag_now->tc_frag_data.ntok = ntok;
3715 break;
3716 }
3717 }
3718
3719 return rv;
3720 }
3721
3722 /* Turn an opcode description and a set of arguments into
3723 an instruction and a fixup. */
3724
3725 static void
3726 assemble_insn (const struct arc_opcode *opcode,
3727 const expressionS *tok,
3728 int ntok,
3729 const struct arc_flags *pflags,
3730 int nflg,
3731 struct arc_insn *insn)
3732 {
3733 const expressionS *reloc_exp = NULL;
3734 unsigned long long image;
3735 const unsigned char *argidx;
3736 int i;
3737 int tokidx = 0;
3738 unsigned char pcrel = 0;
3739 bfd_boolean needGOTSymbol;
3740 bfd_boolean has_delay_slot = FALSE;
3741 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3742
3743 memset (insn, 0, sizeof (*insn));
3744 image = opcode->opcode;
3745
3746 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
3747 frag_now->fr_file, frag_now->fr_line, opcode->name,
3748 opcode->opcode);
3749
3750 /* Handle operands. */
3751 for (argidx = opcode->operands; *argidx; ++argidx)
3752 {
3753 const struct arc_operand *operand = &arc_operands[*argidx];
3754 const expressionS *t = (const expressionS *) 0;
3755
3756 if (ARC_OPERAND_IS_FAKE (operand))
3757 continue;
3758
3759 if (operand->flags & ARC_OPERAND_DUPLICATE)
3760 {
3761 /* Duplicate operand, already inserted. */
3762 tokidx ++;
3763 continue;
3764 }
3765
3766 if (tokidx >= ntok)
3767 {
3768 abort ();
3769 }
3770 else
3771 t = &tok[tokidx++];
3772
3773 /* Regardless if we have a reloc or not mark the instruction
3774 limm if it is the case. */
3775 if (operand->flags & ARC_OPERAND_LIMM)
3776 insn->has_limm = TRUE;
3777
3778 switch (t->X_op)
3779 {
3780 case O_register:
3781 image = insert_operand (image, operand, regno (t->X_add_number),
3782 NULL, 0);
3783 break;
3784
3785 case O_constant:
3786 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3787 reloc_exp = t;
3788 if (operand->flags & ARC_OPERAND_LIMM)
3789 insn->limm = t->X_add_number;
3790 break;
3791
3792 case O_bracket:
3793 case O_colon:
3794 case O_addrtype:
3795 /* Ignore brackets, colons, and address types. */
3796 break;
3797
3798 case O_absent:
3799 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3800 break;
3801
3802 case O_subtract:
3803 /* Maybe register range. */
3804 if ((t->X_add_number == 0)
3805 && contains_register (t->X_add_symbol)
3806 && contains_register (t->X_op_symbol))
3807 {
3808 int regs;
3809
3810 regs = get_register (t->X_add_symbol);
3811 regs <<= 16;
3812 regs |= get_register (t->X_op_symbol);
3813 image = insert_operand (image, operand, regs, NULL, 0);
3814 break;
3815 }
3816 /* Fall through. */
3817
3818 default:
3819 /* This operand needs a relocation. */
3820 needGOTSymbol = FALSE;
3821
3822 switch (t->X_md)
3823 {
3824 case O_plt:
3825 if (opcode->insn_class == JUMP)
3826 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3827 _("Unable to use @plt relocatio for insn %s"),
3828 opcode->name);
3829 needGOTSymbol = TRUE;
3830 reloc = find_reloc ("plt", opcode->name,
3831 pflags, nflg,
3832 operand->default_reloc);
3833 break;
3834
3835 case O_gotoff:
3836 case O_gotpc:
3837 needGOTSymbol = TRUE;
3838 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3839 break;
3840 case O_pcl:
3841 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3842 if (arc_opcode_len (opcode) == 2
3843 || opcode->insn_class == JUMP)
3844 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3845 _("Unable to use @pcl relocation for insn %s"),
3846 opcode->name);
3847 break;
3848 case O_sda:
3849 reloc = find_reloc ("sda", opcode->name,
3850 pflags, nflg,
3851 operand->default_reloc);
3852 break;
3853 case O_tlsgd:
3854 case O_tlsie:
3855 needGOTSymbol = TRUE;
3856 /* Fall-through. */
3857
3858 case O_tpoff:
3859 case O_dtpoff:
3860 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3861 break;
3862
3863 case O_tpoff9: /*FIXME! Check for the conditionality of
3864 the insn. */
3865 case O_dtpoff9: /*FIXME! Check for the conditionality of
3866 the insn. */
3867 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3868 break;
3869
3870 default:
3871 /* Just consider the default relocation. */
3872 reloc = operand->default_reloc;
3873 break;
3874 }
3875
3876 if (needGOTSymbol && (GOT_symbol == NULL))
3877 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3878
3879 reloc_exp = t;
3880
3881 #if 0
3882 if (reloc > 0)
3883 {
3884 /* sanity checks. */
3885 reloc_howto_type *reloc_howto
3886 = bfd_reloc_type_lookup (stdoutput,
3887 (bfd_reloc_code_real_type) reloc);
3888 unsigned reloc_bitsize = reloc_howto->bitsize;
3889 if (reloc_howto->rightshift)
3890 reloc_bitsize -= reloc_howto->rightshift;
3891 if (reloc_bitsize != operand->bits)
3892 {
3893 as_bad (_("invalid relocation %s for field"),
3894 bfd_get_reloc_code_name (reloc));
3895 return;
3896 }
3897 }
3898 #endif
3899 if (insn->nfixups >= MAX_INSN_FIXUPS)
3900 as_fatal (_("too many fixups"));
3901
3902 struct arc_fixup *fixup;
3903 fixup = &insn->fixups[insn->nfixups++];
3904 fixup->exp = *t;
3905 fixup->reloc = reloc;
3906 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
3907 fixup->pcrel = pcrel;
3908 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
3909 TRUE : FALSE;
3910 break;
3911 }
3912 }
3913
3914 /* Handle flags. */
3915 for (i = 0; i < nflg; i++)
3916 {
3917 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
3918
3919 /* Check if the instruction has a delay slot. */
3920 if (!strcmp (flg_operand->name, "d"))
3921 has_delay_slot = TRUE;
3922
3923 /* There is an exceptional case when we cannot insert a flag
3924 just as it is. The .T flag must be handled in relation with
3925 the relative address. */
3926 if (!strcmp (flg_operand->name, "t")
3927 || !strcmp (flg_operand->name, "nt"))
3928 {
3929 unsigned bitYoperand = 0;
3930 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3931 if (!strcmp (flg_operand->name, "t"))
3932 if (!strcmp (opcode->name, "bbit0")
3933 || !strcmp (opcode->name, "bbit1"))
3934 bitYoperand = arc_NToperand;
3935 else
3936 bitYoperand = arc_Toperand;
3937 else
3938 if (!strcmp (opcode->name, "bbit0")
3939 || !strcmp (opcode->name, "bbit1"))
3940 bitYoperand = arc_Toperand;
3941 else
3942 bitYoperand = arc_NToperand;
3943
3944 gas_assert (reloc_exp != NULL);
3945 if (reloc_exp->X_op == O_constant)
3946 {
3947 /* Check if we have a constant and solved it
3948 immediately. */
3949 offsetT val = reloc_exp->X_add_number;
3950 image |= insert_operand (image, &arc_operands[bitYoperand],
3951 val, NULL, 0);
3952 }
3953 else
3954 {
3955 struct arc_fixup *fixup;
3956
3957 if (insn->nfixups >= MAX_INSN_FIXUPS)
3958 as_fatal (_("too many fixups"));
3959
3960 fixup = &insn->fixups[insn->nfixups++];
3961 fixup->exp = *reloc_exp;
3962 fixup->reloc = -bitYoperand;
3963 fixup->pcrel = pcrel;
3964 fixup->islong = FALSE;
3965 }
3966 }
3967 else
3968 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
3969 << flg_operand->shift;
3970 }
3971
3972 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
3973
3974 /* Instruction length. */
3975 insn->len = arc_opcode_len (opcode);
3976
3977 insn->insn = image;
3978
3979 /* Update last insn status. */
3980 arc_last_insns[1] = arc_last_insns[0];
3981 arc_last_insns[0].opcode = opcode;
3982 arc_last_insns[0].has_limm = insn->has_limm;
3983 arc_last_insns[0].has_delay_slot = has_delay_slot;
3984
3985 /* Check if the current instruction is legally used. */
3986 if (arc_last_insns[1].has_delay_slot
3987 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
3988 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3989 _("A jump/branch instruction in delay slot."));
3990 }
3991
3992 void
3993 arc_handle_align (fragS* fragP)
3994 {
3995 if ((fragP)->fr_type == rs_align_code)
3996 {
3997 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
3998 valueT count = ((fragP)->fr_next->fr_address
3999 - (fragP)->fr_address - (fragP)->fr_fix);
4000
4001 (fragP)->fr_var = 2;
4002
4003 if (count & 1)/* Padding in the gap till the next 2-byte
4004 boundary with 0s. */
4005 {
4006 (fragP)->fr_fix++;
4007 *dest++ = 0;
4008 }
4009 /* Writing nop_s. */
4010 md_number_to_chars (dest, NOP_OPCODE_S, 2);
4011 }
4012 }
4013
4014 /* Here we decide which fixups can be adjusted to make them relative
4015 to the beginning of the section instead of the symbol. Basically
4016 we need to make sure that the dynamic relocations are done
4017 correctly, so in some cases we force the original symbol to be
4018 used. */
4019
4020 int
4021 tc_arc_fix_adjustable (fixS *fixP)
4022 {
4023
4024 /* Prevent all adjustments to global symbols. */
4025 if (S_IS_EXTERNAL (fixP->fx_addsy))
4026 return 0;
4027 if (S_IS_WEAK (fixP->fx_addsy))
4028 return 0;
4029
4030 /* Adjust_reloc_syms doesn't know about the GOT. */
4031 switch (fixP->fx_r_type)
4032 {
4033 case BFD_RELOC_ARC_GOTPC32:
4034 case BFD_RELOC_ARC_PLT32:
4035 case BFD_RELOC_ARC_S25H_PCREL_PLT:
4036 case BFD_RELOC_ARC_S21H_PCREL_PLT:
4037 case BFD_RELOC_ARC_S25W_PCREL_PLT:
4038 case BFD_RELOC_ARC_S21W_PCREL_PLT:
4039 return 0;
4040
4041 default:
4042 break;
4043 }
4044
4045 return 1;
4046 }
4047
4048 /* Compute the reloc type of an expression EXP. */
4049
4050 static void
4051 arc_check_reloc (expressionS *exp,
4052 bfd_reloc_code_real_type *r_type_p)
4053 {
4054 if (*r_type_p == BFD_RELOC_32
4055 && exp->X_op == O_subtract
4056 && exp->X_op_symbol != NULL
4057 && exp->X_op_symbol->bsym->section == now_seg)
4058 *r_type_p = BFD_RELOC_ARC_32_PCREL;
4059 }
4060
4061
4062 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4063
4064 void
4065 arc_cons_fix_new (fragS *frag,
4066 int off,
4067 int size,
4068 expressionS *exp,
4069 bfd_reloc_code_real_type r_type)
4070 {
4071 r_type = BFD_RELOC_UNUSED;
4072
4073 switch (size)
4074 {
4075 case 1:
4076 r_type = BFD_RELOC_8;
4077 break;
4078
4079 case 2:
4080 r_type = BFD_RELOC_16;
4081 break;
4082
4083 case 3:
4084 r_type = BFD_RELOC_24;
4085 break;
4086
4087 case 4:
4088 r_type = BFD_RELOC_32;
4089 arc_check_reloc (exp, &r_type);
4090 break;
4091
4092 case 8:
4093 r_type = BFD_RELOC_64;
4094 break;
4095
4096 default:
4097 as_bad (_("unsupported BFD relocation size %u"), size);
4098 r_type = BFD_RELOC_UNUSED;
4099 }
4100
4101 fix_new_exp (frag, off, size, exp, 0, r_type);
4102 }
4103
4104 /* The actual routine that checks the ZOL conditions. */
4105
4106 static void
4107 check_zol (symbolS *s)
4108 {
4109 switch (selected_cpu.mach)
4110 {
4111 case bfd_mach_arc_arcv2:
4112 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
4113 return;
4114
4115 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
4116 || arc_last_insns[1].has_delay_slot)
4117 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4118 S_GET_NAME (s));
4119
4120 break;
4121 case bfd_mach_arc_arc600:
4122
4123 if (is_kernel_insn_p (arc_last_insns[0].opcode))
4124 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4125 S_GET_NAME (s));
4126
4127 if (arc_last_insns[0].has_limm
4128 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4129 as_bad (_("A jump instruction with long immediate detected at the \
4130 end of the ZOL label @%s"), S_GET_NAME (s));
4131
4132 /* Fall through. */
4133 case bfd_mach_arc_arc700:
4134 if (arc_last_insns[0].has_delay_slot)
4135 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4136 S_GET_NAME (s));
4137
4138 break;
4139 default:
4140 break;
4141 }
4142 }
4143
4144 /* If ZOL end check the last two instruction for illegals. */
4145 void
4146 arc_frob_label (symbolS * sym)
4147 {
4148 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
4149 check_zol (sym);
4150
4151 dwarf2_emit_label (sym);
4152 }
4153
4154 /* Used because generic relaxation assumes a pc-rel value whilst we
4155 also relax instructions that use an absolute value resolved out of
4156 relative values (if that makes any sense). An example: 'add r1,
4157 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4158 but if they're in the same section we can subtract the section
4159 offset relocation which ends up in a resolved value. So if @.L2 is
4160 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4161 .text + 0x40 = 0x10. */
4162 int
4163 arc_pcrel_adjust (fragS *fragP)
4164 {
4165 if (!fragP->tc_frag_data.pcrel)
4166 return fragP->fr_address + fragP->fr_fix;
4167
4168 return 0;
4169 }
4170
4171 /* Initialize the DWARF-2 unwind information for this procedure. */
4172
4173 void
4174 tc_arc_frame_initial_instructions (void)
4175 {
4176 /* Stack pointer is register 28. */
4177 cfi_add_CFA_def_cfa (28, 0);
4178 }
4179
4180 int
4181 tc_arc_regname_to_dw2regnum (char *regname)
4182 {
4183 struct symbol *sym;
4184
4185 sym = hash_find (arc_reg_hash, regname);
4186 if (sym)
4187 return S_GET_VALUE (sym);
4188
4189 return -1;
4190 }
4191
4192 /* Adjust the symbol table. Delete found AUX register symbols. */
4193
4194 void
4195 arc_adjust_symtab (void)
4196 {
4197 symbolS * sym;
4198
4199 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4200 {
4201 /* I've created a symbol during parsing process. Now, remove
4202 the symbol as it is found to be an AUX register. */
4203 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
4204 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4205 }
4206
4207 /* Now do generic ELF adjustments. */
4208 elf_adjust_symtab ();
4209 }
4210
4211 static void
4212 tokenize_extinsn (extInstruction_t *einsn)
4213 {
4214 char *p, c;
4215 char *insn_name;
4216 unsigned char major_opcode;
4217 unsigned char sub_opcode;
4218 unsigned char syntax_class = 0;
4219 unsigned char syntax_class_modifiers = 0;
4220 unsigned char suffix_class = 0;
4221 unsigned int i;
4222
4223 SKIP_WHITESPACE ();
4224
4225 /* 1st: get instruction name. */
4226 p = input_line_pointer;
4227 c = get_symbol_name (&p);
4228
4229 insn_name = xstrdup (p);
4230 restore_line_pointer (c);
4231
4232 /* 2nd: get major opcode. */
4233 if (*input_line_pointer != ',')
4234 {
4235 as_bad (_("expected comma after instruction name"));
4236 ignore_rest_of_line ();
4237 return;
4238 }
4239 input_line_pointer++;
4240 major_opcode = get_absolute_expression ();
4241
4242 /* 3rd: get sub-opcode. */
4243 SKIP_WHITESPACE ();
4244
4245 if (*input_line_pointer != ',')
4246 {
4247 as_bad (_("expected comma after major opcode"));
4248 ignore_rest_of_line ();
4249 return;
4250 }
4251 input_line_pointer++;
4252 sub_opcode = get_absolute_expression ();
4253
4254 /* 4th: get suffix class. */
4255 SKIP_WHITESPACE ();
4256
4257 if (*input_line_pointer != ',')
4258 {
4259 as_bad ("expected comma after sub opcode");
4260 ignore_rest_of_line ();
4261 return;
4262 }
4263 input_line_pointer++;
4264
4265 while (1)
4266 {
4267 SKIP_WHITESPACE ();
4268
4269 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4270 {
4271 if (!strncmp (suffixclass[i].name, input_line_pointer,
4272 suffixclass[i].len))
4273 {
4274 suffix_class |= suffixclass[i].attr_class;
4275 input_line_pointer += suffixclass[i].len;
4276 break;
4277 }
4278 }
4279
4280 if (i == ARRAY_SIZE (suffixclass))
4281 {
4282 as_bad ("invalid suffix class");
4283 ignore_rest_of_line ();
4284 return;
4285 }
4286
4287 SKIP_WHITESPACE ();
4288
4289 if (*input_line_pointer == '|')
4290 input_line_pointer++;
4291 else
4292 break;
4293 }
4294
4295 /* 5th: get syntax class and syntax class modifiers. */
4296 if (*input_line_pointer != ',')
4297 {
4298 as_bad ("expected comma after suffix class");
4299 ignore_rest_of_line ();
4300 return;
4301 }
4302 input_line_pointer++;
4303
4304 while (1)
4305 {
4306 SKIP_WHITESPACE ();
4307
4308 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4309 {
4310 if (!strncmp (syntaxclassmod[i].name,
4311 input_line_pointer,
4312 syntaxclassmod[i].len))
4313 {
4314 syntax_class_modifiers |= syntaxclassmod[i].attr_class;
4315 input_line_pointer += syntaxclassmod[i].len;
4316 break;
4317 }
4318 }
4319
4320 if (i == ARRAY_SIZE (syntaxclassmod))
4321 {
4322 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4323 {
4324 if (!strncmp (syntaxclass[i].name,
4325 input_line_pointer,
4326 syntaxclass[i].len))
4327 {
4328 syntax_class |= syntaxclass[i].attr_class;
4329 input_line_pointer += syntaxclass[i].len;
4330 break;
4331 }
4332 }
4333
4334 if (i == ARRAY_SIZE (syntaxclass))
4335 {
4336 as_bad ("missing syntax class");
4337 ignore_rest_of_line ();
4338 return;
4339 }
4340 }
4341
4342 SKIP_WHITESPACE ();
4343
4344 if (*input_line_pointer == '|')
4345 input_line_pointer++;
4346 else
4347 break;
4348 }
4349
4350 demand_empty_rest_of_line ();
4351
4352 einsn->name = insn_name;
4353 einsn->major = major_opcode;
4354 einsn->minor = sub_opcode;
4355 einsn->syntax = syntax_class;
4356 einsn->modsyn = syntax_class_modifiers;
4357 einsn->suffix = suffix_class;
4358 einsn->flags = syntax_class
4359 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4360 }
4361
4362 /* Generate an extension section. */
4363
4364 static int
4365 arc_set_ext_seg (void)
4366 {
4367 if (!arcext_section)
4368 {
4369 arcext_section = subseg_new (".arcextmap", 0);
4370 bfd_set_section_flags (stdoutput, arcext_section,
4371 SEC_READONLY | SEC_HAS_CONTENTS);
4372 }
4373 else
4374 subseg_set (arcext_section, 0);
4375 return 1;
4376 }
4377
4378 /* Create an extension instruction description in the arc extension
4379 section of the output file.
4380 The structure for an instruction is like this:
4381 [0]: Length of the record.
4382 [1]: Type of the record.
4383
4384 [2]: Major opcode.
4385 [3]: Sub-opcode.
4386 [4]: Syntax (flags).
4387 [5]+ Name instruction.
4388
4389 The sequence is terminated by an empty entry. */
4390
4391 static void
4392 create_extinst_section (extInstruction_t *einsn)
4393 {
4394
4395 segT old_sec = now_seg;
4396 int old_subsec = now_subseg;
4397 char *p;
4398 int name_len = strlen (einsn->name);
4399
4400 arc_set_ext_seg ();
4401
4402 p = frag_more (1);
4403 *p = 5 + name_len + 1;
4404 p = frag_more (1);
4405 *p = EXT_INSTRUCTION;
4406 p = frag_more (1);
4407 *p = einsn->major;
4408 p = frag_more (1);
4409 *p = einsn->minor;
4410 p = frag_more (1);
4411 *p = einsn->flags;
4412 p = frag_more (name_len + 1);
4413 strcpy (p, einsn->name);
4414
4415 subseg_set (old_sec, old_subsec);
4416 }
4417
4418 /* Handler .extinstruction pseudo-op. */
4419
4420 static void
4421 arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4422 {
4423 extInstruction_t einsn;
4424 struct arc_opcode *arc_ext_opcodes;
4425 const char *errmsg = NULL;
4426 unsigned char moplow, mophigh;
4427
4428 memset (&einsn, 0, sizeof (einsn));
4429 tokenize_extinsn (&einsn);
4430
4431 /* Check if the name is already used. */
4432 if (arc_find_opcode (einsn.name))
4433 as_warn (_("Pseudocode already used %s"), einsn.name);
4434
4435 /* Check the opcode ranges. */
4436 moplow = 0x05;
4437 mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
4438 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
4439
4440 if ((einsn.major > mophigh) || (einsn.major < moplow))
4441 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4442
4443 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4444 && (einsn.major != 5) && (einsn.major != 9))
4445 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4446
4447 switch (einsn.syntax & ARC_SYNTAX_MASK)
4448 {
4449 case ARC_SYNTAX_3OP:
4450 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4451 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4452 break;
4453 case ARC_SYNTAX_2OP:
4454 case ARC_SYNTAX_1OP:
4455 case ARC_SYNTAX_NOP:
4456 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4457 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4458 break;
4459 default:
4460 break;
4461 }
4462
4463 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
4464 if (arc_ext_opcodes == NULL)
4465 {
4466 if (errmsg)
4467 as_fatal ("%s", errmsg);
4468 else
4469 as_fatal (_("Couldn't generate extension instruction opcodes"));
4470 }
4471 else if (errmsg)
4472 as_warn ("%s", errmsg);
4473
4474 /* Insert the extension instruction. */
4475 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4476
4477 create_extinst_section (&einsn);
4478 }
4479
4480 static void
4481 tokenize_extregister (extRegister_t *ereg, int opertype)
4482 {
4483 char *name;
4484 char *mode;
4485 char c;
4486 char *p;
4487 int number, imode = 0;
4488 bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE;
4489 bfd_boolean isReg_p = (opertype == EXT_CORE_REGISTER
4490 || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE;
4491
4492 /* 1st: get register name. */
4493 SKIP_WHITESPACE ();
4494 p = input_line_pointer;
4495 c = get_symbol_name (&p);
4496
4497 name = xstrdup (p);
4498 restore_line_pointer (c);
4499
4500 /* 2nd: get register number. */
4501 SKIP_WHITESPACE ();
4502
4503 if (*input_line_pointer != ',')
4504 {
4505 as_bad (_("expected comma after register name"));
4506 ignore_rest_of_line ();
4507 free (name);
4508 return;
4509 }
4510 input_line_pointer++;
4511 number = get_absolute_expression ();
4512
4513 if (number < 0)
4514 {
4515 as_bad (_("negative operand number %d"), number);
4516 ignore_rest_of_line ();
4517 free (name);
4518 return;
4519 }
4520
4521 if (isReg_p)
4522 {
4523 /* 3rd: get register mode. */
4524 SKIP_WHITESPACE ();
4525
4526 if (*input_line_pointer != ',')
4527 {
4528 as_bad (_("expected comma after register number"));
4529 ignore_rest_of_line ();
4530 free (name);
4531 return;
4532 }
4533
4534 input_line_pointer++;
4535 mode = input_line_pointer;
4536
4537 if (!strncmp (mode, "r|w", 3))
4538 {
4539 imode = 0;
4540 input_line_pointer += 3;
4541 }
4542 else if (!strncmp (mode, "r", 1))
4543 {
4544 imode = ARC_REGISTER_READONLY;
4545 input_line_pointer += 1;
4546 }
4547 else if (strncmp (mode, "w", 1))
4548 {
4549 as_bad (_("invalid mode"));
4550 ignore_rest_of_line ();
4551 free (name);
4552 return;
4553 }
4554 else
4555 {
4556 imode = ARC_REGISTER_WRITEONLY;
4557 input_line_pointer += 1;
4558 }
4559 }
4560
4561 if (isCore_p)
4562 {
4563 /* 4th: get core register shortcut. */
4564 SKIP_WHITESPACE ();
4565 if (*input_line_pointer != ',')
4566 {
4567 as_bad (_("expected comma after register mode"));
4568 ignore_rest_of_line ();
4569 free (name);
4570 return;
4571 }
4572
4573 input_line_pointer++;
4574
4575 if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
4576 {
4577 imode |= ARC_REGISTER_NOSHORT_CUT;
4578 input_line_pointer += 15;
4579 }
4580 else if (strncmp (input_line_pointer, "can_shortcut", 12))
4581 {
4582 as_bad (_("shortcut designator invalid"));
4583 ignore_rest_of_line ();
4584 free (name);
4585 return;
4586 }
4587 else
4588 {
4589 input_line_pointer += 12;
4590 }
4591 }
4592 demand_empty_rest_of_line ();
4593
4594 ereg->name = name;
4595 ereg->number = number;
4596 ereg->imode = imode;
4597 }
4598
4599 /* Create an extension register/condition description in the arc
4600 extension section of the output file.
4601
4602 The structure for an instruction is like this:
4603 [0]: Length of the record.
4604 [1]: Type of the record.
4605
4606 For core regs and condition codes:
4607 [2]: Value.
4608 [3]+ Name.
4609
4610 For auxilirary registers:
4611 [2..5]: Value.
4612 [6]+ Name
4613
4614 The sequence is terminated by an empty entry. */
4615
4616 static void
4617 create_extcore_section (extRegister_t *ereg, int opertype)
4618 {
4619 segT old_sec = now_seg;
4620 int old_subsec = now_subseg;
4621 char *p;
4622 int name_len = strlen (ereg->name);
4623
4624 arc_set_ext_seg ();
4625
4626 switch (opertype)
4627 {
4628 case EXT_COND_CODE:
4629 case EXT_CORE_REGISTER:
4630 p = frag_more (1);
4631 *p = 3 + name_len + 1;
4632 p = frag_more (1);
4633 *p = opertype;
4634 p = frag_more (1);
4635 *p = ereg->number;
4636 break;
4637 case EXT_AUX_REGISTER:
4638 p = frag_more (1);
4639 *p = 6 + name_len + 1;
4640 p = frag_more (1);
4641 *p = EXT_AUX_REGISTER;
4642 p = frag_more (1);
4643 *p = (ereg->number >> 24) & 0xff;
4644 p = frag_more (1);
4645 *p = (ereg->number >> 16) & 0xff;
4646 p = frag_more (1);
4647 *p = (ereg->number >> 8) & 0xff;
4648 p = frag_more (1);
4649 *p = (ereg->number) & 0xff;
4650 break;
4651 default:
4652 break;
4653 }
4654
4655 p = frag_more (name_len + 1);
4656 strcpy (p, ereg->name);
4657
4658 subseg_set (old_sec, old_subsec);
4659 }
4660
4661 /* Handler .extCoreRegister pseudo-op. */
4662
4663 static void
4664 arc_extcorereg (int opertype)
4665 {
4666 extRegister_t ereg;
4667 struct arc_aux_reg *auxr;
4668 const char *retval;
4669 struct arc_flag_operand *ccode;
4670
4671 memset (&ereg, 0, sizeof (ereg));
4672 tokenize_extregister (&ereg, opertype);
4673
4674 switch (opertype)
4675 {
4676 case EXT_CORE_REGISTER:
4677 /* Core register. */
4678 if (ereg.number > 60)
4679 as_bad (_("core register %s value (%d) too large"), ereg.name,
4680 ereg.number);
4681 declare_register (ereg.name, ereg.number);
4682 break;
4683 case EXT_AUX_REGISTER:
4684 /* Auxiliary register. */
4685 auxr = XNEW (struct arc_aux_reg);
4686 auxr->name = ereg.name;
4687 auxr->cpu = selected_cpu.flags;
4688 auxr->subclass = NONE;
4689 auxr->address = ereg.number;
4690 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
4691 if (retval)
4692 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4693 auxr->name, retval);
4694 break;
4695 case EXT_COND_CODE:
4696 /* Condition code. */
4697 if (ereg.number > 31)
4698 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4699 ereg.number);
4700 ext_condcode.size ++;
4701 ext_condcode.arc_ext_condcode =
4702 XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode,
4703 ext_condcode.size + 1);
4704 if (ext_condcode.arc_ext_condcode == NULL)
4705 as_fatal (_("Virtual memory exhausted"));
4706
4707 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4708 ccode->name = ereg.name;
4709 ccode->code = ereg.number;
4710 ccode->bits = 5;
4711 ccode->shift = 0;
4712 ccode->favail = 0; /* not used. */
4713 ccode++;
4714 memset (ccode, 0, sizeof (struct arc_flag_operand));
4715 break;
4716 default:
4717 as_bad (_("Unknown extension"));
4718 break;
4719 }
4720 create_extcore_section (&ereg, opertype);
4721 }
4722
4723 /* Local variables:
4724 eval: (c-set-style "gnu")
4725 indent-tabs-mode: t
4726 End: */