1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
49 (SUB_OPCODE (x) == 0x28))
51 /* Equal to MAX_PRECISION in atof-ieee.c. */
52 #define MAX_LITTLENUMS 6
54 /* Enum used to enumerate the relaxable ins operands. */
59 REGISTER_S
, /* Register for short instruction(s). */
60 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
61 REGISTER_DUP
, /* Duplication of previous operand of type register. */
95 #define regno(x) ((x) & 0x3F)
96 #define is_ir_num(x) (((x) & ~0x3F) == 0)
97 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
98 #define is_spfp_p(op) (((sc) == SPX))
99 #define is_dpfp_p(op) (((sc) == DPX))
100 #define is_fpuda_p(op) (((sc) == DPA))
101 #define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
102 #define is_kernel_insn_p(op) (((op)->class == KERNEL))
104 /* Generic assembler global variables which must be defined by all
107 /* Characters which always start a comment. */
108 const char comment_chars
[] = "#;";
110 /* Characters which start a comment at the beginning of a line. */
111 const char line_comment_chars
[] = "#";
113 /* Characters which may be used to separate multiple commands on a
115 const char line_separator_chars
[] = "`";
117 /* Characters which are used to indicate an exponent in a floating
119 const char EXP_CHARS
[] = "eE";
121 /* Chars that mean this number is a floating point constant
122 As in 0f12.456 or 0d1.2345e12. */
123 const char FLT_CHARS
[] = "rRsSfFdD";
126 extern int target_big_endian
;
127 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
128 static int byte_order
= DEFAULT_BYTE_ORDER
;
130 /* Arc extension section. */
131 static segT arcext_section
;
133 /* By default relaxation is disabled. */
134 static int relaxation_state
= 0;
136 extern int arc_get_mach (char *);
138 /* Forward declarations. */
139 static void arc_lcomm (int);
140 static void arc_option (int);
141 static void arc_extra_reloc (int);
142 static void arc_extinsn (int);
143 static void arc_extcorereg (int);
145 const pseudo_typeS md_pseudo_table
[] =
147 /* Make sure that .word is 32 bits. */
150 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
151 { "lcomm", arc_lcomm
, 0 },
152 { "lcommon", arc_lcomm
, 0 },
153 { "cpu", arc_option
, 0 },
155 { "extinstruction", arc_extinsn
, 0 },
156 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
157 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
158 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
160 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
161 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
166 const char *md_shortopts
= "";
170 OPTION_EB
= OPTION_MD_BASE
,
183 /* The following options are deprecated and provided here only for
184 compatibility reasons. */
210 struct option md_longopts
[] =
212 { "EB", no_argument
, NULL
, OPTION_EB
},
213 { "EL", no_argument
, NULL
, OPTION_EL
},
214 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
215 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
216 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
217 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
218 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
219 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
220 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
221 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
222 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
223 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
225 /* The following options are deprecated and provided here only for
226 compatibility reasons. */
227 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
228 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
229 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
230 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
231 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
232 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
233 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
234 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
235 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
236 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
237 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
238 { "mea", no_argument
, NULL
, OPTION_EA
},
239 { "mEA", no_argument
, NULL
, OPTION_EA
},
240 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
241 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
242 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
243 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
244 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
245 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
246 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
247 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
248 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
249 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
250 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
251 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
252 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
253 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
254 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
255 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
256 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
257 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
258 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
259 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
260 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
261 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
262 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
263 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
264 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
265 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
267 { NULL
, no_argument
, NULL
, 0 }
270 size_t md_longopts_size
= sizeof (md_longopts
);
272 /* Local data and data types. */
274 /* Used since new relocation types are introduced in this
275 file (DUMMY_RELOC_LITUSE_*). */
276 typedef int extended_bfd_reloc_code_real_type
;
282 extended_bfd_reloc_code_real_type reloc
;
284 /* index into arc_operands. */
285 unsigned int opindex
;
287 /* PC-relative, used by internals fixups. */
290 /* TRUE if this fixup is for LIMM operand. */
298 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
300 bfd_boolean short_insn
; /* Boolean value: TRUE if current insn is
302 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
304 bfd_boolean relax
; /* Boolean value: TRUE if needs
308 /* Structure to hold any last two instructions. */
309 static struct arc_last_insn
311 /* Saved instruction opcode. */
312 const struct arc_opcode
*opcode
;
314 /* Boolean value: TRUE if current insn is short. */
315 bfd_boolean has_limm
;
317 /* Boolean value: TRUE if current insn has delay slot. */
318 bfd_boolean has_delay_slot
;
321 /* Extension instruction suffix classes. */
329 static const attributes_t suffixclass
[] =
331 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
332 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
333 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
336 /* Extension instruction syntax classes. */
337 static const attributes_t syntaxclass
[] =
339 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
340 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
341 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
342 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
345 /* Extension instruction syntax classes modifiers. */
346 static const attributes_t syntaxclassmod
[] =
348 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
349 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
352 /* Extension register type. */
360 /* A structure to hold the additional conditional codes. */
363 struct arc_flag_operand
*arc_ext_condcode
;
365 } ext_condcode
= { NULL
, 0 };
367 /* Structure to hold an entry in ARC_OPCODE_HASH. */
368 struct arc_opcode_hash_entry
370 /* The number of pointers in the OPCODE list. */
373 /* Points to a list of opcode pointers. */
374 const struct arc_opcode
**opcode
;
377 /* Structure used for iterating through an arc_opcode_hash_entry. */
378 struct arc_opcode_hash_entry_iterator
380 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
383 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
384 returned by this iterator. */
385 const struct arc_opcode
*opcode
;
388 /* Forward declaration. */
389 static void assemble_insn
390 (const struct arc_opcode
*, const expressionS
*, int,
391 const struct arc_flags
*, int, struct arc_insn
*);
393 /* The cpu for which we are generating code. */
394 static unsigned arc_target
;
395 static const char *arc_target_name
;
396 static unsigned arc_features
;
398 /* The default architecture. */
399 static int arc_mach_type
;
401 /* TRUE if the cpu type has been explicitly specified. */
402 static bfd_boolean mach_type_specified_p
= FALSE
;
404 /* The hash table of instruction opcodes. */
405 static struct hash_control
*arc_opcode_hash
;
407 /* The hash table of register symbols. */
408 static struct hash_control
*arc_reg_hash
;
410 /* The hash table of aux register symbols. */
411 static struct hash_control
*arc_aux_hash
;
413 /* A table of CPU names and opcode sets. */
414 static const struct cpu_type
424 { "arc600", ARC_OPCODE_ARC600
, bfd_mach_arc_arc600
,
425 E_ARC_MACH_ARC600
, 0x00},
426 { "arc700", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
427 E_ARC_MACH_ARC700
, 0x00},
428 { "nps400", ARC_OPCODE_ARC700
| ARC_OPCODE_NPS400
, bfd_mach_arc_nps400
,
429 E_ARC_MACH_NPS400
, 0x00},
430 { "arcem", ARC_OPCODE_ARCv2EM
, bfd_mach_arc_arcv2
,
431 EF_ARC_CPU_ARCV2EM
, ARC_CD
},
432 { "archs", ARC_OPCODE_ARCv2HS
, bfd_mach_arc_arcv2
,
433 EF_ARC_CPU_ARCV2HS
, ARC_CD
},
437 /* Used by the arc_reloc_op table. Order is important. */
438 #define O_gotoff O_md1 /* @gotoff relocation. */
439 #define O_gotpc O_md2 /* @gotpc relocation. */
440 #define O_plt O_md3 /* @plt relocation. */
441 #define O_sda O_md4 /* @sda relocation. */
442 #define O_pcl O_md5 /* @pcl relocation. */
443 #define O_tlsgd O_md6 /* @tlsgd relocation. */
444 #define O_tlsie O_md7 /* @tlsie relocation. */
445 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
446 #define O_tpoff O_md9 /* @tpoff relocation. */
447 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
448 #define O_dtpoff O_md11 /* @dtpoff relocation. */
449 #define O_last O_dtpoff
451 /* Used to define a bracket as operand in tokens. */
452 #define O_bracket O_md32
454 /* Dummy relocation, to be sorted out. */
455 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
457 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
459 /* A table to map the spelling of a relocation operand into an appropriate
460 bfd_reloc_code_real_type type. The table is assumed to be ordered such
461 that op-O_literal indexes into it. */
462 #define ARC_RELOC_TABLE(op) \
463 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
465 : (int) (op) - (int) O_gotoff) ])
467 #define DEF(NAME, RELOC, REQ) \
468 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
470 static const struct arc_reloc_op_tag
472 /* String to lookup. */
474 /* Size of the string. */
476 /* Which operator to use. */
478 extended_bfd_reloc_code_real_type reloc
;
479 /* Allows complex relocation expression like identifier@reloc +
481 unsigned int complex_expr
: 1;
485 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
486 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
487 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
488 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
489 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
490 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
491 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
492 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
493 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
494 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
495 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 0),
498 static const int arc_num_reloc_op
499 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
501 /* Structure for relaxable instruction that have to be swapped with a
502 smaller alternative instruction. */
503 struct arc_relaxable_ins
505 /* Mnemonic that should be checked. */
506 const char *mnemonic_r
;
508 /* Operands that should be checked.
509 Indexes of operands from operand array. */
510 enum rlx_operand_type operands
[6];
512 /* Flags that should be checked. */
513 unsigned flag_classes
[5];
515 /* Mnemonic (smaller) alternative to be used later for relaxation. */
516 const char *mnemonic_alt
;
518 /* Index of operand that generic relaxation has to check. */
521 /* Base subtype index used. */
522 enum arc_rlx_types subtype
;
525 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
526 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
527 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
531 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
532 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
533 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
538 /* ARC relaxation table. */
539 const relax_typeS md_relax_table
[] =
546 RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL
),
547 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
551 RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B
),
552 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
557 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6
),
558 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM
),
559 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
561 /* LD_S a, [b, u7] ->
562 LD<zz><.x><.aa><.di> a, [b, s9] ->
563 LD<zz><.x><.aa><.di> a, [b, limm] */
564 RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9
),
565 RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM
),
566 RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE
),
571 RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12
),
572 RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM
),
573 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
577 SUB<.f> a, b, limm. */
578 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6
),
579 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM
),
580 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
582 /* MPY<.f> a, b, u6 ->
583 MPY<.f> a, b, limm. */
584 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM
),
585 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
587 /* MOV<.f><.cc> b, u6 ->
588 MOV<.f><.cc> b, limm. */
589 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM
),
590 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
592 /* ADD<.f><.cc> b, b, u6 ->
593 ADD<.f><.cc> b, b, limm. */
594 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM
),
595 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
598 /* Order of this table's entries matters! */
599 const struct arc_relaxable_ins arc_relaxable_insns
[] =
601 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
602 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
603 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
604 2, ARC_RLX_ADD_RRU6
},
605 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
607 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
609 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
610 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
611 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
612 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
613 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
614 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
615 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
616 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
618 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
620 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
624 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
626 /* Flags to set in the elf header. */
627 static flagword arc_eflag
= 0x00;
629 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
630 symbolS
* GOT_symbol
= 0;
632 /* Set to TRUE when we assemble instructions. */
633 static bfd_boolean assembling_insn
= FALSE
;
635 /* Functions implementation. */
637 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
638 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
639 are no matching entries in ARC_OPCODE_HASH. */
641 static const struct arc_opcode_hash_entry
*
642 arc_find_opcode (const char *name
)
644 const struct arc_opcode_hash_entry
*entry
;
646 entry
= hash_find (arc_opcode_hash
, name
);
650 /* Initialise the iterator ITER. */
653 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
659 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
660 calls to this function. Return NULL when all ARC_OPCODE entries have
663 static const struct arc_opcode
*
664 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
665 struct arc_opcode_hash_entry_iterator
*iter
)
667 if (iter
->opcode
== NULL
&& iter
->index
== 0)
669 gas_assert (entry
->count
> 0);
670 iter
->opcode
= entry
->opcode
[iter
->index
];
672 else if (iter
->opcode
!= NULL
)
674 const char *old_name
= iter
->opcode
->name
;
677 if (iter
->opcode
->name
678 && (strcmp (old_name
, iter
->opcode
->name
) != 0))
681 if (iter
->index
== entry
->count
)
684 iter
->opcode
= entry
->opcode
[iter
->index
];
691 /* Insert an opcode into opcode hash structure. */
694 arc_insert_opcode (const struct arc_opcode
*opcode
)
696 const char *name
, *retval
;
697 struct arc_opcode_hash_entry
*entry
;
700 entry
= hash_find (arc_opcode_hash
, name
);
703 entry
= XNEW (struct arc_opcode_hash_entry
);
705 entry
->opcode
= NULL
;
707 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
709 as_fatal (_("internal error: can't hash opcode '%s': %s"),
713 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
716 if (entry
->opcode
== NULL
)
717 as_fatal (_("Virtual memory exhausted"));
719 entry
->opcode
[entry
->count
] = opcode
;
724 /* Like md_number_to_chars but used for limms. The 4-byte limm value,
725 is encoded as 'middle-endian' for a little-endian target. FIXME!
726 this function is used for regular 4 byte instructions as well. */
729 md_number_to_chars_midend (char *buf
, valueT val
, int n
)
733 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
734 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
738 md_number_to_chars (buf
, val
, n
);
742 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
743 the relevant static global variables. */
746 arc_select_cpu (const char *arg
)
751 for (i
= 0; cpu_types
[i
].name
; ++i
)
753 if (!strcasecmp (cpu_types
[i
].name
, arg
))
755 arc_target
= cpu_types
[i
].flags
;
756 arc_target_name
= cpu_types
[i
].name
;
757 arc_features
= cpu_types
[i
].features
;
758 arc_mach_type
= cpu_types
[i
].mach
;
759 cpu_flags
= cpu_types
[i
].eflags
;
764 if (!cpu_types
[i
].name
)
765 as_fatal (_("unknown architecture: %s\n"), arg
);
766 gas_assert (cpu_flags
!= 0);
767 arc_eflag
= (arc_eflag
& ~EF_ARC_MACH_MSK
) | cpu_flags
;
770 /* Here ends all the ARCompact extension instruction assembling
774 arc_extra_reloc (int r_type
)
777 symbolS
*sym
, *lab
= NULL
;
779 if (*input_line_pointer
== '@')
780 input_line_pointer
++;
781 c
= get_symbol_name (&sym_name
);
782 sym
= symbol_find_or_make (sym_name
);
783 restore_line_pointer (c
);
784 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
786 ++input_line_pointer
;
788 c
= get_symbol_name (&lab_name
);
789 lab
= symbol_find_or_make (lab_name
);
790 restore_line_pointer (c
);
793 /* These relocations exist as a mechanism for the compiler to tell the
794 linker how to patch the code if the tls model is optimised. However,
795 the relocation itself does not require any space within the assembler
796 fragment, and so we pass a size of 0.
798 The lines that generate these relocations look like this:
800 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
802 The '.tls_gd_ld @.tdata' is processed first and generates the
803 additional relocation, while the 'bl __tls_get_addr@plt' is processed
804 second and generates the additional branch.
806 It is possible that the additional relocation generated by the
807 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
808 while the 'bl __tls_get_addr@plt' will be generated as the first thing
809 in the next fragment. This will be fine; both relocations will still
810 appear to be at the same address in the generated object file.
811 However, this only works as the additional relocation is generated
812 with size of 0 bytes. */
814 = fix_new (frag_now
, /* Which frag? */
815 frag_now_fix (), /* Where in that frag? */
816 0, /* size: 1, 2, or 4 usually. */
817 sym
, /* X_add_symbol. */
818 0, /* X_add_number. */
819 FALSE
, /* TRUE if PC-relative relocation. */
820 r_type
/* Relocation type. */);
821 fixP
->fx_subsy
= lab
;
825 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
826 symbolS
*symbolP
, addressT size
)
831 if (*input_line_pointer
== ',')
833 align
= parse_align (1);
835 if (align
== (addressT
) -1)
850 bss_alloc (symbolP
, size
, align
);
851 S_CLEAR_EXTERNAL (symbolP
);
857 arc_lcomm (int ignore
)
859 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
862 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
865 /* Select the cpu we're assembling for. */
868 arc_option (int ignore ATTRIBUTE_UNUSED
)
874 c
= get_symbol_name (&cpu
);
875 mach
= arc_get_mach (cpu
);
880 if (!mach_type_specified_p
)
882 if ((!strcmp ("ARC600", cpu
))
883 || (!strcmp ("ARC601", cpu
))
884 || (!strcmp ("A6", cpu
)))
886 md_parse_option (OPTION_MCPU
, "arc600");
888 else if ((!strcmp ("ARC700", cpu
))
889 || (!strcmp ("A7", cpu
)))
891 md_parse_option (OPTION_MCPU
, "arc700");
893 else if (!strcmp ("EM", cpu
))
895 md_parse_option (OPTION_MCPU
, "arcem");
897 else if (!strcmp ("HS", cpu
))
899 md_parse_option (OPTION_MCPU
, "archs");
901 else if (!strcmp ("NPS400", cpu
))
903 md_parse_option (OPTION_MCPU
, "nps400");
906 as_fatal (_("could not find the architecture"));
908 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, mach
))
909 as_fatal (_("could not set architecture and machine"));
911 /* Set elf header flags. */
912 bfd_set_private_flags (stdoutput
, arc_eflag
);
915 if (arc_mach_type
!= mach
)
916 as_warn (_("Command-line value overrides \".cpu\" directive"));
918 restore_line_pointer (c
);
919 demand_empty_rest_of_line ();
923 restore_line_pointer (c
);
924 as_bad (_("invalid identifier for \".cpu\""));
925 ignore_rest_of_line ();
928 /* Smartly print an expression. */
931 debug_exp (expressionS
*t
)
933 const char *name ATTRIBUTE_UNUSED
;
934 const char *namemd ATTRIBUTE_UNUSED
;
936 pr_debug ("debug_exp: ");
940 default: name
= "unknown"; break;
941 case O_illegal
: name
= "O_illegal"; break;
942 case O_absent
: name
= "O_absent"; break;
943 case O_constant
: name
= "O_constant"; break;
944 case O_symbol
: name
= "O_symbol"; break;
945 case O_symbol_rva
: name
= "O_symbol_rva"; break;
946 case O_register
: name
= "O_register"; break;
947 case O_big
: name
= "O_big"; break;
948 case O_uminus
: name
= "O_uminus"; break;
949 case O_bit_not
: name
= "O_bit_not"; break;
950 case O_logical_not
: name
= "O_logical_not"; break;
951 case O_multiply
: name
= "O_multiply"; break;
952 case O_divide
: name
= "O_divide"; break;
953 case O_modulus
: name
= "O_modulus"; break;
954 case O_left_shift
: name
= "O_left_shift"; break;
955 case O_right_shift
: name
= "O_right_shift"; break;
956 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
957 case O_bit_or_not
: name
= "O_bit_or_not"; break;
958 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
959 case O_bit_and
: name
= "O_bit_and"; break;
960 case O_add
: name
= "O_add"; break;
961 case O_subtract
: name
= "O_subtract"; break;
962 case O_eq
: name
= "O_eq"; break;
963 case O_ne
: name
= "O_ne"; break;
964 case O_lt
: name
= "O_lt"; break;
965 case O_le
: name
= "O_le"; break;
966 case O_ge
: name
= "O_ge"; break;
967 case O_gt
: name
= "O_gt"; break;
968 case O_logical_and
: name
= "O_logical_and"; break;
969 case O_logical_or
: name
= "O_logical_or"; break;
970 case O_index
: name
= "O_index"; break;
971 case O_bracket
: name
= "O_bracket"; break;
976 default: namemd
= "unknown"; break;
977 case O_gotoff
: namemd
= "O_gotoff"; break;
978 case O_gotpc
: namemd
= "O_gotpc"; break;
979 case O_plt
: namemd
= "O_plt"; break;
980 case O_sda
: namemd
= "O_sda"; break;
981 case O_pcl
: namemd
= "O_pcl"; break;
982 case O_tlsgd
: namemd
= "O_tlsgd"; break;
983 case O_tlsie
: namemd
= "O_tlsie"; break;
984 case O_tpoff9
: namemd
= "O_tpoff9"; break;
985 case O_tpoff
: namemd
= "O_tpoff"; break;
986 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
987 case O_dtpoff
: namemd
= "O_dtpoff"; break;
990 pr_debug ("%s (%s, %s, %d, %s)", name
,
991 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
992 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
993 (int) t
->X_add_number
,
994 (t
->X_md
) ? namemd
: "--");
999 /* Parse the arguments to an opcode. */
1002 tokenize_arguments (char *str
,
1006 char *old_input_line_pointer
;
1007 bfd_boolean saw_comma
= FALSE
;
1008 bfd_boolean saw_arg
= FALSE
;
1013 const struct arc_reloc_op_tag
*r
;
1015 char *reloc_name
, c
;
1017 memset (tok
, 0, sizeof (*tok
) * ntok
);
1019 /* Save and restore input_line_pointer around this function. */
1020 old_input_line_pointer
= input_line_pointer
;
1021 input_line_pointer
= str
;
1023 while (*input_line_pointer
)
1026 switch (*input_line_pointer
)
1032 input_line_pointer
++;
1033 if (saw_comma
|| !saw_arg
)
1040 ++input_line_pointer
;
1042 if (!saw_arg
|| num_args
== ntok
)
1044 tok
->X_op
= O_bracket
;
1051 input_line_pointer
++;
1052 if (brk_lvl
|| num_args
== ntok
)
1055 tok
->X_op
= O_bracket
;
1061 /* We have labels, function names and relocations, all
1062 starting with @ symbol. Sort them out. */
1063 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1067 tok
->X_op
= O_symbol
;
1068 tok
->X_md
= O_absent
;
1070 if (*input_line_pointer
!= '@')
1071 goto normalsymbol
; /* This is not a relocation. */
1075 /* A relocation opernad has the following form
1076 @identifier@relocation_type. The identifier is already
1078 if (tok
->X_op
!= O_symbol
)
1080 as_bad (_("No valid label relocation operand"));
1084 /* Parse @relocation_type. */
1085 input_line_pointer
++;
1086 c
= get_symbol_name (&reloc_name
);
1087 len
= input_line_pointer
- reloc_name
;
1090 as_bad (_("No relocation operand"));
1094 /* Go through known relocation and try to find a match. */
1095 r
= &arc_reloc_op
[0];
1096 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1097 if (len
== r
->length
1098 && memcmp (reloc_name
, r
->name
, len
) == 0)
1102 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1106 *input_line_pointer
= c
;
1107 SKIP_WHITESPACE_AFTER_NAME ();
1108 /* Extra check for TLS: base. */
1109 if (*input_line_pointer
== '@')
1112 if (tok
->X_op_symbol
!= NULL
1113 || tok
->X_op
!= O_symbol
)
1115 as_bad (_("Unable to parse TLS base: %s"),
1116 input_line_pointer
);
1119 input_line_pointer
++;
1121 c
= get_symbol_name (&sym_name
);
1122 base
= symbol_find_or_make (sym_name
);
1123 tok
->X_op
= O_subtract
;
1124 tok
->X_op_symbol
= base
;
1125 restore_line_pointer (c
);
1126 tmpE
.X_add_number
= 0;
1128 else if ((*input_line_pointer
!= '+')
1129 && (*input_line_pointer
!= '-'))
1131 tmpE
.X_add_number
= 0;
1135 /* Parse the constant of a complex relocation expression
1136 like @identifier@reloc +/- const. */
1137 if (! r
->complex_expr
)
1139 as_bad (_("@%s is not a complex relocation."), r
->name
);
1143 if (tmpE
.X_op
!= O_constant
)
1145 as_bad (_("Bad expression: @%s + %s."),
1146 r
->name
, input_line_pointer
);
1152 tok
->X_add_number
= tmpE
.X_add_number
;
1163 /* Can be a register. */
1164 ++input_line_pointer
;
1168 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1171 tok
->X_op
= O_absent
;
1172 tok
->X_md
= O_absent
;
1175 /* Legacy: There are cases when we have
1176 identifier@relocation_type, if it is the case parse the
1177 relocation type as well. */
1178 if (*input_line_pointer
== '@')
1184 if (tok
->X_op
== O_illegal
1185 || tok
->X_op
== O_absent
1186 || num_args
== ntok
)
1198 if (saw_comma
|| brk_lvl
)
1200 input_line_pointer
= old_input_line_pointer
;
1206 as_bad (_("Brackets in operand field incorrect"));
1208 as_bad (_("extra comma"));
1210 as_bad (_("missing argument"));
1212 as_bad (_("missing comma or colon"));
1213 input_line_pointer
= old_input_line_pointer
;
1217 /* Parse the flags to a structure. */
1220 tokenize_flags (const char *str
,
1221 struct arc_flags flags
[],
1224 char *old_input_line_pointer
;
1225 bfd_boolean saw_flg
= FALSE
;
1226 bfd_boolean saw_dot
= FALSE
;
1230 memset (flags
, 0, sizeof (*flags
) * nflg
);
1232 /* Save and restore input_line_pointer around this function. */
1233 old_input_line_pointer
= input_line_pointer
;
1234 input_line_pointer
= (char *) str
;
1236 while (*input_line_pointer
)
1238 switch (*input_line_pointer
)
1245 input_line_pointer
++;
1253 if (saw_flg
&& !saw_dot
)
1256 if (num_flags
>= nflg
)
1259 flgnamelen
= strspn (input_line_pointer
,
1260 "abcdefghijklmnopqrstuvwxyz0123456789");
1261 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1264 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1266 input_line_pointer
+= flgnamelen
;
1276 input_line_pointer
= old_input_line_pointer
;
1281 as_bad (_("extra dot"));
1283 as_bad (_("unrecognized flag"));
1285 as_bad (_("failed to parse flags"));
1286 input_line_pointer
= old_input_line_pointer
;
1290 /* Apply the fixups in order. */
1293 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1297 for (i
= 0; i
< insn
->nfixups
; i
++)
1299 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1300 int size
, pcrel
, offset
= 0;
1302 /* FIXME! the reloc size is wrong in the BFD file.
1303 When it is fixed please delete me. */
1304 size
= (insn
->short_insn
&& !fixup
->islong
) ? 2 : 4;
1307 offset
= (insn
->short_insn
) ? 2 : 4;
1309 /* Some fixups are only used internally, thus no howto. */
1310 if ((int) fixup
->reloc
== 0)
1311 as_fatal (_("Unhandled reloc type"));
1313 if ((int) fixup
->reloc
< 0)
1315 /* FIXME! the reloc size is wrong in the BFD file.
1316 When it is fixed please enable me.
1317 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1318 pcrel
= fixup
->pcrel
;
1322 reloc_howto_type
*reloc_howto
=
1323 bfd_reloc_type_lookup (stdoutput
,
1324 (bfd_reloc_code_real_type
) fixup
->reloc
);
1325 gas_assert (reloc_howto
);
1327 /* FIXME! the reloc size is wrong in the BFD file.
1328 When it is fixed please enable me.
1329 size = bfd_get_reloc_size (reloc_howto); */
1330 pcrel
= reloc_howto
->pc_relative
;
1333 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1335 fragP
->fr_file
, fragP
->fr_line
,
1336 (fixup
->reloc
< 0) ? "Internal" :
1337 bfd_get_reloc_code_name (fixup
->reloc
),
1340 fix_new_exp (fragP
, fix
+ offset
,
1341 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1343 /* Check for ZOLs, and update symbol info if any. */
1344 if (LP_INSN (insn
->insn
))
1346 gas_assert (fixup
->exp
.X_add_symbol
);
1347 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1352 /* Actually output an instruction with its fixup. */
1355 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1359 pr_debug ("Emit insn : 0x%x\n", insn
->insn
);
1360 pr_debug ("\tShort : 0x%d\n", insn
->short_insn
);
1361 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1363 /* Write out the instruction. */
1364 if (insn
->short_insn
)
1370 md_number_to_chars (f
, insn
->insn
, 2);
1371 md_number_to_chars_midend (f
+ 2, insn
->limm
, 4);
1372 dwarf2_emit_insn (6);
1378 md_number_to_chars (f
, insn
->insn
, 2);
1379 dwarf2_emit_insn (2);
1388 md_number_to_chars_midend (f
, insn
->insn
, 4);
1389 md_number_to_chars_midend (f
+ 4, insn
->limm
, 4);
1390 dwarf2_emit_insn (8);
1396 md_number_to_chars_midend (f
, insn
->insn
, 4);
1397 dwarf2_emit_insn (4);
1402 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1406 emit_insn1 (struct arc_insn
*insn
)
1408 /* How frag_var's args are currently configured:
1409 - rs_machine_dependent, to dictate it's a relaxation frag.
1410 - FRAG_MAX_GROWTH, maximum size of instruction
1411 - 0, variable size that might grow...unused by generic relaxation.
1412 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1413 - s, opand expression.
1414 - 0, offset but it's unused.
1415 - 0, opcode but it's unused. */
1416 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1417 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1419 if (frag_room () < FRAG_MAX_GROWTH
)
1421 /* Handle differently when frag literal memory is exhausted.
1422 This is used because when there's not enough memory left in
1423 the current frag, a new frag is created and the information
1424 we put into frag_now->tc_frag_data is disregarded. */
1426 struct arc_relax_type relax_info_copy
;
1427 relax_substateT subtype
= frag_now
->fr_subtype
;
1429 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1430 sizeof (struct arc_relax_type
));
1432 frag_wane (frag_now
);
1433 frag_grow (FRAG_MAX_GROWTH
);
1435 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1436 sizeof (struct arc_relax_type
));
1438 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1442 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1443 frag_now
->fr_subtype
, s
, 0, 0);
1447 emit_insn (struct arc_insn
*insn
)
1452 emit_insn0 (insn
, NULL
, FALSE
);
1455 /* Check whether a symbol involves a register. */
1458 contains_register (symbolS
*sym
)
1462 expressionS
*ex
= symbol_get_value_expression (sym
);
1464 return ((O_register
== ex
->X_op
)
1465 && !contains_register (ex
->X_add_symbol
)
1466 && !contains_register (ex
->X_op_symbol
));
1472 /* Returns the register number within a symbol. */
1475 get_register (symbolS
*sym
)
1477 if (!contains_register (sym
))
1480 expressionS
*ex
= symbol_get_value_expression (sym
);
1481 return regno (ex
->X_add_number
);
1484 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1485 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1488 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1495 case BFD_RELOC_ARC_SDA_LDST
:
1496 case BFD_RELOC_ARC_SDA_LDST1
:
1497 case BFD_RELOC_ARC_SDA_LDST2
:
1498 case BFD_RELOC_ARC_SDA16_LD
:
1499 case BFD_RELOC_ARC_SDA16_LD1
:
1500 case BFD_RELOC_ARC_SDA16_LD2
:
1501 case BFD_RELOC_ARC_SDA16_ST2
:
1502 case BFD_RELOC_ARC_SDA32_ME
:
1509 /* Allocates a tok entry. */
1512 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1514 if (ntok
> MAX_INSN_ARGS
- 2)
1515 return 0; /* No space left. */
1518 return 0; /* Incorect args. */
1520 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1523 return 1; /* Success. */
1524 return allocate_tok (tok
, ntok
- 1, cidx
);
1527 /* Check if an particular ARC feature is enabled. */
1530 check_cpu_feature (insn_subclass_t sc
)
1532 if (!(arc_features
& ARC_CD
)
1533 && is_code_density_p (sc
))
1536 if (!(arc_features
& ARC_SPFP
)
1540 if (!(arc_features
& ARC_DPFP
)
1544 if (!(arc_features
& ARC_FPUDA
)
1551 /* Search forward through all variants of an opcode looking for a
1554 static const struct arc_opcode
*
1555 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1558 struct arc_flags
*first_pflag
,
1562 const struct arc_opcode
*opcode
;
1563 struct arc_opcode_hash_entry_iterator iter
;
1565 int got_cpu_match
= 0;
1566 expressionS bktok
[MAX_INSN_ARGS
];
1570 arc_opcode_hash_entry_iterator_init (&iter
);
1571 memset (&emptyE
, 0, sizeof (emptyE
));
1572 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1575 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1577 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1579 const unsigned char *opidx
;
1580 const unsigned char *flgidx
;
1581 int tokidx
= 0, lnflg
, i
;
1582 const expressionS
*t
= &emptyE
;
1584 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1585 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1587 /* Don't match opcodes that don't exist on this
1589 if (!(opcode
->cpu
& arc_target
))
1592 if (!check_cpu_feature (opcode
->subclass
))
1598 /* Check the operands. */
1599 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1601 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1603 /* Only take input from real operands. */
1604 if ((operand
->flags
& ARC_OPERAND_FAKE
)
1605 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
1608 /* When we expect input, make sure we have it. */
1612 /* Match operand type with expression type. */
1613 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1615 case ARC_OPERAND_IR
:
1616 /* Check to be a register. */
1617 if ((tok
[tokidx
].X_op
!= O_register
1618 || !is_ir_num (tok
[tokidx
].X_add_number
))
1619 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1622 /* If expect duplicate, make sure it is duplicate. */
1623 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1625 /* Check for duplicate. */
1626 if (t
->X_op
!= O_register
1627 || !is_ir_num (t
->X_add_number
)
1628 || (regno (t
->X_add_number
) !=
1629 regno (tok
[tokidx
].X_add_number
)))
1633 /* Special handling? */
1634 if (operand
->insert
)
1636 const char *errmsg
= NULL
;
1637 (*operand
->insert
)(0,
1638 regno (tok
[tokidx
].X_add_number
),
1642 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1644 /* Missing argument, create one. */
1645 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1648 tok
[tokidx
].X_op
= O_absent
;
1659 case ARC_OPERAND_BRAKET
:
1660 /* Check if bracket is also in opcode table as
1662 if (tok
[tokidx
].X_op
!= O_bracket
)
1666 case ARC_OPERAND_LIMM
:
1667 case ARC_OPERAND_SIGNED
:
1668 case ARC_OPERAND_UNSIGNED
:
1669 switch (tok
[tokidx
].X_op
)
1677 /* Got an (too) early bracket, check if it is an
1678 ignored operand. N.B. This procedure works only
1679 when bracket is the last operand! */
1680 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1682 /* Insert the missing operand. */
1683 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1686 tok
[tokidx
].X_op
= O_absent
;
1693 const struct arc_aux_reg
*auxr
;
1695 if (opcode
->class != AUXREG
)
1697 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1699 auxr
= hash_find (arc_aux_hash
, p
);
1702 /* We modify the token array here, safe in the
1703 knowledge, that if this was the wrong
1704 choice then the original contents will be
1705 restored from BKTOK. */
1706 tok
[tokidx
].X_op
= O_constant
;
1707 tok
[tokidx
].X_add_number
= auxr
->address
;
1708 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1711 if (tok
[tokidx
].X_op
!= O_constant
)
1716 /* Check the range. */
1717 if (operand
->bits
!= 32
1718 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1720 offsetT min
, max
, val
;
1721 val
= tok
[tokidx
].X_add_number
;
1723 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1725 max
= (1 << (operand
->bits
- 1)) - 1;
1726 min
= -(1 << (operand
->bits
- 1));
1730 max
= (1 << operand
->bits
) - 1;
1734 if (val
< min
|| val
> max
)
1737 /* Check alignmets. */
1738 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1742 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1746 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1748 if (operand
->insert
)
1750 const char *errmsg
= NULL
;
1751 (*operand
->insert
)(0,
1752 tok
[tokidx
].X_add_number
,
1763 /* Check if it is register range. */
1764 if ((tok
[tokidx
].X_add_number
== 0)
1765 && contains_register (tok
[tokidx
].X_add_symbol
)
1766 && contains_register (tok
[tokidx
].X_op_symbol
))
1770 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1772 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1773 if (operand
->insert
)
1775 const char *errmsg
= NULL
;
1776 (*operand
->insert
)(0,
1788 if (operand
->default_reloc
== 0)
1789 goto match_failed
; /* The operand needs relocation. */
1791 /* Relocs requiring long immediate. FIXME! make it
1792 generic and move it to a function. */
1793 switch (tok
[tokidx
].X_md
)
1802 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
1805 if (!generic_reloc_p (operand
->default_reloc
))
1812 /* If expect duplicate, make sure it is duplicate. */
1813 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1815 if (t
->X_op
== O_illegal
1816 || t
->X_op
== O_absent
1817 || t
->X_op
== O_register
1818 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
1825 /* Everything else should have been fake. */
1833 /* Setup ready for flag parsing. */
1835 for (i
= 0; i
< nflgs
; i
++)
1836 first_pflag
[i
].flgp
= NULL
;
1838 /* Check the flags. Iterate over the valid flag classes. */
1839 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1841 /* Get a valid flag class. */
1842 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1843 const unsigned *flgopridx
;
1845 struct arc_flags
*pflag
= NULL
;
1847 /* Check for extension conditional codes. */
1848 if (ext_condcode
.arc_ext_condcode
1849 && cl_flags
->class & F_CLASS_EXTEND
)
1851 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1854 pflag
= first_pflag
;
1855 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1857 if (!strcmp (pf
->name
, pflag
->name
))
1859 if (pflag
->flgp
!= NULL
)
1872 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1874 const struct arc_flag_operand
*flg_operand
;
1876 pflag
= first_pflag
;
1877 flg_operand
= &arc_flag_operands
[*flgopridx
];
1878 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1880 /* Match against the parsed flags. */
1881 if (!strcmp (flg_operand
->name
, pflag
->name
))
1883 if (pflag
->flgp
!= NULL
)
1886 pflag
->flgp
= (struct arc_flag_operand
*) flg_operand
;
1888 break; /* goto next flag class and parsed flag. */
1893 if ((cl_flags
->class & F_CLASS_REQUIRED
) && cl_matches
== 0)
1895 if ((cl_flags
->class & F_CLASS_OPTIONAL
) && cl_matches
> 1)
1898 /* Did I check all the parsed flags? */
1903 /* Possible match -- did we use all of our input? */
1913 /* Restore the original parameters. */
1914 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
1919 *pcpumatch
= got_cpu_match
;
1924 /* Swap operand tokens. */
1927 swap_operand (expressionS
*operand_array
,
1929 unsigned destination
)
1931 expressionS cpy_operand
;
1932 expressionS
*src_operand
;
1933 expressionS
*dst_operand
;
1936 if (source
== destination
)
1939 src_operand
= &operand_array
[source
];
1940 dst_operand
= &operand_array
[destination
];
1941 size
= sizeof (expressionS
);
1943 /* Make copy of operand to swap with and swap. */
1944 memcpy (&cpy_operand
, dst_operand
, size
);
1945 memcpy (dst_operand
, src_operand
, size
);
1946 memcpy (src_operand
, &cpy_operand
, size
);
1949 /* Check if *op matches *tok type.
1950 Returns FALSE if they don't match, TRUE if they match. */
1953 pseudo_operand_match (const expressionS
*tok
,
1954 const struct arc_operand_operation
*op
)
1956 offsetT min
, max
, val
;
1958 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
1964 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
1966 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
1968 val
= tok
->X_add_number
+ op
->count
;
1969 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
1971 max
= (1 << (operand_real
->bits
- 1)) - 1;
1972 min
= -(1 << (operand_real
->bits
- 1));
1976 max
= (1 << operand_real
->bits
) - 1;
1979 if (min
<= val
&& val
<= max
)
1985 /* Handle all symbols as long immediates or signed 9. */
1986 if (operand_real
->flags
& ARC_OPERAND_LIMM
||
1987 ((operand_real
->flags
& ARC_OPERAND_SIGNED
) && operand_real
->bits
== 9))
1992 if (operand_real
->flags
& ARC_OPERAND_IR
)
1997 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2008 /* Find pseudo instruction in array. */
2010 static const struct arc_pseudo_insn
*
2011 find_pseudo_insn (const char *opname
,
2013 const expressionS
*tok
)
2015 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2016 const struct arc_operand_operation
*op
;
2020 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2022 pseudo_insn
= &arc_pseudo_insns
[i
];
2023 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2025 op
= pseudo_insn
->operand
;
2026 for (j
= 0; j
< ntok
; ++j
)
2027 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2030 /* Found the right instruction. */
2038 /* Assumes the expressionS *tok is of sufficient size. */
2040 static const struct arc_opcode_hash_entry
*
2041 find_special_case_pseudo (const char *opname
,
2045 struct arc_flags
*pflags
)
2047 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2048 const struct arc_operand_operation
*operand_pseudo
;
2049 const struct arc_operand
*operand_real
;
2051 char construct_operand
[MAX_CONSTR_STR
];
2053 /* Find whether opname is in pseudo instruction array. */
2054 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2056 if (pseudo_insn
== NULL
)
2059 /* Handle flag, Limited to one flag at the moment. */
2060 if (pseudo_insn
->flag_r
!= NULL
)
2061 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2062 MAX_INSN_FLGS
- *nflgs
);
2064 /* Handle operand operations. */
2065 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2067 operand_pseudo
= &pseudo_insn
->operand
[i
];
2068 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2070 if (operand_real
->flags
& ARC_OPERAND_BRAKET
&&
2071 !operand_pseudo
->needs_insert
)
2074 /* Has to be inserted (i.e. this token does not exist yet). */
2075 if (operand_pseudo
->needs_insert
)
2077 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2079 tok
[i
].X_op
= O_bracket
;
2084 /* Check if operand is a register or constant and handle it
2086 if (operand_real
->flags
& ARC_OPERAND_IR
)
2087 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2088 operand_pseudo
->count
);
2090 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2091 operand_pseudo
->count
);
2093 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2097 else if (operand_pseudo
->count
)
2099 /* Operand number has to be adjusted accordingly (by operand
2101 switch (tok
[i
].X_op
)
2104 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2117 /* Swap operands if necessary. Only supports one swap at the
2119 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2121 operand_pseudo
= &pseudo_insn
->operand
[i
];
2123 if (operand_pseudo
->swap_operand_idx
== i
)
2126 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2128 /* Prevent a swap back later by breaking out. */
2132 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2135 static const struct arc_opcode_hash_entry
*
2136 find_special_case_flag (const char *opname
,
2138 struct arc_flags
*pflags
)
2142 unsigned flag_idx
, flag_arr_idx
;
2143 size_t flaglen
, oplen
;
2144 const struct arc_flag_special
*arc_flag_special_opcode
;
2145 const struct arc_opcode_hash_entry
*entry
;
2147 /* Search for special case instruction. */
2148 for (i
= 0; i
< arc_num_flag_special
; i
++)
2150 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2151 oplen
= strlen (arc_flag_special_opcode
->name
);
2153 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2156 /* Found a potential special case instruction, now test for
2158 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2160 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2162 break; /* End of array, nothing found. */
2164 flagnm
= arc_flag_operands
[flag_idx
].name
;
2165 flaglen
= strlen (flagnm
);
2166 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2168 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2170 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2172 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2173 pflags
[*nflgs
].name
[flaglen
] = '\0';
2182 /* Used to find special case opcode. */
2184 static const struct arc_opcode_hash_entry
*
2185 find_special_case (const char *opname
,
2187 struct arc_flags
*pflags
,
2191 const struct arc_opcode_hash_entry
*entry
;
2193 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2196 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2201 /* Given an opcode name, pre-tockenized set of argumenst and the
2202 opcode flags, take it all the way through emission. */
2205 assemble_tokens (const char *opname
,
2208 struct arc_flags
*pflags
,
2211 bfd_boolean found_something
= FALSE
;
2212 const struct arc_opcode_hash_entry
*entry
;
2215 /* Search opcodes. */
2216 entry
= arc_find_opcode (opname
);
2218 /* Couldn't find opcode conventional way, try special cases. */
2220 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2224 const struct arc_opcode
*opcode
;
2226 pr_debug ("%s:%d: assemble_tokens: %s\n",
2227 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2228 found_something
= TRUE
;
2229 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2233 struct arc_insn insn
;
2235 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2241 if (found_something
)
2244 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2246 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2250 as_bad (_("unknown opcode '%s'"), opname
);
2253 /* The public interface to the instruction assembler. */
2256 md_assemble (char *str
)
2259 expressionS tok
[MAX_INSN_ARGS
];
2262 struct arc_flags flags
[MAX_INSN_FLGS
];
2264 /* Split off the opcode. */
2265 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2266 opname
= xmemdup0 (str
, opnamelen
);
2268 /* Signalize we are assmbling the instructions. */
2269 assembling_insn
= TRUE
;
2271 /* Tokenize the flags. */
2272 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2274 as_bad (_("syntax error"));
2278 /* Scan up to the end of the mnemonic which must end in space or end
2281 for (; *str
!= '\0'; str
++)
2285 /* Tokenize the rest of the line. */
2286 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2288 as_bad (_("syntax error"));
2292 /* Finish it off. */
2293 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2294 assembling_insn
= FALSE
;
2297 /* Callback to insert a register into the hash table. */
2300 declare_register (const char *name
, int number
)
2303 symbolS
*regS
= symbol_create (name
, reg_section
,
2304 number
, &zero_address_frag
);
2306 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2308 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2312 /* Construct symbols for each of the general registers. */
2315 declare_register_set (void)
2318 for (i
= 0; i
< 64; ++i
)
2322 sprintf (name
, "r%d", i
);
2323 declare_register (name
, i
);
2324 if ((i
& 0x01) == 0)
2326 sprintf (name
, "r%dr%d", i
, i
+1);
2327 declare_register (name
, i
);
2332 /* Port-specific assembler initialization. This function is called
2333 once, at assembler startup time. */
2338 const struct arc_opcode
*opcode
= arc_opcodes
;
2340 if (!mach_type_specified_p
)
2341 arc_select_cpu ("arc700");
2343 /* The endianness can be chosen "at the factory". */
2344 target_big_endian
= byte_order
== BIG_ENDIAN
;
2346 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, arc_mach_type
))
2347 as_warn (_("could not set architecture and machine"));
2349 /* Set elf header flags. */
2350 bfd_set_private_flags (stdoutput
, arc_eflag
);
2352 /* Set up a hash table for the instructions. */
2353 arc_opcode_hash
= hash_new ();
2354 if (arc_opcode_hash
== NULL
)
2355 as_fatal (_("Virtual memory exhausted"));
2357 /* Initialize the hash table with the insns. */
2360 const char *name
= opcode
->name
;
2362 arc_insert_opcode (opcode
);
2364 while (++opcode
&& opcode
->name
2365 && (opcode
->name
== name
2366 || !strcmp (opcode
->name
, name
)))
2368 }while (opcode
->name
);
2370 /* Register declaration. */
2371 arc_reg_hash
= hash_new ();
2372 if (arc_reg_hash
== NULL
)
2373 as_fatal (_("Virtual memory exhausted"));
2375 declare_register_set ();
2376 declare_register ("gp", 26);
2377 declare_register ("fp", 27);
2378 declare_register ("sp", 28);
2379 declare_register ("ilink", 29);
2380 declare_register ("ilink1", 29);
2381 declare_register ("ilink2", 30);
2382 declare_register ("blink", 31);
2384 declare_register ("mlo", 57);
2385 declare_register ("mmid", 58);
2386 declare_register ("mhi", 59);
2388 declare_register ("acc1", 56);
2389 declare_register ("acc2", 57);
2391 declare_register ("lp_count", 60);
2392 declare_register ("pcl", 63);
2394 /* Initialize the last instructions. */
2395 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2397 /* Aux register declaration. */
2398 arc_aux_hash
= hash_new ();
2399 if (arc_aux_hash
== NULL
)
2400 as_fatal (_("Virtual memory exhausted"));
2402 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2404 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2408 if (!(auxr
->cpu
& arc_target
))
2411 if ((auxr
->subclass
!= NONE
)
2412 && !check_cpu_feature (auxr
->subclass
))
2415 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2417 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2418 auxr
->name
, retval
);
2422 /* Write a value out to the object file, using the appropriate
2426 md_number_to_chars (char *buf
,
2430 if (target_big_endian
)
2431 number_to_chars_bigendian (buf
, val
, n
);
2433 number_to_chars_littleendian (buf
, val
, n
);
2436 /* Round up a section size to the appropriate boundary. */
2439 md_section_align (segT segment
,
2442 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2444 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2447 /* The location from which a PC relative jump should be calculated,
2448 given a PC relative reloc. */
2451 md_pcrel_from_section (fixS
*fixP
,
2454 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2456 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2458 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2459 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2460 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2462 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2464 /* The symbol is undefined (or is defined but not in this section).
2465 Let the linker figure it out. */
2469 if ((int) fixP
->fx_r_type
< 0)
2471 /* These are the "internal" relocations. Align them to
2472 32 bit boundary (PCL), for the moment. */
2477 switch (fixP
->fx_r_type
)
2479 case BFD_RELOC_ARC_PC32
:
2480 /* The hardware calculates relative to the start of the
2481 insn, but this relocation is relative to location of the
2482 LIMM, compensate. The base always needs to be
2483 substracted by 4 as we do not support this type of PCrel
2484 relocation for short instructions. */
2487 case BFD_RELOC_ARC_PLT32
:
2488 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2489 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2490 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2491 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2493 case BFD_RELOC_ARC_S21H_PCREL
:
2494 case BFD_RELOC_ARC_S25H_PCREL
:
2495 case BFD_RELOC_ARC_S13_PCREL
:
2496 case BFD_RELOC_ARC_S21W_PCREL
:
2497 case BFD_RELOC_ARC_S25W_PCREL
:
2501 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2502 _("unhandled reloc %s in md_pcrel_from_section"),
2503 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2508 pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n",
2509 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2510 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2511 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2516 /* Given a BFD relocation find the coresponding operand. */
2518 static const struct arc_operand
*
2519 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2523 for (i
= 0; i
< arc_num_operands
; i
++)
2524 if (arc_operands
[i
].default_reloc
== reloc
)
2525 return &arc_operands
[i
];
2529 /* Insert an operand value into an instruction. */
2532 insert_operand (unsigned insn
,
2533 const struct arc_operand
*operand
,
2538 offsetT min
= 0, max
= 0;
2540 if (operand
->bits
!= 32
2541 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2542 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2544 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2546 max
= (1 << (operand
->bits
- 1)) - 1;
2547 min
= -(1 << (operand
->bits
- 1));
2551 max
= (1 << operand
->bits
) - 1;
2555 if (val
< min
|| val
> max
)
2556 as_bad_value_out_of_range (_("operand"),
2557 val
, min
, max
, file
, line
);
2560 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2561 min
, val
, max
, insn
);
2563 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2565 as_bad_where (file
, line
,
2566 _("Unaligned operand. Needs to be 32bit aligned"));
2568 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2570 as_bad_where (file
, line
,
2571 _("Unaligned operand. Needs to be 16bit aligned"));
2573 if (operand
->insert
)
2575 const char *errmsg
= NULL
;
2577 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2579 as_warn_where (file
, line
, "%s", errmsg
);
2583 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2585 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2587 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2590 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2595 /* Apply a fixup to the object code. At this point all symbol values
2596 should be fully resolved, and we attempt to completely resolve the
2597 reloc. If we can not do that, we determine the correct reloc code
2598 and put it back in the fixup. To indicate that a fixup has been
2599 eliminated, set fixP->fx_done. */
2602 md_apply_fix (fixS
*fixP
,
2606 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2607 valueT value
= *valP
;
2609 symbolS
*fx_addsy
, *fx_subsy
;
2611 segT add_symbol_segment
= absolute_section
;
2612 segT sub_symbol_segment
= absolute_section
;
2613 const struct arc_operand
*operand
= NULL
;
2614 extended_bfd_reloc_code_real_type reloc
;
2616 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2617 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2618 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2619 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2622 fx_addsy
= fixP
->fx_addsy
;
2623 fx_subsy
= fixP
->fx_subsy
;
2628 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2632 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2633 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2634 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2636 resolve_symbol_value (fx_subsy
);
2637 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2639 if (sub_symbol_segment
== absolute_section
)
2641 /* The symbol is really a constant. */
2642 fx_offset
-= S_GET_VALUE (fx_subsy
);
2647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2648 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2649 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2650 segment_name (add_symbol_segment
),
2651 S_GET_NAME (fx_subsy
),
2652 segment_name (sub_symbol_segment
));
2658 && !S_IS_WEAK (fx_addsy
))
2660 if (add_symbol_segment
== seg
2663 value
+= S_GET_VALUE (fx_addsy
);
2664 value
-= md_pcrel_from_section (fixP
, seg
);
2666 fixP
->fx_pcrel
= FALSE
;
2668 else if (add_symbol_segment
== absolute_section
)
2670 value
= fixP
->fx_offset
;
2671 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2673 fixP
->fx_pcrel
= FALSE
;
2678 fixP
->fx_done
= TRUE
;
2683 && ((S_IS_DEFINED (fx_addsy
)
2684 && S_GET_SEGMENT (fx_addsy
) != seg
)
2685 || S_IS_WEAK (fx_addsy
)))
2686 value
+= md_pcrel_from_section (fixP
, seg
);
2688 switch (fixP
->fx_r_type
)
2690 case BFD_RELOC_ARC_32_ME
:
2691 /* This is a pc-relative value in a LIMM. Adjust it to the
2692 address of the instruction not to the address of the
2693 LIMM. Note: it is not anylonger valid this afirmation as
2694 the linker consider ARC_PC32 a fixup to entire 64 bit
2696 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2699 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2701 case BFD_RELOC_ARC_PC32
:
2702 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2705 if ((int) fixP
->fx_r_type
< 0)
2706 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2712 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2713 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2714 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2715 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2719 /* Now check for TLS relocations. */
2720 reloc
= fixP
->fx_r_type
;
2723 case BFD_RELOC_ARC_TLS_DTPOFF
:
2724 case BFD_RELOC_ARC_TLS_LE_32
:
2728 case BFD_RELOC_ARC_TLS_GD_GOT
:
2729 case BFD_RELOC_ARC_TLS_IE_GOT
:
2730 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2733 case BFD_RELOC_ARC_TLS_GD_LD
:
2734 gas_assert (!fixP
->fx_offset
);
2737 = (S_GET_VALUE (fixP
->fx_subsy
)
2738 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2739 fixP
->fx_subsy
= NULL
;
2741 case BFD_RELOC_ARC_TLS_GD_CALL
:
2742 /* These two relocs are there just to allow ld to change the tls
2743 model for this symbol, by patching the code. The offset -
2744 and scale, if any - will be installed by the linker. */
2745 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2748 case BFD_RELOC_ARC_TLS_LE_S9
:
2749 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
2750 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2762 /* Addjust the value if we have a constant. */
2765 /* For hosts with longs bigger than 32-bits make sure that the top
2766 bits of a 32-bit negative value read in by the parser are set,
2767 so that the correct comparisons are made. */
2768 if (value
& 0x80000000)
2769 value
|= (-1L << 31);
2771 reloc
= fixP
->fx_r_type
;
2779 case BFD_RELOC_ARC_32_PCREL
:
2780 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
2783 case BFD_RELOC_ARC_GOTPC32
:
2784 /* I cannot fix an GOTPC relocation because I need to relax it
2785 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2786 as_bad (_("Unsupported operation on reloc"));
2789 case BFD_RELOC_ARC_TLS_DTPOFF
:
2790 case BFD_RELOC_ARC_TLS_LE_32
:
2791 gas_assert (!fixP
->fx_addsy
);
2792 gas_assert (!fixP
->fx_subsy
);
2794 case BFD_RELOC_ARC_GOTOFF
:
2795 case BFD_RELOC_ARC_32_ME
:
2796 case BFD_RELOC_ARC_PC32
:
2797 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2800 case BFD_RELOC_ARC_PLT32
:
2801 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2804 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2805 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2808 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2809 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
2812 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2813 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2816 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2817 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
2819 case BFD_RELOC_ARC_S25W_PCREL
:
2820 case BFD_RELOC_ARC_S21W_PCREL
:
2821 case BFD_RELOC_ARC_S21H_PCREL
:
2822 case BFD_RELOC_ARC_S25H_PCREL
:
2823 case BFD_RELOC_ARC_S13_PCREL
:
2825 operand
= find_operand_for_reloc (reloc
);
2826 gas_assert (operand
);
2831 if ((int) fixP
->fx_r_type
>= 0)
2832 as_fatal (_("unhandled relocation type %s"),
2833 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2835 /* The rest of these fixups needs to be completely resolved as
2837 if (fixP
->fx_addsy
!= 0
2838 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
2839 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2840 _("non-absolute expression in constant field"));
2842 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
2843 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
2848 if (target_big_endian
)
2850 switch (fixP
->fx_size
)
2853 insn
= bfd_getb32 (fixpos
);
2856 insn
= bfd_getb16 (fixpos
);
2859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2860 _("unknown fixup size"));
2866 switch (fixP
->fx_size
)
2869 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
2872 insn
= bfd_getl16 (fixpos
);
2875 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2876 _("unknown fixup size"));
2880 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
2881 fixP
->fx_file
, fixP
->fx_line
);
2883 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
2886 /* Prepare machine-dependent frags for relaxation.
2888 Called just before relaxation starts. Any symbol that is now undefined
2889 will not become defined.
2891 Return the correct fr_subtype in the frag.
2893 Return the initial "guess for fr_var" to caller. The guess for fr_var
2894 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
2895 or fr_var contributes to our returned value.
2897 Although it may not be explicit in the frag, pretend
2898 fr_var starts with a value. */
2901 md_estimate_size_before_relax (fragS
*fragP
,
2906 /* If the symbol is not located within the same section AND it's not
2907 an absolute section, use the maximum. OR if the symbol is a
2908 constant AND the insn is by nature not pc-rel, use the maximum.
2909 OR if the symbol is being equated against another symbol, use the
2910 maximum. OR if the symbol is weak use the maximum. */
2911 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
2912 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2913 || (symbol_constant_p (fragP
->fr_symbol
)
2914 && !fragP
->tc_frag_data
.pcrel
)
2915 || symbol_equated_p (fragP
->fr_symbol
)
2916 || S_IS_WEAK (fragP
->fr_symbol
))
2918 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
2919 ++fragP
->fr_subtype
;
2922 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
2923 fragP
->fr_var
= growth
;
2925 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
2926 fragP
->fr_file
, fragP
->fr_line
, growth
);
2931 /* Translate internal representation of relocation info to BFD target
2935 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
2939 bfd_reloc_code_real_type code
;
2941 reloc
= XNEW (arelent
);
2942 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
2943 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
2944 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
2946 /* Make sure none of our internal relocations make it this far.
2947 They'd better have been fully resolved by this point. */
2948 gas_assert ((int) fixP
->fx_r_type
> 0);
2950 code
= fixP
->fx_r_type
;
2952 /* if we have something like add gp, pcl,
2953 _GLOBAL_OFFSET_TABLE_@gotpc. */
2954 if (code
== BFD_RELOC_ARC_GOTPC32
2956 && fixP
->fx_addsy
== GOT_symbol
)
2957 code
= BFD_RELOC_ARC_GOTPC
;
2959 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
2960 if (reloc
->howto
== NULL
)
2962 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2963 _("cannot represent `%s' relocation in object file"),
2964 bfd_get_reloc_code_name (code
));
2968 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
2969 as_fatal (_("internal error? cannot generate `%s' relocation"),
2970 bfd_get_reloc_code_name (code
));
2972 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
2974 if (code
== BFD_RELOC_ARC_TLS_DTPOFF
2975 || code
== BFD_RELOC_ARC_TLS_DTPOFF_S9
)
2978 = fixP
->fx_subsy
? symbol_get_bfdsym (fixP
->fx_subsy
) : NULL
;
2979 /* We just want to store a 24 bit index, but we have to wait
2980 till after write_contents has been called via
2981 bfd_map_over_sections before we can get the index from
2982 _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
2983 function is elf32-arc.c has to pick up the slack.
2984 Unfortunately, this leads to problems with hosts that have
2985 pointers wider than long (bfd_vma). There would be various
2986 ways to handle this, all error-prone :-( */
2987 reloc
->addend
= (bfd_vma
) sym
;
2988 if ((asymbol
*) reloc
->addend
!= sym
)
2990 as_bad ("Can't store pointer\n");
2995 reloc
->addend
= fixP
->fx_offset
;
3000 /* Perform post-processing of machine-dependent frags after relaxation.
3001 Called after relaxation is finished.
3002 In: Address of frag.
3003 fr_type == rs_machine_dependent.
3004 fr_subtype is what the address relaxed to.
3006 Out: Any fixS:s and constants are set up. */
3009 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3010 segT segment ATTRIBUTE_UNUSED
,
3013 const relax_typeS
*table_entry
;
3015 const struct arc_opcode
*opcode
;
3016 struct arc_insn insn
;
3018 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3020 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
3021 dest
= fragP
->fr_literal
+ fix
;
3022 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3024 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n",
3025 fragP
->fr_file
, fragP
->fr_line
,
3026 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3028 if (fragP
->fr_subtype
<= 0
3029 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3030 as_fatal (_("no relaxation found for this instruction."));
3032 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3034 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3035 relax_arg
->nflg
, &insn
);
3037 apply_fixups (&insn
, fragP
, fix
);
3039 size
= insn
.short_insn
? (insn
.has_limm
? 6 : 2) : (insn
.has_limm
? 8 : 4);
3040 gas_assert (table_entry
->rlx_length
== size
);
3041 emit_insn0 (&insn
, dest
, TRUE
);
3043 fragP
->fr_fix
+= table_entry
->rlx_length
;
3047 /* We have no need to default values of symbols. We could catch
3048 register names here, but that is handled by inserting them all in
3049 the symbol table to begin with. */
3052 md_undefined_symbol (char *name
)
3054 /* The arc abi demands that a GOT[0] should be referencible as
3055 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3056 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3058 && (*(name
+1) == 'G')
3059 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
3061 && (*(name
+1) == 'D')
3062 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
3066 if (symbol_find (name
))
3067 as_bad ("GOT already in symbol table");
3069 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3070 (valueT
) 0, &zero_address_frag
);
3077 /* Turn a string in input_line_pointer into a floating point constant
3078 of type type, and store the appropriate bytes in *litP. The number
3079 of LITTLENUMS emitted is stored in *sizeP. An error message is
3080 returned, or NULL on OK. */
3083 md_atof (int type
, char *litP
, int *sizeP
)
3085 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3088 /* Called for any expression that can not be recognized. When the
3089 function is called, `input_line_pointer' will point to the start of
3093 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3095 char *p
= input_line_pointer
;
3098 input_line_pointer
++;
3099 expressionP
->X_op
= O_symbol
;
3100 expression (expressionP
);
3104 /* This function is called from the function 'expression', it attempts
3105 to parse special names (in our case register names). It fills in
3106 the expression with the identified register. It returns TRUE if
3107 it is a register and FALSE otherwise. */
3110 arc_parse_name (const char *name
,
3111 struct expressionS
*e
)
3115 if (!assembling_insn
)
3118 /* Handle only registers. */
3119 if (e
->X_op
!= O_absent
)
3122 sym
= hash_find (arc_reg_hash
, name
);
3125 e
->X_op
= O_register
;
3126 e
->X_add_number
= S_GET_VALUE (sym
);
3133 Invocation line includes a switch not recognized by the base assembler.
3134 See if it's a processor-specific option.
3136 New options (supported) are:
3138 -mcpu=<cpu name> Assemble for selected processor
3139 -EB/-mbig-endian Big-endian
3140 -EL/-mlittle-endian Little-endian
3141 -mrelax Enable relaxation
3143 The following CPU names are recognized:
3144 arc700, av2em, av2hs. */
3147 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3153 return md_parse_option (OPTION_MCPU
, "arc600");
3156 return md_parse_option (OPTION_MCPU
, "arc700");
3159 return md_parse_option (OPTION_MCPU
, "arcem");
3162 return md_parse_option (OPTION_MCPU
, "archs");
3166 arc_select_cpu (arg
);
3167 mach_type_specified_p
= TRUE
;
3172 arc_target_format
= "elf32-bigarc";
3173 byte_order
= BIG_ENDIAN
;
3177 arc_target_format
= "elf32-littlearc";
3178 byte_order
= LITTLE_ENDIAN
;
3182 /* This option has an effect only on ARC EM. */
3183 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3184 arc_features
|= ARC_CD
;
3186 as_warn (_("Code density option invalid for selected CPU"));
3190 relaxation_state
= 1;
3193 case OPTION_USER_MODE
:
3194 case OPTION_LD_EXT_MASK
:
3197 case OPTION_BARREL_SHIFT
:
3198 case OPTION_MIN_MAX
:
3203 /* Dummy options are accepted but have no effect. */
3207 arc_features
|= ARC_SPFP
;
3211 arc_features
|= ARC_DPFP
;
3214 case OPTION_XMAC_D16
:
3215 case OPTION_XMAC_24
:
3216 case OPTION_DSP_PACKA
:
3219 case OPTION_TELEPHONY
:
3220 case OPTION_XYMEMORY
:
3224 /* Dummy options are accepted but have no effect. */
3228 /* This option has an effect only on ARC EM. */
3229 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3230 arc_features
|= ARC_FPUDA
;
3232 as_warn (_("FPUDA invalid for selected CPU"));
3243 md_show_usage (FILE *stream
)
3245 fprintf (stream
, _("ARC-specific assembler options:\n"));
3247 fprintf (stream
, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
3249 " -mcode-density\t enable code density option for ARC EM\n");
3251 fprintf (stream
, _("\
3252 -EB assemble code for a big-endian cpu\n"));
3253 fprintf (stream
, _("\
3254 -EL assemble code for a little-endian cpu\n"));
3255 fprintf (stream
, _("\
3256 -mrelax Enable relaxation\n"));
3260 /* Find the proper relocation for the given opcode. */
3262 static extended_bfd_reloc_code_real_type
3263 find_reloc (const char *name
,
3264 const char *opcodename
,
3265 const struct arc_flags
*pflags
,
3267 extended_bfd_reloc_code_real_type reloc
)
3271 bfd_boolean found_flag
, tmp
;
3272 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3274 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3276 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3278 /* Find the entry. */
3279 if (strcmp (name
, r
->name
))
3281 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3288 unsigned * psflg
= (unsigned *)r
->flags
;
3292 for (j
= 0; j
< nflg
; j
++)
3293 if (!strcmp (pflags
[j
].name
,
3294 arc_flag_operands
[*psflg
].name
))
3315 if (reloc
!= r
->oldreloc
)
3322 if (ret
== BFD_RELOC_UNUSED
)
3323 as_bad (_("Unable to find %s relocation for instruction %s"),
3328 /* All the symbol types that are allowed to be used for
3332 may_relax_expr (expressionS tok
)
3334 /* Check if we have unrelaxable relocs. */
3359 /* Checks if flags are in line with relaxable insn. */
3362 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3363 const struct arc_flags
*pflags
,
3366 unsigned flag_class
,
3371 const struct arc_flag_operand
*flag_opand
;
3372 int i
, counttrue
= 0;
3374 /* Iterate through flags classes. */
3375 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3377 /* Iterate through flags in flag class. */
3378 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3381 flag_opand
= &arc_flag_operands
[flag
];
3382 /* Iterate through flags in ins to compare. */
3383 for (i
= 0; i
< nflgs
; ++i
)
3385 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3396 /* If counttrue == nflgs, then all flags have been found. */
3397 return (counttrue
== nflgs
? TRUE
: FALSE
);
3400 /* Checks if operands are in line with relaxable insn. */
3403 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3404 const expressionS
*tok
,
3407 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3410 while (*operand
!= EMPTY
)
3412 const expressionS
*epr
= &tok
[i
];
3414 if (i
!= 0 && i
>= ntok
)
3420 if (!(epr
->X_op
== O_multiply
3421 || epr
->X_op
== O_divide
3422 || epr
->X_op
== O_modulus
3423 || epr
->X_op
== O_add
3424 || epr
->X_op
== O_subtract
3425 || epr
->X_op
== O_symbol
))
3431 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3435 if (epr
->X_op
!= O_register
)
3440 if (epr
->X_op
!= O_register
)
3443 switch (epr
->X_add_number
)
3445 case 0: case 1: case 2: case 3:
3446 case 12: case 13: case 14: case 15:
3453 case REGISTER_NO_GP
:
3454 if ((epr
->X_op
!= O_register
)
3455 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3460 if (epr
->X_op
!= O_bracket
)
3465 /* Don't understand, bail out. */
3471 operand
= &ins
->operands
[i
];
3474 return (i
== ntok
? TRUE
: FALSE
);
3477 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3480 relax_insn_p (const struct arc_opcode
*opcode
,
3481 const expressionS
*tok
,
3483 const struct arc_flags
*pflags
,
3487 bfd_boolean rv
= FALSE
;
3489 /* Check the relaxation table. */
3490 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3492 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3494 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3495 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3496 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3497 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3500 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3501 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3502 sizeof (expressionS
) * ntok
);
3503 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3504 sizeof (struct arc_flags
) * nflg
);
3505 frag_now
->tc_frag_data
.nflg
= nflg
;
3506 frag_now
->tc_frag_data
.ntok
= ntok
;
3514 /* Turn an opcode description and a set of arguments into
3515 an instruction and a fixup. */
3518 assemble_insn (const struct arc_opcode
*opcode
,
3519 const expressionS
*tok
,
3521 const struct arc_flags
*pflags
,
3523 struct arc_insn
*insn
)
3525 const expressionS
*reloc_exp
= NULL
;
3527 const unsigned char *argidx
;
3530 unsigned char pcrel
= 0;
3531 bfd_boolean needGOTSymbol
;
3532 bfd_boolean has_delay_slot
= FALSE
;
3533 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3535 memset (insn
, 0, sizeof (*insn
));
3536 image
= opcode
->opcode
;
3538 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3539 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3542 /* Handle operands. */
3543 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3545 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3546 const expressionS
*t
= (const expressionS
*) 0;
3548 if ((operand
->flags
& ARC_OPERAND_FAKE
)
3549 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
3552 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3554 /* Duplicate operand, already inserted. */
3566 /* Regardless if we have a reloc or not mark the instruction
3567 limm if it is the case. */
3568 if (operand
->flags
& ARC_OPERAND_LIMM
)
3569 insn
->has_limm
= TRUE
;
3574 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3579 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3581 if (operand
->flags
& ARC_OPERAND_LIMM
)
3582 insn
->limm
= t
->X_add_number
;
3586 /* Ignore brackets. */
3590 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3594 /* Maybe register range. */
3595 if ((t
->X_add_number
== 0)
3596 && contains_register (t
->X_add_symbol
)
3597 && contains_register (t
->X_op_symbol
))
3601 regs
= get_register (t
->X_add_symbol
);
3603 regs
|= get_register (t
->X_op_symbol
);
3604 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3609 /* This operand needs a relocation. */
3610 needGOTSymbol
= FALSE
;
3615 if (opcode
->class == JUMP
)
3616 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3617 _("Unable to use @plt relocatio for insn %s"),
3619 needGOTSymbol
= TRUE
;
3620 reloc
= find_reloc ("plt", opcode
->name
,
3622 operand
->default_reloc
);
3627 needGOTSymbol
= TRUE
;
3628 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3631 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3632 if (ARC_SHORT (opcode
->mask
) || opcode
->class == JUMP
)
3633 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3634 _("Unable to use @pcl relocation for insn %s"),
3638 reloc
= find_reloc ("sda", opcode
->name
,
3640 operand
->default_reloc
);
3644 needGOTSymbol
= TRUE
;
3649 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3652 case O_tpoff9
: /*FIXME! Check for the conditionality of
3654 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3656 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3660 /* Just consider the default relocation. */
3661 reloc
= operand
->default_reloc
;
3665 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3666 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3673 /* sanity checks. */
3674 reloc_howto_type
*reloc_howto
3675 = bfd_reloc_type_lookup (stdoutput
,
3676 (bfd_reloc_code_real_type
) reloc
);
3677 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
3678 if (reloc_howto
->rightshift
)
3679 reloc_bitsize
-= reloc_howto
->rightshift
;
3680 if (reloc_bitsize
!= operand
->bits
)
3682 as_bad (_("invalid relocation %s for field"),
3683 bfd_get_reloc_code_name (reloc
));
3688 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3689 as_fatal (_("too many fixups"));
3691 struct arc_fixup
*fixup
;
3692 fixup
= &insn
->fixups
[insn
->nfixups
++];
3694 fixup
->reloc
= reloc
;
3695 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
3696 fixup
->pcrel
= pcrel
;
3697 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
3704 for (i
= 0; i
< nflg
; i
++)
3706 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
3708 /* Check if the instruction has a delay slot. */
3709 if (!strcmp (flg_operand
->name
, "d"))
3710 has_delay_slot
= TRUE
;
3712 /* There is an exceptional case when we cannot insert a flag
3713 just as it is. The .T flag must be handled in relation with
3714 the relative address. */
3715 if (!strcmp (flg_operand
->name
, "t")
3716 || !strcmp (flg_operand
->name
, "nt"))
3718 unsigned bitYoperand
= 0;
3719 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3720 if (!strcmp (flg_operand
->name
, "t"))
3721 if (!strcmp (opcode
->name
, "bbit0")
3722 || !strcmp (opcode
->name
, "bbit1"))
3723 bitYoperand
= arc_NToperand
;
3725 bitYoperand
= arc_Toperand
;
3727 if (!strcmp (opcode
->name
, "bbit0")
3728 || !strcmp (opcode
->name
, "bbit1"))
3729 bitYoperand
= arc_Toperand
;
3731 bitYoperand
= arc_NToperand
;
3733 gas_assert (reloc_exp
!= NULL
);
3734 if (reloc_exp
->X_op
== O_constant
)
3736 /* Check if we have a constant and solved it
3738 offsetT val
= reloc_exp
->X_add_number
;
3739 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
3744 struct arc_fixup
*fixup
;
3746 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3747 as_fatal (_("too many fixups"));
3749 fixup
= &insn
->fixups
[insn
->nfixups
++];
3750 fixup
->exp
= *reloc_exp
;
3751 fixup
->reloc
= -bitYoperand
;
3752 fixup
->pcrel
= pcrel
;
3753 fixup
->islong
= FALSE
;
3757 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
3758 << flg_operand
->shift
;
3761 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
3763 /* Short instruction? */
3764 insn
->short_insn
= ARC_SHORT (opcode
->mask
) ? TRUE
: FALSE
;
3768 /* Update last insn status. */
3769 arc_last_insns
[1] = arc_last_insns
[0];
3770 arc_last_insns
[0].opcode
= opcode
;
3771 arc_last_insns
[0].has_limm
= insn
->has_limm
;
3772 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
3774 /* Check if the current instruction is legally used. */
3775 if (arc_last_insns
[1].has_delay_slot
3776 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3777 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3778 _("A jump/branch instruction in delay slot."));
3782 arc_handle_align (fragS
* fragP
)
3784 if ((fragP
)->fr_type
== rs_align_code
)
3786 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
3787 valueT count
= ((fragP
)->fr_next
->fr_address
3788 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
3790 (fragP
)->fr_var
= 2;
3792 if (count
& 1)/* Padding in the gap till the next 2-byte
3793 boundary with 0s. */
3798 /* Writing nop_s. */
3799 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
3803 /* Here we decide which fixups can be adjusted to make them relative
3804 to the beginning of the section instead of the symbol. Basically
3805 we need to make sure that the dynamic relocations are done
3806 correctly, so in some cases we force the original symbol to be
3810 tc_arc_fix_adjustable (fixS
*fixP
)
3813 /* Prevent all adjustments to global symbols. */
3814 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
3816 if (S_IS_WEAK (fixP
->fx_addsy
))
3819 /* Adjust_reloc_syms doesn't know about the GOT. */
3820 switch (fixP
->fx_r_type
)
3822 case BFD_RELOC_ARC_GOTPC32
:
3823 case BFD_RELOC_ARC_PLT32
:
3824 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3825 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3826 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3827 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3837 /* Compute the reloc type of an expression EXP. */
3840 arc_check_reloc (expressionS
*exp
,
3841 bfd_reloc_code_real_type
*r_type_p
)
3843 if (*r_type_p
== BFD_RELOC_32
3844 && exp
->X_op
== O_subtract
3845 && exp
->X_op_symbol
!= NULL
3846 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
3847 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
3851 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
3854 arc_cons_fix_new (fragS
*frag
,
3858 bfd_reloc_code_real_type r_type
)
3860 r_type
= BFD_RELOC_UNUSED
;
3865 r_type
= BFD_RELOC_8
;
3869 r_type
= BFD_RELOC_16
;
3873 r_type
= BFD_RELOC_24
;
3877 r_type
= BFD_RELOC_32
;
3878 arc_check_reloc (exp
, &r_type
);
3882 r_type
= BFD_RELOC_64
;
3886 as_bad (_("unsupported BFD relocation size %u"), size
);
3887 r_type
= BFD_RELOC_UNUSED
;
3890 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
3893 /* The actual routine that checks the ZOL conditions. */
3896 check_zol (symbolS
*s
)
3898 switch (arc_mach_type
)
3900 case bfd_mach_arc_arcv2
:
3901 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3904 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
3905 || arc_last_insns
[1].has_delay_slot
)
3906 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
3910 case bfd_mach_arc_arc600
:
3912 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
3913 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
3916 if (arc_last_insns
[0].has_limm
3917 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3918 as_bad (_("A jump instruction with long immediate detected at the \
3919 end of the ZOL label @%s"), S_GET_NAME (s
));
3922 case bfd_mach_arc_nps400
:
3923 case bfd_mach_arc_arc700
:
3924 if (arc_last_insns
[0].has_delay_slot
)
3925 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
3934 /* If ZOL end check the last two instruction for illegals. */
3936 arc_frob_label (symbolS
* sym
)
3938 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
3941 dwarf2_emit_label (sym
);
3944 /* Used because generic relaxation assumes a pc-rel value whilst we
3945 also relax instructions that use an absolute value resolved out of
3946 relative values (if that makes any sense). An example: 'add r1,
3947 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
3948 but if they're in the same section we can subtract the section
3949 offset relocation which ends up in a resolved value. So if @.L2 is
3950 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
3951 .text + 0x40 = 0x10. */
3953 arc_pcrel_adjust (fragS
*fragP
)
3955 if (!fragP
->tc_frag_data
.pcrel
)
3956 return fragP
->fr_address
+ fragP
->fr_fix
;
3961 /* Initialize the DWARF-2 unwind information for this procedure. */
3964 tc_arc_frame_initial_instructions (void)
3966 /* Stack pointer is register 28. */
3967 cfi_add_CFA_def_cfa_register (28);
3971 tc_arc_regname_to_dw2regnum (char *regname
)
3975 sym
= hash_find (arc_reg_hash
, regname
);
3977 return S_GET_VALUE (sym
);
3982 /* Adjust the symbol table. Delete found AUX register symbols. */
3985 arc_adjust_symtab (void)
3989 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
3991 /* I've created a symbol during parsing process. Now, remove
3992 the symbol as it is found to be an AUX register. */
3993 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
3994 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
3997 /* Now do generic ELF adjustments. */
3998 elf_adjust_symtab ();
4002 tokenize_extinsn (extInstruction_t
*einsn
)
4006 unsigned char major_opcode
;
4007 unsigned char sub_opcode
;
4008 unsigned char syntax_class
= 0;
4009 unsigned char syntax_class_modifiers
= 0;
4010 unsigned char suffix_class
= 0;
4015 /* 1st: get instruction name. */
4016 p
= input_line_pointer
;
4017 c
= get_symbol_name (&p
);
4019 insn_name
= xstrdup (p
);
4020 restore_line_pointer (c
);
4022 /* 2nd: get major opcode. */
4023 if (*input_line_pointer
!= ',')
4025 as_bad (_("expected comma after instruction name"));
4026 ignore_rest_of_line ();
4029 input_line_pointer
++;
4030 major_opcode
= get_absolute_expression ();
4032 /* 3rd: get sub-opcode. */
4035 if (*input_line_pointer
!= ',')
4037 as_bad (_("expected comma after major opcode"));
4038 ignore_rest_of_line ();
4041 input_line_pointer
++;
4042 sub_opcode
= get_absolute_expression ();
4044 /* 4th: get suffix class. */
4047 if (*input_line_pointer
!= ',')
4049 as_bad ("expected comma after sub opcode");
4050 ignore_rest_of_line ();
4053 input_line_pointer
++;
4059 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4061 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4062 suffixclass
[i
].len
))
4064 suffix_class
|= suffixclass
[i
].class;
4065 input_line_pointer
+= suffixclass
[i
].len
;
4070 if (i
== ARRAY_SIZE (suffixclass
))
4072 as_bad ("invalid suffix class");
4073 ignore_rest_of_line ();
4079 if (*input_line_pointer
== '|')
4080 input_line_pointer
++;
4085 /* 5th: get syntax class and syntax class modifiers. */
4086 if (*input_line_pointer
!= ',')
4088 as_bad ("expected comma after suffix class");
4089 ignore_rest_of_line ();
4092 input_line_pointer
++;
4098 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4100 if (!strncmp (syntaxclassmod
[i
].name
,
4102 syntaxclassmod
[i
].len
))
4104 syntax_class_modifiers
|= syntaxclassmod
[i
].class;
4105 input_line_pointer
+= syntaxclassmod
[i
].len
;
4110 if (i
== ARRAY_SIZE (syntaxclassmod
))
4112 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4114 if (!strncmp (syntaxclass
[i
].name
,
4116 syntaxclass
[i
].len
))
4118 syntax_class
|= syntaxclass
[i
].class;
4119 input_line_pointer
+= syntaxclass
[i
].len
;
4124 if (i
== ARRAY_SIZE (syntaxclass
))
4126 as_bad ("missing syntax class");
4127 ignore_rest_of_line ();
4134 if (*input_line_pointer
== '|')
4135 input_line_pointer
++;
4140 demand_empty_rest_of_line ();
4142 einsn
->name
= insn_name
;
4143 einsn
->major
= major_opcode
;
4144 einsn
->minor
= sub_opcode
;
4145 einsn
->syntax
= syntax_class
;
4146 einsn
->modsyn
= syntax_class_modifiers
;
4147 einsn
->suffix
= suffix_class
;
4148 einsn
->flags
= syntax_class
4149 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4152 /* Generate an extension section. */
4155 arc_set_ext_seg (void)
4157 if (!arcext_section
)
4159 arcext_section
= subseg_new (".arcextmap", 0);
4160 bfd_set_section_flags (stdoutput
, arcext_section
,
4161 SEC_READONLY
| SEC_HAS_CONTENTS
);
4164 subseg_set (arcext_section
, 0);
4168 /* Create an extension instruction description in the arc extension
4169 section of the output file.
4170 The structure for an instruction is like this:
4171 [0]: Length of the record.
4172 [1]: Type of the record.
4176 [4]: Syntax (flags).
4177 [5]+ Name instruction.
4179 The sequence is terminated by an empty entry. */
4182 create_extinst_section (extInstruction_t
*einsn
)
4185 segT old_sec
= now_seg
;
4186 int old_subsec
= now_subseg
;
4188 int name_len
= strlen (einsn
->name
);
4193 *p
= 5 + name_len
+ 1;
4195 *p
= EXT_INSTRUCTION
;
4202 p
= frag_more (name_len
+ 1);
4203 strcpy (p
, einsn
->name
);
4205 subseg_set (old_sec
, old_subsec
);
4208 /* Handler .extinstruction pseudo-op. */
4211 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4213 extInstruction_t einsn
;
4214 struct arc_opcode
*arc_ext_opcodes
;
4215 const char *errmsg
= NULL
;
4216 unsigned char moplow
, mophigh
;
4218 memset (&einsn
, 0, sizeof (einsn
));
4219 tokenize_extinsn (&einsn
);
4221 /* Check if the name is already used. */
4222 if (arc_find_opcode (einsn
.name
))
4223 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4225 /* Check the opcode ranges. */
4227 mophigh
= (arc_target
& (ARC_OPCODE_ARCv2EM
4228 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4230 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4231 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4233 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4234 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4235 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4237 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4239 case ARC_SYNTAX_3OP
:
4240 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4241 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4243 case ARC_SYNTAX_2OP
:
4244 case ARC_SYNTAX_1OP
:
4245 case ARC_SYNTAX_NOP
:
4246 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4247 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4253 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, arc_target
, &errmsg
);
4254 if (arc_ext_opcodes
== NULL
)
4257 as_fatal ("%s", errmsg
);
4259 as_fatal (_("Couldn't generate extension instruction opcodes"));
4262 as_warn ("%s", errmsg
);
4264 /* Insert the extension instruction. */
4265 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4267 create_extinst_section (&einsn
);
4271 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4277 int number
, imode
= 0;
4278 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4279 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4280 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4282 /* 1st: get register name. */
4284 p
= input_line_pointer
;
4285 c
= get_symbol_name (&p
);
4288 restore_line_pointer (c
);
4290 /* 2nd: get register number. */
4293 if (*input_line_pointer
!= ',')
4295 as_bad (_("expected comma after register name"));
4296 ignore_rest_of_line ();
4300 input_line_pointer
++;
4301 number
= get_absolute_expression ();
4305 as_bad (_("negative operand number %d"), number
);
4306 ignore_rest_of_line ();
4313 /* 3rd: get register mode. */
4316 if (*input_line_pointer
!= ',')
4318 as_bad (_("expected comma after register number"));
4319 ignore_rest_of_line ();
4324 input_line_pointer
++;
4325 mode
= input_line_pointer
;
4327 if (!strncmp (mode
, "r|w", 3))
4330 input_line_pointer
+= 3;
4332 else if (!strncmp (mode
, "r", 1))
4334 imode
= ARC_REGISTER_READONLY
;
4335 input_line_pointer
+= 1;
4337 else if (strncmp (mode
, "w", 1))
4339 as_bad (_("invalid mode"));
4340 ignore_rest_of_line ();
4346 imode
= ARC_REGISTER_WRITEONLY
;
4347 input_line_pointer
+= 1;
4353 /* 4th: get core register shortcut. */
4355 if (*input_line_pointer
!= ',')
4357 as_bad (_("expected comma after register mode"));
4358 ignore_rest_of_line ();
4363 input_line_pointer
++;
4365 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4367 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4368 input_line_pointer
+= 15;
4370 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4372 as_bad (_("shortcut designator invalid"));
4373 ignore_rest_of_line ();
4379 input_line_pointer
+= 12;
4382 demand_empty_rest_of_line ();
4385 ereg
->number
= number
;
4386 ereg
->imode
= imode
;
4389 /* Create an extension register/condition description in the arc
4390 extension section of the output file.
4392 The structure for an instruction is like this:
4393 [0]: Length of the record.
4394 [1]: Type of the record.
4396 For core regs and condition codes:
4400 For auxilirary registers:
4404 The sequence is terminated by an empty entry. */
4407 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4409 segT old_sec
= now_seg
;
4410 int old_subsec
= now_subseg
;
4412 int name_len
= strlen (ereg
->name
);
4419 case EXT_CORE_REGISTER
:
4421 *p
= 3 + name_len
+ 1;
4427 case EXT_AUX_REGISTER
:
4429 *p
= 6 + name_len
+ 1;
4431 *p
= EXT_AUX_REGISTER
;
4433 *p
= (ereg
->number
>> 24) & 0xff;
4435 *p
= (ereg
->number
>> 16) & 0xff;
4437 *p
= (ereg
->number
>> 8) & 0xff;
4439 *p
= (ereg
->number
) & 0xff;
4445 p
= frag_more (name_len
+ 1);
4446 strcpy (p
, ereg
->name
);
4448 subseg_set (old_sec
, old_subsec
);
4451 /* Handler .extCoreRegister pseudo-op. */
4454 arc_extcorereg (int opertype
)
4457 struct arc_aux_reg
*auxr
;
4459 struct arc_flag_operand
*ccode
;
4461 memset (&ereg
, 0, sizeof (ereg
));
4462 tokenize_extregister (&ereg
, opertype
);
4466 case EXT_CORE_REGISTER
:
4467 /* Core register. */
4468 if (ereg
.number
> 60)
4469 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4471 declare_register (ereg
.name
, ereg
.number
);
4473 case EXT_AUX_REGISTER
:
4474 /* Auxiliary register. */
4475 auxr
= XNEW (struct arc_aux_reg
);
4476 auxr
->name
= ereg
.name
;
4477 auxr
->cpu
= arc_target
;
4478 auxr
->subclass
= NONE
;
4479 auxr
->address
= ereg
.number
;
4480 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4482 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4483 auxr
->name
, retval
);
4486 /* Condition code. */
4487 if (ereg
.number
> 31)
4488 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4490 ext_condcode
.size
++;
4491 ext_condcode
.arc_ext_condcode
=
4492 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4493 ext_condcode
.size
+ 1);
4494 if (ext_condcode
.arc_ext_condcode
== NULL
)
4495 as_fatal (_("Virtual memory exhausted"));
4497 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4498 ccode
->name
= ereg
.name
;
4499 ccode
->code
= ereg
.number
;
4502 ccode
->favail
= 0; /* not used. */
4504 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4507 as_bad (_("Unknown extension"));
4510 create_extcore_section (&ereg
, opertype
);
4514 eval: (c-set-style "gnu")