1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
31 #include "opcode/arc-attrs.h"
33 #include "../opcodes/arc-ext.h"
35 /* Defines section. */
37 #define MAX_INSN_FIXUPS 2
38 #define MAX_CONSTR_STR 20
39 #define FRAG_MAX_GROWTH 8
42 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
44 # define pr_debug(fmt, args...)
47 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
48 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
49 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
50 && (SUB_OPCODE (x) == 0x28))
52 /* Equal to MAX_PRECISION in atof-ieee.c. */
53 #define MAX_LITTLENUMS 6
55 #ifndef TARGET_WITH_CPU
56 #define TARGET_WITH_CPU "arc700"
57 #endif /* TARGET_WITH_CPU */
59 #define ARC_GET_FLAG(s) (*symbol_get_tc (s))
60 #define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
61 #define streq(a, b) (strcmp (a, b) == 0)
63 /* Enum used to enumerate the relaxable ins operands. */
68 REGISTER_S
, /* Register for short instruction(s). */
69 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
70 REGISTER_DUP
, /* Duplication of previous operand of type register. */
102 /* Macros section. */
104 #define regno(x) ((x) & 0x3F)
105 #define is_ir_num(x) (((x) & ~0x3F) == 0)
106 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
107 #define is_spfp_p(op) (((sc) == SPX))
108 #define is_dpfp_p(op) (((sc) == DPX))
109 #define is_fpuda_p(op) (((sc) == DPA))
110 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
111 || (op)->insn_class == JUMP))
112 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
113 #define is_nps400_p(op) (((sc) == NPS400))
115 /* Generic assembler global variables which must be defined by all
118 /* Characters which always start a comment. */
119 const char comment_chars
[] = "#;";
121 /* Characters which start a comment at the beginning of a line. */
122 const char line_comment_chars
[] = "#";
124 /* Characters which may be used to separate multiple commands on a
126 const char line_separator_chars
[] = "`";
128 /* Characters which are used to indicate an exponent in a floating
130 const char EXP_CHARS
[] = "eE";
132 /* Chars that mean this number is a floating point constant
133 As in 0f12.456 or 0d1.2345e12. */
134 const char FLT_CHARS
[] = "rRsSfFdD";
137 extern int target_big_endian
;
138 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
139 static int byte_order
= DEFAULT_BYTE_ORDER
;
141 /* Arc extension section. */
142 static segT arcext_section
;
144 /* By default relaxation is disabled. */
145 static int relaxation_state
= 0;
147 extern int arc_get_mach (char *);
149 /* Forward declarations. */
150 static void arc_lcomm (int);
151 static void arc_option (int);
152 static void arc_extra_reloc (int);
153 static void arc_extinsn (int);
154 static void arc_extcorereg (int);
155 static void arc_attribute (int);
157 const pseudo_typeS md_pseudo_table
[] =
159 /* Make sure that .word is 32 bits. */
162 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
163 { "lcomm", arc_lcomm
, 0 },
164 { "lcommon", arc_lcomm
, 0 },
165 { "cpu", arc_option
, 0 },
167 { "arc_attribute", arc_attribute
, 0 },
168 { "extinstruction", arc_extinsn
, 0 },
169 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
170 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
171 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
173 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
174 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
179 const char *md_shortopts
= "";
183 OPTION_EB
= OPTION_MD_BASE
,
201 /* The following options are deprecated and provided here only for
202 compatibility reasons. */
225 struct option md_longopts
[] =
227 { "EB", no_argument
, NULL
, OPTION_EB
},
228 { "EL", no_argument
, NULL
, OPTION_EL
},
229 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
230 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
231 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
232 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
233 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
234 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
235 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
236 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
237 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
238 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
239 { "mnps400", no_argument
, NULL
, OPTION_NPS400
},
241 /* Floating point options */
242 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
243 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
244 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
245 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
246 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
247 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
248 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
249 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
250 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
251 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
252 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
254 /* The following options are deprecated and provided here only for
255 compatibility reasons. */
256 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
257 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
258 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
259 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
260 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
261 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
262 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
263 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
264 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
265 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
266 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
267 { "mea", no_argument
, NULL
, OPTION_EA
},
268 { "mEA", no_argument
, NULL
, OPTION_EA
},
269 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
270 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
271 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
272 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
273 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
274 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
275 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
276 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
277 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
278 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
279 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
280 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
281 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
282 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
283 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
285 { NULL
, no_argument
, NULL
, 0 }
288 size_t md_longopts_size
= sizeof (md_longopts
);
290 /* Local data and data types. */
292 /* Used since new relocation types are introduced in this
293 file (DUMMY_RELOC_LITUSE_*). */
294 typedef int extended_bfd_reloc_code_real_type
;
300 extended_bfd_reloc_code_real_type reloc
;
302 /* index into arc_operands. */
303 unsigned int opindex
;
305 /* PC-relative, used by internals fixups. */
308 /* TRUE if this fixup is for LIMM operand. */
314 unsigned long long int insn
;
316 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
318 unsigned int len
; /* Length of instruction in bytes. */
319 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
321 bfd_boolean relax
; /* Boolean value: TRUE if needs
325 /* Structure to hold any last two instructions. */
326 static struct arc_last_insn
328 /* Saved instruction opcode. */
329 const struct arc_opcode
*opcode
;
331 /* Boolean value: TRUE if current insn is short. */
332 bfd_boolean has_limm
;
334 /* Boolean value: TRUE if current insn has delay slot. */
335 bfd_boolean has_delay_slot
;
338 /* Extension instruction suffix classes. */
346 static const attributes_t suffixclass
[] =
348 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
349 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
350 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
353 /* Extension instruction syntax classes. */
354 static const attributes_t syntaxclass
[] =
356 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
357 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
358 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
359 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
362 /* Extension instruction syntax classes modifiers. */
363 static const attributes_t syntaxclassmod
[] =
365 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
366 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
369 /* Extension register type. */
377 /* A structure to hold the additional conditional codes. */
380 struct arc_flag_operand
*arc_ext_condcode
;
382 } ext_condcode
= { NULL
, 0 };
384 /* Structure to hold an entry in ARC_OPCODE_HASH. */
385 struct arc_opcode_hash_entry
387 /* The number of pointers in the OPCODE list. */
390 /* Points to a list of opcode pointers. */
391 const struct arc_opcode
**opcode
;
394 /* Structure used for iterating through an arc_opcode_hash_entry. */
395 struct arc_opcode_hash_entry_iterator
397 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
400 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
401 returned by this iterator. */
402 const struct arc_opcode
*opcode
;
405 /* Forward declaration. */
406 static void assemble_insn
407 (const struct arc_opcode
*, const expressionS
*, int,
408 const struct arc_flags
*, int, struct arc_insn
*);
410 /* The selection of the machine type can come from different sources. This
411 enum is used to track how the selection was made in order to perform
413 enum mach_selection_type
416 MACH_SELECTION_FROM_DEFAULT
,
417 MACH_SELECTION_FROM_CPU_DIRECTIVE
,
418 MACH_SELECTION_FROM_COMMAND_LINE
421 /* How the current machine type was selected. */
422 static enum mach_selection_type mach_selection_mode
= MACH_SELECTION_NONE
;
424 /* The hash table of instruction opcodes. */
425 static struct hash_control
*arc_opcode_hash
;
427 /* The hash table of register symbols. */
428 static struct hash_control
*arc_reg_hash
;
430 /* The hash table of aux register symbols. */
431 static struct hash_control
*arc_aux_hash
;
433 /* The hash table of address types. */
434 static struct hash_control
*arc_addrtype_hash
;
436 #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
437 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
438 E_ARC_MACH_ARC600, EXTRA}
439 #define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
440 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
441 E_ARC_MACH_ARC700, EXTRA}
442 #define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
443 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
444 EF_ARC_CPU_ARCV2EM, EXTRA}
445 #define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
446 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
447 EF_ARC_CPU_ARCV2HS, EXTRA}
449 /* A table of CPU names and opcode sets. */
450 static const struct cpu_type
460 ARC_CPU_TYPE_A7xx (arc700
, 0x00),
461 ARC_CPU_TYPE_A7xx (nps400
, NPS400
),
463 ARC_CPU_TYPE_AV2EM (arcem
, 0x00),
464 ARC_CPU_TYPE_AV2EM (em
, 0x00),
465 ARC_CPU_TYPE_AV2EM (em4
, CD
),
466 ARC_CPU_TYPE_AV2EM (em4_dmips
, CD
),
467 ARC_CPU_TYPE_AV2EM (em4_fpus
, CD
),
468 ARC_CPU_TYPE_AV2EM (em4_fpuda
, CD
| DPA
),
469 ARC_CPU_TYPE_AV2EM (quarkse_em
, CD
| SPX
| DPX
),
471 ARC_CPU_TYPE_AV2HS (archs
, CD
),
472 ARC_CPU_TYPE_AV2HS (hs
, CD
),
473 ARC_CPU_TYPE_AV2HS (hs34
, CD
),
474 ARC_CPU_TYPE_AV2HS (hs38
, CD
),
475 ARC_CPU_TYPE_AV2HS (hs38_linux
, CD
),
477 ARC_CPU_TYPE_A6xx (arc600
, 0x00),
478 ARC_CPU_TYPE_A6xx (arc600_norm
, 0x00),
479 ARC_CPU_TYPE_A6xx (arc600_mul64
, 0x00),
480 ARC_CPU_TYPE_A6xx (arc600_mul32x16
, 0x00),
481 ARC_CPU_TYPE_A6xx (arc601
, 0x00),
482 ARC_CPU_TYPE_A6xx (arc601_norm
, 0x00),
483 ARC_CPU_TYPE_A6xx (arc601_mul64
, 0x00),
484 ARC_CPU_TYPE_A6xx (arc601_mul32x16
, 0x00),
488 /* Information about the cpu/variant we're assembling for. */
489 static struct cpu_type selected_cpu
= { 0, 0, 0, E_ARC_OSABI_CURRENT
, 0 };
492 static unsigned mpy_option
= 0;
495 static unsigned pic_option
= 0;
497 /* Use small data. */
498 static unsigned sda_option
= 0;
501 static unsigned tls_option
= 0;
503 /* Command line given features. */
504 static unsigned cl_features
= 0;
506 /* Used by the arc_reloc_op table. Order is important. */
507 #define O_gotoff O_md1 /* @gotoff relocation. */
508 #define O_gotpc O_md2 /* @gotpc relocation. */
509 #define O_plt O_md3 /* @plt relocation. */
510 #define O_sda O_md4 /* @sda relocation. */
511 #define O_pcl O_md5 /* @pcl relocation. */
512 #define O_tlsgd O_md6 /* @tlsgd relocation. */
513 #define O_tlsie O_md7 /* @tlsie relocation. */
514 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
515 #define O_tpoff O_md9 /* @tpoff relocation. */
516 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
517 #define O_dtpoff O_md11 /* @dtpoff relocation. */
518 #define O_last O_dtpoff
520 /* Used to define a bracket as operand in tokens. */
521 #define O_bracket O_md32
523 /* Used to define a colon as an operand in tokens. */
524 #define O_colon O_md31
526 /* Used to define address types in nps400. */
527 #define O_addrtype O_md30
529 /* Dummy relocation, to be sorted out. */
530 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
532 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
534 /* A table to map the spelling of a relocation operand into an appropriate
535 bfd_reloc_code_real_type type. The table is assumed to be ordered such
536 that op-O_literal indexes into it. */
537 #define ARC_RELOC_TABLE(op) \
538 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
540 : (int) (op) - (int) O_gotoff) ])
542 #define DEF(NAME, RELOC, REQ) \
543 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
545 static const struct arc_reloc_op_tag
547 /* String to lookup. */
549 /* Size of the string. */
551 /* Which operator to use. */
553 extended_bfd_reloc_code_real_type reloc
;
554 /* Allows complex relocation expression like identifier@reloc +
556 unsigned int complex_expr
: 1;
560 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
561 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
562 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
563 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
564 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
565 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
566 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
567 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
568 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
569 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
570 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 1),
573 static const int arc_num_reloc_op
574 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
576 /* Structure for relaxable instruction that have to be swapped with a
577 smaller alternative instruction. */
578 struct arc_relaxable_ins
580 /* Mnemonic that should be checked. */
581 const char *mnemonic_r
;
583 /* Operands that should be checked.
584 Indexes of operands from operand array. */
585 enum rlx_operand_type operands
[6];
587 /* Flags that should be checked. */
588 unsigned flag_classes
[5];
590 /* Mnemonic (smaller) alternative to be used later for relaxation. */
591 const char *mnemonic_alt
;
593 /* Index of operand that generic relaxation has to check. */
596 /* Base subtype index used. */
597 enum arc_rlx_types subtype
;
600 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
601 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
602 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
606 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
607 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
608 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
613 /* ARC relaxation table. */
614 const relax_typeS md_relax_table
[] =
621 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL
),
622 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
626 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B
),
627 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
632 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6
),
633 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM
),
634 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
636 /* LD_S a, [b, u7] ->
637 LD<zz><.x><.aa><.di> a, [b, s9] ->
638 LD<zz><.x><.aa><.di> a, [b, limm] */
639 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9
),
640 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM
),
641 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE
),
646 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12
),
647 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM
),
648 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
652 SUB<.f> a, b, limm. */
653 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6
),
654 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM
),
655 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
657 /* MPY<.f> a, b, u6 ->
658 MPY<.f> a, b, limm. */
659 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM
),
660 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
662 /* MOV<.f><.cc> b, u6 ->
663 MOV<.f><.cc> b, limm. */
664 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM
),
665 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
667 /* ADD<.f><.cc> b, b, u6 ->
668 ADD<.f><.cc> b, b, limm. */
669 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM
),
670 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
673 /* Order of this table's entries matters! */
674 const struct arc_relaxable_ins arc_relaxable_insns
[] =
676 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
677 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
678 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
679 2, ARC_RLX_ADD_RRU6
},
680 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
682 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
684 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
685 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
686 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
687 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
688 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
689 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
690 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
691 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
693 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
695 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
699 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
701 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
702 symbolS
* GOT_symbol
= 0;
704 /* Set to TRUE when we assemble instructions. */
705 static bfd_boolean assembling_insn
= FALSE
;
707 /* List with attributes set explicitly. */
708 static bfd_boolean attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
710 /* Functions implementation. */
712 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
713 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
714 are no matching entries in ARC_OPCODE_HASH. */
716 static const struct arc_opcode_hash_entry
*
717 arc_find_opcode (const char *name
)
719 const struct arc_opcode_hash_entry
*entry
;
721 entry
= hash_find (arc_opcode_hash
, name
);
725 /* Initialise the iterator ITER. */
728 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
734 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
735 calls to this function. Return NULL when all ARC_OPCODE entries have
738 static const struct arc_opcode
*
739 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
740 struct arc_opcode_hash_entry_iterator
*iter
)
742 if (iter
->opcode
== NULL
&& iter
->index
== 0)
744 gas_assert (entry
->count
> 0);
745 iter
->opcode
= entry
->opcode
[iter
->index
];
747 else if (iter
->opcode
!= NULL
)
749 const char *old_name
= iter
->opcode
->name
;
752 if (iter
->opcode
->name
== NULL
753 || strcmp (old_name
, iter
->opcode
->name
) != 0)
756 if (iter
->index
== entry
->count
)
759 iter
->opcode
= entry
->opcode
[iter
->index
];
766 /* Insert an opcode into opcode hash structure. */
769 arc_insert_opcode (const struct arc_opcode
*opcode
)
771 const char *name
, *retval
;
772 struct arc_opcode_hash_entry
*entry
;
775 entry
= hash_find (arc_opcode_hash
, name
);
778 entry
= XNEW (struct arc_opcode_hash_entry
);
780 entry
->opcode
= NULL
;
782 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
784 as_fatal (_("internal error: can't hash opcode '%s': %s"),
788 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
791 if (entry
->opcode
== NULL
)
792 as_fatal (_("Virtual memory exhausted"));
794 entry
->opcode
[entry
->count
] = opcode
;
799 /* Like md_number_to_chars but for middle-endian values. The 4-byte limm
800 value, is encoded as 'middle-endian' for a little-endian target. This
801 function is used for regular 4, 6, and 8 byte instructions as well. */
804 md_number_to_chars_midend (char *buf
, unsigned long long val
, int n
)
809 md_number_to_chars (buf
, val
, n
);
812 md_number_to_chars (buf
, (val
& 0xffff00000000) >> 32, 2);
813 md_number_to_chars_midend (buf
+ 2, (val
& 0xffffffff), 4);
816 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
817 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
820 md_number_to_chars_midend (buf
, (val
& 0xffffffff00000000) >> 32, 4);
821 md_number_to_chars_midend (buf
+ 4, (val
& 0xffffffff), 4);
828 /* Check if a feature is allowed for a specific CPU. */
831 arc_check_feature (void)
835 if (!selected_cpu
.features
836 || !selected_cpu
.name
)
839 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
840 if ((selected_cpu
.features
& feature_list
[i
].feature
)
841 && !(selected_cpu
.flags
& feature_list
[i
].cpus
))
842 as_bad (_("invalid %s option for %s cpu"), feature_list
[i
].name
,
845 for (i
= 0; i
< ARRAY_SIZE (conflict_list
); i
++)
846 if ((selected_cpu
.features
& conflict_list
[i
]) == conflict_list
[i
])
847 as_bad(_("conflicting ISA extension attributes."));
850 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
851 the relevant static global variables. Parameter SEL describes where
852 this selection originated from. */
855 arc_select_cpu (const char *arg
, enum mach_selection_type sel
)
859 /* We should only set a default if we've not made a selection from some
861 gas_assert (sel
!= MACH_SELECTION_FROM_DEFAULT
862 || mach_selection_mode
== MACH_SELECTION_NONE
);
864 if ((mach_selection_mode
== MACH_SELECTION_FROM_CPU_DIRECTIVE
)
865 && (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
))
866 as_bad (_("Multiple .cpu directives found"));
868 /* Look for a matching entry in CPU_TYPES array. */
869 for (i
= 0; cpu_types
[i
].name
; ++i
)
871 if (!strcasecmp (cpu_types
[i
].name
, arg
))
873 /* If a previous selection was made on the command line, then we
874 allow later selections on the command line to override earlier
875 ones. However, a selection from a '.cpu NAME' directive must
876 match the command line selection, or we give a warning. */
877 if (mach_selection_mode
== MACH_SELECTION_FROM_COMMAND_LINE
)
879 gas_assert (sel
== MACH_SELECTION_FROM_COMMAND_LINE
880 || sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
);
881 if (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
882 && selected_cpu
.mach
!= cpu_types
[i
].mach
)
884 as_warn (_("Command-line value overrides \".cpu\" directive"));
889 /* Initialise static global data about selected machine type. */
890 selected_cpu
.flags
= cpu_types
[i
].flags
;
891 selected_cpu
.name
= cpu_types
[i
].name
;
892 selected_cpu
.features
= cpu_types
[i
].features
| cl_features
;
893 selected_cpu
.mach
= cpu_types
[i
].mach
;
894 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_MACH_MSK
)
895 | cpu_types
[i
].eflags
);
900 if (!cpu_types
[i
].name
)
901 as_fatal (_("unknown architecture: %s\n"), arg
);
903 /* Check if set features are compatible with the chosen CPU. */
904 arc_check_feature ();
906 mach_selection_mode
= sel
;
909 /* Here ends all the ARCompact extension instruction assembling
913 arc_extra_reloc (int r_type
)
916 symbolS
*sym
, *lab
= NULL
;
918 if (*input_line_pointer
== '@')
919 input_line_pointer
++;
920 c
= get_symbol_name (&sym_name
);
921 sym
= symbol_find_or_make (sym_name
);
922 restore_line_pointer (c
);
923 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
925 ++input_line_pointer
;
927 c
= get_symbol_name (&lab_name
);
928 lab
= symbol_find_or_make (lab_name
);
929 restore_line_pointer (c
);
932 /* These relocations exist as a mechanism for the compiler to tell the
933 linker how to patch the code if the tls model is optimised. However,
934 the relocation itself does not require any space within the assembler
935 fragment, and so we pass a size of 0.
937 The lines that generate these relocations look like this:
939 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
941 The '.tls_gd_ld @.tdata' is processed first and generates the
942 additional relocation, while the 'bl __tls_get_addr@plt' is processed
943 second and generates the additional branch.
945 It is possible that the additional relocation generated by the
946 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
947 while the 'bl __tls_get_addr@plt' will be generated as the first thing
948 in the next fragment. This will be fine; both relocations will still
949 appear to be at the same address in the generated object file.
950 However, this only works as the additional relocation is generated
951 with size of 0 bytes. */
953 = fix_new (frag_now
, /* Which frag? */
954 frag_now_fix (), /* Where in that frag? */
955 0, /* size: 1, 2, or 4 usually. */
956 sym
, /* X_add_symbol. */
957 0, /* X_add_number. */
958 FALSE
, /* TRUE if PC-relative relocation. */
959 r_type
/* Relocation type. */);
960 fixP
->fx_subsy
= lab
;
964 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
965 symbolS
*symbolP
, addressT size
)
970 if (*input_line_pointer
== ',')
972 align
= parse_align (1);
974 if (align
== (addressT
) -1)
989 bss_alloc (symbolP
, size
, align
);
990 S_CLEAR_EXTERNAL (symbolP
);
996 arc_lcomm (int ignore
)
998 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
1001 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
1004 /* Select the cpu we're assembling for. */
1007 arc_option (int ignore ATTRIBUTE_UNUSED
)
1011 const char *cpu_name
;
1013 c
= get_symbol_name (&cpu
);
1016 if ((!strcmp ("ARC600", cpu
))
1017 || (!strcmp ("ARC601", cpu
))
1018 || (!strcmp ("A6", cpu
)))
1019 cpu_name
= "arc600";
1020 else if ((!strcmp ("ARC700", cpu
))
1021 || (!strcmp ("A7", cpu
)))
1022 cpu_name
= "arc700";
1023 else if (!strcmp ("EM", cpu
))
1025 else if (!strcmp ("HS", cpu
))
1027 else if (!strcmp ("NPS400", cpu
))
1028 cpu_name
= "nps400";
1030 arc_select_cpu (cpu_name
, MACH_SELECTION_FROM_CPU_DIRECTIVE
);
1032 restore_line_pointer (c
);
1033 demand_empty_rest_of_line ();
1036 /* Smartly print an expression. */
1039 debug_exp (expressionS
*t
)
1041 const char *name ATTRIBUTE_UNUSED
;
1042 const char *namemd ATTRIBUTE_UNUSED
;
1044 pr_debug ("debug_exp: ");
1048 default: name
= "unknown"; break;
1049 case O_illegal
: name
= "O_illegal"; break;
1050 case O_absent
: name
= "O_absent"; break;
1051 case O_constant
: name
= "O_constant"; break;
1052 case O_symbol
: name
= "O_symbol"; break;
1053 case O_symbol_rva
: name
= "O_symbol_rva"; break;
1054 case O_register
: name
= "O_register"; break;
1055 case O_big
: name
= "O_big"; break;
1056 case O_uminus
: name
= "O_uminus"; break;
1057 case O_bit_not
: name
= "O_bit_not"; break;
1058 case O_logical_not
: name
= "O_logical_not"; break;
1059 case O_multiply
: name
= "O_multiply"; break;
1060 case O_divide
: name
= "O_divide"; break;
1061 case O_modulus
: name
= "O_modulus"; break;
1062 case O_left_shift
: name
= "O_left_shift"; break;
1063 case O_right_shift
: name
= "O_right_shift"; break;
1064 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
1065 case O_bit_or_not
: name
= "O_bit_or_not"; break;
1066 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
1067 case O_bit_and
: name
= "O_bit_and"; break;
1068 case O_add
: name
= "O_add"; break;
1069 case O_subtract
: name
= "O_subtract"; break;
1070 case O_eq
: name
= "O_eq"; break;
1071 case O_ne
: name
= "O_ne"; break;
1072 case O_lt
: name
= "O_lt"; break;
1073 case O_le
: name
= "O_le"; break;
1074 case O_ge
: name
= "O_ge"; break;
1075 case O_gt
: name
= "O_gt"; break;
1076 case O_logical_and
: name
= "O_logical_and"; break;
1077 case O_logical_or
: name
= "O_logical_or"; break;
1078 case O_index
: name
= "O_index"; break;
1079 case O_bracket
: name
= "O_bracket"; break;
1080 case O_colon
: name
= "O_colon"; break;
1081 case O_addrtype
: name
= "O_addrtype"; break;
1086 default: namemd
= "unknown"; break;
1087 case O_gotoff
: namemd
= "O_gotoff"; break;
1088 case O_gotpc
: namemd
= "O_gotpc"; break;
1089 case O_plt
: namemd
= "O_plt"; break;
1090 case O_sda
: namemd
= "O_sda"; break;
1091 case O_pcl
: namemd
= "O_pcl"; break;
1092 case O_tlsgd
: namemd
= "O_tlsgd"; break;
1093 case O_tlsie
: namemd
= "O_tlsie"; break;
1094 case O_tpoff9
: namemd
= "O_tpoff9"; break;
1095 case O_tpoff
: namemd
= "O_tpoff"; break;
1096 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
1097 case O_dtpoff
: namemd
= "O_dtpoff"; break;
1100 pr_debug ("%s (%s, %s, %d, %s)", name
,
1101 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
1102 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
1103 (int) t
->X_add_number
,
1104 (t
->X_md
) ? namemd
: "--");
1109 /* Parse the arguments to an opcode. */
1112 tokenize_arguments (char *str
,
1116 char *old_input_line_pointer
;
1117 bfd_boolean saw_comma
= FALSE
;
1118 bfd_boolean saw_arg
= FALSE
;
1123 const struct arc_reloc_op_tag
*r
;
1125 char *reloc_name
, c
;
1127 memset (tok
, 0, sizeof (*tok
) * ntok
);
1129 /* Save and restore input_line_pointer around this function. */
1130 old_input_line_pointer
= input_line_pointer
;
1131 input_line_pointer
= str
;
1133 while (*input_line_pointer
)
1136 switch (*input_line_pointer
)
1142 input_line_pointer
++;
1143 if (saw_comma
|| !saw_arg
)
1150 ++input_line_pointer
;
1152 if (!saw_arg
|| num_args
== ntok
)
1154 tok
->X_op
= O_bracket
;
1161 input_line_pointer
++;
1162 if (brk_lvl
|| num_args
== ntok
)
1165 tok
->X_op
= O_bracket
;
1171 input_line_pointer
++;
1172 if (!saw_arg
|| num_args
== ntok
)
1174 tok
->X_op
= O_colon
;
1181 /* We have labels, function names and relocations, all
1182 starting with @ symbol. Sort them out. */
1183 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1187 tok
->X_op
= O_symbol
;
1188 tok
->X_md
= O_absent
;
1190 if (*input_line_pointer
!= '@')
1191 goto normalsymbol
; /* This is not a relocation. */
1195 /* A relocation operand has the following form
1196 @identifier@relocation_type. The identifier is already
1198 if (tok
->X_op
!= O_symbol
)
1200 as_bad (_("No valid label relocation operand"));
1204 /* Parse @relocation_type. */
1205 input_line_pointer
++;
1206 c
= get_symbol_name (&reloc_name
);
1207 len
= input_line_pointer
- reloc_name
;
1210 as_bad (_("No relocation operand"));
1214 /* Go through known relocation and try to find a match. */
1215 r
= &arc_reloc_op
[0];
1216 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1217 if (len
== r
->length
1218 && memcmp (reloc_name
, r
->name
, len
) == 0)
1222 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1226 *input_line_pointer
= c
;
1227 SKIP_WHITESPACE_AFTER_NAME ();
1228 /* Extra check for TLS: base. */
1229 if (*input_line_pointer
== '@')
1232 if (tok
->X_op_symbol
!= NULL
1233 || tok
->X_op
!= O_symbol
)
1235 as_bad (_("Unable to parse TLS base: %s"),
1236 input_line_pointer
);
1239 input_line_pointer
++;
1241 c
= get_symbol_name (&sym_name
);
1242 base
= symbol_find_or_make (sym_name
);
1243 tok
->X_op
= O_subtract
;
1244 tok
->X_op_symbol
= base
;
1245 restore_line_pointer (c
);
1246 tmpE
.X_add_number
= 0;
1248 if ((*input_line_pointer
!= '+')
1249 && (*input_line_pointer
!= '-'))
1251 tmpE
.X_add_number
= 0;
1255 /* Parse the constant of a complex relocation expression
1256 like @identifier@reloc +/- const. */
1257 if (! r
->complex_expr
)
1259 as_bad (_("@%s is not a complex relocation."), r
->name
);
1263 if (tmpE
.X_op
!= O_constant
)
1265 as_bad (_("Bad expression: @%s + %s."),
1266 r
->name
, input_line_pointer
);
1272 tok
->X_add_number
= tmpE
.X_add_number
;
1283 /* Can be a register. */
1284 ++input_line_pointer
;
1288 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1291 tok
->X_op
= O_absent
;
1292 tok
->X_md
= O_absent
;
1295 /* Legacy: There are cases when we have
1296 identifier@relocation_type, if it is the case parse the
1297 relocation type as well. */
1298 if (*input_line_pointer
== '@')
1304 if (tok
->X_op
== O_illegal
1305 || tok
->X_op
== O_absent
1306 || num_args
== ntok
)
1318 if (saw_comma
|| brk_lvl
)
1320 input_line_pointer
= old_input_line_pointer
;
1326 as_bad (_("Brackets in operand field incorrect"));
1328 as_bad (_("extra comma"));
1330 as_bad (_("missing argument"));
1332 as_bad (_("missing comma or colon"));
1333 input_line_pointer
= old_input_line_pointer
;
1337 /* Parse the flags to a structure. */
1340 tokenize_flags (const char *str
,
1341 struct arc_flags flags
[],
1344 char *old_input_line_pointer
;
1345 bfd_boolean saw_flg
= FALSE
;
1346 bfd_boolean saw_dot
= FALSE
;
1350 memset (flags
, 0, sizeof (*flags
) * nflg
);
1352 /* Save and restore input_line_pointer around this function. */
1353 old_input_line_pointer
= input_line_pointer
;
1354 input_line_pointer
= (char *) str
;
1356 while (*input_line_pointer
)
1358 switch (*input_line_pointer
)
1365 input_line_pointer
++;
1373 if (saw_flg
&& !saw_dot
)
1376 if (num_flags
>= nflg
)
1379 flgnamelen
= strspn (input_line_pointer
,
1380 "abcdefghijklmnopqrstuvwxyz0123456789");
1381 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1384 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1386 input_line_pointer
+= flgnamelen
;
1396 input_line_pointer
= old_input_line_pointer
;
1401 as_bad (_("extra dot"));
1403 as_bad (_("unrecognized flag"));
1405 as_bad (_("failed to parse flags"));
1406 input_line_pointer
= old_input_line_pointer
;
1410 /* Apply the fixups in order. */
1413 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1417 for (i
= 0; i
< insn
->nfixups
; i
++)
1419 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1420 int size
, pcrel
, offset
= 0;
1422 /* FIXME! the reloc size is wrong in the BFD file.
1423 When it is fixed please delete me. */
1424 size
= ((insn
->len
== 2) && !fixup
->islong
) ? 2 : 4;
1429 /* Some fixups are only used internally, thus no howto. */
1430 if ((int) fixup
->reloc
== 0)
1431 as_fatal (_("Unhandled reloc type"));
1433 if ((int) fixup
->reloc
< 0)
1435 /* FIXME! the reloc size is wrong in the BFD file.
1436 When it is fixed please enable me.
1437 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
1438 pcrel
= fixup
->pcrel
;
1442 reloc_howto_type
*reloc_howto
=
1443 bfd_reloc_type_lookup (stdoutput
,
1444 (bfd_reloc_code_real_type
) fixup
->reloc
);
1445 gas_assert (reloc_howto
);
1447 /* FIXME! the reloc size is wrong in the BFD file.
1448 When it is fixed please enable me.
1449 size = bfd_get_reloc_size (reloc_howto); */
1450 pcrel
= reloc_howto
->pc_relative
;
1453 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1455 fragP
->fr_file
, fragP
->fr_line
,
1456 (fixup
->reloc
< 0) ? "Internal" :
1457 bfd_get_reloc_code_name (fixup
->reloc
),
1460 fix_new_exp (fragP
, fix
+ offset
,
1461 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1463 /* Check for ZOLs, and update symbol info if any. */
1464 if (LP_INSN (insn
->insn
))
1466 gas_assert (fixup
->exp
.X_add_symbol
);
1467 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1472 /* Actually output an instruction with its fixup. */
1475 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1480 pr_debug ("Emit insn : 0x%llx\n", insn
->insn
);
1481 pr_debug ("\tLength : 0x%d\n", insn
->len
);
1482 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1484 /* Write out the instruction. */
1485 total_len
= insn
->len
+ (insn
->has_limm
? 4 : 0);
1487 f
= frag_more (total_len
);
1489 md_number_to_chars_midend(f
, insn
->insn
, insn
->len
);
1492 md_number_to_chars_midend (f
+ insn
->len
, insn
->limm
, 4);
1493 dwarf2_emit_insn (total_len
);
1496 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1500 emit_insn1 (struct arc_insn
*insn
)
1502 /* How frag_var's args are currently configured:
1503 - rs_machine_dependent, to dictate it's a relaxation frag.
1504 - FRAG_MAX_GROWTH, maximum size of instruction
1505 - 0, variable size that might grow...unused by generic relaxation.
1506 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1507 - s, opand expression.
1508 - 0, offset but it's unused.
1509 - 0, opcode but it's unused. */
1510 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1511 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1513 if (frag_room () < FRAG_MAX_GROWTH
)
1515 /* Handle differently when frag literal memory is exhausted.
1516 This is used because when there's not enough memory left in
1517 the current frag, a new frag is created and the information
1518 we put into frag_now->tc_frag_data is disregarded. */
1520 struct arc_relax_type relax_info_copy
;
1521 relax_substateT subtype
= frag_now
->fr_subtype
;
1523 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1524 sizeof (struct arc_relax_type
));
1526 frag_wane (frag_now
);
1527 frag_grow (FRAG_MAX_GROWTH
);
1529 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1530 sizeof (struct arc_relax_type
));
1532 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1536 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1537 frag_now
->fr_subtype
, s
, 0, 0);
1541 emit_insn (struct arc_insn
*insn
)
1546 emit_insn0 (insn
, NULL
, FALSE
);
1549 /* Check whether a symbol involves a register. */
1552 contains_register (symbolS
*sym
)
1556 expressionS
*ex
= symbol_get_value_expression (sym
);
1558 return ((O_register
== ex
->X_op
)
1559 && !contains_register (ex
->X_add_symbol
)
1560 && !contains_register (ex
->X_op_symbol
));
1566 /* Returns the register number within a symbol. */
1569 get_register (symbolS
*sym
)
1571 if (!contains_register (sym
))
1574 expressionS
*ex
= symbol_get_value_expression (sym
);
1575 return regno (ex
->X_add_number
);
1578 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1579 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1582 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1589 case BFD_RELOC_ARC_SDA_LDST
:
1590 case BFD_RELOC_ARC_SDA_LDST1
:
1591 case BFD_RELOC_ARC_SDA_LDST2
:
1592 case BFD_RELOC_ARC_SDA16_LD
:
1593 case BFD_RELOC_ARC_SDA16_LD1
:
1594 case BFD_RELOC_ARC_SDA16_LD2
:
1595 case BFD_RELOC_ARC_SDA16_ST2
:
1596 case BFD_RELOC_ARC_SDA32_ME
:
1603 /* Allocates a tok entry. */
1606 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1608 if (ntok
> MAX_INSN_ARGS
- 2)
1609 return 0; /* No space left. */
1612 return 0; /* Incorrect args. */
1614 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1617 return 1; /* Success. */
1618 return allocate_tok (tok
, ntok
- 1, cidx
);
1621 /* Check if an particular ARC feature is enabled. */
1624 check_cpu_feature (insn_subclass_t sc
)
1626 if (is_code_density_p (sc
) && !(selected_cpu
.features
& CD
))
1629 if (is_spfp_p (sc
) && !(selected_cpu
.features
& SPX
))
1632 if (is_dpfp_p (sc
) && !(selected_cpu
.features
& DPX
))
1635 if (is_fpuda_p (sc
) && !(selected_cpu
.features
& DPA
))
1638 if (is_nps400_p (sc
) && !(selected_cpu
.features
& NPS400
))
1644 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1645 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1646 array and returns TRUE if the flag operands all match, otherwise,
1647 returns FALSE, in which case the FIRST_PFLAG array may have been
1651 parse_opcode_flags (const struct arc_opcode
*opcode
,
1653 struct arc_flags
*first_pflag
)
1656 const unsigned char *flgidx
;
1659 for (i
= 0; i
< nflgs
; i
++)
1660 first_pflag
[i
].flgp
= NULL
;
1662 /* Check the flags. Iterate over the valid flag classes. */
1663 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1665 /* Get a valid flag class. */
1666 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1667 const unsigned *flgopridx
;
1669 struct arc_flags
*pflag
= NULL
;
1671 /* Check if opcode has implicit flag classes. */
1672 if (cl_flags
->flag_class
& F_CLASS_IMPLICIT
)
1675 /* Check for extension conditional codes. */
1676 if (ext_condcode
.arc_ext_condcode
1677 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1679 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1682 pflag
= first_pflag
;
1683 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1685 if (!strcmp (pf
->name
, pflag
->name
))
1687 if (pflag
->flgp
!= NULL
)
1700 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1702 const struct arc_flag_operand
*flg_operand
;
1704 pflag
= first_pflag
;
1705 flg_operand
= &arc_flag_operands
[*flgopridx
];
1706 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1708 /* Match against the parsed flags. */
1709 if (!strcmp (flg_operand
->name
, pflag
->name
))
1711 if (pflag
->flgp
!= NULL
)
1714 pflag
->flgp
= flg_operand
;
1716 break; /* goto next flag class and parsed flag. */
1721 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1723 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1727 /* Did I check all the parsed flags? */
1728 return lnflg
? FALSE
: TRUE
;
1732 /* Search forward through all variants of an opcode looking for a
1735 static const struct arc_opcode
*
1736 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1739 struct arc_flags
*first_pflag
,
1742 const char **errmsg
)
1744 const struct arc_opcode
*opcode
;
1745 struct arc_opcode_hash_entry_iterator iter
;
1747 int got_cpu_match
= 0;
1748 expressionS bktok
[MAX_INSN_ARGS
];
1752 arc_opcode_hash_entry_iterator_init (&iter
);
1753 memset (&emptyE
, 0, sizeof (emptyE
));
1754 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1757 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1759 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1761 const unsigned char *opidx
;
1763 const expressionS
*t
= &emptyE
;
1765 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
1766 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1768 /* Don't match opcodes that don't exist on this
1770 if (!(opcode
->cpu
& selected_cpu
.flags
))
1773 if (!check_cpu_feature (opcode
->subclass
))
1779 /* Check the operands. */
1780 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1782 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1784 /* Only take input from real operands. */
1785 if (ARC_OPERAND_IS_FAKE (operand
))
1788 /* When we expect input, make sure we have it. */
1792 /* Match operand type with expression type. */
1793 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1795 case ARC_OPERAND_ADDRTYPE
:
1799 /* Check to be an address type. */
1800 if (tok
[tokidx
].X_op
!= O_addrtype
)
1803 /* All address type operands need to have an insert
1804 method in order to check that we have the correct
1806 gas_assert (operand
->insert
!= NULL
);
1807 (*operand
->insert
) (0, tok
[tokidx
].X_add_number
,
1809 if (*errmsg
!= NULL
)
1814 case ARC_OPERAND_IR
:
1815 /* Check to be a register. */
1816 if ((tok
[tokidx
].X_op
!= O_register
1817 || !is_ir_num (tok
[tokidx
].X_add_number
))
1818 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1821 /* If expect duplicate, make sure it is duplicate. */
1822 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1824 /* Check for duplicate. */
1825 if (t
->X_op
!= O_register
1826 || !is_ir_num (t
->X_add_number
)
1827 || (regno (t
->X_add_number
) !=
1828 regno (tok
[tokidx
].X_add_number
)))
1832 /* Special handling? */
1833 if (operand
->insert
)
1836 (*operand
->insert
)(0,
1837 regno (tok
[tokidx
].X_add_number
),
1841 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1843 /* Missing argument, create one. */
1844 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1847 tok
[tokidx
].X_op
= O_absent
;
1858 case ARC_OPERAND_BRAKET
:
1859 /* Check if bracket is also in opcode table as
1861 if (tok
[tokidx
].X_op
!= O_bracket
)
1865 case ARC_OPERAND_COLON
:
1866 /* Check if colon is also in opcode table as operand. */
1867 if (tok
[tokidx
].X_op
!= O_colon
)
1871 case ARC_OPERAND_LIMM
:
1872 case ARC_OPERAND_SIGNED
:
1873 case ARC_OPERAND_UNSIGNED
:
1874 switch (tok
[tokidx
].X_op
)
1882 /* Got an (too) early bracket, check if it is an
1883 ignored operand. N.B. This procedure works only
1884 when bracket is the last operand! */
1885 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1887 /* Insert the missing operand. */
1888 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1891 tok
[tokidx
].X_op
= O_absent
;
1898 const struct arc_aux_reg
*auxr
;
1900 if (opcode
->insn_class
!= AUXREG
)
1902 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1904 auxr
= hash_find (arc_aux_hash
, p
);
1907 /* We modify the token array here, safe in the
1908 knowledge, that if this was the wrong
1909 choice then the original contents will be
1910 restored from BKTOK. */
1911 tok
[tokidx
].X_op
= O_constant
;
1912 tok
[tokidx
].X_add_number
= auxr
->address
;
1913 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1916 if (tok
[tokidx
].X_op
!= O_constant
)
1921 /* Check the range. */
1922 if (operand
->bits
!= 32
1923 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1925 offsetT min
, max
, val
;
1926 val
= tok
[tokidx
].X_add_number
;
1928 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1930 max
= (1 << (operand
->bits
- 1)) - 1;
1931 min
= -(1 << (operand
->bits
- 1));
1935 max
= (1 << operand
->bits
) - 1;
1939 if (val
< min
|| val
> max
)
1942 /* Check alignments. */
1943 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1947 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1951 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1953 if (operand
->insert
)
1956 (*operand
->insert
)(0,
1957 tok
[tokidx
].X_add_number
,
1962 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1968 /* Check if it is register range. */
1969 if ((tok
[tokidx
].X_add_number
== 0)
1970 && contains_register (tok
[tokidx
].X_add_symbol
)
1971 && contains_register (tok
[tokidx
].X_op_symbol
))
1975 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1977 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1978 if (operand
->insert
)
1981 (*operand
->insert
)(0,
1994 if (operand
->default_reloc
== 0)
1995 goto match_failed
; /* The operand needs relocation. */
1997 /* Relocs requiring long immediate. FIXME! make it
1998 generic and move it to a function. */
1999 switch (tok
[tokidx
].X_md
)
2008 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
2012 if (!generic_reloc_p (operand
->default_reloc
))
2020 /* If expect duplicate, make sure it is duplicate. */
2021 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
2023 if (t
->X_op
== O_illegal
2024 || t
->X_op
== O_absent
2025 || t
->X_op
== O_register
2026 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
2033 /* Everything else should have been fake. */
2041 /* Setup ready for flag parsing. */
2042 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
2046 /* Possible match -- did we use all of our input? */
2056 /* Restore the original parameters. */
2057 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
2062 *pcpumatch
= got_cpu_match
;
2067 /* Swap operand tokens. */
2070 swap_operand (expressionS
*operand_array
,
2072 unsigned destination
)
2074 expressionS cpy_operand
;
2075 expressionS
*src_operand
;
2076 expressionS
*dst_operand
;
2079 if (source
== destination
)
2082 src_operand
= &operand_array
[source
];
2083 dst_operand
= &operand_array
[destination
];
2084 size
= sizeof (expressionS
);
2086 /* Make copy of operand to swap with and swap. */
2087 memcpy (&cpy_operand
, dst_operand
, size
);
2088 memcpy (dst_operand
, src_operand
, size
);
2089 memcpy (src_operand
, &cpy_operand
, size
);
2092 /* Check if *op matches *tok type.
2093 Returns FALSE if they don't match, TRUE if they match. */
2096 pseudo_operand_match (const expressionS
*tok
,
2097 const struct arc_operand_operation
*op
)
2099 offsetT min
, max
, val
;
2101 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
2107 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
2109 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
2111 val
= tok
->X_add_number
+ op
->count
;
2112 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
2114 max
= (1 << (operand_real
->bits
- 1)) - 1;
2115 min
= -(1 << (operand_real
->bits
- 1));
2119 max
= (1 << operand_real
->bits
) - 1;
2122 if (min
<= val
&& val
<= max
)
2128 /* Handle all symbols as long immediates or signed 9. */
2129 if (operand_real
->flags
& ARC_OPERAND_LIMM
2130 || ((operand_real
->flags
& ARC_OPERAND_SIGNED
)
2131 && operand_real
->bits
== 9))
2136 if (operand_real
->flags
& ARC_OPERAND_IR
)
2141 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2152 /* Find pseudo instruction in array. */
2154 static const struct arc_pseudo_insn
*
2155 find_pseudo_insn (const char *opname
,
2157 const expressionS
*tok
)
2159 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2160 const struct arc_operand_operation
*op
;
2164 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2166 pseudo_insn
= &arc_pseudo_insns
[i
];
2167 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2169 op
= pseudo_insn
->operand
;
2170 for (j
= 0; j
< ntok
; ++j
)
2171 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2174 /* Found the right instruction. */
2182 /* Assumes the expressionS *tok is of sufficient size. */
2184 static const struct arc_opcode_hash_entry
*
2185 find_special_case_pseudo (const char *opname
,
2189 struct arc_flags
*pflags
)
2191 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2192 const struct arc_operand_operation
*operand_pseudo
;
2193 const struct arc_operand
*operand_real
;
2195 char construct_operand
[MAX_CONSTR_STR
];
2197 /* Find whether opname is in pseudo instruction array. */
2198 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2200 if (pseudo_insn
== NULL
)
2203 /* Handle flag, Limited to one flag at the moment. */
2204 if (pseudo_insn
->flag_r
!= NULL
)
2205 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2206 MAX_INSN_FLGS
- *nflgs
);
2208 /* Handle operand operations. */
2209 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2211 operand_pseudo
= &pseudo_insn
->operand
[i
];
2212 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2214 if (operand_real
->flags
& ARC_OPERAND_BRAKET
2215 && !operand_pseudo
->needs_insert
)
2218 /* Has to be inserted (i.e. this token does not exist yet). */
2219 if (operand_pseudo
->needs_insert
)
2221 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2223 tok
[i
].X_op
= O_bracket
;
2228 /* Check if operand is a register or constant and handle it
2230 if (operand_real
->flags
& ARC_OPERAND_IR
)
2231 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2232 operand_pseudo
->count
);
2234 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2235 operand_pseudo
->count
);
2237 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2241 else if (operand_pseudo
->count
)
2243 /* Operand number has to be adjusted accordingly (by operand
2245 switch (tok
[i
].X_op
)
2248 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2261 /* Swap operands if necessary. Only supports one swap at the
2263 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2265 operand_pseudo
= &pseudo_insn
->operand
[i
];
2267 if (operand_pseudo
->swap_operand_idx
== i
)
2270 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2272 /* Prevent a swap back later by breaking out. */
2276 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2279 static const struct arc_opcode_hash_entry
*
2280 find_special_case_flag (const char *opname
,
2282 struct arc_flags
*pflags
)
2286 unsigned flag_idx
, flag_arr_idx
;
2287 size_t flaglen
, oplen
;
2288 const struct arc_flag_special
*arc_flag_special_opcode
;
2289 const struct arc_opcode_hash_entry
*entry
;
2291 /* Search for special case instruction. */
2292 for (i
= 0; i
< arc_num_flag_special
; i
++)
2294 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2295 oplen
= strlen (arc_flag_special_opcode
->name
);
2297 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2300 /* Found a potential special case instruction, now test for
2302 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2304 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2306 break; /* End of array, nothing found. */
2308 flagnm
= arc_flag_operands
[flag_idx
].name
;
2309 flaglen
= strlen (flagnm
);
2310 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2312 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2314 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2316 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2317 pflags
[*nflgs
].name
[flaglen
] = '\0';
2326 /* Used to find special case opcode. */
2328 static const struct arc_opcode_hash_entry
*
2329 find_special_case (const char *opname
,
2331 struct arc_flags
*pflags
,
2335 const struct arc_opcode_hash_entry
*entry
;
2337 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2340 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2345 /* Autodetect cpu attribute list. */
2348 autodetect_attributes (const struct arc_opcode
*opcode
,
2349 const expressionS
*tok
,
2357 } mpy_list
[] = {{ MPY1E
, 1 }, { MPY6E
, 6 }, { MPY7E
, 7 }, { MPY8E
, 8 },
2360 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
2361 if (opcode
->subclass
== feature_list
[i
].feature
)
2362 selected_cpu
.features
|= feature_list
[i
].feature
;
2364 for (i
= 0; i
< ARRAY_SIZE (mpy_list
); i
++)
2365 if (opcode
->subclass
== mpy_list
[i
].feature
)
2366 mpy_option
= mpy_list
[i
].encoding
;
2368 for (i
= 0; i
< (unsigned) ntok
; i
++)
2370 switch (tok
[i
].X_md
)
2394 /* Given an opcode name, pre-tockenized set of argumenst and the
2395 opcode flags, take it all the way through emission. */
2398 assemble_tokens (const char *opname
,
2401 struct arc_flags
*pflags
,
2404 bfd_boolean found_something
= FALSE
;
2405 const struct arc_opcode_hash_entry
*entry
;
2407 const char *errmsg
= NULL
;
2409 /* Search opcodes. */
2410 entry
= arc_find_opcode (opname
);
2412 /* Couldn't find opcode conventional way, try special cases. */
2414 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2418 const struct arc_opcode
*opcode
;
2420 pr_debug ("%s:%d: assemble_tokens: %s\n",
2421 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2422 found_something
= TRUE
;
2423 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2424 nflgs
, &cpumatch
, &errmsg
);
2427 struct arc_insn insn
;
2429 autodetect_attributes (opcode
, tok
, ntok
);
2430 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2436 if (found_something
)
2440 as_bad (_("%s for instruction '%s'"), errmsg
, opname
);
2442 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2444 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2448 as_bad (_("unknown opcode '%s'"), opname
);
2451 /* The public interface to the instruction assembler. */
2454 md_assemble (char *str
)
2457 expressionS tok
[MAX_INSN_ARGS
];
2460 struct arc_flags flags
[MAX_INSN_FLGS
];
2462 /* Split off the opcode. */
2463 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2464 opname
= xmemdup0 (str
, opnamelen
);
2466 /* Signalize we are assembling the instructions. */
2467 assembling_insn
= TRUE
;
2469 /* Tokenize the flags. */
2470 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2472 as_bad (_("syntax error"));
2476 /* Scan up to the end of the mnemonic which must end in space or end
2479 for (; *str
!= '\0'; str
++)
2483 /* Tokenize the rest of the line. */
2484 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2486 as_bad (_("syntax error"));
2490 /* Finish it off. */
2491 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2492 assembling_insn
= FALSE
;
2495 /* Callback to insert a register into the hash table. */
2498 declare_register (const char *name
, int number
)
2501 symbolS
*regS
= symbol_create (name
, reg_section
,
2502 number
, &zero_address_frag
);
2504 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2506 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2510 /* Construct symbols for each of the general registers. */
2513 declare_register_set (void)
2516 for (i
= 0; i
< 64; ++i
)
2520 sprintf (name
, "r%d", i
);
2521 declare_register (name
, i
);
2522 if ((i
& 0x01) == 0)
2524 sprintf (name
, "r%dr%d", i
, i
+1);
2525 declare_register (name
, i
);
2530 /* Construct a symbol for an address type. */
2533 declare_addrtype (const char *name
, int number
)
2536 symbolS
*addrtypeS
= symbol_create (name
, undefined_section
,
2537 number
, &zero_address_frag
);
2539 err
= hash_insert (arc_addrtype_hash
, S_GET_NAME (addrtypeS
),
2540 (void *) addrtypeS
);
2542 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2546 /* Port-specific assembler initialization. This function is called
2547 once, at assembler startup time. */
2552 const struct arc_opcode
*opcode
= arc_opcodes
;
2554 if (mach_selection_mode
== MACH_SELECTION_NONE
)
2555 arc_select_cpu (TARGET_WITH_CPU
, MACH_SELECTION_FROM_DEFAULT
);
2557 /* The endianness can be chosen "at the factory". */
2558 target_big_endian
= byte_order
== BIG_ENDIAN
;
2560 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
2561 as_warn (_("could not set architecture and machine"));
2563 /* Set elf header flags. */
2564 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
2566 /* Set up a hash table for the instructions. */
2567 arc_opcode_hash
= hash_new ();
2568 if (arc_opcode_hash
== NULL
)
2569 as_fatal (_("Virtual memory exhausted"));
2571 /* Initialize the hash table with the insns. */
2574 const char *name
= opcode
->name
;
2576 arc_insert_opcode (opcode
);
2578 while (++opcode
&& opcode
->name
2579 && (opcode
->name
== name
2580 || !strcmp (opcode
->name
, name
)))
2582 }while (opcode
->name
);
2584 /* Register declaration. */
2585 arc_reg_hash
= hash_new ();
2586 if (arc_reg_hash
== NULL
)
2587 as_fatal (_("Virtual memory exhausted"));
2589 declare_register_set ();
2590 declare_register ("gp", 26);
2591 declare_register ("fp", 27);
2592 declare_register ("sp", 28);
2593 declare_register ("ilink", 29);
2594 declare_register ("ilink1", 29);
2595 declare_register ("ilink2", 30);
2596 declare_register ("blink", 31);
2598 /* XY memory registers. */
2599 declare_register ("x0_u0", 32);
2600 declare_register ("x0_u1", 33);
2601 declare_register ("x1_u0", 34);
2602 declare_register ("x1_u1", 35);
2603 declare_register ("x2_u0", 36);
2604 declare_register ("x2_u1", 37);
2605 declare_register ("x3_u0", 38);
2606 declare_register ("x3_u1", 39);
2607 declare_register ("y0_u0", 40);
2608 declare_register ("y0_u1", 41);
2609 declare_register ("y1_u0", 42);
2610 declare_register ("y1_u1", 43);
2611 declare_register ("y2_u0", 44);
2612 declare_register ("y2_u1", 45);
2613 declare_register ("y3_u0", 46);
2614 declare_register ("y3_u1", 47);
2615 declare_register ("x0_nu", 48);
2616 declare_register ("x1_nu", 49);
2617 declare_register ("x2_nu", 50);
2618 declare_register ("x3_nu", 51);
2619 declare_register ("y0_nu", 52);
2620 declare_register ("y1_nu", 53);
2621 declare_register ("y2_nu", 54);
2622 declare_register ("y3_nu", 55);
2624 declare_register ("mlo", 57);
2625 declare_register ("mmid", 58);
2626 declare_register ("mhi", 59);
2628 declare_register ("acc1", 56);
2629 declare_register ("acc2", 57);
2631 declare_register ("lp_count", 60);
2632 declare_register ("pcl", 63);
2634 /* Initialize the last instructions. */
2635 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2637 /* Aux register declaration. */
2638 arc_aux_hash
= hash_new ();
2639 if (arc_aux_hash
== NULL
)
2640 as_fatal (_("Virtual memory exhausted"));
2642 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2644 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2648 if (!(auxr
->cpu
& selected_cpu
.flags
))
2651 if ((auxr
->subclass
!= NONE
)
2652 && !check_cpu_feature (auxr
->subclass
))
2655 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2657 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2658 auxr
->name
, retval
);
2661 /* Address type declaration. */
2662 arc_addrtype_hash
= hash_new ();
2663 if (arc_addrtype_hash
== NULL
)
2664 as_fatal (_("Virtual memory exhausted"));
2666 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD
);
2667 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID
);
2668 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD
);
2669 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD
);
2670 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD
);
2671 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM
);
2672 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA
);
2673 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD
);
2674 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD
);
2675 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD
);
2676 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID
);
2677 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD
);
2678 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM
);
2679 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD
);
2680 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA
);
2681 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD
);
2684 /* Write a value out to the object file, using the appropriate
2688 md_number_to_chars (char *buf
,
2692 if (target_big_endian
)
2693 number_to_chars_bigendian (buf
, val
, n
);
2695 number_to_chars_littleendian (buf
, val
, n
);
2698 /* Round up a section size to the appropriate boundary. */
2701 md_section_align (segT segment
,
2704 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2706 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2709 /* The location from which a PC relative jump should be calculated,
2710 given a PC relative reloc. */
2713 md_pcrel_from_section (fixS
*fixP
,
2716 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2718 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2720 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2721 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2722 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2724 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2726 /* The symbol is undefined (or is defined but not in this section).
2727 Let the linker figure it out. */
2731 if ((int) fixP
->fx_r_type
< 0)
2733 /* These are the "internal" relocations. Align them to
2734 32 bit boundary (PCL), for the moment. */
2739 switch (fixP
->fx_r_type
)
2741 case BFD_RELOC_ARC_PC32
:
2742 /* The hardware calculates relative to the start of the
2743 insn, but this relocation is relative to location of the
2744 LIMM, compensate. The base always needs to be
2745 subtracted by 4 as we do not support this type of PCrel
2746 relocation for short instructions. */
2749 case BFD_RELOC_ARC_PLT32
:
2750 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2751 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2752 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2753 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2755 case BFD_RELOC_ARC_S21H_PCREL
:
2756 case BFD_RELOC_ARC_S25H_PCREL
:
2757 case BFD_RELOC_ARC_S13_PCREL
:
2758 case BFD_RELOC_ARC_S21W_PCREL
:
2759 case BFD_RELOC_ARC_S25W_PCREL
:
2763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2764 _("unhandled reloc %s in md_pcrel_from_section"),
2765 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2770 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2771 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2772 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2773 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2774 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2779 /* Given a BFD relocation find the corresponding operand. */
2781 static const struct arc_operand
*
2782 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2786 for (i
= 0; i
< arc_num_operands
; i
++)
2787 if (arc_operands
[i
].default_reloc
== reloc
)
2788 return &arc_operands
[i
];
2792 /* Insert an operand value into an instruction. */
2794 static unsigned long long
2795 insert_operand (unsigned long long insn
,
2796 const struct arc_operand
*operand
,
2801 offsetT min
= 0, max
= 0;
2803 if (operand
->bits
!= 32
2804 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2805 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2807 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2809 max
= (1 << (operand
->bits
- 1)) - 1;
2810 min
= -(1 << (operand
->bits
- 1));
2814 max
= (1 << operand
->bits
) - 1;
2818 if (val
< min
|| val
> max
)
2819 as_bad_value_out_of_range (_("operand"),
2820 val
, min
, max
, file
, line
);
2823 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
2824 min
, val
, max
, insn
);
2826 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2828 as_bad_where (file
, line
,
2829 _("Unaligned operand. Needs to be 32bit aligned"));
2831 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2833 as_bad_where (file
, line
,
2834 _("Unaligned operand. Needs to be 16bit aligned"));
2836 if (operand
->insert
)
2838 const char *errmsg
= NULL
;
2840 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2842 as_warn_where (file
, line
, "%s", errmsg
);
2846 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2848 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2850 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2853 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2858 /* Apply a fixup to the object code. At this point all symbol values
2859 should be fully resolved, and we attempt to completely resolve the
2860 reloc. If we can not do that, we determine the correct reloc code
2861 and put it back in the fixup. To indicate that a fixup has been
2862 eliminated, set fixP->fx_done. */
2865 md_apply_fix (fixS
*fixP
,
2869 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2870 valueT value
= *valP
;
2872 symbolS
*fx_addsy
, *fx_subsy
;
2874 segT add_symbol_segment
= absolute_section
;
2875 segT sub_symbol_segment
= absolute_section
;
2876 const struct arc_operand
*operand
= NULL
;
2877 extended_bfd_reloc_code_real_type reloc
;
2879 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2880 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2881 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2882 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2885 fx_addsy
= fixP
->fx_addsy
;
2886 fx_subsy
= fixP
->fx_subsy
;
2891 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2895 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2896 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2897 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2899 resolve_symbol_value (fx_subsy
);
2900 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2902 if (sub_symbol_segment
== absolute_section
)
2904 /* The symbol is really a constant. */
2905 fx_offset
-= S_GET_VALUE (fx_subsy
);
2910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2911 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2912 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2913 segment_name (add_symbol_segment
),
2914 S_GET_NAME (fx_subsy
),
2915 segment_name (sub_symbol_segment
));
2921 && !S_IS_WEAK (fx_addsy
))
2923 if (add_symbol_segment
== seg
2926 value
+= S_GET_VALUE (fx_addsy
);
2927 value
-= md_pcrel_from_section (fixP
, seg
);
2929 fixP
->fx_pcrel
= FALSE
;
2931 else if (add_symbol_segment
== absolute_section
)
2933 value
= fixP
->fx_offset
;
2934 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2936 fixP
->fx_pcrel
= FALSE
;
2941 fixP
->fx_done
= TRUE
;
2946 && ((S_IS_DEFINED (fx_addsy
)
2947 && S_GET_SEGMENT (fx_addsy
) != seg
)
2948 || S_IS_WEAK (fx_addsy
)))
2949 value
+= md_pcrel_from_section (fixP
, seg
);
2951 switch (fixP
->fx_r_type
)
2953 case BFD_RELOC_ARC_32_ME
:
2954 /* This is a pc-relative value in a LIMM. Adjust it to the
2955 address of the instruction not to the address of the
2956 LIMM. Note: it is not any longer valid this affirmation as
2957 the linker consider ARC_PC32 a fixup to entire 64 bit
2959 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2962 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2964 case BFD_RELOC_ARC_PC32
:
2965 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2968 if ((int) fixP
->fx_r_type
< 0)
2969 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2970 _("PC relative relocation not allowed for (internal)"
2977 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2978 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2979 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2980 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2984 /* Now check for TLS relocations. */
2985 reloc
= fixP
->fx_r_type
;
2988 case BFD_RELOC_ARC_TLS_DTPOFF
:
2989 case BFD_RELOC_ARC_TLS_LE_32
:
2993 case BFD_RELOC_ARC_TLS_GD_GOT
:
2994 case BFD_RELOC_ARC_TLS_IE_GOT
:
2995 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2998 case BFD_RELOC_ARC_TLS_GD_LD
:
2999 gas_assert (!fixP
->fx_offset
);
3002 = (S_GET_VALUE (fixP
->fx_subsy
)
3003 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
3004 fixP
->fx_subsy
= NULL
;
3006 case BFD_RELOC_ARC_TLS_GD_CALL
:
3007 /* These two relocs are there just to allow ld to change the tls
3008 model for this symbol, by patching the code. The offset -
3009 and scale, if any - will be installed by the linker. */
3010 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3013 case BFD_RELOC_ARC_TLS_LE_S9
:
3014 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
3015 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3027 /* Adjust the value if we have a constant. */
3030 /* For hosts with longs bigger than 32-bits make sure that the top
3031 bits of a 32-bit negative value read in by the parser are set,
3032 so that the correct comparisons are made. */
3033 if (value
& 0x80000000)
3034 value
|= (-1UL << 31);
3036 reloc
= fixP
->fx_r_type
;
3044 case BFD_RELOC_ARC_32_PCREL
:
3045 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
3048 case BFD_RELOC_ARC_GOTPC32
:
3049 /* I cannot fix an GOTPC relocation because I need to relax it
3050 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3051 as_bad (_("Unsupported operation on reloc"));
3054 case BFD_RELOC_ARC_TLS_DTPOFF
:
3055 case BFD_RELOC_ARC_TLS_LE_32
:
3056 gas_assert (!fixP
->fx_addsy
);
3057 gas_assert (!fixP
->fx_subsy
);
3060 case BFD_RELOC_ARC_GOTOFF
:
3061 case BFD_RELOC_ARC_32_ME
:
3062 case BFD_RELOC_ARC_PC32
:
3063 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3066 case BFD_RELOC_ARC_PLT32
:
3067 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3070 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3071 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3074 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3075 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
3078 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3079 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3082 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3083 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
3086 case BFD_RELOC_ARC_S25W_PCREL
:
3087 case BFD_RELOC_ARC_S21W_PCREL
:
3088 case BFD_RELOC_ARC_S21H_PCREL
:
3089 case BFD_RELOC_ARC_S25H_PCREL
:
3090 case BFD_RELOC_ARC_S13_PCREL
:
3092 operand
= find_operand_for_reloc (reloc
);
3093 gas_assert (operand
);
3098 if ((int) fixP
->fx_r_type
>= 0)
3099 as_fatal (_("unhandled relocation type %s"),
3100 bfd_get_reloc_code_name (fixP
->fx_r_type
));
3102 /* The rest of these fixups needs to be completely resolved as
3104 if (fixP
->fx_addsy
!= 0
3105 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
3106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3107 _("non-absolute expression in constant field"));
3109 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
3110 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
3115 if (target_big_endian
)
3117 switch (fixP
->fx_size
)
3120 insn
= bfd_getb32 (fixpos
);
3123 insn
= bfd_getb16 (fixpos
);
3126 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3127 _("unknown fixup size"));
3133 switch (fixP
->fx_size
)
3136 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
3139 insn
= bfd_getl16 (fixpos
);
3142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3143 _("unknown fixup size"));
3147 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3148 fixP
->fx_file
, fixP
->fx_line
);
3150 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3153 /* Prepare machine-dependent frags for relaxation.
3155 Called just before relaxation starts. Any symbol that is now undefined
3156 will not become defined.
3158 Return the correct fr_subtype in the frag.
3160 Return the initial "guess for fr_var" to caller. The guess for fr_var
3161 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3162 or fr_var contributes to our returned value.
3164 Although it may not be explicit in the frag, pretend
3165 fr_var starts with a value. */
3168 md_estimate_size_before_relax (fragS
*fragP
,
3173 /* If the symbol is not located within the same section AND it's not
3174 an absolute section, use the maximum. OR if the symbol is a
3175 constant AND the insn is by nature not pc-rel, use the maximum.
3176 OR if the symbol is being equated against another symbol, use the
3177 maximum. OR if the symbol is weak use the maximum. */
3178 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3179 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3180 || (symbol_constant_p (fragP
->fr_symbol
)
3181 && !fragP
->tc_frag_data
.pcrel
)
3182 || symbol_equated_p (fragP
->fr_symbol
)
3183 || S_IS_WEAK (fragP
->fr_symbol
))
3185 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3186 ++fragP
->fr_subtype
;
3189 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3190 fragP
->fr_var
= growth
;
3192 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3193 fragP
->fr_file
, fragP
->fr_line
, growth
);
3198 /* Translate internal representation of relocation info to BFD target
3202 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3206 bfd_reloc_code_real_type code
;
3208 reloc
= XNEW (arelent
);
3209 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3210 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3211 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3213 /* Make sure none of our internal relocations make it this far.
3214 They'd better have been fully resolved by this point. */
3215 gas_assert ((int) fixP
->fx_r_type
> 0);
3217 code
= fixP
->fx_r_type
;
3219 /* if we have something like add gp, pcl,
3220 _GLOBAL_OFFSET_TABLE_@gotpc. */
3221 if (code
== BFD_RELOC_ARC_GOTPC32
3223 && fixP
->fx_addsy
== GOT_symbol
)
3224 code
= BFD_RELOC_ARC_GOTPC
;
3226 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3227 if (reloc
->howto
== NULL
)
3229 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3230 _("cannot represent `%s' relocation in object file"),
3231 bfd_get_reloc_code_name (code
));
3235 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3236 as_fatal (_("internal error? cannot generate `%s' relocation"),
3237 bfd_get_reloc_code_name (code
));
3239 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3241 reloc
->addend
= fixP
->fx_offset
;
3246 /* Perform post-processing of machine-dependent frags after relaxation.
3247 Called after relaxation is finished.
3248 In: Address of frag.
3249 fr_type == rs_machine_dependent.
3250 fr_subtype is what the address relaxed to.
3252 Out: Any fixS:s and constants are set up. */
3255 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3256 segT segment ATTRIBUTE_UNUSED
,
3259 const relax_typeS
*table_entry
;
3261 const struct arc_opcode
*opcode
;
3262 struct arc_insn insn
;
3264 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3266 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
3267 dest
= fragP
->fr_literal
+ fix
;
3268 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3270 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3271 "var: %"BFD_VMA_FMT
"d\n",
3272 fragP
->fr_file
, fragP
->fr_line
,
3273 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3275 if (fragP
->fr_subtype
<= 0
3276 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3277 as_fatal (_("no relaxation found for this instruction."));
3279 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3281 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3282 relax_arg
->nflg
, &insn
);
3284 apply_fixups (&insn
, fragP
, fix
);
3286 size
= insn
.len
+ (insn
.has_limm
? 4 : 0);
3287 gas_assert (table_entry
->rlx_length
== size
);
3288 emit_insn0 (&insn
, dest
, TRUE
);
3290 fragP
->fr_fix
+= table_entry
->rlx_length
;
3294 /* We have no need to default values of symbols. We could catch
3295 register names here, but that is handled by inserting them all in
3296 the symbol table to begin with. */
3299 md_undefined_symbol (char *name
)
3301 /* The arc abi demands that a GOT[0] should be referencible as
3302 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3303 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3305 && (*(name
+1) == 'G')
3306 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
3308 && (*(name
+1) == 'D')
3309 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
3313 if (symbol_find (name
))
3314 as_bad ("GOT already in symbol table");
3316 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3317 (valueT
) 0, &zero_address_frag
);
3324 /* Turn a string in input_line_pointer into a floating point constant
3325 of type type, and store the appropriate bytes in *litP. The number
3326 of LITTLENUMS emitted is stored in *sizeP. An error message is
3327 returned, or NULL on OK. */
3330 md_atof (int type
, char *litP
, int *sizeP
)
3332 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3335 /* Called for any expression that can not be recognized. When the
3336 function is called, `input_line_pointer' will point to the start of
3340 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3342 char *p
= input_line_pointer
;
3345 input_line_pointer
++;
3346 expressionP
->X_op
= O_symbol
;
3347 expression (expressionP
);
3351 /* This function is called from the function 'expression', it attempts
3352 to parse special names (in our case register names). It fills in
3353 the expression with the identified register. It returns TRUE if
3354 it is a register and FALSE otherwise. */
3357 arc_parse_name (const char *name
,
3358 struct expressionS
*e
)
3362 if (!assembling_insn
)
3365 if (e
->X_op
== O_symbol
)
3368 sym
= hash_find (arc_reg_hash
, name
);
3371 e
->X_op
= O_register
;
3372 e
->X_add_number
= S_GET_VALUE (sym
);
3376 sym
= hash_find (arc_addrtype_hash
, name
);
3379 e
->X_op
= O_addrtype
;
3380 e
->X_add_number
= S_GET_VALUE (sym
);
3388 Invocation line includes a switch not recognized by the base assembler.
3389 See if it's a processor-specific option.
3391 New options (supported) are:
3393 -mcpu=<cpu name> Assemble for selected processor
3394 -EB/-mbig-endian Big-endian
3395 -EL/-mlittle-endian Little-endian
3396 -mrelax Enable relaxation
3398 The following CPU names are recognized:
3399 arc600, arc700, arcem, archs, nps400. */
3402 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3408 return md_parse_option (OPTION_MCPU
, "arc600");
3411 return md_parse_option (OPTION_MCPU
, "arc700");
3414 return md_parse_option (OPTION_MCPU
, "arcem");
3417 return md_parse_option (OPTION_MCPU
, "archs");
3421 arc_select_cpu (arg
, MACH_SELECTION_FROM_COMMAND_LINE
);
3426 arc_target_format
= "elf32-bigarc";
3427 byte_order
= BIG_ENDIAN
;
3431 arc_target_format
= "elf32-littlearc";
3432 byte_order
= LITTLE_ENDIAN
;
3436 selected_cpu
.features
|= CD
;
3438 arc_check_feature ();
3442 relaxation_state
= 1;
3446 selected_cpu
.features
|= NPS400
;
3447 cl_features
|= NPS400
;
3448 arc_check_feature ();
3452 selected_cpu
.features
|= SPX
;
3454 arc_check_feature ();
3458 selected_cpu
.features
|= DPX
;
3460 arc_check_feature ();
3464 selected_cpu
.features
|= DPA
;
3466 arc_check_feature ();
3469 /* Dummy options are accepted but have no effect. */
3470 case OPTION_USER_MODE
:
3471 case OPTION_LD_EXT_MASK
:
3474 case OPTION_BARREL_SHIFT
:
3475 case OPTION_MIN_MAX
:
3480 case OPTION_XMAC_D16
:
3481 case OPTION_XMAC_24
:
3482 case OPTION_DSP_PACKA
:
3485 case OPTION_TELEPHONY
:
3486 case OPTION_XYMEMORY
:
3499 /* Display the list of cpu names for use in the help text. */
3502 arc_show_cpu_list (FILE *stream
)
3505 static const char *space_buf
= " ";
3507 fprintf (stream
, "%s", space_buf
);
3508 offset
= strlen (space_buf
);
3509 for (i
= 0; cpu_types
[i
].name
!= NULL
; ++i
)
3511 bfd_boolean last
= (cpu_types
[i
+ 1].name
== NULL
);
3513 /* If displaying the new cpu name string, and the ', ' (for all
3514 but the last one) will take us past a target width of 80
3515 characters, then it's time for a new line. */
3516 if (offset
+ strlen (cpu_types
[i
].name
) + (last
? 0 : 2) > 80)
3518 fprintf (stream
, "\n%s", space_buf
);
3519 offset
= strlen (space_buf
);
3522 fprintf (stream
, "%s%s", cpu_types
[i
].name
, (last
? "\n" : ", "));
3523 offset
+= strlen (cpu_types
[i
].name
) + (last
? 0 : 2);
3528 md_show_usage (FILE *stream
)
3530 fprintf (stream
, _("ARC-specific assembler options:\n"));
3532 fprintf (stream
, " -mcpu=<cpu name>\t (default: %s), assemble for"
3533 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU
);
3534 arc_show_cpu_list (stream
);
3535 fprintf (stream
, "\n");
3536 fprintf (stream
, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3537 fprintf (stream
, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3538 fprintf (stream
, " -mEM\t\t\t same as -mcpu=arcem\n");
3539 fprintf (stream
, " -mHS\t\t\t same as -mcpu=archs\n");
3541 fprintf (stream
, " -mnps400\t\t enable NPS-400 extended instructions\n");
3542 fprintf (stream
, " -mspfp\t\t enable single-precision floating point"
3544 fprintf (stream
, " -mdpfp\t\t enable double-precision floating point"
3546 fprintf (stream
, " -mfpuda\t\t enable double-precision assist floating "
3547 "point\n\t\t\t instructions for ARC EM\n");
3550 " -mcode-density\t enable code density option for ARC EM\n");
3552 fprintf (stream
, _("\
3553 -EB assemble code for a big-endian cpu\n"));
3554 fprintf (stream
, _("\
3555 -EL assemble code for a little-endian cpu\n"));
3556 fprintf (stream
, _("\
3557 -mrelax enable relaxation\n"));
3559 fprintf (stream
, _("The following ARC-specific assembler options are "
3560 "deprecated and are accepted\nfor compatibility only:\n"));
3562 fprintf (stream
, _(" -mEA\n"
3563 " -mbarrel-shifter\n"
3564 " -mbarrel_shifter\n"
3569 " -mld-extension-reg-mask\n"
3585 " -muser-mode-only\n"
3589 /* Find the proper relocation for the given opcode. */
3591 static extended_bfd_reloc_code_real_type
3592 find_reloc (const char *name
,
3593 const char *opcodename
,
3594 const struct arc_flags
*pflags
,
3596 extended_bfd_reloc_code_real_type reloc
)
3600 bfd_boolean found_flag
, tmp
;
3601 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3603 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3605 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3607 /* Find the entry. */
3608 if (strcmp (name
, r
->name
))
3610 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3617 unsigned * psflg
= (unsigned *)r
->flags
;
3621 for (j
= 0; j
< nflg
; j
++)
3622 if (!strcmp (pflags
[j
].name
,
3623 arc_flag_operands
[*psflg
].name
))
3644 if (reloc
!= r
->oldreloc
)
3651 if (ret
== BFD_RELOC_UNUSED
)
3652 as_bad (_("Unable to find %s relocation for instruction %s"),
3657 /* All the symbol types that are allowed to be used for
3661 may_relax_expr (expressionS tok
)
3663 /* Check if we have unrelaxable relocs. */
3688 /* Checks if flags are in line with relaxable insn. */
3691 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3692 const struct arc_flags
*pflags
,
3695 unsigned flag_class
,
3700 const struct arc_flag_operand
*flag_opand
;
3701 int i
, counttrue
= 0;
3703 /* Iterate through flags classes. */
3704 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3706 /* Iterate through flags in flag class. */
3707 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3710 flag_opand
= &arc_flag_operands
[flag
];
3711 /* Iterate through flags in ins to compare. */
3712 for (i
= 0; i
< nflgs
; ++i
)
3714 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3725 /* If counttrue == nflgs, then all flags have been found. */
3726 return (counttrue
== nflgs
? TRUE
: FALSE
);
3729 /* Checks if operands are in line with relaxable insn. */
3732 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3733 const expressionS
*tok
,
3736 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3739 while (*operand
!= EMPTY
)
3741 const expressionS
*epr
= &tok
[i
];
3743 if (i
!= 0 && i
>= ntok
)
3749 if (!(epr
->X_op
== O_multiply
3750 || epr
->X_op
== O_divide
3751 || epr
->X_op
== O_modulus
3752 || epr
->X_op
== O_add
3753 || epr
->X_op
== O_subtract
3754 || epr
->X_op
== O_symbol
))
3760 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3764 if (epr
->X_op
!= O_register
)
3769 if (epr
->X_op
!= O_register
)
3772 switch (epr
->X_add_number
)
3774 case 0: case 1: case 2: case 3:
3775 case 12: case 13: case 14: case 15:
3782 case REGISTER_NO_GP
:
3783 if ((epr
->X_op
!= O_register
)
3784 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3789 if (epr
->X_op
!= O_bracket
)
3794 /* Don't understand, bail out. */
3800 operand
= &ins
->operands
[i
];
3803 return (i
== ntok
? TRUE
: FALSE
);
3806 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3809 relax_insn_p (const struct arc_opcode
*opcode
,
3810 const expressionS
*tok
,
3812 const struct arc_flags
*pflags
,
3816 bfd_boolean rv
= FALSE
;
3818 /* Check the relaxation table. */
3819 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3821 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3823 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3824 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3825 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3826 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3829 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3830 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3831 sizeof (expressionS
) * ntok
);
3832 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3833 sizeof (struct arc_flags
) * nflg
);
3834 frag_now
->tc_frag_data
.nflg
= nflg
;
3835 frag_now
->tc_frag_data
.ntok
= ntok
;
3843 /* Turn an opcode description and a set of arguments into
3844 an instruction and a fixup. */
3847 assemble_insn (const struct arc_opcode
*opcode
,
3848 const expressionS
*tok
,
3850 const struct arc_flags
*pflags
,
3852 struct arc_insn
*insn
)
3854 const expressionS
*reloc_exp
= NULL
;
3855 unsigned long long image
;
3856 const unsigned char *argidx
;
3859 unsigned char pcrel
= 0;
3860 bfd_boolean needGOTSymbol
;
3861 bfd_boolean has_delay_slot
= FALSE
;
3862 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3864 memset (insn
, 0, sizeof (*insn
));
3865 image
= opcode
->opcode
;
3867 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
3868 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3871 /* Handle operands. */
3872 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3874 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3875 const expressionS
*t
= (const expressionS
*) 0;
3877 if (ARC_OPERAND_IS_FAKE (operand
))
3880 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3882 /* Duplicate operand, already inserted. */
3894 /* Regardless if we have a reloc or not mark the instruction
3895 limm if it is the case. */
3896 if (operand
->flags
& ARC_OPERAND_LIMM
)
3897 insn
->has_limm
= TRUE
;
3902 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3907 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3909 if (operand
->flags
& ARC_OPERAND_LIMM
)
3910 insn
->limm
= t
->X_add_number
;
3916 /* Ignore brackets, colons, and address types. */
3920 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3924 /* Maybe register range. */
3925 if ((t
->X_add_number
== 0)
3926 && contains_register (t
->X_add_symbol
)
3927 && contains_register (t
->X_op_symbol
))
3931 regs
= get_register (t
->X_add_symbol
);
3933 regs
|= get_register (t
->X_op_symbol
);
3934 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3940 /* This operand needs a relocation. */
3941 needGOTSymbol
= FALSE
;
3946 if (opcode
->insn_class
== JUMP
)
3947 as_bad (_("Unable to use @plt relocation for insn %s"),
3949 needGOTSymbol
= TRUE
;
3950 reloc
= find_reloc ("plt", opcode
->name
,
3952 operand
->default_reloc
);
3957 needGOTSymbol
= TRUE
;
3958 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3961 if (operand
->flags
& ARC_OPERAND_LIMM
)
3963 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3964 if (arc_opcode_len (opcode
) == 2
3965 || opcode
->insn_class
== JUMP
)
3966 as_bad (_("Unable to use @pcl relocation for insn %s"),
3971 /* This is a relaxed operand which initially was
3972 limm, choose whatever we have defined in the
3974 reloc
= operand
->default_reloc
;
3978 reloc
= find_reloc ("sda", opcode
->name
,
3980 operand
->default_reloc
);
3984 needGOTSymbol
= TRUE
;
3989 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3992 case O_tpoff9
: /*FIXME! Check for the conditionality of
3994 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3996 as_bad (_("TLS_*_S9 relocs are not supported yet"));
4000 /* Just consider the default relocation. */
4001 reloc
= operand
->default_reloc
;
4005 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
4006 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4013 /* sanity checks. */
4014 reloc_howto_type
*reloc_howto
4015 = bfd_reloc_type_lookup (stdoutput
,
4016 (bfd_reloc_code_real_type
) reloc
);
4017 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
4018 if (reloc_howto
->rightshift
)
4019 reloc_bitsize
-= reloc_howto
->rightshift
;
4020 if (reloc_bitsize
!= operand
->bits
)
4022 as_bad (_("invalid relocation %s for field"),
4023 bfd_get_reloc_code_name (reloc
));
4028 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4029 as_fatal (_("too many fixups"));
4031 struct arc_fixup
*fixup
;
4032 fixup
= &insn
->fixups
[insn
->nfixups
++];
4034 fixup
->reloc
= reloc
;
4035 if ((int) reloc
< 0)
4036 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
4039 reloc_howto_type
*reloc_howto
=
4040 bfd_reloc_type_lookup (stdoutput
,
4041 (bfd_reloc_code_real_type
) fixup
->reloc
);
4042 pcrel
= reloc_howto
->pc_relative
;
4044 fixup
->pcrel
= pcrel
;
4045 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
4052 for (i
= 0; i
< nflg
; i
++)
4054 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
4056 /* Check if the instruction has a delay slot. */
4057 if (!strcmp (flg_operand
->name
, "d"))
4058 has_delay_slot
= TRUE
;
4060 /* There is an exceptional case when we cannot insert a flag just as
4061 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4062 relation with the relative address. Unfortunately, some of the
4063 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4064 handled in the normal way.
4066 Flag operands don't have an architecture field, so we can't
4067 directly validate that FLAG_OPERAND is valid for the current
4068 architecture, what we do instead is just validate that we're
4069 assembling for an ARCv2 architecture. */
4070 if ((selected_cpu
.flags
& ARC_OPCODE_ARCV2
)
4071 && (!strcmp (flg_operand
->name
, "t")
4072 || !strcmp (flg_operand
->name
, "nt")))
4074 unsigned bitYoperand
= 0;
4075 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4076 if (!strcmp (flg_operand
->name
, "t"))
4077 if (!strcmp (opcode
->name
, "bbit0")
4078 || !strcmp (opcode
->name
, "bbit1"))
4079 bitYoperand
= arc_NToperand
;
4081 bitYoperand
= arc_Toperand
;
4083 if (!strcmp (opcode
->name
, "bbit0")
4084 || !strcmp (opcode
->name
, "bbit1"))
4085 bitYoperand
= arc_Toperand
;
4087 bitYoperand
= arc_NToperand
;
4089 gas_assert (reloc_exp
!= NULL
);
4090 if (reloc_exp
->X_op
== O_constant
)
4092 /* Check if we have a constant and solved it
4094 offsetT val
= reloc_exp
->X_add_number
;
4095 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
4100 struct arc_fixup
*fixup
;
4102 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4103 as_fatal (_("too many fixups"));
4105 fixup
= &insn
->fixups
[insn
->nfixups
++];
4106 fixup
->exp
= *reloc_exp
;
4107 fixup
->reloc
= -bitYoperand
;
4108 fixup
->pcrel
= pcrel
;
4109 fixup
->islong
= FALSE
;
4113 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
4114 << flg_operand
->shift
;
4117 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
4119 /* Instruction length. */
4120 insn
->len
= arc_opcode_len (opcode
);
4124 /* Update last insn status. */
4125 arc_last_insns
[1] = arc_last_insns
[0];
4126 arc_last_insns
[0].opcode
= opcode
;
4127 arc_last_insns
[0].has_limm
= insn
->has_limm
;
4128 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
4130 /* Check if the current instruction is legally used. */
4131 if (arc_last_insns
[1].has_delay_slot
4132 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4133 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4134 arc_last_insns
[1].opcode
->name
,
4135 arc_last_insns
[0].opcode
->name
);
4139 arc_handle_align (fragS
* fragP
)
4141 if ((fragP
)->fr_type
== rs_align_code
)
4143 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
4144 valueT count
= ((fragP
)->fr_next
->fr_address
4145 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
4147 (fragP
)->fr_var
= 2;
4149 if (count
& 1)/* Padding in the gap till the next 2-byte
4150 boundary with 0s. */
4155 /* Writing nop_s. */
4156 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
4160 /* Here we decide which fixups can be adjusted to make them relative
4161 to the beginning of the section instead of the symbol. Basically
4162 we need to make sure that the dynamic relocations are done
4163 correctly, so in some cases we force the original symbol to be
4167 tc_arc_fix_adjustable (fixS
*fixP
)
4170 /* Prevent all adjustments to global symbols. */
4171 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
4173 if (S_IS_WEAK (fixP
->fx_addsy
))
4176 /* Adjust_reloc_syms doesn't know about the GOT. */
4177 switch (fixP
->fx_r_type
)
4179 case BFD_RELOC_ARC_GOTPC32
:
4180 case BFD_RELOC_ARC_PLT32
:
4181 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
4182 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
4183 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
4184 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
4194 /* Compute the reloc type of an expression EXP. */
4197 arc_check_reloc (expressionS
*exp
,
4198 bfd_reloc_code_real_type
*r_type_p
)
4200 if (*r_type_p
== BFD_RELOC_32
4201 && exp
->X_op
== O_subtract
4202 && exp
->X_op_symbol
!= NULL
4203 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
4204 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4208 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4211 arc_cons_fix_new (fragS
*frag
,
4215 bfd_reloc_code_real_type r_type
)
4217 r_type
= BFD_RELOC_UNUSED
;
4222 r_type
= BFD_RELOC_8
;
4226 r_type
= BFD_RELOC_16
;
4230 r_type
= BFD_RELOC_24
;
4234 r_type
= BFD_RELOC_32
;
4235 arc_check_reloc (exp
, &r_type
);
4239 r_type
= BFD_RELOC_64
;
4243 as_bad (_("unsupported BFD relocation size %u"), size
);
4244 r_type
= BFD_RELOC_UNUSED
;
4247 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4250 /* The actual routine that checks the ZOL conditions. */
4253 check_zol (symbolS
*s
)
4255 switch (selected_cpu
.mach
)
4257 case bfd_mach_arc_arcv2
:
4258 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
4261 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4262 || arc_last_insns
[1].has_delay_slot
)
4263 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4267 case bfd_mach_arc_arc600
:
4269 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4270 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4273 if (arc_last_insns
[0].has_limm
4274 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4275 as_bad (_("A jump instruction with long immediate detected at the \
4276 end of the ZOL label @%s"), S_GET_NAME (s
));
4279 case bfd_mach_arc_arc700
:
4280 if (arc_last_insns
[0].has_delay_slot
)
4281 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4290 /* If ZOL end check the last two instruction for illegals. */
4292 arc_frob_label (symbolS
* sym
)
4294 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4297 dwarf2_emit_label (sym
);
4300 /* Used because generic relaxation assumes a pc-rel value whilst we
4301 also relax instructions that use an absolute value resolved out of
4302 relative values (if that makes any sense). An example: 'add r1,
4303 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4304 but if they're in the same section we can subtract the section
4305 offset relocation which ends up in a resolved value. So if @.L2 is
4306 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4307 .text + 0x40 = 0x10. */
4309 arc_pcrel_adjust (fragS
*fragP
)
4311 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4312 fragP
->fr_address
, fragP
->fr_fix
,
4313 fragP
->tc_frag_data
.pcrel
? "Y" : "N");
4315 if (!fragP
->tc_frag_data
.pcrel
)
4316 return fragP
->fr_address
+ fragP
->fr_fix
;
4318 /* Take into account the PCL rounding. */
4319 return (fragP
->fr_address
+ fragP
->fr_fix
) & 0x03;
4322 /* Initialize the DWARF-2 unwind information for this procedure. */
4325 tc_arc_frame_initial_instructions (void)
4327 /* Stack pointer is register 28. */
4328 cfi_add_CFA_def_cfa (28, 0);
4332 tc_arc_regname_to_dw2regnum (char *regname
)
4336 sym
= hash_find (arc_reg_hash
, regname
);
4338 return S_GET_VALUE (sym
);
4343 /* Adjust the symbol table. Delete found AUX register symbols. */
4346 arc_adjust_symtab (void)
4350 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4352 /* I've created a symbol during parsing process. Now, remove
4353 the symbol as it is found to be an AUX register. */
4354 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4355 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4358 /* Now do generic ELF adjustments. */
4359 elf_adjust_symtab ();
4363 tokenize_extinsn (extInstruction_t
*einsn
)
4367 unsigned char major_opcode
;
4368 unsigned char sub_opcode
;
4369 unsigned char syntax_class
= 0;
4370 unsigned char syntax_class_modifiers
= 0;
4371 unsigned char suffix_class
= 0;
4376 /* 1st: get instruction name. */
4377 p
= input_line_pointer
;
4378 c
= get_symbol_name (&p
);
4380 insn_name
= xstrdup (p
);
4381 restore_line_pointer (c
);
4383 /* 2nd: get major opcode. */
4384 if (*input_line_pointer
!= ',')
4386 as_bad (_("expected comma after instruction name"));
4387 ignore_rest_of_line ();
4390 input_line_pointer
++;
4391 major_opcode
= get_absolute_expression ();
4393 /* 3rd: get sub-opcode. */
4396 if (*input_line_pointer
!= ',')
4398 as_bad (_("expected comma after major opcode"));
4399 ignore_rest_of_line ();
4402 input_line_pointer
++;
4403 sub_opcode
= get_absolute_expression ();
4405 /* 4th: get suffix class. */
4408 if (*input_line_pointer
!= ',')
4410 as_bad ("expected comma after sub opcode");
4411 ignore_rest_of_line ();
4414 input_line_pointer
++;
4420 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4422 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4423 suffixclass
[i
].len
))
4425 suffix_class
|= suffixclass
[i
].attr_class
;
4426 input_line_pointer
+= suffixclass
[i
].len
;
4431 if (i
== ARRAY_SIZE (suffixclass
))
4433 as_bad ("invalid suffix class");
4434 ignore_rest_of_line ();
4440 if (*input_line_pointer
== '|')
4441 input_line_pointer
++;
4446 /* 5th: get syntax class and syntax class modifiers. */
4447 if (*input_line_pointer
!= ',')
4449 as_bad ("expected comma after suffix class");
4450 ignore_rest_of_line ();
4453 input_line_pointer
++;
4459 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4461 if (!strncmp (syntaxclassmod
[i
].name
,
4463 syntaxclassmod
[i
].len
))
4465 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4466 input_line_pointer
+= syntaxclassmod
[i
].len
;
4471 if (i
== ARRAY_SIZE (syntaxclassmod
))
4473 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4475 if (!strncmp (syntaxclass
[i
].name
,
4477 syntaxclass
[i
].len
))
4479 syntax_class
|= syntaxclass
[i
].attr_class
;
4480 input_line_pointer
+= syntaxclass
[i
].len
;
4485 if (i
== ARRAY_SIZE (syntaxclass
))
4487 as_bad ("missing syntax class");
4488 ignore_rest_of_line ();
4495 if (*input_line_pointer
== '|')
4496 input_line_pointer
++;
4501 demand_empty_rest_of_line ();
4503 einsn
->name
= insn_name
;
4504 einsn
->major
= major_opcode
;
4505 einsn
->minor
= sub_opcode
;
4506 einsn
->syntax
= syntax_class
;
4507 einsn
->modsyn
= syntax_class_modifiers
;
4508 einsn
->suffix
= suffix_class
;
4509 einsn
->flags
= syntax_class
4510 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4513 /* Generate an extension section. */
4516 arc_set_ext_seg (void)
4518 if (!arcext_section
)
4520 arcext_section
= subseg_new (".arcextmap", 0);
4521 bfd_set_section_flags (stdoutput
, arcext_section
,
4522 SEC_READONLY
| SEC_HAS_CONTENTS
);
4525 subseg_set (arcext_section
, 0);
4529 /* Create an extension instruction description in the arc extension
4530 section of the output file.
4531 The structure for an instruction is like this:
4532 [0]: Length of the record.
4533 [1]: Type of the record.
4537 [4]: Syntax (flags).
4538 [5]+ Name instruction.
4540 The sequence is terminated by an empty entry. */
4543 create_extinst_section (extInstruction_t
*einsn
)
4546 segT old_sec
= now_seg
;
4547 int old_subsec
= now_subseg
;
4549 int name_len
= strlen (einsn
->name
);
4554 *p
= 5 + name_len
+ 1;
4556 *p
= EXT_INSTRUCTION
;
4563 p
= frag_more (name_len
+ 1);
4564 strcpy (p
, einsn
->name
);
4566 subseg_set (old_sec
, old_subsec
);
4569 /* Handler .extinstruction pseudo-op. */
4572 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4574 extInstruction_t einsn
;
4575 struct arc_opcode
*arc_ext_opcodes
;
4576 const char *errmsg
= NULL
;
4577 unsigned char moplow
, mophigh
;
4579 memset (&einsn
, 0, sizeof (einsn
));
4580 tokenize_extinsn (&einsn
);
4582 /* Check if the name is already used. */
4583 if (arc_find_opcode (einsn
.name
))
4584 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4586 /* Check the opcode ranges. */
4588 mophigh
= (selected_cpu
.flags
& (ARC_OPCODE_ARCv2EM
4589 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4591 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4592 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4594 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4595 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4596 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4598 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4600 case ARC_SYNTAX_3OP
:
4601 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4602 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4604 case ARC_SYNTAX_2OP
:
4605 case ARC_SYNTAX_1OP
:
4606 case ARC_SYNTAX_NOP
:
4607 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4608 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4614 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, selected_cpu
.flags
, &errmsg
);
4615 if (arc_ext_opcodes
== NULL
)
4618 as_fatal ("%s", errmsg
);
4620 as_fatal (_("Couldn't generate extension instruction opcodes"));
4623 as_warn ("%s", errmsg
);
4625 /* Insert the extension instruction. */
4626 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4628 create_extinst_section (&einsn
);
4632 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4638 int number
, imode
= 0;
4639 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4640 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4641 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4643 /* 1st: get register name. */
4645 p
= input_line_pointer
;
4646 c
= get_symbol_name (&p
);
4649 restore_line_pointer (c
);
4651 /* 2nd: get register number. */
4654 if (*input_line_pointer
!= ',')
4656 as_bad (_("expected comma after name"));
4657 ignore_rest_of_line ();
4661 input_line_pointer
++;
4662 number
= get_absolute_expression ();
4665 && (opertype
!= EXT_AUX_REGISTER
))
4667 as_bad (_("%s second argument cannot be a negative number %d"),
4668 isCore_p
? "extCoreRegister's" : "extCondCode's",
4670 ignore_rest_of_line ();
4677 /* 3rd: get register mode. */
4680 if (*input_line_pointer
!= ',')
4682 as_bad (_("expected comma after register number"));
4683 ignore_rest_of_line ();
4688 input_line_pointer
++;
4689 mode
= input_line_pointer
;
4691 if (!strncmp (mode
, "r|w", 3))
4694 input_line_pointer
+= 3;
4696 else if (!strncmp (mode
, "r", 1))
4698 imode
= ARC_REGISTER_READONLY
;
4699 input_line_pointer
+= 1;
4701 else if (strncmp (mode
, "w", 1))
4703 as_bad (_("invalid mode"));
4704 ignore_rest_of_line ();
4710 imode
= ARC_REGISTER_WRITEONLY
;
4711 input_line_pointer
+= 1;
4717 /* 4th: get core register shortcut. */
4719 if (*input_line_pointer
!= ',')
4721 as_bad (_("expected comma after register mode"));
4722 ignore_rest_of_line ();
4727 input_line_pointer
++;
4729 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4731 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4732 input_line_pointer
+= 15;
4734 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4736 as_bad (_("shortcut designator invalid"));
4737 ignore_rest_of_line ();
4743 input_line_pointer
+= 12;
4746 demand_empty_rest_of_line ();
4749 ereg
->number
= number
;
4750 ereg
->imode
= imode
;
4754 /* Create an extension register/condition description in the arc
4755 extension section of the output file.
4757 The structure for an instruction is like this:
4758 [0]: Length of the record.
4759 [1]: Type of the record.
4761 For core regs and condition codes:
4765 For auxiliary registers:
4769 The sequence is terminated by an empty entry. */
4772 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4774 segT old_sec
= now_seg
;
4775 int old_subsec
= now_subseg
;
4777 int name_len
= strlen (ereg
->name
);
4784 case EXT_CORE_REGISTER
:
4786 *p
= 3 + name_len
+ 1;
4792 case EXT_AUX_REGISTER
:
4794 *p
= 6 + name_len
+ 1;
4796 *p
= EXT_AUX_REGISTER
;
4798 *p
= (ereg
->number
>> 24) & 0xff;
4800 *p
= (ereg
->number
>> 16) & 0xff;
4802 *p
= (ereg
->number
>> 8) & 0xff;
4804 *p
= (ereg
->number
) & 0xff;
4810 p
= frag_more (name_len
+ 1);
4811 strcpy (p
, ereg
->name
);
4813 subseg_set (old_sec
, old_subsec
);
4816 /* Handler .extCoreRegister pseudo-op. */
4819 arc_extcorereg (int opertype
)
4822 struct arc_aux_reg
*auxr
;
4824 struct arc_flag_operand
*ccode
;
4826 memset (&ereg
, 0, sizeof (ereg
));
4827 if (!tokenize_extregister (&ereg
, opertype
))
4832 case EXT_CORE_REGISTER
:
4833 /* Core register. */
4834 if (ereg
.number
> 60)
4835 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4837 declare_register (ereg
.name
, ereg
.number
);
4839 case EXT_AUX_REGISTER
:
4840 /* Auxiliary register. */
4841 auxr
= XNEW (struct arc_aux_reg
);
4842 auxr
->name
= ereg
.name
;
4843 auxr
->cpu
= selected_cpu
.flags
;
4844 auxr
->subclass
= NONE
;
4845 auxr
->address
= ereg
.number
;
4846 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4848 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4849 auxr
->name
, retval
);
4852 /* Condition code. */
4853 if (ereg
.number
> 31)
4854 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4856 ext_condcode
.size
++;
4857 ext_condcode
.arc_ext_condcode
=
4858 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4859 ext_condcode
.size
+ 1);
4860 if (ext_condcode
.arc_ext_condcode
== NULL
)
4861 as_fatal (_("Virtual memory exhausted"));
4863 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4864 ccode
->name
= ereg
.name
;
4865 ccode
->code
= ereg
.number
;
4868 ccode
->favail
= 0; /* not used. */
4870 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4873 as_bad (_("Unknown extension"));
4876 create_extcore_section (&ereg
, opertype
);
4879 /* Parse a .arc_attribute directive. */
4882 arc_attribute (int ignored ATTRIBUTE_UNUSED
)
4884 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4886 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4887 attributes_set_explicitly
[tag
] = TRUE
;
4890 /* Set an attribute if it has not already been set by the user. */
4893 arc_set_attribute_int (int tag
, int value
)
4896 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4897 || !attributes_set_explicitly
[tag
])
4898 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
4902 arc_set_attribute_string (int tag
, const char *value
)
4905 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4906 || !attributes_set_explicitly
[tag
])
4907 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
4910 /* Allocate and concatenate two strings. s1 can be NULL but not
4911 s2. s1 pointer is freed at end of this procedure. */
4914 arc_stralloc (char * s1
, const char * s2
)
4920 len
= strlen (s1
) + 1;
4922 /* Only s1 can be null. */
4924 len
+= strlen (s2
) + 1;
4926 p
= (char *) xmalloc (len
);
4928 as_fatal (_("Virtual memory exhausted"));
4943 /* Set the public ARC object attributes. */
4946 arc_set_public_attributes (void)
4952 /* Tag_ARC_CPU_name. */
4953 arc_set_attribute_string (Tag_ARC_CPU_name
, selected_cpu
.name
);
4955 /* Tag_ARC_CPU_base. */
4956 switch (selected_cpu
.eflags
& EF_ARC_MACH_MSK
)
4958 case E_ARC_MACH_ARC600
:
4959 case E_ARC_MACH_ARC601
:
4960 base
= TAG_CPU_ARC6xx
;
4962 case E_ARC_MACH_ARC700
:
4963 base
= TAG_CPU_ARC7xx
;
4965 case EF_ARC_CPU_ARCV2EM
:
4966 base
= TAG_CPU_ARCEM
;
4968 case EF_ARC_CPU_ARCV2HS
:
4969 base
= TAG_CPU_ARCHS
;
4975 if (attributes_set_explicitly
[Tag_ARC_CPU_base
]
4976 && (base
!= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
4978 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
4979 bfd_elf_add_proc_attr_int (stdoutput
, Tag_ARC_CPU_base
, base
);
4981 /* Tag_ARC_ABI_osver. */
4982 if (attributes_set_explicitly
[Tag_ARC_ABI_osver
])
4984 int val
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
4987 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_OSABI_MSK
)
4988 | (val
& 0x0f << 8));
4992 arc_set_attribute_int (Tag_ARC_ABI_osver
, E_ARC_OSABI_CURRENT
>> 8);
4995 /* Tag_ARC_ISA_config. */
4996 arc_check_feature();
4998 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
4999 if (selected_cpu
.features
& feature_list
[i
].feature
)
5000 s
= arc_stralloc (s
, feature_list
[i
].attr
);
5003 arc_set_attribute_string (Tag_ARC_ISA_config
, s
);
5005 /* Tag_ARC_ISA_mpy_option. */
5006 arc_set_attribute_int (Tag_ARC_ISA_mpy_option
, mpy_option
);
5008 /* Tag_ARC_ABI_pic. */
5009 arc_set_attribute_int (Tag_ARC_ABI_pic
, pic_option
);
5011 /* Tag_ARC_ABI_sda. */
5012 arc_set_attribute_int (Tag_ARC_ABI_sda
, sda_option
);
5014 /* Tag_ARC_ABI_tls. */
5015 arc_set_attribute_int (Tag_ARC_ABI_tls
, tls_option
);
5018 /* Add the default contents for the .ARC.attributes section. */
5023 arc_set_public_attributes ();
5025 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
5026 as_fatal (_("could not set architecture and machine"));
5028 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
5031 void arc_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
5033 ARC_GET_FLAG (dest
) = ARC_GET_FLAG (src
);
5036 int arc_convert_symbolic_attribute (const char *name
)
5045 #define T(tag) {#tag, tag}
5046 T (Tag_ARC_PCS_config
),
5047 T (Tag_ARC_CPU_base
),
5048 T (Tag_ARC_CPU_variation
),
5049 T (Tag_ARC_CPU_name
),
5050 T (Tag_ARC_ABI_rf16
),
5051 T (Tag_ARC_ABI_osver
),
5052 T (Tag_ARC_ABI_sda
),
5053 T (Tag_ARC_ABI_pic
),
5054 T (Tag_ARC_ABI_tls
),
5055 T (Tag_ARC_ABI_enumsize
),
5056 T (Tag_ARC_ABI_exceptions
),
5057 T (Tag_ARC_ABI_double_size
),
5058 T (Tag_ARC_ISA_config
),
5059 T (Tag_ARC_ISA_apex
),
5060 T (Tag_ARC_ISA_mpy_option
)
5068 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
5069 if (streq (name
, attribute_table
[i
].name
))
5070 return attribute_table
[i
].tag
;
5076 eval: (c-set-style "gnu")