1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
51 /* Equal to MAX_PRECISION in atof-ieee.c. */
52 #define MAX_LITTLENUMS 6
54 #ifndef TARGET_WITH_CPU
55 #define TARGET_WITH_CPU "arc700"
56 #endif /* TARGET_WITH_CPU */
58 /* Enum used to enumerate the relaxable ins operands. */
63 REGISTER_S
, /* Register for short instruction(s). */
64 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
65 REGISTER_DUP
, /* Duplication of previous operand of type register. */
99 #define regno(x) ((x) & 0x3F)
100 #define is_ir_num(x) (((x) & ~0x3F) == 0)
101 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
102 #define is_spfp_p(op) (((sc) == SPX))
103 #define is_dpfp_p(op) (((sc) == DPX))
104 #define is_fpuda_p(op) (((sc) == DPA))
105 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
106 || (op)->insn_class == JUMP))
107 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
108 #define is_nps400_p(op) (((sc) == NPS400))
110 /* Generic assembler global variables which must be defined by all
113 /* Characters which always start a comment. */
114 const char comment_chars
[] = "#;";
116 /* Characters which start a comment at the beginning of a line. */
117 const char line_comment_chars
[] = "#";
119 /* Characters which may be used to separate multiple commands on a
121 const char line_separator_chars
[] = "`";
123 /* Characters which are used to indicate an exponent in a floating
125 const char EXP_CHARS
[] = "eE";
127 /* Chars that mean this number is a floating point constant
128 As in 0f12.456 or 0d1.2345e12. */
129 const char FLT_CHARS
[] = "rRsSfFdD";
132 extern int target_big_endian
;
133 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
134 static int byte_order
= DEFAULT_BYTE_ORDER
;
136 /* Arc extension section. */
137 static segT arcext_section
;
139 /* By default relaxation is disabled. */
140 static int relaxation_state
= 0;
142 extern int arc_get_mach (char *);
144 /* Forward declarations. */
145 static void arc_lcomm (int);
146 static void arc_option (int);
147 static void arc_extra_reloc (int);
148 static void arc_extinsn (int);
149 static void arc_extcorereg (int);
151 const pseudo_typeS md_pseudo_table
[] =
153 /* Make sure that .word is 32 bits. */
156 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
157 { "lcomm", arc_lcomm
, 0 },
158 { "lcommon", arc_lcomm
, 0 },
159 { "cpu", arc_option
, 0 },
161 { "extinstruction", arc_extinsn
, 0 },
162 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
163 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
164 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
166 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
167 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
172 const char *md_shortopts
= "";
176 OPTION_EB
= OPTION_MD_BASE
,
194 /* The following options are deprecated and provided here only for
195 compatibility reasons. */
218 struct option md_longopts
[] =
220 { "EB", no_argument
, NULL
, OPTION_EB
},
221 { "EL", no_argument
, NULL
, OPTION_EL
},
222 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
223 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
224 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
225 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
226 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
227 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
228 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
229 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
230 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
231 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
232 { "mnps400", no_argument
, NULL
, OPTION_NPS400
},
234 /* Floating point options */
235 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
236 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
237 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
238 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
239 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
240 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
241 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
242 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
243 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
244 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
245 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
247 /* The following options are deprecated and provided here only for
248 compatibility reasons. */
249 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
250 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
251 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
252 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
253 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
254 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
255 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
256 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
257 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
258 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
259 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
260 { "mea", no_argument
, NULL
, OPTION_EA
},
261 { "mEA", no_argument
, NULL
, OPTION_EA
},
262 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
263 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
264 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
265 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
266 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
267 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
268 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
269 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
270 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
271 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
272 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
273 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
274 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
275 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
276 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
278 { NULL
, no_argument
, NULL
, 0 }
281 size_t md_longopts_size
= sizeof (md_longopts
);
283 /* Local data and data types. */
285 /* Used since new relocation types are introduced in this
286 file (DUMMY_RELOC_LITUSE_*). */
287 typedef int extended_bfd_reloc_code_real_type
;
293 extended_bfd_reloc_code_real_type reloc
;
295 /* index into arc_operands. */
296 unsigned int opindex
;
298 /* PC-relative, used by internals fixups. */
301 /* TRUE if this fixup is for LIMM operand. */
309 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
311 bfd_boolean short_insn
; /* Boolean value: TRUE if current insn is
313 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
315 bfd_boolean relax
; /* Boolean value: TRUE if needs
319 /* Structure to hold any last two instructions. */
320 static struct arc_last_insn
322 /* Saved instruction opcode. */
323 const struct arc_opcode
*opcode
;
325 /* Boolean value: TRUE if current insn is short. */
326 bfd_boolean has_limm
;
328 /* Boolean value: TRUE if current insn has delay slot. */
329 bfd_boolean has_delay_slot
;
332 /* Extension instruction suffix classes. */
340 static const attributes_t suffixclass
[] =
342 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
343 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
344 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
347 /* Extension instruction syntax classes. */
348 static const attributes_t syntaxclass
[] =
350 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
351 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
352 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
353 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
356 /* Extension instruction syntax classes modifiers. */
357 static const attributes_t syntaxclassmod
[] =
359 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
360 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
363 /* Extension register type. */
371 /* A structure to hold the additional conditional codes. */
374 struct arc_flag_operand
*arc_ext_condcode
;
376 } ext_condcode
= { NULL
, 0 };
378 /* Structure to hold an entry in ARC_OPCODE_HASH. */
379 struct arc_opcode_hash_entry
381 /* The number of pointers in the OPCODE list. */
384 /* Points to a list of opcode pointers. */
385 const struct arc_opcode
**opcode
;
388 /* Structure used for iterating through an arc_opcode_hash_entry. */
389 struct arc_opcode_hash_entry_iterator
391 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
394 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
395 returned by this iterator. */
396 const struct arc_opcode
*opcode
;
399 /* Forward declaration. */
400 static void assemble_insn
401 (const struct arc_opcode
*, const expressionS
*, int,
402 const struct arc_flags
*, int, struct arc_insn
*);
404 /* The selection of the machine type can come from different sources. This
405 enum is used to track how the selection was made in order to perform
407 enum mach_selection_type
410 MACH_SELECTION_FROM_DEFAULT
,
411 MACH_SELECTION_FROM_CPU_DIRECTIVE
,
412 MACH_SELECTION_FROM_COMMAND_LINE
415 /* How the current machine type was selected. */
416 static enum mach_selection_type mach_selection_mode
= MACH_SELECTION_NONE
;
418 /* The hash table of instruction opcodes. */
419 static struct hash_control
*arc_opcode_hash
;
421 /* The hash table of register symbols. */
422 static struct hash_control
*arc_reg_hash
;
424 /* The hash table of aux register symbols. */
425 static struct hash_control
*arc_aux_hash
;
427 /* The hash table of address types. */
428 static struct hash_control
*arc_addrtype_hash
;
430 /* A table of CPU names and opcode sets. */
431 static const struct cpu_type
441 { "arc600", ARC_OPCODE_ARC600
, bfd_mach_arc_arc600
,
442 E_ARC_MACH_ARC600
, 0x00},
443 { "arc700", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
444 E_ARC_MACH_ARC700
, 0x00},
445 { "nps400", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
446 E_ARC_MACH_ARC700
, ARC_NPS400
},
447 { "arcem", ARC_OPCODE_ARCv2EM
, bfd_mach_arc_arcv2
,
448 EF_ARC_CPU_ARCV2EM
, 0x00},
449 { "archs", ARC_OPCODE_ARCv2HS
, bfd_mach_arc_arcv2
,
450 EF_ARC_CPU_ARCV2HS
, ARC_CD
},
454 /* Information about the cpu/variant we're assembling for. */
455 static struct cpu_type selected_cpu
;
457 /* Used by the arc_reloc_op table. Order is important. */
458 #define O_gotoff O_md1 /* @gotoff relocation. */
459 #define O_gotpc O_md2 /* @gotpc relocation. */
460 #define O_plt O_md3 /* @plt relocation. */
461 #define O_sda O_md4 /* @sda relocation. */
462 #define O_pcl O_md5 /* @pcl relocation. */
463 #define O_tlsgd O_md6 /* @tlsgd relocation. */
464 #define O_tlsie O_md7 /* @tlsie relocation. */
465 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
466 #define O_tpoff O_md9 /* @tpoff relocation. */
467 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
468 #define O_dtpoff O_md11 /* @dtpoff relocation. */
469 #define O_last O_dtpoff
471 /* Used to define a bracket as operand in tokens. */
472 #define O_bracket O_md32
474 /* Used to define a colon as an operand in tokens. */
475 #define O_colon O_md31
477 /* Used to define address types in nps400. */
478 #define O_addrtype O_md30
480 /* Dummy relocation, to be sorted out. */
481 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
483 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
485 /* A table to map the spelling of a relocation operand into an appropriate
486 bfd_reloc_code_real_type type. The table is assumed to be ordered such
487 that op-O_literal indexes into it. */
488 #define ARC_RELOC_TABLE(op) \
489 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
491 : (int) (op) - (int) O_gotoff) ])
493 #define DEF(NAME, RELOC, REQ) \
494 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
496 static const struct arc_reloc_op_tag
498 /* String to lookup. */
500 /* Size of the string. */
502 /* Which operator to use. */
504 extended_bfd_reloc_code_real_type reloc
;
505 /* Allows complex relocation expression like identifier@reloc +
507 unsigned int complex_expr
: 1;
511 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
512 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
513 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
514 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
515 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
516 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
517 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
518 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
519 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
520 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
521 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 1),
524 static const int arc_num_reloc_op
525 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
527 /* Structure for relaxable instruction that have to be swapped with a
528 smaller alternative instruction. */
529 struct arc_relaxable_ins
531 /* Mnemonic that should be checked. */
532 const char *mnemonic_r
;
534 /* Operands that should be checked.
535 Indexes of operands from operand array. */
536 enum rlx_operand_type operands
[6];
538 /* Flags that should be checked. */
539 unsigned flag_classes
[5];
541 /* Mnemonic (smaller) alternative to be used later for relaxation. */
542 const char *mnemonic_alt
;
544 /* Index of operand that generic relaxation has to check. */
547 /* Base subtype index used. */
548 enum arc_rlx_types subtype
;
551 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
552 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
553 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
557 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
558 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
559 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
564 /* ARC relaxation table. */
565 const relax_typeS md_relax_table
[] =
572 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL
),
573 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
577 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B
),
578 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
583 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6
),
584 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM
),
585 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
587 /* LD_S a, [b, u7] ->
588 LD<zz><.x><.aa><.di> a, [b, s9] ->
589 LD<zz><.x><.aa><.di> a, [b, limm] */
590 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9
),
591 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM
),
592 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE
),
597 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12
),
598 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM
),
599 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
603 SUB<.f> a, b, limm. */
604 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6
),
605 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM
),
606 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
608 /* MPY<.f> a, b, u6 ->
609 MPY<.f> a, b, limm. */
610 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM
),
611 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
613 /* MOV<.f><.cc> b, u6 ->
614 MOV<.f><.cc> b, limm. */
615 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM
),
616 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
618 /* ADD<.f><.cc> b, b, u6 ->
619 ADD<.f><.cc> b, b, limm. */
620 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM
),
621 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
624 /* Order of this table's entries matters! */
625 const struct arc_relaxable_ins arc_relaxable_insns
[] =
627 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
628 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
629 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
630 2, ARC_RLX_ADD_RRU6
},
631 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
633 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
635 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
636 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
637 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
638 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
639 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
640 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
641 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
642 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
644 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
646 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
650 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
652 /* Flags to set in the elf header. */
653 static const flagword arc_initial_eflag
= 0x00;
655 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
656 symbolS
* GOT_symbol
= 0;
658 /* Set to TRUE when we assemble instructions. */
659 static bfd_boolean assembling_insn
= FALSE
;
661 /* Functions implementation. */
663 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
664 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
665 are no matching entries in ARC_OPCODE_HASH. */
667 static const struct arc_opcode_hash_entry
*
668 arc_find_opcode (const char *name
)
670 const struct arc_opcode_hash_entry
*entry
;
672 entry
= hash_find (arc_opcode_hash
, name
);
676 /* Initialise the iterator ITER. */
679 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
685 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
686 calls to this function. Return NULL when all ARC_OPCODE entries have
689 static const struct arc_opcode
*
690 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
691 struct arc_opcode_hash_entry_iterator
*iter
)
693 if (iter
->opcode
== NULL
&& iter
->index
== 0)
695 gas_assert (entry
->count
> 0);
696 iter
->opcode
= entry
->opcode
[iter
->index
];
698 else if (iter
->opcode
!= NULL
)
700 const char *old_name
= iter
->opcode
->name
;
703 if (iter
->opcode
->name
== NULL
704 || strcmp (old_name
, iter
->opcode
->name
) != 0)
707 if (iter
->index
== entry
->count
)
710 iter
->opcode
= entry
->opcode
[iter
->index
];
717 /* Insert an opcode into opcode hash structure. */
720 arc_insert_opcode (const struct arc_opcode
*opcode
)
722 const char *name
, *retval
;
723 struct arc_opcode_hash_entry
*entry
;
726 entry
= hash_find (arc_opcode_hash
, name
);
729 entry
= XNEW (struct arc_opcode_hash_entry
);
731 entry
->opcode
= NULL
;
733 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
735 as_fatal (_("internal error: can't hash opcode '%s': %s"),
739 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
742 if (entry
->opcode
== NULL
)
743 as_fatal (_("Virtual memory exhausted"));
745 entry
->opcode
[entry
->count
] = opcode
;
750 /* Like md_number_to_chars but used for limms. The 4-byte limm value,
751 is encoded as 'middle-endian' for a little-endian target. FIXME!
752 this function is used for regular 4 byte instructions as well. */
755 md_number_to_chars_midend (char *buf
, valueT val
, int n
)
759 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
760 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
764 md_number_to_chars (buf
, val
, n
);
768 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
769 the relevant static global variables. Parameter SEL describes where
770 this selection originated from. */
773 arc_select_cpu (const char *arg
, enum mach_selection_type sel
)
778 /* We should only set a default if we've not made a selection from some
780 gas_assert (sel
!= MACH_SELECTION_FROM_DEFAULT
781 || mach_selection_mode
== MACH_SELECTION_NONE
);
783 /* Look for a matching entry in CPU_TYPES array. */
784 for (i
= 0; cpu_types
[i
].name
; ++i
)
786 if (!strcasecmp (cpu_types
[i
].name
, arg
))
788 /* If a previous selection was made on the command line, then we
789 allow later selections on the command line to override earlier
790 ones. However, a selection from a '.cpu NAME' directive must
791 match the command line selection, or we give a warning. */
792 if (mach_selection_mode
== MACH_SELECTION_FROM_COMMAND_LINE
)
794 gas_assert (sel
== MACH_SELECTION_FROM_COMMAND_LINE
795 || sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
);
796 if (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
797 && selected_cpu
.mach
!= cpu_types
[i
].mach
)
799 as_warn (_("Command-line value overrides \".cpu\" directive"));
804 /* Initialise static global data about selected machine type. */
805 selected_cpu
.flags
= cpu_types
[i
].flags
;
806 selected_cpu
.name
= cpu_types
[i
].name
;
807 selected_cpu
.features
= cpu_types
[i
].features
;
808 selected_cpu
.mach
= cpu_types
[i
].mach
;
809 cpu_flags
= cpu_types
[i
].eflags
;
814 if (!cpu_types
[i
].name
)
815 as_fatal (_("unknown architecture: %s\n"), arg
);
816 gas_assert (cpu_flags
!= 0);
817 selected_cpu
.eflags
= (arc_initial_eflag
& ~EF_ARC_MACH_MSK
) | cpu_flags
;
818 mach_selection_mode
= sel
;
821 /* Here ends all the ARCompact extension instruction assembling
825 arc_extra_reloc (int r_type
)
828 symbolS
*sym
, *lab
= NULL
;
830 if (*input_line_pointer
== '@')
831 input_line_pointer
++;
832 c
= get_symbol_name (&sym_name
);
833 sym
= symbol_find_or_make (sym_name
);
834 restore_line_pointer (c
);
835 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
837 ++input_line_pointer
;
839 c
= get_symbol_name (&lab_name
);
840 lab
= symbol_find_or_make (lab_name
);
841 restore_line_pointer (c
);
844 /* These relocations exist as a mechanism for the compiler to tell the
845 linker how to patch the code if the tls model is optimised. However,
846 the relocation itself does not require any space within the assembler
847 fragment, and so we pass a size of 0.
849 The lines that generate these relocations look like this:
851 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
853 The '.tls_gd_ld @.tdata' is processed first and generates the
854 additional relocation, while the 'bl __tls_get_addr@plt' is processed
855 second and generates the additional branch.
857 It is possible that the additional relocation generated by the
858 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
859 while the 'bl __tls_get_addr@plt' will be generated as the first thing
860 in the next fragment. This will be fine; both relocations will still
861 appear to be at the same address in the generated object file.
862 However, this only works as the additional relocation is generated
863 with size of 0 bytes. */
865 = fix_new (frag_now
, /* Which frag? */
866 frag_now_fix (), /* Where in that frag? */
867 0, /* size: 1, 2, or 4 usually. */
868 sym
, /* X_add_symbol. */
869 0, /* X_add_number. */
870 FALSE
, /* TRUE if PC-relative relocation. */
871 r_type
/* Relocation type. */);
872 fixP
->fx_subsy
= lab
;
876 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
877 symbolS
*symbolP
, addressT size
)
882 if (*input_line_pointer
== ',')
884 align
= parse_align (1);
886 if (align
== (addressT
) -1)
901 bss_alloc (symbolP
, size
, align
);
902 S_CLEAR_EXTERNAL (symbolP
);
908 arc_lcomm (int ignore
)
910 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
913 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
916 /* Select the cpu we're assembling for. */
919 arc_option (int ignore ATTRIBUTE_UNUSED
)
923 const char *cpu_name
;
925 c
= get_symbol_name (&cpu
);
927 if ((!strcmp ("ARC600", cpu
))
928 || (!strcmp ("ARC601", cpu
))
929 || (!strcmp ("A6", cpu
)))
931 else if ((!strcmp ("ARC700", cpu
))
932 || (!strcmp ("A7", cpu
)))
934 else if (!strcmp ("EM", cpu
))
936 else if (!strcmp ("HS", cpu
))
938 else if (!strcmp ("NPS400", cpu
))
943 if (cpu_name
!= NULL
)
944 arc_select_cpu (cpu_name
, MACH_SELECTION_FROM_CPU_DIRECTIVE
);
946 as_fatal (_("invalid architecture `%s' in .cpu directive"), cpu
);
948 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
949 as_fatal (_("could not set architecture and machine"));
951 /* Set elf header flags. */
952 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
954 restore_line_pointer (c
);
955 demand_empty_rest_of_line ();
958 /* Smartly print an expression. */
961 debug_exp (expressionS
*t
)
963 const char *name ATTRIBUTE_UNUSED
;
964 const char *namemd ATTRIBUTE_UNUSED
;
966 pr_debug ("debug_exp: ");
970 default: name
= "unknown"; break;
971 case O_illegal
: name
= "O_illegal"; break;
972 case O_absent
: name
= "O_absent"; break;
973 case O_constant
: name
= "O_constant"; break;
974 case O_symbol
: name
= "O_symbol"; break;
975 case O_symbol_rva
: name
= "O_symbol_rva"; break;
976 case O_register
: name
= "O_register"; break;
977 case O_big
: name
= "O_big"; break;
978 case O_uminus
: name
= "O_uminus"; break;
979 case O_bit_not
: name
= "O_bit_not"; break;
980 case O_logical_not
: name
= "O_logical_not"; break;
981 case O_multiply
: name
= "O_multiply"; break;
982 case O_divide
: name
= "O_divide"; break;
983 case O_modulus
: name
= "O_modulus"; break;
984 case O_left_shift
: name
= "O_left_shift"; break;
985 case O_right_shift
: name
= "O_right_shift"; break;
986 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
987 case O_bit_or_not
: name
= "O_bit_or_not"; break;
988 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
989 case O_bit_and
: name
= "O_bit_and"; break;
990 case O_add
: name
= "O_add"; break;
991 case O_subtract
: name
= "O_subtract"; break;
992 case O_eq
: name
= "O_eq"; break;
993 case O_ne
: name
= "O_ne"; break;
994 case O_lt
: name
= "O_lt"; break;
995 case O_le
: name
= "O_le"; break;
996 case O_ge
: name
= "O_ge"; break;
997 case O_gt
: name
= "O_gt"; break;
998 case O_logical_and
: name
= "O_logical_and"; break;
999 case O_logical_or
: name
= "O_logical_or"; break;
1000 case O_index
: name
= "O_index"; break;
1001 case O_bracket
: name
= "O_bracket"; break;
1002 case O_colon
: name
= "O_colon"; break;
1003 case O_addrtype
: name
= "O_addrtype"; break;
1008 default: namemd
= "unknown"; break;
1009 case O_gotoff
: namemd
= "O_gotoff"; break;
1010 case O_gotpc
: namemd
= "O_gotpc"; break;
1011 case O_plt
: namemd
= "O_plt"; break;
1012 case O_sda
: namemd
= "O_sda"; break;
1013 case O_pcl
: namemd
= "O_pcl"; break;
1014 case O_tlsgd
: namemd
= "O_tlsgd"; break;
1015 case O_tlsie
: namemd
= "O_tlsie"; break;
1016 case O_tpoff9
: namemd
= "O_tpoff9"; break;
1017 case O_tpoff
: namemd
= "O_tpoff"; break;
1018 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
1019 case O_dtpoff
: namemd
= "O_dtpoff"; break;
1022 pr_debug ("%s (%s, %s, %d, %s)", name
,
1023 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
1024 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
1025 (int) t
->X_add_number
,
1026 (t
->X_md
) ? namemd
: "--");
1031 /* Parse the arguments to an opcode. */
1034 tokenize_arguments (char *str
,
1038 char *old_input_line_pointer
;
1039 bfd_boolean saw_comma
= FALSE
;
1040 bfd_boolean saw_arg
= FALSE
;
1045 const struct arc_reloc_op_tag
*r
;
1047 char *reloc_name
, c
;
1049 memset (tok
, 0, sizeof (*tok
) * ntok
);
1051 /* Save and restore input_line_pointer around this function. */
1052 old_input_line_pointer
= input_line_pointer
;
1053 input_line_pointer
= str
;
1055 while (*input_line_pointer
)
1058 switch (*input_line_pointer
)
1064 input_line_pointer
++;
1065 if (saw_comma
|| !saw_arg
)
1072 ++input_line_pointer
;
1074 if (!saw_arg
|| num_args
== ntok
)
1076 tok
->X_op
= O_bracket
;
1083 input_line_pointer
++;
1084 if (brk_lvl
|| num_args
== ntok
)
1087 tok
->X_op
= O_bracket
;
1093 input_line_pointer
++;
1094 if (!saw_arg
|| num_args
== ntok
)
1096 tok
->X_op
= O_colon
;
1103 /* We have labels, function names and relocations, all
1104 starting with @ symbol. Sort them out. */
1105 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1109 tok
->X_op
= O_symbol
;
1110 tok
->X_md
= O_absent
;
1112 if (*input_line_pointer
!= '@')
1113 goto normalsymbol
; /* This is not a relocation. */
1117 /* A relocation opernad has the following form
1118 @identifier@relocation_type. The identifier is already
1120 if (tok
->X_op
!= O_symbol
)
1122 as_bad (_("No valid label relocation operand"));
1126 /* Parse @relocation_type. */
1127 input_line_pointer
++;
1128 c
= get_symbol_name (&reloc_name
);
1129 len
= input_line_pointer
- reloc_name
;
1132 as_bad (_("No relocation operand"));
1136 /* Go through known relocation and try to find a match. */
1137 r
= &arc_reloc_op
[0];
1138 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1139 if (len
== r
->length
1140 && memcmp (reloc_name
, r
->name
, len
) == 0)
1144 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1148 *input_line_pointer
= c
;
1149 SKIP_WHITESPACE_AFTER_NAME ();
1150 /* Extra check for TLS: base. */
1151 if (*input_line_pointer
== '@')
1154 if (tok
->X_op_symbol
!= NULL
1155 || tok
->X_op
!= O_symbol
)
1157 as_bad (_("Unable to parse TLS base: %s"),
1158 input_line_pointer
);
1161 input_line_pointer
++;
1163 c
= get_symbol_name (&sym_name
);
1164 base
= symbol_find_or_make (sym_name
);
1165 tok
->X_op
= O_subtract
;
1166 tok
->X_op_symbol
= base
;
1167 restore_line_pointer (c
);
1168 tmpE
.X_add_number
= 0;
1170 if ((*input_line_pointer
!= '+')
1171 && (*input_line_pointer
!= '-'))
1173 tmpE
.X_add_number
= 0;
1177 /* Parse the constant of a complex relocation expression
1178 like @identifier@reloc +/- const. */
1179 if (! r
->complex_expr
)
1181 as_bad (_("@%s is not a complex relocation."), r
->name
);
1185 if (tmpE
.X_op
!= O_constant
)
1187 as_bad (_("Bad expression: @%s + %s."),
1188 r
->name
, input_line_pointer
);
1194 tok
->X_add_number
= tmpE
.X_add_number
;
1205 /* Can be a register. */
1206 ++input_line_pointer
;
1210 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1213 tok
->X_op
= O_absent
;
1214 tok
->X_md
= O_absent
;
1217 /* Legacy: There are cases when we have
1218 identifier@relocation_type, if it is the case parse the
1219 relocation type as well. */
1220 if (*input_line_pointer
== '@')
1226 if (tok
->X_op
== O_illegal
1227 || tok
->X_op
== O_absent
1228 || num_args
== ntok
)
1240 if (saw_comma
|| brk_lvl
)
1242 input_line_pointer
= old_input_line_pointer
;
1248 as_bad (_("Brackets in operand field incorrect"));
1250 as_bad (_("extra comma"));
1252 as_bad (_("missing argument"));
1254 as_bad (_("missing comma or colon"));
1255 input_line_pointer
= old_input_line_pointer
;
1259 /* Parse the flags to a structure. */
1262 tokenize_flags (const char *str
,
1263 struct arc_flags flags
[],
1266 char *old_input_line_pointer
;
1267 bfd_boolean saw_flg
= FALSE
;
1268 bfd_boolean saw_dot
= FALSE
;
1272 memset (flags
, 0, sizeof (*flags
) * nflg
);
1274 /* Save and restore input_line_pointer around this function. */
1275 old_input_line_pointer
= input_line_pointer
;
1276 input_line_pointer
= (char *) str
;
1278 while (*input_line_pointer
)
1280 switch (*input_line_pointer
)
1287 input_line_pointer
++;
1295 if (saw_flg
&& !saw_dot
)
1298 if (num_flags
>= nflg
)
1301 flgnamelen
= strspn (input_line_pointer
,
1302 "abcdefghijklmnopqrstuvwxyz0123456789");
1303 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1306 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1308 input_line_pointer
+= flgnamelen
;
1318 input_line_pointer
= old_input_line_pointer
;
1323 as_bad (_("extra dot"));
1325 as_bad (_("unrecognized flag"));
1327 as_bad (_("failed to parse flags"));
1328 input_line_pointer
= old_input_line_pointer
;
1332 /* Apply the fixups in order. */
1335 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1339 for (i
= 0; i
< insn
->nfixups
; i
++)
1341 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1342 int size
, pcrel
, offset
= 0;
1344 /* FIXME! the reloc size is wrong in the BFD file.
1345 When it is fixed please delete me. */
1346 size
= (insn
->short_insn
&& !fixup
->islong
) ? 2 : 4;
1349 offset
= (insn
->short_insn
) ? 2 : 4;
1351 /* Some fixups are only used internally, thus no howto. */
1352 if ((int) fixup
->reloc
== 0)
1353 as_fatal (_("Unhandled reloc type"));
1355 if ((int) fixup
->reloc
< 0)
1357 /* FIXME! the reloc size is wrong in the BFD file.
1358 When it is fixed please enable me.
1359 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1360 pcrel
= fixup
->pcrel
;
1364 reloc_howto_type
*reloc_howto
=
1365 bfd_reloc_type_lookup (stdoutput
,
1366 (bfd_reloc_code_real_type
) fixup
->reloc
);
1367 gas_assert (reloc_howto
);
1369 /* FIXME! the reloc size is wrong in the BFD file.
1370 When it is fixed please enable me.
1371 size = bfd_get_reloc_size (reloc_howto); */
1372 pcrel
= reloc_howto
->pc_relative
;
1375 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1377 fragP
->fr_file
, fragP
->fr_line
,
1378 (fixup
->reloc
< 0) ? "Internal" :
1379 bfd_get_reloc_code_name (fixup
->reloc
),
1382 fix_new_exp (fragP
, fix
+ offset
,
1383 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1385 /* Check for ZOLs, and update symbol info if any. */
1386 if (LP_INSN (insn
->insn
))
1388 gas_assert (fixup
->exp
.X_add_symbol
);
1389 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1394 /* Actually output an instruction with its fixup. */
1397 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1401 pr_debug ("Emit insn : 0x%x\n", insn
->insn
);
1402 pr_debug ("\tShort : 0x%d\n", insn
->short_insn
);
1403 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1405 /* Write out the instruction. */
1406 if (insn
->short_insn
)
1412 md_number_to_chars (f
, insn
->insn
, 2);
1413 md_number_to_chars_midend (f
+ 2, insn
->limm
, 4);
1414 dwarf2_emit_insn (6);
1420 md_number_to_chars (f
, insn
->insn
, 2);
1421 dwarf2_emit_insn (2);
1430 md_number_to_chars_midend (f
, insn
->insn
, 4);
1431 md_number_to_chars_midend (f
+ 4, insn
->limm
, 4);
1432 dwarf2_emit_insn (8);
1438 md_number_to_chars_midend (f
, insn
->insn
, 4);
1439 dwarf2_emit_insn (4);
1444 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1448 emit_insn1 (struct arc_insn
*insn
)
1450 /* How frag_var's args are currently configured:
1451 - rs_machine_dependent, to dictate it's a relaxation frag.
1452 - FRAG_MAX_GROWTH, maximum size of instruction
1453 - 0, variable size that might grow...unused by generic relaxation.
1454 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1455 - s, opand expression.
1456 - 0, offset but it's unused.
1457 - 0, opcode but it's unused. */
1458 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1459 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1461 if (frag_room () < FRAG_MAX_GROWTH
)
1463 /* Handle differently when frag literal memory is exhausted.
1464 This is used because when there's not enough memory left in
1465 the current frag, a new frag is created and the information
1466 we put into frag_now->tc_frag_data is disregarded. */
1468 struct arc_relax_type relax_info_copy
;
1469 relax_substateT subtype
= frag_now
->fr_subtype
;
1471 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1472 sizeof (struct arc_relax_type
));
1474 frag_wane (frag_now
);
1475 frag_grow (FRAG_MAX_GROWTH
);
1477 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1478 sizeof (struct arc_relax_type
));
1480 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1484 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1485 frag_now
->fr_subtype
, s
, 0, 0);
1489 emit_insn (struct arc_insn
*insn
)
1494 emit_insn0 (insn
, NULL
, FALSE
);
1497 /* Check whether a symbol involves a register. */
1500 contains_register (symbolS
*sym
)
1504 expressionS
*ex
= symbol_get_value_expression (sym
);
1506 return ((O_register
== ex
->X_op
)
1507 && !contains_register (ex
->X_add_symbol
)
1508 && !contains_register (ex
->X_op_symbol
));
1514 /* Returns the register number within a symbol. */
1517 get_register (symbolS
*sym
)
1519 if (!contains_register (sym
))
1522 expressionS
*ex
= symbol_get_value_expression (sym
);
1523 return regno (ex
->X_add_number
);
1526 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1527 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1530 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1537 case BFD_RELOC_ARC_SDA_LDST
:
1538 case BFD_RELOC_ARC_SDA_LDST1
:
1539 case BFD_RELOC_ARC_SDA_LDST2
:
1540 case BFD_RELOC_ARC_SDA16_LD
:
1541 case BFD_RELOC_ARC_SDA16_LD1
:
1542 case BFD_RELOC_ARC_SDA16_LD2
:
1543 case BFD_RELOC_ARC_SDA16_ST2
:
1544 case BFD_RELOC_ARC_SDA32_ME
:
1551 /* Allocates a tok entry. */
1554 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1556 if (ntok
> MAX_INSN_ARGS
- 2)
1557 return 0; /* No space left. */
1560 return 0; /* Incorect args. */
1562 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1565 return 1; /* Success. */
1566 return allocate_tok (tok
, ntok
- 1, cidx
);
1569 /* Check if an particular ARC feature is enabled. */
1572 check_cpu_feature (insn_subclass_t sc
)
1574 if (is_code_density_p (sc
) && !(selected_cpu
.features
& ARC_CD
))
1577 if (is_spfp_p (sc
) && !(selected_cpu
.features
& ARC_SPFP
))
1580 if (is_dpfp_p (sc
) && !(selected_cpu
.features
& ARC_DPFP
))
1583 if (is_fpuda_p (sc
) && !(selected_cpu
.features
& ARC_FPUDA
))
1586 if (is_nps400_p (sc
) && !(selected_cpu
.features
& ARC_NPS400
))
1592 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1593 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1594 array and returns TRUE if the flag operands all match, otherwise,
1595 returns FALSE, in which case the FIRST_PFLAG array may have been
1599 parse_opcode_flags (const struct arc_opcode
*opcode
,
1601 struct arc_flags
*first_pflag
)
1604 const unsigned char *flgidx
;
1607 for (i
= 0; i
< nflgs
; i
++)
1608 first_pflag
[i
].flgp
= NULL
;
1610 /* Check the flags. Iterate over the valid flag classes. */
1611 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1613 /* Get a valid flag class. */
1614 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1615 const unsigned *flgopridx
;
1617 struct arc_flags
*pflag
= NULL
;
1619 /* Check for extension conditional codes. */
1620 if (ext_condcode
.arc_ext_condcode
1621 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1623 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1626 pflag
= first_pflag
;
1627 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1629 if (!strcmp (pf
->name
, pflag
->name
))
1631 if (pflag
->flgp
!= NULL
)
1644 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1646 const struct arc_flag_operand
*flg_operand
;
1648 pflag
= first_pflag
;
1649 flg_operand
= &arc_flag_operands
[*flgopridx
];
1650 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1652 /* Match against the parsed flags. */
1653 if (!strcmp (flg_operand
->name
, pflag
->name
))
1655 if (pflag
->flgp
!= NULL
)
1658 pflag
->flgp
= flg_operand
;
1660 break; /* goto next flag class and parsed flag. */
1665 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1667 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1671 /* Did I check all the parsed flags? */
1672 return lnflg
? FALSE
: TRUE
;
1676 /* Search forward through all variants of an opcode looking for a
1679 static const struct arc_opcode
*
1680 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1683 struct arc_flags
*first_pflag
,
1687 const struct arc_opcode
*opcode
;
1688 struct arc_opcode_hash_entry_iterator iter
;
1690 int got_cpu_match
= 0;
1691 expressionS bktok
[MAX_INSN_ARGS
];
1695 arc_opcode_hash_entry_iterator_init (&iter
);
1696 memset (&emptyE
, 0, sizeof (emptyE
));
1697 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1700 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1702 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1704 const unsigned char *opidx
;
1706 const expressionS
*t
= &emptyE
;
1708 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1709 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1711 /* Don't match opcodes that don't exist on this
1713 if (!(opcode
->cpu
& selected_cpu
.flags
))
1716 if (!check_cpu_feature (opcode
->subclass
))
1722 /* Check the operands. */
1723 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1725 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1727 /* Only take input from real operands. */
1728 if (ARC_OPERAND_IS_FAKE (operand
))
1731 /* When we expect input, make sure we have it. */
1735 /* Match operand type with expression type. */
1736 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1738 case ARC_OPERAND_ADDRTYPE
:
1739 /* Check to be an address type. */
1740 if (tok
[tokidx
].X_op
!= O_addrtype
)
1744 case ARC_OPERAND_IR
:
1745 /* Check to be a register. */
1746 if ((tok
[tokidx
].X_op
!= O_register
1747 || !is_ir_num (tok
[tokidx
].X_add_number
))
1748 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1751 /* If expect duplicate, make sure it is duplicate. */
1752 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1754 /* Check for duplicate. */
1755 if (t
->X_op
!= O_register
1756 || !is_ir_num (t
->X_add_number
)
1757 || (regno (t
->X_add_number
) !=
1758 regno (tok
[tokidx
].X_add_number
)))
1762 /* Special handling? */
1763 if (operand
->insert
)
1765 const char *errmsg
= NULL
;
1766 (*operand
->insert
)(0,
1767 regno (tok
[tokidx
].X_add_number
),
1771 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1773 /* Missing argument, create one. */
1774 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1777 tok
[tokidx
].X_op
= O_absent
;
1788 case ARC_OPERAND_BRAKET
:
1789 /* Check if bracket is also in opcode table as
1791 if (tok
[tokidx
].X_op
!= O_bracket
)
1795 case ARC_OPERAND_COLON
:
1796 /* Check if colon is also in opcode table as operand. */
1797 if (tok
[tokidx
].X_op
!= O_colon
)
1801 case ARC_OPERAND_LIMM
:
1802 case ARC_OPERAND_SIGNED
:
1803 case ARC_OPERAND_UNSIGNED
:
1804 switch (tok
[tokidx
].X_op
)
1812 /* Got an (too) early bracket, check if it is an
1813 ignored operand. N.B. This procedure works only
1814 when bracket is the last operand! */
1815 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1817 /* Insert the missing operand. */
1818 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1821 tok
[tokidx
].X_op
= O_absent
;
1828 const struct arc_aux_reg
*auxr
;
1830 if (opcode
->insn_class
!= AUXREG
)
1832 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1834 auxr
= hash_find (arc_aux_hash
, p
);
1837 /* We modify the token array here, safe in the
1838 knowledge, that if this was the wrong
1839 choice then the original contents will be
1840 restored from BKTOK. */
1841 tok
[tokidx
].X_op
= O_constant
;
1842 tok
[tokidx
].X_add_number
= auxr
->address
;
1843 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1846 if (tok
[tokidx
].X_op
!= O_constant
)
1851 /* Check the range. */
1852 if (operand
->bits
!= 32
1853 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1855 offsetT min
, max
, val
;
1856 val
= tok
[tokidx
].X_add_number
;
1858 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1860 max
= (1 << (operand
->bits
- 1)) - 1;
1861 min
= -(1 << (operand
->bits
- 1));
1865 max
= (1 << operand
->bits
) - 1;
1869 if (val
< min
|| val
> max
)
1872 /* Check alignmets. */
1873 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1877 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1881 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1883 if (operand
->insert
)
1885 const char *errmsg
= NULL
;
1886 (*operand
->insert
)(0,
1887 tok
[tokidx
].X_add_number
,
1892 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1898 /* Check if it is register range. */
1899 if ((tok
[tokidx
].X_add_number
== 0)
1900 && contains_register (tok
[tokidx
].X_add_symbol
)
1901 && contains_register (tok
[tokidx
].X_op_symbol
))
1905 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1907 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1908 if (operand
->insert
)
1910 const char *errmsg
= NULL
;
1911 (*operand
->insert
)(0,
1924 if (operand
->default_reloc
== 0)
1925 goto match_failed
; /* The operand needs relocation. */
1927 /* Relocs requiring long immediate. FIXME! make it
1928 generic and move it to a function. */
1929 switch (tok
[tokidx
].X_md
)
1938 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
1942 if (!generic_reloc_p (operand
->default_reloc
))
1950 /* If expect duplicate, make sure it is duplicate. */
1951 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1953 if (t
->X_op
== O_illegal
1954 || t
->X_op
== O_absent
1955 || t
->X_op
== O_register
1956 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
1963 /* Everything else should have been fake. */
1971 /* Setup ready for flag parsing. */
1972 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
1976 /* Possible match -- did we use all of our input? */
1986 /* Restore the original parameters. */
1987 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
1992 *pcpumatch
= got_cpu_match
;
1997 /* Swap operand tokens. */
2000 swap_operand (expressionS
*operand_array
,
2002 unsigned destination
)
2004 expressionS cpy_operand
;
2005 expressionS
*src_operand
;
2006 expressionS
*dst_operand
;
2009 if (source
== destination
)
2012 src_operand
= &operand_array
[source
];
2013 dst_operand
= &operand_array
[destination
];
2014 size
= sizeof (expressionS
);
2016 /* Make copy of operand to swap with and swap. */
2017 memcpy (&cpy_operand
, dst_operand
, size
);
2018 memcpy (dst_operand
, src_operand
, size
);
2019 memcpy (src_operand
, &cpy_operand
, size
);
2022 /* Check if *op matches *tok type.
2023 Returns FALSE if they don't match, TRUE if they match. */
2026 pseudo_operand_match (const expressionS
*tok
,
2027 const struct arc_operand_operation
*op
)
2029 offsetT min
, max
, val
;
2031 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
2037 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
2039 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
2041 val
= tok
->X_add_number
+ op
->count
;
2042 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
2044 max
= (1 << (operand_real
->bits
- 1)) - 1;
2045 min
= -(1 << (operand_real
->bits
- 1));
2049 max
= (1 << operand_real
->bits
) - 1;
2052 if (min
<= val
&& val
<= max
)
2058 /* Handle all symbols as long immediates or signed 9. */
2059 if (operand_real
->flags
& ARC_OPERAND_LIMM
2060 || ((operand_real
->flags
& ARC_OPERAND_SIGNED
)
2061 && operand_real
->bits
== 9))
2066 if (operand_real
->flags
& ARC_OPERAND_IR
)
2071 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2082 /* Find pseudo instruction in array. */
2084 static const struct arc_pseudo_insn
*
2085 find_pseudo_insn (const char *opname
,
2087 const expressionS
*tok
)
2089 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2090 const struct arc_operand_operation
*op
;
2094 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2096 pseudo_insn
= &arc_pseudo_insns
[i
];
2097 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2099 op
= pseudo_insn
->operand
;
2100 for (j
= 0; j
< ntok
; ++j
)
2101 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2104 /* Found the right instruction. */
2112 /* Assumes the expressionS *tok is of sufficient size. */
2114 static const struct arc_opcode_hash_entry
*
2115 find_special_case_pseudo (const char *opname
,
2119 struct arc_flags
*pflags
)
2121 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2122 const struct arc_operand_operation
*operand_pseudo
;
2123 const struct arc_operand
*operand_real
;
2125 char construct_operand
[MAX_CONSTR_STR
];
2127 /* Find whether opname is in pseudo instruction array. */
2128 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2130 if (pseudo_insn
== NULL
)
2133 /* Handle flag, Limited to one flag at the moment. */
2134 if (pseudo_insn
->flag_r
!= NULL
)
2135 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2136 MAX_INSN_FLGS
- *nflgs
);
2138 /* Handle operand operations. */
2139 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2141 operand_pseudo
= &pseudo_insn
->operand
[i
];
2142 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2144 if (operand_real
->flags
& ARC_OPERAND_BRAKET
2145 && !operand_pseudo
->needs_insert
)
2148 /* Has to be inserted (i.e. this token does not exist yet). */
2149 if (operand_pseudo
->needs_insert
)
2151 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2153 tok
[i
].X_op
= O_bracket
;
2158 /* Check if operand is a register or constant and handle it
2160 if (operand_real
->flags
& ARC_OPERAND_IR
)
2161 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2162 operand_pseudo
->count
);
2164 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2165 operand_pseudo
->count
);
2167 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2171 else if (operand_pseudo
->count
)
2173 /* Operand number has to be adjusted accordingly (by operand
2175 switch (tok
[i
].X_op
)
2178 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2191 /* Swap operands if necessary. Only supports one swap at the
2193 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2195 operand_pseudo
= &pseudo_insn
->operand
[i
];
2197 if (operand_pseudo
->swap_operand_idx
== i
)
2200 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2202 /* Prevent a swap back later by breaking out. */
2206 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2209 static const struct arc_opcode_hash_entry
*
2210 find_special_case_flag (const char *opname
,
2212 struct arc_flags
*pflags
)
2216 unsigned flag_idx
, flag_arr_idx
;
2217 size_t flaglen
, oplen
;
2218 const struct arc_flag_special
*arc_flag_special_opcode
;
2219 const struct arc_opcode_hash_entry
*entry
;
2221 /* Search for special case instruction. */
2222 for (i
= 0; i
< arc_num_flag_special
; i
++)
2224 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2225 oplen
= strlen (arc_flag_special_opcode
->name
);
2227 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2230 /* Found a potential special case instruction, now test for
2232 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2234 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2236 break; /* End of array, nothing found. */
2238 flagnm
= arc_flag_operands
[flag_idx
].name
;
2239 flaglen
= strlen (flagnm
);
2240 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2242 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2244 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2246 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2247 pflags
[*nflgs
].name
[flaglen
] = '\0';
2256 /* The long instructions are not stored in a hash (there's not many of
2257 them) and so there's no arc_opcode_hash_entry structure to return. This
2258 helper function for find_special_case_long_opcode takes an arc_opcode
2259 result and places it into a fake arc_opcode_hash_entry that points to
2260 the single arc_opcode OPCODE, which is then returned. */
2262 static const struct arc_opcode_hash_entry
*
2263 build_fake_opcode_hash_entry (const struct arc_opcode
*opcode
)
2265 static struct arc_opcode_hash_entry entry
;
2266 static struct arc_opcode tmp
[2];
2267 static const struct arc_opcode
*ptr
[2];
2269 memcpy (&tmp
[0], opcode
, sizeof (struct arc_opcode
));
2270 memset (&tmp
[1], 0, sizeof (struct arc_opcode
));
2279 /* Used by the assembler to match the list of tokens against a long (48 or
2280 64 bits) instruction. If a matching long instruction is found, then
2281 some of the tokens are consumed in this function and converted into a
2282 single LIMM value, which is then added to the end of the token list,
2283 where it will be consumed by a LIMM operand that exists in the base
2284 opcode of the long instruction. */
2286 static const struct arc_opcode_hash_entry
*
2287 find_special_case_long_opcode (const char *opname
,
2288 int *ntok ATTRIBUTE_UNUSED
,
2289 expressionS
*tok ATTRIBUTE_UNUSED
,
2291 struct arc_flags
*pflags
)
2295 if (*ntok
== MAX_INSN_ARGS
)
2298 for (i
= 0; i
< arc_num_long_opcodes
; ++i
)
2300 struct arc_opcode fake_opcode
;
2301 const struct arc_opcode
*opcode
;
2302 struct arc_insn insn
;
2303 expressionS
*limm_token
;
2305 opcode
= &arc_long_opcodes
[i
].base_opcode
;
2307 if (!(opcode
->cpu
& selected_cpu
.flags
))
2310 if (!check_cpu_feature (opcode
->subclass
))
2313 if (strcmp (opname
, opcode
->name
) != 0)
2316 /* Check that the flags are a match. */
2317 if (!parse_opcode_flags (opcode
, *nflgs
, pflags
))
2320 /* Parse the LIMM operands into the LIMM template. */
2321 memset (&fake_opcode
, 0, sizeof (fake_opcode
));
2322 fake_opcode
.name
= "fake limm";
2323 fake_opcode
.opcode
= arc_long_opcodes
[i
].limm_template
;
2324 fake_opcode
.mask
= arc_long_opcodes
[i
].limm_mask
;
2325 fake_opcode
.cpu
= opcode
->cpu
;
2326 fake_opcode
.insn_class
= opcode
->insn_class
;
2327 fake_opcode
.subclass
= opcode
->subclass
;
2328 memcpy (&fake_opcode
.operands
[0],
2329 &arc_long_opcodes
[i
].operands
,
2331 /* Leave fake_opcode.flags as zero. */
2333 pr_debug ("Calling assemble_insn to build fake limm value\n");
2334 assemble_insn (&fake_opcode
, tok
, *ntok
,
2336 pr_debug (" got limm value: 0x%x\n", insn
.insn
);
2338 /* Now create a new token at the end of the token array (We know this
2339 is safe as the token array is always created with enough space for
2340 MAX_INSN_ARGS, and we check at the start at the start of this
2341 function that we're not there yet). This new token will
2342 correspond to a LIMM operand that will be contained in the
2343 base_opcode of the arc_long_opcode. */
2344 limm_token
= &tok
[(*ntok
)];
2347 /* Modify the LIMM token to hold the constant. */
2348 limm_token
->X_op
= O_constant
;
2349 limm_token
->X_add_number
= insn
.insn
;
2351 /* Return the base opcode. */
2352 return build_fake_opcode_hash_entry (opcode
);
2358 /* Used to find special case opcode. */
2360 static const struct arc_opcode_hash_entry
*
2361 find_special_case (const char *opname
,
2363 struct arc_flags
*pflags
,
2367 const struct arc_opcode_hash_entry
*entry
;
2369 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2372 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2375 entry
= find_special_case_long_opcode (opname
, ntok
, tok
, nflgs
, pflags
);
2380 /* Given an opcode name, pre-tockenized set of argumenst and the
2381 opcode flags, take it all the way through emission. */
2384 assemble_tokens (const char *opname
,
2387 struct arc_flags
*pflags
,
2390 bfd_boolean found_something
= FALSE
;
2391 const struct arc_opcode_hash_entry
*entry
;
2394 /* Search opcodes. */
2395 entry
= arc_find_opcode (opname
);
2397 /* Couldn't find opcode conventional way, try special cases. */
2399 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2403 const struct arc_opcode
*opcode
;
2405 pr_debug ("%s:%d: assemble_tokens: %s\n",
2406 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2407 found_something
= TRUE
;
2408 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2412 struct arc_insn insn
;
2414 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2420 if (found_something
)
2423 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2425 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2429 as_bad (_("unknown opcode '%s'"), opname
);
2432 /* The public interface to the instruction assembler. */
2435 md_assemble (char *str
)
2438 expressionS tok
[MAX_INSN_ARGS
];
2441 struct arc_flags flags
[MAX_INSN_FLGS
];
2443 /* Split off the opcode. */
2444 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2445 opname
= xmemdup0 (str
, opnamelen
);
2447 /* Signalize we are assmbling the instructions. */
2448 assembling_insn
= TRUE
;
2450 /* Tokenize the flags. */
2451 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2453 as_bad (_("syntax error"));
2457 /* Scan up to the end of the mnemonic which must end in space or end
2460 for (; *str
!= '\0'; str
++)
2464 /* Tokenize the rest of the line. */
2465 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2467 as_bad (_("syntax error"));
2471 /* Finish it off. */
2472 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2473 assembling_insn
= FALSE
;
2476 /* Callback to insert a register into the hash table. */
2479 declare_register (const char *name
, int number
)
2482 symbolS
*regS
= symbol_create (name
, reg_section
,
2483 number
, &zero_address_frag
);
2485 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2487 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2491 /* Construct symbols for each of the general registers. */
2494 declare_register_set (void)
2497 for (i
= 0; i
< 64; ++i
)
2501 sprintf (name
, "r%d", i
);
2502 declare_register (name
, i
);
2503 if ((i
& 0x01) == 0)
2505 sprintf (name
, "r%dr%d", i
, i
+1);
2506 declare_register (name
, i
);
2511 /* Construct a symbol for an address type. */
2514 declare_addrtype (const char *name
, int number
)
2517 symbolS
*addrtypeS
= symbol_create (name
, undefined_section
,
2518 number
, &zero_address_frag
);
2520 err
= hash_insert (arc_addrtype_hash
, S_GET_NAME (addrtypeS
),
2521 (void *) addrtypeS
);
2523 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2527 /* Port-specific assembler initialization. This function is called
2528 once, at assembler startup time. */
2533 const struct arc_opcode
*opcode
= arc_opcodes
;
2535 if (mach_selection_mode
== MACH_SELECTION_NONE
)
2536 arc_select_cpu (TARGET_WITH_CPU
, MACH_SELECTION_FROM_DEFAULT
);
2538 /* The endianness can be chosen "at the factory". */
2539 target_big_endian
= byte_order
== BIG_ENDIAN
;
2541 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
2542 as_warn (_("could not set architecture and machine"));
2544 /* Set elf header flags. */
2545 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
2547 /* Set up a hash table for the instructions. */
2548 arc_opcode_hash
= hash_new ();
2549 if (arc_opcode_hash
== NULL
)
2550 as_fatal (_("Virtual memory exhausted"));
2552 /* Initialize the hash table with the insns. */
2555 const char *name
= opcode
->name
;
2557 arc_insert_opcode (opcode
);
2559 while (++opcode
&& opcode
->name
2560 && (opcode
->name
== name
2561 || !strcmp (opcode
->name
, name
)))
2563 }while (opcode
->name
);
2565 /* Register declaration. */
2566 arc_reg_hash
= hash_new ();
2567 if (arc_reg_hash
== NULL
)
2568 as_fatal (_("Virtual memory exhausted"));
2570 declare_register_set ();
2571 declare_register ("gp", 26);
2572 declare_register ("fp", 27);
2573 declare_register ("sp", 28);
2574 declare_register ("ilink", 29);
2575 declare_register ("ilink1", 29);
2576 declare_register ("ilink2", 30);
2577 declare_register ("blink", 31);
2579 /* XY memory registers. */
2580 declare_register ("x0_u0", 32);
2581 declare_register ("x0_u1", 33);
2582 declare_register ("x1_u0", 34);
2583 declare_register ("x1_u1", 35);
2584 declare_register ("x2_u0", 36);
2585 declare_register ("x2_u1", 37);
2586 declare_register ("x3_u0", 38);
2587 declare_register ("x3_u1", 39);
2588 declare_register ("y0_u0", 40);
2589 declare_register ("y0_u1", 41);
2590 declare_register ("y1_u0", 42);
2591 declare_register ("y1_u1", 43);
2592 declare_register ("y2_u0", 44);
2593 declare_register ("y2_u1", 45);
2594 declare_register ("y3_u0", 46);
2595 declare_register ("y3_u1", 47);
2596 declare_register ("x0_nu", 48);
2597 declare_register ("x1_nu", 49);
2598 declare_register ("x2_nu", 50);
2599 declare_register ("x3_nu", 51);
2600 declare_register ("y0_nu", 52);
2601 declare_register ("y1_nu", 53);
2602 declare_register ("y2_nu", 54);
2603 declare_register ("y3_nu", 55);
2605 declare_register ("mlo", 57);
2606 declare_register ("mmid", 58);
2607 declare_register ("mhi", 59);
2609 declare_register ("acc1", 56);
2610 declare_register ("acc2", 57);
2612 declare_register ("lp_count", 60);
2613 declare_register ("pcl", 63);
2615 /* Initialize the last instructions. */
2616 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2618 /* Aux register declaration. */
2619 arc_aux_hash
= hash_new ();
2620 if (arc_aux_hash
== NULL
)
2621 as_fatal (_("Virtual memory exhausted"));
2623 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2625 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2629 if (!(auxr
->cpu
& selected_cpu
.flags
))
2632 if ((auxr
->subclass
!= NONE
)
2633 && !check_cpu_feature (auxr
->subclass
))
2636 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2638 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2639 auxr
->name
, retval
);
2642 /* Address type declaration. */
2643 arc_addrtype_hash
= hash_new ();
2644 if (arc_addrtype_hash
== NULL
)
2645 as_fatal (_("Virtual memory exhausted"));
2647 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD
);
2648 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID
);
2649 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD
);
2650 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD
);
2651 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD
);
2652 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM
);
2653 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA
);
2654 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD
);
2655 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD
);
2656 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD
);
2657 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID
);
2658 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD
);
2659 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM
);
2660 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD
);
2661 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA
);
2662 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD
);
2665 /* Write a value out to the object file, using the appropriate
2669 md_number_to_chars (char *buf
,
2673 if (target_big_endian
)
2674 number_to_chars_bigendian (buf
, val
, n
);
2676 number_to_chars_littleendian (buf
, val
, n
);
2679 /* Round up a section size to the appropriate boundary. */
2682 md_section_align (segT segment
,
2685 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2687 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2690 /* The location from which a PC relative jump should be calculated,
2691 given a PC relative reloc. */
2694 md_pcrel_from_section (fixS
*fixP
,
2697 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2699 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2701 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2702 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2703 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2705 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2707 /* The symbol is undefined (or is defined but not in this section).
2708 Let the linker figure it out. */
2712 if ((int) fixP
->fx_r_type
< 0)
2714 /* These are the "internal" relocations. Align them to
2715 32 bit boundary (PCL), for the moment. */
2720 switch (fixP
->fx_r_type
)
2722 case BFD_RELOC_ARC_PC32
:
2723 /* The hardware calculates relative to the start of the
2724 insn, but this relocation is relative to location of the
2725 LIMM, compensate. The base always needs to be
2726 substracted by 4 as we do not support this type of PCrel
2727 relocation for short instructions. */
2730 case BFD_RELOC_ARC_PLT32
:
2731 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2732 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2733 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2734 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2736 case BFD_RELOC_ARC_S21H_PCREL
:
2737 case BFD_RELOC_ARC_S25H_PCREL
:
2738 case BFD_RELOC_ARC_S13_PCREL
:
2739 case BFD_RELOC_ARC_S21W_PCREL
:
2740 case BFD_RELOC_ARC_S25W_PCREL
:
2744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2745 _("unhandled reloc %s in md_pcrel_from_section"),
2746 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2751 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2752 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2753 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2754 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2755 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2760 /* Given a BFD relocation find the coresponding operand. */
2762 static const struct arc_operand
*
2763 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2767 for (i
= 0; i
< arc_num_operands
; i
++)
2768 if (arc_operands
[i
].default_reloc
== reloc
)
2769 return &arc_operands
[i
];
2773 /* Insert an operand value into an instruction. */
2776 insert_operand (unsigned insn
,
2777 const struct arc_operand
*operand
,
2782 offsetT min
= 0, max
= 0;
2784 if (operand
->bits
!= 32
2785 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2786 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2788 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2790 max
= (1 << (operand
->bits
- 1)) - 1;
2791 min
= -(1 << (operand
->bits
- 1));
2795 max
= (1 << operand
->bits
) - 1;
2799 if (val
< min
|| val
> max
)
2800 as_bad_value_out_of_range (_("operand"),
2801 val
, min
, max
, file
, line
);
2804 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2805 min
, val
, max
, insn
);
2807 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2809 as_bad_where (file
, line
,
2810 _("Unaligned operand. Needs to be 32bit aligned"));
2812 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2814 as_bad_where (file
, line
,
2815 _("Unaligned operand. Needs to be 16bit aligned"));
2817 if (operand
->insert
)
2819 const char *errmsg
= NULL
;
2821 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2823 as_warn_where (file
, line
, "%s", errmsg
);
2827 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2829 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2831 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2834 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2839 /* Apply a fixup to the object code. At this point all symbol values
2840 should be fully resolved, and we attempt to completely resolve the
2841 reloc. If we can not do that, we determine the correct reloc code
2842 and put it back in the fixup. To indicate that a fixup has been
2843 eliminated, set fixP->fx_done. */
2846 md_apply_fix (fixS
*fixP
,
2850 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2851 valueT value
= *valP
;
2853 symbolS
*fx_addsy
, *fx_subsy
;
2855 segT add_symbol_segment
= absolute_section
;
2856 segT sub_symbol_segment
= absolute_section
;
2857 const struct arc_operand
*operand
= NULL
;
2858 extended_bfd_reloc_code_real_type reloc
;
2860 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2861 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2862 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2863 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2866 fx_addsy
= fixP
->fx_addsy
;
2867 fx_subsy
= fixP
->fx_subsy
;
2872 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2876 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2877 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2878 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2880 resolve_symbol_value (fx_subsy
);
2881 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2883 if (sub_symbol_segment
== absolute_section
)
2885 /* The symbol is really a constant. */
2886 fx_offset
-= S_GET_VALUE (fx_subsy
);
2891 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2892 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2893 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2894 segment_name (add_symbol_segment
),
2895 S_GET_NAME (fx_subsy
),
2896 segment_name (sub_symbol_segment
));
2902 && !S_IS_WEAK (fx_addsy
))
2904 if (add_symbol_segment
== seg
2907 value
+= S_GET_VALUE (fx_addsy
);
2908 value
-= md_pcrel_from_section (fixP
, seg
);
2910 fixP
->fx_pcrel
= FALSE
;
2912 else if (add_symbol_segment
== absolute_section
)
2914 value
= fixP
->fx_offset
;
2915 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2917 fixP
->fx_pcrel
= FALSE
;
2922 fixP
->fx_done
= TRUE
;
2927 && ((S_IS_DEFINED (fx_addsy
)
2928 && S_GET_SEGMENT (fx_addsy
) != seg
)
2929 || S_IS_WEAK (fx_addsy
)))
2930 value
+= md_pcrel_from_section (fixP
, seg
);
2932 switch (fixP
->fx_r_type
)
2934 case BFD_RELOC_ARC_32_ME
:
2935 /* This is a pc-relative value in a LIMM. Adjust it to the
2936 address of the instruction not to the address of the
2937 LIMM. Note: it is not anylonger valid this afirmation as
2938 the linker consider ARC_PC32 a fixup to entire 64 bit
2940 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2943 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2945 case BFD_RELOC_ARC_PC32
:
2946 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2949 if ((int) fixP
->fx_r_type
< 0)
2950 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2956 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2957 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2958 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2959 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2963 /* Now check for TLS relocations. */
2964 reloc
= fixP
->fx_r_type
;
2967 case BFD_RELOC_ARC_TLS_DTPOFF
:
2968 case BFD_RELOC_ARC_TLS_LE_32
:
2972 case BFD_RELOC_ARC_TLS_GD_GOT
:
2973 case BFD_RELOC_ARC_TLS_IE_GOT
:
2974 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2977 case BFD_RELOC_ARC_TLS_GD_LD
:
2978 gas_assert (!fixP
->fx_offset
);
2981 = (S_GET_VALUE (fixP
->fx_subsy
)
2982 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2983 fixP
->fx_subsy
= NULL
;
2985 case BFD_RELOC_ARC_TLS_GD_CALL
:
2986 /* These two relocs are there just to allow ld to change the tls
2987 model for this symbol, by patching the code. The offset -
2988 and scale, if any - will be installed by the linker. */
2989 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2992 case BFD_RELOC_ARC_TLS_LE_S9
:
2993 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
2994 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3006 /* Addjust the value if we have a constant. */
3009 /* For hosts with longs bigger than 32-bits make sure that the top
3010 bits of a 32-bit negative value read in by the parser are set,
3011 so that the correct comparisons are made. */
3012 if (value
& 0x80000000)
3013 value
|= (-1UL << 31);
3015 reloc
= fixP
->fx_r_type
;
3023 case BFD_RELOC_ARC_32_PCREL
:
3024 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
3027 case BFD_RELOC_ARC_GOTPC32
:
3028 /* I cannot fix an GOTPC relocation because I need to relax it
3029 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3030 as_bad (_("Unsupported operation on reloc"));
3033 case BFD_RELOC_ARC_TLS_DTPOFF
:
3034 case BFD_RELOC_ARC_TLS_LE_32
:
3035 gas_assert (!fixP
->fx_addsy
);
3036 gas_assert (!fixP
->fx_subsy
);
3039 case BFD_RELOC_ARC_GOTOFF
:
3040 case BFD_RELOC_ARC_32_ME
:
3041 case BFD_RELOC_ARC_PC32
:
3042 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3045 case BFD_RELOC_ARC_PLT32
:
3046 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3049 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3050 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3053 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3054 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
3057 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3058 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3061 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3062 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
3065 case BFD_RELOC_ARC_S25W_PCREL
:
3066 case BFD_RELOC_ARC_S21W_PCREL
:
3067 case BFD_RELOC_ARC_S21H_PCREL
:
3068 case BFD_RELOC_ARC_S25H_PCREL
:
3069 case BFD_RELOC_ARC_S13_PCREL
:
3071 operand
= find_operand_for_reloc (reloc
);
3072 gas_assert (operand
);
3077 if ((int) fixP
->fx_r_type
>= 0)
3078 as_fatal (_("unhandled relocation type %s"),
3079 bfd_get_reloc_code_name (fixP
->fx_r_type
));
3081 /* The rest of these fixups needs to be completely resolved as
3083 if (fixP
->fx_addsy
!= 0
3084 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
3085 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3086 _("non-absolute expression in constant field"));
3088 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
3089 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
3094 if (target_big_endian
)
3096 switch (fixP
->fx_size
)
3099 insn
= bfd_getb32 (fixpos
);
3102 insn
= bfd_getb16 (fixpos
);
3105 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3106 _("unknown fixup size"));
3112 switch (fixP
->fx_size
)
3115 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
3118 insn
= bfd_getl16 (fixpos
);
3121 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3122 _("unknown fixup size"));
3126 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3127 fixP
->fx_file
, fixP
->fx_line
);
3129 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3132 /* Prepare machine-dependent frags for relaxation.
3134 Called just before relaxation starts. Any symbol that is now undefined
3135 will not become defined.
3137 Return the correct fr_subtype in the frag.
3139 Return the initial "guess for fr_var" to caller. The guess for fr_var
3140 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3141 or fr_var contributes to our returned value.
3143 Although it may not be explicit in the frag, pretend
3144 fr_var starts with a value. */
3147 md_estimate_size_before_relax (fragS
*fragP
,
3152 /* If the symbol is not located within the same section AND it's not
3153 an absolute section, use the maximum. OR if the symbol is a
3154 constant AND the insn is by nature not pc-rel, use the maximum.
3155 OR if the symbol is being equated against another symbol, use the
3156 maximum. OR if the symbol is weak use the maximum. */
3157 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3158 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3159 || (symbol_constant_p (fragP
->fr_symbol
)
3160 && !fragP
->tc_frag_data
.pcrel
)
3161 || symbol_equated_p (fragP
->fr_symbol
)
3162 || S_IS_WEAK (fragP
->fr_symbol
))
3164 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3165 ++fragP
->fr_subtype
;
3168 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3169 fragP
->fr_var
= growth
;
3171 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3172 fragP
->fr_file
, fragP
->fr_line
, growth
);
3177 /* Translate internal representation of relocation info to BFD target
3181 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3185 bfd_reloc_code_real_type code
;
3187 reloc
= XNEW (arelent
);
3188 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3189 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3190 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3192 /* Make sure none of our internal relocations make it this far.
3193 They'd better have been fully resolved by this point. */
3194 gas_assert ((int) fixP
->fx_r_type
> 0);
3196 code
= fixP
->fx_r_type
;
3198 /* if we have something like add gp, pcl,
3199 _GLOBAL_OFFSET_TABLE_@gotpc. */
3200 if (code
== BFD_RELOC_ARC_GOTPC32
3202 && fixP
->fx_addsy
== GOT_symbol
)
3203 code
= BFD_RELOC_ARC_GOTPC
;
3205 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3206 if (reloc
->howto
== NULL
)
3208 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3209 _("cannot represent `%s' relocation in object file"),
3210 bfd_get_reloc_code_name (code
));
3214 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3215 as_fatal (_("internal error? cannot generate `%s' relocation"),
3216 bfd_get_reloc_code_name (code
));
3218 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3220 reloc
->addend
= fixP
->fx_offset
;
3225 /* Perform post-processing of machine-dependent frags after relaxation.
3226 Called after relaxation is finished.
3227 In: Address of frag.
3228 fr_type == rs_machine_dependent.
3229 fr_subtype is what the address relaxed to.
3231 Out: Any fixS:s and constants are set up. */
3234 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3235 segT segment ATTRIBUTE_UNUSED
,
3238 const relax_typeS
*table_entry
;
3240 const struct arc_opcode
*opcode
;
3241 struct arc_insn insn
;
3243 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3245 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
3246 dest
= fragP
->fr_literal
+ fix
;
3247 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3249 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3250 "var: %"BFD_VMA_FMT
"d\n",
3251 fragP
->fr_file
, fragP
->fr_line
,
3252 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3254 if (fragP
->fr_subtype
<= 0
3255 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3256 as_fatal (_("no relaxation found for this instruction."));
3258 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3260 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3261 relax_arg
->nflg
, &insn
);
3263 apply_fixups (&insn
, fragP
, fix
);
3265 size
= insn
.short_insn
? (insn
.has_limm
? 6 : 2) : (insn
.has_limm
? 8 : 4);
3266 gas_assert (table_entry
->rlx_length
== size
);
3267 emit_insn0 (&insn
, dest
, TRUE
);
3269 fragP
->fr_fix
+= table_entry
->rlx_length
;
3273 /* We have no need to default values of symbols. We could catch
3274 register names here, but that is handled by inserting them all in
3275 the symbol table to begin with. */
3278 md_undefined_symbol (char *name
)
3280 /* The arc abi demands that a GOT[0] should be referencible as
3281 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3282 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3284 && (*(name
+1) == 'G')
3285 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
3287 && (*(name
+1) == 'D')
3288 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
3292 if (symbol_find (name
))
3293 as_bad ("GOT already in symbol table");
3295 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3296 (valueT
) 0, &zero_address_frag
);
3303 /* Turn a string in input_line_pointer into a floating point constant
3304 of type type, and store the appropriate bytes in *litP. The number
3305 of LITTLENUMS emitted is stored in *sizeP. An error message is
3306 returned, or NULL on OK. */
3309 md_atof (int type
, char *litP
, int *sizeP
)
3311 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3314 /* Called for any expression that can not be recognized. When the
3315 function is called, `input_line_pointer' will point to the start of
3319 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3321 char *p
= input_line_pointer
;
3324 input_line_pointer
++;
3325 expressionP
->X_op
= O_symbol
;
3326 expression (expressionP
);
3330 /* This function is called from the function 'expression', it attempts
3331 to parse special names (in our case register names). It fills in
3332 the expression with the identified register. It returns TRUE if
3333 it is a register and FALSE otherwise. */
3336 arc_parse_name (const char *name
,
3337 struct expressionS
*e
)
3341 if (!assembling_insn
)
3344 if (e
->X_op
== O_symbol
)
3347 sym
= hash_find (arc_reg_hash
, name
);
3350 e
->X_op
= O_register
;
3351 e
->X_add_number
= S_GET_VALUE (sym
);
3355 sym
= hash_find (arc_addrtype_hash
, name
);
3358 e
->X_op
= O_addrtype
;
3359 e
->X_add_number
= S_GET_VALUE (sym
);
3367 Invocation line includes a switch not recognized by the base assembler.
3368 See if it's a processor-specific option.
3370 New options (supported) are:
3372 -mcpu=<cpu name> Assemble for selected processor
3373 -EB/-mbig-endian Big-endian
3374 -EL/-mlittle-endian Little-endian
3375 -mrelax Enable relaxation
3377 The following CPU names are recognized:
3378 arc600, arc700, arcem, archs, nps400. */
3381 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3387 return md_parse_option (OPTION_MCPU
, "arc600");
3390 return md_parse_option (OPTION_MCPU
, "arc700");
3393 return md_parse_option (OPTION_MCPU
, "arcem");
3396 return md_parse_option (OPTION_MCPU
, "archs");
3400 arc_select_cpu (arg
, MACH_SELECTION_FROM_COMMAND_LINE
);
3405 arc_target_format
= "elf32-bigarc";
3406 byte_order
= BIG_ENDIAN
;
3410 arc_target_format
= "elf32-littlearc";
3411 byte_order
= LITTLE_ENDIAN
;
3415 /* This option has an effect only on ARC EM. */
3416 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
3417 selected_cpu
.features
|= ARC_CD
;
3419 as_warn (_("Code density option invalid for selected CPU"));
3423 relaxation_state
= 1;
3427 selected_cpu
.features
|= ARC_NPS400
;
3431 selected_cpu
.features
|= ARC_SPFP
;
3435 selected_cpu
.features
|= ARC_DPFP
;
3439 /* This option has an effect only on ARC EM. */
3440 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
3441 selected_cpu
.features
|= ARC_FPUDA
;
3443 as_warn (_("FPUDA invalid for selected CPU"));
3446 /* Dummy options are accepted but have no effect. */
3447 case OPTION_USER_MODE
:
3448 case OPTION_LD_EXT_MASK
:
3451 case OPTION_BARREL_SHIFT
:
3452 case OPTION_MIN_MAX
:
3457 case OPTION_XMAC_D16
:
3458 case OPTION_XMAC_24
:
3459 case OPTION_DSP_PACKA
:
3462 case OPTION_TELEPHONY
:
3463 case OPTION_XYMEMORY
:
3477 md_show_usage (FILE *stream
)
3479 fprintf (stream
, _("ARC-specific assembler options:\n"));
3481 fprintf (stream
, " -mcpu=<cpu name>\t assemble for CPU <cpu name> "
3482 "(default: %s)\n", TARGET_WITH_CPU
);
3483 fprintf (stream
, " -mcpu=nps400\t\t same as -mcpu=arc700 -mnps400\n");
3484 fprintf (stream
, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3485 fprintf (stream
, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3486 fprintf (stream
, " -mEM\t\t\t same as -mcpu=arcem\n");
3487 fprintf (stream
, " -mHS\t\t\t same as -mcpu=archs\n");
3489 fprintf (stream
, " -mnps400\t\t enable NPS-400 extended instructions\n");
3490 fprintf (stream
, " -mspfp\t\t enable single-precision floating point instructions\n");
3491 fprintf (stream
, " -mdpfp\t\t enable double-precision floating point instructions\n");
3492 fprintf (stream
, " -mfpuda\t\t enable double-precision assist floating "
3493 "point\n\t\t\t instructions for ARC EM\n");
3496 " -mcode-density\t enable code density option for ARC EM\n");
3498 fprintf (stream
, _("\
3499 -EB assemble code for a big-endian cpu\n"));
3500 fprintf (stream
, _("\
3501 -EL assemble code for a little-endian cpu\n"));
3502 fprintf (stream
, _("\
3503 -mrelax enable relaxation\n"));
3505 fprintf (stream
, _("The following ARC-specific assembler options are "
3506 "deprecated and are accepted\nfor compatibility only:\n"));
3508 fprintf (stream
, _(" -mEA\n"
3509 " -mbarrel-shifter\n"
3510 " -mbarrel_shifter\n"
3515 " -mld-extension-reg-mask\n"
3531 " -muser-mode-only\n"
3535 /* Find the proper relocation for the given opcode. */
3537 static extended_bfd_reloc_code_real_type
3538 find_reloc (const char *name
,
3539 const char *opcodename
,
3540 const struct arc_flags
*pflags
,
3542 extended_bfd_reloc_code_real_type reloc
)
3546 bfd_boolean found_flag
, tmp
;
3547 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3549 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3551 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3553 /* Find the entry. */
3554 if (strcmp (name
, r
->name
))
3556 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3563 unsigned * psflg
= (unsigned *)r
->flags
;
3567 for (j
= 0; j
< nflg
; j
++)
3568 if (!strcmp (pflags
[j
].name
,
3569 arc_flag_operands
[*psflg
].name
))
3590 if (reloc
!= r
->oldreloc
)
3597 if (ret
== BFD_RELOC_UNUSED
)
3598 as_bad (_("Unable to find %s relocation for instruction %s"),
3603 /* All the symbol types that are allowed to be used for
3607 may_relax_expr (expressionS tok
)
3609 /* Check if we have unrelaxable relocs. */
3634 /* Checks if flags are in line with relaxable insn. */
3637 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3638 const struct arc_flags
*pflags
,
3641 unsigned flag_class
,
3646 const struct arc_flag_operand
*flag_opand
;
3647 int i
, counttrue
= 0;
3649 /* Iterate through flags classes. */
3650 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3652 /* Iterate through flags in flag class. */
3653 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3656 flag_opand
= &arc_flag_operands
[flag
];
3657 /* Iterate through flags in ins to compare. */
3658 for (i
= 0; i
< nflgs
; ++i
)
3660 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3671 /* If counttrue == nflgs, then all flags have been found. */
3672 return (counttrue
== nflgs
? TRUE
: FALSE
);
3675 /* Checks if operands are in line with relaxable insn. */
3678 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3679 const expressionS
*tok
,
3682 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3685 while (*operand
!= EMPTY
)
3687 const expressionS
*epr
= &tok
[i
];
3689 if (i
!= 0 && i
>= ntok
)
3695 if (!(epr
->X_op
== O_multiply
3696 || epr
->X_op
== O_divide
3697 || epr
->X_op
== O_modulus
3698 || epr
->X_op
== O_add
3699 || epr
->X_op
== O_subtract
3700 || epr
->X_op
== O_symbol
))
3706 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3710 if (epr
->X_op
!= O_register
)
3715 if (epr
->X_op
!= O_register
)
3718 switch (epr
->X_add_number
)
3720 case 0: case 1: case 2: case 3:
3721 case 12: case 13: case 14: case 15:
3728 case REGISTER_NO_GP
:
3729 if ((epr
->X_op
!= O_register
)
3730 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3735 if (epr
->X_op
!= O_bracket
)
3740 /* Don't understand, bail out. */
3746 operand
= &ins
->operands
[i
];
3749 return (i
== ntok
? TRUE
: FALSE
);
3752 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3755 relax_insn_p (const struct arc_opcode
*opcode
,
3756 const expressionS
*tok
,
3758 const struct arc_flags
*pflags
,
3762 bfd_boolean rv
= FALSE
;
3764 /* Check the relaxation table. */
3765 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3767 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3769 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3770 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3771 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3772 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3775 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3776 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3777 sizeof (expressionS
) * ntok
);
3778 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3779 sizeof (struct arc_flags
) * nflg
);
3780 frag_now
->tc_frag_data
.nflg
= nflg
;
3781 frag_now
->tc_frag_data
.ntok
= ntok
;
3789 /* Turn an opcode description and a set of arguments into
3790 an instruction and a fixup. */
3793 assemble_insn (const struct arc_opcode
*opcode
,
3794 const expressionS
*tok
,
3796 const struct arc_flags
*pflags
,
3798 struct arc_insn
*insn
)
3800 const expressionS
*reloc_exp
= NULL
;
3802 const unsigned char *argidx
;
3805 unsigned char pcrel
= 0;
3806 bfd_boolean needGOTSymbol
;
3807 bfd_boolean has_delay_slot
= FALSE
;
3808 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3810 memset (insn
, 0, sizeof (*insn
));
3811 image
= opcode
->opcode
;
3813 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3814 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3817 /* Handle operands. */
3818 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3820 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3821 const expressionS
*t
= (const expressionS
*) 0;
3823 if (ARC_OPERAND_IS_FAKE (operand
))
3826 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3828 /* Duplicate operand, already inserted. */
3840 /* Regardless if we have a reloc or not mark the instruction
3841 limm if it is the case. */
3842 if (operand
->flags
& ARC_OPERAND_LIMM
)
3843 insn
->has_limm
= TRUE
;
3848 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3853 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3855 if (operand
->flags
& ARC_OPERAND_LIMM
)
3856 insn
->limm
= t
->X_add_number
;
3862 /* Ignore brackets, colons, and address types. */
3866 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3870 /* Maybe register range. */
3871 if ((t
->X_add_number
== 0)
3872 && contains_register (t
->X_add_symbol
)
3873 && contains_register (t
->X_op_symbol
))
3877 regs
= get_register (t
->X_add_symbol
);
3879 regs
|= get_register (t
->X_op_symbol
);
3880 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3886 /* This operand needs a relocation. */
3887 needGOTSymbol
= FALSE
;
3892 if (opcode
->insn_class
== JUMP
)
3893 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3894 _("Unable to use @plt relocatio for insn %s"),
3896 needGOTSymbol
= TRUE
;
3897 reloc
= find_reloc ("plt", opcode
->name
,
3899 operand
->default_reloc
);
3904 needGOTSymbol
= TRUE
;
3905 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3908 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3909 if (ARC_SHORT (opcode
->mask
) || opcode
->insn_class
== JUMP
)
3910 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3911 _("Unable to use @pcl relocation for insn %s"),
3915 reloc
= find_reloc ("sda", opcode
->name
,
3917 operand
->default_reloc
);
3921 needGOTSymbol
= TRUE
;
3926 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3929 case O_tpoff9
: /*FIXME! Check for the conditionality of
3931 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3933 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3937 /* Just consider the default relocation. */
3938 reloc
= operand
->default_reloc
;
3942 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3943 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3950 /* sanity checks. */
3951 reloc_howto_type
*reloc_howto
3952 = bfd_reloc_type_lookup (stdoutput
,
3953 (bfd_reloc_code_real_type
) reloc
);
3954 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
3955 if (reloc_howto
->rightshift
)
3956 reloc_bitsize
-= reloc_howto
->rightshift
;
3957 if (reloc_bitsize
!= operand
->bits
)
3959 as_bad (_("invalid relocation %s for field"),
3960 bfd_get_reloc_code_name (reloc
));
3965 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3966 as_fatal (_("too many fixups"));
3968 struct arc_fixup
*fixup
;
3969 fixup
= &insn
->fixups
[insn
->nfixups
++];
3971 fixup
->reloc
= reloc
;
3972 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
3973 fixup
->pcrel
= pcrel
;
3974 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
3981 for (i
= 0; i
< nflg
; i
++)
3983 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
3985 /* Check if the instruction has a delay slot. */
3986 if (!strcmp (flg_operand
->name
, "d"))
3987 has_delay_slot
= TRUE
;
3989 /* There is an exceptional case when we cannot insert a flag
3990 just as it is. The .T flag must be handled in relation with
3991 the relative address. */
3992 if (!strcmp (flg_operand
->name
, "t")
3993 || !strcmp (flg_operand
->name
, "nt"))
3995 unsigned bitYoperand
= 0;
3996 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3997 if (!strcmp (flg_operand
->name
, "t"))
3998 if (!strcmp (opcode
->name
, "bbit0")
3999 || !strcmp (opcode
->name
, "bbit1"))
4000 bitYoperand
= arc_NToperand
;
4002 bitYoperand
= arc_Toperand
;
4004 if (!strcmp (opcode
->name
, "bbit0")
4005 || !strcmp (opcode
->name
, "bbit1"))
4006 bitYoperand
= arc_Toperand
;
4008 bitYoperand
= arc_NToperand
;
4010 gas_assert (reloc_exp
!= NULL
);
4011 if (reloc_exp
->X_op
== O_constant
)
4013 /* Check if we have a constant and solved it
4015 offsetT val
= reloc_exp
->X_add_number
;
4016 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
4021 struct arc_fixup
*fixup
;
4023 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4024 as_fatal (_("too many fixups"));
4026 fixup
= &insn
->fixups
[insn
->nfixups
++];
4027 fixup
->exp
= *reloc_exp
;
4028 fixup
->reloc
= -bitYoperand
;
4029 fixup
->pcrel
= pcrel
;
4030 fixup
->islong
= FALSE
;
4034 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
4035 << flg_operand
->shift
;
4038 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
4040 /* Short instruction? */
4041 insn
->short_insn
= ARC_SHORT (opcode
->mask
) ? TRUE
: FALSE
;
4045 /* Update last insn status. */
4046 arc_last_insns
[1] = arc_last_insns
[0];
4047 arc_last_insns
[0].opcode
= opcode
;
4048 arc_last_insns
[0].has_limm
= insn
->has_limm
;
4049 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
4051 /* Check if the current instruction is legally used. */
4052 if (arc_last_insns
[1].has_delay_slot
4053 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4054 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4055 _("A jump/branch instruction in delay slot."));
4059 arc_handle_align (fragS
* fragP
)
4061 if ((fragP
)->fr_type
== rs_align_code
)
4063 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
4064 valueT count
= ((fragP
)->fr_next
->fr_address
4065 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
4067 (fragP
)->fr_var
= 2;
4069 if (count
& 1)/* Padding in the gap till the next 2-byte
4070 boundary with 0s. */
4075 /* Writing nop_s. */
4076 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
4080 /* Here we decide which fixups can be adjusted to make them relative
4081 to the beginning of the section instead of the symbol. Basically
4082 we need to make sure that the dynamic relocations are done
4083 correctly, so in some cases we force the original symbol to be
4087 tc_arc_fix_adjustable (fixS
*fixP
)
4090 /* Prevent all adjustments to global symbols. */
4091 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
4093 if (S_IS_WEAK (fixP
->fx_addsy
))
4096 /* Adjust_reloc_syms doesn't know about the GOT. */
4097 switch (fixP
->fx_r_type
)
4099 case BFD_RELOC_ARC_GOTPC32
:
4100 case BFD_RELOC_ARC_PLT32
:
4101 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
4102 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
4103 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
4104 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
4114 /* Compute the reloc type of an expression EXP. */
4117 arc_check_reloc (expressionS
*exp
,
4118 bfd_reloc_code_real_type
*r_type_p
)
4120 if (*r_type_p
== BFD_RELOC_32
4121 && exp
->X_op
== O_subtract
4122 && exp
->X_op_symbol
!= NULL
4123 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
4124 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4128 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4131 arc_cons_fix_new (fragS
*frag
,
4135 bfd_reloc_code_real_type r_type
)
4137 r_type
= BFD_RELOC_UNUSED
;
4142 r_type
= BFD_RELOC_8
;
4146 r_type
= BFD_RELOC_16
;
4150 r_type
= BFD_RELOC_24
;
4154 r_type
= BFD_RELOC_32
;
4155 arc_check_reloc (exp
, &r_type
);
4159 r_type
= BFD_RELOC_64
;
4163 as_bad (_("unsupported BFD relocation size %u"), size
);
4164 r_type
= BFD_RELOC_UNUSED
;
4167 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4170 /* The actual routine that checks the ZOL conditions. */
4173 check_zol (symbolS
*s
)
4175 switch (selected_cpu
.mach
)
4177 case bfd_mach_arc_arcv2
:
4178 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
4181 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4182 || arc_last_insns
[1].has_delay_slot
)
4183 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4187 case bfd_mach_arc_arc600
:
4189 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4190 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4193 if (arc_last_insns
[0].has_limm
4194 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4195 as_bad (_("A jump instruction with long immediate detected at the \
4196 end of the ZOL label @%s"), S_GET_NAME (s
));
4199 case bfd_mach_arc_arc700
:
4200 if (arc_last_insns
[0].has_delay_slot
)
4201 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4210 /* If ZOL end check the last two instruction for illegals. */
4212 arc_frob_label (symbolS
* sym
)
4214 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4217 dwarf2_emit_label (sym
);
4220 /* Used because generic relaxation assumes a pc-rel value whilst we
4221 also relax instructions that use an absolute value resolved out of
4222 relative values (if that makes any sense). An example: 'add r1,
4223 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4224 but if they're in the same section we can subtract the section
4225 offset relocation which ends up in a resolved value. So if @.L2 is
4226 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4227 .text + 0x40 = 0x10. */
4229 arc_pcrel_adjust (fragS
*fragP
)
4231 if (!fragP
->tc_frag_data
.pcrel
)
4232 return fragP
->fr_address
+ fragP
->fr_fix
;
4237 /* Initialize the DWARF-2 unwind information for this procedure. */
4240 tc_arc_frame_initial_instructions (void)
4242 /* Stack pointer is register 28. */
4243 cfi_add_CFA_def_cfa (28, 0);
4247 tc_arc_regname_to_dw2regnum (char *regname
)
4251 sym
= hash_find (arc_reg_hash
, regname
);
4253 return S_GET_VALUE (sym
);
4258 /* Adjust the symbol table. Delete found AUX register symbols. */
4261 arc_adjust_symtab (void)
4265 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4267 /* I've created a symbol during parsing process. Now, remove
4268 the symbol as it is found to be an AUX register. */
4269 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4270 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4273 /* Now do generic ELF adjustments. */
4274 elf_adjust_symtab ();
4278 tokenize_extinsn (extInstruction_t
*einsn
)
4282 unsigned char major_opcode
;
4283 unsigned char sub_opcode
;
4284 unsigned char syntax_class
= 0;
4285 unsigned char syntax_class_modifiers
= 0;
4286 unsigned char suffix_class
= 0;
4291 /* 1st: get instruction name. */
4292 p
= input_line_pointer
;
4293 c
= get_symbol_name (&p
);
4295 insn_name
= xstrdup (p
);
4296 restore_line_pointer (c
);
4298 /* 2nd: get major opcode. */
4299 if (*input_line_pointer
!= ',')
4301 as_bad (_("expected comma after instruction name"));
4302 ignore_rest_of_line ();
4305 input_line_pointer
++;
4306 major_opcode
= get_absolute_expression ();
4308 /* 3rd: get sub-opcode. */
4311 if (*input_line_pointer
!= ',')
4313 as_bad (_("expected comma after major opcode"));
4314 ignore_rest_of_line ();
4317 input_line_pointer
++;
4318 sub_opcode
= get_absolute_expression ();
4320 /* 4th: get suffix class. */
4323 if (*input_line_pointer
!= ',')
4325 as_bad ("expected comma after sub opcode");
4326 ignore_rest_of_line ();
4329 input_line_pointer
++;
4335 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4337 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4338 suffixclass
[i
].len
))
4340 suffix_class
|= suffixclass
[i
].attr_class
;
4341 input_line_pointer
+= suffixclass
[i
].len
;
4346 if (i
== ARRAY_SIZE (suffixclass
))
4348 as_bad ("invalid suffix class");
4349 ignore_rest_of_line ();
4355 if (*input_line_pointer
== '|')
4356 input_line_pointer
++;
4361 /* 5th: get syntax class and syntax class modifiers. */
4362 if (*input_line_pointer
!= ',')
4364 as_bad ("expected comma after suffix class");
4365 ignore_rest_of_line ();
4368 input_line_pointer
++;
4374 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4376 if (!strncmp (syntaxclassmod
[i
].name
,
4378 syntaxclassmod
[i
].len
))
4380 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4381 input_line_pointer
+= syntaxclassmod
[i
].len
;
4386 if (i
== ARRAY_SIZE (syntaxclassmod
))
4388 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4390 if (!strncmp (syntaxclass
[i
].name
,
4392 syntaxclass
[i
].len
))
4394 syntax_class
|= syntaxclass
[i
].attr_class
;
4395 input_line_pointer
+= syntaxclass
[i
].len
;
4400 if (i
== ARRAY_SIZE (syntaxclass
))
4402 as_bad ("missing syntax class");
4403 ignore_rest_of_line ();
4410 if (*input_line_pointer
== '|')
4411 input_line_pointer
++;
4416 demand_empty_rest_of_line ();
4418 einsn
->name
= insn_name
;
4419 einsn
->major
= major_opcode
;
4420 einsn
->minor
= sub_opcode
;
4421 einsn
->syntax
= syntax_class
;
4422 einsn
->modsyn
= syntax_class_modifiers
;
4423 einsn
->suffix
= suffix_class
;
4424 einsn
->flags
= syntax_class
4425 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4428 /* Generate an extension section. */
4431 arc_set_ext_seg (void)
4433 if (!arcext_section
)
4435 arcext_section
= subseg_new (".arcextmap", 0);
4436 bfd_set_section_flags (stdoutput
, arcext_section
,
4437 SEC_READONLY
| SEC_HAS_CONTENTS
);
4440 subseg_set (arcext_section
, 0);
4444 /* Create an extension instruction description in the arc extension
4445 section of the output file.
4446 The structure for an instruction is like this:
4447 [0]: Length of the record.
4448 [1]: Type of the record.
4452 [4]: Syntax (flags).
4453 [5]+ Name instruction.
4455 The sequence is terminated by an empty entry. */
4458 create_extinst_section (extInstruction_t
*einsn
)
4461 segT old_sec
= now_seg
;
4462 int old_subsec
= now_subseg
;
4464 int name_len
= strlen (einsn
->name
);
4469 *p
= 5 + name_len
+ 1;
4471 *p
= EXT_INSTRUCTION
;
4478 p
= frag_more (name_len
+ 1);
4479 strcpy (p
, einsn
->name
);
4481 subseg_set (old_sec
, old_subsec
);
4484 /* Handler .extinstruction pseudo-op. */
4487 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4489 extInstruction_t einsn
;
4490 struct arc_opcode
*arc_ext_opcodes
;
4491 const char *errmsg
= NULL
;
4492 unsigned char moplow
, mophigh
;
4494 memset (&einsn
, 0, sizeof (einsn
));
4495 tokenize_extinsn (&einsn
);
4497 /* Check if the name is already used. */
4498 if (arc_find_opcode (einsn
.name
))
4499 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4501 /* Check the opcode ranges. */
4503 mophigh
= (selected_cpu
.flags
& (ARC_OPCODE_ARCv2EM
4504 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4506 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4507 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4509 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4510 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4511 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4513 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4515 case ARC_SYNTAX_3OP
:
4516 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4517 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4519 case ARC_SYNTAX_2OP
:
4520 case ARC_SYNTAX_1OP
:
4521 case ARC_SYNTAX_NOP
:
4522 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4523 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4529 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, selected_cpu
.flags
, &errmsg
);
4530 if (arc_ext_opcodes
== NULL
)
4533 as_fatal ("%s", errmsg
);
4535 as_fatal (_("Couldn't generate extension instruction opcodes"));
4538 as_warn ("%s", errmsg
);
4540 /* Insert the extension instruction. */
4541 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4543 create_extinst_section (&einsn
);
4547 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4553 int number
, imode
= 0;
4554 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4555 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4556 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4558 /* 1st: get register name. */
4560 p
= input_line_pointer
;
4561 c
= get_symbol_name (&p
);
4564 restore_line_pointer (c
);
4566 /* 2nd: get register number. */
4569 if (*input_line_pointer
!= ',')
4571 as_bad (_("expected comma after register name"));
4572 ignore_rest_of_line ();
4576 input_line_pointer
++;
4577 number
= get_absolute_expression ();
4581 as_bad (_("negative operand number %d"), number
);
4582 ignore_rest_of_line ();
4589 /* 3rd: get register mode. */
4592 if (*input_line_pointer
!= ',')
4594 as_bad (_("expected comma after register number"));
4595 ignore_rest_of_line ();
4600 input_line_pointer
++;
4601 mode
= input_line_pointer
;
4603 if (!strncmp (mode
, "r|w", 3))
4606 input_line_pointer
+= 3;
4608 else if (!strncmp (mode
, "r", 1))
4610 imode
= ARC_REGISTER_READONLY
;
4611 input_line_pointer
+= 1;
4613 else if (strncmp (mode
, "w", 1))
4615 as_bad (_("invalid mode"));
4616 ignore_rest_of_line ();
4622 imode
= ARC_REGISTER_WRITEONLY
;
4623 input_line_pointer
+= 1;
4629 /* 4th: get core register shortcut. */
4631 if (*input_line_pointer
!= ',')
4633 as_bad (_("expected comma after register mode"));
4634 ignore_rest_of_line ();
4639 input_line_pointer
++;
4641 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4643 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4644 input_line_pointer
+= 15;
4646 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4648 as_bad (_("shortcut designator invalid"));
4649 ignore_rest_of_line ();
4655 input_line_pointer
+= 12;
4658 demand_empty_rest_of_line ();
4661 ereg
->number
= number
;
4662 ereg
->imode
= imode
;
4665 /* Create an extension register/condition description in the arc
4666 extension section of the output file.
4668 The structure for an instruction is like this:
4669 [0]: Length of the record.
4670 [1]: Type of the record.
4672 For core regs and condition codes:
4676 For auxilirary registers:
4680 The sequence is terminated by an empty entry. */
4683 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4685 segT old_sec
= now_seg
;
4686 int old_subsec
= now_subseg
;
4688 int name_len
= strlen (ereg
->name
);
4695 case EXT_CORE_REGISTER
:
4697 *p
= 3 + name_len
+ 1;
4703 case EXT_AUX_REGISTER
:
4705 *p
= 6 + name_len
+ 1;
4707 *p
= EXT_AUX_REGISTER
;
4709 *p
= (ereg
->number
>> 24) & 0xff;
4711 *p
= (ereg
->number
>> 16) & 0xff;
4713 *p
= (ereg
->number
>> 8) & 0xff;
4715 *p
= (ereg
->number
) & 0xff;
4721 p
= frag_more (name_len
+ 1);
4722 strcpy (p
, ereg
->name
);
4724 subseg_set (old_sec
, old_subsec
);
4727 /* Handler .extCoreRegister pseudo-op. */
4730 arc_extcorereg (int opertype
)
4733 struct arc_aux_reg
*auxr
;
4735 struct arc_flag_operand
*ccode
;
4737 memset (&ereg
, 0, sizeof (ereg
));
4738 tokenize_extregister (&ereg
, opertype
);
4742 case EXT_CORE_REGISTER
:
4743 /* Core register. */
4744 if (ereg
.number
> 60)
4745 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4747 declare_register (ereg
.name
, ereg
.number
);
4749 case EXT_AUX_REGISTER
:
4750 /* Auxiliary register. */
4751 auxr
= XNEW (struct arc_aux_reg
);
4752 auxr
->name
= ereg
.name
;
4753 auxr
->cpu
= selected_cpu
.flags
;
4754 auxr
->subclass
= NONE
;
4755 auxr
->address
= ereg
.number
;
4756 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4758 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4759 auxr
->name
, retval
);
4762 /* Condition code. */
4763 if (ereg
.number
> 31)
4764 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4766 ext_condcode
.size
++;
4767 ext_condcode
.arc_ext_condcode
=
4768 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4769 ext_condcode
.size
+ 1);
4770 if (ext_condcode
.arc_ext_condcode
== NULL
)
4771 as_fatal (_("Virtual memory exhausted"));
4773 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4774 ccode
->name
= ereg
.name
;
4775 ccode
->code
= ereg
.number
;
4778 ccode
->favail
= 0; /* not used. */
4780 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4783 as_bad (_("Unknown extension"));
4786 create_extcore_section (&ereg
, opertype
);
4790 eval: (c-set-style "gnu")