1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
49 (SUB_OPCODE (x) == 0x28))
51 /* Equal to MAX_PRECISION in atof-ieee.c. */
52 #define MAX_LITTLENUMS 6
54 /* Enum used to enumerate the relaxable ins operands. */
59 REGISTER_S
, /* Register for short instruction(s). */
60 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
61 REGISTER_DUP
, /* Duplication of previous operand of type register. */
95 #define regno(x) ((x) & 0x3F)
96 #define is_ir_num(x) (((x) & ~0x3F) == 0)
97 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
98 #define is_spfp_p(op) (((sc) == SPX))
99 #define is_dpfp_p(op) (((sc) == DPX))
100 #define is_fpuda_p(op) (((sc) == DPA))
101 #define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
102 #define is_kernel_insn_p(op) (((op)->class == KERNEL))
104 /* Generic assembler global variables which must be defined by all
107 /* Characters which always start a comment. */
108 const char comment_chars
[] = "#;";
110 /* Characters which start a comment at the beginning of a line. */
111 const char line_comment_chars
[] = "#";
113 /* Characters which may be used to separate multiple commands on a
115 const char line_separator_chars
[] = "`";
117 /* Characters which are used to indicate an exponent in a floating
119 const char EXP_CHARS
[] = "eE";
121 /* Chars that mean this number is a floating point constant
122 As in 0f12.456 or 0d1.2345e12. */
123 const char FLT_CHARS
[] = "rRsSfFdD";
126 extern int target_big_endian
;
127 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
128 static int byte_order
= DEFAULT_BYTE_ORDER
;
130 /* Arc extension section. */
131 static segT arcext_section
;
133 /* By default relaxation is disabled. */
134 static int relaxation_state
= 0;
136 extern int arc_get_mach (char *);
138 /* Forward declarations. */
139 static void arc_lcomm (int);
140 static void arc_option (int);
141 static void arc_extra_reloc (int);
142 static void arc_extinsn (int);
143 static void arc_extcorereg (int);
145 const pseudo_typeS md_pseudo_table
[] =
147 /* Make sure that .word is 32 bits. */
150 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
151 { "lcomm", arc_lcomm
, 0 },
152 { "lcommon", arc_lcomm
, 0 },
153 { "cpu", arc_option
, 0 },
155 { "extinstruction", arc_extinsn
, 0 },
156 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
157 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
158 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
160 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
161 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
166 const char *md_shortopts
= "";
170 OPTION_EB
= OPTION_MD_BASE
,
183 /* The following options are deprecated and provided here only for
184 compatibility reasons. */
210 struct option md_longopts
[] =
212 { "EB", no_argument
, NULL
, OPTION_EB
},
213 { "EL", no_argument
, NULL
, OPTION_EL
},
214 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
215 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
216 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
217 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
218 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
219 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
220 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
221 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
222 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
223 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
225 /* The following options are deprecated and provided here only for
226 compatibility reasons. */
227 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
228 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
229 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
230 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
231 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
232 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
233 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
234 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
235 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
236 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
237 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
238 { "mea", no_argument
, NULL
, OPTION_EA
},
239 { "mEA", no_argument
, NULL
, OPTION_EA
},
240 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
241 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
242 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
243 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
244 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
245 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
246 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
247 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
248 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
249 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
250 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
251 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
252 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
253 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
254 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
255 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
256 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
257 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
258 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
259 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
260 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
261 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
262 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
263 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
264 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
265 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
267 { NULL
, no_argument
, NULL
, 0 }
270 size_t md_longopts_size
= sizeof (md_longopts
);
272 /* Local data and data types. */
274 /* Used since new relocation types are introduced in this
275 file (DUMMY_RELOC_LITUSE_*). */
276 typedef int extended_bfd_reloc_code_real_type
;
282 extended_bfd_reloc_code_real_type reloc
;
284 /* index into arc_operands. */
285 unsigned int opindex
;
287 /* PC-relative, used by internals fixups. */
290 /* TRUE if this fixup is for LIMM operand. */
298 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
300 bfd_boolean short_insn
; /* Boolean value: TRUE if current insn is
302 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
304 bfd_boolean relax
; /* Boolean value: TRUE if needs
308 /* Structure to hold any last two instructions. */
309 static struct arc_last_insn
311 /* Saved instruction opcode. */
312 const struct arc_opcode
*opcode
;
314 /* Boolean value: TRUE if current insn is short. */
315 bfd_boolean has_limm
;
317 /* Boolean value: TRUE if current insn has delay slot. */
318 bfd_boolean has_delay_slot
;
321 /* Extension instruction suffix classes. */
329 static const attributes_t suffixclass
[] =
331 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
332 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
333 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
336 /* Extension instruction syntax classes. */
337 static const attributes_t syntaxclass
[] =
339 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
340 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
}
343 /* Extension instruction syntax classes modifiers. */
344 static const attributes_t syntaxclassmod
[] =
346 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
347 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
350 /* Extension register type. */
358 /* A structure to hold the additional conditional codes. */
361 struct arc_flag_operand
*arc_ext_condcode
;
363 } ext_condcode
= { NULL
, 0 };
365 /* Structure to hold an entry in ARC_OPCODE_HASH. */
366 struct arc_opcode_hash_entry
368 /* The number of pointers in the OPCODE list. */
371 /* Points to a list of opcode pointers. */
372 const struct arc_opcode
**opcode
;
375 /* Structure used for iterating through an arc_opcode_hash_entry. */
376 struct arc_opcode_hash_entry_iterator
378 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
381 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
382 returned by this iterator. */
383 const struct arc_opcode
*opcode
;
386 /* Forward declaration. */
387 static void assemble_insn
388 (const struct arc_opcode
*, const expressionS
*, int,
389 const struct arc_flags
*, int, struct arc_insn
*);
391 /* The cpu for which we are generating code. */
392 static unsigned arc_target
;
393 static const char *arc_target_name
;
394 static unsigned arc_features
;
396 /* The default architecture. */
397 static int arc_mach_type
;
399 /* Non-zero if the cpu type has been explicitly specified. */
400 static int mach_type_specified_p
= 0;
402 /* The hash table of instruction opcodes. */
403 static struct hash_control
*arc_opcode_hash
;
405 /* The hash table of register symbols. */
406 static struct hash_control
*arc_reg_hash
;
408 /* The hash table of aux register symbols. */
409 static struct hash_control
*arc_aux_hash
;
411 /* A table of CPU names and opcode sets. */
412 static const struct cpu_type
422 { "arc600", ARC_OPCODE_ARC600
, bfd_mach_arc_arc600
,
423 E_ARC_MACH_ARC600
, 0x00},
424 { "arc700", ARC_OPCODE_ARC700
, bfd_mach_arc_arc700
,
425 E_ARC_MACH_ARC700
, 0x00},
426 { "nps400", ARC_OPCODE_ARC700
| ARC_OPCODE_NPS400
, bfd_mach_arc_nps400
,
427 E_ARC_MACH_NPS400
, 0x00},
428 { "arcem", ARC_OPCODE_ARCv2EM
, bfd_mach_arc_arcv2
,
429 EF_ARC_CPU_ARCV2EM
, ARC_CD
},
430 { "archs", ARC_OPCODE_ARCv2HS
, bfd_mach_arc_arcv2
,
431 EF_ARC_CPU_ARCV2HS
, ARC_CD
},
435 /* Used by the arc_reloc_op table. Order is important. */
436 #define O_gotoff O_md1 /* @gotoff relocation. */
437 #define O_gotpc O_md2 /* @gotpc relocation. */
438 #define O_plt O_md3 /* @plt relocation. */
439 #define O_sda O_md4 /* @sda relocation. */
440 #define O_pcl O_md5 /* @pcl relocation. */
441 #define O_tlsgd O_md6 /* @tlsgd relocation. */
442 #define O_tlsie O_md7 /* @tlsie relocation. */
443 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
444 #define O_tpoff O_md9 /* @tpoff relocation. */
445 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
446 #define O_dtpoff O_md11 /* @dtpoff relocation. */
447 #define O_last O_dtpoff
449 /* Used to define a bracket as operand in tokens. */
450 #define O_bracket O_md32
452 /* Dummy relocation, to be sorted out. */
453 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
455 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
457 /* A table to map the spelling of a relocation operand into an appropriate
458 bfd_reloc_code_real_type type. The table is assumed to be ordered such
459 that op-O_literal indexes into it. */
460 #define ARC_RELOC_TABLE(op) \
461 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
463 : (int) (op) - (int) O_gotoff) ])
465 #define DEF(NAME, RELOC, REQ) \
466 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
468 static const struct arc_reloc_op_tag
470 /* String to lookup. */
472 /* Size of the string. */
474 /* Which operator to use. */
476 extended_bfd_reloc_code_real_type reloc
;
477 /* Allows complex relocation expression like identifier@reloc +
479 unsigned int complex_expr
: 1;
483 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
484 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
485 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
486 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
487 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
488 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
489 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
490 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
491 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
492 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
493 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 0),
496 static const int arc_num_reloc_op
497 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
499 /* Structure for relaxable instruction that have to be swapped with a
500 smaller alternative instruction. */
501 struct arc_relaxable_ins
503 /* Mnemonic that should be checked. */
504 const char *mnemonic_r
;
506 /* Operands that should be checked.
507 Indexes of operands from operand array. */
508 enum rlx_operand_type operands
[6];
510 /* Flags that should be checked. */
511 unsigned flag_classes
[5];
513 /* Mnemonic (smaller) alternative to be used later for relaxation. */
514 const char *mnemonic_alt
;
516 /* Index of operand that generic relaxation has to check. */
519 /* Base subtype index used. */
520 enum arc_rlx_types subtype
;
523 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
524 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
525 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
529 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
530 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
531 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
536 /* ARC relaxation table. */
537 const relax_typeS md_relax_table
[] =
544 RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL
),
545 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
549 RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B
),
550 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE
),
555 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6
),
556 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM
),
557 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
559 /* LD_S a, [b, u7] ->
560 LD<zz><.x><.aa><.di> a, [b, s9] ->
561 LD<zz><.x><.aa><.di> a, [b, limm] */
562 RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9
),
563 RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM
),
564 RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE
),
569 RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12
),
570 RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM
),
571 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
575 SUB<.f> a, b, limm. */
576 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6
),
577 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM
),
578 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
580 /* MPY<.f> a, b, u6 ->
581 MPY<.f> a, b, limm. */
582 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM
),
583 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
585 /* MOV<.f><.cc> b, u6 ->
586 MOV<.f><.cc> b, limm. */
587 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM
),
588 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
590 /* ADD<.f><.cc> b, b, u6 ->
591 ADD<.f><.cc> b, b, limm. */
592 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM
),
593 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE
),
596 /* Order of this table's entries matters! */
597 const struct arc_relaxable_ins arc_relaxable_insns
[] =
599 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
600 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
601 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
602 2, ARC_RLX_ADD_RRU6
},
603 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
605 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
607 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
608 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
609 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
610 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
611 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
612 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
613 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
614 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
616 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
618 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
622 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
624 /* Flags to set in the elf header. */
625 static flagword arc_eflag
= 0x00;
627 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
628 symbolS
* GOT_symbol
= 0;
630 /* Set to TRUE when we assemble instructions. */
631 static bfd_boolean assembling_insn
= FALSE
;
633 /* Functions implementation. */
635 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
636 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
637 are no matching entries in ARC_OPCODE_HASH. */
639 static const struct arc_opcode_hash_entry
*
640 arc_find_opcode (const char *name
)
642 const struct arc_opcode_hash_entry
*entry
;
644 entry
= hash_find (arc_opcode_hash
, name
);
648 /* Initialise the iterator ITER. */
651 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
657 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
658 calls to this function. Return NULL when all ARC_OPCODE entries have
661 static const struct arc_opcode
*
662 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
663 struct arc_opcode_hash_entry_iterator
*iter
)
665 if (iter
->opcode
== NULL
&& iter
->index
== 0)
667 gas_assert (entry
->count
> 0);
668 iter
->opcode
= entry
->opcode
[iter
->index
];
670 else if (iter
->opcode
!= NULL
)
672 const char *old_name
= iter
->opcode
->name
;
675 if (iter
->opcode
->name
676 && (strcmp (old_name
, iter
->opcode
->name
) != 0))
679 if (iter
->index
== entry
->count
)
682 iter
->opcode
= entry
->opcode
[iter
->index
];
689 /* Insert an opcode into opcode hash structure. */
692 arc_insert_opcode (const struct arc_opcode
*opcode
)
694 const char *name
, *retval
;
695 struct arc_opcode_hash_entry
*entry
;
698 entry
= hash_find (arc_opcode_hash
, name
);
701 entry
= xmalloc (sizeof (*entry
));
703 entry
->opcode
= NULL
;
705 retval
= hash_insert (arc_opcode_hash
, name
, (void *) entry
);
707 as_fatal (_("internal error: can't hash opcode '%s': %s"),
711 entry
->opcode
= xrealloc (entry
->opcode
,
712 sizeof (const struct arc_opcode
*)
713 * (entry
->count
+ 1));
715 if (entry
->opcode
== NULL
)
716 as_fatal (_("Virtual memory exhausted"));
718 entry
->opcode
[entry
->count
] = opcode
;
723 /* Like md_number_to_chars but used for limms. The 4-byte limm value,
724 is encoded as 'middle-endian' for a little-endian target. FIXME!
725 this function is used for regular 4 byte instructions as well. */
728 md_number_to_chars_midend (char *buf
, valueT val
, int n
)
732 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
733 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
737 md_number_to_chars (buf
, val
, n
);
741 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
742 the relevant static global variables. */
745 arc_select_cpu (const char *arg
)
750 for (i
= 0; cpu_types
[i
].name
; ++i
)
752 if (!strcasecmp (cpu_types
[i
].name
, arg
))
754 arc_target
= cpu_types
[i
].flags
;
755 arc_target_name
= cpu_types
[i
].name
;
756 arc_features
= cpu_types
[i
].features
;
757 arc_mach_type
= cpu_types
[i
].mach
;
758 cpu_flags
= cpu_types
[i
].eflags
;
763 if (!cpu_types
[i
].name
)
764 as_fatal (_("unknown architecture: %s\n"), arg
);
765 gas_assert (cpu_flags
!= 0);
766 arc_eflag
= (arc_eflag
& ~EF_ARC_MACH_MSK
) | cpu_flags
;
769 /* Here ends all the ARCompact extension instruction assembling
773 arc_extra_reloc (int r_type
)
776 symbolS
*sym
, *lab
= NULL
;
778 if (*input_line_pointer
== '@')
779 input_line_pointer
++;
780 c
= get_symbol_name (&sym_name
);
781 sym
= symbol_find_or_make (sym_name
);
782 restore_line_pointer (c
);
783 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
785 ++input_line_pointer
;
787 c
= get_symbol_name (&lab_name
);
788 lab
= symbol_find_or_make (lab_name
);
789 restore_line_pointer (c
);
792 /* These relocations exist as a mechanism for the compiler to tell the
793 linker how to patch the code if the tls model is optimised. However,
794 the relocation itself does not require any space within the assembler
795 fragment, and so we pass a size of 0.
797 The lines that generate these relocations look like this:
799 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
801 The '.tls_gd_ld @.tdata' is processed first and generates the
802 additional relocation, while the 'bl __tls_get_addr@plt' is processed
803 second and generates the additional branch.
805 It is possible that the additional relocation generated by the
806 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
807 while the 'bl __tls_get_addr@plt' will be generated as the first thing
808 in the next fragment. This will be fine; both relocations will still
809 appear to be at the same address in the generated object file.
810 However, this only works as the additional relocation is generated
811 with size of 0 bytes. */
813 = fix_new (frag_now
, /* Which frag? */
814 frag_now_fix (), /* Where in that frag? */
815 0, /* size: 1, 2, or 4 usually. */
816 sym
, /* X_add_symbol. */
817 0, /* X_add_number. */
818 FALSE
, /* TRUE if PC-relative relocation. */
819 r_type
/* Relocation type. */);
820 fixP
->fx_subsy
= lab
;
824 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
825 symbolS
*symbolP
, addressT size
)
830 if (*input_line_pointer
== ',')
832 align
= parse_align (1);
834 if (align
== (addressT
) -1)
849 bss_alloc (symbolP
, size
, align
);
850 S_CLEAR_EXTERNAL (symbolP
);
856 arc_lcomm (int ignore
)
858 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
861 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
864 /* Select the cpu we're assembling for. */
867 arc_option (int ignore ATTRIBUTE_UNUSED
)
873 c
= get_symbol_name (&cpu
);
874 mach
= arc_get_mach (cpu
);
879 if (!mach_type_specified_p
)
881 if ((!strcmp ("ARC600", cpu
))
882 || (!strcmp ("ARC601", cpu
))
883 || (!strcmp ("A6", cpu
)))
885 md_parse_option (OPTION_MCPU
, "arc600");
887 else if ((!strcmp ("ARC700", cpu
))
888 || (!strcmp ("A7", cpu
)))
890 md_parse_option (OPTION_MCPU
, "arc700");
892 else if (!strcmp ("EM", cpu
))
894 md_parse_option (OPTION_MCPU
, "arcem");
896 else if (!strcmp ("HS", cpu
))
898 md_parse_option (OPTION_MCPU
, "archs");
901 as_fatal (_("could not find the architecture"));
903 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, mach
))
904 as_fatal (_("could not set architecture and machine"));
907 if (arc_mach_type
!= mach
)
908 as_warn (_("Command-line value overrides \".cpu\" directive"));
910 restore_line_pointer (c
);
911 demand_empty_rest_of_line ();
915 restore_line_pointer (c
);
916 as_bad (_("invalid identifier for \".cpu\""));
917 ignore_rest_of_line ();
920 /* Smartly print an expression. */
923 debug_exp (expressionS
*t
)
925 const char *name ATTRIBUTE_UNUSED
;
926 const char *namemd ATTRIBUTE_UNUSED
;
928 pr_debug ("debug_exp: ");
932 default: name
= "unknown"; break;
933 case O_illegal
: name
= "O_illegal"; break;
934 case O_absent
: name
= "O_absent"; break;
935 case O_constant
: name
= "O_constant"; break;
936 case O_symbol
: name
= "O_symbol"; break;
937 case O_symbol_rva
: name
= "O_symbol_rva"; break;
938 case O_register
: name
= "O_register"; break;
939 case O_big
: name
= "O_big"; break;
940 case O_uminus
: name
= "O_uminus"; break;
941 case O_bit_not
: name
= "O_bit_not"; break;
942 case O_logical_not
: name
= "O_logical_not"; break;
943 case O_multiply
: name
= "O_multiply"; break;
944 case O_divide
: name
= "O_divide"; break;
945 case O_modulus
: name
= "O_modulus"; break;
946 case O_left_shift
: name
= "O_left_shift"; break;
947 case O_right_shift
: name
= "O_right_shift"; break;
948 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
949 case O_bit_or_not
: name
= "O_bit_or_not"; break;
950 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
951 case O_bit_and
: name
= "O_bit_and"; break;
952 case O_add
: name
= "O_add"; break;
953 case O_subtract
: name
= "O_subtract"; break;
954 case O_eq
: name
= "O_eq"; break;
955 case O_ne
: name
= "O_ne"; break;
956 case O_lt
: name
= "O_lt"; break;
957 case O_le
: name
= "O_le"; break;
958 case O_ge
: name
= "O_ge"; break;
959 case O_gt
: name
= "O_gt"; break;
960 case O_logical_and
: name
= "O_logical_and"; break;
961 case O_logical_or
: name
= "O_logical_or"; break;
962 case O_index
: name
= "O_index"; break;
963 case O_bracket
: name
= "O_bracket"; break;
968 default: namemd
= "unknown"; break;
969 case O_gotoff
: namemd
= "O_gotoff"; break;
970 case O_gotpc
: namemd
= "O_gotpc"; break;
971 case O_plt
: namemd
= "O_plt"; break;
972 case O_sda
: namemd
= "O_sda"; break;
973 case O_pcl
: namemd
= "O_pcl"; break;
974 case O_tlsgd
: namemd
= "O_tlsgd"; break;
975 case O_tlsie
: namemd
= "O_tlsie"; break;
976 case O_tpoff9
: namemd
= "O_tpoff9"; break;
977 case O_tpoff
: namemd
= "O_tpoff"; break;
978 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
979 case O_dtpoff
: namemd
= "O_dtpoff"; break;
982 pr_debug ("%s (%s, %s, %d, %s)", name
,
983 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
984 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
985 (int) t
->X_add_number
,
986 (t
->X_md
) ? namemd
: "--");
991 /* Parse the arguments to an opcode. */
994 tokenize_arguments (char *str
,
998 char *old_input_line_pointer
;
999 bfd_boolean saw_comma
= FALSE
;
1000 bfd_boolean saw_arg
= FALSE
;
1005 const struct arc_reloc_op_tag
*r
;
1007 char *reloc_name
, c
;
1009 memset (tok
, 0, sizeof (*tok
) * ntok
);
1011 /* Save and restore input_line_pointer around this function. */
1012 old_input_line_pointer
= input_line_pointer
;
1013 input_line_pointer
= str
;
1015 while (*input_line_pointer
)
1018 switch (*input_line_pointer
)
1024 input_line_pointer
++;
1025 if (saw_comma
|| !saw_arg
)
1032 ++input_line_pointer
;
1036 tok
->X_op
= O_bracket
;
1043 input_line_pointer
++;
1047 tok
->X_op
= O_bracket
;
1053 /* We have labels, function names and relocations, all
1054 starting with @ symbol. Sort them out. */
1055 if (saw_arg
&& !saw_comma
)
1059 tok
->X_op
= O_symbol
;
1060 tok
->X_md
= O_absent
;
1062 if (*input_line_pointer
!= '@')
1063 goto normalsymbol
; /* This is not a relocation. */
1067 /* A relocation opernad has the following form
1068 @identifier@relocation_type. The identifier is already
1070 if (tok
->X_op
!= O_symbol
)
1072 as_bad (_("No valid label relocation operand"));
1076 /* Parse @relocation_type. */
1077 input_line_pointer
++;
1078 c
= get_symbol_name (&reloc_name
);
1079 len
= input_line_pointer
- reloc_name
;
1082 as_bad (_("No relocation operand"));
1086 /* Go through known relocation and try to find a match. */
1087 r
= &arc_reloc_op
[0];
1088 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1089 if (len
== r
->length
1090 && memcmp (reloc_name
, r
->name
, len
) == 0)
1094 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1098 *input_line_pointer
= c
;
1099 SKIP_WHITESPACE_AFTER_NAME ();
1100 /* Extra check for TLS: base. */
1101 if (*input_line_pointer
== '@')
1104 if (tok
->X_op_symbol
!= NULL
1105 || tok
->X_op
!= O_symbol
)
1107 as_bad (_("Unable to parse TLS base: %s"),
1108 input_line_pointer
);
1111 input_line_pointer
++;
1113 c
= get_symbol_name (&sym_name
);
1114 base
= symbol_find_or_make (sym_name
);
1115 tok
->X_op
= O_subtract
;
1116 tok
->X_op_symbol
= base
;
1117 restore_line_pointer (c
);
1118 tmpE
.X_add_number
= 0;
1120 else if ((*input_line_pointer
!= '+')
1121 && (*input_line_pointer
!= '-'))
1123 tmpE
.X_add_number
= 0;
1127 /* Parse the constant of a complex relocation expression
1128 like @identifier@reloc +/- const. */
1129 if (! r
->complex_expr
)
1131 as_bad (_("@%s is not a complex relocation."), r
->name
);
1135 if (tmpE
.X_op
!= O_constant
)
1137 as_bad (_("Bad expression: @%s + %s."),
1138 r
->name
, input_line_pointer
);
1144 tok
->X_add_number
= tmpE
.X_add_number
;
1155 /* Can be a register. */
1156 ++input_line_pointer
;
1160 if (saw_arg
&& !saw_comma
)
1163 tok
->X_op
= O_absent
;
1164 tok
->X_md
= O_absent
;
1167 /* Legacy: There are cases when we have
1168 identifier@relocation_type, if it is the case parse the
1169 relocation type as well. */
1170 if (*input_line_pointer
== '@')
1176 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1188 if (saw_comma
|| brk_lvl
)
1190 input_line_pointer
= old_input_line_pointer
;
1196 as_bad (_("Brackets in operand field incorrect"));
1198 as_bad (_("extra comma"));
1200 as_bad (_("missing argument"));
1202 as_bad (_("missing comma or colon"));
1203 input_line_pointer
= old_input_line_pointer
;
1207 /* Parse the flags to a structure. */
1210 tokenize_flags (const char *str
,
1211 struct arc_flags flags
[],
1214 char *old_input_line_pointer
;
1215 bfd_boolean saw_flg
= FALSE
;
1216 bfd_boolean saw_dot
= FALSE
;
1220 memset (flags
, 0, sizeof (*flags
) * nflg
);
1222 /* Save and restore input_line_pointer around this function. */
1223 old_input_line_pointer
= input_line_pointer
;
1224 input_line_pointer
= (char *) str
;
1226 while (*input_line_pointer
)
1228 switch (*input_line_pointer
)
1235 input_line_pointer
++;
1243 if (saw_flg
&& !saw_dot
)
1246 if (num_flags
>= nflg
)
1249 flgnamelen
= strspn (input_line_pointer
,
1250 "abcdefghijklmnopqrstuvwxyz0123456789");
1251 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1254 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1256 input_line_pointer
+= flgnamelen
;
1266 input_line_pointer
= old_input_line_pointer
;
1271 as_bad (_("extra dot"));
1273 as_bad (_("unrecognized flag"));
1275 as_bad (_("failed to parse flags"));
1276 input_line_pointer
= old_input_line_pointer
;
1280 /* Apply the fixups in order. */
1283 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1287 for (i
= 0; i
< insn
->nfixups
; i
++)
1289 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1290 int size
, pcrel
, offset
= 0;
1292 /* FIXME! the reloc size is wrong in the BFD file.
1293 When it is fixed please delete me. */
1294 size
= (insn
->short_insn
&& !fixup
->islong
) ? 2 : 4;
1297 offset
= (insn
->short_insn
) ? 2 : 4;
1299 /* Some fixups are only used internally, thus no howto. */
1300 if ((int) fixup
->reloc
== 0)
1301 as_fatal (_("Unhandled reloc type"));
1303 if ((int) fixup
->reloc
< 0)
1305 /* FIXME! the reloc size is wrong in the BFD file.
1306 When it is fixed please enable me.
1307 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1308 pcrel
= fixup
->pcrel
;
1312 reloc_howto_type
*reloc_howto
=
1313 bfd_reloc_type_lookup (stdoutput
,
1314 (bfd_reloc_code_real_type
) fixup
->reloc
);
1315 gas_assert (reloc_howto
);
1317 /* FIXME! the reloc size is wrong in the BFD file.
1318 When it is fixed please enable me.
1319 size = bfd_get_reloc_size (reloc_howto); */
1320 pcrel
= reloc_howto
->pc_relative
;
1323 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1325 fragP
->fr_file
, fragP
->fr_line
,
1326 (fixup
->reloc
< 0) ? "Internal" :
1327 bfd_get_reloc_code_name (fixup
->reloc
),
1330 fix_new_exp (fragP
, fix
+ offset
,
1331 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1333 /* Check for ZOLs, and update symbol info if any. */
1334 if (LP_INSN (insn
->insn
))
1336 gas_assert (fixup
->exp
.X_add_symbol
);
1337 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1342 /* Actually output an instruction with its fixup. */
1345 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1349 pr_debug ("Emit insn : 0x%x\n", insn
->insn
);
1350 pr_debug ("\tShort : 0x%d\n", insn
->short_insn
);
1351 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1353 /* Write out the instruction. */
1354 if (insn
->short_insn
)
1360 md_number_to_chars (f
, insn
->insn
, 2);
1361 md_number_to_chars_midend (f
+ 2, insn
->limm
, 4);
1362 dwarf2_emit_insn (6);
1368 md_number_to_chars (f
, insn
->insn
, 2);
1369 dwarf2_emit_insn (2);
1378 md_number_to_chars_midend (f
, insn
->insn
, 4);
1379 md_number_to_chars_midend (f
+ 4, insn
->limm
, 4);
1380 dwarf2_emit_insn (8);
1386 md_number_to_chars_midend (f
, insn
->insn
, 4);
1387 dwarf2_emit_insn (4);
1392 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1396 emit_insn1 (struct arc_insn
*insn
)
1398 /* How frag_var's args are currently configured:
1399 - rs_machine_dependent, to dictate it's a relaxation frag.
1400 - FRAG_MAX_GROWTH, maximum size of instruction
1401 - 0, variable size that might grow...unused by generic relaxation.
1402 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1403 - s, opand expression.
1404 - 0, offset but it's unused.
1405 - 0, opcode but it's unused. */
1406 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1407 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1409 if (frag_room () < FRAG_MAX_GROWTH
)
1411 /* Handle differently when frag literal memory is exhausted.
1412 This is used because when there's not enough memory left in
1413 the current frag, a new frag is created and the information
1414 we put into frag_now->tc_frag_data is disregarded. */
1416 struct arc_relax_type relax_info_copy
;
1417 relax_substateT subtype
= frag_now
->fr_subtype
;
1419 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1420 sizeof (struct arc_relax_type
));
1422 frag_wane (frag_now
);
1423 frag_grow (FRAG_MAX_GROWTH
);
1425 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1426 sizeof (struct arc_relax_type
));
1428 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1432 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1433 frag_now
->fr_subtype
, s
, 0, 0);
1437 emit_insn (struct arc_insn
*insn
)
1442 emit_insn0 (insn
, NULL
, FALSE
);
1445 /* Check whether a symbol involves a register. */
1448 contains_register (symbolS
*sym
)
1452 expressionS
*ex
= symbol_get_value_expression (sym
);
1454 return ((O_register
== ex
->X_op
)
1455 && !contains_register (ex
->X_add_symbol
)
1456 && !contains_register (ex
->X_op_symbol
));
1462 /* Returns the register number within a symbol. */
1465 get_register (symbolS
*sym
)
1467 if (!contains_register (sym
))
1470 expressionS
*ex
= symbol_get_value_expression (sym
);
1471 return regno (ex
->X_add_number
);
1474 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1475 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1478 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1485 case BFD_RELOC_ARC_SDA_LDST
:
1486 case BFD_RELOC_ARC_SDA_LDST1
:
1487 case BFD_RELOC_ARC_SDA_LDST2
:
1488 case BFD_RELOC_ARC_SDA16_LD
:
1489 case BFD_RELOC_ARC_SDA16_LD1
:
1490 case BFD_RELOC_ARC_SDA16_LD2
:
1491 case BFD_RELOC_ARC_SDA16_ST2
:
1492 case BFD_RELOC_ARC_SDA32_ME
:
1499 /* Allocates a tok entry. */
1502 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1504 if (ntok
> MAX_INSN_ARGS
- 2)
1505 return 0; /* No space left. */
1508 return 0; /* Incorect args. */
1510 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1513 return 1; /* Success. */
1514 return allocate_tok (tok
, ntok
- 1, cidx
);
1517 /* Check if an particular ARC feature is enabled. */
1520 check_cpu_feature (insn_subclass_t sc
)
1522 if (!(arc_features
& ARC_CD
)
1523 && is_code_density_p (sc
))
1526 if (!(arc_features
& ARC_SPFP
)
1530 if (!(arc_features
& ARC_DPFP
)
1534 if (!(arc_features
& ARC_FPUDA
)
1541 /* Search forward through all variants of an opcode looking for a
1544 static const struct arc_opcode
*
1545 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1548 struct arc_flags
*first_pflag
,
1552 const struct arc_opcode
*opcode
;
1553 struct arc_opcode_hash_entry_iterator iter
;
1555 int got_cpu_match
= 0;
1556 expressionS bktok
[MAX_INSN_ARGS
];
1560 arc_opcode_hash_entry_iterator_init (&iter
);
1561 memset (&emptyE
, 0, sizeof (emptyE
));
1562 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1565 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1567 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1569 const unsigned char *opidx
;
1570 const unsigned char *flgidx
;
1571 int tokidx
= 0, lnflg
, i
;
1572 const expressionS
*t
= &emptyE
;
1574 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1575 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1577 /* Don't match opcodes that don't exist on this
1579 if (!(opcode
->cpu
& arc_target
))
1582 if (!check_cpu_feature (opcode
->subclass
))
1588 /* Check the operands. */
1589 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1591 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1593 /* Only take input from real operands. */
1594 if ((operand
->flags
& ARC_OPERAND_FAKE
)
1595 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
1598 /* When we expect input, make sure we have it. */
1602 /* Match operand type with expression type. */
1603 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1605 case ARC_OPERAND_IR
:
1606 /* Check to be a register. */
1607 if ((tok
[tokidx
].X_op
!= O_register
1608 || !is_ir_num (tok
[tokidx
].X_add_number
))
1609 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1612 /* If expect duplicate, make sure it is duplicate. */
1613 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1615 /* Check for duplicate. */
1616 if (t
->X_op
!= O_register
1617 || !is_ir_num (t
->X_add_number
)
1618 || (regno (t
->X_add_number
) !=
1619 regno (tok
[tokidx
].X_add_number
)))
1623 /* Special handling? */
1624 if (operand
->insert
)
1626 const char *errmsg
= NULL
;
1627 (*operand
->insert
)(0,
1628 regno (tok
[tokidx
].X_add_number
),
1632 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1634 /* Missing argument, create one. */
1635 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1638 tok
[tokidx
].X_op
= O_absent
;
1649 case ARC_OPERAND_BRAKET
:
1650 /* Check if bracket is also in opcode table as
1652 if (tok
[tokidx
].X_op
!= O_bracket
)
1656 case ARC_OPERAND_LIMM
:
1657 case ARC_OPERAND_SIGNED
:
1658 case ARC_OPERAND_UNSIGNED
:
1659 switch (tok
[tokidx
].X_op
)
1667 /* Got an (too) early bracket, check if it is an
1668 ignored operand. N.B. This procedure works only
1669 when bracket is the last operand! */
1670 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1672 /* Insert the missing operand. */
1673 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1676 tok
[tokidx
].X_op
= O_absent
;
1683 const struct arc_aux_reg
*auxr
;
1685 if (opcode
->class != AUXREG
)
1687 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1689 auxr
= hash_find (arc_aux_hash
, p
);
1692 /* We modify the token array here, safe in the
1693 knowledge, that if this was the wrong
1694 choice then the original contents will be
1695 restored from BKTOK. */
1696 tok
[tokidx
].X_op
= O_constant
;
1697 tok
[tokidx
].X_add_number
= auxr
->address
;
1698 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1701 if (tok
[tokidx
].X_op
!= O_constant
)
1706 /* Check the range. */
1707 if (operand
->bits
!= 32
1708 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1710 offsetT min
, max
, val
;
1711 val
= tok
[tokidx
].X_add_number
;
1713 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1715 max
= (1 << (operand
->bits
- 1)) - 1;
1716 min
= -(1 << (operand
->bits
- 1));
1720 max
= (1 << operand
->bits
) - 1;
1724 if (val
< min
|| val
> max
)
1727 /* Check alignmets. */
1728 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1732 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1736 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1738 if (operand
->insert
)
1740 const char *errmsg
= NULL
;
1741 (*operand
->insert
)(0,
1742 tok
[tokidx
].X_add_number
,
1753 /* Check if it is register range. */
1754 if ((tok
[tokidx
].X_add_number
== 0)
1755 && contains_register (tok
[tokidx
].X_add_symbol
)
1756 && contains_register (tok
[tokidx
].X_op_symbol
))
1760 regs
= get_register (tok
[tokidx
].X_add_symbol
);
1762 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
1763 if (operand
->insert
)
1765 const char *errmsg
= NULL
;
1766 (*operand
->insert
)(0,
1778 if (operand
->default_reloc
== 0)
1779 goto match_failed
; /* The operand needs relocation. */
1781 /* Relocs requiring long immediate. FIXME! make it
1782 generic and move it to a function. */
1783 switch (tok
[tokidx
].X_md
)
1792 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
1795 if (!generic_reloc_p (operand
->default_reloc
))
1802 /* If expect duplicate, make sure it is duplicate. */
1803 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1805 if (t
->X_op
== O_illegal
1806 || t
->X_op
== O_absent
1807 || t
->X_op
== O_register
1808 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
1815 /* Everything else should have been fake. */
1823 /* Setup ready for flag parsing. */
1825 for (i
= 0; i
< nflgs
; i
++)
1826 first_pflag
[i
].flgp
= NULL
;
1828 /* Check the flags. Iterate over the valid flag classes. */
1829 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1831 /* Get a valid flag class. */
1832 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1833 const unsigned *flgopridx
;
1835 struct arc_flags
*pflag
= NULL
;
1837 /* Check for extension conditional codes. */
1838 if (ext_condcode
.arc_ext_condcode
1839 && cl_flags
->class & F_CLASS_EXTEND
)
1841 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1844 pflag
= first_pflag
;
1845 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1847 if (!strcmp (pf
->name
, pflag
->name
))
1849 if (pflag
->flgp
!= NULL
)
1862 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1864 const struct arc_flag_operand
*flg_operand
;
1866 pflag
= first_pflag
;
1867 flg_operand
= &arc_flag_operands
[*flgopridx
];
1868 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1870 /* Match against the parsed flags. */
1871 if (!strcmp (flg_operand
->name
, pflag
->name
))
1873 if (pflag
->flgp
!= NULL
)
1876 pflag
->flgp
= (struct arc_flag_operand
*) flg_operand
;
1878 break; /* goto next flag class and parsed flag. */
1883 if ((cl_flags
->class & F_CLASS_REQUIRED
) && cl_matches
== 0)
1885 if ((cl_flags
->class & F_CLASS_OPTIONAL
) && cl_matches
> 1)
1888 /* Did I check all the parsed flags? */
1893 /* Possible match -- did we use all of our input? */
1903 /* Restore the original parameters. */
1904 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
1909 *pcpumatch
= got_cpu_match
;
1914 /* Swap operand tokens. */
1917 swap_operand (expressionS
*operand_array
,
1919 unsigned destination
)
1921 expressionS cpy_operand
;
1922 expressionS
*src_operand
;
1923 expressionS
*dst_operand
;
1926 if (source
== destination
)
1929 src_operand
= &operand_array
[source
];
1930 dst_operand
= &operand_array
[destination
];
1931 size
= sizeof (expressionS
);
1933 /* Make copy of operand to swap with and swap. */
1934 memcpy (&cpy_operand
, dst_operand
, size
);
1935 memcpy (dst_operand
, src_operand
, size
);
1936 memcpy (src_operand
, &cpy_operand
, size
);
1939 /* Check if *op matches *tok type.
1940 Returns FALSE if they don't match, TRUE if they match. */
1943 pseudo_operand_match (const expressionS
*tok
,
1944 const struct arc_operand_operation
*op
)
1946 offsetT min
, max
, val
;
1948 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
1954 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
1956 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
1958 val
= tok
->X_add_number
+ op
->count
;
1959 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
1961 max
= (1 << (operand_real
->bits
- 1)) - 1;
1962 min
= -(1 << (operand_real
->bits
- 1));
1966 max
= (1 << operand_real
->bits
) - 1;
1969 if (min
<= val
&& val
<= max
)
1975 /* Handle all symbols as long immediates or signed 9. */
1976 if (operand_real
->flags
& ARC_OPERAND_LIMM
||
1977 ((operand_real
->flags
& ARC_OPERAND_SIGNED
) && operand_real
->bits
== 9))
1982 if (operand_real
->flags
& ARC_OPERAND_IR
)
1987 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
1998 /* Find pseudo instruction in array. */
2000 static const struct arc_pseudo_insn
*
2001 find_pseudo_insn (const char *opname
,
2003 const expressionS
*tok
)
2005 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2006 const struct arc_operand_operation
*op
;
2010 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2012 pseudo_insn
= &arc_pseudo_insns
[i
];
2013 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2015 op
= pseudo_insn
->operand
;
2016 for (j
= 0; j
< ntok
; ++j
)
2017 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2020 /* Found the right instruction. */
2028 /* Assumes the expressionS *tok is of sufficient size. */
2030 static const struct arc_opcode_hash_entry
*
2031 find_special_case_pseudo (const char *opname
,
2035 struct arc_flags
*pflags
)
2037 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2038 const struct arc_operand_operation
*operand_pseudo
;
2039 const struct arc_operand
*operand_real
;
2041 char construct_operand
[MAX_CONSTR_STR
];
2043 /* Find whether opname is in pseudo instruction array. */
2044 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2046 if (pseudo_insn
== NULL
)
2049 /* Handle flag, Limited to one flag at the moment. */
2050 if (pseudo_insn
->flag_r
!= NULL
)
2051 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2052 MAX_INSN_FLGS
- *nflgs
);
2054 /* Handle operand operations. */
2055 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2057 operand_pseudo
= &pseudo_insn
->operand
[i
];
2058 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2060 if (operand_real
->flags
& ARC_OPERAND_BRAKET
&&
2061 !operand_pseudo
->needs_insert
)
2064 /* Has to be inserted (i.e. this token does not exist yet). */
2065 if (operand_pseudo
->needs_insert
)
2067 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2069 tok
[i
].X_op
= O_bracket
;
2074 /* Check if operand is a register or constant and handle it
2076 if (operand_real
->flags
& ARC_OPERAND_IR
)
2077 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2078 operand_pseudo
->count
);
2080 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2081 operand_pseudo
->count
);
2083 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2087 else if (operand_pseudo
->count
)
2089 /* Operand number has to be adjusted accordingly (by operand
2091 switch (tok
[i
].X_op
)
2094 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2107 /* Swap operands if necessary. Only supports one swap at the
2109 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2111 operand_pseudo
= &pseudo_insn
->operand
[i
];
2113 if (operand_pseudo
->swap_operand_idx
== i
)
2116 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2118 /* Prevent a swap back later by breaking out. */
2122 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2125 static const struct arc_opcode_hash_entry
*
2126 find_special_case_flag (const char *opname
,
2128 struct arc_flags
*pflags
)
2132 unsigned flag_idx
, flag_arr_idx
;
2133 size_t flaglen
, oplen
;
2134 const struct arc_flag_special
*arc_flag_special_opcode
;
2135 const struct arc_opcode_hash_entry
*entry
;
2137 /* Search for special case instruction. */
2138 for (i
= 0; i
< arc_num_flag_special
; i
++)
2140 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2141 oplen
= strlen (arc_flag_special_opcode
->name
);
2143 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2146 /* Found a potential special case instruction, now test for
2148 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2150 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2152 break; /* End of array, nothing found. */
2154 flagnm
= arc_flag_operands
[flag_idx
].name
;
2155 flaglen
= strlen (flagnm
);
2156 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2158 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2160 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2162 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2163 pflags
[*nflgs
].name
[flaglen
] = '\0';
2172 /* Used to find special case opcode. */
2174 static const struct arc_opcode_hash_entry
*
2175 find_special_case (const char *opname
,
2177 struct arc_flags
*pflags
,
2181 const struct arc_opcode_hash_entry
*entry
;
2183 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2186 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2191 /* Given an opcode name, pre-tockenized set of argumenst and the
2192 opcode flags, take it all the way through emission. */
2195 assemble_tokens (const char *opname
,
2198 struct arc_flags
*pflags
,
2201 bfd_boolean found_something
= FALSE
;
2202 const struct arc_opcode_hash_entry
*entry
;
2205 /* Search opcodes. */
2206 entry
= arc_find_opcode (opname
);
2208 /* Couldn't find opcode conventional way, try special cases. */
2210 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2214 const struct arc_opcode
*opcode
;
2216 pr_debug ("%s:%d: assemble_tokens: %s\n",
2217 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2218 found_something
= TRUE
;
2219 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2223 struct arc_insn insn
;
2225 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2231 if (found_something
)
2234 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2236 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2240 as_bad (_("unknown opcode '%s'"), opname
);
2243 /* The public interface to the instruction assembler. */
2246 md_assemble (char *str
)
2249 expressionS tok
[MAX_INSN_ARGS
];
2252 struct arc_flags flags
[MAX_INSN_FLGS
];
2254 /* Split off the opcode. */
2255 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2256 opname
= xmalloc (opnamelen
+ 1);
2257 memcpy (opname
, str
, opnamelen
);
2258 opname
[opnamelen
] = '\0';
2260 /* Signalize we are assmbling the instructions. */
2261 assembling_insn
= TRUE
;
2263 /* Tokenize the flags. */
2264 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2266 as_bad (_("syntax error"));
2270 /* Scan up to the end of the mnemonic which must end in space or end
2273 for (; *str
!= '\0'; str
++)
2277 /* Tokenize the rest of the line. */
2278 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2280 as_bad (_("syntax error"));
2284 /* Finish it off. */
2285 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2286 assembling_insn
= FALSE
;
2289 /* Callback to insert a register into the hash table. */
2292 declare_register (const char *name
, int number
)
2295 symbolS
*regS
= symbol_create (name
, reg_section
,
2296 number
, &zero_address_frag
);
2298 err
= hash_insert (arc_reg_hash
, S_GET_NAME (regS
), (void *) regS
);
2300 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
2304 /* Construct symbols for each of the general registers. */
2307 declare_register_set (void)
2310 for (i
= 0; i
< 64; ++i
)
2314 sprintf (name
, "r%d", i
);
2315 declare_register (name
, i
);
2316 if ((i
& 0x01) == 0)
2318 sprintf (name
, "r%dr%d", i
, i
+1);
2319 declare_register (name
, i
);
2324 /* Port-specific assembler initialization. This function is called
2325 once, at assembler startup time. */
2330 const struct arc_opcode
*opcode
= arc_opcodes
;
2332 if (!mach_type_specified_p
)
2333 arc_select_cpu ("arc700");
2335 /* The endianness can be chosen "at the factory". */
2336 target_big_endian
= byte_order
== BIG_ENDIAN
;
2338 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, arc_mach_type
))
2339 as_warn (_("could not set architecture and machine"));
2341 /* Set elf header flags. */
2342 bfd_set_private_flags (stdoutput
, arc_eflag
);
2344 /* Set up a hash table for the instructions. */
2345 arc_opcode_hash
= hash_new ();
2346 if (arc_opcode_hash
== NULL
)
2347 as_fatal (_("Virtual memory exhausted"));
2349 /* Initialize the hash table with the insns. */
2352 const char *name
= opcode
->name
;
2354 arc_insert_opcode (opcode
);
2356 while (++opcode
&& opcode
->name
2357 && (opcode
->name
== name
2358 || !strcmp (opcode
->name
, name
)))
2360 }while (opcode
->name
);
2362 /* Register declaration. */
2363 arc_reg_hash
= hash_new ();
2364 if (arc_reg_hash
== NULL
)
2365 as_fatal (_("Virtual memory exhausted"));
2367 declare_register_set ();
2368 declare_register ("gp", 26);
2369 declare_register ("fp", 27);
2370 declare_register ("sp", 28);
2371 declare_register ("ilink", 29);
2372 declare_register ("ilink1", 29);
2373 declare_register ("ilink2", 30);
2374 declare_register ("blink", 31);
2376 declare_register ("mlo", 57);
2377 declare_register ("mmid", 58);
2378 declare_register ("mhi", 59);
2380 declare_register ("acc1", 56);
2381 declare_register ("acc2", 57);
2383 declare_register ("lp_count", 60);
2384 declare_register ("pcl", 63);
2386 /* Initialize the last instructions. */
2387 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2389 /* Aux register declaration. */
2390 arc_aux_hash
= hash_new ();
2391 if (arc_aux_hash
== NULL
)
2392 as_fatal (_("Virtual memory exhausted"));
2394 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2396 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2400 if (!(auxr
->cpu
& arc_target
))
2403 if ((auxr
->subclass
!= NONE
)
2404 && !check_cpu_feature (auxr
->subclass
))
2407 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
2409 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2410 auxr
->name
, retval
);
2414 /* Write a value out to the object file, using the appropriate
2418 md_number_to_chars (char *buf
,
2422 if (target_big_endian
)
2423 number_to_chars_bigendian (buf
, val
, n
);
2425 number_to_chars_littleendian (buf
, val
, n
);
2428 /* Round up a section size to the appropriate boundary. */
2431 md_section_align (segT segment
,
2434 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2436 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2439 /* The location from which a PC relative jump should be calculated,
2440 given a PC relative reloc. */
2443 md_pcrel_from_section (fixS
*fixP
,
2446 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2448 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2450 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2451 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2452 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2454 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2456 /* The symbol is undefined (or is defined but not in this section).
2457 Let the linker figure it out. */
2461 if ((int) fixP
->fx_r_type
< 0)
2463 /* These are the "internal" relocations. Align them to
2464 32 bit boundary (PCL), for the moment. */
2469 switch (fixP
->fx_r_type
)
2471 case BFD_RELOC_ARC_PC32
:
2472 /* The hardware calculates relative to the start of the
2473 insn, but this relocation is relative to location of the
2474 LIMM, compensate. The base always needs to be
2475 substracted by 4 as we do not support this type of PCrel
2476 relocation for short instructions. */
2479 case BFD_RELOC_ARC_PLT32
:
2480 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2481 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2482 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2483 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2485 case BFD_RELOC_ARC_S21H_PCREL
:
2486 case BFD_RELOC_ARC_S25H_PCREL
:
2487 case BFD_RELOC_ARC_S13_PCREL
:
2488 case BFD_RELOC_ARC_S21W_PCREL
:
2489 case BFD_RELOC_ARC_S25W_PCREL
:
2493 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2494 _("unhandled reloc %s in md_pcrel_from_section"),
2495 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2500 pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n",
2501 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2502 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2503 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2508 /* Given a BFD relocation find the coresponding operand. */
2510 static const struct arc_operand
*
2511 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2515 for (i
= 0; i
< arc_num_operands
; i
++)
2516 if (arc_operands
[i
].default_reloc
== reloc
)
2517 return &arc_operands
[i
];
2521 /* Insert an operand value into an instruction. */
2524 insert_operand (unsigned insn
,
2525 const struct arc_operand
*operand
,
2530 offsetT min
= 0, max
= 0;
2532 if (operand
->bits
!= 32
2533 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2534 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2536 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2538 max
= (1 << (operand
->bits
- 1)) - 1;
2539 min
= -(1 << (operand
->bits
- 1));
2543 max
= (1 << operand
->bits
) - 1;
2547 if (val
< min
|| val
> max
)
2548 as_bad_value_out_of_range (_("operand"),
2549 val
, min
, max
, file
, line
);
2552 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2553 min
, val
, max
, insn
);
2555 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2557 as_bad_where (file
, line
,
2558 _("Unaligned operand. Needs to be 32bit aligned"));
2560 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2562 as_bad_where (file
, line
,
2563 _("Unaligned operand. Needs to be 16bit aligned"));
2565 if (operand
->insert
)
2567 const char *errmsg
= NULL
;
2569 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2571 as_warn_where (file
, line
, "%s", errmsg
);
2575 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2577 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2579 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2582 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2587 /* Apply a fixup to the object code. At this point all symbol values
2588 should be fully resolved, and we attempt to completely resolve the
2589 reloc. If we can not do that, we determine the correct reloc code
2590 and put it back in the fixup. To indicate that a fixup has been
2591 eliminated, set fixP->fx_done. */
2594 md_apply_fix (fixS
*fixP
,
2598 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2599 valueT value
= *valP
;
2601 symbolS
*fx_addsy
, *fx_subsy
;
2603 segT add_symbol_segment
= absolute_section
;
2604 segT sub_symbol_segment
= absolute_section
;
2605 const struct arc_operand
*operand
= NULL
;
2606 extended_bfd_reloc_code_real_type reloc
;
2608 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2609 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2610 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2611 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2614 fx_addsy
= fixP
->fx_addsy
;
2615 fx_subsy
= fixP
->fx_subsy
;
2620 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2624 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2625 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2626 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2628 resolve_symbol_value (fx_subsy
);
2629 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2631 if (sub_symbol_segment
== absolute_section
)
2633 /* The symbol is really a constant. */
2634 fx_offset
-= S_GET_VALUE (fx_subsy
);
2639 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2640 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2641 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2642 segment_name (add_symbol_segment
),
2643 S_GET_NAME (fx_subsy
),
2644 segment_name (sub_symbol_segment
));
2650 && !S_IS_WEAK (fx_addsy
))
2652 if (add_symbol_segment
== seg
2655 value
+= S_GET_VALUE (fx_addsy
);
2656 value
-= md_pcrel_from_section (fixP
, seg
);
2658 fixP
->fx_pcrel
= FALSE
;
2660 else if (add_symbol_segment
== absolute_section
)
2662 value
= fixP
->fx_offset
;
2663 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2665 fixP
->fx_pcrel
= FALSE
;
2670 fixP
->fx_done
= TRUE
;
2675 && ((S_IS_DEFINED (fx_addsy
)
2676 && S_GET_SEGMENT (fx_addsy
) != seg
)
2677 || S_IS_WEAK (fx_addsy
)))
2678 value
+= md_pcrel_from_section (fixP
, seg
);
2680 switch (fixP
->fx_r_type
)
2682 case BFD_RELOC_ARC_32_ME
:
2683 /* This is a pc-relative value in a LIMM. Adjust it to the
2684 address of the instruction not to the address of the
2685 LIMM. Note: it is not anylonger valid this afirmation as
2686 the linker consider ARC_PC32 a fixup to entire 64 bit
2688 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2691 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2693 case BFD_RELOC_ARC_PC32
:
2694 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2697 if ((int) fixP
->fx_r_type
< 0)
2698 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2704 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2705 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2706 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2707 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2711 /* Now check for TLS relocations. */
2712 reloc
= fixP
->fx_r_type
;
2715 case BFD_RELOC_ARC_TLS_DTPOFF
:
2716 case BFD_RELOC_ARC_TLS_LE_32
:
2720 case BFD_RELOC_ARC_TLS_GD_GOT
:
2721 case BFD_RELOC_ARC_TLS_IE_GOT
:
2722 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2725 case BFD_RELOC_ARC_TLS_GD_LD
:
2726 gas_assert (!fixP
->fx_offset
);
2729 = (S_GET_VALUE (fixP
->fx_subsy
)
2730 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
2731 fixP
->fx_subsy
= NULL
;
2733 case BFD_RELOC_ARC_TLS_GD_CALL
:
2734 /* These two relocs are there just to allow ld to change the tls
2735 model for this symbol, by patching the code. The offset -
2736 and scale, if any - will be installed by the linker. */
2737 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2740 case BFD_RELOC_ARC_TLS_LE_S9
:
2741 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
2742 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2754 /* Addjust the value if we have a constant. */
2757 /* For hosts with longs bigger than 32-bits make sure that the top
2758 bits of a 32-bit negative value read in by the parser are set,
2759 so that the correct comparisons are made. */
2760 if (value
& 0x80000000)
2761 value
|= (-1L << 31);
2763 reloc
= fixP
->fx_r_type
;
2771 case BFD_RELOC_ARC_32_PCREL
:
2772 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
2775 case BFD_RELOC_ARC_GOTPC32
:
2776 /* I cannot fix an GOTPC relocation because I need to relax it
2777 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2778 as_bad (_("Unsupported operation on reloc"));
2781 case BFD_RELOC_ARC_TLS_DTPOFF
:
2782 case BFD_RELOC_ARC_TLS_LE_32
:
2783 gas_assert (!fixP
->fx_addsy
);
2784 gas_assert (!fixP
->fx_subsy
);
2786 case BFD_RELOC_ARC_GOTOFF
:
2787 case BFD_RELOC_ARC_32_ME
:
2788 case BFD_RELOC_ARC_PC32
:
2789 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2792 case BFD_RELOC_ARC_PLT32
:
2793 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
2796 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2797 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2800 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2801 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
2804 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2805 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
2808 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2809 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
2811 case BFD_RELOC_ARC_S25W_PCREL
:
2812 case BFD_RELOC_ARC_S21W_PCREL
:
2813 case BFD_RELOC_ARC_S21H_PCREL
:
2814 case BFD_RELOC_ARC_S25H_PCREL
:
2815 case BFD_RELOC_ARC_S13_PCREL
:
2817 operand
= find_operand_for_reloc (reloc
);
2818 gas_assert (operand
);
2823 if ((int) fixP
->fx_r_type
>= 0)
2824 as_fatal (_("unhandled relocation type %s"),
2825 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2827 /* The rest of these fixups needs to be completely resolved as
2829 if (fixP
->fx_addsy
!= 0
2830 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
2831 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2832 _("non-absolute expression in constant field"));
2834 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
2835 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
2840 if (target_big_endian
)
2842 switch (fixP
->fx_size
)
2845 insn
= bfd_getb32 (fixpos
);
2848 insn
= bfd_getb16 (fixpos
);
2851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2852 _("unknown fixup size"));
2858 switch (fixP
->fx_size
)
2861 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
2864 insn
= bfd_getl16 (fixpos
);
2867 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2868 _("unknown fixup size"));
2872 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
2873 fixP
->fx_file
, fixP
->fx_line
);
2875 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
2878 /* Prepare machine-dependent frags for relaxation.
2880 Called just before relaxation starts. Any symbol that is now undefined
2881 will not become defined.
2883 Return the correct fr_subtype in the frag.
2885 Return the initial "guess for fr_var" to caller. The guess for fr_var
2886 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
2887 or fr_var contributes to our returned value.
2889 Although it may not be explicit in the frag, pretend
2890 fr_var starts with a value. */
2893 md_estimate_size_before_relax (fragS
*fragP
,
2898 /* If the symbol is not located within the same section AND it's not
2899 an absolute section, use the maximum. OR if the symbol is a
2900 constant AND the insn is by nature not pc-rel, use the maximum.
2901 OR if the symbol is being equated against another symbol, use the
2902 maximum. OR if the symbol is weak use the maximum. */
2903 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
2904 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2905 || (symbol_constant_p (fragP
->fr_symbol
)
2906 && !fragP
->tc_frag_data
.pcrel
)
2907 || symbol_equated_p (fragP
->fr_symbol
)
2908 || S_IS_WEAK (fragP
->fr_symbol
))
2910 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
2911 ++fragP
->fr_subtype
;
2914 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
2915 fragP
->fr_var
= growth
;
2917 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
2918 fragP
->fr_file
, fragP
->fr_line
, growth
);
2923 /* Translate internal representation of relocation info to BFD target
2927 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
2931 bfd_reloc_code_real_type code
;
2933 reloc
= (arelent
*) xmalloc (sizeof (* reloc
));
2934 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2935 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
2936 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
2938 /* Make sure none of our internal relocations make it this far.
2939 They'd better have been fully resolved by this point. */
2940 gas_assert ((int) fixP
->fx_r_type
> 0);
2942 code
= fixP
->fx_r_type
;
2944 /* if we have something like add gp, pcl,
2945 _GLOBAL_OFFSET_TABLE_@gotpc. */
2946 if (code
== BFD_RELOC_ARC_GOTPC32
2948 && fixP
->fx_addsy
== GOT_symbol
)
2949 code
= BFD_RELOC_ARC_GOTPC
;
2951 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
2952 if (reloc
->howto
== NULL
)
2954 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2955 _("cannot represent `%s' relocation in object file"),
2956 bfd_get_reloc_code_name (code
));
2960 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
2961 as_fatal (_("internal error? cannot generate `%s' relocation"),
2962 bfd_get_reloc_code_name (code
));
2964 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
2966 if (code
== BFD_RELOC_ARC_TLS_DTPOFF
2967 || code
== BFD_RELOC_ARC_TLS_DTPOFF_S9
)
2970 = fixP
->fx_subsy
? symbol_get_bfdsym (fixP
->fx_subsy
) : NULL
;
2971 /* We just want to store a 24 bit index, but we have to wait
2972 till after write_contents has been called via
2973 bfd_map_over_sections before we can get the index from
2974 _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
2975 function is elf32-arc.c has to pick up the slack.
2976 Unfortunately, this leads to problems with hosts that have
2977 pointers wider than long (bfd_vma). There would be various
2978 ways to handle this, all error-prone :-( */
2979 reloc
->addend
= (bfd_vma
) sym
;
2980 if ((asymbol
*) reloc
->addend
!= sym
)
2982 as_bad ("Can't store pointer\n");
2987 reloc
->addend
= fixP
->fx_offset
;
2992 /* Perform post-processing of machine-dependent frags after relaxation.
2993 Called after relaxation is finished.
2994 In: Address of frag.
2995 fr_type == rs_machine_dependent.
2996 fr_subtype is what the address relaxed to.
2998 Out: Any fixS:s and constants are set up. */
3001 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3002 segT segment ATTRIBUTE_UNUSED
,
3005 const relax_typeS
*table_entry
;
3007 const struct arc_opcode
*opcode
;
3008 struct arc_insn insn
;
3010 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3012 fix
= (fragP
->fr_fix
< 0 ? 0 : fragP
->fr_fix
);
3013 dest
= fragP
->fr_literal
+ fix
;
3014 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3016 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n",
3017 fragP
->fr_file
, fragP
->fr_line
,
3018 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3020 if (fragP
->fr_subtype
<= 0
3021 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3022 as_fatal (_("no relaxation found for this instruction."));
3024 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3026 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3027 relax_arg
->nflg
, &insn
);
3029 apply_fixups (&insn
, fragP
, fix
);
3031 size
= insn
.short_insn
? (insn
.has_limm
? 6 : 2) : (insn
.has_limm
? 8 : 4);
3032 gas_assert (table_entry
->rlx_length
== size
);
3033 emit_insn0 (&insn
, dest
, TRUE
);
3035 fragP
->fr_fix
+= table_entry
->rlx_length
;
3039 /* We have no need to default values of symbols. We could catch
3040 register names here, but that is handled by inserting them all in
3041 the symbol table to begin with. */
3044 md_undefined_symbol (char *name
)
3046 /* The arc abi demands that a GOT[0] should be referencible as
3047 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3048 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3050 && (*(name
+1) == 'G')
3051 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0))
3053 && (*(name
+1) == 'D')
3054 && (strcmp (name
, DYNAMIC_STRUCT_NAME
) == 0)))
3058 if (symbol_find (name
))
3059 as_bad ("GOT already in symbol table");
3061 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3062 (valueT
) 0, &zero_address_frag
);
3069 /* Turn a string in input_line_pointer into a floating point constant
3070 of type type, and store the appropriate bytes in *litP. The number
3071 of LITTLENUMS emitted is stored in *sizeP. An error message is
3072 returned, or NULL on OK. */
3075 md_atof (int type
, char *litP
, int *sizeP
)
3077 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3080 /* Called for any expression that can not be recognized. When the
3081 function is called, `input_line_pointer' will point to the start of
3085 md_operand (expressionS
*expressionP ATTRIBUTE_UNUSED
)
3087 char *p
= input_line_pointer
;
3090 input_line_pointer
++;
3091 expressionP
->X_op
= O_symbol
;
3092 expression (expressionP
);
3096 /* This function is called from the function 'expression', it attempts
3097 to parse special names (in our case register names). It fills in
3098 the expression with the identified register. It returns TRUE if
3099 it is a register and FALSE otherwise. */
3102 arc_parse_name (const char *name
,
3103 struct expressionS
*e
)
3107 if (!assembling_insn
)
3110 /* Handle only registers. */
3111 if (e
->X_op
!= O_absent
)
3114 sym
= hash_find (arc_reg_hash
, name
);
3117 e
->X_op
= O_register
;
3118 e
->X_add_number
= S_GET_VALUE (sym
);
3125 Invocation line includes a switch not recognized by the base assembler.
3126 See if it's a processor-specific option.
3128 New options (supported) are:
3130 -mcpu=<cpu name> Assemble for selected processor
3131 -EB/-mbig-endian Big-endian
3132 -EL/-mlittle-endian Little-endian
3133 -mrelax Enable relaxation
3135 The following CPU names are recognized:
3136 arc700, av2em, av2hs. */
3139 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3145 return md_parse_option (OPTION_MCPU
, "arc600");
3148 return md_parse_option (OPTION_MCPU
, "arc700");
3151 return md_parse_option (OPTION_MCPU
, "arcem");
3154 return md_parse_option (OPTION_MCPU
, "archs");
3158 arc_select_cpu (arg
);
3159 mach_type_specified_p
= 1;
3164 arc_target_format
= "elf32-bigarc";
3165 byte_order
= BIG_ENDIAN
;
3169 arc_target_format
= "elf32-littlearc";
3170 byte_order
= LITTLE_ENDIAN
;
3174 /* This option has an effect only on ARC EM. */
3175 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3176 arc_features
|= ARC_CD
;
3178 as_warn (_("Code density option invalid for selected CPU"));
3182 relaxation_state
= 1;
3185 case OPTION_USER_MODE
:
3186 case OPTION_LD_EXT_MASK
:
3189 case OPTION_BARREL_SHIFT
:
3190 case OPTION_MIN_MAX
:
3195 /* Dummy options are accepted but have no effect. */
3199 arc_features
|= ARC_SPFP
;
3203 arc_features
|= ARC_DPFP
;
3206 case OPTION_XMAC_D16
:
3207 case OPTION_XMAC_24
:
3208 case OPTION_DSP_PACKA
:
3211 case OPTION_TELEPHONY
:
3212 case OPTION_XYMEMORY
:
3216 /* Dummy options are accepted but have no effect. */
3220 /* This option has an effect only on ARC EM. */
3221 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3222 arc_features
|= ARC_FPUDA
;
3224 as_warn (_("FPUDA invalid for selected CPU"));
3235 md_show_usage (FILE *stream
)
3237 fprintf (stream
, _("ARC-specific assembler options:\n"));
3239 fprintf (stream
, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
3241 " -mcode-density\t enable code density option for ARC EM\n");
3243 fprintf (stream
, _("\
3244 -EB assemble code for a big-endian cpu\n"));
3245 fprintf (stream
, _("\
3246 -EL assemble code for a little-endian cpu\n"));
3247 fprintf (stream
, _("\
3248 -mrelax Enable relaxation\n"));
3252 /* Find the proper relocation for the given opcode. */
3254 static extended_bfd_reloc_code_real_type
3255 find_reloc (const char *name
,
3256 const char *opcodename
,
3257 const struct arc_flags
*pflags
,
3259 extended_bfd_reloc_code_real_type reloc
)
3263 bfd_boolean found_flag
, tmp
;
3264 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3266 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3268 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3270 /* Find the entry. */
3271 if (strcmp (name
, r
->name
))
3273 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3280 unsigned * psflg
= (unsigned *)r
->flags
;
3284 for (j
= 0; j
< nflg
; j
++)
3285 if (!strcmp (pflags
[j
].name
,
3286 arc_flag_operands
[*psflg
].name
))
3307 if (reloc
!= r
->oldreloc
)
3314 if (ret
== BFD_RELOC_UNUSED
)
3315 as_bad (_("Unable to find %s relocation for instruction %s"),
3320 /* All the symbol types that are allowed to be used for
3324 may_relax_expr (expressionS tok
)
3326 /* Check if we have unrelaxable relocs. */
3351 /* Checks if flags are in line with relaxable insn. */
3354 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3355 const struct arc_flags
*pflags
,
3358 unsigned flag_class
,
3363 const struct arc_flag_operand
*flag_opand
;
3364 int i
, counttrue
= 0;
3366 /* Iterate through flags classes. */
3367 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3369 /* Iterate through flags in flag class. */
3370 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3373 flag_opand
= &arc_flag_operands
[flag
];
3374 /* Iterate through flags in ins to compare. */
3375 for (i
= 0; i
< nflgs
; ++i
)
3377 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3388 /* If counttrue == nflgs, then all flags have been found. */
3389 return (counttrue
== nflgs
? TRUE
: FALSE
);
3392 /* Checks if operands are in line with relaxable insn. */
3395 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3396 const expressionS
*tok
,
3399 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3402 while (*operand
!= EMPTY
)
3404 const expressionS
*epr
= &tok
[i
];
3406 if (i
!= 0 && i
>= ntok
)
3412 if (!(epr
->X_op
== O_multiply
3413 || epr
->X_op
== O_divide
3414 || epr
->X_op
== O_modulus
3415 || epr
->X_op
== O_add
3416 || epr
->X_op
== O_subtract
3417 || epr
->X_op
== O_symbol
))
3423 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3427 if (epr
->X_op
!= O_register
)
3432 if (epr
->X_op
!= O_register
)
3435 switch (epr
->X_add_number
)
3437 case 0: case 1: case 2: case 3:
3438 case 12: case 13: case 14: case 15:
3445 case REGISTER_NO_GP
:
3446 if ((epr
->X_op
!= O_register
)
3447 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3452 if (epr
->X_op
!= O_bracket
)
3457 /* Don't understand, bail out. */
3463 operand
= &ins
->operands
[i
];
3466 return (i
== ntok
? TRUE
: FALSE
);
3469 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3472 relax_insn_p (const struct arc_opcode
*opcode
,
3473 const expressionS
*tok
,
3475 const struct arc_flags
*pflags
,
3479 bfd_boolean rv
= FALSE
;
3481 /* Check the relaxation table. */
3482 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3484 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3486 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3487 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3488 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3489 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3492 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3493 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3494 sizeof (expressionS
) * ntok
);
3495 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3496 sizeof (struct arc_flags
) * nflg
);
3497 frag_now
->tc_frag_data
.nflg
= nflg
;
3498 frag_now
->tc_frag_data
.ntok
= ntok
;
3506 /* Turn an opcode description and a set of arguments into
3507 an instruction and a fixup. */
3510 assemble_insn (const struct arc_opcode
*opcode
,
3511 const expressionS
*tok
,
3513 const struct arc_flags
*pflags
,
3515 struct arc_insn
*insn
)
3517 const expressionS
*reloc_exp
= NULL
;
3519 const unsigned char *argidx
;
3522 unsigned char pcrel
= 0;
3523 bfd_boolean needGOTSymbol
;
3524 bfd_boolean has_delay_slot
= FALSE
;
3525 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3527 memset (insn
, 0, sizeof (*insn
));
3528 image
= opcode
->opcode
;
3530 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3531 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3534 /* Handle operands. */
3535 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3537 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3538 const expressionS
*t
= (const expressionS
*) 0;
3540 if ((operand
->flags
& ARC_OPERAND_FAKE
)
3541 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
3544 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3546 /* Duplicate operand, already inserted. */
3558 /* Regardless if we have a reloc or not mark the instruction
3559 limm if it is the case. */
3560 if (operand
->flags
& ARC_OPERAND_LIMM
)
3561 insn
->has_limm
= TRUE
;
3566 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3571 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3573 if (operand
->flags
& ARC_OPERAND_LIMM
)
3574 insn
->limm
= t
->X_add_number
;
3578 /* Ignore brackets. */
3582 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3586 /* Maybe register range. */
3587 if ((t
->X_add_number
== 0)
3588 && contains_register (t
->X_add_symbol
)
3589 && contains_register (t
->X_op_symbol
))
3593 regs
= get_register (t
->X_add_symbol
);
3595 regs
|= get_register (t
->X_op_symbol
);
3596 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3601 /* This operand needs a relocation. */
3602 needGOTSymbol
= FALSE
;
3607 if (opcode
->class == JUMP
)
3608 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3609 _("Unable to use @plt relocatio for insn %s"),
3611 needGOTSymbol
= TRUE
;
3612 reloc
= find_reloc ("plt", opcode
->name
,
3614 operand
->default_reloc
);
3619 needGOTSymbol
= TRUE
;
3620 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3623 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3624 if (ARC_SHORT (opcode
->mask
) || opcode
->class == JUMP
)
3625 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3626 _("Unable to use @pcl relocation for insn %s"),
3630 reloc
= find_reloc ("sda", opcode
->name
,
3632 operand
->default_reloc
);
3636 needGOTSymbol
= TRUE
;
3641 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3644 case O_tpoff9
: /*FIXME! Check for the conditionality of
3646 case O_dtpoff9
: /*FIXME! Check for the conditionality of
3648 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3652 /* Just consider the default relocation. */
3653 reloc
= operand
->default_reloc
;
3657 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
3658 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3665 /* sanity checks. */
3666 reloc_howto_type
*reloc_howto
3667 = bfd_reloc_type_lookup (stdoutput
,
3668 (bfd_reloc_code_real_type
) reloc
);
3669 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
3670 if (reloc_howto
->rightshift
)
3671 reloc_bitsize
-= reloc_howto
->rightshift
;
3672 if (reloc_bitsize
!= operand
->bits
)
3674 as_bad (_("invalid relocation %s for field"),
3675 bfd_get_reloc_code_name (reloc
));
3680 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3681 as_fatal (_("too many fixups"));
3683 struct arc_fixup
*fixup
;
3684 fixup
= &insn
->fixups
[insn
->nfixups
++];
3686 fixup
->reloc
= reloc
;
3687 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
3688 fixup
->pcrel
= pcrel
;
3689 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
3696 for (i
= 0; i
< nflg
; i
++)
3698 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
3700 /* Check if the instruction has a delay slot. */
3701 if (!strcmp (flg_operand
->name
, "d"))
3702 has_delay_slot
= TRUE
;
3704 /* There is an exceptional case when we cannot insert a flag
3705 just as it is. The .T flag must be handled in relation with
3706 the relative address. */
3707 if (!strcmp (flg_operand
->name
, "t")
3708 || !strcmp (flg_operand
->name
, "nt"))
3710 unsigned bitYoperand
= 0;
3711 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3712 if (!strcmp (flg_operand
->name
, "t"))
3713 if (!strcmp (opcode
->name
, "bbit0")
3714 || !strcmp (opcode
->name
, "bbit1"))
3715 bitYoperand
= arc_NToperand
;
3717 bitYoperand
= arc_Toperand
;
3719 if (!strcmp (opcode
->name
, "bbit0")
3720 || !strcmp (opcode
->name
, "bbit1"))
3721 bitYoperand
= arc_Toperand
;
3723 bitYoperand
= arc_NToperand
;
3725 gas_assert (reloc_exp
!= NULL
);
3726 if (reloc_exp
->X_op
== O_constant
)
3728 /* Check if we have a constant and solved it
3730 offsetT val
= reloc_exp
->X_add_number
;
3731 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
3736 struct arc_fixup
*fixup
;
3738 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
3739 as_fatal (_("too many fixups"));
3741 fixup
= &insn
->fixups
[insn
->nfixups
++];
3742 fixup
->exp
= *reloc_exp
;
3743 fixup
->reloc
= -bitYoperand
;
3744 fixup
->pcrel
= pcrel
;
3745 fixup
->islong
= FALSE
;
3749 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
3750 << flg_operand
->shift
;
3753 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
3755 /* Short instruction? */
3756 insn
->short_insn
= ARC_SHORT (opcode
->mask
) ? TRUE
: FALSE
;
3760 /* Update last insn status. */
3761 arc_last_insns
[1] = arc_last_insns
[0];
3762 arc_last_insns
[0].opcode
= opcode
;
3763 arc_last_insns
[0].has_limm
= insn
->has_limm
;
3764 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
3766 /* Check if the current instruction is legally used. */
3767 if (arc_last_insns
[1].has_delay_slot
3768 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3769 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3770 _("A jump/branch instruction in delay slot."));
3774 arc_handle_align (fragS
* fragP
)
3776 if ((fragP
)->fr_type
== rs_align_code
)
3778 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
3779 valueT count
= ((fragP
)->fr_next
->fr_address
3780 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
3782 (fragP
)->fr_var
= 2;
3784 if (count
& 1)/* Padding in the gap till the next 2-byte
3785 boundary with 0s. */
3790 /* Writing nop_s. */
3791 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
3795 /* Here we decide which fixups can be adjusted to make them relative
3796 to the beginning of the section instead of the symbol. Basically
3797 we need to make sure that the dynamic relocations are done
3798 correctly, so in some cases we force the original symbol to be
3802 tc_arc_fix_adjustable (fixS
*fixP
)
3805 /* Prevent all adjustments to global symbols. */
3806 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
3808 if (S_IS_WEAK (fixP
->fx_addsy
))
3811 /* Adjust_reloc_syms doesn't know about the GOT. */
3812 switch (fixP
->fx_r_type
)
3814 case BFD_RELOC_ARC_GOTPC32
:
3815 case BFD_RELOC_ARC_PLT32
:
3816 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3817 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3818 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3819 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3829 /* Compute the reloc type of an expression EXP. */
3832 arc_check_reloc (expressionS
*exp
,
3833 bfd_reloc_code_real_type
*r_type_p
)
3835 if (*r_type_p
== BFD_RELOC_32
3836 && exp
->X_op
== O_subtract
3837 && exp
->X_op_symbol
!= NULL
3838 && exp
->X_op_symbol
->bsym
->section
== now_seg
)
3839 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
3843 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
3846 arc_cons_fix_new (fragS
*frag
,
3850 bfd_reloc_code_real_type r_type
)
3852 r_type
= BFD_RELOC_UNUSED
;
3857 r_type
= BFD_RELOC_8
;
3861 r_type
= BFD_RELOC_16
;
3865 r_type
= BFD_RELOC_24
;
3869 r_type
= BFD_RELOC_32
;
3870 arc_check_reloc (exp
, &r_type
);
3874 r_type
= BFD_RELOC_64
;
3878 as_bad (_("unsupported BFD relocation size %u"), size
);
3879 r_type
= BFD_RELOC_UNUSED
;
3882 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
3885 /* The actual routine that checks the ZOL conditions. */
3888 check_zol (symbolS
*s
)
3890 switch (arc_mach_type
)
3892 case bfd_mach_arc_arcv2
:
3893 if (arc_target
& ARC_OPCODE_ARCv2EM
)
3896 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
3897 || arc_last_insns
[1].has_delay_slot
)
3898 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
3902 case bfd_mach_arc_arc600
:
3904 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
3905 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
3908 if (arc_last_insns
[0].has_limm
3909 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
3910 as_bad (_("A jump instruction with long immediate detected at the \
3911 end of the ZOL label @%s"), S_GET_NAME (s
));
3914 case bfd_mach_arc_nps400
:
3915 case bfd_mach_arc_arc700
:
3916 if (arc_last_insns
[0].has_delay_slot
)
3917 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
3926 /* If ZOL end check the last two instruction for illegals. */
3928 arc_frob_label (symbolS
* sym
)
3930 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
3933 dwarf2_emit_label (sym
);
3936 /* Used because generic relaxation assumes a pc-rel value whilst we
3937 also relax instructions that use an absolute value resolved out of
3938 relative values (if that makes any sense). An example: 'add r1,
3939 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
3940 but if they're in the same section we can subtract the section
3941 offset relocation which ends up in a resolved value. So if @.L2 is
3942 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
3943 .text + 0x40 = 0x10. */
3945 arc_pcrel_adjust (fragS
*fragP
)
3947 if (!fragP
->tc_frag_data
.pcrel
)
3948 return fragP
->fr_address
+ fragP
->fr_fix
;
3953 /* Initialize the DWARF-2 unwind information for this procedure. */
3956 tc_arc_frame_initial_instructions (void)
3958 /* Stack pointer is register 28. */
3959 cfi_add_CFA_def_cfa_register (28);
3963 tc_arc_regname_to_dw2regnum (char *regname
)
3967 sym
= hash_find (arc_reg_hash
, regname
);
3969 return S_GET_VALUE (sym
);
3974 /* Adjust the symbol table. Delete found AUX register symbols. */
3977 arc_adjust_symtab (void)
3981 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
3983 /* I've created a symbol during parsing process. Now, remove
3984 the symbol as it is found to be an AUX register. */
3985 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
3986 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
3989 /* Now do generic ELF adjustments. */
3990 elf_adjust_symtab ();
3994 tokenize_extinsn (extInstruction_t
*einsn
)
3998 unsigned char major_opcode
;
3999 unsigned char sub_opcode
;
4000 unsigned char syntax_class
= 0;
4001 unsigned char syntax_class_modifiers
= 0;
4002 unsigned char suffix_class
= 0;
4007 /* 1st: get instruction name. */
4008 p
= input_line_pointer
;
4009 c
= get_symbol_name (&p
);
4011 insn_name
= xstrdup (p
);
4012 restore_line_pointer (c
);
4014 /* 2nd: get major opcode. */
4015 if (*input_line_pointer
!= ',')
4017 as_bad (_("expected comma after instruction name"));
4018 ignore_rest_of_line ();
4021 input_line_pointer
++;
4022 major_opcode
= get_absolute_expression ();
4024 /* 3rd: get sub-opcode. */
4027 if (*input_line_pointer
!= ',')
4029 as_bad (_("expected comma after major opcode"));
4030 ignore_rest_of_line ();
4033 input_line_pointer
++;
4034 sub_opcode
= get_absolute_expression ();
4036 /* 4th: get suffix class. */
4039 if (*input_line_pointer
!= ',')
4041 as_bad ("expected comma after sub opcode");
4042 ignore_rest_of_line ();
4045 input_line_pointer
++;
4051 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4053 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4054 suffixclass
[i
].len
))
4056 suffix_class
|= suffixclass
[i
].class;
4057 input_line_pointer
+= suffixclass
[i
].len
;
4062 if (i
== ARRAY_SIZE (suffixclass
))
4064 as_bad ("invalid suffix class");
4065 ignore_rest_of_line ();
4071 if (*input_line_pointer
== '|')
4072 input_line_pointer
++;
4077 /* 5th: get syntax class and syntax class modifiers. */
4078 if (*input_line_pointer
!= ',')
4080 as_bad ("expected comma after suffix class");
4081 ignore_rest_of_line ();
4084 input_line_pointer
++;
4090 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4092 if (!strncmp (syntaxclassmod
[i
].name
,
4094 syntaxclassmod
[i
].len
))
4096 syntax_class_modifiers
|= syntaxclassmod
[i
].class;
4097 input_line_pointer
+= syntaxclassmod
[i
].len
;
4102 if (i
== ARRAY_SIZE (syntaxclassmod
))
4104 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4106 if (!strncmp (syntaxclass
[i
].name
,
4108 syntaxclass
[i
].len
))
4110 syntax_class
|= syntaxclass
[i
].class;
4111 input_line_pointer
+= syntaxclass
[i
].len
;
4116 if (i
== ARRAY_SIZE (syntaxclass
))
4118 as_bad ("missing syntax class");
4119 ignore_rest_of_line ();
4126 if (*input_line_pointer
== '|')
4127 input_line_pointer
++;
4132 demand_empty_rest_of_line ();
4134 einsn
->name
= insn_name
;
4135 einsn
->major
= major_opcode
;
4136 einsn
->minor
= sub_opcode
;
4137 einsn
->syntax
= syntax_class
;
4138 einsn
->modsyn
= syntax_class_modifiers
;
4139 einsn
->suffix
= suffix_class
;
4140 einsn
->flags
= syntax_class
4141 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4144 /* Generate an extension section. */
4147 arc_set_ext_seg (void)
4149 if (!arcext_section
)
4151 arcext_section
= subseg_new (".arcextmap", 0);
4152 bfd_set_section_flags (stdoutput
, arcext_section
,
4153 SEC_READONLY
| SEC_HAS_CONTENTS
);
4156 subseg_set (arcext_section
, 0);
4160 /* Create an extension instruction description in the arc extension
4161 section of the output file.
4162 The structure for an instruction is like this:
4163 [0]: Length of the record.
4164 [1]: Type of the record.
4168 [4]: Syntax (flags).
4169 [5]+ Name instruction.
4171 The sequence is terminated by an empty entry. */
4174 create_extinst_section (extInstruction_t
*einsn
)
4177 segT old_sec
= now_seg
;
4178 int old_subsec
= now_subseg
;
4180 int name_len
= strlen (einsn
->name
);
4185 *p
= 5 + name_len
+ 1;
4187 *p
= EXT_INSTRUCTION
;
4194 p
= frag_more (name_len
+ 1);
4195 strcpy (p
, einsn
->name
);
4197 subseg_set (old_sec
, old_subsec
);
4200 /* Handler .extinstruction pseudo-op. */
4203 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4205 extInstruction_t einsn
;
4206 struct arc_opcode
*arc_ext_opcodes
;
4207 const char *errmsg
= NULL
;
4208 unsigned char moplow
, mophigh
;
4210 memset (&einsn
, 0, sizeof (einsn
));
4211 tokenize_extinsn (&einsn
);
4213 /* Check if the name is already used. */
4214 if (arc_find_opcode (einsn
.name
))
4215 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4217 /* Check the opcode ranges. */
4219 mophigh
= (arc_target
& (ARC_OPCODE_ARCv2EM
4220 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4222 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4223 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4225 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4226 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4227 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4229 switch (einsn
.syntax
& (ARC_SYNTAX_3OP
| ARC_SYNTAX_2OP
))
4231 case ARC_SYNTAX_3OP
:
4232 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4233 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4235 case ARC_SYNTAX_2OP
:
4236 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4237 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4243 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, arc_target
, &errmsg
);
4244 if (arc_ext_opcodes
== NULL
)
4247 as_fatal ("%s", errmsg
);
4249 as_fatal (_("Couldn't generate extension instruction opcodes"));
4252 as_warn ("%s", errmsg
);
4254 /* Insert the extension instruction. */
4255 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4257 create_extinst_section (&einsn
);
4261 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4267 int number
, imode
= 0;
4268 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4269 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4270 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4272 /* 1st: get register name. */
4274 p
= input_line_pointer
;
4275 c
= get_symbol_name (&p
);
4278 restore_line_pointer (c
);
4280 /* 2nd: get register number. */
4283 if (*input_line_pointer
!= ',')
4285 as_bad (_("expected comma after register name"));
4286 ignore_rest_of_line ();
4290 input_line_pointer
++;
4291 number
= get_absolute_expression ();
4295 as_bad (_("negative operand number %d"), number
);
4296 ignore_rest_of_line ();
4303 /* 3rd: get register mode. */
4306 if (*input_line_pointer
!= ',')
4308 as_bad (_("expected comma after register number"));
4309 ignore_rest_of_line ();
4314 input_line_pointer
++;
4315 mode
= input_line_pointer
;
4317 if (!strncmp (mode
, "r|w", 3))
4320 input_line_pointer
+= 3;
4322 else if (!strncmp (mode
, "r", 1))
4324 imode
= ARC_REGISTER_READONLY
;
4325 input_line_pointer
+= 1;
4327 else if (strncmp (mode
, "w", 1))
4329 as_bad (_("invalid mode"));
4330 ignore_rest_of_line ();
4336 imode
= ARC_REGISTER_WRITEONLY
;
4337 input_line_pointer
+= 1;
4343 /* 4th: get core register shortcut. */
4345 if (*input_line_pointer
!= ',')
4347 as_bad (_("expected comma after register mode"));
4348 ignore_rest_of_line ();
4353 input_line_pointer
++;
4355 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4357 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4358 input_line_pointer
+= 15;
4360 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4362 as_bad (_("shortcut designator invalid"));
4363 ignore_rest_of_line ();
4369 input_line_pointer
+= 12;
4372 demand_empty_rest_of_line ();
4375 ereg
->number
= number
;
4376 ereg
->imode
= imode
;
4379 /* Create an extension register/condition description in the arc
4380 extension section of the output file.
4382 The structure for an instruction is like this:
4383 [0]: Length of the record.
4384 [1]: Type of the record.
4386 For core regs and condition codes:
4390 For auxilirary registers:
4394 The sequence is terminated by an empty entry. */
4397 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4399 segT old_sec
= now_seg
;
4400 int old_subsec
= now_subseg
;
4402 int name_len
= strlen (ereg
->name
);
4409 case EXT_CORE_REGISTER
:
4411 *p
= 3 + name_len
+ 1;
4417 case EXT_AUX_REGISTER
:
4419 *p
= 6 + name_len
+ 1;
4421 *p
= EXT_AUX_REGISTER
;
4423 *p
= (ereg
->number
>> 24) & 0xff;
4425 *p
= (ereg
->number
>> 16) & 0xff;
4427 *p
= (ereg
->number
>> 8) & 0xff;
4429 *p
= (ereg
->number
) & 0xff;
4435 p
= frag_more (name_len
+ 1);
4436 strcpy (p
, ereg
->name
);
4438 subseg_set (old_sec
, old_subsec
);
4441 /* Handler .extCoreRegister pseudo-op. */
4444 arc_extcorereg (int opertype
)
4447 struct arc_aux_reg
*auxr
;
4449 struct arc_flag_operand
*ccode
;
4451 memset (&ereg
, 0, sizeof (ereg
));
4452 tokenize_extregister (&ereg
, opertype
);
4456 case EXT_CORE_REGISTER
:
4457 /* Core register. */
4458 if (ereg
.number
> 60)
4459 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4461 declare_register (ereg
.name
, ereg
.number
);
4463 case EXT_AUX_REGISTER
:
4464 /* Auxiliary register. */
4465 auxr
= xmalloc (sizeof (struct arc_aux_reg
));
4466 auxr
->name
= ereg
.name
;
4467 auxr
->cpu
= arc_target
;
4468 auxr
->subclass
= NONE
;
4469 auxr
->address
= ereg
.number
;
4470 retval
= hash_insert (arc_aux_hash
, auxr
->name
, (void *) auxr
);
4472 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4473 auxr
->name
, retval
);
4476 /* Condition code. */
4477 if (ereg
.number
> 31)
4478 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4480 ext_condcode
.size
++;
4481 ext_condcode
.arc_ext_condcode
=
4482 xrealloc (ext_condcode
.arc_ext_condcode
,
4483 (ext_condcode
.size
+ 1) * sizeof (struct arc_flag_operand
));
4484 if (ext_condcode
.arc_ext_condcode
== NULL
)
4485 as_fatal (_("Virtual memory exhausted"));
4487 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4488 ccode
->name
= ereg
.name
;
4489 ccode
->code
= ereg
.number
;
4492 ccode
->favail
= 0; /* not used. */
4494 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4497 as_bad (_("Unknown extension"));
4500 create_extcore_section (&ereg
, opertype
);
4504 eval: (c-set-style "gnu")