1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
201 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
202 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
203 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
204 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
206 static const arm_feature_set arm_arch_any
= ARM_ANY
;
207 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
209 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
212 static const arm_feature_set arm_cext_iwmmxt2
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
214 static const arm_feature_set arm_cext_iwmmxt
=
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
216 static const arm_feature_set arm_cext_xscale
=
217 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
218 static const arm_feature_set arm_cext_maverick
=
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
220 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
221 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
222 static const arm_feature_set fpu_vfp_ext_v1xd
=
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
224 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
225 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
226 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
227 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
228 static const arm_feature_set fpu_vfp_ext_d32
=
229 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
230 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
232 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
233 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
234 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
235 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static int mfloat_abi_opt
= -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name
[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu
.core
== arm_arch_none
.core
248 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
253 static int meabi_flags
= EABI_DEFAULT
;
255 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
258 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
263 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS
* GOT_symbol
;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode
= 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER
= 0x00,
286 IMPLICIT_IT_MODE_ARM
= 0x01,
287 IMPLICIT_IT_MODE_THUMB
= 0x02,
288 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
290 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax
= FALSE
;
330 enum neon_el_type type
;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN
/* The IT insn has been parsed. */
357 unsigned long instruction
;
361 /* "uncond_value" is set to the value in place of the conditional field in
362 unconditional versions of the instruction, or -1 if nothing is
365 struct neon_type vectype
;
366 /* This does not indicate an actual NEON instruction, only that
367 the mnemonic accepts neon-style type suffixes. */
369 /* Set to the opcode if the instruction needs relaxation.
370 Zero if the instruction is not relaxed. */
374 bfd_reloc_code_real_type type
;
379 enum it_instruction_type it_insn_type
;
385 struct neon_type_el vectype
;
386 unsigned present
: 1; /* Operand present. */
387 unsigned isreg
: 1; /* Operand was a register. */
388 unsigned immisreg
: 1; /* .imm field is a second register. */
389 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
390 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
391 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
392 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
393 instructions. This allows us to disambiguate ARM <-> vector insns. */
394 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
395 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
396 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
397 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
398 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
399 unsigned writeback
: 1; /* Operand has trailing ! */
400 unsigned preind
: 1; /* Preindexed address. */
401 unsigned postind
: 1; /* Postindexed address. */
402 unsigned negative
: 1; /* Index register was negated. */
403 unsigned shifted
: 1; /* Shift applied to operation. */
404 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
408 static struct arm_it inst
;
410 #define NUM_FLOAT_VALS 8
412 const char * fp_const
[] =
414 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
417 /* Number of littlenums required to hold an extended precision number. */
418 #define MAX_LITTLENUMS 6
420 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
430 #define CP_T_X 0x00008000
431 #define CP_T_Y 0x00400000
433 #define CONDS_BIT 0x00100000
434 #define LOAD_BIT 0x00100000
436 #define DOUBLE_LOAD_FLAG 0x00000001
440 const char * template_name
;
444 #define COND_ALWAYS 0xE
448 const char * template_name
;
452 struct asm_barrier_opt
454 const char * template_name
;
458 /* The bit that distinguishes CPSR and SPSR. */
459 #define SPSR_BIT (1 << 22)
461 /* The individual PSR flag bits. */
462 #define PSR_c (1 << 16)
463 #define PSR_x (1 << 17)
464 #define PSR_s (1 << 18)
465 #define PSR_f (1 << 19)
470 bfd_reloc_code_real_type reloc
;
475 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
476 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
481 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
484 /* Bits for DEFINED field in neon_typed_alias. */
485 #define NTA_HASTYPE 1
486 #define NTA_HASINDEX 2
488 struct neon_typed_alias
490 unsigned char defined
;
492 struct neon_type_el eltype
;
495 /* ARM register categories. This includes coprocessor numbers and various
496 architecture extensions' registers. */
523 /* Structure for a hash table entry for a register.
524 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
525 information which states whether a vector type or index is specified (for a
526 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
532 unsigned char builtin
;
533 struct neon_typed_alias
* neon
;
536 /* Diagnostics used when we don't get a register of the expected type. */
537 const char * const reg_expected_msgs
[] =
539 N_("ARM register expected"),
540 N_("bad or missing co-processor number"),
541 N_("co-processor register expected"),
542 N_("FPA register expected"),
543 N_("VFP single precision register expected"),
544 N_("VFP/Neon double precision register expected"),
545 N_("Neon quad precision register expected"),
546 N_("VFP single or double precision register expected"),
547 N_("Neon double or quad precision register expected"),
548 N_("VFP single, double or Neon quad precision register expected"),
549 N_("VFP system register expected"),
550 N_("Maverick MVF register expected"),
551 N_("Maverick MVD register expected"),
552 N_("Maverick MVFX register expected"),
553 N_("Maverick MVDX register expected"),
554 N_("Maverick MVAX register expected"),
555 N_("Maverick DSPSC register expected"),
556 N_("iWMMXt data register expected"),
557 N_("iWMMXt control register expected"),
558 N_("iWMMXt scalar register expected"),
559 N_("XScale accumulator register expected"),
562 /* Some well known registers that we refer to directly elsewhere. */
567 /* ARM instructions take 4bytes in the object file, Thumb instructions
573 /* Basic string to match. */
574 const char * template_name
;
576 /* Parameters to instruction. */
577 unsigned int operands
[8];
579 /* Conditional tag - see opcode_lookup. */
580 unsigned int tag
: 4;
582 /* Basic instruction code. */
583 unsigned int avalue
: 28;
585 /* Thumb-format instruction code. */
588 /* Which architecture variant provides this instruction. */
589 const arm_feature_set
* avariant
;
590 const arm_feature_set
* tvariant
;
592 /* Function to call to encode instruction in ARM format. */
593 void (* aencode
) (void);
595 /* Function to call to encode instruction in Thumb format. */
596 void (* tencode
) (void);
599 /* Defines for various bits that we will want to toggle. */
600 #define INST_IMMEDIATE 0x02000000
601 #define OFFSET_REG 0x02000000
602 #define HWOFFSET_IMM 0x00400000
603 #define SHIFT_BY_REG 0x00000010
604 #define PRE_INDEX 0x01000000
605 #define INDEX_UP 0x00800000
606 #define WRITE_BACK 0x00200000
607 #define LDM_TYPE_2_OR_3 0x00400000
608 #define CPSI_MMOD 0x00020000
610 #define LITERAL_MASK 0xf000f000
611 #define OPCODE_MASK 0xfe1fffff
612 #define V4_STR_BIT 0x00000020
614 #define T2_SUBS_PC_LR 0xf3de8f00
616 #define DATA_OP_SHIFT 21
618 #define T2_OPCODE_MASK 0xfe1fffff
619 #define T2_DATA_OP_SHIFT 21
621 /* Codes to distinguish the arithmetic instructions. */
632 #define OPCODE_CMP 10
633 #define OPCODE_CMN 11
634 #define OPCODE_ORR 12
635 #define OPCODE_MOV 13
636 #define OPCODE_BIC 14
637 #define OPCODE_MVN 15
639 #define T2_OPCODE_AND 0
640 #define T2_OPCODE_BIC 1
641 #define T2_OPCODE_ORR 2
642 #define T2_OPCODE_ORN 3
643 #define T2_OPCODE_EOR 4
644 #define T2_OPCODE_ADD 8
645 #define T2_OPCODE_ADC 10
646 #define T2_OPCODE_SBC 11
647 #define T2_OPCODE_SUB 13
648 #define T2_OPCODE_RSB 14
650 #define T_OPCODE_MUL 0x4340
651 #define T_OPCODE_TST 0x4200
652 #define T_OPCODE_CMN 0x42c0
653 #define T_OPCODE_NEG 0x4240
654 #define T_OPCODE_MVN 0x43c0
656 #define T_OPCODE_ADD_R3 0x1800
657 #define T_OPCODE_SUB_R3 0x1a00
658 #define T_OPCODE_ADD_HI 0x4400
659 #define T_OPCODE_ADD_ST 0xb000
660 #define T_OPCODE_SUB_ST 0xb080
661 #define T_OPCODE_ADD_SP 0xa800
662 #define T_OPCODE_ADD_PC 0xa000
663 #define T_OPCODE_ADD_I8 0x3000
664 #define T_OPCODE_SUB_I8 0x3800
665 #define T_OPCODE_ADD_I3 0x1c00
666 #define T_OPCODE_SUB_I3 0x1e00
668 #define T_OPCODE_ASR_R 0x4100
669 #define T_OPCODE_LSL_R 0x4080
670 #define T_OPCODE_LSR_R 0x40c0
671 #define T_OPCODE_ROR_R 0x41c0
672 #define T_OPCODE_ASR_I 0x1000
673 #define T_OPCODE_LSL_I 0x0000
674 #define T_OPCODE_LSR_I 0x0800
676 #define T_OPCODE_MOV_I8 0x2000
677 #define T_OPCODE_CMP_I8 0x2800
678 #define T_OPCODE_CMP_LR 0x4280
679 #define T_OPCODE_MOV_HR 0x4600
680 #define T_OPCODE_CMP_HR 0x4500
682 #define T_OPCODE_LDR_PC 0x4800
683 #define T_OPCODE_LDR_SP 0x9800
684 #define T_OPCODE_STR_SP 0x9000
685 #define T_OPCODE_LDR_IW 0x6800
686 #define T_OPCODE_STR_IW 0x6000
687 #define T_OPCODE_LDR_IH 0x8800
688 #define T_OPCODE_STR_IH 0x8000
689 #define T_OPCODE_LDR_IB 0x7800
690 #define T_OPCODE_STR_IB 0x7000
691 #define T_OPCODE_LDR_RW 0x5800
692 #define T_OPCODE_STR_RW 0x5000
693 #define T_OPCODE_LDR_RH 0x5a00
694 #define T_OPCODE_STR_RH 0x5200
695 #define T_OPCODE_LDR_RB 0x5c00
696 #define T_OPCODE_STR_RB 0x5400
698 #define T_OPCODE_PUSH 0xb400
699 #define T_OPCODE_POP 0xbc00
701 #define T_OPCODE_BRANCH 0xe000
703 #define THUMB_SIZE 2 /* Size of thumb instruction. */
704 #define THUMB_PP_PC_LR 0x0100
705 #define THUMB_LOAD_BIT 0x0800
706 #define THUMB2_LOAD_BIT 0x00100000
708 #define BAD_ARGS _("bad arguments to instruction")
709 #define BAD_SP _("r13 not allowed here")
710 #define BAD_PC _("r15 not allowed here")
711 #define BAD_COND _("instruction cannot be conditional")
712 #define BAD_OVERLAP _("registers may not be the same")
713 #define BAD_HIREG _("lo register required")
714 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
715 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
716 #define BAD_BRANCH _("branch must be last instruction in IT block")
717 #define BAD_NOT_IT _("instruction not allowed in IT block")
718 #define BAD_FPU _("selected FPU does not support instruction")
719 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
720 #define BAD_IT_COND _("incorrect condition in IT block")
721 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
722 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
723 #define BAD_PC_ADDRESSING \
724 _("cannot use register index with PC-relative addressing")
725 #define BAD_PC_WRITEBACK \
726 _("cannot use writeback with PC-relative addressing")
728 static struct hash_control
* arm_ops_hsh
;
729 static struct hash_control
* arm_cond_hsh
;
730 static struct hash_control
* arm_shift_hsh
;
731 static struct hash_control
* arm_psr_hsh
;
732 static struct hash_control
* arm_v7m_psr_hsh
;
733 static struct hash_control
* arm_reg_hsh
;
734 static struct hash_control
* arm_reloc_hsh
;
735 static struct hash_control
* arm_barrier_opt_hsh
;
737 /* Stuff needed to resolve the label ambiguity
746 symbolS
* last_label_seen
;
747 static int label_is_thumb_function_name
= FALSE
;
749 /* Literal pool structure. Held on a per-section
750 and per-sub-section basis. */
752 #define MAX_LITERAL_POOL_SIZE 1024
753 typedef struct literal_pool
755 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
756 unsigned int next_free_entry
;
761 struct literal_pool
* next
;
764 /* Pointer to a linked list of literal pools. */
765 literal_pool
* list_of_pools
= NULL
;
768 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
770 static struct current_it now_it
;
774 now_it_compatible (int cond
)
776 return (cond
& ~1) == (now_it
.cc
& ~1);
780 conditional_insn (void)
782 return inst
.cond
!= COND_ALWAYS
;
785 static int in_it_block (void);
787 static int handle_it_state (void);
789 static void force_automatic_it_block_close (void);
791 static void it_fsm_post_encode (void);
793 #define set_it_insn_type(type) \
796 inst.it_insn_type = type; \
797 if (handle_it_state () == FAIL) \
802 #define set_it_insn_type_nonvoid(type, failret) \
805 inst.it_insn_type = type; \
806 if (handle_it_state () == FAIL) \
811 #define set_it_insn_type_last() \
814 if (inst.cond == COND_ALWAYS) \
815 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
817 set_it_insn_type (INSIDE_IT_LAST_INSN); \
823 /* This array holds the chars that always start a comment. If the
824 pre-processor is disabled, these aren't very useful. */
825 const char comment_chars
[] = "@";
827 /* This array holds the chars that only start a comment at the beginning of
828 a line. If the line seems to have the form '# 123 filename'
829 .line and .file directives will appear in the pre-processed output. */
830 /* Note that input_file.c hand checks for '#' at the beginning of the
831 first line of the input file. This is because the compiler outputs
832 #NO_APP at the beginning of its output. */
833 /* Also note that comments like this one will always work. */
834 const char line_comment_chars
[] = "#";
836 const char line_separator_chars
[] = ";";
838 /* Chars that can be used to separate mant
839 from exp in floating point numbers. */
840 const char EXP_CHARS
[] = "eE";
842 /* Chars that mean this number is a floating point constant. */
846 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
848 /* Prefix characters that indicate the start of an immediate
850 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
852 /* Separator character handling. */
854 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
857 skip_past_char (char ** str
, char c
)
868 #define skip_past_comma(str) skip_past_char (str, ',')
870 /* Arithmetic expressions (possibly involving symbols). */
872 /* Return TRUE if anything in the expression is a bignum. */
875 walk_no_bignums (symbolS
* sp
)
877 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
880 if (symbol_get_value_expression (sp
)->X_add_symbol
)
882 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
883 || (symbol_get_value_expression (sp
)->X_op_symbol
884 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
890 static int in_my_get_expression
= 0;
892 /* Third argument to my_get_expression. */
893 #define GE_NO_PREFIX 0
894 #define GE_IMM_PREFIX 1
895 #define GE_OPT_PREFIX 2
896 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
897 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
898 #define GE_OPT_PREFIX_BIG 3
901 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
906 /* In unified syntax, all prefixes are optional. */
908 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
913 case GE_NO_PREFIX
: break;
915 if (!is_immediate_prefix (**str
))
917 inst
.error
= _("immediate expression requires a # prefix");
923 case GE_OPT_PREFIX_BIG
:
924 if (is_immediate_prefix (**str
))
930 memset (ep
, 0, sizeof (expressionS
));
932 save_in
= input_line_pointer
;
933 input_line_pointer
= *str
;
934 in_my_get_expression
= 1;
935 seg
= expression (ep
);
936 in_my_get_expression
= 0;
938 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
940 /* We found a bad or missing expression in md_operand(). */
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
943 if (inst
.error
== NULL
)
944 inst
.error
= (ep
->X_op
== O_absent
945 ? _("missing expression") :_("bad expression"));
950 if (seg
!= absolute_section
951 && seg
!= text_section
952 && seg
!= data_section
953 && seg
!= bss_section
954 && seg
!= undefined_section
)
956 inst
.error
= _("bad segment");
957 *str
= input_line_pointer
;
958 input_line_pointer
= save_in
;
965 /* Get rid of any bignums now, so that we don't generate an error for which
966 we can't establish a line number later on. Big numbers are never valid
967 in instructions, which is where this routine is always called. */
968 if (prefix_mode
!= GE_OPT_PREFIX_BIG
969 && (ep
->X_op
== O_big
971 && (walk_no_bignums (ep
->X_add_symbol
)
973 && walk_no_bignums (ep
->X_op_symbol
))))))
975 inst
.error
= _("invalid constant");
976 *str
= input_line_pointer
;
977 input_line_pointer
= save_in
;
981 *str
= input_line_pointer
;
982 input_line_pointer
= save_in
;
986 /* Turn a string in input_line_pointer into a floating point constant
987 of type TYPE, and store the appropriate bytes in *LITP. The number
988 of LITTLENUMS emitted is stored in *SIZEP. An error message is
989 returned, or NULL on OK.
991 Note that fp constants aren't represent in the normal way on the ARM.
992 In big endian mode, things are as expected. However, in little endian
993 mode fp constants are big-endian word-wise, and little-endian byte-wise
994 within the words. For example, (double) 1.1 in big endian mode is
995 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
996 the byte sequence 99 99 f1 3f 9a 99 99 99.
998 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1001 md_atof (int type
, char * litP
, int * sizeP
)
1004 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1036 return _("Unrecognized or unsupported floating point constant");
1039 t
= atof_ieee (input_line_pointer
, type
, words
);
1041 input_line_pointer
= t
;
1042 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1044 if (target_big_endian
)
1046 for (i
= 0; i
< prec
; i
++)
1048 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1049 litP
+= sizeof (LITTLENUM_TYPE
);
1054 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1055 for (i
= prec
- 1; i
>= 0; i
--)
1057 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1058 litP
+= sizeof (LITTLENUM_TYPE
);
1061 /* For a 4 byte float the order of elements in `words' is 1 0.
1062 For an 8 byte float the order is 1 0 3 2. */
1063 for (i
= 0; i
< prec
; i
+= 2)
1065 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1066 sizeof (LITTLENUM_TYPE
));
1067 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1068 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1069 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1076 /* We handle all bad expressions here, so that we can report the faulty
1077 instruction in the error message. */
1079 md_operand (expressionS
* exp
)
1081 if (in_my_get_expression
)
1082 exp
->X_op
= O_illegal
;
1085 /* Immediate values. */
1087 /* Generic immediate-value read function for use in directives.
1088 Accepts anything that 'expression' can fold to a constant.
1089 *val receives the number. */
1092 immediate_for_directive (int *val
)
1095 exp
.X_op
= O_illegal
;
1097 if (is_immediate_prefix (*input_line_pointer
))
1099 input_line_pointer
++;
1103 if (exp
.X_op
!= O_constant
)
1105 as_bad (_("expected #constant"));
1106 ignore_rest_of_line ();
1109 *val
= exp
.X_add_number
;
1114 /* Register parsing. */
1116 /* Generic register parser. CCP points to what should be the
1117 beginning of a register name. If it is indeed a valid register
1118 name, advance CCP over it and return the reg_entry structure;
1119 otherwise return NULL. Does not issue diagnostics. */
1121 static struct reg_entry
*
1122 arm_reg_parse_multi (char **ccp
)
1126 struct reg_entry
*reg
;
1128 #ifdef REGISTER_PREFIX
1129 if (*start
!= REGISTER_PREFIX
)
1133 #ifdef OPTIONAL_REGISTER_PREFIX
1134 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1139 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1144 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1146 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1156 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1157 enum arm_reg_type type
)
1159 /* Alternative syntaxes are accepted for a few register classes. */
1166 /* Generic coprocessor register names are allowed for these. */
1167 if (reg
&& reg
->type
== REG_TYPE_CN
)
1172 /* For backward compatibility, a bare number is valid here. */
1174 unsigned long processor
= strtoul (start
, ccp
, 10);
1175 if (*ccp
!= start
&& processor
<= 15)
1179 case REG_TYPE_MMXWC
:
1180 /* WC includes WCG. ??? I'm not sure this is true for all
1181 instructions that take WC registers. */
1182 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1193 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1194 return value is the register number or FAIL. */
1197 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1200 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1203 /* Do not allow a scalar (reg+index) to parse as a register. */
1204 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1207 if (reg
&& reg
->type
== type
)
1210 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1217 /* Parse a Neon type specifier. *STR should point at the leading '.'
1218 character. Does no verification at this stage that the type fits the opcode
1225 Can all be legally parsed by this function.
1227 Fills in neon_type struct pointer with parsed information, and updates STR
1228 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1229 type, FAIL if not. */
1232 parse_neon_type (struct neon_type
*type
, char **str
)
1239 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1241 enum neon_el_type thistype
= NT_untyped
;
1242 unsigned thissize
= -1u;
1249 /* Just a size without an explicit type. */
1253 switch (TOLOWER (*ptr
))
1255 case 'i': thistype
= NT_integer
; break;
1256 case 'f': thistype
= NT_float
; break;
1257 case 'p': thistype
= NT_poly
; break;
1258 case 's': thistype
= NT_signed
; break;
1259 case 'u': thistype
= NT_unsigned
; break;
1261 thistype
= NT_float
;
1266 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1272 /* .f is an abbreviation for .f32. */
1273 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1278 thissize
= strtoul (ptr
, &ptr
, 10);
1280 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1283 as_bad (_("bad size %d in type specifier"), thissize
);
1291 type
->el
[type
->elems
].type
= thistype
;
1292 type
->el
[type
->elems
].size
= thissize
;
1297 /* Empty/missing type is not a successful parse. */
1298 if (type
->elems
== 0)
1306 /* Errors may be set multiple times during parsing or bit encoding
1307 (particularly in the Neon bits), but usually the earliest error which is set
1308 will be the most meaningful. Avoid overwriting it with later (cascading)
1309 errors by calling this function. */
1312 first_error (const char *err
)
1318 /* Parse a single type, e.g. ".s32", leading period included. */
1320 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1323 struct neon_type optype
;
1327 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1329 if (optype
.elems
== 1)
1330 *vectype
= optype
.el
[0];
1333 first_error (_("only one type should be specified for operand"));
1339 first_error (_("vector type expected"));
1351 /* Special meanings for indices (which have a range of 0-7), which will fit into
1354 #define NEON_ALL_LANES 15
1355 #define NEON_INTERLEAVE_LANES 14
1357 /* Parse either a register or a scalar, with an optional type. Return the
1358 register number, and optionally fill in the actual type of the register
1359 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1360 type/index information in *TYPEINFO. */
1363 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1364 enum arm_reg_type
*rtype
,
1365 struct neon_typed_alias
*typeinfo
)
1368 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1369 struct neon_typed_alias atype
;
1370 struct neon_type_el parsetype
;
1374 atype
.eltype
.type
= NT_invtype
;
1375 atype
.eltype
.size
= -1;
1377 /* Try alternate syntax for some types of register. Note these are mutually
1378 exclusive with the Neon syntax extensions. */
1381 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1389 /* Undo polymorphism when a set of register types may be accepted. */
1390 if ((type
== REG_TYPE_NDQ
1391 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1392 || (type
== REG_TYPE_VFSD
1393 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1394 || (type
== REG_TYPE_NSDQ
1395 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1396 || reg
->type
== REG_TYPE_NQ
))
1397 || (type
== REG_TYPE_MMXWC
1398 && (reg
->type
== REG_TYPE_MMXWCG
)))
1399 type
= (enum arm_reg_type
) reg
->type
;
1401 if (type
!= reg
->type
)
1407 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1409 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1411 first_error (_("can't redefine type for operand"));
1414 atype
.defined
|= NTA_HASTYPE
;
1415 atype
.eltype
= parsetype
;
1418 if (skip_past_char (&str
, '[') == SUCCESS
)
1420 if (type
!= REG_TYPE_VFD
)
1422 first_error (_("only D registers may be indexed"));
1426 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1428 first_error (_("can't change index for operand"));
1432 atype
.defined
|= NTA_HASINDEX
;
1434 if (skip_past_char (&str
, ']') == SUCCESS
)
1435 atype
.index
= NEON_ALL_LANES
;
1440 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1442 if (exp
.X_op
!= O_constant
)
1444 first_error (_("constant expression required"));
1448 if (skip_past_char (&str
, ']') == FAIL
)
1451 atype
.index
= exp
.X_add_number
;
1466 /* Like arm_reg_parse, but allow allow the following extra features:
1467 - If RTYPE is non-zero, return the (possibly restricted) type of the
1468 register (e.g. Neon double or quad reg when either has been requested).
1469 - If this is a Neon vector type with additional type information, fill
1470 in the struct pointed to by VECTYPE (if non-NULL).
1471 This function will fault on encountering a scalar. */
1474 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1475 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1477 struct neon_typed_alias atype
;
1479 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1484 /* Do not allow regname(... to parse as a register. */
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1491 first_error (_("register operand expected, but got scalar"));
1496 *vectype
= atype
.eltype
;
1503 #define NEON_SCALAR_REG(X) ((X) >> 4)
1504 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1506 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1507 have enough information to be able to do a good job bounds-checking. So, we
1508 just do easy checks here, and do further checks later. */
1511 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1515 struct neon_typed_alias atype
;
1517 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1519 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1522 if (atype
.index
== NEON_ALL_LANES
)
1524 first_error (_("scalar must have an index"));
1527 else if (atype
.index
>= 64 / elsize
)
1529 first_error (_("scalar index out of range"));
1534 *type
= atype
.eltype
;
1538 return reg
* 16 + atype
.index
;
1541 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1544 parse_reg_list (char ** strp
)
1546 char * str
= * strp
;
1550 /* We come back here if we get ranges concatenated by '+' or '|'. */
1565 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1567 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1577 first_error (_("bad range in register list"));
1581 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1583 if (range
& (1 << i
))
1585 (_("Warning: duplicated register (r%d) in register list"),
1593 if (range
& (1 << reg
))
1594 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1596 else if (reg
<= cur_reg
)
1597 as_tsktsk (_("Warning: register range not in ascending order"));
1602 while (skip_past_comma (&str
) != FAIL
1603 || (in_range
= 1, *str
++ == '-'));
1608 first_error (_("missing `}'"));
1616 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1619 if (exp
.X_op
== O_constant
)
1621 if (exp
.X_add_number
1622 != (exp
.X_add_number
& 0x0000ffff))
1624 inst
.error
= _("invalid register mask");
1628 if ((range
& exp
.X_add_number
) != 0)
1630 int regno
= range
& exp
.X_add_number
;
1633 regno
= (1 << regno
) - 1;
1635 (_("Warning: duplicated register (r%d) in register list"),
1639 range
|= exp
.X_add_number
;
1643 if (inst
.reloc
.type
!= 0)
1645 inst
.error
= _("expression too complex");
1649 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1650 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1651 inst
.reloc
.pc_rel
= 0;
1655 if (*str
== '|' || *str
== '+')
1661 while (another_range
);
1667 /* Types of registers in a list. */
1676 /* Parse a VFP register list. If the string is invalid return FAIL.
1677 Otherwise return the number of registers, and set PBASE to the first
1678 register. Parses registers of type ETYPE.
1679 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1680 - Q registers can be used to specify pairs of D registers
1681 - { } can be omitted from around a singleton register list
1682 FIXME: This is not implemented, as it would require backtracking in
1685 This could be done (the meaning isn't really ambiguous), but doesn't
1686 fit in well with the current parsing framework.
1687 - 32 D registers may be used (also true for VFPv3).
1688 FIXME: Types are ignored in these register lists, which is probably a
1692 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1697 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1701 unsigned long mask
= 0;
1706 inst
.error
= _("expecting {");
1715 regtype
= REG_TYPE_VFS
;
1720 regtype
= REG_TYPE_VFD
;
1723 case REGLIST_NEON_D
:
1724 regtype
= REG_TYPE_NDQ
;
1728 if (etype
!= REGLIST_VFP_S
)
1730 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1731 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1735 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1738 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1745 base_reg
= max_regs
;
1749 int setmask
= 1, addregs
= 1;
1751 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1753 if (new_base
== FAIL
)
1755 first_error (_(reg_expected_msgs
[regtype
]));
1759 if (new_base
>= max_regs
)
1761 first_error (_("register out of range in list"));
1765 /* Note: a value of 2 * n is returned for the register Q<n>. */
1766 if (regtype
== REG_TYPE_NQ
)
1772 if (new_base
< base_reg
)
1773 base_reg
= new_base
;
1775 if (mask
& (setmask
<< new_base
))
1777 first_error (_("invalid register list"));
1781 if ((mask
>> new_base
) != 0 && ! warned
)
1783 as_tsktsk (_("register list not in ascending order"));
1787 mask
|= setmask
<< new_base
;
1790 if (*str
== '-') /* We have the start of a range expression */
1796 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1799 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1803 if (high_range
>= max_regs
)
1805 first_error (_("register out of range in list"));
1809 if (regtype
== REG_TYPE_NQ
)
1810 high_range
= high_range
+ 1;
1812 if (high_range
<= new_base
)
1814 inst
.error
= _("register range not in ascending order");
1818 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1820 if (mask
& (setmask
<< new_base
))
1822 inst
.error
= _("invalid register list");
1826 mask
|= setmask
<< new_base
;
1831 while (skip_past_comma (&str
) != FAIL
);
1835 /* Sanity check -- should have raised a parse error above. */
1836 if (count
== 0 || count
> max_regs
)
1841 /* Final test -- the registers must be consecutive. */
1843 for (i
= 0; i
< count
; i
++)
1845 if ((mask
& (1u << i
)) == 0)
1847 inst
.error
= _("non-contiguous register range");
1857 /* True if two alias types are the same. */
1860 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1868 if (a
->defined
!= b
->defined
)
1871 if ((a
->defined
& NTA_HASTYPE
) != 0
1872 && (a
->eltype
.type
!= b
->eltype
.type
1873 || a
->eltype
.size
!= b
->eltype
.size
))
1876 if ((a
->defined
& NTA_HASINDEX
) != 0
1877 && (a
->index
!= b
->index
))
1883 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1884 The base register is put in *PBASE.
1885 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1887 The register stride (minus one) is put in bit 4 of the return value.
1888 Bits [6:5] encode the list length (minus one).
1889 The type of the list elements is put in *ELTYPE, if non-NULL. */
1891 #define NEON_LANE(X) ((X) & 0xf)
1892 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1893 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1896 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1897 struct neon_type_el
*eltype
)
1904 int leading_brace
= 0;
1905 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1906 const char *const incr_error
= _("register stride must be 1 or 2");
1907 const char *const type_error
= _("mismatched element/structure types in list");
1908 struct neon_typed_alias firsttype
;
1910 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1915 struct neon_typed_alias atype
;
1916 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1920 first_error (_(reg_expected_msgs
[rtype
]));
1927 if (rtype
== REG_TYPE_NQ
)
1933 else if (reg_incr
== -1)
1935 reg_incr
= getreg
- base_reg
;
1936 if (reg_incr
< 1 || reg_incr
> 2)
1938 first_error (_(incr_error
));
1942 else if (getreg
!= base_reg
+ reg_incr
* count
)
1944 first_error (_(incr_error
));
1948 if (! neon_alias_types_same (&atype
, &firsttype
))
1950 first_error (_(type_error
));
1954 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1958 struct neon_typed_alias htype
;
1959 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1961 lane
= NEON_INTERLEAVE_LANES
;
1962 else if (lane
!= NEON_INTERLEAVE_LANES
)
1964 first_error (_(type_error
));
1969 else if (reg_incr
!= 1)
1971 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1975 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1978 first_error (_(reg_expected_msgs
[rtype
]));
1981 if (! neon_alias_types_same (&htype
, &firsttype
))
1983 first_error (_(type_error
));
1986 count
+= hireg
+ dregs
- getreg
;
1990 /* If we're using Q registers, we can't use [] or [n] syntax. */
1991 if (rtype
== REG_TYPE_NQ
)
1997 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2001 else if (lane
!= atype
.index
)
2003 first_error (_(type_error
));
2007 else if (lane
== -1)
2008 lane
= NEON_INTERLEAVE_LANES
;
2009 else if (lane
!= NEON_INTERLEAVE_LANES
)
2011 first_error (_(type_error
));
2016 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2018 /* No lane set by [x]. We must be interleaving structures. */
2020 lane
= NEON_INTERLEAVE_LANES
;
2023 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2024 || (count
> 1 && reg_incr
== -1))
2026 first_error (_("error parsing element/structure list"));
2030 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2032 first_error (_("expected }"));
2040 *eltype
= firsttype
.eltype
;
2045 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2048 /* Parse an explicit relocation suffix on an expression. This is
2049 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2050 arm_reloc_hsh contains no entries, so this function can only
2051 succeed if there is no () after the word. Returns -1 on error,
2052 BFD_RELOC_UNUSED if there wasn't any suffix. */
2054 parse_reloc (char **str
)
2056 struct reloc_entry
*r
;
2060 return BFD_RELOC_UNUSED
;
2065 while (*q
&& *q
!= ')' && *q
!= ',')
2070 if ((r
= (struct reloc_entry
*)
2071 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2078 /* Directives: register aliases. */
2080 static struct reg_entry
*
2081 insert_reg_alias (char *str
, unsigned number
, int type
)
2083 struct reg_entry
*new_reg
;
2086 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2088 if (new_reg
->builtin
)
2089 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2091 /* Only warn about a redefinition if it's not defined as the
2093 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2094 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2099 name
= xstrdup (str
);
2100 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2102 new_reg
->name
= name
;
2103 new_reg
->number
= number
;
2104 new_reg
->type
= type
;
2105 new_reg
->builtin
= FALSE
;
2106 new_reg
->neon
= NULL
;
2108 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2115 insert_neon_reg_alias (char *str
, int number
, int type
,
2116 struct neon_typed_alias
*atype
)
2118 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2122 first_error (_("attempt to redefine typed alias"));
2128 reg
->neon
= (struct neon_typed_alias
*)
2129 xmalloc (sizeof (struct neon_typed_alias
));
2130 *reg
->neon
= *atype
;
2134 /* Look for the .req directive. This is of the form:
2136 new_register_name .req existing_register_name
2138 If we find one, or if it looks sufficiently like one that we want to
2139 handle any error here, return TRUE. Otherwise return FALSE. */
2142 create_register_alias (char * newname
, char *p
)
2144 struct reg_entry
*old
;
2145 char *oldname
, *nbuf
;
2148 /* The input scrubber ensures that whitespace after the mnemonic is
2149 collapsed to single spaces. */
2151 if (strncmp (oldname
, " .req ", 6) != 0)
2155 if (*oldname
== '\0')
2158 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2161 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2165 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2166 the desired alias name, and p points to its end. If not, then
2167 the desired alias name is in the global original_case_string. */
2168 #ifdef TC_CASE_SENSITIVE
2171 newname
= original_case_string
;
2172 nlen
= strlen (newname
);
2175 nbuf
= (char *) alloca (nlen
+ 1);
2176 memcpy (nbuf
, newname
, nlen
);
2179 /* Create aliases under the new name as stated; an all-lowercase
2180 version of the new name; and an all-uppercase version of the new
2182 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2184 for (p
= nbuf
; *p
; p
++)
2187 if (strncmp (nbuf
, newname
, nlen
))
2189 /* If this attempt to create an additional alias fails, do not bother
2190 trying to create the all-lower case alias. We will fail and issue
2191 a second, duplicate error message. This situation arises when the
2192 programmer does something like:
2195 The second .req creates the "Foo" alias but then fails to create
2196 the artificial FOO alias because it has already been created by the
2198 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2202 for (p
= nbuf
; *p
; p
++)
2205 if (strncmp (nbuf
, newname
, nlen
))
2206 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2212 /* Create a Neon typed/indexed register alias using directives, e.g.:
2217 These typed registers can be used instead of the types specified after the
2218 Neon mnemonic, so long as all operands given have types. Types can also be
2219 specified directly, e.g.:
2220 vadd d0.s32, d1.s32, d2.s32 */
2223 create_neon_reg_alias (char *newname
, char *p
)
2225 enum arm_reg_type basetype
;
2226 struct reg_entry
*basereg
;
2227 struct reg_entry mybasereg
;
2228 struct neon_type ntype
;
2229 struct neon_typed_alias typeinfo
;
2230 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2233 typeinfo
.defined
= 0;
2234 typeinfo
.eltype
.type
= NT_invtype
;
2235 typeinfo
.eltype
.size
= -1;
2236 typeinfo
.index
= -1;
2240 if (strncmp (p
, " .dn ", 5) == 0)
2241 basetype
= REG_TYPE_VFD
;
2242 else if (strncmp (p
, " .qn ", 5) == 0)
2243 basetype
= REG_TYPE_NQ
;
2252 basereg
= arm_reg_parse_multi (&p
);
2254 if (basereg
&& basereg
->type
!= basetype
)
2256 as_bad (_("bad type for register"));
2260 if (basereg
== NULL
)
2263 /* Try parsing as an integer. */
2264 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2265 if (exp
.X_op
!= O_constant
)
2267 as_bad (_("expression must be constant"));
2270 basereg
= &mybasereg
;
2271 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2277 typeinfo
= *basereg
->neon
;
2279 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2281 /* We got a type. */
2282 if (typeinfo
.defined
& NTA_HASTYPE
)
2284 as_bad (_("can't redefine the type of a register alias"));
2288 typeinfo
.defined
|= NTA_HASTYPE
;
2289 if (ntype
.elems
!= 1)
2291 as_bad (_("you must specify a single type only"));
2294 typeinfo
.eltype
= ntype
.el
[0];
2297 if (skip_past_char (&p
, '[') == SUCCESS
)
2300 /* We got a scalar index. */
2302 if (typeinfo
.defined
& NTA_HASINDEX
)
2304 as_bad (_("can't redefine the index of a scalar alias"));
2308 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2310 if (exp
.X_op
!= O_constant
)
2312 as_bad (_("scalar index must be constant"));
2316 typeinfo
.defined
|= NTA_HASINDEX
;
2317 typeinfo
.index
= exp
.X_add_number
;
2319 if (skip_past_char (&p
, ']') == FAIL
)
2321 as_bad (_("expecting ]"));
2326 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2327 the desired alias name, and p points to its end. If not, then
2328 the desired alias name is in the global original_case_string. */
2329 #ifdef TC_CASE_SENSITIVE
2330 namelen
= nameend
- newname
;
2332 newname
= original_case_string
;
2333 namelen
= strlen (newname
);
2336 namebuf
= (char *) alloca (namelen
+ 1);
2337 strncpy (namebuf
, newname
, namelen
);
2338 namebuf
[namelen
] = '\0';
2340 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2341 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2343 /* Insert name in all uppercase. */
2344 for (p
= namebuf
; *p
; p
++)
2347 if (strncmp (namebuf
, newname
, namelen
))
2348 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2349 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2351 /* Insert name in all lowercase. */
2352 for (p
= namebuf
; *p
; p
++)
2355 if (strncmp (namebuf
, newname
, namelen
))
2356 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2357 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2362 /* Should never be called, as .req goes between the alias and the
2363 register name, not at the beginning of the line. */
2366 s_req (int a ATTRIBUTE_UNUSED
)
2368 as_bad (_("invalid syntax for .req directive"));
2372 s_dn (int a ATTRIBUTE_UNUSED
)
2374 as_bad (_("invalid syntax for .dn directive"));
2378 s_qn (int a ATTRIBUTE_UNUSED
)
2380 as_bad (_("invalid syntax for .qn directive"));
2383 /* The .unreq directive deletes an alias which was previously defined
2384 by .req. For example:
2390 s_unreq (int a ATTRIBUTE_UNUSED
)
2395 name
= input_line_pointer
;
2397 while (*input_line_pointer
!= 0
2398 && *input_line_pointer
!= ' '
2399 && *input_line_pointer
!= '\n')
2400 ++input_line_pointer
;
2402 saved_char
= *input_line_pointer
;
2403 *input_line_pointer
= 0;
2406 as_bad (_("invalid syntax for .unreq directive"));
2409 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2413 as_bad (_("unknown register alias '%s'"), name
);
2414 else if (reg
->builtin
)
2415 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2422 hash_delete (arm_reg_hsh
, name
, FALSE
);
2423 free ((char *) reg
->name
);
2428 /* Also locate the all upper case and all lower case versions.
2429 Do not complain if we cannot find one or the other as it
2430 was probably deleted above. */
2432 nbuf
= strdup (name
);
2433 for (p
= nbuf
; *p
; p
++)
2435 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2438 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2439 free ((char *) reg
->name
);
2445 for (p
= nbuf
; *p
; p
++)
2447 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2450 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2451 free ((char *) reg
->name
);
2461 *input_line_pointer
= saved_char
;
2462 demand_empty_rest_of_line ();
2465 /* Directives: Instruction set selection. */
2468 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2469 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2470 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2471 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2473 /* Create a new mapping symbol for the transition to STATE. */
2476 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2479 const char * symname
;
2486 type
= BSF_NO_FLAGS
;
2490 type
= BSF_NO_FLAGS
;
2494 type
= BSF_NO_FLAGS
;
2500 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2501 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2506 THUMB_SET_FUNC (symbolP
, 0);
2507 ARM_SET_THUMB (symbolP
, 0);
2508 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2512 THUMB_SET_FUNC (symbolP
, 1);
2513 ARM_SET_THUMB (symbolP
, 1);
2514 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2522 /* Save the mapping symbols for future reference. Also check that
2523 we do not place two mapping symbols at the same offset within a
2524 frag. We'll handle overlap between frags in
2525 check_mapping_symbols.
2527 If .fill or other data filling directive generates zero sized data,
2528 the mapping symbol for the following code will have the same value
2529 as the one generated for the data filling directive. In this case,
2530 we replace the old symbol with the new one at the same address. */
2533 if (frag
->tc_frag_data
.first_map
!= NULL
)
2535 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2536 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2538 frag
->tc_frag_data
.first_map
= symbolP
;
2540 if (frag
->tc_frag_data
.last_map
!= NULL
)
2542 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2543 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2544 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2546 frag
->tc_frag_data
.last_map
= symbolP
;
2549 /* We must sometimes convert a region marked as code to data during
2550 code alignment, if an odd number of bytes have to be padded. The
2551 code mapping symbol is pushed to an aligned address. */
2554 insert_data_mapping_symbol (enum mstate state
,
2555 valueT value
, fragS
*frag
, offsetT bytes
)
2557 /* If there was already a mapping symbol, remove it. */
2558 if (frag
->tc_frag_data
.last_map
!= NULL
2559 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2561 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2565 know (frag
->tc_frag_data
.first_map
== symp
);
2566 frag
->tc_frag_data
.first_map
= NULL
;
2568 frag
->tc_frag_data
.last_map
= NULL
;
2569 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2572 make_mapping_symbol (MAP_DATA
, value
, frag
);
2573 make_mapping_symbol (state
, value
+ bytes
, frag
);
2576 static void mapping_state_2 (enum mstate state
, int max_chars
);
2578 /* Set the mapping state to STATE. Only call this when about to
2579 emit some STATE bytes to the file. */
2582 mapping_state (enum mstate state
)
2584 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2586 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2588 if (mapstate
== state
)
2589 /* The mapping symbol has already been emitted.
2590 There is nothing else to do. */
2592 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2593 /* This case will be evaluated later in the next else. */
2595 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2596 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2598 /* Only add the symbol if the offset is > 0:
2599 if we're at the first frag, check it's size > 0;
2600 if we're not at the first frag, then for sure
2601 the offset is > 0. */
2602 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2603 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2606 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2609 mapping_state_2 (state
, 0);
2613 /* Same as mapping_state, but MAX_CHARS bytes have already been
2614 allocated. Put the mapping symbol that far back. */
2617 mapping_state_2 (enum mstate state
, int max_chars
)
2619 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2621 if (!SEG_NORMAL (now_seg
))
2624 if (mapstate
== state
)
2625 /* The mapping symbol has already been emitted.
2626 There is nothing else to do. */
2629 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2630 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2633 #define mapping_state(x) ((void)0)
2634 #define mapping_state_2(x, y) ((void)0)
2637 /* Find the real, Thumb encoded start of a Thumb function. */
2641 find_real_start (symbolS
* symbolP
)
2644 const char * name
= S_GET_NAME (symbolP
);
2645 symbolS
* new_target
;
2647 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2648 #define STUB_NAME ".real_start_of"
2653 /* The compiler may generate BL instructions to local labels because
2654 it needs to perform a branch to a far away location. These labels
2655 do not have a corresponding ".real_start_of" label. We check
2656 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2657 the ".real_start_of" convention for nonlocal branches. */
2658 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2661 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2662 new_target
= symbol_find (real_start
);
2664 if (new_target
== NULL
)
2666 as_warn (_("Failed to find real start of function: %s\n"), name
);
2667 new_target
= symbolP
;
2675 opcode_select (int width
)
2682 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2683 as_bad (_("selected processor does not support THUMB opcodes"));
2686 /* No need to force the alignment, since we will have been
2687 coming from ARM mode, which is word-aligned. */
2688 record_alignment (now_seg
, 1);
2695 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2696 as_bad (_("selected processor does not support ARM opcodes"));
2701 frag_align (2, 0, 0);
2703 record_alignment (now_seg
, 1);
2708 as_bad (_("invalid instruction size selected (%d)"), width
);
2713 s_arm (int ignore ATTRIBUTE_UNUSED
)
2716 demand_empty_rest_of_line ();
2720 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2723 demand_empty_rest_of_line ();
2727 s_code (int unused ATTRIBUTE_UNUSED
)
2731 temp
= get_absolute_expression ();
2736 opcode_select (temp
);
2740 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2745 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2747 /* If we are not already in thumb mode go into it, EVEN if
2748 the target processor does not support thumb instructions.
2749 This is used by gcc/config/arm/lib1funcs.asm for example
2750 to compile interworking support functions even if the
2751 target processor should not support interworking. */
2755 record_alignment (now_seg
, 1);
2758 demand_empty_rest_of_line ();
2762 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2766 /* The following label is the name/address of the start of a Thumb function.
2767 We need to know this for the interworking support. */
2768 label_is_thumb_function_name
= TRUE
;
2771 /* Perform a .set directive, but also mark the alias as
2772 being a thumb function. */
2775 s_thumb_set (int equiv
)
2777 /* XXX the following is a duplicate of the code for s_set() in read.c
2778 We cannot just call that code as we need to get at the symbol that
2785 /* Especial apologies for the random logic:
2786 This just grew, and could be parsed much more simply!
2788 name
= input_line_pointer
;
2789 delim
= get_symbol_end ();
2790 end_name
= input_line_pointer
;
2793 if (*input_line_pointer
!= ',')
2796 as_bad (_("expected comma after name \"%s\""), name
);
2798 ignore_rest_of_line ();
2802 input_line_pointer
++;
2805 if (name
[0] == '.' && name
[1] == '\0')
2807 /* XXX - this should not happen to .thumb_set. */
2811 if ((symbolP
= symbol_find (name
)) == NULL
2812 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2815 /* When doing symbol listings, play games with dummy fragments living
2816 outside the normal fragment chain to record the file and line info
2818 if (listing
& LISTING_SYMBOLS
)
2820 extern struct list_info_struct
* listing_tail
;
2821 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2823 memset (dummy_frag
, 0, sizeof (fragS
));
2824 dummy_frag
->fr_type
= rs_fill
;
2825 dummy_frag
->line
= listing_tail
;
2826 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2827 dummy_frag
->fr_symbol
= symbolP
;
2831 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2834 /* "set" symbols are local unless otherwise specified. */
2835 SF_SET_LOCAL (symbolP
);
2836 #endif /* OBJ_COFF */
2837 } /* Make a new symbol. */
2839 symbol_table_insert (symbolP
);
2844 && S_IS_DEFINED (symbolP
)
2845 && S_GET_SEGMENT (symbolP
) != reg_section
)
2846 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2848 pseudo_set (symbolP
);
2850 demand_empty_rest_of_line ();
2852 /* XXX Now we come to the Thumb specific bit of code. */
2854 THUMB_SET_FUNC (symbolP
, 1);
2855 ARM_SET_THUMB (symbolP
, 1);
2856 #if defined OBJ_ELF || defined OBJ_COFF
2857 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2861 /* Directives: Mode selection. */
2863 /* .syntax [unified|divided] - choose the new unified syntax
2864 (same for Arm and Thumb encoding, modulo slight differences in what
2865 can be represented) or the old divergent syntax for each mode. */
2867 s_syntax (int unused ATTRIBUTE_UNUSED
)
2871 name
= input_line_pointer
;
2872 delim
= get_symbol_end ();
2874 if (!strcasecmp (name
, "unified"))
2875 unified_syntax
= TRUE
;
2876 else if (!strcasecmp (name
, "divided"))
2877 unified_syntax
= FALSE
;
2880 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2883 *input_line_pointer
= delim
;
2884 demand_empty_rest_of_line ();
2887 /* Directives: sectioning and alignment. */
2889 /* Same as s_align_ptwo but align 0 => align 2. */
2892 s_align (int unused ATTRIBUTE_UNUSED
)
2897 long max_alignment
= 15;
2899 temp
= get_absolute_expression ();
2900 if (temp
> max_alignment
)
2901 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2904 as_bad (_("alignment negative. 0 assumed."));
2908 if (*input_line_pointer
== ',')
2910 input_line_pointer
++;
2911 temp_fill
= get_absolute_expression ();
2923 /* Only make a frag if we HAVE to. */
2924 if (temp
&& !need_pass_2
)
2926 if (!fill_p
&& subseg_text_p (now_seg
))
2927 frag_align_code (temp
, 0);
2929 frag_align (temp
, (int) temp_fill
, 0);
2931 demand_empty_rest_of_line ();
2933 record_alignment (now_seg
, temp
);
2937 s_bss (int ignore ATTRIBUTE_UNUSED
)
2939 /* We don't support putting frags in the BSS segment, we fake it by
2940 marking in_bss, then looking at s_skip for clues. */
2941 subseg_set (bss_section
, 0);
2942 demand_empty_rest_of_line ();
2944 #ifdef md_elf_section_change_hook
2945 md_elf_section_change_hook ();
2950 s_even (int ignore ATTRIBUTE_UNUSED
)
2952 /* Never make frag if expect extra pass. */
2954 frag_align (1, 0, 0);
2956 record_alignment (now_seg
, 1);
2958 demand_empty_rest_of_line ();
2961 /* Directives: Literal pools. */
2963 static literal_pool
*
2964 find_literal_pool (void)
2966 literal_pool
* pool
;
2968 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2970 if (pool
->section
== now_seg
2971 && pool
->sub_section
== now_subseg
)
2978 static literal_pool
*
2979 find_or_make_literal_pool (void)
2981 /* Next literal pool ID number. */
2982 static unsigned int latest_pool_num
= 1;
2983 literal_pool
* pool
;
2985 pool
= find_literal_pool ();
2989 /* Create a new pool. */
2990 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2994 pool
->next_free_entry
= 0;
2995 pool
->section
= now_seg
;
2996 pool
->sub_section
= now_subseg
;
2997 pool
->next
= list_of_pools
;
2998 pool
->symbol
= NULL
;
3000 /* Add it to the list. */
3001 list_of_pools
= pool
;
3004 /* New pools, and emptied pools, will have a NULL symbol. */
3005 if (pool
->symbol
== NULL
)
3007 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3008 (valueT
) 0, &zero_address_frag
);
3009 pool
->id
= latest_pool_num
++;
3016 /* Add the literal in the global 'inst'
3017 structure to the relevant literal pool. */
3020 add_to_lit_pool (void)
3022 literal_pool
* pool
;
3025 pool
= find_or_make_literal_pool ();
3027 /* Check if this literal value is already in the pool. */
3028 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3030 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3031 && (inst
.reloc
.exp
.X_op
== O_constant
)
3032 && (pool
->literals
[entry
].X_add_number
3033 == inst
.reloc
.exp
.X_add_number
)
3034 && (pool
->literals
[entry
].X_unsigned
3035 == inst
.reloc
.exp
.X_unsigned
))
3038 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3039 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3040 && (pool
->literals
[entry
].X_add_number
3041 == inst
.reloc
.exp
.X_add_number
)
3042 && (pool
->literals
[entry
].X_add_symbol
3043 == inst
.reloc
.exp
.X_add_symbol
)
3044 && (pool
->literals
[entry
].X_op_symbol
3045 == inst
.reloc
.exp
.X_op_symbol
))
3049 /* Do we need to create a new entry? */
3050 if (entry
== pool
->next_free_entry
)
3052 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3054 inst
.error
= _("literal pool overflow");
3058 pool
->literals
[entry
] = inst
.reloc
.exp
;
3059 pool
->next_free_entry
+= 1;
3062 inst
.reloc
.exp
.X_op
= O_symbol
;
3063 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3064 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3069 /* Can't use symbol_new here, so have to create a symbol and then at
3070 a later date assign it a value. Thats what these functions do. */
3073 symbol_locate (symbolS
* symbolP
,
3074 const char * name
, /* It is copied, the caller can modify. */
3075 segT segment
, /* Segment identifier (SEG_<something>). */
3076 valueT valu
, /* Symbol value. */
3077 fragS
* frag
) /* Associated fragment. */
3079 unsigned int name_length
;
3080 char * preserved_copy_of_name
;
3082 name_length
= strlen (name
) + 1; /* +1 for \0. */
3083 obstack_grow (¬es
, name
, name_length
);
3084 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3086 #ifdef tc_canonicalize_symbol_name
3087 preserved_copy_of_name
=
3088 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3091 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3093 S_SET_SEGMENT (symbolP
, segment
);
3094 S_SET_VALUE (symbolP
, valu
);
3095 symbol_clear_list_pointers (symbolP
);
3097 symbol_set_frag (symbolP
, frag
);
3099 /* Link to end of symbol chain. */
3101 extern int symbol_table_frozen
;
3103 if (symbol_table_frozen
)
3107 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3109 obj_symbol_new_hook (symbolP
);
3111 #ifdef tc_symbol_new_hook
3112 tc_symbol_new_hook (symbolP
);
3116 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3117 #endif /* DEBUG_SYMS */
3122 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3125 literal_pool
* pool
;
3128 pool
= find_literal_pool ();
3130 || pool
->symbol
== NULL
3131 || pool
->next_free_entry
== 0)
3134 mapping_state (MAP_DATA
);
3136 /* Align pool as you have word accesses.
3137 Only make a frag if we have to. */
3139 frag_align (2, 0, 0);
3141 record_alignment (now_seg
, 2);
3143 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3145 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3146 (valueT
) frag_now_fix (), frag_now
);
3147 symbol_table_insert (pool
->symbol
);
3149 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3151 #if defined OBJ_COFF || defined OBJ_ELF
3152 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3155 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3156 /* First output the expression in the instruction to the pool. */
3157 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3159 /* Mark the pool as empty. */
3160 pool
->next_free_entry
= 0;
3161 pool
->symbol
= NULL
;
3165 /* Forward declarations for functions below, in the MD interface
3167 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3168 static valueT
create_unwind_entry (int);
3169 static void start_unwind_section (const segT
, int);
3170 static void add_unwind_opcode (valueT
, int);
3171 static void flush_pending_unwind (void);
3173 /* Directives: Data. */
3176 s_arm_elf_cons (int nbytes
)
3180 #ifdef md_flush_pending_output
3181 md_flush_pending_output ();
3184 if (is_it_end_of_statement ())
3186 demand_empty_rest_of_line ();
3190 #ifdef md_cons_align
3191 md_cons_align (nbytes
);
3194 mapping_state (MAP_DATA
);
3198 char *base
= input_line_pointer
;
3202 if (exp
.X_op
!= O_symbol
)
3203 emit_expr (&exp
, (unsigned int) nbytes
);
3206 char *before_reloc
= input_line_pointer
;
3207 reloc
= parse_reloc (&input_line_pointer
);
3210 as_bad (_("unrecognized relocation suffix"));
3211 ignore_rest_of_line ();
3214 else if (reloc
== BFD_RELOC_UNUSED
)
3215 emit_expr (&exp
, (unsigned int) nbytes
);
3218 reloc_howto_type
*howto
= (reloc_howto_type
*)
3219 bfd_reloc_type_lookup (stdoutput
,
3220 (bfd_reloc_code_real_type
) reloc
);
3221 int size
= bfd_get_reloc_size (howto
);
3223 if (reloc
== BFD_RELOC_ARM_PLT32
)
3225 as_bad (_("(plt) is only valid on branch targets"));
3226 reloc
= BFD_RELOC_UNUSED
;
3231 as_bad (_("%s relocations do not fit in %d bytes"),
3232 howto
->name
, nbytes
);
3235 /* We've parsed an expression stopping at O_symbol.
3236 But there may be more expression left now that we
3237 have parsed the relocation marker. Parse it again.
3238 XXX Surely there is a cleaner way to do this. */
3239 char *p
= input_line_pointer
;
3241 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3242 memcpy (save_buf
, base
, input_line_pointer
- base
);
3243 memmove (base
+ (input_line_pointer
- before_reloc
),
3244 base
, before_reloc
- base
);
3246 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3248 memcpy (base
, save_buf
, p
- base
);
3250 offset
= nbytes
- size
;
3251 p
= frag_more ((int) nbytes
);
3252 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3253 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3258 while (*input_line_pointer
++ == ',');
3260 /* Put terminator back into stream. */
3261 input_line_pointer
--;
3262 demand_empty_rest_of_line ();
3265 /* Emit an expression containing a 32-bit thumb instruction.
3266 Implementation based on put_thumb32_insn. */
3269 emit_thumb32_expr (expressionS
* exp
)
3271 expressionS exp_high
= *exp
;
3273 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3274 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3275 exp
->X_add_number
&= 0xffff;
3276 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3279 /* Guess the instruction size based on the opcode. */
3282 thumb_insn_size (int opcode
)
3284 if ((unsigned int) opcode
< 0xe800u
)
3286 else if ((unsigned int) opcode
>= 0xe8000000u
)
3293 emit_insn (expressionS
*exp
, int nbytes
)
3297 if (exp
->X_op
== O_constant
)
3302 size
= thumb_insn_size (exp
->X_add_number
);
3306 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3308 as_bad (_(".inst.n operand too big. "\
3309 "Use .inst.w instead"));
3314 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3315 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3317 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3319 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3320 emit_thumb32_expr (exp
);
3322 emit_expr (exp
, (unsigned int) size
);
3324 it_fsm_post_encode ();
3328 as_bad (_("cannot determine Thumb instruction size. " \
3329 "Use .inst.n/.inst.w instead"));
3332 as_bad (_("constant expression required"));
3337 /* Like s_arm_elf_cons but do not use md_cons_align and
3338 set the mapping state to MAP_ARM/MAP_THUMB. */
3341 s_arm_elf_inst (int nbytes
)
3343 if (is_it_end_of_statement ())
3345 demand_empty_rest_of_line ();
3349 /* Calling mapping_state () here will not change ARM/THUMB,
3350 but will ensure not to be in DATA state. */
3353 mapping_state (MAP_THUMB
);
3358 as_bad (_("width suffixes are invalid in ARM mode"));
3359 ignore_rest_of_line ();
3365 mapping_state (MAP_ARM
);
3374 if (! emit_insn (& exp
, nbytes
))
3376 ignore_rest_of_line ();
3380 while (*input_line_pointer
++ == ',');
3382 /* Put terminator back into stream. */
3383 input_line_pointer
--;
3384 demand_empty_rest_of_line ();
3387 /* Parse a .rel31 directive. */
3390 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3397 if (*input_line_pointer
== '1')
3398 highbit
= 0x80000000;
3399 else if (*input_line_pointer
!= '0')
3400 as_bad (_("expected 0 or 1"));
3402 input_line_pointer
++;
3403 if (*input_line_pointer
!= ',')
3404 as_bad (_("missing comma"));
3405 input_line_pointer
++;
3407 #ifdef md_flush_pending_output
3408 md_flush_pending_output ();
3411 #ifdef md_cons_align
3415 mapping_state (MAP_DATA
);
3420 md_number_to_chars (p
, highbit
, 4);
3421 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3422 BFD_RELOC_ARM_PREL31
);
3424 demand_empty_rest_of_line ();
3427 /* Directives: AEABI stack-unwind tables. */
3429 /* Parse an unwind_fnstart directive. Simply records the current location. */
3432 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3434 demand_empty_rest_of_line ();
3435 if (unwind
.proc_start
)
3437 as_bad (_("duplicate .fnstart directive"));
3441 /* Mark the start of the function. */
3442 unwind
.proc_start
= expr_build_dot ();
3444 /* Reset the rest of the unwind info. */
3445 unwind
.opcode_count
= 0;
3446 unwind
.table_entry
= NULL
;
3447 unwind
.personality_routine
= NULL
;
3448 unwind
.personality_index
= -1;
3449 unwind
.frame_size
= 0;
3450 unwind
.fp_offset
= 0;
3451 unwind
.fp_reg
= REG_SP
;
3453 unwind
.sp_restored
= 0;
3457 /* Parse a handlerdata directive. Creates the exception handling table entry
3458 for the function. */
3461 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3463 demand_empty_rest_of_line ();
3464 if (!unwind
.proc_start
)
3465 as_bad (MISSING_FNSTART
);
3467 if (unwind
.table_entry
)
3468 as_bad (_("duplicate .handlerdata directive"));
3470 create_unwind_entry (1);
3473 /* Parse an unwind_fnend directive. Generates the index table entry. */
3476 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3481 unsigned int marked_pr_dependency
;
3483 demand_empty_rest_of_line ();
3485 if (!unwind
.proc_start
)
3487 as_bad (_(".fnend directive without .fnstart"));
3491 /* Add eh table entry. */
3492 if (unwind
.table_entry
== NULL
)
3493 val
= create_unwind_entry (0);
3497 /* Add index table entry. This is two words. */
3498 start_unwind_section (unwind
.saved_seg
, 1);
3499 frag_align (2, 0, 0);
3500 record_alignment (now_seg
, 2);
3502 ptr
= frag_more (8);
3503 where
= frag_now_fix () - 8;
3505 /* Self relative offset of the function start. */
3506 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3507 BFD_RELOC_ARM_PREL31
);
3509 /* Indicate dependency on EHABI-defined personality routines to the
3510 linker, if it hasn't been done already. */
3511 marked_pr_dependency
3512 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3513 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3514 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3516 static const char *const name
[] =
3518 "__aeabi_unwind_cpp_pr0",
3519 "__aeabi_unwind_cpp_pr1",
3520 "__aeabi_unwind_cpp_pr2"
3522 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3523 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3524 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3525 |= 1 << unwind
.personality_index
;
3529 /* Inline exception table entry. */
3530 md_number_to_chars (ptr
+ 4, val
, 4);
3532 /* Self relative offset of the table entry. */
3533 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3534 BFD_RELOC_ARM_PREL31
);
3536 /* Restore the original section. */
3537 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3539 unwind
.proc_start
= NULL
;
3543 /* Parse an unwind_cantunwind directive. */
3546 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3548 demand_empty_rest_of_line ();
3549 if (!unwind
.proc_start
)
3550 as_bad (MISSING_FNSTART
);
3552 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3553 as_bad (_("personality routine specified for cantunwind frame"));
3555 unwind
.personality_index
= -2;
3559 /* Parse a personalityindex directive. */
3562 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3566 if (!unwind
.proc_start
)
3567 as_bad (MISSING_FNSTART
);
3569 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3570 as_bad (_("duplicate .personalityindex directive"));
3574 if (exp
.X_op
!= O_constant
3575 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3577 as_bad (_("bad personality routine number"));
3578 ignore_rest_of_line ();
3582 unwind
.personality_index
= exp
.X_add_number
;
3584 demand_empty_rest_of_line ();
3588 /* Parse a personality directive. */
3591 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3595 if (!unwind
.proc_start
)
3596 as_bad (MISSING_FNSTART
);
3598 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3599 as_bad (_("duplicate .personality directive"));
3601 name
= input_line_pointer
;
3602 c
= get_symbol_end ();
3603 p
= input_line_pointer
;
3604 unwind
.personality_routine
= symbol_find_or_make (name
);
3606 demand_empty_rest_of_line ();
3610 /* Parse a directive saving core registers. */
3613 s_arm_unwind_save_core (void)
3619 range
= parse_reg_list (&input_line_pointer
);
3622 as_bad (_("expected register list"));
3623 ignore_rest_of_line ();
3627 demand_empty_rest_of_line ();
3629 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3630 into .unwind_save {..., sp...}. We aren't bothered about the value of
3631 ip because it is clobbered by calls. */
3632 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3633 && (range
& 0x3000) == 0x1000)
3635 unwind
.opcode_count
--;
3636 unwind
.sp_restored
= 0;
3637 range
= (range
| 0x2000) & ~0x1000;
3638 unwind
.pending_offset
= 0;
3644 /* See if we can use the short opcodes. These pop a block of up to 8
3645 registers starting with r4, plus maybe r14. */
3646 for (n
= 0; n
< 8; n
++)
3648 /* Break at the first non-saved register. */
3649 if ((range
& (1 << (n
+ 4))) == 0)
3652 /* See if there are any other bits set. */
3653 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3655 /* Use the long form. */
3656 op
= 0x8000 | ((range
>> 4) & 0xfff);
3657 add_unwind_opcode (op
, 2);
3661 /* Use the short form. */
3663 op
= 0xa8; /* Pop r14. */
3665 op
= 0xa0; /* Do not pop r14. */
3667 add_unwind_opcode (op
, 1);
3674 op
= 0xb100 | (range
& 0xf);
3675 add_unwind_opcode (op
, 2);
3678 /* Record the number of bytes pushed. */
3679 for (n
= 0; n
< 16; n
++)
3681 if (range
& (1 << n
))
3682 unwind
.frame_size
+= 4;
3687 /* Parse a directive saving FPA registers. */
3690 s_arm_unwind_save_fpa (int reg
)
3696 /* Get Number of registers to transfer. */
3697 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3700 exp
.X_op
= O_illegal
;
3702 if (exp
.X_op
!= O_constant
)
3704 as_bad (_("expected , <constant>"));
3705 ignore_rest_of_line ();
3709 num_regs
= exp
.X_add_number
;
3711 if (num_regs
< 1 || num_regs
> 4)
3713 as_bad (_("number of registers must be in the range [1:4]"));
3714 ignore_rest_of_line ();
3718 demand_empty_rest_of_line ();
3723 op
= 0xb4 | (num_regs
- 1);
3724 add_unwind_opcode (op
, 1);
3729 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3730 add_unwind_opcode (op
, 2);
3732 unwind
.frame_size
+= num_regs
* 12;
3736 /* Parse a directive saving VFP registers for ARMv6 and above. */
3739 s_arm_unwind_save_vfp_armv6 (void)
3744 int num_vfpv3_regs
= 0;
3745 int num_regs_below_16
;
3747 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3750 as_bad (_("expected register list"));
3751 ignore_rest_of_line ();
3755 demand_empty_rest_of_line ();
3757 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3758 than FSTMX/FLDMX-style ones). */
3760 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3762 num_vfpv3_regs
= count
;
3763 else if (start
+ count
> 16)
3764 num_vfpv3_regs
= start
+ count
- 16;
3766 if (num_vfpv3_regs
> 0)
3768 int start_offset
= start
> 16 ? start
- 16 : 0;
3769 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3770 add_unwind_opcode (op
, 2);
3773 /* Generate opcode for registers numbered in the range 0 .. 15. */
3774 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3775 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3776 if (num_regs_below_16
> 0)
3778 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3779 add_unwind_opcode (op
, 2);
3782 unwind
.frame_size
+= count
* 8;
3786 /* Parse a directive saving VFP registers for pre-ARMv6. */
3789 s_arm_unwind_save_vfp (void)
3795 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3798 as_bad (_("expected register list"));
3799 ignore_rest_of_line ();
3803 demand_empty_rest_of_line ();
3808 op
= 0xb8 | (count
- 1);
3809 add_unwind_opcode (op
, 1);
3814 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3815 add_unwind_opcode (op
, 2);
3817 unwind
.frame_size
+= count
* 8 + 4;
3821 /* Parse a directive saving iWMMXt data registers. */
3824 s_arm_unwind_save_mmxwr (void)
3832 if (*input_line_pointer
== '{')
3833 input_line_pointer
++;
3837 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3841 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3846 as_tsktsk (_("register list not in ascending order"));
3849 if (*input_line_pointer
== '-')
3851 input_line_pointer
++;
3852 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3855 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3858 else if (reg
>= hi_reg
)
3860 as_bad (_("bad register range"));
3863 for (; reg
< hi_reg
; reg
++)
3867 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3869 if (*input_line_pointer
== '}')
3870 input_line_pointer
++;
3872 demand_empty_rest_of_line ();
3874 /* Generate any deferred opcodes because we're going to be looking at
3876 flush_pending_unwind ();
3878 for (i
= 0; i
< 16; i
++)
3880 if (mask
& (1 << i
))
3881 unwind
.frame_size
+= 8;
3884 /* Attempt to combine with a previous opcode. We do this because gcc
3885 likes to output separate unwind directives for a single block of
3887 if (unwind
.opcode_count
> 0)
3889 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3890 if ((i
& 0xf8) == 0xc0)
3893 /* Only merge if the blocks are contiguous. */
3896 if ((mask
& 0xfe00) == (1 << 9))
3898 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3899 unwind
.opcode_count
--;
3902 else if (i
== 6 && unwind
.opcode_count
>= 2)
3904 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3908 op
= 0xffff << (reg
- 1);
3910 && ((mask
& op
) == (1u << (reg
- 1))))
3912 op
= (1 << (reg
+ i
+ 1)) - 1;
3913 op
&= ~((1 << reg
) - 1);
3915 unwind
.opcode_count
-= 2;
3922 /* We want to generate opcodes in the order the registers have been
3923 saved, ie. descending order. */
3924 for (reg
= 15; reg
>= -1; reg
--)
3926 /* Save registers in blocks. */
3928 || !(mask
& (1 << reg
)))
3930 /* We found an unsaved reg. Generate opcodes to save the
3937 op
= 0xc0 | (hi_reg
- 10);
3938 add_unwind_opcode (op
, 1);
3943 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3944 add_unwind_opcode (op
, 2);
3953 ignore_rest_of_line ();
3957 s_arm_unwind_save_mmxwcg (void)
3964 if (*input_line_pointer
== '{')
3965 input_line_pointer
++;
3969 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3973 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3979 as_tsktsk (_("register list not in ascending order"));
3982 if (*input_line_pointer
== '-')
3984 input_line_pointer
++;
3985 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3988 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3991 else if (reg
>= hi_reg
)
3993 as_bad (_("bad register range"));
3996 for (; reg
< hi_reg
; reg
++)
4000 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4002 if (*input_line_pointer
== '}')
4003 input_line_pointer
++;
4005 demand_empty_rest_of_line ();
4007 /* Generate any deferred opcodes because we're going to be looking at
4009 flush_pending_unwind ();
4011 for (reg
= 0; reg
< 16; reg
++)
4013 if (mask
& (1 << reg
))
4014 unwind
.frame_size
+= 4;
4017 add_unwind_opcode (op
, 2);
4020 ignore_rest_of_line ();
4024 /* Parse an unwind_save directive.
4025 If the argument is non-zero, this is a .vsave directive. */
4028 s_arm_unwind_save (int arch_v6
)
4031 struct reg_entry
*reg
;
4032 bfd_boolean had_brace
= FALSE
;
4034 if (!unwind
.proc_start
)
4035 as_bad (MISSING_FNSTART
);
4037 /* Figure out what sort of save we have. */
4038 peek
= input_line_pointer
;
4046 reg
= arm_reg_parse_multi (&peek
);
4050 as_bad (_("register expected"));
4051 ignore_rest_of_line ();
4060 as_bad (_("FPA .unwind_save does not take a register list"));
4061 ignore_rest_of_line ();
4064 input_line_pointer
= peek
;
4065 s_arm_unwind_save_fpa (reg
->number
);
4068 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4071 s_arm_unwind_save_vfp_armv6 ();
4073 s_arm_unwind_save_vfp ();
4075 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4076 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4079 as_bad (_(".unwind_save does not support this kind of register"));
4080 ignore_rest_of_line ();
4085 /* Parse an unwind_movsp directive. */
4088 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4094 if (!unwind
.proc_start
)
4095 as_bad (MISSING_FNSTART
);
4097 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4100 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4101 ignore_rest_of_line ();
4105 /* Optional constant. */
4106 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4108 if (immediate_for_directive (&offset
) == FAIL
)
4114 demand_empty_rest_of_line ();
4116 if (reg
== REG_SP
|| reg
== REG_PC
)
4118 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4122 if (unwind
.fp_reg
!= REG_SP
)
4123 as_bad (_("unexpected .unwind_movsp directive"));
4125 /* Generate opcode to restore the value. */
4127 add_unwind_opcode (op
, 1);
4129 /* Record the information for later. */
4130 unwind
.fp_reg
= reg
;
4131 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4132 unwind
.sp_restored
= 1;
4135 /* Parse an unwind_pad directive. */
4138 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4142 if (!unwind
.proc_start
)
4143 as_bad (MISSING_FNSTART
);
4145 if (immediate_for_directive (&offset
) == FAIL
)
4150 as_bad (_("stack increment must be multiple of 4"));
4151 ignore_rest_of_line ();
4155 /* Don't generate any opcodes, just record the details for later. */
4156 unwind
.frame_size
+= offset
;
4157 unwind
.pending_offset
+= offset
;
4159 demand_empty_rest_of_line ();
4162 /* Parse an unwind_setfp directive. */
4165 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4171 if (!unwind
.proc_start
)
4172 as_bad (MISSING_FNSTART
);
4174 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4175 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4178 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4180 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4182 as_bad (_("expected <reg>, <reg>"));
4183 ignore_rest_of_line ();
4187 /* Optional constant. */
4188 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4190 if (immediate_for_directive (&offset
) == FAIL
)
4196 demand_empty_rest_of_line ();
4198 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4200 as_bad (_("register must be either sp or set by a previous"
4201 "unwind_movsp directive"));
4205 /* Don't generate any opcodes, just record the information for later. */
4206 unwind
.fp_reg
= fp_reg
;
4208 if (sp_reg
== REG_SP
)
4209 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4211 unwind
.fp_offset
-= offset
;
4214 /* Parse an unwind_raw directive. */
4217 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4220 /* This is an arbitrary limit. */
4221 unsigned char op
[16];
4224 if (!unwind
.proc_start
)
4225 as_bad (MISSING_FNSTART
);
4228 if (exp
.X_op
== O_constant
4229 && skip_past_comma (&input_line_pointer
) != FAIL
)
4231 unwind
.frame_size
+= exp
.X_add_number
;
4235 exp
.X_op
= O_illegal
;
4237 if (exp
.X_op
!= O_constant
)
4239 as_bad (_("expected <offset>, <opcode>"));
4240 ignore_rest_of_line ();
4246 /* Parse the opcode. */
4251 as_bad (_("unwind opcode too long"));
4252 ignore_rest_of_line ();
4254 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4256 as_bad (_("invalid unwind opcode"));
4257 ignore_rest_of_line ();
4260 op
[count
++] = exp
.X_add_number
;
4262 /* Parse the next byte. */
4263 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4269 /* Add the opcode bytes in reverse order. */
4271 add_unwind_opcode (op
[count
], 1);
4273 demand_empty_rest_of_line ();
4277 /* Parse a .eabi_attribute directive. */
4280 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4282 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4284 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4285 attributes_set_explicitly
[tag
] = 1;
4288 /* Emit a tls fix for the symbol. */
4291 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4295 #ifdef md_flush_pending_output
4296 md_flush_pending_output ();
4299 #ifdef md_cons_align
4303 /* Since we're just labelling the code, there's no need to define a
4306 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4307 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4308 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4309 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4311 #endif /* OBJ_ELF */
4313 static void s_arm_arch (int);
4314 static void s_arm_object_arch (int);
4315 static void s_arm_cpu (int);
4316 static void s_arm_fpu (int);
4317 static void s_arm_arch_extension (int);
4322 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4329 if (exp
.X_op
== O_symbol
)
4330 exp
.X_op
= O_secrel
;
4332 emit_expr (&exp
, 4);
4334 while (*input_line_pointer
++ == ',');
4336 input_line_pointer
--;
4337 demand_empty_rest_of_line ();
4341 /* This table describes all the machine specific pseudo-ops the assembler
4342 has to support. The fields are:
4343 pseudo-op name without dot
4344 function to call to execute this pseudo-op
4345 Integer arg to pass to the function. */
4347 const pseudo_typeS md_pseudo_table
[] =
4349 /* Never called because '.req' does not start a line. */
4350 { "req", s_req
, 0 },
4351 /* Following two are likewise never called. */
4354 { "unreq", s_unreq
, 0 },
4355 { "bss", s_bss
, 0 },
4356 { "align", s_align
, 0 },
4357 { "arm", s_arm
, 0 },
4358 { "thumb", s_thumb
, 0 },
4359 { "code", s_code
, 0 },
4360 { "force_thumb", s_force_thumb
, 0 },
4361 { "thumb_func", s_thumb_func
, 0 },
4362 { "thumb_set", s_thumb_set
, 0 },
4363 { "even", s_even
, 0 },
4364 { "ltorg", s_ltorg
, 0 },
4365 { "pool", s_ltorg
, 0 },
4366 { "syntax", s_syntax
, 0 },
4367 { "cpu", s_arm_cpu
, 0 },
4368 { "arch", s_arm_arch
, 0 },
4369 { "object_arch", s_arm_object_arch
, 0 },
4370 { "fpu", s_arm_fpu
, 0 },
4371 { "arch_extension", s_arm_arch_extension
, 0 },
4373 { "word", s_arm_elf_cons
, 4 },
4374 { "long", s_arm_elf_cons
, 4 },
4375 { "inst.n", s_arm_elf_inst
, 2 },
4376 { "inst.w", s_arm_elf_inst
, 4 },
4377 { "inst", s_arm_elf_inst
, 0 },
4378 { "rel31", s_arm_rel31
, 0 },
4379 { "fnstart", s_arm_unwind_fnstart
, 0 },
4380 { "fnend", s_arm_unwind_fnend
, 0 },
4381 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4382 { "personality", s_arm_unwind_personality
, 0 },
4383 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4384 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4385 { "save", s_arm_unwind_save
, 0 },
4386 { "vsave", s_arm_unwind_save
, 1 },
4387 { "movsp", s_arm_unwind_movsp
, 0 },
4388 { "pad", s_arm_unwind_pad
, 0 },
4389 { "setfp", s_arm_unwind_setfp
, 0 },
4390 { "unwind_raw", s_arm_unwind_raw
, 0 },
4391 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4392 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4396 /* These are used for dwarf. */
4400 /* These are used for dwarf2. */
4401 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4402 { "loc", dwarf2_directive_loc
, 0 },
4403 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4405 { "extend", float_cons
, 'x' },
4406 { "ldouble", float_cons
, 'x' },
4407 { "packed", float_cons
, 'p' },
4409 {"secrel32", pe_directive_secrel
, 0},
4414 /* Parser functions used exclusively in instruction operands. */
4416 /* Generic immediate-value read function for use in insn parsing.
4417 STR points to the beginning of the immediate (the leading #);
4418 VAL receives the value; if the value is outside [MIN, MAX]
4419 issue an error. PREFIX_OPT is true if the immediate prefix is
4423 parse_immediate (char **str
, int *val
, int min
, int max
,
4424 bfd_boolean prefix_opt
)
4427 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4428 if (exp
.X_op
!= O_constant
)
4430 inst
.error
= _("constant expression required");
4434 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4436 inst
.error
= _("immediate value out of range");
4440 *val
= exp
.X_add_number
;
4444 /* Less-generic immediate-value read function with the possibility of loading a
4445 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4446 instructions. Puts the result directly in inst.operands[i]. */
4449 parse_big_immediate (char **str
, int i
)
4454 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4456 if (exp
.X_op
== O_constant
)
4458 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4459 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4460 O_constant. We have to be careful not to break compilation for
4461 32-bit X_add_number, though. */
4462 if ((exp
.X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4464 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4465 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4466 inst
.operands
[i
].regisimm
= 1;
4469 else if (exp
.X_op
== O_big
4470 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4472 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4474 /* Bignums have their least significant bits in
4475 generic_bignum[0]. Make sure we put 32 bits in imm and
4476 32 bits in reg, in a (hopefully) portable way. */
4477 gas_assert (parts
!= 0);
4479 /* Make sure that the number is not too big.
4480 PR 11972: Bignums can now be sign-extended to the
4481 size of a .octa so check that the out of range bits
4482 are all zero or all one. */
4483 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4485 LITTLENUM_TYPE m
= -1;
4487 if (generic_bignum
[parts
* 2] != 0
4488 && generic_bignum
[parts
* 2] != m
)
4491 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4492 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4496 inst
.operands
[i
].imm
= 0;
4497 for (j
= 0; j
< parts
; j
++, idx
++)
4498 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4499 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4500 inst
.operands
[i
].reg
= 0;
4501 for (j
= 0; j
< parts
; j
++, idx
++)
4502 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4503 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4504 inst
.operands
[i
].regisimm
= 1;
4514 /* Returns the pseudo-register number of an FPA immediate constant,
4515 or FAIL if there isn't a valid constant here. */
4518 parse_fpa_immediate (char ** str
)
4520 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4526 /* First try and match exact strings, this is to guarantee
4527 that some formats will work even for cross assembly. */
4529 for (i
= 0; fp_const
[i
]; i
++)
4531 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4535 *str
+= strlen (fp_const
[i
]);
4536 if (is_end_of_line
[(unsigned char) **str
])
4542 /* Just because we didn't get a match doesn't mean that the constant
4543 isn't valid, just that it is in a format that we don't
4544 automatically recognize. Try parsing it with the standard
4545 expression routines. */
4547 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4549 /* Look for a raw floating point number. */
4550 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4551 && is_end_of_line
[(unsigned char) *save_in
])
4553 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4555 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4557 if (words
[j
] != fp_values
[i
][j
])
4561 if (j
== MAX_LITTLENUMS
)
4569 /* Try and parse a more complex expression, this will probably fail
4570 unless the code uses a floating point prefix (eg "0f"). */
4571 save_in
= input_line_pointer
;
4572 input_line_pointer
= *str
;
4573 if (expression (&exp
) == absolute_section
4574 && exp
.X_op
== O_big
4575 && exp
.X_add_number
< 0)
4577 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4579 if (gen_to_words (words
, 5, (long) 15) == 0)
4581 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4583 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4585 if (words
[j
] != fp_values
[i
][j
])
4589 if (j
== MAX_LITTLENUMS
)
4591 *str
= input_line_pointer
;
4592 input_line_pointer
= save_in
;
4599 *str
= input_line_pointer
;
4600 input_line_pointer
= save_in
;
4601 inst
.error
= _("invalid FPA immediate expression");
4605 /* Returns 1 if a number has "quarter-precision" float format
4606 0baBbbbbbc defgh000 00000000 00000000. */
4609 is_quarter_float (unsigned imm
)
4611 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4612 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4615 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4616 0baBbbbbbc defgh000 00000000 00000000.
4617 The zero and minus-zero cases need special handling, since they can't be
4618 encoded in the "quarter-precision" float format, but can nonetheless be
4619 loaded as integer constants. */
4622 parse_qfloat_immediate (char **ccp
, int *immed
)
4626 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4627 int found_fpchar
= 0;
4629 skip_past_char (&str
, '#');
4631 /* We must not accidentally parse an integer as a floating-point number. Make
4632 sure that the value we parse is not an integer by checking for special
4633 characters '.' or 'e'.
4634 FIXME: This is a horrible hack, but doing better is tricky because type
4635 information isn't in a very usable state at parse time. */
4637 skip_whitespace (fpnum
);
4639 if (strncmp (fpnum
, "0x", 2) == 0)
4643 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4644 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4654 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4656 unsigned fpword
= 0;
4659 /* Our FP word must be 32 bits (single-precision FP). */
4660 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4662 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4666 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4679 /* Shift operands. */
4682 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4685 struct asm_shift_name
4688 enum shift_kind kind
;
4691 /* Third argument to parse_shift. */
4692 enum parse_shift_mode
4694 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4695 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4696 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4697 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4698 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4701 /* Parse a <shift> specifier on an ARM data processing instruction.
4702 This has three forms:
4704 (LSL|LSR|ASL|ASR|ROR) Rs
4705 (LSL|LSR|ASL|ASR|ROR) #imm
4708 Note that ASL is assimilated to LSL in the instruction encoding, and
4709 RRX to ROR #0 (which cannot be written as such). */
4712 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4714 const struct asm_shift_name
*shift_name
;
4715 enum shift_kind shift
;
4720 for (p
= *str
; ISALPHA (*p
); p
++)
4725 inst
.error
= _("shift expression expected");
4729 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4732 if (shift_name
== NULL
)
4734 inst
.error
= _("shift expression expected");
4738 shift
= shift_name
->kind
;
4742 case NO_SHIFT_RESTRICT
:
4743 case SHIFT_IMMEDIATE
: break;
4745 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4746 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4748 inst
.error
= _("'LSL' or 'ASR' required");
4753 case SHIFT_LSL_IMMEDIATE
:
4754 if (shift
!= SHIFT_LSL
)
4756 inst
.error
= _("'LSL' required");
4761 case SHIFT_ASR_IMMEDIATE
:
4762 if (shift
!= SHIFT_ASR
)
4764 inst
.error
= _("'ASR' required");
4772 if (shift
!= SHIFT_RRX
)
4774 /* Whitespace can appear here if the next thing is a bare digit. */
4775 skip_whitespace (p
);
4777 if (mode
== NO_SHIFT_RESTRICT
4778 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4780 inst
.operands
[i
].imm
= reg
;
4781 inst
.operands
[i
].immisreg
= 1;
4783 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4786 inst
.operands
[i
].shift_kind
= shift
;
4787 inst
.operands
[i
].shifted
= 1;
4792 /* Parse a <shifter_operand> for an ARM data processing instruction:
4795 #<immediate>, <rotate>
4799 where <shift> is defined by parse_shift above, and <rotate> is a
4800 multiple of 2 between 0 and 30. Validation of immediate operands
4801 is deferred to md_apply_fix. */
4804 parse_shifter_operand (char **str
, int i
)
4809 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4811 inst
.operands
[i
].reg
= value
;
4812 inst
.operands
[i
].isreg
= 1;
4814 /* parse_shift will override this if appropriate */
4815 inst
.reloc
.exp
.X_op
= O_constant
;
4816 inst
.reloc
.exp
.X_add_number
= 0;
4818 if (skip_past_comma (str
) == FAIL
)
4821 /* Shift operation on register. */
4822 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4825 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4828 if (skip_past_comma (str
) == SUCCESS
)
4830 /* #x, y -- ie explicit rotation by Y. */
4831 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4834 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4836 inst
.error
= _("constant expression expected");
4840 value
= exp
.X_add_number
;
4841 if (value
< 0 || value
> 30 || value
% 2 != 0)
4843 inst
.error
= _("invalid rotation");
4846 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4848 inst
.error
= _("invalid constant");
4852 /* Convert to decoded value. md_apply_fix will put it back. */
4853 inst
.reloc
.exp
.X_add_number
4854 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4855 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4858 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4859 inst
.reloc
.pc_rel
= 0;
4863 /* Group relocation information. Each entry in the table contains the
4864 textual name of the relocation as may appear in assembler source
4865 and must end with a colon.
4866 Along with this textual name are the relocation codes to be used if
4867 the corresponding instruction is an ALU instruction (ADD or SUB only),
4868 an LDR, an LDRS, or an LDC. */
4870 struct group_reloc_table_entry
4881 /* Varieties of non-ALU group relocation. */
4888 static struct group_reloc_table_entry group_reloc_table
[] =
4889 { /* Program counter relative: */
4891 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4896 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4897 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4898 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4899 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4901 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4906 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4907 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4908 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4909 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4911 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4912 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4913 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4914 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4915 /* Section base relative */
4917 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4922 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4923 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4924 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4925 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4927 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4932 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4933 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4934 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4935 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4937 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4938 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4939 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4940 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4942 /* Given the address of a pointer pointing to the textual name of a group
4943 relocation as may appear in assembler source, attempt to find its details
4944 in group_reloc_table. The pointer will be updated to the character after
4945 the trailing colon. On failure, FAIL will be returned; SUCCESS
4946 otherwise. On success, *entry will be updated to point at the relevant
4947 group_reloc_table entry. */
4950 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4953 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4955 int length
= strlen (group_reloc_table
[i
].name
);
4957 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4958 && (*str
)[length
] == ':')
4960 *out
= &group_reloc_table
[i
];
4961 *str
+= (length
+ 1);
4969 /* Parse a <shifter_operand> for an ARM data processing instruction
4970 (as for parse_shifter_operand) where group relocations are allowed:
4973 #<immediate>, <rotate>
4974 #:<group_reloc>:<expression>
4978 where <group_reloc> is one of the strings defined in group_reloc_table.
4979 The hashes are optional.
4981 Everything else is as for parse_shifter_operand. */
4983 static parse_operand_result
4984 parse_shifter_operand_group_reloc (char **str
, int i
)
4986 /* Determine if we have the sequence of characters #: or just :
4987 coming next. If we do, then we check for a group relocation.
4988 If we don't, punt the whole lot to parse_shifter_operand. */
4990 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4991 || (*str
)[0] == ':')
4993 struct group_reloc_table_entry
*entry
;
4995 if ((*str
)[0] == '#')
5000 /* Try to parse a group relocation. Anything else is an error. */
5001 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5003 inst
.error
= _("unknown group relocation");
5004 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5007 /* We now have the group relocation table entry corresponding to
5008 the name in the assembler source. Next, we parse the expression. */
5009 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5010 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5012 /* Record the relocation type (always the ALU variant here). */
5013 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5014 gas_assert (inst
.reloc
.type
!= 0);
5016 return PARSE_OPERAND_SUCCESS
;
5019 return parse_shifter_operand (str
, i
) == SUCCESS
5020 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5022 /* Never reached. */
5025 /* Parse a Neon alignment expression. Information is written to
5026 inst.operands[i]. We assume the initial ':' has been skipped.
5028 align .imm = align << 8, .immisalign=1, .preind=0 */
5029 static parse_operand_result
5030 parse_neon_alignment (char **str
, int i
)
5035 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5037 if (exp
.X_op
!= O_constant
)
5039 inst
.error
= _("alignment must be constant");
5040 return PARSE_OPERAND_FAIL
;
5043 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5044 inst
.operands
[i
].immisalign
= 1;
5045 /* Alignments are not pre-indexes. */
5046 inst
.operands
[i
].preind
= 0;
5049 return PARSE_OPERAND_SUCCESS
;
5052 /* Parse all forms of an ARM address expression. Information is written
5053 to inst.operands[i] and/or inst.reloc.
5055 Preindexed addressing (.preind=1):
5057 [Rn, #offset] .reg=Rn .reloc.exp=offset
5058 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5059 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5060 .shift_kind=shift .reloc.exp=shift_imm
5062 These three may have a trailing ! which causes .writeback to be set also.
5064 Postindexed addressing (.postind=1, .writeback=1):
5066 [Rn], #offset .reg=Rn .reloc.exp=offset
5067 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5068 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5069 .shift_kind=shift .reloc.exp=shift_imm
5071 Unindexed addressing (.preind=0, .postind=0):
5073 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5077 [Rn]{!} shorthand for [Rn,#0]{!}
5078 =immediate .isreg=0 .reloc.exp=immediate
5079 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5081 It is the caller's responsibility to check for addressing modes not
5082 supported by the instruction, and to set inst.reloc.type. */
5084 static parse_operand_result
5085 parse_address_main (char **str
, int i
, int group_relocations
,
5086 group_reloc_type group_type
)
5091 if (skip_past_char (&p
, '[') == FAIL
)
5093 if (skip_past_char (&p
, '=') == FAIL
)
5095 /* Bare address - translate to PC-relative offset. */
5096 inst
.reloc
.pc_rel
= 1;
5097 inst
.operands
[i
].reg
= REG_PC
;
5098 inst
.operands
[i
].isreg
= 1;
5099 inst
.operands
[i
].preind
= 1;
5101 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5103 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5104 return PARSE_OPERAND_FAIL
;
5107 return PARSE_OPERAND_SUCCESS
;
5110 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5112 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5113 return PARSE_OPERAND_FAIL
;
5115 inst
.operands
[i
].reg
= reg
;
5116 inst
.operands
[i
].isreg
= 1;
5118 if (skip_past_comma (&p
) == SUCCESS
)
5120 inst
.operands
[i
].preind
= 1;
5123 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5125 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5127 inst
.operands
[i
].imm
= reg
;
5128 inst
.operands
[i
].immisreg
= 1;
5130 if (skip_past_comma (&p
) == SUCCESS
)
5131 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5132 return PARSE_OPERAND_FAIL
;
5134 else if (skip_past_char (&p
, ':') == SUCCESS
)
5136 /* FIXME: '@' should be used here, but it's filtered out by generic
5137 code before we get to see it here. This may be subject to
5139 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5141 if (result
!= PARSE_OPERAND_SUCCESS
)
5146 if (inst
.operands
[i
].negative
)
5148 inst
.operands
[i
].negative
= 0;
5152 if (group_relocations
5153 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5155 struct group_reloc_table_entry
*entry
;
5157 /* Skip over the #: or : sequence. */
5163 /* Try to parse a group relocation. Anything else is an
5165 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5167 inst
.error
= _("unknown group relocation");
5168 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5171 /* We now have the group relocation table entry corresponding to
5172 the name in the assembler source. Next, we parse the
5174 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5175 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5177 /* Record the relocation type. */
5181 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5185 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5189 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5196 if (inst
.reloc
.type
== 0)
5198 inst
.error
= _("this group relocation is not allowed on this instruction");
5199 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5205 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5206 return PARSE_OPERAND_FAIL
;
5207 /* If the offset is 0, find out if it's a +0 or -0. */
5208 if (inst
.reloc
.exp
.X_op
== O_constant
5209 && inst
.reloc
.exp
.X_add_number
== 0)
5211 skip_whitespace (q
);
5215 skip_whitespace (q
);
5218 inst
.operands
[i
].negative
= 1;
5223 else if (skip_past_char (&p
, ':') == SUCCESS
)
5225 /* FIXME: '@' should be used here, but it's filtered out by generic code
5226 before we get to see it here. This may be subject to change. */
5227 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5229 if (result
!= PARSE_OPERAND_SUCCESS
)
5233 if (skip_past_char (&p
, ']') == FAIL
)
5235 inst
.error
= _("']' expected");
5236 return PARSE_OPERAND_FAIL
;
5239 if (skip_past_char (&p
, '!') == SUCCESS
)
5240 inst
.operands
[i
].writeback
= 1;
5242 else if (skip_past_comma (&p
) == SUCCESS
)
5244 if (skip_past_char (&p
, '{') == SUCCESS
)
5246 /* [Rn], {expr} - unindexed, with option */
5247 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5248 0, 255, TRUE
) == FAIL
)
5249 return PARSE_OPERAND_FAIL
;
5251 if (skip_past_char (&p
, '}') == FAIL
)
5253 inst
.error
= _("'}' expected at end of 'option' field");
5254 return PARSE_OPERAND_FAIL
;
5256 if (inst
.operands
[i
].preind
)
5258 inst
.error
= _("cannot combine index with option");
5259 return PARSE_OPERAND_FAIL
;
5262 return PARSE_OPERAND_SUCCESS
;
5266 inst
.operands
[i
].postind
= 1;
5267 inst
.operands
[i
].writeback
= 1;
5269 if (inst
.operands
[i
].preind
)
5271 inst
.error
= _("cannot combine pre- and post-indexing");
5272 return PARSE_OPERAND_FAIL
;
5276 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5278 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5280 /* We might be using the immediate for alignment already. If we
5281 are, OR the register number into the low-order bits. */
5282 if (inst
.operands
[i
].immisalign
)
5283 inst
.operands
[i
].imm
|= reg
;
5285 inst
.operands
[i
].imm
= reg
;
5286 inst
.operands
[i
].immisreg
= 1;
5288 if (skip_past_comma (&p
) == SUCCESS
)
5289 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5290 return PARSE_OPERAND_FAIL
;
5295 if (inst
.operands
[i
].negative
)
5297 inst
.operands
[i
].negative
= 0;
5300 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5301 return PARSE_OPERAND_FAIL
;
5302 /* If the offset is 0, find out if it's a +0 or -0. */
5303 if (inst
.reloc
.exp
.X_op
== O_constant
5304 && inst
.reloc
.exp
.X_add_number
== 0)
5306 skip_whitespace (q
);
5310 skip_whitespace (q
);
5313 inst
.operands
[i
].negative
= 1;
5319 /* If at this point neither .preind nor .postind is set, we have a
5320 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5321 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5323 inst
.operands
[i
].preind
= 1;
5324 inst
.reloc
.exp
.X_op
= O_constant
;
5325 inst
.reloc
.exp
.X_add_number
= 0;
5328 return PARSE_OPERAND_SUCCESS
;
5332 parse_address (char **str
, int i
)
5334 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5338 static parse_operand_result
5339 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5341 return parse_address_main (str
, i
, 1, type
);
5344 /* Parse an operand for a MOVW or MOVT instruction. */
5346 parse_half (char **str
)
5351 skip_past_char (&p
, '#');
5352 if (strncasecmp (p
, ":lower16:", 9) == 0)
5353 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5354 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5355 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5357 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5360 skip_whitespace (p
);
5363 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5366 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5368 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5370 inst
.error
= _("constant expression expected");
5373 if (inst
.reloc
.exp
.X_add_number
< 0
5374 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5376 inst
.error
= _("immediate value out of range");
5384 /* Miscellaneous. */
5386 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5387 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5389 parse_psr (char **str
, bfd_boolean lhs
)
5392 unsigned long psr_field
;
5393 const struct asm_psr
*psr
;
5395 bfd_boolean is_apsr
= FALSE
;
5396 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5398 /* PR gas/12698: If the user has specified -march=all then m_profile will
5399 be TRUE, but we want to ignore it in this case as we are building for any
5400 CPU type, including non-m variants. */
5401 if (selected_cpu
.core
== arm_arch_any
.core
)
5404 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5405 feature for ease of use and backwards compatibility. */
5407 if (strncasecmp (p
, "SPSR", 4) == 0)
5410 goto unsupported_psr
;
5412 psr_field
= SPSR_BIT
;
5414 else if (strncasecmp (p
, "CPSR", 4) == 0)
5417 goto unsupported_psr
;
5421 else if (strncasecmp (p
, "APSR", 4) == 0)
5423 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5424 and ARMv7-R architecture CPUs. */
5433 while (ISALNUM (*p
) || *p
== '_');
5435 if (strncasecmp (start
, "iapsr", 5) == 0
5436 || strncasecmp (start
, "eapsr", 5) == 0
5437 || strncasecmp (start
, "xpsr", 4) == 0
5438 || strncasecmp (start
, "psr", 3) == 0)
5439 p
= start
+ strcspn (start
, "rR") + 1;
5441 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5447 /* If APSR is being written, a bitfield may be specified. Note that
5448 APSR itself is handled above. */
5449 if (psr
->field
<= 3)
5451 psr_field
= psr
->field
;
5457 /* M-profile MSR instructions have the mask field set to "10", except
5458 *PSR variants which modify APSR, which may use a different mask (and
5459 have been handled already). Do that by setting the PSR_f field
5461 return psr
->field
| (lhs
? PSR_f
: 0);
5464 goto unsupported_psr
;
5470 /* A suffix follows. */
5476 while (ISALNUM (*p
) || *p
== '_');
5480 /* APSR uses a notation for bits, rather than fields. */
5481 unsigned int nzcvq_bits
= 0;
5482 unsigned int g_bit
= 0;
5485 for (bit
= start
; bit
!= p
; bit
++)
5487 switch (TOLOWER (*bit
))
5490 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5494 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5498 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5502 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5506 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5510 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5514 inst
.error
= _("unexpected bit specified after APSR");
5519 if (nzcvq_bits
== 0x1f)
5524 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5526 inst
.error
= _("selected processor does not "
5527 "support DSP extension");
5534 if ((nzcvq_bits
& 0x20) != 0
5535 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5536 || (g_bit
& 0x2) != 0)
5538 inst
.error
= _("bad bitmask specified after APSR");
5544 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5549 psr_field
|= psr
->field
;
5555 goto error
; /* Garbage after "[CS]PSR". */
5557 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5558 is deprecated, but allow it anyway. */
5562 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5565 else if (!m_profile
)
5566 /* These bits are never right for M-profile devices: don't set them
5567 (only code paths which read/write APSR reach here). */
5568 psr_field
|= (PSR_c
| PSR_f
);
5574 inst
.error
= _("selected processor does not support requested special "
5575 "purpose register");
5579 inst
.error
= _("flag for {c}psr instruction expected");
5583 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5584 value suitable for splatting into the AIF field of the instruction. */
5587 parse_cps_flags (char **str
)
5596 case '\0': case ',':
5599 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5600 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5601 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5604 inst
.error
= _("unrecognized CPS flag");
5609 if (saw_a_flag
== 0)
5611 inst
.error
= _("missing CPS flags");
5619 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5620 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5623 parse_endian_specifier (char **str
)
5628 if (strncasecmp (s
, "BE", 2))
5630 else if (strncasecmp (s
, "LE", 2))
5634 inst
.error
= _("valid endian specifiers are be or le");
5638 if (ISALNUM (s
[2]) || s
[2] == '_')
5640 inst
.error
= _("valid endian specifiers are be or le");
5645 return little_endian
;
5648 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5649 value suitable for poking into the rotate field of an sxt or sxta
5650 instruction, or FAIL on error. */
5653 parse_ror (char **str
)
5658 if (strncasecmp (s
, "ROR", 3) == 0)
5662 inst
.error
= _("missing rotation field after comma");
5666 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5671 case 0: *str
= s
; return 0x0;
5672 case 8: *str
= s
; return 0x1;
5673 case 16: *str
= s
; return 0x2;
5674 case 24: *str
= s
; return 0x3;
5677 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5682 /* Parse a conditional code (from conds[] below). The value returned is in the
5683 range 0 .. 14, or FAIL. */
5685 parse_cond (char **str
)
5688 const struct asm_cond
*c
;
5690 /* Condition codes are always 2 characters, so matching up to
5691 3 characters is sufficient. */
5696 while (ISALPHA (*q
) && n
< 3)
5698 cond
[n
] = TOLOWER (*q
);
5703 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5706 inst
.error
= _("condition required");
5714 /* Parse an option for a barrier instruction. Returns the encoding for the
5717 parse_barrier (char **str
)
5720 const struct asm_barrier_opt
*o
;
5723 while (ISALPHA (*q
))
5726 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5735 /* Parse the operands of a table branch instruction. Similar to a memory
5738 parse_tb (char **str
)
5743 if (skip_past_char (&p
, '[') == FAIL
)
5745 inst
.error
= _("'[' expected");
5749 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5751 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5754 inst
.operands
[0].reg
= reg
;
5756 if (skip_past_comma (&p
) == FAIL
)
5758 inst
.error
= _("',' expected");
5762 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5764 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5767 inst
.operands
[0].imm
= reg
;
5769 if (skip_past_comma (&p
) == SUCCESS
)
5771 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5773 if (inst
.reloc
.exp
.X_add_number
!= 1)
5775 inst
.error
= _("invalid shift");
5778 inst
.operands
[0].shifted
= 1;
5781 if (skip_past_char (&p
, ']') == FAIL
)
5783 inst
.error
= _("']' expected");
5790 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5791 information on the types the operands can take and how they are encoded.
5792 Up to four operands may be read; this function handles setting the
5793 ".present" field for each read operand itself.
5794 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5795 else returns FAIL. */
5798 parse_neon_mov (char **str
, int *which_operand
)
5800 int i
= *which_operand
, val
;
5801 enum arm_reg_type rtype
;
5803 struct neon_type_el optype
;
5805 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5807 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5808 inst
.operands
[i
].reg
= val
;
5809 inst
.operands
[i
].isscalar
= 1;
5810 inst
.operands
[i
].vectype
= optype
;
5811 inst
.operands
[i
++].present
= 1;
5813 if (skip_past_comma (&ptr
) == FAIL
)
5816 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5819 inst
.operands
[i
].reg
= val
;
5820 inst
.operands
[i
].isreg
= 1;
5821 inst
.operands
[i
].present
= 1;
5823 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5826 /* Cases 0, 1, 2, 3, 5 (D only). */
5827 if (skip_past_comma (&ptr
) == FAIL
)
5830 inst
.operands
[i
].reg
= val
;
5831 inst
.operands
[i
].isreg
= 1;
5832 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5833 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5834 inst
.operands
[i
].isvec
= 1;
5835 inst
.operands
[i
].vectype
= optype
;
5836 inst
.operands
[i
++].present
= 1;
5838 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5840 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5841 Case 13: VMOV <Sd>, <Rm> */
5842 inst
.operands
[i
].reg
= val
;
5843 inst
.operands
[i
].isreg
= 1;
5844 inst
.operands
[i
].present
= 1;
5846 if (rtype
== REG_TYPE_NQ
)
5848 first_error (_("can't use Neon quad register here"));
5851 else if (rtype
!= REG_TYPE_VFS
)
5854 if (skip_past_comma (&ptr
) == FAIL
)
5856 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5858 inst
.operands
[i
].reg
= val
;
5859 inst
.operands
[i
].isreg
= 1;
5860 inst
.operands
[i
].present
= 1;
5863 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5866 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5867 Case 1: VMOV<c><q> <Dd>, <Dm>
5868 Case 8: VMOV.F32 <Sd>, <Sm>
5869 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5871 inst
.operands
[i
].reg
= val
;
5872 inst
.operands
[i
].isreg
= 1;
5873 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5874 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5875 inst
.operands
[i
].isvec
= 1;
5876 inst
.operands
[i
].vectype
= optype
;
5877 inst
.operands
[i
].present
= 1;
5879 if (skip_past_comma (&ptr
) == SUCCESS
)
5884 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5887 inst
.operands
[i
].reg
= val
;
5888 inst
.operands
[i
].isreg
= 1;
5889 inst
.operands
[i
++].present
= 1;
5891 if (skip_past_comma (&ptr
) == FAIL
)
5894 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5897 inst
.operands
[i
].reg
= val
;
5898 inst
.operands
[i
].isreg
= 1;
5899 inst
.operands
[i
++].present
= 1;
5902 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5903 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5904 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5905 Case 10: VMOV.F32 <Sd>, #<imm>
5906 Case 11: VMOV.F64 <Dd>, #<imm> */
5907 inst
.operands
[i
].immisfloat
= 1;
5908 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5909 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5910 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5914 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5918 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5921 inst
.operands
[i
].reg
= val
;
5922 inst
.operands
[i
].isreg
= 1;
5923 inst
.operands
[i
++].present
= 1;
5925 if (skip_past_comma (&ptr
) == FAIL
)
5928 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5930 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5931 inst
.operands
[i
].reg
= val
;
5932 inst
.operands
[i
].isscalar
= 1;
5933 inst
.operands
[i
].present
= 1;
5934 inst
.operands
[i
].vectype
= optype
;
5936 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5938 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5939 inst
.operands
[i
].reg
= val
;
5940 inst
.operands
[i
].isreg
= 1;
5941 inst
.operands
[i
++].present
= 1;
5943 if (skip_past_comma (&ptr
) == FAIL
)
5946 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5949 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5953 inst
.operands
[i
].reg
= val
;
5954 inst
.operands
[i
].isreg
= 1;
5955 inst
.operands
[i
].isvec
= 1;
5956 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5957 inst
.operands
[i
].vectype
= optype
;
5958 inst
.operands
[i
].present
= 1;
5960 if (rtype
== REG_TYPE_VFS
)
5964 if (skip_past_comma (&ptr
) == FAIL
)
5966 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5969 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5972 inst
.operands
[i
].reg
= val
;
5973 inst
.operands
[i
].isreg
= 1;
5974 inst
.operands
[i
].isvec
= 1;
5975 inst
.operands
[i
].issingle
= 1;
5976 inst
.operands
[i
].vectype
= optype
;
5977 inst
.operands
[i
].present
= 1;
5980 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5984 inst
.operands
[i
].reg
= val
;
5985 inst
.operands
[i
].isreg
= 1;
5986 inst
.operands
[i
].isvec
= 1;
5987 inst
.operands
[i
].issingle
= 1;
5988 inst
.operands
[i
].vectype
= optype
;
5989 inst
.operands
[i
++].present
= 1;
5994 first_error (_("parse error"));
5998 /* Successfully parsed the operands. Update args. */
6004 first_error (_("expected comma"));
6008 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6012 /* Use this macro when the operand constraints are different
6013 for ARM and THUMB (e.g. ldrd). */
6014 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6015 ((arm_operand) | ((thumb_operand) << 16))
6017 /* Matcher codes for parse_operands. */
6018 enum operand_parse_code
6020 OP_stop
, /* end of line */
6022 OP_RR
, /* ARM register */
6023 OP_RRnpc
, /* ARM register, not r15 */
6024 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6025 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6026 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6027 optional trailing ! */
6028 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6029 OP_RCP
, /* Coprocessor number */
6030 OP_RCN
, /* Coprocessor register */
6031 OP_RF
, /* FPA register */
6032 OP_RVS
, /* VFP single precision register */
6033 OP_RVD
, /* VFP double precision register (0..15) */
6034 OP_RND
, /* Neon double precision register (0..31) */
6035 OP_RNQ
, /* Neon quad precision register */
6036 OP_RVSD
, /* VFP single or double precision register */
6037 OP_RNDQ
, /* Neon double or quad precision register */
6038 OP_RNSDQ
, /* Neon single, double or quad precision register */
6039 OP_RNSC
, /* Neon scalar D[X] */
6040 OP_RVC
, /* VFP control register */
6041 OP_RMF
, /* Maverick F register */
6042 OP_RMD
, /* Maverick D register */
6043 OP_RMFX
, /* Maverick FX register */
6044 OP_RMDX
, /* Maverick DX register */
6045 OP_RMAX
, /* Maverick AX register */
6046 OP_RMDS
, /* Maverick DSPSC register */
6047 OP_RIWR
, /* iWMMXt wR register */
6048 OP_RIWC
, /* iWMMXt wC register */
6049 OP_RIWG
, /* iWMMXt wCG register */
6050 OP_RXA
, /* XScale accumulator register */
6052 OP_REGLST
, /* ARM register list */
6053 OP_VRSLST
, /* VFP single-precision register list */
6054 OP_VRDLST
, /* VFP double-precision register list */
6055 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6056 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6057 OP_NSTRLST
, /* Neon element/structure list */
6059 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6060 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6061 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6062 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6063 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6064 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6065 OP_VMOV
, /* Neon VMOV operands. */
6066 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6067 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6068 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6070 OP_I0
, /* immediate zero */
6071 OP_I7
, /* immediate value 0 .. 7 */
6072 OP_I15
, /* 0 .. 15 */
6073 OP_I16
, /* 1 .. 16 */
6074 OP_I16z
, /* 0 .. 16 */
6075 OP_I31
, /* 0 .. 31 */
6076 OP_I31w
, /* 0 .. 31, optional trailing ! */
6077 OP_I32
, /* 1 .. 32 */
6078 OP_I32z
, /* 0 .. 32 */
6079 OP_I63
, /* 0 .. 63 */
6080 OP_I63s
, /* -64 .. 63 */
6081 OP_I64
, /* 1 .. 64 */
6082 OP_I64z
, /* 0 .. 64 */
6083 OP_I255
, /* 0 .. 255 */
6085 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6086 OP_I7b
, /* 0 .. 7 */
6087 OP_I15b
, /* 0 .. 15 */
6088 OP_I31b
, /* 0 .. 31 */
6090 OP_SH
, /* shifter operand */
6091 OP_SHG
, /* shifter operand with possible group relocation */
6092 OP_ADDR
, /* Memory address expression (any mode) */
6093 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6094 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6095 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6096 OP_EXP
, /* arbitrary expression */
6097 OP_EXPi
, /* same, with optional immediate prefix */
6098 OP_EXPr
, /* same, with optional relocation suffix */
6099 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6101 OP_CPSF
, /* CPS flags */
6102 OP_ENDI
, /* Endianness specifier */
6103 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6104 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6105 OP_COND
, /* conditional code */
6106 OP_TB
, /* Table branch. */
6108 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6110 OP_RRnpc_I0
, /* ARM register or literal 0 */
6111 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6112 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6113 OP_RF_IF
, /* FPA register or immediate */
6114 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6115 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6117 /* Optional operands. */
6118 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6119 OP_oI31b
, /* 0 .. 31 */
6120 OP_oI32b
, /* 1 .. 32 */
6121 OP_oI32z
, /* 0 .. 32 */
6122 OP_oIffffb
, /* 0 .. 65535 */
6123 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6125 OP_oRR
, /* ARM register */
6126 OP_oRRnpc
, /* ARM register, not the PC */
6127 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6128 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6129 OP_oRND
, /* Optional Neon double precision register */
6130 OP_oRNQ
, /* Optional Neon quad precision register */
6131 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6132 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6133 OP_oSHll
, /* LSL immediate */
6134 OP_oSHar
, /* ASR immediate */
6135 OP_oSHllar
, /* LSL or ASR immediate */
6136 OP_oROR
, /* ROR 0/8/16/24 */
6137 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6139 /* Some pre-defined mixed (ARM/THUMB) operands. */
6140 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6141 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6142 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6144 OP_FIRST_OPTIONAL
= OP_oI7b
6147 /* Generic instruction operand parser. This does no encoding and no
6148 semantic validation; it merely squirrels values away in the inst
6149 structure. Returns SUCCESS or FAIL depending on whether the
6150 specified grammar matched. */
6152 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6154 unsigned const int *upat
= pattern
;
6155 char *backtrack_pos
= 0;
6156 const char *backtrack_error
= 0;
6157 int i
, val
, backtrack_index
= 0;
6158 enum arm_reg_type rtype
;
6159 parse_operand_result result
;
6160 unsigned int op_parse_code
;
6162 #define po_char_or_fail(chr) \
6165 if (skip_past_char (&str, chr) == FAIL) \
6170 #define po_reg_or_fail(regtype) \
6173 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6174 & inst.operands[i].vectype); \
6177 first_error (_(reg_expected_msgs[regtype])); \
6180 inst.operands[i].reg = val; \
6181 inst.operands[i].isreg = 1; \
6182 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6183 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6184 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6185 || rtype == REG_TYPE_VFD \
6186 || rtype == REG_TYPE_NQ); \
6190 #define po_reg_or_goto(regtype, label) \
6193 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6194 & inst.operands[i].vectype); \
6198 inst.operands[i].reg = val; \
6199 inst.operands[i].isreg = 1; \
6200 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6201 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6202 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6203 || rtype == REG_TYPE_VFD \
6204 || rtype == REG_TYPE_NQ); \
6208 #define po_imm_or_fail(min, max, popt) \
6211 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6213 inst.operands[i].imm = val; \
6217 #define po_scalar_or_goto(elsz, label) \
6220 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6223 inst.operands[i].reg = val; \
6224 inst.operands[i].isscalar = 1; \
6228 #define po_misc_or_fail(expr) \
6236 #define po_misc_or_fail_no_backtrack(expr) \
6240 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6241 backtrack_pos = 0; \
6242 if (result != PARSE_OPERAND_SUCCESS) \
6247 #define po_barrier_or_imm(str) \
6250 val = parse_barrier (&str); \
6253 if (ISALPHA (*str)) \
6260 if ((inst.instruction & 0xf0) == 0x60 \
6263 /* ISB can only take SY as an option. */ \
6264 inst.error = _("invalid barrier type"); \
6271 skip_whitespace (str
);
6273 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6275 op_parse_code
= upat
[i
];
6276 if (op_parse_code
>= 1<<16)
6277 op_parse_code
= thumb
? (op_parse_code
>> 16)
6278 : (op_parse_code
& ((1<<16)-1));
6280 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6282 /* Remember where we are in case we need to backtrack. */
6283 gas_assert (!backtrack_pos
);
6284 backtrack_pos
= str
;
6285 backtrack_error
= inst
.error
;
6286 backtrack_index
= i
;
6289 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6290 po_char_or_fail (',');
6292 switch (op_parse_code
)
6300 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6301 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6302 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6303 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6304 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6305 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6307 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6309 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6311 /* Also accept generic coprocessor regs for unknown registers. */
6313 po_reg_or_fail (REG_TYPE_CN
);
6315 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6316 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6317 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6318 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6319 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6320 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6321 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6322 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6323 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6324 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6326 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6328 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6329 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6331 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6333 /* Neon scalar. Using an element size of 8 means that some invalid
6334 scalars are accepted here, so deal with those in later code. */
6335 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6339 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6342 po_imm_or_fail (0, 0, TRUE
);
6347 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6352 po_scalar_or_goto (8, try_rr
);
6355 po_reg_or_fail (REG_TYPE_RN
);
6361 po_scalar_or_goto (8, try_nsdq
);
6364 po_reg_or_fail (REG_TYPE_NSDQ
);
6370 po_scalar_or_goto (8, try_ndq
);
6373 po_reg_or_fail (REG_TYPE_NDQ
);
6379 po_scalar_or_goto (8, try_vfd
);
6382 po_reg_or_fail (REG_TYPE_VFD
);
6387 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6388 not careful then bad things might happen. */
6389 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6394 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6397 /* There's a possibility of getting a 64-bit immediate here, so
6398 we need special handling. */
6399 if (parse_big_immediate (&str
, i
) == FAIL
)
6401 inst
.error
= _("immediate value is out of range");
6409 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6412 po_imm_or_fail (0, 63, TRUE
);
6417 po_char_or_fail ('[');
6418 po_reg_or_fail (REG_TYPE_RN
);
6419 po_char_or_fail (']');
6425 po_reg_or_fail (REG_TYPE_RN
);
6426 if (skip_past_char (&str
, '!') == SUCCESS
)
6427 inst
.operands
[i
].writeback
= 1;
6431 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6432 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6433 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6434 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6435 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6436 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6437 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6438 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6439 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6440 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6441 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6442 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6444 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6446 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6447 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6449 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6450 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6451 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6452 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6454 /* Immediate variants */
6456 po_char_or_fail ('{');
6457 po_imm_or_fail (0, 255, TRUE
);
6458 po_char_or_fail ('}');
6462 /* The expression parser chokes on a trailing !, so we have
6463 to find it first and zap it. */
6466 while (*s
&& *s
!= ',')
6471 inst
.operands
[i
].writeback
= 1;
6473 po_imm_or_fail (0, 31, TRUE
);
6481 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6486 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6491 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6493 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6495 val
= parse_reloc (&str
);
6498 inst
.error
= _("unrecognized relocation suffix");
6501 else if (val
!= BFD_RELOC_UNUSED
)
6503 inst
.operands
[i
].imm
= val
;
6504 inst
.operands
[i
].hasreloc
= 1;
6509 /* Operand for MOVW or MOVT. */
6511 po_misc_or_fail (parse_half (&str
));
6514 /* Register or expression. */
6515 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6516 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6518 /* Register or immediate. */
6519 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6520 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6522 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6524 if (!is_immediate_prefix (*str
))
6527 val
= parse_fpa_immediate (&str
);
6530 /* FPA immediates are encoded as registers 8-15.
6531 parse_fpa_immediate has already applied the offset. */
6532 inst
.operands
[i
].reg
= val
;
6533 inst
.operands
[i
].isreg
= 1;
6536 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6537 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6539 /* Two kinds of register. */
6542 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6544 || (rege
->type
!= REG_TYPE_MMXWR
6545 && rege
->type
!= REG_TYPE_MMXWC
6546 && rege
->type
!= REG_TYPE_MMXWCG
))
6548 inst
.error
= _("iWMMXt data or control register expected");
6551 inst
.operands
[i
].reg
= rege
->number
;
6552 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6558 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6560 || (rege
->type
!= REG_TYPE_MMXWC
6561 && rege
->type
!= REG_TYPE_MMXWCG
))
6563 inst
.error
= _("iWMMXt control register expected");
6566 inst
.operands
[i
].reg
= rege
->number
;
6567 inst
.operands
[i
].isreg
= 1;
6572 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6573 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6574 case OP_oROR
: val
= parse_ror (&str
); break;
6575 case OP_COND
: val
= parse_cond (&str
); break;
6576 case OP_oBARRIER_I15
:
6577 po_barrier_or_imm (str
); break;
6579 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6585 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6586 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6588 inst
.error
= _("Banked registers are not available with this "
6594 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6598 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6601 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6603 if (strncasecmp (str
, "APSR_", 5) == 0)
6610 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6611 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6612 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6613 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6614 default: found
= 16;
6618 inst
.operands
[i
].isvec
= 1;
6619 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6620 inst
.operands
[i
].reg
= REG_PC
;
6627 po_misc_or_fail (parse_tb (&str
));
6630 /* Register lists. */
6632 val
= parse_reg_list (&str
);
6635 inst
.operands
[1].writeback
= 1;
6641 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6645 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6649 /* Allow Q registers too. */
6650 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6655 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6657 inst
.operands
[i
].issingle
= 1;
6662 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6667 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6668 &inst
.operands
[i
].vectype
);
6671 /* Addressing modes */
6673 po_misc_or_fail (parse_address (&str
, i
));
6677 po_misc_or_fail_no_backtrack (
6678 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6682 po_misc_or_fail_no_backtrack (
6683 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6687 po_misc_or_fail_no_backtrack (
6688 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6692 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6696 po_misc_or_fail_no_backtrack (
6697 parse_shifter_operand_group_reloc (&str
, i
));
6701 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6705 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6709 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6713 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6716 /* Various value-based sanity checks and shared operations. We
6717 do not signal immediate failures for the register constraints;
6718 this allows a syntax error to take precedence. */
6719 switch (op_parse_code
)
6727 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6728 inst
.error
= BAD_PC
;
6733 if (inst
.operands
[i
].isreg
)
6735 if (inst
.operands
[i
].reg
== REG_PC
)
6736 inst
.error
= BAD_PC
;
6737 else if (inst
.operands
[i
].reg
== REG_SP
)
6738 inst
.error
= BAD_SP
;
6743 if (inst
.operands
[i
].isreg
6744 && inst
.operands
[i
].reg
== REG_PC
6745 && (inst
.operands
[i
].writeback
|| thumb
))
6746 inst
.error
= BAD_PC
;
6755 case OP_oBARRIER_I15
:
6764 inst
.operands
[i
].imm
= val
;
6771 /* If we get here, this operand was successfully parsed. */
6772 inst
.operands
[i
].present
= 1;
6776 inst
.error
= BAD_ARGS
;
6781 /* The parse routine should already have set inst.error, but set a
6782 default here just in case. */
6784 inst
.error
= _("syntax error");
6788 /* Do not backtrack over a trailing optional argument that
6789 absorbed some text. We will only fail again, with the
6790 'garbage following instruction' error message, which is
6791 probably less helpful than the current one. */
6792 if (backtrack_index
== i
&& backtrack_pos
!= str
6793 && upat
[i
+1] == OP_stop
)
6796 inst
.error
= _("syntax error");
6800 /* Try again, skipping the optional argument at backtrack_pos. */
6801 str
= backtrack_pos
;
6802 inst
.error
= backtrack_error
;
6803 inst
.operands
[backtrack_index
].present
= 0;
6804 i
= backtrack_index
;
6808 /* Check that we have parsed all the arguments. */
6809 if (*str
!= '\0' && !inst
.error
)
6810 inst
.error
= _("garbage following instruction");
6812 return inst
.error
? FAIL
: SUCCESS
;
6815 #undef po_char_or_fail
6816 #undef po_reg_or_fail
6817 #undef po_reg_or_goto
6818 #undef po_imm_or_fail
6819 #undef po_scalar_or_fail
6820 #undef po_barrier_or_imm
6822 /* Shorthand macro for instruction encoding functions issuing errors. */
6823 #define constraint(expr, err) \
6834 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6835 instructions are unpredictable if these registers are used. This
6836 is the BadReg predicate in ARM's Thumb-2 documentation. */
6837 #define reject_bad_reg(reg) \
6839 if (reg == REG_SP || reg == REG_PC) \
6841 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6846 /* If REG is R13 (the stack pointer), warn that its use is
6848 #define warn_deprecated_sp(reg) \
6850 if (warn_on_deprecated && reg == REG_SP) \
6851 as_warn (_("use of r13 is deprecated")); \
6854 /* Functions for operand encoding. ARM, then Thumb. */
6856 #define rotate_left(v, n) (v << n | v >> (32 - n))
6858 /* If VAL can be encoded in the immediate field of an ARM instruction,
6859 return the encoded form. Otherwise, return FAIL. */
6862 encode_arm_immediate (unsigned int val
)
6866 for (i
= 0; i
< 32; i
+= 2)
6867 if ((a
= rotate_left (val
, i
)) <= 0xff)
6868 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6873 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6874 return the encoded form. Otherwise, return FAIL. */
6876 encode_thumb32_immediate (unsigned int val
)
6883 for (i
= 1; i
<= 24; i
++)
6886 if ((val
& ~(0xff << i
)) == 0)
6887 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6891 if (val
== ((a
<< 16) | a
))
6893 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6897 if (val
== ((a
<< 16) | a
))
6898 return 0x200 | (a
>> 8);
6902 /* Encode a VFP SP or DP register number into inst.instruction. */
6905 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6907 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6910 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6913 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6916 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6921 first_error (_("D register out of range for selected VFP version"));
6929 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6933 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6937 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6941 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6945 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6949 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6957 /* Encode a <shift> in an ARM-format instruction. The immediate,
6958 if any, is handled by md_apply_fix. */
6960 encode_arm_shift (int i
)
6962 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6963 inst
.instruction
|= SHIFT_ROR
<< 5;
6966 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6967 if (inst
.operands
[i
].immisreg
)
6969 inst
.instruction
|= SHIFT_BY_REG
;
6970 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6973 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6978 encode_arm_shifter_operand (int i
)
6980 if (inst
.operands
[i
].isreg
)
6982 inst
.instruction
|= inst
.operands
[i
].reg
;
6983 encode_arm_shift (i
);
6986 inst
.instruction
|= INST_IMMEDIATE
;
6989 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6991 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6993 gas_assert (inst
.operands
[i
].isreg
);
6994 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6996 if (inst
.operands
[i
].preind
)
7000 inst
.error
= _("instruction does not accept preindexed addressing");
7003 inst
.instruction
|= PRE_INDEX
;
7004 if (inst
.operands
[i
].writeback
)
7005 inst
.instruction
|= WRITE_BACK
;
7008 else if (inst
.operands
[i
].postind
)
7010 gas_assert (inst
.operands
[i
].writeback
);
7012 inst
.instruction
|= WRITE_BACK
;
7014 else /* unindexed - only for coprocessor */
7016 inst
.error
= _("instruction does not accept unindexed addressing");
7020 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7021 && (((inst
.instruction
& 0x000f0000) >> 16)
7022 == ((inst
.instruction
& 0x0000f000) >> 12)))
7023 as_warn ((inst
.instruction
& LOAD_BIT
)
7024 ? _("destination register same as write-back base")
7025 : _("source register same as write-back base"));
7028 /* inst.operands[i] was set up by parse_address. Encode it into an
7029 ARM-format mode 2 load or store instruction. If is_t is true,
7030 reject forms that cannot be used with a T instruction (i.e. not
7033 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7035 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7037 encode_arm_addr_mode_common (i
, is_t
);
7039 if (inst
.operands
[i
].immisreg
)
7041 constraint ((inst
.operands
[i
].imm
== REG_PC
7042 || (is_pc
&& inst
.operands
[i
].writeback
)),
7044 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7045 inst
.instruction
|= inst
.operands
[i
].imm
;
7046 if (!inst
.operands
[i
].negative
)
7047 inst
.instruction
|= INDEX_UP
;
7048 if (inst
.operands
[i
].shifted
)
7050 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7051 inst
.instruction
|= SHIFT_ROR
<< 5;
7054 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7055 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7059 else /* immediate offset in inst.reloc */
7061 if (is_pc
&& !inst
.reloc
.pc_rel
)
7063 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7065 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7066 cannot use PC in addressing.
7067 PC cannot be used in writeback addressing, either. */
7068 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7071 /* Use of PC in str is deprecated for ARMv7. */
7072 if (warn_on_deprecated
7074 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7075 as_warn (_("use of PC in this instruction is deprecated"));
7078 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7080 /* Prefer + for zero encoded value. */
7081 if (!inst
.operands
[i
].negative
)
7082 inst
.instruction
|= INDEX_UP
;
7083 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7088 /* inst.operands[i] was set up by parse_address. Encode it into an
7089 ARM-format mode 3 load or store instruction. Reject forms that
7090 cannot be used with such instructions. If is_t is true, reject
7091 forms that cannot be used with a T instruction (i.e. not
7094 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7096 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7098 inst
.error
= _("instruction does not accept scaled register index");
7102 encode_arm_addr_mode_common (i
, is_t
);
7104 if (inst
.operands
[i
].immisreg
)
7106 constraint ((inst
.operands
[i
].imm
== REG_PC
7107 || inst
.operands
[i
].reg
== REG_PC
),
7109 inst
.instruction
|= inst
.operands
[i
].imm
;
7110 if (!inst
.operands
[i
].negative
)
7111 inst
.instruction
|= INDEX_UP
;
7113 else /* immediate offset in inst.reloc */
7115 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7116 && inst
.operands
[i
].writeback
),
7118 inst
.instruction
|= HWOFFSET_IMM
;
7119 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7121 /* Prefer + for zero encoded value. */
7122 if (!inst
.operands
[i
].negative
)
7123 inst
.instruction
|= INDEX_UP
;
7125 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7130 /* inst.operands[i] was set up by parse_address. Encode it into an
7131 ARM-format instruction. Reject all forms which cannot be encoded
7132 into a coprocessor load/store instruction. If wb_ok is false,
7133 reject use of writeback; if unind_ok is false, reject use of
7134 unindexed addressing. If reloc_override is not 0, use it instead
7135 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7136 (in which case it is preserved). */
7139 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7141 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7143 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7145 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7147 gas_assert (!inst
.operands
[i
].writeback
);
7150 inst
.error
= _("instruction does not support unindexed addressing");
7153 inst
.instruction
|= inst
.operands
[i
].imm
;
7154 inst
.instruction
|= INDEX_UP
;
7158 if (inst
.operands
[i
].preind
)
7159 inst
.instruction
|= PRE_INDEX
;
7161 if (inst
.operands
[i
].writeback
)
7163 if (inst
.operands
[i
].reg
== REG_PC
)
7165 inst
.error
= _("pc may not be used with write-back");
7170 inst
.error
= _("instruction does not support writeback");
7173 inst
.instruction
|= WRITE_BACK
;
7177 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7178 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7179 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7180 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7183 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7185 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7188 /* Prefer + for zero encoded value. */
7189 if (!inst
.operands
[i
].negative
)
7190 inst
.instruction
|= INDEX_UP
;
7195 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7196 Determine whether it can be performed with a move instruction; if
7197 it can, convert inst.instruction to that move instruction and
7198 return TRUE; if it can't, convert inst.instruction to a literal-pool
7199 load and return FALSE. If this is not a valid thing to do in the
7200 current context, set inst.error and return TRUE.
7202 inst.operands[i] describes the destination register. */
7205 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7210 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7214 if ((inst
.instruction
& tbit
) == 0)
7216 inst
.error
= _("invalid pseudo operation");
7219 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7221 inst
.error
= _("constant expression expected");
7224 if (inst
.reloc
.exp
.X_op
== O_constant
)
7228 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7230 /* This can be done with a mov(1) instruction. */
7231 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7232 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7238 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7241 /* This can be done with a mov instruction. */
7242 inst
.instruction
&= LITERAL_MASK
;
7243 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7244 inst
.instruction
|= value
& 0xfff;
7248 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7251 /* This can be done with a mvn instruction. */
7252 inst
.instruction
&= LITERAL_MASK
;
7253 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7254 inst
.instruction
|= value
& 0xfff;
7260 if (add_to_lit_pool () == FAIL
)
7262 inst
.error
= _("literal pool insertion failed");
7265 inst
.operands
[1].reg
= REG_PC
;
7266 inst
.operands
[1].isreg
= 1;
7267 inst
.operands
[1].preind
= 1;
7268 inst
.reloc
.pc_rel
= 1;
7269 inst
.reloc
.type
= (thumb_p
7270 ? BFD_RELOC_ARM_THUMB_OFFSET
7272 ? BFD_RELOC_ARM_HWLITERAL
7273 : BFD_RELOC_ARM_LITERAL
));
7277 /* Functions for instruction encoding, sorted by sub-architecture.
7278 First some generics; their names are taken from the conventional
7279 bit positions for register arguments in ARM format instructions. */
7289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7295 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7296 inst
.instruction
|= inst
.operands
[1].reg
;
7302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7303 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7309 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7310 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7316 unsigned Rn
= inst
.operands
[2].reg
;
7317 /* Enforce restrictions on SWP instruction. */
7318 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7320 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7321 _("Rn must not overlap other operands"));
7323 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7324 if (warn_on_deprecated
7325 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7326 as_warn (_("swp{b} use is deprecated for this architecture"));
7329 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7330 inst
.instruction
|= inst
.operands
[1].reg
;
7331 inst
.instruction
|= Rn
<< 16;
7337 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7338 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7339 inst
.instruction
|= inst
.operands
[2].reg
;
7345 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7346 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7347 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7348 || inst
.reloc
.exp
.X_add_number
!= 0),
7350 inst
.instruction
|= inst
.operands
[0].reg
;
7351 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7352 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7358 inst
.instruction
|= inst
.operands
[0].imm
;
7364 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7365 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7368 /* ARM instructions, in alphabetical order by function name (except
7369 that wrapper functions appear immediately after the function they
7372 /* This is a pseudo-op of the form "adr rd, label" to be converted
7373 into a relative address of the form "add rd, pc, #label-.-8". */
7378 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7380 /* Frag hacking will turn this into a sub instruction if the offset turns
7381 out to be negative. */
7382 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7383 inst
.reloc
.pc_rel
= 1;
7384 inst
.reloc
.exp
.X_add_number
-= 8;
7387 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7388 into a relative address of the form:
7389 add rd, pc, #low(label-.-8)"
7390 add rd, rd, #high(label-.-8)" */
7395 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7397 /* Frag hacking will turn this into a sub instruction if the offset turns
7398 out to be negative. */
7399 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7400 inst
.reloc
.pc_rel
= 1;
7401 inst
.size
= INSN_SIZE
* 2;
7402 inst
.reloc
.exp
.X_add_number
-= 8;
7408 if (!inst
.operands
[1].present
)
7409 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7410 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7411 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7412 encode_arm_shifter_operand (2);
7418 if (inst
.operands
[0].present
)
7420 constraint ((inst
.instruction
& 0xf0) != 0x40
7421 && inst
.operands
[0].imm
> 0xf
7422 && inst
.operands
[0].imm
< 0x0,
7423 _("bad barrier type"));
7424 inst
.instruction
|= inst
.operands
[0].imm
;
7427 inst
.instruction
|= 0xf;
7433 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7434 constraint (msb
> 32, _("bit-field extends past end of register"));
7435 /* The instruction encoding stores the LSB and MSB,
7436 not the LSB and width. */
7437 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7438 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7439 inst
.instruction
|= (msb
- 1) << 16;
7447 /* #0 in second position is alternative syntax for bfc, which is
7448 the same instruction but with REG_PC in the Rm field. */
7449 if (!inst
.operands
[1].isreg
)
7450 inst
.operands
[1].reg
= REG_PC
;
7452 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7453 constraint (msb
> 32, _("bit-field extends past end of register"));
7454 /* The instruction encoding stores the LSB and MSB,
7455 not the LSB and width. */
7456 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7457 inst
.instruction
|= inst
.operands
[1].reg
;
7458 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7459 inst
.instruction
|= (msb
- 1) << 16;
7465 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7466 _("bit-field extends past end of register"));
7467 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7468 inst
.instruction
|= inst
.operands
[1].reg
;
7469 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7470 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7473 /* ARM V5 breakpoint instruction (argument parse)
7474 BKPT <16 bit unsigned immediate>
7475 Instruction is not conditional.
7476 The bit pattern given in insns[] has the COND_ALWAYS condition,
7477 and it is an error if the caller tried to override that. */
7482 /* Top 12 of 16 bits to bits 19:8. */
7483 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7485 /* Bottom 4 of 16 bits to bits 3:0. */
7486 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7490 encode_branch (int default_reloc
)
7492 if (inst
.operands
[0].hasreloc
)
7494 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
7495 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
7496 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7497 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
7498 ? BFD_RELOC_ARM_PLT32
7499 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
7502 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7503 inst
.reloc
.pc_rel
= 1;
7510 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7511 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7514 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7521 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7523 if (inst
.cond
== COND_ALWAYS
)
7524 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7526 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7530 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7533 /* ARM V5 branch-link-exchange instruction (argument parse)
7534 BLX <target_addr> ie BLX(1)
7535 BLX{<condition>} <Rm> ie BLX(2)
7536 Unfortunately, there are two different opcodes for this mnemonic.
7537 So, the insns[].value is not used, and the code here zaps values
7538 into inst.instruction.
7539 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7544 if (inst
.operands
[0].isreg
)
7546 /* Arg is a register; the opcode provided by insns[] is correct.
7547 It is not illegal to do "blx pc", just useless. */
7548 if (inst
.operands
[0].reg
== REG_PC
)
7549 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7551 inst
.instruction
|= inst
.operands
[0].reg
;
7555 /* Arg is an address; this instruction cannot be executed
7556 conditionally, and the opcode must be adjusted.
7557 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7558 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7559 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7560 inst
.instruction
= 0xfa000000;
7561 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7568 bfd_boolean want_reloc
;
7570 if (inst
.operands
[0].reg
== REG_PC
)
7571 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7573 inst
.instruction
|= inst
.operands
[0].reg
;
7574 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7575 it is for ARMv4t or earlier. */
7576 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7577 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7581 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7586 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7590 /* ARM v5TEJ. Jump to Jazelle code. */
7595 if (inst
.operands
[0].reg
== REG_PC
)
7596 as_tsktsk (_("use of r15 in bxj is not really useful"));
7598 inst
.instruction
|= inst
.operands
[0].reg
;
7601 /* Co-processor data operation:
7602 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7603 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7607 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7608 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7609 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7610 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7611 inst
.instruction
|= inst
.operands
[4].reg
;
7612 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7618 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7619 encode_arm_shifter_operand (1);
7622 /* Transfer between coprocessor and ARM registers.
7623 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7628 No special properties. */
7635 Rd
= inst
.operands
[2].reg
;
7638 if (inst
.instruction
== 0xee000010
7639 || inst
.instruction
== 0xfe000010)
7641 reject_bad_reg (Rd
);
7644 constraint (Rd
== REG_SP
, BAD_SP
);
7649 if (inst
.instruction
== 0xe000010)
7650 constraint (Rd
== REG_PC
, BAD_PC
);
7654 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7655 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7656 inst
.instruction
|= Rd
<< 12;
7657 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7658 inst
.instruction
|= inst
.operands
[4].reg
;
7659 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7662 /* Transfer between coprocessor register and pair of ARM registers.
7663 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7668 Two XScale instructions are special cases of these:
7670 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7671 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7673 Result unpredictable if Rd or Rn is R15. */
7680 Rd
= inst
.operands
[2].reg
;
7681 Rn
= inst
.operands
[3].reg
;
7685 reject_bad_reg (Rd
);
7686 reject_bad_reg (Rn
);
7690 constraint (Rd
== REG_PC
, BAD_PC
);
7691 constraint (Rn
== REG_PC
, BAD_PC
);
7694 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7695 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7696 inst
.instruction
|= Rd
<< 12;
7697 inst
.instruction
|= Rn
<< 16;
7698 inst
.instruction
|= inst
.operands
[4].reg
;
7704 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7705 if (inst
.operands
[1].present
)
7707 inst
.instruction
|= CPSI_MMOD
;
7708 inst
.instruction
|= inst
.operands
[1].imm
;
7715 inst
.instruction
|= inst
.operands
[0].imm
;
7721 unsigned Rd
, Rn
, Rm
;
7723 Rd
= inst
.operands
[0].reg
;
7724 Rn
= (inst
.operands
[1].present
7725 ? inst
.operands
[1].reg
: Rd
);
7726 Rm
= inst
.operands
[2].reg
;
7728 constraint ((Rd
== REG_PC
), BAD_PC
);
7729 constraint ((Rn
== REG_PC
), BAD_PC
);
7730 constraint ((Rm
== REG_PC
), BAD_PC
);
7732 inst
.instruction
|= Rd
<< 16;
7733 inst
.instruction
|= Rn
<< 0;
7734 inst
.instruction
|= Rm
<< 8;
7740 /* There is no IT instruction in ARM mode. We
7741 process it to do the validation as if in
7742 thumb mode, just in case the code gets
7743 assembled for thumb using the unified syntax. */
7748 set_it_insn_type (IT_INSN
);
7749 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7750 now_it
.cc
= inst
.operands
[0].imm
;
7757 int base_reg
= inst
.operands
[0].reg
;
7758 int range
= inst
.operands
[1].imm
;
7760 inst
.instruction
|= base_reg
<< 16;
7761 inst
.instruction
|= range
;
7763 if (inst
.operands
[1].writeback
)
7764 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7766 if (inst
.operands
[0].writeback
)
7768 inst
.instruction
|= WRITE_BACK
;
7769 /* Check for unpredictable uses of writeback. */
7770 if (inst
.instruction
& LOAD_BIT
)
7772 /* Not allowed in LDM type 2. */
7773 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7774 && ((range
& (1 << REG_PC
)) == 0))
7775 as_warn (_("writeback of base register is UNPREDICTABLE"));
7776 /* Only allowed if base reg not in list for other types. */
7777 else if (range
& (1 << base_reg
))
7778 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7782 /* Not allowed for type 2. */
7783 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7784 as_warn (_("writeback of base register is UNPREDICTABLE"));
7785 /* Only allowed if base reg not in list, or first in list. */
7786 else if ((range
& (1 << base_reg
))
7787 && (range
& ((1 << base_reg
) - 1)))
7788 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7793 /* ARMv5TE load-consecutive (argument parse)
7802 constraint (inst
.operands
[0].reg
% 2 != 0,
7803 _("first transfer register must be even"));
7804 constraint (inst
.operands
[1].present
7805 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7806 _("can only transfer two consecutive registers"));
7807 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7808 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7810 if (!inst
.operands
[1].present
)
7811 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7813 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7814 register and the first register written; we have to diagnose
7815 overlap between the base and the second register written here. */
7817 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7818 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7819 as_warn (_("base register written back, and overlaps "
7820 "second transfer register"));
7822 if (!(inst
.instruction
& V4_STR_BIT
))
7824 /* For an index-register load, the index register must not overlap the
7825 destination (even if not write-back). */
7826 if (inst
.operands
[2].immisreg
7827 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7828 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7829 as_warn (_("index register overlaps transfer register"));
7831 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7832 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7838 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7839 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7840 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7841 || inst
.operands
[1].negative
7842 /* This can arise if the programmer has written
7844 or if they have mistakenly used a register name as the last
7847 It is very difficult to distinguish between these two cases
7848 because "rX" might actually be a label. ie the register
7849 name has been occluded by a symbol of the same name. So we
7850 just generate a general 'bad addressing mode' type error
7851 message and leave it up to the programmer to discover the
7852 true cause and fix their mistake. */
7853 || (inst
.operands
[1].reg
== REG_PC
),
7856 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7857 || inst
.reloc
.exp
.X_add_number
!= 0,
7858 _("offset must be zero in ARM encoding"));
7860 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7862 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7863 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7864 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7870 constraint (inst
.operands
[0].reg
% 2 != 0,
7871 _("even register required"));
7872 constraint (inst
.operands
[1].present
7873 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7874 _("can only load two consecutive registers"));
7875 /* If op 1 were present and equal to PC, this function wouldn't
7876 have been called in the first place. */
7877 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7879 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7880 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7886 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7887 if (!inst
.operands
[1].isreg
)
7888 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7890 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7896 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7898 if (inst
.operands
[1].preind
)
7900 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7901 || inst
.reloc
.exp
.X_add_number
!= 0,
7902 _("this instruction requires a post-indexed address"));
7904 inst
.operands
[1].preind
= 0;
7905 inst
.operands
[1].postind
= 1;
7906 inst
.operands
[1].writeback
= 1;
7908 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7909 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7912 /* Halfword and signed-byte load/store operations. */
7917 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7918 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7919 if (!inst
.operands
[1].isreg
)
7920 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7922 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7928 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7930 if (inst
.operands
[1].preind
)
7932 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7933 || inst
.reloc
.exp
.X_add_number
!= 0,
7934 _("this instruction requires a post-indexed address"));
7936 inst
.operands
[1].preind
= 0;
7937 inst
.operands
[1].postind
= 1;
7938 inst
.operands
[1].writeback
= 1;
7940 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7941 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7944 /* Co-processor register load/store.
7945 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7949 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7950 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7951 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7957 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7958 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7959 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7960 && !(inst
.instruction
& 0x00400000))
7961 as_tsktsk (_("Rd and Rm should be different in mla"));
7963 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7964 inst
.instruction
|= inst
.operands
[1].reg
;
7965 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7966 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7973 encode_arm_shifter_operand (1);
7976 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7983 top
= (inst
.instruction
& 0x00400000) != 0;
7984 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7985 _(":lower16: not allowed this instruction"));
7986 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7987 _(":upper16: not allowed instruction"));
7988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7989 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7991 imm
= inst
.reloc
.exp
.X_add_number
;
7992 /* The value is in two pieces: 0:11, 16:19. */
7993 inst
.instruction
|= (imm
& 0x00000fff);
7994 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7998 static void do_vfp_nsyn_opcode (const char *);
8001 do_vfp_nsyn_mrs (void)
8003 if (inst
.operands
[0].isvec
)
8005 if (inst
.operands
[1].reg
!= 1)
8006 first_error (_("operand 1 must be FPSCR"));
8007 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8008 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8009 do_vfp_nsyn_opcode ("fmstat");
8011 else if (inst
.operands
[1].isvec
)
8012 do_vfp_nsyn_opcode ("fmrx");
8020 do_vfp_nsyn_msr (void)
8022 if (inst
.operands
[0].isvec
)
8023 do_vfp_nsyn_opcode ("fmxr");
8033 unsigned Rt
= inst
.operands
[0].reg
;
8035 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
8037 inst
.error
= BAD_SP
;
8041 /* APSR_ sets isvec. All other refs to PC are illegal. */
8042 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
8044 inst
.error
= BAD_PC
;
8048 if (inst
.operands
[1].reg
!= 1)
8049 first_error (_("operand 1 must be FPSCR"));
8051 inst
.instruction
|= (Rt
<< 12);
8057 unsigned Rt
= inst
.operands
[1].reg
;
8060 reject_bad_reg (Rt
);
8061 else if (Rt
== REG_PC
)
8063 inst
.error
= BAD_PC
;
8067 if (inst
.operands
[0].reg
!= 1)
8068 first_error (_("operand 0 must be FPSCR"));
8070 inst
.instruction
|= (Rt
<< 12);
8078 if (do_vfp_nsyn_mrs () == SUCCESS
)
8081 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8082 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8084 if (inst
.operands
[1].isreg
)
8086 br
= inst
.operands
[1].reg
;
8087 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8088 as_bad (_("bad register for mrs"));
8092 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8093 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8095 _("'APSR', 'CPSR' or 'SPSR' expected"));
8096 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8099 inst
.instruction
|= br
;
8102 /* Two possible forms:
8103 "{C|S}PSR_<field>, Rm",
8104 "{C|S}PSR_f, #expression". */
8109 if (do_vfp_nsyn_msr () == SUCCESS
)
8112 inst
.instruction
|= inst
.operands
[0].imm
;
8113 if (inst
.operands
[1].isreg
)
8114 inst
.instruction
|= inst
.operands
[1].reg
;
8117 inst
.instruction
|= INST_IMMEDIATE
;
8118 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8119 inst
.reloc
.pc_rel
= 0;
8126 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8128 if (!inst
.operands
[2].present
)
8129 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8130 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8131 inst
.instruction
|= inst
.operands
[1].reg
;
8132 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8134 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8135 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8136 as_tsktsk (_("Rd and Rm should be different in mul"));
8139 /* Long Multiply Parser
8140 UMULL RdLo, RdHi, Rm, Rs
8141 SMULL RdLo, RdHi, Rm, Rs
8142 UMLAL RdLo, RdHi, Rm, Rs
8143 SMLAL RdLo, RdHi, Rm, Rs. */
8148 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8149 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8150 inst
.instruction
|= inst
.operands
[2].reg
;
8151 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8153 /* rdhi and rdlo must be different. */
8154 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8155 as_tsktsk (_("rdhi and rdlo must be different"));
8157 /* rdhi, rdlo and rm must all be different before armv6. */
8158 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8159 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8160 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8161 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8167 if (inst
.operands
[0].present
8168 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8170 /* Architectural NOP hints are CPSR sets with no bits selected. */
8171 inst
.instruction
&= 0xf0000000;
8172 inst
.instruction
|= 0x0320f000;
8173 if (inst
.operands
[0].present
)
8174 inst
.instruction
|= inst
.operands
[0].imm
;
8178 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8179 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8180 Condition defaults to COND_ALWAYS.
8181 Error if Rd, Rn or Rm are R15. */
8186 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8187 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8188 inst
.instruction
|= inst
.operands
[2].reg
;
8189 if (inst
.operands
[3].present
)
8190 encode_arm_shift (3);
8193 /* ARM V6 PKHTB (Argument Parse). */
8198 if (!inst
.operands
[3].present
)
8200 /* If the shift specifier is omitted, turn the instruction
8201 into pkhbt rd, rm, rn. */
8202 inst
.instruction
&= 0xfff00010;
8203 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8204 inst
.instruction
|= inst
.operands
[1].reg
;
8205 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8209 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8210 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8211 inst
.instruction
|= inst
.operands
[2].reg
;
8212 encode_arm_shift (3);
8216 /* ARMv5TE: Preload-Cache
8217 MP Extensions: Preload for write
8221 Syntactically, like LDR with B=1, W=0, L=1. */
8226 constraint (!inst
.operands
[0].isreg
,
8227 _("'[' expected after PLD mnemonic"));
8228 constraint (inst
.operands
[0].postind
,
8229 _("post-indexed expression used in preload instruction"));
8230 constraint (inst
.operands
[0].writeback
,
8231 _("writeback used in preload instruction"));
8232 constraint (!inst
.operands
[0].preind
,
8233 _("unindexed addressing used in preload instruction"));
8234 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8237 /* ARMv7: PLI <addr_mode> */
8241 constraint (!inst
.operands
[0].isreg
,
8242 _("'[' expected after PLI mnemonic"));
8243 constraint (inst
.operands
[0].postind
,
8244 _("post-indexed expression used in preload instruction"));
8245 constraint (inst
.operands
[0].writeback
,
8246 _("writeback used in preload instruction"));
8247 constraint (!inst
.operands
[0].preind
,
8248 _("unindexed addressing used in preload instruction"));
8249 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8250 inst
.instruction
&= ~PRE_INDEX
;
8256 inst
.operands
[1] = inst
.operands
[0];
8257 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8258 inst
.operands
[0].isreg
= 1;
8259 inst
.operands
[0].writeback
= 1;
8260 inst
.operands
[0].reg
= REG_SP
;
8264 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8265 word at the specified address and the following word
8267 Unconditionally executed.
8268 Error if Rn is R15. */
8273 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8274 if (inst
.operands
[0].writeback
)
8275 inst
.instruction
|= WRITE_BACK
;
8278 /* ARM V6 ssat (argument parse). */
8283 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8284 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8285 inst
.instruction
|= inst
.operands
[2].reg
;
8287 if (inst
.operands
[3].present
)
8288 encode_arm_shift (3);
8291 /* ARM V6 usat (argument parse). */
8296 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8297 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8298 inst
.instruction
|= inst
.operands
[2].reg
;
8300 if (inst
.operands
[3].present
)
8301 encode_arm_shift (3);
8304 /* ARM V6 ssat16 (argument parse). */
8309 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8310 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8311 inst
.instruction
|= inst
.operands
[2].reg
;
8317 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8318 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8319 inst
.instruction
|= inst
.operands
[2].reg
;
8322 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8323 preserving the other bits.
8325 setend <endian_specifier>, where <endian_specifier> is either
8331 if (inst
.operands
[0].imm
)
8332 inst
.instruction
|= 0x200;
8338 unsigned int Rm
= (inst
.operands
[1].present
8339 ? inst
.operands
[1].reg
8340 : inst
.operands
[0].reg
);
8342 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8343 inst
.instruction
|= Rm
;
8344 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8346 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8347 inst
.instruction
|= SHIFT_BY_REG
;
8348 /* PR 12854: Error on extraneous shifts. */
8349 constraint (inst
.operands
[2].shifted
,
8350 _("extraneous shift as part of operand to shift insn"));
8353 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8359 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8360 inst
.reloc
.pc_rel
= 0;
8366 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8367 inst
.reloc
.pc_rel
= 0;
8373 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8374 inst
.reloc
.pc_rel
= 0;
8377 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8378 SMLAxy{cond} Rd,Rm,Rs,Rn
8379 SMLAWy{cond} Rd,Rm,Rs,Rn
8380 Error if any register is R15. */
8385 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8386 inst
.instruction
|= inst
.operands
[1].reg
;
8387 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8388 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8391 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8392 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8393 Error if any register is R15.
8394 Warning if Rdlo == Rdhi. */
8399 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8400 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8401 inst
.instruction
|= inst
.operands
[2].reg
;
8402 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8404 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8405 as_tsktsk (_("rdhi and rdlo must be different"));
8408 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8409 SMULxy{cond} Rd,Rm,Rs
8410 Error if any register is R15. */
8415 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8416 inst
.instruction
|= inst
.operands
[1].reg
;
8417 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8420 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8421 the same for both ARM and Thumb-2. */
8428 if (inst
.operands
[0].present
)
8430 reg
= inst
.operands
[0].reg
;
8431 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8436 inst
.instruction
|= reg
<< 16;
8437 inst
.instruction
|= inst
.operands
[1].imm
;
8438 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8439 inst
.instruction
|= WRITE_BACK
;
8442 /* ARM V6 strex (argument parse). */
8447 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8448 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8449 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8450 || inst
.operands
[2].negative
8451 /* See comment in do_ldrex(). */
8452 || (inst
.operands
[2].reg
== REG_PC
),
8455 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8456 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8458 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8459 || inst
.reloc
.exp
.X_add_number
!= 0,
8460 _("offset must be zero in ARM encoding"));
8462 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8463 inst
.instruction
|= inst
.operands
[1].reg
;
8464 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8465 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8471 constraint (inst
.operands
[1].reg
% 2 != 0,
8472 _("even register required"));
8473 constraint (inst
.operands
[2].present
8474 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8475 _("can only store two consecutive registers"));
8476 /* If op 2 were present and equal to PC, this function wouldn't
8477 have been called in the first place. */
8478 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8480 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8481 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8482 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8485 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8486 inst
.instruction
|= inst
.operands
[1].reg
;
8487 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8490 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8491 extends it to 32-bits, and adds the result to a value in another
8492 register. You can specify a rotation by 0, 8, 16, or 24 bits
8493 before extracting the 16-bit value.
8494 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8495 Condition defaults to COND_ALWAYS.
8496 Error if any register uses R15. */
8501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8502 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8503 inst
.instruction
|= inst
.operands
[2].reg
;
8504 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8509 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8510 Condition defaults to COND_ALWAYS.
8511 Error if any register uses R15. */
8516 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8517 inst
.instruction
|= inst
.operands
[1].reg
;
8518 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8521 /* VFP instructions. In a logical order: SP variant first, monad
8522 before dyad, arithmetic then move then load/store. */
8525 do_vfp_sp_monadic (void)
8527 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8528 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8532 do_vfp_sp_dyadic (void)
8534 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8535 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8536 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8540 do_vfp_sp_compare_z (void)
8542 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8546 do_vfp_dp_sp_cvt (void)
8548 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8549 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8553 do_vfp_sp_dp_cvt (void)
8555 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8556 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8560 do_vfp_reg_from_sp (void)
8562 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8563 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8567 do_vfp_reg2_from_sp2 (void)
8569 constraint (inst
.operands
[2].imm
!= 2,
8570 _("only two consecutive VFP SP registers allowed here"));
8571 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8572 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8573 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8577 do_vfp_sp_from_reg (void)
8579 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8580 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8584 do_vfp_sp2_from_reg2 (void)
8586 constraint (inst
.operands
[0].imm
!= 2,
8587 _("only two consecutive VFP SP registers allowed here"));
8588 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8589 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8590 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8594 do_vfp_sp_ldst (void)
8596 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8597 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8601 do_vfp_dp_ldst (void)
8603 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8604 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8609 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8611 if (inst
.operands
[0].writeback
)
8612 inst
.instruction
|= WRITE_BACK
;
8614 constraint (ldstm_type
!= VFP_LDSTMIA
,
8615 _("this addressing mode requires base-register writeback"));
8616 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8617 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8618 inst
.instruction
|= inst
.operands
[1].imm
;
8622 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8626 if (inst
.operands
[0].writeback
)
8627 inst
.instruction
|= WRITE_BACK
;
8629 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8630 _("this addressing mode requires base-register writeback"));
8632 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8633 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8635 count
= inst
.operands
[1].imm
<< 1;
8636 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8639 inst
.instruction
|= count
;
8643 do_vfp_sp_ldstmia (void)
8645 vfp_sp_ldstm (VFP_LDSTMIA
);
8649 do_vfp_sp_ldstmdb (void)
8651 vfp_sp_ldstm (VFP_LDSTMDB
);
8655 do_vfp_dp_ldstmia (void)
8657 vfp_dp_ldstm (VFP_LDSTMIA
);
8661 do_vfp_dp_ldstmdb (void)
8663 vfp_dp_ldstm (VFP_LDSTMDB
);
8667 do_vfp_xp_ldstmia (void)
8669 vfp_dp_ldstm (VFP_LDSTMIAX
);
8673 do_vfp_xp_ldstmdb (void)
8675 vfp_dp_ldstm (VFP_LDSTMDBX
);
8679 do_vfp_dp_rd_rm (void)
8681 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8682 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8686 do_vfp_dp_rn_rd (void)
8688 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8689 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8693 do_vfp_dp_rd_rn (void)
8695 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8696 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8700 do_vfp_dp_rd_rn_rm (void)
8702 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8703 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8704 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8710 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8714 do_vfp_dp_rm_rd_rn (void)
8716 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8717 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8718 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8721 /* VFPv3 instructions. */
8723 do_vfp_sp_const (void)
8725 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8726 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8727 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8731 do_vfp_dp_const (void)
8733 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8734 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8735 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8739 vfp_conv (int srcsize
)
8741 int immbits
= srcsize
- inst
.operands
[1].imm
;
8743 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
8745 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8746 i.e. immbits must be in range 0 - 16. */
8747 inst
.error
= _("immediate value out of range, expected range [0, 16]");
8750 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
8752 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8753 i.e. immbits must be in range 0 - 31. */
8754 inst
.error
= _("immediate value out of range, expected range [1, 32]");
8758 inst
.instruction
|= (immbits
& 1) << 5;
8759 inst
.instruction
|= (immbits
>> 1);
8763 do_vfp_sp_conv_16 (void)
8765 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8770 do_vfp_dp_conv_16 (void)
8772 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8777 do_vfp_sp_conv_32 (void)
8779 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8784 do_vfp_dp_conv_32 (void)
8786 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8790 /* FPA instructions. Also in a logical order. */
8795 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8796 inst
.instruction
|= inst
.operands
[1].reg
;
8800 do_fpa_ldmstm (void)
8802 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8803 switch (inst
.operands
[1].imm
)
8805 case 1: inst
.instruction
|= CP_T_X
; break;
8806 case 2: inst
.instruction
|= CP_T_Y
; break;
8807 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8812 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8814 /* The instruction specified "ea" or "fd", so we can only accept
8815 [Rn]{!}. The instruction does not really support stacking or
8816 unstacking, so we have to emulate these by setting appropriate
8817 bits and offsets. */
8818 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8819 || inst
.reloc
.exp
.X_add_number
!= 0,
8820 _("this instruction does not support indexing"));
8822 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8823 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8825 if (!(inst
.instruction
& INDEX_UP
))
8826 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8828 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8830 inst
.operands
[2].preind
= 0;
8831 inst
.operands
[2].postind
= 1;
8835 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8838 /* iWMMXt instructions: strictly in alphabetical order. */
8841 do_iwmmxt_tandorc (void)
8843 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8847 do_iwmmxt_textrc (void)
8849 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8850 inst
.instruction
|= inst
.operands
[1].imm
;
8854 do_iwmmxt_textrm (void)
8856 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8857 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8858 inst
.instruction
|= inst
.operands
[2].imm
;
8862 do_iwmmxt_tinsr (void)
8864 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8865 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8866 inst
.instruction
|= inst
.operands
[2].imm
;
8870 do_iwmmxt_tmia (void)
8872 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8873 inst
.instruction
|= inst
.operands
[1].reg
;
8874 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8878 do_iwmmxt_waligni (void)
8880 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8881 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8882 inst
.instruction
|= inst
.operands
[2].reg
;
8883 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8887 do_iwmmxt_wmerge (void)
8889 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8890 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8891 inst
.instruction
|= inst
.operands
[2].reg
;
8892 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8896 do_iwmmxt_wmov (void)
8898 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8899 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8900 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8901 inst
.instruction
|= inst
.operands
[1].reg
;
8905 do_iwmmxt_wldstbh (void)
8908 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8910 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8912 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8913 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8917 do_iwmmxt_wldstw (void)
8919 /* RIWR_RIWC clears .isreg for a control register. */
8920 if (!inst
.operands
[0].isreg
)
8922 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8923 inst
.instruction
|= 0xf0000000;
8926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8927 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8931 do_iwmmxt_wldstd (void)
8933 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8934 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8935 && inst
.operands
[1].immisreg
)
8937 inst
.instruction
&= ~0x1a000ff;
8938 inst
.instruction
|= (0xf << 28);
8939 if (inst
.operands
[1].preind
)
8940 inst
.instruction
|= PRE_INDEX
;
8941 if (!inst
.operands
[1].negative
)
8942 inst
.instruction
|= INDEX_UP
;
8943 if (inst
.operands
[1].writeback
)
8944 inst
.instruction
|= WRITE_BACK
;
8945 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8946 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8947 inst
.instruction
|= inst
.operands
[1].imm
;
8950 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8954 do_iwmmxt_wshufh (void)
8956 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8957 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8958 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8959 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8963 do_iwmmxt_wzero (void)
8965 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8966 inst
.instruction
|= inst
.operands
[0].reg
;
8967 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8968 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8972 do_iwmmxt_wrwrwr_or_imm5 (void)
8974 if (inst
.operands
[2].isreg
)
8977 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8978 _("immediate operand requires iWMMXt2"));
8980 if (inst
.operands
[2].imm
== 0)
8982 switch ((inst
.instruction
>> 20) & 0xf)
8988 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8989 inst
.operands
[2].imm
= 16;
8990 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8996 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8997 inst
.operands
[2].imm
= 32;
8998 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9005 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9007 wrn
= (inst
.instruction
>> 16) & 0xf;
9008 inst
.instruction
&= 0xff0fff0f;
9009 inst
.instruction
|= wrn
;
9010 /* Bail out here; the instruction is now assembled. */
9015 /* Map 32 -> 0, etc. */
9016 inst
.operands
[2].imm
&= 0x1f;
9017 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
9021 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9022 operations first, then control, shift, and load/store. */
9024 /* Insns like "foo X,Y,Z". */
9027 do_mav_triple (void)
9029 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9030 inst
.instruction
|= inst
.operands
[1].reg
;
9031 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9034 /* Insns like "foo W,X,Y,Z".
9035 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9040 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9041 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9042 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9043 inst
.instruction
|= inst
.operands
[3].reg
;
9046 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9050 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9053 /* Maverick shift immediate instructions.
9054 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9055 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9060 int imm
= inst
.operands
[2].imm
;
9062 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9063 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9065 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9066 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9067 Bit 4 should be 0. */
9068 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
9070 inst
.instruction
|= imm
;
9073 /* XScale instructions. Also sorted arithmetic before move. */
9075 /* Xscale multiply-accumulate (argument parse)
9078 MIAxycc acc0,Rm,Rs. */
9083 inst
.instruction
|= inst
.operands
[1].reg
;
9084 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9087 /* Xscale move-accumulator-register (argument parse)
9089 MARcc acc0,RdLo,RdHi. */
9094 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9095 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9098 /* Xscale move-register-accumulator (argument parse)
9100 MRAcc RdLo,RdHi,acc0. */
9105 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9106 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9107 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9110 /* Encoding functions relevant only to Thumb. */
9112 /* inst.operands[i] is a shifted-register operand; encode
9113 it into inst.instruction in the format used by Thumb32. */
9116 encode_thumb32_shifted_operand (int i
)
9118 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9119 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9121 constraint (inst
.operands
[i
].immisreg
,
9122 _("shift by register not allowed in thumb mode"));
9123 inst
.instruction
|= inst
.operands
[i
].reg
;
9124 if (shift
== SHIFT_RRX
)
9125 inst
.instruction
|= SHIFT_ROR
<< 4;
9128 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9129 _("expression too complex"));
9131 constraint (value
> 32
9132 || (value
== 32 && (shift
== SHIFT_LSL
9133 || shift
== SHIFT_ROR
)),
9134 _("shift expression is too large"));
9138 else if (value
== 32)
9141 inst
.instruction
|= shift
<< 4;
9142 inst
.instruction
|= (value
& 0x1c) << 10;
9143 inst
.instruction
|= (value
& 0x03) << 6;
9148 /* inst.operands[i] was set up by parse_address. Encode it into a
9149 Thumb32 format load or store instruction. Reject forms that cannot
9150 be used with such instructions. If is_t is true, reject forms that
9151 cannot be used with a T instruction; if is_d is true, reject forms
9152 that cannot be used with a D instruction. If it is a store insn,
9156 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9158 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9160 constraint (!inst
.operands
[i
].isreg
,
9161 _("Instruction does not support =N addresses"));
9163 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9164 if (inst
.operands
[i
].immisreg
)
9166 constraint (is_pc
, BAD_PC_ADDRESSING
);
9167 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9168 constraint (inst
.operands
[i
].negative
,
9169 _("Thumb does not support negative register indexing"));
9170 constraint (inst
.operands
[i
].postind
,
9171 _("Thumb does not support register post-indexing"));
9172 constraint (inst
.operands
[i
].writeback
,
9173 _("Thumb does not support register indexing with writeback"));
9174 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9175 _("Thumb supports only LSL in shifted register indexing"));
9177 inst
.instruction
|= inst
.operands
[i
].imm
;
9178 if (inst
.operands
[i
].shifted
)
9180 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9181 _("expression too complex"));
9182 constraint (inst
.reloc
.exp
.X_add_number
< 0
9183 || inst
.reloc
.exp
.X_add_number
> 3,
9184 _("shift out of range"));
9185 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9187 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9189 else if (inst
.operands
[i
].preind
)
9191 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
9192 constraint (is_t
&& inst
.operands
[i
].writeback
,
9193 _("cannot use writeback with this instruction"));
9194 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
9195 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
9199 inst
.instruction
|= 0x01000000;
9200 if (inst
.operands
[i
].writeback
)
9201 inst
.instruction
|= 0x00200000;
9205 inst
.instruction
|= 0x00000c00;
9206 if (inst
.operands
[i
].writeback
)
9207 inst
.instruction
|= 0x00000100;
9209 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9211 else if (inst
.operands
[i
].postind
)
9213 gas_assert (inst
.operands
[i
].writeback
);
9214 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
9215 constraint (is_t
, _("cannot use post-indexing with this instruction"));
9218 inst
.instruction
|= 0x00200000;
9220 inst
.instruction
|= 0x00000900;
9221 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9223 else /* unindexed - only for coprocessor */
9224 inst
.error
= _("instruction does not accept unindexed addressing");
9227 /* Table of Thumb instructions which exist in both 16- and 32-bit
9228 encodings (the latter only in post-V6T2 cores). The index is the
9229 value used in the insns table below. When there is more than one
9230 possible 16-bit encoding for the instruction, this table always
9232 Also contains several pseudo-instructions used during relaxation. */
9233 #define T16_32_TAB \
9234 X(_adc, 4140, eb400000), \
9235 X(_adcs, 4140, eb500000), \
9236 X(_add, 1c00, eb000000), \
9237 X(_adds, 1c00, eb100000), \
9238 X(_addi, 0000, f1000000), \
9239 X(_addis, 0000, f1100000), \
9240 X(_add_pc,000f, f20f0000), \
9241 X(_add_sp,000d, f10d0000), \
9242 X(_adr, 000f, f20f0000), \
9243 X(_and, 4000, ea000000), \
9244 X(_ands, 4000, ea100000), \
9245 X(_asr, 1000, fa40f000), \
9246 X(_asrs, 1000, fa50f000), \
9247 X(_b, e000, f000b000), \
9248 X(_bcond, d000, f0008000), \
9249 X(_bic, 4380, ea200000), \
9250 X(_bics, 4380, ea300000), \
9251 X(_cmn, 42c0, eb100f00), \
9252 X(_cmp, 2800, ebb00f00), \
9253 X(_cpsie, b660, f3af8400), \
9254 X(_cpsid, b670, f3af8600), \
9255 X(_cpy, 4600, ea4f0000), \
9256 X(_dec_sp,80dd, f1ad0d00), \
9257 X(_eor, 4040, ea800000), \
9258 X(_eors, 4040, ea900000), \
9259 X(_inc_sp,00dd, f10d0d00), \
9260 X(_ldmia, c800, e8900000), \
9261 X(_ldr, 6800, f8500000), \
9262 X(_ldrb, 7800, f8100000), \
9263 X(_ldrh, 8800, f8300000), \
9264 X(_ldrsb, 5600, f9100000), \
9265 X(_ldrsh, 5e00, f9300000), \
9266 X(_ldr_pc,4800, f85f0000), \
9267 X(_ldr_pc2,4800, f85f0000), \
9268 X(_ldr_sp,9800, f85d0000), \
9269 X(_lsl, 0000, fa00f000), \
9270 X(_lsls, 0000, fa10f000), \
9271 X(_lsr, 0800, fa20f000), \
9272 X(_lsrs, 0800, fa30f000), \
9273 X(_mov, 2000, ea4f0000), \
9274 X(_movs, 2000, ea5f0000), \
9275 X(_mul, 4340, fb00f000), \
9276 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9277 X(_mvn, 43c0, ea6f0000), \
9278 X(_mvns, 43c0, ea7f0000), \
9279 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9280 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9281 X(_orr, 4300, ea400000), \
9282 X(_orrs, 4300, ea500000), \
9283 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9284 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9285 X(_rev, ba00, fa90f080), \
9286 X(_rev16, ba40, fa90f090), \
9287 X(_revsh, bac0, fa90f0b0), \
9288 X(_ror, 41c0, fa60f000), \
9289 X(_rors, 41c0, fa70f000), \
9290 X(_sbc, 4180, eb600000), \
9291 X(_sbcs, 4180, eb700000), \
9292 X(_stmia, c000, e8800000), \
9293 X(_str, 6000, f8400000), \
9294 X(_strb, 7000, f8000000), \
9295 X(_strh, 8000, f8200000), \
9296 X(_str_sp,9000, f84d0000), \
9297 X(_sub, 1e00, eba00000), \
9298 X(_subs, 1e00, ebb00000), \
9299 X(_subi, 8000, f1a00000), \
9300 X(_subis, 8000, f1b00000), \
9301 X(_sxtb, b240, fa4ff080), \
9302 X(_sxth, b200, fa0ff080), \
9303 X(_tst, 4200, ea100f00), \
9304 X(_uxtb, b2c0, fa5ff080), \
9305 X(_uxth, b280, fa1ff080), \
9306 X(_nop, bf00, f3af8000), \
9307 X(_yield, bf10, f3af8001), \
9308 X(_wfe, bf20, f3af8002), \
9309 X(_wfi, bf30, f3af8003), \
9310 X(_sev, bf40, f3af8004),
9312 /* To catch errors in encoding functions, the codes are all offset by
9313 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9314 as 16-bit instructions. */
9315 #define X(a,b,c) T_MNEM##a
9316 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9319 #define X(a,b,c) 0x##b
9320 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9321 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9324 #define X(a,b,c) 0x##c
9325 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9326 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9327 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9331 /* Thumb instruction encoders, in alphabetical order. */
9336 do_t_add_sub_w (void)
9340 Rd
= inst
.operands
[0].reg
;
9341 Rn
= inst
.operands
[1].reg
;
9343 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9344 is the SP-{plus,minus}-immediate form of the instruction. */
9346 constraint (Rd
== REG_PC
, BAD_PC
);
9348 reject_bad_reg (Rd
);
9350 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9351 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9354 /* Parse an add or subtract instruction. We get here with inst.instruction
9355 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9362 Rd
= inst
.operands
[0].reg
;
9363 Rs
= (inst
.operands
[1].present
9364 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9365 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9368 set_it_insn_type_last ();
9376 flags
= (inst
.instruction
== T_MNEM_adds
9377 || inst
.instruction
== T_MNEM_subs
);
9379 narrow
= !in_it_block ();
9381 narrow
= in_it_block ();
9382 if (!inst
.operands
[2].isreg
)
9386 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9388 add
= (inst
.instruction
== T_MNEM_add
9389 || inst
.instruction
== T_MNEM_adds
);
9391 if (inst
.size_req
!= 4)
9393 /* Attempt to use a narrow opcode, with relaxation if
9395 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9396 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9397 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9398 opcode
= T_MNEM_add_sp
;
9399 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9400 opcode
= T_MNEM_add_pc
;
9401 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9404 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9406 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9410 inst
.instruction
= THUMB_OP16(opcode
);
9411 inst
.instruction
|= (Rd
<< 4) | Rs
;
9412 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9413 if (inst
.size_req
!= 2)
9414 inst
.relax
= opcode
;
9417 constraint (inst
.size_req
== 2, BAD_HIREG
);
9419 if (inst
.size_req
== 4
9420 || (inst
.size_req
!= 2 && !opcode
))
9424 constraint (add
, BAD_PC
);
9425 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9426 _("only SUBS PC, LR, #const allowed"));
9427 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9428 _("expression too complex"));
9429 constraint (inst
.reloc
.exp
.X_add_number
< 0
9430 || inst
.reloc
.exp
.X_add_number
> 0xff,
9431 _("immediate value out of range"));
9432 inst
.instruction
= T2_SUBS_PC_LR
9433 | inst
.reloc
.exp
.X_add_number
;
9434 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9437 else if (Rs
== REG_PC
)
9439 /* Always use addw/subw. */
9440 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9441 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9445 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9446 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9449 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9451 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9453 inst
.instruction
|= Rd
<< 8;
9454 inst
.instruction
|= Rs
<< 16;
9459 Rn
= inst
.operands
[2].reg
;
9460 /* See if we can do this with a 16-bit instruction. */
9461 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9463 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9468 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9469 || inst
.instruction
== T_MNEM_add
)
9472 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9476 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9478 /* Thumb-1 cores (except v6-M) require at least one high
9479 register in a narrow non flag setting add. */
9480 if (Rd
> 7 || Rn
> 7
9481 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9482 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9489 inst
.instruction
= T_OPCODE_ADD_HI
;
9490 inst
.instruction
|= (Rd
& 8) << 4;
9491 inst
.instruction
|= (Rd
& 7);
9492 inst
.instruction
|= Rn
<< 3;
9498 constraint (Rd
== REG_PC
, BAD_PC
);
9499 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9500 constraint (Rs
== REG_PC
, BAD_PC
);
9501 reject_bad_reg (Rn
);
9503 /* If we get here, it can't be done in 16 bits. */
9504 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9505 _("shift must be constant"));
9506 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9507 inst
.instruction
|= Rd
<< 8;
9508 inst
.instruction
|= Rs
<< 16;
9509 encode_thumb32_shifted_operand (2);
9514 constraint (inst
.instruction
== T_MNEM_adds
9515 || inst
.instruction
== T_MNEM_subs
,
9518 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9520 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9521 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9524 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9526 inst
.instruction
|= (Rd
<< 4) | Rs
;
9527 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9531 Rn
= inst
.operands
[2].reg
;
9532 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9534 /* We now have Rd, Rs, and Rn set to registers. */
9535 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9537 /* Can't do this for SUB. */
9538 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9539 inst
.instruction
= T_OPCODE_ADD_HI
;
9540 inst
.instruction
|= (Rd
& 8) << 4;
9541 inst
.instruction
|= (Rd
& 7);
9543 inst
.instruction
|= Rn
<< 3;
9545 inst
.instruction
|= Rs
<< 3;
9547 constraint (1, _("dest must overlap one source register"));
9551 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9552 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9553 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9563 Rd
= inst
.operands
[0].reg
;
9564 reject_bad_reg (Rd
);
9566 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9568 /* Defer to section relaxation. */
9569 inst
.relax
= inst
.instruction
;
9570 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9571 inst
.instruction
|= Rd
<< 4;
9573 else if (unified_syntax
&& inst
.size_req
!= 2)
9575 /* Generate a 32-bit opcode. */
9576 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9577 inst
.instruction
|= Rd
<< 8;
9578 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9579 inst
.reloc
.pc_rel
= 1;
9583 /* Generate a 16-bit opcode. */
9584 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9585 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9586 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9587 inst
.reloc
.pc_rel
= 1;
9589 inst
.instruction
|= Rd
<< 4;
9593 /* Arithmetic instructions for which there is just one 16-bit
9594 instruction encoding, and it allows only two low registers.
9595 For maximal compatibility with ARM syntax, we allow three register
9596 operands even when Thumb-32 instructions are not available, as long
9597 as the first two are identical. For instance, both "sbc r0,r1" and
9598 "sbc r0,r0,r1" are allowed. */
9604 Rd
= inst
.operands
[0].reg
;
9605 Rs
= (inst
.operands
[1].present
9606 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9607 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9608 Rn
= inst
.operands
[2].reg
;
9610 reject_bad_reg (Rd
);
9611 reject_bad_reg (Rs
);
9612 if (inst
.operands
[2].isreg
)
9613 reject_bad_reg (Rn
);
9617 if (!inst
.operands
[2].isreg
)
9619 /* For an immediate, we always generate a 32-bit opcode;
9620 section relaxation will shrink it later if possible. */
9621 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9622 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9623 inst
.instruction
|= Rd
<< 8;
9624 inst
.instruction
|= Rs
<< 16;
9625 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9631 /* See if we can do this with a 16-bit instruction. */
9632 if (THUMB_SETS_FLAGS (inst
.instruction
))
9633 narrow
= !in_it_block ();
9635 narrow
= in_it_block ();
9637 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9639 if (inst
.operands
[2].shifted
)
9641 if (inst
.size_req
== 4)
9647 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9648 inst
.instruction
|= Rd
;
9649 inst
.instruction
|= Rn
<< 3;
9653 /* If we get here, it can't be done in 16 bits. */
9654 constraint (inst
.operands
[2].shifted
9655 && inst
.operands
[2].immisreg
,
9656 _("shift must be constant"));
9657 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9658 inst
.instruction
|= Rd
<< 8;
9659 inst
.instruction
|= Rs
<< 16;
9660 encode_thumb32_shifted_operand (2);
9665 /* On its face this is a lie - the instruction does set the
9666 flags. However, the only supported mnemonic in this mode
9668 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9670 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9671 _("unshifted register required"));
9672 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9673 constraint (Rd
!= Rs
,
9674 _("dest and source1 must be the same register"));
9676 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9677 inst
.instruction
|= Rd
;
9678 inst
.instruction
|= Rn
<< 3;
9682 /* Similarly, but for instructions where the arithmetic operation is
9683 commutative, so we can allow either of them to be different from
9684 the destination operand in a 16-bit instruction. For instance, all
9685 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9692 Rd
= inst
.operands
[0].reg
;
9693 Rs
= (inst
.operands
[1].present
9694 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9695 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9696 Rn
= inst
.operands
[2].reg
;
9698 reject_bad_reg (Rd
);
9699 reject_bad_reg (Rs
);
9700 if (inst
.operands
[2].isreg
)
9701 reject_bad_reg (Rn
);
9705 if (!inst
.operands
[2].isreg
)
9707 /* For an immediate, we always generate a 32-bit opcode;
9708 section relaxation will shrink it later if possible. */
9709 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9710 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9711 inst
.instruction
|= Rd
<< 8;
9712 inst
.instruction
|= Rs
<< 16;
9713 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9719 /* See if we can do this with a 16-bit instruction. */
9720 if (THUMB_SETS_FLAGS (inst
.instruction
))
9721 narrow
= !in_it_block ();
9723 narrow
= in_it_block ();
9725 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9727 if (inst
.operands
[2].shifted
)
9729 if (inst
.size_req
== 4)
9736 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9737 inst
.instruction
|= Rd
;
9738 inst
.instruction
|= Rn
<< 3;
9743 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9744 inst
.instruction
|= Rd
;
9745 inst
.instruction
|= Rs
<< 3;
9750 /* If we get here, it can't be done in 16 bits. */
9751 constraint (inst
.operands
[2].shifted
9752 && inst
.operands
[2].immisreg
,
9753 _("shift must be constant"));
9754 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9755 inst
.instruction
|= Rd
<< 8;
9756 inst
.instruction
|= Rs
<< 16;
9757 encode_thumb32_shifted_operand (2);
9762 /* On its face this is a lie - the instruction does set the
9763 flags. However, the only supported mnemonic in this mode
9765 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9767 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9768 _("unshifted register required"));
9769 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9771 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9772 inst
.instruction
|= Rd
;
9775 inst
.instruction
|= Rn
<< 3;
9777 inst
.instruction
|= Rs
<< 3;
9779 constraint (1, _("dest must overlap one source register"));
9786 if (inst
.operands
[0].present
)
9788 constraint ((inst
.instruction
& 0xf0) != 0x40
9789 && inst
.operands
[0].imm
> 0xf
9790 && inst
.operands
[0].imm
< 0x0,
9791 _("bad barrier type"));
9792 inst
.instruction
|= inst
.operands
[0].imm
;
9795 inst
.instruction
|= 0xf;
9802 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9803 constraint (msb
> 32, _("bit-field extends past end of register"));
9804 /* The instruction encoding stores the LSB and MSB,
9805 not the LSB and width. */
9806 Rd
= inst
.operands
[0].reg
;
9807 reject_bad_reg (Rd
);
9808 inst
.instruction
|= Rd
<< 8;
9809 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9810 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9811 inst
.instruction
|= msb
- 1;
9820 Rd
= inst
.operands
[0].reg
;
9821 reject_bad_reg (Rd
);
9823 /* #0 in second position is alternative syntax for bfc, which is
9824 the same instruction but with REG_PC in the Rm field. */
9825 if (!inst
.operands
[1].isreg
)
9829 Rn
= inst
.operands
[1].reg
;
9830 reject_bad_reg (Rn
);
9833 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9834 constraint (msb
> 32, _("bit-field extends past end of register"));
9835 /* The instruction encoding stores the LSB and MSB,
9836 not the LSB and width. */
9837 inst
.instruction
|= Rd
<< 8;
9838 inst
.instruction
|= Rn
<< 16;
9839 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9840 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9841 inst
.instruction
|= msb
- 1;
9849 Rd
= inst
.operands
[0].reg
;
9850 Rn
= inst
.operands
[1].reg
;
9852 reject_bad_reg (Rd
);
9853 reject_bad_reg (Rn
);
9855 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9856 _("bit-field extends past end of register"));
9857 inst
.instruction
|= Rd
<< 8;
9858 inst
.instruction
|= Rn
<< 16;
9859 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9860 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9861 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9864 /* ARM V5 Thumb BLX (argument parse)
9865 BLX <target_addr> which is BLX(1)
9866 BLX <Rm> which is BLX(2)
9867 Unfortunately, there are two different opcodes for this mnemonic.
9868 So, the insns[].value is not used, and the code here zaps values
9869 into inst.instruction.
9871 ??? How to take advantage of the additional two bits of displacement
9872 available in Thumb32 mode? Need new relocation? */
9877 set_it_insn_type_last ();
9879 if (inst
.operands
[0].isreg
)
9881 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9882 /* We have a register, so this is BLX(2). */
9883 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9887 /* No register. This must be BLX(1). */
9888 inst
.instruction
= 0xf000e800;
9889 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
9901 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9905 /* Conditional branches inside IT blocks are encoded as unconditional
9912 if (cond
!= COND_ALWAYS
)
9913 opcode
= T_MNEM_bcond
;
9915 opcode
= inst
.instruction
;
9918 && (inst
.size_req
== 4
9919 || (inst
.size_req
!= 2
9920 && (inst
.operands
[0].hasreloc
9921 || inst
.reloc
.exp
.X_op
== O_constant
))))
9923 inst
.instruction
= THUMB_OP32(opcode
);
9924 if (cond
== COND_ALWAYS
)
9925 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9928 gas_assert (cond
!= 0xF);
9929 inst
.instruction
|= cond
<< 22;
9930 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9935 inst
.instruction
= THUMB_OP16(opcode
);
9936 if (cond
== COND_ALWAYS
)
9937 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9940 inst
.instruction
|= cond
<< 8;
9941 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9943 /* Allow section relaxation. */
9944 if (unified_syntax
&& inst
.size_req
!= 2)
9945 inst
.relax
= opcode
;
9947 inst
.reloc
.type
= reloc
;
9948 inst
.reloc
.pc_rel
= 1;
9954 constraint (inst
.cond
!= COND_ALWAYS
,
9955 _("instruction is always unconditional"));
9956 if (inst
.operands
[0].present
)
9958 constraint (inst
.operands
[0].imm
> 255,
9959 _("immediate value out of range"));
9960 inst
.instruction
|= inst
.operands
[0].imm
;
9961 set_it_insn_type (NEUTRAL_IT_INSN
);
9966 do_t_branch23 (void)
9968 set_it_insn_type_last ();
9969 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
9971 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
9972 this file. We used to simply ignore the PLT reloc type here --
9973 the branch encoding is now needed to deal with TLSCALL relocs.
9974 So if we see a PLT reloc now, put it back to how it used to be to
9975 keep the preexisting behaviour. */
9976 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
9977 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9979 #if defined(OBJ_COFF)
9980 /* If the destination of the branch is a defined symbol which does not have
9981 the THUMB_FUNC attribute, then we must be calling a function which has
9982 the (interfacearm) attribute. We look for the Thumb entry point to that
9983 function and change the branch to refer to that function instead. */
9984 if ( inst
.reloc
.exp
.X_op
== O_symbol
9985 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9986 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9987 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9988 inst
.reloc
.exp
.X_add_symbol
=
9989 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9996 set_it_insn_type_last ();
9997 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9998 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9999 should cause the alignment to be checked once it is known. This is
10000 because BX PC only works if the instruction is word aligned. */
10008 set_it_insn_type_last ();
10009 Rm
= inst
.operands
[0].reg
;
10010 reject_bad_reg (Rm
);
10011 inst
.instruction
|= Rm
<< 16;
10020 Rd
= inst
.operands
[0].reg
;
10021 Rm
= inst
.operands
[1].reg
;
10023 reject_bad_reg (Rd
);
10024 reject_bad_reg (Rm
);
10026 inst
.instruction
|= Rd
<< 8;
10027 inst
.instruction
|= Rm
<< 16;
10028 inst
.instruction
|= Rm
;
10034 set_it_insn_type (OUTSIDE_IT_INSN
);
10035 inst
.instruction
|= inst
.operands
[0].imm
;
10041 set_it_insn_type (OUTSIDE_IT_INSN
);
10043 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
10044 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
10046 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
10047 inst
.instruction
= 0xf3af8000;
10048 inst
.instruction
|= imod
<< 9;
10049 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
10050 if (inst
.operands
[1].present
)
10051 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
10055 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
10056 && (inst
.operands
[0].imm
& 4),
10057 _("selected processor does not support 'A' form "
10058 "of this instruction"));
10059 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
10060 _("Thumb does not support the 2-argument "
10061 "form of this instruction"));
10062 inst
.instruction
|= inst
.operands
[0].imm
;
10066 /* THUMB CPY instruction (argument parse). */
10071 if (inst
.size_req
== 4)
10073 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10074 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10075 inst
.instruction
|= inst
.operands
[1].reg
;
10079 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10080 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10081 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10088 set_it_insn_type (OUTSIDE_IT_INSN
);
10089 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10090 inst
.instruction
|= inst
.operands
[0].reg
;
10091 inst
.reloc
.pc_rel
= 1;
10092 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10098 inst
.instruction
|= inst
.operands
[0].imm
;
10104 unsigned Rd
, Rn
, Rm
;
10106 Rd
= inst
.operands
[0].reg
;
10107 Rn
= (inst
.operands
[1].present
10108 ? inst
.operands
[1].reg
: Rd
);
10109 Rm
= inst
.operands
[2].reg
;
10111 reject_bad_reg (Rd
);
10112 reject_bad_reg (Rn
);
10113 reject_bad_reg (Rm
);
10115 inst
.instruction
|= Rd
<< 8;
10116 inst
.instruction
|= Rn
<< 16;
10117 inst
.instruction
|= Rm
;
10123 if (unified_syntax
&& inst
.size_req
== 4)
10124 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10126 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10132 unsigned int cond
= inst
.operands
[0].imm
;
10134 set_it_insn_type (IT_INSN
);
10135 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10138 /* If the condition is a negative condition, invert the mask. */
10139 if ((cond
& 0x1) == 0x0)
10141 unsigned int mask
= inst
.instruction
& 0x000f;
10143 if ((mask
& 0x7) == 0)
10144 /* no conversion needed */;
10145 else if ((mask
& 0x3) == 0)
10147 else if ((mask
& 0x1) == 0)
10152 inst
.instruction
&= 0xfff0;
10153 inst
.instruction
|= mask
;
10156 inst
.instruction
|= cond
<< 4;
10159 /* Helper function used for both push/pop and ldm/stm. */
10161 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
10165 load
= (inst
.instruction
& (1 << 20)) != 0;
10167 if (mask
& (1 << 13))
10168 inst
.error
= _("SP not allowed in register list");
10170 if ((mask
& (1 << base
)) != 0
10172 inst
.error
= _("having the base register in the register list when "
10173 "using write back is UNPREDICTABLE");
10177 if (mask
& (1 << 15))
10179 if (mask
& (1 << 14))
10180 inst
.error
= _("LR and PC should not both be in register list");
10182 set_it_insn_type_last ();
10187 if (mask
& (1 << 15))
10188 inst
.error
= _("PC not allowed in register list");
10191 if ((mask
& (mask
- 1)) == 0)
10193 /* Single register transfers implemented as str/ldr. */
10196 if (inst
.instruction
& (1 << 23))
10197 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
10199 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
10203 if (inst
.instruction
& (1 << 23))
10204 inst
.instruction
= 0x00800000; /* ia -> [base] */
10206 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
10209 inst
.instruction
|= 0xf8400000;
10211 inst
.instruction
|= 0x00100000;
10213 mask
= ffs (mask
) - 1;
10216 else if (writeback
)
10217 inst
.instruction
|= WRITE_BACK
;
10219 inst
.instruction
|= mask
;
10220 inst
.instruction
|= base
<< 16;
10226 /* This really doesn't seem worth it. */
10227 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10228 _("expression too complex"));
10229 constraint (inst
.operands
[1].writeback
,
10230 _("Thumb load/store multiple does not support {reglist}^"));
10232 if (unified_syntax
)
10234 bfd_boolean narrow
;
10238 /* See if we can use a 16-bit instruction. */
10239 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10240 && inst
.size_req
!= 4
10241 && !(inst
.operands
[1].imm
& ~0xff))
10243 mask
= 1 << inst
.operands
[0].reg
;
10245 if (inst
.operands
[0].reg
<= 7)
10247 if (inst
.instruction
== T_MNEM_stmia
10248 ? inst
.operands
[0].writeback
10249 : (inst
.operands
[0].writeback
10250 == !(inst
.operands
[1].imm
& mask
)))
10252 if (inst
.instruction
== T_MNEM_stmia
10253 && (inst
.operands
[1].imm
& mask
)
10254 && (inst
.operands
[1].imm
& (mask
- 1)))
10255 as_warn (_("value stored for r%d is UNKNOWN"),
10256 inst
.operands
[0].reg
);
10258 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10259 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10260 inst
.instruction
|= inst
.operands
[1].imm
;
10263 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10265 /* This means 1 register in reg list one of 3 situations:
10266 1. Instruction is stmia, but without writeback.
10267 2. lmdia without writeback, but with Rn not in
10269 3. ldmia with writeback, but with Rn in reglist.
10270 Case 3 is UNPREDICTABLE behaviour, so we handle
10271 case 1 and 2 which can be converted into a 16-bit
10272 str or ldr. The SP cases are handled below. */
10273 unsigned long opcode
;
10274 /* First, record an error for Case 3. */
10275 if (inst
.operands
[1].imm
& mask
10276 && inst
.operands
[0].writeback
)
10278 _("having the base register in the register list when "
10279 "using write back is UNPREDICTABLE");
10281 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10283 inst
.instruction
= THUMB_OP16 (opcode
);
10284 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10285 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10289 else if (inst
.operands
[0] .reg
== REG_SP
)
10291 if (inst
.operands
[0].writeback
)
10294 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10295 ? T_MNEM_push
: T_MNEM_pop
);
10296 inst
.instruction
|= inst
.operands
[1].imm
;
10299 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10302 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10303 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10304 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10312 if (inst
.instruction
< 0xffff)
10313 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10315 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10316 inst
.operands
[0].writeback
);
10321 constraint (inst
.operands
[0].reg
> 7
10322 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10323 constraint (inst
.instruction
!= T_MNEM_ldmia
10324 && inst
.instruction
!= T_MNEM_stmia
,
10325 _("Thumb-2 instruction only valid in unified syntax"));
10326 if (inst
.instruction
== T_MNEM_stmia
)
10328 if (!inst
.operands
[0].writeback
)
10329 as_warn (_("this instruction will write back the base register"));
10330 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10331 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10332 as_warn (_("value stored for r%d is UNKNOWN"),
10333 inst
.operands
[0].reg
);
10337 if (!inst
.operands
[0].writeback
10338 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10339 as_warn (_("this instruction will write back the base register"));
10340 else if (inst
.operands
[0].writeback
10341 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10342 as_warn (_("this instruction will not write back the base register"));
10345 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10346 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10347 inst
.instruction
|= inst
.operands
[1].imm
;
10354 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10355 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10356 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10357 || inst
.operands
[1].negative
,
10360 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10362 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10363 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10364 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10370 if (!inst
.operands
[1].present
)
10372 constraint (inst
.operands
[0].reg
== REG_LR
,
10373 _("r14 not allowed as first register "
10374 "when second register is omitted"));
10375 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10377 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10380 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10381 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10382 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10388 unsigned long opcode
;
10391 if (inst
.operands
[0].isreg
10392 && !inst
.operands
[0].preind
10393 && inst
.operands
[0].reg
== REG_PC
)
10394 set_it_insn_type_last ();
10396 opcode
= inst
.instruction
;
10397 if (unified_syntax
)
10399 if (!inst
.operands
[1].isreg
)
10401 if (opcode
<= 0xffff)
10402 inst
.instruction
= THUMB_OP32 (opcode
);
10403 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10406 if (inst
.operands
[1].isreg
10407 && !inst
.operands
[1].writeback
10408 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10409 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10410 && opcode
<= 0xffff
10411 && inst
.size_req
!= 4)
10413 /* Insn may have a 16-bit form. */
10414 Rn
= inst
.operands
[1].reg
;
10415 if (inst
.operands
[1].immisreg
)
10417 inst
.instruction
= THUMB_OP16 (opcode
);
10419 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10421 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10422 reject_bad_reg (inst
.operands
[1].imm
);
10424 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10425 && opcode
!= T_MNEM_ldrsb
)
10426 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10427 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10434 if (inst
.reloc
.pc_rel
)
10435 opcode
= T_MNEM_ldr_pc2
;
10437 opcode
= T_MNEM_ldr_pc
;
10441 if (opcode
== T_MNEM_ldr
)
10442 opcode
= T_MNEM_ldr_sp
;
10444 opcode
= T_MNEM_str_sp
;
10446 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10450 inst
.instruction
= inst
.operands
[0].reg
;
10451 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10453 inst
.instruction
|= THUMB_OP16 (opcode
);
10454 if (inst
.size_req
== 2)
10455 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10457 inst
.relax
= opcode
;
10461 /* Definitely a 32-bit variant. */
10463 /* Warning for Erratum 752419. */
10464 if (opcode
== T_MNEM_ldr
10465 && inst
.operands
[0].reg
== REG_SP
10466 && inst
.operands
[1].writeback
== 1
10467 && !inst
.operands
[1].immisreg
)
10469 if (no_cpu_selected ()
10470 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
10471 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
10472 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
10473 as_warn (_("This instruction may be unpredictable "
10474 "if executed on M-profile cores "
10475 "with interrupts enabled."));
10478 /* Do some validations regarding addressing modes. */
10479 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10480 && opcode
!= T_MNEM_str
)
10481 reject_bad_reg (inst
.operands
[1].imm
);
10483 inst
.instruction
= THUMB_OP32 (opcode
);
10484 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10485 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10489 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10491 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10493 /* Only [Rn,Rm] is acceptable. */
10494 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10495 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10496 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10497 || inst
.operands
[1].negative
,
10498 _("Thumb does not support this addressing mode"));
10499 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10503 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10504 if (!inst
.operands
[1].isreg
)
10505 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10508 constraint (!inst
.operands
[1].preind
10509 || inst
.operands
[1].shifted
10510 || inst
.operands
[1].writeback
,
10511 _("Thumb does not support this addressing mode"));
10512 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10514 constraint (inst
.instruction
& 0x0600,
10515 _("byte or halfword not valid for base register"));
10516 constraint (inst
.operands
[1].reg
== REG_PC
10517 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10518 _("r15 based store not allowed"));
10519 constraint (inst
.operands
[1].immisreg
,
10520 _("invalid base register for register offset"));
10522 if (inst
.operands
[1].reg
== REG_PC
)
10523 inst
.instruction
= T_OPCODE_LDR_PC
;
10524 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10525 inst
.instruction
= T_OPCODE_LDR_SP
;
10527 inst
.instruction
= T_OPCODE_STR_SP
;
10529 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10530 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10534 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10535 if (!inst
.operands
[1].immisreg
)
10537 /* Immediate offset. */
10538 inst
.instruction
|= inst
.operands
[0].reg
;
10539 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10540 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10544 /* Register offset. */
10545 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10546 constraint (inst
.operands
[1].negative
,
10547 _("Thumb does not support this addressing mode"));
10550 switch (inst
.instruction
)
10552 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10553 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10554 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10555 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10556 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10557 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10558 case 0x5600 /* ldrsb */:
10559 case 0x5e00 /* ldrsh */: break;
10563 inst
.instruction
|= inst
.operands
[0].reg
;
10564 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10565 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10571 if (!inst
.operands
[1].present
)
10573 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10574 constraint (inst
.operands
[0].reg
== REG_LR
,
10575 _("r14 not allowed here"));
10577 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10578 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10579 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10585 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10586 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10592 unsigned Rd
, Rn
, Rm
, Ra
;
10594 Rd
= inst
.operands
[0].reg
;
10595 Rn
= inst
.operands
[1].reg
;
10596 Rm
= inst
.operands
[2].reg
;
10597 Ra
= inst
.operands
[3].reg
;
10599 reject_bad_reg (Rd
);
10600 reject_bad_reg (Rn
);
10601 reject_bad_reg (Rm
);
10602 reject_bad_reg (Ra
);
10604 inst
.instruction
|= Rd
<< 8;
10605 inst
.instruction
|= Rn
<< 16;
10606 inst
.instruction
|= Rm
;
10607 inst
.instruction
|= Ra
<< 12;
10613 unsigned RdLo
, RdHi
, Rn
, Rm
;
10615 RdLo
= inst
.operands
[0].reg
;
10616 RdHi
= inst
.operands
[1].reg
;
10617 Rn
= inst
.operands
[2].reg
;
10618 Rm
= inst
.operands
[3].reg
;
10620 reject_bad_reg (RdLo
);
10621 reject_bad_reg (RdHi
);
10622 reject_bad_reg (Rn
);
10623 reject_bad_reg (Rm
);
10625 inst
.instruction
|= RdLo
<< 12;
10626 inst
.instruction
|= RdHi
<< 8;
10627 inst
.instruction
|= Rn
<< 16;
10628 inst
.instruction
|= Rm
;
10632 do_t_mov_cmp (void)
10636 Rn
= inst
.operands
[0].reg
;
10637 Rm
= inst
.operands
[1].reg
;
10640 set_it_insn_type_last ();
10642 if (unified_syntax
)
10644 int r0off
= (inst
.instruction
== T_MNEM_mov
10645 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10646 unsigned long opcode
;
10647 bfd_boolean narrow
;
10648 bfd_boolean low_regs
;
10650 low_regs
= (Rn
<= 7 && Rm
<= 7);
10651 opcode
= inst
.instruction
;
10652 if (in_it_block ())
10653 narrow
= opcode
!= T_MNEM_movs
;
10655 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10656 if (inst
.size_req
== 4
10657 || inst
.operands
[1].shifted
)
10660 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10661 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10662 && !inst
.operands
[1].shifted
10666 inst
.instruction
= T2_SUBS_PC_LR
;
10670 if (opcode
== T_MNEM_cmp
)
10672 constraint (Rn
== REG_PC
, BAD_PC
);
10675 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10677 warn_deprecated_sp (Rm
);
10678 /* R15 was documented as a valid choice for Rm in ARMv6,
10679 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10680 tools reject R15, so we do too. */
10681 constraint (Rm
== REG_PC
, BAD_PC
);
10684 reject_bad_reg (Rm
);
10686 else if (opcode
== T_MNEM_mov
10687 || opcode
== T_MNEM_movs
)
10689 if (inst
.operands
[1].isreg
)
10691 if (opcode
== T_MNEM_movs
)
10693 reject_bad_reg (Rn
);
10694 reject_bad_reg (Rm
);
10698 /* This is mov.n. */
10699 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10700 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10702 as_warn (_("Use of r%u as a source register is "
10703 "deprecated when r%u is the destination "
10704 "register."), Rm
, Rn
);
10709 /* This is mov.w. */
10710 constraint (Rn
== REG_PC
, BAD_PC
);
10711 constraint (Rm
== REG_PC
, BAD_PC
);
10712 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10716 reject_bad_reg (Rn
);
10719 if (!inst
.operands
[1].isreg
)
10721 /* Immediate operand. */
10722 if (!in_it_block () && opcode
== T_MNEM_mov
)
10724 if (low_regs
&& narrow
)
10726 inst
.instruction
= THUMB_OP16 (opcode
);
10727 inst
.instruction
|= Rn
<< 8;
10728 if (inst
.size_req
== 2)
10729 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10731 inst
.relax
= opcode
;
10735 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10736 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10737 inst
.instruction
|= Rn
<< r0off
;
10738 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10741 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10742 && (inst
.instruction
== T_MNEM_mov
10743 || inst
.instruction
== T_MNEM_movs
))
10745 /* Register shifts are encoded as separate shift instructions. */
10746 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10748 if (in_it_block ())
10753 if (inst
.size_req
== 4)
10756 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10762 switch (inst
.operands
[1].shift_kind
)
10765 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10768 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10771 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10774 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10780 inst
.instruction
= opcode
;
10783 inst
.instruction
|= Rn
;
10784 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10789 inst
.instruction
|= CONDS_BIT
;
10791 inst
.instruction
|= Rn
<< 8;
10792 inst
.instruction
|= Rm
<< 16;
10793 inst
.instruction
|= inst
.operands
[1].imm
;
10798 /* Some mov with immediate shift have narrow variants.
10799 Register shifts are handled above. */
10800 if (low_regs
&& inst
.operands
[1].shifted
10801 && (inst
.instruction
== T_MNEM_mov
10802 || inst
.instruction
== T_MNEM_movs
))
10804 if (in_it_block ())
10805 narrow
= (inst
.instruction
== T_MNEM_mov
);
10807 narrow
= (inst
.instruction
== T_MNEM_movs
);
10812 switch (inst
.operands
[1].shift_kind
)
10814 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10815 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10816 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10817 default: narrow
= FALSE
; break;
10823 inst
.instruction
|= Rn
;
10824 inst
.instruction
|= Rm
<< 3;
10825 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10829 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10830 inst
.instruction
|= Rn
<< r0off
;
10831 encode_thumb32_shifted_operand (1);
10835 switch (inst
.instruction
)
10838 inst
.instruction
= T_OPCODE_MOV_HR
;
10839 inst
.instruction
|= (Rn
& 0x8) << 4;
10840 inst
.instruction
|= (Rn
& 0x7);
10841 inst
.instruction
|= Rm
<< 3;
10845 /* We know we have low registers at this point.
10846 Generate LSLS Rd, Rs, #0. */
10847 inst
.instruction
= T_OPCODE_LSL_I
;
10848 inst
.instruction
|= Rn
;
10849 inst
.instruction
|= Rm
<< 3;
10855 inst
.instruction
= T_OPCODE_CMP_LR
;
10856 inst
.instruction
|= Rn
;
10857 inst
.instruction
|= Rm
<< 3;
10861 inst
.instruction
= T_OPCODE_CMP_HR
;
10862 inst
.instruction
|= (Rn
& 0x8) << 4;
10863 inst
.instruction
|= (Rn
& 0x7);
10864 inst
.instruction
|= Rm
<< 3;
10871 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10873 /* PR 10443: Do not silently ignore shifted operands. */
10874 constraint (inst
.operands
[1].shifted
,
10875 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10877 if (inst
.operands
[1].isreg
)
10879 if (Rn
< 8 && Rm
< 8)
10881 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10882 since a MOV instruction produces unpredictable results. */
10883 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10884 inst
.instruction
= T_OPCODE_ADD_I3
;
10886 inst
.instruction
= T_OPCODE_CMP_LR
;
10888 inst
.instruction
|= Rn
;
10889 inst
.instruction
|= Rm
<< 3;
10893 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10894 inst
.instruction
= T_OPCODE_MOV_HR
;
10896 inst
.instruction
= T_OPCODE_CMP_HR
;
10902 constraint (Rn
> 7,
10903 _("only lo regs allowed with immediate"));
10904 inst
.instruction
|= Rn
<< 8;
10905 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10916 top
= (inst
.instruction
& 0x00800000) != 0;
10917 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10919 constraint (top
, _(":lower16: not allowed this instruction"));
10920 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10922 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10924 constraint (!top
, _(":upper16: not allowed this instruction"));
10925 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10928 Rd
= inst
.operands
[0].reg
;
10929 reject_bad_reg (Rd
);
10931 inst
.instruction
|= Rd
<< 8;
10932 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10934 imm
= inst
.reloc
.exp
.X_add_number
;
10935 inst
.instruction
|= (imm
& 0xf000) << 4;
10936 inst
.instruction
|= (imm
& 0x0800) << 15;
10937 inst
.instruction
|= (imm
& 0x0700) << 4;
10938 inst
.instruction
|= (imm
& 0x00ff);
10943 do_t_mvn_tst (void)
10947 Rn
= inst
.operands
[0].reg
;
10948 Rm
= inst
.operands
[1].reg
;
10950 if (inst
.instruction
== T_MNEM_cmp
10951 || inst
.instruction
== T_MNEM_cmn
)
10952 constraint (Rn
== REG_PC
, BAD_PC
);
10954 reject_bad_reg (Rn
);
10955 reject_bad_reg (Rm
);
10957 if (unified_syntax
)
10959 int r0off
= (inst
.instruction
== T_MNEM_mvn
10960 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10961 bfd_boolean narrow
;
10963 if (inst
.size_req
== 4
10964 || inst
.instruction
> 0xffff
10965 || inst
.operands
[1].shifted
10966 || Rn
> 7 || Rm
> 7)
10968 else if (inst
.instruction
== T_MNEM_cmn
)
10970 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10971 narrow
= !in_it_block ();
10973 narrow
= in_it_block ();
10975 if (!inst
.operands
[1].isreg
)
10977 /* For an immediate, we always generate a 32-bit opcode;
10978 section relaxation will shrink it later if possible. */
10979 if (inst
.instruction
< 0xffff)
10980 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10981 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10982 inst
.instruction
|= Rn
<< r0off
;
10983 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10987 /* See if we can do this with a 16-bit instruction. */
10990 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10991 inst
.instruction
|= Rn
;
10992 inst
.instruction
|= Rm
<< 3;
10996 constraint (inst
.operands
[1].shifted
10997 && inst
.operands
[1].immisreg
,
10998 _("shift must be constant"));
10999 if (inst
.instruction
< 0xffff)
11000 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11001 inst
.instruction
|= Rn
<< r0off
;
11002 encode_thumb32_shifted_operand (1);
11008 constraint (inst
.instruction
> 0xffff
11009 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
11010 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
11011 _("unshifted register required"));
11012 constraint (Rn
> 7 || Rm
> 7,
11015 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11016 inst
.instruction
|= Rn
;
11017 inst
.instruction
|= Rm
<< 3;
11026 if (do_vfp_nsyn_mrs () == SUCCESS
)
11029 Rd
= inst
.operands
[0].reg
;
11030 reject_bad_reg (Rd
);
11031 inst
.instruction
|= Rd
<< 8;
11033 if (inst
.operands
[1].isreg
)
11035 unsigned br
= inst
.operands
[1].reg
;
11036 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
11037 as_bad (_("bad register for mrs"));
11039 inst
.instruction
|= br
& (0xf << 16);
11040 inst
.instruction
|= (br
& 0x300) >> 4;
11041 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
11045 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11047 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11048 constraint (flags
!= 0, _("selected processor does not support "
11049 "requested special purpose register"));
11051 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11053 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
11054 _("'APSR', 'CPSR' or 'SPSR' expected"));
11056 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11057 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
11058 inst
.instruction
|= 0xf0000;
11068 if (do_vfp_nsyn_msr () == SUCCESS
)
11071 constraint (!inst
.operands
[1].isreg
,
11072 _("Thumb encoding does not support an immediate here"));
11074 if (inst
.operands
[0].isreg
)
11075 flags
= (int)(inst
.operands
[0].reg
);
11077 flags
= inst
.operands
[0].imm
;
11079 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11081 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11083 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11084 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11085 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11087 _("selected processor does not support requested special "
11088 "purpose register"));
11091 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11092 "requested special purpose register"));
11094 Rn
= inst
.operands
[1].reg
;
11095 reject_bad_reg (Rn
);
11097 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11098 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11099 inst
.instruction
|= (flags
& 0x300) >> 4;
11100 inst
.instruction
|= (flags
& 0xff);
11101 inst
.instruction
|= Rn
<< 16;
11107 bfd_boolean narrow
;
11108 unsigned Rd
, Rn
, Rm
;
11110 if (!inst
.operands
[2].present
)
11111 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11113 Rd
= inst
.operands
[0].reg
;
11114 Rn
= inst
.operands
[1].reg
;
11115 Rm
= inst
.operands
[2].reg
;
11117 if (unified_syntax
)
11119 if (inst
.size_req
== 4
11125 else if (inst
.instruction
== T_MNEM_muls
)
11126 narrow
= !in_it_block ();
11128 narrow
= in_it_block ();
11132 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
11133 constraint (Rn
> 7 || Rm
> 7,
11140 /* 16-bit MULS/Conditional MUL. */
11141 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11142 inst
.instruction
|= Rd
;
11145 inst
.instruction
|= Rm
<< 3;
11147 inst
.instruction
|= Rn
<< 3;
11149 constraint (1, _("dest must overlap one source register"));
11153 constraint (inst
.instruction
!= T_MNEM_mul
,
11154 _("Thumb-2 MUL must not set flags"));
11156 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11157 inst
.instruction
|= Rd
<< 8;
11158 inst
.instruction
|= Rn
<< 16;
11159 inst
.instruction
|= Rm
<< 0;
11161 reject_bad_reg (Rd
);
11162 reject_bad_reg (Rn
);
11163 reject_bad_reg (Rm
);
11170 unsigned RdLo
, RdHi
, Rn
, Rm
;
11172 RdLo
= inst
.operands
[0].reg
;
11173 RdHi
= inst
.operands
[1].reg
;
11174 Rn
= inst
.operands
[2].reg
;
11175 Rm
= inst
.operands
[3].reg
;
11177 reject_bad_reg (RdLo
);
11178 reject_bad_reg (RdHi
);
11179 reject_bad_reg (Rn
);
11180 reject_bad_reg (Rm
);
11182 inst
.instruction
|= RdLo
<< 12;
11183 inst
.instruction
|= RdHi
<< 8;
11184 inst
.instruction
|= Rn
<< 16;
11185 inst
.instruction
|= Rm
;
11188 as_tsktsk (_("rdhi and rdlo must be different"));
11194 set_it_insn_type (NEUTRAL_IT_INSN
);
11196 if (unified_syntax
)
11198 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
11200 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11201 inst
.instruction
|= inst
.operands
[0].imm
;
11205 /* PR9722: Check for Thumb2 availability before
11206 generating a thumb2 nop instruction. */
11207 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
11209 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11210 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
11213 inst
.instruction
= 0x46c0;
11218 constraint (inst
.operands
[0].present
,
11219 _("Thumb does not support NOP with hints"));
11220 inst
.instruction
= 0x46c0;
11227 if (unified_syntax
)
11229 bfd_boolean narrow
;
11231 if (THUMB_SETS_FLAGS (inst
.instruction
))
11232 narrow
= !in_it_block ();
11234 narrow
= in_it_block ();
11235 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11237 if (inst
.size_req
== 4)
11242 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11243 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11244 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11248 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11249 inst
.instruction
|= inst
.operands
[0].reg
;
11250 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11255 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11257 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11259 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11260 inst
.instruction
|= inst
.operands
[0].reg
;
11261 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11270 Rd
= inst
.operands
[0].reg
;
11271 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11273 reject_bad_reg (Rd
);
11274 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11275 reject_bad_reg (Rn
);
11277 inst
.instruction
|= Rd
<< 8;
11278 inst
.instruction
|= Rn
<< 16;
11280 if (!inst
.operands
[2].isreg
)
11282 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11283 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11289 Rm
= inst
.operands
[2].reg
;
11290 reject_bad_reg (Rm
);
11292 constraint (inst
.operands
[2].shifted
11293 && inst
.operands
[2].immisreg
,
11294 _("shift must be constant"));
11295 encode_thumb32_shifted_operand (2);
11302 unsigned Rd
, Rn
, Rm
;
11304 Rd
= inst
.operands
[0].reg
;
11305 Rn
= inst
.operands
[1].reg
;
11306 Rm
= inst
.operands
[2].reg
;
11308 reject_bad_reg (Rd
);
11309 reject_bad_reg (Rn
);
11310 reject_bad_reg (Rm
);
11312 inst
.instruction
|= Rd
<< 8;
11313 inst
.instruction
|= Rn
<< 16;
11314 inst
.instruction
|= Rm
;
11315 if (inst
.operands
[3].present
)
11317 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11318 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11319 _("expression too complex"));
11320 inst
.instruction
|= (val
& 0x1c) << 10;
11321 inst
.instruction
|= (val
& 0x03) << 6;
11328 if (!inst
.operands
[3].present
)
11332 inst
.instruction
&= ~0x00000020;
11334 /* PR 10168. Swap the Rm and Rn registers. */
11335 Rtmp
= inst
.operands
[1].reg
;
11336 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11337 inst
.operands
[2].reg
= Rtmp
;
11345 if (inst
.operands
[0].immisreg
)
11346 reject_bad_reg (inst
.operands
[0].imm
);
11348 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11352 do_t_push_pop (void)
11356 constraint (inst
.operands
[0].writeback
,
11357 _("push/pop do not support {reglist}^"));
11358 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11359 _("expression too complex"));
11361 mask
= inst
.operands
[0].imm
;
11362 if ((mask
& ~0xff) == 0)
11363 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11364 else if ((inst
.instruction
== T_MNEM_push
11365 && (mask
& ~0xff) == 1 << REG_LR
)
11366 || (inst
.instruction
== T_MNEM_pop
11367 && (mask
& ~0xff) == 1 << REG_PC
))
11369 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11370 inst
.instruction
|= THUMB_PP_PC_LR
;
11371 inst
.instruction
|= mask
& 0xff;
11373 else if (unified_syntax
)
11375 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11376 encode_thumb2_ldmstm (13, mask
, TRUE
);
11380 inst
.error
= _("invalid register list to push/pop instruction");
11390 Rd
= inst
.operands
[0].reg
;
11391 Rm
= inst
.operands
[1].reg
;
11393 reject_bad_reg (Rd
);
11394 reject_bad_reg (Rm
);
11396 inst
.instruction
|= Rd
<< 8;
11397 inst
.instruction
|= Rm
<< 16;
11398 inst
.instruction
|= Rm
;
11406 Rd
= inst
.operands
[0].reg
;
11407 Rm
= inst
.operands
[1].reg
;
11409 reject_bad_reg (Rd
);
11410 reject_bad_reg (Rm
);
11412 if (Rd
<= 7 && Rm
<= 7
11413 && inst
.size_req
!= 4)
11415 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11416 inst
.instruction
|= Rd
;
11417 inst
.instruction
|= Rm
<< 3;
11419 else if (unified_syntax
)
11421 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11422 inst
.instruction
|= Rd
<< 8;
11423 inst
.instruction
|= Rm
<< 16;
11424 inst
.instruction
|= Rm
;
11427 inst
.error
= BAD_HIREG
;
11435 Rd
= inst
.operands
[0].reg
;
11436 Rm
= inst
.operands
[1].reg
;
11438 reject_bad_reg (Rd
);
11439 reject_bad_reg (Rm
);
11441 inst
.instruction
|= Rd
<< 8;
11442 inst
.instruction
|= Rm
;
11450 Rd
= inst
.operands
[0].reg
;
11451 Rs
= (inst
.operands
[1].present
11452 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11453 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11455 reject_bad_reg (Rd
);
11456 reject_bad_reg (Rs
);
11457 if (inst
.operands
[2].isreg
)
11458 reject_bad_reg (inst
.operands
[2].reg
);
11460 inst
.instruction
|= Rd
<< 8;
11461 inst
.instruction
|= Rs
<< 16;
11462 if (!inst
.operands
[2].isreg
)
11464 bfd_boolean narrow
;
11466 if ((inst
.instruction
& 0x00100000) != 0)
11467 narrow
= !in_it_block ();
11469 narrow
= in_it_block ();
11471 if (Rd
> 7 || Rs
> 7)
11474 if (inst
.size_req
== 4 || !unified_syntax
)
11477 if (inst
.reloc
.exp
.X_op
!= O_constant
11478 || inst
.reloc
.exp
.X_add_number
!= 0)
11481 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11482 relaxation, but it doesn't seem worth the hassle. */
11485 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11486 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11487 inst
.instruction
|= Rs
<< 3;
11488 inst
.instruction
|= Rd
;
11492 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11493 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11497 encode_thumb32_shifted_operand (2);
11503 set_it_insn_type (OUTSIDE_IT_INSN
);
11504 if (inst
.operands
[0].imm
)
11505 inst
.instruction
|= 0x8;
11511 if (!inst
.operands
[1].present
)
11512 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11514 if (unified_syntax
)
11516 bfd_boolean narrow
;
11519 switch (inst
.instruction
)
11522 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11524 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11526 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11528 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11532 if (THUMB_SETS_FLAGS (inst
.instruction
))
11533 narrow
= !in_it_block ();
11535 narrow
= in_it_block ();
11536 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11538 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11540 if (inst
.operands
[2].isreg
11541 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11542 || inst
.operands
[2].reg
> 7))
11544 if (inst
.size_req
== 4)
11547 reject_bad_reg (inst
.operands
[0].reg
);
11548 reject_bad_reg (inst
.operands
[1].reg
);
11552 if (inst
.operands
[2].isreg
)
11554 reject_bad_reg (inst
.operands
[2].reg
);
11555 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11556 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11557 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11558 inst
.instruction
|= inst
.operands
[2].reg
;
11560 /* PR 12854: Error on extraneous shifts. */
11561 constraint (inst
.operands
[2].shifted
,
11562 _("extraneous shift as part of operand to shift insn"));
11566 inst
.operands
[1].shifted
= 1;
11567 inst
.operands
[1].shift_kind
= shift_kind
;
11568 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11569 ? T_MNEM_movs
: T_MNEM_mov
);
11570 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11571 encode_thumb32_shifted_operand (1);
11572 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11573 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11578 if (inst
.operands
[2].isreg
)
11580 switch (shift_kind
)
11582 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11583 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11584 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11585 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11589 inst
.instruction
|= inst
.operands
[0].reg
;
11590 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11592 /* PR 12854: Error on extraneous shifts. */
11593 constraint (inst
.operands
[2].shifted
,
11594 _("extraneous shift as part of operand to shift insn"));
11598 switch (shift_kind
)
11600 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11601 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11602 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11605 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11606 inst
.instruction
|= inst
.operands
[0].reg
;
11607 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11613 constraint (inst
.operands
[0].reg
> 7
11614 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11615 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11617 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11619 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11620 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11621 _("source1 and dest must be same register"));
11623 switch (inst
.instruction
)
11625 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11626 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11627 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11628 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11632 inst
.instruction
|= inst
.operands
[0].reg
;
11633 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11635 /* PR 12854: Error on extraneous shifts. */
11636 constraint (inst
.operands
[2].shifted
,
11637 _("extraneous shift as part of operand to shift insn"));
11641 switch (inst
.instruction
)
11643 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11644 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11645 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11646 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11649 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11650 inst
.instruction
|= inst
.operands
[0].reg
;
11651 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11659 unsigned Rd
, Rn
, Rm
;
11661 Rd
= inst
.operands
[0].reg
;
11662 Rn
= inst
.operands
[1].reg
;
11663 Rm
= inst
.operands
[2].reg
;
11665 reject_bad_reg (Rd
);
11666 reject_bad_reg (Rn
);
11667 reject_bad_reg (Rm
);
11669 inst
.instruction
|= Rd
<< 8;
11670 inst
.instruction
|= Rn
<< 16;
11671 inst
.instruction
|= Rm
;
11677 unsigned Rd
, Rn
, Rm
;
11679 Rd
= inst
.operands
[0].reg
;
11680 Rm
= inst
.operands
[1].reg
;
11681 Rn
= inst
.operands
[2].reg
;
11683 reject_bad_reg (Rd
);
11684 reject_bad_reg (Rn
);
11685 reject_bad_reg (Rm
);
11687 inst
.instruction
|= Rd
<< 8;
11688 inst
.instruction
|= Rn
<< 16;
11689 inst
.instruction
|= Rm
;
11695 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11696 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
11697 _("SMC is not permitted on this architecture"));
11698 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11699 _("expression too complex"));
11700 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11701 inst
.instruction
|= (value
& 0xf000) >> 12;
11702 inst
.instruction
|= (value
& 0x0ff0);
11703 inst
.instruction
|= (value
& 0x000f) << 16;
11709 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11711 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11712 inst
.instruction
|= (value
& 0x0fff);
11713 inst
.instruction
|= (value
& 0xf000) << 4;
11717 do_t_ssat_usat (int bias
)
11721 Rd
= inst
.operands
[0].reg
;
11722 Rn
= inst
.operands
[2].reg
;
11724 reject_bad_reg (Rd
);
11725 reject_bad_reg (Rn
);
11727 inst
.instruction
|= Rd
<< 8;
11728 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11729 inst
.instruction
|= Rn
<< 16;
11731 if (inst
.operands
[3].present
)
11733 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11735 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11737 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11738 _("expression too complex"));
11740 if (shift_amount
!= 0)
11742 constraint (shift_amount
> 31,
11743 _("shift expression is too large"));
11745 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11746 inst
.instruction
|= 0x00200000; /* sh bit. */
11748 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11749 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11757 do_t_ssat_usat (1);
11765 Rd
= inst
.operands
[0].reg
;
11766 Rn
= inst
.operands
[2].reg
;
11768 reject_bad_reg (Rd
);
11769 reject_bad_reg (Rn
);
11771 inst
.instruction
|= Rd
<< 8;
11772 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11773 inst
.instruction
|= Rn
<< 16;
11779 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11780 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11781 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11782 || inst
.operands
[2].negative
,
11785 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11787 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11788 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11789 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11790 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11796 if (!inst
.operands
[2].present
)
11797 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11799 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11800 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11801 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11804 inst
.instruction
|= inst
.operands
[0].reg
;
11805 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11806 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11807 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11813 unsigned Rd
, Rn
, Rm
;
11815 Rd
= inst
.operands
[0].reg
;
11816 Rn
= inst
.operands
[1].reg
;
11817 Rm
= inst
.operands
[2].reg
;
11819 reject_bad_reg (Rd
);
11820 reject_bad_reg (Rn
);
11821 reject_bad_reg (Rm
);
11823 inst
.instruction
|= Rd
<< 8;
11824 inst
.instruction
|= Rn
<< 16;
11825 inst
.instruction
|= Rm
;
11826 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11834 Rd
= inst
.operands
[0].reg
;
11835 Rm
= inst
.operands
[1].reg
;
11837 reject_bad_reg (Rd
);
11838 reject_bad_reg (Rm
);
11840 if (inst
.instruction
<= 0xffff
11841 && inst
.size_req
!= 4
11842 && Rd
<= 7 && Rm
<= 7
11843 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11845 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11846 inst
.instruction
|= Rd
;
11847 inst
.instruction
|= Rm
<< 3;
11849 else if (unified_syntax
)
11851 if (inst
.instruction
<= 0xffff)
11852 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11853 inst
.instruction
|= Rd
<< 8;
11854 inst
.instruction
|= Rm
;
11855 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11859 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11860 _("Thumb encoding does not support rotation"));
11861 constraint (1, BAD_HIREG
);
11868 /* We have to do the following check manually as ARM_EXT_OS only applies
11870 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
11872 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
11873 /* This only applies to the v6m howver, not later architectures. */
11874 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
11875 as_bad (_("SVC is not permitted on this architecture"));
11876 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
11879 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11888 half
= (inst
.instruction
& 0x10) != 0;
11889 set_it_insn_type_last ();
11890 constraint (inst
.operands
[0].immisreg
,
11891 _("instruction requires register index"));
11893 Rn
= inst
.operands
[0].reg
;
11894 Rm
= inst
.operands
[0].imm
;
11896 constraint (Rn
== REG_SP
, BAD_SP
);
11897 reject_bad_reg (Rm
);
11899 constraint (!half
&& inst
.operands
[0].shifted
,
11900 _("instruction does not allow shifted index"));
11901 inst
.instruction
|= (Rn
<< 16) | Rm
;
11907 do_t_ssat_usat (0);
11915 Rd
= inst
.operands
[0].reg
;
11916 Rn
= inst
.operands
[2].reg
;
11918 reject_bad_reg (Rd
);
11919 reject_bad_reg (Rn
);
11921 inst
.instruction
|= Rd
<< 8;
11922 inst
.instruction
|= inst
.operands
[1].imm
;
11923 inst
.instruction
|= Rn
<< 16;
11926 /* Neon instruction encoder helpers. */
11928 /* Encodings for the different types for various Neon opcodes. */
11930 /* An "invalid" code for the following tables. */
11933 struct neon_tab_entry
11936 unsigned float_or_poly
;
11937 unsigned scalar_or_imm
;
11940 /* Map overloaded Neon opcodes to their respective encodings. */
11941 #define NEON_ENC_TAB \
11942 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11943 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11944 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11945 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11946 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11947 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11948 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11949 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11950 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11951 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11952 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11953 /* Register variants of the following two instructions are encoded as
11954 vcge / vcgt with the operands reversed. */ \
11955 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11956 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11957 X(vfma, N_INV, 0x0000c10, N_INV), \
11958 X(vfms, N_INV, 0x0200c10, N_INV), \
11959 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11960 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11961 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11962 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11963 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11964 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11965 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11966 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11967 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11968 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11969 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11970 X(vshl, 0x0000400, N_INV, 0x0800510), \
11971 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11972 X(vand, 0x0000110, N_INV, 0x0800030), \
11973 X(vbic, 0x0100110, N_INV, 0x0800030), \
11974 X(veor, 0x1000110, N_INV, N_INV), \
11975 X(vorn, 0x0300110, N_INV, 0x0800010), \
11976 X(vorr, 0x0200110, N_INV, 0x0800010), \
11977 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11978 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11979 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11980 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11981 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11982 X(vst1, 0x0000000, 0x0800000, N_INV), \
11983 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11984 X(vst2, 0x0000100, 0x0800100, N_INV), \
11985 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11986 X(vst3, 0x0000200, 0x0800200, N_INV), \
11987 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11988 X(vst4, 0x0000300, 0x0800300, N_INV), \
11989 X(vmovn, 0x1b20200, N_INV, N_INV), \
11990 X(vtrn, 0x1b20080, N_INV, N_INV), \
11991 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11992 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11993 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11994 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11995 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11996 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11997 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11998 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11999 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12000 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12001 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12005 #define X(OPC,I,F,S) N_MNEM_##OPC
12010 static const struct neon_tab_entry neon_enc_tab
[] =
12012 #define X(OPC,I,F,S) { (I), (F), (S) }
12017 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12018 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12019 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12020 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12021 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12022 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12023 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12024 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12025 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12026 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12027 #define NEON_ENC_SINGLE_(X) \
12028 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12029 #define NEON_ENC_DOUBLE_(X) \
12030 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12032 #define NEON_ENCODE(type, inst) \
12035 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12036 inst.is_neon = 1; \
12040 #define check_neon_suffixes \
12043 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12045 as_bad (_("invalid neon suffix for non neon instruction")); \
12051 /* Define shapes for instruction operands. The following mnemonic characters
12052 are used in this table:
12054 F - VFP S<n> register
12055 D - Neon D<n> register
12056 Q - Neon Q<n> register
12060 L - D<n> register list
12062 This table is used to generate various data:
12063 - enumerations of the form NS_DDR to be used as arguments to
12065 - a table classifying shapes into single, double, quad, mixed.
12066 - a table used to drive neon_select_shape. */
12068 #define NEON_SHAPE_DEF \
12069 X(3, (D, D, D), DOUBLE), \
12070 X(3, (Q, Q, Q), QUAD), \
12071 X(3, (D, D, I), DOUBLE), \
12072 X(3, (Q, Q, I), QUAD), \
12073 X(3, (D, D, S), DOUBLE), \
12074 X(3, (Q, Q, S), QUAD), \
12075 X(2, (D, D), DOUBLE), \
12076 X(2, (Q, Q), QUAD), \
12077 X(2, (D, S), DOUBLE), \
12078 X(2, (Q, S), QUAD), \
12079 X(2, (D, R), DOUBLE), \
12080 X(2, (Q, R), QUAD), \
12081 X(2, (D, I), DOUBLE), \
12082 X(2, (Q, I), QUAD), \
12083 X(3, (D, L, D), DOUBLE), \
12084 X(2, (D, Q), MIXED), \
12085 X(2, (Q, D), MIXED), \
12086 X(3, (D, Q, I), MIXED), \
12087 X(3, (Q, D, I), MIXED), \
12088 X(3, (Q, D, D), MIXED), \
12089 X(3, (D, Q, Q), MIXED), \
12090 X(3, (Q, Q, D), MIXED), \
12091 X(3, (Q, D, S), MIXED), \
12092 X(3, (D, Q, S), MIXED), \
12093 X(4, (D, D, D, I), DOUBLE), \
12094 X(4, (Q, Q, Q, I), QUAD), \
12095 X(2, (F, F), SINGLE), \
12096 X(3, (F, F, F), SINGLE), \
12097 X(2, (F, I), SINGLE), \
12098 X(2, (F, D), MIXED), \
12099 X(2, (D, F), MIXED), \
12100 X(3, (F, F, I), MIXED), \
12101 X(4, (R, R, F, F), SINGLE), \
12102 X(4, (F, F, R, R), SINGLE), \
12103 X(3, (D, R, R), DOUBLE), \
12104 X(3, (R, R, D), DOUBLE), \
12105 X(2, (S, R), SINGLE), \
12106 X(2, (R, S), SINGLE), \
12107 X(2, (F, R), SINGLE), \
12108 X(2, (R, F), SINGLE)
12110 #define S2(A,B) NS_##A##B
12111 #define S3(A,B,C) NS_##A##B##C
12112 #define S4(A,B,C,D) NS_##A##B##C##D
12114 #define X(N, L, C) S##N L
12127 enum neon_shape_class
12135 #define X(N, L, C) SC_##C
12137 static enum neon_shape_class neon_shape_class
[] =
12155 /* Register widths of above. */
12156 static unsigned neon_shape_el_size
[] =
12167 struct neon_shape_info
12170 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
12173 #define S2(A,B) { SE_##A, SE_##B }
12174 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12175 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12177 #define X(N, L, C) { N, S##N L }
12179 static struct neon_shape_info neon_shape_tab
[] =
12189 /* Bit masks used in type checking given instructions.
12190 'N_EQK' means the type must be the same as (or based on in some way) the key
12191 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12192 set, various other bits can be set as well in order to modify the meaning of
12193 the type constraint. */
12195 enum neon_type_mask
12218 N_KEY
= 0x1000000, /* Key element (main type specifier). */
12219 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
12220 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
12221 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
12222 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
12223 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12224 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12225 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12226 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
12227 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12229 N_MAX_NONSPECIAL
= N_F64
12232 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12234 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12235 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12236 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12237 #define N_SUF_32 (N_SU_32 | N_F32)
12238 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12239 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12241 /* Pass this as the first type argument to neon_check_type to ignore types
12243 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12245 /* Select a "shape" for the current instruction (describing register types or
12246 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12247 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12248 function of operand parsing, so this function doesn't need to be called.
12249 Shapes should be listed in order of decreasing length. */
12251 static enum neon_shape
12252 neon_select_shape (enum neon_shape shape
, ...)
12255 enum neon_shape first_shape
= shape
;
12257 /* Fix missing optional operands. FIXME: we don't know at this point how
12258 many arguments we should have, so this makes the assumption that we have
12259 > 1. This is true of all current Neon opcodes, I think, but may not be
12260 true in the future. */
12261 if (!inst
.operands
[1].present
)
12262 inst
.operands
[1] = inst
.operands
[0];
12264 va_start (ap
, shape
);
12266 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12271 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12273 if (!inst
.operands
[j
].present
)
12279 switch (neon_shape_tab
[shape
].el
[j
])
12282 if (!(inst
.operands
[j
].isreg
12283 && inst
.operands
[j
].isvec
12284 && inst
.operands
[j
].issingle
12285 && !inst
.operands
[j
].isquad
))
12290 if (!(inst
.operands
[j
].isreg
12291 && inst
.operands
[j
].isvec
12292 && !inst
.operands
[j
].isquad
12293 && !inst
.operands
[j
].issingle
))
12298 if (!(inst
.operands
[j
].isreg
12299 && !inst
.operands
[j
].isvec
))
12304 if (!(inst
.operands
[j
].isreg
12305 && inst
.operands
[j
].isvec
12306 && inst
.operands
[j
].isquad
12307 && !inst
.operands
[j
].issingle
))
12312 if (!(!inst
.operands
[j
].isreg
12313 && !inst
.operands
[j
].isscalar
))
12318 if (!(!inst
.operands
[j
].isreg
12319 && inst
.operands
[j
].isscalar
))
12335 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12336 first_error (_("invalid instruction shape"));
12341 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12342 means the Q bit should be set). */
12345 neon_quad (enum neon_shape shape
)
12347 return neon_shape_class
[shape
] == SC_QUAD
;
12351 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12354 /* Allow modification to be made to types which are constrained to be
12355 based on the key element, based on bits set alongside N_EQK. */
12356 if ((typebits
& N_EQK
) != 0)
12358 if ((typebits
& N_HLF
) != 0)
12360 else if ((typebits
& N_DBL
) != 0)
12362 if ((typebits
& N_SGN
) != 0)
12363 *g_type
= NT_signed
;
12364 else if ((typebits
& N_UNS
) != 0)
12365 *g_type
= NT_unsigned
;
12366 else if ((typebits
& N_INT
) != 0)
12367 *g_type
= NT_integer
;
12368 else if ((typebits
& N_FLT
) != 0)
12369 *g_type
= NT_float
;
12370 else if ((typebits
& N_SIZ
) != 0)
12371 *g_type
= NT_untyped
;
12375 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12376 operand type, i.e. the single type specified in a Neon instruction when it
12377 is the only one given. */
12379 static struct neon_type_el
12380 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12382 struct neon_type_el dest
= *key
;
12384 gas_assert ((thisarg
& N_EQK
) != 0);
12386 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12391 /* Convert Neon type and size into compact bitmask representation. */
12393 static enum neon_type_mask
12394 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12401 case 8: return N_8
;
12402 case 16: return N_16
;
12403 case 32: return N_32
;
12404 case 64: return N_64
;
12412 case 8: return N_I8
;
12413 case 16: return N_I16
;
12414 case 32: return N_I32
;
12415 case 64: return N_I64
;
12423 case 16: return N_F16
;
12424 case 32: return N_F32
;
12425 case 64: return N_F64
;
12433 case 8: return N_P8
;
12434 case 16: return N_P16
;
12442 case 8: return N_S8
;
12443 case 16: return N_S16
;
12444 case 32: return N_S32
;
12445 case 64: return N_S64
;
12453 case 8: return N_U8
;
12454 case 16: return N_U16
;
12455 case 32: return N_U32
;
12456 case 64: return N_U64
;
12467 /* Convert compact Neon bitmask type representation to a type and size. Only
12468 handles the case where a single bit is set in the mask. */
12471 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12472 enum neon_type_mask mask
)
12474 if ((mask
& N_EQK
) != 0)
12477 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12479 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12481 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12483 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12488 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12490 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12491 *type
= NT_unsigned
;
12492 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12493 *type
= NT_integer
;
12494 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12495 *type
= NT_untyped
;
12496 else if ((mask
& (N_P8
| N_P16
)) != 0)
12498 else if ((mask
& (N_F32
| N_F64
)) != 0)
12506 /* Modify a bitmask of allowed types. This is only needed for type
12510 modify_types_allowed (unsigned allowed
, unsigned mods
)
12513 enum neon_el_type type
;
12519 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12521 if (el_type_of_type_chk (&type
, &size
,
12522 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12524 neon_modify_type_size (mods
, &type
, &size
);
12525 destmask
|= type_chk_of_el_type (type
, size
);
12532 /* Check type and return type classification.
12533 The manual states (paraphrase): If one datatype is given, it indicates the
12535 - the second operand, if there is one
12536 - the operand, if there is no second operand
12537 - the result, if there are no operands.
12538 This isn't quite good enough though, so we use a concept of a "key" datatype
12539 which is set on a per-instruction basis, which is the one which matters when
12540 only one data type is written.
12541 Note: this function has side-effects (e.g. filling in missing operands). All
12542 Neon instructions should call it before performing bit encoding. */
12544 static struct neon_type_el
12545 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12548 unsigned i
, pass
, key_el
= 0;
12549 unsigned types
[NEON_MAX_TYPE_ELS
];
12550 enum neon_el_type k_type
= NT_invtype
;
12551 unsigned k_size
= -1u;
12552 struct neon_type_el badtype
= {NT_invtype
, -1};
12553 unsigned key_allowed
= 0;
12555 /* Optional registers in Neon instructions are always (not) in operand 1.
12556 Fill in the missing operand here, if it was omitted. */
12557 if (els
> 1 && !inst
.operands
[1].present
)
12558 inst
.operands
[1] = inst
.operands
[0];
12560 /* Suck up all the varargs. */
12562 for (i
= 0; i
< els
; i
++)
12564 unsigned thisarg
= va_arg (ap
, unsigned);
12565 if (thisarg
== N_IGNORE_TYPE
)
12570 types
[i
] = thisarg
;
12571 if ((thisarg
& N_KEY
) != 0)
12576 if (inst
.vectype
.elems
> 0)
12577 for (i
= 0; i
< els
; i
++)
12578 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12580 first_error (_("types specified in both the mnemonic and operands"));
12584 /* Duplicate inst.vectype elements here as necessary.
12585 FIXME: No idea if this is exactly the same as the ARM assembler,
12586 particularly when an insn takes one register and one non-register
12588 if (inst
.vectype
.elems
== 1 && els
> 1)
12591 inst
.vectype
.elems
= els
;
12592 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12593 for (j
= 0; j
< els
; j
++)
12595 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12598 else if (inst
.vectype
.elems
== 0 && els
> 0)
12601 /* No types were given after the mnemonic, so look for types specified
12602 after each operand. We allow some flexibility here; as long as the
12603 "key" operand has a type, we can infer the others. */
12604 for (j
= 0; j
< els
; j
++)
12605 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12606 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12608 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12610 for (j
= 0; j
< els
; j
++)
12611 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12612 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12617 first_error (_("operand types can't be inferred"));
12621 else if (inst
.vectype
.elems
!= els
)
12623 first_error (_("type specifier has the wrong number of parts"));
12627 for (pass
= 0; pass
< 2; pass
++)
12629 for (i
= 0; i
< els
; i
++)
12631 unsigned thisarg
= types
[i
];
12632 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12633 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12634 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12635 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12637 /* Decay more-specific signed & unsigned types to sign-insensitive
12638 integer types if sign-specific variants are unavailable. */
12639 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12640 && (types_allowed
& N_SU_ALL
) == 0)
12641 g_type
= NT_integer
;
12643 /* If only untyped args are allowed, decay any more specific types to
12644 them. Some instructions only care about signs for some element
12645 sizes, so handle that properly. */
12646 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12647 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12648 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12649 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12650 g_type
= NT_untyped
;
12654 if ((thisarg
& N_KEY
) != 0)
12658 key_allowed
= thisarg
& ~N_KEY
;
12663 if ((thisarg
& N_VFP
) != 0)
12665 enum neon_shape_el regshape
;
12666 unsigned regwidth
, match
;
12668 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12671 first_error (_("invalid instruction shape"));
12674 regshape
= neon_shape_tab
[ns
].el
[i
];
12675 regwidth
= neon_shape_el_size
[regshape
];
12677 /* In VFP mode, operands must match register widths. If we
12678 have a key operand, use its width, else use the width of
12679 the current operand. */
12685 if (regwidth
!= match
)
12687 first_error (_("operand size must match register width"));
12692 if ((thisarg
& N_EQK
) == 0)
12694 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12696 if ((given_type
& types_allowed
) == 0)
12698 first_error (_("bad type in Neon instruction"));
12704 enum neon_el_type mod_k_type
= k_type
;
12705 unsigned mod_k_size
= k_size
;
12706 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12707 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12709 first_error (_("inconsistent types in Neon instruction"));
12717 return inst
.vectype
.el
[key_el
];
12720 /* Neon-style VFP instruction forwarding. */
12722 /* Thumb VFP instructions have 0xE in the condition field. */
12725 do_vfp_cond_or_thumb (void)
12730 inst
.instruction
|= 0xe0000000;
12732 inst
.instruction
|= inst
.cond
<< 28;
12735 /* Look up and encode a simple mnemonic, for use as a helper function for the
12736 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12737 etc. It is assumed that operand parsing has already been done, and that the
12738 operands are in the form expected by the given opcode (this isn't necessarily
12739 the same as the form in which they were parsed, hence some massaging must
12740 take place before this function is called).
12741 Checks current arch version against that in the looked-up opcode. */
12744 do_vfp_nsyn_opcode (const char *opname
)
12746 const struct asm_opcode
*opcode
;
12748 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12753 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12754 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12761 inst
.instruction
= opcode
->tvalue
;
12762 opcode
->tencode ();
12766 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12767 opcode
->aencode ();
12772 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12774 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12779 do_vfp_nsyn_opcode ("fadds");
12781 do_vfp_nsyn_opcode ("fsubs");
12786 do_vfp_nsyn_opcode ("faddd");
12788 do_vfp_nsyn_opcode ("fsubd");
12792 /* Check operand types to see if this is a VFP instruction, and if so call
12796 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12798 enum neon_shape rs
;
12799 struct neon_type_el et
;
12804 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12805 et
= neon_check_type (2, rs
,
12806 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12810 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12811 et
= neon_check_type (3, rs
,
12812 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12819 if (et
.type
!= NT_invtype
)
12830 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12832 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12837 do_vfp_nsyn_opcode ("fmacs");
12839 do_vfp_nsyn_opcode ("fnmacs");
12844 do_vfp_nsyn_opcode ("fmacd");
12846 do_vfp_nsyn_opcode ("fnmacd");
12851 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12853 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12858 do_vfp_nsyn_opcode ("ffmas");
12860 do_vfp_nsyn_opcode ("ffnmas");
12865 do_vfp_nsyn_opcode ("ffmad");
12867 do_vfp_nsyn_opcode ("ffnmad");
12872 do_vfp_nsyn_mul (enum neon_shape rs
)
12875 do_vfp_nsyn_opcode ("fmuls");
12877 do_vfp_nsyn_opcode ("fmuld");
12881 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12883 int is_neg
= (inst
.instruction
& 0x80) != 0;
12884 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12889 do_vfp_nsyn_opcode ("fnegs");
12891 do_vfp_nsyn_opcode ("fabss");
12896 do_vfp_nsyn_opcode ("fnegd");
12898 do_vfp_nsyn_opcode ("fabsd");
12902 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12903 insns belong to Neon, and are handled elsewhere. */
12906 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12908 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12912 do_vfp_nsyn_opcode ("fldmdbs");
12914 do_vfp_nsyn_opcode ("fldmias");
12919 do_vfp_nsyn_opcode ("fstmdbs");
12921 do_vfp_nsyn_opcode ("fstmias");
12926 do_vfp_nsyn_sqrt (void)
12928 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12929 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12932 do_vfp_nsyn_opcode ("fsqrts");
12934 do_vfp_nsyn_opcode ("fsqrtd");
12938 do_vfp_nsyn_div (void)
12940 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12941 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12942 N_F32
| N_F64
| N_KEY
| N_VFP
);
12945 do_vfp_nsyn_opcode ("fdivs");
12947 do_vfp_nsyn_opcode ("fdivd");
12951 do_vfp_nsyn_nmul (void)
12953 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12954 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12955 N_F32
| N_F64
| N_KEY
| N_VFP
);
12959 NEON_ENCODE (SINGLE
, inst
);
12960 do_vfp_sp_dyadic ();
12964 NEON_ENCODE (DOUBLE
, inst
);
12965 do_vfp_dp_rd_rn_rm ();
12967 do_vfp_cond_or_thumb ();
12971 do_vfp_nsyn_cmp (void)
12973 if (inst
.operands
[1].isreg
)
12975 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12976 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12980 NEON_ENCODE (SINGLE
, inst
);
12981 do_vfp_sp_monadic ();
12985 NEON_ENCODE (DOUBLE
, inst
);
12986 do_vfp_dp_rd_rm ();
12991 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12992 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12994 switch (inst
.instruction
& 0x0fffffff)
12997 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
13000 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
13008 NEON_ENCODE (SINGLE
, inst
);
13009 do_vfp_sp_compare_z ();
13013 NEON_ENCODE (DOUBLE
, inst
);
13017 do_vfp_cond_or_thumb ();
13021 nsyn_insert_sp (void)
13023 inst
.operands
[1] = inst
.operands
[0];
13024 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
13025 inst
.operands
[0].reg
= REG_SP
;
13026 inst
.operands
[0].isreg
= 1;
13027 inst
.operands
[0].writeback
= 1;
13028 inst
.operands
[0].present
= 1;
13032 do_vfp_nsyn_push (void)
13035 if (inst
.operands
[1].issingle
)
13036 do_vfp_nsyn_opcode ("fstmdbs");
13038 do_vfp_nsyn_opcode ("fstmdbd");
13042 do_vfp_nsyn_pop (void)
13045 if (inst
.operands
[1].issingle
)
13046 do_vfp_nsyn_opcode ("fldmias");
13048 do_vfp_nsyn_opcode ("fldmiad");
13051 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13052 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13055 neon_dp_fixup (struct arm_it
* insn
)
13057 unsigned int i
= insn
->instruction
;
13062 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13073 insn
->instruction
= i
;
13076 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13080 neon_logbits (unsigned x
)
13082 return ffs (x
) - 4;
13085 #define LOW4(R) ((R) & 0xf)
13086 #define HI1(R) (((R) >> 4) & 1)
13088 /* Encode insns with bit pattern:
13090 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13091 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13093 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13094 different meaning for some instruction. */
13097 neon_three_same (int isquad
, int ubit
, int size
)
13099 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13100 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13101 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13102 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13103 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13104 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13105 inst
.instruction
|= (isquad
!= 0) << 6;
13106 inst
.instruction
|= (ubit
!= 0) << 24;
13108 inst
.instruction
|= neon_logbits (size
) << 20;
13110 neon_dp_fixup (&inst
);
13113 /* Encode instructions of the form:
13115 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13116 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13118 Don't write size if SIZE == -1. */
13121 neon_two_same (int qbit
, int ubit
, int size
)
13123 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13124 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13125 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13126 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13127 inst
.instruction
|= (qbit
!= 0) << 6;
13128 inst
.instruction
|= (ubit
!= 0) << 24;
13131 inst
.instruction
|= neon_logbits (size
) << 18;
13133 neon_dp_fixup (&inst
);
13136 /* Neon instruction encoders, in approximate order of appearance. */
13139 do_neon_dyadic_i_su (void)
13141 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13142 struct neon_type_el et
= neon_check_type (3, rs
,
13143 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
13144 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13148 do_neon_dyadic_i64_su (void)
13150 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13151 struct neon_type_el et
= neon_check_type (3, rs
,
13152 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13153 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13157 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
13160 unsigned size
= et
.size
>> 3;
13161 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13162 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13163 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13164 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13165 inst
.instruction
|= (isquad
!= 0) << 6;
13166 inst
.instruction
|= immbits
<< 16;
13167 inst
.instruction
|= (size
>> 3) << 7;
13168 inst
.instruction
|= (size
& 0x7) << 19;
13170 inst
.instruction
|= (uval
!= 0) << 24;
13172 neon_dp_fixup (&inst
);
13176 do_neon_shl_imm (void)
13178 if (!inst
.operands
[2].isreg
)
13180 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13181 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
13182 NEON_ENCODE (IMMED
, inst
);
13183 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
13187 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13188 struct neon_type_el et
= neon_check_type (3, rs
,
13189 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13192 /* VSHL/VQSHL 3-register variants have syntax such as:
13194 whereas other 3-register operations encoded by neon_three_same have
13197 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13199 tmp
= inst
.operands
[2].reg
;
13200 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13201 inst
.operands
[1].reg
= tmp
;
13202 NEON_ENCODE (INTEGER
, inst
);
13203 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13208 do_neon_qshl_imm (void)
13210 if (!inst
.operands
[2].isreg
)
13212 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13213 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13215 NEON_ENCODE (IMMED
, inst
);
13216 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13217 inst
.operands
[2].imm
);
13221 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13222 struct neon_type_el et
= neon_check_type (3, rs
,
13223 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13226 /* See note in do_neon_shl_imm. */
13227 tmp
= inst
.operands
[2].reg
;
13228 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13229 inst
.operands
[1].reg
= tmp
;
13230 NEON_ENCODE (INTEGER
, inst
);
13231 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13236 do_neon_rshl (void)
13238 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13239 struct neon_type_el et
= neon_check_type (3, rs
,
13240 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13243 tmp
= inst
.operands
[2].reg
;
13244 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13245 inst
.operands
[1].reg
= tmp
;
13246 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13250 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
13252 /* Handle .I8 pseudo-instructions. */
13255 /* Unfortunately, this will make everything apart from zero out-of-range.
13256 FIXME is this the intended semantics? There doesn't seem much point in
13257 accepting .I8 if so. */
13258 immediate
|= immediate
<< 8;
13264 if (immediate
== (immediate
& 0x000000ff))
13266 *immbits
= immediate
;
13269 else if (immediate
== (immediate
& 0x0000ff00))
13271 *immbits
= immediate
>> 8;
13274 else if (immediate
== (immediate
& 0x00ff0000))
13276 *immbits
= immediate
>> 16;
13279 else if (immediate
== (immediate
& 0xff000000))
13281 *immbits
= immediate
>> 24;
13284 if ((immediate
& 0xffff) != (immediate
>> 16))
13285 goto bad_immediate
;
13286 immediate
&= 0xffff;
13289 if (immediate
== (immediate
& 0x000000ff))
13291 *immbits
= immediate
;
13294 else if (immediate
== (immediate
& 0x0000ff00))
13296 *immbits
= immediate
>> 8;
13301 first_error (_("immediate value out of range"));
13305 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13309 neon_bits_same_in_bytes (unsigned imm
)
13311 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13312 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13313 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13314 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13317 /* For immediate of above form, return 0bABCD. */
13320 neon_squash_bits (unsigned imm
)
13322 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13323 | ((imm
& 0x01000000) >> 21);
13326 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13329 neon_qfloat_bits (unsigned imm
)
13331 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13334 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13335 the instruction. *OP is passed as the initial value of the op field, and
13336 may be set to a different value depending on the constant (i.e.
13337 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13338 MVN). If the immediate looks like a repeated pattern then also
13339 try smaller element sizes. */
13342 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13343 unsigned *immbits
, int *op
, int size
,
13344 enum neon_el_type type
)
13346 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13348 if (type
== NT_float
&& !float_p
)
13351 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13353 if (size
!= 32 || *op
== 1)
13355 *immbits
= neon_qfloat_bits (immlo
);
13361 if (neon_bits_same_in_bytes (immhi
)
13362 && neon_bits_same_in_bytes (immlo
))
13366 *immbits
= (neon_squash_bits (immhi
) << 4)
13367 | neon_squash_bits (immlo
);
13372 if (immhi
!= immlo
)
13378 if (immlo
== (immlo
& 0x000000ff))
13383 else if (immlo
== (immlo
& 0x0000ff00))
13385 *immbits
= immlo
>> 8;
13388 else if (immlo
== (immlo
& 0x00ff0000))
13390 *immbits
= immlo
>> 16;
13393 else if (immlo
== (immlo
& 0xff000000))
13395 *immbits
= immlo
>> 24;
13398 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13400 *immbits
= (immlo
>> 8) & 0xff;
13403 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13405 *immbits
= (immlo
>> 16) & 0xff;
13409 if ((immlo
& 0xffff) != (immlo
>> 16))
13416 if (immlo
== (immlo
& 0x000000ff))
13421 else if (immlo
== (immlo
& 0x0000ff00))
13423 *immbits
= immlo
>> 8;
13427 if ((immlo
& 0xff) != (immlo
>> 8))
13432 if (immlo
== (immlo
& 0x000000ff))
13434 /* Don't allow MVN with 8-bit immediate. */
13444 /* Write immediate bits [7:0] to the following locations:
13446 |28/24|23 19|18 16|15 4|3 0|
13447 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13449 This function is used by VMOV/VMVN/VORR/VBIC. */
13452 neon_write_immbits (unsigned immbits
)
13454 inst
.instruction
|= immbits
& 0xf;
13455 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13456 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13459 /* Invert low-order SIZE bits of XHI:XLO. */
13462 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13464 unsigned immlo
= xlo
? *xlo
: 0;
13465 unsigned immhi
= xhi
? *xhi
: 0;
13470 immlo
= (~immlo
) & 0xff;
13474 immlo
= (~immlo
) & 0xffff;
13478 immhi
= (~immhi
) & 0xffffffff;
13479 /* fall through. */
13482 immlo
= (~immlo
) & 0xffffffff;
13497 do_neon_logic (void)
13499 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13501 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13502 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13503 /* U bit and size field were set as part of the bitmask. */
13504 NEON_ENCODE (INTEGER
, inst
);
13505 neon_three_same (neon_quad (rs
), 0, -1);
13509 const int three_ops_form
= (inst
.operands
[2].present
13510 && !inst
.operands
[2].isreg
);
13511 const int immoperand
= (three_ops_form
? 2 : 1);
13512 enum neon_shape rs
= (three_ops_form
13513 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13514 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13515 struct neon_type_el et
= neon_check_type (2, rs
,
13516 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13517 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13521 if (et
.type
== NT_invtype
)
13524 if (three_ops_form
)
13525 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13526 _("first and second operands shall be the same register"));
13528 NEON_ENCODE (IMMED
, inst
);
13530 immbits
= inst
.operands
[immoperand
].imm
;
13533 /* .i64 is a pseudo-op, so the immediate must be a repeating
13535 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13536 inst
.operands
[immoperand
].reg
: 0))
13538 /* Set immbits to an invalid constant. */
13539 immbits
= 0xdeadbeef;
13546 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13550 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13554 /* Pseudo-instruction for VBIC. */
13555 neon_invert_size (&immbits
, 0, et
.size
);
13556 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13560 /* Pseudo-instruction for VORR. */
13561 neon_invert_size (&immbits
, 0, et
.size
);
13562 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13572 inst
.instruction
|= neon_quad (rs
) << 6;
13573 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13574 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13575 inst
.instruction
|= cmode
<< 8;
13576 neon_write_immbits (immbits
);
13578 neon_dp_fixup (&inst
);
13583 do_neon_bitfield (void)
13585 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13586 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13587 neon_three_same (neon_quad (rs
), 0, -1);
13591 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13594 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13595 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13597 if (et
.type
== NT_float
)
13599 NEON_ENCODE (FLOAT
, inst
);
13600 neon_three_same (neon_quad (rs
), 0, -1);
13604 NEON_ENCODE (INTEGER
, inst
);
13605 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13610 do_neon_dyadic_if_su (void)
13612 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13616 do_neon_dyadic_if_su_d (void)
13618 /* This version only allow D registers, but that constraint is enforced during
13619 operand parsing so we don't need to do anything extra here. */
13620 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13624 do_neon_dyadic_if_i_d (void)
13626 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13627 affected if we specify unsigned args. */
13628 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13631 enum vfp_or_neon_is_neon_bits
13634 NEON_CHECK_ARCH
= 2
13637 /* Call this function if an instruction which may have belonged to the VFP or
13638 Neon instruction sets, but turned out to be a Neon instruction (due to the
13639 operand types involved, etc.). We have to check and/or fix-up a couple of
13642 - Make sure the user hasn't attempted to make a Neon instruction
13644 - Alter the value in the condition code field if necessary.
13645 - Make sure that the arch supports Neon instructions.
13647 Which of these operations take place depends on bits from enum
13648 vfp_or_neon_is_neon_bits.
13650 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13651 current instruction's condition is COND_ALWAYS, the condition field is
13652 changed to inst.uncond_value. This is necessary because instructions shared
13653 between VFP and Neon may be conditional for the VFP variants only, and the
13654 unconditional Neon version must have, e.g., 0xF in the condition field. */
13657 vfp_or_neon_is_neon (unsigned check
)
13659 /* Conditions are always legal in Thumb mode (IT blocks). */
13660 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13662 if (inst
.cond
!= COND_ALWAYS
)
13664 first_error (_(BAD_COND
));
13667 if (inst
.uncond_value
!= -1)
13668 inst
.instruction
|= inst
.uncond_value
<< 28;
13671 if ((check
& NEON_CHECK_ARCH
)
13672 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13674 first_error (_(BAD_FPU
));
13682 do_neon_addsub_if_i (void)
13684 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13687 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13690 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13691 affected if we specify unsigned args. */
13692 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13695 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13697 V<op> A,B (A is operand 0, B is operand 2)
13702 so handle that case specially. */
13705 neon_exchange_operands (void)
13707 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13708 if (inst
.operands
[1].present
)
13710 /* Swap operands[1] and operands[2]. */
13711 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13712 inst
.operands
[1] = inst
.operands
[2];
13713 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13717 inst
.operands
[1] = inst
.operands
[2];
13718 inst
.operands
[2] = inst
.operands
[0];
13723 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13725 if (inst
.operands
[2].isreg
)
13728 neon_exchange_operands ();
13729 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13733 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13734 struct neon_type_el et
= neon_check_type (2, rs
,
13735 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13737 NEON_ENCODE (IMMED
, inst
);
13738 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13739 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13740 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13741 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13742 inst
.instruction
|= neon_quad (rs
) << 6;
13743 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13744 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13746 neon_dp_fixup (&inst
);
13753 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13757 do_neon_cmp_inv (void)
13759 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13765 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13768 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13769 scalars, which are encoded in 5 bits, M : Rm.
13770 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13771 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13775 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13777 unsigned regno
= NEON_SCALAR_REG (scalar
);
13778 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13783 if (regno
> 7 || elno
> 3)
13785 return regno
| (elno
<< 3);
13788 if (regno
> 15 || elno
> 1)
13790 return regno
| (elno
<< 4);
13794 first_error (_("scalar out of range for multiply instruction"));
13800 /* Encode multiply / multiply-accumulate scalar instructions. */
13803 neon_mul_mac (struct neon_type_el et
, int ubit
)
13807 /* Give a more helpful error message if we have an invalid type. */
13808 if (et
.type
== NT_invtype
)
13811 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13812 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13813 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13814 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13815 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13816 inst
.instruction
|= LOW4 (scalar
);
13817 inst
.instruction
|= HI1 (scalar
) << 5;
13818 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13819 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13820 inst
.instruction
|= (ubit
!= 0) << 24;
13822 neon_dp_fixup (&inst
);
13826 do_neon_mac_maybe_scalar (void)
13828 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13831 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13834 if (inst
.operands
[2].isscalar
)
13836 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13837 struct neon_type_el et
= neon_check_type (3, rs
,
13838 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13839 NEON_ENCODE (SCALAR
, inst
);
13840 neon_mul_mac (et
, neon_quad (rs
));
13844 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13845 affected if we specify unsigned args. */
13846 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13851 do_neon_fmac (void)
13853 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13856 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13859 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13865 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13866 struct neon_type_el et
= neon_check_type (3, rs
,
13867 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13868 neon_three_same (neon_quad (rs
), 0, et
.size
);
13871 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13872 same types as the MAC equivalents. The polynomial type for this instruction
13873 is encoded the same as the integer type. */
13878 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13881 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13884 if (inst
.operands
[2].isscalar
)
13885 do_neon_mac_maybe_scalar ();
13887 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13891 do_neon_qdmulh (void)
13893 if (inst
.operands
[2].isscalar
)
13895 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13896 struct neon_type_el et
= neon_check_type (3, rs
,
13897 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13898 NEON_ENCODE (SCALAR
, inst
);
13899 neon_mul_mac (et
, neon_quad (rs
));
13903 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13904 struct neon_type_el et
= neon_check_type (3, rs
,
13905 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13906 NEON_ENCODE (INTEGER
, inst
);
13907 /* The U bit (rounding) comes from bit mask. */
13908 neon_three_same (neon_quad (rs
), 0, et
.size
);
13913 do_neon_fcmp_absolute (void)
13915 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13916 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13917 /* Size field comes from bit mask. */
13918 neon_three_same (neon_quad (rs
), 1, -1);
13922 do_neon_fcmp_absolute_inv (void)
13924 neon_exchange_operands ();
13925 do_neon_fcmp_absolute ();
13929 do_neon_step (void)
13931 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13932 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13933 neon_three_same (neon_quad (rs
), 0, -1);
13937 do_neon_abs_neg (void)
13939 enum neon_shape rs
;
13940 struct neon_type_el et
;
13942 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13945 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13948 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13949 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13951 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13952 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13953 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13954 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13955 inst
.instruction
|= neon_quad (rs
) << 6;
13956 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13957 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13959 neon_dp_fixup (&inst
);
13965 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13966 struct neon_type_el et
= neon_check_type (2, rs
,
13967 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13968 int imm
= inst
.operands
[2].imm
;
13969 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13970 _("immediate out of range for insert"));
13971 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13977 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13978 struct neon_type_el et
= neon_check_type (2, rs
,
13979 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13980 int imm
= inst
.operands
[2].imm
;
13981 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13982 _("immediate out of range for insert"));
13983 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13987 do_neon_qshlu_imm (void)
13989 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13990 struct neon_type_el et
= neon_check_type (2, rs
,
13991 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13992 int imm
= inst
.operands
[2].imm
;
13993 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13994 _("immediate out of range for shift"));
13995 /* Only encodes the 'U present' variant of the instruction.
13996 In this case, signed types have OP (bit 8) set to 0.
13997 Unsigned types have OP set to 1. */
13998 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13999 /* The rest of the bits are the same as other immediate shifts. */
14000 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14004 do_neon_qmovn (void)
14006 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14007 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14008 /* Saturating move where operands can be signed or unsigned, and the
14009 destination has the same signedness. */
14010 NEON_ENCODE (INTEGER
, inst
);
14011 if (et
.type
== NT_unsigned
)
14012 inst
.instruction
|= 0xc0;
14014 inst
.instruction
|= 0x80;
14015 neon_two_same (0, 1, et
.size
/ 2);
14019 do_neon_qmovun (void)
14021 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14022 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14023 /* Saturating move with unsigned results. Operands must be signed. */
14024 NEON_ENCODE (INTEGER
, inst
);
14025 neon_two_same (0, 1, et
.size
/ 2);
14029 do_neon_rshift_sat_narrow (void)
14031 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14032 or unsigned. If operands are unsigned, results must also be unsigned. */
14033 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14034 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14035 int imm
= inst
.operands
[2].imm
;
14036 /* This gets the bounds check, size encoding and immediate bits calculation
14040 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14041 VQMOVN.I<size> <Dd>, <Qm>. */
14044 inst
.operands
[2].present
= 0;
14045 inst
.instruction
= N_MNEM_vqmovn
;
14050 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14051 _("immediate out of range"));
14052 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14056 do_neon_rshift_sat_narrow_u (void)
14058 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14059 or unsigned. If operands are unsigned, results must also be unsigned. */
14060 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14061 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14062 int imm
= inst
.operands
[2].imm
;
14063 /* This gets the bounds check, size encoding and immediate bits calculation
14067 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14068 VQMOVUN.I<size> <Dd>, <Qm>. */
14071 inst
.operands
[2].present
= 0;
14072 inst
.instruction
= N_MNEM_vqmovun
;
14077 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14078 _("immediate out of range"));
14079 /* FIXME: The manual is kind of unclear about what value U should have in
14080 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14082 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14086 do_neon_movn (void)
14088 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14089 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14090 NEON_ENCODE (INTEGER
, inst
);
14091 neon_two_same (0, 1, et
.size
/ 2);
14095 do_neon_rshift_narrow (void)
14097 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14098 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14099 int imm
= inst
.operands
[2].imm
;
14100 /* This gets the bounds check, size encoding and immediate bits calculation
14104 /* If immediate is zero then we are a pseudo-instruction for
14105 VMOVN.I<size> <Dd>, <Qm> */
14108 inst
.operands
[2].present
= 0;
14109 inst
.instruction
= N_MNEM_vmovn
;
14114 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14115 _("immediate out of range for narrowing operation"));
14116 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14120 do_neon_shll (void)
14122 /* FIXME: Type checking when lengthening. */
14123 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14124 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14125 unsigned imm
= inst
.operands
[2].imm
;
14127 if (imm
== et
.size
)
14129 /* Maximum shift variant. */
14130 NEON_ENCODE (INTEGER
, inst
);
14131 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14132 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14133 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14134 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14135 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14137 neon_dp_fixup (&inst
);
14141 /* A more-specific type check for non-max versions. */
14142 et
= neon_check_type (2, NS_QDI
,
14143 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14144 NEON_ENCODE (IMMED
, inst
);
14145 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14149 /* Check the various types for the VCVT instruction, and return which version
14150 the current instruction is. */
14153 neon_cvt_flavour (enum neon_shape rs
)
14155 #define CVT_VAR(C,X,Y) \
14156 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14157 if (et.type != NT_invtype) \
14159 inst.error = NULL; \
14162 struct neon_type_el et
;
14163 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14164 || rs
== NS_FF
) ? N_VFP
: 0;
14165 /* The instruction versions which take an immediate take one register
14166 argument, which is extended to the width of the full register. Thus the
14167 "source" and "destination" registers must have the same width. Hack that
14168 here by making the size equal to the key (wider, in this case) operand. */
14169 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14171 CVT_VAR (0, N_S32
, N_F32
);
14172 CVT_VAR (1, N_U32
, N_F32
);
14173 CVT_VAR (2, N_F32
, N_S32
);
14174 CVT_VAR (3, N_F32
, N_U32
);
14175 /* Half-precision conversions. */
14176 CVT_VAR (4, N_F32
, N_F16
);
14177 CVT_VAR (5, N_F16
, N_F32
);
14181 /* VFP instructions. */
14182 CVT_VAR (6, N_F32
, N_F64
);
14183 CVT_VAR (7, N_F64
, N_F32
);
14184 CVT_VAR (8, N_S32
, N_F64
| key
);
14185 CVT_VAR (9, N_U32
, N_F64
| key
);
14186 CVT_VAR (10, N_F64
| key
, N_S32
);
14187 CVT_VAR (11, N_F64
| key
, N_U32
);
14188 /* VFP instructions with bitshift. */
14189 CVT_VAR (12, N_F32
| key
, N_S16
);
14190 CVT_VAR (13, N_F32
| key
, N_U16
);
14191 CVT_VAR (14, N_F64
| key
, N_S16
);
14192 CVT_VAR (15, N_F64
| key
, N_U16
);
14193 CVT_VAR (16, N_S16
, N_F32
| key
);
14194 CVT_VAR (17, N_U16
, N_F32
| key
);
14195 CVT_VAR (18, N_S16
, N_F64
| key
);
14196 CVT_VAR (19, N_U16
, N_F64
| key
);
14202 /* Neon-syntax VFP conversions. */
14205 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
14207 const char *opname
= 0;
14209 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14211 /* Conversions with immediate bitshift. */
14212 const char *enc
[] =
14236 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14238 opname
= enc
[flavour
];
14239 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14240 _("operands 0 and 1 must be the same register"));
14241 inst
.operands
[1] = inst
.operands
[2];
14242 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
14247 /* Conversions without bitshift. */
14248 const char *enc
[] =
14264 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14265 opname
= enc
[flavour
];
14269 do_vfp_nsyn_opcode (opname
);
14273 do_vfp_nsyn_cvtz (void)
14275 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14276 int flavour
= neon_cvt_flavour (rs
);
14277 const char *enc
[] =
14291 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14292 do_vfp_nsyn_opcode (enc
[flavour
]);
14296 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
14298 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14299 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14300 int flavour
= neon_cvt_flavour (rs
);
14302 /* PR11109: Handle round-to-zero for VCVT conversions. */
14304 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14305 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
14306 && (rs
== NS_FD
|| rs
== NS_FF
))
14308 do_vfp_nsyn_cvtz ();
14312 /* VFP rather than Neon conversions. */
14315 do_vfp_nsyn_cvt (rs
, flavour
);
14325 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14327 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14330 /* Fixed-point conversion with #0 immediate is encoded as an
14331 integer conversion. */
14332 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14334 immbits
= 32 - inst
.operands
[2].imm
;
14335 NEON_ENCODE (IMMED
, inst
);
14337 inst
.instruction
|= enctab
[flavour
];
14338 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14339 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14340 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14341 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14342 inst
.instruction
|= neon_quad (rs
) << 6;
14343 inst
.instruction
|= 1 << 21;
14344 inst
.instruction
|= immbits
<< 16;
14346 neon_dp_fixup (&inst
);
14354 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14356 NEON_ENCODE (INTEGER
, inst
);
14358 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14362 inst
.instruction
|= enctab
[flavour
];
14364 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14365 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14366 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14367 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14368 inst
.instruction
|= neon_quad (rs
) << 6;
14369 inst
.instruction
|= 2 << 18;
14371 neon_dp_fixup (&inst
);
14375 /* Half-precision conversions for Advanced SIMD -- neon. */
14380 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14382 as_bad (_("operand size must match register width"));
14387 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14389 as_bad (_("operand size must match register width"));
14394 inst
.instruction
= 0x3b60600;
14396 inst
.instruction
= 0x3b60700;
14398 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14399 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14400 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14401 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14402 neon_dp_fixup (&inst
);
14406 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14407 do_vfp_nsyn_cvt (rs
, flavour
);
14412 do_neon_cvtr (void)
14414 do_neon_cvt_1 (FALSE
);
14420 do_neon_cvt_1 (TRUE
);
14424 do_neon_cvtb (void)
14426 inst
.instruction
= 0xeb20a40;
14428 /* The sizes are attached to the mnemonic. */
14429 if (inst
.vectype
.el
[0].type
!= NT_invtype
14430 && inst
.vectype
.el
[0].size
== 16)
14431 inst
.instruction
|= 0x00010000;
14433 /* Programmer's syntax: the sizes are attached to the operands. */
14434 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14435 && inst
.operands
[0].vectype
.size
== 16)
14436 inst
.instruction
|= 0x00010000;
14438 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14439 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14440 do_vfp_cond_or_thumb ();
14445 do_neon_cvtt (void)
14448 inst
.instruction
|= 0x80;
14452 neon_move_immediate (void)
14454 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14455 struct neon_type_el et
= neon_check_type (2, rs
,
14456 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14457 unsigned immlo
, immhi
= 0, immbits
;
14458 int op
, cmode
, float_p
;
14460 constraint (et
.type
== NT_invtype
,
14461 _("operand size must be specified for immediate VMOV"));
14463 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14464 op
= (inst
.instruction
& (1 << 5)) != 0;
14466 immlo
= inst
.operands
[1].imm
;
14467 if (inst
.operands
[1].regisimm
)
14468 immhi
= inst
.operands
[1].reg
;
14470 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14471 _("immediate has bits set outside the operand size"));
14473 float_p
= inst
.operands
[1].immisfloat
;
14475 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14476 et
.size
, et
.type
)) == FAIL
)
14478 /* Invert relevant bits only. */
14479 neon_invert_size (&immlo
, &immhi
, et
.size
);
14480 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14481 with one or the other; those cases are caught by
14482 neon_cmode_for_move_imm. */
14484 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14485 &op
, et
.size
, et
.type
)) == FAIL
)
14487 first_error (_("immediate out of range"));
14492 inst
.instruction
&= ~(1 << 5);
14493 inst
.instruction
|= op
<< 5;
14495 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14496 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14497 inst
.instruction
|= neon_quad (rs
) << 6;
14498 inst
.instruction
|= cmode
<< 8;
14500 neon_write_immbits (immbits
);
14506 if (inst
.operands
[1].isreg
)
14508 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14510 NEON_ENCODE (INTEGER
, inst
);
14511 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14512 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14513 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14514 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14515 inst
.instruction
|= neon_quad (rs
) << 6;
14519 NEON_ENCODE (IMMED
, inst
);
14520 neon_move_immediate ();
14523 neon_dp_fixup (&inst
);
14526 /* Encode instructions of form:
14528 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14529 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14532 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14534 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14535 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14536 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14537 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14538 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14539 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14540 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14541 inst
.instruction
|= neon_logbits (size
) << 20;
14543 neon_dp_fixup (&inst
);
14547 do_neon_dyadic_long (void)
14549 /* FIXME: Type checking for lengthening op. */
14550 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14551 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14552 neon_mixed_length (et
, et
.size
);
14556 do_neon_abal (void)
14558 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14559 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14560 neon_mixed_length (et
, et
.size
);
14564 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14566 if (inst
.operands
[2].isscalar
)
14568 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14569 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14570 NEON_ENCODE (SCALAR
, inst
);
14571 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14575 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14576 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14577 NEON_ENCODE (INTEGER
, inst
);
14578 neon_mixed_length (et
, et
.size
);
14583 do_neon_mac_maybe_scalar_long (void)
14585 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14589 do_neon_dyadic_wide (void)
14591 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14592 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14593 neon_mixed_length (et
, et
.size
);
14597 do_neon_dyadic_narrow (void)
14599 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14600 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14601 /* Operand sign is unimportant, and the U bit is part of the opcode,
14602 so force the operand type to integer. */
14603 et
.type
= NT_integer
;
14604 neon_mixed_length (et
, et
.size
/ 2);
14608 do_neon_mul_sat_scalar_long (void)
14610 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14614 do_neon_vmull (void)
14616 if (inst
.operands
[2].isscalar
)
14617 do_neon_mac_maybe_scalar_long ();
14620 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14621 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14622 if (et
.type
== NT_poly
)
14623 NEON_ENCODE (POLY
, inst
);
14625 NEON_ENCODE (INTEGER
, inst
);
14626 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14627 zero. Should be OK as-is. */
14628 neon_mixed_length (et
, et
.size
);
14635 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14636 struct neon_type_el et
= neon_check_type (3, rs
,
14637 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14638 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14640 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14641 _("shift out of range"));
14642 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14643 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14644 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14645 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14646 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14647 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14648 inst
.instruction
|= neon_quad (rs
) << 6;
14649 inst
.instruction
|= imm
<< 8;
14651 neon_dp_fixup (&inst
);
14657 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14658 struct neon_type_el et
= neon_check_type (2, rs
,
14659 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14660 unsigned op
= (inst
.instruction
>> 7) & 3;
14661 /* N (width of reversed regions) is encoded as part of the bitmask. We
14662 extract it here to check the elements to be reversed are smaller.
14663 Otherwise we'd get a reserved instruction. */
14664 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14665 gas_assert (elsize
!= 0);
14666 constraint (et
.size
>= elsize
,
14667 _("elements must be smaller than reversal region"));
14668 neon_two_same (neon_quad (rs
), 1, et
.size
);
14674 if (inst
.operands
[1].isscalar
)
14676 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14677 struct neon_type_el et
= neon_check_type (2, rs
,
14678 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14679 unsigned sizebits
= et
.size
>> 3;
14680 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14681 int logsize
= neon_logbits (et
.size
);
14682 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14684 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14687 NEON_ENCODE (SCALAR
, inst
);
14688 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14689 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14690 inst
.instruction
|= LOW4 (dm
);
14691 inst
.instruction
|= HI1 (dm
) << 5;
14692 inst
.instruction
|= neon_quad (rs
) << 6;
14693 inst
.instruction
|= x
<< 17;
14694 inst
.instruction
|= sizebits
<< 16;
14696 neon_dp_fixup (&inst
);
14700 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14701 struct neon_type_el et
= neon_check_type (2, rs
,
14702 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14703 /* Duplicate ARM register to lanes of vector. */
14704 NEON_ENCODE (ARMREG
, inst
);
14707 case 8: inst
.instruction
|= 0x400000; break;
14708 case 16: inst
.instruction
|= 0x000020; break;
14709 case 32: inst
.instruction
|= 0x000000; break;
14712 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14713 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14714 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14715 inst
.instruction
|= neon_quad (rs
) << 21;
14716 /* The encoding for this instruction is identical for the ARM and Thumb
14717 variants, except for the condition field. */
14718 do_vfp_cond_or_thumb ();
14722 /* VMOV has particularly many variations. It can be one of:
14723 0. VMOV<c><q> <Qd>, <Qm>
14724 1. VMOV<c><q> <Dd>, <Dm>
14725 (Register operations, which are VORR with Rm = Rn.)
14726 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14727 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14729 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14730 (ARM register to scalar.)
14731 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14732 (Two ARM registers to vector.)
14733 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14734 (Scalar to ARM register.)
14735 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14736 (Vector to two ARM registers.)
14737 8. VMOV.F32 <Sd>, <Sm>
14738 9. VMOV.F64 <Dd>, <Dm>
14739 (VFP register moves.)
14740 10. VMOV.F32 <Sd>, #imm
14741 11. VMOV.F64 <Dd>, #imm
14742 (VFP float immediate load.)
14743 12. VMOV <Rd>, <Sm>
14744 (VFP single to ARM reg.)
14745 13. VMOV <Sd>, <Rm>
14746 (ARM reg to VFP single.)
14747 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14748 (Two ARM regs to two VFP singles.)
14749 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14750 (Two VFP singles to two ARM regs.)
14752 These cases can be disambiguated using neon_select_shape, except cases 1/9
14753 and 3/11 which depend on the operand type too.
14755 All the encoded bits are hardcoded by this function.
14757 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14758 Cases 5, 7 may be used with VFPv2 and above.
14760 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14761 can specify a type where it doesn't make sense to, and is ignored). */
14766 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14767 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14769 struct neon_type_el et
;
14770 const char *ldconst
= 0;
14774 case NS_DD
: /* case 1/9. */
14775 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14776 /* It is not an error here if no type is given. */
14778 if (et
.type
== NT_float
&& et
.size
== 64)
14780 do_vfp_nsyn_opcode ("fcpyd");
14783 /* fall through. */
14785 case NS_QQ
: /* case 0/1. */
14787 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14789 /* The architecture manual I have doesn't explicitly state which
14790 value the U bit should have for register->register moves, but
14791 the equivalent VORR instruction has U = 0, so do that. */
14792 inst
.instruction
= 0x0200110;
14793 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14794 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14795 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14796 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14797 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14798 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14799 inst
.instruction
|= neon_quad (rs
) << 6;
14801 neon_dp_fixup (&inst
);
14805 case NS_DI
: /* case 3/11. */
14806 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14808 if (et
.type
== NT_float
&& et
.size
== 64)
14810 /* case 11 (fconstd). */
14811 ldconst
= "fconstd";
14812 goto encode_fconstd
;
14814 /* fall through. */
14816 case NS_QI
: /* case 2/3. */
14817 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14819 inst
.instruction
= 0x0800010;
14820 neon_move_immediate ();
14821 neon_dp_fixup (&inst
);
14824 case NS_SR
: /* case 4. */
14826 unsigned bcdebits
= 0;
14828 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14829 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14831 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14832 logsize
= neon_logbits (et
.size
);
14834 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14836 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14837 && et
.size
!= 32, _(BAD_FPU
));
14838 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14839 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14843 case 8: bcdebits
= 0x8; break;
14844 case 16: bcdebits
= 0x1; break;
14845 case 32: bcdebits
= 0x0; break;
14849 bcdebits
|= x
<< logsize
;
14851 inst
.instruction
= 0xe000b10;
14852 do_vfp_cond_or_thumb ();
14853 inst
.instruction
|= LOW4 (dn
) << 16;
14854 inst
.instruction
|= HI1 (dn
) << 7;
14855 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14856 inst
.instruction
|= (bcdebits
& 3) << 5;
14857 inst
.instruction
|= (bcdebits
>> 2) << 21;
14861 case NS_DRR
: /* case 5 (fmdrr). */
14862 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14865 inst
.instruction
= 0xc400b10;
14866 do_vfp_cond_or_thumb ();
14867 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14868 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14869 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14870 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14873 case NS_RS
: /* case 6. */
14876 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14877 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14878 unsigned abcdebits
= 0;
14880 et
= neon_check_type (2, NS_NULL
,
14881 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14882 logsize
= neon_logbits (et
.size
);
14884 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14886 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14887 && et
.size
!= 32, _(BAD_FPU
));
14888 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14889 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14893 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14894 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14895 case 32: abcdebits
= 0x00; break;
14899 abcdebits
|= x
<< logsize
;
14900 inst
.instruction
= 0xe100b10;
14901 do_vfp_cond_or_thumb ();
14902 inst
.instruction
|= LOW4 (dn
) << 16;
14903 inst
.instruction
|= HI1 (dn
) << 7;
14904 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14905 inst
.instruction
|= (abcdebits
& 3) << 5;
14906 inst
.instruction
|= (abcdebits
>> 2) << 21;
14910 case NS_RRD
: /* case 7 (fmrrd). */
14911 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14914 inst
.instruction
= 0xc500b10;
14915 do_vfp_cond_or_thumb ();
14916 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14917 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14918 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14919 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14922 case NS_FF
: /* case 8 (fcpys). */
14923 do_vfp_nsyn_opcode ("fcpys");
14926 case NS_FI
: /* case 10 (fconsts). */
14927 ldconst
= "fconsts";
14929 if (is_quarter_float (inst
.operands
[1].imm
))
14931 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14932 do_vfp_nsyn_opcode (ldconst
);
14935 first_error (_("immediate out of range"));
14938 case NS_RF
: /* case 12 (fmrs). */
14939 do_vfp_nsyn_opcode ("fmrs");
14942 case NS_FR
: /* case 13 (fmsr). */
14943 do_vfp_nsyn_opcode ("fmsr");
14946 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14947 (one of which is a list), but we have parsed four. Do some fiddling to
14948 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14950 case NS_RRFF
: /* case 14 (fmrrs). */
14951 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14952 _("VFP registers must be adjacent"));
14953 inst
.operands
[2].imm
= 2;
14954 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14955 do_vfp_nsyn_opcode ("fmrrs");
14958 case NS_FFRR
: /* case 15 (fmsrr). */
14959 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14960 _("VFP registers must be adjacent"));
14961 inst
.operands
[1] = inst
.operands
[2];
14962 inst
.operands
[2] = inst
.operands
[3];
14963 inst
.operands
[0].imm
= 2;
14964 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14965 do_vfp_nsyn_opcode ("fmsrr");
14974 do_neon_rshift_round_imm (void)
14976 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14977 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14978 int imm
= inst
.operands
[2].imm
;
14980 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14983 inst
.operands
[2].present
= 0;
14988 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14989 _("immediate out of range for shift"));
14990 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14995 do_neon_movl (void)
14997 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14998 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14999 unsigned sizebits
= et
.size
>> 3;
15000 inst
.instruction
|= sizebits
<< 19;
15001 neon_two_same (0, et
.type
== NT_unsigned
, -1);
15007 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15008 struct neon_type_el et
= neon_check_type (2, rs
,
15009 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15010 NEON_ENCODE (INTEGER
, inst
);
15011 neon_two_same (neon_quad (rs
), 1, et
.size
);
15015 do_neon_zip_uzp (void)
15017 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15018 struct neon_type_el et
= neon_check_type (2, rs
,
15019 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15020 if (rs
== NS_DD
&& et
.size
== 32)
15022 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15023 inst
.instruction
= N_MNEM_vtrn
;
15027 neon_two_same (neon_quad (rs
), 1, et
.size
);
15031 do_neon_sat_abs_neg (void)
15033 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15034 struct neon_type_el et
= neon_check_type (2, rs
,
15035 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15036 neon_two_same (neon_quad (rs
), 1, et
.size
);
15040 do_neon_pair_long (void)
15042 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15043 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
15044 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15045 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
15046 neon_two_same (neon_quad (rs
), 1, et
.size
);
15050 do_neon_recip_est (void)
15052 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15053 struct neon_type_el et
= neon_check_type (2, rs
,
15054 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
15055 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15056 neon_two_same (neon_quad (rs
), 1, et
.size
);
15062 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15063 struct neon_type_el et
= neon_check_type (2, rs
,
15064 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15065 neon_two_same (neon_quad (rs
), 1, et
.size
);
15071 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15072 struct neon_type_el et
= neon_check_type (2, rs
,
15073 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
15074 neon_two_same (neon_quad (rs
), 1, et
.size
);
15080 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15081 struct neon_type_el et
= neon_check_type (2, rs
,
15082 N_EQK
| N_INT
, N_8
| N_KEY
);
15083 neon_two_same (neon_quad (rs
), 1, et
.size
);
15089 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15090 neon_two_same (neon_quad (rs
), 1, -1);
15094 do_neon_tbl_tbx (void)
15096 unsigned listlenbits
;
15097 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
15099 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
15101 first_error (_("bad list length for table lookup"));
15105 listlenbits
= inst
.operands
[1].imm
- 1;
15106 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15107 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15108 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15109 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15110 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15111 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15112 inst
.instruction
|= listlenbits
<< 8;
15114 neon_dp_fixup (&inst
);
15118 do_neon_ldm_stm (void)
15120 /* P, U and L bits are part of bitmask. */
15121 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
15122 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
15124 if (inst
.operands
[1].issingle
)
15126 do_vfp_nsyn_ldm_stm (is_dbmode
);
15130 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
15131 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15133 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15134 _("register list must contain at least 1 and at most 16 "
15137 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15138 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
15139 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15140 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
15142 inst
.instruction
|= offsetbits
;
15144 do_vfp_cond_or_thumb ();
15148 do_neon_ldr_str (void)
15150 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
15152 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15153 And is UNPREDICTABLE in thumb mode. */
15155 && inst
.operands
[1].reg
== REG_PC
15156 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
15158 if (!thumb_mode
&& warn_on_deprecated
)
15159 as_warn (_("Use of PC here is deprecated"));
15161 inst
.error
= _("Use of PC here is UNPREDICTABLE");
15164 if (inst
.operands
[0].issingle
)
15167 do_vfp_nsyn_opcode ("flds");
15169 do_vfp_nsyn_opcode ("fsts");
15174 do_vfp_nsyn_opcode ("fldd");
15176 do_vfp_nsyn_opcode ("fstd");
15180 /* "interleave" version also handles non-interleaving register VLD1/VST1
15184 do_neon_ld_st_interleave (void)
15186 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
15187 N_8
| N_16
| N_32
| N_64
);
15188 unsigned alignbits
= 0;
15190 /* The bits in this table go:
15191 0: register stride of one (0) or two (1)
15192 1,2: register list length, minus one (1, 2, 3, 4).
15193 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15194 We use -1 for invalid entries. */
15195 const int typetable
[] =
15197 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15198 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15199 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15200 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15204 if (et
.type
== NT_invtype
)
15207 if (inst
.operands
[1].immisalign
)
15208 switch (inst
.operands
[1].imm
>> 8)
15210 case 64: alignbits
= 1; break;
15212 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
15213 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15214 goto bad_alignment
;
15218 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15219 goto bad_alignment
;
15224 first_error (_("bad alignment"));
15228 inst
.instruction
|= alignbits
<< 4;
15229 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15231 /* Bits [4:6] of the immediate in a list specifier encode register stride
15232 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15233 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15234 up the right value for "type" in a table based on this value and the given
15235 list style, then stick it back. */
15236 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
15237 | (((inst
.instruction
>> 8) & 3) << 3);
15239 typebits
= typetable
[idx
];
15241 constraint (typebits
== -1, _("bad list type for instruction"));
15243 inst
.instruction
&= ~0xf00;
15244 inst
.instruction
|= typebits
<< 8;
15247 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15248 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15249 otherwise. The variable arguments are a list of pairs of legal (size, align)
15250 values, terminated with -1. */
15253 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
15256 int result
= FAIL
, thissize
, thisalign
;
15258 if (!inst
.operands
[1].immisalign
)
15264 va_start (ap
, do_align
);
15268 thissize
= va_arg (ap
, int);
15269 if (thissize
== -1)
15271 thisalign
= va_arg (ap
, int);
15273 if (size
== thissize
&& align
== thisalign
)
15276 while (result
!= SUCCESS
);
15280 if (result
== SUCCESS
)
15283 first_error (_("unsupported alignment for instruction"));
15289 do_neon_ld_st_lane (void)
15291 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15292 int align_good
, do_align
= 0;
15293 int logsize
= neon_logbits (et
.size
);
15294 int align
= inst
.operands
[1].imm
>> 8;
15295 int n
= (inst
.instruction
>> 8) & 3;
15296 int max_el
= 64 / et
.size
;
15298 if (et
.type
== NT_invtype
)
15301 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
15302 _("bad list length"));
15303 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
15304 _("scalar index out of range"));
15305 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
15307 _("stride of 2 unavailable when element size is 8"));
15311 case 0: /* VLD1 / VST1. */
15312 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
15314 if (align_good
== FAIL
)
15318 unsigned alignbits
= 0;
15321 case 16: alignbits
= 0x1; break;
15322 case 32: alignbits
= 0x3; break;
15325 inst
.instruction
|= alignbits
<< 4;
15329 case 1: /* VLD2 / VST2. */
15330 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
15332 if (align_good
== FAIL
)
15335 inst
.instruction
|= 1 << 4;
15338 case 2: /* VLD3 / VST3. */
15339 constraint (inst
.operands
[1].immisalign
,
15340 _("can't use alignment with this instruction"));
15343 case 3: /* VLD4 / VST4. */
15344 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15345 16, 64, 32, 64, 32, 128, -1);
15346 if (align_good
== FAIL
)
15350 unsigned alignbits
= 0;
15353 case 8: alignbits
= 0x1; break;
15354 case 16: alignbits
= 0x1; break;
15355 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
15358 inst
.instruction
|= alignbits
<< 4;
15365 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15366 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15367 inst
.instruction
|= 1 << (4 + logsize
);
15369 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15370 inst
.instruction
|= logsize
<< 10;
15373 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15376 do_neon_ld_dup (void)
15378 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15379 int align_good
, do_align
= 0;
15381 if (et
.type
== NT_invtype
)
15384 switch ((inst
.instruction
>> 8) & 3)
15386 case 0: /* VLD1. */
15387 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15388 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15389 &do_align
, 16, 16, 32, 32, -1);
15390 if (align_good
== FAIL
)
15392 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15395 case 2: inst
.instruction
|= 1 << 5; break;
15396 default: first_error (_("bad list length")); return;
15398 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15401 case 1: /* VLD2. */
15402 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15403 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15404 if (align_good
== FAIL
)
15406 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15407 _("bad list length"));
15408 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15409 inst
.instruction
|= 1 << 5;
15410 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15413 case 2: /* VLD3. */
15414 constraint (inst
.operands
[1].immisalign
,
15415 _("can't use alignment with this instruction"));
15416 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15417 _("bad list length"));
15418 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15419 inst
.instruction
|= 1 << 5;
15420 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15423 case 3: /* VLD4. */
15425 int align
= inst
.operands
[1].imm
>> 8;
15426 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15427 16, 64, 32, 64, 32, 128, -1);
15428 if (align_good
== FAIL
)
15430 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15431 _("bad list length"));
15432 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15433 inst
.instruction
|= 1 << 5;
15434 if (et
.size
== 32 && align
== 128)
15435 inst
.instruction
|= 0x3 << 6;
15437 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15444 inst
.instruction
|= do_align
<< 4;
15447 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15448 apart from bits [11:4]. */
15451 do_neon_ldx_stx (void)
15453 if (inst
.operands
[1].isreg
)
15454 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15456 switch (NEON_LANE (inst
.operands
[0].imm
))
15458 case NEON_INTERLEAVE_LANES
:
15459 NEON_ENCODE (INTERLV
, inst
);
15460 do_neon_ld_st_interleave ();
15463 case NEON_ALL_LANES
:
15464 NEON_ENCODE (DUP
, inst
);
15469 NEON_ENCODE (LANE
, inst
);
15470 do_neon_ld_st_lane ();
15473 /* L bit comes from bit mask. */
15474 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15475 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15476 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15478 if (inst
.operands
[1].postind
)
15480 int postreg
= inst
.operands
[1].imm
& 0xf;
15481 constraint (!inst
.operands
[1].immisreg
,
15482 _("post-index must be a register"));
15483 constraint (postreg
== 0xd || postreg
== 0xf,
15484 _("bad register for post-index"));
15485 inst
.instruction
|= postreg
;
15487 else if (inst
.operands
[1].writeback
)
15489 inst
.instruction
|= 0xd;
15492 inst
.instruction
|= 0xf;
15495 inst
.instruction
|= 0xf9000000;
15497 inst
.instruction
|= 0xf4000000;
15500 /* Overall per-instruction processing. */
15502 /* We need to be able to fix up arbitrary expressions in some statements.
15503 This is so that we can handle symbols that are an arbitrary distance from
15504 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15505 which returns part of an address in a form which will be valid for
15506 a data instruction. We do this by pushing the expression into a symbol
15507 in the expr_section, and creating a fix for that. */
15510 fix_new_arm (fragS
* frag
,
15524 /* Create an absolute valued symbol, so we have something to
15525 refer to in the object file. Unfortunately for us, gas's
15526 generic expression parsing will already have folded out
15527 any use of .set foo/.type foo %function that may have
15528 been used to set type information of the target location,
15529 that's being specified symbolically. We have to presume
15530 the user knows what they are doing. */
15534 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
15536 symbol
= symbol_find_or_make (name
);
15537 S_SET_SEGMENT (symbol
, absolute_section
);
15538 symbol_set_frag (symbol
, &zero_address_frag
);
15539 S_SET_VALUE (symbol
, exp
->X_add_number
);
15540 exp
->X_op
= O_symbol
;
15541 exp
->X_add_symbol
= symbol
;
15542 exp
->X_add_number
= 0;
15548 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15549 (enum bfd_reloc_code_real
) reloc
);
15553 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15554 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15558 /* Mark whether the fix is to a THUMB instruction, or an ARM
15560 new_fix
->tc_fix_data
= thumb_mode
;
15563 /* Create a frg for an instruction requiring relaxation. */
15565 output_relax_insn (void)
15571 /* The size of the instruction is unknown, so tie the debug info to the
15572 start of the instruction. */
15573 dwarf2_emit_insn (0);
15575 switch (inst
.reloc
.exp
.X_op
)
15578 sym
= inst
.reloc
.exp
.X_add_symbol
;
15579 offset
= inst
.reloc
.exp
.X_add_number
;
15583 offset
= inst
.reloc
.exp
.X_add_number
;
15586 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15590 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15591 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15592 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15595 /* Write a 32-bit thumb instruction to buf. */
15597 put_thumb32_insn (char * buf
, unsigned long insn
)
15599 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15600 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15604 output_inst (const char * str
)
15610 as_bad ("%s -- `%s'", inst
.error
, str
);
15615 output_relax_insn ();
15618 if (inst
.size
== 0)
15621 to
= frag_more (inst
.size
);
15622 /* PR 9814: Record the thumb mode into the current frag so that we know
15623 what type of NOP padding to use, if necessary. We override any previous
15624 setting so that if the mode has changed then the NOPS that we use will
15625 match the encoding of the last instruction in the frag. */
15626 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15628 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15630 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15631 put_thumb32_insn (to
, inst
.instruction
);
15633 else if (inst
.size
> INSN_SIZE
)
15635 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15636 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15637 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15640 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15642 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15643 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15644 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15647 dwarf2_emit_insn (inst
.size
);
15651 output_it_inst (int cond
, int mask
, char * to
)
15653 unsigned long instruction
= 0xbf00;
15656 instruction
|= mask
;
15657 instruction
|= cond
<< 4;
15661 to
= frag_more (2);
15663 dwarf2_emit_insn (2);
15667 md_number_to_chars (to
, instruction
, 2);
15672 /* Tag values used in struct asm_opcode's tag field. */
15675 OT_unconditional
, /* Instruction cannot be conditionalized.
15676 The ARM condition field is still 0xE. */
15677 OT_unconditionalF
, /* Instruction cannot be conditionalized
15678 and carries 0xF in its ARM condition field. */
15679 OT_csuffix
, /* Instruction takes a conditional suffix. */
15680 OT_csuffixF
, /* Some forms of the instruction take a conditional
15681 suffix, others place 0xF where the condition field
15683 OT_cinfix3
, /* Instruction takes a conditional infix,
15684 beginning at character index 3. (In
15685 unified mode, it becomes a suffix.) */
15686 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15687 tsts, cmps, cmns, and teqs. */
15688 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15689 character index 3, even in unified mode. Used for
15690 legacy instructions where suffix and infix forms
15691 may be ambiguous. */
15692 OT_csuf_or_in3
, /* Instruction takes either a conditional
15693 suffix or an infix at character index 3. */
15694 OT_odd_infix_unc
, /* This is the unconditional variant of an
15695 instruction that takes a conditional infix
15696 at an unusual position. In unified mode,
15697 this variant will accept a suffix. */
15698 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15699 are the conditional variants of instructions that
15700 take conditional infixes in unusual positions.
15701 The infix appears at character index
15702 (tag - OT_odd_infix_0). These are not accepted
15703 in unified mode. */
15706 /* Subroutine of md_assemble, responsible for looking up the primary
15707 opcode from the mnemonic the user wrote. STR points to the
15708 beginning of the mnemonic.
15710 This is not simply a hash table lookup, because of conditional
15711 variants. Most instructions have conditional variants, which are
15712 expressed with a _conditional affix_ to the mnemonic. If we were
15713 to encode each conditional variant as a literal string in the opcode
15714 table, it would have approximately 20,000 entries.
15716 Most mnemonics take this affix as a suffix, and in unified syntax,
15717 'most' is upgraded to 'all'. However, in the divided syntax, some
15718 instructions take the affix as an infix, notably the s-variants of
15719 the arithmetic instructions. Of those instructions, all but six
15720 have the infix appear after the third character of the mnemonic.
15722 Accordingly, the algorithm for looking up primary opcodes given
15725 1. Look up the identifier in the opcode table.
15726 If we find a match, go to step U.
15728 2. Look up the last two characters of the identifier in the
15729 conditions table. If we find a match, look up the first N-2
15730 characters of the identifier in the opcode table. If we
15731 find a match, go to step CE.
15733 3. Look up the fourth and fifth characters of the identifier in
15734 the conditions table. If we find a match, extract those
15735 characters from the identifier, and look up the remaining
15736 characters in the opcode table. If we find a match, go
15741 U. Examine the tag field of the opcode structure, in case this is
15742 one of the six instructions with its conditional infix in an
15743 unusual place. If it is, the tag tells us where to find the
15744 infix; look it up in the conditions table and set inst.cond
15745 accordingly. Otherwise, this is an unconditional instruction.
15746 Again set inst.cond accordingly. Return the opcode structure.
15748 CE. Examine the tag field to make sure this is an instruction that
15749 should receive a conditional suffix. If it is not, fail.
15750 Otherwise, set inst.cond from the suffix we already looked up,
15751 and return the opcode structure.
15753 CM. Examine the tag field to make sure this is an instruction that
15754 should receive a conditional infix after the third character.
15755 If it is not, fail. Otherwise, undo the edits to the current
15756 line of input and proceed as for case CE. */
15758 static const struct asm_opcode
*
15759 opcode_lookup (char **str
)
15763 const struct asm_opcode
*opcode
;
15764 const struct asm_cond
*cond
;
15767 /* Scan up to the end of the mnemonic, which must end in white space,
15768 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15769 for (base
= end
= *str
; *end
!= '\0'; end
++)
15770 if (*end
== ' ' || *end
== '.')
15776 /* Handle a possible width suffix and/or Neon type suffix. */
15781 /* The .w and .n suffixes are only valid if the unified syntax is in
15783 if (unified_syntax
&& end
[1] == 'w')
15785 else if (unified_syntax
&& end
[1] == 'n')
15790 inst
.vectype
.elems
= 0;
15792 *str
= end
+ offset
;
15794 if (end
[offset
] == '.')
15796 /* See if we have a Neon type suffix (possible in either unified or
15797 non-unified ARM syntax mode). */
15798 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15801 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15807 /* Look for unaffixed or special-case affixed mnemonic. */
15808 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15813 if (opcode
->tag
< OT_odd_infix_0
)
15815 inst
.cond
= COND_ALWAYS
;
15819 if (warn_on_deprecated
&& unified_syntax
)
15820 as_warn (_("conditional infixes are deprecated in unified syntax"));
15821 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15822 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15825 inst
.cond
= cond
->value
;
15829 /* Cannot have a conditional suffix on a mnemonic of less than two
15831 if (end
- base
< 3)
15834 /* Look for suffixed mnemonic. */
15836 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15837 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15839 if (opcode
&& cond
)
15842 switch (opcode
->tag
)
15844 case OT_cinfix3_legacy
:
15845 /* Ignore conditional suffixes matched on infix only mnemonics. */
15849 case OT_cinfix3_deprecated
:
15850 case OT_odd_infix_unc
:
15851 if (!unified_syntax
)
15853 /* else fall through */
15857 case OT_csuf_or_in3
:
15858 inst
.cond
= cond
->value
;
15861 case OT_unconditional
:
15862 case OT_unconditionalF
:
15864 inst
.cond
= cond
->value
;
15867 /* Delayed diagnostic. */
15868 inst
.error
= BAD_COND
;
15869 inst
.cond
= COND_ALWAYS
;
15878 /* Cannot have a usual-position infix on a mnemonic of less than
15879 six characters (five would be a suffix). */
15880 if (end
- base
< 6)
15883 /* Look for infixed mnemonic in the usual position. */
15885 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15889 memcpy (save
, affix
, 2);
15890 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15891 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15893 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15894 memcpy (affix
, save
, 2);
15897 && (opcode
->tag
== OT_cinfix3
15898 || opcode
->tag
== OT_cinfix3_deprecated
15899 || opcode
->tag
== OT_csuf_or_in3
15900 || opcode
->tag
== OT_cinfix3_legacy
))
15903 if (warn_on_deprecated
&& unified_syntax
15904 && (opcode
->tag
== OT_cinfix3
15905 || opcode
->tag
== OT_cinfix3_deprecated
))
15906 as_warn (_("conditional infixes are deprecated in unified syntax"));
15908 inst
.cond
= cond
->value
;
15915 /* This function generates an initial IT instruction, leaving its block
15916 virtually open for the new instructions. Eventually,
15917 the mask will be updated by now_it_add_mask () each time
15918 a new instruction needs to be included in the IT block.
15919 Finally, the block is closed with close_automatic_it_block ().
15920 The block closure can be requested either from md_assemble (),
15921 a tencode (), or due to a label hook. */
15924 new_automatic_it_block (int cond
)
15926 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15927 now_it
.mask
= 0x18;
15929 now_it
.block_length
= 1;
15930 mapping_state (MAP_THUMB
);
15931 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15934 /* Close an automatic IT block.
15935 See comments in new_automatic_it_block (). */
15938 close_automatic_it_block (void)
15940 now_it
.mask
= 0x10;
15941 now_it
.block_length
= 0;
15944 /* Update the mask of the current automatically-generated IT
15945 instruction. See comments in new_automatic_it_block (). */
15948 now_it_add_mask (int cond
)
15950 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15951 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15952 | ((bitvalue) << (nbit)))
15953 const int resulting_bit
= (cond
& 1);
15955 now_it
.mask
&= 0xf;
15956 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15958 (5 - now_it
.block_length
));
15959 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15961 ((5 - now_it
.block_length
) - 1) );
15962 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15965 #undef SET_BIT_VALUE
15968 /* The IT blocks handling machinery is accessed through the these functions:
15969 it_fsm_pre_encode () from md_assemble ()
15970 set_it_insn_type () optional, from the tencode functions
15971 set_it_insn_type_last () ditto
15972 in_it_block () ditto
15973 it_fsm_post_encode () from md_assemble ()
15974 force_automatic_it_block_close () from label habdling functions
15977 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15978 initializing the IT insn type with a generic initial value depending
15979 on the inst.condition.
15980 2) During the tencode function, two things may happen:
15981 a) The tencode function overrides the IT insn type by
15982 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15983 b) The tencode function queries the IT block state by
15984 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15986 Both set_it_insn_type and in_it_block run the internal FSM state
15987 handling function (handle_it_state), because: a) setting the IT insn
15988 type may incur in an invalid state (exiting the function),
15989 and b) querying the state requires the FSM to be updated.
15990 Specifically we want to avoid creating an IT block for conditional
15991 branches, so it_fsm_pre_encode is actually a guess and we can't
15992 determine whether an IT block is required until the tencode () routine
15993 has decided what type of instruction this actually it.
15994 Because of this, if set_it_insn_type and in_it_block have to be used,
15995 set_it_insn_type has to be called first.
15997 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15998 determines the insn IT type depending on the inst.cond code.
15999 When a tencode () routine encodes an instruction that can be
16000 either outside an IT block, or, in the case of being inside, has to be
16001 the last one, set_it_insn_type_last () will determine the proper
16002 IT instruction type based on the inst.cond code. Otherwise,
16003 set_it_insn_type can be called for overriding that logic or
16004 for covering other cases.
16006 Calling handle_it_state () may not transition the IT block state to
16007 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16008 still queried. Instead, if the FSM determines that the state should
16009 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16010 after the tencode () function: that's what it_fsm_post_encode () does.
16012 Since in_it_block () calls the state handling function to get an
16013 updated state, an error may occur (due to invalid insns combination).
16014 In that case, inst.error is set.
16015 Therefore, inst.error has to be checked after the execution of
16016 the tencode () routine.
16018 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16019 any pending state change (if any) that didn't take place in
16020 handle_it_state () as explained above. */
16023 it_fsm_pre_encode (void)
16025 if (inst
.cond
!= COND_ALWAYS
)
16026 inst
.it_insn_type
= INSIDE_IT_INSN
;
16028 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
16030 now_it
.state_handled
= 0;
16033 /* IT state FSM handling function. */
16036 handle_it_state (void)
16038 now_it
.state_handled
= 1;
16040 switch (now_it
.state
)
16042 case OUTSIDE_IT_BLOCK
:
16043 switch (inst
.it_insn_type
)
16045 case OUTSIDE_IT_INSN
:
16048 case INSIDE_IT_INSN
:
16049 case INSIDE_IT_LAST_INSN
:
16050 if (thumb_mode
== 0)
16053 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
16054 as_tsktsk (_("Warning: conditional outside an IT block"\
16059 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
16060 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
16062 /* Automatically generate the IT instruction. */
16063 new_automatic_it_block (inst
.cond
);
16064 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
16065 close_automatic_it_block ();
16069 inst
.error
= BAD_OUT_IT
;
16075 case IF_INSIDE_IT_LAST_INSN
:
16076 case NEUTRAL_IT_INSN
:
16080 now_it
.state
= MANUAL_IT_BLOCK
;
16081 now_it
.block_length
= 0;
16086 case AUTOMATIC_IT_BLOCK
:
16087 /* Three things may happen now:
16088 a) We should increment current it block size;
16089 b) We should close current it block (closing insn or 4 insns);
16090 c) We should close current it block and start a new one (due
16091 to incompatible conditions or
16092 4 insns-length block reached). */
16094 switch (inst
.it_insn_type
)
16096 case OUTSIDE_IT_INSN
:
16097 /* The closure of the block shall happen immediatelly,
16098 so any in_it_block () call reports the block as closed. */
16099 force_automatic_it_block_close ();
16102 case INSIDE_IT_INSN
:
16103 case INSIDE_IT_LAST_INSN
:
16104 case IF_INSIDE_IT_LAST_INSN
:
16105 now_it
.block_length
++;
16107 if (now_it
.block_length
> 4
16108 || !now_it_compatible (inst
.cond
))
16110 force_automatic_it_block_close ();
16111 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
16112 new_automatic_it_block (inst
.cond
);
16116 now_it_add_mask (inst
.cond
);
16119 if (now_it
.state
== AUTOMATIC_IT_BLOCK
16120 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
16121 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
16122 close_automatic_it_block ();
16125 case NEUTRAL_IT_INSN
:
16126 now_it
.block_length
++;
16128 if (now_it
.block_length
> 4)
16129 force_automatic_it_block_close ();
16131 now_it_add_mask (now_it
.cc
& 1);
16135 close_automatic_it_block ();
16136 now_it
.state
= MANUAL_IT_BLOCK
;
16141 case MANUAL_IT_BLOCK
:
16143 /* Check conditional suffixes. */
16144 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
16147 now_it
.mask
&= 0x1f;
16148 is_last
= (now_it
.mask
== 0x10);
16150 switch (inst
.it_insn_type
)
16152 case OUTSIDE_IT_INSN
:
16153 inst
.error
= BAD_NOT_IT
;
16156 case INSIDE_IT_INSN
:
16157 if (cond
!= inst
.cond
)
16159 inst
.error
= BAD_IT_COND
;
16164 case INSIDE_IT_LAST_INSN
:
16165 case IF_INSIDE_IT_LAST_INSN
:
16166 if (cond
!= inst
.cond
)
16168 inst
.error
= BAD_IT_COND
;
16173 inst
.error
= BAD_BRANCH
;
16178 case NEUTRAL_IT_INSN
:
16179 /* The BKPT instruction is unconditional even in an IT block. */
16183 inst
.error
= BAD_IT_IT
;
16194 it_fsm_post_encode (void)
16198 if (!now_it
.state_handled
)
16199 handle_it_state ();
16201 is_last
= (now_it
.mask
== 0x10);
16204 now_it
.state
= OUTSIDE_IT_BLOCK
;
16210 force_automatic_it_block_close (void)
16212 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
16214 close_automatic_it_block ();
16215 now_it
.state
= OUTSIDE_IT_BLOCK
;
16223 if (!now_it
.state_handled
)
16224 handle_it_state ();
16226 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
16230 md_assemble (char *str
)
16233 const struct asm_opcode
* opcode
;
16235 /* Align the previous label if needed. */
16236 if (last_label_seen
!= NULL
)
16238 symbol_set_frag (last_label_seen
, frag_now
);
16239 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
16240 S_SET_SEGMENT (last_label_seen
, now_seg
);
16243 memset (&inst
, '\0', sizeof (inst
));
16244 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
16246 opcode
= opcode_lookup (&p
);
16249 /* It wasn't an instruction, but it might be a register alias of
16250 the form alias .req reg, or a Neon .dn/.qn directive. */
16251 if (! create_register_alias (str
, p
)
16252 && ! create_neon_reg_alias (str
, p
))
16253 as_bad (_("bad instruction `%s'"), str
);
16258 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
16259 as_warn (_("s suffix on comparison instruction is deprecated"));
16261 /* The value which unconditional instructions should have in place of the
16262 condition field. */
16263 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
16267 arm_feature_set variant
;
16269 variant
= cpu_variant
;
16270 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16271 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
16272 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
16273 /* Check that this instruction is supported for this CPU. */
16274 if (!opcode
->tvariant
16275 || (thumb_mode
== 1
16276 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
16278 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
16281 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
16282 && opcode
->tencode
!= do_t_branch
)
16284 as_bad (_("Thumb does not support conditional execution"));
16288 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
16290 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
16291 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
16292 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
16294 /* Two things are addressed here.
16295 1) Implicit require narrow instructions on Thumb-1.
16296 This avoids relaxation accidentally introducing Thumb-2
16298 2) Reject wide instructions in non Thumb-2 cores. */
16299 if (inst
.size_req
== 0)
16301 else if (inst
.size_req
== 4)
16303 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
16309 inst
.instruction
= opcode
->tvalue
;
16311 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
16313 /* Prepare the it_insn_type for those encodings that don't set
16315 it_fsm_pre_encode ();
16317 opcode
->tencode ();
16319 it_fsm_post_encode ();
16322 if (!(inst
.error
|| inst
.relax
))
16324 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
16325 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
16326 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
16328 as_bad (_("cannot honor width suffix -- `%s'"), str
);
16333 /* Something has gone badly wrong if we try to relax a fixed size
16335 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
16337 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16338 *opcode
->tvariant
);
16339 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16340 set those bits when Thumb-2 32-bit instructions are seen. ie.
16341 anything other than bl/blx and v6-M instructions.
16342 This is overly pessimistic for relaxable instructions. */
16343 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
16345 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
16346 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
16347 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16350 check_neon_suffixes
;
16354 mapping_state (MAP_THUMB
);
16357 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
16361 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16362 is_bx
= (opcode
->aencode
== do_bx
);
16364 /* Check that this instruction is supported for this CPU. */
16365 if (!(is_bx
&& fix_v4bx
)
16366 && !(opcode
->avariant
&&
16367 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
16369 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
16374 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
16378 inst
.instruction
= opcode
->avalue
;
16379 if (opcode
->tag
== OT_unconditionalF
)
16380 inst
.instruction
|= 0xF << 28;
16382 inst
.instruction
|= inst
.cond
<< 28;
16383 inst
.size
= INSN_SIZE
;
16384 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
16386 it_fsm_pre_encode ();
16387 opcode
->aencode ();
16388 it_fsm_post_encode ();
16390 /* Arm mode bx is marked as both v4T and v5 because it's still required
16391 on a hypothetical non-thumb v5 core. */
16393 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
16395 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16396 *opcode
->avariant
);
16398 check_neon_suffixes
;
16402 mapping_state (MAP_ARM
);
16407 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16415 check_it_blocks_finished (void)
16420 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16421 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16422 == MANUAL_IT_BLOCK
)
16424 as_warn (_("section '%s' finished with an open IT block."),
16428 if (now_it
.state
== MANUAL_IT_BLOCK
)
16429 as_warn (_("file finished with an open IT block."));
16433 /* Various frobbings of labels and their addresses. */
16436 arm_start_line_hook (void)
16438 last_label_seen
= NULL
;
16442 arm_frob_label (symbolS
* sym
)
16444 last_label_seen
= sym
;
16446 ARM_SET_THUMB (sym
, thumb_mode
);
16448 #if defined OBJ_COFF || defined OBJ_ELF
16449 ARM_SET_INTERWORK (sym
, support_interwork
);
16452 force_automatic_it_block_close ();
16454 /* Note - do not allow local symbols (.Lxxx) to be labelled
16455 as Thumb functions. This is because these labels, whilst
16456 they exist inside Thumb code, are not the entry points for
16457 possible ARM->Thumb calls. Also, these labels can be used
16458 as part of a computed goto or switch statement. eg gcc
16459 can generate code that looks like this:
16461 ldr r2, [pc, .Laaa]
16471 The first instruction loads the address of the jump table.
16472 The second instruction converts a table index into a byte offset.
16473 The third instruction gets the jump address out of the table.
16474 The fourth instruction performs the jump.
16476 If the address stored at .Laaa is that of a symbol which has the
16477 Thumb_Func bit set, then the linker will arrange for this address
16478 to have the bottom bit set, which in turn would mean that the
16479 address computation performed by the third instruction would end
16480 up with the bottom bit set. Since the ARM is capable of unaligned
16481 word loads, the instruction would then load the incorrect address
16482 out of the jump table, and chaos would ensue. */
16483 if (label_is_thumb_function_name
16484 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16485 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16487 /* When the address of a Thumb function is taken the bottom
16488 bit of that address should be set. This will allow
16489 interworking between Arm and Thumb functions to work
16492 THUMB_SET_FUNC (sym
, 1);
16494 label_is_thumb_function_name
= FALSE
;
16497 dwarf2_emit_label (sym
);
16501 arm_data_in_code (void)
16503 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16505 *input_line_pointer
= '/';
16506 input_line_pointer
+= 5;
16507 *input_line_pointer
= 0;
16515 arm_canonicalize_symbol_name (char * name
)
16519 if (thumb_mode
&& (len
= strlen (name
)) > 5
16520 && streq (name
+ len
- 5, "/data"))
16521 *(name
+ len
- 5) = 0;
16526 /* Table of all register names defined by default. The user can
16527 define additional names with .req. Note that all register names
16528 should appear in both upper and lowercase variants. Some registers
16529 also have mixed-case names. */
16531 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16532 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16533 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16534 #define REGSET(p,t) \
16535 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16536 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16537 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16538 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16539 #define REGSETH(p,t) \
16540 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16541 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16542 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16543 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16544 #define REGSET2(p,t) \
16545 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16546 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16547 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16548 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16549 #define SPLRBANK(base,bank,t) \
16550 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16551 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16552 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16553 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16554 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16555 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16557 static const struct reg_entry reg_names
[] =
16559 /* ARM integer registers. */
16560 REGSET(r
, RN
), REGSET(R
, RN
),
16562 /* ATPCS synonyms. */
16563 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16564 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16565 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16567 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16568 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16569 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16571 /* Well-known aliases. */
16572 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16573 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16575 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16576 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16578 /* Coprocessor numbers. */
16579 REGSET(p
, CP
), REGSET(P
, CP
),
16581 /* Coprocessor register numbers. The "cr" variants are for backward
16583 REGSET(c
, CN
), REGSET(C
, CN
),
16584 REGSET(cr
, CN
), REGSET(CR
, CN
),
16586 /* ARM banked registers. */
16587 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
16588 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
16589 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
16590 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
16591 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
16592 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
16593 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
16595 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
16596 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
16597 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
16598 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
16599 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
16600 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(SP_fiq
,512|(13<<16),RNB
),
16601 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
16602 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
16604 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
16605 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
16606 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
16607 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
16608 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
16609 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
16610 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
16611 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16612 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16614 /* FPA registers. */
16615 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16616 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16618 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16619 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16621 /* VFP SP registers. */
16622 REGSET(s
,VFS
), REGSET(S
,VFS
),
16623 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16625 /* VFP DP Registers. */
16626 REGSET(d
,VFD
), REGSET(D
,VFD
),
16627 /* Extra Neon DP registers. */
16628 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16630 /* Neon QP registers. */
16631 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16633 /* VFP control registers. */
16634 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16635 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16636 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16637 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16638 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16639 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16641 /* Maverick DSP coprocessor registers. */
16642 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16643 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16645 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16646 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16647 REGDEF(dspsc
,0,DSPSC
),
16649 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16650 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16651 REGDEF(DSPSC
,0,DSPSC
),
16653 /* iWMMXt data registers - p0, c0-15. */
16654 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16656 /* iWMMXt control registers - p1, c0-3. */
16657 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16658 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16659 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16660 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16662 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16663 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16664 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16665 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16666 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16668 /* XScale accumulator registers. */
16669 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16675 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16676 within psr_required_here. */
16677 static const struct asm_psr psrs
[] =
16679 /* Backward compatibility notation. Note that "all" is no longer
16680 truly all possible PSR bits. */
16681 {"all", PSR_c
| PSR_f
},
16685 /* Individual flags. */
16691 /* Combinations of flags. */
16692 {"fs", PSR_f
| PSR_s
},
16693 {"fx", PSR_f
| PSR_x
},
16694 {"fc", PSR_f
| PSR_c
},
16695 {"sf", PSR_s
| PSR_f
},
16696 {"sx", PSR_s
| PSR_x
},
16697 {"sc", PSR_s
| PSR_c
},
16698 {"xf", PSR_x
| PSR_f
},
16699 {"xs", PSR_x
| PSR_s
},
16700 {"xc", PSR_x
| PSR_c
},
16701 {"cf", PSR_c
| PSR_f
},
16702 {"cs", PSR_c
| PSR_s
},
16703 {"cx", PSR_c
| PSR_x
},
16704 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16705 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16706 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16707 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16708 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16709 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16710 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16711 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16712 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16713 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16714 {"scf", PSR_s
| PSR_c
| PSR_f
},
16715 {"scx", PSR_s
| PSR_c
| PSR_x
},
16716 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16717 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16718 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16719 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16720 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16721 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16722 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16723 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16724 {"csf", PSR_c
| PSR_s
| PSR_f
},
16725 {"csx", PSR_c
| PSR_s
| PSR_x
},
16726 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16727 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16728 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16729 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16730 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16731 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16732 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16733 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16734 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16735 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16736 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16737 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16738 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16739 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16740 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16741 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16742 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16743 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16744 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16745 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16746 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16747 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16748 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16749 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16750 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16751 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16754 /* Table of V7M psr names. */
16755 static const struct asm_psr v7m_psrs
[] =
16757 {"apsr", 0 }, {"APSR", 0 },
16758 {"iapsr", 1 }, {"IAPSR", 1 },
16759 {"eapsr", 2 }, {"EAPSR", 2 },
16760 {"psr", 3 }, {"PSR", 3 },
16761 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16762 {"ipsr", 5 }, {"IPSR", 5 },
16763 {"epsr", 6 }, {"EPSR", 6 },
16764 {"iepsr", 7 }, {"IEPSR", 7 },
16765 {"msp", 8 }, {"MSP", 8 },
16766 {"psp", 9 }, {"PSP", 9 },
16767 {"primask", 16}, {"PRIMASK", 16},
16768 {"basepri", 17}, {"BASEPRI", 17},
16769 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16770 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16771 {"faultmask", 19}, {"FAULTMASK", 19},
16772 {"control", 20}, {"CONTROL", 20}
16775 /* Table of all shift-in-operand names. */
16776 static const struct asm_shift_name shift_names
[] =
16778 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16779 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16780 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16781 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16782 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16783 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16786 /* Table of all explicit relocation names. */
16788 static struct reloc_entry reloc_names
[] =
16790 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16791 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16792 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16793 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16794 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16795 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16796 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16797 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16798 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16799 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16800 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16801 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
16802 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
16803 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
16804 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
16805 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
16806 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
16807 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
16811 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16812 static const struct asm_cond conds
[] =
16816 {"cs", 0x2}, {"hs", 0x2},
16817 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16831 static struct asm_barrier_opt barrier_opt_names
[] =
16833 { "sy", 0xf }, { "SY", 0xf },
16834 { "un", 0x7 }, { "UN", 0x7 },
16835 { "st", 0xe }, { "ST", 0xe },
16836 { "unst", 0x6 }, { "UNST", 0x6 },
16837 { "ish", 0xb }, { "ISH", 0xb },
16838 { "sh", 0xb }, { "SH", 0xb },
16839 { "ishst", 0xa }, { "ISHST", 0xa },
16840 { "shst", 0xa }, { "SHST", 0xa },
16841 { "nsh", 0x7 }, { "NSH", 0x7 },
16842 { "nshst", 0x6 }, { "NSHST", 0x6 },
16843 { "osh", 0x3 }, { "OSH", 0x3 },
16844 { "oshst", 0x2 }, { "OSHST", 0x2 }
16847 /* Table of ARM-format instructions. */
16849 /* Macros for gluing together operand strings. N.B. In all cases
16850 other than OPS0, the trailing OP_stop comes from default
16851 zero-initialization of the unspecified elements of the array. */
16852 #define OPS0() { OP_stop, }
16853 #define OPS1(a) { OP_##a, }
16854 #define OPS2(a,b) { OP_##a,OP_##b, }
16855 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16856 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16857 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16858 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16860 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16861 This is useful when mixing operands for ARM and THUMB, i.e. using the
16862 MIX_ARM_THUMB_OPERANDS macro.
16863 In order to use these macros, prefix the number of operands with _
16865 #define OPS_1(a) { a, }
16866 #define OPS_2(a,b) { a,b, }
16867 #define OPS_3(a,b,c) { a,b,c, }
16868 #define OPS_4(a,b,c,d) { a,b,c,d, }
16869 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16870 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16872 /* These macros abstract out the exact format of the mnemonic table and
16873 save some repeated characters. */
16875 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16876 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16877 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16878 THUMB_VARIANT, do_##ae, do_##te }
16880 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16881 a T_MNEM_xyz enumerator. */
16882 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16883 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16884 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16885 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16887 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16888 infix after the third character. */
16889 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16890 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16891 THUMB_VARIANT, do_##ae, do_##te }
16892 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16893 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16894 THUMB_VARIANT, do_##ae, do_##te }
16895 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16896 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16897 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16898 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16899 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16900 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16901 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16902 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16904 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16905 appear in the condition table. */
16906 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16907 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16908 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16910 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16911 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16912 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16913 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16914 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16915 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16916 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16917 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16918 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16919 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16920 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16921 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16922 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16923 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16924 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16925 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16926 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16927 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16928 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16929 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16931 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16932 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16933 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16934 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16936 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16937 field is still 0xE. Many of the Thumb variants can be executed
16938 conditionally, so this is checked separately. */
16939 #define TUE(mnem, op, top, nops, ops, ae, te) \
16940 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16941 THUMB_VARIANT, do_##ae, do_##te }
16943 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16944 condition code field. */
16945 #define TUF(mnem, op, top, nops, ops, ae, te) \
16946 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16947 THUMB_VARIANT, do_##ae, do_##te }
16949 /* ARM-only variants of all the above. */
16950 #define CE(mnem, op, nops, ops, ae) \
16951 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16953 #define C3(mnem, op, nops, ops, ae) \
16954 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16956 /* Legacy mnemonics that always have conditional infix after the third
16958 #define CL(mnem, op, nops, ops, ae) \
16959 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16960 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16962 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16963 #define cCE(mnem, op, nops, ops, ae) \
16964 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16966 /* Legacy coprocessor instructions where conditional infix and conditional
16967 suffix are ambiguous. For consistency this includes all FPA instructions,
16968 not just the potentially ambiguous ones. */
16969 #define cCL(mnem, op, nops, ops, ae) \
16970 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16971 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16973 /* Coprocessor, takes either a suffix or a position-3 infix
16974 (for an FPA corner case). */
16975 #define C3E(mnem, op, nops, ops, ae) \
16976 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16977 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16979 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16980 { m1 #m2 m3, OPS##nops ops, \
16981 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16982 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16984 #define CM(m1, m2, op, nops, ops, ae) \
16985 xCM_ (m1, , m2, op, nops, ops, ae), \
16986 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16987 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16988 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16989 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16990 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16991 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16992 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16993 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16994 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16995 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16996 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16997 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16998 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16999 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17000 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17001 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17002 xCM_ (m1, le, m2, op, nops, ops, ae), \
17003 xCM_ (m1, al, m2, op, nops, ops, ae)
17005 #define UE(mnem, op, nops, ops, ae) \
17006 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17008 #define UF(mnem, op, nops, ops, ae) \
17009 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17011 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17012 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17013 use the same encoding function for each. */
17014 #define NUF(mnem, op, nops, ops, enc) \
17015 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17016 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17018 /* Neon data processing, version which indirects through neon_enc_tab for
17019 the various overloaded versions of opcodes. */
17020 #define nUF(mnem, op, nops, ops, enc) \
17021 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17022 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17024 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17026 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17027 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17028 THUMB_VARIANT, do_##enc, do_##enc }
17030 #define NCE(mnem, op, nops, ops, enc) \
17031 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17033 #define NCEF(mnem, op, nops, ops, enc) \
17034 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17036 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17037 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17038 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17039 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17041 #define nCE(mnem, op, nops, ops, enc) \
17042 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17044 #define nCEF(mnem, op, nops, ops, enc) \
17045 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17049 static const struct asm_opcode insns
[] =
17051 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17052 #define THUMB_VARIANT &arm_ext_v4t
17053 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17054 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17055 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17056 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17057 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17058 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17059 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17060 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17061 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17062 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17063 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17064 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17065 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17066 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17067 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17068 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17070 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17071 for setting PSR flag bits. They are obsolete in V6 and do not
17072 have Thumb equivalents. */
17073 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17074 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17075 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
17076 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17077 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17078 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
17079 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17080 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17081 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
17083 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17084 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17085 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17086 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17088 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
17089 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17090 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
17092 OP_ADDRGLDR
),ldst
, t_ldst
),
17093 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17095 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17096 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17097 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17098 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17099 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17100 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17102 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17103 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17104 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
17105 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
17108 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
17109 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
17110 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
17112 /* Thumb-compatibility pseudo ops. */
17113 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17114 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17115 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17116 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17117 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17118 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17119 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17120 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17121 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
17122 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
17123 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
17124 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
17126 /* These may simplify to neg. */
17127 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17128 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17130 #undef THUMB_VARIANT
17131 #define THUMB_VARIANT & arm_ext_v6
17133 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
17135 /* V1 instructions with no Thumb analogue prior to V6T2. */
17136 #undef THUMB_VARIANT
17137 #define THUMB_VARIANT & arm_ext_v6t2
17139 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17140 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17141 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
17143 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17144 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17145 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
17146 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17148 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17149 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17151 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17152 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17154 /* V1 instructions with no Thumb analogue at all. */
17155 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
17156 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
17158 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17159 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17160 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17161 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17162 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17163 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17164 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17165 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17168 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17169 #undef THUMB_VARIANT
17170 #define THUMB_VARIANT & arm_ext_v4t
17172 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17173 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17175 #undef THUMB_VARIANT
17176 #define THUMB_VARIANT & arm_ext_v6t2
17178 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17179 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
17181 /* Generic coprocessor instructions. */
17182 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17183 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17184 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17185 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17186 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17187 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17188 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17191 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17193 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17194 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17197 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17198 #undef THUMB_VARIANT
17199 #define THUMB_VARIANT & arm_ext_msr
17201 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
17202 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
17205 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17206 #undef THUMB_VARIANT
17207 #define THUMB_VARIANT & arm_ext_v6t2
17209 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17210 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17211 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17212 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17213 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17214 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17215 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17216 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17219 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17220 #undef THUMB_VARIANT
17221 #define THUMB_VARIANT & arm_ext_v4t
17223 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17224 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17225 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17226 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17227 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17228 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17231 #define ARM_VARIANT & arm_ext_v4t_5
17233 /* ARM Architecture 4T. */
17234 /* Note: bx (and blx) are required on V5, even if the processor does
17235 not support Thumb. */
17236 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
17239 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17240 #undef THUMB_VARIANT
17241 #define THUMB_VARIANT & arm_ext_v5t
17243 /* Note: blx has 2 variants; the .value coded here is for
17244 BLX(2). Only this variant has conditional execution. */
17245 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
17246 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
17248 #undef THUMB_VARIANT
17249 #define THUMB_VARIANT & arm_ext_v6t2
17251 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
17252 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17253 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17254 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17255 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17256 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17257 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17258 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17261 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17262 #undef THUMB_VARIANT
17263 #define THUMB_VARIANT &arm_ext_v5exp
17265 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17266 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17267 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17268 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17270 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17271 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17273 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17274 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17275 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17276 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17278 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17279 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17280 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17281 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17283 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17284 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17286 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17287 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17288 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17289 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17292 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17293 #undef THUMB_VARIANT
17294 #define THUMB_VARIANT &arm_ext_v6t2
17296 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
17297 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
17299 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
17300 ADDRGLDRS
), ldrd
, t_ldstd
),
17302 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17303 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17306 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17308 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
17311 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17312 #undef THUMB_VARIANT
17313 #define THUMB_VARIANT & arm_ext_v6
17315 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17316 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17317 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17318 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17319 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17320 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17321 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17322 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17323 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17324 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
17326 #undef THUMB_VARIANT
17327 #define THUMB_VARIANT & arm_ext_v6t2
17329 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
17330 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17332 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17333 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17335 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
17336 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
17338 /* ARM V6 not included in V7M. */
17339 #undef THUMB_VARIANT
17340 #define THUMB_VARIANT & arm_ext_v6_notm
17341 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17342 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
17343 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
17344 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17345 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17346 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
17347 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
17348 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17349 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
17350 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
17351 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
17352 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
17354 /* ARM V6 not included in V7M (eg. integer SIMD). */
17355 #undef THUMB_VARIANT
17356 #define THUMB_VARIANT & arm_ext_v6_dsp
17357 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
17358 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
17359 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
17360 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17361 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17362 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17363 /* Old name for QASX. */
17364 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17365 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17366 /* Old name for QSAX. */
17367 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17368 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17369 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17370 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17371 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17372 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17373 /* Old name for SASX. */
17374 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17375 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17376 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17377 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17378 /* Old name for SHASX. */
17379 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17380 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17381 /* Old name for SHSAX. */
17382 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17383 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17384 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17385 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17386 /* Old name for SSAX. */
17387 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17388 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17389 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17390 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17391 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17392 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17393 /* Old name for UASX. */
17394 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17395 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17396 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17397 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17398 /* Old name for UHASX. */
17399 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17400 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17401 /* Old name for UHSAX. */
17402 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17403 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17404 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17405 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17406 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17407 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17408 /* Old name for UQASX. */
17409 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17410 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17411 /* Old name for UQSAX. */
17412 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17413 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17414 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17415 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17416 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17417 /* Old name for USAX. */
17418 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17419 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17420 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17421 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17422 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17423 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17424 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17425 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17426 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17427 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17428 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17429 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17430 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17431 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17432 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17433 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17434 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17435 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17436 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17437 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17438 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17439 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17440 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17441 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17442 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17443 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17444 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17445 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17446 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17447 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17448 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17449 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17450 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17451 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17454 #define ARM_VARIANT & arm_ext_v6k
17455 #undef THUMB_VARIANT
17456 #define THUMB_VARIANT & arm_ext_v6k
17458 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17459 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17460 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17461 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17463 #undef THUMB_VARIANT
17464 #define THUMB_VARIANT & arm_ext_v6_notm
17465 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17467 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17468 RRnpcb
), strexd
, t_strexd
),
17470 #undef THUMB_VARIANT
17471 #define THUMB_VARIANT & arm_ext_v6t2
17472 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17474 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17476 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17478 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17480 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17483 #define ARM_VARIANT & arm_ext_sec
17484 #undef THUMB_VARIANT
17485 #define THUMB_VARIANT & arm_ext_sec
17487 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17490 #define ARM_VARIANT & arm_ext_virt
17491 #undef THUMB_VARIANT
17492 #define THUMB_VARIANT & arm_ext_virt
17494 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
17495 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
17498 #define ARM_VARIANT & arm_ext_v6t2
17499 #undef THUMB_VARIANT
17500 #define THUMB_VARIANT & arm_ext_v6t2
17502 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17503 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17504 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17505 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17507 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17508 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17509 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17510 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17512 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17513 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17514 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17515 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17517 /* Thumb-only instructions. */
17519 #define ARM_VARIANT NULL
17520 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17521 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17523 /* ARM does not really have an IT instruction, so always allow it.
17524 The opcode is copied from Thumb in order to allow warnings in
17525 -mimplicit-it=[never | arm] modes. */
17527 #define ARM_VARIANT & arm_ext_v1
17529 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17530 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17531 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17532 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17533 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17534 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17535 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17536 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17537 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17538 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17539 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17540 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17541 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17542 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17543 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17544 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17545 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17546 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17548 /* Thumb2 only instructions. */
17550 #define ARM_VARIANT NULL
17552 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17553 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17554 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17555 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17556 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17557 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17559 /* Hardware division instructions. */
17561 #define ARM_VARIANT & arm_ext_adiv
17562 #undef THUMB_VARIANT
17563 #define THUMB_VARIANT & arm_ext_div
17565 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17566 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17568 /* ARM V6M/V7 instructions. */
17570 #define ARM_VARIANT & arm_ext_barrier
17571 #undef THUMB_VARIANT
17572 #define THUMB_VARIANT & arm_ext_barrier
17574 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17575 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17576 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17578 /* ARM V7 instructions. */
17580 #define ARM_VARIANT & arm_ext_v7
17581 #undef THUMB_VARIANT
17582 #define THUMB_VARIANT & arm_ext_v7
17584 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17585 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17588 #define ARM_VARIANT & arm_ext_mp
17589 #undef THUMB_VARIANT
17590 #define THUMB_VARIANT & arm_ext_mp
17592 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
17595 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17597 cCE("wfs", e200110
, 1, (RR
), rd
),
17598 cCE("rfs", e300110
, 1, (RR
), rd
),
17599 cCE("wfc", e400110
, 1, (RR
), rd
),
17600 cCE("rfc", e500110
, 1, (RR
), rd
),
17602 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17603 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17604 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17605 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17607 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17608 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17609 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17610 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17612 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17613 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17614 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17615 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17616 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17617 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17618 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17619 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17620 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17621 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17622 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17623 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17625 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17626 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17627 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17628 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17629 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17630 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17631 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17632 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17633 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17634 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17635 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17636 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17638 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17639 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17640 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17641 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17642 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17643 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17644 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17645 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17646 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17647 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17648 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17649 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17651 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17652 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17653 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17654 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17655 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17656 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17657 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17658 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17659 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17660 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17661 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17662 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17664 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17665 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17666 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17667 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17668 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17669 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17670 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17671 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17672 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17673 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17674 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17675 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17677 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17678 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17679 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17680 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17681 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17682 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17683 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17684 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17685 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17686 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17687 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17688 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17690 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17691 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17692 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17693 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17694 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17695 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17696 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17697 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17698 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17699 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17700 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17701 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17703 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17704 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17705 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17706 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17707 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17708 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17709 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17710 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17711 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17712 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17713 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17714 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17716 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17717 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17718 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17719 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17720 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17721 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17722 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17723 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17724 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17725 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17726 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17727 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17729 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17730 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17731 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17732 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17733 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17734 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17735 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17736 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17737 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17738 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17739 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17740 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17742 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17743 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17744 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17745 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17746 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17747 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17748 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17749 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17750 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17751 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17752 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17753 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17755 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17756 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17757 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17758 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17759 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17760 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17761 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17762 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17763 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17764 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17765 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17766 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17768 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17769 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17770 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17771 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17772 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17773 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17774 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17775 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17776 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17777 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17778 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17779 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17781 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17782 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17783 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17784 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17785 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17786 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17787 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17788 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17789 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17790 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17791 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17792 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17794 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17795 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17796 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17797 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17798 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17799 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17800 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17801 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17802 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17803 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17804 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17805 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17807 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17808 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17809 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17810 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17811 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17812 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17813 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17814 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17815 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17816 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17817 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17818 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17820 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17821 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17822 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17823 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17824 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17825 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17826 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17827 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17828 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17829 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17830 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17831 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17833 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17834 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17835 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17836 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17837 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17838 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17839 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17840 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17841 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17842 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17843 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17844 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17846 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17847 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17848 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17849 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17850 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17851 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17852 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17853 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17854 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17855 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17856 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17857 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17859 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17860 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17861 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17862 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17863 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17864 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17865 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17866 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17867 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17868 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17869 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17870 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17872 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17873 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17874 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17875 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17876 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17877 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17878 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17879 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17880 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17881 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17882 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17883 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17885 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17886 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17887 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17888 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17889 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17890 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17891 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17892 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17893 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17894 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17895 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17896 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17898 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17899 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17900 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17901 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17902 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17903 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17904 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17905 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17906 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17907 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17908 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17909 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17911 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17912 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17913 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17914 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17915 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17916 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17917 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17918 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17919 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17920 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17921 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17922 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17924 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17925 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17926 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17927 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17928 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17929 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17930 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17931 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17932 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17933 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17934 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17935 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17937 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17938 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17939 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17940 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17941 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17942 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17943 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17944 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17945 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17946 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17947 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17948 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17950 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17951 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17952 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17953 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17954 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17955 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17956 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17957 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17958 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17959 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17960 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17961 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17963 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17964 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17965 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17966 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17967 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17968 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17969 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17970 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17971 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17972 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17973 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17974 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17976 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17977 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17978 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17979 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17980 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17981 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17982 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17983 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17984 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17985 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17986 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17987 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17989 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17990 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17991 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17992 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17994 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17995 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17996 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17997 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17998 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17999 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
18000 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
18001 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
18002 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
18003 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
18004 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
18005 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
18007 /* The implementation of the FIX instruction is broken on some
18008 assemblers, in that it accepts a precision specifier as well as a
18009 rounding specifier, despite the fact that this is meaningless.
18010 To be more compatible, we accept it as well, though of course it
18011 does not set any bits. */
18012 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
18013 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
18014 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
18015 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
18016 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
18017 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
18018 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
18019 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
18020 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
18021 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
18022 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
18023 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
18024 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
18026 /* Instructions that were new with the real FPA, call them V2. */
18028 #define ARM_VARIANT & fpu_fpa_ext_v2
18030 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18031 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18032 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18033 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18034 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18035 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18038 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18040 /* Moves and type conversions. */
18041 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18042 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
18043 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
18044 cCE("fmstat", ef1fa10
, 0, (), noargs
),
18045 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
18046 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
18047 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18048 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18049 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18050 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18051 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18052 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18053 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
18054 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
18056 /* Memory operations. */
18057 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
18058 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
18059 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18060 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18061 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18062 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18063 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18064 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18065 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18066 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18067 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18068 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18069 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18070 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18071 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18072 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18073 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18074 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18076 /* Monadic operations. */
18077 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18078 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18079 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18081 /* Dyadic operations. */
18082 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18083 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18084 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18085 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18086 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18087 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18088 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18089 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18090 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18093 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18094 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
18095 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18096 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
18098 /* Double precision load/store are still present on single precision
18099 implementations. */
18100 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18101 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18102 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18103 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18104 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18105 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18106 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18107 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18108 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18109 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18112 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18114 /* Moves and type conversions. */
18115 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18116 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18117 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18118 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18119 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18120 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18121 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18122 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18123 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18124 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18125 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18126 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18127 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18129 /* Monadic operations. */
18130 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18131 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18132 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18134 /* Dyadic operations. */
18135 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18136 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18137 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18138 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18139 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18140 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18141 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18142 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18143 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18146 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18147 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
18148 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18149 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
18152 #define ARM_VARIANT & fpu_vfp_ext_v2
18154 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
18155 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
18156 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
18157 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
18159 /* Instructions which may belong to either the Neon or VFP instruction sets.
18160 Individual encoder functions perform additional architecture checks. */
18162 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18163 #undef THUMB_VARIANT
18164 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18166 /* These mnemonics are unique to VFP. */
18167 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
18168 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
18169 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18170 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18171 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18172 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18173 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18174 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
18175 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
18176 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
18178 /* Mnemonics shared by Neon and VFP. */
18179 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
18180 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18181 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18183 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18184 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18186 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18187 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18189 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18190 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18191 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18192 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18193 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18194 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18195 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18196 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18198 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
18199 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
18200 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
18201 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
18204 /* NOTE: All VMOV encoding is special-cased! */
18205 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
18206 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
18208 #undef THUMB_VARIANT
18209 #define THUMB_VARIANT & fpu_neon_ext_v1
18211 #define ARM_VARIANT & fpu_neon_ext_v1
18213 /* Data processing with three registers of the same length. */
18214 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18215 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
18216 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
18217 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18218 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18219 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18220 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18221 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18222 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18223 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18224 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18225 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18226 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18227 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18228 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18229 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18230 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18231 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18232 /* If not immediate, fall back to neon_dyadic_i64_su.
18233 shl_imm should accept I8 I16 I32 I64,
18234 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18235 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
18236 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
18237 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
18238 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
18239 /* Logic ops, types optional & ignored. */
18240 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18241 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18242 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18243 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18244 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18245 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18246 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18247 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18248 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
18249 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
18250 /* Bitfield ops, untyped. */
18251 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18252 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18253 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18254 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18255 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18256 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18257 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18258 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18259 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18260 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18261 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18262 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18263 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18264 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18265 back to neon_dyadic_if_su. */
18266 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18267 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18268 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18269 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18270 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18271 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18272 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18273 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18274 /* Comparison. Type I8 I16 I32 F32. */
18275 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
18276 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
18277 /* As above, D registers only. */
18278 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18279 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18280 /* Int and float variants, signedness unimportant. */
18281 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18282 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18283 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
18284 /* Add/sub take types I8 I16 I32 I64 F32. */
18285 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18286 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18287 /* vtst takes sizes 8, 16, 32. */
18288 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
18289 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
18290 /* VMUL takes I8 I16 I32 F32 P8. */
18291 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
18292 /* VQD{R}MULH takes S16 S32. */
18293 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18294 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18295 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18296 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18297 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18298 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18299 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18300 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18301 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18302 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18303 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18304 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18305 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18306 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18307 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18308 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18310 /* Two address, int/float. Types S8 S16 S32 F32. */
18311 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18312 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18314 /* Data processing with two registers and a shift amount. */
18315 /* Right shifts, and variants with rounding.
18316 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18317 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18318 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18319 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18320 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18321 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18322 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18323 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18324 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18325 /* Shift and insert. Sizes accepted 8 16 32 64. */
18326 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
18327 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
18328 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
18329 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
18330 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18331 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
18332 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
18333 /* Right shift immediate, saturating & narrowing, with rounding variants.
18334 Types accepted S16 S32 S64 U16 U32 U64. */
18335 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18336 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18337 /* As above, unsigned. Types accepted S16 S32 S64. */
18338 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18339 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18340 /* Right shift narrowing. Types accepted I16 I32 I64. */
18341 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18342 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18343 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18344 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
18345 /* CVT with optional immediate for fixed-point variant. */
18346 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
18348 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
18349 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
18351 /* Data processing, three registers of different lengths. */
18352 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18353 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
18354 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18355 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18356 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18357 /* If not scalar, fall back to neon_dyadic_long.
18358 Vector types as above, scalar types S16 S32 U16 U32. */
18359 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18360 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18361 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18362 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18363 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18364 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18365 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18366 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18367 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18368 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18369 /* Saturating doubling multiplies. Types S16 S32. */
18370 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18371 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18372 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18373 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18374 S16 S32 U16 U32. */
18375 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
18377 /* Extract. Size 8. */
18378 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
18379 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
18381 /* Two registers, miscellaneous. */
18382 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18383 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
18384 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
18385 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
18386 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
18387 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
18388 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
18389 /* Vector replicate. Sizes 8 16 32. */
18390 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
18391 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
18392 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18393 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
18394 /* VMOVN. Types I16 I32 I64. */
18395 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
18396 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18397 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
18398 /* VQMOVUN. Types S16 S32 S64. */
18399 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
18400 /* VZIP / VUZP. Sizes 8 16 32. */
18401 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18402 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18403 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18404 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18405 /* VQABS / VQNEG. Types S8 S16 S32. */
18406 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18407 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18408 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18409 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18410 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18411 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18412 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
18413 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18414 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
18415 /* Reciprocal estimates. Types U32 F32. */
18416 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18417 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
18418 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18419 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
18420 /* VCLS. Types S8 S16 S32. */
18421 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
18422 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
18423 /* VCLZ. Types I8 I16 I32. */
18424 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
18425 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
18426 /* VCNT. Size 8. */
18427 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
18428 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
18429 /* Two address, untyped. */
18430 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
18431 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
18432 /* VTRN. Sizes 8 16 32. */
18433 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
18434 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
18436 /* Table lookup. Size 8. */
18437 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18438 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18440 #undef THUMB_VARIANT
18441 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18443 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18445 /* Neon element/structure load/store. */
18446 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18447 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18448 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18449 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18450 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18451 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18452 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18453 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18455 #undef THUMB_VARIANT
18456 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18458 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18459 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18460 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18461 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18462 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18463 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18464 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18465 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18466 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18467 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18469 #undef THUMB_VARIANT
18470 #define THUMB_VARIANT & fpu_vfp_ext_v3
18472 #define ARM_VARIANT & fpu_vfp_ext_v3
18474 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18475 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18476 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18477 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18478 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18479 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18480 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18481 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18482 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18485 #define ARM_VARIANT &fpu_vfp_ext_fma
18486 #undef THUMB_VARIANT
18487 #define THUMB_VARIANT &fpu_vfp_ext_fma
18488 /* Mnemonics shared by Neon and VFP. These are included in the
18489 VFP FMA variant; NEON and VFP FMA always includes the NEON
18490 FMA instructions. */
18491 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18492 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18493 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18494 the v form should always be used. */
18495 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18496 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18497 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18498 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18499 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18500 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18502 #undef THUMB_VARIANT
18504 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18506 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18507 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18508 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18509 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18510 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18511 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18512 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18513 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18516 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18518 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18519 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18520 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18521 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18522 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18523 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18524 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18525 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18526 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18527 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18528 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18529 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18530 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18531 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18532 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18533 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18534 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18535 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18536 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18537 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18538 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18539 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18540 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18541 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18542 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18543 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18544 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18545 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18546 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18547 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18548 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18549 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18550 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18551 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18552 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18553 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18554 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18555 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18556 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18557 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18558 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18559 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18560 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18561 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18562 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18563 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18564 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18565 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18566 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18567 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18568 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18569 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18570 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18571 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18572 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18573 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18574 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18575 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18576 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18577 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18578 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18579 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18580 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18581 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18582 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18583 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18584 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18585 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18586 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18587 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18588 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18589 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18590 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18591 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18592 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18593 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18594 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18595 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18596 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18597 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18598 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18599 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18600 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18601 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18602 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18603 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18604 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18605 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18606 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18607 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18608 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18609 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18610 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18611 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18612 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18613 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18614 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18615 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18616 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18617 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18618 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18619 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18620 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18621 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18622 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18623 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18624 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18625 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18626 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18627 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18628 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18629 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18630 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18631 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18632 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18633 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18634 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18635 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18636 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18637 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18638 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18639 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18640 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18641 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18642 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18643 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18644 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18645 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18646 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18647 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18648 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18649 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18650 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18651 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18652 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18653 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18654 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18655 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18656 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18657 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18658 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18659 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18660 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18661 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18662 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18663 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18664 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18665 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18666 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18667 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18668 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18669 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18670 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18671 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18672 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18673 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18674 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18675 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18676 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18677 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18678 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18679 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18682 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18684 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18685 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18686 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18687 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18688 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18689 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18690 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18691 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18692 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18693 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18694 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18695 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18696 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18697 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18698 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18699 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18700 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18701 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18702 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18703 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18704 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18705 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18706 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18707 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18708 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18709 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18710 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18711 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18712 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18713 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18714 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18715 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18716 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18717 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18718 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18719 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18720 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18721 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18722 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18723 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18724 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18725 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18726 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18727 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18728 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18729 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18730 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18731 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18732 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18733 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18734 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18735 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18736 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18737 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18738 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18739 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18740 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18743 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18745 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18746 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18747 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18748 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18749 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18750 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18751 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18752 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18753 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18754 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18755 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18756 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18757 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18758 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18759 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18760 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18761 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18762 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18763 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18764 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18765 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18766 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18767 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18768 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18769 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18770 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18771 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18772 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18773 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18774 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18775 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18776 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18777 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18778 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18779 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18780 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18781 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18782 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18783 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18784 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18785 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18786 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18787 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18788 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18789 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18790 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18791 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18792 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18793 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18794 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18795 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18796 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18797 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18798 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18799 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18800 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18801 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18802 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18803 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18804 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18805 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18806 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18807 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18808 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18809 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18810 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18811 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18812 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18813 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18814 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18815 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18816 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18817 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18818 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18819 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18820 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18823 #undef THUMB_VARIANT
18850 /* MD interface: bits in the object file. */
18852 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18853 for use in the a.out file, and stores them in the array pointed to by buf.
18854 This knows about the endian-ness of the target machine and does
18855 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18856 2 (short) and 4 (long) Floating numbers are put out as a series of
18857 LITTLENUMS (shorts, here at least). */
18860 md_number_to_chars (char * buf
, valueT val
, int n
)
18862 if (target_big_endian
)
18863 number_to_chars_bigendian (buf
, val
, n
);
18865 number_to_chars_littleendian (buf
, val
, n
);
18869 md_chars_to_number (char * buf
, int n
)
18872 unsigned char * where
= (unsigned char *) buf
;
18874 if (target_big_endian
)
18879 result
|= (*where
++ & 255);
18887 result
|= (where
[n
] & 255);
18894 /* MD interface: Sections. */
18896 /* Estimate the size of a frag before relaxing. Assume everything fits in
18900 md_estimate_size_before_relax (fragS
* fragp
,
18901 segT segtype ATTRIBUTE_UNUSED
)
18907 /* Convert a machine dependent frag. */
18910 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18912 unsigned long insn
;
18913 unsigned long old_op
;
18921 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18923 old_op
= bfd_get_16(abfd
, buf
);
18924 if (fragp
->fr_symbol
)
18926 exp
.X_op
= O_symbol
;
18927 exp
.X_add_symbol
= fragp
->fr_symbol
;
18931 exp
.X_op
= O_constant
;
18933 exp
.X_add_number
= fragp
->fr_offset
;
18934 opcode
= fragp
->fr_subtype
;
18937 case T_MNEM_ldr_pc
:
18938 case T_MNEM_ldr_pc2
:
18939 case T_MNEM_ldr_sp
:
18940 case T_MNEM_str_sp
:
18947 if (fragp
->fr_var
== 4)
18949 insn
= THUMB_OP32 (opcode
);
18950 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18952 insn
|= (old_op
& 0x700) << 4;
18956 insn
|= (old_op
& 7) << 12;
18957 insn
|= (old_op
& 0x38) << 13;
18959 insn
|= 0x00000c00;
18960 put_thumb32_insn (buf
, insn
);
18961 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18965 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18967 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18970 if (fragp
->fr_var
== 4)
18972 insn
= THUMB_OP32 (opcode
);
18973 insn
|= (old_op
& 0xf0) << 4;
18974 put_thumb32_insn (buf
, insn
);
18975 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18979 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18980 exp
.X_add_number
-= 4;
18988 if (fragp
->fr_var
== 4)
18990 int r0off
= (opcode
== T_MNEM_mov
18991 || opcode
== T_MNEM_movs
) ? 0 : 8;
18992 insn
= THUMB_OP32 (opcode
);
18993 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18994 insn
|= (old_op
& 0x700) << r0off
;
18995 put_thumb32_insn (buf
, insn
);
18996 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
19000 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
19005 if (fragp
->fr_var
== 4)
19007 insn
= THUMB_OP32(opcode
);
19008 put_thumb32_insn (buf
, insn
);
19009 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
19012 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
19016 if (fragp
->fr_var
== 4)
19018 insn
= THUMB_OP32(opcode
);
19019 insn
|= (old_op
& 0xf00) << 14;
19020 put_thumb32_insn (buf
, insn
);
19021 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
19024 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
19027 case T_MNEM_add_sp
:
19028 case T_MNEM_add_pc
:
19029 case T_MNEM_inc_sp
:
19030 case T_MNEM_dec_sp
:
19031 if (fragp
->fr_var
== 4)
19033 /* ??? Choose between add and addw. */
19034 insn
= THUMB_OP32 (opcode
);
19035 insn
|= (old_op
& 0xf0) << 4;
19036 put_thumb32_insn (buf
, insn
);
19037 if (opcode
== T_MNEM_add_pc
)
19038 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
19040 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
19043 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19051 if (fragp
->fr_var
== 4)
19053 insn
= THUMB_OP32 (opcode
);
19054 insn
|= (old_op
& 0xf0) << 4;
19055 insn
|= (old_op
& 0xf) << 16;
19056 put_thumb32_insn (buf
, insn
);
19057 if (insn
& (1 << 20))
19058 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
19060 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
19063 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19069 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
19070 (enum bfd_reloc_code_real
) reloc_type
);
19071 fixp
->fx_file
= fragp
->fr_file
;
19072 fixp
->fx_line
= fragp
->fr_line
;
19073 fragp
->fr_fix
+= fragp
->fr_var
;
19076 /* Return the size of a relaxable immediate operand instruction.
19077 SHIFT and SIZE specify the form of the allowable immediate. */
19079 relax_immediate (fragS
*fragp
, int size
, int shift
)
19085 /* ??? Should be able to do better than this. */
19086 if (fragp
->fr_symbol
)
19089 low
= (1 << shift
) - 1;
19090 mask
= (1 << (shift
+ size
)) - (1 << shift
);
19091 offset
= fragp
->fr_offset
;
19092 /* Force misaligned offsets to 32-bit variant. */
19095 if (offset
& ~mask
)
19100 /* Get the address of a symbol during relaxation. */
19102 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
19108 sym
= fragp
->fr_symbol
;
19109 sym_frag
= symbol_get_frag (sym
);
19110 know (S_GET_SEGMENT (sym
) != absolute_section
19111 || sym_frag
== &zero_address_frag
);
19112 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
19114 /* If frag has yet to be reached on this pass, assume it will
19115 move by STRETCH just as we did. If this is not so, it will
19116 be because some frag between grows, and that will force
19120 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
19124 /* Adjust stretch for any alignment frag. Note that if have
19125 been expanding the earlier code, the symbol may be
19126 defined in what appears to be an earlier frag. FIXME:
19127 This doesn't handle the fr_subtype field, which specifies
19128 a maximum number of bytes to skip when doing an
19130 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
19132 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
19135 stretch
= - ((- stretch
)
19136 & ~ ((1 << (int) f
->fr_offset
) - 1));
19138 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
19150 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19153 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
19158 /* Assume worst case for symbols not known to be in the same section. */
19159 if (fragp
->fr_symbol
== NULL
19160 || !S_IS_DEFINED (fragp
->fr_symbol
)
19161 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19162 || S_IS_WEAK (fragp
->fr_symbol
))
19165 val
= relaxed_symbol_addr (fragp
, stretch
);
19166 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
19167 addr
= (addr
+ 4) & ~3;
19168 /* Force misaligned targets to 32-bit variant. */
19172 if (val
< 0 || val
> 1020)
19177 /* Return the size of a relaxable add/sub immediate instruction. */
19179 relax_addsub (fragS
*fragp
, asection
*sec
)
19184 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19185 op
= bfd_get_16(sec
->owner
, buf
);
19186 if ((op
& 0xf) == ((op
>> 4) & 0xf))
19187 return relax_immediate (fragp
, 8, 0);
19189 return relax_immediate (fragp
, 3, 0);
19193 /* Return the size of a relaxable branch instruction. BITS is the
19194 size of the offset field in the narrow instruction. */
19197 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
19203 /* Assume worst case for symbols not known to be in the same section. */
19204 if (!S_IS_DEFINED (fragp
->fr_symbol
)
19205 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19206 || S_IS_WEAK (fragp
->fr_symbol
))
19210 if (S_IS_DEFINED (fragp
->fr_symbol
)
19211 && ARM_IS_FUNC (fragp
->fr_symbol
))
19214 /* PR 12532. Global symbols with default visibility might
19215 be preempted, so do not relax relocations to them. */
19216 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp
->fr_symbol
)) == STV_DEFAULT
)
19217 && (! S_IS_LOCAL (fragp
->fr_symbol
)))
19221 val
= relaxed_symbol_addr (fragp
, stretch
);
19222 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
19225 /* Offset is a signed value *2 */
19227 if (val
>= limit
|| val
< -limit
)
19233 /* Relax a machine dependent frag. This returns the amount by which
19234 the current size of the frag should change. */
19237 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
19242 oldsize
= fragp
->fr_var
;
19243 switch (fragp
->fr_subtype
)
19245 case T_MNEM_ldr_pc2
:
19246 newsize
= relax_adr (fragp
, sec
, stretch
);
19248 case T_MNEM_ldr_pc
:
19249 case T_MNEM_ldr_sp
:
19250 case T_MNEM_str_sp
:
19251 newsize
= relax_immediate (fragp
, 8, 2);
19255 newsize
= relax_immediate (fragp
, 5, 2);
19259 newsize
= relax_immediate (fragp
, 5, 1);
19263 newsize
= relax_immediate (fragp
, 5, 0);
19266 newsize
= relax_adr (fragp
, sec
, stretch
);
19272 newsize
= relax_immediate (fragp
, 8, 0);
19275 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
19278 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
19280 case T_MNEM_add_sp
:
19281 case T_MNEM_add_pc
:
19282 newsize
= relax_immediate (fragp
, 8, 2);
19284 case T_MNEM_inc_sp
:
19285 case T_MNEM_dec_sp
:
19286 newsize
= relax_immediate (fragp
, 7, 2);
19292 newsize
= relax_addsub (fragp
, sec
);
19298 fragp
->fr_var
= newsize
;
19299 /* Freeze wide instructions that are at or before the same location as
19300 in the previous pass. This avoids infinite loops.
19301 Don't freeze them unconditionally because targets may be artificially
19302 misaligned by the expansion of preceding frags. */
19303 if (stretch
<= 0 && newsize
> 2)
19305 md_convert_frag (sec
->owner
, sec
, fragp
);
19309 return newsize
- oldsize
;
19312 /* Round up a section size to the appropriate boundary. */
19315 md_section_align (segT segment ATTRIBUTE_UNUSED
,
19318 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19319 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
19321 /* For a.out, force the section size to be aligned. If we don't do
19322 this, BFD will align it for us, but it will not write out the
19323 final bytes of the section. This may be a bug in BFD, but it is
19324 easier to fix it here since that is how the other a.out targets
19328 align
= bfd_get_section_alignment (stdoutput
, segment
);
19329 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
19336 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19337 of an rs_align_code fragment. */
19340 arm_handle_align (fragS
* fragP
)
19342 static char const arm_noop
[2][2][4] =
19345 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19346 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19349 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19350 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19353 static char const thumb_noop
[2][2][2] =
19356 {0xc0, 0x46}, /* LE */
19357 {0x46, 0xc0}, /* BE */
19360 {0x00, 0xbf}, /* LE */
19361 {0xbf, 0x00} /* BE */
19364 static char const wide_thumb_noop
[2][4] =
19365 { /* Wide Thumb-2 */
19366 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19367 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19370 unsigned bytes
, fix
, noop_size
;
19373 const char *narrow_noop
= NULL
;
19378 if (fragP
->fr_type
!= rs_align_code
)
19381 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
19382 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
19385 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19386 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
19388 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
19390 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
19392 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
19394 narrow_noop
= thumb_noop
[1][target_big_endian
];
19395 noop
= wide_thumb_noop
[target_big_endian
];
19398 noop
= thumb_noop
[0][target_big_endian
];
19406 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
19407 [target_big_endian
];
19414 fragP
->fr_var
= noop_size
;
19416 if (bytes
& (noop_size
- 1))
19418 fix
= bytes
& (noop_size
- 1);
19420 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
19422 memset (p
, 0, fix
);
19429 if (bytes
& noop_size
)
19431 /* Insert a narrow noop. */
19432 memcpy (p
, narrow_noop
, noop_size
);
19434 bytes
-= noop_size
;
19438 /* Use wide noops for the remainder */
19442 while (bytes
>= noop_size
)
19444 memcpy (p
, noop
, noop_size
);
19446 bytes
-= noop_size
;
19450 fragP
->fr_fix
+= fix
;
19453 /* Called from md_do_align. Used to create an alignment
19454 frag in a code section. */
19457 arm_frag_align_code (int n
, int max
)
19461 /* We assume that there will never be a requirement
19462 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19463 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19468 _("alignments greater than %d bytes not supported in .text sections."),
19469 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19470 as_fatal ("%s", err_msg
);
19473 p
= frag_var (rs_align_code
,
19474 MAX_MEM_FOR_RS_ALIGN_CODE
,
19476 (relax_substateT
) max
,
19483 /* Perform target specific initialisation of a frag.
19484 Note - despite the name this initialisation is not done when the frag
19485 is created, but only when its type is assigned. A frag can be created
19486 and used a long time before its type is set, so beware of assuming that
19487 this initialisationis performed first. */
19491 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19493 /* Record whether this frag is in an ARM or a THUMB area. */
19494 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19497 #else /* OBJ_ELF is defined. */
19499 arm_init_frag (fragS
* fragP
, int max_chars
)
19501 /* If the current ARM vs THUMB mode has not already
19502 been recorded into this frag then do so now. */
19503 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19505 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19507 /* Record a mapping symbol for alignment frags. We will delete this
19508 later if the alignment ends up empty. */
19509 switch (fragP
->fr_type
)
19512 case rs_align_test
:
19514 mapping_state_2 (MAP_DATA
, max_chars
);
19516 case rs_align_code
:
19517 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19525 /* When we change sections we need to issue a new mapping symbol. */
19528 arm_elf_change_section (void)
19530 /* Link an unlinked unwind index table section to the .text section. */
19531 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19532 && elf_linked_to_section (now_seg
) == NULL
)
19533 elf_linked_to_section (now_seg
) = text_section
;
19537 arm_elf_section_type (const char * str
, size_t len
)
19539 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19540 return SHT_ARM_EXIDX
;
19545 /* Code to deal with unwinding tables. */
19547 static void add_unwind_adjustsp (offsetT
);
19549 /* Generate any deferred unwind frame offset. */
19552 flush_pending_unwind (void)
19556 offset
= unwind
.pending_offset
;
19557 unwind
.pending_offset
= 0;
19559 add_unwind_adjustsp (offset
);
19562 /* Add an opcode to this list for this function. Two-byte opcodes should
19563 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19567 add_unwind_opcode (valueT op
, int length
)
19569 /* Add any deferred stack adjustment. */
19570 if (unwind
.pending_offset
)
19571 flush_pending_unwind ();
19573 unwind
.sp_restored
= 0;
19575 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19577 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19578 if (unwind
.opcodes
)
19579 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19580 unwind
.opcode_alloc
);
19582 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19587 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19589 unwind
.opcode_count
++;
19593 /* Add unwind opcodes to adjust the stack pointer. */
19596 add_unwind_adjustsp (offsetT offset
)
19600 if (offset
> 0x200)
19602 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19607 /* Long form: 0xb2, uleb128. */
19608 /* This might not fit in a word so add the individual bytes,
19609 remembering the list is built in reverse order. */
19610 o
= (valueT
) ((offset
- 0x204) >> 2);
19612 add_unwind_opcode (0, 1);
19614 /* Calculate the uleb128 encoding of the offset. */
19618 bytes
[n
] = o
& 0x7f;
19624 /* Add the insn. */
19626 add_unwind_opcode (bytes
[n
- 1], 1);
19627 add_unwind_opcode (0xb2, 1);
19629 else if (offset
> 0x100)
19631 /* Two short opcodes. */
19632 add_unwind_opcode (0x3f, 1);
19633 op
= (offset
- 0x104) >> 2;
19634 add_unwind_opcode (op
, 1);
19636 else if (offset
> 0)
19638 /* Short opcode. */
19639 op
= (offset
- 4) >> 2;
19640 add_unwind_opcode (op
, 1);
19642 else if (offset
< 0)
19645 while (offset
> 0x100)
19647 add_unwind_opcode (0x7f, 1);
19650 op
= ((offset
- 4) >> 2) | 0x40;
19651 add_unwind_opcode (op
, 1);
19655 /* Finish the list of unwind opcodes for this function. */
19657 finish_unwind_opcodes (void)
19661 if (unwind
.fp_used
)
19663 /* Adjust sp as necessary. */
19664 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19665 flush_pending_unwind ();
19667 /* After restoring sp from the frame pointer. */
19668 op
= 0x90 | unwind
.fp_reg
;
19669 add_unwind_opcode (op
, 1);
19672 flush_pending_unwind ();
19676 /* Start an exception table entry. If idx is nonzero this is an index table
19680 start_unwind_section (const segT text_seg
, int idx
)
19682 const char * text_name
;
19683 const char * prefix
;
19684 const char * prefix_once
;
19685 const char * group_name
;
19689 size_t sec_name_len
;
19696 prefix
= ELF_STRING_ARM_unwind
;
19697 prefix_once
= ELF_STRING_ARM_unwind_once
;
19698 type
= SHT_ARM_EXIDX
;
19702 prefix
= ELF_STRING_ARM_unwind_info
;
19703 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19704 type
= SHT_PROGBITS
;
19707 text_name
= segment_name (text_seg
);
19708 if (streq (text_name
, ".text"))
19711 if (strncmp (text_name
, ".gnu.linkonce.t.",
19712 strlen (".gnu.linkonce.t.")) == 0)
19714 prefix
= prefix_once
;
19715 text_name
+= strlen (".gnu.linkonce.t.");
19718 prefix_len
= strlen (prefix
);
19719 text_len
= strlen (text_name
);
19720 sec_name_len
= prefix_len
+ text_len
;
19721 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19722 memcpy (sec_name
, prefix
, prefix_len
);
19723 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19724 sec_name
[prefix_len
+ text_len
] = '\0';
19730 /* Handle COMDAT group. */
19731 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19733 group_name
= elf_group_name (text_seg
);
19734 if (group_name
== NULL
)
19736 as_bad (_("Group section `%s' has no group signature"),
19737 segment_name (text_seg
));
19738 ignore_rest_of_line ();
19741 flags
|= SHF_GROUP
;
19745 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19747 /* Set the section link for index tables. */
19749 elf_linked_to_section (now_seg
) = text_seg
;
19753 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19754 personality routine data. Returns zero, or the index table value for
19755 and inline entry. */
19758 create_unwind_entry (int have_data
)
19763 /* The current word of data. */
19765 /* The number of bytes left in this word. */
19768 finish_unwind_opcodes ();
19770 /* Remember the current text section. */
19771 unwind
.saved_seg
= now_seg
;
19772 unwind
.saved_subseg
= now_subseg
;
19774 start_unwind_section (now_seg
, 0);
19776 if (unwind
.personality_routine
== NULL
)
19778 if (unwind
.personality_index
== -2)
19781 as_bad (_("handlerdata in cantunwind frame"));
19782 return 1; /* EXIDX_CANTUNWIND. */
19785 /* Use a default personality routine if none is specified. */
19786 if (unwind
.personality_index
== -1)
19788 if (unwind
.opcode_count
> 3)
19789 unwind
.personality_index
= 1;
19791 unwind
.personality_index
= 0;
19794 /* Space for the personality routine entry. */
19795 if (unwind
.personality_index
== 0)
19797 if (unwind
.opcode_count
> 3)
19798 as_bad (_("too many unwind opcodes for personality routine 0"));
19802 /* All the data is inline in the index table. */
19805 while (unwind
.opcode_count
> 0)
19807 unwind
.opcode_count
--;
19808 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19812 /* Pad with "finish" opcodes. */
19814 data
= (data
<< 8) | 0xb0;
19821 /* We get two opcodes "free" in the first word. */
19822 size
= unwind
.opcode_count
- 2;
19825 /* An extra byte is required for the opcode count. */
19826 size
= unwind
.opcode_count
+ 1;
19828 size
= (size
+ 3) >> 2;
19830 as_bad (_("too many unwind opcodes"));
19832 frag_align (2, 0, 0);
19833 record_alignment (now_seg
, 2);
19834 unwind
.table_entry
= expr_build_dot ();
19836 /* Allocate the table entry. */
19837 ptr
= frag_more ((size
<< 2) + 4);
19838 where
= frag_now_fix () - ((size
<< 2) + 4);
19840 switch (unwind
.personality_index
)
19843 /* ??? Should this be a PLT generating relocation? */
19844 /* Custom personality routine. */
19845 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19846 BFD_RELOC_ARM_PREL31
);
19851 /* Set the first byte to the number of additional words. */
19856 /* ABI defined personality routines. */
19858 /* Three opcodes bytes are packed into the first word. */
19865 /* The size and first two opcode bytes go in the first word. */
19866 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19871 /* Should never happen. */
19875 /* Pack the opcodes into words (MSB first), reversing the list at the same
19877 while (unwind
.opcode_count
> 0)
19881 md_number_to_chars (ptr
, data
, 4);
19886 unwind
.opcode_count
--;
19888 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19891 /* Finish off the last word. */
19894 /* Pad with "finish" opcodes. */
19896 data
= (data
<< 8) | 0xb0;
19898 md_number_to_chars (ptr
, data
, 4);
19903 /* Add an empty descriptor if there is no user-specified data. */
19904 ptr
= frag_more (4);
19905 md_number_to_chars (ptr
, 0, 4);
19912 /* Initialize the DWARF-2 unwind information for this procedure. */
19915 tc_arm_frame_initial_instructions (void)
19917 cfi_add_CFA_def_cfa (REG_SP
, 0);
19919 #endif /* OBJ_ELF */
19921 /* Convert REGNAME to a DWARF-2 register number. */
19924 tc_arm_regname_to_dw2regnum (char *regname
)
19926 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19936 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19940 exp
.X_op
= O_secrel
;
19941 exp
.X_add_symbol
= symbol
;
19942 exp
.X_add_number
= 0;
19943 emit_expr (&exp
, size
);
19947 /* MD interface: Symbol and relocation handling. */
19949 /* Return the address within the segment that a PC-relative fixup is
19950 relative to. For ARM, PC-relative fixups applied to instructions
19951 are generally relative to the location of the fixup plus 8 bytes.
19952 Thumb branches are offset by 4, and Thumb loads relative to PC
19953 require special handling. */
19956 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19958 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19960 /* If this is pc-relative and we are going to emit a relocation
19961 then we just want to put out any pipeline compensation that the linker
19962 will need. Otherwise we want to use the calculated base.
19963 For WinCE we skip the bias for externals as well, since this
19964 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19966 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19967 || (arm_force_relocation (fixP
)
19969 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19975 switch (fixP
->fx_r_type
)
19977 /* PC relative addressing on the Thumb is slightly odd as the
19978 bottom two bits of the PC are forced to zero for the
19979 calculation. This happens *after* application of the
19980 pipeline offset. However, Thumb adrl already adjusts for
19981 this, so we need not do it again. */
19982 case BFD_RELOC_ARM_THUMB_ADD
:
19985 case BFD_RELOC_ARM_THUMB_OFFSET
:
19986 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19987 case BFD_RELOC_ARM_T32_ADD_PC12
:
19988 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19989 return (base
+ 4) & ~3;
19991 /* Thumb branches are simply offset by +4. */
19992 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19993 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19994 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19995 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19996 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19999 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20001 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20002 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20003 && ARM_IS_FUNC (fixP
->fx_addsy
)
20004 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20005 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20008 /* BLX is like branches above, but forces the low two bits of PC to
20010 case BFD_RELOC_THUMB_PCREL_BLX
:
20012 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20013 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20014 && THUMB_IS_FUNC (fixP
->fx_addsy
)
20015 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20016 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20017 return (base
+ 4) & ~3;
20019 /* ARM mode branches are offset by +8. However, the Windows CE
20020 loader expects the relocation not to take this into account. */
20021 case BFD_RELOC_ARM_PCREL_BLX
:
20023 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20024 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20025 && ARM_IS_FUNC (fixP
->fx_addsy
)
20026 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20027 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20030 case BFD_RELOC_ARM_PCREL_CALL
:
20032 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20033 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20034 && THUMB_IS_FUNC (fixP
->fx_addsy
)
20035 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20036 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20039 case BFD_RELOC_ARM_PCREL_BRANCH
:
20040 case BFD_RELOC_ARM_PCREL_JUMP
:
20041 case BFD_RELOC_ARM_PLT32
:
20043 /* When handling fixups immediately, because we have already
20044 discovered the value of a symbol, or the address of the frag involved
20045 we must account for the offset by +8, as the OS loader will never see the reloc.
20046 see fixup_segment() in write.c
20047 The S_IS_EXTERNAL test handles the case of global symbols.
20048 Those need the calculated base, not just the pipe compensation the linker will need. */
20050 && fixP
->fx_addsy
!= NULL
20051 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20052 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
20060 /* ARM mode loads relative to PC are also offset by +8. Unlike
20061 branches, the Windows CE loader *does* expect the relocation
20062 to take this into account. */
20063 case BFD_RELOC_ARM_OFFSET_IMM
:
20064 case BFD_RELOC_ARM_OFFSET_IMM8
:
20065 case BFD_RELOC_ARM_HWLITERAL
:
20066 case BFD_RELOC_ARM_LITERAL
:
20067 case BFD_RELOC_ARM_CP_OFF_IMM
:
20071 /* Other PC-relative relocations are un-offset. */
20077 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20078 Otherwise we have no need to default values of symbols. */
20081 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
20084 if (name
[0] == '_' && name
[1] == 'G'
20085 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
20089 if (symbol_find (name
))
20090 as_bad (_("GOT already in the symbol table"));
20092 GOT_symbol
= symbol_new (name
, undefined_section
,
20093 (valueT
) 0, & zero_address_frag
);
20103 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20104 computed as two separate immediate values, added together. We
20105 already know that this value cannot be computed by just one ARM
20108 static unsigned int
20109 validate_immediate_twopart (unsigned int val
,
20110 unsigned int * highpart
)
20115 for (i
= 0; i
< 32; i
+= 2)
20116 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
20122 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
20124 else if (a
& 0xff0000)
20126 if (a
& 0xff000000)
20128 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
20132 gas_assert (a
& 0xff000000);
20133 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
20136 return (a
& 0xff) | (i
<< 7);
20143 validate_offset_imm (unsigned int val
, int hwse
)
20145 if ((hwse
&& val
> 255) || val
> 4095)
20150 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20151 negative immediate constant by altering the instruction. A bit of
20156 by inverting the second operand, and
20159 by negating the second operand. */
20162 negate_data_op (unsigned long * instruction
,
20163 unsigned long value
)
20166 unsigned long negated
, inverted
;
20168 negated
= encode_arm_immediate (-value
);
20169 inverted
= encode_arm_immediate (~value
);
20171 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
20174 /* First negates. */
20175 case OPCODE_SUB
: /* ADD <-> SUB */
20176 new_inst
= OPCODE_ADD
;
20181 new_inst
= OPCODE_SUB
;
20185 case OPCODE_CMP
: /* CMP <-> CMN */
20186 new_inst
= OPCODE_CMN
;
20191 new_inst
= OPCODE_CMP
;
20195 /* Now Inverted ops. */
20196 case OPCODE_MOV
: /* MOV <-> MVN */
20197 new_inst
= OPCODE_MVN
;
20202 new_inst
= OPCODE_MOV
;
20206 case OPCODE_AND
: /* AND <-> BIC */
20207 new_inst
= OPCODE_BIC
;
20212 new_inst
= OPCODE_AND
;
20216 case OPCODE_ADC
: /* ADC <-> SBC */
20217 new_inst
= OPCODE_SBC
;
20222 new_inst
= OPCODE_ADC
;
20226 /* We cannot do anything. */
20231 if (value
== (unsigned) FAIL
)
20234 *instruction
&= OPCODE_MASK
;
20235 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
20239 /* Like negate_data_op, but for Thumb-2. */
20241 static unsigned int
20242 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
20246 unsigned int negated
, inverted
;
20248 negated
= encode_thumb32_immediate (-value
);
20249 inverted
= encode_thumb32_immediate (~value
);
20251 rd
= (*instruction
>> 8) & 0xf;
20252 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
20255 /* ADD <-> SUB. Includes CMP <-> CMN. */
20256 case T2_OPCODE_SUB
:
20257 new_inst
= T2_OPCODE_ADD
;
20261 case T2_OPCODE_ADD
:
20262 new_inst
= T2_OPCODE_SUB
;
20266 /* ORR <-> ORN. Includes MOV <-> MVN. */
20267 case T2_OPCODE_ORR
:
20268 new_inst
= T2_OPCODE_ORN
;
20272 case T2_OPCODE_ORN
:
20273 new_inst
= T2_OPCODE_ORR
;
20277 /* AND <-> BIC. TST has no inverted equivalent. */
20278 case T2_OPCODE_AND
:
20279 new_inst
= T2_OPCODE_BIC
;
20286 case T2_OPCODE_BIC
:
20287 new_inst
= T2_OPCODE_AND
;
20292 case T2_OPCODE_ADC
:
20293 new_inst
= T2_OPCODE_SBC
;
20297 case T2_OPCODE_SBC
:
20298 new_inst
= T2_OPCODE_ADC
;
20302 /* We cannot do anything. */
20307 if (value
== (unsigned int)FAIL
)
20310 *instruction
&= T2_OPCODE_MASK
;
20311 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
20315 /* Read a 32-bit thumb instruction from buf. */
20316 static unsigned long
20317 get_thumb32_insn (char * buf
)
20319 unsigned long insn
;
20320 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
20321 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20327 /* We usually want to set the low bit on the address of thumb function
20328 symbols. In particular .word foo - . should have the low bit set.
20329 Generic code tries to fold the difference of two symbols to
20330 a constant. Prevent this and force a relocation when the first symbols
20331 is a thumb function. */
20334 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
20336 if (op
== O_subtract
20337 && l
->X_op
== O_symbol
20338 && r
->X_op
== O_symbol
20339 && THUMB_IS_FUNC (l
->X_add_symbol
))
20341 l
->X_op
= O_subtract
;
20342 l
->X_op_symbol
= r
->X_add_symbol
;
20343 l
->X_add_number
-= r
->X_add_number
;
20347 /* Process as normal. */
20351 /* Encode Thumb2 unconditional branches and calls. The encoding
20352 for the 2 are identical for the immediate values. */
20355 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
20357 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20360 addressT S
, I1
, I2
, lo
, hi
;
20362 S
= (value
>> 24) & 0x01;
20363 I1
= (value
>> 23) & 0x01;
20364 I2
= (value
>> 22) & 0x01;
20365 hi
= (value
>> 12) & 0x3ff;
20366 lo
= (value
>> 1) & 0x7ff;
20367 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20368 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20369 newval
|= (S
<< 10) | hi
;
20370 newval2
&= ~T2I1I2MASK
;
20371 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
20372 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20373 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20377 md_apply_fix (fixS
* fixP
,
20381 offsetT value
= * valP
;
20383 unsigned int newimm
;
20384 unsigned long temp
;
20386 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
20388 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
20390 /* Note whether this will delete the relocation. */
20392 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
20395 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20396 consistency with the behaviour on 32-bit hosts. Remember value
20398 value
&= 0xffffffff;
20399 value
^= 0x80000000;
20400 value
-= 0x80000000;
20403 fixP
->fx_addnumber
= value
;
20405 /* Same treatment for fixP->fx_offset. */
20406 fixP
->fx_offset
&= 0xffffffff;
20407 fixP
->fx_offset
^= 0x80000000;
20408 fixP
->fx_offset
-= 0x80000000;
20410 switch (fixP
->fx_r_type
)
20412 case BFD_RELOC_NONE
:
20413 /* This will need to go in the object file. */
20417 case BFD_RELOC_ARM_IMMEDIATE
:
20418 /* We claim that this fixup has been processed here,
20419 even if in fact we generate an error because we do
20420 not have a reloc for it, so tc_gen_reloc will reject it. */
20423 if (fixP
->fx_addsy
)
20425 const char *msg
= 0;
20427 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20428 msg
= _("undefined symbol %s used as an immediate value");
20429 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20430 msg
= _("symbol %s is in a different section");
20431 else if (S_IS_WEAK (fixP
->fx_addsy
))
20432 msg
= _("symbol %s is weak and may be overridden later");
20436 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20437 msg
, S_GET_NAME (fixP
->fx_addsy
));
20442 newimm
= encode_arm_immediate (value
);
20443 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20445 /* If the instruction will fail, see if we can fix things up by
20446 changing the opcode. */
20447 if (newimm
== (unsigned int) FAIL
20448 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
20450 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20451 _("invalid constant (%lx) after fixup"),
20452 (unsigned long) value
);
20456 newimm
|= (temp
& 0xfffff000);
20457 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20460 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20462 unsigned int highpart
= 0;
20463 unsigned int newinsn
= 0xe1a00000; /* nop. */
20465 if (fixP
->fx_addsy
)
20467 const char *msg
= 0;
20469 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20470 msg
= _("undefined symbol %s used as an immediate value");
20471 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20472 msg
= _("symbol %s is in a different section");
20473 else if (S_IS_WEAK (fixP
->fx_addsy
))
20474 msg
= _("symbol %s is weak and may be overridden later");
20478 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20479 msg
, S_GET_NAME (fixP
->fx_addsy
));
20484 newimm
= encode_arm_immediate (value
);
20485 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20487 /* If the instruction will fail, see if we can fix things up by
20488 changing the opcode. */
20489 if (newimm
== (unsigned int) FAIL
20490 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20492 /* No ? OK - try using two ADD instructions to generate
20494 newimm
= validate_immediate_twopart (value
, & highpart
);
20496 /* Yes - then make sure that the second instruction is
20498 if (newimm
!= (unsigned int) FAIL
)
20500 /* Still No ? Try using a negated value. */
20501 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20502 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20503 /* Otherwise - give up. */
20506 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20507 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20512 /* Replace the first operand in the 2nd instruction (which
20513 is the PC) with the destination register. We have
20514 already added in the PC in the first instruction and we
20515 do not want to do it again. */
20516 newinsn
&= ~ 0xf0000;
20517 newinsn
|= ((newinsn
& 0x0f000) << 4);
20520 newimm
|= (temp
& 0xfffff000);
20521 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20523 highpart
|= (newinsn
& 0xfffff000);
20524 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20528 case BFD_RELOC_ARM_OFFSET_IMM
:
20529 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20532 case BFD_RELOC_ARM_LITERAL
:
20538 if (validate_offset_imm (value
, 0) == FAIL
)
20540 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20542 _("invalid literal constant: pool needs to be closer"));
20544 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20545 _("bad immediate value for offset (%ld)"),
20550 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20552 newval
&= 0xfffff000;
20555 newval
&= 0xff7ff000;
20556 newval
|= value
| (sign
? INDEX_UP
: 0);
20558 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20561 case BFD_RELOC_ARM_OFFSET_IMM8
:
20562 case BFD_RELOC_ARM_HWLITERAL
:
20568 if (validate_offset_imm (value
, 1) == FAIL
)
20570 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20572 _("invalid literal constant: pool needs to be closer"));
20574 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20579 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20581 newval
&= 0xfffff0f0;
20584 newval
&= 0xff7ff0f0;
20585 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20587 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20590 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20591 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20593 _("bad immediate value for offset (%ld)"), (long) value
);
20596 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20598 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20601 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20602 /* This is a complicated relocation used for all varieties of Thumb32
20603 load/store instruction with immediate offset:
20605 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20606 *4, optional writeback(W)
20607 (doubleword load/store)
20609 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20610 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20611 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20612 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20613 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20615 Uppercase letters indicate bits that are already encoded at
20616 this point. Lowercase letters are our problem. For the
20617 second block of instructions, the secondary opcode nybble
20618 (bits 8..11) is present, and bit 23 is zero, even if this is
20619 a PC-relative operation. */
20620 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20622 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20624 if ((newval
& 0xf0000000) == 0xe0000000)
20626 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20628 newval
|= (1 << 23);
20631 if (value
% 4 != 0)
20633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20634 _("offset not a multiple of 4"));
20640 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20641 _("offset out of range"));
20646 else if ((newval
& 0x000f0000) == 0x000f0000)
20648 /* PC-relative, 12-bit offset. */
20650 newval
|= (1 << 23);
20655 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20656 _("offset out of range"));
20661 else if ((newval
& 0x00000100) == 0x00000100)
20663 /* Writeback: 8-bit, +/- offset. */
20665 newval
|= (1 << 9);
20670 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20671 _("offset out of range"));
20676 else if ((newval
& 0x00000f00) == 0x00000e00)
20678 /* T-instruction: positive 8-bit offset. */
20679 if (value
< 0 || value
> 0xff)
20681 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20682 _("offset out of range"));
20690 /* Positive 12-bit or negative 8-bit offset. */
20694 newval
|= (1 << 23);
20704 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20705 _("offset out of range"));
20712 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20713 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20716 case BFD_RELOC_ARM_SHIFT_IMM
:
20717 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20718 if (((unsigned long) value
) > 32
20720 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20723 _("shift expression is too large"));
20728 /* Shifts of zero must be done as lsl. */
20730 else if (value
== 32)
20732 newval
&= 0xfffff07f;
20733 newval
|= (value
& 0x1f) << 7;
20734 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20737 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20738 case BFD_RELOC_ARM_T32_ADD_IMM
:
20739 case BFD_RELOC_ARM_T32_IMM12
:
20740 case BFD_RELOC_ARM_T32_ADD_PC12
:
20741 /* We claim that this fixup has been processed here,
20742 even if in fact we generate an error because we do
20743 not have a reloc for it, so tc_gen_reloc will reject it. */
20747 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20749 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20750 _("undefined symbol %s used as an immediate value"),
20751 S_GET_NAME (fixP
->fx_addsy
));
20755 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20757 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20760 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20761 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20763 newimm
= encode_thumb32_immediate (value
);
20764 if (newimm
== (unsigned int) FAIL
)
20765 newimm
= thumb32_negate_data_op (&newval
, value
);
20767 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20768 && newimm
== (unsigned int) FAIL
)
20770 /* Turn add/sum into addw/subw. */
20771 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20772 newval
= (newval
& 0xfeffffff) | 0x02000000;
20773 /* No flat 12-bit imm encoding for addsw/subsw. */
20774 if ((newval
& 0x00100000) == 0)
20776 /* 12 bit immediate for addw/subw. */
20780 newval
^= 0x00a00000;
20783 newimm
= (unsigned int) FAIL
;
20789 if (newimm
== (unsigned int)FAIL
)
20791 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20792 _("invalid constant (%lx) after fixup"),
20793 (unsigned long) value
);
20797 newval
|= (newimm
& 0x800) << 15;
20798 newval
|= (newimm
& 0x700) << 4;
20799 newval
|= (newimm
& 0x0ff);
20801 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20802 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20805 case BFD_RELOC_ARM_SMC
:
20806 if (((unsigned long) value
) > 0xffff)
20807 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20808 _("invalid smc expression"));
20809 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20810 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20811 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20814 case BFD_RELOC_ARM_HVC
:
20815 if (((unsigned long) value
) > 0xffff)
20816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20817 _("invalid hvc expression"));
20818 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20819 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20820 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20823 case BFD_RELOC_ARM_SWI
:
20824 if (fixP
->tc_fix_data
!= 0)
20826 if (((unsigned long) value
) > 0xff)
20827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20828 _("invalid swi expression"));
20829 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20831 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20835 if (((unsigned long) value
) > 0x00ffffff)
20836 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20837 _("invalid swi expression"));
20838 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20840 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20844 case BFD_RELOC_ARM_MULTI
:
20845 if (((unsigned long) value
) > 0xffff)
20846 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20847 _("invalid expression in load/store multiple"));
20848 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20849 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20853 case BFD_RELOC_ARM_PCREL_CALL
:
20855 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20857 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20858 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20859 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20860 /* Flip the bl to blx. This is a simple flip
20861 bit here because we generate PCREL_CALL for
20862 unconditional bls. */
20864 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20865 newval
= newval
| 0x10000000;
20866 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20872 goto arm_branch_common
;
20874 case BFD_RELOC_ARM_PCREL_JUMP
:
20875 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20877 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20878 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20879 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20881 /* This would map to a bl<cond>, b<cond>,
20882 b<always> to a Thumb function. We
20883 need to force a relocation for this particular
20885 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20889 case BFD_RELOC_ARM_PLT32
:
20891 case BFD_RELOC_ARM_PCREL_BRANCH
:
20893 goto arm_branch_common
;
20895 case BFD_RELOC_ARM_PCREL_BLX
:
20898 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20900 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20901 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20902 && ARM_IS_FUNC (fixP
->fx_addsy
))
20904 /* Flip the blx to a bl and warn. */
20905 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20906 newval
= 0xeb000000;
20907 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20908 _("blx to '%s' an ARM ISA state function changed to bl"),
20910 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20916 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20917 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20921 /* We are going to store value (shifted right by two) in the
20922 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20923 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20924 also be be clear. */
20926 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20927 _("misaligned branch destination"));
20928 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20929 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20930 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20931 _("branch out of range"));
20933 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20935 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20936 newval
|= (value
>> 2) & 0x00ffffff;
20937 /* Set the H bit on BLX instructions. */
20941 newval
|= 0x01000000;
20943 newval
&= ~0x01000000;
20945 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20949 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20950 /* CBZ can only branch forward. */
20952 /* Attempts to use CBZ to branch to the next instruction
20953 (which, strictly speaking, are prohibited) will be turned into
20956 FIXME: It may be better to remove the instruction completely and
20957 perform relaxation. */
20960 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20961 newval
= 0xbf00; /* NOP encoding T1 */
20962 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20967 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20968 _("branch out of range"));
20970 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20972 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20973 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20974 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20979 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20980 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20981 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20982 _("branch out of range"));
20984 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20986 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20987 newval
|= (value
& 0x1ff) >> 1;
20988 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20992 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20993 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20994 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20995 _("branch out of range"));
20997 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20999 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21000 newval
|= (value
& 0xfff) >> 1;
21001 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21005 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21007 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21008 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21009 && ARM_IS_FUNC (fixP
->fx_addsy
)
21010 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21012 /* Force a relocation for a branch 20 bits wide. */
21015 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
21016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21017 _("conditional branch out of range"));
21019 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21022 addressT S
, J1
, J2
, lo
, hi
;
21024 S
= (value
& 0x00100000) >> 20;
21025 J2
= (value
& 0x00080000) >> 19;
21026 J1
= (value
& 0x00040000) >> 18;
21027 hi
= (value
& 0x0003f000) >> 12;
21028 lo
= (value
& 0x00000ffe) >> 1;
21030 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21031 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21032 newval
|= (S
<< 10) | hi
;
21033 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
21034 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21035 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
21039 case BFD_RELOC_THUMB_PCREL_BLX
:
21041 /* If there is a blx from a thumb state function to
21042 another thumb function flip this to a bl and warn
21046 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21047 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21048 && THUMB_IS_FUNC (fixP
->fx_addsy
))
21050 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
21051 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
21052 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21054 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21055 newval
= newval
| 0x1000;
21056 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
21057 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21062 goto thumb_bl_common
;
21064 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21066 /* A bl from Thumb state ISA to an internal ARM state function
21067 is converted to a blx. */
21069 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21070 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21071 && ARM_IS_FUNC (fixP
->fx_addsy
)
21072 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21074 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21075 newval
= newval
& ~0x1000;
21076 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
21077 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
21084 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
21085 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
21086 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21089 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
21090 /* For a BLX instruction, make sure that the relocation is rounded up
21091 to a word boundary. This follows the semantics of the instruction
21092 which specifies that bit 1 of the target address will come from bit
21093 1 of the base address. */
21094 value
= (value
+ 1) & ~ 1;
21097 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
21099 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
21101 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21102 _("branch out of range"));
21104 else if ((value
& ~0x1ffffff)
21105 && ((value
& ~0x1ffffff) != ~0x1ffffff))
21107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21108 _("Thumb2 branch out of range"));
21112 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21113 encode_thumb2_b_bl_offset (buf
, value
);
21117 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21118 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
21119 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21120 _("branch out of range"));
21122 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21123 encode_thumb2_b_bl_offset (buf
, value
);
21128 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21129 md_number_to_chars (buf
, value
, 1);
21133 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21134 md_number_to_chars (buf
, value
, 2);
21138 case BFD_RELOC_ARM_TLS_CALL
:
21139 case BFD_RELOC_ARM_THM_TLS_CALL
:
21140 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21141 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21142 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21145 case BFD_RELOC_ARM_TLS_GOTDESC
:
21146 case BFD_RELOC_ARM_TLS_GD32
:
21147 case BFD_RELOC_ARM_TLS_LE32
:
21148 case BFD_RELOC_ARM_TLS_IE32
:
21149 case BFD_RELOC_ARM_TLS_LDM32
:
21150 case BFD_RELOC_ARM_TLS_LDO32
:
21151 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21154 case BFD_RELOC_ARM_GOT32
:
21155 case BFD_RELOC_ARM_GOTOFF
:
21156 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21157 md_number_to_chars (buf
, 0, 4);
21160 case BFD_RELOC_ARM_GOT_PREL
:
21161 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21162 md_number_to_chars (buf
, value
, 4);
21165 case BFD_RELOC_ARM_TARGET2
:
21166 /* TARGET2 is not partial-inplace, so we need to write the
21167 addend here for REL targets, because it won't be written out
21168 during reloc processing later. */
21169 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21170 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
21174 case BFD_RELOC_RVA
:
21176 case BFD_RELOC_ARM_TARGET1
:
21177 case BFD_RELOC_ARM_ROSEGREL32
:
21178 case BFD_RELOC_ARM_SBREL32
:
21179 case BFD_RELOC_32_PCREL
:
21181 case BFD_RELOC_32_SECREL
:
21183 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21185 /* For WinCE we only do this for pcrel fixups. */
21186 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
21188 md_number_to_chars (buf
, value
, 4);
21192 case BFD_RELOC_ARM_PREL31
:
21193 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21195 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
21196 if ((value
^ (value
>> 1)) & 0x40000000)
21198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21199 _("rel31 relocation overflow"));
21201 newval
|= value
& 0x7fffffff;
21202 md_number_to_chars (buf
, newval
, 4);
21207 case BFD_RELOC_ARM_CP_OFF_IMM
:
21208 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21209 if (value
< -1023 || value
> 1023 || (value
& 3))
21210 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21211 _("co-processor offset out of range"));
21216 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21217 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21218 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21220 newval
= get_thumb32_insn (buf
);
21222 newval
&= 0xffffff00;
21225 newval
&= 0xff7fff00;
21226 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
21228 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21229 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21230 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21232 put_thumb32_insn (buf
, newval
);
21235 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
21236 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
21237 if (value
< -255 || value
> 255)
21238 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21239 _("co-processor offset out of range"));
21241 goto cp_off_common
;
21243 case BFD_RELOC_ARM_THUMB_OFFSET
:
21244 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21245 /* Exactly what ranges, and where the offset is inserted depends
21246 on the type of instruction, we can establish this from the
21248 switch (newval
>> 12)
21250 case 4: /* PC load. */
21251 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21252 forced to zero for these loads; md_pcrel_from has already
21253 compensated for this. */
21255 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21256 _("invalid offset, target not word aligned (0x%08lX)"),
21257 (((unsigned long) fixP
->fx_frag
->fr_address
21258 + (unsigned long) fixP
->fx_where
) & ~3)
21259 + (unsigned long) value
);
21261 if (value
& ~0x3fc)
21262 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21263 _("invalid offset, value too big (0x%08lX)"),
21266 newval
|= value
>> 2;
21269 case 9: /* SP load/store. */
21270 if (value
& ~0x3fc)
21271 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21272 _("invalid offset, value too big (0x%08lX)"),
21274 newval
|= value
>> 2;
21277 case 6: /* Word load/store. */
21279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21280 _("invalid offset, value too big (0x%08lX)"),
21282 newval
|= value
<< 4; /* 6 - 2. */
21285 case 7: /* Byte load/store. */
21287 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21288 _("invalid offset, value too big (0x%08lX)"),
21290 newval
|= value
<< 6;
21293 case 8: /* Halfword load/store. */
21295 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21296 _("invalid offset, value too big (0x%08lX)"),
21298 newval
|= value
<< 5; /* 6 - 1. */
21302 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21303 "Unable to process relocation for thumb opcode: %lx",
21304 (unsigned long) newval
);
21307 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21310 case BFD_RELOC_ARM_THUMB_ADD
:
21311 /* This is a complicated relocation, since we use it for all of
21312 the following immediate relocations:
21316 9bit ADD/SUB SP word-aligned
21317 10bit ADD PC/SP word-aligned
21319 The type of instruction being processed is encoded in the
21326 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21328 int rd
= (newval
>> 4) & 0xf;
21329 int rs
= newval
& 0xf;
21330 int subtract
= !!(newval
& 0x8000);
21332 /* Check for HI regs, only very restricted cases allowed:
21333 Adjusting SP, and using PC or SP to get an address. */
21334 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
21335 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
21336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21337 _("invalid Hi register with immediate"));
21339 /* If value is negative, choose the opposite instruction. */
21343 subtract
= !subtract
;
21345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21346 _("immediate value out of range"));
21351 if (value
& ~0x1fc)
21352 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21353 _("invalid immediate for stack address calculation"));
21354 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
21355 newval
|= value
>> 2;
21357 else if (rs
== REG_PC
|| rs
== REG_SP
)
21359 if (subtract
|| value
& ~0x3fc)
21360 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21361 _("invalid immediate for address calculation (value = 0x%08lX)"),
21362 (unsigned long) value
);
21363 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
21365 newval
|= value
>> 2;
21370 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21371 _("immediate value out of range"));
21372 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
21373 newval
|= (rd
<< 8) | value
;
21378 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21379 _("immediate value out of range"));
21380 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
21381 newval
|= rd
| (rs
<< 3) | (value
<< 6);
21384 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21387 case BFD_RELOC_ARM_THUMB_IMM
:
21388 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21389 if (value
< 0 || value
> 255)
21390 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21391 _("invalid immediate: %ld is out of range"),
21394 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21397 case BFD_RELOC_ARM_THUMB_SHIFT
:
21398 /* 5bit shift value (0..32). LSL cannot take 32. */
21399 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
21400 temp
= newval
& 0xf800;
21401 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
21402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21403 _("invalid shift value: %ld"), (long) value
);
21404 /* Shifts of zero must be encoded as LSL. */
21406 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
21407 /* Shifts of 32 are encoded as zero. */
21408 else if (value
== 32)
21410 newval
|= value
<< 6;
21411 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21414 case BFD_RELOC_VTABLE_INHERIT
:
21415 case BFD_RELOC_VTABLE_ENTRY
:
21419 case BFD_RELOC_ARM_MOVW
:
21420 case BFD_RELOC_ARM_MOVT
:
21421 case BFD_RELOC_ARM_THUMB_MOVW
:
21422 case BFD_RELOC_ARM_THUMB_MOVT
:
21423 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21425 /* REL format relocations are limited to a 16-bit addend. */
21426 if (!fixP
->fx_done
)
21428 if (value
< -0x8000 || value
> 0x7fff)
21429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21430 _("offset out of range"));
21432 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21433 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21438 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21439 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21441 newval
= get_thumb32_insn (buf
);
21442 newval
&= 0xfbf08f00;
21443 newval
|= (value
& 0xf000) << 4;
21444 newval
|= (value
& 0x0800) << 15;
21445 newval
|= (value
& 0x0700) << 4;
21446 newval
|= (value
& 0x00ff);
21447 put_thumb32_insn (buf
, newval
);
21451 newval
= md_chars_to_number (buf
, 4);
21452 newval
&= 0xfff0f000;
21453 newval
|= value
& 0x0fff;
21454 newval
|= (value
& 0xf000) << 4;
21455 md_number_to_chars (buf
, newval
, 4);
21460 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21461 case BFD_RELOC_ARM_ALU_PC_G0
:
21462 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21463 case BFD_RELOC_ARM_ALU_PC_G1
:
21464 case BFD_RELOC_ARM_ALU_PC_G2
:
21465 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21466 case BFD_RELOC_ARM_ALU_SB_G0
:
21467 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21468 case BFD_RELOC_ARM_ALU_SB_G1
:
21469 case BFD_RELOC_ARM_ALU_SB_G2
:
21470 gas_assert (!fixP
->fx_done
);
21471 if (!seg
->use_rela_p
)
21474 bfd_vma encoded_addend
;
21475 bfd_vma addend_abs
= abs (value
);
21477 /* Check that the absolute value of the addend can be
21478 expressed as an 8-bit constant plus a rotation. */
21479 encoded_addend
= encode_arm_immediate (addend_abs
);
21480 if (encoded_addend
== (unsigned int) FAIL
)
21481 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21482 _("the offset 0x%08lX is not representable"),
21483 (unsigned long) addend_abs
);
21485 /* Extract the instruction. */
21486 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21488 /* If the addend is positive, use an ADD instruction.
21489 Otherwise use a SUB. Take care not to destroy the S bit. */
21490 insn
&= 0xff1fffff;
21496 /* Place the encoded addend into the first 12 bits of the
21498 insn
&= 0xfffff000;
21499 insn
|= encoded_addend
;
21501 /* Update the instruction. */
21502 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21506 case BFD_RELOC_ARM_LDR_PC_G0
:
21507 case BFD_RELOC_ARM_LDR_PC_G1
:
21508 case BFD_RELOC_ARM_LDR_PC_G2
:
21509 case BFD_RELOC_ARM_LDR_SB_G0
:
21510 case BFD_RELOC_ARM_LDR_SB_G1
:
21511 case BFD_RELOC_ARM_LDR_SB_G2
:
21512 gas_assert (!fixP
->fx_done
);
21513 if (!seg
->use_rela_p
)
21516 bfd_vma addend_abs
= abs (value
);
21518 /* Check that the absolute value of the addend can be
21519 encoded in 12 bits. */
21520 if (addend_abs
>= 0x1000)
21521 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21522 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21523 (unsigned long) addend_abs
);
21525 /* Extract the instruction. */
21526 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21528 /* If the addend is negative, clear bit 23 of the instruction.
21529 Otherwise set it. */
21531 insn
&= ~(1 << 23);
21535 /* Place the absolute value of the addend into the first 12 bits
21536 of the instruction. */
21537 insn
&= 0xfffff000;
21538 insn
|= addend_abs
;
21540 /* Update the instruction. */
21541 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21545 case BFD_RELOC_ARM_LDRS_PC_G0
:
21546 case BFD_RELOC_ARM_LDRS_PC_G1
:
21547 case BFD_RELOC_ARM_LDRS_PC_G2
:
21548 case BFD_RELOC_ARM_LDRS_SB_G0
:
21549 case BFD_RELOC_ARM_LDRS_SB_G1
:
21550 case BFD_RELOC_ARM_LDRS_SB_G2
:
21551 gas_assert (!fixP
->fx_done
);
21552 if (!seg
->use_rela_p
)
21555 bfd_vma addend_abs
= abs (value
);
21557 /* Check that the absolute value of the addend can be
21558 encoded in 8 bits. */
21559 if (addend_abs
>= 0x100)
21560 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21561 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21562 (unsigned long) addend_abs
);
21564 /* Extract the instruction. */
21565 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21567 /* If the addend is negative, clear bit 23 of the instruction.
21568 Otherwise set it. */
21570 insn
&= ~(1 << 23);
21574 /* Place the first four bits of the absolute value of the addend
21575 into the first 4 bits of the instruction, and the remaining
21576 four into bits 8 .. 11. */
21577 insn
&= 0xfffff0f0;
21578 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21580 /* Update the instruction. */
21581 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21585 case BFD_RELOC_ARM_LDC_PC_G0
:
21586 case BFD_RELOC_ARM_LDC_PC_G1
:
21587 case BFD_RELOC_ARM_LDC_PC_G2
:
21588 case BFD_RELOC_ARM_LDC_SB_G0
:
21589 case BFD_RELOC_ARM_LDC_SB_G1
:
21590 case BFD_RELOC_ARM_LDC_SB_G2
:
21591 gas_assert (!fixP
->fx_done
);
21592 if (!seg
->use_rela_p
)
21595 bfd_vma addend_abs
= abs (value
);
21597 /* Check that the absolute value of the addend is a multiple of
21598 four and, when divided by four, fits in 8 bits. */
21599 if (addend_abs
& 0x3)
21600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21601 _("bad offset 0x%08lX (must be word-aligned)"),
21602 (unsigned long) addend_abs
);
21604 if ((addend_abs
>> 2) > 0xff)
21605 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21606 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21607 (unsigned long) addend_abs
);
21609 /* Extract the instruction. */
21610 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21612 /* If the addend is negative, clear bit 23 of the instruction.
21613 Otherwise set it. */
21615 insn
&= ~(1 << 23);
21619 /* Place the addend (divided by four) into the first eight
21620 bits of the instruction. */
21621 insn
&= 0xfffffff0;
21622 insn
|= addend_abs
>> 2;
21624 /* Update the instruction. */
21625 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21629 case BFD_RELOC_ARM_V4BX
:
21630 /* This will need to go in the object file. */
21634 case BFD_RELOC_UNUSED
:
21636 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21637 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21641 /* Translate internal representation of relocation info to BFD target
21645 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21648 bfd_reloc_code_real_type code
;
21650 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21652 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21653 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21654 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21656 if (fixp
->fx_pcrel
)
21658 if (section
->use_rela_p
)
21659 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21661 fixp
->fx_offset
= reloc
->address
;
21663 reloc
->addend
= fixp
->fx_offset
;
21665 switch (fixp
->fx_r_type
)
21668 if (fixp
->fx_pcrel
)
21670 code
= BFD_RELOC_8_PCREL
;
21675 if (fixp
->fx_pcrel
)
21677 code
= BFD_RELOC_16_PCREL
;
21682 if (fixp
->fx_pcrel
)
21684 code
= BFD_RELOC_32_PCREL
;
21688 case BFD_RELOC_ARM_MOVW
:
21689 if (fixp
->fx_pcrel
)
21691 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21695 case BFD_RELOC_ARM_MOVT
:
21696 if (fixp
->fx_pcrel
)
21698 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21702 case BFD_RELOC_ARM_THUMB_MOVW
:
21703 if (fixp
->fx_pcrel
)
21705 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21709 case BFD_RELOC_ARM_THUMB_MOVT
:
21710 if (fixp
->fx_pcrel
)
21712 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21716 case BFD_RELOC_NONE
:
21717 case BFD_RELOC_ARM_PCREL_BRANCH
:
21718 case BFD_RELOC_ARM_PCREL_BLX
:
21719 case BFD_RELOC_RVA
:
21720 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21721 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21722 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21723 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21724 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21725 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21726 case BFD_RELOC_VTABLE_ENTRY
:
21727 case BFD_RELOC_VTABLE_INHERIT
:
21729 case BFD_RELOC_32_SECREL
:
21731 code
= fixp
->fx_r_type
;
21734 case BFD_RELOC_THUMB_PCREL_BLX
:
21736 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21737 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21740 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21743 case BFD_RELOC_ARM_LITERAL
:
21744 case BFD_RELOC_ARM_HWLITERAL
:
21745 /* If this is called then the a literal has
21746 been referenced across a section boundary. */
21747 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21748 _("literal referenced across section boundary"));
21752 case BFD_RELOC_ARM_TLS_CALL
:
21753 case BFD_RELOC_ARM_THM_TLS_CALL
:
21754 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21755 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21756 case BFD_RELOC_ARM_GOT32
:
21757 case BFD_RELOC_ARM_GOTOFF
:
21758 case BFD_RELOC_ARM_GOT_PREL
:
21759 case BFD_RELOC_ARM_PLT32
:
21760 case BFD_RELOC_ARM_TARGET1
:
21761 case BFD_RELOC_ARM_ROSEGREL32
:
21762 case BFD_RELOC_ARM_SBREL32
:
21763 case BFD_RELOC_ARM_PREL31
:
21764 case BFD_RELOC_ARM_TARGET2
:
21765 case BFD_RELOC_ARM_TLS_LE32
:
21766 case BFD_RELOC_ARM_TLS_LDO32
:
21767 case BFD_RELOC_ARM_PCREL_CALL
:
21768 case BFD_RELOC_ARM_PCREL_JUMP
:
21769 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21770 case BFD_RELOC_ARM_ALU_PC_G0
:
21771 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21772 case BFD_RELOC_ARM_ALU_PC_G1
:
21773 case BFD_RELOC_ARM_ALU_PC_G2
:
21774 case BFD_RELOC_ARM_LDR_PC_G0
:
21775 case BFD_RELOC_ARM_LDR_PC_G1
:
21776 case BFD_RELOC_ARM_LDR_PC_G2
:
21777 case BFD_RELOC_ARM_LDRS_PC_G0
:
21778 case BFD_RELOC_ARM_LDRS_PC_G1
:
21779 case BFD_RELOC_ARM_LDRS_PC_G2
:
21780 case BFD_RELOC_ARM_LDC_PC_G0
:
21781 case BFD_RELOC_ARM_LDC_PC_G1
:
21782 case BFD_RELOC_ARM_LDC_PC_G2
:
21783 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21784 case BFD_RELOC_ARM_ALU_SB_G0
:
21785 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21786 case BFD_RELOC_ARM_ALU_SB_G1
:
21787 case BFD_RELOC_ARM_ALU_SB_G2
:
21788 case BFD_RELOC_ARM_LDR_SB_G0
:
21789 case BFD_RELOC_ARM_LDR_SB_G1
:
21790 case BFD_RELOC_ARM_LDR_SB_G2
:
21791 case BFD_RELOC_ARM_LDRS_SB_G0
:
21792 case BFD_RELOC_ARM_LDRS_SB_G1
:
21793 case BFD_RELOC_ARM_LDRS_SB_G2
:
21794 case BFD_RELOC_ARM_LDC_SB_G0
:
21795 case BFD_RELOC_ARM_LDC_SB_G1
:
21796 case BFD_RELOC_ARM_LDC_SB_G2
:
21797 case BFD_RELOC_ARM_V4BX
:
21798 code
= fixp
->fx_r_type
;
21801 case BFD_RELOC_ARM_TLS_GOTDESC
:
21802 case BFD_RELOC_ARM_TLS_GD32
:
21803 case BFD_RELOC_ARM_TLS_IE32
:
21804 case BFD_RELOC_ARM_TLS_LDM32
:
21805 /* BFD will include the symbol's address in the addend.
21806 But we don't want that, so subtract it out again here. */
21807 if (!S_IS_COMMON (fixp
->fx_addsy
))
21808 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21809 code
= fixp
->fx_r_type
;
21813 case BFD_RELOC_ARM_IMMEDIATE
:
21814 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21815 _("internal relocation (type: IMMEDIATE) not fixed up"));
21818 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21819 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21820 _("ADRL used for a symbol not defined in the same file"));
21823 case BFD_RELOC_ARM_OFFSET_IMM
:
21824 if (section
->use_rela_p
)
21826 code
= fixp
->fx_r_type
;
21830 if (fixp
->fx_addsy
!= NULL
21831 && !S_IS_DEFINED (fixp
->fx_addsy
)
21832 && S_IS_LOCAL (fixp
->fx_addsy
))
21834 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21835 _("undefined local label `%s'"),
21836 S_GET_NAME (fixp
->fx_addsy
));
21840 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21841 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21848 switch (fixp
->fx_r_type
)
21850 case BFD_RELOC_NONE
: type
= "NONE"; break;
21851 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21852 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21853 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21854 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21855 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21856 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21857 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21858 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21859 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21860 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21861 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21862 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21863 default: type
= _("<unknown>"); break;
21865 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21866 _("cannot represent %s relocation in this object file format"),
21873 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21875 && fixp
->fx_addsy
== GOT_symbol
)
21877 code
= BFD_RELOC_ARM_GOTPC
;
21878 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21882 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21884 if (reloc
->howto
== NULL
)
21886 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21887 _("cannot represent %s relocation in this object file format"),
21888 bfd_get_reloc_code_name (code
));
21892 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21893 vtable entry to be used in the relocation's section offset. */
21894 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21895 reloc
->address
= fixp
->fx_offset
;
21900 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21903 cons_fix_new_arm (fragS
* frag
,
21908 bfd_reloc_code_real_type type
;
21912 FIXME: @@ Should look at CPU word size. */
21916 type
= BFD_RELOC_8
;
21919 type
= BFD_RELOC_16
;
21923 type
= BFD_RELOC_32
;
21926 type
= BFD_RELOC_64
;
21931 if (exp
->X_op
== O_secrel
)
21933 exp
->X_op
= O_symbol
;
21934 type
= BFD_RELOC_32_SECREL
;
21938 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21941 #if defined (OBJ_COFF)
21943 arm_validate_fix (fixS
* fixP
)
21945 /* If the destination of the branch is a defined symbol which does not have
21946 the THUMB_FUNC attribute, then we must be calling a function which has
21947 the (interfacearm) attribute. We look for the Thumb entry point to that
21948 function and change the branch to refer to that function instead. */
21949 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21950 && fixP
->fx_addsy
!= NULL
21951 && S_IS_DEFINED (fixP
->fx_addsy
)
21952 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21954 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21961 arm_force_relocation (struct fix
* fixp
)
21963 #if defined (OBJ_COFF) && defined (TE_PE)
21964 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21968 /* In case we have a call or a branch to a function in ARM ISA mode from
21969 a thumb function or vice-versa force the relocation. These relocations
21970 are cleared off for some cores that might have blx and simple transformations
21974 switch (fixp
->fx_r_type
)
21976 case BFD_RELOC_ARM_PCREL_JUMP
:
21977 case BFD_RELOC_ARM_PCREL_CALL
:
21978 case BFD_RELOC_THUMB_PCREL_BLX
:
21979 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21983 case BFD_RELOC_ARM_PCREL_BLX
:
21984 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21985 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21986 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21987 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21996 /* Resolve these relocations even if the symbol is extern or weak.
21997 Technically this is probably wrong due to symbol preemption.
21998 In practice these relocations do not have enough range to be useful
21999 at dynamic link time, and some code (e.g. in the Linux kernel)
22000 expects these references to be resolved. */
22001 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
22002 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
22003 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
22004 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
22005 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22006 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
22007 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
22008 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
22009 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22010 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
22011 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
22012 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
22013 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
22014 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
22017 /* Always leave these relocations for the linker. */
22018 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
22019 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
22020 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
22023 /* Always generate relocations against function symbols. */
22024 if (fixp
->fx_r_type
== BFD_RELOC_32
22026 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
22029 return generic_force_reloc (fixp
);
22032 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22033 /* Relocations against function names must be left unadjusted,
22034 so that the linker can use this information to generate interworking
22035 stubs. The MIPS version of this function
22036 also prevents relocations that are mips-16 specific, but I do not
22037 know why it does this.
22040 There is one other problem that ought to be addressed here, but
22041 which currently is not: Taking the address of a label (rather
22042 than a function) and then later jumping to that address. Such
22043 addresses also ought to have their bottom bit set (assuming that
22044 they reside in Thumb code), but at the moment they will not. */
22047 arm_fix_adjustable (fixS
* fixP
)
22049 if (fixP
->fx_addsy
== NULL
)
22052 /* Preserve relocations against symbols with function type. */
22053 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
22056 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
22057 && fixP
->fx_subsy
== NULL
)
22060 /* We need the symbol name for the VTABLE entries. */
22061 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
22062 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
22065 /* Don't allow symbols to be discarded on GOT related relocs. */
22066 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
22067 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
22068 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
22069 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
22070 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
22071 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
22072 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
22073 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
22074 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
22075 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
22076 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
22077 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
22078 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
22079 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
22082 /* Similarly for group relocations. */
22083 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
22084 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
22085 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
22088 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22089 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
22090 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
22091 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
22092 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
22093 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
22094 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
22095 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
22096 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
22101 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22106 elf32_arm_target_format (void)
22109 return (target_big_endian
22110 ? "elf32-bigarm-symbian"
22111 : "elf32-littlearm-symbian");
22112 #elif defined (TE_VXWORKS)
22113 return (target_big_endian
22114 ? "elf32-bigarm-vxworks"
22115 : "elf32-littlearm-vxworks");
22117 if (target_big_endian
)
22118 return "elf32-bigarm";
22120 return "elf32-littlearm";
22125 armelf_frob_symbol (symbolS
* symp
,
22128 elf_frob_symbol (symp
, puntp
);
22132 /* MD interface: Finalization. */
22137 literal_pool
* pool
;
22139 /* Ensure that all the IT blocks are properly closed. */
22140 check_it_blocks_finished ();
22142 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
22144 /* Put it at the end of the relevant section. */
22145 subseg_set (pool
->section
, pool
->sub_section
);
22147 arm_elf_change_section ();
22154 /* Remove any excess mapping symbols generated for alignment frags in
22155 SEC. We may have created a mapping symbol before a zero byte
22156 alignment; remove it if there's a mapping symbol after the
22159 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
22160 void *dummy ATTRIBUTE_UNUSED
)
22162 segment_info_type
*seginfo
= seg_info (sec
);
22165 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
22168 for (fragp
= seginfo
->frchainP
->frch_root
;
22170 fragp
= fragp
->fr_next
)
22172 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
22173 fragS
*next
= fragp
->fr_next
;
22175 /* Variable-sized frags have been converted to fixed size by
22176 this point. But if this was variable-sized to start with,
22177 there will be a fixed-size frag after it. So don't handle
22179 if (sym
== NULL
|| next
== NULL
)
22182 if (S_GET_VALUE (sym
) < next
->fr_address
)
22183 /* Not at the end of this frag. */
22185 know (S_GET_VALUE (sym
) == next
->fr_address
);
22189 if (next
->tc_frag_data
.first_map
!= NULL
)
22191 /* Next frag starts with a mapping symbol. Discard this
22193 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22197 if (next
->fr_next
== NULL
)
22199 /* This mapping symbol is at the end of the section. Discard
22201 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
22202 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22206 /* As long as we have empty frags without any mapping symbols,
22208 /* If the next frag is non-empty and does not start with a
22209 mapping symbol, then this mapping symbol is required. */
22210 if (next
->fr_address
!= next
->fr_next
->fr_address
)
22213 next
= next
->fr_next
;
22215 while (next
!= NULL
);
22220 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22224 arm_adjust_symtab (void)
22229 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22231 if (ARM_IS_THUMB (sym
))
22233 if (THUMB_IS_FUNC (sym
))
22235 /* Mark the symbol as a Thumb function. */
22236 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
22237 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
22238 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
22240 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
22241 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
22243 as_bad (_("%s: unexpected function type: %d"),
22244 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
22246 else switch (S_GET_STORAGE_CLASS (sym
))
22249 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
22252 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
22255 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
22263 if (ARM_IS_INTERWORK (sym
))
22264 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
22271 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22273 if (ARM_IS_THUMB (sym
))
22275 elf_symbol_type
* elf_sym
;
22277 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
22278 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
22280 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
22281 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
22283 /* If it's a .thumb_func, declare it as so,
22284 otherwise tag label as .code 16. */
22285 if (THUMB_IS_FUNC (sym
))
22286 elf_sym
->internal_elf_sym
.st_target_internal
22287 = ST_BRANCH_TO_THUMB
;
22288 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22289 elf_sym
->internal_elf_sym
.st_info
=
22290 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
22295 /* Remove any overlapping mapping symbols generated by alignment frags. */
22296 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
22297 /* Now do generic ELF adjustments. */
22298 elf_adjust_symtab ();
22302 /* MD interface: Initialization. */
22305 set_constant_flonums (void)
22309 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
22310 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
22314 /* Auto-select Thumb mode if it's the only available instruction set for the
22315 given architecture. */
22318 autoselect_thumb_from_cpu_variant (void)
22320 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22321 opcode_select (16);
22330 if ( (arm_ops_hsh
= hash_new ()) == NULL
22331 || (arm_cond_hsh
= hash_new ()) == NULL
22332 || (arm_shift_hsh
= hash_new ()) == NULL
22333 || (arm_psr_hsh
= hash_new ()) == NULL
22334 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
22335 || (arm_reg_hsh
= hash_new ()) == NULL
22336 || (arm_reloc_hsh
= hash_new ()) == NULL
22337 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
22338 as_fatal (_("virtual memory exhausted"));
22340 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
22341 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
22342 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
22343 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
22344 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
22345 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
22346 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
22347 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
22348 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
22349 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
22350 (void *) (v7m_psrs
+ i
));
22351 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
22352 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
22354 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
22356 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
22357 (void *) (barrier_opt_names
+ i
));
22359 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
22360 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
22363 set_constant_flonums ();
22365 /* Set the cpu variant based on the command-line options. We prefer
22366 -mcpu= over -march= if both are set (as for GCC); and we prefer
22367 -mfpu= over any other way of setting the floating point unit.
22368 Use of legacy options with new options are faulted. */
22371 if (mcpu_cpu_opt
|| march_cpu_opt
)
22372 as_bad (_("use of old and new-style options to set CPU type"));
22374 mcpu_cpu_opt
= legacy_cpu
;
22376 else if (!mcpu_cpu_opt
)
22377 mcpu_cpu_opt
= march_cpu_opt
;
22382 as_bad (_("use of old and new-style options to set FPU type"));
22384 mfpu_opt
= legacy_fpu
;
22386 else if (!mfpu_opt
)
22388 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22389 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22390 /* Some environments specify a default FPU. If they don't, infer it
22391 from the processor. */
22393 mfpu_opt
= mcpu_fpu_opt
;
22395 mfpu_opt
= march_fpu_opt
;
22397 mfpu_opt
= &fpu_default
;
22403 if (mcpu_cpu_opt
!= NULL
)
22404 mfpu_opt
= &fpu_default
;
22405 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
22406 mfpu_opt
= &fpu_arch_vfp_v2
;
22408 mfpu_opt
= &fpu_arch_fpa
;
22414 mcpu_cpu_opt
= &cpu_default
;
22415 selected_cpu
= cpu_default
;
22419 selected_cpu
= *mcpu_cpu_opt
;
22421 mcpu_cpu_opt
= &arm_arch_any
;
22424 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22426 autoselect_thumb_from_cpu_variant ();
22428 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
22430 #if defined OBJ_COFF || defined OBJ_ELF
22432 unsigned int flags
= 0;
22434 #if defined OBJ_ELF
22435 flags
= meabi_flags
;
22437 switch (meabi_flags
)
22439 case EF_ARM_EABI_UNKNOWN
:
22441 /* Set the flags in the private structure. */
22442 if (uses_apcs_26
) flags
|= F_APCS26
;
22443 if (support_interwork
) flags
|= F_INTERWORK
;
22444 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
22445 if (pic_code
) flags
|= F_PIC
;
22446 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
22447 flags
|= F_SOFT_FLOAT
;
22449 switch (mfloat_abi_opt
)
22451 case ARM_FLOAT_ABI_SOFT
:
22452 case ARM_FLOAT_ABI_SOFTFP
:
22453 flags
|= F_SOFT_FLOAT
;
22456 case ARM_FLOAT_ABI_HARD
:
22457 if (flags
& F_SOFT_FLOAT
)
22458 as_bad (_("hard-float conflicts with specified fpu"));
22462 /* Using pure-endian doubles (even if soft-float). */
22463 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
22464 flags
|= F_VFP_FLOAT
;
22466 #if defined OBJ_ELF
22467 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
22468 flags
|= EF_ARM_MAVERICK_FLOAT
;
22471 case EF_ARM_EABI_VER4
:
22472 case EF_ARM_EABI_VER5
:
22473 /* No additional flags to set. */
22480 bfd_set_private_flags (stdoutput
, flags
);
22482 /* We have run out flags in the COFF header to encode the
22483 status of ATPCS support, so instead we create a dummy,
22484 empty, debug section called .arm.atpcs. */
22489 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
22493 bfd_set_section_flags
22494 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
22495 bfd_set_section_size (stdoutput
, sec
, 0);
22496 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
22502 /* Record the CPU type as well. */
22503 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
22504 mach
= bfd_mach_arm_iWMMXt2
;
22505 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
22506 mach
= bfd_mach_arm_iWMMXt
;
22507 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
22508 mach
= bfd_mach_arm_XScale
;
22509 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
22510 mach
= bfd_mach_arm_ep9312
;
22511 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22512 mach
= bfd_mach_arm_5TE
;
22513 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22515 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22516 mach
= bfd_mach_arm_5T
;
22518 mach
= bfd_mach_arm_5
;
22520 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22522 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22523 mach
= bfd_mach_arm_4T
;
22525 mach
= bfd_mach_arm_4
;
22527 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22528 mach
= bfd_mach_arm_3M
;
22529 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22530 mach
= bfd_mach_arm_3
;
22531 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22532 mach
= bfd_mach_arm_2a
;
22533 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22534 mach
= bfd_mach_arm_2
;
22536 mach
= bfd_mach_arm_unknown
;
22538 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22541 /* Command line processing. */
22544 Invocation line includes a switch not recognized by the base assembler.
22545 See if it's a processor-specific option.
22547 This routine is somewhat complicated by the need for backwards
22548 compatibility (since older releases of gcc can't be changed).
22549 The new options try to make the interface as compatible as
22552 New options (supported) are:
22554 -mcpu=<cpu name> Assemble for selected processor
22555 -march=<architecture name> Assemble for selected architecture
22556 -mfpu=<fpu architecture> Assemble for selected FPU.
22557 -EB/-mbig-endian Big-endian
22558 -EL/-mlittle-endian Little-endian
22559 -k Generate PIC code
22560 -mthumb Start in Thumb mode
22561 -mthumb-interwork Code supports ARM/Thumb interworking
22563 -m[no-]warn-deprecated Warn about deprecated features
22565 For now we will also provide support for:
22567 -mapcs-32 32-bit Program counter
22568 -mapcs-26 26-bit Program counter
22569 -macps-float Floats passed in FP registers
22570 -mapcs-reentrant Reentrant code
22572 (sometime these will probably be replaced with -mapcs=<list of options>
22573 and -matpcs=<list of options>)
22575 The remaining options are only supported for back-wards compatibility.
22576 Cpu variants, the arm part is optional:
22577 -m[arm]1 Currently not supported.
22578 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22579 -m[arm]3 Arm 3 processor
22580 -m[arm]6[xx], Arm 6 processors
22581 -m[arm]7[xx][t][[d]m] Arm 7 processors
22582 -m[arm]8[10] Arm 8 processors
22583 -m[arm]9[20][tdmi] Arm 9 processors
22584 -mstrongarm[110[0]] StrongARM processors
22585 -mxscale XScale processors
22586 -m[arm]v[2345[t[e]]] Arm architectures
22587 -mall All (except the ARM1)
22589 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22590 -mfpe-old (No float load/store multiples)
22591 -mvfpxd VFP Single precision
22593 -mno-fpu Disable all floating point instructions
22595 The following CPU names are recognized:
22596 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22597 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22598 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22599 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22600 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22601 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22602 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22606 const char * md_shortopts
= "m:k";
22608 #ifdef ARM_BI_ENDIAN
22609 #define OPTION_EB (OPTION_MD_BASE + 0)
22610 #define OPTION_EL (OPTION_MD_BASE + 1)
22612 #if TARGET_BYTES_BIG_ENDIAN
22613 #define OPTION_EB (OPTION_MD_BASE + 0)
22615 #define OPTION_EL (OPTION_MD_BASE + 1)
22618 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22620 struct option md_longopts
[] =
22623 {"EB", no_argument
, NULL
, OPTION_EB
},
22626 {"EL", no_argument
, NULL
, OPTION_EL
},
22628 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22629 {NULL
, no_argument
, NULL
, 0}
22632 size_t md_longopts_size
= sizeof (md_longopts
);
22634 struct arm_option_table
22636 char *option
; /* Option name to match. */
22637 char *help
; /* Help information. */
22638 int *var
; /* Variable to change. */
22639 int value
; /* What to change it to. */
22640 char *deprecated
; /* If non-null, print this message. */
22643 struct arm_option_table arm_opts
[] =
22645 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22646 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22647 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22648 &support_interwork
, 1, NULL
},
22649 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22650 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22651 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22653 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22654 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22655 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22656 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22659 /* These are recognized by the assembler, but have no affect on code. */
22660 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22661 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22663 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22664 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22665 &warn_on_deprecated
, 0, NULL
},
22666 {NULL
, NULL
, NULL
, 0, NULL
}
22669 struct arm_legacy_option_table
22671 char *option
; /* Option name to match. */
22672 const arm_feature_set
**var
; /* Variable to change. */
22673 const arm_feature_set value
; /* What to change it to. */
22674 char *deprecated
; /* If non-null, print this message. */
22677 const struct arm_legacy_option_table arm_legacy_opts
[] =
22679 /* DON'T add any new processors to this list -- we want the whole list
22680 to go away... Add them to the processors table instead. */
22681 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22682 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22683 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22684 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22685 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22686 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22687 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22688 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22689 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22690 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22691 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22692 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22693 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22694 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22695 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22696 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22697 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22698 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22699 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22700 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22701 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22702 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22703 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22704 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22705 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22706 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22707 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22708 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22709 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22710 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22711 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22712 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22713 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22714 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22715 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22716 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22717 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22718 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22719 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22720 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22721 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22722 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22723 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22724 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22725 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22726 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22727 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22728 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22729 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22730 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22731 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22732 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22733 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22734 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22735 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22736 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22737 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22738 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22739 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22740 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22741 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22742 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22743 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22744 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22745 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22746 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22747 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22748 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22749 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22750 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22751 N_("use -mcpu=strongarm110")},
22752 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22753 N_("use -mcpu=strongarm1100")},
22754 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22755 N_("use -mcpu=strongarm1110")},
22756 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22757 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22758 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22760 /* Architecture variants -- don't add any more to this list either. */
22761 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22762 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22763 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22764 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22765 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22766 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22767 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22768 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22769 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22770 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22771 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22772 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22773 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22774 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22775 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22776 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22777 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22778 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22780 /* Floating point variants -- don't add any more to this list either. */
22781 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22782 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22783 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22784 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22785 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22787 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22790 struct arm_cpu_option_table
22793 const arm_feature_set value
;
22794 /* For some CPUs we assume an FPU unless the user explicitly sets
22796 const arm_feature_set default_fpu
;
22797 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22799 const char *canonical_name
;
22802 /* This list should, at a minimum, contain all the cpu names
22803 recognized by GCC. */
22804 static const struct arm_cpu_option_table arm_cpus
[] =
22806 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22807 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22808 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22809 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22810 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22811 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22812 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22813 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22814 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22815 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22816 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22817 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22818 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22819 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22820 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22821 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22822 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22823 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22824 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22825 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22826 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22827 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22828 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22829 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22830 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22831 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22832 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22833 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22834 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22835 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22836 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22837 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22838 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22839 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22840 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22841 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22842 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22843 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22844 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22845 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22846 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22847 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22848 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22849 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22850 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22851 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22852 /* For V5 or later processors we default to using VFP; but the user
22853 should really set the FPU type explicitly. */
22854 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22855 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22856 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22857 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22858 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22859 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22860 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22861 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22862 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22863 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22864 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22865 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22866 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22867 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22868 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22869 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22870 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22871 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22872 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22873 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22874 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22875 {"fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22876 {"fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22877 {"fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22878 {"fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22879 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22880 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22881 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22882 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22883 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22884 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"},
22885 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"},
22886 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22887 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22888 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22889 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22890 {"cortex-a5", ARM_ARCH_V7A_MP_SEC
,
22891 FPU_NONE
, "Cortex-A5"},
22892 {"cortex-a8", ARM_ARCH_V7A_SEC
,
22893 ARM_FEATURE (0, FPU_VFP_V3
22894 | FPU_NEON_EXT_V1
),
22896 {"cortex-a9", ARM_ARCH_V7A_MP_SEC
,
22897 ARM_FEATURE (0, FPU_VFP_V3
22898 | FPU_NEON_EXT_V1
),
22900 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
22901 FPU_ARCH_NEON_VFP_V4
,
22903 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"},
22904 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
22906 {"cortex-r5", ARM_ARCH_V7R_IDIV
,
22907 FPU_NONE
, "Cortex-R5"},
22908 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"},
22909 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"},
22910 {"cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"},
22911 {"cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"},
22912 /* ??? XSCALE is really an architecture. */
22913 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22914 /* ??? iwmmxt is not a processor. */
22915 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22916 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22917 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22919 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22920 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22923 struct arm_arch_option_table
22926 const arm_feature_set value
;
22927 const arm_feature_set default_fpu
;
22930 /* This list should, at a minimum, contain all the architecture names
22931 recognized by GCC. */
22932 static const struct arm_arch_option_table arm_archs
[] =
22934 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22935 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22936 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22937 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22938 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22939 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22940 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22941 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22942 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22943 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22944 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22945 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22946 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22947 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22948 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22949 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22950 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22951 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22952 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22953 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22954 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22955 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22956 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22957 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22958 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22959 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22960 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22961 {"armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
},
22962 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22963 /* The official spelling of the ARMv7 profile variants is the dashed form.
22964 Accept the non-dashed form for compatibility with old toolchains. */
22965 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22966 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22967 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22968 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22969 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22970 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22971 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22972 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22973 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22974 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22975 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22978 /* ISA extensions in the co-processor and main instruction set space. */
22979 struct arm_option_extension_value_table
22982 const arm_feature_set value
;
22983 const arm_feature_set allowed_archs
;
22986 /* The following table must be in alphabetical order with a NULL last entry.
22988 static const struct arm_option_extension_value_table arm_extensions
[] =
22990 {"idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
22991 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
22992 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
},
22993 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
},
22994 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
},
22995 {"mp", ARM_FEATURE (ARM_EXT_MP
, 0),
22996 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
22997 {"os", ARM_FEATURE (ARM_EXT_OS
, 0),
22998 ARM_FEATURE (ARM_EXT_V6M
, 0)},
22999 {"sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
23000 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)},
23001 {"virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
23002 ARM_FEATURE (ARM_EXT_V7A
, 0)},
23003 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
},
23004 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
23007 /* ISA floating-point and Advanced SIMD extensions. */
23008 struct arm_option_fpu_value_table
23011 const arm_feature_set value
;
23014 /* This list should, at a minimum, contain all the fpu names
23015 recognized by GCC. */
23016 static const struct arm_option_fpu_value_table arm_fpus
[] =
23018 {"softfpa", FPU_NONE
},
23019 {"fpe", FPU_ARCH_FPE
},
23020 {"fpe2", FPU_ARCH_FPE
},
23021 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
23022 {"fpa", FPU_ARCH_FPA
},
23023 {"fpa10", FPU_ARCH_FPA
},
23024 {"fpa11", FPU_ARCH_FPA
},
23025 {"arm7500fe", FPU_ARCH_FPA
},
23026 {"softvfp", FPU_ARCH_VFP
},
23027 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
23028 {"vfp", FPU_ARCH_VFP_V2
},
23029 {"vfp9", FPU_ARCH_VFP_V2
},
23030 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
23031 {"vfp10", FPU_ARCH_VFP_V2
},
23032 {"vfp10-r0", FPU_ARCH_VFP_V1
},
23033 {"vfpxd", FPU_ARCH_VFP_V1xD
},
23034 {"vfpv2", FPU_ARCH_VFP_V2
},
23035 {"vfpv3", FPU_ARCH_VFP_V3
},
23036 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
23037 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
23038 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
23039 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
23040 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
23041 {"arm1020t", FPU_ARCH_VFP_V1
},
23042 {"arm1020e", FPU_ARCH_VFP_V2
},
23043 {"arm1136jfs", FPU_ARCH_VFP_V2
},
23044 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
23045 {"maverick", FPU_ARCH_MAVERICK
},
23046 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
23047 {"neon-fp16", FPU_ARCH_NEON_FP16
},
23048 {"vfpv4", FPU_ARCH_VFP_V4
},
23049 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
23050 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
23051 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
23052 {NULL
, ARM_ARCH_NONE
}
23055 struct arm_option_value_table
23061 static const struct arm_option_value_table arm_float_abis
[] =
23063 {"hard", ARM_FLOAT_ABI_HARD
},
23064 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
23065 {"soft", ARM_FLOAT_ABI_SOFT
},
23070 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23071 static const struct arm_option_value_table arm_eabis
[] =
23073 {"gnu", EF_ARM_EABI_UNKNOWN
},
23074 {"4", EF_ARM_EABI_VER4
},
23075 {"5", EF_ARM_EABI_VER5
},
23080 struct arm_long_option_table
23082 char * option
; /* Substring to match. */
23083 char * help
; /* Help information. */
23084 int (* func
) (char * subopt
); /* Function to decode sub-option. */
23085 char * deprecated
; /* If non-null, print this message. */
23089 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
23091 arm_feature_set
*ext_set
= (arm_feature_set
*)
23092 xmalloc (sizeof (arm_feature_set
));
23094 /* We insist on extensions being specified in alphabetical order, and with
23095 extensions being added before being removed. We achieve this by having
23096 the global ARM_EXTENSIONS table in alphabetical order, and using the
23097 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23098 or removing it (0) and only allowing it to change in the order
23100 const struct arm_option_extension_value_table
* opt
= NULL
;
23101 int adding_value
= -1;
23103 /* Copy the feature set, so that we can modify it. */
23104 *ext_set
= **opt_p
;
23107 while (str
!= NULL
&& *str
!= 0)
23114 as_bad (_("invalid architectural extension"));
23119 ext
= strchr (str
, '+');
23122 optlen
= ext
- str
;
23124 optlen
= strlen (str
);
23127 && strncmp (str
, "no", 2) == 0)
23129 if (adding_value
!= 0)
23132 opt
= arm_extensions
;
23138 else if (optlen
> 0)
23140 if (adding_value
== -1)
23143 opt
= arm_extensions
;
23145 else if (adding_value
!= 1)
23147 as_bad (_("must specify extensions to add before specifying "
23148 "those to remove"));
23155 as_bad (_("missing architectural extension"));
23159 gas_assert (adding_value
!= -1);
23160 gas_assert (opt
!= NULL
);
23162 /* Scan over the options table trying to find an exact match. */
23163 for (; opt
->name
!= NULL
; opt
++)
23164 if (strncmp (opt
->name
, str
, optlen
) == 0
23165 && strlen (opt
->name
) == optlen
)
23167 /* Check we can apply the extension to this architecture. */
23168 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
23170 as_bad (_("extension does not apply to the base architecture"));
23174 /* Add or remove the extension. */
23176 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
23178 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
23183 if (opt
->name
== NULL
)
23185 /* Did we fail to find an extension because it wasn't specified in
23186 alphabetical order, or because it does not exist? */
23188 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23189 if (strncmp (opt
->name
, str
, optlen
) == 0)
23192 if (opt
->name
== NULL
)
23193 as_bad (_("unknown architectural extension `%s'"), str
);
23195 as_bad (_("architectural extensions must be specified in "
23196 "alphabetical order"));
23202 /* We should skip the extension we've just matched the next time
23214 arm_parse_cpu (char * str
)
23216 const struct arm_cpu_option_table
* opt
;
23217 char * ext
= strchr (str
, '+');
23221 optlen
= ext
- str
;
23223 optlen
= strlen (str
);
23227 as_bad (_("missing cpu name `%s'"), str
);
23231 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
23232 if (strncmp (opt
->name
, str
, optlen
) == 0)
23234 mcpu_cpu_opt
= &opt
->value
;
23235 mcpu_fpu_opt
= &opt
->default_fpu
;
23236 if (opt
->canonical_name
)
23237 strcpy (selected_cpu_name
, opt
->canonical_name
);
23242 for (i
= 0; i
< optlen
; i
++)
23243 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23244 selected_cpu_name
[i
] = 0;
23248 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
23253 as_bad (_("unknown cpu `%s'"), str
);
23258 arm_parse_arch (char * str
)
23260 const struct arm_arch_option_table
*opt
;
23261 char *ext
= strchr (str
, '+');
23265 optlen
= ext
- str
;
23267 optlen
= strlen (str
);
23271 as_bad (_("missing architecture name `%s'"), str
);
23275 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
23276 if (strncmp (opt
->name
, str
, optlen
) == 0)
23278 march_cpu_opt
= &opt
->value
;
23279 march_fpu_opt
= &opt
->default_fpu
;
23280 strcpy (selected_cpu_name
, opt
->name
);
23283 return arm_parse_extension (ext
, &march_cpu_opt
);
23288 as_bad (_("unknown architecture `%s'\n"), str
);
23293 arm_parse_fpu (char * str
)
23295 const struct arm_option_fpu_value_table
* opt
;
23297 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23298 if (streq (opt
->name
, str
))
23300 mfpu_opt
= &opt
->value
;
23304 as_bad (_("unknown floating point format `%s'\n"), str
);
23309 arm_parse_float_abi (char * str
)
23311 const struct arm_option_value_table
* opt
;
23313 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
23314 if (streq (opt
->name
, str
))
23316 mfloat_abi_opt
= opt
->value
;
23320 as_bad (_("unknown floating point abi `%s'\n"), str
);
23326 arm_parse_eabi (char * str
)
23328 const struct arm_option_value_table
*opt
;
23330 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
23331 if (streq (opt
->name
, str
))
23333 meabi_flags
= opt
->value
;
23336 as_bad (_("unknown EABI `%s'\n"), str
);
23342 arm_parse_it_mode (char * str
)
23344 bfd_boolean ret
= TRUE
;
23346 if (streq ("arm", str
))
23347 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
23348 else if (streq ("thumb", str
))
23349 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
23350 else if (streq ("always", str
))
23351 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
23352 else if (streq ("never", str
))
23353 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
23356 as_bad (_("unknown implicit IT mode `%s', should be "\
23357 "arm, thumb, always, or never."), str
);
23364 struct arm_long_option_table arm_long_opts
[] =
23366 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23367 arm_parse_cpu
, NULL
},
23368 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23369 arm_parse_arch
, NULL
},
23370 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23371 arm_parse_fpu
, NULL
},
23372 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23373 arm_parse_float_abi
, NULL
},
23375 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23376 arm_parse_eabi
, NULL
},
23378 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23379 arm_parse_it_mode
, NULL
},
23380 {NULL
, NULL
, 0, NULL
}
23384 md_parse_option (int c
, char * arg
)
23386 struct arm_option_table
*opt
;
23387 const struct arm_legacy_option_table
*fopt
;
23388 struct arm_long_option_table
*lopt
;
23394 target_big_endian
= 1;
23400 target_big_endian
= 0;
23404 case OPTION_FIX_V4BX
:
23409 /* Listing option. Just ignore these, we don't support additional
23414 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23416 if (c
== opt
->option
[0]
23417 && ((arg
== NULL
&& opt
->option
[1] == 0)
23418 || streq (arg
, opt
->option
+ 1)))
23420 /* If the option is deprecated, tell the user. */
23421 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
23422 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23423 arg
? arg
: "", _(opt
->deprecated
));
23425 if (opt
->var
!= NULL
)
23426 *opt
->var
= opt
->value
;
23432 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
23434 if (c
== fopt
->option
[0]
23435 && ((arg
== NULL
&& fopt
->option
[1] == 0)
23436 || streq (arg
, fopt
->option
+ 1)))
23438 /* If the option is deprecated, tell the user. */
23439 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
23440 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23441 arg
? arg
: "", _(fopt
->deprecated
));
23443 if (fopt
->var
!= NULL
)
23444 *fopt
->var
= &fopt
->value
;
23450 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23452 /* These options are expected to have an argument. */
23453 if (c
== lopt
->option
[0]
23455 && strncmp (arg
, lopt
->option
+ 1,
23456 strlen (lopt
->option
+ 1)) == 0)
23458 /* If the option is deprecated, tell the user. */
23459 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
23460 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
23461 _(lopt
->deprecated
));
23463 /* Call the sup-option parser. */
23464 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
23475 md_show_usage (FILE * fp
)
23477 struct arm_option_table
*opt
;
23478 struct arm_long_option_table
*lopt
;
23480 fprintf (fp
, _(" ARM-specific assembler options:\n"));
23482 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23483 if (opt
->help
!= NULL
)
23484 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
23486 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23487 if (lopt
->help
!= NULL
)
23488 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
23492 -EB assemble code for a big-endian cpu\n"));
23497 -EL assemble code for a little-endian cpu\n"));
23501 --fix-v4bx Allow BX in ARMv4 code\n"));
23509 arm_feature_set flags
;
23510 } cpu_arch_ver_table
;
23512 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23513 least features first. */
23514 static const cpu_arch_ver_table cpu_arch_ver
[] =
23520 {4, ARM_ARCH_V5TE
},
23521 {5, ARM_ARCH_V5TEJ
},
23525 {11, ARM_ARCH_V6M
},
23526 {12, ARM_ARCH_V6SM
},
23527 {8, ARM_ARCH_V6T2
},
23528 {10, ARM_ARCH_V7A
},
23529 {10, ARM_ARCH_V7R
},
23530 {10, ARM_ARCH_V7M
},
23534 /* Set an attribute if it has not already been set by the user. */
23536 aeabi_set_attribute_int (int tag
, int value
)
23539 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23540 || !attributes_set_explicitly
[tag
])
23541 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
23545 aeabi_set_attribute_string (int tag
, const char *value
)
23548 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23549 || !attributes_set_explicitly
[tag
])
23550 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
23553 /* Set the public EABI object attributes. */
23555 aeabi_set_public_attributes (void)
23559 arm_feature_set flags
;
23560 arm_feature_set tmp
;
23561 const cpu_arch_ver_table
*p
;
23563 /* Choose the architecture based on the capabilities of the requested cpu
23564 (if any) and/or the instructions actually used. */
23565 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
23566 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
23567 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
23568 /*Allow the user to override the reported architecture. */
23571 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
23572 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
23575 /* We need to make sure that the attributes do not identify us as v6S-M
23576 when the only v6S-M feature in use is the Operating System Extensions. */
23577 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
23578 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
23579 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
23583 for (p
= cpu_arch_ver
; p
->val
; p
++)
23585 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
23588 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
23592 /* The table lookup above finds the last architecture to contribute
23593 a new feature. Unfortunately, Tag13 is a subset of the union of
23594 v6T2 and v7-M, so it is never seen as contributing a new feature.
23595 We can not search for the last entry which is entirely used,
23596 because if no CPU is specified we build up only those flags
23597 actually used. Perhaps we should separate out the specified
23598 and implicit cases. Avoid taking this path for -march=all by
23599 checking for contradictory v7-A / v7-M features. */
23601 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
23602 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
23603 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
23606 /* Tag_CPU_name. */
23607 if (selected_cpu_name
[0])
23611 q
= selected_cpu_name
;
23612 if (strncmp (q
, "armv", 4) == 0)
23617 for (i
= 0; q
[i
]; i
++)
23618 q
[i
] = TOUPPER (q
[i
]);
23620 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23623 /* Tag_CPU_arch. */
23624 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23626 /* Tag_CPU_arch_profile. */
23627 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23628 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23629 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23630 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23631 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23632 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23634 /* Tag_ARM_ISA_use. */
23635 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23637 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23639 /* Tag_THUMB_ISA_use. */
23640 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23642 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23643 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23645 /* Tag_VFP_arch. */
23646 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23647 aeabi_set_attribute_int (Tag_VFP_arch
,
23648 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23650 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23651 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23652 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23653 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23654 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23655 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23656 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23657 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23658 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23660 /* Tag_ABI_HardFP_use. */
23661 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23662 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23663 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23665 /* Tag_WMMX_arch. */
23666 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23667 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23668 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23669 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23671 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23672 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23673 aeabi_set_attribute_int
23674 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23677 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23678 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23679 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23682 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
))
23683 aeabi_set_attribute_int (Tag_DIV_use
, 2);
23684 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23685 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23687 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23689 /* Tag_MP_extension_use. */
23690 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
23691 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
23693 /* Tag Virtualization_use. */
23694 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
23696 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
23699 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
23702 /* Add the default contents for the .ARM.attributes section. */
23706 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23709 aeabi_set_public_attributes ();
23711 #endif /* OBJ_ELF */
23714 /* Parse a .cpu directive. */
23717 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23719 const struct arm_cpu_option_table
*opt
;
23723 name
= input_line_pointer
;
23724 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23725 input_line_pointer
++;
23726 saved_char
= *input_line_pointer
;
23727 *input_line_pointer
= 0;
23729 /* Skip the first "all" entry. */
23730 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23731 if (streq (opt
->name
, name
))
23733 mcpu_cpu_opt
= &opt
->value
;
23734 selected_cpu
= opt
->value
;
23735 if (opt
->canonical_name
)
23736 strcpy (selected_cpu_name
, opt
->canonical_name
);
23740 for (i
= 0; opt
->name
[i
]; i
++)
23741 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23742 selected_cpu_name
[i
] = 0;
23744 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23745 *input_line_pointer
= saved_char
;
23746 demand_empty_rest_of_line ();
23749 as_bad (_("unknown cpu `%s'"), name
);
23750 *input_line_pointer
= saved_char
;
23751 ignore_rest_of_line ();
23755 /* Parse a .arch directive. */
23758 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23760 const struct arm_arch_option_table
*opt
;
23764 name
= input_line_pointer
;
23765 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23766 input_line_pointer
++;
23767 saved_char
= *input_line_pointer
;
23768 *input_line_pointer
= 0;
23770 /* Skip the first "all" entry. */
23771 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23772 if (streq (opt
->name
, name
))
23774 mcpu_cpu_opt
= &opt
->value
;
23775 selected_cpu
= opt
->value
;
23776 strcpy (selected_cpu_name
, opt
->name
);
23777 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23778 *input_line_pointer
= saved_char
;
23779 demand_empty_rest_of_line ();
23783 as_bad (_("unknown architecture `%s'\n"), name
);
23784 *input_line_pointer
= saved_char
;
23785 ignore_rest_of_line ();
23789 /* Parse a .object_arch directive. */
23792 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23794 const struct arm_arch_option_table
*opt
;
23798 name
= input_line_pointer
;
23799 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23800 input_line_pointer
++;
23801 saved_char
= *input_line_pointer
;
23802 *input_line_pointer
= 0;
23804 /* Skip the first "all" entry. */
23805 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23806 if (streq (opt
->name
, name
))
23808 object_arch
= &opt
->value
;
23809 *input_line_pointer
= saved_char
;
23810 demand_empty_rest_of_line ();
23814 as_bad (_("unknown architecture `%s'\n"), name
);
23815 *input_line_pointer
= saved_char
;
23816 ignore_rest_of_line ();
23819 /* Parse a .arch_extension directive. */
23822 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
23824 const struct arm_option_extension_value_table
*opt
;
23827 int adding_value
= 1;
23829 name
= input_line_pointer
;
23830 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23831 input_line_pointer
++;
23832 saved_char
= *input_line_pointer
;
23833 *input_line_pointer
= 0;
23835 if (strlen (name
) >= 2
23836 && strncmp (name
, "no", 2) == 0)
23842 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23843 if (streq (opt
->name
, name
))
23845 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
23847 as_bad (_("architectural extension `%s' is not allowed for the "
23848 "current base architecture"), name
);
23853 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
23855 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
23857 mcpu_cpu_opt
= &selected_cpu
;
23858 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23859 *input_line_pointer
= saved_char
;
23860 demand_empty_rest_of_line ();
23864 if (opt
->name
== NULL
)
23865 as_bad (_("unknown architecture `%s'\n"), name
);
23867 *input_line_pointer
= saved_char
;
23868 ignore_rest_of_line ();
23871 /* Parse a .fpu directive. */
23874 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23876 const struct arm_option_fpu_value_table
*opt
;
23880 name
= input_line_pointer
;
23881 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23882 input_line_pointer
++;
23883 saved_char
= *input_line_pointer
;
23884 *input_line_pointer
= 0;
23886 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23887 if (streq (opt
->name
, name
))
23889 mfpu_opt
= &opt
->value
;
23890 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23891 *input_line_pointer
= saved_char
;
23892 demand_empty_rest_of_line ();
23896 as_bad (_("unknown floating point format `%s'\n"), name
);
23897 *input_line_pointer
= saved_char
;
23898 ignore_rest_of_line ();
23901 /* Copy symbol information. */
23904 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23906 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23910 /* Given a symbolic attribute NAME, return the proper integer value.
23911 Returns -1 if the attribute is not known. */
23914 arm_convert_symbolic_attribute (const char *name
)
23916 static const struct
23921 attribute_table
[] =
23923 /* When you modify this table you should
23924 also modify the list in doc/c-arm.texi. */
23925 #define T(tag) {#tag, tag}
23926 T (Tag_CPU_raw_name
),
23929 T (Tag_CPU_arch_profile
),
23930 T (Tag_ARM_ISA_use
),
23931 T (Tag_THUMB_ISA_use
),
23935 T (Tag_Advanced_SIMD_arch
),
23936 T (Tag_PCS_config
),
23937 T (Tag_ABI_PCS_R9_use
),
23938 T (Tag_ABI_PCS_RW_data
),
23939 T (Tag_ABI_PCS_RO_data
),
23940 T (Tag_ABI_PCS_GOT_use
),
23941 T (Tag_ABI_PCS_wchar_t
),
23942 T (Tag_ABI_FP_rounding
),
23943 T (Tag_ABI_FP_denormal
),
23944 T (Tag_ABI_FP_exceptions
),
23945 T (Tag_ABI_FP_user_exceptions
),
23946 T (Tag_ABI_FP_number_model
),
23947 T (Tag_ABI_align_needed
),
23948 T (Tag_ABI_align8_needed
),
23949 T (Tag_ABI_align_preserved
),
23950 T (Tag_ABI_align8_preserved
),
23951 T (Tag_ABI_enum_size
),
23952 T (Tag_ABI_HardFP_use
),
23953 T (Tag_ABI_VFP_args
),
23954 T (Tag_ABI_WMMX_args
),
23955 T (Tag_ABI_optimization_goals
),
23956 T (Tag_ABI_FP_optimization_goals
),
23957 T (Tag_compatibility
),
23958 T (Tag_CPU_unaligned_access
),
23959 T (Tag_FP_HP_extension
),
23960 T (Tag_VFP_HP_extension
),
23961 T (Tag_ABI_FP_16bit_format
),
23962 T (Tag_MPextension_use
),
23964 T (Tag_nodefaults
),
23965 T (Tag_also_compatible_with
),
23966 T (Tag_conformance
),
23968 T (Tag_Virtualization_use
),
23969 /* We deliberately do not include Tag_MPextension_use_legacy. */
23977 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23978 if (streq (name
, attribute_table
[i
].name
))
23979 return attribute_table
[i
].tag
;
23985 /* Apply sym value for relocations only in the case that
23986 they are for local symbols and you have the respective
23987 architectural feature for blx and simple switches. */
23989 arm_apply_sym_value (struct fix
* fixP
)
23992 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23993 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
23995 switch (fixP
->fx_r_type
)
23997 case BFD_RELOC_ARM_PCREL_BLX
:
23998 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23999 if (ARM_IS_FUNC (fixP
->fx_addsy
))
24003 case BFD_RELOC_ARM_PCREL_CALL
:
24004 case BFD_RELOC_THUMB_PCREL_BLX
:
24005 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
24016 #endif /* OBJ_ELF */