1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2021 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
39 #include "dw2gencfi.h"
42 #include "dwarf2dbg.h"
45 /* Must be at least the size of the largest unwind opcode (currently two). */
46 #define ARM_OPCODE_CHUNK_SIZE 8
48 /* This structure holds the unwinding state. */
53 symbolS
* table_entry
;
54 symbolS
* personality_routine
;
55 int personality_index
;
56 /* The segment containing the function. */
59 /* Opcodes generated from this function. */
60 unsigned char * opcodes
;
63 /* The number of bytes pushed to the stack. */
65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
68 offsetT pending_offset
;
69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
70 hold the reg+offset to use when restoring sp from a frame pointer. */
73 /* Nonzero if an unwind_setfp directive has been seen. */
75 /* Nonzero if the last opcode restores sp from fp_reg. */
76 unsigned sp_restored
:1;
79 /* Whether --fdpic was given. */
84 /* Results from operand parsing worker functions. */
88 PARSE_OPERAND_SUCCESS
,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91 } parse_operand_result
;
100 /* Types of processor to assemble for. */
102 /* The code that was here used to select a default CPU depending on compiler
103 pre-defines which were only present when doing native builds, thus
104 changing gas' default behaviour depending upon the build host.
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
110 /* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112 static bool out_of_range_p (offsetT value
, offsetT bits
)
114 gas_assert (bits
< (offsetT
)(sizeof (value
) * 8));
115 return (value
& ~((1 << bits
)-1))
116 && ((value
& ~((1 << bits
)-1)) != ~((1 << bits
)-1));
121 # define FPU_DEFAULT FPU_ARCH_FPA
122 # elif defined (TE_NetBSD)
124 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
126 /* Legacy a.out format. */
127 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
129 # elif defined (TE_VXWORKS)
130 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
132 /* For backwards compatibility, default to FPA. */
133 # define FPU_DEFAULT FPU_ARCH_FPA
135 #endif /* ifndef FPU_DEFAULT */
137 #define streq(a, b) (strcmp (a, b) == 0)
139 /* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
142 static arm_feature_set cpu_variant
;
143 /* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
145 static arm_feature_set arm_arch_used
;
146 static arm_feature_set thumb_arch_used
;
148 /* Flags stored in private area of BFD structure. */
149 static int uses_apcs_26
= false;
150 static int atpcs
= false;
151 static int support_interwork
= false;
152 static int uses_apcs_float
= false;
153 static int pic_code
= false;
154 static int fix_v4bx
= false;
155 /* Warn on using deprecated features. */
156 static int warn_on_deprecated
= true;
157 static int warn_on_restrict_it
= false;
159 /* Understand CodeComposer Studio assembly syntax. */
160 bool codecomposer_syntax
= false;
162 /* Variables that we set while parsing command-line options. Once all
163 options have been read we re-process these values to set the real
166 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
167 instead of -mcpu=arm1). */
168 static const arm_feature_set
*legacy_cpu
= NULL
;
169 static const arm_feature_set
*legacy_fpu
= NULL
;
171 /* CPU, extension and FPU feature bits selected by -mcpu. */
172 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
173 static arm_feature_set
*mcpu_ext_opt
= NULL
;
174 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
176 /* CPU, extension and FPU feature bits selected by -march. */
177 static const arm_feature_set
*march_cpu_opt
= NULL
;
178 static arm_feature_set
*march_ext_opt
= NULL
;
179 static const arm_feature_set
*march_fpu_opt
= NULL
;
181 /* Feature bits selected by -mfpu. */
182 static const arm_feature_set
*mfpu_opt
= NULL
;
184 /* Constants for known architecture features. */
185 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
186 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
187 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
188 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
189 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
190 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
191 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
193 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
195 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
198 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
201 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
202 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
203 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
204 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
205 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
206 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
207 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
208 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
209 static const arm_feature_set arm_ext_v4t_5
=
210 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
211 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
212 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
213 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
214 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
215 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
216 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
217 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
218 /* Only for compatability of hint instructions. */
219 static const arm_feature_set arm_ext_v6k_v6t2
=
220 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
221 static const arm_feature_set arm_ext_v6_notm
=
222 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
223 static const arm_feature_set arm_ext_v6_dsp
=
224 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
225 static const arm_feature_set arm_ext_barrier
=
226 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
227 static const arm_feature_set arm_ext_msr
=
228 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
229 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
230 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
231 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
232 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
233 static const arm_feature_set arm_ext_v8r
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R
);
235 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
237 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
238 static const arm_feature_set arm_ext_m
=
239 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
240 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
241 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
242 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
243 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
244 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
245 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
246 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
247 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
248 static const arm_feature_set arm_ext_v8m_main
=
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
250 static const arm_feature_set arm_ext_v8_1m_main
=
251 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
252 /* Instructions in ARMv8-M only found in M profile architectures. */
253 static const arm_feature_set arm_ext_v8m_m_only
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
255 static const arm_feature_set arm_ext_v6t2_v8m
=
256 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
257 /* Instructions shared between ARMv8-A and ARMv8-M. */
258 static const arm_feature_set arm_ext_atomics
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
261 /* DSP instructions Tag_DSP_extension refers to. */
262 static const arm_feature_set arm_ext_dsp
=
263 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
265 static const arm_feature_set arm_ext_ras
=
266 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
267 /* FP16 instructions. */
268 static const arm_feature_set arm_ext_fp16
=
269 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
270 static const arm_feature_set arm_ext_fp16_fml
=
271 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
272 static const arm_feature_set arm_ext_v8_2
=
273 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
274 static const arm_feature_set arm_ext_v8_3
=
275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
276 static const arm_feature_set arm_ext_sb
=
277 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
278 static const arm_feature_set arm_ext_predres
=
279 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
280 static const arm_feature_set arm_ext_bf16
=
281 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
);
282 static const arm_feature_set arm_ext_i8mm
=
283 ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
);
284 static const arm_feature_set arm_ext_crc
=
285 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
);
286 static const arm_feature_set arm_ext_cde
=
287 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
);
288 static const arm_feature_set arm_ext_cde0
=
289 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE0
);
290 static const arm_feature_set arm_ext_cde1
=
291 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE1
);
292 static const arm_feature_set arm_ext_cde2
=
293 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE2
);
294 static const arm_feature_set arm_ext_cde3
=
295 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE3
);
296 static const arm_feature_set arm_ext_cde4
=
297 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE4
);
298 static const arm_feature_set arm_ext_cde5
=
299 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE5
);
300 static const arm_feature_set arm_ext_cde6
=
301 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE6
);
302 static const arm_feature_set arm_ext_cde7
=
303 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE7
);
305 static const arm_feature_set arm_arch_any
= ARM_ANY
;
306 static const arm_feature_set fpu_any
= FPU_ANY
;
307 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
308 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
309 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
311 static const arm_feature_set arm_cext_iwmmxt2
=
312 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
313 static const arm_feature_set arm_cext_iwmmxt
=
314 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
315 static const arm_feature_set arm_cext_xscale
=
316 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
317 static const arm_feature_set arm_cext_maverick
=
318 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
319 static const arm_feature_set fpu_fpa_ext_v1
=
320 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
321 static const arm_feature_set fpu_fpa_ext_v2
=
322 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
323 static const arm_feature_set fpu_vfp_ext_v1xd
=
324 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
325 static const arm_feature_set fpu_vfp_ext_v1
=
326 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
327 static const arm_feature_set fpu_vfp_ext_v2
=
328 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
329 static const arm_feature_set fpu_vfp_ext_v3xd
=
330 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
331 static const arm_feature_set fpu_vfp_ext_v3
=
332 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
333 static const arm_feature_set fpu_vfp_ext_d32
=
334 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
335 static const arm_feature_set fpu_neon_ext_v1
=
336 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
337 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
338 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
339 static const arm_feature_set mve_ext
=
340 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
);
341 static const arm_feature_set mve_fp_ext
=
342 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
);
343 /* Note: This has more than one bit set, which means using it with
344 mark_feature_used (which returns if *any* of the bits are set in the current
345 cpu variant) can give surprising results. */
346 static const arm_feature_set armv8m_fp
=
347 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16
);
349 static const arm_feature_set fpu_vfp_fp16
=
350 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
351 static const arm_feature_set fpu_neon_ext_fma
=
352 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
354 static const arm_feature_set fpu_vfp_ext_fma
=
355 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
356 static const arm_feature_set fpu_vfp_ext_armv8
=
357 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
358 static const arm_feature_set fpu_vfp_ext_armv8xd
=
359 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
360 static const arm_feature_set fpu_neon_ext_armv8
=
361 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
362 static const arm_feature_set fpu_crypto_ext_armv8
=
363 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
364 static const arm_feature_set fpu_neon_ext_v8_1
=
365 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
366 static const arm_feature_set fpu_neon_ext_dotprod
=
367 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
368 static const arm_feature_set pacbti_ext
=
369 ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI
);
371 static int mfloat_abi_opt
= -1;
372 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
374 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
375 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
377 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
378 /* Feature bits selected by the last -mcpu/-march or by the combination of the
379 last .cpu/.arch directive .arch_extension directives since that
381 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
382 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
383 static arm_feature_set selected_fpu
= FPU_NONE
;
384 /* Feature bits selected by the last .object_arch directive. */
385 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
386 /* Must be long enough to hold any of the names in arm_cpus. */
387 static const struct arm_ext_table
* selected_ctx_ext_table
= NULL
;
388 static char selected_cpu_name
[20];
390 extern FLONUM_TYPE generic_floating_point_number
;
392 /* Return if no cpu was selected on command-line. */
394 no_cpu_selected (void)
396 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
401 static int meabi_flags
= EABI_DEFAULT
;
403 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
406 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
411 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
416 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
417 symbolS
* GOT_symbol
;
420 /* 0: assemble for ARM,
421 1: assemble for Thumb,
422 2: assemble for Thumb even though target CPU does not support thumb
424 static int thumb_mode
= 0;
425 /* A value distinct from the possible values for thumb_mode that we
426 can use to record whether thumb_mode has been copied into the
427 tc_frag_data field of a frag. */
428 #define MODE_RECORDED (1 << 4)
430 /* Specifies the intrinsic IT insn behavior mode. */
431 enum implicit_it_mode
433 IMPLICIT_IT_MODE_NEVER
= 0x00,
434 IMPLICIT_IT_MODE_ARM
= 0x01,
435 IMPLICIT_IT_MODE_THUMB
= 0x02,
436 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
438 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
440 /* If unified_syntax is true, we are processing the new unified
441 ARM/Thumb syntax. Important differences from the old ARM mode:
443 - Immediate operands do not require a # prefix.
444 - Conditional affixes always appear at the end of the
445 instruction. (For backward compatibility, those instructions
446 that formerly had them in the middle, continue to accept them
448 - The IT instruction may appear, and if it does is validated
449 against subsequent conditional affixes. It does not generate
452 Important differences from the old Thumb mode:
454 - Immediate operands do not require a # prefix.
455 - Most of the V6T2 instructions are only available in unified mode.
456 - The .N and .W suffixes are recognized and honored (it is an error
457 if they cannot be honored).
458 - All instructions set the flags if and only if they have an 's' affix.
459 - Conditional affixes may be used. They are validated against
460 preceding IT instructions. Unlike ARM mode, you cannot use a
461 conditional affix except in the scope of an IT instruction. */
463 static bool unified_syntax
= false;
465 /* An immediate operand can start with #, and ld*, st*, pld operands
466 can contain [ and ]. We need to tell APP not to elide whitespace
467 before a [, which can appear as the first operand for pld.
468 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
469 const char arm_symbol_chars
[] = "#[]{}";
485 enum neon_el_type type
;
489 #define NEON_MAX_TYPE_ELS 5
493 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
497 enum pred_instruction_type
503 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
504 if inside, should be the last one. */
505 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
506 i.e. BKPT and NOP. */
507 IT_INSN
, /* The IT insn has been parsed. */
508 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
509 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
510 a predication code. */
511 MVE_UNPREDICABLE_INSN
, /* MVE instruction that is non-predicable. */
514 /* The maximum number of operands we need. */
515 #define ARM_IT_MAX_OPERANDS 6
516 #define ARM_IT_MAX_RELOCS 3
521 unsigned long instruction
;
523 unsigned int size_req
;
525 /* "uncond_value" is set to the value in place of the conditional field in
526 unconditional versions of the instruction, or -1u if nothing is
528 unsigned int uncond_value
;
529 struct neon_type vectype
;
530 /* This does not indicate an actual NEON instruction, only that
531 the mnemonic accepts neon-style type suffixes. */
533 /* Set to the opcode if the instruction needs relaxation.
534 Zero if the instruction is not relaxed. */
538 bfd_reloc_code_real_type type
;
541 } relocs
[ARM_IT_MAX_RELOCS
];
543 enum pred_instruction_type pred_insn_type
;
549 struct neon_type_el vectype
;
550 unsigned present
: 1; /* Operand present. */
551 unsigned isreg
: 1; /* Operand was a register. */
552 unsigned immisreg
: 2; /* .imm field is a second register.
553 0: imm, 1: gpr, 2: MVE Q-register. */
554 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
558 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
559 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
560 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
561 instructions. This allows us to disambiguate ARM <-> vector insns. */
562 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
563 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
564 unsigned isquad
: 1; /* Operand is SIMD quad register. */
565 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
566 unsigned iszr
: 1; /* Operand is ZR register. */
567 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
568 unsigned writeback
: 1; /* Operand has trailing ! */
569 unsigned preind
: 1; /* Preindexed address. */
570 unsigned postind
: 1; /* Postindexed address. */
571 unsigned negative
: 1; /* Index register was negated. */
572 unsigned shifted
: 1; /* Shift applied to operation. */
573 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
574 } operands
[ARM_IT_MAX_OPERANDS
];
577 static struct arm_it inst
;
579 #define NUM_FLOAT_VALS 8
581 const char * fp_const
[] =
583 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
586 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
596 #define CP_T_X 0x00008000
597 #define CP_T_Y 0x00400000
599 #define CONDS_BIT 0x00100000
600 #define LOAD_BIT 0x00100000
602 #define DOUBLE_LOAD_FLAG 0x00000001
606 const char * template_name
;
610 #define COND_ALWAYS 0xE
614 const char * template_name
;
618 struct asm_barrier_opt
620 const char * template_name
;
622 const arm_feature_set arch
;
625 /* The bit that distinguishes CPSR and SPSR. */
626 #define SPSR_BIT (1 << 22)
628 /* The individual PSR flag bits. */
629 #define PSR_c (1 << 16)
630 #define PSR_x (1 << 17)
631 #define PSR_s (1 << 18)
632 #define PSR_f (1 << 19)
637 bfd_reloc_code_real_type reloc
;
642 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
643 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
648 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
651 /* Bits for DEFINED field in neon_typed_alias. */
652 #define NTA_HASTYPE 1
653 #define NTA_HASINDEX 2
655 struct neon_typed_alias
657 unsigned char defined
;
659 struct neon_type_el eltype
;
662 /* ARM register categories. This includes coprocessor numbers and various
663 architecture extensions' registers. Each entry should have an error message
664 in reg_expected_msgs below. */
694 /* Structure for a hash table entry for a register.
695 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
696 information which states whether a vector type or index is specified (for a
697 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
703 unsigned char builtin
;
704 struct neon_typed_alias
* neon
;
707 /* Diagnostics used when we don't get a register of the expected type. */
708 const char * const reg_expected_msgs
[] =
710 [REG_TYPE_RN
] = N_("ARM register expected"),
711 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
712 [REG_TYPE_CN
] = N_("co-processor register expected"),
713 [REG_TYPE_FN
] = N_("FPA register expected"),
714 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
715 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
716 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
717 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
718 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
719 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
720 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
722 [REG_TYPE_VFC
] = N_("VFP system register expected"),
723 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
724 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
725 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
726 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
727 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
728 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
729 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
730 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
731 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
732 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
733 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
735 [REG_TYPE_ZR
] = N_("ZR register expected"),
738 /* Some well known registers that we refer to directly elsewhere. */
744 /* ARM instructions take 4bytes in the object file, Thumb instructions
750 /* Basic string to match. */
751 const char * template_name
;
753 /* Parameters to instruction. */
754 unsigned int operands
[8];
756 /* Conditional tag - see opcode_lookup. */
757 unsigned int tag
: 4;
759 /* Basic instruction code. */
762 /* Thumb-format instruction code. */
765 /* Which architecture variant provides this instruction. */
766 const arm_feature_set
* avariant
;
767 const arm_feature_set
* tvariant
;
769 /* Function to call to encode instruction in ARM format. */
770 void (* aencode
) (void);
772 /* Function to call to encode instruction in Thumb format. */
773 void (* tencode
) (void);
775 /* Indicates whether this instruction may be vector predicated. */
776 unsigned int mayBeVecPred
: 1;
779 /* Defines for various bits that we will want to toggle. */
780 #define INST_IMMEDIATE 0x02000000
781 #define OFFSET_REG 0x02000000
782 #define HWOFFSET_IMM 0x00400000
783 #define SHIFT_BY_REG 0x00000010
784 #define PRE_INDEX 0x01000000
785 #define INDEX_UP 0x00800000
786 #define WRITE_BACK 0x00200000
787 #define LDM_TYPE_2_OR_3 0x00400000
788 #define CPSI_MMOD 0x00020000
790 #define LITERAL_MASK 0xf000f000
791 #define OPCODE_MASK 0xfe1fffff
792 #define V4_STR_BIT 0x00000020
793 #define VLDR_VMOV_SAME 0x0040f000
795 #define T2_SUBS_PC_LR 0xf3de8f00
797 #define DATA_OP_SHIFT 21
798 #define SBIT_SHIFT 20
800 #define T2_OPCODE_MASK 0xfe1fffff
801 #define T2_DATA_OP_SHIFT 21
802 #define T2_SBIT_SHIFT 20
804 #define A_COND_MASK 0xf0000000
805 #define A_PUSH_POP_OP_MASK 0x0fff0000
807 /* Opcodes for pushing/poping registers to/from the stack. */
808 #define A1_OPCODE_PUSH 0x092d0000
809 #define A2_OPCODE_PUSH 0x052d0004
810 #define A2_OPCODE_POP 0x049d0004
812 /* Codes to distinguish the arithmetic instructions. */
823 #define OPCODE_CMP 10
824 #define OPCODE_CMN 11
825 #define OPCODE_ORR 12
826 #define OPCODE_MOV 13
827 #define OPCODE_BIC 14
828 #define OPCODE_MVN 15
830 #define T2_OPCODE_AND 0
831 #define T2_OPCODE_BIC 1
832 #define T2_OPCODE_ORR 2
833 #define T2_OPCODE_ORN 3
834 #define T2_OPCODE_EOR 4
835 #define T2_OPCODE_ADD 8
836 #define T2_OPCODE_ADC 10
837 #define T2_OPCODE_SBC 11
838 #define T2_OPCODE_SUB 13
839 #define T2_OPCODE_RSB 14
841 #define T_OPCODE_MUL 0x4340
842 #define T_OPCODE_TST 0x4200
843 #define T_OPCODE_CMN 0x42c0
844 #define T_OPCODE_NEG 0x4240
845 #define T_OPCODE_MVN 0x43c0
847 #define T_OPCODE_ADD_R3 0x1800
848 #define T_OPCODE_SUB_R3 0x1a00
849 #define T_OPCODE_ADD_HI 0x4400
850 #define T_OPCODE_ADD_ST 0xb000
851 #define T_OPCODE_SUB_ST 0xb080
852 #define T_OPCODE_ADD_SP 0xa800
853 #define T_OPCODE_ADD_PC 0xa000
854 #define T_OPCODE_ADD_I8 0x3000
855 #define T_OPCODE_SUB_I8 0x3800
856 #define T_OPCODE_ADD_I3 0x1c00
857 #define T_OPCODE_SUB_I3 0x1e00
859 #define T_OPCODE_ASR_R 0x4100
860 #define T_OPCODE_LSL_R 0x4080
861 #define T_OPCODE_LSR_R 0x40c0
862 #define T_OPCODE_ROR_R 0x41c0
863 #define T_OPCODE_ASR_I 0x1000
864 #define T_OPCODE_LSL_I 0x0000
865 #define T_OPCODE_LSR_I 0x0800
867 #define T_OPCODE_MOV_I8 0x2000
868 #define T_OPCODE_CMP_I8 0x2800
869 #define T_OPCODE_CMP_LR 0x4280
870 #define T_OPCODE_MOV_HR 0x4600
871 #define T_OPCODE_CMP_HR 0x4500
873 #define T_OPCODE_LDR_PC 0x4800
874 #define T_OPCODE_LDR_SP 0x9800
875 #define T_OPCODE_STR_SP 0x9000
876 #define T_OPCODE_LDR_IW 0x6800
877 #define T_OPCODE_STR_IW 0x6000
878 #define T_OPCODE_LDR_IH 0x8800
879 #define T_OPCODE_STR_IH 0x8000
880 #define T_OPCODE_LDR_IB 0x7800
881 #define T_OPCODE_STR_IB 0x7000
882 #define T_OPCODE_LDR_RW 0x5800
883 #define T_OPCODE_STR_RW 0x5000
884 #define T_OPCODE_LDR_RH 0x5a00
885 #define T_OPCODE_STR_RH 0x5200
886 #define T_OPCODE_LDR_RB 0x5c00
887 #define T_OPCODE_STR_RB 0x5400
889 #define T_OPCODE_PUSH 0xb400
890 #define T_OPCODE_POP 0xbc00
892 #define T_OPCODE_BRANCH 0xe000
894 #define THUMB_SIZE 2 /* Size of thumb instruction. */
895 #define THUMB_PP_PC_LR 0x0100
896 #define THUMB_LOAD_BIT 0x0800
897 #define THUMB2_LOAD_BIT 0x00100000
899 #define BAD_SYNTAX _("syntax error")
900 #define BAD_ARGS _("bad arguments to instruction")
901 #define BAD_SP _("r13 not allowed here")
902 #define BAD_PC _("r15 not allowed here")
903 #define BAD_ODD _("Odd register not allowed here")
904 #define BAD_EVEN _("Even register not allowed here")
905 #define BAD_COND _("instruction cannot be conditional")
906 #define BAD_OVERLAP _("registers may not be the same")
907 #define BAD_HIREG _("lo register required")
908 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
909 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
910 #define BAD_BRANCH _("branch must be last instruction in IT block")
911 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
912 #define BAD_NO_VPT _("instruction not allowed in VPT block")
913 #define BAD_NOT_IT _("instruction not allowed in IT block")
914 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
915 #define BAD_FPU _("selected FPU does not support instruction")
916 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
917 #define BAD_OUT_VPT \
918 _("vector predicated instruction should be in VPT/VPST block")
919 #define BAD_IT_COND _("incorrect condition in IT block")
920 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
921 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
922 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
923 #define BAD_PC_ADDRESSING \
924 _("cannot use register index with PC-relative addressing")
925 #define BAD_PC_WRITEBACK \
926 _("cannot use writeback with PC-relative addressing")
927 #define BAD_RANGE _("branch out of range")
928 #define BAD_FP16 _("selected processor does not support fp16 instruction")
929 #define BAD_BF16 _("selected processor does not support bf16 instruction")
930 #define BAD_CDE _("selected processor does not support cde instruction")
931 #define BAD_CDE_COPROC _("coprocessor for insn is not enabled for cde")
932 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
933 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
934 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
936 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
938 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
940 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
942 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
943 #define BAD_MVE_AUTO \
944 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
945 " use a valid -march or -mcpu option.")
946 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
947 "and source operands makes instruction UNPREDICTABLE")
948 #define BAD_EL_TYPE _("bad element type for instruction")
949 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
950 #define BAD_PACBTI _("selected processor does not support PACBTI extention")
952 static htab_t arm_ops_hsh
;
953 static htab_t arm_cond_hsh
;
954 static htab_t arm_vcond_hsh
;
955 static htab_t arm_shift_hsh
;
956 static htab_t arm_psr_hsh
;
957 static htab_t arm_v7m_psr_hsh
;
958 static htab_t arm_reg_hsh
;
959 static htab_t arm_reloc_hsh
;
960 static htab_t arm_barrier_opt_hsh
;
962 /* Stuff needed to resolve the label ambiguity
971 symbolS
* last_label_seen
;
972 static int label_is_thumb_function_name
= false;
974 /* Literal pool structure. Held on a per-section
975 and per-sub-section basis. */
977 #define MAX_LITERAL_POOL_SIZE 1024
978 typedef struct literal_pool
980 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
981 unsigned int next_free_entry
;
987 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
989 struct literal_pool
* next
;
990 unsigned int alignment
;
993 /* Pointer to a linked list of literal pools. */
994 literal_pool
* list_of_pools
= NULL
;
996 typedef enum asmfunc_states
999 WAITING_ASMFUNC_NAME
,
1003 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
1006 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
1008 static struct current_pred now_pred
;
1012 now_pred_compatible (int cond
)
1014 return (cond
& ~1) == (now_pred
.cc
& ~1);
1018 conditional_insn (void)
1020 return inst
.cond
!= COND_ALWAYS
;
1023 static int in_pred_block (void);
1025 static int handle_pred_state (void);
1027 static void force_automatic_it_block_close (void);
1029 static void it_fsm_post_encode (void);
1031 #define set_pred_insn_type(type) \
1034 inst.pred_insn_type = type; \
1035 if (handle_pred_state () == FAIL) \
1040 #define set_pred_insn_type_nonvoid(type, failret) \
1043 inst.pred_insn_type = type; \
1044 if (handle_pred_state () == FAIL) \
1049 #define set_pred_insn_type_last() \
1052 if (inst.cond == COND_ALWAYS) \
1053 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1055 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1059 /* Toggle value[pos]. */
1060 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1064 /* This array holds the chars that always start a comment. If the
1065 pre-processor is disabled, these aren't very useful. */
1066 char arm_comment_chars
[] = "@";
1068 /* This array holds the chars that only start a comment at the beginning of
1069 a line. If the line seems to have the form '# 123 filename'
1070 .line and .file directives will appear in the pre-processed output. */
1071 /* Note that input_file.c hand checks for '#' at the beginning of the
1072 first line of the input file. This is because the compiler outputs
1073 #NO_APP at the beginning of its output. */
1074 /* Also note that comments like this one will always work. */
1075 const char line_comment_chars
[] = "#";
1077 char arm_line_separator_chars
[] = ";";
1079 /* Chars that can be used to separate mant
1080 from exp in floating point numbers. */
1081 const char EXP_CHARS
[] = "eE";
1083 /* Chars that mean this number is a floating point constant. */
1084 /* As in 0f12.456 */
1085 /* or 0d1.2345e12 */
1087 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1089 /* Prefix characters that indicate the start of an immediate
1091 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1093 /* Separator character handling. */
1095 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1097 enum fp_16bit_format
1099 ARM_FP16_FORMAT_IEEE
= 0x1,
1100 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1101 ARM_FP16_FORMAT_DEFAULT
= 0x3
1104 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1108 skip_past_char (char ** str
, char c
)
1110 /* PR gas/14987: Allow for whitespace before the expected character. */
1111 skip_whitespace (*str
);
1122 #define skip_past_comma(str) skip_past_char (str, ',')
1124 /* Arithmetic expressions (possibly involving symbols). */
1126 /* Return TRUE if anything in the expression is a bignum. */
1129 walk_no_bignums (symbolS
* sp
)
1131 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1134 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1136 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1137 || (symbol_get_value_expression (sp
)->X_op_symbol
1138 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1144 static bool in_my_get_expression
= false;
1146 /* Third argument to my_get_expression. */
1147 #define GE_NO_PREFIX 0
1148 #define GE_IMM_PREFIX 1
1149 #define GE_OPT_PREFIX 2
1150 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1151 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1152 #define GE_OPT_PREFIX_BIG 3
1155 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1159 /* In unified syntax, all prefixes are optional. */
1161 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1164 switch (prefix_mode
)
1166 case GE_NO_PREFIX
: break;
1168 if (!is_immediate_prefix (**str
))
1170 inst
.error
= _("immediate expression requires a # prefix");
1176 case GE_OPT_PREFIX_BIG
:
1177 if (is_immediate_prefix (**str
))
1184 memset (ep
, 0, sizeof (expressionS
));
1186 save_in
= input_line_pointer
;
1187 input_line_pointer
= *str
;
1188 in_my_get_expression
= true;
1190 in_my_get_expression
= false;
1192 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1194 /* We found a bad or missing expression in md_operand(). */
1195 *str
= input_line_pointer
;
1196 input_line_pointer
= save_in
;
1197 if (inst
.error
== NULL
)
1198 inst
.error
= (ep
->X_op
== O_absent
1199 ? _("missing expression") :_("bad expression"));
1203 /* Get rid of any bignums now, so that we don't generate an error for which
1204 we can't establish a line number later on. Big numbers are never valid
1205 in instructions, which is where this routine is always called. */
1206 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1207 && (ep
->X_op
== O_big
1208 || (ep
->X_add_symbol
1209 && (walk_no_bignums (ep
->X_add_symbol
)
1211 && walk_no_bignums (ep
->X_op_symbol
))))))
1213 inst
.error
= _("invalid constant");
1214 *str
= input_line_pointer
;
1215 input_line_pointer
= save_in
;
1219 *str
= input_line_pointer
;
1220 input_line_pointer
= save_in
;
1224 /* Turn a string in input_line_pointer into a floating point constant
1225 of type TYPE, and store the appropriate bytes in *LITP. The number
1226 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1227 returned, or NULL on OK.
1229 Note that fp constants aren't represent in the normal way on the ARM.
1230 In big endian mode, things are as expected. However, in little endian
1231 mode fp constants are big-endian word-wise, and little-endian byte-wise
1232 within the words. For example, (double) 1.1 in big endian mode is
1233 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1234 the byte sequence 99 99 f1 3f 9a 99 99 99.
1236 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1239 md_atof (int type
, char * litP
, int * sizeP
)
1242 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1250 /* bfloat16, despite not being part of the IEEE specification, can also
1251 be handled by atof_ieee(). */
1282 return _("Unrecognized or unsupported floating point constant");
1285 t
= atof_ieee (input_line_pointer
, type
, words
);
1287 input_line_pointer
= t
;
1288 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1290 if (target_big_endian
|| prec
== 1)
1291 for (i
= 0; i
< prec
; i
++)
1293 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1294 litP
+= sizeof (LITTLENUM_TYPE
);
1296 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1297 for (i
= prec
- 1; i
>= 0; i
--)
1299 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1300 litP
+= sizeof (LITTLENUM_TYPE
);
1303 /* For a 4 byte float the order of elements in `words' is 1 0.
1304 For an 8 byte float the order is 1 0 3 2. */
1305 for (i
= 0; i
< prec
; i
+= 2)
1307 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1308 sizeof (LITTLENUM_TYPE
));
1309 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1310 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1311 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1317 /* We handle all bad expressions here, so that we can report the faulty
1318 instruction in the error message. */
1321 md_operand (expressionS
* exp
)
1323 if (in_my_get_expression
)
1324 exp
->X_op
= O_illegal
;
1327 /* Immediate values. */
1330 /* Generic immediate-value read function for use in directives.
1331 Accepts anything that 'expression' can fold to a constant.
1332 *val receives the number. */
1335 immediate_for_directive (int *val
)
1338 exp
.X_op
= O_illegal
;
1340 if (is_immediate_prefix (*input_line_pointer
))
1342 input_line_pointer
++;
1346 if (exp
.X_op
!= O_constant
)
1348 as_bad (_("expected #constant"));
1349 ignore_rest_of_line ();
1352 *val
= exp
.X_add_number
;
1357 /* Register parsing. */
1359 /* Generic register parser. CCP points to what should be the
1360 beginning of a register name. If it is indeed a valid register
1361 name, advance CCP over it and return the reg_entry structure;
1362 otherwise return NULL. Does not issue diagnostics. */
1364 static struct reg_entry
*
1365 arm_reg_parse_multi (char **ccp
)
1369 struct reg_entry
*reg
;
1371 skip_whitespace (start
);
1373 #ifdef REGISTER_PREFIX
1374 if (*start
!= REGISTER_PREFIX
)
1378 #ifdef OPTIONAL_REGISTER_PREFIX
1379 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1384 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1389 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1391 reg
= (struct reg_entry
*) str_hash_find_n (arm_reg_hsh
, start
, p
- start
);
1401 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1402 enum arm_reg_type type
)
1404 /* Alternative syntaxes are accepted for a few register classes. */
1411 /* Generic coprocessor register names are allowed for these. */
1412 if (reg
&& reg
->type
== REG_TYPE_CN
)
1417 /* For backward compatibility, a bare number is valid here. */
1419 unsigned long processor
= strtoul (start
, ccp
, 10);
1420 if (*ccp
!= start
&& processor
<= 15)
1425 case REG_TYPE_MMXWC
:
1426 /* WC includes WCG. ??? I'm not sure this is true for all
1427 instructions that take WC registers. */
1428 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1439 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1440 return value is the register number or FAIL. */
1443 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1446 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1449 /* Do not allow a scalar (reg+index) to parse as a register. */
1450 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1453 if (reg
&& reg
->type
== type
)
1456 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1463 /* Parse a Neon type specifier. *STR should point at the leading '.'
1464 character. Does no verification at this stage that the type fits the opcode
1471 Can all be legally parsed by this function.
1473 Fills in neon_type struct pointer with parsed information, and updates STR
1474 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1475 type, FAIL if not. */
1478 parse_neon_type (struct neon_type
*type
, char **str
)
1485 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1487 enum neon_el_type thistype
= NT_untyped
;
1488 unsigned thissize
= -1u;
1495 /* Just a size without an explicit type. */
1499 switch (TOLOWER (*ptr
))
1501 case 'i': thistype
= NT_integer
; break;
1502 case 'f': thistype
= NT_float
; break;
1503 case 'p': thistype
= NT_poly
; break;
1504 case 's': thistype
= NT_signed
; break;
1505 case 'u': thistype
= NT_unsigned
; break;
1507 thistype
= NT_float
;
1512 thistype
= NT_bfloat
;
1513 switch (TOLOWER (*(++ptr
)))
1517 thissize
= strtoul (ptr
, &ptr
, 10);
1520 as_bad (_("bad size %d in type specifier"), thissize
);
1524 case '0': case '1': case '2': case '3': case '4':
1525 case '5': case '6': case '7': case '8': case '9':
1527 as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1534 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1540 /* .f is an abbreviation for .f32. */
1541 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1546 thissize
= strtoul (ptr
, &ptr
, 10);
1548 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1551 as_bad (_("bad size %d in type specifier"), thissize
);
1559 type
->el
[type
->elems
].type
= thistype
;
1560 type
->el
[type
->elems
].size
= thissize
;
1565 /* Empty/missing type is not a successful parse. */
1566 if (type
->elems
== 0)
1574 /* Errors may be set multiple times during parsing or bit encoding
1575 (particularly in the Neon bits), but usually the earliest error which is set
1576 will be the most meaningful. Avoid overwriting it with later (cascading)
1577 errors by calling this function. */
1580 first_error (const char *err
)
1586 /* Parse a single type, e.g. ".s32", leading period included. */
1588 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1591 struct neon_type optype
;
1595 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1597 if (optype
.elems
== 1)
1598 *vectype
= optype
.el
[0];
1601 first_error (_("only one type should be specified for operand"));
1607 first_error (_("vector type expected"));
1619 /* Special meanings for indices (which have a range of 0-7), which will fit into
1622 #define NEON_ALL_LANES 15
1623 #define NEON_INTERLEAVE_LANES 14
1625 /* Record a use of the given feature. */
1627 record_feature_use (const arm_feature_set
*feature
)
1630 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1632 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1635 /* If the given feature available in the selected CPU, mark it as used.
1636 Returns TRUE iff feature is available. */
1638 mark_feature_used (const arm_feature_set
*feature
)
1641 /* Do not support the use of MVE only instructions when in auto-detection or
1643 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1644 && ARM_CPU_IS_ANY (cpu_variant
))
1646 first_error (BAD_MVE_AUTO
);
1649 /* Ensure the option is valid on the current architecture. */
1650 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1653 /* Add the appropriate architecture feature for the barrier option used.
1655 record_feature_use (feature
);
1660 /* Parse either a register or a scalar, with an optional type. Return the
1661 register number, and optionally fill in the actual type of the register
1662 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1663 type/index information in *TYPEINFO. */
1666 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1667 enum arm_reg_type
*rtype
,
1668 struct neon_typed_alias
*typeinfo
)
1671 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1672 struct neon_typed_alias atype
;
1673 struct neon_type_el parsetype
;
1677 atype
.eltype
.type
= NT_invtype
;
1678 atype
.eltype
.size
= -1;
1680 /* Try alternate syntax for some types of register. Note these are mutually
1681 exclusive with the Neon syntax extensions. */
1684 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1692 /* Undo polymorphism when a set of register types may be accepted. */
1693 if ((type
== REG_TYPE_NDQ
1694 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1695 || (type
== REG_TYPE_VFSD
1696 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1697 || (type
== REG_TYPE_NSDQ
1698 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1699 || reg
->type
== REG_TYPE_NQ
))
1700 || (type
== REG_TYPE_NSD
1701 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1702 || (type
== REG_TYPE_MMXWC
1703 && (reg
->type
== REG_TYPE_MMXWCG
)))
1704 type
= (enum arm_reg_type
) reg
->type
;
1706 if (type
== REG_TYPE_MQ
)
1708 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1711 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1714 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1716 first_error (_("expected MVE register [q0..q7]"));
1721 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1722 && (type
== REG_TYPE_NQ
))
1726 if (type
!= reg
->type
)
1732 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1734 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1736 first_error (_("can't redefine type for operand"));
1739 atype
.defined
|= NTA_HASTYPE
;
1740 atype
.eltype
= parsetype
;
1743 if (skip_past_char (&str
, '[') == SUCCESS
)
1745 if (type
!= REG_TYPE_VFD
1746 && !(type
== REG_TYPE_VFS
1747 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1748 && !(type
== REG_TYPE_NQ
1749 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1751 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1752 first_error (_("only D and Q registers may be indexed"));
1754 first_error (_("only D registers may be indexed"));
1758 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1760 first_error (_("can't change index for operand"));
1764 atype
.defined
|= NTA_HASINDEX
;
1766 if (skip_past_char (&str
, ']') == SUCCESS
)
1767 atype
.index
= NEON_ALL_LANES
;
1772 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1774 if (exp
.X_op
!= O_constant
)
1776 first_error (_("constant expression required"));
1780 if (skip_past_char (&str
, ']') == FAIL
)
1783 atype
.index
= exp
.X_add_number
;
1798 /* Like arm_reg_parse, but also allow the following extra features:
1799 - If RTYPE is non-zero, return the (possibly restricted) type of the
1800 register (e.g. Neon double or quad reg when either has been requested).
1801 - If this is a Neon vector type with additional type information, fill
1802 in the struct pointed to by VECTYPE (if non-NULL).
1803 This function will fault on encountering a scalar. */
1806 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1807 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1809 struct neon_typed_alias atype
;
1811 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1816 /* Do not allow regname(... to parse as a register. */
1820 /* Do not allow a scalar (reg+index) to parse as a register. */
1821 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1823 first_error (_("register operand expected, but got scalar"));
1828 *vectype
= atype
.eltype
;
1835 #define NEON_SCALAR_REG(X) ((X) >> 4)
1836 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1838 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1839 have enough information to be able to do a good job bounds-checking. So, we
1840 just do easy checks here, and do further checks later. */
1843 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1844 arm_reg_type reg_type
)
1848 struct neon_typed_alias atype
;
1851 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1869 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1872 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1874 first_error (_("scalar must have an index"));
1877 else if (atype
.index
>= reg_size
/ elsize
)
1879 first_error (_("scalar index out of range"));
1884 *type
= atype
.eltype
;
1888 return reg
* 16 + atype
.index
;
1891 /* Types of registers in a list. */
1904 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1907 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1913 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1915 /* We come back here if we get ranges concatenated by '+' or '|'. */
1918 skip_whitespace (str
);
1931 const char apsr_str
[] = "apsr";
1932 int apsr_str_len
= strlen (apsr_str
);
1934 reg
= arm_reg_parse (&str
, REG_TYPE_RN
);
1935 if (etype
== REGLIST_CLRM
)
1937 if (reg
== REG_SP
|| reg
== REG_PC
)
1939 else if (reg
== FAIL
1940 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1941 && !ISALPHA (*(str
+ apsr_str_len
)))
1944 str
+= apsr_str_len
;
1949 first_error (_("r0-r12, lr or APSR expected"));
1953 else /* etype == REGLIST_RN. */
1957 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1968 first_error (_("bad range in register list"));
1972 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1974 if (range
& (1 << i
))
1976 (_("Warning: duplicated register (r%d) in register list"),
1984 if (range
& (1 << reg
))
1985 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1987 else if (reg
<= cur_reg
)
1988 as_tsktsk (_("Warning: register range not in ascending order"));
1993 while (skip_past_comma (&str
) != FAIL
1994 || (in_range
= 1, *str
++ == '-'));
1997 if (skip_past_char (&str
, '}') == FAIL
)
1999 first_error (_("missing `}'"));
2003 else if (etype
== REGLIST_RN
)
2007 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
2010 if (exp
.X_op
== O_constant
)
2012 if (exp
.X_add_number
2013 != (exp
.X_add_number
& 0x0000ffff))
2015 inst
.error
= _("invalid register mask");
2019 if ((range
& exp
.X_add_number
) != 0)
2021 int regno
= range
& exp
.X_add_number
;
2024 regno
= (1 << regno
) - 1;
2026 (_("Warning: duplicated register (r%d) in register list"),
2030 range
|= exp
.X_add_number
;
2034 if (inst
.relocs
[0].type
!= 0)
2036 inst
.error
= _("expression too complex");
2040 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
2041 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
2042 inst
.relocs
[0].pc_rel
= 0;
2046 if (*str
== '|' || *str
== '+')
2052 while (another_range
);
2058 /* Parse a VFP register list. If the string is invalid return FAIL.
2059 Otherwise return the number of registers, and set PBASE to the first
2060 register. Parses registers of type ETYPE.
2061 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2062 - Q registers can be used to specify pairs of D registers
2063 - { } can be omitted from around a singleton register list
2064 FIXME: This is not implemented, as it would require backtracking in
2067 This could be done (the meaning isn't really ambiguous), but doesn't
2068 fit in well with the current parsing framework.
2069 - 32 D registers may be used (also true for VFPv3).
2070 FIXME: Types are ignored in these register lists, which is probably a
2074 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2075 bool *partial_match
)
2080 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2084 unsigned long mask
= 0;
2086 bool vpr_seen
= false;
2088 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2090 if (skip_past_char (&str
, '{') == FAIL
)
2092 inst
.error
= _("expecting {");
2099 case REGLIST_VFP_S_VPR
:
2100 regtype
= REG_TYPE_VFS
;
2105 case REGLIST_VFP_D_VPR
:
2106 regtype
= REG_TYPE_VFD
;
2109 case REGLIST_NEON_D
:
2110 regtype
= REG_TYPE_NDQ
;
2117 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2119 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2120 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2124 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2127 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2134 base_reg
= max_regs
;
2135 *partial_match
= false;
2139 unsigned int setmask
= 1, addregs
= 1;
2140 const char vpr_str
[] = "vpr";
2141 size_t vpr_str_len
= strlen (vpr_str
);
2143 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2147 if (new_base
== FAIL
2148 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2149 && !ISALPHA (*(str
+ vpr_str_len
))
2155 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2159 first_error (_("VPR expected last"));
2162 else if (new_base
== FAIL
)
2164 if (regtype
== REG_TYPE_VFS
)
2165 first_error (_("VFP single precision register or VPR "
2167 else /* regtype == REG_TYPE_VFD. */
2168 first_error (_("VFP/Neon double precision register or VPR "
2173 else if (new_base
== FAIL
)
2175 first_error (_(reg_expected_msgs
[regtype
]));
2179 *partial_match
= true;
2183 if (new_base
>= max_regs
)
2185 first_error (_("register out of range in list"));
2189 /* Note: a value of 2 * n is returned for the register Q<n>. */
2190 if (regtype
== REG_TYPE_NQ
)
2196 if (new_base
< base_reg
)
2197 base_reg
= new_base
;
2199 if (mask
& (setmask
<< new_base
))
2201 first_error (_("invalid register list"));
2205 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2207 as_tsktsk (_("register list not in ascending order"));
2211 mask
|= setmask
<< new_base
;
2214 if (*str
== '-') /* We have the start of a range expression */
2220 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2223 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2227 if (high_range
>= max_regs
)
2229 first_error (_("register out of range in list"));
2233 if (regtype
== REG_TYPE_NQ
)
2234 high_range
= high_range
+ 1;
2236 if (high_range
<= new_base
)
2238 inst
.error
= _("register range not in ascending order");
2242 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2244 if (mask
& (setmask
<< new_base
))
2246 inst
.error
= _("invalid register list");
2250 mask
|= setmask
<< new_base
;
2255 while (skip_past_comma (&str
) != FAIL
);
2259 /* Sanity check -- should have raised a parse error above. */
2260 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2265 if (expect_vpr
&& !vpr_seen
)
2267 first_error (_("VPR expected last"));
2271 /* Final test -- the registers must be consecutive. */
2273 for (i
= 0; i
< count
; i
++)
2275 if ((mask
& (1u << i
)) == 0)
2277 inst
.error
= _("non-contiguous register range");
2287 /* True if two alias types are the same. */
2290 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2298 if (a
->defined
!= b
->defined
)
2301 if ((a
->defined
& NTA_HASTYPE
) != 0
2302 && (a
->eltype
.type
!= b
->eltype
.type
2303 || a
->eltype
.size
!= b
->eltype
.size
))
2306 if ((a
->defined
& NTA_HASINDEX
) != 0
2307 && (a
->index
!= b
->index
))
2313 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2314 The base register is put in *PBASE.
2315 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2317 The register stride (minus one) is put in bit 4 of the return value.
2318 Bits [6:5] encode the list length (minus one).
2319 The type of the list elements is put in *ELTYPE, if non-NULL. */
2321 #define NEON_LANE(X) ((X) & 0xf)
2322 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2323 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2326 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2328 struct neon_type_el
*eltype
)
2335 int leading_brace
= 0;
2336 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2337 const char *const incr_error
= mve
? _("register stride must be 1") :
2338 _("register stride must be 1 or 2");
2339 const char *const type_error
= _("mismatched element/structure types in list");
2340 struct neon_typed_alias firsttype
;
2341 firsttype
.defined
= 0;
2342 firsttype
.eltype
.type
= NT_invtype
;
2343 firsttype
.eltype
.size
= -1;
2344 firsttype
.index
= -1;
2346 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2351 struct neon_typed_alias atype
;
2353 rtype
= REG_TYPE_MQ
;
2354 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2358 first_error (_(reg_expected_msgs
[rtype
]));
2365 if (rtype
== REG_TYPE_NQ
)
2371 else if (reg_incr
== -1)
2373 reg_incr
= getreg
- base_reg
;
2374 if (reg_incr
< 1 || reg_incr
> 2)
2376 first_error (_(incr_error
));
2380 else if (getreg
!= base_reg
+ reg_incr
* count
)
2382 first_error (_(incr_error
));
2386 if (! neon_alias_types_same (&atype
, &firsttype
))
2388 first_error (_(type_error
));
2392 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2396 struct neon_typed_alias htype
;
2397 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2399 lane
= NEON_INTERLEAVE_LANES
;
2400 else if (lane
!= NEON_INTERLEAVE_LANES
)
2402 first_error (_(type_error
));
2407 else if (reg_incr
!= 1)
2409 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2413 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2416 first_error (_(reg_expected_msgs
[rtype
]));
2419 if (! neon_alias_types_same (&htype
, &firsttype
))
2421 first_error (_(type_error
));
2424 count
+= hireg
+ dregs
- getreg
;
2428 /* If we're using Q registers, we can't use [] or [n] syntax. */
2429 if (rtype
== REG_TYPE_NQ
)
2435 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2439 else if (lane
!= atype
.index
)
2441 first_error (_(type_error
));
2445 else if (lane
== -1)
2446 lane
= NEON_INTERLEAVE_LANES
;
2447 else if (lane
!= NEON_INTERLEAVE_LANES
)
2449 first_error (_(type_error
));
2454 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2456 /* No lane set by [x]. We must be interleaving structures. */
2458 lane
= NEON_INTERLEAVE_LANES
;
2461 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2462 || (count
> 1 && reg_incr
== -1))
2464 first_error (_("error parsing element/structure list"));
2468 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2470 first_error (_("expected }"));
2478 *eltype
= firsttype
.eltype
;
2483 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2486 /* Parse an explicit relocation suffix on an expression. This is
2487 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2488 arm_reloc_hsh contains no entries, so this function can only
2489 succeed if there is no () after the word. Returns -1 on error,
2490 BFD_RELOC_UNUSED if there wasn't any suffix. */
2493 parse_reloc (char **str
)
2495 struct reloc_entry
*r
;
2499 return BFD_RELOC_UNUSED
;
2504 while (*q
&& *q
!= ')' && *q
!= ',')
2509 if ((r
= (struct reloc_entry
*)
2510 str_hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2517 /* Directives: register aliases. */
2519 static struct reg_entry
*
2520 insert_reg_alias (char *str
, unsigned number
, int type
)
2522 struct reg_entry
*new_reg
;
2525 if ((new_reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, str
)) != 0)
2527 if (new_reg
->builtin
)
2528 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2530 /* Only warn about a redefinition if it's not defined as the
2532 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2533 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2538 name
= xstrdup (str
);
2539 new_reg
= XNEW (struct reg_entry
);
2541 new_reg
->name
= name
;
2542 new_reg
->number
= number
;
2543 new_reg
->type
= type
;
2544 new_reg
->builtin
= false;
2545 new_reg
->neon
= NULL
;
2547 str_hash_insert (arm_reg_hsh
, name
, new_reg
, 0);
2553 insert_neon_reg_alias (char *str
, int number
, int type
,
2554 struct neon_typed_alias
*atype
)
2556 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2560 first_error (_("attempt to redefine typed alias"));
2566 reg
->neon
= XNEW (struct neon_typed_alias
);
2567 *reg
->neon
= *atype
;
2571 /* Look for the .req directive. This is of the form:
2573 new_register_name .req existing_register_name
2575 If we find one, or if it looks sufficiently like one that we want to
2576 handle any error here, return TRUE. Otherwise return FALSE. */
2579 create_register_alias (char * newname
, char *p
)
2581 struct reg_entry
*old
;
2582 char *oldname
, *nbuf
;
2585 /* The input scrubber ensures that whitespace after the mnemonic is
2586 collapsed to single spaces. */
2588 if (!startswith (oldname
, " .req "))
2592 if (*oldname
== '\0')
2595 old
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, oldname
);
2598 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2602 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2603 the desired alias name, and p points to its end. If not, then
2604 the desired alias name is in the global original_case_string. */
2605 #ifdef TC_CASE_SENSITIVE
2608 newname
= original_case_string
;
2609 nlen
= strlen (newname
);
2612 nbuf
= xmemdup0 (newname
, nlen
);
2614 /* Create aliases under the new name as stated; an all-lowercase
2615 version of the new name; and an all-uppercase version of the new
2617 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2619 for (p
= nbuf
; *p
; p
++)
2622 if (strncmp (nbuf
, newname
, nlen
))
2624 /* If this attempt to create an additional alias fails, do not bother
2625 trying to create the all-lower case alias. We will fail and issue
2626 a second, duplicate error message. This situation arises when the
2627 programmer does something like:
2630 The second .req creates the "Foo" alias but then fails to create
2631 the artificial FOO alias because it has already been created by the
2633 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2640 for (p
= nbuf
; *p
; p
++)
2643 if (strncmp (nbuf
, newname
, nlen
))
2644 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2651 /* Create a Neon typed/indexed register alias using directives, e.g.:
2656 These typed registers can be used instead of the types specified after the
2657 Neon mnemonic, so long as all operands given have types. Types can also be
2658 specified directly, e.g.:
2659 vadd d0.s32, d1.s32, d2.s32 */
2662 create_neon_reg_alias (char *newname
, char *p
)
2664 enum arm_reg_type basetype
;
2665 struct reg_entry
*basereg
;
2666 struct reg_entry mybasereg
;
2667 struct neon_type ntype
;
2668 struct neon_typed_alias typeinfo
;
2669 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2672 typeinfo
.defined
= 0;
2673 typeinfo
.eltype
.type
= NT_invtype
;
2674 typeinfo
.eltype
.size
= -1;
2675 typeinfo
.index
= -1;
2679 if (startswith (p
, " .dn "))
2680 basetype
= REG_TYPE_VFD
;
2681 else if (startswith (p
, " .qn "))
2682 basetype
= REG_TYPE_NQ
;
2691 basereg
= arm_reg_parse_multi (&p
);
2693 if (basereg
&& basereg
->type
!= basetype
)
2695 as_bad (_("bad type for register"));
2699 if (basereg
== NULL
)
2702 /* Try parsing as an integer. */
2703 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2704 if (exp
.X_op
!= O_constant
)
2706 as_bad (_("expression must be constant"));
2709 basereg
= &mybasereg
;
2710 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2716 typeinfo
= *basereg
->neon
;
2718 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2720 /* We got a type. */
2721 if (typeinfo
.defined
& NTA_HASTYPE
)
2723 as_bad (_("can't redefine the type of a register alias"));
2727 typeinfo
.defined
|= NTA_HASTYPE
;
2728 if (ntype
.elems
!= 1)
2730 as_bad (_("you must specify a single type only"));
2733 typeinfo
.eltype
= ntype
.el
[0];
2736 if (skip_past_char (&p
, '[') == SUCCESS
)
2739 /* We got a scalar index. */
2741 if (typeinfo
.defined
& NTA_HASINDEX
)
2743 as_bad (_("can't redefine the index of a scalar alias"));
2747 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2749 if (exp
.X_op
!= O_constant
)
2751 as_bad (_("scalar index must be constant"));
2755 typeinfo
.defined
|= NTA_HASINDEX
;
2756 typeinfo
.index
= exp
.X_add_number
;
2758 if (skip_past_char (&p
, ']') == FAIL
)
2760 as_bad (_("expecting ]"));
2765 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2766 the desired alias name, and p points to its end. If not, then
2767 the desired alias name is in the global original_case_string. */
2768 #ifdef TC_CASE_SENSITIVE
2769 namelen
= nameend
- newname
;
2771 newname
= original_case_string
;
2772 namelen
= strlen (newname
);
2775 namebuf
= xmemdup0 (newname
, namelen
);
2777 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2778 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2780 /* Insert name in all uppercase. */
2781 for (p
= namebuf
; *p
; p
++)
2784 if (strncmp (namebuf
, newname
, namelen
))
2785 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2786 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2788 /* Insert name in all lowercase. */
2789 for (p
= namebuf
; *p
; p
++)
2792 if (strncmp (namebuf
, newname
, namelen
))
2793 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2794 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2800 /* Should never be called, as .req goes between the alias and the
2801 register name, not at the beginning of the line. */
2804 s_req (int a ATTRIBUTE_UNUSED
)
2806 as_bad (_("invalid syntax for .req directive"));
2810 s_dn (int a ATTRIBUTE_UNUSED
)
2812 as_bad (_("invalid syntax for .dn directive"));
2816 s_qn (int a ATTRIBUTE_UNUSED
)
2818 as_bad (_("invalid syntax for .qn directive"));
2821 /* The .unreq directive deletes an alias which was previously defined
2822 by .req. For example:
2828 s_unreq (int a ATTRIBUTE_UNUSED
)
2833 name
= input_line_pointer
;
2835 while (*input_line_pointer
!= 0
2836 && *input_line_pointer
!= ' '
2837 && *input_line_pointer
!= '\n')
2838 ++input_line_pointer
;
2840 saved_char
= *input_line_pointer
;
2841 *input_line_pointer
= 0;
2844 as_bad (_("invalid syntax for .unreq directive"));
2847 struct reg_entry
*reg
2848 = (struct reg_entry
*) str_hash_find (arm_reg_hsh
, name
);
2851 as_bad (_("unknown register alias '%s'"), name
);
2852 else if (reg
->builtin
)
2853 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2860 str_hash_delete (arm_reg_hsh
, name
);
2861 free ((char *) reg
->name
);
2865 /* Also locate the all upper case and all lower case versions.
2866 Do not complain if we cannot find one or the other as it
2867 was probably deleted above. */
2869 nbuf
= strdup (name
);
2870 for (p
= nbuf
; *p
; p
++)
2872 reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, nbuf
);
2875 str_hash_delete (arm_reg_hsh
, nbuf
);
2876 free ((char *) reg
->name
);
2881 for (p
= nbuf
; *p
; p
++)
2883 reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, nbuf
);
2886 str_hash_delete (arm_reg_hsh
, nbuf
);
2887 free ((char *) reg
->name
);
2896 *input_line_pointer
= saved_char
;
2897 demand_empty_rest_of_line ();
2900 /* Directives: Instruction set selection. */
2903 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2904 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2905 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2906 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2908 /* Create a new mapping symbol for the transition to STATE. */
2911 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2914 const char * symname
;
2921 type
= BSF_NO_FLAGS
;
2925 type
= BSF_NO_FLAGS
;
2929 type
= BSF_NO_FLAGS
;
2935 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
2936 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2941 THUMB_SET_FUNC (symbolP
, 0);
2942 ARM_SET_THUMB (symbolP
, 0);
2943 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2947 THUMB_SET_FUNC (symbolP
, 1);
2948 ARM_SET_THUMB (symbolP
, 1);
2949 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2957 /* Save the mapping symbols for future reference. Also check that
2958 we do not place two mapping symbols at the same offset within a
2959 frag. We'll handle overlap between frags in
2960 check_mapping_symbols.
2962 If .fill or other data filling directive generates zero sized data,
2963 the mapping symbol for the following code will have the same value
2964 as the one generated for the data filling directive. In this case,
2965 we replace the old symbol with the new one at the same address. */
2968 if (frag
->tc_frag_data
.first_map
!= NULL
)
2970 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2971 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2973 frag
->tc_frag_data
.first_map
= symbolP
;
2975 if (frag
->tc_frag_data
.last_map
!= NULL
)
2977 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2978 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2979 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2981 frag
->tc_frag_data
.last_map
= symbolP
;
2984 /* We must sometimes convert a region marked as code to data during
2985 code alignment, if an odd number of bytes have to be padded. The
2986 code mapping symbol is pushed to an aligned address. */
2989 insert_data_mapping_symbol (enum mstate state
,
2990 valueT value
, fragS
*frag
, offsetT bytes
)
2992 /* If there was already a mapping symbol, remove it. */
2993 if (frag
->tc_frag_data
.last_map
!= NULL
2994 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2996 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
3000 know (frag
->tc_frag_data
.first_map
== symp
);
3001 frag
->tc_frag_data
.first_map
= NULL
;
3003 frag
->tc_frag_data
.last_map
= NULL
;
3004 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
3007 make_mapping_symbol (MAP_DATA
, value
, frag
);
3008 make_mapping_symbol (state
, value
+ bytes
, frag
);
3011 static void mapping_state_2 (enum mstate state
, int max_chars
);
3013 /* Set the mapping state to STATE. Only call this when about to
3014 emit some STATE bytes to the file. */
3016 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
3018 mapping_state (enum mstate state
)
3020 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3022 if (mapstate
== state
)
3023 /* The mapping symbol has already been emitted.
3024 There is nothing else to do. */
3027 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
3029 All ARM instructions require 4-byte alignment.
3030 (Almost) all Thumb instructions require 2-byte alignment.
3032 When emitting instructions into any section, mark the section
3035 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3036 but themselves require 2-byte alignment; this applies to some
3037 PC- relative forms. However, these cases will involve implicit
3038 literal pool generation or an explicit .align >=2, both of
3039 which will cause the section to me marked with sufficient
3040 alignment. Thus, we don't handle those cases here. */
3041 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
3043 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
3044 /* This case will be evaluated later. */
3047 mapping_state_2 (state
, 0);
3050 /* Same as mapping_state, but MAX_CHARS bytes have already been
3051 allocated. Put the mapping symbol that far back. */
3054 mapping_state_2 (enum mstate state
, int max_chars
)
3056 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3058 if (!SEG_NORMAL (now_seg
))
3061 if (mapstate
== state
)
3062 /* The mapping symbol has already been emitted.
3063 There is nothing else to do. */
3066 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
3067 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3069 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3070 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3073 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3076 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3077 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3081 #define mapping_state(x) ((void)0)
3082 #define mapping_state_2(x, y) ((void)0)
3085 /* Find the real, Thumb encoded start of a Thumb function. */
3089 find_real_start (symbolS
* symbolP
)
3092 const char * name
= S_GET_NAME (symbolP
);
3093 symbolS
* new_target
;
3095 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3096 #define STUB_NAME ".real_start_of"
3101 /* The compiler may generate BL instructions to local labels because
3102 it needs to perform a branch to a far away location. These labels
3103 do not have a corresponding ".real_start_of" label. We check
3104 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3105 the ".real_start_of" convention for nonlocal branches. */
3106 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3109 real_start
= concat (STUB_NAME
, name
, NULL
);
3110 new_target
= symbol_find (real_start
);
3113 if (new_target
== NULL
)
3115 as_warn (_("Failed to find real start of function: %s\n"), name
);
3116 new_target
= symbolP
;
3124 opcode_select (int width
)
3131 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3132 as_bad (_("selected processor does not support THUMB opcodes"));
3135 /* No need to force the alignment, since we will have been
3136 coming from ARM mode, which is word-aligned. */
3137 record_alignment (now_seg
, 1);
3144 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3145 as_bad (_("selected processor does not support ARM opcodes"));
3150 frag_align (2, 0, 0);
3152 record_alignment (now_seg
, 1);
3157 as_bad (_("invalid instruction size selected (%d)"), width
);
3162 s_arm (int ignore ATTRIBUTE_UNUSED
)
3165 demand_empty_rest_of_line ();
3169 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3172 demand_empty_rest_of_line ();
3176 s_code (int unused ATTRIBUTE_UNUSED
)
3180 temp
= get_absolute_expression ();
3185 opcode_select (temp
);
3189 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3194 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3196 /* If we are not already in thumb mode go into it, EVEN if
3197 the target processor does not support thumb instructions.
3198 This is used by gcc/config/arm/lib1funcs.asm for example
3199 to compile interworking support functions even if the
3200 target processor should not support interworking. */
3204 record_alignment (now_seg
, 1);
3207 demand_empty_rest_of_line ();
3211 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3215 /* The following label is the name/address of the start of a Thumb function.
3216 We need to know this for the interworking support. */
3217 label_is_thumb_function_name
= true;
3220 /* Perform a .set directive, but also mark the alias as
3221 being a thumb function. */
3224 s_thumb_set (int equiv
)
3226 /* XXX the following is a duplicate of the code for s_set() in read.c
3227 We cannot just call that code as we need to get at the symbol that
3234 /* Especial apologies for the random logic:
3235 This just grew, and could be parsed much more simply!
3237 delim
= get_symbol_name (& name
);
3238 end_name
= input_line_pointer
;
3239 (void) restore_line_pointer (delim
);
3241 if (*input_line_pointer
!= ',')
3244 as_bad (_("expected comma after name \"%s\""), name
);
3246 ignore_rest_of_line ();
3250 input_line_pointer
++;
3253 if (name
[0] == '.' && name
[1] == '\0')
3255 /* XXX - this should not happen to .thumb_set. */
3259 if ((symbolP
= symbol_find (name
)) == NULL
3260 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3263 /* When doing symbol listings, play games with dummy fragments living
3264 outside the normal fragment chain to record the file and line info
3266 if (listing
& LISTING_SYMBOLS
)
3268 extern struct list_info_struct
* listing_tail
;
3269 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3271 memset (dummy_frag
, 0, sizeof (fragS
));
3272 dummy_frag
->fr_type
= rs_fill
;
3273 dummy_frag
->line
= listing_tail
;
3274 symbolP
= symbol_new (name
, undefined_section
, dummy_frag
, 0);
3275 dummy_frag
->fr_symbol
= symbolP
;
3279 symbolP
= symbol_new (name
, undefined_section
, &zero_address_frag
, 0);
3282 /* "set" symbols are local unless otherwise specified. */
3283 SF_SET_LOCAL (symbolP
);
3284 #endif /* OBJ_COFF */
3285 } /* Make a new symbol. */
3287 symbol_table_insert (symbolP
);
3292 && S_IS_DEFINED (symbolP
)
3293 && S_GET_SEGMENT (symbolP
) != reg_section
)
3294 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3296 pseudo_set (symbolP
);
3298 demand_empty_rest_of_line ();
3300 /* XXX Now we come to the Thumb specific bit of code. */
3302 THUMB_SET_FUNC (symbolP
, 1);
3303 ARM_SET_THUMB (symbolP
, 1);
3304 #if defined OBJ_ELF || defined OBJ_COFF
3305 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3309 /* Directives: Mode selection. */
3311 /* .syntax [unified|divided] - choose the new unified syntax
3312 (same for Arm and Thumb encoding, modulo slight differences in what
3313 can be represented) or the old divergent syntax for each mode. */
3315 s_syntax (int unused ATTRIBUTE_UNUSED
)
3319 delim
= get_symbol_name (& name
);
3321 if (!strcasecmp (name
, "unified"))
3322 unified_syntax
= true;
3323 else if (!strcasecmp (name
, "divided"))
3324 unified_syntax
= false;
3327 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3330 (void) restore_line_pointer (delim
);
3331 demand_empty_rest_of_line ();
3334 /* Directives: sectioning and alignment. */
3337 s_bss (int ignore ATTRIBUTE_UNUSED
)
3339 /* We don't support putting frags in the BSS segment, we fake it by
3340 marking in_bss, then looking at s_skip for clues. */
3341 subseg_set (bss_section
, 0);
3342 demand_empty_rest_of_line ();
3344 #ifdef md_elf_section_change_hook
3345 md_elf_section_change_hook ();
3350 s_even (int ignore ATTRIBUTE_UNUSED
)
3352 /* Never make frag if expect extra pass. */
3354 frag_align (1, 0, 0);
3356 record_alignment (now_seg
, 1);
3358 demand_empty_rest_of_line ();
3361 /* Directives: CodeComposer Studio. */
3363 /* .ref (for CodeComposer Studio syntax only). */
3365 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3367 if (codecomposer_syntax
)
3368 ignore_rest_of_line ();
3370 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3373 /* If name is not NULL, then it is used for marking the beginning of a
3374 function, whereas if it is NULL then it means the function end. */
3376 asmfunc_debug (const char * name
)
3378 static const char * last_name
= NULL
;
3382 gas_assert (last_name
== NULL
);
3385 if (debug_type
== DEBUG_STABS
)
3386 stabs_generate_asm_func (name
, name
);
3390 gas_assert (last_name
!= NULL
);
3392 if (debug_type
== DEBUG_STABS
)
3393 stabs_generate_asm_endfunc (last_name
, last_name
);
3400 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3402 if (codecomposer_syntax
)
3404 switch (asmfunc_state
)
3406 case OUTSIDE_ASMFUNC
:
3407 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3410 case WAITING_ASMFUNC_NAME
:
3411 as_bad (_(".asmfunc repeated."));
3414 case WAITING_ENDASMFUNC
:
3415 as_bad (_(".asmfunc without function."));
3418 demand_empty_rest_of_line ();
3421 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3425 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3427 if (codecomposer_syntax
)
3429 switch (asmfunc_state
)
3431 case OUTSIDE_ASMFUNC
:
3432 as_bad (_(".endasmfunc without a .asmfunc."));
3435 case WAITING_ASMFUNC_NAME
:
3436 as_bad (_(".endasmfunc without function."));
3439 case WAITING_ENDASMFUNC
:
3440 asmfunc_state
= OUTSIDE_ASMFUNC
;
3441 asmfunc_debug (NULL
);
3444 demand_empty_rest_of_line ();
3447 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3451 s_ccs_def (int name
)
3453 if (codecomposer_syntax
)
3456 as_bad (_(".def pseudo-op only available with -mccs flag."));
3459 /* Directives: Literal pools. */
3461 static literal_pool
*
3462 find_literal_pool (void)
3464 literal_pool
* pool
;
3466 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3468 if (pool
->section
== now_seg
3469 && pool
->sub_section
== now_subseg
)
3476 static literal_pool
*
3477 find_or_make_literal_pool (void)
3479 /* Next literal pool ID number. */
3480 static unsigned int latest_pool_num
= 1;
3481 literal_pool
* pool
;
3483 pool
= find_literal_pool ();
3487 /* Create a new pool. */
3488 pool
= XNEW (literal_pool
);
3492 pool
->next_free_entry
= 0;
3493 pool
->section
= now_seg
;
3494 pool
->sub_section
= now_subseg
;
3495 pool
->next
= list_of_pools
;
3496 pool
->symbol
= NULL
;
3497 pool
->alignment
= 2;
3499 /* Add it to the list. */
3500 list_of_pools
= pool
;
3503 /* New pools, and emptied pools, will have a NULL symbol. */
3504 if (pool
->symbol
== NULL
)
3506 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3507 &zero_address_frag
, 0);
3508 pool
->id
= latest_pool_num
++;
3515 /* Add the literal in the global 'inst'
3516 structure to the relevant literal pool. */
3519 add_to_lit_pool (unsigned int nbytes
)
3521 #define PADDING_SLOT 0x1
3522 #define LIT_ENTRY_SIZE_MASK 0xFF
3523 literal_pool
* pool
;
3524 unsigned int entry
, pool_size
= 0;
3525 bool padding_slot_p
= false;
3531 imm1
= inst
.operands
[1].imm
;
3532 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3533 : inst
.relocs
[0].exp
.X_unsigned
? 0
3534 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3535 if (target_big_endian
)
3538 imm2
= inst
.operands
[1].imm
;
3542 pool
= find_or_make_literal_pool ();
3544 /* Check if this literal value is already in the pool. */
3545 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3549 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3550 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3551 && (pool
->literals
[entry
].X_add_number
3552 == inst
.relocs
[0].exp
.X_add_number
)
3553 && (pool
->literals
[entry
].X_md
== nbytes
)
3554 && (pool
->literals
[entry
].X_unsigned
3555 == inst
.relocs
[0].exp
.X_unsigned
))
3558 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3559 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3560 && (pool
->literals
[entry
].X_add_number
3561 == inst
.relocs
[0].exp
.X_add_number
)
3562 && (pool
->literals
[entry
].X_add_symbol
3563 == inst
.relocs
[0].exp
.X_add_symbol
)
3564 && (pool
->literals
[entry
].X_op_symbol
3565 == inst
.relocs
[0].exp
.X_op_symbol
)
3566 && (pool
->literals
[entry
].X_md
== nbytes
))
3569 else if ((nbytes
== 8)
3570 && !(pool_size
& 0x7)
3571 && ((entry
+ 1) != pool
->next_free_entry
)
3572 && (pool
->literals
[entry
].X_op
== O_constant
)
3573 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3574 && (pool
->literals
[entry
].X_unsigned
3575 == inst
.relocs
[0].exp
.X_unsigned
)
3576 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3577 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3578 && (pool
->literals
[entry
+ 1].X_unsigned
3579 == inst
.relocs
[0].exp
.X_unsigned
))
3582 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3583 if (padding_slot_p
&& (nbytes
== 4))
3589 /* Do we need to create a new entry? */
3590 if (entry
== pool
->next_free_entry
)
3592 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3594 inst
.error
= _("literal pool overflow");
3600 /* For 8-byte entries, we align to an 8-byte boundary,
3601 and split it into two 4-byte entries, because on 32-bit
3602 host, 8-byte constants are treated as big num, thus
3603 saved in "generic_bignum" which will be overwritten
3604 by later assignments.
3606 We also need to make sure there is enough space for
3609 We also check to make sure the literal operand is a
3611 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3612 || inst
.relocs
[0].exp
.X_op
== O_big
))
3614 inst
.error
= _("invalid type for literal pool");
3617 else if (pool_size
& 0x7)
3619 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3621 inst
.error
= _("literal pool overflow");
3625 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3626 pool
->literals
[entry
].X_op
= O_constant
;
3627 pool
->literals
[entry
].X_add_number
= 0;
3628 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3629 pool
->next_free_entry
+= 1;
3632 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3634 inst
.error
= _("literal pool overflow");
3638 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3639 pool
->literals
[entry
].X_op
= O_constant
;
3640 pool
->literals
[entry
].X_add_number
= imm1
;
3641 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3642 pool
->literals
[entry
++].X_md
= 4;
3643 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3644 pool
->literals
[entry
].X_op
= O_constant
;
3645 pool
->literals
[entry
].X_add_number
= imm2
;
3646 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3647 pool
->literals
[entry
].X_md
= 4;
3648 pool
->alignment
= 3;
3649 pool
->next_free_entry
+= 1;
3653 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3654 pool
->literals
[entry
].X_md
= 4;
3658 /* PR ld/12974: Record the location of the first source line to reference
3659 this entry in the literal pool. If it turns out during linking that the
3660 symbol does not exist we will be able to give an accurate line number for
3661 the (first use of the) missing reference. */
3662 if (debug_type
== DEBUG_DWARF2
)
3663 dwarf2_where (pool
->locs
+ entry
);
3665 pool
->next_free_entry
+= 1;
3667 else if (padding_slot_p
)
3669 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3670 pool
->literals
[entry
].X_md
= nbytes
;
3673 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3674 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3675 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3681 tc_start_label_without_colon (void)
3685 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3687 const char *label
= input_line_pointer
;
3689 while (!is_end_of_line
[(int) label
[-1]])
3694 as_bad (_("Invalid label '%s'"), label
);
3698 asmfunc_debug (label
);
3700 asmfunc_state
= WAITING_ENDASMFUNC
;
3706 /* Can't use symbol_new here, so have to create a symbol and then at
3707 a later date assign it a value. That's what these functions do. */
3710 symbol_locate (symbolS
* symbolP
,
3711 const char * name
, /* It is copied, the caller can modify. */
3712 segT segment
, /* Segment identifier (SEG_<something>). */
3713 valueT valu
, /* Symbol value. */
3714 fragS
* frag
) /* Associated fragment. */
3717 char * preserved_copy_of_name
;
3719 name_length
= strlen (name
) + 1; /* +1 for \0. */
3720 obstack_grow (¬es
, name
, name_length
);
3721 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3723 #ifdef tc_canonicalize_symbol_name
3724 preserved_copy_of_name
=
3725 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3728 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3730 S_SET_SEGMENT (symbolP
, segment
);
3731 S_SET_VALUE (symbolP
, valu
);
3732 symbol_clear_list_pointers (symbolP
);
3734 symbol_set_frag (symbolP
, frag
);
3736 /* Link to end of symbol chain. */
3738 extern int symbol_table_frozen
;
3740 if (symbol_table_frozen
)
3744 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3746 obj_symbol_new_hook (symbolP
);
3748 #ifdef tc_symbol_new_hook
3749 tc_symbol_new_hook (symbolP
);
3753 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3754 #endif /* DEBUG_SYMS */
3758 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3761 literal_pool
* pool
;
3764 pool
= find_literal_pool ();
3766 || pool
->symbol
== NULL
3767 || pool
->next_free_entry
== 0)
3770 /* Align pool as you have word accesses.
3771 Only make a frag if we have to. */
3773 frag_align (pool
->alignment
, 0, 0);
3775 record_alignment (now_seg
, 2);
3778 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3779 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3781 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3783 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3784 (valueT
) frag_now_fix (), frag_now
);
3785 symbol_table_insert (pool
->symbol
);
3787 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3789 #if defined OBJ_COFF || defined OBJ_ELF
3790 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3793 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3796 if (debug_type
== DEBUG_DWARF2
)
3797 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3799 /* First output the expression in the instruction to the pool. */
3800 emit_expr (&(pool
->literals
[entry
]),
3801 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3804 /* Mark the pool as empty. */
3805 pool
->next_free_entry
= 0;
3806 pool
->symbol
= NULL
;
3810 /* Forward declarations for functions below, in the MD interface
3812 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3813 static valueT
create_unwind_entry (int);
3814 static void start_unwind_section (const segT
, int);
3815 static void add_unwind_opcode (valueT
, int);
3816 static void flush_pending_unwind (void);
3818 /* Directives: Data. */
3821 s_arm_elf_cons (int nbytes
)
3825 #ifdef md_flush_pending_output
3826 md_flush_pending_output ();
3829 if (is_it_end_of_statement ())
3831 demand_empty_rest_of_line ();
3835 #ifdef md_cons_align
3836 md_cons_align (nbytes
);
3839 mapping_state (MAP_DATA
);
3843 char *base
= input_line_pointer
;
3847 if (exp
.X_op
!= O_symbol
)
3848 emit_expr (&exp
, (unsigned int) nbytes
);
3851 char *before_reloc
= input_line_pointer
;
3852 reloc
= parse_reloc (&input_line_pointer
);
3855 as_bad (_("unrecognized relocation suffix"));
3856 ignore_rest_of_line ();
3859 else if (reloc
== BFD_RELOC_UNUSED
)
3860 emit_expr (&exp
, (unsigned int) nbytes
);
3863 reloc_howto_type
*howto
= (reloc_howto_type
*)
3864 bfd_reloc_type_lookup (stdoutput
,
3865 (bfd_reloc_code_real_type
) reloc
);
3866 int size
= bfd_get_reloc_size (howto
);
3868 if (reloc
== BFD_RELOC_ARM_PLT32
)
3870 as_bad (_("(plt) is only valid on branch targets"));
3871 reloc
= BFD_RELOC_UNUSED
;
3876 as_bad (ngettext ("%s relocations do not fit in %d byte",
3877 "%s relocations do not fit in %d bytes",
3879 howto
->name
, nbytes
);
3882 /* We've parsed an expression stopping at O_symbol.
3883 But there may be more expression left now that we
3884 have parsed the relocation marker. Parse it again.
3885 XXX Surely there is a cleaner way to do this. */
3886 char *p
= input_line_pointer
;
3888 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3890 memcpy (save_buf
, base
, input_line_pointer
- base
);
3891 memmove (base
+ (input_line_pointer
- before_reloc
),
3892 base
, before_reloc
- base
);
3894 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3896 memcpy (base
, save_buf
, p
- base
);
3898 offset
= nbytes
- size
;
3899 p
= frag_more (nbytes
);
3900 memset (p
, 0, nbytes
);
3901 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3902 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3908 while (*input_line_pointer
++ == ',');
3910 /* Put terminator back into stream. */
3911 input_line_pointer
--;
3912 demand_empty_rest_of_line ();
3915 /* Emit an expression containing a 32-bit thumb instruction.
3916 Implementation based on put_thumb32_insn. */
3919 emit_thumb32_expr (expressionS
* exp
)
3921 expressionS exp_high
= *exp
;
3923 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3924 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3925 exp
->X_add_number
&= 0xffff;
3926 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3929 /* Guess the instruction size based on the opcode. */
3932 thumb_insn_size (int opcode
)
3934 if ((unsigned int) opcode
< 0xe800u
)
3936 else if ((unsigned int) opcode
>= 0xe8000000u
)
3943 emit_insn (expressionS
*exp
, int nbytes
)
3947 if (exp
->X_op
== O_constant
)
3952 size
= thumb_insn_size (exp
->X_add_number
);
3956 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3958 as_bad (_(".inst.n operand too big. "\
3959 "Use .inst.w instead"));
3964 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3965 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3967 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3969 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3970 emit_thumb32_expr (exp
);
3972 emit_expr (exp
, (unsigned int) size
);
3974 it_fsm_post_encode ();
3978 as_bad (_("cannot determine Thumb instruction size. " \
3979 "Use .inst.n/.inst.w instead"));
3982 as_bad (_("constant expression required"));
3987 /* Like s_arm_elf_cons but do not use md_cons_align and
3988 set the mapping state to MAP_ARM/MAP_THUMB. */
3991 s_arm_elf_inst (int nbytes
)
3993 if (is_it_end_of_statement ())
3995 demand_empty_rest_of_line ();
3999 /* Calling mapping_state () here will not change ARM/THUMB,
4000 but will ensure not to be in DATA state. */
4003 mapping_state (MAP_THUMB
);
4008 as_bad (_("width suffixes are invalid in ARM mode"));
4009 ignore_rest_of_line ();
4015 mapping_state (MAP_ARM
);
4024 if (! emit_insn (& exp
, nbytes
))
4026 ignore_rest_of_line ();
4030 while (*input_line_pointer
++ == ',');
4032 /* Put terminator back into stream. */
4033 input_line_pointer
--;
4034 demand_empty_rest_of_line ();
4037 /* Parse a .rel31 directive. */
4040 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
4047 if (*input_line_pointer
== '1')
4048 highbit
= 0x80000000;
4049 else if (*input_line_pointer
!= '0')
4050 as_bad (_("expected 0 or 1"));
4052 input_line_pointer
++;
4053 if (*input_line_pointer
!= ',')
4054 as_bad (_("missing comma"));
4055 input_line_pointer
++;
4057 #ifdef md_flush_pending_output
4058 md_flush_pending_output ();
4061 #ifdef md_cons_align
4065 mapping_state (MAP_DATA
);
4070 md_number_to_chars (p
, highbit
, 4);
4071 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4072 BFD_RELOC_ARM_PREL31
);
4074 demand_empty_rest_of_line ();
4077 /* Directives: AEABI stack-unwind tables. */
4079 /* Parse an unwind_fnstart directive. Simply records the current location. */
4082 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4084 demand_empty_rest_of_line ();
4085 if (unwind
.proc_start
)
4087 as_bad (_("duplicate .fnstart directive"));
4091 /* Mark the start of the function. */
4092 unwind
.proc_start
= expr_build_dot ();
4094 /* Reset the rest of the unwind info. */
4095 unwind
.opcode_count
= 0;
4096 unwind
.table_entry
= NULL
;
4097 unwind
.personality_routine
= NULL
;
4098 unwind
.personality_index
= -1;
4099 unwind
.frame_size
= 0;
4100 unwind
.fp_offset
= 0;
4101 unwind
.fp_reg
= REG_SP
;
4103 unwind
.sp_restored
= 0;
4107 /* Parse a handlerdata directive. Creates the exception handling table entry
4108 for the function. */
4111 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4113 demand_empty_rest_of_line ();
4114 if (!unwind
.proc_start
)
4115 as_bad (MISSING_FNSTART
);
4117 if (unwind
.table_entry
)
4118 as_bad (_("duplicate .handlerdata directive"));
4120 create_unwind_entry (1);
4123 /* Parse an unwind_fnend directive. Generates the index table entry. */
4126 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4131 unsigned int marked_pr_dependency
;
4133 demand_empty_rest_of_line ();
4135 if (!unwind
.proc_start
)
4137 as_bad (_(".fnend directive without .fnstart"));
4141 /* Add eh table entry. */
4142 if (unwind
.table_entry
== NULL
)
4143 val
= create_unwind_entry (0);
4147 /* Add index table entry. This is two words. */
4148 start_unwind_section (unwind
.saved_seg
, 1);
4149 frag_align (2, 0, 0);
4150 record_alignment (now_seg
, 2);
4152 ptr
= frag_more (8);
4154 where
= frag_now_fix () - 8;
4156 /* Self relative offset of the function start. */
4157 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4158 BFD_RELOC_ARM_PREL31
);
4160 /* Indicate dependency on EHABI-defined personality routines to the
4161 linker, if it hasn't been done already. */
4162 marked_pr_dependency
4163 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4164 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4165 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4167 static const char *const name
[] =
4169 "__aeabi_unwind_cpp_pr0",
4170 "__aeabi_unwind_cpp_pr1",
4171 "__aeabi_unwind_cpp_pr2"
4173 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4174 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4175 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4176 |= 1 << unwind
.personality_index
;
4180 /* Inline exception table entry. */
4181 md_number_to_chars (ptr
+ 4, val
, 4);
4183 /* Self relative offset of the table entry. */
4184 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4185 BFD_RELOC_ARM_PREL31
);
4187 /* Restore the original section. */
4188 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4190 unwind
.proc_start
= NULL
;
4194 /* Parse an unwind_cantunwind directive. */
4197 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4199 demand_empty_rest_of_line ();
4200 if (!unwind
.proc_start
)
4201 as_bad (MISSING_FNSTART
);
4203 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4204 as_bad (_("personality routine specified for cantunwind frame"));
4206 unwind
.personality_index
= -2;
4210 /* Parse a personalityindex directive. */
4213 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4217 if (!unwind
.proc_start
)
4218 as_bad (MISSING_FNSTART
);
4220 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4221 as_bad (_("duplicate .personalityindex directive"));
4225 if (exp
.X_op
!= O_constant
4226 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4228 as_bad (_("bad personality routine number"));
4229 ignore_rest_of_line ();
4233 unwind
.personality_index
= exp
.X_add_number
;
4235 demand_empty_rest_of_line ();
4239 /* Parse a personality directive. */
4242 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4246 if (!unwind
.proc_start
)
4247 as_bad (MISSING_FNSTART
);
4249 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4250 as_bad (_("duplicate .personality directive"));
4252 c
= get_symbol_name (& name
);
4253 p
= input_line_pointer
;
4255 ++ input_line_pointer
;
4256 unwind
.personality_routine
= symbol_find_or_make (name
);
4258 demand_empty_rest_of_line ();
4262 /* Parse a directive saving core registers. */
4265 s_arm_unwind_save_core (void)
4271 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4274 as_bad (_("expected register list"));
4275 ignore_rest_of_line ();
4279 demand_empty_rest_of_line ();
4281 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4282 into .unwind_save {..., sp...}. We aren't bothered about the value of
4283 ip because it is clobbered by calls. */
4284 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4285 && (range
& 0x3000) == 0x1000)
4287 unwind
.opcode_count
--;
4288 unwind
.sp_restored
= 0;
4289 range
= (range
| 0x2000) & ~0x1000;
4290 unwind
.pending_offset
= 0;
4296 /* See if we can use the short opcodes. These pop a block of up to 8
4297 registers starting with r4, plus maybe r14. */
4298 for (n
= 0; n
< 8; n
++)
4300 /* Break at the first non-saved register. */
4301 if ((range
& (1 << (n
+ 4))) == 0)
4304 /* See if there are any other bits set. */
4305 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4307 /* Use the long form. */
4308 op
= 0x8000 | ((range
>> 4) & 0xfff);
4309 add_unwind_opcode (op
, 2);
4313 /* Use the short form. */
4315 op
= 0xa8; /* Pop r14. */
4317 op
= 0xa0; /* Do not pop r14. */
4319 add_unwind_opcode (op
, 1);
4326 op
= 0xb100 | (range
& 0xf);
4327 add_unwind_opcode (op
, 2);
4330 /* Record the number of bytes pushed. */
4331 for (n
= 0; n
< 16; n
++)
4333 if (range
& (1 << n
))
4334 unwind
.frame_size
+= 4;
4339 /* Parse a directive saving FPA registers. */
4342 s_arm_unwind_save_fpa (int reg
)
4348 /* Get Number of registers to transfer. */
4349 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4352 exp
.X_op
= O_illegal
;
4354 if (exp
.X_op
!= O_constant
)
4356 as_bad (_("expected , <constant>"));
4357 ignore_rest_of_line ();
4361 num_regs
= exp
.X_add_number
;
4363 if (num_regs
< 1 || num_regs
> 4)
4365 as_bad (_("number of registers must be in the range [1:4]"));
4366 ignore_rest_of_line ();
4370 demand_empty_rest_of_line ();
4375 op
= 0xb4 | (num_regs
- 1);
4376 add_unwind_opcode (op
, 1);
4381 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4382 add_unwind_opcode (op
, 2);
4384 unwind
.frame_size
+= num_regs
* 12;
4388 /* Parse a directive saving VFP registers for ARMv6 and above. */
4391 s_arm_unwind_save_vfp_armv6 (void)
4396 int num_vfpv3_regs
= 0;
4397 int num_regs_below_16
;
4400 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4404 as_bad (_("expected register list"));
4405 ignore_rest_of_line ();
4409 demand_empty_rest_of_line ();
4411 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4412 than FSTMX/FLDMX-style ones). */
4414 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4416 num_vfpv3_regs
= count
;
4417 else if (start
+ count
> 16)
4418 num_vfpv3_regs
= start
+ count
- 16;
4420 if (num_vfpv3_regs
> 0)
4422 int start_offset
= start
> 16 ? start
- 16 : 0;
4423 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4424 add_unwind_opcode (op
, 2);
4427 /* Generate opcode for registers numbered in the range 0 .. 15. */
4428 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4429 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4430 if (num_regs_below_16
> 0)
4432 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4433 add_unwind_opcode (op
, 2);
4436 unwind
.frame_size
+= count
* 8;
4440 /* Parse a directive saving VFP registers for pre-ARMv6. */
4443 s_arm_unwind_save_vfp (void)
4450 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4454 as_bad (_("expected register list"));
4455 ignore_rest_of_line ();
4459 demand_empty_rest_of_line ();
4464 op
= 0xb8 | (count
- 1);
4465 add_unwind_opcode (op
, 1);
4470 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4471 add_unwind_opcode (op
, 2);
4473 unwind
.frame_size
+= count
* 8 + 4;
4477 /* Parse a directive saving iWMMXt data registers. */
4480 s_arm_unwind_save_mmxwr (void)
4488 if (*input_line_pointer
== '{')
4489 input_line_pointer
++;
4493 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4497 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4502 as_tsktsk (_("register list not in ascending order"));
4505 if (*input_line_pointer
== '-')
4507 input_line_pointer
++;
4508 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4511 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4514 else if (reg
>= hi_reg
)
4516 as_bad (_("bad register range"));
4519 for (; reg
< hi_reg
; reg
++)
4523 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4525 skip_past_char (&input_line_pointer
, '}');
4527 demand_empty_rest_of_line ();
4529 /* Generate any deferred opcodes because we're going to be looking at
4531 flush_pending_unwind ();
4533 for (i
= 0; i
< 16; i
++)
4535 if (mask
& (1 << i
))
4536 unwind
.frame_size
+= 8;
4539 /* Attempt to combine with a previous opcode. We do this because gcc
4540 likes to output separate unwind directives for a single block of
4542 if (unwind
.opcode_count
> 0)
4544 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4545 if ((i
& 0xf8) == 0xc0)
4548 /* Only merge if the blocks are contiguous. */
4551 if ((mask
& 0xfe00) == (1 << 9))
4553 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4554 unwind
.opcode_count
--;
4557 else if (i
== 6 && unwind
.opcode_count
>= 2)
4559 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4563 op
= 0xffff << (reg
- 1);
4565 && ((mask
& op
) == (1u << (reg
- 1))))
4567 op
= (1 << (reg
+ i
+ 1)) - 1;
4568 op
&= ~((1 << reg
) - 1);
4570 unwind
.opcode_count
-= 2;
4577 /* We want to generate opcodes in the order the registers have been
4578 saved, ie. descending order. */
4579 for (reg
= 15; reg
>= -1; reg
--)
4581 /* Save registers in blocks. */
4583 || !(mask
& (1 << reg
)))
4585 /* We found an unsaved reg. Generate opcodes to save the
4592 op
= 0xc0 | (hi_reg
- 10);
4593 add_unwind_opcode (op
, 1);
4598 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4599 add_unwind_opcode (op
, 2);
4608 ignore_rest_of_line ();
4612 s_arm_unwind_save_mmxwcg (void)
4619 if (*input_line_pointer
== '{')
4620 input_line_pointer
++;
4622 skip_whitespace (input_line_pointer
);
4626 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4630 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4636 as_tsktsk (_("register list not in ascending order"));
4639 if (*input_line_pointer
== '-')
4641 input_line_pointer
++;
4642 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4645 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4648 else if (reg
>= hi_reg
)
4650 as_bad (_("bad register range"));
4653 for (; reg
< hi_reg
; reg
++)
4657 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4659 skip_past_char (&input_line_pointer
, '}');
4661 demand_empty_rest_of_line ();
4663 /* Generate any deferred opcodes because we're going to be looking at
4665 flush_pending_unwind ();
4667 for (reg
= 0; reg
< 16; reg
++)
4669 if (mask
& (1 << reg
))
4670 unwind
.frame_size
+= 4;
4673 add_unwind_opcode (op
, 2);
4676 ignore_rest_of_line ();
4680 /* Parse an unwind_save directive.
4681 If the argument is non-zero, this is a .vsave directive. */
4684 s_arm_unwind_save (int arch_v6
)
4687 struct reg_entry
*reg
;
4688 bool had_brace
= false;
4690 if (!unwind
.proc_start
)
4691 as_bad (MISSING_FNSTART
);
4693 /* Figure out what sort of save we have. */
4694 peek
= input_line_pointer
;
4702 reg
= arm_reg_parse_multi (&peek
);
4706 as_bad (_("register expected"));
4707 ignore_rest_of_line ();
4716 as_bad (_("FPA .unwind_save does not take a register list"));
4717 ignore_rest_of_line ();
4720 input_line_pointer
= peek
;
4721 s_arm_unwind_save_fpa (reg
->number
);
4725 s_arm_unwind_save_core ();
4730 s_arm_unwind_save_vfp_armv6 ();
4732 s_arm_unwind_save_vfp ();
4735 case REG_TYPE_MMXWR
:
4736 s_arm_unwind_save_mmxwr ();
4739 case REG_TYPE_MMXWCG
:
4740 s_arm_unwind_save_mmxwcg ();
4744 as_bad (_(".unwind_save does not support this kind of register"));
4745 ignore_rest_of_line ();
4750 /* Parse an unwind_movsp directive. */
4753 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4759 if (!unwind
.proc_start
)
4760 as_bad (MISSING_FNSTART
);
4762 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4765 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4766 ignore_rest_of_line ();
4770 /* Optional constant. */
4771 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4773 if (immediate_for_directive (&offset
) == FAIL
)
4779 demand_empty_rest_of_line ();
4781 if (reg
== REG_SP
|| reg
== REG_PC
)
4783 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4787 if (unwind
.fp_reg
!= REG_SP
)
4788 as_bad (_("unexpected .unwind_movsp directive"));
4790 /* Generate opcode to restore the value. */
4792 add_unwind_opcode (op
, 1);
4794 /* Record the information for later. */
4795 unwind
.fp_reg
= reg
;
4796 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4797 unwind
.sp_restored
= 1;
4800 /* Parse an unwind_pad directive. */
4803 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4807 if (!unwind
.proc_start
)
4808 as_bad (MISSING_FNSTART
);
4810 if (immediate_for_directive (&offset
) == FAIL
)
4815 as_bad (_("stack increment must be multiple of 4"));
4816 ignore_rest_of_line ();
4820 /* Don't generate any opcodes, just record the details for later. */
4821 unwind
.frame_size
+= offset
;
4822 unwind
.pending_offset
+= offset
;
4824 demand_empty_rest_of_line ();
4827 /* Parse an unwind_setfp directive. */
4830 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4836 if (!unwind
.proc_start
)
4837 as_bad (MISSING_FNSTART
);
4839 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4840 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4843 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4845 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4847 as_bad (_("expected <reg>, <reg>"));
4848 ignore_rest_of_line ();
4852 /* Optional constant. */
4853 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4855 if (immediate_for_directive (&offset
) == FAIL
)
4861 demand_empty_rest_of_line ();
4863 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4865 as_bad (_("register must be either sp or set by a previous"
4866 "unwind_movsp directive"));
4870 /* Don't generate any opcodes, just record the information for later. */
4871 unwind
.fp_reg
= fp_reg
;
4873 if (sp_reg
== REG_SP
)
4874 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4876 unwind
.fp_offset
-= offset
;
4879 /* Parse an unwind_raw directive. */
4882 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4885 /* This is an arbitrary limit. */
4886 unsigned char op
[16];
4889 if (!unwind
.proc_start
)
4890 as_bad (MISSING_FNSTART
);
4893 if (exp
.X_op
== O_constant
4894 && skip_past_comma (&input_line_pointer
) != FAIL
)
4896 unwind
.frame_size
+= exp
.X_add_number
;
4900 exp
.X_op
= O_illegal
;
4902 if (exp
.X_op
!= O_constant
)
4904 as_bad (_("expected <offset>, <opcode>"));
4905 ignore_rest_of_line ();
4911 /* Parse the opcode. */
4916 as_bad (_("unwind opcode too long"));
4917 ignore_rest_of_line ();
4919 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4921 as_bad (_("invalid unwind opcode"));
4922 ignore_rest_of_line ();
4925 op
[count
++] = exp
.X_add_number
;
4927 /* Parse the next byte. */
4928 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4934 /* Add the opcode bytes in reverse order. */
4936 add_unwind_opcode (op
[count
], 1);
4938 demand_empty_rest_of_line ();
4942 /* Parse a .eabi_attribute directive. */
4945 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4947 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4949 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4950 attributes_set_explicitly
[tag
] = 1;
4953 /* Emit a tls fix for the symbol. */
4956 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4960 #ifdef md_flush_pending_output
4961 md_flush_pending_output ();
4964 #ifdef md_cons_align
4968 /* Since we're just labelling the code, there's no need to define a
4971 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4972 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4973 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4974 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4976 #endif /* OBJ_ELF */
4978 static void s_arm_arch (int);
4979 static void s_arm_object_arch (int);
4980 static void s_arm_cpu (int);
4981 static void s_arm_fpu (int);
4982 static void s_arm_arch_extension (int);
4987 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4994 if (exp
.X_op
== O_symbol
)
4995 exp
.X_op
= O_secrel
;
4997 emit_expr (&exp
, 4);
4999 while (*input_line_pointer
++ == ',');
5001 input_line_pointer
--;
5002 demand_empty_rest_of_line ();
5007 arm_is_largest_exponent_ok (int precision
)
5009 /* precision == 1 ensures that this will only return
5010 true for 16 bit floats. */
5011 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
5015 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
5019 enum fp_16bit_format new_format
;
5021 new_format
= ARM_FP16_FORMAT_DEFAULT
;
5023 name
= input_line_pointer
;
5024 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
5025 input_line_pointer
++;
5027 saved_char
= *input_line_pointer
;
5028 *input_line_pointer
= 0;
5030 if (strcasecmp (name
, "ieee") == 0)
5031 new_format
= ARM_FP16_FORMAT_IEEE
;
5032 else if (strcasecmp (name
, "alternative") == 0)
5033 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
5036 as_bad (_("unrecognised float16 format \"%s\""), name
);
5040 /* Only set fp16_format if it is still the default (aka not already
5042 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
5043 fp16_format
= new_format
;
5046 if (new_format
!= fp16_format
)
5047 as_warn (_("float16 format cannot be set more than once, ignoring."));
5051 *input_line_pointer
= saved_char
;
5052 ignore_rest_of_line ();
5055 /* This table describes all the machine specific pseudo-ops the assembler
5056 has to support. The fields are:
5057 pseudo-op name without dot
5058 function to call to execute this pseudo-op
5059 Integer arg to pass to the function. */
5061 const pseudo_typeS md_pseudo_table
[] =
5063 /* Never called because '.req' does not start a line. */
5064 { "req", s_req
, 0 },
5065 /* Following two are likewise never called. */
5068 { "unreq", s_unreq
, 0 },
5069 { "bss", s_bss
, 0 },
5070 { "align", s_align_ptwo
, 2 },
5071 { "arm", s_arm
, 0 },
5072 { "thumb", s_thumb
, 0 },
5073 { "code", s_code
, 0 },
5074 { "force_thumb", s_force_thumb
, 0 },
5075 { "thumb_func", s_thumb_func
, 0 },
5076 { "thumb_set", s_thumb_set
, 0 },
5077 { "even", s_even
, 0 },
5078 { "ltorg", s_ltorg
, 0 },
5079 { "pool", s_ltorg
, 0 },
5080 { "syntax", s_syntax
, 0 },
5081 { "cpu", s_arm_cpu
, 0 },
5082 { "arch", s_arm_arch
, 0 },
5083 { "object_arch", s_arm_object_arch
, 0 },
5084 { "fpu", s_arm_fpu
, 0 },
5085 { "arch_extension", s_arm_arch_extension
, 0 },
5087 { "word", s_arm_elf_cons
, 4 },
5088 { "long", s_arm_elf_cons
, 4 },
5089 { "inst.n", s_arm_elf_inst
, 2 },
5090 { "inst.w", s_arm_elf_inst
, 4 },
5091 { "inst", s_arm_elf_inst
, 0 },
5092 { "rel31", s_arm_rel31
, 0 },
5093 { "fnstart", s_arm_unwind_fnstart
, 0 },
5094 { "fnend", s_arm_unwind_fnend
, 0 },
5095 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5096 { "personality", s_arm_unwind_personality
, 0 },
5097 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5098 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5099 { "save", s_arm_unwind_save
, 0 },
5100 { "vsave", s_arm_unwind_save
, 1 },
5101 { "movsp", s_arm_unwind_movsp
, 0 },
5102 { "pad", s_arm_unwind_pad
, 0 },
5103 { "setfp", s_arm_unwind_setfp
, 0 },
5104 { "unwind_raw", s_arm_unwind_raw
, 0 },
5105 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5106 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5110 /* These are used for dwarf. */
5114 /* These are used for dwarf2. */
5115 { "file", dwarf2_directive_file
, 0 },
5116 { "loc", dwarf2_directive_loc
, 0 },
5117 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5119 { "extend", float_cons
, 'x' },
5120 { "ldouble", float_cons
, 'x' },
5121 { "packed", float_cons
, 'p' },
5122 { "bfloat16", float_cons
, 'b' },
5124 {"secrel32", pe_directive_secrel
, 0},
5127 /* These are for compatibility with CodeComposer Studio. */
5128 {"ref", s_ccs_ref
, 0},
5129 {"def", s_ccs_def
, 0},
5130 {"asmfunc", s_ccs_asmfunc
, 0},
5131 {"endasmfunc", s_ccs_endasmfunc
, 0},
5133 {"float16", float_cons
, 'h' },
5134 {"float16_format", set_fp16_format
, 0 },
5139 /* Parser functions used exclusively in instruction operands. */
5141 /* Generic immediate-value read function for use in insn parsing.
5142 STR points to the beginning of the immediate (the leading #);
5143 VAL receives the value; if the value is outside [MIN, MAX]
5144 issue an error. PREFIX_OPT is true if the immediate prefix is
5148 parse_immediate (char **str
, int *val
, int min
, int max
,
5153 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5154 if (exp
.X_op
!= O_constant
)
5156 inst
.error
= _("constant expression required");
5160 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5162 inst
.error
= _("immediate value out of range");
5166 *val
= exp
.X_add_number
;
5170 /* Less-generic immediate-value read function with the possibility of loading a
5171 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5172 instructions. Puts the result directly in inst.operands[i]. */
5175 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5176 bool allow_symbol_p
)
5179 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5182 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5184 if (exp_p
->X_op
== O_constant
)
5186 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5187 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5188 O_constant. We have to be careful not to break compilation for
5189 32-bit X_add_number, though. */
5190 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5192 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5193 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5195 inst
.operands
[i
].regisimm
= 1;
5198 else if (exp_p
->X_op
== O_big
5199 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5201 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5203 /* Bignums have their least significant bits in
5204 generic_bignum[0]. Make sure we put 32 bits in imm and
5205 32 bits in reg, in a (hopefully) portable way. */
5206 gas_assert (parts
!= 0);
5208 /* Make sure that the number is not too big.
5209 PR 11972: Bignums can now be sign-extended to the
5210 size of a .octa so check that the out of range bits
5211 are all zero or all one. */
5212 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5214 LITTLENUM_TYPE m
= -1;
5216 if (generic_bignum
[parts
* 2] != 0
5217 && generic_bignum
[parts
* 2] != m
)
5220 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5221 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5225 inst
.operands
[i
].imm
= 0;
5226 for (j
= 0; j
< parts
; j
++, idx
++)
5227 inst
.operands
[i
].imm
|= ((unsigned) generic_bignum
[idx
]
5228 << (LITTLENUM_NUMBER_OF_BITS
* j
));
5229 inst
.operands
[i
].reg
= 0;
5230 for (j
= 0; j
< parts
; j
++, idx
++)
5231 inst
.operands
[i
].reg
|= ((unsigned) generic_bignum
[idx
]
5232 << (LITTLENUM_NUMBER_OF_BITS
* j
));
5233 inst
.operands
[i
].regisimm
= 1;
5235 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5243 /* Returns the pseudo-register number of an FPA immediate constant,
5244 or FAIL if there isn't a valid constant here. */
5247 parse_fpa_immediate (char ** str
)
5249 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5255 /* First try and match exact strings, this is to guarantee
5256 that some formats will work even for cross assembly. */
5258 for (i
= 0; fp_const
[i
]; i
++)
5260 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5264 *str
+= strlen (fp_const
[i
]);
5265 if (is_end_of_line
[(unsigned char) **str
])
5271 /* Just because we didn't get a match doesn't mean that the constant
5272 isn't valid, just that it is in a format that we don't
5273 automatically recognize. Try parsing it with the standard
5274 expression routines. */
5276 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5278 /* Look for a raw floating point number. */
5279 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5280 && is_end_of_line
[(unsigned char) *save_in
])
5282 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5284 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5286 if (words
[j
] != fp_values
[i
][j
])
5290 if (j
== MAX_LITTLENUMS
)
5298 /* Try and parse a more complex expression, this will probably fail
5299 unless the code uses a floating point prefix (eg "0f"). */
5300 save_in
= input_line_pointer
;
5301 input_line_pointer
= *str
;
5302 if (expression (&exp
) == absolute_section
5303 && exp
.X_op
== O_big
5304 && exp
.X_add_number
< 0)
5306 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5308 #define X_PRECISION 5
5309 #define E_PRECISION 15L
5310 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5312 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5314 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5316 if (words
[j
] != fp_values
[i
][j
])
5320 if (j
== MAX_LITTLENUMS
)
5322 *str
= input_line_pointer
;
5323 input_line_pointer
= save_in
;
5330 *str
= input_line_pointer
;
5331 input_line_pointer
= save_in
;
5332 inst
.error
= _("invalid FPA immediate expression");
5336 /* Returns 1 if a number has "quarter-precision" float format
5337 0baBbbbbbc defgh000 00000000 00000000. */
5340 is_quarter_float (unsigned imm
)
5342 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5343 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5347 /* Detect the presence of a floating point or integer zero constant,
5351 parse_ifimm_zero (char **in
)
5355 if (!is_immediate_prefix (**in
))
5357 /* In unified syntax, all prefixes are optional. */
5358 if (!unified_syntax
)
5364 /* Accept #0x0 as a synonym for #0. */
5365 if (startswith (*in
, "0x"))
5368 if (parse_immediate (in
, &val
, 0, 0, true) == FAIL
)
5373 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5374 &generic_floating_point_number
);
5377 && generic_floating_point_number
.sign
== '+'
5378 && (generic_floating_point_number
.low
5379 > generic_floating_point_number
.leader
))
5385 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5386 0baBbbbbbc defgh000 00000000 00000000.
5387 The zero and minus-zero cases need special handling, since they can't be
5388 encoded in the "quarter-precision" float format, but can nonetheless be
5389 loaded as integer constants. */
5392 parse_qfloat_immediate (char **ccp
, int *immed
)
5396 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5397 int found_fpchar
= 0;
5399 skip_past_char (&str
, '#');
5401 /* We must not accidentally parse an integer as a floating-point number. Make
5402 sure that the value we parse is not an integer by checking for special
5403 characters '.' or 'e'.
5404 FIXME: This is a horrible hack, but doing better is tricky because type
5405 information isn't in a very usable state at parse time. */
5407 skip_whitespace (fpnum
);
5409 if (startswith (fpnum
, "0x"))
5413 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5414 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5424 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5426 unsigned fpword
= 0;
5429 /* Our FP word must be 32 bits (single-precision FP). */
5430 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5432 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5436 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5449 /* Shift operands. */
5452 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5455 struct asm_shift_name
5458 enum shift_kind kind
;
5461 /* Third argument to parse_shift. */
5462 enum parse_shift_mode
5464 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5465 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5466 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5467 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5468 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5469 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5472 /* Parse a <shift> specifier on an ARM data processing instruction.
5473 This has three forms:
5475 (LSL|LSR|ASL|ASR|ROR) Rs
5476 (LSL|LSR|ASL|ASR|ROR) #imm
5479 Note that ASL is assimilated to LSL in the instruction encoding, and
5480 RRX to ROR #0 (which cannot be written as such). */
5483 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5485 const struct asm_shift_name
*shift_name
;
5486 enum shift_kind shift
;
5491 for (p
= *str
; ISALPHA (*p
); p
++)
5496 inst
.error
= _("shift expression expected");
5501 = (const struct asm_shift_name
*) str_hash_find_n (arm_shift_hsh
, *str
,
5504 if (shift_name
== NULL
)
5506 inst
.error
= _("shift expression expected");
5510 shift
= shift_name
->kind
;
5514 case NO_SHIFT_RESTRICT
:
5515 case SHIFT_IMMEDIATE
:
5516 if (shift
== SHIFT_UXTW
)
5518 inst
.error
= _("'UXTW' not allowed here");
5523 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5524 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5526 inst
.error
= _("'LSL' or 'ASR' required");
5531 case SHIFT_LSL_IMMEDIATE
:
5532 if (shift
!= SHIFT_LSL
)
5534 inst
.error
= _("'LSL' required");
5539 case SHIFT_ASR_IMMEDIATE
:
5540 if (shift
!= SHIFT_ASR
)
5542 inst
.error
= _("'ASR' required");
5546 case SHIFT_UXTW_IMMEDIATE
:
5547 if (shift
!= SHIFT_UXTW
)
5549 inst
.error
= _("'UXTW' required");
5557 if (shift
!= SHIFT_RRX
)
5559 /* Whitespace can appear here if the next thing is a bare digit. */
5560 skip_whitespace (p
);
5562 if (mode
== NO_SHIFT_RESTRICT
5563 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5565 inst
.operands
[i
].imm
= reg
;
5566 inst
.operands
[i
].immisreg
= 1;
5568 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5571 inst
.operands
[i
].shift_kind
= shift
;
5572 inst
.operands
[i
].shifted
= 1;
5577 /* Parse a <shifter_operand> for an ARM data processing instruction:
5580 #<immediate>, <rotate>
5584 where <shift> is defined by parse_shift above, and <rotate> is a
5585 multiple of 2 between 0 and 30. Validation of immediate operands
5586 is deferred to md_apply_fix. */
5589 parse_shifter_operand (char **str
, int i
)
5594 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5596 inst
.operands
[i
].reg
= value
;
5597 inst
.operands
[i
].isreg
= 1;
5599 /* parse_shift will override this if appropriate */
5600 inst
.relocs
[0].exp
.X_op
= O_constant
;
5601 inst
.relocs
[0].exp
.X_add_number
= 0;
5603 if (skip_past_comma (str
) == FAIL
)
5606 /* Shift operation on register. */
5607 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5610 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5613 if (skip_past_comma (str
) == SUCCESS
)
5615 /* #x, y -- ie explicit rotation by Y. */
5616 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5619 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5621 inst
.error
= _("constant expression expected");
5625 value
= exp
.X_add_number
;
5626 if (value
< 0 || value
> 30 || value
% 2 != 0)
5628 inst
.error
= _("invalid rotation");
5631 if (inst
.relocs
[0].exp
.X_add_number
< 0
5632 || inst
.relocs
[0].exp
.X_add_number
> 255)
5634 inst
.error
= _("invalid constant");
5638 /* Encode as specified. */
5639 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5643 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5644 inst
.relocs
[0].pc_rel
= 0;
5648 /* Group relocation information. Each entry in the table contains the
5649 textual name of the relocation as may appear in assembler source
5650 and must end with a colon.
5651 Along with this textual name are the relocation codes to be used if
5652 the corresponding instruction is an ALU instruction (ADD or SUB only),
5653 an LDR, an LDRS, or an LDC. */
5655 struct group_reloc_table_entry
5666 /* Varieties of non-ALU group relocation. */
5674 static struct group_reloc_table_entry group_reloc_table
[] =
5675 { /* Program counter relative: */
5677 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5682 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5683 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5684 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5685 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5687 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5692 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5693 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5694 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5695 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5697 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5698 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5699 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5700 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5701 /* Section base relative */
5703 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5708 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5709 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5710 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5711 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5713 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5718 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5719 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5720 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5721 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5723 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5724 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5725 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5726 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5727 /* Absolute thumb alu relocations. */
5729 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5734 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5739 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5744 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5749 /* Given the address of a pointer pointing to the textual name of a group
5750 relocation as may appear in assembler source, attempt to find its details
5751 in group_reloc_table. The pointer will be updated to the character after
5752 the trailing colon. On failure, FAIL will be returned; SUCCESS
5753 otherwise. On success, *entry will be updated to point at the relevant
5754 group_reloc_table entry. */
5757 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5760 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5762 int length
= strlen (group_reloc_table
[i
].name
);
5764 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5765 && (*str
)[length
] == ':')
5767 *out
= &group_reloc_table
[i
];
5768 *str
+= (length
+ 1);
5776 /* Parse a <shifter_operand> for an ARM data processing instruction
5777 (as for parse_shifter_operand) where group relocations are allowed:
5780 #<immediate>, <rotate>
5781 #:<group_reloc>:<expression>
5785 where <group_reloc> is one of the strings defined in group_reloc_table.
5786 The hashes are optional.
5788 Everything else is as for parse_shifter_operand. */
5790 static parse_operand_result
5791 parse_shifter_operand_group_reloc (char **str
, int i
)
5793 /* Determine if we have the sequence of characters #: or just :
5794 coming next. If we do, then we check for a group relocation.
5795 If we don't, punt the whole lot to parse_shifter_operand. */
5797 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5798 || (*str
)[0] == ':')
5800 struct group_reloc_table_entry
*entry
;
5802 if ((*str
)[0] == '#')
5807 /* Try to parse a group relocation. Anything else is an error. */
5808 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5810 inst
.error
= _("unknown group relocation");
5811 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5814 /* We now have the group relocation table entry corresponding to
5815 the name in the assembler source. Next, we parse the expression. */
5816 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5817 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5819 /* Record the relocation type (always the ALU variant here). */
5820 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5821 gas_assert (inst
.relocs
[0].type
!= 0);
5823 return PARSE_OPERAND_SUCCESS
;
5826 return parse_shifter_operand (str
, i
) == SUCCESS
5827 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5829 /* Never reached. */
5832 /* Parse a Neon alignment expression. Information is written to
5833 inst.operands[i]. We assume the initial ':' has been skipped.
5835 align .imm = align << 8, .immisalign=1, .preind=0 */
5836 static parse_operand_result
5837 parse_neon_alignment (char **str
, int i
)
5842 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5844 if (exp
.X_op
!= O_constant
)
5846 inst
.error
= _("alignment must be constant");
5847 return PARSE_OPERAND_FAIL
;
5850 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5851 inst
.operands
[i
].immisalign
= 1;
5852 /* Alignments are not pre-indexes. */
5853 inst
.operands
[i
].preind
= 0;
5856 return PARSE_OPERAND_SUCCESS
;
5859 /* Parse all forms of an ARM address expression. Information is written
5860 to inst.operands[i] and/or inst.relocs[0].
5862 Preindexed addressing (.preind=1):
5864 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5865 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5866 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5867 .shift_kind=shift .relocs[0].exp=shift_imm
5869 These three may have a trailing ! which causes .writeback to be set also.
5871 Postindexed addressing (.postind=1, .writeback=1):
5873 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5874 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5875 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5876 .shift_kind=shift .relocs[0].exp=shift_imm
5878 Unindexed addressing (.preind=0, .postind=0):
5880 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5884 [Rn]{!} shorthand for [Rn,#0]{!}
5885 =immediate .isreg=0 .relocs[0].exp=immediate
5886 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5888 It is the caller's responsibility to check for addressing modes not
5889 supported by the instruction, and to set inst.relocs[0].type. */
5891 static parse_operand_result
5892 parse_address_main (char **str
, int i
, int group_relocations
,
5893 group_reloc_type group_type
)
5898 if (skip_past_char (&p
, '[') == FAIL
)
5900 if (group_type
== GROUP_MVE
5901 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5903 /* [r0-r15] expected as argument but receiving r0-r15 without
5905 inst
.error
= BAD_SYNTAX
;
5906 return PARSE_OPERAND_FAIL
;
5908 else if (skip_past_char (&p
, '=') == FAIL
)
5910 /* Bare address - translate to PC-relative offset. */
5911 inst
.relocs
[0].pc_rel
= 1;
5912 inst
.operands
[i
].reg
= REG_PC
;
5913 inst
.operands
[i
].isreg
= 1;
5914 inst
.operands
[i
].preind
= 1;
5916 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5917 return PARSE_OPERAND_FAIL
;
5919 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5920 /*allow_symbol_p=*/true))
5921 return PARSE_OPERAND_FAIL
;
5924 return PARSE_OPERAND_SUCCESS
;
5927 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5928 skip_whitespace (p
);
5930 if (group_type
== GROUP_MVE
)
5932 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5933 struct neon_type_el et
;
5934 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5936 inst
.operands
[i
].isquad
= 1;
5938 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5940 inst
.error
= BAD_ADDR_MODE
;
5941 return PARSE_OPERAND_FAIL
;
5944 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5946 if (group_type
== GROUP_MVE
)
5947 inst
.error
= BAD_ADDR_MODE
;
5949 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5950 return PARSE_OPERAND_FAIL
;
5952 inst
.operands
[i
].reg
= reg
;
5953 inst
.operands
[i
].isreg
= 1;
5955 if (skip_past_comma (&p
) == SUCCESS
)
5957 inst
.operands
[i
].preind
= 1;
5960 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5962 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5963 struct neon_type_el et
;
5964 if (group_type
== GROUP_MVE
5965 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5967 inst
.operands
[i
].immisreg
= 2;
5968 inst
.operands
[i
].imm
= reg
;
5970 if (skip_past_comma (&p
) == SUCCESS
)
5972 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5974 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5975 inst
.relocs
[0].exp
.X_add_number
= 0;
5978 return PARSE_OPERAND_FAIL
;
5981 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5983 inst
.operands
[i
].imm
= reg
;
5984 inst
.operands
[i
].immisreg
= 1;
5986 if (skip_past_comma (&p
) == SUCCESS
)
5987 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5988 return PARSE_OPERAND_FAIL
;
5990 else if (skip_past_char (&p
, ':') == SUCCESS
)
5992 /* FIXME: '@' should be used here, but it's filtered out by generic
5993 code before we get to see it here. This may be subject to
5995 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5997 if (result
!= PARSE_OPERAND_SUCCESS
)
6002 if (inst
.operands
[i
].negative
)
6004 inst
.operands
[i
].negative
= 0;
6008 if (group_relocations
6009 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
6011 struct group_reloc_table_entry
*entry
;
6013 /* Skip over the #: or : sequence. */
6019 /* Try to parse a group relocation. Anything else is an
6021 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
6023 inst
.error
= _("unknown group relocation");
6024 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6027 /* We now have the group relocation table entry corresponding to
6028 the name in the assembler source. Next, we parse the
6030 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6031 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6033 /* Record the relocation type. */
6038 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
6043 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
6048 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
6055 if (inst
.relocs
[0].type
== 0)
6057 inst
.error
= _("this group relocation is not allowed on this instruction");
6058 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6065 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6066 return PARSE_OPERAND_FAIL
;
6067 /* If the offset is 0, find out if it's a +0 or -0. */
6068 if (inst
.relocs
[0].exp
.X_op
== O_constant
6069 && inst
.relocs
[0].exp
.X_add_number
== 0)
6071 skip_whitespace (q
);
6075 skip_whitespace (q
);
6078 inst
.operands
[i
].negative
= 1;
6083 else if (skip_past_char (&p
, ':') == SUCCESS
)
6085 /* FIXME: '@' should be used here, but it's filtered out by generic code
6086 before we get to see it here. This may be subject to change. */
6087 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6089 if (result
!= PARSE_OPERAND_SUCCESS
)
6093 if (skip_past_char (&p
, ']') == FAIL
)
6095 inst
.error
= _("']' expected");
6096 return PARSE_OPERAND_FAIL
;
6099 if (skip_past_char (&p
, '!') == SUCCESS
)
6100 inst
.operands
[i
].writeback
= 1;
6102 else if (skip_past_comma (&p
) == SUCCESS
)
6104 if (skip_past_char (&p
, '{') == SUCCESS
)
6106 /* [Rn], {expr} - unindexed, with option */
6107 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6108 0, 255, true) == FAIL
)
6109 return PARSE_OPERAND_FAIL
;
6111 if (skip_past_char (&p
, '}') == FAIL
)
6113 inst
.error
= _("'}' expected at end of 'option' field");
6114 return PARSE_OPERAND_FAIL
;
6116 if (inst
.operands
[i
].preind
)
6118 inst
.error
= _("cannot combine index with option");
6119 return PARSE_OPERAND_FAIL
;
6122 return PARSE_OPERAND_SUCCESS
;
6126 inst
.operands
[i
].postind
= 1;
6127 inst
.operands
[i
].writeback
= 1;
6129 if (inst
.operands
[i
].preind
)
6131 inst
.error
= _("cannot combine pre- and post-indexing");
6132 return PARSE_OPERAND_FAIL
;
6136 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6138 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6139 struct neon_type_el et
;
6140 if (group_type
== GROUP_MVE
6141 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6143 inst
.operands
[i
].immisreg
= 2;
6144 inst
.operands
[i
].imm
= reg
;
6146 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6148 /* We might be using the immediate for alignment already. If we
6149 are, OR the register number into the low-order bits. */
6150 if (inst
.operands
[i
].immisalign
)
6151 inst
.operands
[i
].imm
|= reg
;
6153 inst
.operands
[i
].imm
= reg
;
6154 inst
.operands
[i
].immisreg
= 1;
6156 if (skip_past_comma (&p
) == SUCCESS
)
6157 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6158 return PARSE_OPERAND_FAIL
;
6164 if (inst
.operands
[i
].negative
)
6166 inst
.operands
[i
].negative
= 0;
6169 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6170 return PARSE_OPERAND_FAIL
;
6171 /* If the offset is 0, find out if it's a +0 or -0. */
6172 if (inst
.relocs
[0].exp
.X_op
== O_constant
6173 && inst
.relocs
[0].exp
.X_add_number
== 0)
6175 skip_whitespace (q
);
6179 skip_whitespace (q
);
6182 inst
.operands
[i
].negative
= 1;
6188 /* If at this point neither .preind nor .postind is set, we have a
6189 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6190 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6192 inst
.operands
[i
].preind
= 1;
6193 inst
.relocs
[0].exp
.X_op
= O_constant
;
6194 inst
.relocs
[0].exp
.X_add_number
= 0;
6197 return PARSE_OPERAND_SUCCESS
;
6201 parse_address (char **str
, int i
)
6203 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6207 static parse_operand_result
6208 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6210 return parse_address_main (str
, i
, 1, type
);
6213 /* Parse an operand for a MOVW or MOVT instruction. */
6215 parse_half (char **str
)
6220 skip_past_char (&p
, '#');
6221 if (strncasecmp (p
, ":lower16:", 9) == 0)
6222 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6223 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6224 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6226 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6229 skip_whitespace (p
);
6232 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6235 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6237 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6239 inst
.error
= _("constant expression expected");
6242 if (inst
.relocs
[0].exp
.X_add_number
< 0
6243 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6245 inst
.error
= _("immediate value out of range");
6253 /* Miscellaneous. */
6255 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6256 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6258 parse_psr (char **str
, bool lhs
)
6261 unsigned long psr_field
;
6262 const struct asm_psr
*psr
;
6264 bool is_apsr
= false;
6265 bool m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6267 /* PR gas/12698: If the user has specified -march=all then m_profile will
6268 be TRUE, but we want to ignore it in this case as we are building for any
6269 CPU type, including non-m variants. */
6270 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6273 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6274 feature for ease of use and backwards compatibility. */
6276 if (strncasecmp (p
, "SPSR", 4) == 0)
6279 goto unsupported_psr
;
6281 psr_field
= SPSR_BIT
;
6283 else if (strncasecmp (p
, "CPSR", 4) == 0)
6286 goto unsupported_psr
;
6290 else if (strncasecmp (p
, "APSR", 4) == 0)
6292 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6293 and ARMv7-R architecture CPUs. */
6302 while (ISALNUM (*p
) || *p
== '_');
6304 if (strncasecmp (start
, "iapsr", 5) == 0
6305 || strncasecmp (start
, "eapsr", 5) == 0
6306 || strncasecmp (start
, "xpsr", 4) == 0
6307 || strncasecmp (start
, "psr", 3) == 0)
6308 p
= start
+ strcspn (start
, "rR") + 1;
6310 psr
= (const struct asm_psr
*) str_hash_find_n (arm_v7m_psr_hsh
, start
,
6316 /* If APSR is being written, a bitfield may be specified. Note that
6317 APSR itself is handled above. */
6318 if (psr
->field
<= 3)
6320 psr_field
= psr
->field
;
6326 /* M-profile MSR instructions have the mask field set to "10", except
6327 *PSR variants which modify APSR, which may use a different mask (and
6328 have been handled already). Do that by setting the PSR_f field
6330 return psr
->field
| (lhs
? PSR_f
: 0);
6333 goto unsupported_psr
;
6339 /* A suffix follows. */
6345 while (ISALNUM (*p
) || *p
== '_');
6349 /* APSR uses a notation for bits, rather than fields. */
6350 unsigned int nzcvq_bits
= 0;
6351 unsigned int g_bit
= 0;
6354 for (bit
= start
; bit
!= p
; bit
++)
6356 switch (TOLOWER (*bit
))
6359 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6363 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6367 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6371 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6375 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6379 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6383 inst
.error
= _("unexpected bit specified after APSR");
6388 if (nzcvq_bits
== 0x1f)
6393 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6395 inst
.error
= _("selected processor does not "
6396 "support DSP extension");
6403 if ((nzcvq_bits
& 0x20) != 0
6404 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6405 || (g_bit
& 0x2) != 0)
6407 inst
.error
= _("bad bitmask specified after APSR");
6413 psr
= (const struct asm_psr
*) str_hash_find_n (arm_psr_hsh
, start
,
6418 psr_field
|= psr
->field
;
6424 goto error
; /* Garbage after "[CS]PSR". */
6426 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6427 is deprecated, but allow it anyway. */
6431 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6434 else if (!m_profile
)
6435 /* These bits are never right for M-profile devices: don't set them
6436 (only code paths which read/write APSR reach here). */
6437 psr_field
|= (PSR_c
| PSR_f
);
6443 inst
.error
= _("selected processor does not support requested special "
6444 "purpose register");
6448 inst
.error
= _("flag for {c}psr instruction expected");
6453 parse_sys_vldr_vstr (char **str
)
6462 {"FPSCR", 0x1, 0x0},
6463 {"FPSCR_nzcvqc", 0x2, 0x0},
6466 {"FPCXTNS", 0x6, 0x1},
6467 {"FPCXTS", 0x7, 0x1}
6469 char *op_end
= strchr (*str
, ',');
6470 size_t op_strlen
= op_end
- *str
;
6472 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6474 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6476 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6485 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6486 value suitable for splatting into the AIF field of the instruction. */
6489 parse_cps_flags (char **str
)
6498 case '\0': case ',':
6501 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6502 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6503 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6506 inst
.error
= _("unrecognized CPS flag");
6511 if (saw_a_flag
== 0)
6513 inst
.error
= _("missing CPS flags");
6521 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6522 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6525 parse_endian_specifier (char **str
)
6530 if (strncasecmp (s
, "BE", 2))
6532 else if (strncasecmp (s
, "LE", 2))
6536 inst
.error
= _("valid endian specifiers are be or le");
6540 if (ISALNUM (s
[2]) || s
[2] == '_')
6542 inst
.error
= _("valid endian specifiers are be or le");
6547 return little_endian
;
6550 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6551 value suitable for poking into the rotate field of an sxt or sxta
6552 instruction, or FAIL on error. */
6555 parse_ror (char **str
)
6560 if (strncasecmp (s
, "ROR", 3) == 0)
6564 inst
.error
= _("missing rotation field after comma");
6568 if (parse_immediate (&s
, &rot
, 0, 24, false) == FAIL
)
6573 case 0: *str
= s
; return 0x0;
6574 case 8: *str
= s
; return 0x1;
6575 case 16: *str
= s
; return 0x2;
6576 case 24: *str
= s
; return 0x3;
6579 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6584 /* Parse a conditional code (from conds[] below). The value returned is in the
6585 range 0 .. 14, or FAIL. */
6587 parse_cond (char **str
)
6590 const struct asm_cond
*c
;
6592 /* Condition codes are always 2 characters, so matching up to
6593 3 characters is sufficient. */
6598 while (ISALPHA (*q
) && n
< 3)
6600 cond
[n
] = TOLOWER (*q
);
6605 c
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, cond
, n
);
6608 inst
.error
= _("condition required");
6616 /* Parse an option for a barrier instruction. Returns the encoding for the
6619 parse_barrier (char **str
)
6622 const struct asm_barrier_opt
*o
;
6625 while (ISALPHA (*q
))
6628 o
= (const struct asm_barrier_opt
*) str_hash_find_n (arm_barrier_opt_hsh
, p
,
6633 if (!mark_feature_used (&o
->arch
))
6640 /* Parse the operands of a table branch instruction. Similar to a memory
6643 parse_tb (char **str
)
6648 if (skip_past_char (&p
, '[') == FAIL
)
6650 inst
.error
= _("'[' expected");
6654 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6656 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6659 inst
.operands
[0].reg
= reg
;
6661 if (skip_past_comma (&p
) == FAIL
)
6663 inst
.error
= _("',' expected");
6667 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6669 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6672 inst
.operands
[0].imm
= reg
;
6674 if (skip_past_comma (&p
) == SUCCESS
)
6676 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6678 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6680 inst
.error
= _("invalid shift");
6683 inst
.operands
[0].shifted
= 1;
6686 if (skip_past_char (&p
, ']') == FAIL
)
6688 inst
.error
= _("']' expected");
6695 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6696 information on the types the operands can take and how they are encoded.
6697 Up to four operands may be read; this function handles setting the
6698 ".present" field for each read operand itself.
6699 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6700 else returns FAIL. */
6703 parse_neon_mov (char **str
, int *which_operand
)
6705 int i
= *which_operand
, val
;
6706 enum arm_reg_type rtype
;
6708 struct neon_type_el optype
;
6710 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6712 /* Cases 17 or 19. */
6713 inst
.operands
[i
].reg
= val
;
6714 inst
.operands
[i
].isvec
= 1;
6715 inst
.operands
[i
].isscalar
= 2;
6716 inst
.operands
[i
].vectype
= optype
;
6717 inst
.operands
[i
++].present
= 1;
6719 if (skip_past_comma (&ptr
) == FAIL
)
6722 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6724 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6725 inst
.operands
[i
].reg
= val
;
6726 inst
.operands
[i
].isreg
= 1;
6727 inst
.operands
[i
].present
= 1;
6729 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6731 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6732 inst
.operands
[i
].reg
= val
;
6733 inst
.operands
[i
].isvec
= 1;
6734 inst
.operands
[i
].isscalar
= 2;
6735 inst
.operands
[i
].vectype
= optype
;
6736 inst
.operands
[i
++].present
= 1;
6738 if (skip_past_comma (&ptr
) == FAIL
)
6741 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6744 inst
.operands
[i
].reg
= val
;
6745 inst
.operands
[i
].isreg
= 1;
6746 inst
.operands
[i
++].present
= 1;
6748 if (skip_past_comma (&ptr
) == FAIL
)
6751 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6754 inst
.operands
[i
].reg
= val
;
6755 inst
.operands
[i
].isreg
= 1;
6756 inst
.operands
[i
].present
= 1;
6760 first_error (_("expected ARM or MVE vector register"));
6764 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6766 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6767 inst
.operands
[i
].reg
= val
;
6768 inst
.operands
[i
].isscalar
= 1;
6769 inst
.operands
[i
].vectype
= optype
;
6770 inst
.operands
[i
++].present
= 1;
6772 if (skip_past_comma (&ptr
) == FAIL
)
6775 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6778 inst
.operands
[i
].reg
= val
;
6779 inst
.operands
[i
].isreg
= 1;
6780 inst
.operands
[i
].present
= 1;
6782 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6784 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6787 /* Cases 0, 1, 2, 3, 5 (D only). */
6788 if (skip_past_comma (&ptr
) == FAIL
)
6791 inst
.operands
[i
].reg
= val
;
6792 inst
.operands
[i
].isreg
= 1;
6793 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6794 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6795 inst
.operands
[i
].isvec
= 1;
6796 inst
.operands
[i
].vectype
= optype
;
6797 inst
.operands
[i
++].present
= 1;
6799 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6801 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6802 Case 13: VMOV <Sd>, <Rm> */
6803 inst
.operands
[i
].reg
= val
;
6804 inst
.operands
[i
].isreg
= 1;
6805 inst
.operands
[i
].present
= 1;
6807 if (rtype
== REG_TYPE_NQ
)
6809 first_error (_("can't use Neon quad register here"));
6812 else if (rtype
!= REG_TYPE_VFS
)
6815 if (skip_past_comma (&ptr
) == FAIL
)
6817 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6819 inst
.operands
[i
].reg
= val
;
6820 inst
.operands
[i
].isreg
= 1;
6821 inst
.operands
[i
].present
= 1;
6824 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6826 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6829 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6830 Case 1: VMOV<c><q> <Dd>, <Dm>
6831 Case 8: VMOV.F32 <Sd>, <Sm>
6832 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6834 inst
.operands
[i
].reg
= val
;
6835 inst
.operands
[i
].isreg
= 1;
6836 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6837 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6838 inst
.operands
[i
].isvec
= 1;
6839 inst
.operands
[i
].vectype
= optype
;
6840 inst
.operands
[i
].present
= 1;
6842 if (skip_past_comma (&ptr
) == SUCCESS
)
6847 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6850 inst
.operands
[i
].reg
= val
;
6851 inst
.operands
[i
].isreg
= 1;
6852 inst
.operands
[i
++].present
= 1;
6854 if (skip_past_comma (&ptr
) == FAIL
)
6857 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6860 inst
.operands
[i
].reg
= val
;
6861 inst
.operands
[i
].isreg
= 1;
6862 inst
.operands
[i
].present
= 1;
6865 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6866 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6867 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6868 Case 10: VMOV.F32 <Sd>, #<imm>
6869 Case 11: VMOV.F64 <Dd>, #<imm> */
6870 inst
.operands
[i
].immisfloat
= 1;
6871 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/false)
6873 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6874 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6878 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6882 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6884 /* Cases 6, 7, 16, 18. */
6885 inst
.operands
[i
].reg
= val
;
6886 inst
.operands
[i
].isreg
= 1;
6887 inst
.operands
[i
++].present
= 1;
6889 if (skip_past_comma (&ptr
) == FAIL
)
6892 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6894 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6895 inst
.operands
[i
].reg
= val
;
6896 inst
.operands
[i
].isscalar
= 2;
6897 inst
.operands
[i
].present
= 1;
6898 inst
.operands
[i
].vectype
= optype
;
6900 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6902 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6903 inst
.operands
[i
].reg
= val
;
6904 inst
.operands
[i
].isscalar
= 1;
6905 inst
.operands
[i
].present
= 1;
6906 inst
.operands
[i
].vectype
= optype
;
6908 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6910 inst
.operands
[i
].reg
= val
;
6911 inst
.operands
[i
].isreg
= 1;
6912 inst
.operands
[i
++].present
= 1;
6914 if (skip_past_comma (&ptr
) == FAIL
)
6917 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6920 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6922 inst
.operands
[i
].reg
= val
;
6923 inst
.operands
[i
].isreg
= 1;
6924 inst
.operands
[i
].isvec
= 1;
6925 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6926 inst
.operands
[i
].vectype
= optype
;
6927 inst
.operands
[i
].present
= 1;
6929 if (rtype
== REG_TYPE_VFS
)
6933 if (skip_past_comma (&ptr
) == FAIL
)
6935 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6938 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6941 inst
.operands
[i
].reg
= val
;
6942 inst
.operands
[i
].isreg
= 1;
6943 inst
.operands
[i
].isvec
= 1;
6944 inst
.operands
[i
].issingle
= 1;
6945 inst
.operands
[i
].vectype
= optype
;
6946 inst
.operands
[i
].present
= 1;
6951 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6954 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6955 inst
.operands
[i
].reg
= val
;
6956 inst
.operands
[i
].isvec
= 1;
6957 inst
.operands
[i
].isscalar
= 2;
6958 inst
.operands
[i
].vectype
= optype
;
6959 inst
.operands
[i
++].present
= 1;
6961 if (skip_past_comma (&ptr
) == FAIL
)
6964 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6967 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6970 inst
.operands
[i
].reg
= val
;
6971 inst
.operands
[i
].isvec
= 1;
6972 inst
.operands
[i
].isscalar
= 2;
6973 inst
.operands
[i
].vectype
= optype
;
6974 inst
.operands
[i
].present
= 1;
6978 first_error (_("VFP single, double or MVE vector register"
6984 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6988 inst
.operands
[i
].reg
= val
;
6989 inst
.operands
[i
].isreg
= 1;
6990 inst
.operands
[i
].isvec
= 1;
6991 inst
.operands
[i
].issingle
= 1;
6992 inst
.operands
[i
].vectype
= optype
;
6993 inst
.operands
[i
].present
= 1;
6998 first_error (_("parse error"));
7002 /* Successfully parsed the operands. Update args. */
7008 first_error (_("expected comma"));
7012 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
7016 /* Use this macro when the operand constraints are different
7017 for ARM and THUMB (e.g. ldrd). */
7018 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
7019 ((arm_operand) | ((thumb_operand) << 16))
7021 /* Matcher codes for parse_operands. */
7022 enum operand_parse_code
7024 OP_stop
, /* end of line */
7026 OP_RR
, /* ARM register */
7027 OP_RRnpc
, /* ARM register, not r15 */
7028 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
7029 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
7030 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
7031 optional trailing ! */
7032 OP_RRw
, /* ARM register, not r15, optional trailing ! */
7033 OP_RCP
, /* Coprocessor number */
7034 OP_RCN
, /* Coprocessor register */
7035 OP_RF
, /* FPA register */
7036 OP_RVS
, /* VFP single precision register */
7037 OP_RVD
, /* VFP double precision register (0..15) */
7038 OP_RND
, /* Neon double precision register (0..31) */
7039 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
7040 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
7042 OP_RNSDMQR
, /* Neon single or double precision, MVE vector or ARM register.
7044 OP_RNQ
, /* Neon quad precision register */
7045 OP_RNQMQ
, /* Neon quad or MVE vector register. */
7046 OP_RVSD
, /* VFP single or double precision register */
7047 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
7048 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
7049 OP_RNSD
, /* Neon single or double precision register */
7050 OP_RNDQ
, /* Neon double or quad precision register */
7051 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
7052 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
7053 OP_RNSDQ
, /* Neon single, double or quad precision register */
7054 OP_RNSC
, /* Neon scalar D[X] */
7055 OP_RVC
, /* VFP control register */
7056 OP_RMF
, /* Maverick F register */
7057 OP_RMD
, /* Maverick D register */
7058 OP_RMFX
, /* Maverick FX register */
7059 OP_RMDX
, /* Maverick DX register */
7060 OP_RMAX
, /* Maverick AX register */
7061 OP_RMDS
, /* Maverick DSPSC register */
7062 OP_RIWR
, /* iWMMXt wR register */
7063 OP_RIWC
, /* iWMMXt wC register */
7064 OP_RIWG
, /* iWMMXt wCG register */
7065 OP_RXA
, /* XScale accumulator register */
7067 OP_RNSDMQ
, /* Neon single, double or MVE vector register */
7068 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
7070 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
7072 OP_RMQ
, /* MVE vector register. */
7073 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
7074 OP_RMQRR
, /* MVE vector or ARM register. */
7076 /* New operands for Armv8.1-M Mainline. */
7077 OP_LR
, /* ARM LR register */
7078 OP_SP
, /* ARM SP register */
7080 OP_RRe
, /* ARM register, only even numbered. */
7081 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
7082 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7083 OP_RR_ZR
, /* ARM register or ZR but no PC */
7085 OP_REGLST
, /* ARM register list */
7086 OP_CLRMLST
, /* CLRM register list */
7087 OP_VRSLST
, /* VFP single-precision register list */
7088 OP_VRDLST
, /* VFP double-precision register list */
7089 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7090 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7091 OP_NSTRLST
, /* Neon element/structure list */
7092 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7093 OP_MSTRLST2
, /* MVE vector list with two elements. */
7094 OP_MSTRLST4
, /* MVE vector list with four elements. */
7096 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7097 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7098 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7099 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7101 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7102 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7103 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7104 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7106 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7107 scalar, or ARM register. */
7108 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7109 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7110 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7112 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7113 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7114 OP_VMOV
, /* Neon VMOV operands. */
7115 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7116 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7118 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7119 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7121 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7122 OP_VLDR
, /* VLDR operand. */
7124 OP_I0
, /* immediate zero */
7125 OP_I7
, /* immediate value 0 .. 7 */
7126 OP_I15
, /* 0 .. 15 */
7127 OP_I16
, /* 1 .. 16 */
7128 OP_I16z
, /* 0 .. 16 */
7129 OP_I31
, /* 0 .. 31 */
7130 OP_I31w
, /* 0 .. 31, optional trailing ! */
7131 OP_I32
, /* 1 .. 32 */
7132 OP_I32z
, /* 0 .. 32 */
7133 OP_I48_I64
, /* 48 or 64 */
7134 OP_I63
, /* 0 .. 63 */
7135 OP_I63s
, /* -64 .. 63 */
7136 OP_I64
, /* 1 .. 64 */
7137 OP_I64z
, /* 0 .. 64 */
7138 OP_I127
, /* 0 .. 127 */
7139 OP_I255
, /* 0 .. 255 */
7140 OP_I511
, /* 0 .. 511 */
7141 OP_I4095
, /* 0 .. 4095 */
7142 OP_I8191
, /* 0 .. 8191 */
7143 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7144 OP_I7b
, /* 0 .. 7 */
7145 OP_I15b
, /* 0 .. 15 */
7146 OP_I31b
, /* 0 .. 31 */
7148 OP_SH
, /* shifter operand */
7149 OP_SHG
, /* shifter operand with possible group relocation */
7150 OP_ADDR
, /* Memory address expression (any mode) */
7151 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7152 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7153 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7154 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7155 OP_EXP
, /* arbitrary expression */
7156 OP_EXPi
, /* same, with optional immediate prefix */
7157 OP_EXPr
, /* same, with optional relocation suffix */
7158 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7159 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7160 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7161 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7163 OP_CPSF
, /* CPS flags */
7164 OP_ENDI
, /* Endianness specifier */
7165 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7166 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7167 OP_COND
, /* conditional code */
7168 OP_TB
, /* Table branch. */
7170 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7172 OP_RRnpc_I0
, /* ARM register or literal 0 */
7173 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7174 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7175 OP_RF_IF
, /* FPA register or immediate */
7176 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7177 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7179 /* Optional operands. */
7180 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7181 OP_oI31b
, /* 0 .. 31 */
7182 OP_oI32b
, /* 1 .. 32 */
7183 OP_oI32z
, /* 0 .. 32 */
7184 OP_oIffffb
, /* 0 .. 65535 */
7185 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7187 OP_oRR
, /* ARM register */
7188 OP_oLR
, /* ARM LR register */
7189 OP_oRRnpc
, /* ARM register, not the PC */
7190 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7191 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7192 OP_oRND
, /* Optional Neon double precision register */
7193 OP_oRNQ
, /* Optional Neon quad precision register */
7194 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7195 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7196 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7197 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7199 OP_oRNSDMQ
, /* Optional single, double register or MVE vector
7201 OP_oSHll
, /* LSL immediate */
7202 OP_oSHar
, /* ASR immediate */
7203 OP_oSHllar
, /* LSL or ASR immediate */
7204 OP_oROR
, /* ROR 0/8/16/24 */
7205 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7207 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7209 /* Some pre-defined mixed (ARM/THUMB) operands. */
7210 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7211 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7212 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7214 OP_FIRST_OPTIONAL
= OP_oI7b
7217 /* Generic instruction operand parser. This does no encoding and no
7218 semantic validation; it merely squirrels values away in the inst
7219 structure. Returns SUCCESS or FAIL depending on whether the
7220 specified grammar matched. */
7222 parse_operands (char *str
, const unsigned int *pattern
, bool thumb
)
7224 unsigned const int *upat
= pattern
;
7225 char *backtrack_pos
= 0;
7226 const char *backtrack_error
= 0;
7227 int i
, val
= 0, backtrack_index
= 0;
7228 enum arm_reg_type rtype
;
7229 parse_operand_result result
;
7230 unsigned int op_parse_code
;
7233 #define po_char_or_fail(chr) \
7236 if (skip_past_char (&str, chr) == FAIL) \
7241 #define po_reg_or_fail(regtype) \
7244 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7245 & inst.operands[i].vectype); \
7248 first_error (_(reg_expected_msgs[regtype])); \
7251 inst.operands[i].reg = val; \
7252 inst.operands[i].isreg = 1; \
7253 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7254 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7255 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7256 || rtype == REG_TYPE_VFD \
7257 || rtype == REG_TYPE_NQ); \
7258 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7262 #define po_reg_or_goto(regtype, label) \
7265 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7266 & inst.operands[i].vectype); \
7270 inst.operands[i].reg = val; \
7271 inst.operands[i].isreg = 1; \
7272 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7273 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7274 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7275 || rtype == REG_TYPE_VFD \
7276 || rtype == REG_TYPE_NQ); \
7277 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7281 #define po_imm_or_fail(min, max, popt) \
7284 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7286 inst.operands[i].imm = val; \
7290 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7294 my_get_expression (&exp, &str, popt); \
7295 if (exp.X_op != O_constant) \
7297 inst.error = _("constant expression required"); \
7300 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7302 inst.error = _("immediate value 48 or 64 expected"); \
7305 inst.operands[i].imm = exp.X_add_number; \
7309 #define po_scalar_or_goto(elsz, label, reg_type) \
7312 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7316 inst.operands[i].reg = val; \
7317 inst.operands[i].isscalar = 1; \
7321 #define po_misc_or_fail(expr) \
7329 #define po_misc_or_fail_no_backtrack(expr) \
7333 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7334 backtrack_pos = 0; \
7335 if (result != PARSE_OPERAND_SUCCESS) \
7340 #define po_barrier_or_imm(str) \
7343 val = parse_barrier (&str); \
7344 if (val == FAIL && ! ISALPHA (*str)) \
7347 /* ISB can only take SY as an option. */ \
7348 || ((inst.instruction & 0xf0) == 0x60 \
7351 inst.error = _("invalid barrier type"); \
7352 backtrack_pos = 0; \
7358 skip_whitespace (str
);
7360 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7362 op_parse_code
= upat
[i
];
7363 if (op_parse_code
>= 1<<16)
7364 op_parse_code
= thumb
? (op_parse_code
>> 16)
7365 : (op_parse_code
& ((1<<16)-1));
7367 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7369 /* Remember where we are in case we need to backtrack. */
7370 backtrack_pos
= str
;
7371 backtrack_error
= inst
.error
;
7372 backtrack_index
= i
;
7375 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7376 po_char_or_fail (',');
7378 switch (op_parse_code
)
7392 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7393 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7394 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7395 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7396 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7397 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7400 po_reg_or_goto (REG_TYPE_VFS
, try_rndmqr
);
7404 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7408 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7411 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7413 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7415 /* Also accept generic coprocessor regs for unknown registers. */
7417 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7419 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7420 existing register with a value of 0, this seems like the
7421 best way to parse P0. */
7423 if (strncasecmp (str
, "P0", 2) == 0)
7426 inst
.operands
[i
].isreg
= 1;
7427 inst
.operands
[i
].reg
= 13;
7432 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7433 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7434 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7435 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7436 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7437 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7438 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7439 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7440 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7441 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7444 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7447 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7448 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7450 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7455 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7459 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7461 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7464 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7466 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7470 po_reg_or_goto (REG_TYPE_NSD
, try_mq2
);
7473 po_reg_or_fail (REG_TYPE_MQ
);
7476 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7478 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7483 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7486 po_reg_or_fail (REG_TYPE_NSDQ
);
7490 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7494 po_reg_or_fail (REG_TYPE_MQ
);
7496 /* Neon scalar. Using an element size of 8 means that some invalid
7497 scalars are accepted here, so deal with those in later code. */
7498 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7502 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7505 po_imm_or_fail (0, 0, true);
7510 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7514 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7519 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7522 if (parse_ifimm_zero (&str
))
7523 inst
.operands
[i
].imm
= 0;
7527 = _("only floating point zero is allowed as immediate value");
7535 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7538 po_reg_or_fail (REG_TYPE_RN
);
7542 case OP_RNSDQ_RNSC_MQ_RR
:
7543 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7546 case OP_RNSDQ_RNSC_MQ
:
7547 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7552 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7556 po_reg_or_fail (REG_TYPE_NSDQ
);
7563 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7566 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7569 po_reg_or_fail (REG_TYPE_NSD
);
7573 case OP_RNDQMQ_RNSC_RR
:
7574 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7577 case OP_RNDQ_RNSC_RR
:
7578 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7580 case OP_RNDQMQ_RNSC
:
7581 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7586 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7589 po_reg_or_fail (REG_TYPE_NDQ
);
7595 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7598 po_reg_or_fail (REG_TYPE_VFD
);
7603 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7604 not careful then bad things might happen. */
7605 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7608 case OP_RNDQMQ_Ibig
:
7609 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7614 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7617 /* There's a possibility of getting a 64-bit immediate here, so
7618 we need special handling. */
7619 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/false)
7622 inst
.error
= _("immediate value is out of range");
7628 case OP_RNDQMQ_I63b_RR
:
7629 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7632 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7637 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7640 po_imm_or_fail (0, 63, true);
7645 po_char_or_fail ('[');
7646 po_reg_or_fail (REG_TYPE_RN
);
7647 po_char_or_fail (']');
7653 po_reg_or_fail (REG_TYPE_RN
);
7654 if (skip_past_char (&str
, '!') == SUCCESS
)
7655 inst
.operands
[i
].writeback
= 1;
7659 case OP_I7
: po_imm_or_fail ( 0, 7, false); break;
7660 case OP_I15
: po_imm_or_fail ( 0, 15, false); break;
7661 case OP_I16
: po_imm_or_fail ( 1, 16, false); break;
7662 case OP_I16z
: po_imm_or_fail ( 0, 16, false); break;
7663 case OP_I31
: po_imm_or_fail ( 0, 31, false); break;
7664 case OP_I32
: po_imm_or_fail ( 1, 32, false); break;
7665 case OP_I32z
: po_imm_or_fail ( 0, 32, false); break;
7666 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, false); break;
7667 case OP_I63s
: po_imm_or_fail (-64, 63, false); break;
7668 case OP_I63
: po_imm_or_fail ( 0, 63, false); break;
7669 case OP_I64
: po_imm_or_fail ( 1, 64, false); break;
7670 case OP_I64z
: po_imm_or_fail ( 0, 64, false); break;
7671 case OP_I127
: po_imm_or_fail ( 0, 127, false); break;
7672 case OP_I255
: po_imm_or_fail ( 0, 255, false); break;
7673 case OP_I511
: po_imm_or_fail ( 0, 511, false); break;
7674 case OP_I4095
: po_imm_or_fail ( 0, 4095, false); break;
7675 case OP_I8191
: po_imm_or_fail ( 0, 8191, false); break;
7676 case OP_I4b
: po_imm_or_fail ( 1, 4, true); break;
7678 case OP_I7b
: po_imm_or_fail ( 0, 7, true); break;
7679 case OP_I15b
: po_imm_or_fail ( 0, 15, true); break;
7681 case OP_I31b
: po_imm_or_fail ( 0, 31, true); break;
7682 case OP_oI32b
: po_imm_or_fail ( 1, 32, true); break;
7683 case OP_oI32z
: po_imm_or_fail ( 0, 32, true); break;
7684 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, true); break;
7686 /* Immediate variants */
7688 po_char_or_fail ('{');
7689 po_imm_or_fail (0, 255, true);
7690 po_char_or_fail ('}');
7694 /* The expression parser chokes on a trailing !, so we have
7695 to find it first and zap it. */
7698 while (*s
&& *s
!= ',')
7703 inst
.operands
[i
].writeback
= 1;
7705 po_imm_or_fail (0, 31, true);
7713 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7718 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7723 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7725 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7727 val
= parse_reloc (&str
);
7730 inst
.error
= _("unrecognized relocation suffix");
7733 else if (val
!= BFD_RELOC_UNUSED
)
7735 inst
.operands
[i
].imm
= val
;
7736 inst
.operands
[i
].hasreloc
= 1;
7742 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7744 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7746 inst
.operands
[i
].hasreloc
= 1;
7748 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7750 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7751 inst
.operands
[i
].hasreloc
= 0;
7755 /* Operand for MOVW or MOVT. */
7757 po_misc_or_fail (parse_half (&str
));
7760 /* Register or expression. */
7761 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7762 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7764 /* Register or immediate. */
7765 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7766 I0
: po_imm_or_fail (0, 0, false); break;
7768 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7769 I32
: po_imm_or_fail (1, 32, false); break;
7771 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7773 if (!is_immediate_prefix (*str
))
7776 val
= parse_fpa_immediate (&str
);
7779 /* FPA immediates are encoded as registers 8-15.
7780 parse_fpa_immediate has already applied the offset. */
7781 inst
.operands
[i
].reg
= val
;
7782 inst
.operands
[i
].isreg
= 1;
7785 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7786 I32z
: po_imm_or_fail (0, 32, false); break;
7788 /* Two kinds of register. */
7791 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7793 || (rege
->type
!= REG_TYPE_MMXWR
7794 && rege
->type
!= REG_TYPE_MMXWC
7795 && rege
->type
!= REG_TYPE_MMXWCG
))
7797 inst
.error
= _("iWMMXt data or control register expected");
7800 inst
.operands
[i
].reg
= rege
->number
;
7801 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7807 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7809 || (rege
->type
!= REG_TYPE_MMXWC
7810 && rege
->type
!= REG_TYPE_MMXWCG
))
7812 inst
.error
= _("iWMMXt control register expected");
7815 inst
.operands
[i
].reg
= rege
->number
;
7816 inst
.operands
[i
].isreg
= 1;
7821 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7822 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7823 case OP_oROR
: val
= parse_ror (&str
); break;
7825 case OP_COND
: val
= parse_cond (&str
); break;
7826 case OP_oBARRIER_I15
:
7827 po_barrier_or_imm (str
); break;
7829 if (parse_immediate (&str
, &val
, 0, 15, true) == FAIL
)
7835 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7836 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7838 inst
.error
= _("Banked registers are not available with this "
7844 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7848 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7851 val
= parse_sys_vldr_vstr (&str
);
7855 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7858 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7860 if (strncasecmp (str
, "APSR_", 5) == 0)
7867 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7868 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7869 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7870 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7871 default: found
= 16;
7875 inst
.operands
[i
].isvec
= 1;
7876 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7877 inst
.operands
[i
].reg
= REG_PC
;
7884 po_misc_or_fail (parse_tb (&str
));
7887 /* Register lists. */
7889 val
= parse_reg_list (&str
, REGLIST_RN
);
7892 inst
.operands
[i
].writeback
= 1;
7898 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7902 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7907 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7912 /* Allow Q registers too. */
7913 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7914 REGLIST_NEON_D
, &partial_match
);
7918 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7919 REGLIST_VFP_S
, &partial_match
);
7920 inst
.operands
[i
].issingle
= 1;
7925 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7926 REGLIST_VFP_D_VPR
, &partial_match
);
7927 if (val
== FAIL
&& !partial_match
)
7930 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7931 REGLIST_VFP_S_VPR
, &partial_match
);
7932 inst
.operands
[i
].issingle
= 1;
7937 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7938 REGLIST_NEON_D
, &partial_match
);
7943 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7944 1, &inst
.operands
[i
].vectype
);
7945 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7949 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7950 0, &inst
.operands
[i
].vectype
);
7953 /* Addressing modes */
7955 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7959 po_misc_or_fail (parse_address (&str
, i
));
7963 po_misc_or_fail_no_backtrack (
7964 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7968 po_misc_or_fail_no_backtrack (
7969 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7973 po_misc_or_fail_no_backtrack (
7974 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7978 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7982 po_misc_or_fail_no_backtrack (
7983 parse_shifter_operand_group_reloc (&str
, i
));
7987 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7991 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7995 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
8000 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
8005 po_reg_or_goto (REG_TYPE_RN
, ZR
);
8008 po_reg_or_fail (REG_TYPE_ZR
);
8012 as_fatal (_("unhandled operand code %d"), op_parse_code
);
8015 /* Various value-based sanity checks and shared operations. We
8016 do not signal immediate failures for the register constraints;
8017 this allows a syntax error to take precedence. */
8018 switch (op_parse_code
)
8026 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
8027 inst
.error
= BAD_PC
;
8032 case OP_RRnpcsp_I32
:
8033 if (inst
.operands
[i
].isreg
)
8035 if (inst
.operands
[i
].reg
== REG_PC
)
8036 inst
.error
= BAD_PC
;
8037 else if (inst
.operands
[i
].reg
== REG_SP
8038 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
8039 relaxed since ARMv8-A. */
8040 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8043 inst
.error
= BAD_SP
;
8049 if (inst
.operands
[i
].isreg
8050 && inst
.operands
[i
].reg
== REG_PC
8051 && (inst
.operands
[i
].writeback
|| thumb
))
8052 inst
.error
= BAD_PC
;
8057 if (inst
.operands
[i
].isreg
)
8067 case OP_oBARRIER_I15
:
8080 inst
.operands
[i
].imm
= val
;
8085 if (inst
.operands
[i
].reg
!= REG_LR
)
8086 inst
.error
= _("operand must be LR register");
8090 if (inst
.operands
[i
].reg
!= REG_SP
)
8091 inst
.error
= _("operand must be SP register");
8095 if (inst
.operands
[i
].reg
!= REG_R12
)
8096 inst
.error
= _("operand must be r12");
8102 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
8103 inst
.error
= BAD_PC
;
8107 if (inst
.operands
[i
].isreg
8108 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
8109 inst
.error
= BAD_ODD
;
8113 if (inst
.operands
[i
].isreg
)
8115 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8116 inst
.error
= BAD_EVEN
;
8117 else if (inst
.operands
[i
].reg
== REG_SP
)
8118 as_tsktsk (MVE_BAD_SP
);
8119 else if (inst
.operands
[i
].reg
== REG_PC
)
8120 inst
.error
= BAD_PC
;
8128 /* If we get here, this operand was successfully parsed. */
8129 inst
.operands
[i
].present
= 1;
8133 inst
.error
= BAD_ARGS
;
8138 /* The parse routine should already have set inst.error, but set a
8139 default here just in case. */
8141 inst
.error
= BAD_SYNTAX
;
8145 /* Do not backtrack over a trailing optional argument that
8146 absorbed some text. We will only fail again, with the
8147 'garbage following instruction' error message, which is
8148 probably less helpful than the current one. */
8149 if (backtrack_index
== i
&& backtrack_pos
!= str
8150 && upat
[i
+1] == OP_stop
)
8153 inst
.error
= BAD_SYNTAX
;
8157 /* Try again, skipping the optional argument at backtrack_pos. */
8158 str
= backtrack_pos
;
8159 inst
.error
= backtrack_error
;
8160 inst
.operands
[backtrack_index
].present
= 0;
8161 i
= backtrack_index
;
8165 /* Check that we have parsed all the arguments. */
8166 if (*str
!= '\0' && !inst
.error
)
8167 inst
.error
= _("garbage following instruction");
8169 return inst
.error
? FAIL
: SUCCESS
;
8172 #undef po_char_or_fail
8173 #undef po_reg_or_fail
8174 #undef po_reg_or_goto
8175 #undef po_imm_or_fail
8176 #undef po_scalar_or_fail
8177 #undef po_barrier_or_imm
8179 /* Shorthand macro for instruction encoding functions issuing errors. */
8180 #define constraint(expr, err) \
8191 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8192 instructions are unpredictable if these registers are used. This
8193 is the BadReg predicate in ARM's Thumb-2 documentation.
8195 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8196 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8197 #define reject_bad_reg(reg) \
8199 if (reg == REG_PC) \
8201 inst.error = BAD_PC; \
8204 else if (reg == REG_SP \
8205 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8207 inst.error = BAD_SP; \
8212 /* If REG is R13 (the stack pointer), warn that its use is
8214 #define warn_deprecated_sp(reg) \
8216 if (warn_on_deprecated && reg == REG_SP) \
8217 as_tsktsk (_("use of r13 is deprecated")); \
8220 /* Functions for operand encoding. ARM, then Thumb. */
8222 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8224 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8226 The only binary encoding difference is the Coprocessor number. Coprocessor
8227 9 is used for half-precision calculations or conversions. The format of the
8228 instruction is the same as the equivalent Coprocessor 10 instruction that
8229 exists for Single-Precision operation. */
8232 do_scalar_fp16_v82_encode (void)
8234 if (inst
.cond
< COND_ALWAYS
)
8235 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8236 " the behaviour is UNPREDICTABLE"));
8237 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8240 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8241 mark_feature_used (&arm_ext_fp16
);
8244 /* If VAL can be encoded in the immediate field of an ARM instruction,
8245 return the encoded form. Otherwise, return FAIL. */
8248 encode_arm_immediate (unsigned int val
)
8255 for (i
= 2; i
< 32; i
+= 2)
8256 if ((a
= rotate_left (val
, i
)) <= 0xff)
8257 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8262 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8263 return the encoded form. Otherwise, return FAIL. */
8265 encode_thumb32_immediate (unsigned int val
)
8272 for (i
= 1; i
<= 24; i
++)
8275 if ((val
& ~(0xffU
<< i
)) == 0)
8276 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8280 if (val
== ((a
<< 16) | a
))
8282 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8286 if (val
== ((a
<< 16) | a
))
8287 return 0x200 | (a
>> 8);
8291 /* Encode a VFP SP or DP register number into inst.instruction. */
8294 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8296 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8299 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8302 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8305 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8310 first_error (_("D register out of range for selected VFP version"));
8318 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8322 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8326 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8330 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8334 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8338 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8346 /* Encode a <shift> in an ARM-format instruction. The immediate,
8347 if any, is handled by md_apply_fix. */
8349 encode_arm_shift (int i
)
8351 /* register-shifted register. */
8352 if (inst
.operands
[i
].immisreg
)
8355 for (op_index
= 0; op_index
<= i
; ++op_index
)
8357 /* Check the operand only when it's presented. In pre-UAL syntax,
8358 if the destination register is the same as the first operand, two
8359 register form of the instruction can be used. */
8360 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8361 && inst
.operands
[op_index
].reg
== REG_PC
)
8362 as_warn (UNPRED_REG ("r15"));
8365 if (inst
.operands
[i
].imm
== REG_PC
)
8366 as_warn (UNPRED_REG ("r15"));
8369 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8370 inst
.instruction
|= SHIFT_ROR
<< 5;
8373 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8374 if (inst
.operands
[i
].immisreg
)
8376 inst
.instruction
|= SHIFT_BY_REG
;
8377 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8380 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8385 encode_arm_shifter_operand (int i
)
8387 if (inst
.operands
[i
].isreg
)
8389 inst
.instruction
|= inst
.operands
[i
].reg
;
8390 encode_arm_shift (i
);
8394 inst
.instruction
|= INST_IMMEDIATE
;
8395 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8396 inst
.instruction
|= inst
.operands
[i
].imm
;
8400 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8402 encode_arm_addr_mode_common (int i
, bool is_t
)
8405 Generate an error if the operand is not a register. */
8406 constraint (!inst
.operands
[i
].isreg
,
8407 _("Instruction does not support =N addresses"));
8409 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8411 if (inst
.operands
[i
].preind
)
8415 inst
.error
= _("instruction does not accept preindexed addressing");
8418 inst
.instruction
|= PRE_INDEX
;
8419 if (inst
.operands
[i
].writeback
)
8420 inst
.instruction
|= WRITE_BACK
;
8423 else if (inst
.operands
[i
].postind
)
8425 gas_assert (inst
.operands
[i
].writeback
);
8427 inst
.instruction
|= WRITE_BACK
;
8429 else /* unindexed - only for coprocessor */
8431 inst
.error
= _("instruction does not accept unindexed addressing");
8435 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8436 && (((inst
.instruction
& 0x000f0000) >> 16)
8437 == ((inst
.instruction
& 0x0000f000) >> 12)))
8438 as_warn ((inst
.instruction
& LOAD_BIT
)
8439 ? _("destination register same as write-back base")
8440 : _("source register same as write-back base"));
8443 /* inst.operands[i] was set up by parse_address. Encode it into an
8444 ARM-format mode 2 load or store instruction. If is_t is true,
8445 reject forms that cannot be used with a T instruction (i.e. not
8448 encode_arm_addr_mode_2 (int i
, bool is_t
)
8450 const bool is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8452 encode_arm_addr_mode_common (i
, is_t
);
8454 if (inst
.operands
[i
].immisreg
)
8456 constraint ((inst
.operands
[i
].imm
== REG_PC
8457 || (is_pc
&& inst
.operands
[i
].writeback
)),
8459 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8460 inst
.instruction
|= inst
.operands
[i
].imm
;
8461 if (!inst
.operands
[i
].negative
)
8462 inst
.instruction
|= INDEX_UP
;
8463 if (inst
.operands
[i
].shifted
)
8465 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8466 inst
.instruction
|= SHIFT_ROR
<< 5;
8469 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8470 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8474 else /* immediate offset in inst.relocs[0] */
8476 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8478 const bool is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8480 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8481 cannot use PC in addressing.
8482 PC cannot be used in writeback addressing, either. */
8483 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8486 /* Use of PC in str is deprecated for ARMv7. */
8487 if (warn_on_deprecated
8489 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8490 as_tsktsk (_("use of PC in this instruction is deprecated"));
8493 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8495 /* Prefer + for zero encoded value. */
8496 if (!inst
.operands
[i
].negative
)
8497 inst
.instruction
|= INDEX_UP
;
8498 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8503 /* inst.operands[i] was set up by parse_address. Encode it into an
8504 ARM-format mode 3 load or store instruction. Reject forms that
8505 cannot be used with such instructions. If is_t is true, reject
8506 forms that cannot be used with a T instruction (i.e. not
8509 encode_arm_addr_mode_3 (int i
, bool is_t
)
8511 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8513 inst
.error
= _("instruction does not accept scaled register index");
8517 encode_arm_addr_mode_common (i
, is_t
);
8519 if (inst
.operands
[i
].immisreg
)
8521 constraint ((inst
.operands
[i
].imm
== REG_PC
8522 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8524 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8526 inst
.instruction
|= inst
.operands
[i
].imm
;
8527 if (!inst
.operands
[i
].negative
)
8528 inst
.instruction
|= INDEX_UP
;
8530 else /* immediate offset in inst.relocs[0] */
8532 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8533 && inst
.operands
[i
].writeback
),
8535 inst
.instruction
|= HWOFFSET_IMM
;
8536 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8538 /* Prefer + for zero encoded value. */
8539 if (!inst
.operands
[i
].negative
)
8540 inst
.instruction
|= INDEX_UP
;
8542 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8547 /* Write immediate bits [7:0] to the following locations:
8549 |28/24|23 19|18 16|15 4|3 0|
8550 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8552 This function is used by VMOV/VMVN/VORR/VBIC. */
8555 neon_write_immbits (unsigned immbits
)
8557 inst
.instruction
|= immbits
& 0xf;
8558 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8559 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8562 /* Invert low-order SIZE bits of XHI:XLO. */
8565 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8567 unsigned immlo
= xlo
? *xlo
: 0;
8568 unsigned immhi
= xhi
? *xhi
: 0;
8573 immlo
= (~immlo
) & 0xff;
8577 immlo
= (~immlo
) & 0xffff;
8581 immhi
= (~immhi
) & 0xffffffff;
8585 immlo
= (~immlo
) & 0xffffffff;
8599 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8603 neon_bits_same_in_bytes (unsigned imm
)
8605 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8606 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8607 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8608 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8611 /* For immediate of above form, return 0bABCD. */
8614 neon_squash_bits (unsigned imm
)
8616 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8617 | ((imm
& 0x01000000) >> 21);
8620 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8623 neon_qfloat_bits (unsigned imm
)
8625 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8628 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8629 the instruction. *OP is passed as the initial value of the op field, and
8630 may be set to a different value depending on the constant (i.e.
8631 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8632 MVN). If the immediate looks like a repeated pattern then also
8633 try smaller element sizes. */
8636 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8637 unsigned *immbits
, int *op
, int size
,
8638 enum neon_el_type type
)
8640 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8642 if (type
== NT_float
&& !float_p
)
8645 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8647 if (size
!= 32 || *op
== 1)
8649 *immbits
= neon_qfloat_bits (immlo
);
8655 if (neon_bits_same_in_bytes (immhi
)
8656 && neon_bits_same_in_bytes (immlo
))
8660 *immbits
= (neon_squash_bits (immhi
) << 4)
8661 | neon_squash_bits (immlo
);
8672 if (immlo
== (immlo
& 0x000000ff))
8677 else if (immlo
== (immlo
& 0x0000ff00))
8679 *immbits
= immlo
>> 8;
8682 else if (immlo
== (immlo
& 0x00ff0000))
8684 *immbits
= immlo
>> 16;
8687 else if (immlo
== (immlo
& 0xff000000))
8689 *immbits
= immlo
>> 24;
8692 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8694 *immbits
= (immlo
>> 8) & 0xff;
8697 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8699 *immbits
= (immlo
>> 16) & 0xff;
8703 if ((immlo
& 0xffff) != (immlo
>> 16))
8710 if (immlo
== (immlo
& 0x000000ff))
8715 else if (immlo
== (immlo
& 0x0000ff00))
8717 *immbits
= immlo
>> 8;
8721 if ((immlo
& 0xff) != (immlo
>> 8))
8726 if (immlo
== (immlo
& 0x000000ff))
8728 /* Don't allow MVN with 8-bit immediate. */
8738 #if defined BFD_HOST_64_BIT
8739 /* Returns TRUE if double precision value V may be cast
8740 to single precision without loss of accuracy. */
8743 is_double_a_single (bfd_uint64_t v
)
8745 int exp
= (v
>> 52) & 0x7FF;
8746 bfd_uint64_t mantissa
= v
& 0xFFFFFFFFFFFFFULL
;
8748 return ((exp
== 0 || exp
== 0x7FF
8749 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8750 && (mantissa
& 0x1FFFFFFFL
) == 0);
8753 /* Returns a double precision value casted to single precision
8754 (ignoring the least significant bits in exponent and mantissa). */
8757 double_to_single (bfd_uint64_t v
)
8759 unsigned int sign
= (v
>> 63) & 1;
8760 int exp
= (v
>> 52) & 0x7FF;
8761 bfd_uint64_t mantissa
= v
& 0xFFFFFFFFFFFFFULL
;
8767 exp
= exp
- 1023 + 127;
8776 /* No denormalized numbers. */
8782 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8784 #endif /* BFD_HOST_64_BIT */
8793 static void do_vfp_nsyn_opcode (const char *);
8795 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8796 Determine whether it can be performed with a move instruction; if
8797 it can, convert inst.instruction to that move instruction and
8798 return true; if it can't, convert inst.instruction to a literal-pool
8799 load and return FALSE. If this is not a valid thing to do in the
8800 current context, set inst.error and return TRUE.
8802 inst.operands[i] describes the destination register. */
8805 move_or_literal_pool (int i
, enum lit_type t
, bool mode_3
)
8808 bool thumb_p
= (t
== CONST_THUMB
);
8809 bool arm_p
= (t
== CONST_ARM
);
8812 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8816 if ((inst
.instruction
& tbit
) == 0)
8818 inst
.error
= _("invalid pseudo operation");
8822 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8823 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8824 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8826 inst
.error
= _("constant expression expected");
8830 if (inst
.relocs
[0].exp
.X_op
== O_constant
8831 || inst
.relocs
[0].exp
.X_op
== O_big
)
8833 #if defined BFD_HOST_64_BIT
8838 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8840 LITTLENUM_TYPE w
[X_PRECISION
];
8843 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8845 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8847 /* FIXME: Should we check words w[2..5] ? */
8852 #if defined BFD_HOST_64_BIT
8853 v
= l
[3] & LITTLENUM_MASK
;
8854 v
<<= LITTLENUM_NUMBER_OF_BITS
;
8855 v
|= l
[2] & LITTLENUM_MASK
;
8856 v
<<= LITTLENUM_NUMBER_OF_BITS
;
8857 v
|= l
[1] & LITTLENUM_MASK
;
8858 v
<<= LITTLENUM_NUMBER_OF_BITS
;
8859 v
|= l
[0] & LITTLENUM_MASK
;
8861 v
= l
[1] & LITTLENUM_MASK
;
8862 v
<<= LITTLENUM_NUMBER_OF_BITS
;
8863 v
|= l
[0] & LITTLENUM_MASK
;
8867 v
= inst
.relocs
[0].exp
.X_add_number
;
8869 if (!inst
.operands
[i
].issingle
)
8873 /* LDR should not use lead in a flag-setting instruction being
8874 chosen so we do not check whether movs can be used. */
8876 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8877 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8878 && inst
.operands
[i
].reg
!= 13
8879 && inst
.operands
[i
].reg
!= 15)
8881 /* Check if on thumb2 it can be done with a mov.w, mvn or
8882 movw instruction. */
8883 unsigned int newimm
;
8884 bool isNegated
= false;
8886 newimm
= encode_thumb32_immediate (v
);
8887 if (newimm
== (unsigned int) FAIL
)
8889 newimm
= encode_thumb32_immediate (~v
);
8893 /* The number can be loaded with a mov.w or mvn
8895 if (newimm
!= (unsigned int) FAIL
8896 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8898 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8899 | (inst
.operands
[i
].reg
<< 8));
8900 /* Change to MOVN. */
8901 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8902 inst
.instruction
|= (newimm
& 0x800) << 15;
8903 inst
.instruction
|= (newimm
& 0x700) << 4;
8904 inst
.instruction
|= (newimm
& 0x0ff);
8907 /* The number can be loaded with a movw instruction. */
8908 else if ((v
& ~0xFFFF) == 0
8909 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8911 int imm
= v
& 0xFFFF;
8913 inst
.instruction
= 0xf2400000; /* MOVW. */
8914 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8915 inst
.instruction
|= (imm
& 0xf000) << 4;
8916 inst
.instruction
|= (imm
& 0x0800) << 15;
8917 inst
.instruction
|= (imm
& 0x0700) << 4;
8918 inst
.instruction
|= (imm
& 0x00ff);
8919 /* In case this replacement is being done on Armv8-M
8920 Baseline we need to make sure to disable the
8921 instruction size check, as otherwise GAS will reject
8922 the use of this T32 instruction. */
8930 int value
= encode_arm_immediate (v
);
8934 /* This can be done with a mov instruction. */
8935 inst
.instruction
&= LITERAL_MASK
;
8936 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8937 inst
.instruction
|= value
& 0xfff;
8941 value
= encode_arm_immediate (~ v
);
8944 /* This can be done with a mvn instruction. */
8945 inst
.instruction
&= LITERAL_MASK
;
8946 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8947 inst
.instruction
|= value
& 0xfff;
8951 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8954 unsigned immbits
= 0;
8955 unsigned immlo
= inst
.operands
[1].imm
;
8956 unsigned immhi
= inst
.operands
[1].regisimm
8957 ? inst
.operands
[1].reg
8958 : inst
.relocs
[0].exp
.X_unsigned
8960 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8961 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, false, &immbits
,
8962 &op
, 64, NT_invtype
);
8966 neon_invert_size (&immlo
, &immhi
, 64);
8968 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, false, &immbits
,
8969 &op
, 64, NT_invtype
);
8974 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8980 /* Fill other bits in vmov encoding for both thumb and arm. */
8982 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8984 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8985 neon_write_immbits (immbits
);
8993 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8994 if (inst
.operands
[i
].issingle
8995 && is_quarter_float (inst
.operands
[1].imm
)
8996 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8998 inst
.operands
[1].imm
=
8999 neon_qfloat_bits (v
);
9000 do_vfp_nsyn_opcode ("fconsts");
9004 /* If our host does not support a 64-bit type then we cannot perform
9005 the following optimization. This mean that there will be a
9006 discrepancy between the output produced by an assembler built for
9007 a 32-bit-only host and the output produced from a 64-bit host, but
9008 this cannot be helped. */
9009 #if defined BFD_HOST_64_BIT
9010 else if (!inst
.operands
[1].issingle
9011 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
9013 if (is_double_a_single (v
)
9014 && is_quarter_float (double_to_single (v
)))
9016 inst
.operands
[1].imm
=
9017 neon_qfloat_bits (double_to_single (v
));
9018 do_vfp_nsyn_opcode ("fconstd");
9026 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
9027 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
9030 inst
.operands
[1].reg
= REG_PC
;
9031 inst
.operands
[1].isreg
= 1;
9032 inst
.operands
[1].preind
= 1;
9033 inst
.relocs
[0].pc_rel
= 1;
9034 inst
.relocs
[0].type
= (thumb_p
9035 ? BFD_RELOC_ARM_THUMB_OFFSET
9037 ? BFD_RELOC_ARM_HWLITERAL
9038 : BFD_RELOC_ARM_LITERAL
));
9042 /* inst.operands[i] was set up by parse_address. Encode it into an
9043 ARM-format instruction. Reject all forms which cannot be encoded
9044 into a coprocessor load/store instruction. If wb_ok is false,
9045 reject use of writeback; if unind_ok is false, reject use of
9046 unindexed addressing. If reloc_override is not 0, use it instead
9047 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
9048 (in which case it is preserved). */
9051 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
9053 if (!inst
.operands
[i
].isreg
)
9056 if (! inst
.operands
[0].isvec
)
9058 inst
.error
= _("invalid co-processor operand");
9061 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/false))
9065 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9067 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
9069 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
9071 gas_assert (!inst
.operands
[i
].writeback
);
9074 inst
.error
= _("instruction does not support unindexed addressing");
9077 inst
.instruction
|= inst
.operands
[i
].imm
;
9078 inst
.instruction
|= INDEX_UP
;
9082 if (inst
.operands
[i
].preind
)
9083 inst
.instruction
|= PRE_INDEX
;
9085 if (inst
.operands
[i
].writeback
)
9087 if (inst
.operands
[i
].reg
== REG_PC
)
9089 inst
.error
= _("pc may not be used with write-back");
9094 inst
.error
= _("instruction does not support writeback");
9097 inst
.instruction
|= WRITE_BACK
;
9101 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
9102 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
9103 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
9104 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
9107 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
9109 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9112 /* Prefer + for zero encoded value. */
9113 if (!inst
.operands
[i
].negative
)
9114 inst
.instruction
|= INDEX_UP
;
9119 /* Functions for instruction encoding, sorted by sub-architecture.
9120 First some generics; their names are taken from the conventional
9121 bit positions for register arguments in ARM format instructions. */
9131 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9137 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9143 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9144 inst
.instruction
|= inst
.operands
[1].reg
;
9150 inst
.instruction
|= inst
.operands
[0].reg
;
9151 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9157 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9158 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9164 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9165 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9171 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9172 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9176 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9178 if (ARM_CPU_IS_ANY (cpu_variant
))
9180 as_tsktsk ("%s", msg
);
9183 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9195 unsigned Rn
= inst
.operands
[2].reg
;
9196 /* Enforce restrictions on SWP instruction. */
9197 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9199 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9200 _("Rn must not overlap other operands"));
9202 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9204 if (!check_obsolete (&arm_ext_v8
,
9205 _("swp{b} use is obsoleted for ARMv8 and later"))
9206 && warn_on_deprecated
9207 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9208 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9211 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9212 inst
.instruction
|= inst
.operands
[1].reg
;
9213 inst
.instruction
|= Rn
<< 16;
9219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9220 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9221 inst
.instruction
|= inst
.operands
[2].reg
;
9227 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9228 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9229 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9230 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9232 inst
.instruction
|= inst
.operands
[0].reg
;
9233 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9234 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9240 inst
.instruction
|= inst
.operands
[0].imm
;
9246 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9247 encode_arm_cp_address (1, true, true, 0);
9250 /* ARM instructions, in alphabetical order by function name (except
9251 that wrapper functions appear immediately after the function they
9254 /* This is a pseudo-op of the form "adr rd, label" to be converted
9255 into a relative address of the form "add rd, pc, #label-.-8". */
9260 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9262 /* Frag hacking will turn this into a sub instruction if the offset turns
9263 out to be negative. */
9264 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9265 inst
.relocs
[0].pc_rel
= 1;
9266 inst
.relocs
[0].exp
.X_add_number
-= 8;
9268 if (support_interwork
9269 && inst
.relocs
[0].exp
.X_op
== O_symbol
9270 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9271 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9272 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9273 inst
.relocs
[0].exp
.X_add_number
|= 1;
9276 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9277 into a relative address of the form:
9278 add rd, pc, #low(label-.-8)"
9279 add rd, rd, #high(label-.-8)" */
9284 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9286 /* Frag hacking will turn this into a sub instruction if the offset turns
9287 out to be negative. */
9288 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9289 inst
.relocs
[0].pc_rel
= 1;
9290 inst
.size
= INSN_SIZE
* 2;
9291 inst
.relocs
[0].exp
.X_add_number
-= 8;
9293 if (support_interwork
9294 && inst
.relocs
[0].exp
.X_op
== O_symbol
9295 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9296 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9297 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9298 inst
.relocs
[0].exp
.X_add_number
|= 1;
9304 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9305 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9307 if (!inst
.operands
[1].present
)
9308 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9309 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9310 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9311 encode_arm_shifter_operand (2);
9317 if (inst
.operands
[0].present
)
9318 inst
.instruction
|= inst
.operands
[0].imm
;
9320 inst
.instruction
|= 0xf;
9326 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9327 constraint (msb
> 32, _("bit-field extends past end of register"));
9328 /* The instruction encoding stores the LSB and MSB,
9329 not the LSB and width. */
9330 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9331 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9332 inst
.instruction
|= (msb
- 1) << 16;
9340 /* #0 in second position is alternative syntax for bfc, which is
9341 the same instruction but with REG_PC in the Rm field. */
9342 if (!inst
.operands
[1].isreg
)
9343 inst
.operands
[1].reg
= REG_PC
;
9345 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9346 constraint (msb
> 32, _("bit-field extends past end of register"));
9347 /* The instruction encoding stores the LSB and MSB,
9348 not the LSB and width. */
9349 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9350 inst
.instruction
|= inst
.operands
[1].reg
;
9351 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9352 inst
.instruction
|= (msb
- 1) << 16;
9358 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9359 _("bit-field extends past end of register"));
9360 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9361 inst
.instruction
|= inst
.operands
[1].reg
;
9362 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9363 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9366 /* ARM V5 breakpoint instruction (argument parse)
9367 BKPT <16 bit unsigned immediate>
9368 Instruction is not conditional.
9369 The bit pattern given in insns[] has the COND_ALWAYS condition,
9370 and it is an error if the caller tried to override that. */
9375 /* Top 12 of 16 bits to bits 19:8. */
9376 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9378 /* Bottom 4 of 16 bits to bits 3:0. */
9379 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9383 encode_branch (int default_reloc
)
9385 if (inst
.operands
[0].hasreloc
)
9387 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9388 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9389 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9390 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9391 ? BFD_RELOC_ARM_PLT32
9392 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9395 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9396 inst
.relocs
[0].pc_rel
= 1;
9403 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9404 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9407 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9414 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9416 if (inst
.cond
== COND_ALWAYS
)
9417 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9419 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9423 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9426 /* ARM V5 branch-link-exchange instruction (argument parse)
9427 BLX <target_addr> ie BLX(1)
9428 BLX{<condition>} <Rm> ie BLX(2)
9429 Unfortunately, there are two different opcodes for this mnemonic.
9430 So, the insns[].value is not used, and the code here zaps values
9431 into inst.instruction.
9432 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9437 if (inst
.operands
[0].isreg
)
9439 /* Arg is a register; the opcode provided by insns[] is correct.
9440 It is not illegal to do "blx pc", just useless. */
9441 if (inst
.operands
[0].reg
== REG_PC
)
9442 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9444 inst
.instruction
|= inst
.operands
[0].reg
;
9448 /* Arg is an address; this instruction cannot be executed
9449 conditionally, and the opcode must be adjusted.
9450 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9451 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9452 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9453 inst
.instruction
= 0xfa000000;
9454 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9463 if (inst
.operands
[0].reg
== REG_PC
)
9464 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9466 inst
.instruction
|= inst
.operands
[0].reg
;
9467 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9468 it is for ARMv4t or earlier. */
9469 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9470 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9471 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9475 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9480 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9484 /* ARM v5TEJ. Jump to Jazelle code. */
9489 if (inst
.operands
[0].reg
== REG_PC
)
9490 as_tsktsk (_("use of r15 in bxj is not really useful"));
9492 inst
.instruction
|= inst
.operands
[0].reg
;
9495 /* Co-processor data operation:
9496 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9497 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9501 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9502 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9503 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9504 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9505 inst
.instruction
|= inst
.operands
[4].reg
;
9506 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9512 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9513 encode_arm_shifter_operand (1);
9516 /* Transfer between coprocessor and ARM registers.
9517 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9522 No special properties. */
9524 struct deprecated_coproc_regs_s
9531 arm_feature_set deprecated
;
9532 arm_feature_set obsoleted
;
9533 const char *dep_msg
;
9534 const char *obs_msg
;
9537 #define DEPR_ACCESS_V8 \
9538 N_("This coprocessor register access is deprecated in ARMv8")
9540 /* Table of all deprecated coprocessor registers. */
9541 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9543 {15, 0, 7, 10, 5, /* CP15DMB. */
9544 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9545 DEPR_ACCESS_V8
, NULL
},
9546 {15, 0, 7, 10, 4, /* CP15DSB. */
9547 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9548 DEPR_ACCESS_V8
, NULL
},
9549 {15, 0, 7, 5, 4, /* CP15ISB. */
9550 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9551 DEPR_ACCESS_V8
, NULL
},
9552 {14, 6, 1, 0, 0, /* TEEHBR. */
9553 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9554 DEPR_ACCESS_V8
, NULL
},
9555 {14, 6, 0, 0, 0, /* TEECR. */
9556 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9557 DEPR_ACCESS_V8
, NULL
},
9560 #undef DEPR_ACCESS_V8
9562 static const size_t deprecated_coproc_reg_count
=
9563 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9571 Rd
= inst
.operands
[2].reg
;
9574 if (inst
.instruction
== 0xee000010
9575 || inst
.instruction
== 0xfe000010)
9577 reject_bad_reg (Rd
);
9578 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9580 constraint (Rd
== REG_SP
, BAD_SP
);
9585 if (inst
.instruction
== 0xe000010)
9586 constraint (Rd
== REG_PC
, BAD_PC
);
9589 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9591 const struct deprecated_coproc_regs_s
*r
=
9592 deprecated_coproc_regs
+ i
;
9594 if (inst
.operands
[0].reg
== r
->cp
9595 && inst
.operands
[1].imm
== r
->opc1
9596 && inst
.operands
[3].reg
== r
->crn
9597 && inst
.operands
[4].reg
== r
->crm
9598 && inst
.operands
[5].imm
== r
->opc2
)
9600 if (! ARM_CPU_IS_ANY (cpu_variant
)
9601 && warn_on_deprecated
9602 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9603 as_tsktsk ("%s", r
->dep_msg
);
9607 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9608 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9609 inst
.instruction
|= Rd
<< 12;
9610 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9611 inst
.instruction
|= inst
.operands
[4].reg
;
9612 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9615 /* Transfer between coprocessor register and pair of ARM registers.
9616 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9621 Two XScale instructions are special cases of these:
9623 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9624 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9626 Result unpredictable if Rd or Rn is R15. */
9633 Rd
= inst
.operands
[2].reg
;
9634 Rn
= inst
.operands
[3].reg
;
9638 reject_bad_reg (Rd
);
9639 reject_bad_reg (Rn
);
9643 constraint (Rd
== REG_PC
, BAD_PC
);
9644 constraint (Rn
== REG_PC
, BAD_PC
);
9647 /* Only check the MRRC{2} variants. */
9648 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9650 /* If Rd == Rn, error that the operation is
9651 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9652 constraint (Rd
== Rn
, BAD_OVERLAP
);
9655 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9656 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9657 inst
.instruction
|= Rd
<< 12;
9658 inst
.instruction
|= Rn
<< 16;
9659 inst
.instruction
|= inst
.operands
[4].reg
;
9665 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9666 if (inst
.operands
[1].present
)
9668 inst
.instruction
|= CPSI_MMOD
;
9669 inst
.instruction
|= inst
.operands
[1].imm
;
9676 inst
.instruction
|= inst
.operands
[0].imm
;
9682 unsigned Rd
, Rn
, Rm
;
9684 Rd
= inst
.operands
[0].reg
;
9685 Rn
= (inst
.operands
[1].present
9686 ? inst
.operands
[1].reg
: Rd
);
9687 Rm
= inst
.operands
[2].reg
;
9689 constraint ((Rd
== REG_PC
), BAD_PC
);
9690 constraint ((Rn
== REG_PC
), BAD_PC
);
9691 constraint ((Rm
== REG_PC
), BAD_PC
);
9693 inst
.instruction
|= Rd
<< 16;
9694 inst
.instruction
|= Rn
<< 0;
9695 inst
.instruction
|= Rm
<< 8;
9701 /* There is no IT instruction in ARM mode. We
9702 process it to do the validation as if in
9703 thumb mode, just in case the code gets
9704 assembled for thumb using the unified syntax. */
9709 set_pred_insn_type (IT_INSN
);
9710 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9711 now_pred
.cc
= inst
.operands
[0].imm
;
9715 /* If there is only one register in the register list,
9716 then return its register number. Otherwise return -1. */
9718 only_one_reg_in_list (int range
)
9720 int i
= ffs (range
) - 1;
9721 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9725 encode_ldmstm(int from_push_pop_mnem
)
9727 int base_reg
= inst
.operands
[0].reg
;
9728 int range
= inst
.operands
[1].imm
;
9731 inst
.instruction
|= base_reg
<< 16;
9732 inst
.instruction
|= range
;
9734 if (inst
.operands
[1].writeback
)
9735 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9737 if (inst
.operands
[0].writeback
)
9739 inst
.instruction
|= WRITE_BACK
;
9740 /* Check for unpredictable uses of writeback. */
9741 if (inst
.instruction
& LOAD_BIT
)
9743 /* Not allowed in LDM type 2. */
9744 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9745 && ((range
& (1 << REG_PC
)) == 0))
9746 as_warn (_("writeback of base register is UNPREDICTABLE"));
9747 /* Only allowed if base reg not in list for other types. */
9748 else if (range
& (1 << base_reg
))
9749 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9753 /* Not allowed for type 2. */
9754 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9755 as_warn (_("writeback of base register is UNPREDICTABLE"));
9756 /* Only allowed if base reg not in list, or first in list. */
9757 else if ((range
& (1 << base_reg
))
9758 && (range
& ((1 << base_reg
) - 1)))
9759 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9763 /* If PUSH/POP has only one register, then use the A2 encoding. */
9764 one_reg
= only_one_reg_in_list (range
);
9765 if (from_push_pop_mnem
&& one_reg
>= 0)
9767 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9769 if (is_push
&& one_reg
== 13 /* SP */)
9770 /* PR 22483: The A2 encoding cannot be used when
9771 pushing the stack pointer as this is UNPREDICTABLE. */
9774 inst
.instruction
&= A_COND_MASK
;
9775 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9776 inst
.instruction
|= one_reg
<< 12;
9783 encode_ldmstm (/*from_push_pop_mnem=*/false);
9786 /* ARMv5TE load-consecutive (argument parse)
9795 constraint (inst
.operands
[0].reg
% 2 != 0,
9796 _("first transfer register must be even"));
9797 constraint (inst
.operands
[1].present
9798 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9799 _("can only transfer two consecutive registers"));
9800 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9801 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9803 if (!inst
.operands
[1].present
)
9804 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9806 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9807 register and the first register written; we have to diagnose
9808 overlap between the base and the second register written here. */
9810 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9811 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9812 as_warn (_("base register written back, and overlaps "
9813 "second transfer register"));
9815 if (!(inst
.instruction
& V4_STR_BIT
))
9817 /* For an index-register load, the index register must not overlap the
9818 destination (even if not write-back). */
9819 if (inst
.operands
[2].immisreg
9820 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9821 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9822 as_warn (_("index register overlaps transfer register"));
9824 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9825 encode_arm_addr_mode_3 (2, /*is_t=*/false);
9831 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9832 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9833 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9834 || inst
.operands
[1].negative
9835 /* This can arise if the programmer has written
9837 or if they have mistakenly used a register name as the last
9840 It is very difficult to distinguish between these two cases
9841 because "rX" might actually be a label. ie the register
9842 name has been occluded by a symbol of the same name. So we
9843 just generate a general 'bad addressing mode' type error
9844 message and leave it up to the programmer to discover the
9845 true cause and fix their mistake. */
9846 || (inst
.operands
[1].reg
== REG_PC
),
9849 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9850 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9851 _("offset must be zero in ARM encoding"));
9853 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9855 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9856 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9857 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9863 constraint (inst
.operands
[0].reg
% 2 != 0,
9864 _("even register required"));
9865 constraint (inst
.operands
[1].present
9866 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9867 _("can only load two consecutive registers"));
9868 /* If op 1 were present and equal to PC, this function wouldn't
9869 have been called in the first place. */
9870 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9872 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9873 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9876 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9877 which is not a multiple of four is UNPREDICTABLE. */
9879 check_ldr_r15_aligned (void)
9881 constraint (!(inst
.operands
[1].immisreg
)
9882 && (inst
.operands
[0].reg
== REG_PC
9883 && inst
.operands
[1].reg
== REG_PC
9884 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9885 _("ldr to register 15 must be 4-byte aligned"));
9891 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9892 if (!inst
.operands
[1].isreg
)
9893 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/false))
9895 encode_arm_addr_mode_2 (1, /*is_t=*/false);
9896 check_ldr_r15_aligned ();
9902 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9904 if (inst
.operands
[1].preind
)
9906 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9907 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9908 _("this instruction requires a post-indexed address"));
9910 inst
.operands
[1].preind
= 0;
9911 inst
.operands
[1].postind
= 1;
9912 inst
.operands
[1].writeback
= 1;
9914 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9915 encode_arm_addr_mode_2 (1, /*is_t=*/true);
9918 /* Halfword and signed-byte load/store operations. */
9923 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9924 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9925 if (!inst
.operands
[1].isreg
)
9926 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/true))
9928 encode_arm_addr_mode_3 (1, /*is_t=*/false);
9934 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9936 if (inst
.operands
[1].preind
)
9938 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9939 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9940 _("this instruction requires a post-indexed address"));
9942 inst
.operands
[1].preind
= 0;
9943 inst
.operands
[1].postind
= 1;
9944 inst
.operands
[1].writeback
= 1;
9946 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9947 encode_arm_addr_mode_3 (1, /*is_t=*/true);
9950 /* Co-processor register load/store.
9951 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9955 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9956 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9957 encode_arm_cp_address (2, true, true, 0);
9963 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9964 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9965 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9966 && !(inst
.instruction
& 0x00400000))
9967 as_tsktsk (_("Rd and Rm should be different in mla"));
9969 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9970 inst
.instruction
|= inst
.operands
[1].reg
;
9971 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9972 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9978 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9979 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9981 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9982 encode_arm_shifter_operand (1);
9985 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9992 top
= (inst
.instruction
& 0x00400000) != 0;
9993 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9994 _(":lower16: not allowed in this instruction"));
9995 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9996 _(":upper16: not allowed in this instruction"));
9997 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9998 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
10000 imm
= inst
.relocs
[0].exp
.X_add_number
;
10001 /* The value is in two pieces: 0:11, 16:19. */
10002 inst
.instruction
|= (imm
& 0x00000fff);
10003 inst
.instruction
|= (imm
& 0x0000f000) << 4;
10008 do_vfp_nsyn_mrs (void)
10010 if (inst
.operands
[0].isvec
)
10012 if (inst
.operands
[1].reg
!= 1)
10013 first_error (_("operand 1 must be FPSCR"));
10014 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
10015 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
10016 do_vfp_nsyn_opcode ("fmstat");
10018 else if (inst
.operands
[1].isvec
)
10019 do_vfp_nsyn_opcode ("fmrx");
10027 do_vfp_nsyn_msr (void)
10029 if (inst
.operands
[0].isvec
)
10030 do_vfp_nsyn_opcode ("fmxr");
10040 unsigned Rt
= inst
.operands
[0].reg
;
10042 if (thumb_mode
&& Rt
== REG_SP
)
10044 inst
.error
= BAD_SP
;
10048 switch (inst
.operands
[1].reg
)
10050 /* MVFR2 is only valid for Armv8-A. */
10052 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10056 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10057 case 1: /* fpscr. */
10058 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10059 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10063 case 14: /* fpcxt_ns. */
10064 case 15: /* fpcxt_s. */
10065 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10066 _("selected processor does not support instruction"));
10069 case 2: /* fpscr_nzcvqc. */
10070 case 12: /* vpr. */
10072 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10073 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10074 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10075 _("selected processor does not support instruction"));
10076 if (inst
.operands
[0].reg
!= 2
10077 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10078 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10085 /* APSR_ sets isvec. All other refs to PC are illegal. */
10086 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
10088 inst
.error
= BAD_PC
;
10092 /* If we get through parsing the register name, we just insert the number
10093 generated into the instruction without further validation. */
10094 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
10095 inst
.instruction
|= (Rt
<< 12);
10101 unsigned Rt
= inst
.operands
[1].reg
;
10104 reject_bad_reg (Rt
);
10105 else if (Rt
== REG_PC
)
10107 inst
.error
= BAD_PC
;
10111 switch (inst
.operands
[0].reg
)
10113 /* MVFR2 is only valid for Armv8-A. */
10115 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10119 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10120 case 1: /* fpcr. */
10121 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10122 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10126 case 14: /* fpcxt_ns. */
10127 case 15: /* fpcxt_s. */
10128 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10129 _("selected processor does not support instruction"));
10132 case 2: /* fpscr_nzcvqc. */
10133 case 12: /* vpr. */
10135 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10136 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10137 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10138 _("selected processor does not support instruction"));
10139 if (inst
.operands
[0].reg
!= 2
10140 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10141 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10148 /* If we get through parsing the register name, we just insert the number
10149 generated into the instruction without further validation. */
10150 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10151 inst
.instruction
|= (Rt
<< 12);
10159 if (do_vfp_nsyn_mrs () == SUCCESS
)
10162 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10163 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10165 if (inst
.operands
[1].isreg
)
10167 br
= inst
.operands
[1].reg
;
10168 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10169 as_bad (_("bad register for mrs"));
10173 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10174 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10176 _("'APSR', 'CPSR' or 'SPSR' expected"));
10177 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10180 inst
.instruction
|= br
;
10183 /* Two possible forms:
10184 "{C|S}PSR_<field>, Rm",
10185 "{C|S}PSR_f, #expression". */
10190 if (do_vfp_nsyn_msr () == SUCCESS
)
10193 inst
.instruction
|= inst
.operands
[0].imm
;
10194 if (inst
.operands
[1].isreg
)
10195 inst
.instruction
|= inst
.operands
[1].reg
;
10198 inst
.instruction
|= INST_IMMEDIATE
;
10199 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10200 inst
.relocs
[0].pc_rel
= 0;
10207 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10209 if (!inst
.operands
[2].present
)
10210 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10211 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10212 inst
.instruction
|= inst
.operands
[1].reg
;
10213 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10215 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10216 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10217 as_tsktsk (_("Rd and Rm should be different in mul"));
10220 /* Long Multiply Parser
10221 UMULL RdLo, RdHi, Rm, Rs
10222 SMULL RdLo, RdHi, Rm, Rs
10223 UMLAL RdLo, RdHi, Rm, Rs
10224 SMLAL RdLo, RdHi, Rm, Rs. */
10229 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10230 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10231 inst
.instruction
|= inst
.operands
[2].reg
;
10232 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10234 /* rdhi and rdlo must be different. */
10235 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10236 as_tsktsk (_("rdhi and rdlo must be different"));
10238 /* rdhi, rdlo and rm must all be different before armv6. */
10239 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10240 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10241 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10242 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10248 if (inst
.operands
[0].present
10249 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10251 /* Architectural NOP hints are CPSR sets with no bits selected. */
10252 inst
.instruction
&= 0xf0000000;
10253 inst
.instruction
|= 0x0320f000;
10254 if (inst
.operands
[0].present
)
10255 inst
.instruction
|= inst
.operands
[0].imm
;
10259 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10260 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10261 Condition defaults to COND_ALWAYS.
10262 Error if Rd, Rn or Rm are R15. */
10267 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10268 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10269 inst
.instruction
|= inst
.operands
[2].reg
;
10270 if (inst
.operands
[3].present
)
10271 encode_arm_shift (3);
10274 /* ARM V6 PKHTB (Argument Parse). */
10279 if (!inst
.operands
[3].present
)
10281 /* If the shift specifier is omitted, turn the instruction
10282 into pkhbt rd, rm, rn. */
10283 inst
.instruction
&= 0xfff00010;
10284 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10285 inst
.instruction
|= inst
.operands
[1].reg
;
10286 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10290 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10291 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10292 inst
.instruction
|= inst
.operands
[2].reg
;
10293 encode_arm_shift (3);
10297 /* ARMv5TE: Preload-Cache
10298 MP Extensions: Preload for write
10302 Syntactically, like LDR with B=1, W=0, L=1. */
10307 constraint (!inst
.operands
[0].isreg
,
10308 _("'[' expected after PLD mnemonic"));
10309 constraint (inst
.operands
[0].postind
,
10310 _("post-indexed expression used in preload instruction"));
10311 constraint (inst
.operands
[0].writeback
,
10312 _("writeback used in preload instruction"));
10313 constraint (!inst
.operands
[0].preind
,
10314 _("unindexed addressing used in preload instruction"));
10315 encode_arm_addr_mode_2 (0, /*is_t=*/false);
10318 /* ARMv7: PLI <addr_mode> */
10322 constraint (!inst
.operands
[0].isreg
,
10323 _("'[' expected after PLI mnemonic"));
10324 constraint (inst
.operands
[0].postind
,
10325 _("post-indexed expression used in preload instruction"));
10326 constraint (inst
.operands
[0].writeback
,
10327 _("writeback used in preload instruction"));
10328 constraint (!inst
.operands
[0].preind
,
10329 _("unindexed addressing used in preload instruction"));
10330 encode_arm_addr_mode_2 (0, /*is_t=*/false);
10331 inst
.instruction
&= ~PRE_INDEX
;
10337 constraint (inst
.operands
[0].writeback
,
10338 _("push/pop do not support {reglist}^"));
10339 inst
.operands
[1] = inst
.operands
[0];
10340 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10341 inst
.operands
[0].isreg
= 1;
10342 inst
.operands
[0].writeback
= 1;
10343 inst
.operands
[0].reg
= REG_SP
;
10344 encode_ldmstm (/*from_push_pop_mnem=*/true);
10347 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10348 word at the specified address and the following word
10350 Unconditionally executed.
10351 Error if Rn is R15. */
10356 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10357 if (inst
.operands
[0].writeback
)
10358 inst
.instruction
|= WRITE_BACK
;
10361 /* ARM V6 ssat (argument parse). */
10366 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10367 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10368 inst
.instruction
|= inst
.operands
[2].reg
;
10370 if (inst
.operands
[3].present
)
10371 encode_arm_shift (3);
10374 /* ARM V6 usat (argument parse). */
10379 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10380 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10381 inst
.instruction
|= inst
.operands
[2].reg
;
10383 if (inst
.operands
[3].present
)
10384 encode_arm_shift (3);
10387 /* ARM V6 ssat16 (argument parse). */
10392 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10393 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10394 inst
.instruction
|= inst
.operands
[2].reg
;
10400 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10401 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10402 inst
.instruction
|= inst
.operands
[2].reg
;
10405 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10406 preserving the other bits.
10408 setend <endian_specifier>, where <endian_specifier> is either
10414 if (warn_on_deprecated
10415 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10416 as_tsktsk (_("setend use is deprecated for ARMv8"));
10418 if (inst
.operands
[0].imm
)
10419 inst
.instruction
|= 0x200;
10425 unsigned int Rm
= (inst
.operands
[1].present
10426 ? inst
.operands
[1].reg
10427 : inst
.operands
[0].reg
);
10429 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10430 inst
.instruction
|= Rm
;
10431 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10433 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10434 inst
.instruction
|= SHIFT_BY_REG
;
10435 /* PR 12854: Error on extraneous shifts. */
10436 constraint (inst
.operands
[2].shifted
,
10437 _("extraneous shift as part of operand to shift insn"));
10440 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10446 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10447 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10449 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10450 inst
.relocs
[0].pc_rel
= 0;
10456 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10457 inst
.relocs
[0].pc_rel
= 0;
10463 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10464 inst
.relocs
[0].pc_rel
= 0;
10470 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10471 _("selected processor does not support SETPAN instruction"));
10473 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10479 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10480 _("selected processor does not support SETPAN instruction"));
10482 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10485 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10486 SMLAxy{cond} Rd,Rm,Rs,Rn
10487 SMLAWy{cond} Rd,Rm,Rs,Rn
10488 Error if any register is R15. */
10493 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10494 inst
.instruction
|= inst
.operands
[1].reg
;
10495 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10496 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10499 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10500 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10501 Error if any register is R15.
10502 Warning if Rdlo == Rdhi. */
10507 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10508 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10509 inst
.instruction
|= inst
.operands
[2].reg
;
10510 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10512 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10513 as_tsktsk (_("rdhi and rdlo must be different"));
10516 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10517 SMULxy{cond} Rd,Rm,Rs
10518 Error if any register is R15. */
10523 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10524 inst
.instruction
|= inst
.operands
[1].reg
;
10525 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10528 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10529 the same for both ARM and Thumb-2. */
10536 if (inst
.operands
[0].present
)
10538 reg
= inst
.operands
[0].reg
;
10539 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10544 inst
.instruction
|= reg
<< 16;
10545 inst
.instruction
|= inst
.operands
[1].imm
;
10546 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10547 inst
.instruction
|= WRITE_BACK
;
10550 /* ARM V6 strex (argument parse). */
10555 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10556 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10557 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10558 || inst
.operands
[2].negative
10559 /* See comment in do_ldrex(). */
10560 || (inst
.operands
[2].reg
== REG_PC
),
10563 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10564 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10566 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10567 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10568 _("offset must be zero in ARM encoding"));
10570 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10571 inst
.instruction
|= inst
.operands
[1].reg
;
10572 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10573 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10577 do_t_strexbh (void)
10579 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10580 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10581 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10582 || inst
.operands
[2].negative
,
10585 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10586 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10594 constraint (inst
.operands
[1].reg
% 2 != 0,
10595 _("even register required"));
10596 constraint (inst
.operands
[2].present
10597 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10598 _("can only store two consecutive registers"));
10599 /* If op 2 were present and equal to PC, this function wouldn't
10600 have been called in the first place. */
10601 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10603 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10604 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10605 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10608 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10609 inst
.instruction
|= inst
.operands
[1].reg
;
10610 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10617 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10618 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10626 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10627 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10632 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10633 extends it to 32-bits, and adds the result to a value in another
10634 register. You can specify a rotation by 0, 8, 16, or 24 bits
10635 before extracting the 16-bit value.
10636 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10637 Condition defaults to COND_ALWAYS.
10638 Error if any register uses R15. */
10643 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10644 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10645 inst
.instruction
|= inst
.operands
[2].reg
;
10646 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10651 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10652 Condition defaults to COND_ALWAYS.
10653 Error if any register uses R15. */
10658 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10659 inst
.instruction
|= inst
.operands
[1].reg
;
10660 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10663 /* VFP instructions. In a logical order: SP variant first, monad
10664 before dyad, arithmetic then move then load/store. */
10667 do_vfp_sp_monadic (void)
10669 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10670 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10673 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10674 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10678 do_vfp_sp_dyadic (void)
10680 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10681 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10682 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10686 do_vfp_sp_compare_z (void)
10688 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10692 do_vfp_dp_sp_cvt (void)
10694 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10695 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10699 do_vfp_sp_dp_cvt (void)
10701 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10702 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10706 do_vfp_reg_from_sp (void)
10708 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10709 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10712 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10713 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10717 do_vfp_reg2_from_sp2 (void)
10719 constraint (inst
.operands
[2].imm
!= 2,
10720 _("only two consecutive VFP SP registers allowed here"));
10721 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10722 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10723 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10727 do_vfp_sp_from_reg (void)
10729 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10730 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10733 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10734 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10738 do_vfp_sp2_from_reg2 (void)
10740 constraint (inst
.operands
[0].imm
!= 2,
10741 _("only two consecutive VFP SP registers allowed here"));
10742 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10743 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10744 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10748 do_vfp_sp_ldst (void)
10750 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10751 encode_arm_cp_address (1, false, true, 0);
10755 do_vfp_dp_ldst (void)
10757 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10758 encode_arm_cp_address (1, false, true, 0);
10763 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10765 if (inst
.operands
[0].writeback
)
10766 inst
.instruction
|= WRITE_BACK
;
10768 constraint (ldstm_type
!= VFP_LDSTMIA
,
10769 _("this addressing mode requires base-register writeback"));
10770 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10771 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10772 inst
.instruction
|= inst
.operands
[1].imm
;
10776 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10780 if (inst
.operands
[0].writeback
)
10781 inst
.instruction
|= WRITE_BACK
;
10783 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10784 _("this addressing mode requires base-register writeback"));
10786 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10787 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10789 count
= inst
.operands
[1].imm
<< 1;
10790 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10793 inst
.instruction
|= count
;
10797 do_vfp_sp_ldstmia (void)
10799 vfp_sp_ldstm (VFP_LDSTMIA
);
10803 do_vfp_sp_ldstmdb (void)
10805 vfp_sp_ldstm (VFP_LDSTMDB
);
10809 do_vfp_dp_ldstmia (void)
10811 vfp_dp_ldstm (VFP_LDSTMIA
);
10815 do_vfp_dp_ldstmdb (void)
10817 vfp_dp_ldstm (VFP_LDSTMDB
);
10821 do_vfp_xp_ldstmia (void)
10823 vfp_dp_ldstm (VFP_LDSTMIAX
);
10827 do_vfp_xp_ldstmdb (void)
10829 vfp_dp_ldstm (VFP_LDSTMDBX
);
10833 do_vfp_dp_rd_rm (void)
10835 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10836 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10839 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10840 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10844 do_vfp_dp_rn_rd (void)
10846 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10847 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10851 do_vfp_dp_rd_rn (void)
10853 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10854 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10858 do_vfp_dp_rd_rn_rm (void)
10860 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10861 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10864 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10865 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10866 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10870 do_vfp_dp_rd (void)
10872 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10876 do_vfp_dp_rm_rd_rn (void)
10878 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10879 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10882 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10883 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10884 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10887 /* VFPv3 instructions. */
10889 do_vfp_sp_const (void)
10891 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10892 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10893 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10897 do_vfp_dp_const (void)
10899 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10900 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10901 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10905 vfp_conv (int srcsize
)
10907 int immbits
= srcsize
- inst
.operands
[1].imm
;
10909 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10911 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10912 i.e. immbits must be in range 0 - 16. */
10913 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10916 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10918 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10919 i.e. immbits must be in range 0 - 31. */
10920 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10924 inst
.instruction
|= (immbits
& 1) << 5;
10925 inst
.instruction
|= (immbits
>> 1);
10929 do_vfp_sp_conv_16 (void)
10931 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10936 do_vfp_dp_conv_16 (void)
10938 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10943 do_vfp_sp_conv_32 (void)
10945 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10950 do_vfp_dp_conv_32 (void)
10952 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10956 /* FPA instructions. Also in a logical order. */
10961 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10962 inst
.instruction
|= inst
.operands
[1].reg
;
10966 do_fpa_ldmstm (void)
10968 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10969 switch (inst
.operands
[1].imm
)
10971 case 1: inst
.instruction
|= CP_T_X
; break;
10972 case 2: inst
.instruction
|= CP_T_Y
; break;
10973 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10978 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10980 /* The instruction specified "ea" or "fd", so we can only accept
10981 [Rn]{!}. The instruction does not really support stacking or
10982 unstacking, so we have to emulate these by setting appropriate
10983 bits and offsets. */
10984 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10985 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10986 _("this instruction does not support indexing"));
10988 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10989 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10991 if (!(inst
.instruction
& INDEX_UP
))
10992 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10994 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10996 inst
.operands
[2].preind
= 0;
10997 inst
.operands
[2].postind
= 1;
11001 encode_arm_cp_address (2, true, true, 0);
11004 /* iWMMXt instructions: strictly in alphabetical order. */
11007 do_iwmmxt_tandorc (void)
11009 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
11013 do_iwmmxt_textrc (void)
11015 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11016 inst
.instruction
|= inst
.operands
[1].imm
;
11020 do_iwmmxt_textrm (void)
11022 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11023 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11024 inst
.instruction
|= inst
.operands
[2].imm
;
11028 do_iwmmxt_tinsr (void)
11030 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11031 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11032 inst
.instruction
|= inst
.operands
[2].imm
;
11036 do_iwmmxt_tmia (void)
11038 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11039 inst
.instruction
|= inst
.operands
[1].reg
;
11040 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11044 do_iwmmxt_waligni (void)
11046 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11047 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11048 inst
.instruction
|= inst
.operands
[2].reg
;
11049 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
11053 do_iwmmxt_wmerge (void)
11055 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11056 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11057 inst
.instruction
|= inst
.operands
[2].reg
;
11058 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
11062 do_iwmmxt_wmov (void)
11064 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
11065 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11066 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11067 inst
.instruction
|= inst
.operands
[1].reg
;
11071 do_iwmmxt_wldstbh (void)
11074 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11076 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
11078 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
11079 encode_arm_cp_address (1, true, false, reloc
);
11083 do_iwmmxt_wldstw (void)
11085 /* RIWR_RIWC clears .isreg for a control register. */
11086 if (!inst
.operands
[0].isreg
)
11088 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
11089 inst
.instruction
|= 0xf0000000;
11092 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11093 encode_arm_cp_address (1, true, true, 0);
11097 do_iwmmxt_wldstd (void)
11099 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11100 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
11101 && inst
.operands
[1].immisreg
)
11103 inst
.instruction
&= ~0x1a000ff;
11104 inst
.instruction
|= (0xfU
<< 28);
11105 if (inst
.operands
[1].preind
)
11106 inst
.instruction
|= PRE_INDEX
;
11107 if (!inst
.operands
[1].negative
)
11108 inst
.instruction
|= INDEX_UP
;
11109 if (inst
.operands
[1].writeback
)
11110 inst
.instruction
|= WRITE_BACK
;
11111 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11112 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11113 inst
.instruction
|= inst
.operands
[1].imm
;
11116 encode_arm_cp_address (1, true, false, 0);
11120 do_iwmmxt_wshufh (void)
11122 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11123 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11124 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11125 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11129 do_iwmmxt_wzero (void)
11131 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11132 inst
.instruction
|= inst
.operands
[0].reg
;
11133 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11134 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11138 do_iwmmxt_wrwrwr_or_imm5 (void)
11140 if (inst
.operands
[2].isreg
)
11143 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11144 _("immediate operand requires iWMMXt2"));
11146 if (inst
.operands
[2].imm
== 0)
11148 switch ((inst
.instruction
>> 20) & 0xf)
11154 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11155 inst
.operands
[2].imm
= 16;
11156 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11162 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11163 inst
.operands
[2].imm
= 32;
11164 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11171 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11173 wrn
= (inst
.instruction
>> 16) & 0xf;
11174 inst
.instruction
&= 0xff0fff0f;
11175 inst
.instruction
|= wrn
;
11176 /* Bail out here; the instruction is now assembled. */
11181 /* Map 32 -> 0, etc. */
11182 inst
.operands
[2].imm
&= 0x1f;
11183 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11187 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11188 operations first, then control, shift, and load/store. */
11190 /* Insns like "foo X,Y,Z". */
11193 do_mav_triple (void)
11195 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11196 inst
.instruction
|= inst
.operands
[1].reg
;
11197 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11200 /* Insns like "foo W,X,Y,Z".
11201 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11206 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11207 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11208 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11209 inst
.instruction
|= inst
.operands
[3].reg
;
11212 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11214 do_mav_dspsc (void)
11216 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11219 /* Maverick shift immediate instructions.
11220 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11221 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11224 do_mav_shift (void)
11226 int imm
= inst
.operands
[2].imm
;
11228 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11229 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11231 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11232 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11233 Bit 4 should be 0. */
11234 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11236 inst
.instruction
|= imm
;
11239 /* XScale instructions. Also sorted arithmetic before move. */
11241 /* Xscale multiply-accumulate (argument parse)
11244 MIAxycc acc0,Rm,Rs. */
11249 inst
.instruction
|= inst
.operands
[1].reg
;
11250 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11253 /* Xscale move-accumulator-register (argument parse)
11255 MARcc acc0,RdLo,RdHi. */
11260 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11261 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11264 /* Xscale move-register-accumulator (argument parse)
11266 MRAcc RdLo,RdHi,acc0. */
11271 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11272 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11273 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11276 /* Encoding functions relevant only to Thumb. */
11278 /* inst.operands[i] is a shifted-register operand; encode
11279 it into inst.instruction in the format used by Thumb32. */
11282 encode_thumb32_shifted_operand (int i
)
11284 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11285 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11287 constraint (inst
.operands
[i
].immisreg
,
11288 _("shift by register not allowed in thumb mode"));
11289 inst
.instruction
|= inst
.operands
[i
].reg
;
11290 if (shift
== SHIFT_RRX
)
11291 inst
.instruction
|= SHIFT_ROR
<< 4;
11294 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11295 _("expression too complex"));
11297 constraint (value
> 32
11298 || (value
== 32 && (shift
== SHIFT_LSL
11299 || shift
== SHIFT_ROR
)),
11300 _("shift expression is too large"));
11304 else if (value
== 32)
11307 inst
.instruction
|= shift
<< 4;
11308 inst
.instruction
|= (value
& 0x1c) << 10;
11309 inst
.instruction
|= (value
& 0x03) << 6;
11314 /* inst.operands[i] was set up by parse_address. Encode it into a
11315 Thumb32 format load or store instruction. Reject forms that cannot
11316 be used with such instructions. If is_t is true, reject forms that
11317 cannot be used with a T instruction; if is_d is true, reject forms
11318 that cannot be used with a D instruction. If it is a store insn,
11319 reject PC in Rn. */
11322 encode_thumb32_addr_mode (int i
, bool is_t
, bool is_d
)
11324 const bool is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11326 constraint (!inst
.operands
[i
].isreg
,
11327 _("Instruction does not support =N addresses"));
11329 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11330 if (inst
.operands
[i
].immisreg
)
11332 constraint (is_pc
, BAD_PC_ADDRESSING
);
11333 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11334 constraint (inst
.operands
[i
].negative
,
11335 _("Thumb does not support negative register indexing"));
11336 constraint (inst
.operands
[i
].postind
,
11337 _("Thumb does not support register post-indexing"));
11338 constraint (inst
.operands
[i
].writeback
,
11339 _("Thumb does not support register indexing with writeback"));
11340 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11341 _("Thumb supports only LSL in shifted register indexing"));
11343 inst
.instruction
|= inst
.operands
[i
].imm
;
11344 if (inst
.operands
[i
].shifted
)
11346 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11347 _("expression too complex"));
11348 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11349 || inst
.relocs
[0].exp
.X_add_number
> 3,
11350 _("shift out of range"));
11351 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11353 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11355 else if (inst
.operands
[i
].preind
)
11357 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11358 constraint (is_t
&& inst
.operands
[i
].writeback
,
11359 _("cannot use writeback with this instruction"));
11360 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11361 BAD_PC_ADDRESSING
);
11365 inst
.instruction
|= 0x01000000;
11366 if (inst
.operands
[i
].writeback
)
11367 inst
.instruction
|= 0x00200000;
11371 inst
.instruction
|= 0x00000c00;
11372 if (inst
.operands
[i
].writeback
)
11373 inst
.instruction
|= 0x00000100;
11375 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11377 else if (inst
.operands
[i
].postind
)
11379 gas_assert (inst
.operands
[i
].writeback
);
11380 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11381 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11384 inst
.instruction
|= 0x00200000;
11386 inst
.instruction
|= 0x00000900;
11387 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11389 else /* unindexed - only for coprocessor */
11390 inst
.error
= _("instruction does not accept unindexed addressing");
11393 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11394 encodings (the latter only in post-V6T2 cores). The index is the
11395 value used in the insns table below. When there is more than one
11396 possible 16-bit encoding for the instruction, this table always
11398 Also contains several pseudo-instructions used during relaxation. */
11399 #define T16_32_TAB \
11400 X(_adc, 4140, eb400000), \
11401 X(_adcs, 4140, eb500000), \
11402 X(_add, 1c00, eb000000), \
11403 X(_adds, 1c00, eb100000), \
11404 X(_addi, 0000, f1000000), \
11405 X(_addis, 0000, f1100000), \
11406 X(_add_pc,000f, f20f0000), \
11407 X(_add_sp,000d, f10d0000), \
11408 X(_adr, 000f, f20f0000), \
11409 X(_and, 4000, ea000000), \
11410 X(_ands, 4000, ea100000), \
11411 X(_asr, 1000, fa40f000), \
11412 X(_asrs, 1000, fa50f000), \
11413 X(_aut, 0000, f3af802d), \
11414 X(_autg, 0000, fb500f00), \
11415 X(_b, e000, f000b000), \
11416 X(_bcond, d000, f0008000), \
11417 X(_bf, 0000, f040e001), \
11418 X(_bfcsel,0000, f000e001), \
11419 X(_bfx, 0000, f060e001), \
11420 X(_bfl, 0000, f000c001), \
11421 X(_bflx, 0000, f070e001), \
11422 X(_bic, 4380, ea200000), \
11423 X(_bics, 4380, ea300000), \
11424 X(_bxaut, 0000, fb500f10), \
11425 X(_cinc, 0000, ea509000), \
11426 X(_cinv, 0000, ea50a000), \
11427 X(_cmn, 42c0, eb100f00), \
11428 X(_cmp, 2800, ebb00f00), \
11429 X(_cneg, 0000, ea50b000), \
11430 X(_cpsie, b660, f3af8400), \
11431 X(_cpsid, b670, f3af8600), \
11432 X(_cpy, 4600, ea4f0000), \
11433 X(_csel, 0000, ea508000), \
11434 X(_cset, 0000, ea5f900f), \
11435 X(_csetm, 0000, ea5fa00f), \
11436 X(_csinc, 0000, ea509000), \
11437 X(_csinv, 0000, ea50a000), \
11438 X(_csneg, 0000, ea50b000), \
11439 X(_dec_sp,80dd, f1ad0d00), \
11440 X(_dls, 0000, f040e001), \
11441 X(_dlstp, 0000, f000e001), \
11442 X(_eor, 4040, ea800000), \
11443 X(_eors, 4040, ea900000), \
11444 X(_inc_sp,00dd, f10d0d00), \
11445 X(_lctp, 0000, f00fe001), \
11446 X(_ldmia, c800, e8900000), \
11447 X(_ldr, 6800, f8500000), \
11448 X(_ldrb, 7800, f8100000), \
11449 X(_ldrh, 8800, f8300000), \
11450 X(_ldrsb, 5600, f9100000), \
11451 X(_ldrsh, 5e00, f9300000), \
11452 X(_ldr_pc,4800, f85f0000), \
11453 X(_ldr_pc2,4800, f85f0000), \
11454 X(_ldr_sp,9800, f85d0000), \
11455 X(_le, 0000, f00fc001), \
11456 X(_letp, 0000, f01fc001), \
11457 X(_lsl, 0000, fa00f000), \
11458 X(_lsls, 0000, fa10f000), \
11459 X(_lsr, 0800, fa20f000), \
11460 X(_lsrs, 0800, fa30f000), \
11461 X(_mov, 2000, ea4f0000), \
11462 X(_movs, 2000, ea5f0000), \
11463 X(_mul, 4340, fb00f000), \
11464 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11465 X(_mvn, 43c0, ea6f0000), \
11466 X(_mvns, 43c0, ea7f0000), \
11467 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11468 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11469 X(_orr, 4300, ea400000), \
11470 X(_orrs, 4300, ea500000), \
11471 X(_pac, 0000, f3af801d), \
11472 X(_pacbti, 0000, f3af800d), \
11473 X(_pacg, 0000, fb60f000), \
11474 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11475 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11476 X(_rev, ba00, fa90f080), \
11477 X(_rev16, ba40, fa90f090), \
11478 X(_revsh, bac0, fa90f0b0), \
11479 X(_ror, 41c0, fa60f000), \
11480 X(_rors, 41c0, fa70f000), \
11481 X(_sbc, 4180, eb600000), \
11482 X(_sbcs, 4180, eb700000), \
11483 X(_stmia, c000, e8800000), \
11484 X(_str, 6000, f8400000), \
11485 X(_strb, 7000, f8000000), \
11486 X(_strh, 8000, f8200000), \
11487 X(_str_sp,9000, f84d0000), \
11488 X(_sub, 1e00, eba00000), \
11489 X(_subs, 1e00, ebb00000), \
11490 X(_subi, 8000, f1a00000), \
11491 X(_subis, 8000, f1b00000), \
11492 X(_sxtb, b240, fa4ff080), \
11493 X(_sxth, b200, fa0ff080), \
11494 X(_tst, 4200, ea100f00), \
11495 X(_uxtb, b2c0, fa5ff080), \
11496 X(_uxth, b280, fa1ff080), \
11497 X(_nop, bf00, f3af8000), \
11498 X(_yield, bf10, f3af8001), \
11499 X(_wfe, bf20, f3af8002), \
11500 X(_wfi, bf30, f3af8003), \
11501 X(_wls, 0000, f040c001), \
11502 X(_wlstp, 0000, f000c001), \
11503 X(_sev, bf40, f3af8004), \
11504 X(_sevl, bf50, f3af8005), \
11505 X(_udf, de00, f7f0a000)
11507 /* To catch errors in encoding functions, the codes are all offset by
11508 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11509 as 16-bit instructions. */
11510 #define X(a,b,c) T_MNEM##a
11511 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11514 #define X(a,b,c) 0x##b
11515 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11516 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11519 #define X(a,b,c) 0x##c
11520 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11521 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11522 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11526 /* Thumb instruction encoders, in alphabetical order. */
11528 /* ADDW or SUBW. */
11531 do_t_add_sub_w (void)
11535 Rd
= inst
.operands
[0].reg
;
11536 Rn
= inst
.operands
[1].reg
;
11538 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11539 is the SP-{plus,minus}-immediate form of the instruction. */
11541 constraint (Rd
== REG_PC
, BAD_PC
);
11543 reject_bad_reg (Rd
);
11545 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11546 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11549 /* Parse an add or subtract instruction. We get here with inst.instruction
11550 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11553 do_t_add_sub (void)
11557 Rd
= inst
.operands
[0].reg
;
11558 Rs
= (inst
.operands
[1].present
11559 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11560 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11563 set_pred_insn_type_last ();
11565 if (unified_syntax
)
11571 flags
= (inst
.instruction
== T_MNEM_adds
11572 || inst
.instruction
== T_MNEM_subs
);
11574 narrow
= !in_pred_block ();
11576 narrow
= in_pred_block ();
11577 if (!inst
.operands
[2].isreg
)
11581 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11582 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11584 add
= (inst
.instruction
== T_MNEM_add
11585 || inst
.instruction
== T_MNEM_adds
);
11587 if (inst
.size_req
!= 4)
11589 /* Attempt to use a narrow opcode, with relaxation if
11591 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11592 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11593 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11594 opcode
= T_MNEM_add_sp
;
11595 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11596 opcode
= T_MNEM_add_pc
;
11597 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11600 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11602 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11606 inst
.instruction
= THUMB_OP16(opcode
);
11607 inst
.instruction
|= (Rd
<< 4) | Rs
;
11608 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11609 || (inst
.relocs
[0].type
11610 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11612 if (inst
.size_req
== 2)
11613 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11615 inst
.relax
= opcode
;
11619 constraint (inst
.size_req
== 2, _("cannot honor width suffix"));
11621 if (inst
.size_req
== 4
11622 || (inst
.size_req
!= 2 && !opcode
))
11624 constraint ((inst
.relocs
[0].type
11625 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11626 && (inst
.relocs
[0].type
11627 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11628 THUMB1_RELOC_ONLY
);
11631 constraint (add
, BAD_PC
);
11632 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11633 _("only SUBS PC, LR, #const allowed"));
11634 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11635 _("expression too complex"));
11636 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11637 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11638 _("immediate value out of range"));
11639 inst
.instruction
= T2_SUBS_PC_LR
11640 | inst
.relocs
[0].exp
.X_add_number
;
11641 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11644 else if (Rs
== REG_PC
)
11646 /* Always use addw/subw. */
11647 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11648 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11652 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11653 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11656 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11658 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11660 inst
.instruction
|= Rd
<< 8;
11661 inst
.instruction
|= Rs
<< 16;
11666 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11667 unsigned int shift
= inst
.operands
[2].shift_kind
;
11669 Rn
= inst
.operands
[2].reg
;
11670 /* See if we can do this with a 16-bit instruction. */
11671 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11673 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11678 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11679 || inst
.instruction
== T_MNEM_add
)
11681 : T_OPCODE_SUB_R3
);
11682 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11686 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11688 /* Thumb-1 cores (except v6-M) require at least one high
11689 register in a narrow non flag setting add. */
11690 if (Rd
> 7 || Rn
> 7
11691 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11692 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11699 inst
.instruction
= T_OPCODE_ADD_HI
;
11700 inst
.instruction
|= (Rd
& 8) << 4;
11701 inst
.instruction
|= (Rd
& 7);
11702 inst
.instruction
|= Rn
<< 3;
11708 constraint (Rd
== REG_PC
, BAD_PC
);
11709 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11710 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11711 constraint (Rs
== REG_PC
, BAD_PC
);
11712 reject_bad_reg (Rn
);
11714 /* If we get here, it can't be done in 16 bits. */
11715 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11716 _("shift must be constant"));
11717 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11718 inst
.instruction
|= Rd
<< 8;
11719 inst
.instruction
|= Rs
<< 16;
11720 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11721 _("shift value over 3 not allowed in thumb mode"));
11722 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11723 _("only LSL shift allowed in thumb mode"));
11724 encode_thumb32_shifted_operand (2);
11729 constraint (inst
.instruction
== T_MNEM_adds
11730 || inst
.instruction
== T_MNEM_subs
,
11733 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11735 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11736 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11739 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11740 ? 0x0000 : 0x8000);
11741 inst
.instruction
|= (Rd
<< 4) | Rs
;
11742 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11746 Rn
= inst
.operands
[2].reg
;
11747 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11749 /* We now have Rd, Rs, and Rn set to registers. */
11750 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11752 /* Can't do this for SUB. */
11753 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11754 inst
.instruction
= T_OPCODE_ADD_HI
;
11755 inst
.instruction
|= (Rd
& 8) << 4;
11756 inst
.instruction
|= (Rd
& 7);
11758 inst
.instruction
|= Rn
<< 3;
11760 inst
.instruction
|= Rs
<< 3;
11762 constraint (1, _("dest must overlap one source register"));
11766 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11767 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11768 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11778 Rd
= inst
.operands
[0].reg
;
11779 reject_bad_reg (Rd
);
11781 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11783 /* Defer to section relaxation. */
11784 inst
.relax
= inst
.instruction
;
11785 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11786 inst
.instruction
|= Rd
<< 4;
11788 else if (unified_syntax
&& inst
.size_req
!= 2)
11790 /* Generate a 32-bit opcode. */
11791 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11792 inst
.instruction
|= Rd
<< 8;
11793 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11794 inst
.relocs
[0].pc_rel
= 1;
11798 /* Generate a 16-bit opcode. */
11799 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11800 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11801 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11802 inst
.relocs
[0].pc_rel
= 1;
11803 inst
.instruction
|= Rd
<< 4;
11806 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11807 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11808 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11809 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11810 inst
.relocs
[0].exp
.X_add_number
+= 1;
11813 /* Arithmetic instructions for which there is just one 16-bit
11814 instruction encoding, and it allows only two low registers.
11815 For maximal compatibility with ARM syntax, we allow three register
11816 operands even when Thumb-32 instructions are not available, as long
11817 as the first two are identical. For instance, both "sbc r0,r1" and
11818 "sbc r0,r0,r1" are allowed. */
11824 Rd
= inst
.operands
[0].reg
;
11825 Rs
= (inst
.operands
[1].present
11826 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11827 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11828 Rn
= inst
.operands
[2].reg
;
11830 reject_bad_reg (Rd
);
11831 reject_bad_reg (Rs
);
11832 if (inst
.operands
[2].isreg
)
11833 reject_bad_reg (Rn
);
11835 if (unified_syntax
)
11837 if (!inst
.operands
[2].isreg
)
11839 /* For an immediate, we always generate a 32-bit opcode;
11840 section relaxation will shrink it later if possible. */
11841 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11842 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11843 inst
.instruction
|= Rd
<< 8;
11844 inst
.instruction
|= Rs
<< 16;
11845 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11851 /* See if we can do this with a 16-bit instruction. */
11852 if (THUMB_SETS_FLAGS (inst
.instruction
))
11853 narrow
= !in_pred_block ();
11855 narrow
= in_pred_block ();
11857 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11859 if (inst
.operands
[2].shifted
)
11861 if (inst
.size_req
== 4)
11867 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11868 inst
.instruction
|= Rd
;
11869 inst
.instruction
|= Rn
<< 3;
11873 /* If we get here, it can't be done in 16 bits. */
11874 constraint (inst
.operands
[2].shifted
11875 && inst
.operands
[2].immisreg
,
11876 _("shift must be constant"));
11877 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11878 inst
.instruction
|= Rd
<< 8;
11879 inst
.instruction
|= Rs
<< 16;
11880 encode_thumb32_shifted_operand (2);
11885 /* On its face this is a lie - the instruction does set the
11886 flags. However, the only supported mnemonic in this mode
11887 says it doesn't. */
11888 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11890 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11891 _("unshifted register required"));
11892 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11893 constraint (Rd
!= Rs
,
11894 _("dest and source1 must be the same register"));
11896 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11897 inst
.instruction
|= Rd
;
11898 inst
.instruction
|= Rn
<< 3;
11902 /* Similarly, but for instructions where the arithmetic operation is
11903 commutative, so we can allow either of them to be different from
11904 the destination operand in a 16-bit instruction. For instance, all
11905 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11912 Rd
= inst
.operands
[0].reg
;
11913 Rs
= (inst
.operands
[1].present
11914 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11915 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11916 Rn
= inst
.operands
[2].reg
;
11918 reject_bad_reg (Rd
);
11919 reject_bad_reg (Rs
);
11920 if (inst
.operands
[2].isreg
)
11921 reject_bad_reg (Rn
);
11923 if (unified_syntax
)
11925 if (!inst
.operands
[2].isreg
)
11927 /* For an immediate, we always generate a 32-bit opcode;
11928 section relaxation will shrink it later if possible. */
11929 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11930 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11931 inst
.instruction
|= Rd
<< 8;
11932 inst
.instruction
|= Rs
<< 16;
11933 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11939 /* See if we can do this with a 16-bit instruction. */
11940 if (THUMB_SETS_FLAGS (inst
.instruction
))
11941 narrow
= !in_pred_block ();
11943 narrow
= in_pred_block ();
11945 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11947 if (inst
.operands
[2].shifted
)
11949 if (inst
.size_req
== 4)
11956 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11957 inst
.instruction
|= Rd
;
11958 inst
.instruction
|= Rn
<< 3;
11963 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11964 inst
.instruction
|= Rd
;
11965 inst
.instruction
|= Rs
<< 3;
11970 /* If we get here, it can't be done in 16 bits. */
11971 constraint (inst
.operands
[2].shifted
11972 && inst
.operands
[2].immisreg
,
11973 _("shift must be constant"));
11974 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11975 inst
.instruction
|= Rd
<< 8;
11976 inst
.instruction
|= Rs
<< 16;
11977 encode_thumb32_shifted_operand (2);
11982 /* On its face this is a lie - the instruction does set the
11983 flags. However, the only supported mnemonic in this mode
11984 says it doesn't. */
11985 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11987 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11988 _("unshifted register required"));
11989 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11991 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11992 inst
.instruction
|= Rd
;
11995 inst
.instruction
|= Rn
<< 3;
11997 inst
.instruction
|= Rs
<< 3;
11999 constraint (1, _("dest must overlap one source register"));
12007 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
12008 constraint (msb
> 32, _("bit-field extends past end of register"));
12009 /* The instruction encoding stores the LSB and MSB,
12010 not the LSB and width. */
12011 Rd
= inst
.operands
[0].reg
;
12012 reject_bad_reg (Rd
);
12013 inst
.instruction
|= Rd
<< 8;
12014 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
12015 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
12016 inst
.instruction
|= msb
- 1;
12025 Rd
= inst
.operands
[0].reg
;
12026 reject_bad_reg (Rd
);
12028 /* #0 in second position is alternative syntax for bfc, which is
12029 the same instruction but with REG_PC in the Rm field. */
12030 if (!inst
.operands
[1].isreg
)
12034 Rn
= inst
.operands
[1].reg
;
12035 reject_bad_reg (Rn
);
12038 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
12039 constraint (msb
> 32, _("bit-field extends past end of register"));
12040 /* The instruction encoding stores the LSB and MSB,
12041 not the LSB and width. */
12042 inst
.instruction
|= Rd
<< 8;
12043 inst
.instruction
|= Rn
<< 16;
12044 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12045 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12046 inst
.instruction
|= msb
- 1;
12054 Rd
= inst
.operands
[0].reg
;
12055 Rn
= inst
.operands
[1].reg
;
12057 reject_bad_reg (Rd
);
12058 reject_bad_reg (Rn
);
12060 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
12061 _("bit-field extends past end of register"));
12062 inst
.instruction
|= Rd
<< 8;
12063 inst
.instruction
|= Rn
<< 16;
12064 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12065 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12066 inst
.instruction
|= inst
.operands
[3].imm
- 1;
12069 /* ARM V5 Thumb BLX (argument parse)
12070 BLX <target_addr> which is BLX(1)
12071 BLX <Rm> which is BLX(2)
12072 Unfortunately, there are two different opcodes for this mnemonic.
12073 So, the insns[].value is not used, and the code here zaps values
12074 into inst.instruction.
12076 ??? How to take advantage of the additional two bits of displacement
12077 available in Thumb32 mode? Need new relocation? */
12082 set_pred_insn_type_last ();
12084 if (inst
.operands
[0].isreg
)
12086 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
12087 /* We have a register, so this is BLX(2). */
12088 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12092 /* No register. This must be BLX(1). */
12093 inst
.instruction
= 0xf000e800;
12094 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
12103 bfd_reloc_code_real_type reloc
;
12106 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
12108 if (in_pred_block ())
12110 /* Conditional branches inside IT blocks are encoded as unconditional
12112 cond
= COND_ALWAYS
;
12117 if (cond
!= COND_ALWAYS
)
12118 opcode
= T_MNEM_bcond
;
12120 opcode
= inst
.instruction
;
12123 && (inst
.size_req
== 4
12124 || (inst
.size_req
!= 2
12125 && (inst
.operands
[0].hasreloc
12126 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12128 inst
.instruction
= THUMB_OP32(opcode
);
12129 if (cond
== COND_ALWAYS
)
12130 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12133 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12134 _("selected architecture does not support "
12135 "wide conditional branch instruction"));
12137 gas_assert (cond
!= 0xF);
12138 inst
.instruction
|= cond
<< 22;
12139 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12144 inst
.instruction
= THUMB_OP16(opcode
);
12145 if (cond
== COND_ALWAYS
)
12146 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12149 inst
.instruction
|= cond
<< 8;
12150 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12152 /* Allow section relaxation. */
12153 if (unified_syntax
&& inst
.size_req
!= 2)
12154 inst
.relax
= opcode
;
12156 inst
.relocs
[0].type
= reloc
;
12157 inst
.relocs
[0].pc_rel
= 1;
12160 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12161 between the two is the maximum immediate allowed - which is passed in
12164 do_t_bkpt_hlt1 (int range
)
12166 constraint (inst
.cond
!= COND_ALWAYS
,
12167 _("instruction is always unconditional"));
12168 if (inst
.operands
[0].present
)
12170 constraint (inst
.operands
[0].imm
> range
,
12171 _("immediate value out of range"));
12172 inst
.instruction
|= inst
.operands
[0].imm
;
12175 set_pred_insn_type (NEUTRAL_IT_INSN
);
12181 do_t_bkpt_hlt1 (63);
12187 do_t_bkpt_hlt1 (255);
12191 do_t_branch23 (void)
12193 set_pred_insn_type_last ();
12194 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12196 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12197 this file. We used to simply ignore the PLT reloc type here --
12198 the branch encoding is now needed to deal with TLSCALL relocs.
12199 So if we see a PLT reloc now, put it back to how it used to be to
12200 keep the preexisting behaviour. */
12201 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12202 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12204 #if defined(OBJ_COFF)
12205 /* If the destination of the branch is a defined symbol which does not have
12206 the THUMB_FUNC attribute, then we must be calling a function which has
12207 the (interfacearm) attribute. We look for the Thumb entry point to that
12208 function and change the branch to refer to that function instead. */
12209 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12210 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12211 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12212 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12213 inst
.relocs
[0].exp
.X_add_symbol
12214 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12221 set_pred_insn_type_last ();
12222 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12223 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12224 should cause the alignment to be checked once it is known. This is
12225 because BX PC only works if the instruction is word aligned. */
12233 set_pred_insn_type_last ();
12234 Rm
= inst
.operands
[0].reg
;
12235 reject_bad_reg (Rm
);
12236 inst
.instruction
|= Rm
<< 16;
12245 Rd
= inst
.operands
[0].reg
;
12246 Rm
= inst
.operands
[1].reg
;
12248 reject_bad_reg (Rd
);
12249 reject_bad_reg (Rm
);
12251 inst
.instruction
|= Rd
<< 8;
12252 inst
.instruction
|= Rm
<< 16;
12253 inst
.instruction
|= Rm
;
12256 /* For the Armv8.1-M conditional instructions. */
12260 unsigned Rd
, Rn
, Rm
;
12263 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12265 Rd
= inst
.operands
[0].reg
;
12266 switch (inst
.instruction
)
12272 Rn
= inst
.operands
[1].reg
;
12273 Rm
= inst
.operands
[2].reg
;
12274 cond
= inst
.operands
[3].imm
;
12275 constraint (Rn
== REG_SP
, BAD_SP
);
12276 constraint (Rm
== REG_SP
, BAD_SP
);
12282 Rn
= inst
.operands
[1].reg
;
12283 cond
= inst
.operands
[2].imm
;
12284 /* Invert the last bit to invert the cond. */
12285 cond
= TOGGLE_BIT (cond
, 0);
12286 constraint (Rn
== REG_SP
, BAD_SP
);
12292 cond
= inst
.operands
[1].imm
;
12293 /* Invert the last bit to invert the cond. */
12294 cond
= TOGGLE_BIT (cond
, 0);
12302 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12303 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12304 inst
.instruction
|= Rd
<< 8;
12305 inst
.instruction
|= Rn
<< 16;
12306 inst
.instruction
|= Rm
;
12307 inst
.instruction
|= cond
<< 4;
12313 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12319 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12320 inst
.instruction
|= inst
.operands
[0].imm
;
12326 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12328 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12329 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12331 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12332 inst
.instruction
= 0xf3af8000;
12333 inst
.instruction
|= imod
<< 9;
12334 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12335 if (inst
.operands
[1].present
)
12336 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12340 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12341 && (inst
.operands
[0].imm
& 4),
12342 _("selected processor does not support 'A' form "
12343 "of this instruction"));
12344 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12345 _("Thumb does not support the 2-argument "
12346 "form of this instruction"));
12347 inst
.instruction
|= inst
.operands
[0].imm
;
12351 /* THUMB CPY instruction (argument parse). */
12356 if (inst
.size_req
== 4)
12358 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12359 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12360 inst
.instruction
|= inst
.operands
[1].reg
;
12364 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12365 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12366 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12373 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12374 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12375 inst
.instruction
|= inst
.operands
[0].reg
;
12376 inst
.relocs
[0].pc_rel
= 1;
12377 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12383 inst
.instruction
|= inst
.operands
[0].imm
;
12389 unsigned Rd
, Rn
, Rm
;
12391 Rd
= inst
.operands
[0].reg
;
12392 Rn
= (inst
.operands
[1].present
12393 ? inst
.operands
[1].reg
: Rd
);
12394 Rm
= inst
.operands
[2].reg
;
12396 reject_bad_reg (Rd
);
12397 reject_bad_reg (Rn
);
12398 reject_bad_reg (Rm
);
12400 inst
.instruction
|= Rd
<< 8;
12401 inst
.instruction
|= Rn
<< 16;
12402 inst
.instruction
|= Rm
;
12408 if (unified_syntax
&& inst
.size_req
== 4)
12409 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12411 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12417 unsigned int cond
= inst
.operands
[0].imm
;
12419 set_pred_insn_type (IT_INSN
);
12420 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12421 now_pred
.cc
= cond
;
12422 now_pred
.warn_deprecated
= false;
12423 now_pred
.type
= SCALAR_PRED
;
12425 /* If the condition is a negative condition, invert the mask. */
12426 if ((cond
& 0x1) == 0x0)
12428 unsigned int mask
= inst
.instruction
& 0x000f;
12430 if ((mask
& 0x7) == 0)
12432 /* No conversion needed. */
12433 now_pred
.block_length
= 1;
12435 else if ((mask
& 0x3) == 0)
12438 now_pred
.block_length
= 2;
12440 else if ((mask
& 0x1) == 0)
12443 now_pred
.block_length
= 3;
12448 now_pred
.block_length
= 4;
12451 inst
.instruction
&= 0xfff0;
12452 inst
.instruction
|= mask
;
12455 inst
.instruction
|= cond
<< 4;
12458 /* Helper function used for both push/pop and ldm/stm. */
12460 encode_thumb2_multi (bool do_io
, int base
, unsigned mask
,
12465 gas_assert (base
!= -1 || !do_io
);
12466 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12467 store
= do_io
&& !load
;
12469 if (mask
& (1 << 13))
12470 inst
.error
= _("SP not allowed in register list");
12472 if (do_io
&& (mask
& (1 << base
)) != 0
12474 inst
.error
= _("having the base register in the register list when "
12475 "using write back is UNPREDICTABLE");
12479 if (mask
& (1 << 15))
12481 if (mask
& (1 << 14))
12482 inst
.error
= _("LR and PC should not both be in register list");
12484 set_pred_insn_type_last ();
12489 if (mask
& (1 << 15))
12490 inst
.error
= _("PC not allowed in register list");
12493 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12495 /* Single register transfers implemented as str/ldr. */
12498 if (inst
.instruction
& (1 << 23))
12499 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12501 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12505 if (inst
.instruction
& (1 << 23))
12506 inst
.instruction
= 0x00800000; /* ia -> [base] */
12508 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12511 inst
.instruction
|= 0xf8400000;
12513 inst
.instruction
|= 0x00100000;
12515 mask
= ffs (mask
) - 1;
12518 else if (writeback
)
12519 inst
.instruction
|= WRITE_BACK
;
12521 inst
.instruction
|= mask
;
12523 inst
.instruction
|= base
<< 16;
12529 /* This really doesn't seem worth it. */
12530 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12531 _("expression too complex"));
12532 constraint (inst
.operands
[1].writeback
,
12533 _("Thumb load/store multiple does not support {reglist}^"));
12535 if (unified_syntax
)
12541 /* See if we can use a 16-bit instruction. */
12542 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12543 && inst
.size_req
!= 4
12544 && !(inst
.operands
[1].imm
& ~0xff))
12546 mask
= 1 << inst
.operands
[0].reg
;
12548 if (inst
.operands
[0].reg
<= 7)
12550 if (inst
.instruction
== T_MNEM_stmia
12551 ? inst
.operands
[0].writeback
12552 : (inst
.operands
[0].writeback
12553 == !(inst
.operands
[1].imm
& mask
)))
12555 if (inst
.instruction
== T_MNEM_stmia
12556 && (inst
.operands
[1].imm
& mask
)
12557 && (inst
.operands
[1].imm
& (mask
- 1)))
12558 as_warn (_("value stored for r%d is UNKNOWN"),
12559 inst
.operands
[0].reg
);
12561 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12562 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12563 inst
.instruction
|= inst
.operands
[1].imm
;
12566 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12568 /* This means 1 register in reg list one of 3 situations:
12569 1. Instruction is stmia, but without writeback.
12570 2. lmdia without writeback, but with Rn not in
12572 3. ldmia with writeback, but with Rn in reglist.
12573 Case 3 is UNPREDICTABLE behaviour, so we handle
12574 case 1 and 2 which can be converted into a 16-bit
12575 str or ldr. The SP cases are handled below. */
12576 unsigned long opcode
;
12577 /* First, record an error for Case 3. */
12578 if (inst
.operands
[1].imm
& mask
12579 && inst
.operands
[0].writeback
)
12581 _("having the base register in the register list when "
12582 "using write back is UNPREDICTABLE");
12584 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12586 inst
.instruction
= THUMB_OP16 (opcode
);
12587 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12588 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12592 else if (inst
.operands
[0] .reg
== REG_SP
)
12594 if (inst
.operands
[0].writeback
)
12597 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12598 ? T_MNEM_push
: T_MNEM_pop
);
12599 inst
.instruction
|= inst
.operands
[1].imm
;
12602 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12605 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12606 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12607 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12615 if (inst
.instruction
< 0xffff)
12616 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12618 encode_thumb2_multi (true /* do_io */, inst
.operands
[0].reg
,
12619 inst
.operands
[1].imm
,
12620 inst
.operands
[0].writeback
);
12625 constraint (inst
.operands
[0].reg
> 7
12626 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12627 constraint (inst
.instruction
!= T_MNEM_ldmia
12628 && inst
.instruction
!= T_MNEM_stmia
,
12629 _("Thumb-2 instruction only valid in unified syntax"));
12630 if (inst
.instruction
== T_MNEM_stmia
)
12632 if (!inst
.operands
[0].writeback
)
12633 as_warn (_("this instruction will write back the base register"));
12634 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12635 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12636 as_warn (_("value stored for r%d is UNKNOWN"),
12637 inst
.operands
[0].reg
);
12641 if (!inst
.operands
[0].writeback
12642 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12643 as_warn (_("this instruction will write back the base register"));
12644 else if (inst
.operands
[0].writeback
12645 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12646 as_warn (_("this instruction will not write back the base register"));
12649 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12650 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12651 inst
.instruction
|= inst
.operands
[1].imm
;
12658 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12659 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12660 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12661 || inst
.operands
[1].negative
,
12664 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12666 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12667 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12668 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12674 if (!inst
.operands
[1].present
)
12676 constraint (inst
.operands
[0].reg
== REG_LR
,
12677 _("r14 not allowed as first register "
12678 "when second register is omitted"));
12679 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12681 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12684 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12685 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12686 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12692 unsigned long opcode
;
12695 if (inst
.operands
[0].isreg
12696 && !inst
.operands
[0].preind
12697 && inst
.operands
[0].reg
== REG_PC
)
12698 set_pred_insn_type_last ();
12700 opcode
= inst
.instruction
;
12701 if (unified_syntax
)
12703 if (!inst
.operands
[1].isreg
)
12705 if (opcode
<= 0xffff)
12706 inst
.instruction
= THUMB_OP32 (opcode
);
12707 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/false))
12710 if (inst
.operands
[1].isreg
12711 && !inst
.operands
[1].writeback
12712 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12713 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12714 && opcode
<= 0xffff
12715 && inst
.size_req
!= 4)
12717 /* Insn may have a 16-bit form. */
12718 Rn
= inst
.operands
[1].reg
;
12719 if (inst
.operands
[1].immisreg
)
12721 inst
.instruction
= THUMB_OP16 (opcode
);
12723 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12725 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12726 reject_bad_reg (inst
.operands
[1].imm
);
12728 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12729 && opcode
!= T_MNEM_ldrsb
)
12730 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12731 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12738 if (inst
.relocs
[0].pc_rel
)
12739 opcode
= T_MNEM_ldr_pc2
;
12741 opcode
= T_MNEM_ldr_pc
;
12745 if (opcode
== T_MNEM_ldr
)
12746 opcode
= T_MNEM_ldr_sp
;
12748 opcode
= T_MNEM_str_sp
;
12750 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12754 inst
.instruction
= inst
.operands
[0].reg
;
12755 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12757 inst
.instruction
|= THUMB_OP16 (opcode
);
12758 if (inst
.size_req
== 2)
12759 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12761 inst
.relax
= opcode
;
12765 /* Definitely a 32-bit variant. */
12767 /* Warning for Erratum 752419. */
12768 if (opcode
== T_MNEM_ldr
12769 && inst
.operands
[0].reg
== REG_SP
12770 && inst
.operands
[1].writeback
== 1
12771 && !inst
.operands
[1].immisreg
)
12773 if (no_cpu_selected ()
12774 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12775 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12776 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12777 as_warn (_("This instruction may be unpredictable "
12778 "if executed on M-profile cores "
12779 "with interrupts enabled."));
12782 /* Do some validations regarding addressing modes. */
12783 if (inst
.operands
[1].immisreg
)
12784 reject_bad_reg (inst
.operands
[1].imm
);
12786 constraint (inst
.operands
[1].writeback
== 1
12787 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12790 inst
.instruction
= THUMB_OP32 (opcode
);
12791 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12792 encode_thumb32_addr_mode (1, /*is_t=*/false, /*is_d=*/false);
12793 check_ldr_r15_aligned ();
12797 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12799 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12801 /* Only [Rn,Rm] is acceptable. */
12802 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12803 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12804 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12805 || inst
.operands
[1].negative
,
12806 _("Thumb does not support this addressing mode"));
12807 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12811 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12812 if (!inst
.operands
[1].isreg
)
12813 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/false))
12816 constraint (!inst
.operands
[1].preind
12817 || inst
.operands
[1].shifted
12818 || inst
.operands
[1].writeback
,
12819 _("Thumb does not support this addressing mode"));
12820 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12822 constraint (inst
.instruction
& 0x0600,
12823 _("byte or halfword not valid for base register"));
12824 constraint (inst
.operands
[1].reg
== REG_PC
12825 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12826 _("r15 based store not allowed"));
12827 constraint (inst
.operands
[1].immisreg
,
12828 _("invalid base register for register offset"));
12830 if (inst
.operands
[1].reg
== REG_PC
)
12831 inst
.instruction
= T_OPCODE_LDR_PC
;
12832 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12833 inst
.instruction
= T_OPCODE_LDR_SP
;
12835 inst
.instruction
= T_OPCODE_STR_SP
;
12837 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12838 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12842 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12843 if (!inst
.operands
[1].immisreg
)
12845 /* Immediate offset. */
12846 inst
.instruction
|= inst
.operands
[0].reg
;
12847 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12848 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12852 /* Register offset. */
12853 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12854 constraint (inst
.operands
[1].negative
,
12855 _("Thumb does not support this addressing mode"));
12858 switch (inst
.instruction
)
12860 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12861 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12862 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12863 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12864 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12865 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12866 case 0x5600 /* ldrsb */:
12867 case 0x5e00 /* ldrsh */: break;
12871 inst
.instruction
|= inst
.operands
[0].reg
;
12872 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12873 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12879 if (!inst
.operands
[1].present
)
12881 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12882 constraint (inst
.operands
[0].reg
== REG_LR
,
12883 _("r14 not allowed here"));
12884 constraint (inst
.operands
[0].reg
== REG_R12
,
12885 _("r12 not allowed here"));
12888 if (inst
.operands
[2].writeback
12889 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12890 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12891 as_warn (_("base register written back, and overlaps "
12892 "one of transfer registers"));
12894 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12895 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12896 encode_thumb32_addr_mode (2, /*is_t=*/false, /*is_d=*/true);
12902 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12903 encode_thumb32_addr_mode (1, /*is_t=*/true, /*is_d=*/false);
12909 unsigned Rd
, Rn
, Rm
, Ra
;
12911 Rd
= inst
.operands
[0].reg
;
12912 Rn
= inst
.operands
[1].reg
;
12913 Rm
= inst
.operands
[2].reg
;
12914 Ra
= inst
.operands
[3].reg
;
12916 reject_bad_reg (Rd
);
12917 reject_bad_reg (Rn
);
12918 reject_bad_reg (Rm
);
12919 reject_bad_reg (Ra
);
12921 inst
.instruction
|= Rd
<< 8;
12922 inst
.instruction
|= Rn
<< 16;
12923 inst
.instruction
|= Rm
;
12924 inst
.instruction
|= Ra
<< 12;
12930 unsigned RdLo
, RdHi
, Rn
, Rm
;
12932 RdLo
= inst
.operands
[0].reg
;
12933 RdHi
= inst
.operands
[1].reg
;
12934 Rn
= inst
.operands
[2].reg
;
12935 Rm
= inst
.operands
[3].reg
;
12937 reject_bad_reg (RdLo
);
12938 reject_bad_reg (RdHi
);
12939 reject_bad_reg (Rn
);
12940 reject_bad_reg (Rm
);
12942 inst
.instruction
|= RdLo
<< 12;
12943 inst
.instruction
|= RdHi
<< 8;
12944 inst
.instruction
|= Rn
<< 16;
12945 inst
.instruction
|= Rm
;
12949 do_t_mov_cmp (void)
12953 Rn
= inst
.operands
[0].reg
;
12954 Rm
= inst
.operands
[1].reg
;
12957 set_pred_insn_type_last ();
12959 if (unified_syntax
)
12961 int r0off
= (inst
.instruction
== T_MNEM_mov
12962 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12963 unsigned long opcode
;
12967 low_regs
= (Rn
<= 7 && Rm
<= 7);
12968 opcode
= inst
.instruction
;
12969 if (in_pred_block ())
12970 narrow
= opcode
!= T_MNEM_movs
;
12972 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12973 if (inst
.size_req
== 4
12974 || inst
.operands
[1].shifted
)
12977 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12978 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12979 && !inst
.operands
[1].shifted
12983 inst
.instruction
= T2_SUBS_PC_LR
;
12987 if (opcode
== T_MNEM_cmp
)
12989 constraint (Rn
== REG_PC
, BAD_PC
);
12992 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12994 warn_deprecated_sp (Rm
);
12995 /* R15 was documented as a valid choice for Rm in ARMv6,
12996 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12997 tools reject R15, so we do too. */
12998 constraint (Rm
== REG_PC
, BAD_PC
);
13001 reject_bad_reg (Rm
);
13003 else if (opcode
== T_MNEM_mov
13004 || opcode
== T_MNEM_movs
)
13006 if (inst
.operands
[1].isreg
)
13008 if (opcode
== T_MNEM_movs
)
13010 reject_bad_reg (Rn
);
13011 reject_bad_reg (Rm
);
13015 /* This is mov.n. */
13016 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
13017 && (Rm
== REG_SP
|| Rm
== REG_PC
))
13019 as_tsktsk (_("Use of r%u as a source register is "
13020 "deprecated when r%u is the destination "
13021 "register."), Rm
, Rn
);
13026 /* This is mov.w. */
13027 constraint (Rn
== REG_PC
, BAD_PC
);
13028 constraint (Rm
== REG_PC
, BAD_PC
);
13029 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13030 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
13034 reject_bad_reg (Rn
);
13037 if (!inst
.operands
[1].isreg
)
13039 /* Immediate operand. */
13040 if (!in_pred_block () && opcode
== T_MNEM_mov
)
13042 if (low_regs
&& narrow
)
13044 inst
.instruction
= THUMB_OP16 (opcode
);
13045 inst
.instruction
|= Rn
<< 8;
13046 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
13047 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
13049 if (inst
.size_req
== 2)
13050 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13052 inst
.relax
= opcode
;
13057 constraint ((inst
.relocs
[0].type
13058 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
13059 && (inst
.relocs
[0].type
13060 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
13061 THUMB1_RELOC_ONLY
);
13063 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13064 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13065 inst
.instruction
|= Rn
<< r0off
;
13066 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13069 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
13070 && (inst
.instruction
== T_MNEM_mov
13071 || inst
.instruction
== T_MNEM_movs
))
13073 /* Register shifts are encoded as separate shift instructions. */
13074 bool flags
= (inst
.instruction
== T_MNEM_movs
);
13076 if (in_pred_block ())
13081 if (inst
.size_req
== 4)
13084 if (!low_regs
|| inst
.operands
[1].imm
> 7)
13090 switch (inst
.operands
[1].shift_kind
)
13093 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
13096 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
13099 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
13102 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
13108 inst
.instruction
= opcode
;
13111 inst
.instruction
|= Rn
;
13112 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13117 inst
.instruction
|= CONDS_BIT
;
13119 inst
.instruction
|= Rn
<< 8;
13120 inst
.instruction
|= Rm
<< 16;
13121 inst
.instruction
|= inst
.operands
[1].imm
;
13126 /* Some mov with immediate shift have narrow variants.
13127 Register shifts are handled above. */
13128 if (low_regs
&& inst
.operands
[1].shifted
13129 && (inst
.instruction
== T_MNEM_mov
13130 || inst
.instruction
== T_MNEM_movs
))
13132 if (in_pred_block ())
13133 narrow
= (inst
.instruction
== T_MNEM_mov
);
13135 narrow
= (inst
.instruction
== T_MNEM_movs
);
13140 switch (inst
.operands
[1].shift_kind
)
13142 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13143 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13144 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13145 default: narrow
= false; break;
13151 inst
.instruction
|= Rn
;
13152 inst
.instruction
|= Rm
<< 3;
13153 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13157 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13158 inst
.instruction
|= Rn
<< r0off
;
13159 encode_thumb32_shifted_operand (1);
13163 switch (inst
.instruction
)
13166 /* In v4t or v5t a move of two lowregs produces unpredictable
13167 results. Don't allow this. */
13170 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13171 "MOV Rd, Rs with two low registers is not "
13172 "permitted on this architecture");
13173 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13177 inst
.instruction
= T_OPCODE_MOV_HR
;
13178 inst
.instruction
|= (Rn
& 0x8) << 4;
13179 inst
.instruction
|= (Rn
& 0x7);
13180 inst
.instruction
|= Rm
<< 3;
13184 /* We know we have low registers at this point.
13185 Generate LSLS Rd, Rs, #0. */
13186 inst
.instruction
= T_OPCODE_LSL_I
;
13187 inst
.instruction
|= Rn
;
13188 inst
.instruction
|= Rm
<< 3;
13194 inst
.instruction
= T_OPCODE_CMP_LR
;
13195 inst
.instruction
|= Rn
;
13196 inst
.instruction
|= Rm
<< 3;
13200 inst
.instruction
= T_OPCODE_CMP_HR
;
13201 inst
.instruction
|= (Rn
& 0x8) << 4;
13202 inst
.instruction
|= (Rn
& 0x7);
13203 inst
.instruction
|= Rm
<< 3;
13210 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13212 /* PR 10443: Do not silently ignore shifted operands. */
13213 constraint (inst
.operands
[1].shifted
,
13214 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13216 if (inst
.operands
[1].isreg
)
13218 if (Rn
< 8 && Rm
< 8)
13220 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13221 since a MOV instruction produces unpredictable results. */
13222 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13223 inst
.instruction
= T_OPCODE_ADD_I3
;
13225 inst
.instruction
= T_OPCODE_CMP_LR
;
13227 inst
.instruction
|= Rn
;
13228 inst
.instruction
|= Rm
<< 3;
13232 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13233 inst
.instruction
= T_OPCODE_MOV_HR
;
13235 inst
.instruction
= T_OPCODE_CMP_HR
;
13241 constraint (Rn
> 7,
13242 _("only lo regs allowed with immediate"));
13243 inst
.instruction
|= Rn
<< 8;
13244 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13255 top
= (inst
.instruction
& 0x00800000) != 0;
13256 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13258 constraint (top
, _(":lower16: not allowed in this instruction"));
13259 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13261 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13263 constraint (!top
, _(":upper16: not allowed in this instruction"));
13264 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13267 Rd
= inst
.operands
[0].reg
;
13268 reject_bad_reg (Rd
);
13270 inst
.instruction
|= Rd
<< 8;
13271 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13273 imm
= inst
.relocs
[0].exp
.X_add_number
;
13274 inst
.instruction
|= (imm
& 0xf000) << 4;
13275 inst
.instruction
|= (imm
& 0x0800) << 15;
13276 inst
.instruction
|= (imm
& 0x0700) << 4;
13277 inst
.instruction
|= (imm
& 0x00ff);
13282 do_t_mvn_tst (void)
13286 Rn
= inst
.operands
[0].reg
;
13287 Rm
= inst
.operands
[1].reg
;
13289 if (inst
.instruction
== T_MNEM_cmp
13290 || inst
.instruction
== T_MNEM_cmn
)
13291 constraint (Rn
== REG_PC
, BAD_PC
);
13293 reject_bad_reg (Rn
);
13294 reject_bad_reg (Rm
);
13296 if (unified_syntax
)
13298 int r0off
= (inst
.instruction
== T_MNEM_mvn
13299 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13302 if (inst
.size_req
== 4
13303 || inst
.instruction
> 0xffff
13304 || inst
.operands
[1].shifted
13305 || Rn
> 7 || Rm
> 7)
13307 else if (inst
.instruction
== T_MNEM_cmn
13308 || inst
.instruction
== T_MNEM_tst
)
13310 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13311 narrow
= !in_pred_block ();
13313 narrow
= in_pred_block ();
13315 if (!inst
.operands
[1].isreg
)
13317 /* For an immediate, we always generate a 32-bit opcode;
13318 section relaxation will shrink it later if possible. */
13319 if (inst
.instruction
< 0xffff)
13320 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13321 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13322 inst
.instruction
|= Rn
<< r0off
;
13323 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13327 /* See if we can do this with a 16-bit instruction. */
13330 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13331 inst
.instruction
|= Rn
;
13332 inst
.instruction
|= Rm
<< 3;
13336 constraint (inst
.operands
[1].shifted
13337 && inst
.operands
[1].immisreg
,
13338 _("shift must be constant"));
13339 if (inst
.instruction
< 0xffff)
13340 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13341 inst
.instruction
|= Rn
<< r0off
;
13342 encode_thumb32_shifted_operand (1);
13348 constraint (inst
.instruction
> 0xffff
13349 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13350 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13351 _("unshifted register required"));
13352 constraint (Rn
> 7 || Rm
> 7,
13355 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13356 inst
.instruction
|= Rn
;
13357 inst
.instruction
|= Rm
<< 3;
13366 if (do_vfp_nsyn_mrs () == SUCCESS
)
13369 Rd
= inst
.operands
[0].reg
;
13370 reject_bad_reg (Rd
);
13371 inst
.instruction
|= Rd
<< 8;
13373 if (inst
.operands
[1].isreg
)
13375 unsigned br
= inst
.operands
[1].reg
;
13376 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13377 as_bad (_("bad register for mrs"));
13379 inst
.instruction
|= br
& (0xf << 16);
13380 inst
.instruction
|= (br
& 0x300) >> 4;
13381 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13385 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13387 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13389 /* PR gas/12698: The constraint is only applied for m_profile.
13390 If the user has specified -march=all, we want to ignore it as
13391 we are building for any CPU type, including non-m variants. */
13393 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13394 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13395 "not support requested special purpose register"));
13398 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13400 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13401 _("'APSR', 'CPSR' or 'SPSR' expected"));
13403 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13404 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13405 inst
.instruction
|= 0xf0000;
13415 if (do_vfp_nsyn_msr () == SUCCESS
)
13418 constraint (!inst
.operands
[1].isreg
,
13419 _("Thumb encoding does not support an immediate here"));
13421 if (inst
.operands
[0].isreg
)
13422 flags
= (int)(inst
.operands
[0].reg
);
13424 flags
= inst
.operands
[0].imm
;
13426 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13428 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13430 /* PR gas/12698: The constraint is only applied for m_profile.
13431 If the user has specified -march=all, we want to ignore it as
13432 we are building for any CPU type, including non-m variants. */
13434 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13435 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13436 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13437 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13438 && bits
!= PSR_f
)) && m_profile
,
13439 _("selected processor does not support requested special "
13440 "purpose register"));
13443 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13444 "requested special purpose register"));
13446 Rn
= inst
.operands
[1].reg
;
13447 reject_bad_reg (Rn
);
13449 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13450 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13451 inst
.instruction
|= (flags
& 0x300) >> 4;
13452 inst
.instruction
|= (flags
& 0xff);
13453 inst
.instruction
|= Rn
<< 16;
13460 unsigned Rd
, Rn
, Rm
;
13462 if (!inst
.operands
[2].present
)
13463 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13465 Rd
= inst
.operands
[0].reg
;
13466 Rn
= inst
.operands
[1].reg
;
13467 Rm
= inst
.operands
[2].reg
;
13469 if (unified_syntax
)
13471 if (inst
.size_req
== 4
13477 else if (inst
.instruction
== T_MNEM_muls
)
13478 narrow
= !in_pred_block ();
13480 narrow
= in_pred_block ();
13484 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13485 constraint (Rn
> 7 || Rm
> 7,
13492 /* 16-bit MULS/Conditional MUL. */
13493 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13494 inst
.instruction
|= Rd
;
13497 inst
.instruction
|= Rm
<< 3;
13499 inst
.instruction
|= Rn
<< 3;
13501 constraint (1, _("dest must overlap one source register"));
13505 constraint (inst
.instruction
!= T_MNEM_mul
,
13506 _("Thumb-2 MUL must not set flags"));
13508 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13509 inst
.instruction
|= Rd
<< 8;
13510 inst
.instruction
|= Rn
<< 16;
13511 inst
.instruction
|= Rm
<< 0;
13513 reject_bad_reg (Rd
);
13514 reject_bad_reg (Rn
);
13515 reject_bad_reg (Rm
);
13522 unsigned RdLo
, RdHi
, Rn
, Rm
;
13524 RdLo
= inst
.operands
[0].reg
;
13525 RdHi
= inst
.operands
[1].reg
;
13526 Rn
= inst
.operands
[2].reg
;
13527 Rm
= inst
.operands
[3].reg
;
13529 reject_bad_reg (RdLo
);
13530 reject_bad_reg (RdHi
);
13531 reject_bad_reg (Rn
);
13532 reject_bad_reg (Rm
);
13534 inst
.instruction
|= RdLo
<< 12;
13535 inst
.instruction
|= RdHi
<< 8;
13536 inst
.instruction
|= Rn
<< 16;
13537 inst
.instruction
|= Rm
;
13540 as_tsktsk (_("rdhi and rdlo must be different"));
13546 set_pred_insn_type (NEUTRAL_IT_INSN
);
13548 if (unified_syntax
)
13550 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13552 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13553 inst
.instruction
|= inst
.operands
[0].imm
;
13557 /* PR9722: Check for Thumb2 availability before
13558 generating a thumb2 nop instruction. */
13559 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13561 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13562 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13565 inst
.instruction
= 0x46c0;
13570 constraint (inst
.operands
[0].present
,
13571 _("Thumb does not support NOP with hints"));
13572 inst
.instruction
= 0x46c0;
13579 if (unified_syntax
)
13583 if (THUMB_SETS_FLAGS (inst
.instruction
))
13584 narrow
= !in_pred_block ();
13586 narrow
= in_pred_block ();
13587 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13589 if (inst
.size_req
== 4)
13594 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13595 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13596 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13600 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13601 inst
.instruction
|= inst
.operands
[0].reg
;
13602 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13607 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13609 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13611 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13612 inst
.instruction
|= inst
.operands
[0].reg
;
13613 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13622 Rd
= inst
.operands
[0].reg
;
13623 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13625 reject_bad_reg (Rd
);
13626 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13627 reject_bad_reg (Rn
);
13629 inst
.instruction
|= Rd
<< 8;
13630 inst
.instruction
|= Rn
<< 16;
13632 if (!inst
.operands
[2].isreg
)
13634 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13635 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13641 Rm
= inst
.operands
[2].reg
;
13642 reject_bad_reg (Rm
);
13644 constraint (inst
.operands
[2].shifted
13645 && inst
.operands
[2].immisreg
,
13646 _("shift must be constant"));
13647 encode_thumb32_shifted_operand (2);
13654 unsigned Rd
, Rn
, Rm
;
13656 Rd
= inst
.operands
[0].reg
;
13657 Rn
= inst
.operands
[1].reg
;
13658 Rm
= inst
.operands
[2].reg
;
13660 reject_bad_reg (Rd
);
13661 reject_bad_reg (Rn
);
13662 reject_bad_reg (Rm
);
13664 inst
.instruction
|= Rd
<< 8;
13665 inst
.instruction
|= Rn
<< 16;
13666 inst
.instruction
|= Rm
;
13667 if (inst
.operands
[3].present
)
13669 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13670 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13671 _("expression too complex"));
13672 inst
.instruction
|= (val
& 0x1c) << 10;
13673 inst
.instruction
|= (val
& 0x03) << 6;
13680 if (!inst
.operands
[3].present
)
13684 inst
.instruction
&= ~0x00000020;
13686 /* PR 10168. Swap the Rm and Rn registers. */
13687 Rtmp
= inst
.operands
[1].reg
;
13688 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13689 inst
.operands
[2].reg
= Rtmp
;
13697 if (inst
.operands
[0].immisreg
)
13698 reject_bad_reg (inst
.operands
[0].imm
);
13700 encode_thumb32_addr_mode (0, /*is_t=*/false, /*is_d=*/false);
13704 do_t_push_pop (void)
13708 constraint (inst
.operands
[0].writeback
,
13709 _("push/pop do not support {reglist}^"));
13710 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13711 _("expression too complex"));
13713 mask
= inst
.operands
[0].imm
;
13714 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13715 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13716 else if (inst
.size_req
!= 4
13717 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13718 ? REG_LR
: REG_PC
)))
13720 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13721 inst
.instruction
|= THUMB_PP_PC_LR
;
13722 inst
.instruction
|= mask
& 0xff;
13724 else if (unified_syntax
)
13726 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13727 encode_thumb2_multi (true /* do_io */, 13, mask
, true);
13731 inst
.error
= _("invalid register list to push/pop instruction");
13739 if (unified_syntax
)
13740 encode_thumb2_multi (false /* do_io */, -1, inst
.operands
[0].imm
, false);
13743 inst
.error
= _("invalid register list to push/pop instruction");
13749 do_t_vscclrm (void)
13751 if (inst
.operands
[0].issingle
)
13753 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13754 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13755 inst
.instruction
|= inst
.operands
[0].imm
;
13759 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13760 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13761 inst
.instruction
|= 1 << 8;
13762 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13771 Rd
= inst
.operands
[0].reg
;
13772 Rm
= inst
.operands
[1].reg
;
13774 reject_bad_reg (Rd
);
13775 reject_bad_reg (Rm
);
13777 inst
.instruction
|= Rd
<< 8;
13778 inst
.instruction
|= Rm
<< 16;
13779 inst
.instruction
|= Rm
;
13787 Rd
= inst
.operands
[0].reg
;
13788 Rm
= inst
.operands
[1].reg
;
13790 reject_bad_reg (Rd
);
13791 reject_bad_reg (Rm
);
13793 if (Rd
<= 7 && Rm
<= 7
13794 && inst
.size_req
!= 4)
13796 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13797 inst
.instruction
|= Rd
;
13798 inst
.instruction
|= Rm
<< 3;
13800 else if (unified_syntax
)
13802 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13803 inst
.instruction
|= Rd
<< 8;
13804 inst
.instruction
|= Rm
<< 16;
13805 inst
.instruction
|= Rm
;
13808 inst
.error
= BAD_HIREG
;
13816 Rd
= inst
.operands
[0].reg
;
13817 Rm
= inst
.operands
[1].reg
;
13819 reject_bad_reg (Rd
);
13820 reject_bad_reg (Rm
);
13822 inst
.instruction
|= Rd
<< 8;
13823 inst
.instruction
|= Rm
;
13831 Rd
= inst
.operands
[0].reg
;
13832 Rs
= (inst
.operands
[1].present
13833 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13834 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13836 reject_bad_reg (Rd
);
13837 reject_bad_reg (Rs
);
13838 if (inst
.operands
[2].isreg
)
13839 reject_bad_reg (inst
.operands
[2].reg
);
13841 inst
.instruction
|= Rd
<< 8;
13842 inst
.instruction
|= Rs
<< 16;
13843 if (!inst
.operands
[2].isreg
)
13847 if ((inst
.instruction
& 0x00100000) != 0)
13848 narrow
= !in_pred_block ();
13850 narrow
= in_pred_block ();
13852 if (Rd
> 7 || Rs
> 7)
13855 if (inst
.size_req
== 4 || !unified_syntax
)
13858 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13859 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13862 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13863 relaxation, but it doesn't seem worth the hassle. */
13866 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13867 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13868 inst
.instruction
|= Rs
<< 3;
13869 inst
.instruction
|= Rd
;
13873 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13874 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13878 encode_thumb32_shifted_operand (2);
13884 if (warn_on_deprecated
13885 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13886 as_tsktsk (_("setend use is deprecated for ARMv8"));
13888 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13889 if (inst
.operands
[0].imm
)
13890 inst
.instruction
|= 0x8;
13896 if (!inst
.operands
[1].present
)
13897 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13899 if (unified_syntax
)
13904 switch (inst
.instruction
)
13907 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13909 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13911 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13913 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13917 if (THUMB_SETS_FLAGS (inst
.instruction
))
13918 narrow
= !in_pred_block ();
13920 narrow
= in_pred_block ();
13921 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13923 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13925 if (inst
.operands
[2].isreg
13926 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13927 || inst
.operands
[2].reg
> 7))
13929 if (inst
.size_req
== 4)
13932 reject_bad_reg (inst
.operands
[0].reg
);
13933 reject_bad_reg (inst
.operands
[1].reg
);
13937 if (inst
.operands
[2].isreg
)
13939 reject_bad_reg (inst
.operands
[2].reg
);
13940 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13941 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13942 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13943 inst
.instruction
|= inst
.operands
[2].reg
;
13945 /* PR 12854: Error on extraneous shifts. */
13946 constraint (inst
.operands
[2].shifted
,
13947 _("extraneous shift as part of operand to shift insn"));
13951 inst
.operands
[1].shifted
= 1;
13952 inst
.operands
[1].shift_kind
= shift_kind
;
13953 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13954 ? T_MNEM_movs
: T_MNEM_mov
);
13955 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13956 encode_thumb32_shifted_operand (1);
13957 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13958 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13963 if (inst
.operands
[2].isreg
)
13965 switch (shift_kind
)
13967 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13968 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13969 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13970 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13974 inst
.instruction
|= inst
.operands
[0].reg
;
13975 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13977 /* PR 12854: Error on extraneous shifts. */
13978 constraint (inst
.operands
[2].shifted
,
13979 _("extraneous shift as part of operand to shift insn"));
13983 switch (shift_kind
)
13985 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13986 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13987 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13990 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13991 inst
.instruction
|= inst
.operands
[0].reg
;
13992 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13998 constraint (inst
.operands
[0].reg
> 7
13999 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
14000 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
14002 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
14004 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
14005 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14006 _("source1 and dest must be same register"));
14008 switch (inst
.instruction
)
14010 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
14011 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
14012 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
14013 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
14017 inst
.instruction
|= inst
.operands
[0].reg
;
14018 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
14020 /* PR 12854: Error on extraneous shifts. */
14021 constraint (inst
.operands
[2].shifted
,
14022 _("extraneous shift as part of operand to shift insn"));
14026 switch (inst
.instruction
)
14028 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
14029 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
14030 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14031 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
14034 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14035 inst
.instruction
|= inst
.operands
[0].reg
;
14036 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14044 unsigned Rd
, Rn
, Rm
;
14046 Rd
= inst
.operands
[0].reg
;
14047 Rn
= inst
.operands
[1].reg
;
14048 Rm
= inst
.operands
[2].reg
;
14050 reject_bad_reg (Rd
);
14051 reject_bad_reg (Rn
);
14052 reject_bad_reg (Rm
);
14054 inst
.instruction
|= Rd
<< 8;
14055 inst
.instruction
|= Rn
<< 16;
14056 inst
.instruction
|= Rm
;
14062 unsigned Rd
, Rn
, Rm
;
14064 Rd
= inst
.operands
[0].reg
;
14065 Rm
= inst
.operands
[1].reg
;
14066 Rn
= inst
.operands
[2].reg
;
14068 reject_bad_reg (Rd
);
14069 reject_bad_reg (Rn
);
14070 reject_bad_reg (Rm
);
14072 inst
.instruction
|= Rd
<< 8;
14073 inst
.instruction
|= Rn
<< 16;
14074 inst
.instruction
|= Rm
;
14080 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14081 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
14082 _("SMC is not permitted on this architecture"));
14083 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14084 _("expression too complex"));
14085 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
14087 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14088 inst
.instruction
|= (value
& 0x000f) << 16;
14090 /* PR gas/15623: SMC instructions must be last in an IT block. */
14091 set_pred_insn_type_last ();
14097 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14099 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14100 inst
.instruction
|= (value
& 0x0fff);
14101 inst
.instruction
|= (value
& 0xf000) << 4;
14105 do_t_ssat_usat (int bias
)
14109 Rd
= inst
.operands
[0].reg
;
14110 Rn
= inst
.operands
[2].reg
;
14112 reject_bad_reg (Rd
);
14113 reject_bad_reg (Rn
);
14115 inst
.instruction
|= Rd
<< 8;
14116 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14117 inst
.instruction
|= Rn
<< 16;
14119 if (inst
.operands
[3].present
)
14121 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14123 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14125 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14126 _("expression too complex"));
14128 if (shift_amount
!= 0)
14130 constraint (shift_amount
> 31,
14131 _("shift expression is too large"));
14133 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14134 inst
.instruction
|= 0x00200000; /* sh bit. */
14136 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14137 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14145 do_t_ssat_usat (1);
14153 Rd
= inst
.operands
[0].reg
;
14154 Rn
= inst
.operands
[2].reg
;
14156 reject_bad_reg (Rd
);
14157 reject_bad_reg (Rn
);
14159 inst
.instruction
|= Rd
<< 8;
14160 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14161 inst
.instruction
|= Rn
<< 16;
14167 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14168 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14169 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14170 || inst
.operands
[2].negative
,
14173 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14175 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14176 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14177 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14178 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14184 if (!inst
.operands
[2].present
)
14185 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14187 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14188 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14189 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14192 inst
.instruction
|= inst
.operands
[0].reg
;
14193 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14194 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14195 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14201 unsigned Rd
, Rn
, Rm
;
14203 Rd
= inst
.operands
[0].reg
;
14204 Rn
= inst
.operands
[1].reg
;
14205 Rm
= inst
.operands
[2].reg
;
14207 reject_bad_reg (Rd
);
14208 reject_bad_reg (Rn
);
14209 reject_bad_reg (Rm
);
14211 inst
.instruction
|= Rd
<< 8;
14212 inst
.instruction
|= Rn
<< 16;
14213 inst
.instruction
|= Rm
;
14214 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14222 Rd
= inst
.operands
[0].reg
;
14223 Rm
= inst
.operands
[1].reg
;
14225 reject_bad_reg (Rd
);
14226 reject_bad_reg (Rm
);
14228 if (inst
.instruction
<= 0xffff
14229 && inst
.size_req
!= 4
14230 && Rd
<= 7 && Rm
<= 7
14231 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14233 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14234 inst
.instruction
|= Rd
;
14235 inst
.instruction
|= Rm
<< 3;
14237 else if (unified_syntax
)
14239 if (inst
.instruction
<= 0xffff)
14240 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14241 inst
.instruction
|= Rd
<< 8;
14242 inst
.instruction
|= Rm
;
14243 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14247 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14248 _("Thumb encoding does not support rotation"));
14249 constraint (1, BAD_HIREG
);
14256 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14265 half
= (inst
.instruction
& 0x10) != 0;
14266 set_pred_insn_type_last ();
14267 constraint (inst
.operands
[0].immisreg
,
14268 _("instruction requires register index"));
14270 Rn
= inst
.operands
[0].reg
;
14271 Rm
= inst
.operands
[0].imm
;
14273 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14274 constraint (Rn
== REG_SP
, BAD_SP
);
14275 reject_bad_reg (Rm
);
14277 constraint (!half
&& inst
.operands
[0].shifted
,
14278 _("instruction does not allow shifted index"));
14279 inst
.instruction
|= (Rn
<< 16) | Rm
;
14285 if (!inst
.operands
[0].present
)
14286 inst
.operands
[0].imm
= 0;
14288 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14290 constraint (inst
.size_req
== 2,
14291 _("immediate value out of range"));
14292 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14293 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14294 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14298 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14299 inst
.instruction
|= inst
.operands
[0].imm
;
14302 set_pred_insn_type (NEUTRAL_IT_INSN
);
14309 do_t_ssat_usat (0);
14317 Rd
= inst
.operands
[0].reg
;
14318 Rn
= inst
.operands
[2].reg
;
14320 reject_bad_reg (Rd
);
14321 reject_bad_reg (Rn
);
14323 inst
.instruction
|= Rd
<< 8;
14324 inst
.instruction
|= inst
.operands
[1].imm
;
14325 inst
.instruction
|= Rn
<< 16;
14328 /* Checking the range of the branch offset (VAL) with NBITS bits
14329 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14331 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14333 gas_assert (nbits
> 0 && nbits
<= 32);
14336 int cmp
= (1 << (nbits
- 1));
14337 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14342 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14348 /* For branches in Armv8.1-M Mainline. */
14350 do_t_branch_future (void)
14352 unsigned long insn
= inst
.instruction
;
14354 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14355 if (inst
.operands
[0].hasreloc
== 0)
14357 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, false) == FAIL
)
14358 as_bad (BAD_BRANCH_OFF
);
14360 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14364 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14365 inst
.relocs
[0].pc_rel
= 1;
14371 if (inst
.operands
[1].hasreloc
== 0)
14373 int val
= inst
.operands
[1].imm
;
14374 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, true) == FAIL
)
14375 as_bad (BAD_BRANCH_OFF
);
14377 int immA
= (val
& 0x0001f000) >> 12;
14378 int immB
= (val
& 0x00000ffc) >> 2;
14379 int immC
= (val
& 0x00000002) >> 1;
14380 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14384 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14385 inst
.relocs
[1].pc_rel
= 1;
14390 if (inst
.operands
[1].hasreloc
== 0)
14392 int val
= inst
.operands
[1].imm
;
14393 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, true) == FAIL
)
14394 as_bad (BAD_BRANCH_OFF
);
14396 int immA
= (val
& 0x0007f000) >> 12;
14397 int immB
= (val
& 0x00000ffc) >> 2;
14398 int immC
= (val
& 0x00000002) >> 1;
14399 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14403 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14404 inst
.relocs
[1].pc_rel
= 1;
14408 case T_MNEM_bfcsel
:
14410 if (inst
.operands
[1].hasreloc
== 0)
14412 int val
= inst
.operands
[1].imm
;
14413 int immA
= (val
& 0x00001000) >> 12;
14414 int immB
= (val
& 0x00000ffc) >> 2;
14415 int immC
= (val
& 0x00000002) >> 1;
14416 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14420 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14421 inst
.relocs
[1].pc_rel
= 1;
14425 if (inst
.operands
[2].hasreloc
== 0)
14427 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14428 int val2
= inst
.operands
[2].imm
;
14429 int val0
= inst
.operands
[0].imm
& 0x1f;
14430 int diff
= val2
- val0
;
14432 inst
.instruction
|= 1 << 17; /* T bit. */
14433 else if (diff
!= 2)
14434 as_bad (_("out of range label-relative fixup value"));
14438 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14439 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14440 inst
.relocs
[2].pc_rel
= 1;
14444 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14445 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14450 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14457 /* Helper function for do_t_loloop to handle relocations. */
14459 v8_1_loop_reloc (int is_le
)
14461 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14463 int value
= inst
.relocs
[0].exp
.X_add_number
;
14464 value
= (is_le
) ? -value
: value
;
14466 if (v8_1_branch_value_check (value
, 12, false) == FAIL
)
14467 as_bad (BAD_BRANCH_OFF
);
14471 immh
= (value
& 0x00000ffc) >> 2;
14472 imml
= (value
& 0x00000002) >> 1;
14474 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14478 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14479 inst
.relocs
[0].pc_rel
= 1;
14483 /* For shifts with four operands in MVE. */
14485 do_mve_scalar_shift1 (void)
14487 unsigned int value
= inst
.operands
[2].imm
;
14489 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14490 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14492 /* Setting the bit for saturation. */
14493 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14495 /* Assuming Rm is already checked not to be 11x1. */
14496 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14497 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14498 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14501 /* For shifts in MVE. */
14503 do_mve_scalar_shift (void)
14505 if (!inst
.operands
[2].present
)
14507 inst
.operands
[2] = inst
.operands
[1];
14508 inst
.operands
[1].reg
= 0xf;
14511 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14512 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14514 if (inst
.operands
[2].isreg
)
14516 /* Assuming Rm is already checked not to be 11x1. */
14517 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14518 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14519 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14523 /* Assuming imm is already checked as [1,32]. */
14524 unsigned int value
= inst
.operands
[2].imm
;
14525 inst
.instruction
|= (value
& 0x1c) << 10;
14526 inst
.instruction
|= (value
& 0x03) << 6;
14527 /* Change last 4 bits from 0xd to 0xf. */
14528 inst
.instruction
|= 0x2;
14532 /* MVE instruction encoder helpers. */
14533 #define M_MNEM_vabav 0xee800f01
14534 #define M_MNEM_vmladav 0xeef00e00
14535 #define M_MNEM_vmladava 0xeef00e20
14536 #define M_MNEM_vmladavx 0xeef01e00
14537 #define M_MNEM_vmladavax 0xeef01e20
14538 #define M_MNEM_vmlsdav 0xeef00e01
14539 #define M_MNEM_vmlsdava 0xeef00e21
14540 #define M_MNEM_vmlsdavx 0xeef01e01
14541 #define M_MNEM_vmlsdavax 0xeef01e21
14542 #define M_MNEM_vmullt 0xee011e00
14543 #define M_MNEM_vmullb 0xee010e00
14544 #define M_MNEM_vctp 0xf000e801
14545 #define M_MNEM_vst20 0xfc801e00
14546 #define M_MNEM_vst21 0xfc801e20
14547 #define M_MNEM_vst40 0xfc801e01
14548 #define M_MNEM_vst41 0xfc801e21
14549 #define M_MNEM_vst42 0xfc801e41
14550 #define M_MNEM_vst43 0xfc801e61
14551 #define M_MNEM_vld20 0xfc901e00
14552 #define M_MNEM_vld21 0xfc901e20
14553 #define M_MNEM_vld40 0xfc901e01
14554 #define M_MNEM_vld41 0xfc901e21
14555 #define M_MNEM_vld42 0xfc901e41
14556 #define M_MNEM_vld43 0xfc901e61
14557 #define M_MNEM_vstrb 0xec000e00
14558 #define M_MNEM_vstrh 0xec000e10
14559 #define M_MNEM_vstrw 0xec000e40
14560 #define M_MNEM_vstrd 0xec000e50
14561 #define M_MNEM_vldrb 0xec100e00
14562 #define M_MNEM_vldrh 0xec100e10
14563 #define M_MNEM_vldrw 0xec100e40
14564 #define M_MNEM_vldrd 0xec100e50
14565 #define M_MNEM_vmovlt 0xeea01f40
14566 #define M_MNEM_vmovlb 0xeea00f40
14567 #define M_MNEM_vmovnt 0xfe311e81
14568 #define M_MNEM_vmovnb 0xfe310e81
14569 #define M_MNEM_vadc 0xee300f00
14570 #define M_MNEM_vadci 0xee301f00
14571 #define M_MNEM_vbrsr 0xfe011e60
14572 #define M_MNEM_vaddlv 0xee890f00
14573 #define M_MNEM_vaddlva 0xee890f20
14574 #define M_MNEM_vaddv 0xeef10f00
14575 #define M_MNEM_vaddva 0xeef10f20
14576 #define M_MNEM_vddup 0xee011f6e
14577 #define M_MNEM_vdwdup 0xee011f60
14578 #define M_MNEM_vidup 0xee010f6e
14579 #define M_MNEM_viwdup 0xee010f60
14580 #define M_MNEM_vmaxv 0xeee20f00
14581 #define M_MNEM_vmaxav 0xeee00f00
14582 #define M_MNEM_vminv 0xeee20f80
14583 #define M_MNEM_vminav 0xeee00f80
14584 #define M_MNEM_vmlaldav 0xee800e00
14585 #define M_MNEM_vmlaldava 0xee800e20
14586 #define M_MNEM_vmlaldavx 0xee801e00
14587 #define M_MNEM_vmlaldavax 0xee801e20
14588 #define M_MNEM_vmlsldav 0xee800e01
14589 #define M_MNEM_vmlsldava 0xee800e21
14590 #define M_MNEM_vmlsldavx 0xee801e01
14591 #define M_MNEM_vmlsldavax 0xee801e21
14592 #define M_MNEM_vrmlaldavhx 0xee801f00
14593 #define M_MNEM_vrmlaldavhax 0xee801f20
14594 #define M_MNEM_vrmlsldavh 0xfe800e01
14595 #define M_MNEM_vrmlsldavha 0xfe800e21
14596 #define M_MNEM_vrmlsldavhx 0xfe801e01
14597 #define M_MNEM_vrmlsldavhax 0xfe801e21
14598 #define M_MNEM_vqmovnt 0xee331e01
14599 #define M_MNEM_vqmovnb 0xee330e01
14600 #define M_MNEM_vqmovunt 0xee311e81
14601 #define M_MNEM_vqmovunb 0xee310e81
14602 #define M_MNEM_vshrnt 0xee801fc1
14603 #define M_MNEM_vshrnb 0xee800fc1
14604 #define M_MNEM_vrshrnt 0xfe801fc1
14605 #define M_MNEM_vqshrnt 0xee801f40
14606 #define M_MNEM_vqshrnb 0xee800f40
14607 #define M_MNEM_vqshrunt 0xee801fc0
14608 #define M_MNEM_vqshrunb 0xee800fc0
14609 #define M_MNEM_vrshrnb 0xfe800fc1
14610 #define M_MNEM_vqrshrnt 0xee801f41
14611 #define M_MNEM_vqrshrnb 0xee800f41
14612 #define M_MNEM_vqrshrunt 0xfe801fc0
14613 #define M_MNEM_vqrshrunb 0xfe800fc0
14615 /* Bfloat16 instruction encoder helpers. */
14616 #define B_MNEM_vfmat 0xfc300850
14617 #define B_MNEM_vfmab 0xfc300810
14619 /* Neon instruction encoder helpers. */
14621 /* Encodings for the different types for various Neon opcodes. */
14623 /* An "invalid" code for the following tables. */
14626 struct neon_tab_entry
14629 unsigned float_or_poly
;
14630 unsigned scalar_or_imm
;
14633 /* Map overloaded Neon opcodes to their respective encodings. */
14634 #define NEON_ENC_TAB \
14635 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14636 X(vabdl, 0x0800700, N_INV, N_INV), \
14637 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14638 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14639 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14640 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14641 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14642 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14643 X(vaddl, 0x0800000, N_INV, N_INV), \
14644 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14645 X(vsubl, 0x0800200, N_INV, N_INV), \
14646 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14647 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14648 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14649 /* Register variants of the following two instructions are encoded as
14650 vcge / vcgt with the operands reversed. */ \
14651 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14652 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14653 X(vfma, N_INV, 0x0000c10, N_INV), \
14654 X(vfms, N_INV, 0x0200c10, N_INV), \
14655 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14656 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14657 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14658 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14659 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14660 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14661 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14662 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14663 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14664 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14665 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14666 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14667 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14668 X(vshl, 0x0000400, N_INV, 0x0800510), \
14669 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14670 X(vand, 0x0000110, N_INV, 0x0800030), \
14671 X(vbic, 0x0100110, N_INV, 0x0800030), \
14672 X(veor, 0x1000110, N_INV, N_INV), \
14673 X(vorn, 0x0300110, N_INV, 0x0800010), \
14674 X(vorr, 0x0200110, N_INV, 0x0800010), \
14675 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14676 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14677 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14678 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14679 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14680 X(vst1, 0x0000000, 0x0800000, N_INV), \
14681 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14682 X(vst2, 0x0000100, 0x0800100, N_INV), \
14683 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14684 X(vst3, 0x0000200, 0x0800200, N_INV), \
14685 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14686 X(vst4, 0x0000300, 0x0800300, N_INV), \
14687 X(vmovn, 0x1b20200, N_INV, N_INV), \
14688 X(vtrn, 0x1b20080, N_INV, N_INV), \
14689 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14690 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14691 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14692 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14693 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14694 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14695 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14696 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14697 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14698 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14699 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14700 X(vseleq, 0xe000a00, N_INV, N_INV), \
14701 X(vselvs, 0xe100a00, N_INV, N_INV), \
14702 X(vselge, 0xe200a00, N_INV, N_INV), \
14703 X(vselgt, 0xe300a00, N_INV, N_INV), \
14704 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14705 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14706 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14707 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14708 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14709 X(aes, 0x3b00300, N_INV, N_INV), \
14710 X(sha3op, 0x2000c00, N_INV, N_INV), \
14711 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14712 X(sha2op, 0x3ba0380, N_INV, N_INV)
14716 #define X(OPC,I,F,S) N_MNEM_##OPC
14721 static const struct neon_tab_entry neon_enc_tab
[] =
14723 #define X(OPC,I,F,S) { (I), (F), (S) }
14728 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14729 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14730 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14731 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14732 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14733 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14734 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14735 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14736 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14737 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14738 #define NEON_ENC_SINGLE_(X) \
14739 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14740 #define NEON_ENC_DOUBLE_(X) \
14741 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14742 #define NEON_ENC_FPV8_(X) \
14743 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14745 #define NEON_ENCODE(type, inst) \
14748 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14749 inst.is_neon = 1; \
14753 #define check_neon_suffixes \
14756 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14758 as_bad (_("invalid neon suffix for non neon instruction")); \
14764 /* Define shapes for instruction operands. The following mnemonic characters
14765 are used in this table:
14767 F - VFP S<n> register
14768 D - Neon D<n> register
14769 Q - Neon Q<n> register
14773 L - D<n> register list
14775 This table is used to generate various data:
14776 - enumerations of the form NS_DDR to be used as arguments to
14778 - a table classifying shapes into single, double, quad, mixed.
14779 - a table used to drive neon_select_shape. */
14781 #define NEON_SHAPE_DEF \
14782 X(4, (R, R, Q, Q), QUAD), \
14783 X(4, (Q, R, R, I), QUAD), \
14784 X(4, (R, R, S, S), QUAD), \
14785 X(4, (S, S, R, R), QUAD), \
14786 X(3, (Q, R, I), QUAD), \
14787 X(3, (I, Q, Q), QUAD), \
14788 X(3, (I, Q, R), QUAD), \
14789 X(3, (R, Q, Q), QUAD), \
14790 X(3, (D, D, D), DOUBLE), \
14791 X(3, (Q, Q, Q), QUAD), \
14792 X(3, (D, D, I), DOUBLE), \
14793 X(3, (Q, Q, I), QUAD), \
14794 X(3, (D, D, S), DOUBLE), \
14795 X(3, (Q, Q, S), QUAD), \
14796 X(3, (Q, Q, R), QUAD), \
14797 X(3, (R, R, Q), QUAD), \
14798 X(2, (R, Q), QUAD), \
14799 X(2, (D, D), DOUBLE), \
14800 X(2, (Q, Q), QUAD), \
14801 X(2, (D, S), DOUBLE), \
14802 X(2, (Q, S), QUAD), \
14803 X(2, (D, R), DOUBLE), \
14804 X(2, (Q, R), QUAD), \
14805 X(2, (D, I), DOUBLE), \
14806 X(2, (Q, I), QUAD), \
14807 X(3, (P, F, I), SINGLE), \
14808 X(3, (P, D, I), DOUBLE), \
14809 X(3, (P, Q, I), QUAD), \
14810 X(4, (P, F, F, I), SINGLE), \
14811 X(4, (P, D, D, I), DOUBLE), \
14812 X(4, (P, Q, Q, I), QUAD), \
14813 X(5, (P, F, F, F, I), SINGLE), \
14814 X(5, (P, D, D, D, I), DOUBLE), \
14815 X(5, (P, Q, Q, Q, I), QUAD), \
14816 X(3, (D, L, D), DOUBLE), \
14817 X(2, (D, Q), MIXED), \
14818 X(2, (Q, D), MIXED), \
14819 X(3, (D, Q, I), MIXED), \
14820 X(3, (Q, D, I), MIXED), \
14821 X(3, (Q, D, D), MIXED), \
14822 X(3, (D, Q, Q), MIXED), \
14823 X(3, (Q, Q, D), MIXED), \
14824 X(3, (Q, D, S), MIXED), \
14825 X(3, (D, Q, S), MIXED), \
14826 X(4, (D, D, D, I), DOUBLE), \
14827 X(4, (Q, Q, Q, I), QUAD), \
14828 X(4, (D, D, S, I), DOUBLE), \
14829 X(4, (Q, Q, S, I), QUAD), \
14830 X(2, (F, F), SINGLE), \
14831 X(3, (F, F, F), SINGLE), \
14832 X(2, (F, I), SINGLE), \
14833 X(2, (F, D), MIXED), \
14834 X(2, (D, F), MIXED), \
14835 X(3, (F, F, I), MIXED), \
14836 X(4, (R, R, F, F), SINGLE), \
14837 X(4, (F, F, R, R), SINGLE), \
14838 X(3, (D, R, R), DOUBLE), \
14839 X(3, (R, R, D), DOUBLE), \
14840 X(2, (S, R), SINGLE), \
14841 X(2, (R, S), SINGLE), \
14842 X(2, (F, R), SINGLE), \
14843 X(2, (R, F), SINGLE), \
14844 /* Used for MVE tail predicated loop instructions. */\
14845 X(2, (R, R), QUAD), \
14846 /* Half float shape supported so far. */\
14847 X (2, (H, D), MIXED), \
14848 X (2, (D, H), MIXED), \
14849 X (2, (H, F), MIXED), \
14850 X (2, (F, H), MIXED), \
14851 X (2, (H, H), HALF), \
14852 X (2, (H, R), HALF), \
14853 X (2, (R, H), HALF), \
14854 X (2, (H, I), HALF), \
14855 X (3, (H, H, H), HALF), \
14856 X (3, (H, F, I), MIXED), \
14857 X (3, (F, H, I), MIXED), \
14858 X (3, (D, H, H), MIXED), \
14859 X (3, (D, H, S), MIXED)
14861 #define S2(A,B) NS_##A##B
14862 #define S3(A,B,C) NS_##A##B##C
14863 #define S4(A,B,C,D) NS_##A##B##C##D
14864 #define S5(A,B,C,D,E) NS_##A##B##C##D##E
14866 #define X(N, L, C) S##N L
14880 enum neon_shape_class
14889 #define X(N, L, C) SC_##C
14891 static enum neon_shape_class neon_shape_class
[] =
14911 /* Register widths of above. */
14912 static unsigned neon_shape_el_size
[] =
14925 struct neon_shape_info
14928 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14931 #define S2(A,B) { SE_##A, SE_##B }
14932 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14933 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14934 #define S5(A,B,C,D,E) { SE_##A, SE_##B, SE_##C, SE_##D, SE_##E }
14936 #define X(N, L, C) { N, S##N L }
14938 static struct neon_shape_info neon_shape_tab
[] =
14949 /* Bit masks used in type checking given instructions.
14950 'N_EQK' means the type must be the same as (or based on in some way) the key
14951 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14952 set, various other bits can be set as well in order to modify the meaning of
14953 the type constraint. */
14955 enum neon_type_mask
14979 N_BF16
= 0x0400000,
14980 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14981 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14982 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14983 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14984 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14985 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14986 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14987 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14988 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14989 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14990 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14992 N_MAX_NONSPECIAL
= N_P64
14995 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14997 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14998 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14999 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
15000 #define N_S_32 (N_S8 | N_S16 | N_S32)
15001 #define N_F_16_32 (N_F16 | N_F32)
15002 #define N_SUF_32 (N_SU_32 | N_F_16_32)
15003 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
15004 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
15005 #define N_F_ALL (N_F16 | N_F32 | N_F64)
15006 #define N_I_MVE (N_I8 | N_I16 | N_I32)
15007 #define N_F_MVE (N_F16 | N_F32)
15008 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15010 /* Pass this as the first type argument to neon_check_type to ignore types
15012 #define N_IGNORE_TYPE (N_KEY | N_EQK)
15014 /* Select a "shape" for the current instruction (describing register types or
15015 sizes) from a list of alternatives. Return NS_NULL if the current instruction
15016 doesn't fit. For non-polymorphic shapes, checking is usually done as a
15017 function of operand parsing, so this function doesn't need to be called.
15018 Shapes should be listed in order of decreasing length. */
15020 static enum neon_shape
15021 neon_select_shape (enum neon_shape shape
, ...)
15024 enum neon_shape first_shape
= shape
;
15026 /* Fix missing optional operands. FIXME: we don't know at this point how
15027 many arguments we should have, so this makes the assumption that we have
15028 > 1. This is true of all current Neon opcodes, I think, but may not be
15029 true in the future. */
15030 if (!inst
.operands
[1].present
)
15031 inst
.operands
[1] = inst
.operands
[0];
15033 va_start (ap
, shape
);
15035 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
15040 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
15042 if (!inst
.operands
[j
].present
)
15048 switch (neon_shape_tab
[shape
].el
[j
])
15050 /* If a .f16, .16, .u16, .s16 type specifier is given over
15051 a VFP single precision register operand, it's essentially
15052 means only half of the register is used.
15054 If the type specifier is given after the mnemonics, the
15055 information is stored in inst.vectype. If the type specifier
15056 is given after register operand, the information is stored
15057 in inst.operands[].vectype.
15059 When there is only one type specifier, and all the register
15060 operands are the same type of hardware register, the type
15061 specifier applies to all register operands.
15063 If no type specifier is given, the shape is inferred from
15064 operand information.
15067 vadd.f16 s0, s1, s2: NS_HHH
15068 vabs.f16 s0, s1: NS_HH
15069 vmov.f16 s0, r1: NS_HR
15070 vmov.f16 r0, s1: NS_RH
15071 vcvt.f16 r0, s1: NS_RH
15072 vcvt.f16.s32 s2, s2, #29: NS_HFI
15073 vcvt.f16.s32 s2, s2: NS_HF
15076 if (!(inst
.operands
[j
].isreg
15077 && inst
.operands
[j
].isvec
15078 && inst
.operands
[j
].issingle
15079 && !inst
.operands
[j
].isquad
15080 && ((inst
.vectype
.elems
== 1
15081 && inst
.vectype
.el
[0].size
== 16)
15082 || (inst
.vectype
.elems
> 1
15083 && inst
.vectype
.el
[j
].size
== 16)
15084 || (inst
.vectype
.elems
== 0
15085 && inst
.operands
[j
].vectype
.type
!= NT_invtype
15086 && inst
.operands
[j
].vectype
.size
== 16))))
15091 if (!(inst
.operands
[j
].isreg
15092 && inst
.operands
[j
].isvec
15093 && inst
.operands
[j
].issingle
15094 && !inst
.operands
[j
].isquad
15095 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
15096 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
15097 || (inst
.vectype
.elems
== 0
15098 && (inst
.operands
[j
].vectype
.size
== 32
15099 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
15104 if (!(inst
.operands
[j
].isreg
15105 && inst
.operands
[j
].isvec
15106 && !inst
.operands
[j
].isquad
15107 && !inst
.operands
[j
].issingle
))
15112 if (!(inst
.operands
[j
].isreg
15113 && !inst
.operands
[j
].isvec
))
15118 if (!(inst
.operands
[j
].isreg
15119 && inst
.operands
[j
].isvec
15120 && inst
.operands
[j
].isquad
15121 && !inst
.operands
[j
].issingle
))
15126 if (!(!inst
.operands
[j
].isreg
15127 && !inst
.operands
[j
].isscalar
))
15132 if (!(!inst
.operands
[j
].isreg
15133 && inst
.operands
[j
].isscalar
))
15144 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15145 /* We've matched all the entries in the shape table, and we don't
15146 have any left over operands which have not been matched. */
15152 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15153 first_error (_("invalid instruction shape"));
15158 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15159 means the Q bit should be set). */
15162 neon_quad (enum neon_shape shape
)
15164 return neon_shape_class
[shape
] == SC_QUAD
;
15168 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15171 /* Allow modification to be made to types which are constrained to be
15172 based on the key element, based on bits set alongside N_EQK. */
15173 if ((typebits
& N_EQK
) != 0)
15175 if ((typebits
& N_HLF
) != 0)
15177 else if ((typebits
& N_DBL
) != 0)
15179 if ((typebits
& N_SGN
) != 0)
15180 *g_type
= NT_signed
;
15181 else if ((typebits
& N_UNS
) != 0)
15182 *g_type
= NT_unsigned
;
15183 else if ((typebits
& N_INT
) != 0)
15184 *g_type
= NT_integer
;
15185 else if ((typebits
& N_FLT
) != 0)
15186 *g_type
= NT_float
;
15187 else if ((typebits
& N_SIZ
) != 0)
15188 *g_type
= NT_untyped
;
15192 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15193 operand type, i.e. the single type specified in a Neon instruction when it
15194 is the only one given. */
15196 static struct neon_type_el
15197 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15199 struct neon_type_el dest
= *key
;
15201 gas_assert ((thisarg
& N_EQK
) != 0);
15203 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15208 /* Convert Neon type and size into compact bitmask representation. */
15210 static enum neon_type_mask
15211 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15218 case 8: return N_8
;
15219 case 16: return N_16
;
15220 case 32: return N_32
;
15221 case 64: return N_64
;
15229 case 8: return N_I8
;
15230 case 16: return N_I16
;
15231 case 32: return N_I32
;
15232 case 64: return N_I64
;
15240 case 16: return N_F16
;
15241 case 32: return N_F32
;
15242 case 64: return N_F64
;
15250 case 8: return N_P8
;
15251 case 16: return N_P16
;
15252 case 64: return N_P64
;
15260 case 8: return N_S8
;
15261 case 16: return N_S16
;
15262 case 32: return N_S32
;
15263 case 64: return N_S64
;
15271 case 8: return N_U8
;
15272 case 16: return N_U16
;
15273 case 32: return N_U32
;
15274 case 64: return N_U64
;
15280 if (size
== 16) return N_BF16
;
15289 /* Convert compact Neon bitmask type representation to a type and size. Only
15290 handles the case where a single bit is set in the mask. */
15293 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15294 enum neon_type_mask mask
)
15296 if ((mask
& N_EQK
) != 0)
15299 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15301 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
| N_BF16
))
15304 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15306 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15311 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15313 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15314 *type
= NT_unsigned
;
15315 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15316 *type
= NT_integer
;
15317 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15318 *type
= NT_untyped
;
15319 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15321 else if ((mask
& (N_F_ALL
)) != 0)
15323 else if ((mask
& (N_BF16
)) != 0)
15331 /* Modify a bitmask of allowed types. This is only needed for type
15335 modify_types_allowed (unsigned allowed
, unsigned mods
)
15338 enum neon_el_type type
;
15344 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15346 if (el_type_of_type_chk (&type
, &size
,
15347 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15349 neon_modify_type_size (mods
, &type
, &size
);
15350 destmask
|= type_chk_of_el_type (type
, size
);
15357 /* Check type and return type classification.
15358 The manual states (paraphrase): If one datatype is given, it indicates the
15360 - the second operand, if there is one
15361 - the operand, if there is no second operand
15362 - the result, if there are no operands.
15363 This isn't quite good enough though, so we use a concept of a "key" datatype
15364 which is set on a per-instruction basis, which is the one which matters when
15365 only one data type is written.
15366 Note: this function has side-effects (e.g. filling in missing operands). All
15367 Neon instructions should call it before performing bit encoding. */
15369 static struct neon_type_el
15370 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15373 unsigned i
, pass
, key_el
= 0;
15374 unsigned types
[NEON_MAX_TYPE_ELS
];
15375 enum neon_el_type k_type
= NT_invtype
;
15376 unsigned k_size
= -1u;
15377 struct neon_type_el badtype
= {NT_invtype
, -1};
15378 unsigned key_allowed
= 0;
15380 /* Optional registers in Neon instructions are always (not) in operand 1.
15381 Fill in the missing operand here, if it was omitted. */
15382 if (els
> 1 && !inst
.operands
[1].present
)
15383 inst
.operands
[1] = inst
.operands
[0];
15385 /* Suck up all the varargs. */
15387 for (i
= 0; i
< els
; i
++)
15389 unsigned thisarg
= va_arg (ap
, unsigned);
15390 if (thisarg
== N_IGNORE_TYPE
)
15395 types
[i
] = thisarg
;
15396 if ((thisarg
& N_KEY
) != 0)
15401 if (inst
.vectype
.elems
> 0)
15402 for (i
= 0; i
< els
; i
++)
15403 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15405 first_error (_("types specified in both the mnemonic and operands"));
15409 /* Duplicate inst.vectype elements here as necessary.
15410 FIXME: No idea if this is exactly the same as the ARM assembler,
15411 particularly when an insn takes one register and one non-register
15413 if (inst
.vectype
.elems
== 1 && els
> 1)
15416 inst
.vectype
.elems
= els
;
15417 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15418 for (j
= 0; j
< els
; j
++)
15420 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15423 else if (inst
.vectype
.elems
== 0 && els
> 0)
15426 /* No types were given after the mnemonic, so look for types specified
15427 after each operand. We allow some flexibility here; as long as the
15428 "key" operand has a type, we can infer the others. */
15429 for (j
= 0; j
< els
; j
++)
15430 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15431 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15433 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15435 for (j
= 0; j
< els
; j
++)
15436 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15437 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15442 first_error (_("operand types can't be inferred"));
15446 else if (inst
.vectype
.elems
!= els
)
15448 first_error (_("type specifier has the wrong number of parts"));
15452 for (pass
= 0; pass
< 2; pass
++)
15454 for (i
= 0; i
< els
; i
++)
15456 unsigned thisarg
= types
[i
];
15457 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15458 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15459 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15460 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15462 /* Decay more-specific signed & unsigned types to sign-insensitive
15463 integer types if sign-specific variants are unavailable. */
15464 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15465 && (types_allowed
& N_SU_ALL
) == 0)
15466 g_type
= NT_integer
;
15468 /* If only untyped args are allowed, decay any more specific types to
15469 them. Some instructions only care about signs for some element
15470 sizes, so handle that properly. */
15471 if (((types_allowed
& N_UNT
) == 0)
15472 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15473 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15474 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15475 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15476 g_type
= NT_untyped
;
15480 if ((thisarg
& N_KEY
) != 0)
15484 key_allowed
= thisarg
& ~N_KEY
;
15486 /* Check architecture constraint on FP16 extension. */
15488 && k_type
== NT_float
15489 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15491 inst
.error
= _(BAD_FP16
);
15498 if ((thisarg
& N_VFP
) != 0)
15500 enum neon_shape_el regshape
;
15501 unsigned regwidth
, match
;
15503 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15506 first_error (_("invalid instruction shape"));
15509 regshape
= neon_shape_tab
[ns
].el
[i
];
15510 regwidth
= neon_shape_el_size
[regshape
];
15512 /* In VFP mode, operands must match register widths. If we
15513 have a key operand, use its width, else use the width of
15514 the current operand. */
15520 /* FP16 will use a single precision register. */
15521 if (regwidth
== 32 && match
== 16)
15523 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15527 inst
.error
= _(BAD_FP16
);
15532 if (regwidth
!= match
)
15534 first_error (_("operand size must match register width"));
15539 if ((thisarg
& N_EQK
) == 0)
15541 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15543 if ((given_type
& types_allowed
) == 0)
15545 first_error (BAD_SIMD_TYPE
);
15551 enum neon_el_type mod_k_type
= k_type
;
15552 unsigned mod_k_size
= k_size
;
15553 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15554 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15556 first_error (_("inconsistent types in Neon instruction"));
15564 return inst
.vectype
.el
[key_el
];
15567 /* Neon-style VFP instruction forwarding. */
15569 /* Thumb VFP instructions have 0xE in the condition field. */
15572 do_vfp_cond_or_thumb (void)
15577 inst
.instruction
|= 0xe0000000;
15579 inst
.instruction
|= inst
.cond
<< 28;
15582 /* Look up and encode a simple mnemonic, for use as a helper function for the
15583 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15584 etc. It is assumed that operand parsing has already been done, and that the
15585 operands are in the form expected by the given opcode (this isn't necessarily
15586 the same as the form in which they were parsed, hence some massaging must
15587 take place before this function is called).
15588 Checks current arch version against that in the looked-up opcode. */
15591 do_vfp_nsyn_opcode (const char *opname
)
15593 const struct asm_opcode
*opcode
;
15595 opcode
= (const struct asm_opcode
*) str_hash_find (arm_ops_hsh
, opname
);
15600 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15601 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15608 inst
.instruction
= opcode
->tvalue
;
15609 opcode
->tencode ();
15613 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15614 opcode
->aencode ();
15619 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15621 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15623 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15626 do_vfp_nsyn_opcode ("fadds");
15628 do_vfp_nsyn_opcode ("fsubs");
15630 /* ARMv8.2 fp16 instruction. */
15632 do_scalar_fp16_v82_encode ();
15637 do_vfp_nsyn_opcode ("faddd");
15639 do_vfp_nsyn_opcode ("fsubd");
15643 /* Check operand types to see if this is a VFP instruction, and if so call
15647 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15649 enum neon_shape rs
;
15650 struct neon_type_el et
;
15655 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15656 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15660 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15661 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15662 N_F_ALL
| N_KEY
| N_VFP
);
15669 if (et
.type
!= NT_invtype
)
15680 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15682 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15684 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15687 do_vfp_nsyn_opcode ("fmacs");
15689 do_vfp_nsyn_opcode ("fnmacs");
15691 /* ARMv8.2 fp16 instruction. */
15693 do_scalar_fp16_v82_encode ();
15698 do_vfp_nsyn_opcode ("fmacd");
15700 do_vfp_nsyn_opcode ("fnmacd");
15705 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15707 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15709 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15712 do_vfp_nsyn_opcode ("ffmas");
15714 do_vfp_nsyn_opcode ("ffnmas");
15716 /* ARMv8.2 fp16 instruction. */
15718 do_scalar_fp16_v82_encode ();
15723 do_vfp_nsyn_opcode ("ffmad");
15725 do_vfp_nsyn_opcode ("ffnmad");
15730 do_vfp_nsyn_mul (enum neon_shape rs
)
15732 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15734 do_vfp_nsyn_opcode ("fmuls");
15736 /* ARMv8.2 fp16 instruction. */
15738 do_scalar_fp16_v82_encode ();
15741 do_vfp_nsyn_opcode ("fmuld");
15745 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15747 int is_neg
= (inst
.instruction
& 0x80) != 0;
15748 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15750 if (rs
== NS_FF
|| rs
== NS_HH
)
15753 do_vfp_nsyn_opcode ("fnegs");
15755 do_vfp_nsyn_opcode ("fabss");
15757 /* ARMv8.2 fp16 instruction. */
15759 do_scalar_fp16_v82_encode ();
15764 do_vfp_nsyn_opcode ("fnegd");
15766 do_vfp_nsyn_opcode ("fabsd");
15770 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15771 insns belong to Neon, and are handled elsewhere. */
15774 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15776 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15780 do_vfp_nsyn_opcode ("fldmdbs");
15782 do_vfp_nsyn_opcode ("fldmias");
15787 do_vfp_nsyn_opcode ("fstmdbs");
15789 do_vfp_nsyn_opcode ("fstmias");
15794 do_vfp_nsyn_sqrt (void)
15796 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15797 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15799 if (rs
== NS_FF
|| rs
== NS_HH
)
15801 do_vfp_nsyn_opcode ("fsqrts");
15803 /* ARMv8.2 fp16 instruction. */
15805 do_scalar_fp16_v82_encode ();
15808 do_vfp_nsyn_opcode ("fsqrtd");
15812 do_vfp_nsyn_div (void)
15814 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15815 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15816 N_F_ALL
| N_KEY
| N_VFP
);
15818 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15820 do_vfp_nsyn_opcode ("fdivs");
15822 /* ARMv8.2 fp16 instruction. */
15824 do_scalar_fp16_v82_encode ();
15827 do_vfp_nsyn_opcode ("fdivd");
15831 do_vfp_nsyn_nmul (void)
15833 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15834 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15835 N_F_ALL
| N_KEY
| N_VFP
);
15837 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15839 NEON_ENCODE (SINGLE
, inst
);
15840 do_vfp_sp_dyadic ();
15842 /* ARMv8.2 fp16 instruction. */
15844 do_scalar_fp16_v82_encode ();
15848 NEON_ENCODE (DOUBLE
, inst
);
15849 do_vfp_dp_rd_rn_rm ();
15851 do_vfp_cond_or_thumb ();
15855 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15859 neon_logbits (unsigned x
)
15861 return ffs (x
) - 4;
15864 #define LOW4(R) ((R) & 0xf)
15865 #define HI1(R) (((R) >> 4) & 1)
15866 #define LOW1(R) ((R) & 0x1)
15867 #define HI4(R) (((R) >> 1) & 0xf)
15870 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15875 first_error (BAD_EL_TYPE
);
15878 switch (inst
.operands
[0].imm
)
15881 first_error (_("invalid condition"));
15903 /* only accept eq and ne. */
15904 if (inst
.operands
[0].imm
> 1)
15906 first_error (_("invalid condition"));
15909 return inst
.operands
[0].imm
;
15911 if (inst
.operands
[0].imm
== 0x2)
15913 else if (inst
.operands
[0].imm
== 0x8)
15917 first_error (_("invalid condition"));
15921 switch (inst
.operands
[0].imm
)
15924 first_error (_("invalid condition"));
15940 /* Should be unreachable. */
15944 /* For VCTP (create vector tail predicate) in MVE. */
15949 unsigned size
= 0x0;
15951 if (inst
.cond
> COND_ALWAYS
)
15952 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15954 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15956 /* This is a typical MVE instruction which has no type but have size 8, 16,
15957 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15958 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15959 if ((inst
.operands
[0].present
) && (inst
.vectype
.el
[0].type
== NT_untyped
))
15960 dt
= inst
.vectype
.el
[0].size
;
15962 /* Setting this does not indicate an actual NEON instruction, but only
15963 indicates that the mnemonic accepts neon-style type suffixes. */
15977 first_error (_("Type is not allowed for this instruction"));
15979 inst
.instruction
|= size
<< 20;
15980 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15986 /* We are dealing with a vector predicated block. */
15987 if (inst
.operands
[0].present
)
15989 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15990 struct neon_type_el et
15991 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15994 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15996 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15998 if (et
.type
== NT_invtype
)
16001 if (et
.type
== NT_float
)
16003 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16005 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
16006 inst
.instruction
|= (et
.size
== 16) << 28;
16007 inst
.instruction
|= 0x3 << 20;
16011 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
16013 inst
.instruction
|= 1 << 28;
16014 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16017 if (inst
.operands
[2].isquad
)
16019 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16020 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16021 inst
.instruction
|= (fcond
& 0x2) >> 1;
16025 if (inst
.operands
[2].reg
== REG_SP
)
16026 as_tsktsk (MVE_BAD_SP
);
16027 inst
.instruction
|= 1 << 6;
16028 inst
.instruction
|= (fcond
& 0x2) << 4;
16029 inst
.instruction
|= inst
.operands
[2].reg
;
16031 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16032 inst
.instruction
|= (fcond
& 0x4) << 10;
16033 inst
.instruction
|= (fcond
& 0x1) << 7;
16036 set_pred_insn_type (VPT_INSN
);
16038 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
16039 | ((inst
.instruction
& 0xe000) >> 13);
16040 now_pred
.warn_deprecated
= false;
16041 now_pred
.type
= VECTOR_PRED
;
16048 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
16049 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
16050 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
16051 if (!inst
.operands
[2].present
)
16052 first_error (_("MVE vector or ARM register expected"));
16053 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16055 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
16056 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
16057 && inst
.operands
[1].isquad
)
16059 inst
.instruction
= N_MNEM_vcmp
;
16063 if (inst
.cond
> COND_ALWAYS
)
16064 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16066 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16068 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16069 struct neon_type_el et
16070 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16073 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
16074 && !inst
.operands
[2].iszr
, BAD_PC
);
16076 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16078 inst
.instruction
= 0xee010f00;
16079 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16080 inst
.instruction
|= (fcond
& 0x4) << 10;
16081 inst
.instruction
|= (fcond
& 0x1) << 7;
16082 if (et
.type
== NT_float
)
16084 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16086 inst
.instruction
|= (et
.size
== 16) << 28;
16087 inst
.instruction
|= 0x3 << 20;
16091 inst
.instruction
|= 1 << 28;
16092 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16094 if (inst
.operands
[2].isquad
)
16096 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16097 inst
.instruction
|= (fcond
& 0x2) >> 1;
16098 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16102 if (inst
.operands
[2].reg
== REG_SP
)
16103 as_tsktsk (MVE_BAD_SP
);
16104 inst
.instruction
|= 1 << 6;
16105 inst
.instruction
|= (fcond
& 0x2) << 4;
16106 inst
.instruction
|= inst
.operands
[2].reg
;
16114 do_mve_vmaxa_vmina (void)
16116 if (inst
.cond
> COND_ALWAYS
)
16117 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16119 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16121 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16122 struct neon_type_el et
16123 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
16125 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16126 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16127 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16128 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16129 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16134 do_mve_vfmas (void)
16136 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16137 struct neon_type_el et
16138 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
16140 if (inst
.cond
> COND_ALWAYS
)
16141 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16143 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16145 if (inst
.operands
[2].reg
== REG_SP
)
16146 as_tsktsk (MVE_BAD_SP
);
16147 else if (inst
.operands
[2].reg
== REG_PC
)
16148 as_tsktsk (MVE_BAD_PC
);
16150 inst
.instruction
|= (et
.size
== 16) << 28;
16151 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16152 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16153 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16154 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16155 inst
.instruction
|= inst
.operands
[2].reg
;
16160 do_mve_viddup (void)
16162 if (inst
.cond
> COND_ALWAYS
)
16163 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16165 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16167 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
16168 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
16169 _("immediate must be either 1, 2, 4 or 8"));
16171 enum neon_shape rs
;
16172 struct neon_type_el et
;
16174 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
16176 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
16177 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
16182 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
16183 if (inst
.operands
[2].reg
== REG_SP
)
16184 as_tsktsk (MVE_BAD_SP
);
16185 else if (inst
.operands
[2].reg
== REG_PC
)
16186 first_error (BAD_PC
);
16188 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16189 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16190 Rm
= inst
.operands
[2].reg
>> 1;
16192 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16193 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16194 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16195 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16196 inst
.instruction
|= (imm
> 2) << 7;
16197 inst
.instruction
|= Rm
<< 1;
16198 inst
.instruction
|= (imm
== 2 || imm
== 8);
16203 do_mve_vmlas (void)
16205 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16206 struct neon_type_el et
16207 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16209 if (inst
.operands
[2].reg
== REG_PC
)
16210 as_tsktsk (MVE_BAD_PC
);
16211 else if (inst
.operands
[2].reg
== REG_SP
)
16212 as_tsktsk (MVE_BAD_SP
);
16214 if (inst
.cond
> COND_ALWAYS
)
16215 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16217 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16219 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16220 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16221 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16222 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16223 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16224 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16225 inst
.instruction
|= inst
.operands
[2].reg
;
16230 do_mve_vshll (void)
16232 struct neon_type_el et
16233 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16235 if (inst
.cond
> COND_ALWAYS
)
16236 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16238 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16240 int imm
= inst
.operands
[2].imm
;
16241 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16242 _("immediate value out of range"));
16244 if ((unsigned)imm
== et
.size
)
16246 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16247 inst
.instruction
|= 0x110001;
16251 inst
.instruction
|= (et
.size
+ imm
) << 16;
16252 inst
.instruction
|= 0x800140;
16255 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16256 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16257 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16258 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16259 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16264 do_mve_vshlc (void)
16266 if (inst
.cond
> COND_ALWAYS
)
16267 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16269 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16271 if (inst
.operands
[1].reg
== REG_PC
)
16272 as_tsktsk (MVE_BAD_PC
);
16273 else if (inst
.operands
[1].reg
== REG_SP
)
16274 as_tsktsk (MVE_BAD_SP
);
16276 int imm
= inst
.operands
[2].imm
;
16277 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16279 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16280 inst
.instruction
|= (imm
& 0x1f) << 16;
16281 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16282 inst
.instruction
|= inst
.operands
[1].reg
;
16287 do_mve_vshrn (void)
16290 switch (inst
.instruction
)
16292 case M_MNEM_vshrnt
:
16293 case M_MNEM_vshrnb
:
16294 case M_MNEM_vrshrnt
:
16295 case M_MNEM_vrshrnb
:
16296 types
= N_I16
| N_I32
;
16298 case M_MNEM_vqshrnt
:
16299 case M_MNEM_vqshrnb
:
16300 case M_MNEM_vqrshrnt
:
16301 case M_MNEM_vqrshrnb
:
16302 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16304 case M_MNEM_vqshrunt
:
16305 case M_MNEM_vqshrunb
:
16306 case M_MNEM_vqrshrunt
:
16307 case M_MNEM_vqrshrunb
:
16308 types
= N_S16
| N_S32
;
16314 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16316 if (inst
.cond
> COND_ALWAYS
)
16317 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16319 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16321 unsigned Qd
= inst
.operands
[0].reg
;
16322 unsigned Qm
= inst
.operands
[1].reg
;
16323 unsigned imm
= inst
.operands
[2].imm
;
16324 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16326 ? _("immediate operand expected in the range [1,8]")
16327 : _("immediate operand expected in the range [1,16]"));
16329 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16330 inst
.instruction
|= HI1 (Qd
) << 22;
16331 inst
.instruction
|= (et
.size
- imm
) << 16;
16332 inst
.instruction
|= LOW4 (Qd
) << 12;
16333 inst
.instruction
|= HI1 (Qm
) << 5;
16334 inst
.instruction
|= LOW4 (Qm
);
16339 do_mve_vqmovn (void)
16341 struct neon_type_el et
;
16342 if (inst
.instruction
== M_MNEM_vqmovnt
16343 || inst
.instruction
== M_MNEM_vqmovnb
)
16344 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16345 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16347 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16349 if (inst
.cond
> COND_ALWAYS
)
16350 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16352 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16354 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16355 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16356 inst
.instruction
|= (et
.size
== 32) << 18;
16357 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16358 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16359 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16364 do_mve_vpsel (void)
16366 neon_select_shape (NS_QQQ
, NS_NULL
);
16368 if (inst
.cond
> COND_ALWAYS
)
16369 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16371 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16373 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16374 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16375 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16376 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16377 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16378 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16383 do_mve_vpnot (void)
16385 if (inst
.cond
> COND_ALWAYS
)
16386 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16388 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16392 do_mve_vmaxnma_vminnma (void)
16394 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16395 struct neon_type_el et
16396 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16398 if (inst
.cond
> COND_ALWAYS
)
16399 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16401 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16403 inst
.instruction
|= (et
.size
== 16) << 28;
16404 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16405 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16406 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16407 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16412 do_mve_vcmul (void)
16414 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16415 struct neon_type_el et
16416 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16418 if (inst
.cond
> COND_ALWAYS
)
16419 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16421 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16423 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16424 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16425 _("immediate out of range"));
16427 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16428 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16429 as_tsktsk (BAD_MVE_SRCDEST
);
16431 inst
.instruction
|= (et
.size
== 32) << 28;
16432 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16433 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16434 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16435 inst
.instruction
|= (rot
> 90) << 12;
16436 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16437 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16438 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16439 inst
.instruction
|= (rot
== 90 || rot
== 270);
16443 /* To handle the Low Overhead Loop instructions
16444 in Armv8.1-M Mainline and MVE. */
16448 unsigned long insn
= inst
.instruction
;
16450 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16452 if (insn
== T_MNEM_lctp
)
16455 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16457 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16459 struct neon_type_el et
16460 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16461 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16468 constraint (!inst
.operands
[0].present
,
16470 /* fall through. */
16473 if (!inst
.operands
[0].present
)
16474 inst
.instruction
|= 1 << 21;
16476 v8_1_loop_reloc (true);
16481 v8_1_loop_reloc (false);
16482 /* fall through. */
16485 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16487 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16488 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16489 else if (inst
.operands
[1].reg
== REG_PC
)
16490 as_tsktsk (MVE_BAD_PC
);
16491 if (inst
.operands
[1].reg
== REG_SP
)
16492 as_tsktsk (MVE_BAD_SP
);
16494 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16504 do_vfp_nsyn_cmp (void)
16506 enum neon_shape rs
;
16507 if (!inst
.operands
[0].isreg
)
16514 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16515 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16519 if (inst
.operands
[1].isreg
)
16521 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16522 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16524 if (rs
== NS_FF
|| rs
== NS_HH
)
16526 NEON_ENCODE (SINGLE
, inst
);
16527 do_vfp_sp_monadic ();
16531 NEON_ENCODE (DOUBLE
, inst
);
16532 do_vfp_dp_rd_rm ();
16537 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16538 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16540 switch (inst
.instruction
& 0x0fffffff)
16543 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16546 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16552 if (rs
== NS_FI
|| rs
== NS_HI
)
16554 NEON_ENCODE (SINGLE
, inst
);
16555 do_vfp_sp_compare_z ();
16559 NEON_ENCODE (DOUBLE
, inst
);
16563 do_vfp_cond_or_thumb ();
16565 /* ARMv8.2 fp16 instruction. */
16566 if (rs
== NS_HI
|| rs
== NS_HH
)
16567 do_scalar_fp16_v82_encode ();
16571 nsyn_insert_sp (void)
16573 inst
.operands
[1] = inst
.operands
[0];
16574 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16575 inst
.operands
[0].reg
= REG_SP
;
16576 inst
.operands
[0].isreg
= 1;
16577 inst
.operands
[0].writeback
= 1;
16578 inst
.operands
[0].present
= 1;
16581 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16582 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16585 neon_dp_fixup (struct arm_it
* insn
)
16587 unsigned int i
= insn
->instruction
;
16592 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16603 insn
->instruction
= i
;
16607 mve_encode_qqr (int size
, int U
, int fp
)
16609 if (inst
.operands
[2].reg
== REG_SP
)
16610 as_tsktsk (MVE_BAD_SP
);
16611 else if (inst
.operands
[2].reg
== REG_PC
)
16612 as_tsktsk (MVE_BAD_PC
);
16617 if (((unsigned)inst
.instruction
) == 0xd00)
16618 inst
.instruction
= 0xee300f40;
16620 else if (((unsigned)inst
.instruction
) == 0x200d00)
16621 inst
.instruction
= 0xee301f40;
16623 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16624 inst
.instruction
= 0xee310e60;
16626 /* Setting size which is 1 for F16 and 0 for F32. */
16627 inst
.instruction
|= (size
== 16) << 28;
16632 if (((unsigned)inst
.instruction
) == 0x800)
16633 inst
.instruction
= 0xee010f40;
16635 else if (((unsigned)inst
.instruction
) == 0x1000800)
16636 inst
.instruction
= 0xee011f40;
16638 else if (((unsigned)inst
.instruction
) == 0)
16639 inst
.instruction
= 0xee000f40;
16641 else if (((unsigned)inst
.instruction
) == 0x200)
16642 inst
.instruction
= 0xee001f40;
16644 else if (((unsigned)inst
.instruction
) == 0x900)
16645 inst
.instruction
= 0xee010e40;
16647 else if (((unsigned)inst
.instruction
) == 0x910)
16648 inst
.instruction
= 0xee011e60;
16650 else if (((unsigned)inst
.instruction
) == 0x10)
16651 inst
.instruction
= 0xee000f60;
16653 else if (((unsigned)inst
.instruction
) == 0x210)
16654 inst
.instruction
= 0xee001f60;
16656 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16657 inst
.instruction
= 0xee000e40;
16659 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16660 inst
.instruction
= 0xee010e60;
16662 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16663 inst
.instruction
= 0xfe010e60;
16666 inst
.instruction
|= U
<< 28;
16668 /* Setting bits for size. */
16669 inst
.instruction
|= neon_logbits (size
) << 20;
16671 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16672 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16673 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16674 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16675 inst
.instruction
|= inst
.operands
[2].reg
;
16680 mve_encode_rqq (unsigned bit28
, unsigned size
)
16682 inst
.instruction
|= bit28
<< 28;
16683 inst
.instruction
|= neon_logbits (size
) << 20;
16684 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16685 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16686 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16687 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16688 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16693 mve_encode_qqq (int ubit
, int size
)
16696 inst
.instruction
|= (ubit
!= 0) << 28;
16697 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16698 inst
.instruction
|= neon_logbits (size
) << 20;
16699 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16700 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16701 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16702 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16703 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16709 mve_encode_rq (unsigned bit28
, unsigned size
)
16711 inst
.instruction
|= bit28
<< 28;
16712 inst
.instruction
|= neon_logbits (size
) << 18;
16713 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16714 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16719 mve_encode_rrqq (unsigned U
, unsigned size
)
16721 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16723 inst
.instruction
|= U
<< 28;
16724 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16725 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16726 inst
.instruction
|= (size
== 32) << 16;
16727 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16728 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16729 inst
.instruction
|= inst
.operands
[3].reg
;
16733 /* Helper function for neon_three_same handling the operands. */
16735 neon_three_args (int isquad
)
16737 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16738 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16739 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16740 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16741 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16742 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16743 inst
.instruction
|= (isquad
!= 0) << 6;
16747 /* Encode insns with bit pattern:
16749 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16750 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16752 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16753 different meaning for some instruction. */
16756 neon_three_same (int isquad
, int ubit
, int size
)
16758 neon_three_args (isquad
);
16759 inst
.instruction
|= (ubit
!= 0) << 24;
16761 inst
.instruction
|= neon_logbits (size
) << 20;
16763 neon_dp_fixup (&inst
);
16766 /* Encode instructions of the form:
16768 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16769 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16771 Don't write size if SIZE == -1. */
16774 neon_two_same (int qbit
, int ubit
, int size
)
16776 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16777 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16778 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16779 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16780 inst
.instruction
|= (qbit
!= 0) << 6;
16781 inst
.instruction
|= (ubit
!= 0) << 24;
16784 inst
.instruction
|= neon_logbits (size
) << 18;
16786 neon_dp_fixup (&inst
);
16789 enum vfp_or_neon_is_neon_bits
16792 NEON_CHECK_ARCH
= 2,
16793 NEON_CHECK_ARCH8
= 4
16796 /* Call this function if an instruction which may have belonged to the VFP or
16797 Neon instruction sets, but turned out to be a Neon instruction (due to the
16798 operand types involved, etc.). We have to check and/or fix-up a couple of
16801 - Make sure the user hasn't attempted to make a Neon instruction
16803 - Alter the value in the condition code field if necessary.
16804 - Make sure that the arch supports Neon instructions.
16806 Which of these operations take place depends on bits from enum
16807 vfp_or_neon_is_neon_bits.
16809 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16810 current instruction's condition is COND_ALWAYS, the condition field is
16811 changed to inst.uncond_value. This is necessary because instructions shared
16812 between VFP and Neon may be conditional for the VFP variants only, and the
16813 unconditional Neon version must have, e.g., 0xF in the condition field. */
16816 vfp_or_neon_is_neon (unsigned check
)
16818 /* Conditions are always legal in Thumb mode (IT blocks). */
16819 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16821 if (inst
.cond
!= COND_ALWAYS
)
16823 first_error (_(BAD_COND
));
16826 if (inst
.uncond_value
!= -1u)
16827 inst
.instruction
|= inst
.uncond_value
<< 28;
16831 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16832 || ((check
& NEON_CHECK_ARCH8
)
16833 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16835 first_error (_(BAD_FPU
));
16843 /* Return TRUE if the SIMD instruction is available for the current
16844 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16845 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16846 vfp_or_neon_is_neon for the NEON specific checks. */
16849 check_simd_pred_availability (int fp
, unsigned check
)
16851 if (inst
.cond
> COND_ALWAYS
)
16853 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16855 inst
.error
= BAD_FPU
;
16858 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16860 else if (inst
.cond
< COND_ALWAYS
)
16862 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16863 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16864 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16869 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16870 && vfp_or_neon_is_neon (check
) == FAIL
)
16873 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16874 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16879 /* Neon instruction encoders, in approximate order of appearance. */
16882 do_neon_dyadic_i_su (void)
16884 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16887 enum neon_shape rs
;
16888 struct neon_type_el et
;
16889 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16890 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16892 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16894 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16898 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16900 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16904 do_neon_dyadic_i64_su (void)
16906 if (!check_simd_pred_availability (false, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16908 enum neon_shape rs
;
16909 struct neon_type_el et
;
16910 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16912 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16913 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16917 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16918 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16921 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16923 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16927 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16930 unsigned size
= et
.size
>> 3;
16931 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16932 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16933 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16934 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16935 inst
.instruction
|= (isquad
!= 0) << 6;
16936 inst
.instruction
|= immbits
<< 16;
16937 inst
.instruction
|= (size
>> 3) << 7;
16938 inst
.instruction
|= (size
& 0x7) << 19;
16940 inst
.instruction
|= (uval
!= 0) << 24;
16942 neon_dp_fixup (&inst
);
16948 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16951 if (!inst
.operands
[2].isreg
)
16953 enum neon_shape rs
;
16954 struct neon_type_el et
;
16955 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16957 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16958 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16962 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16963 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16965 int imm
= inst
.operands
[2].imm
;
16967 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16968 _("immediate out of range for shift"));
16969 NEON_ENCODE (IMMED
, inst
);
16970 neon_imm_shift (false, 0, neon_quad (rs
), et
, imm
);
16974 enum neon_shape rs
;
16975 struct neon_type_el et
;
16976 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16978 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16979 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16983 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16984 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16990 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16991 _("invalid instruction shape"));
16992 if (inst
.operands
[2].reg
== REG_SP
)
16993 as_tsktsk (MVE_BAD_SP
);
16994 else if (inst
.operands
[2].reg
== REG_PC
)
16995 as_tsktsk (MVE_BAD_PC
);
16997 inst
.instruction
= 0xee311e60;
16998 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16999 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17000 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17001 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17002 inst
.instruction
|= inst
.operands
[2].reg
;
17009 /* VSHL/VQSHL 3-register variants have syntax such as:
17011 whereas other 3-register operations encoded by neon_three_same have
17014 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
17015 operands[2].reg here. */
17016 tmp
= inst
.operands
[2].reg
;
17017 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17018 inst
.operands
[1].reg
= tmp
;
17019 NEON_ENCODE (INTEGER
, inst
);
17020 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17026 do_neon_qshl (void)
17028 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17031 if (!inst
.operands
[2].isreg
)
17033 enum neon_shape rs
;
17034 struct neon_type_el et
;
17035 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17037 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
17038 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
17042 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17043 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
17045 int imm
= inst
.operands
[2].imm
;
17047 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17048 _("immediate out of range for shift"));
17049 NEON_ENCODE (IMMED
, inst
);
17050 neon_imm_shift (true, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
17054 enum neon_shape rs
;
17055 struct neon_type_el et
;
17057 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17059 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17060 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
17064 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17065 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17070 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17071 _("invalid instruction shape"));
17072 if (inst
.operands
[2].reg
== REG_SP
)
17073 as_tsktsk (MVE_BAD_SP
);
17074 else if (inst
.operands
[2].reg
== REG_PC
)
17075 as_tsktsk (MVE_BAD_PC
);
17077 inst
.instruction
= 0xee311ee0;
17078 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17079 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17080 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17081 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17082 inst
.instruction
|= inst
.operands
[2].reg
;
17089 /* See note in do_neon_shl. */
17090 tmp
= inst
.operands
[2].reg
;
17091 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17092 inst
.operands
[1].reg
= tmp
;
17093 NEON_ENCODE (INTEGER
, inst
);
17094 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17100 do_neon_rshl (void)
17102 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17105 enum neon_shape rs
;
17106 struct neon_type_el et
;
17107 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17109 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17110 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17114 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17115 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
17122 if (inst
.operands
[2].reg
== REG_PC
)
17123 as_tsktsk (MVE_BAD_PC
);
17124 else if (inst
.operands
[2].reg
== REG_SP
)
17125 as_tsktsk (MVE_BAD_SP
);
17127 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17128 _("invalid instruction shape"));
17130 if (inst
.instruction
== 0x0000510)
17131 /* We are dealing with vqrshl. */
17132 inst
.instruction
= 0xee331ee0;
17134 /* We are dealing with vrshl. */
17135 inst
.instruction
= 0xee331e60;
17137 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17138 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17139 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17140 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17141 inst
.instruction
|= inst
.operands
[2].reg
;
17146 tmp
= inst
.operands
[2].reg
;
17147 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17148 inst
.operands
[1].reg
= tmp
;
17149 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17154 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
17156 /* Handle .I8 pseudo-instructions. */
17159 /* Unfortunately, this will make everything apart from zero out-of-range.
17160 FIXME is this the intended semantics? There doesn't seem much point in
17161 accepting .I8 if so. */
17162 immediate
|= immediate
<< 8;
17168 if (immediate
== (immediate
& 0x000000ff))
17170 *immbits
= immediate
;
17173 else if (immediate
== (immediate
& 0x0000ff00))
17175 *immbits
= immediate
>> 8;
17178 else if (immediate
== (immediate
& 0x00ff0000))
17180 *immbits
= immediate
>> 16;
17183 else if (immediate
== (immediate
& 0xff000000))
17185 *immbits
= immediate
>> 24;
17188 if ((immediate
& 0xffff) != (immediate
>> 16))
17189 goto bad_immediate
;
17190 immediate
&= 0xffff;
17193 if (immediate
== (immediate
& 0x000000ff))
17195 *immbits
= immediate
;
17198 else if (immediate
== (immediate
& 0x0000ff00))
17200 *immbits
= immediate
>> 8;
17205 first_error (_("immediate value out of range"));
17210 do_neon_logic (void)
17212 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17214 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17216 && !check_simd_pred_availability (false,
17217 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17219 else if (rs
!= NS_QQQ
17220 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17221 first_error (BAD_FPU
);
17223 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17224 /* U bit and size field were set as part of the bitmask. */
17225 NEON_ENCODE (INTEGER
, inst
);
17226 neon_three_same (neon_quad (rs
), 0, -1);
17230 const int three_ops_form
= (inst
.operands
[2].present
17231 && !inst
.operands
[2].isreg
);
17232 const int immoperand
= (three_ops_form
? 2 : 1);
17233 enum neon_shape rs
= (three_ops_form
17234 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17235 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17236 /* Because neon_select_shape makes the second operand a copy of the first
17237 if the second operand is not present. */
17239 && !check_simd_pred_availability (false,
17240 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17242 else if (rs
!= NS_QQI
17243 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17244 first_error (BAD_FPU
);
17246 struct neon_type_el et
;
17247 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17248 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17250 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17253 if (et
.type
== NT_invtype
)
17255 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17260 if (three_ops_form
)
17261 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17262 _("first and second operands shall be the same register"));
17264 NEON_ENCODE (IMMED
, inst
);
17266 immbits
= inst
.operands
[immoperand
].imm
;
17269 /* .i64 is a pseudo-op, so the immediate must be a repeating
17271 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17272 inst
.operands
[immoperand
].reg
: 0))
17274 /* Set immbits to an invalid constant. */
17275 immbits
= 0xdeadbeef;
17282 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17286 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17290 /* Pseudo-instruction for VBIC. */
17291 neon_invert_size (&immbits
, 0, et
.size
);
17292 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17296 /* Pseudo-instruction for VORR. */
17297 neon_invert_size (&immbits
, 0, et
.size
);
17298 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17308 inst
.instruction
|= neon_quad (rs
) << 6;
17309 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17310 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17311 inst
.instruction
|= cmode
<< 8;
17312 neon_write_immbits (immbits
);
17314 neon_dp_fixup (&inst
);
17319 do_neon_bitfield (void)
17321 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17322 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17323 neon_three_same (neon_quad (rs
), 0, -1);
17327 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17330 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17331 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17333 if (et
.type
== NT_float
)
17335 NEON_ENCODE (FLOAT
, inst
);
17337 mve_encode_qqr (et
.size
, 0, 1);
17339 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17343 NEON_ENCODE (INTEGER
, inst
);
17345 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17347 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17353 do_neon_dyadic_if_su_d (void)
17355 /* This version only allow D registers, but that constraint is enforced during
17356 operand parsing so we don't need to do anything extra here. */
17357 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17361 do_neon_dyadic_if_i_d (void)
17363 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17364 affected if we specify unsigned args. */
17365 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17369 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17371 constraint (size
< 32, BAD_ADDR_MODE
);
17372 constraint (size
!= elsize
, BAD_EL_TYPE
);
17373 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17374 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17375 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17376 _("destination register and offset register may not be the"
17379 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17386 constraint ((imm
% (size
/ 8) != 0)
17387 || imm
> (0x7f << neon_logbits (size
)),
17388 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17389 " range of +/-[0,508]")
17390 : _("immediate must be a multiple of 8 in the"
17391 " range of +/-[0,1016]"));
17392 inst
.instruction
|= 0x11 << 24;
17393 inst
.instruction
|= add
<< 23;
17394 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17395 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17396 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17397 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17398 inst
.instruction
|= 1 << 12;
17399 inst
.instruction
|= (size
== 64) << 8;
17400 inst
.instruction
&= 0xffffff00;
17401 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17402 inst
.instruction
|= imm
>> neon_logbits (size
);
17406 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17408 unsigned os
= inst
.operands
[1].imm
>> 5;
17409 unsigned type
= inst
.vectype
.el
[0].type
;
17410 constraint (os
!= 0 && size
== 8,
17411 _("can not shift offsets when accessing less than half-word"));
17412 constraint (os
&& os
!= neon_logbits (size
),
17413 _("shift immediate must be 1, 2 or 3 for half-word, word"
17414 " or double-word accesses respectively"));
17415 if (inst
.operands
[1].reg
== REG_PC
)
17416 as_tsktsk (MVE_BAD_PC
);
17421 constraint (elsize
>= 64, BAD_EL_TYPE
);
17424 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17428 constraint (elsize
!= size
, BAD_EL_TYPE
);
17433 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17437 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17438 _("destination register and offset register may not be"
17440 constraint (size
== elsize
&& type
== NT_signed
, BAD_EL_TYPE
);
17441 constraint (size
!= elsize
&& type
!= NT_unsigned
&& type
!= NT_signed
,
17443 inst
.instruction
|= ((size
== elsize
) || (type
== NT_unsigned
)) << 28;
17447 constraint (type
!= NT_untyped
, BAD_EL_TYPE
);
17450 inst
.instruction
|= 1 << 23;
17451 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17452 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17453 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17454 inst
.instruction
|= neon_logbits (elsize
) << 7;
17455 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17456 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17457 inst
.instruction
|= !!os
;
17461 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17463 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17465 constraint (size
>= 64, BAD_ADDR_MODE
);
17469 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17472 constraint (elsize
!= size
, BAD_EL_TYPE
);
17479 constraint (elsize
!= size
&& type
!= NT_unsigned
17480 && type
!= NT_signed
, BAD_EL_TYPE
);
17484 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17487 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17495 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17500 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17503 constraint (1, _("immediate must be a multiple of 2 in the"
17504 " range of +/-[0,254]"));
17507 constraint (1, _("immediate must be a multiple of 4 in the"
17508 " range of +/-[0,508]"));
17513 if (size
!= elsize
)
17515 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17516 constraint (inst
.operands
[0].reg
> 14,
17517 _("MVE vector register in the range [Q0..Q7] expected"));
17518 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17519 inst
.instruction
|= (size
== 16) << 19;
17520 inst
.instruction
|= neon_logbits (elsize
) << 7;
17524 if (inst
.operands
[1].reg
== REG_PC
)
17525 as_tsktsk (MVE_BAD_PC
);
17526 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17527 as_tsktsk (MVE_BAD_SP
);
17528 inst
.instruction
|= 1 << 12;
17529 inst
.instruction
|= neon_logbits (size
) << 7;
17531 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17532 inst
.instruction
|= add
<< 23;
17533 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17534 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17535 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17536 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17537 inst
.instruction
&= 0xffffff80;
17538 inst
.instruction
|= imm
>> neon_logbits (size
);
17543 do_mve_vstr_vldr (void)
17548 if (inst
.cond
> COND_ALWAYS
)
17549 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17551 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17553 switch (inst
.instruction
)
17560 /* fall through. */
17566 /* fall through. */
17572 /* fall through. */
17578 /* fall through. */
17583 unsigned elsize
= inst
.vectype
.el
[0].size
;
17585 if (inst
.operands
[1].isquad
)
17587 /* We are dealing with [Q, imm]{!} cases. */
17588 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17592 if (inst
.operands
[1].immisreg
== 2)
17594 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17595 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17597 else if (!inst
.operands
[1].immisreg
)
17599 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17600 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17603 constraint (1, BAD_ADDR_MODE
);
17610 do_mve_vst_vld (void)
17612 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17615 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17616 || inst
.relocs
[0].exp
.X_add_number
!= 0
17617 || inst
.operands
[1].immisreg
!= 0,
17619 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17620 if (inst
.operands
[1].reg
== REG_PC
)
17621 as_tsktsk (MVE_BAD_PC
);
17622 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17623 as_tsktsk (MVE_BAD_SP
);
17626 /* These instructions are one of the "exceptions" mentioned in
17627 handle_pred_state. They are MVE instructions that are not VPT compatible
17628 and do not accept a VPT code, thus appending such a code is a syntax
17630 if (inst
.cond
> COND_ALWAYS
)
17631 first_error (BAD_SYNTAX
);
17632 /* If we append a scalar condition code we can set this to
17633 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17634 else if (inst
.cond
< COND_ALWAYS
)
17635 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17637 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17639 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17640 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17641 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17642 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17643 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17648 do_mve_vaddlv (void)
17650 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17651 struct neon_type_el et
17652 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17654 if (et
.type
== NT_invtype
)
17655 first_error (BAD_EL_TYPE
);
17657 if (inst
.cond
> COND_ALWAYS
)
17658 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17660 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17662 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17664 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17665 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17666 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17667 inst
.instruction
|= inst
.operands
[2].reg
;
17672 do_neon_dyadic_if_su (void)
17674 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17675 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17678 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17679 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17680 && et
.type
== NT_float
17681 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17683 if (!check_simd_pred_availability (et
.type
== NT_float
,
17684 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17687 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17691 do_neon_addsub_if_i (void)
17693 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17694 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17697 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17698 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17699 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17701 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17702 /* If we are parsing Q registers and the element types match MVE, which NEON
17703 also supports, then we must check whether this is an instruction that can
17704 be used by both MVE/NEON. This distinction can be made based on whether
17705 they are predicated or not. */
17706 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17708 if (!check_simd_pred_availability (et
.type
== NT_float
,
17709 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17714 /* If they are either in a D register or are using an unsupported. */
17716 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17720 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17721 affected if we specify unsigned args. */
17722 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17725 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17727 V<op> A,B (A is operand 0, B is operand 2)
17732 so handle that case specially. */
17735 neon_exchange_operands (void)
17737 if (inst
.operands
[1].present
)
17739 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17741 /* Swap operands[1] and operands[2]. */
17742 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17743 inst
.operands
[1] = inst
.operands
[2];
17744 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17749 inst
.operands
[1] = inst
.operands
[2];
17750 inst
.operands
[2] = inst
.operands
[0];
17755 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17757 if (inst
.operands
[2].isreg
)
17760 neon_exchange_operands ();
17761 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17765 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17766 struct neon_type_el et
= neon_check_type (2, rs
,
17767 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17769 NEON_ENCODE (IMMED
, inst
);
17770 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17771 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17772 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17773 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17774 inst
.instruction
|= neon_quad (rs
) << 6;
17775 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17776 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17778 neon_dp_fixup (&inst
);
17785 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, false);
17789 do_neon_cmp_inv (void)
17791 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, true);
17797 neon_compare (N_IF_32
, N_IF_32
, false);
17800 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17801 scalars, which are encoded in 5 bits, M : Rm.
17802 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17803 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17806 Dot Product instructions are similar to multiply instructions except elsize
17807 should always be 32.
17809 This function translates SCALAR, which is GAS's internal encoding of indexed
17810 scalar register, to raw encoding. There is also register and index range
17811 check based on ELSIZE. */
17814 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17816 unsigned regno
= NEON_SCALAR_REG (scalar
);
17817 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17822 if (regno
> 7 || elno
> 3)
17824 return regno
| (elno
<< 3);
17827 if (regno
> 15 || elno
> 1)
17829 return regno
| (elno
<< 4);
17833 first_error (_("scalar out of range for multiply instruction"));
17839 /* Encode multiply / multiply-accumulate scalar instructions. */
17842 neon_mul_mac (struct neon_type_el et
, int ubit
)
17846 /* Give a more helpful error message if we have an invalid type. */
17847 if (et
.type
== NT_invtype
)
17850 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17851 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17852 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17853 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17854 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17855 inst
.instruction
|= LOW4 (scalar
);
17856 inst
.instruction
|= HI1 (scalar
) << 5;
17857 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17858 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17859 inst
.instruction
|= (ubit
!= 0) << 24;
17861 neon_dp_fixup (&inst
);
17865 do_neon_mac_maybe_scalar (void)
17867 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17870 if (!check_simd_pred_availability (false, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17873 if (inst
.operands
[2].isscalar
)
17875 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17876 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17877 struct neon_type_el et
= neon_check_type (3, rs
,
17878 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17879 NEON_ENCODE (SCALAR
, inst
);
17880 neon_mul_mac (et
, neon_quad (rs
));
17882 else if (!inst
.operands
[2].isvec
)
17884 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17886 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17887 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17889 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17893 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17894 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17895 affected if we specify unsigned args. */
17896 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17901 do_bfloat_vfma (void)
17903 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
17904 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
17905 enum neon_shape rs
;
17908 if (inst
.instruction
!= B_MNEM_vfmab
)
17911 inst
.instruction
= B_MNEM_vfmat
;
17914 if (inst
.operands
[2].isscalar
)
17916 rs
= neon_select_shape (NS_QQS
, NS_NULL
);
17917 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17919 inst
.instruction
|= (1 << 25);
17920 int idx
= inst
.operands
[2].reg
& 0xf;
17921 constraint (!(idx
< 4), _("index must be in the range 0 to 3"));
17922 inst
.operands
[2].reg
>>= 4;
17923 constraint (!(inst
.operands
[2].reg
< 8),
17924 _("indexed register must be less than 8"));
17925 neon_three_args (t_bit
);
17926 inst
.instruction
|= ((idx
& 1) << 3);
17927 inst
.instruction
|= ((idx
& 2) << 4);
17931 rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17932 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17933 neon_three_args (t_bit
);
17939 do_neon_fmac (void)
17941 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17942 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17945 if (!check_simd_pred_availability (true, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17948 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17950 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17951 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17957 if (inst
.operands
[2].reg
== REG_SP
)
17958 as_tsktsk (MVE_BAD_SP
);
17959 else if (inst
.operands
[2].reg
== REG_PC
)
17960 as_tsktsk (MVE_BAD_PC
);
17962 inst
.instruction
= 0xee310e40;
17963 inst
.instruction
|= (et
.size
== 16) << 28;
17964 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17965 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17966 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17967 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17968 inst
.instruction
|= inst
.operands
[2].reg
;
17975 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17978 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17984 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_bf16
) &&
17985 inst
.cond
== COND_ALWAYS
)
17987 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17988 inst
.instruction
= N_MNEM_vfma
;
17989 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17991 return do_neon_fmac();
18002 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18003 struct neon_type_el et
= neon_check_type (3, rs
,
18004 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18005 neon_three_same (neon_quad (rs
), 0, et
.size
);
18008 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
18009 same types as the MAC equivalents. The polynomial type for this instruction
18010 is encoded the same as the integer type. */
18015 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
18018 if (!check_simd_pred_availability (false, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18021 if (inst
.operands
[2].isscalar
)
18023 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18024 do_neon_mac_maybe_scalar ();
18028 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18030 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18031 struct neon_type_el et
18032 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
18033 if (et
.type
== NT_float
)
18034 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
18037 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
18041 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
18042 neon_dyadic_misc (NT_poly
,
18043 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
18049 do_neon_qdmulh (void)
18051 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18054 if (inst
.operands
[2].isscalar
)
18056 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18057 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18058 struct neon_type_el et
= neon_check_type (3, rs
,
18059 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18060 NEON_ENCODE (SCALAR
, inst
);
18061 neon_mul_mac (et
, neon_quad (rs
));
18065 enum neon_shape rs
;
18066 struct neon_type_el et
;
18067 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18069 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18070 et
= neon_check_type (3, rs
,
18071 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18075 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18076 et
= neon_check_type (3, rs
,
18077 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18080 NEON_ENCODE (INTEGER
, inst
);
18082 mve_encode_qqr (et
.size
, 0, 0);
18084 /* The U bit (rounding) comes from bit mask. */
18085 neon_three_same (neon_quad (rs
), 0, et
.size
);
18090 do_mve_vaddv (void)
18092 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18093 struct neon_type_el et
18094 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18096 if (et
.type
== NT_invtype
)
18097 first_error (BAD_EL_TYPE
);
18099 if (inst
.cond
> COND_ALWAYS
)
18100 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18102 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18104 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
18106 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18110 do_mve_vhcadd (void)
18112 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
18113 struct neon_type_el et
18114 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18116 if (inst
.cond
> COND_ALWAYS
)
18117 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18119 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18121 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
18122 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
18124 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
18125 as_tsktsk (_("Warning: 32-bit element size and same first and third "
18126 "operand makes instruction UNPREDICTABLE"));
18128 mve_encode_qqq (0, et
.size
);
18129 inst
.instruction
|= (rot
== 270) << 12;
18134 do_mve_vqdmull (void)
18136 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
18137 struct neon_type_el et
18138 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18141 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18142 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
18143 as_tsktsk (BAD_MVE_SRCDEST
);
18145 if (inst
.cond
> COND_ALWAYS
)
18146 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18148 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18152 mve_encode_qqq (et
.size
== 32, 64);
18153 inst
.instruction
|= 1;
18157 mve_encode_qqr (64, et
.size
== 32, 0);
18158 inst
.instruction
|= 0x3 << 5;
18165 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18166 struct neon_type_el et
18167 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
18169 if (et
.type
== NT_invtype
)
18170 first_error (BAD_EL_TYPE
);
18172 if (inst
.cond
> COND_ALWAYS
)
18173 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18175 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18177 mve_encode_qqq (0, 64);
18181 do_mve_vbrsr (void)
18183 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18184 struct neon_type_el et
18185 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18187 if (inst
.cond
> COND_ALWAYS
)
18188 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18190 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18192 mve_encode_qqr (et
.size
, 0, 0);
18198 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
18200 if (inst
.cond
> COND_ALWAYS
)
18201 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18203 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18205 mve_encode_qqq (1, 64);
18209 do_mve_vmulh (void)
18211 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18212 struct neon_type_el et
18213 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18215 if (inst
.cond
> COND_ALWAYS
)
18216 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18218 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18220 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18224 do_mve_vqdmlah (void)
18226 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18227 struct neon_type_el et
18228 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18230 if (inst
.cond
> COND_ALWAYS
)
18231 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18233 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18235 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18239 do_mve_vqdmladh (void)
18241 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18242 struct neon_type_el et
18243 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18245 if (inst
.cond
> COND_ALWAYS
)
18246 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18248 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18250 mve_encode_qqq (0, et
.size
);
18255 do_mve_vmull (void)
18258 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18259 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18260 if (inst
.cond
== COND_ALWAYS
18261 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18266 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18273 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18274 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18275 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18277 /* We are dealing with MVE's vmullt. */
18279 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18280 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18281 as_tsktsk (BAD_MVE_SRCDEST
);
18283 if (inst
.cond
> COND_ALWAYS
)
18284 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18286 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18288 if (et
.type
== NT_poly
)
18289 mve_encode_qqq (neon_logbits (et
.size
), 64);
18291 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18296 inst
.instruction
= N_MNEM_vmul
;
18299 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18304 do_mve_vabav (void)
18306 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18311 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18314 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18315 | N_S16
| N_S32
| N_U8
| N_U16
18318 if (inst
.cond
> COND_ALWAYS
)
18319 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18321 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18323 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18327 do_mve_vmladav (void)
18329 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18330 struct neon_type_el et
= neon_check_type (3, rs
,
18331 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18333 if (et
.type
== NT_unsigned
18334 && (inst
.instruction
== M_MNEM_vmladavx
18335 || inst
.instruction
== M_MNEM_vmladavax
18336 || inst
.instruction
== M_MNEM_vmlsdav
18337 || inst
.instruction
== M_MNEM_vmlsdava
18338 || inst
.instruction
== M_MNEM_vmlsdavx
18339 || inst
.instruction
== M_MNEM_vmlsdavax
))
18340 first_error (BAD_SIMD_TYPE
);
18342 constraint (inst
.operands
[2].reg
> 14,
18343 _("MVE vector register in the range [Q0..Q7] expected"));
18345 if (inst
.cond
> COND_ALWAYS
)
18346 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18348 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18350 if (inst
.instruction
== M_MNEM_vmlsdav
18351 || inst
.instruction
== M_MNEM_vmlsdava
18352 || inst
.instruction
== M_MNEM_vmlsdavx
18353 || inst
.instruction
== M_MNEM_vmlsdavax
)
18354 inst
.instruction
|= (et
.size
== 8) << 28;
18356 inst
.instruction
|= (et
.size
== 8) << 8;
18358 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18359 inst
.instruction
|= (et
.size
== 32) << 16;
18363 do_mve_vmlaldav (void)
18365 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18366 struct neon_type_el et
18367 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18368 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18370 if (et
.type
== NT_unsigned
18371 && (inst
.instruction
== M_MNEM_vmlsldav
18372 || inst
.instruction
== M_MNEM_vmlsldava
18373 || inst
.instruction
== M_MNEM_vmlsldavx
18374 || inst
.instruction
== M_MNEM_vmlsldavax
))
18375 first_error (BAD_SIMD_TYPE
);
18377 if (inst
.cond
> COND_ALWAYS
)
18378 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18380 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18382 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18386 do_mve_vrmlaldavh (void)
18388 struct neon_type_el et
;
18389 if (inst
.instruction
== M_MNEM_vrmlsldavh
18390 || inst
.instruction
== M_MNEM_vrmlsldavha
18391 || inst
.instruction
== M_MNEM_vrmlsldavhx
18392 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18394 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18395 if (inst
.operands
[1].reg
== REG_SP
)
18396 as_tsktsk (MVE_BAD_SP
);
18400 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18401 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18402 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18404 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18405 N_U32
| N_S32
| N_KEY
);
18406 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18407 with vmax/min instructions, making the use of SP in assembly really
18408 nonsensical, so instead of issuing a warning like we do for other uses
18409 of SP for the odd register operand we error out. */
18410 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18413 /* Make sure we still check the second operand is an odd one and that PC is
18414 disallowed. This because we are parsing for any GPR operand, to be able
18415 to distinguish between giving a warning or an error for SP as described
18417 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18418 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18420 if (inst
.cond
> COND_ALWAYS
)
18421 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18423 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18425 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18430 do_mve_vmaxnmv (void)
18432 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18433 struct neon_type_el et
18434 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18436 if (inst
.cond
> COND_ALWAYS
)
18437 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18439 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18441 if (inst
.operands
[0].reg
== REG_SP
)
18442 as_tsktsk (MVE_BAD_SP
);
18443 else if (inst
.operands
[0].reg
== REG_PC
)
18444 as_tsktsk (MVE_BAD_PC
);
18446 mve_encode_rq (et
.size
== 16, 64);
18450 do_mve_vmaxv (void)
18452 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18453 struct neon_type_el et
;
18455 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18456 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18458 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18460 if (inst
.cond
> COND_ALWAYS
)
18461 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18463 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18465 if (inst
.operands
[0].reg
== REG_SP
)
18466 as_tsktsk (MVE_BAD_SP
);
18467 else if (inst
.operands
[0].reg
== REG_PC
)
18468 as_tsktsk (MVE_BAD_PC
);
18470 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18475 do_neon_qrdmlah (void)
18477 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18479 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18481 /* Check we're on the correct architecture. */
18482 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18484 = _("instruction form not available on this architecture.");
18485 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18487 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18488 record_feature_use (&fpu_neon_ext_v8_1
);
18490 if (inst
.operands
[2].isscalar
)
18492 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18493 struct neon_type_el et
= neon_check_type (3, rs
,
18494 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18495 NEON_ENCODE (SCALAR
, inst
);
18496 neon_mul_mac (et
, neon_quad (rs
));
18500 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18501 struct neon_type_el et
= neon_check_type (3, rs
,
18502 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18503 NEON_ENCODE (INTEGER
, inst
);
18504 /* The U bit (rounding) comes from bit mask. */
18505 neon_three_same (neon_quad (rs
), 0, et
.size
);
18510 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18511 struct neon_type_el et
18512 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18514 NEON_ENCODE (INTEGER
, inst
);
18515 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18520 do_neon_fcmp_absolute (void)
18522 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18523 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18524 N_F_16_32
| N_KEY
);
18525 /* Size field comes from bit mask. */
18526 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18530 do_neon_fcmp_absolute_inv (void)
18532 neon_exchange_operands ();
18533 do_neon_fcmp_absolute ();
18537 do_neon_step (void)
18539 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18540 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18541 N_F_16_32
| N_KEY
);
18542 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18546 do_neon_abs_neg (void)
18548 enum neon_shape rs
;
18549 struct neon_type_el et
;
18551 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18554 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18555 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18557 if (!check_simd_pred_availability (et
.type
== NT_float
,
18558 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18561 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18562 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18563 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18564 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18565 inst
.instruction
|= neon_quad (rs
) << 6;
18566 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18567 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18569 neon_dp_fixup (&inst
);
18575 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18578 enum neon_shape rs
;
18579 struct neon_type_el et
;
18580 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18582 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18583 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18587 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18588 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18592 int imm
= inst
.operands
[2].imm
;
18593 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18594 _("immediate out of range for insert"));
18595 neon_imm_shift (false, 0, neon_quad (rs
), et
, imm
);
18601 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18604 enum neon_shape rs
;
18605 struct neon_type_el et
;
18606 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18608 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18609 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18613 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18614 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18617 int imm
= inst
.operands
[2].imm
;
18618 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18619 _("immediate out of range for insert"));
18620 neon_imm_shift (false, 0, neon_quad (rs
), et
, et
.size
- imm
);
18624 do_neon_qshlu_imm (void)
18626 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18629 enum neon_shape rs
;
18630 struct neon_type_el et
;
18631 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18633 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18634 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18638 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18639 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18640 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18643 int imm
= inst
.operands
[2].imm
;
18644 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18645 _("immediate out of range for shift"));
18646 /* Only encodes the 'U present' variant of the instruction.
18647 In this case, signed types have OP (bit 8) set to 0.
18648 Unsigned types have OP set to 1. */
18649 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18650 /* The rest of the bits are the same as other immediate shifts. */
18651 neon_imm_shift (false, 0, neon_quad (rs
), et
, imm
);
18655 do_neon_qmovn (void)
18657 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18658 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18659 /* Saturating move where operands can be signed or unsigned, and the
18660 destination has the same signedness. */
18661 NEON_ENCODE (INTEGER
, inst
);
18662 if (et
.type
== NT_unsigned
)
18663 inst
.instruction
|= 0xc0;
18665 inst
.instruction
|= 0x80;
18666 neon_two_same (0, 1, et
.size
/ 2);
18670 do_neon_qmovun (void)
18672 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18673 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18674 /* Saturating move with unsigned results. Operands must be signed. */
18675 NEON_ENCODE (INTEGER
, inst
);
18676 neon_two_same (0, 1, et
.size
/ 2);
18680 do_neon_rshift_sat_narrow (void)
18682 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18683 or unsigned. If operands are unsigned, results must also be unsigned. */
18684 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18685 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18686 int imm
= inst
.operands
[2].imm
;
18687 /* This gets the bounds check, size encoding and immediate bits calculation
18691 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18692 VQMOVN.I<size> <Dd>, <Qm>. */
18695 inst
.operands
[2].present
= 0;
18696 inst
.instruction
= N_MNEM_vqmovn
;
18701 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18702 _("immediate out of range"));
18703 neon_imm_shift (true, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18707 do_neon_rshift_sat_narrow_u (void)
18709 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18710 or unsigned. If operands are unsigned, results must also be unsigned. */
18711 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18712 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18713 int imm
= inst
.operands
[2].imm
;
18714 /* This gets the bounds check, size encoding and immediate bits calculation
18718 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18719 VQMOVUN.I<size> <Dd>, <Qm>. */
18722 inst
.operands
[2].present
= 0;
18723 inst
.instruction
= N_MNEM_vqmovun
;
18728 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18729 _("immediate out of range"));
18730 /* FIXME: The manual is kind of unclear about what value U should have in
18731 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18733 neon_imm_shift (true, 1, 0, et
, et
.size
- imm
);
18737 do_neon_movn (void)
18739 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18740 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18741 NEON_ENCODE (INTEGER
, inst
);
18742 neon_two_same (0, 1, et
.size
/ 2);
18746 do_neon_rshift_narrow (void)
18748 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18749 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18750 int imm
= inst
.operands
[2].imm
;
18751 /* This gets the bounds check, size encoding and immediate bits calculation
18755 /* If immediate is zero then we are a pseudo-instruction for
18756 VMOVN.I<size> <Dd>, <Qm> */
18759 inst
.operands
[2].present
= 0;
18760 inst
.instruction
= N_MNEM_vmovn
;
18765 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18766 _("immediate out of range for narrowing operation"));
18767 neon_imm_shift (false, 0, 0, et
, et
.size
- imm
);
18771 do_neon_shll (void)
18773 /* FIXME: Type checking when lengthening. */
18774 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18775 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18776 unsigned imm
= inst
.operands
[2].imm
;
18778 if (imm
== et
.size
)
18780 /* Maximum shift variant. */
18781 NEON_ENCODE (INTEGER
, inst
);
18782 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18783 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18784 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18785 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18786 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18788 neon_dp_fixup (&inst
);
18792 /* A more-specific type check for non-max versions. */
18793 et
= neon_check_type (2, NS_QDI
,
18794 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18795 NEON_ENCODE (IMMED
, inst
);
18796 neon_imm_shift (true, et
.type
== NT_unsigned
, 0, et
, imm
);
18800 /* Check the various types for the VCVT instruction, and return which version
18801 the current instruction is. */
18803 #define CVT_FLAVOUR_VAR \
18804 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18805 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18806 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18807 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18808 /* Half-precision conversions. */ \
18809 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18810 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18811 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18812 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18813 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18814 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18815 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18816 Compared with single/double precision variants, only the co-processor \
18817 field is different, so the encoding flow is reused here. */ \
18818 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18819 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18820 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18821 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18822 CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg, NULL, NULL, NULL) \
18823 /* VFP instructions. */ \
18824 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18825 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18826 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18827 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18828 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18829 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18830 /* VFP instructions with bitshift. */ \
18831 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18832 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18833 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18834 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18835 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18836 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18837 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18838 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18840 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18841 neon_cvt_flavour_##C,
18843 /* The different types of conversions we can do. */
18844 enum neon_cvt_flavour
18847 neon_cvt_flavour_invalid
,
18848 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18853 static enum neon_cvt_flavour
18854 get_neon_cvt_flavour (enum neon_shape rs
)
18856 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18857 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18858 if (et.type != NT_invtype) \
18860 inst.error = NULL; \
18861 return (neon_cvt_flavour_##C); \
18864 struct neon_type_el et
;
18865 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18866 || rs
== NS_FF
) ? N_VFP
: 0;
18867 /* The instruction versions which take an immediate take one register
18868 argument, which is extended to the width of the full register. Thus the
18869 "source" and "destination" registers must have the same width. Hack that
18870 here by making the size equal to the key (wider, in this case) operand. */
18871 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18875 return neon_cvt_flavour_invalid
;
18890 /* Neon-syntax VFP conversions. */
18893 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18895 const char *opname
= 0;
18897 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18898 || rs
== NS_FHI
|| rs
== NS_HFI
)
18900 /* Conversions with immediate bitshift. */
18901 const char *enc
[] =
18903 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18909 if (flavour
< (int) ARRAY_SIZE (enc
))
18911 opname
= enc
[flavour
];
18912 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18913 _("operands 0 and 1 must be the same register"));
18914 inst
.operands
[1] = inst
.operands
[2];
18915 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18920 /* Conversions without bitshift. */
18921 const char *enc
[] =
18923 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18929 if (flavour
< (int) ARRAY_SIZE (enc
))
18930 opname
= enc
[flavour
];
18934 do_vfp_nsyn_opcode (opname
);
18936 /* ARMv8.2 fp16 VCVT instruction. */
18937 if (flavour
== neon_cvt_flavour_s32_f16
18938 || flavour
== neon_cvt_flavour_u32_f16
18939 || flavour
== neon_cvt_flavour_f16_u32
18940 || flavour
== neon_cvt_flavour_f16_s32
)
18941 do_scalar_fp16_v82_encode ();
18945 do_vfp_nsyn_cvtz (void)
18947 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18948 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18949 const char *enc
[] =
18951 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18957 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18958 do_vfp_nsyn_opcode (enc
[flavour
]);
18962 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18963 enum neon_cvt_mode mode
)
18968 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18969 D register operands. */
18970 if (flavour
== neon_cvt_flavour_s32_f64
18971 || flavour
== neon_cvt_flavour_u32_f64
)
18972 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18975 if (flavour
== neon_cvt_flavour_s32_f16
18976 || flavour
== neon_cvt_flavour_u32_f16
)
18977 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18980 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18984 case neon_cvt_flavour_s32_f64
:
18988 case neon_cvt_flavour_s32_f32
:
18992 case neon_cvt_flavour_s32_f16
:
18996 case neon_cvt_flavour_u32_f64
:
19000 case neon_cvt_flavour_u32_f32
:
19004 case neon_cvt_flavour_u32_f16
:
19009 first_error (_("invalid instruction shape"));
19015 case neon_cvt_mode_a
: rm
= 0; break;
19016 case neon_cvt_mode_n
: rm
= 1; break;
19017 case neon_cvt_mode_p
: rm
= 2; break;
19018 case neon_cvt_mode_m
: rm
= 3; break;
19019 default: first_error (_("invalid rounding mode")); return;
19022 NEON_ENCODE (FPV8
, inst
);
19023 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
19024 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
19025 inst
.instruction
|= sz
<< 8;
19027 /* ARMv8.2 fp16 VCVT instruction. */
19028 if (flavour
== neon_cvt_flavour_s32_f16
19029 ||flavour
== neon_cvt_flavour_u32_f16
)
19030 do_scalar_fp16_v82_encode ();
19031 inst
.instruction
|= op
<< 7;
19032 inst
.instruction
|= rm
<< 16;
19033 inst
.instruction
|= 0xf0000000;
19034 inst
.is_neon
= true;
19038 do_neon_cvt_1 (enum neon_cvt_mode mode
)
19040 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
19041 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
19042 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
19044 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19046 if (flavour
== neon_cvt_flavour_invalid
)
19049 /* PR11109: Handle round-to-zero for VCVT conversions. */
19050 if (mode
== neon_cvt_mode_z
19051 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
19052 && (flavour
== neon_cvt_flavour_s16_f16
19053 || flavour
== neon_cvt_flavour_u16_f16
19054 || flavour
== neon_cvt_flavour_s32_f32
19055 || flavour
== neon_cvt_flavour_u32_f32
19056 || flavour
== neon_cvt_flavour_s32_f64
19057 || flavour
== neon_cvt_flavour_u32_f64
)
19058 && (rs
== NS_FD
|| rs
== NS_FF
))
19060 do_vfp_nsyn_cvtz ();
19064 /* ARMv8.2 fp16 VCVT conversions. */
19065 if (mode
== neon_cvt_mode_z
19066 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
19067 && (flavour
== neon_cvt_flavour_s32_f16
19068 || flavour
== neon_cvt_flavour_u32_f16
)
19071 do_vfp_nsyn_cvtz ();
19072 do_scalar_fp16_v82_encode ();
19076 if ((rs
== NS_FD
|| rs
== NS_QQI
) && mode
== neon_cvt_mode_n
19077 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19079 /* We are dealing with vcvt with the 'ne' condition. */
19081 inst
.instruction
= N_MNEM_vcvt
;
19082 do_neon_cvt_1 (neon_cvt_mode_z
);
19086 /* VFP rather than Neon conversions. */
19087 if (flavour
>= neon_cvt_flavour_first_fp
)
19089 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19090 do_vfp_nsyn_cvt (rs
, flavour
);
19092 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19100 if (mode
== neon_cvt_mode_z
19101 && (flavour
== neon_cvt_flavour_f16_s16
19102 || flavour
== neon_cvt_flavour_f16_u16
19103 || flavour
== neon_cvt_flavour_s16_f16
19104 || flavour
== neon_cvt_flavour_u16_f16
19105 || flavour
== neon_cvt_flavour_f32_u32
19106 || flavour
== neon_cvt_flavour_f32_s32
19107 || flavour
== neon_cvt_flavour_s32_f32
19108 || flavour
== neon_cvt_flavour_u32_f32
))
19110 if (!check_simd_pred_availability (true,
19111 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19114 /* fall through. */
19118 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19119 0x0000100, 0x1000100, 0x0, 0x1000000};
19121 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19122 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19125 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19127 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
19128 _("immediate value out of range"));
19131 case neon_cvt_flavour_f16_s16
:
19132 case neon_cvt_flavour_f16_u16
:
19133 case neon_cvt_flavour_s16_f16
:
19134 case neon_cvt_flavour_u16_f16
:
19135 constraint (inst
.operands
[2].imm
> 16,
19136 _("immediate value out of range"));
19138 case neon_cvt_flavour_f32_u32
:
19139 case neon_cvt_flavour_f32_s32
:
19140 case neon_cvt_flavour_s32_f32
:
19141 case neon_cvt_flavour_u32_f32
:
19142 constraint (inst
.operands
[2].imm
> 32,
19143 _("immediate value out of range"));
19146 inst
.error
= BAD_FPU
;
19151 /* Fixed-point conversion with #0 immediate is encoded as an
19152 integer conversion. */
19153 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
19155 NEON_ENCODE (IMMED
, inst
);
19156 if (flavour
!= neon_cvt_flavour_invalid
)
19157 inst
.instruction
|= enctab
[flavour
];
19158 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19159 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19160 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19161 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19162 inst
.instruction
|= neon_quad (rs
) << 6;
19163 inst
.instruction
|= 1 << 21;
19164 if (flavour
< neon_cvt_flavour_s16_f16
)
19166 inst
.instruction
|= 1 << 21;
19167 immbits
= 32 - inst
.operands
[2].imm
;
19168 inst
.instruction
|= immbits
<< 16;
19172 inst
.instruction
|= 3 << 20;
19173 immbits
= 16 - inst
.operands
[2].imm
;
19174 inst
.instruction
|= immbits
<< 16;
19175 inst
.instruction
&= ~(1 << 9);
19178 neon_dp_fixup (&inst
);
19183 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19184 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
19185 && (flavour
== neon_cvt_flavour_s16_f16
19186 || flavour
== neon_cvt_flavour_u16_f16
19187 || flavour
== neon_cvt_flavour_s32_f32
19188 || flavour
== neon_cvt_flavour_u32_f32
))
19190 if (!check_simd_pred_availability (true,
19191 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19194 else if (mode
== neon_cvt_mode_z
19195 && (flavour
== neon_cvt_flavour_f16_s16
19196 || flavour
== neon_cvt_flavour_f16_u16
19197 || flavour
== neon_cvt_flavour_s16_f16
19198 || flavour
== neon_cvt_flavour_u16_f16
19199 || flavour
== neon_cvt_flavour_f32_u32
19200 || flavour
== neon_cvt_flavour_f32_s32
19201 || flavour
== neon_cvt_flavour_s32_f32
19202 || flavour
== neon_cvt_flavour_u32_f32
))
19204 if (!check_simd_pred_availability (true,
19205 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19208 /* fall through. */
19210 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
19213 NEON_ENCODE (FLOAT
, inst
);
19214 if (!check_simd_pred_availability (true,
19215 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19218 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19219 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19220 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19221 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19222 inst
.instruction
|= neon_quad (rs
) << 6;
19223 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19224 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19225 inst
.instruction
|= mode
<< 8;
19226 if (flavour
== neon_cvt_flavour_u16_f16
19227 || flavour
== neon_cvt_flavour_s16_f16
)
19228 /* Mask off the original size bits and reencode them. */
19229 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19232 inst
.instruction
|= 0xfc000000;
19234 inst
.instruction
|= 0xf0000000;
19240 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19241 0x100, 0x180, 0x0, 0x080};
19243 NEON_ENCODE (INTEGER
, inst
);
19245 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19247 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19251 if (flavour
!= neon_cvt_flavour_invalid
)
19252 inst
.instruction
|= enctab
[flavour
];
19254 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19255 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19256 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19257 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19258 inst
.instruction
|= neon_quad (rs
) << 6;
19259 if (flavour
>= neon_cvt_flavour_s16_f16
19260 && flavour
<= neon_cvt_flavour_f16_u16
)
19261 /* Half precision. */
19262 inst
.instruction
|= 1 << 18;
19264 inst
.instruction
|= 2 << 18;
19266 neon_dp_fixup (&inst
);
19271 /* Half-precision conversions for Advanced SIMD -- neon. */
19274 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19278 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19280 as_bad (_("operand size must match register width"));
19285 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19287 as_bad (_("operand size must match register width"));
19293 if (flavour
== neon_cvt_flavour_bf16_f32
)
19295 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8
) == FAIL
)
19297 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19298 /* VCVT.bf16.f32. */
19299 inst
.instruction
= 0x11b60640;
19302 /* VCVT.f16.f32. */
19303 inst
.instruction
= 0x3b60600;
19306 /* VCVT.f32.f16. */
19307 inst
.instruction
= 0x3b60700;
19309 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19310 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19311 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19312 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19313 neon_dp_fixup (&inst
);
19317 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19318 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19319 do_vfp_nsyn_cvt (rs
, flavour
);
19321 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19326 do_neon_cvtr (void)
19328 do_neon_cvt_1 (neon_cvt_mode_x
);
19334 do_neon_cvt_1 (neon_cvt_mode_z
);
19338 do_neon_cvta (void)
19340 do_neon_cvt_1 (neon_cvt_mode_a
);
19344 do_neon_cvtn (void)
19346 do_neon_cvt_1 (neon_cvt_mode_n
);
19350 do_neon_cvtp (void)
19352 do_neon_cvt_1 (neon_cvt_mode_p
);
19356 do_neon_cvtm (void)
19358 do_neon_cvt_1 (neon_cvt_mode_m
);
19362 do_neon_cvttb_2 (bool t
, bool to
, bool is_double
)
19365 mark_feature_used (&fpu_vfp_ext_armv8
);
19367 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19368 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19369 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19370 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19371 inst
.instruction
|= to
? 0x10000 : 0;
19372 inst
.instruction
|= t
? 0x80 : 0;
19373 inst
.instruction
|= is_double
? 0x100 : 0;
19374 do_vfp_cond_or_thumb ();
19378 do_neon_cvttb_1 (bool t
)
19380 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19381 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19385 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19387 int single_to_half
= 0;
19388 if (!check_simd_pred_availability (true, NEON_CHECK_ARCH
))
19391 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19393 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19394 && (flavour
== neon_cvt_flavour_u16_f16
19395 || flavour
== neon_cvt_flavour_s16_f16
19396 || flavour
== neon_cvt_flavour_f16_s16
19397 || flavour
== neon_cvt_flavour_f16_u16
19398 || flavour
== neon_cvt_flavour_u32_f32
19399 || flavour
== neon_cvt_flavour_s32_f32
19400 || flavour
== neon_cvt_flavour_f32_s32
19401 || flavour
== neon_cvt_flavour_f32_u32
))
19404 inst
.instruction
= N_MNEM_vcvt
;
19405 set_pred_insn_type (INSIDE_VPT_INSN
);
19406 do_neon_cvt_1 (neon_cvt_mode_z
);
19409 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19410 single_to_half
= 1;
19411 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19413 first_error (BAD_FPU
);
19417 inst
.instruction
= 0xee3f0e01;
19418 inst
.instruction
|= single_to_half
<< 28;
19419 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19420 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19421 inst
.instruction
|= t
<< 12;
19422 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19423 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19426 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19429 do_neon_cvttb_2 (t
, /*to=*/true, /*is_double=*/false);
19431 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19434 do_neon_cvttb_2 (t
, /*to=*/false, /*is_double=*/false);
19436 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19438 /* The VCVTB and VCVTT instructions with D-register operands
19439 don't work for SP only targets. */
19440 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19444 do_neon_cvttb_2 (t
, /*to=*/true, /*is_double=*/true);
19446 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19448 /* The VCVTB and VCVTT instructions with D-register operands
19449 don't work for SP only targets. */
19450 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19454 do_neon_cvttb_2 (t
, /*to=*/false, /*is_double=*/true);
19456 else if (neon_check_type (2, rs
, N_BF16
| N_VFP
, N_F32
).type
!= NT_invtype
)
19458 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19460 inst
.instruction
|= (1 << 8);
19461 inst
.instruction
&= ~(1 << 9);
19462 do_neon_cvttb_2 (t
, /*to=*/true, /*is_double=*/false);
19469 do_neon_cvtb (void)
19471 do_neon_cvttb_1 (false);
19476 do_neon_cvtt (void)
19478 do_neon_cvttb_1 (true);
19482 neon_move_immediate (void)
19484 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19485 struct neon_type_el et
= neon_check_type (2, rs
,
19486 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19487 unsigned immlo
, immhi
= 0, immbits
;
19488 int op
, cmode
, float_p
;
19490 constraint (et
.type
== NT_invtype
,
19491 _("operand size must be specified for immediate VMOV"));
19493 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19494 op
= (inst
.instruction
& (1 << 5)) != 0;
19496 immlo
= inst
.operands
[1].imm
;
19497 if (inst
.operands
[1].regisimm
)
19498 immhi
= inst
.operands
[1].reg
;
19500 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19501 _("immediate has bits set outside the operand size"));
19503 float_p
= inst
.operands
[1].immisfloat
;
19505 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19506 et
.size
, et
.type
)) == FAIL
)
19508 /* Invert relevant bits only. */
19509 neon_invert_size (&immlo
, &immhi
, et
.size
);
19510 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19511 with one or the other; those cases are caught by
19512 neon_cmode_for_move_imm. */
19514 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19515 &op
, et
.size
, et
.type
)) == FAIL
)
19517 first_error (_("immediate out of range"));
19522 inst
.instruction
&= ~(1 << 5);
19523 inst
.instruction
|= op
<< 5;
19525 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19526 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19527 inst
.instruction
|= neon_quad (rs
) << 6;
19528 inst
.instruction
|= cmode
<< 8;
19530 neon_write_immbits (immbits
);
19536 if (!check_simd_pred_availability (false, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19539 if (inst
.operands
[1].isreg
)
19541 enum neon_shape rs
;
19542 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19543 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19545 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19550 NEON_ENCODE (INTEGER
, inst
);
19551 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19552 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19553 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19554 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19555 inst
.instruction
|= neon_quad (rs
) << 6;
19559 NEON_ENCODE (IMMED
, inst
);
19560 neon_move_immediate ();
19563 neon_dp_fixup (&inst
);
19565 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19567 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19571 /* Encode instructions of form:
19573 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19574 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19577 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19579 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19580 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19581 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19582 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19583 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19584 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19585 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19586 inst
.instruction
|= neon_logbits (size
) << 20;
19588 neon_dp_fixup (&inst
);
19592 do_neon_dyadic_long (void)
19594 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
19597 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19600 NEON_ENCODE (INTEGER
, inst
);
19601 /* FIXME: Type checking for lengthening op. */
19602 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19603 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19604 neon_mixed_length (et
, et
.size
);
19606 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19607 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19609 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19610 in an IT block with le/lt conditions. */
19612 if (inst
.cond
== 0xf)
19614 else if (inst
.cond
== 0x10)
19617 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19619 if (inst
.instruction
== N_MNEM_vaddl
)
19621 inst
.instruction
= N_MNEM_vadd
;
19622 do_neon_addsub_if_i ();
19624 else if (inst
.instruction
== N_MNEM_vsubl
)
19626 inst
.instruction
= N_MNEM_vsub
;
19627 do_neon_addsub_if_i ();
19629 else if (inst
.instruction
== N_MNEM_vabdl
)
19631 inst
.instruction
= N_MNEM_vabd
;
19632 do_neon_dyadic_if_su ();
19636 first_error (BAD_FPU
);
19640 do_neon_abal (void)
19642 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19643 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19644 neon_mixed_length (et
, et
.size
);
19648 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19650 if (inst
.operands
[2].isscalar
)
19652 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19653 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19654 NEON_ENCODE (SCALAR
, inst
);
19655 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19659 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19660 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19661 NEON_ENCODE (INTEGER
, inst
);
19662 neon_mixed_length (et
, et
.size
);
19667 do_neon_mac_maybe_scalar_long (void)
19669 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19672 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19673 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19676 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19678 unsigned regno
= NEON_SCALAR_REG (scalar
);
19679 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19683 if (regno
> 7 || elno
> 3)
19686 return ((regno
& 0x7)
19687 | ((elno
& 0x1) << 3)
19688 | (((elno
>> 1) & 0x1) << 5));
19692 if (regno
> 15 || elno
> 1)
19695 return (((regno
& 0x1) << 5)
19696 | ((regno
>> 1) & 0x7)
19697 | ((elno
& 0x1) << 3));
19701 first_error (_("scalar out of range for multiply instruction"));
19706 do_neon_fmac_maybe_scalar_long (int subtype
)
19708 enum neon_shape rs
;
19710 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19711 field (bits[21:20]) has different meaning. For scalar index variant, it's
19712 used to differentiate add and subtract, otherwise it's with fixed value
19716 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19717 be a scalar index register. */
19718 if (inst
.operands
[2].isscalar
)
19720 high8
= 0xfe000000;
19723 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19727 high8
= 0xfc000000;
19730 inst
.instruction
|= (0x1 << 23);
19731 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19735 if (inst
.cond
!= COND_ALWAYS
)
19736 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19737 "behaviour is UNPREDICTABLE"));
19739 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19742 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19745 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19746 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19747 so we simply pass -1 as size. */
19748 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19749 neon_three_same (quad_p
, 0, size
);
19751 /* Undo neon_dp_fixup. Redo the high eight bits. */
19752 inst
.instruction
&= 0x00ffffff;
19753 inst
.instruction
|= high8
;
19755 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19756 whether the instruction is in Q form and whether Vm is a scalar indexed
19758 if (inst
.operands
[2].isscalar
)
19761 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19762 inst
.instruction
&= 0xffffffd0;
19763 inst
.instruction
|= rm
;
19767 /* Redo Rn as well. */
19768 inst
.instruction
&= 0xfff0ff7f;
19769 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19770 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19775 /* Redo Rn and Rm. */
19776 inst
.instruction
&= 0xfff0ff50;
19777 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19778 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19779 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19780 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19785 do_neon_vfmal (void)
19787 return do_neon_fmac_maybe_scalar_long (0);
19791 do_neon_vfmsl (void)
19793 return do_neon_fmac_maybe_scalar_long (1);
19797 do_neon_dyadic_wide (void)
19799 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19800 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19801 neon_mixed_length (et
, et
.size
);
19805 do_neon_dyadic_narrow (void)
19807 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19808 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19809 /* Operand sign is unimportant, and the U bit is part of the opcode,
19810 so force the operand type to integer. */
19811 et
.type
= NT_integer
;
19812 neon_mixed_length (et
, et
.size
/ 2);
19816 do_neon_mul_sat_scalar_long (void)
19818 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19822 do_neon_vmull (void)
19824 if (inst
.operands
[2].isscalar
)
19825 do_neon_mac_maybe_scalar_long ();
19828 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19829 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19831 if (et
.type
== NT_poly
)
19832 NEON_ENCODE (POLY
, inst
);
19834 NEON_ENCODE (INTEGER
, inst
);
19836 /* For polynomial encoding the U bit must be zero, and the size must
19837 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19838 obviously, as 0b10). */
19841 /* Check we're on the correct architecture. */
19842 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19844 _("Instruction form not available on this architecture.");
19849 neon_mixed_length (et
, et
.size
);
19856 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19857 struct neon_type_el et
= neon_check_type (3, rs
,
19858 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19859 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19861 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19862 _("shift out of range"));
19863 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19864 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19865 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19866 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19867 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19868 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19869 inst
.instruction
|= neon_quad (rs
) << 6;
19870 inst
.instruction
|= imm
<< 8;
19872 neon_dp_fixup (&inst
);
19878 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19881 enum neon_shape rs
;
19882 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19883 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19885 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19887 struct neon_type_el et
= neon_check_type (2, rs
,
19888 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19890 unsigned op
= (inst
.instruction
>> 7) & 3;
19891 /* N (width of reversed regions) is encoded as part of the bitmask. We
19892 extract it here to check the elements to be reversed are smaller.
19893 Otherwise we'd get a reserved instruction. */
19894 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19896 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19897 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19898 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19899 " operands makes instruction UNPREDICTABLE"));
19901 gas_assert (elsize
!= 0);
19902 constraint (et
.size
>= elsize
,
19903 _("elements must be smaller than reversal region"));
19904 neon_two_same (neon_quad (rs
), 1, et
.size
);
19910 if (inst
.operands
[1].isscalar
)
19912 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19914 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19915 struct neon_type_el et
= neon_check_type (2, rs
,
19916 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19917 unsigned sizebits
= et
.size
>> 3;
19918 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19919 int logsize
= neon_logbits (et
.size
);
19920 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19922 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19925 NEON_ENCODE (SCALAR
, inst
);
19926 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19927 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19928 inst
.instruction
|= LOW4 (dm
);
19929 inst
.instruction
|= HI1 (dm
) << 5;
19930 inst
.instruction
|= neon_quad (rs
) << 6;
19931 inst
.instruction
|= x
<< 17;
19932 inst
.instruction
|= sizebits
<< 16;
19934 neon_dp_fixup (&inst
);
19938 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19939 struct neon_type_el et
= neon_check_type (2, rs
,
19940 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19943 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
))
19947 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19950 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19952 if (inst
.operands
[1].reg
== REG_SP
)
19953 as_tsktsk (MVE_BAD_SP
);
19954 else if (inst
.operands
[1].reg
== REG_PC
)
19955 as_tsktsk (MVE_BAD_PC
);
19958 /* Duplicate ARM register to lanes of vector. */
19959 NEON_ENCODE (ARMREG
, inst
);
19962 case 8: inst
.instruction
|= 0x400000; break;
19963 case 16: inst
.instruction
|= 0x000020; break;
19964 case 32: inst
.instruction
|= 0x000000; break;
19967 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19968 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19969 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19970 inst
.instruction
|= neon_quad (rs
) << 21;
19971 /* The encoding for this instruction is identical for the ARM and Thumb
19972 variants, except for the condition field. */
19973 do_vfp_cond_or_thumb ();
19978 do_mve_mov (int toQ
)
19980 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19982 if (inst
.cond
> COND_ALWAYS
)
19983 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19985 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19994 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19995 _("Index one must be [2,3] and index two must be two less than"
19997 constraint (!toQ
&& inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19998 _("Destination registers may not be the same"));
19999 constraint (inst
.operands
[Rt
].reg
== REG_SP
20000 || inst
.operands
[Rt2
].reg
== REG_SP
,
20002 constraint (inst
.operands
[Rt
].reg
== REG_PC
20003 || inst
.operands
[Rt2
].reg
== REG_PC
,
20006 inst
.instruction
= 0xec000f00;
20007 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
20008 inst
.instruction
|= !!toQ
<< 20;
20009 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
20010 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
20011 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
20012 inst
.instruction
|= inst
.operands
[Rt
].reg
;
20018 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20021 if (inst
.cond
> COND_ALWAYS
)
20022 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20024 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
20026 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
20029 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20030 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
20031 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20032 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20033 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20038 /* VMOV has particularly many variations. It can be one of:
20039 0. VMOV<c><q> <Qd>, <Qm>
20040 1. VMOV<c><q> <Dd>, <Dm>
20041 (Register operations, which are VORR with Rm = Rn.)
20042 2. VMOV<c><q>.<dt> <Qd>, #<imm>
20043 3. VMOV<c><q>.<dt> <Dd>, #<imm>
20045 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
20046 (ARM register to scalar.)
20047 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
20048 (Two ARM registers to vector.)
20049 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
20050 (Scalar to ARM register.)
20051 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
20052 (Vector to two ARM registers.)
20053 8. VMOV.F32 <Sd>, <Sm>
20054 9. VMOV.F64 <Dd>, <Dm>
20055 (VFP register moves.)
20056 10. VMOV.F32 <Sd>, #imm
20057 11. VMOV.F64 <Dd>, #imm
20058 (VFP float immediate load.)
20059 12. VMOV <Rd>, <Sm>
20060 (VFP single to ARM reg.)
20061 13. VMOV <Sd>, <Rm>
20062 (ARM reg to VFP single.)
20063 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20064 (Two ARM regs to two VFP singles.)
20065 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20066 (Two VFP singles to two ARM regs.)
20067 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20068 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20069 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20070 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
20072 These cases can be disambiguated using neon_select_shape, except cases 1/9
20073 and 3/11 which depend on the operand type too.
20075 All the encoded bits are hardcoded by this function.
20077 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20078 Cases 5, 7 may be used with VFPv2 and above.
20080 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
20081 can specify a type where it doesn't make sense to, and is ignored). */
20086 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
20087 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
20088 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
20089 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
20091 struct neon_type_el et
;
20092 const char *ldconst
= 0;
20096 case NS_DD
: /* case 1/9. */
20097 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20098 /* It is not an error here if no type is given. */
20101 /* In MVE we interpret the following instructions as same, so ignoring
20102 the following type (float) and size (64) checks.
20103 a: VMOV<c><q> <Dd>, <Dm>
20104 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
20105 if ((et
.type
== NT_float
&& et
.size
== 64)
20106 || (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
20108 do_vfp_nsyn_opcode ("fcpyd");
20111 /* fall through. */
20113 case NS_QQ
: /* case 0/1. */
20115 if (!check_simd_pred_availability (false,
20116 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20118 /* The architecture manual I have doesn't explicitly state which
20119 value the U bit should have for register->register moves, but
20120 the equivalent VORR instruction has U = 0, so do that. */
20121 inst
.instruction
= 0x0200110;
20122 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20123 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20124 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20125 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20126 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20127 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20128 inst
.instruction
|= neon_quad (rs
) << 6;
20130 neon_dp_fixup (&inst
);
20134 case NS_DI
: /* case 3/11. */
20135 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20137 if (et
.type
== NT_float
&& et
.size
== 64)
20139 /* case 11 (fconstd). */
20140 ldconst
= "fconstd";
20141 goto encode_fconstd
;
20143 /* fall through. */
20145 case NS_QI
: /* case 2/3. */
20146 if (!check_simd_pred_availability (false,
20147 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20149 inst
.instruction
= 0x0800010;
20150 neon_move_immediate ();
20151 neon_dp_fixup (&inst
);
20154 case NS_SR
: /* case 4. */
20156 unsigned bcdebits
= 0;
20158 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
20159 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
20161 /* .<size> is optional here, defaulting to .32. */
20162 if (inst
.vectype
.elems
== 0
20163 && inst
.operands
[0].vectype
.type
== NT_invtype
20164 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20166 inst
.vectype
.el
[0].type
= NT_untyped
;
20167 inst
.vectype
.el
[0].size
= 32;
20168 inst
.vectype
.elems
= 1;
20171 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
20172 logsize
= neon_logbits (et
.size
);
20176 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20177 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
20182 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20183 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20187 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20189 if (inst
.operands
[1].reg
== REG_SP
)
20190 as_tsktsk (MVE_BAD_SP
);
20191 else if (inst
.operands
[1].reg
== REG_PC
)
20192 as_tsktsk (MVE_BAD_PC
);
20194 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
20196 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20197 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20202 case 8: bcdebits
= 0x8; break;
20203 case 16: bcdebits
= 0x1; break;
20204 case 32: bcdebits
= 0x0; break;
20208 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20210 inst
.instruction
= 0xe000b10;
20211 do_vfp_cond_or_thumb ();
20212 inst
.instruction
|= LOW4 (dn
) << 16;
20213 inst
.instruction
|= HI1 (dn
) << 7;
20214 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20215 inst
.instruction
|= (bcdebits
& 3) << 5;
20216 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
20217 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20221 case NS_DRR
: /* case 5 (fmdrr). */
20222 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20223 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20226 inst
.instruction
= 0xc400b10;
20227 do_vfp_cond_or_thumb ();
20228 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
20229 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
20230 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20231 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
20234 case NS_RS
: /* case 6. */
20237 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
20238 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
20239 unsigned abcdebits
= 0;
20241 /* .<dt> is optional here, defaulting to .32. */
20242 if (inst
.vectype
.elems
== 0
20243 && inst
.operands
[0].vectype
.type
== NT_invtype
20244 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20246 inst
.vectype
.el
[0].type
= NT_untyped
;
20247 inst
.vectype
.el
[0].size
= 32;
20248 inst
.vectype
.elems
= 1;
20251 et
= neon_check_type (2, NS_NULL
,
20252 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20253 logsize
= neon_logbits (et
.size
);
20257 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20258 && vfp_or_neon_is_neon (NEON_CHECK_CC
20259 | NEON_CHECK_ARCH
) == FAIL
)
20264 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20265 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20269 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20271 if (inst
.operands
[0].reg
== REG_SP
)
20272 as_tsktsk (MVE_BAD_SP
);
20273 else if (inst
.operands
[0].reg
== REG_PC
)
20274 as_tsktsk (MVE_BAD_PC
);
20277 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20279 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20280 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20284 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20285 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20286 case 32: abcdebits
= 0x00; break;
20290 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20291 inst
.instruction
= 0xe100b10;
20292 do_vfp_cond_or_thumb ();
20293 inst
.instruction
|= LOW4 (dn
) << 16;
20294 inst
.instruction
|= HI1 (dn
) << 7;
20295 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20296 inst
.instruction
|= (abcdebits
& 3) << 5;
20297 inst
.instruction
|= (abcdebits
>> 2) << 21;
20298 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20302 case NS_RRD
: /* case 7 (fmrrd). */
20303 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20304 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20307 inst
.instruction
= 0xc500b10;
20308 do_vfp_cond_or_thumb ();
20309 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20310 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20311 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20312 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20315 case NS_FF
: /* case 8 (fcpys). */
20316 do_vfp_nsyn_opcode ("fcpys");
20320 case NS_FI
: /* case 10 (fconsts). */
20321 ldconst
= "fconsts";
20323 if (!inst
.operands
[1].immisfloat
)
20326 /* Immediate has to fit in 8 bits so float is enough. */
20327 float imm
= (float) inst
.operands
[1].imm
;
20328 memcpy (&new_imm
, &imm
, sizeof (float));
20329 /* But the assembly may have been written to provide an integer
20330 bit pattern that equates to a float, so check that the
20331 conversion has worked. */
20332 if (is_quarter_float (new_imm
))
20334 if (is_quarter_float (inst
.operands
[1].imm
))
20335 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20337 inst
.operands
[1].imm
= new_imm
;
20338 inst
.operands
[1].immisfloat
= 1;
20342 if (is_quarter_float (inst
.operands
[1].imm
))
20344 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20345 do_vfp_nsyn_opcode (ldconst
);
20347 /* ARMv8.2 fp16 vmov.f16 instruction. */
20349 do_scalar_fp16_v82_encode ();
20352 first_error (_("immediate out of range"));
20356 case NS_RF
: /* case 12 (fmrs). */
20357 do_vfp_nsyn_opcode ("fmrs");
20358 /* ARMv8.2 fp16 vmov.f16 instruction. */
20360 do_scalar_fp16_v82_encode ();
20364 case NS_FR
: /* case 13 (fmsr). */
20365 do_vfp_nsyn_opcode ("fmsr");
20366 /* ARMv8.2 fp16 vmov.f16 instruction. */
20368 do_scalar_fp16_v82_encode ();
20378 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20379 (one of which is a list), but we have parsed four. Do some fiddling to
20380 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20382 case NS_RRFF
: /* case 14 (fmrrs). */
20383 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20384 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20386 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20387 _("VFP registers must be adjacent"));
20388 inst
.operands
[2].imm
= 2;
20389 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20390 do_vfp_nsyn_opcode ("fmrrs");
20393 case NS_FFRR
: /* case 15 (fmsrr). */
20394 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20395 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20397 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20398 _("VFP registers must be adjacent"));
20399 inst
.operands
[1] = inst
.operands
[2];
20400 inst
.operands
[2] = inst
.operands
[3];
20401 inst
.operands
[0].imm
= 2;
20402 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20403 do_vfp_nsyn_opcode ("fmsrr");
20407 /* neon_select_shape has determined that the instruction
20408 shape is wrong and has already set the error message. */
20419 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20420 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20421 && !inst
.operands
[2].present
))
20423 inst
.instruction
= 0;
20426 set_pred_insn_type (INSIDE_IT_INSN
);
20431 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20434 if (inst
.cond
!= COND_ALWAYS
)
20435 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20437 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20438 | N_S16
| N_U16
| N_KEY
);
20440 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20441 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20442 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20443 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20444 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20445 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20450 do_neon_rshift_round_imm (void)
20452 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20455 enum neon_shape rs
;
20456 struct neon_type_el et
;
20458 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20460 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20461 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20465 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20466 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20468 int imm
= inst
.operands
[2].imm
;
20470 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20473 inst
.operands
[2].present
= 0;
20478 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20479 _("immediate out of range for shift"));
20480 neon_imm_shift (true, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20485 do_neon_movhf (void)
20487 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20488 constraint (rs
!= NS_HH
, _("invalid suffix"));
20490 if (inst
.cond
!= COND_ALWAYS
)
20494 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20495 " the behaviour is UNPREDICTABLE"));
20499 inst
.error
= BAD_COND
;
20504 do_vfp_sp_monadic ();
20507 inst
.instruction
|= 0xf0000000;
20511 do_neon_movl (void)
20513 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20514 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20515 unsigned sizebits
= et
.size
>> 3;
20516 inst
.instruction
|= sizebits
<< 19;
20517 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20523 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20524 struct neon_type_el et
= neon_check_type (2, rs
,
20525 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20526 NEON_ENCODE (INTEGER
, inst
);
20527 neon_two_same (neon_quad (rs
), 1, et
.size
);
20531 do_neon_zip_uzp (void)
20533 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20534 struct neon_type_el et
= neon_check_type (2, rs
,
20535 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20536 if (rs
== NS_DD
&& et
.size
== 32)
20538 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20539 inst
.instruction
= N_MNEM_vtrn
;
20543 neon_two_same (neon_quad (rs
), 1, et
.size
);
20547 do_neon_sat_abs_neg (void)
20549 if (!check_simd_pred_availability (false, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20552 enum neon_shape rs
;
20553 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20554 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20556 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20557 struct neon_type_el et
= neon_check_type (2, rs
,
20558 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20559 neon_two_same (neon_quad (rs
), 1, et
.size
);
20563 do_neon_pair_long (void)
20565 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20566 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20567 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20568 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20569 neon_two_same (neon_quad (rs
), 1, et
.size
);
20573 do_neon_recip_est (void)
20575 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20576 struct neon_type_el et
= neon_check_type (2, rs
,
20577 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20578 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20579 neon_two_same (neon_quad (rs
), 1, et
.size
);
20585 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20588 enum neon_shape rs
;
20589 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20590 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20592 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20594 struct neon_type_el et
= neon_check_type (2, rs
,
20595 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20596 neon_two_same (neon_quad (rs
), 1, et
.size
);
20602 if (!check_simd_pred_availability (false, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20605 enum neon_shape rs
;
20606 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20607 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20609 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20611 struct neon_type_el et
= neon_check_type (2, rs
,
20612 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20613 neon_two_same (neon_quad (rs
), 1, et
.size
);
20619 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20620 struct neon_type_el et
= neon_check_type (2, rs
,
20621 N_EQK
| N_INT
, N_8
| N_KEY
);
20622 neon_two_same (neon_quad (rs
), 1, et
.size
);
20628 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20631 neon_two_same (neon_quad (rs
), 1, -1);
20635 do_neon_tbl_tbx (void)
20637 unsigned listlenbits
;
20638 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20640 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20642 first_error (_("bad list length for table lookup"));
20646 listlenbits
= inst
.operands
[1].imm
- 1;
20647 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20648 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20649 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20650 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20651 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20652 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20653 inst
.instruction
|= listlenbits
<< 8;
20655 neon_dp_fixup (&inst
);
20659 do_neon_ldm_stm (void)
20661 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
20662 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20664 /* P, U and L bits are part of bitmask. */
20665 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20666 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20668 if (inst
.operands
[1].issingle
)
20670 do_vfp_nsyn_ldm_stm (is_dbmode
);
20674 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20675 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20677 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20678 _("register list must contain at least 1 and at most 16 "
20681 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20682 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20683 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20684 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20686 inst
.instruction
|= offsetbits
;
20688 do_vfp_cond_or_thumb ();
20692 do_vfp_nsyn_pop (void)
20695 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20696 return do_vfp_nsyn_opcode ("vldm");
20699 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20702 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20703 _("register list must contain at least 1 and at most 16 "
20706 if (inst
.operands
[1].issingle
)
20707 do_vfp_nsyn_opcode ("fldmias");
20709 do_vfp_nsyn_opcode ("fldmiad");
20713 do_vfp_nsyn_push (void)
20716 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20717 return do_vfp_nsyn_opcode ("vstmdb");
20720 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20723 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20724 _("register list must contain at least 1 and at most 16 "
20727 if (inst
.operands
[1].issingle
)
20728 do_vfp_nsyn_opcode ("fstmdbs");
20730 do_vfp_nsyn_opcode ("fstmdbd");
20735 do_neon_ldr_str (void)
20737 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20739 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20740 And is UNPREDICTABLE in thumb mode. */
20742 && inst
.operands
[1].reg
== REG_PC
20743 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20746 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20747 else if (warn_on_deprecated
)
20748 as_tsktsk (_("Use of PC here is deprecated"));
20751 if (inst
.operands
[0].issingle
)
20754 do_vfp_nsyn_opcode ("flds");
20756 do_vfp_nsyn_opcode ("fsts");
20758 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20759 if (inst
.vectype
.el
[0].size
== 16)
20760 do_scalar_fp16_v82_encode ();
20765 do_vfp_nsyn_opcode ("fldd");
20767 do_vfp_nsyn_opcode ("fstd");
20772 do_t_vldr_vstr_sysreg (void)
20774 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20775 bool is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20777 /* Use of PC is UNPREDICTABLE. */
20778 if (inst
.operands
[1].reg
== REG_PC
)
20779 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20781 if (inst
.operands
[1].immisreg
)
20782 inst
.error
= _("instruction does not accept register index");
20784 if (!inst
.operands
[1].isreg
)
20785 inst
.error
= _("instruction does not accept PC-relative addressing");
20787 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20788 inst
.error
= _("immediate value out of range");
20790 inst
.instruction
= 0xec000f80;
20792 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20793 encode_arm_cp_address (1, true, false, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20794 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20795 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20799 do_vldr_vstr (void)
20801 bool sysreg_op
= !inst
.operands
[0].isreg
;
20803 /* VLDR/VSTR (System Register). */
20806 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20807 as_bad (_("Instruction not permitted on this architecture"));
20809 do_t_vldr_vstr_sysreg ();
20814 if (!mark_feature_used (&fpu_vfp_ext_v1xd
)
20815 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20816 as_bad (_("Instruction not permitted on this architecture"));
20817 do_neon_ldr_str ();
20821 /* "interleave" version also handles non-interleaving register VLD1/VST1
20825 do_neon_ld_st_interleave (void)
20827 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20828 N_8
| N_16
| N_32
| N_64
);
20829 unsigned alignbits
= 0;
20831 /* The bits in this table go:
20832 0: register stride of one (0) or two (1)
20833 1,2: register list length, minus one (1, 2, 3, 4).
20834 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20835 We use -1 for invalid entries. */
20836 const int typetable
[] =
20838 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20839 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20840 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20841 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20845 if (et
.type
== NT_invtype
)
20848 if (inst
.operands
[1].immisalign
)
20849 switch (inst
.operands
[1].imm
>> 8)
20851 case 64: alignbits
= 1; break;
20853 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20854 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20855 goto bad_alignment
;
20859 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20860 goto bad_alignment
;
20865 first_error (_("bad alignment"));
20869 inst
.instruction
|= alignbits
<< 4;
20870 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20872 /* Bits [4:6] of the immediate in a list specifier encode register stride
20873 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20874 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20875 up the right value for "type" in a table based on this value and the given
20876 list style, then stick it back. */
20877 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20878 | (((inst
.instruction
>> 8) & 3) << 3);
20880 typebits
= typetable
[idx
];
20882 constraint (typebits
== -1, _("bad list type for instruction"));
20883 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20886 inst
.instruction
&= ~0xf00;
20887 inst
.instruction
|= typebits
<< 8;
20890 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20891 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20892 otherwise. The variable arguments are a list of pairs of legal (size, align)
20893 values, terminated with -1. */
20896 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20899 int result
= FAIL
, thissize
, thisalign
;
20901 if (!inst
.operands
[1].immisalign
)
20907 va_start (ap
, do_alignment
);
20911 thissize
= va_arg (ap
, int);
20912 if (thissize
== -1)
20914 thisalign
= va_arg (ap
, int);
20916 if (size
== thissize
&& align
== thisalign
)
20919 while (result
!= SUCCESS
);
20923 if (result
== SUCCESS
)
20926 first_error (_("unsupported alignment for instruction"));
20932 do_neon_ld_st_lane (void)
20934 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20935 int align_good
, do_alignment
= 0;
20936 int logsize
= neon_logbits (et
.size
);
20937 int align
= inst
.operands
[1].imm
>> 8;
20938 int n
= (inst
.instruction
>> 8) & 3;
20939 int max_el
= 64 / et
.size
;
20941 if (et
.type
== NT_invtype
)
20944 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20945 _("bad list length"));
20946 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20947 _("scalar index out of range"));
20948 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20950 _("stride of 2 unavailable when element size is 8"));
20954 case 0: /* VLD1 / VST1. */
20955 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20957 if (align_good
== FAIL
)
20961 unsigned alignbits
= 0;
20964 case 16: alignbits
= 0x1; break;
20965 case 32: alignbits
= 0x3; break;
20968 inst
.instruction
|= alignbits
<< 4;
20972 case 1: /* VLD2 / VST2. */
20973 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20974 16, 32, 32, 64, -1);
20975 if (align_good
== FAIL
)
20978 inst
.instruction
|= 1 << 4;
20981 case 2: /* VLD3 / VST3. */
20982 constraint (inst
.operands
[1].immisalign
,
20983 _("can't use alignment with this instruction"));
20986 case 3: /* VLD4 / VST4. */
20987 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20988 16, 64, 32, 64, 32, 128, -1);
20989 if (align_good
== FAIL
)
20993 unsigned alignbits
= 0;
20996 case 8: alignbits
= 0x1; break;
20997 case 16: alignbits
= 0x1; break;
20998 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
21001 inst
.instruction
|= alignbits
<< 4;
21008 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
21009 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21010 inst
.instruction
|= 1 << (4 + logsize
);
21012 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
21013 inst
.instruction
|= logsize
<< 10;
21016 /* Encode single n-element structure to all lanes VLD<n> instructions. */
21019 do_neon_ld_dup (void)
21021 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
21022 int align_good
, do_alignment
= 0;
21024 if (et
.type
== NT_invtype
)
21027 switch ((inst
.instruction
>> 8) & 3)
21029 case 0: /* VLD1. */
21030 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
21031 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21032 &do_alignment
, 16, 16, 32, 32, -1);
21033 if (align_good
== FAIL
)
21035 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
21038 case 2: inst
.instruction
|= 1 << 5; break;
21039 default: first_error (_("bad list length")); return;
21041 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21044 case 1: /* VLD2. */
21045 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21046 &do_alignment
, 8, 16, 16, 32, 32, 64,
21048 if (align_good
== FAIL
)
21050 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
21051 _("bad list length"));
21052 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21053 inst
.instruction
|= 1 << 5;
21054 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21057 case 2: /* VLD3. */
21058 constraint (inst
.operands
[1].immisalign
,
21059 _("can't use alignment with this instruction"));
21060 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
21061 _("bad list length"));
21062 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21063 inst
.instruction
|= 1 << 5;
21064 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21067 case 3: /* VLD4. */
21069 int align
= inst
.operands
[1].imm
>> 8;
21070 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
21071 16, 64, 32, 64, 32, 128, -1);
21072 if (align_good
== FAIL
)
21074 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
21075 _("bad list length"));
21076 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21077 inst
.instruction
|= 1 << 5;
21078 if (et
.size
== 32 && align
== 128)
21079 inst
.instruction
|= 0x3 << 6;
21081 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21088 inst
.instruction
|= do_alignment
<< 4;
21091 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
21092 apart from bits [11:4]. */
21095 do_neon_ldx_stx (void)
21097 if (inst
.operands
[1].isreg
)
21098 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
21100 switch (NEON_LANE (inst
.operands
[0].imm
))
21102 case NEON_INTERLEAVE_LANES
:
21103 NEON_ENCODE (INTERLV
, inst
);
21104 do_neon_ld_st_interleave ();
21107 case NEON_ALL_LANES
:
21108 NEON_ENCODE (DUP
, inst
);
21109 if (inst
.instruction
== N_INV
)
21111 first_error ("only loads support such operands");
21118 NEON_ENCODE (LANE
, inst
);
21119 do_neon_ld_st_lane ();
21122 /* L bit comes from bit mask. */
21123 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21124 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21125 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
21127 if (inst
.operands
[1].postind
)
21129 int postreg
= inst
.operands
[1].imm
& 0xf;
21130 constraint (!inst
.operands
[1].immisreg
,
21131 _("post-index must be a register"));
21132 constraint (postreg
== 0xd || postreg
== 0xf,
21133 _("bad register for post-index"));
21134 inst
.instruction
|= postreg
;
21138 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
21139 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
21140 || inst
.relocs
[0].exp
.X_add_number
!= 0,
21143 if (inst
.operands
[1].writeback
)
21145 inst
.instruction
|= 0xd;
21148 inst
.instruction
|= 0xf;
21152 inst
.instruction
|= 0xf9000000;
21154 inst
.instruction
|= 0xf4000000;
21159 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
21161 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21162 D register operands. */
21163 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21164 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21167 NEON_ENCODE (FPV8
, inst
);
21169 if (rs
== NS_FFF
|| rs
== NS_HHH
)
21171 do_vfp_sp_dyadic ();
21173 /* ARMv8.2 fp16 instruction. */
21175 do_scalar_fp16_v82_encode ();
21178 do_vfp_dp_rd_rn_rm ();
21181 inst
.instruction
|= 0x100;
21183 inst
.instruction
|= 0xf0000000;
21189 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21191 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
21192 first_error (_("invalid instruction shape"));
21198 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21199 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21201 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
21204 if (!check_simd_pred_availability (true, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21207 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
21211 do_vrint_1 (enum neon_cvt_mode mode
)
21213 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
21214 struct neon_type_el et
;
21219 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21220 D register operands. */
21221 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21222 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21225 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
21227 if (et
.type
!= NT_invtype
)
21229 /* VFP encodings. */
21230 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
21231 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
21232 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21234 NEON_ENCODE (FPV8
, inst
);
21235 if (rs
== NS_FF
|| rs
== NS_HH
)
21236 do_vfp_sp_monadic ();
21238 do_vfp_dp_rd_rm ();
21242 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
21243 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
21244 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
21245 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
21246 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
21247 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
21248 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
21252 inst
.instruction
|= (rs
== NS_DD
) << 8;
21253 do_vfp_cond_or_thumb ();
21255 /* ARMv8.2 fp16 vrint instruction. */
21257 do_scalar_fp16_v82_encode ();
21261 /* Neon encodings (or something broken...). */
21263 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
21265 if (et
.type
== NT_invtype
)
21268 if (!check_simd_pred_availability (true,
21269 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21272 NEON_ENCODE (FLOAT
, inst
);
21274 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21275 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21276 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21277 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21278 inst
.instruction
|= neon_quad (rs
) << 6;
21279 /* Mask off the original size bits and reencode them. */
21280 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
21281 | neon_logbits (et
.size
) << 18);
21285 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
21286 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
21287 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
21288 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
21289 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
21290 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
21291 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21296 inst
.instruction
|= 0xfc000000;
21298 inst
.instruction
|= 0xf0000000;
21305 do_vrint_1 (neon_cvt_mode_x
);
21311 do_vrint_1 (neon_cvt_mode_z
);
21317 do_vrint_1 (neon_cvt_mode_r
);
21323 do_vrint_1 (neon_cvt_mode_a
);
21329 do_vrint_1 (neon_cvt_mode_n
);
21335 do_vrint_1 (neon_cvt_mode_p
);
21341 do_vrint_1 (neon_cvt_mode_m
);
21345 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21347 unsigned regno
= NEON_SCALAR_REG (opnd
);
21348 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21350 if (elsize
== 16 && elno
< 2 && regno
< 16)
21351 return regno
| (elno
<< 4);
21352 else if (elsize
== 32 && elno
== 0)
21355 first_error (_("scalar out of range"));
21362 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21363 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21364 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21365 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21366 _("expression too complex"));
21367 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21368 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21369 _("immediate out of range"));
21372 if (!check_simd_pred_availability (true,
21373 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21376 if (inst
.operands
[2].isscalar
)
21378 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21379 first_error (_("invalid instruction shape"));
21380 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21381 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21382 N_KEY
| N_F16
| N_F32
).size
;
21383 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21385 inst
.instruction
= 0xfe000800;
21386 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21387 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21388 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21389 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21390 inst
.instruction
|= LOW4 (m
);
21391 inst
.instruction
|= HI1 (m
) << 5;
21392 inst
.instruction
|= neon_quad (rs
) << 6;
21393 inst
.instruction
|= rot
<< 20;
21394 inst
.instruction
|= (size
== 32) << 23;
21398 enum neon_shape rs
;
21399 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21400 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21402 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21404 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21405 N_KEY
| N_F16
| N_F32
).size
;
21406 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21407 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21408 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21409 as_tsktsk (BAD_MVE_SRCDEST
);
21411 neon_three_same (neon_quad (rs
), 0, -1);
21412 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21413 inst
.instruction
|= 0xfc200800;
21414 inst
.instruction
|= rot
<< 23;
21415 inst
.instruction
|= (size
== 32) << 20;
21422 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21423 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21424 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21425 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21426 _("expression too complex"));
21428 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21429 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21430 enum neon_shape rs
;
21431 struct neon_type_el et
;
21432 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21434 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21435 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21439 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21440 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21442 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21443 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21444 "operand makes instruction UNPREDICTABLE"));
21447 if (et
.type
== NT_invtype
)
21450 if (!check_simd_pred_availability (et
.type
== NT_float
,
21451 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21454 if (et
.type
== NT_float
)
21456 neon_three_same (neon_quad (rs
), 0, -1);
21457 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21458 inst
.instruction
|= 0xfc800800;
21459 inst
.instruction
|= (rot
== 270) << 24;
21460 inst
.instruction
|= (et
.size
== 32) << 20;
21464 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21465 inst
.instruction
= 0xfe000f00;
21466 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21467 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21468 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21469 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21470 inst
.instruction
|= (rot
== 270) << 12;
21471 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21472 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21473 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21478 /* Dot Product instructions encoding support. */
21481 do_neon_dotproduct (int unsigned_p
)
21483 enum neon_shape rs
;
21484 unsigned scalar_oprd2
= 0;
21487 if (inst
.cond
!= COND_ALWAYS
)
21488 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21489 "is UNPREDICTABLE"));
21491 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21494 /* Dot Product instructions are in three-same D/Q register format or the third
21495 operand can be a scalar index register. */
21496 if (inst
.operands
[2].isscalar
)
21498 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21499 high8
= 0xfe000000;
21500 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21504 high8
= 0xfc000000;
21505 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21509 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21511 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21513 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21514 Product instruction, so we pass 0 as the "ubit" parameter. And the
21515 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21516 neon_three_same (neon_quad (rs
), 0, 32);
21518 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21519 different NEON three-same encoding. */
21520 inst
.instruction
&= 0x00ffffff;
21521 inst
.instruction
|= high8
;
21522 /* Encode 'U' bit which indicates signedness. */
21523 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21524 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21525 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21526 the instruction encoding. */
21527 if (inst
.operands
[2].isscalar
)
21529 inst
.instruction
&= 0xffffffd0;
21530 inst
.instruction
|= LOW4 (scalar_oprd2
);
21531 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21535 /* Dot Product instructions for signed integer. */
21538 do_neon_dotproduct_s (void)
21540 return do_neon_dotproduct (0);
21543 /* Dot Product instructions for unsigned integer. */
21546 do_neon_dotproduct_u (void)
21548 return do_neon_dotproduct (1);
21554 enum neon_shape rs
;
21555 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21556 if (inst
.operands
[2].isscalar
)
21558 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21559 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21561 inst
.instruction
|= (1 << 25);
21562 int idx
= inst
.operands
[2].reg
& 0xf;
21563 constraint ((idx
!= 1 && idx
!= 0), _("index must be 0 or 1"));
21564 inst
.operands
[2].reg
>>= 4;
21565 constraint (!(inst
.operands
[2].reg
< 16),
21566 _("indexed register must be less than 16"));
21567 neon_three_args (rs
== NS_QQS
);
21568 inst
.instruction
|= (idx
<< 5);
21572 inst
.instruction
|= (1 << 21);
21573 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21574 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21575 neon_three_args (rs
== NS_QQQ
);
21582 enum neon_shape rs
;
21583 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21584 if (inst
.operands
[2].isscalar
)
21586 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21587 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21589 inst
.instruction
|= (1 << 25);
21590 int idx
= inst
.operands
[2].reg
& 0xf;
21591 constraint ((idx
!= 1 && idx
!= 0), _("index must be 0 or 1"));
21592 inst
.operands
[2].reg
>>= 4;
21593 constraint (!(inst
.operands
[2].reg
< 16),
21594 _("indexed register must be less than 16"));
21595 neon_three_args (rs
== NS_QQS
);
21596 inst
.instruction
|= (idx
<< 5);
21603 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21604 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21606 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21608 neon_three_args (1);
21615 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21616 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21618 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21620 neon_three_args (1);
21625 check_cde_operand (size_t idx
, int is_dual
)
21627 unsigned Rx
= inst
.operands
[idx
].reg
;
21628 bool isvec
= inst
.operands
[idx
].isvec
;
21629 if (is_dual
== 0 && thumb_mode
)
21631 !((Rx
<= 14 && Rx
!= 13) || (Rx
== REG_PC
&& isvec
)),
21632 _("Register must be r0-r14 except r13, or APSR_nzcv."));
21634 constraint ( !((Rx
<= 10 && Rx
% 2 == 0 )),
21635 _("Register must be an even register between r0-r10."));
21639 cde_coproc_enabled (unsigned coproc
)
21643 case 0: return mark_feature_used (&arm_ext_cde0
);
21644 case 1: return mark_feature_used (&arm_ext_cde1
);
21645 case 2: return mark_feature_used (&arm_ext_cde2
);
21646 case 3: return mark_feature_used (&arm_ext_cde3
);
21647 case 4: return mark_feature_used (&arm_ext_cde4
);
21648 case 5: return mark_feature_used (&arm_ext_cde5
);
21649 case 6: return mark_feature_used (&arm_ext_cde6
);
21650 case 7: return mark_feature_used (&arm_ext_cde7
);
21651 default: return false;
21655 #define cde_coproc_pos 8
21657 cde_handle_coproc (void)
21659 unsigned coproc
= inst
.operands
[0].reg
;
21660 constraint (coproc
> 7, _("CDE Coprocessor must be in range 0-7"));
21661 constraint (!(cde_coproc_enabled (coproc
)), BAD_CDE_COPROC
);
21662 inst
.instruction
|= coproc
<< cde_coproc_pos
;
21664 #undef cde_coproc_pos
21667 cxn_handle_predication (bool is_accum
)
21669 if (is_accum
&& conditional_insn ())
21670 set_pred_insn_type (INSIDE_IT_INSN
);
21671 else if (conditional_insn ())
21672 /* conditional_insn essentially checks for a suffix, not whether the
21673 instruction is inside an IT block or not.
21674 The non-accumulator versions should not have suffixes. */
21675 inst
.error
= BAD_SYNTAX
;
21677 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21681 do_custom_instruction_1 (int is_dual
, bool is_accum
)
21684 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21688 Rd
= inst
.operands
[1].reg
;
21689 check_cde_operand (1, is_dual
);
21693 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21694 _("cx1d requires consecutive destination registers."));
21695 imm
= inst
.operands
[3].imm
;
21697 else if (is_dual
== 0)
21698 imm
= inst
.operands
[2].imm
;
21702 inst
.instruction
|= Rd
<< 12;
21703 inst
.instruction
|= (imm
& 0x1F80) << 9;
21704 inst
.instruction
|= (imm
& 0x0040) << 1;
21705 inst
.instruction
|= (imm
& 0x003f);
21707 cde_handle_coproc ();
21708 cxn_handle_predication (is_accum
);
21712 do_custom_instruction_2 (int is_dual
, bool is_accum
)
21715 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21717 unsigned imm
, Rd
, Rn
;
21719 Rd
= inst
.operands
[1].reg
;
21723 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21724 _("cx2d requires consecutive destination registers."));
21725 imm
= inst
.operands
[4].imm
;
21726 Rn
= inst
.operands
[3].reg
;
21728 else if (is_dual
== 0)
21730 imm
= inst
.operands
[3].imm
;
21731 Rn
= inst
.operands
[2].reg
;
21736 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21737 check_cde_operand (1, is_dual
);
21739 inst
.instruction
|= Rd
<< 12;
21740 inst
.instruction
|= Rn
<< 16;
21742 inst
.instruction
|= (imm
& 0x0380) << 13;
21743 inst
.instruction
|= (imm
& 0x0040) << 1;
21744 inst
.instruction
|= (imm
& 0x003f);
21746 cde_handle_coproc ();
21747 cxn_handle_predication (is_accum
);
21751 do_custom_instruction_3 (int is_dual
, bool is_accum
)
21754 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21756 unsigned imm
, Rd
, Rn
, Rm
;
21758 Rd
= inst
.operands
[1].reg
;
21762 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21763 _("cx3d requires consecutive destination registers."));
21764 imm
= inst
.operands
[5].imm
;
21765 Rn
= inst
.operands
[3].reg
;
21766 Rm
= inst
.operands
[4].reg
;
21768 else if (is_dual
== 0)
21770 imm
= inst
.operands
[4].imm
;
21771 Rn
= inst
.operands
[2].reg
;
21772 Rm
= inst
.operands
[3].reg
;
21777 check_cde_operand (1, is_dual
);
21778 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21779 check_cde_operand (3 + is_dual
, /* is_dual = */0);
21781 inst
.instruction
|= Rd
;
21782 inst
.instruction
|= Rn
<< 16;
21783 inst
.instruction
|= Rm
<< 12;
21785 inst
.instruction
|= (imm
& 0x0038) << 17;
21786 inst
.instruction
|= (imm
& 0x0004) << 5;
21787 inst
.instruction
|= (imm
& 0x0003) << 4;
21789 cde_handle_coproc ();
21790 cxn_handle_predication (is_accum
);
21796 return do_custom_instruction_1 (0, 0);
21802 return do_custom_instruction_1 (0, 1);
21808 return do_custom_instruction_1 (1, 0);
21814 return do_custom_instruction_1 (1, 1);
21820 return do_custom_instruction_2 (0, 0);
21826 return do_custom_instruction_2 (0, 1);
21832 return do_custom_instruction_2 (1, 0);
21838 return do_custom_instruction_2 (1, 1);
21844 return do_custom_instruction_3 (0, 0);
21850 return do_custom_instruction_3 (0, 1);
21856 return do_custom_instruction_3 (1, 0);
21862 return do_custom_instruction_3 (1, 1);
21866 vcx_assign_vec_d (unsigned regnum
)
21868 inst
.instruction
|= HI4 (regnum
) << 12;
21869 inst
.instruction
|= LOW1 (regnum
) << 22;
21873 vcx_assign_vec_m (unsigned regnum
)
21875 inst
.instruction
|= HI4 (regnum
);
21876 inst
.instruction
|= LOW1 (regnum
) << 5;
21880 vcx_assign_vec_n (unsigned regnum
)
21882 inst
.instruction
|= HI4 (regnum
) << 16;
21883 inst
.instruction
|= LOW1 (regnum
) << 7;
21886 enum vcx_reg_type
{
21892 static enum vcx_reg_type
21893 vcx_get_reg_type (enum neon_shape ns
)
21895 gas_assert (ns
== NS_PQI
21903 || ns
== NS_PFFFI
);
21904 if (ns
== NS_PQI
|| ns
== NS_PQQI
|| ns
== NS_PQQQI
)
21906 if (ns
== NS_PDI
|| ns
== NS_PDDI
|| ns
== NS_PDDDI
)
21911 #define vcx_size_pos 24
21912 #define vcx_vec_pos 6
21914 vcx_handle_shape (enum vcx_reg_type reg_type
)
21917 if (reg_type
== q_reg
)
21918 inst
.instruction
|= 1 << vcx_vec_pos
;
21919 else if (reg_type
== d_reg
)
21920 inst
.instruction
|= 1 << vcx_size_pos
;
21924 The documentation says that the Q registers are encoded as 2*N in the D:Vd
21925 bits (or equivalent for N and M registers).
21926 Similarly the D registers are encoded as N in D:Vd bits.
21927 While the S registers are encoded as N in the Vd:D bits.
21929 Taking into account the maximum values of these registers we can see a
21930 nicer pattern for calculation:
21931 Q -> 7, D -> 15, S -> 31
21933 If we say that everything is encoded in the Vd:D bits, then we can say
21934 that Q is encoded as 4*N, and D is encoded as 2*N.
21935 This way the bits will end up the same, and calculation is simpler.
21936 (calculation is now:
21937 1. Multiply by a number determined by the register letter.
21938 2. Encode resulting number in Vd:D bits.)
21940 This is made a little more complicated by automatic handling of 'Q'
21941 registers elsewhere, which means the register number is already 2*N where
21942 N is the number the user wrote after the register letter.
21947 #undef vcx_size_pos
21950 vcx_ensure_register_in_range (unsigned R
, enum vcx_reg_type reg_type
)
21952 if (reg_type
== q_reg
)
21954 gas_assert (R
% 2 == 0);
21955 constraint (R
>= 16, _("'q' register must be in range 0-7"));
21957 else if (reg_type
== d_reg
)
21958 constraint (R
>= 16, _("'d' register must be in range 0-15"));
21960 constraint (R
>= 32, _("'s' register must be in range 0-31"));
21963 static void (*vcx_assign_vec
[3]) (unsigned) = {
21970 vcx_handle_register_arguments (unsigned num_registers
,
21971 enum vcx_reg_type reg_type
)
21974 unsigned reg_mult
= vcx_handle_shape (reg_type
);
21975 for (i
= 0; i
< num_registers
; i
++)
21977 R
= inst
.operands
[i
+1].reg
;
21978 vcx_ensure_register_in_range (R
, reg_type
);
21979 if (num_registers
== 3 && i
> 0)
21982 vcx_assign_vec
[1] (R
* reg_mult
);
21984 vcx_assign_vec
[2] (R
* reg_mult
);
21987 vcx_assign_vec
[i
](R
* reg_mult
);
21992 vcx_handle_insn_block (enum vcx_reg_type reg_type
)
21994 if (reg_type
== q_reg
)
21995 if (inst
.cond
> COND_ALWAYS
)
21996 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
21998 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
21999 else if (inst
.cond
== COND_ALWAYS
)
22000 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22002 inst
.error
= BAD_NOT_IT
;
22006 vcx_handle_common_checks (unsigned num_args
, enum neon_shape rs
)
22008 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
22009 cde_handle_coproc ();
22010 enum vcx_reg_type reg_type
= vcx_get_reg_type (rs
);
22011 vcx_handle_register_arguments (num_args
, reg_type
);
22012 vcx_handle_insn_block (reg_type
);
22013 if (reg_type
== q_reg
)
22014 constraint (!mark_feature_used (&mve_ext
),
22015 _("vcx instructions with Q registers require MVE"));
22017 constraint (!(ARM_FSET_CPU_SUBSET (armv8m_fp
, cpu_variant
)
22018 && mark_feature_used (&armv8m_fp
))
22019 && !mark_feature_used (&mve_ext
),
22020 _("vcx instructions with S or D registers require either MVE"
22021 " or Armv8-M floating point extension."));
22027 enum neon_shape rs
= neon_select_shape (NS_PQI
, NS_PDI
, NS_PFI
, NS_NULL
);
22028 vcx_handle_common_checks (1, rs
);
22030 unsigned imm
= inst
.operands
[2].imm
;
22031 inst
.instruction
|= (imm
& 0x03f);
22032 inst
.instruction
|= (imm
& 0x040) << 1;
22033 inst
.instruction
|= (imm
& 0x780) << 9;
22035 constraint (imm
>= 2048,
22036 _("vcx1 with S or D registers takes immediate within 0-2047"));
22037 inst
.instruction
|= (imm
& 0x800) << 13;
22043 enum neon_shape rs
= neon_select_shape (NS_PQQI
, NS_PDDI
, NS_PFFI
, NS_NULL
);
22044 vcx_handle_common_checks (2, rs
);
22046 unsigned imm
= inst
.operands
[3].imm
;
22047 inst
.instruction
|= (imm
& 0x01) << 4;
22048 inst
.instruction
|= (imm
& 0x02) << 6;
22049 inst
.instruction
|= (imm
& 0x3c) << 14;
22051 constraint (imm
>= 64,
22052 _("vcx2 with S or D registers takes immediate within 0-63"));
22053 inst
.instruction
|= (imm
& 0x40) << 18;
22059 enum neon_shape rs
= neon_select_shape (NS_PQQQI
, NS_PDDDI
, NS_PFFFI
, NS_NULL
);
22060 vcx_handle_common_checks (3, rs
);
22062 unsigned imm
= inst
.operands
[4].imm
;
22063 inst
.instruction
|= (imm
& 0x1) << 4;
22064 inst
.instruction
|= (imm
& 0x6) << 19;
22065 if (rs
!= NS_PQQQI
)
22066 constraint (imm
>= 8,
22067 _("vcx2 with S or D registers takes immediate within 0-7"));
22068 inst
.instruction
|= (imm
& 0x8) << 21;
22071 /* Crypto v1 instructions. */
22073 do_crypto_2op_1 (unsigned elttype
, int op
)
22075 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22077 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
22083 NEON_ENCODE (INTEGER
, inst
);
22084 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
22085 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
22086 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
22087 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
22089 inst
.instruction
|= op
<< 6;
22092 inst
.instruction
|= 0xfc000000;
22094 inst
.instruction
|= 0xf0000000;
22098 do_crypto_3op_1 (int u
, int op
)
22100 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22102 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
22103 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
22108 NEON_ENCODE (INTEGER
, inst
);
22109 neon_three_same (1, u
, 8 << op
);
22115 do_crypto_2op_1 (N_8
, 0);
22121 do_crypto_2op_1 (N_8
, 1);
22127 do_crypto_2op_1 (N_8
, 2);
22133 do_crypto_2op_1 (N_8
, 3);
22139 do_crypto_3op_1 (0, 0);
22145 do_crypto_3op_1 (0, 1);
22151 do_crypto_3op_1 (0, 2);
22157 do_crypto_3op_1 (0, 3);
22163 do_crypto_3op_1 (1, 0);
22169 do_crypto_3op_1 (1, 1);
22173 do_sha256su1 (void)
22175 do_crypto_3op_1 (1, 2);
22181 do_crypto_2op_1 (N_32
, -1);
22187 do_crypto_2op_1 (N_32
, 0);
22191 do_sha256su0 (void)
22193 do_crypto_2op_1 (N_32
, 1);
22197 do_crc32_1 (unsigned int poly
, unsigned int sz
)
22199 unsigned int Rd
= inst
.operands
[0].reg
;
22200 unsigned int Rn
= inst
.operands
[1].reg
;
22201 unsigned int Rm
= inst
.operands
[2].reg
;
22203 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22204 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
22205 inst
.instruction
|= LOW4 (Rn
) << 16;
22206 inst
.instruction
|= LOW4 (Rm
);
22207 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
22208 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
22210 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
22211 as_warn (UNPRED_REG ("r15"));
22253 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
22255 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
22256 do_vfp_sp_dp_cvt ();
22257 do_vfp_cond_or_thumb ();
22263 enum neon_shape rs
;
22264 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22265 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22266 if (inst
.operands
[2].isscalar
)
22268 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
22269 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22271 inst
.instruction
|= (1 << 25);
22272 int idx
= inst
.operands
[2].reg
& 0xf;
22273 constraint ((idx
!= 1 && idx
!= 0), _("index must be 0 or 1"));
22274 inst
.operands
[2].reg
>>= 4;
22275 constraint (!(inst
.operands
[2].reg
< 16),
22276 _("indexed register must be less than 16"));
22277 neon_three_args (rs
== NS_QQS
);
22278 inst
.instruction
|= (idx
<< 5);
22282 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
22283 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22284 neon_three_args (rs
== NS_QQQ
);
22291 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
22292 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22294 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22295 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22297 neon_three_args (1);
22303 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
22307 do_t_pacbti_nonop (void)
22309 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, pacbti_ext
),
22312 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
22313 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
22314 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
22315 inst
.instruction
|= inst
.operands
[2].reg
;
22319 do_t_pacbti_pacg (void)
22321 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, pacbti_ext
),
22324 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
22325 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
22326 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
22327 inst
.instruction
|= inst
.operands
[2].reg
;
22331 /* Overall per-instruction processing. */
22333 /* We need to be able to fix up arbitrary expressions in some statements.
22334 This is so that we can handle symbols that are an arbitrary distance from
22335 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
22336 which returns part of an address in a form which will be valid for
22337 a data instruction. We do this by pushing the expression into a symbol
22338 in the expr_section, and creating a fix for that. */
22341 fix_new_arm (fragS
* frag
,
22355 /* Create an absolute valued symbol, so we have something to
22356 refer to in the object file. Unfortunately for us, gas's
22357 generic expression parsing will already have folded out
22358 any use of .set foo/.type foo %function that may have
22359 been used to set type information of the target location,
22360 that's being specified symbolically. We have to presume
22361 the user knows what they are doing. */
22365 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
22367 symbol
= symbol_find_or_make (name
);
22368 S_SET_SEGMENT (symbol
, absolute_section
);
22369 symbol_set_frag (symbol
, &zero_address_frag
);
22370 S_SET_VALUE (symbol
, exp
->X_add_number
);
22371 exp
->X_op
= O_symbol
;
22372 exp
->X_add_symbol
= symbol
;
22373 exp
->X_add_number
= 0;
22379 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
22380 (enum bfd_reloc_code_real
) reloc
);
22384 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
22385 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
22389 /* Mark whether the fix is to a THUMB instruction, or an ARM
22391 new_fix
->tc_fix_data
= thumb_mode
;
22394 /* Create a frg for an instruction requiring relaxation. */
22396 output_relax_insn (void)
22402 /* The size of the instruction is unknown, so tie the debug info to the
22403 start of the instruction. */
22404 dwarf2_emit_insn (0);
22406 switch (inst
.relocs
[0].exp
.X_op
)
22409 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
22410 offset
= inst
.relocs
[0].exp
.X_add_number
;
22414 offset
= inst
.relocs
[0].exp
.X_add_number
;
22417 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
22421 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
22422 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
22423 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
22426 /* Write a 32-bit thumb instruction to buf. */
22428 put_thumb32_insn (char * buf
, unsigned long insn
)
22430 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
22431 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
22435 output_inst (const char * str
)
22441 as_bad ("%s -- `%s'", inst
.error
, str
);
22446 output_relax_insn ();
22449 if (inst
.size
== 0)
22452 to
= frag_more (inst
.size
);
22453 /* PR 9814: Record the thumb mode into the current frag so that we know
22454 what type of NOP padding to use, if necessary. We override any previous
22455 setting so that if the mode has changed then the NOPS that we use will
22456 match the encoding of the last instruction in the frag. */
22457 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22459 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
22461 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
22462 put_thumb32_insn (to
, inst
.instruction
);
22464 else if (inst
.size
> INSN_SIZE
)
22466 gas_assert (inst
.size
== (2 * INSN_SIZE
));
22467 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
22468 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
22471 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
22474 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22476 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
22477 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
22478 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
22479 inst
.relocs
[r
].type
);
22482 dwarf2_emit_insn (inst
.size
);
22486 output_it_inst (int cond
, int mask
, char * to
)
22488 unsigned long instruction
= 0xbf00;
22491 instruction
|= mask
;
22492 instruction
|= cond
<< 4;
22496 to
= frag_more (2);
22498 dwarf2_emit_insn (2);
22502 md_number_to_chars (to
, instruction
, 2);
22507 /* Tag values used in struct asm_opcode's tag field. */
22510 OT_unconditional
, /* Instruction cannot be conditionalized.
22511 The ARM condition field is still 0xE. */
22512 OT_unconditionalF
, /* Instruction cannot be conditionalized
22513 and carries 0xF in its ARM condition field. */
22514 OT_csuffix
, /* Instruction takes a conditional suffix. */
22515 OT_csuffixF
, /* Some forms of the instruction take a scalar
22516 conditional suffix, others place 0xF where the
22517 condition field would be, others take a vector
22518 conditional suffix. */
22519 OT_cinfix3
, /* Instruction takes a conditional infix,
22520 beginning at character index 3. (In
22521 unified mode, it becomes a suffix.) */
22522 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
22523 tsts, cmps, cmns, and teqs. */
22524 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
22525 character index 3, even in unified mode. Used for
22526 legacy instructions where suffix and infix forms
22527 may be ambiguous. */
22528 OT_csuf_or_in3
, /* Instruction takes either a conditional
22529 suffix or an infix at character index 3. */
22530 OT_odd_infix_unc
, /* This is the unconditional variant of an
22531 instruction that takes a conditional infix
22532 at an unusual position. In unified mode,
22533 this variant will accept a suffix. */
22534 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
22535 are the conditional variants of instructions that
22536 take conditional infixes in unusual positions.
22537 The infix appears at character index
22538 (tag - OT_odd_infix_0). These are not accepted
22539 in unified mode. */
22542 /* Subroutine of md_assemble, responsible for looking up the primary
22543 opcode from the mnemonic the user wrote. STR points to the
22544 beginning of the mnemonic.
22546 This is not simply a hash table lookup, because of conditional
22547 variants. Most instructions have conditional variants, which are
22548 expressed with a _conditional affix_ to the mnemonic. If we were
22549 to encode each conditional variant as a literal string in the opcode
22550 table, it would have approximately 20,000 entries.
22552 Most mnemonics take this affix as a suffix, and in unified syntax,
22553 'most' is upgraded to 'all'. However, in the divided syntax, some
22554 instructions take the affix as an infix, notably the s-variants of
22555 the arithmetic instructions. Of those instructions, all but six
22556 have the infix appear after the third character of the mnemonic.
22558 Accordingly, the algorithm for looking up primary opcodes given
22561 1. Look up the identifier in the opcode table.
22562 If we find a match, go to step U.
22564 2. Look up the last two characters of the identifier in the
22565 conditions table. If we find a match, look up the first N-2
22566 characters of the identifier in the opcode table. If we
22567 find a match, go to step CE.
22569 3. Look up the fourth and fifth characters of the identifier in
22570 the conditions table. If we find a match, extract those
22571 characters from the identifier, and look up the remaining
22572 characters in the opcode table. If we find a match, go
22577 U. Examine the tag field of the opcode structure, in case this is
22578 one of the six instructions with its conditional infix in an
22579 unusual place. If it is, the tag tells us where to find the
22580 infix; look it up in the conditions table and set inst.cond
22581 accordingly. Otherwise, this is an unconditional instruction.
22582 Again set inst.cond accordingly. Return the opcode structure.
22584 CE. Examine the tag field to make sure this is an instruction that
22585 should receive a conditional suffix. If it is not, fail.
22586 Otherwise, set inst.cond from the suffix we already looked up,
22587 and return the opcode structure.
22589 CM. Examine the tag field to make sure this is an instruction that
22590 should receive a conditional infix after the third character.
22591 If it is not, fail. Otherwise, undo the edits to the current
22592 line of input and proceed as for case CE. */
22594 static const struct asm_opcode
*
22595 opcode_lookup (char **str
)
22599 const struct asm_opcode
*opcode
;
22600 const struct asm_cond
*cond
;
22603 /* Scan up to the end of the mnemonic, which must end in white space,
22604 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
22605 for (base
= end
= *str
; *end
!= '\0'; end
++)
22606 if (*end
== ' ' || *end
== '.')
22612 /* Handle a possible width suffix and/or Neon type suffix. */
22617 /* The .w and .n suffixes are only valid if the unified syntax is in
22619 if (unified_syntax
&& end
[1] == 'w')
22621 else if (unified_syntax
&& end
[1] == 'n')
22626 inst
.vectype
.elems
= 0;
22628 *str
= end
+ offset
;
22630 if (end
[offset
] == '.')
22632 /* See if we have a Neon type suffix (possible in either unified or
22633 non-unified ARM syntax mode). */
22634 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
22637 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
22643 /* Look for unaffixed or special-case affixed mnemonic. */
22644 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22650 if (opcode
->tag
< OT_odd_infix_0
)
22652 inst
.cond
= COND_ALWAYS
;
22656 if (warn_on_deprecated
&& unified_syntax
)
22657 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22658 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
22659 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22662 inst
.cond
= cond
->value
;
22665 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
22667 /* Cannot have a conditional suffix on a mnemonic of less than a character.
22669 if (end
- base
< 2)
22672 cond
= (const struct asm_cond
*) str_hash_find_n (arm_vcond_hsh
, affix
, 1);
22673 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22675 /* If this opcode can not be vector predicated then don't accept it with a
22676 vector predication code. */
22677 if (opcode
&& !opcode
->mayBeVecPred
)
22680 if (!opcode
|| !cond
)
22682 /* Cannot have a conditional suffix on a mnemonic of less than two
22684 if (end
- base
< 3)
22687 /* Look for suffixed mnemonic. */
22689 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22690 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22694 if (opcode
&& cond
)
22697 switch (opcode
->tag
)
22699 case OT_cinfix3_legacy
:
22700 /* Ignore conditional suffixes matched on infix only mnemonics. */
22704 case OT_cinfix3_deprecated
:
22705 case OT_odd_infix_unc
:
22706 if (!unified_syntax
)
22708 /* Fall through. */
22712 case OT_csuf_or_in3
:
22713 inst
.cond
= cond
->value
;
22716 case OT_unconditional
:
22717 case OT_unconditionalF
:
22719 inst
.cond
= cond
->value
;
22722 /* Delayed diagnostic. */
22723 inst
.error
= BAD_COND
;
22724 inst
.cond
= COND_ALWAYS
;
22733 /* Cannot have a usual-position infix on a mnemonic of less than
22734 six characters (five would be a suffix). */
22735 if (end
- base
< 6)
22738 /* Look for infixed mnemonic in the usual position. */
22740 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22744 memcpy (save
, affix
, 2);
22745 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
22746 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22748 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
22749 memcpy (affix
, save
, 2);
22752 && (opcode
->tag
== OT_cinfix3
22753 || opcode
->tag
== OT_cinfix3_deprecated
22754 || opcode
->tag
== OT_csuf_or_in3
22755 || opcode
->tag
== OT_cinfix3_legacy
))
22758 if (warn_on_deprecated
&& unified_syntax
22759 && (opcode
->tag
== OT_cinfix3
22760 || opcode
->tag
== OT_cinfix3_deprecated
))
22761 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22763 inst
.cond
= cond
->value
;
22770 /* This function generates an initial IT instruction, leaving its block
22771 virtually open for the new instructions. Eventually,
22772 the mask will be updated by now_pred_add_mask () each time
22773 a new instruction needs to be included in the IT block.
22774 Finally, the block is closed with close_automatic_it_block ().
22775 The block closure can be requested either from md_assemble (),
22776 a tencode (), or due to a label hook. */
22779 new_automatic_it_block (int cond
)
22781 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
22782 now_pred
.mask
= 0x18;
22783 now_pred
.cc
= cond
;
22784 now_pred
.block_length
= 1;
22785 mapping_state (MAP_THUMB
);
22786 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
22787 now_pred
.warn_deprecated
= false;
22788 now_pred
.insn_cond
= true;
22791 /* Close an automatic IT block.
22792 See comments in new_automatic_it_block (). */
22795 close_automatic_it_block (void)
22797 now_pred
.mask
= 0x10;
22798 now_pred
.block_length
= 0;
22801 /* Update the mask of the current automatically-generated IT
22802 instruction. See comments in new_automatic_it_block (). */
22805 now_pred_add_mask (int cond
)
22807 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
22808 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
22809 | ((bitvalue) << (nbit)))
22810 const int resulting_bit
= (cond
& 1);
22812 now_pred
.mask
&= 0xf;
22813 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22815 (5 - now_pred
.block_length
));
22816 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22818 ((5 - now_pred
.block_length
) - 1));
22819 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
22822 #undef SET_BIT_VALUE
22825 /* The IT blocks handling machinery is accessed through the these functions:
22826 it_fsm_pre_encode () from md_assemble ()
22827 set_pred_insn_type () optional, from the tencode functions
22828 set_pred_insn_type_last () ditto
22829 in_pred_block () ditto
22830 it_fsm_post_encode () from md_assemble ()
22831 force_automatic_it_block_close () from label handling functions
22834 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22835 initializing the IT insn type with a generic initial value depending
22836 on the inst.condition.
22837 2) During the tencode function, two things may happen:
22838 a) The tencode function overrides the IT insn type by
22839 calling either set_pred_insn_type (type) or
22840 set_pred_insn_type_last ().
22841 b) The tencode function queries the IT block state by
22842 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22844 Both set_pred_insn_type and in_pred_block run the internal FSM state
22845 handling function (handle_pred_state), because: a) setting the IT insn
22846 type may incur in an invalid state (exiting the function),
22847 and b) querying the state requires the FSM to be updated.
22848 Specifically we want to avoid creating an IT block for conditional
22849 branches, so it_fsm_pre_encode is actually a guess and we can't
22850 determine whether an IT block is required until the tencode () routine
22851 has decided what type of instruction this actually it.
22852 Because of this, if set_pred_insn_type and in_pred_block have to be
22853 used, set_pred_insn_type has to be called first.
22855 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22856 that determines the insn IT type depending on the inst.cond code.
22857 When a tencode () routine encodes an instruction that can be
22858 either outside an IT block, or, in the case of being inside, has to be
22859 the last one, set_pred_insn_type_last () will determine the proper
22860 IT instruction type based on the inst.cond code. Otherwise,
22861 set_pred_insn_type can be called for overriding that logic or
22862 for covering other cases.
22864 Calling handle_pred_state () may not transition the IT block state to
22865 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22866 still queried. Instead, if the FSM determines that the state should
22867 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22868 after the tencode () function: that's what it_fsm_post_encode () does.
22870 Since in_pred_block () calls the state handling function to get an
22871 updated state, an error may occur (due to invalid insns combination).
22872 In that case, inst.error is set.
22873 Therefore, inst.error has to be checked after the execution of
22874 the tencode () routine.
22876 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22877 any pending state change (if any) that didn't take place in
22878 handle_pred_state () as explained above. */
22881 it_fsm_pre_encode (void)
22883 if (inst
.cond
!= COND_ALWAYS
)
22884 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22886 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22888 now_pred
.state_handled
= 0;
22891 /* IT state FSM handling function. */
22892 /* MVE instructions and non-MVE instructions are handled differently because of
22893 the introduction of VPT blocks.
22894 Specifications say that any non-MVE instruction inside a VPT block is
22895 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22896 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22897 few exceptions we have MVE_UNPREDICABLE_INSN.
22898 The error messages provided depending on the different combinations possible
22899 are described in the cases below:
22900 For 'most' MVE instructions:
22901 1) In an IT block, with an IT code: syntax error
22902 2) In an IT block, with a VPT code: error: must be in a VPT block
22903 3) In an IT block, with no code: warning: UNPREDICTABLE
22904 4) In a VPT block, with an IT code: syntax error
22905 5) In a VPT block, with a VPT code: OK!
22906 6) In a VPT block, with no code: error: missing code
22907 7) Outside a pred block, with an IT code: error: syntax error
22908 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22909 9) Outside a pred block, with no code: OK!
22910 For non-MVE instructions:
22911 10) In an IT block, with an IT code: OK!
22912 11) In an IT block, with a VPT code: syntax error
22913 12) In an IT block, with no code: error: missing code
22914 13) In a VPT block, with an IT code: error: should be in an IT block
22915 14) In a VPT block, with a VPT code: syntax error
22916 15) In a VPT block, with no code: UNPREDICTABLE
22917 16) Outside a pred block, with an IT code: error: should be in an IT block
22918 17) Outside a pred block, with a VPT code: syntax error
22919 18) Outside a pred block, with no code: OK!
22924 handle_pred_state (void)
22926 now_pred
.state_handled
= 1;
22927 now_pred
.insn_cond
= false;
22929 switch (now_pred
.state
)
22931 case OUTSIDE_PRED_BLOCK
:
22932 switch (inst
.pred_insn_type
)
22934 case MVE_UNPREDICABLE_INSN
:
22935 case MVE_OUTSIDE_PRED_INSN
:
22936 if (inst
.cond
< COND_ALWAYS
)
22938 /* Case 7: Outside a pred block, with an IT code: error: syntax
22940 inst
.error
= BAD_SYNTAX
;
22943 /* Case 9: Outside a pred block, with no code: OK! */
22945 case OUTSIDE_PRED_INSN
:
22946 if (inst
.cond
> COND_ALWAYS
)
22948 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22950 inst
.error
= BAD_SYNTAX
;
22953 /* Case 18: Outside a pred block, with no code: OK! */
22956 case INSIDE_VPT_INSN
:
22957 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22959 inst
.error
= BAD_OUT_VPT
;
22962 case INSIDE_IT_INSN
:
22963 case INSIDE_IT_LAST_INSN
:
22964 if (inst
.cond
< COND_ALWAYS
)
22966 /* Case 16: Outside a pred block, with an IT code: error: should
22967 be in an IT block. */
22968 if (thumb_mode
== 0)
22971 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22972 as_tsktsk (_("Warning: conditional outside an IT block"\
22977 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22978 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22980 /* Automatically generate the IT instruction. */
22981 new_automatic_it_block (inst
.cond
);
22982 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22983 close_automatic_it_block ();
22987 inst
.error
= BAD_OUT_IT
;
22993 else if (inst
.cond
> COND_ALWAYS
)
22995 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22997 inst
.error
= BAD_SYNTAX
;
23002 case IF_INSIDE_IT_LAST_INSN
:
23003 case NEUTRAL_IT_INSN
:
23007 if (inst
.cond
!= COND_ALWAYS
)
23008 first_error (BAD_SYNTAX
);
23009 now_pred
.state
= MANUAL_PRED_BLOCK
;
23010 now_pred
.block_length
= 0;
23011 now_pred
.type
= VECTOR_PRED
;
23015 now_pred
.state
= MANUAL_PRED_BLOCK
;
23016 now_pred
.block_length
= 0;
23017 now_pred
.type
= SCALAR_PRED
;
23022 case AUTOMATIC_PRED_BLOCK
:
23023 /* Three things may happen now:
23024 a) We should increment current it block size;
23025 b) We should close current it block (closing insn or 4 insns);
23026 c) We should close current it block and start a new one (due
23027 to incompatible conditions or
23028 4 insns-length block reached). */
23030 switch (inst
.pred_insn_type
)
23032 case INSIDE_VPT_INSN
:
23034 case MVE_UNPREDICABLE_INSN
:
23035 case MVE_OUTSIDE_PRED_INSN
:
23037 case OUTSIDE_PRED_INSN
:
23038 /* The closure of the block shall happen immediately,
23039 so any in_pred_block () call reports the block as closed. */
23040 force_automatic_it_block_close ();
23043 case INSIDE_IT_INSN
:
23044 case INSIDE_IT_LAST_INSN
:
23045 case IF_INSIDE_IT_LAST_INSN
:
23046 now_pred
.block_length
++;
23048 if (now_pred
.block_length
> 4
23049 || !now_pred_compatible (inst
.cond
))
23051 force_automatic_it_block_close ();
23052 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
23053 new_automatic_it_block (inst
.cond
);
23057 now_pred
.insn_cond
= true;
23058 now_pred_add_mask (inst
.cond
);
23061 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
23062 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
23063 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
23064 close_automatic_it_block ();
23068 case NEUTRAL_IT_INSN
:
23069 now_pred
.block_length
++;
23070 now_pred
.insn_cond
= true;
23072 if (now_pred
.block_length
> 4)
23073 force_automatic_it_block_close ();
23075 now_pred_add_mask (now_pred
.cc
& 1);
23079 close_automatic_it_block ();
23080 now_pred
.state
= MANUAL_PRED_BLOCK
;
23085 case MANUAL_PRED_BLOCK
:
23089 if (now_pred
.type
== SCALAR_PRED
)
23091 /* Check conditional suffixes. */
23092 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
23093 now_pred
.mask
<<= 1;
23094 now_pred
.mask
&= 0x1f;
23095 is_last
= (now_pred
.mask
== 0x10);
23099 now_pred
.cc
^= (now_pred
.mask
>> 4);
23100 cond
= now_pred
.cc
+ 0xf;
23101 now_pred
.mask
<<= 1;
23102 now_pred
.mask
&= 0x1f;
23103 is_last
= now_pred
.mask
== 0x10;
23105 now_pred
.insn_cond
= true;
23107 switch (inst
.pred_insn_type
)
23109 case OUTSIDE_PRED_INSN
:
23110 if (now_pred
.type
== SCALAR_PRED
)
23112 if (inst
.cond
== COND_ALWAYS
)
23114 /* Case 12: In an IT block, with no code: error: missing
23116 inst
.error
= BAD_NOT_IT
;
23119 else if (inst
.cond
> COND_ALWAYS
)
23121 /* Case 11: In an IT block, with a VPT code: syntax error.
23123 inst
.error
= BAD_SYNTAX
;
23126 else if (thumb_mode
)
23128 /* This is for some special cases where a non-MVE
23129 instruction is not allowed in an IT block, such as cbz,
23130 but are put into one with a condition code.
23131 You could argue this should be a syntax error, but we
23132 gave the 'not allowed in IT block' diagnostic in the
23133 past so we will keep doing so. */
23134 inst
.error
= BAD_NOT_IT
;
23141 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
23142 as_tsktsk (MVE_NOT_VPT
);
23145 case MVE_OUTSIDE_PRED_INSN
:
23146 if (now_pred
.type
== SCALAR_PRED
)
23148 if (inst
.cond
== COND_ALWAYS
)
23150 /* Case 3: In an IT block, with no code: warning:
23152 as_tsktsk (MVE_NOT_IT
);
23155 else if (inst
.cond
< COND_ALWAYS
)
23157 /* Case 1: In an IT block, with an IT code: syntax error.
23159 inst
.error
= BAD_SYNTAX
;
23167 if (inst
.cond
< COND_ALWAYS
)
23169 /* Case 4: In a VPT block, with an IT code: syntax error.
23171 inst
.error
= BAD_SYNTAX
;
23174 else if (inst
.cond
== COND_ALWAYS
)
23176 /* Case 6: In a VPT block, with no code: error: missing
23178 inst
.error
= BAD_NOT_VPT
;
23186 case MVE_UNPREDICABLE_INSN
:
23187 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
23189 case INSIDE_IT_INSN
:
23190 if (inst
.cond
> COND_ALWAYS
)
23192 /* Case 11: In an IT block, with a VPT code: syntax error. */
23193 /* Case 14: In a VPT block, with a VPT code: syntax error. */
23194 inst
.error
= BAD_SYNTAX
;
23197 else if (now_pred
.type
== SCALAR_PRED
)
23199 /* Case 10: In an IT block, with an IT code: OK! */
23200 if (cond
!= inst
.cond
)
23202 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
23209 /* Case 13: In a VPT block, with an IT code: error: should be
23211 inst
.error
= BAD_OUT_IT
;
23216 case INSIDE_VPT_INSN
:
23217 if (now_pred
.type
== SCALAR_PRED
)
23219 /* Case 2: In an IT block, with a VPT code: error: must be in a
23221 inst
.error
= BAD_OUT_VPT
;
23224 /* Case 5: In a VPT block, with a VPT code: OK! */
23225 else if (cond
!= inst
.cond
)
23227 inst
.error
= BAD_VPT_COND
;
23231 case INSIDE_IT_LAST_INSN
:
23232 case IF_INSIDE_IT_LAST_INSN
:
23233 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
23235 /* Case 4: In a VPT block, with an IT code: syntax error. */
23236 /* Case 11: In an IT block, with a VPT code: syntax error. */
23237 inst
.error
= BAD_SYNTAX
;
23240 else if (cond
!= inst
.cond
)
23242 inst
.error
= BAD_IT_COND
;
23247 inst
.error
= BAD_BRANCH
;
23252 case NEUTRAL_IT_INSN
:
23253 /* The BKPT instruction is unconditional even in a IT or VPT
23258 if (now_pred
.type
== SCALAR_PRED
)
23260 inst
.error
= BAD_IT_IT
;
23263 /* fall through. */
23265 if (inst
.cond
== COND_ALWAYS
)
23267 /* Executing a VPT/VPST instruction inside an IT block or a
23268 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
23270 if (now_pred
.type
== SCALAR_PRED
)
23271 as_tsktsk (MVE_NOT_IT
);
23273 as_tsktsk (MVE_NOT_VPT
);
23278 /* VPT/VPST do not accept condition codes. */
23279 inst
.error
= BAD_SYNTAX
;
23290 struct depr_insn_mask
23292 unsigned long pattern
;
23293 unsigned long mask
;
23294 const char* description
;
23297 /* List of 16-bit instruction patterns deprecated in an IT block in
23299 static const struct depr_insn_mask depr_it_insns
[] = {
23300 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
23301 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
23302 { 0xa000, 0xb800, N_("ADR") },
23303 { 0x4800, 0xf800, N_("Literal loads") },
23304 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
23305 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
23306 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
23307 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
23308 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
23313 it_fsm_post_encode (void)
23317 if (!now_pred
.state_handled
)
23318 handle_pred_state ();
23320 if (now_pred
.insn_cond
23321 && warn_on_restrict_it
23322 && !now_pred
.warn_deprecated
23323 && warn_on_deprecated
23324 && (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
23325 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8r
))
23326 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
23328 if (inst
.instruction
>= 0x10000)
23330 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
23331 "performance deprecated in ARMv8-A and ARMv8-R"));
23332 now_pred
.warn_deprecated
= true;
23336 const struct depr_insn_mask
*p
= depr_it_insns
;
23338 while (p
->mask
!= 0)
23340 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
23342 as_tsktsk (_("IT blocks containing 16-bit Thumb "
23343 "instructions of the following class are "
23344 "performance deprecated in ARMv8-A and "
23345 "ARMv8-R: %s"), p
->description
);
23346 now_pred
.warn_deprecated
= true;
23354 if (now_pred
.block_length
> 1)
23356 as_tsktsk (_("IT blocks containing more than one conditional "
23357 "instruction are performance deprecated in ARMv8-A and "
23359 now_pred
.warn_deprecated
= true;
23363 is_last
= (now_pred
.mask
== 0x10);
23366 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23372 force_automatic_it_block_close (void)
23374 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
23376 close_automatic_it_block ();
23377 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23383 in_pred_block (void)
23385 if (!now_pred
.state_handled
)
23386 handle_pred_state ();
23388 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
23391 /* Whether OPCODE only has T32 encoding. Since this function is only used by
23392 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
23393 here, hence the "known" in the function name. */
23396 known_t32_only_insn (const struct asm_opcode
*opcode
)
23398 /* Original Thumb-1 wide instruction. */
23399 if (opcode
->tencode
== do_t_blx
23400 || opcode
->tencode
== do_t_branch23
23401 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
23402 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
23405 /* Wide-only instruction added to ARMv8-M Baseline. */
23406 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
23407 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
23408 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
23409 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
23415 /* Whether wide instruction variant can be used if available for a valid OPCODE
23419 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
23421 if (known_t32_only_insn (opcode
))
23424 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
23425 of variant T3 of B.W is checked in do_t_branch. */
23426 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23427 && opcode
->tencode
== do_t_branch
)
23430 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
23431 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23432 && opcode
->tencode
== do_t_mov_cmp
23433 /* Make sure CMP instruction is not affected. */
23434 && opcode
->aencode
== do_mov
)
23437 /* Wide instruction variants of all instructions with narrow *and* wide
23438 variants become available with ARMv6t2. Other opcodes are either
23439 narrow-only or wide-only and are thus available if OPCODE is valid. */
23440 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
23443 /* OPCODE with narrow only instruction variant or wide variant not
23449 md_assemble (char *str
)
23452 const struct asm_opcode
* opcode
;
23454 /* Align the previous label if needed. */
23455 if (last_label_seen
!= NULL
)
23457 symbol_set_frag (last_label_seen
, frag_now
);
23458 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
23459 S_SET_SEGMENT (last_label_seen
, now_seg
);
23462 memset (&inst
, '\0', sizeof (inst
));
23464 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
23465 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
23467 opcode
= opcode_lookup (&p
);
23470 /* It wasn't an instruction, but it might be a register alias of
23471 the form alias .req reg, or a Neon .dn/.qn directive. */
23472 if (! create_register_alias (str
, p
)
23473 && ! create_neon_reg_alias (str
, p
))
23474 as_bad (_("bad instruction `%s'"), str
);
23479 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
23480 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
23482 /* The value which unconditional instructions should have in place of the
23483 condition field. */
23484 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1u;
23488 arm_feature_set variant
;
23490 variant
= cpu_variant
;
23491 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
23492 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
23493 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
23494 /* Check that this instruction is supported for this CPU. */
23495 if (!opcode
->tvariant
23496 || (thumb_mode
== 1
23497 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
23499 if (opcode
->tencode
== do_t_swi
)
23500 as_bad (_("SVC is not permitted on this architecture"));
23502 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
23505 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
23506 && opcode
->tencode
!= do_t_branch
)
23508 as_bad (_("Thumb does not support conditional execution"));
23512 /* Two things are addressed here:
23513 1) Implicit require narrow instructions on Thumb-1.
23514 This avoids relaxation accidentally introducing Thumb-2
23516 2) Reject wide instructions in non Thumb-2 cores.
23518 Only instructions with narrow and wide variants need to be handled
23519 but selecting all non wide-only instructions is easier. */
23520 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
23521 && !t32_insn_ok (variant
, opcode
))
23523 if (inst
.size_req
== 0)
23525 else if (inst
.size_req
== 4)
23527 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
23528 as_bad (_("selected processor does not support 32bit wide "
23529 "variant of instruction `%s'"), str
);
23531 as_bad (_("selected processor does not support `%s' in "
23532 "Thumb-2 mode"), str
);
23537 inst
.instruction
= opcode
->tvalue
;
23539 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/true))
23541 /* Prepare the pred_insn_type for those encodings that don't set
23543 it_fsm_pre_encode ();
23545 opcode
->tencode ();
23547 it_fsm_post_encode ();
23550 if (!(inst
.error
|| inst
.relax
))
23552 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
23553 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
23554 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
23556 as_bad (_("cannot honor width suffix -- `%s'"), str
);
23561 /* Something has gone badly wrong if we try to relax a fixed size
23563 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
23565 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23566 *opcode
->tvariant
);
23567 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
23568 set those bits when Thumb-2 32-bit instructions are seen. The impact
23569 of relaxable instructions will be considered later after we finish all
23571 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
23572 variant
= arm_arch_none
;
23574 variant
= cpu_variant
;
23575 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
23576 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23579 check_neon_suffixes
;
23583 mapping_state (MAP_THUMB
);
23586 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23590 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23591 is_bx
= (opcode
->aencode
== do_bx
);
23593 /* Check that this instruction is supported for this CPU. */
23594 if (!(is_bx
&& fix_v4bx
)
23595 && !(opcode
->avariant
&&
23596 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
23598 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
23603 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
23607 inst
.instruction
= opcode
->avalue
;
23608 if (opcode
->tag
== OT_unconditionalF
)
23609 inst
.instruction
|= 0xFU
<< 28;
23611 inst
.instruction
|= inst
.cond
<< 28;
23612 inst
.size
= INSN_SIZE
;
23613 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/false))
23615 it_fsm_pre_encode ();
23616 opcode
->aencode ();
23617 it_fsm_post_encode ();
23619 /* Arm mode bx is marked as both v4T and v5 because it's still required
23620 on a hypothetical non-thumb v5 core. */
23622 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
23624 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
23625 *opcode
->avariant
);
23627 check_neon_suffixes
;
23631 mapping_state (MAP_ARM
);
23636 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
23644 check_pred_blocks_finished (void)
23649 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
23650 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
23651 == MANUAL_PRED_BLOCK
)
23653 if (now_pred
.type
== SCALAR_PRED
)
23654 as_warn (_("section '%s' finished with an open IT block."),
23657 as_warn (_("section '%s' finished with an open VPT/VPST block."),
23661 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
23663 if (now_pred
.type
== SCALAR_PRED
)
23664 as_warn (_("file finished with an open IT block."));
23666 as_warn (_("file finished with an open VPT/VPST block."));
23671 /* Various frobbings of labels and their addresses. */
23674 arm_start_line_hook (void)
23676 last_label_seen
= NULL
;
23680 arm_frob_label (symbolS
* sym
)
23682 last_label_seen
= sym
;
23684 ARM_SET_THUMB (sym
, thumb_mode
);
23686 #if defined OBJ_COFF || defined OBJ_ELF
23687 ARM_SET_INTERWORK (sym
, support_interwork
);
23690 force_automatic_it_block_close ();
23692 /* Note - do not allow local symbols (.Lxxx) to be labelled
23693 as Thumb functions. This is because these labels, whilst
23694 they exist inside Thumb code, are not the entry points for
23695 possible ARM->Thumb calls. Also, these labels can be used
23696 as part of a computed goto or switch statement. eg gcc
23697 can generate code that looks like this:
23699 ldr r2, [pc, .Laaa]
23709 The first instruction loads the address of the jump table.
23710 The second instruction converts a table index into a byte offset.
23711 The third instruction gets the jump address out of the table.
23712 The fourth instruction performs the jump.
23714 If the address stored at .Laaa is that of a symbol which has the
23715 Thumb_Func bit set, then the linker will arrange for this address
23716 to have the bottom bit set, which in turn would mean that the
23717 address computation performed by the third instruction would end
23718 up with the bottom bit set. Since the ARM is capable of unaligned
23719 word loads, the instruction would then load the incorrect address
23720 out of the jump table, and chaos would ensue. */
23721 if (label_is_thumb_function_name
23722 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
23723 && (bfd_section_flags (now_seg
) & SEC_CODE
) != 0)
23725 /* When the address of a Thumb function is taken the bottom
23726 bit of that address should be set. This will allow
23727 interworking between Arm and Thumb functions to work
23730 THUMB_SET_FUNC (sym
, 1);
23732 label_is_thumb_function_name
= false;
23735 dwarf2_emit_label (sym
);
23739 arm_data_in_code (void)
23741 if (thumb_mode
&& startswith (input_line_pointer
+ 1, "data:"))
23743 *input_line_pointer
= '/';
23744 input_line_pointer
+= 5;
23745 *input_line_pointer
= 0;
23753 arm_canonicalize_symbol_name (char * name
)
23757 if (thumb_mode
&& (len
= strlen (name
)) > 5
23758 && streq (name
+ len
- 5, "/data"))
23759 *(name
+ len
- 5) = 0;
23764 /* Table of all register names defined by default. The user can
23765 define additional names with .req. Note that all register names
23766 should appear in both upper and lowercase variants. Some registers
23767 also have mixed-case names. */
23769 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true, 0 }
23770 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
23771 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
23772 #define REGSET(p,t) \
23773 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23774 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23775 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23776 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
23777 #define REGSETH(p,t) \
23778 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23779 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23780 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23781 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23782 #define REGSET2(p,t) \
23783 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23784 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23785 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23786 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
23787 #define SPLRBANK(base,bank,t) \
23788 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23789 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23790 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23791 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23792 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23793 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
23795 static const struct reg_entry reg_names
[] =
23797 /* ARM integer registers. */
23798 REGSET(r
, RN
), REGSET(R
, RN
),
23800 /* ATPCS synonyms. */
23801 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
23802 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
23803 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
23805 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
23806 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
23807 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
23809 /* Well-known aliases. */
23810 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
23811 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
23813 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
23814 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
23816 /* Defining the new Zero register from ARMv8.1-M. */
23820 /* Coprocessor numbers. */
23821 REGSET(p
, CP
), REGSET(P
, CP
),
23823 /* Coprocessor register numbers. The "cr" variants are for backward
23825 REGSET(c
, CN
), REGSET(C
, CN
),
23826 REGSET(cr
, CN
), REGSET(CR
, CN
),
23828 /* ARM banked registers. */
23829 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
23830 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
23831 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
23832 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
23833 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
23834 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
23835 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
23837 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
23838 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
23839 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
23840 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
23841 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
23842 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
23843 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
23844 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
23846 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
23847 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
23848 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
23849 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
23850 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
23851 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
23852 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
23853 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23854 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23856 /* FPA registers. */
23857 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
23858 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
23860 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
23861 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
23863 /* VFP SP registers. */
23864 REGSET(s
,VFS
), REGSET(S
,VFS
),
23865 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
23867 /* VFP DP Registers. */
23868 REGSET(d
,VFD
), REGSET(D
,VFD
),
23869 /* Extra Neon DP registers. */
23870 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
23872 /* Neon QP registers. */
23873 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
23875 /* VFP control registers. */
23876 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
23877 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
23878 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
23879 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
23880 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
23881 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
23882 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
23883 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
23884 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
23885 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
23886 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23888 /* Maverick DSP coprocessor registers. */
23889 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23890 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23892 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23893 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23894 REGDEF(dspsc
,0,DSPSC
),
23896 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23897 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23898 REGDEF(DSPSC
,0,DSPSC
),
23900 /* iWMMXt data registers - p0, c0-15. */
23901 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23903 /* iWMMXt control registers - p1, c0-3. */
23904 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23905 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23906 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23907 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23909 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23910 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23911 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23912 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23913 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23915 /* XScale accumulator registers. */
23916 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23918 /* Alias 'ra_auth_code' to r12 for pacbti. */
23919 REGDEF(ra_auth_code
,12,RN
),
23925 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23926 within psr_required_here. */
23927 static const struct asm_psr psrs
[] =
23929 /* Backward compatibility notation. Note that "all" is no longer
23930 truly all possible PSR bits. */
23931 {"all", PSR_c
| PSR_f
},
23935 /* Individual flags. */
23941 /* Combinations of flags. */
23942 {"fs", PSR_f
| PSR_s
},
23943 {"fx", PSR_f
| PSR_x
},
23944 {"fc", PSR_f
| PSR_c
},
23945 {"sf", PSR_s
| PSR_f
},
23946 {"sx", PSR_s
| PSR_x
},
23947 {"sc", PSR_s
| PSR_c
},
23948 {"xf", PSR_x
| PSR_f
},
23949 {"xs", PSR_x
| PSR_s
},
23950 {"xc", PSR_x
| PSR_c
},
23951 {"cf", PSR_c
| PSR_f
},
23952 {"cs", PSR_c
| PSR_s
},
23953 {"cx", PSR_c
| PSR_x
},
23954 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23955 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23956 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23957 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23958 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23959 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23960 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23961 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23962 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23963 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23964 {"scf", PSR_s
| PSR_c
| PSR_f
},
23965 {"scx", PSR_s
| PSR_c
| PSR_x
},
23966 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23967 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23968 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23969 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23970 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23971 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23972 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23973 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23974 {"csf", PSR_c
| PSR_s
| PSR_f
},
23975 {"csx", PSR_c
| PSR_s
| PSR_x
},
23976 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23977 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23978 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23979 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23980 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23981 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23982 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23983 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23984 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23985 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23986 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23987 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23988 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23989 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23990 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23991 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23992 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23993 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23994 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23995 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23996 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23997 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23998 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23999 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
24000 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
24001 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
24004 /* Table of V7M psr names. */
24005 static const struct asm_psr v7m_psrs
[] =
24007 {"apsr", 0x0 }, {"APSR", 0x0 },
24008 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
24009 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
24010 {"psr", 0x3 }, {"PSR", 0x3 },
24011 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
24012 {"ipsr", 0x5 }, {"IPSR", 0x5 },
24013 {"epsr", 0x6 }, {"EPSR", 0x6 },
24014 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
24015 {"msp", 0x8 }, {"MSP", 0x8 },
24016 {"psp", 0x9 }, {"PSP", 0x9 },
24017 {"msplim", 0xa }, {"MSPLIM", 0xa },
24018 {"psplim", 0xb }, {"PSPLIM", 0xb },
24019 {"primask", 0x10}, {"PRIMASK", 0x10},
24020 {"basepri", 0x11}, {"BASEPRI", 0x11},
24021 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
24022 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
24023 {"control", 0x14}, {"CONTROL", 0x14},
24024 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
24025 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
24026 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
24027 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
24028 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
24029 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
24030 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
24031 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
24032 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
24035 /* Table of all shift-in-operand names. */
24036 static const struct asm_shift_name shift_names
[] =
24038 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
24039 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
24040 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
24041 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
24042 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
24043 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
24044 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
24047 /* Table of all explicit relocation names. */
24049 static struct reloc_entry reloc_names
[] =
24051 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
24052 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
24053 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
24054 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
24055 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
24056 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
24057 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
24058 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
24059 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
24060 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
24061 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
24062 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
24063 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
24064 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
24065 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
24066 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
24067 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
24068 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
24069 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
24070 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
24071 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24072 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24073 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
24074 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
24075 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
24076 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
24077 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
24081 /* Table of all conditional affixes. */
24082 static const struct asm_cond conds
[] =
24086 {"cs", 0x2}, {"hs", 0x2},
24087 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
24100 static const struct asm_cond vconds
[] =
24106 #define UL_BARRIER(L,U,CODE,FEAT) \
24107 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
24108 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
24110 static struct asm_barrier_opt barrier_opt_names
[] =
24112 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
24113 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
24114 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
24115 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
24116 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
24117 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
24118 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
24119 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
24120 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
24121 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
24122 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
24123 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
24124 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
24125 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
24126 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
24127 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
24132 /* Table of ARM-format instructions. */
24134 /* Macros for gluing together operand strings. N.B. In all cases
24135 other than OPS0, the trailing OP_stop comes from default
24136 zero-initialization of the unspecified elements of the array. */
24137 #define OPS0() { OP_stop, }
24138 #define OPS1(a) { OP_##a, }
24139 #define OPS2(a,b) { OP_##a,OP_##b, }
24140 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
24141 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
24142 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
24143 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
24145 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
24146 This is useful when mixing operands for ARM and THUMB, i.e. using the
24147 MIX_ARM_THUMB_OPERANDS macro.
24148 In order to use these macros, prefix the number of operands with _
24150 #define OPS_1(a) { a, }
24151 #define OPS_2(a,b) { a,b, }
24152 #define OPS_3(a,b,c) { a,b,c, }
24153 #define OPS_4(a,b,c,d) { a,b,c,d, }
24154 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
24155 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
24157 /* These macros abstract out the exact format of the mnemonic table and
24158 save some repeated characters. */
24160 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
24161 #define TxCE(mnem, op, top, nops, ops, ae, te) \
24162 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
24163 THUMB_VARIANT, do_##ae, do_##te, 0 }
24165 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
24166 a T_MNEM_xyz enumerator. */
24167 #define TCE(mnem, aop, top, nops, ops, ae, te) \
24168 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
24169 #define tCE(mnem, aop, top, nops, ops, ae, te) \
24170 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24172 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
24173 infix after the third character. */
24174 #define TxC3(mnem, op, top, nops, ops, ae, te) \
24175 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
24176 THUMB_VARIANT, do_##ae, do_##te, 0 }
24177 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
24178 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
24179 THUMB_VARIANT, do_##ae, do_##te, 0 }
24180 #define TC3(mnem, aop, top, nops, ops, ae, te) \
24181 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
24182 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
24183 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
24184 #define tC3(mnem, aop, top, nops, ops, ae, te) \
24185 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24186 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
24187 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24189 /* Mnemonic that cannot be conditionalized. The ARM condition-code
24190 field is still 0xE. Many of the Thumb variants can be executed
24191 conditionally, so this is checked separately. */
24192 #define TUE(mnem, op, top, nops, ops, ae, te) \
24193 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24194 THUMB_VARIANT, do_##ae, do_##te, 0 }
24196 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
24197 Used by mnemonics that have very minimal differences in the encoding for
24198 ARM and Thumb variants and can be handled in a common function. */
24199 #define TUEc(mnem, op, top, nops, ops, en) \
24200 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24201 THUMB_VARIANT, do_##en, do_##en, 0 }
24203 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
24204 condition code field. */
24205 #define TUF(mnem, op, top, nops, ops, ae, te) \
24206 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
24207 THUMB_VARIANT, do_##ae, do_##te, 0 }
24209 /* ARM-only variants of all the above. */
24210 #define CE(mnem, op, nops, ops, ae) \
24211 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24213 #define C3(mnem, op, nops, ops, ae) \
24214 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24216 /* Thumb-only variants of TCE and TUE. */
24217 #define ToC(mnem, top, nops, ops, te) \
24218 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24221 #define ToU(mnem, top, nops, ops, te) \
24222 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
24225 /* T_MNEM_xyz enumerator variants of ToC. */
24226 #define toC(mnem, top, nops, ops, te) \
24227 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
24230 /* T_MNEM_xyz enumerator variants of ToU. */
24231 #define toU(mnem, top, nops, ops, te) \
24232 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
24235 /* Legacy mnemonics that always have conditional infix after the third
24237 #define CL(mnem, op, nops, ops, ae) \
24238 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24239 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24241 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
24242 #define cCE(mnem, op, nops, ops, ae) \
24243 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24245 /* mov instructions that are shared between coprocessor and MVE. */
24246 #define mcCE(mnem, op, nops, ops, ae) \
24247 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
24249 /* Legacy coprocessor instructions where conditional infix and conditional
24250 suffix are ambiguous. For consistency this includes all FPA instructions,
24251 not just the potentially ambiguous ones. */
24252 #define cCL(mnem, op, nops, ops, ae) \
24253 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24254 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24256 /* Coprocessor, takes either a suffix or a position-3 infix
24257 (for an FPA corner case). */
24258 #define C3E(mnem, op, nops, ops, ae) \
24259 { mnem, OPS##nops ops, OT_csuf_or_in3, \
24260 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24262 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
24263 { m1 #m2 m3, OPS##nops ops, \
24264 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
24265 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24267 #define CM(m1, m2, op, nops, ops, ae) \
24268 xCM_ (m1, , m2, op, nops, ops, ae), \
24269 xCM_ (m1, eq, m2, op, nops, ops, ae), \
24270 xCM_ (m1, ne, m2, op, nops, ops, ae), \
24271 xCM_ (m1, cs, m2, op, nops, ops, ae), \
24272 xCM_ (m1, hs, m2, op, nops, ops, ae), \
24273 xCM_ (m1, cc, m2, op, nops, ops, ae), \
24274 xCM_ (m1, ul, m2, op, nops, ops, ae), \
24275 xCM_ (m1, lo, m2, op, nops, ops, ae), \
24276 xCM_ (m1, mi, m2, op, nops, ops, ae), \
24277 xCM_ (m1, pl, m2, op, nops, ops, ae), \
24278 xCM_ (m1, vs, m2, op, nops, ops, ae), \
24279 xCM_ (m1, vc, m2, op, nops, ops, ae), \
24280 xCM_ (m1, hi, m2, op, nops, ops, ae), \
24281 xCM_ (m1, ls, m2, op, nops, ops, ae), \
24282 xCM_ (m1, ge, m2, op, nops, ops, ae), \
24283 xCM_ (m1, lt, m2, op, nops, ops, ae), \
24284 xCM_ (m1, gt, m2, op, nops, ops, ae), \
24285 xCM_ (m1, le, m2, op, nops, ops, ae), \
24286 xCM_ (m1, al, m2, op, nops, ops, ae)
24288 #define UE(mnem, op, nops, ops, ae) \
24289 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24291 #define UF(mnem, op, nops, ops, ae) \
24292 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24294 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
24295 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
24296 use the same encoding function for each. */
24297 #define NUF(mnem, op, nops, ops, enc) \
24298 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24299 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24301 /* Neon data processing, version which indirects through neon_enc_tab for
24302 the various overloaded versions of opcodes. */
24303 #define nUF(mnem, op, nops, ops, enc) \
24304 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24305 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24307 /* Neon insn with conditional suffix for the ARM version, non-overloaded
24309 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24310 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
24311 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24313 #define NCE(mnem, op, nops, ops, enc) \
24314 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24316 #define NCEF(mnem, op, nops, ops, enc) \
24317 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24319 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
24320 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24321 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
24322 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24324 #define nCE(mnem, op, nops, ops, enc) \
24325 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24327 #define nCEF(mnem, op, nops, ops, enc) \
24328 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24331 #define mCEF(mnem, op, nops, ops, enc) \
24332 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
24333 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24336 /* nCEF but for MVE predicated instructions. */
24337 #define mnCEF(mnem, op, nops, ops, enc) \
24338 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24340 /* nCE but for MVE predicated instructions. */
24341 #define mnCE(mnem, op, nops, ops, enc) \
24342 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24344 /* NUF but for potentially MVE predicated instructions. */
24345 #define MNUF(mnem, op, nops, ops, enc) \
24346 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24347 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24349 /* nUF but for potentially MVE predicated instructions. */
24350 #define mnUF(mnem, op, nops, ops, enc) \
24351 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24352 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24354 /* ToC but for potentially MVE predicated instructions. */
24355 #define mToC(mnem, top, nops, ops, te) \
24356 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24359 /* NCE but for MVE predicated instructions. */
24360 #define MNCE(mnem, op, nops, ops, enc) \
24361 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24363 /* NCEF but for MVE predicated instructions. */
24364 #define MNCEF(mnem, op, nops, ops, enc) \
24365 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24368 static const struct asm_opcode insns
[] =
24370 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
24371 #define THUMB_VARIANT & arm_ext_v4t
24372 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24373 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24374 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24375 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24376 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24377 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24378 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24379 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24380 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24381 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24382 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24383 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24384 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24385 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24386 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24387 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24389 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
24390 for setting PSR flag bits. They are obsolete in V6 and do not
24391 have Thumb equivalents. */
24392 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24393 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24394 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
24395 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24396 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24397 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
24398 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24399 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24400 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
24402 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
24403 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
24404 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24405 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24407 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
24408 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24409 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
24411 OP_ADDRGLDR
),ldst
, t_ldst
),
24412 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24414 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24415 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24416 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24417 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24418 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24419 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24421 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
24422 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
24425 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
24426 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
24427 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
24428 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
24430 /* Thumb-compatibility pseudo ops. */
24431 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24432 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24433 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24434 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24435 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24436 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24437 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24438 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24439 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
24440 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
24441 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
24442 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
24444 /* These may simplify to neg. */
24445 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24446 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24448 #undef THUMB_VARIANT
24449 #define THUMB_VARIANT & arm_ext_os
24451 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24452 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24454 #undef THUMB_VARIANT
24455 #define THUMB_VARIANT & arm_ext_v6
24457 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
24459 /* V1 instructions with no Thumb analogue prior to V6T2. */
24460 #undef THUMB_VARIANT
24461 #define THUMB_VARIANT & arm_ext_v6t2
24463 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24464 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24465 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
24467 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24468 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24469 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
24470 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24472 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24473 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24475 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24476 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24478 /* V1 instructions with no Thumb analogue at all. */
24479 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
24480 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
24482 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24483 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24484 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24485 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24486 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24487 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24488 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24489 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24492 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
24493 #undef THUMB_VARIANT
24494 #define THUMB_VARIANT & arm_ext_v4t
24496 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24497 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24499 #undef THUMB_VARIANT
24500 #define THUMB_VARIANT & arm_ext_v6t2
24502 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24503 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
24505 /* Generic coprocessor instructions. */
24506 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24507 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24508 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24509 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24510 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24511 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24512 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24515 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
24517 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24518 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24521 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
24522 #undef THUMB_VARIANT
24523 #define THUMB_VARIANT & arm_ext_msr
24525 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
24526 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
24529 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
24530 #undef THUMB_VARIANT
24531 #define THUMB_VARIANT & arm_ext_v6t2
24533 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24534 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24535 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24536 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24537 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24538 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24539 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24540 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24543 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
24544 #undef THUMB_VARIANT
24545 #define THUMB_VARIANT & arm_ext_v4t
24547 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24548 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24549 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24550 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24551 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24552 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24555 #define ARM_VARIANT & arm_ext_v4t_5
24557 /* ARM Architecture 4T. */
24558 /* Note: bx (and blx) are required on V5, even if the processor does
24559 not support Thumb. */
24560 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
24563 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
24564 #undef THUMB_VARIANT
24565 #define THUMB_VARIANT & arm_ext_v5t
24567 /* Note: blx has 2 variants; the .value coded here is for
24568 BLX(2). Only this variant has conditional execution. */
24569 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
24570 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
24572 #undef THUMB_VARIANT
24573 #define THUMB_VARIANT & arm_ext_v6t2
24575 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
24576 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24577 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24578 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24579 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24580 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24581 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24582 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24585 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
24586 #undef THUMB_VARIANT
24587 #define THUMB_VARIANT & arm_ext_v5exp
24589 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24590 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24591 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24592 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24594 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24595 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24597 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24598 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24599 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24600 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24602 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24603 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24604 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24605 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24607 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24608 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24610 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24611 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24612 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24613 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24616 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
24617 #undef THUMB_VARIANT
24618 #define THUMB_VARIANT & arm_ext_v6t2
24620 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
24621 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
24623 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
24624 ADDRGLDRS
), ldrd
, t_ldstd
),
24626 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24627 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24630 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
24632 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
24635 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
24636 #undef THUMB_VARIANT
24637 #define THUMB_VARIANT & arm_ext_v6
24639 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24640 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24641 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24642 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24643 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24644 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24645 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24646 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24647 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24648 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
24650 #undef THUMB_VARIANT
24651 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24653 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
24654 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24656 #undef THUMB_VARIANT
24657 #define THUMB_VARIANT & arm_ext_v6t2
24659 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24660 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24662 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
24663 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
24665 /* ARM V6 not included in V7M. */
24666 #undef THUMB_VARIANT
24667 #define THUMB_VARIANT & arm_ext_v6_notm
24668 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24669 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24670 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
24671 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
24672 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24673 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24674 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
24675 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24676 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
24677 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24678 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24679 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24680 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24681 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24682 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
24683 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
24684 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24685 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24686 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
24688 /* ARM V6 not included in V7M (eg. integer SIMD). */
24689 #undef THUMB_VARIANT
24690 #define THUMB_VARIANT & arm_ext_v6_dsp
24691 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
24692 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
24693 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24694 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24695 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24696 /* Old name for QASX. */
24697 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24698 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24699 /* Old name for QSAX. */
24700 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24701 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24702 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24703 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24704 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24705 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24706 /* Old name for SASX. */
24707 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24708 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24709 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24710 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24711 /* Old name for SHASX. */
24712 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24713 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24714 /* Old name for SHSAX. */
24715 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24716 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24717 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24718 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24719 /* Old name for SSAX. */
24720 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24721 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24722 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24723 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24724 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24725 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24726 /* Old name for UASX. */
24727 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24728 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24729 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24730 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24731 /* Old name for UHASX. */
24732 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24733 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24734 /* Old name for UHSAX. */
24735 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24736 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24737 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24738 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24739 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24740 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24741 /* Old name for UQASX. */
24742 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24743 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24744 /* Old name for UQSAX. */
24745 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24746 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24747 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24748 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24749 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24750 /* Old name for USAX. */
24751 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24752 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24753 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24754 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24755 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24756 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24757 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24758 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24759 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24760 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24761 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24762 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24763 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24764 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24765 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24766 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24767 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24768 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24769 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24770 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24771 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24772 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24773 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24774 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24775 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24776 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24777 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24778 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24779 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24780 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
24781 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
24782 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24783 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24784 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
24787 #define ARM_VARIANT & arm_ext_v6k_v6t2
24788 #undef THUMB_VARIANT
24789 #define THUMB_VARIANT & arm_ext_v6k_v6t2
24791 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
24792 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
24793 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
24794 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
24796 #undef THUMB_VARIANT
24797 #define THUMB_VARIANT & arm_ext_v6_notm
24798 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
24800 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
24801 RRnpcb
), strexd
, t_strexd
),
24803 #undef THUMB_VARIANT
24804 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24805 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
24807 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
24809 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24811 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24813 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
24816 #define ARM_VARIANT & arm_ext_sec
24817 #undef THUMB_VARIANT
24818 #define THUMB_VARIANT & arm_ext_sec
24820 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
24823 #define ARM_VARIANT & arm_ext_virt
24824 #undef THUMB_VARIANT
24825 #define THUMB_VARIANT & arm_ext_virt
24827 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
24828 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
24831 #define ARM_VARIANT & arm_ext_pan
24832 #undef THUMB_VARIANT
24833 #define THUMB_VARIANT & arm_ext_pan
24835 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
24838 #define ARM_VARIANT & arm_ext_v6t2
24839 #undef THUMB_VARIANT
24840 #define THUMB_VARIANT & arm_ext_v6t2
24842 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
24843 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
24844 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24845 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24847 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24848 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
24850 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24851 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24852 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24853 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24856 #define ARM_VARIANT & arm_ext_v3
24857 #undef THUMB_VARIANT
24858 #define THUMB_VARIANT & arm_ext_v6t2
24860 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
24861 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
24862 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
24865 #define ARM_VARIANT & arm_ext_v6t2
24866 #undef THUMB_VARIANT
24867 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24868 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24869 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24871 /* Thumb-only instructions. */
24873 #define ARM_VARIANT NULL
24874 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
24875 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
24877 /* ARM does not really have an IT instruction, so always allow it.
24878 The opcode is copied from Thumb in order to allow warnings in
24879 -mimplicit-it=[never | arm] modes. */
24881 #define ARM_VARIANT & arm_ext_v1
24882 #undef THUMB_VARIANT
24883 #define THUMB_VARIANT & arm_ext_v6t2
24885 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
24886 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
24887 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
24888 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
24889 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
24890 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24891 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24892 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24893 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24894 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24895 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24896 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24897 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24898 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24899 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24900 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24901 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24902 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24904 /* Thumb2 only instructions. */
24906 #define ARM_VARIANT NULL
24908 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24909 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24910 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24911 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24912 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24913 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24915 /* Hardware division instructions. */
24917 #define ARM_VARIANT & arm_ext_adiv
24918 #undef THUMB_VARIANT
24919 #define THUMB_VARIANT & arm_ext_div
24921 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24922 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24924 /* ARM V6M/V7 instructions. */
24926 #define ARM_VARIANT & arm_ext_barrier
24927 #undef THUMB_VARIANT
24928 #define THUMB_VARIANT & arm_ext_barrier
24930 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24931 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24932 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24934 /* ARM V7 instructions. */
24936 #define ARM_VARIANT & arm_ext_v7
24937 #undef THUMB_VARIANT
24938 #define THUMB_VARIANT & arm_ext_v7
24940 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24941 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24944 #define ARM_VARIANT & arm_ext_mp
24945 #undef THUMB_VARIANT
24946 #define THUMB_VARIANT & arm_ext_mp
24948 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24950 /* AArchv8 instructions. */
24952 #define ARM_VARIANT & arm_ext_v8
24954 /* Instructions shared between armv8-a and armv8-m. */
24955 #undef THUMB_VARIANT
24956 #define THUMB_VARIANT & arm_ext_atomics
24958 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24959 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24960 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24961 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24962 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24963 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24964 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24965 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24966 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24967 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24969 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24971 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24973 #undef THUMB_VARIANT
24974 #define THUMB_VARIANT & arm_ext_v8
24976 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24977 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24979 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24981 #undef THUMB_VARIANT
24982 #define THUMB_VARIANT & arm_ext_v8r
24984 #define ARM_VARIANT & arm_ext_v8r
24986 /* ARMv8-R instructions. */
24987 TUF("dfb", 57ff04c
, f3bf8f4c
, 0, (), noargs
, noargs
),
24989 /* Defined in V8 but is in undefined encoding space for earlier
24990 architectures. However earlier architectures are required to treat
24991 this instuction as a semihosting trap as well. Hence while not explicitly
24992 defined as such, it is in fact correct to define the instruction for all
24994 #undef THUMB_VARIANT
24995 #define THUMB_VARIANT & arm_ext_v1
24997 #define ARM_VARIANT & arm_ext_v1
24998 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
25000 /* ARMv8 T32 only. */
25002 #define ARM_VARIANT NULL
25003 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
25004 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
25005 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
25007 /* FP for ARMv8. */
25009 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25010 #undef THUMB_VARIANT
25011 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
25013 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
25014 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
25015 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
25016 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
25017 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
25018 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
25019 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
25020 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
25021 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
25022 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
25023 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
25025 /* Crypto v1 extensions. */
25027 #define ARM_VARIANT & fpu_crypto_ext_armv8
25028 #undef THUMB_VARIANT
25029 #define THUMB_VARIANT & fpu_crypto_ext_armv8
25031 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
25032 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
25033 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
25034 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
25035 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
25036 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
25037 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
25038 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
25039 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
25040 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
25041 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
25042 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
25043 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
25044 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
25047 #define ARM_VARIANT & arm_ext_crc
25048 #undef THUMB_VARIANT
25049 #define THUMB_VARIANT & arm_ext_crc
25050 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
25051 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
25052 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
25053 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
25054 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
25055 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
25057 /* ARMv8.2 RAS extension. */
25059 #define ARM_VARIANT & arm_ext_ras
25060 #undef THUMB_VARIANT
25061 #define THUMB_VARIANT & arm_ext_ras
25062 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
25065 #define ARM_VARIANT & arm_ext_v8_3
25066 #undef THUMB_VARIANT
25067 #define THUMB_VARIANT & arm_ext_v8_3
25068 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
25071 #define ARM_VARIANT & fpu_neon_ext_dotprod
25072 #undef THUMB_VARIANT
25073 #define THUMB_VARIANT & fpu_neon_ext_dotprod
25074 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
25075 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
25078 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
25079 #undef THUMB_VARIANT
25080 #define THUMB_VARIANT NULL
25082 cCE("wfs", e200110
, 1, (RR
), rd
),
25083 cCE("rfs", e300110
, 1, (RR
), rd
),
25084 cCE("wfc", e400110
, 1, (RR
), rd
),
25085 cCE("rfc", e500110
, 1, (RR
), rd
),
25087 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25088 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25089 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25090 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25092 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25093 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25094 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25095 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25097 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
25098 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
25099 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
25100 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
25101 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
25102 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
25103 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
25104 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
25105 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
25106 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
25107 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
25108 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
25110 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
25111 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
25112 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
25113 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
25114 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
25115 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
25116 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
25117 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
25118 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
25119 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
25120 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
25121 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
25123 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
25124 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
25125 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
25126 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
25127 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
25128 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
25129 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
25130 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
25131 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
25132 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
25133 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
25134 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
25136 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
25137 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
25138 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
25139 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
25140 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
25141 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
25142 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
25143 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
25144 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
25145 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
25146 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
25147 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
25149 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
25150 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
25151 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
25152 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
25153 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
25154 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
25155 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
25156 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
25157 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
25158 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
25159 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
25160 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
25162 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
25163 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
25164 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
25165 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
25166 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
25167 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
25168 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
25169 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
25170 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
25171 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
25172 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
25173 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
25175 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
25176 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
25177 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
25178 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
25179 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
25180 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
25181 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
25182 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
25183 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
25184 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
25185 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
25186 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
25188 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
25189 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
25190 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
25191 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
25192 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
25193 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
25194 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
25195 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
25196 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
25197 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
25198 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
25199 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
25201 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
25202 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
25203 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
25204 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
25205 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
25206 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
25207 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
25208 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
25209 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
25210 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
25211 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
25212 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
25214 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
25215 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
25216 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
25217 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
25218 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
25219 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
25220 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
25221 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
25222 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
25223 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
25224 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
25225 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
25227 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
25228 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
25229 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
25230 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
25231 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
25232 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
25233 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
25234 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
25235 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
25236 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
25237 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
25238 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
25240 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
25241 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
25242 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
25243 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
25244 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
25245 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
25246 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
25247 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
25248 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
25249 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
25250 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
25251 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
25253 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
25254 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
25255 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
25256 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
25257 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
25258 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
25259 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
25260 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
25261 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
25262 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
25263 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
25264 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
25266 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
25267 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
25268 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
25269 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
25270 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
25271 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
25272 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
25273 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
25274 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
25275 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
25276 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
25277 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
25279 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
25280 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
25281 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
25282 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
25283 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
25284 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
25285 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
25286 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
25287 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
25288 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
25289 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
25290 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
25292 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
25293 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
25294 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
25295 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
25296 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
25297 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
25298 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
25299 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
25300 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
25301 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
25302 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
25303 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
25305 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25306 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25307 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25308 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25309 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25310 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25311 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25312 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25313 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25314 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25315 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25316 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25318 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25319 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25320 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25321 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25322 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25323 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25324 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25325 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25326 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25327 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25328 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25329 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25331 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25332 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25333 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25334 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25335 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25336 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25337 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25338 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25339 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25340 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25341 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25342 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25344 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25345 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25346 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25347 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25348 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25349 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25350 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25351 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25352 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25353 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25354 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25355 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25357 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25358 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25359 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25360 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25361 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25362 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25363 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25364 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25365 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25366 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25367 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25368 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25370 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25371 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25372 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25373 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25374 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25375 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25376 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25377 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25378 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25379 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25380 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25381 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25383 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25384 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25385 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25386 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25387 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25388 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25389 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25390 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25391 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25392 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25393 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25394 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25396 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25397 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25398 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25399 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25400 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25401 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25402 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25403 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25404 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25405 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25406 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25407 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25409 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25410 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25411 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25412 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25413 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25414 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25415 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25416 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25417 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25418 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25419 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25420 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25422 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25423 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25424 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25425 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25426 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25427 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25428 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25429 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25430 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25431 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25432 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25433 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25435 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25436 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25437 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25438 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25439 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25440 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25441 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25442 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25443 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25444 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25445 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25446 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25448 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25449 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25450 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25451 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25452 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25453 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25454 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25455 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25456 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25457 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25458 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25459 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25461 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25462 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25463 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25464 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25465 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25466 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25467 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25468 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25469 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25470 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25471 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25472 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25474 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25475 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25476 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25477 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25479 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
25480 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
25481 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
25482 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
25483 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
25484 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
25485 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
25486 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
25487 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
25488 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
25489 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
25490 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
25492 /* The implementation of the FIX instruction is broken on some
25493 assemblers, in that it accepts a precision specifier as well as a
25494 rounding specifier, despite the fact that this is meaningless.
25495 To be more compatible, we accept it as well, though of course it
25496 does not set any bits. */
25497 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
25498 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
25499 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
25500 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
25501 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
25502 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
25503 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
25504 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
25505 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
25506 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
25507 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
25508 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
25509 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
25511 /* Instructions that were new with the real FPA, call them V2. */
25513 #define ARM_VARIANT & fpu_fpa_ext_v2
25515 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25516 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25517 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25518 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25519 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25520 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25523 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
25524 #undef THUMB_VARIANT
25525 #define THUMB_VARIANT & arm_ext_v6t2
25526 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
25527 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
25528 mcCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25529 mcCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25530 mcCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25531 mcCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25533 /* Memory operations. */
25534 mcCE(fldmias
, c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25535 mcCE(fldmdbs
, d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25536 mcCE(fstmias
, c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25537 mcCE(fstmdbs
, d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25538 #undef THUMB_VARIANT
25540 /* Moves and type conversions. */
25541 cCE("fmstat", ef1fa10
, 0, (), noargs
),
25542 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25543 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25544 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25545 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25546 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25547 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25548 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
25549 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
25551 /* Memory operations. */
25552 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25553 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25554 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25555 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25556 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25557 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25558 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25559 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25560 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25561 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25562 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25563 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25565 /* Monadic operations. */
25566 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25567 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25568 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25570 /* Dyadic operations. */
25571 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25572 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25573 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25574 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25575 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25576 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25577 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25578 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25579 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25582 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25583 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
25584 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25585 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
25587 /* Double precision load/store are still present on single precision
25588 implementations. */
25589 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25590 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25591 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25592 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25593 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25594 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25595 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25596 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25599 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
25601 /* Moves and type conversions. */
25602 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25603 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25604 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25605 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25606 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25607 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25608 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25609 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25610 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25611 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25612 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25613 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25615 /* Monadic operations. */
25616 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25617 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25618 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25620 /* Dyadic operations. */
25621 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25622 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25623 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25624 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25625 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25626 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25627 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25628 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25629 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25632 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25633 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
25634 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25635 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
25637 /* Instructions which may belong to either the Neon or VFP instruction sets.
25638 Individual encoder functions perform additional architecture checks. */
25640 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25641 #undef THUMB_VARIANT
25642 #define THUMB_VARIANT & arm_ext_v6t2
25644 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25645 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25646 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25647 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25648 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25649 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25651 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
25652 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
25654 #undef THUMB_VARIANT
25655 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
25657 /* These mnemonics are unique to VFP. */
25658 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
25659 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
25660 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25661 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25662 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25663 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
25665 /* Mnemonics shared by Neon and VFP. */
25666 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
25668 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
25669 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
25670 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
25671 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
25674 /* NOTE: All VMOV encoding is special-cased! */
25675 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
25677 #undef THUMB_VARIANT
25678 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
25679 by different feature bits. Since we are setting the Thumb guard, we can
25680 require Thumb-1 which makes it a nop guard and set the right feature bit in
25681 do_vldr_vstr (). */
25682 #define THUMB_VARIANT & arm_ext_v4t
25683 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25684 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25687 #define ARM_VARIANT & arm_ext_fp16
25688 #undef THUMB_VARIANT
25689 #define THUMB_VARIANT & arm_ext_fp16
25690 /* New instructions added from v8.2, allowing the extraction and insertion of
25691 the upper 16 bits of a 32-bit vector register. */
25692 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
25693 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
25695 /* New backported fma/fms instructions optional in v8.2. */
25696 NUF (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
25697 NUF (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
25699 #undef THUMB_VARIANT
25700 #define THUMB_VARIANT & fpu_neon_ext_v1
25702 #define ARM_VARIANT & fpu_neon_ext_v1
25704 /* Data processing with three registers of the same length. */
25705 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
25706 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
25707 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
25708 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25709 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25710 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25711 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
25712 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25713 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25714 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25715 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25716 /* If not immediate, fall back to neon_dyadic_i64_su.
25717 shl should accept I8 I16 I32 I64,
25718 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
25719 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
25720 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
25721 /* Logic ops, types optional & ignored. */
25722 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25723 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25724 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25725 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25726 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
25727 /* Bitfield ops, untyped. */
25728 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25729 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25730 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25731 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25732 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25733 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25734 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
25735 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25736 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25737 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25738 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25739 back to neon_dyadic_if_su. */
25740 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25741 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25742 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25743 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25744 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25745 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25746 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25747 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25748 /* Comparison. Type I8 I16 I32 F32. */
25749 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
25750 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
25751 /* As above, D registers only. */
25752 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25753 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25754 /* Int and float variants, signedness unimportant. */
25755 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25756 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25757 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
25758 /* Add/sub take types I8 I16 I32 I64 F32. */
25759 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25760 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25761 /* vtst takes sizes 8, 16, 32. */
25762 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
25763 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
25764 /* VMUL takes I8 I16 I32 F32 P8. */
25765 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
25766 /* VQD{R}MULH takes S16 S32. */
25767 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25768 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25769 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25770 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25771 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25772 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25773 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25774 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25775 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25776 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25777 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25778 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25779 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25780 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25781 /* ARM v8.1 extension. */
25782 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25783 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
25784 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25786 /* Two address, int/float. Types S8 S16 S32 F32. */
25787 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25788 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25790 /* Data processing with two registers and a shift amount. */
25791 /* Right shifts, and variants with rounding.
25792 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
25793 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25794 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25795 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25796 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25797 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25798 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25799 /* Shift and insert. Sizes accepted 8 16 32 64. */
25800 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
25801 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
25802 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
25803 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
25804 /* Right shift immediate, saturating & narrowing, with rounding variants.
25805 Types accepted S16 S32 S64 U16 U32 U64. */
25806 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25807 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25808 /* As above, unsigned. Types accepted S16 S32 S64. */
25809 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25810 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25811 /* Right shift narrowing. Types accepted I16 I32 I64. */
25812 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25813 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25814 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
25815 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
25816 /* CVT with optional immediate for fixed-point variant. */
25817 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
25819 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
25821 /* Data processing, three registers of different lengths. */
25822 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
25823 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
25824 /* If not scalar, fall back to neon_dyadic_long.
25825 Vector types as above, scalar types S16 S32 U16 U32. */
25826 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25827 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25828 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
25829 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25830 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25831 /* Dyadic, narrowing insns. Types I16 I32 I64. */
25832 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25833 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25834 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25835 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25836 /* Saturating doubling multiplies. Types S16 S32. */
25837 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25838 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25839 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25840 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25841 S16 S32 U16 U32. */
25842 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
25844 /* Extract. Size 8. */
25845 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
25846 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
25848 /* Two registers, miscellaneous. */
25849 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
25850 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
25851 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
25852 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
25853 /* Vector replicate. Sizes 8 16 32. */
25854 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
25855 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25856 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
25857 /* VMOVN. Types I16 I32 I64. */
25858 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
25859 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25860 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
25861 /* VQMOVUN. Types S16 S32 S64. */
25862 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
25863 /* VZIP / VUZP. Sizes 8 16 32. */
25864 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25865 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25866 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25867 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25868 /* VQABS / VQNEG. Types S8 S16 S32. */
25869 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25870 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25871 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25872 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25873 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
25874 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25875 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
25876 /* Reciprocal estimates. Types U32 F16 F32. */
25877 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25878 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
25879 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25880 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
25881 /* VCLS. Types S8 S16 S32. */
25882 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
25883 /* VCLZ. Types I8 I16 I32. */
25884 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
25885 /* VCNT. Size 8. */
25886 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
25887 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
25888 /* Two address, untyped. */
25889 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
25890 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
25891 /* VTRN. Sizes 8 16 32. */
25892 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
25893 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
25895 /* Table lookup. Size 8. */
25896 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25897 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25899 #undef THUMB_VARIANT
25900 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25902 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25904 /* Neon element/structure load/store. */
25905 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25906 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25907 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25908 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25909 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25910 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25911 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25912 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25914 #undef THUMB_VARIANT
25915 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25917 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25918 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25919 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25920 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25921 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25922 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25923 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25924 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25925 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25926 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25928 #undef THUMB_VARIANT
25929 #define THUMB_VARIANT & fpu_vfp_ext_v3
25931 #define ARM_VARIANT & fpu_vfp_ext_v3
25933 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25934 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25935 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25936 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25937 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25938 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25939 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25940 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25941 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25944 #define ARM_VARIANT & fpu_vfp_ext_fma
25945 #undef THUMB_VARIANT
25946 #define THUMB_VARIANT & fpu_vfp_ext_fma
25947 /* Mnemonics shared by Neon, VFP, MVE and BF16. These are included in the
25948 VFP FMA variant; NEON and VFP FMA always includes the NEON
25949 FMA instructions. */
25950 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25951 TUF ("vfmat", c300850
, fc300850
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), mve_vfma
, mve_vfma
),
25952 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25954 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25955 the v form should always be used. */
25956 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25957 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25958 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25959 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25960 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25961 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25963 #undef THUMB_VARIANT
25965 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25967 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25968 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25969 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25970 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25971 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25972 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25973 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25974 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25977 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25979 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25980 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25981 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25982 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25983 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25984 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25985 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25986 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25987 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25988 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25989 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25990 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25991 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25992 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25993 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25994 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25995 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25996 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25997 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25998 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25999 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
26000 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
26001 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
26002 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
26003 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
26004 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
26005 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
26006 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
26007 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
26008 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
26009 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
26010 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
26011 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
26012 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
26013 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26014 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26015 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26016 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26017 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26018 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26019 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26020 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26021 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26022 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26023 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26024 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26025 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
26026 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26027 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26028 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26029 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26030 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26031 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26032 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26033 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26034 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26035 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26036 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26037 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26038 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26039 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26040 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26041 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26042 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26043 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26044 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26045 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26046 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26047 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26048 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26049 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26050 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26051 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26052 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26053 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26054 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26055 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26056 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26057 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26058 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26059 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26060 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26061 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26062 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26063 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26064 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26065 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26066 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26067 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
26068 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26069 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26070 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26071 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26072 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26073 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26074 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26075 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26076 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26077 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26078 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26079 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26080 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26081 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26082 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26083 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26084 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26085 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26086 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26087 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26088 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26089 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
26090 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26091 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26092 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26093 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26094 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26095 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26096 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26097 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26098 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26099 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26100 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26101 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26102 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26103 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26104 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26105 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26106 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26107 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26108 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26109 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26110 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26111 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26112 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26113 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26114 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26115 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26116 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26117 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26118 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26119 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26120 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26121 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26122 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26123 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26124 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26125 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26126 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26127 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26128 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26129 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26130 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26131 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26132 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26133 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26134 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26135 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26136 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26137 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26138 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26139 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26140 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
26143 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
26145 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
26146 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
26147 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
26148 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26149 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26150 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26151 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26152 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26153 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26154 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26155 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26156 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26157 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26158 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26159 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26160 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26161 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26162 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26163 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26164 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26165 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
26166 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26167 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26168 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26169 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26170 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26171 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26172 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26173 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26174 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26175 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26176 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26177 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26178 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26179 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26180 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26181 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26182 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26183 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26184 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26185 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26186 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26187 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26188 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26189 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26190 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26191 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26192 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26193 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26194 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26195 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26196 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26197 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26198 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26199 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26200 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26201 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26204 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
26206 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26207 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26208 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26209 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26210 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26211 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26212 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26213 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26214 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
26215 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
26216 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
26217 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
26218 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
26219 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
26220 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
26221 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
26222 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
26223 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
26224 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
26225 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
26226 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
26227 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
26228 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
26229 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
26230 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
26231 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
26232 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
26233 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
26234 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
26235 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
26236 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
26237 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
26238 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
26239 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
26240 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
26241 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
26242 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
26243 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
26244 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
26245 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
26246 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
26247 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
26248 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
26249 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
26250 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
26251 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
26252 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
26253 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
26254 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
26255 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
26256 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
26257 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
26258 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
26259 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
26260 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26261 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26262 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26263 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26264 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26265 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26266 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
26267 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
26268 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
26269 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
26270 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26271 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26272 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26273 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26274 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26275 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26276 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26277 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26278 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26279 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26280 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26281 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26283 /* ARMv8.5-A instructions. */
26285 #define ARM_VARIANT & arm_ext_sb
26286 #undef THUMB_VARIANT
26287 #define THUMB_VARIANT & arm_ext_sb
26288 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
26291 #define ARM_VARIANT & arm_ext_predres
26292 #undef THUMB_VARIANT
26293 #define THUMB_VARIANT & arm_ext_predres
26294 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
26295 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
26296 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
26298 /* ARMv8-M instructions. */
26300 #define ARM_VARIANT NULL
26301 #undef THUMB_VARIANT
26302 #define THUMB_VARIANT & arm_ext_v8m
26303 ToU("sg", e97fe97f
, 0, (), noargs
),
26304 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
26305 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
26306 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
26307 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
26308 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
26309 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
26311 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
26312 instructions behave as nop if no VFP is present. */
26313 #undef THUMB_VARIANT
26314 #define THUMB_VARIANT & arm_ext_v8m_main
26315 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
26316 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
26318 /* Armv8.1-M Mainline instructions. */
26319 #undef THUMB_VARIANT
26320 #define THUMB_VARIANT & arm_ext_v8_1m_main
26321 toU("aut", _aut
, 3, (R12
, LR
, SP
), t_pacbti
),
26322 toU("autg", _autg
, 3, (RR
, RR
, RR
), t_pacbti_nonop
),
26323 ToU("bti", f3af800f
, 0, (), noargs
),
26324 toU("bxaut", _bxaut
, 3, (RR
, RR
, RR
), t_pacbti_nonop
),
26325 toU("pac", _pac
, 3, (R12
, LR
, SP
), t_pacbti
),
26326 toU("pacbti", _pacbti
, 3, (R12
, LR
, SP
), t_pacbti
),
26327 toU("pacg", _pacg
, 3, (RR
, RR
, RR
), t_pacbti_pacg
),
26328 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26329 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26330 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26331 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26332 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
26333 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
26334 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26335 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26336 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26338 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
26339 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
26340 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26341 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
26342 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26344 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
26345 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
26346 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
26348 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
26349 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
26351 #undef THUMB_VARIANT
26352 #define THUMB_VARIANT & mve_ext
26353 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26354 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26355 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26356 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26357 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26358 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26359 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26360 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26361 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26362 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26363 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26364 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26365 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26366 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26367 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26369 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26370 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26371 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26372 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26373 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26374 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26375 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26376 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26377 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26378 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26379 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26380 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26381 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26382 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26383 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26385 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
26386 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
26387 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
26388 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
26389 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
26390 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
26391 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
26392 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
26393 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
26394 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
26395 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
26396 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
26397 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
26398 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
26399 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
26401 /* MVE and MVE FP only. */
26402 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
26403 mCEF(vctp
, _vctp
, 1, (RRnpc
), mve_vctp
),
26404 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26405 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26406 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26407 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26408 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
26409 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
26410 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26411 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26412 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26413 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26414 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26415 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26416 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26417 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26418 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26419 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26421 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26422 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26423 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26424 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26425 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26426 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26427 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26428 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26429 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26430 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26431 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26432 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26433 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26434 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26435 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26436 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26437 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26438 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26439 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26440 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26442 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
26443 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
26444 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
26445 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26446 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26447 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
26448 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
26449 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26450 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26451 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26452 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26453 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26454 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26455 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
26456 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
26457 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
26458 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
26460 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26461 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26462 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26463 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26464 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26465 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26466 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26467 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26468 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26469 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26470 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26471 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26472 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26473 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26474 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26475 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26476 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26477 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26478 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26479 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26481 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
26482 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26483 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26484 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
26485 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
26487 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26488 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26489 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26490 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26491 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26492 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26493 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26494 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26495 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26496 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26497 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26498 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26499 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26500 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26501 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26502 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26503 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26505 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26506 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26507 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26508 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26509 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26510 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26511 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26512 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26513 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26514 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26515 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26516 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26518 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
26519 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26520 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26522 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
26523 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
26524 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
26525 toU("lctp", _lctp
, 0, (), t_loloop
),
26527 #undef THUMB_VARIANT
26528 #define THUMB_VARIANT & mve_fp_ext
26529 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
26530 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
26531 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26532 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26533 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26534 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26535 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26536 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26539 #define ARM_VARIANT & fpu_vfp_ext_v1
26540 #undef THUMB_VARIANT
26541 #define THUMB_VARIANT & arm_ext_v6t2
26543 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
26546 #define ARM_VARIANT & fpu_vfp_ext_v1xd
26548 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
26549 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
26550 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
26551 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
26552 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
26553 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
26555 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
26556 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26557 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26559 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26560 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26562 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
26563 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
26565 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26566 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26569 #define ARM_VARIANT & fpu_vfp_ext_v2
26571 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
26572 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
26573 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
26574 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
26577 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
26578 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
26579 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
26580 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
26581 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
26582 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26583 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26586 #define ARM_VARIANT & fpu_neon_ext_v1
26587 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26588 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
26589 mnUF(vaddl
, _vaddl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26590 mnUF(vsubl
, _vsubl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26591 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26592 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26593 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26594 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26595 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
26596 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
26597 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
26598 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
26599 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26600 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
26601 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26602 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26603 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26604 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26605 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26606 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
26607 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26608 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26609 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
26610 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26611 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26612 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26613 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26614 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26615 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26616 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
26617 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
26618 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26619 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26620 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26621 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
26622 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
26623 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
26626 #define ARM_VARIANT & arm_ext_v8_3
26627 #undef THUMB_VARIANT
26628 #define THUMB_VARIANT & arm_ext_v6t2_v8m
26629 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
26630 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
26633 #define ARM_VARIANT &arm_ext_bf16
26634 #undef THUMB_VARIANT
26635 #define THUMB_VARIANT &arm_ext_bf16
26636 TUF ("vdot", c000d00
, fc000d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vdot
, vdot
),
26637 TUF ("vmmla", c000c40
, fc000c40
, 3, (RNQ
, RNQ
, RNQ
), vmmla
, vmmla
),
26638 TUF ("vfmab", c300810
, fc300810
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), bfloat_vfma
, bfloat_vfma
),
26641 #define ARM_VARIANT &arm_ext_i8mm
26642 #undef THUMB_VARIANT
26643 #define THUMB_VARIANT &arm_ext_i8mm
26644 TUF ("vsmmla", c200c40
, fc200c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26645 TUF ("vummla", c200c50
, fc200c50
, 3, (RNQ
, RNQ
, RNQ
), vummla
, vummla
),
26646 TUF ("vusmmla", ca00c40
, fca00c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26647 TUF ("vusdot", c800d00
, fc800d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vusdot
, vusdot
),
26648 TUF ("vsudot", c800d10
, fc800d10
, 3, (RNDQ
, RNDQ
, RNSC
), vsudot
, vsudot
),
26651 #undef THUMB_VARIANT
26652 #define THUMB_VARIANT &arm_ext_cde
26653 ToC ("cx1", ee000000
, 3, (RCP
, APSR_RR
, I8191
), cx1
),
26654 ToC ("cx1a", fe000000
, 3, (RCP
, APSR_RR
, I8191
), cx1a
),
26655 ToC ("cx1d", ee000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1d
),
26656 ToC ("cx1da", fe000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1da
),
26658 ToC ("cx2", ee400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2
),
26659 ToC ("cx2a", fe400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2a
),
26660 ToC ("cx2d", ee400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2d
),
26661 ToC ("cx2da", fe400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2da
),
26663 ToC ("cx3", ee800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3
),
26664 ToC ("cx3a", fe800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3a
),
26665 ToC ("cx3d", ee800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3d
),
26666 ToC ("cx3da", fe800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3da
),
26668 mToC ("vcx1", ec200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26669 mToC ("vcx1a", fc200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26671 mToC ("vcx2", ec300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26672 mToC ("vcx2a", fc300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26674 mToC ("vcx3", ec800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26675 mToC ("vcx3a", fc800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26679 #undef THUMB_VARIANT
26711 /* MD interface: bits in the object file. */
26713 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
26714 for use in the a.out file, and stores them in the array pointed to by buf.
26715 This knows about the endian-ness of the target machine and does
26716 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
26717 2 (short) and 4 (long) Floating numbers are put out as a series of
26718 LITTLENUMS (shorts, here at least). */
26721 md_number_to_chars (char * buf
, valueT val
, int n
)
26723 if (target_big_endian
)
26724 number_to_chars_bigendian (buf
, val
, n
);
26726 number_to_chars_littleendian (buf
, val
, n
);
26730 md_chars_to_number (char * buf
, int n
)
26733 unsigned char * where
= (unsigned char *) buf
;
26735 if (target_big_endian
)
26740 result
|= (*where
++ & 255);
26748 result
|= (where
[n
] & 255);
26755 /* MD interface: Sections. */
26757 /* Calculate the maximum variable size (i.e., excluding fr_fix)
26758 that an rs_machine_dependent frag may reach. */
26761 arm_frag_max_var (fragS
*fragp
)
26763 /* We only use rs_machine_dependent for variable-size Thumb instructions,
26764 which are either THUMB_SIZE (2) or INSN_SIZE (4).
26766 Note that we generate relaxable instructions even for cases that don't
26767 really need it, like an immediate that's a trivial constant. So we're
26768 overestimating the instruction size for some of those cases. Rather
26769 than putting more intelligence here, it would probably be better to
26770 avoid generating a relaxation frag in the first place when it can be
26771 determined up front that a short instruction will suffice. */
26773 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
26777 /* Estimate the size of a frag before relaxing. Assume everything fits in
26781 md_estimate_size_before_relax (fragS
* fragp
,
26782 segT segtype ATTRIBUTE_UNUSED
)
26788 /* Convert a machine dependent frag. */
26791 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
26793 unsigned long insn
;
26794 unsigned long old_op
;
26802 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26804 old_op
= bfd_get_16(abfd
, buf
);
26805 if (fragp
->fr_symbol
)
26807 exp
.X_op
= O_symbol
;
26808 exp
.X_add_symbol
= fragp
->fr_symbol
;
26812 exp
.X_op
= O_constant
;
26814 exp
.X_add_number
= fragp
->fr_offset
;
26815 opcode
= fragp
->fr_subtype
;
26818 case T_MNEM_ldr_pc
:
26819 case T_MNEM_ldr_pc2
:
26820 case T_MNEM_ldr_sp
:
26821 case T_MNEM_str_sp
:
26828 if (fragp
->fr_var
== 4)
26830 insn
= THUMB_OP32 (opcode
);
26831 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
26833 insn
|= (old_op
& 0x700) << 4;
26837 insn
|= (old_op
& 7) << 12;
26838 insn
|= (old_op
& 0x38) << 13;
26840 insn
|= 0x00000c00;
26841 put_thumb32_insn (buf
, insn
);
26842 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
26846 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
26848 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
26851 /* Thumb bits should be set in the frag handling so we process them
26852 after all symbols have been seen. PR gas/25235. */
26853 if (exp
.X_op
== O_symbol
26854 && exp
.X_add_symbol
!= NULL
26855 && S_IS_DEFINED (exp
.X_add_symbol
)
26856 && THUMB_IS_FUNC (exp
.X_add_symbol
))
26857 exp
.X_add_number
|= 1;
26859 if (fragp
->fr_var
== 4)
26861 insn
= THUMB_OP32 (opcode
);
26862 insn
|= (old_op
& 0xf0) << 4;
26863 put_thumb32_insn (buf
, insn
);
26864 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
26868 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26869 exp
.X_add_number
-= 4;
26877 if (fragp
->fr_var
== 4)
26879 int r0off
= (opcode
== T_MNEM_mov
26880 || opcode
== T_MNEM_movs
) ? 0 : 8;
26881 insn
= THUMB_OP32 (opcode
);
26882 insn
= (insn
& 0xe1ffffff) | 0x10000000;
26883 insn
|= (old_op
& 0x700) << r0off
;
26884 put_thumb32_insn (buf
, insn
);
26885 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26889 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
26894 if (fragp
->fr_var
== 4)
26896 insn
= THUMB_OP32(opcode
);
26897 put_thumb32_insn (buf
, insn
);
26898 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
26901 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
26905 if (fragp
->fr_var
== 4)
26907 insn
= THUMB_OP32(opcode
);
26908 insn
|= (old_op
& 0xf00) << 14;
26909 put_thumb32_insn (buf
, insn
);
26910 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
26913 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
26916 case T_MNEM_add_sp
:
26917 case T_MNEM_add_pc
:
26918 case T_MNEM_inc_sp
:
26919 case T_MNEM_dec_sp
:
26920 if (fragp
->fr_var
== 4)
26922 /* ??? Choose between add and addw. */
26923 insn
= THUMB_OP32 (opcode
);
26924 insn
|= (old_op
& 0xf0) << 4;
26925 put_thumb32_insn (buf
, insn
);
26926 if (opcode
== T_MNEM_add_pc
)
26927 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
26929 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26932 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26940 if (fragp
->fr_var
== 4)
26942 insn
= THUMB_OP32 (opcode
);
26943 insn
|= (old_op
& 0xf0) << 4;
26944 insn
|= (old_op
& 0xf) << 16;
26945 put_thumb32_insn (buf
, insn
);
26946 if (insn
& (1 << 20))
26947 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26949 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26952 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26958 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
26959 (enum bfd_reloc_code_real
) reloc_type
);
26960 fixp
->fx_file
= fragp
->fr_file
;
26961 fixp
->fx_line
= fragp
->fr_line
;
26962 fragp
->fr_fix
+= fragp
->fr_var
;
26964 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26965 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
26966 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26967 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26970 /* Return the size of a relaxable immediate operand instruction.
26971 SHIFT and SIZE specify the form of the allowable immediate. */
26973 relax_immediate (fragS
*fragp
, int size
, int shift
)
26979 /* ??? Should be able to do better than this. */
26980 if (fragp
->fr_symbol
)
26983 low
= (1 << shift
) - 1;
26984 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26985 offset
= fragp
->fr_offset
;
26986 /* Force misaligned offsets to 32-bit variant. */
26989 if (offset
& ~mask
)
26994 /* Get the address of a symbol during relaxation. */
26996 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
27002 sym
= fragp
->fr_symbol
;
27003 sym_frag
= symbol_get_frag (sym
);
27004 know (S_GET_SEGMENT (sym
) != absolute_section
27005 || sym_frag
== &zero_address_frag
);
27006 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
27008 /* If frag has yet to be reached on this pass, assume it will
27009 move by STRETCH just as we did. If this is not so, it will
27010 be because some frag between grows, and that will force
27014 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
27018 /* Adjust stretch for any alignment frag. Note that if have
27019 been expanding the earlier code, the symbol may be
27020 defined in what appears to be an earlier frag. FIXME:
27021 This doesn't handle the fr_subtype field, which specifies
27022 a maximum number of bytes to skip when doing an
27024 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
27026 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
27029 stretch
= - ((- stretch
)
27030 & ~ ((1 << (int) f
->fr_offset
) - 1));
27032 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
27044 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
27047 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
27052 /* Assume worst case for symbols not known to be in the same section. */
27053 if (fragp
->fr_symbol
== NULL
27054 || !S_IS_DEFINED (fragp
->fr_symbol
)
27055 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27056 || S_IS_WEAK (fragp
->fr_symbol
)
27057 || THUMB_IS_FUNC (fragp
->fr_symbol
))
27060 val
= relaxed_symbol_addr (fragp
, stretch
);
27061 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
27062 addr
= (addr
+ 4) & ~3;
27063 /* Force misaligned targets to 32-bit variant. */
27067 if (val
< 0 || val
> 1020)
27072 /* Return the size of a relaxable add/sub immediate instruction. */
27074 relax_addsub (fragS
*fragp
, asection
*sec
)
27079 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
27080 op
= bfd_get_16(sec
->owner
, buf
);
27081 if ((op
& 0xf) == ((op
>> 4) & 0xf))
27082 return relax_immediate (fragp
, 8, 0);
27084 return relax_immediate (fragp
, 3, 0);
27087 /* Return TRUE iff the definition of symbol S could be pre-empted
27088 (overridden) at link or load time. */
27090 symbol_preemptible (symbolS
*s
)
27092 /* Weak symbols can always be pre-empted. */
27096 /* Non-global symbols cannot be pre-empted. */
27097 if (! S_IS_EXTERNAL (s
))
27101 /* In ELF, a global symbol can be marked protected, or private. In that
27102 case it can't be pre-empted (other definitions in the same link unit
27103 would violate the ODR). */
27104 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
27108 /* Other global symbols might be pre-empted. */
27112 /* Return the size of a relaxable branch instruction. BITS is the
27113 size of the offset field in the narrow instruction. */
27116 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
27122 /* Assume worst case for symbols not known to be in the same section. */
27123 if (!S_IS_DEFINED (fragp
->fr_symbol
)
27124 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27125 || S_IS_WEAK (fragp
->fr_symbol
))
27129 /* A branch to a function in ARM state will require interworking. */
27130 if (S_IS_DEFINED (fragp
->fr_symbol
)
27131 && ARM_IS_FUNC (fragp
->fr_symbol
))
27135 if (symbol_preemptible (fragp
->fr_symbol
))
27138 val
= relaxed_symbol_addr (fragp
, stretch
);
27139 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
27142 /* Offset is a signed value *2 */
27144 if (val
>= limit
|| val
< -limit
)
27150 /* Relax a machine dependent frag. This returns the amount by which
27151 the current size of the frag should change. */
27154 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
27159 oldsize
= fragp
->fr_var
;
27160 switch (fragp
->fr_subtype
)
27162 case T_MNEM_ldr_pc2
:
27163 newsize
= relax_adr (fragp
, sec
, stretch
);
27165 case T_MNEM_ldr_pc
:
27166 case T_MNEM_ldr_sp
:
27167 case T_MNEM_str_sp
:
27168 newsize
= relax_immediate (fragp
, 8, 2);
27172 newsize
= relax_immediate (fragp
, 5, 2);
27176 newsize
= relax_immediate (fragp
, 5, 1);
27180 newsize
= relax_immediate (fragp
, 5, 0);
27183 newsize
= relax_adr (fragp
, sec
, stretch
);
27189 newsize
= relax_immediate (fragp
, 8, 0);
27192 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
27195 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
27197 case T_MNEM_add_sp
:
27198 case T_MNEM_add_pc
:
27199 newsize
= relax_immediate (fragp
, 8, 2);
27201 case T_MNEM_inc_sp
:
27202 case T_MNEM_dec_sp
:
27203 newsize
= relax_immediate (fragp
, 7, 2);
27209 newsize
= relax_addsub (fragp
, sec
);
27215 fragp
->fr_var
= newsize
;
27216 /* Freeze wide instructions that are at or before the same location as
27217 in the previous pass. This avoids infinite loops.
27218 Don't freeze them unconditionally because targets may be artificially
27219 misaligned by the expansion of preceding frags. */
27220 if (stretch
<= 0 && newsize
> 2)
27222 md_convert_frag (sec
->owner
, sec
, fragp
);
27226 return newsize
- oldsize
;
27229 /* Round up a section size to the appropriate boundary. */
27232 md_section_align (segT segment ATTRIBUTE_UNUSED
,
27238 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
27239 of an rs_align_code fragment. */
27242 arm_handle_align (fragS
* fragP
)
27244 static unsigned char const arm_noop
[2][2][4] =
27247 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
27248 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
27251 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
27252 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
27255 static unsigned char const thumb_noop
[2][2][2] =
27258 {0xc0, 0x46}, /* LE */
27259 {0x46, 0xc0}, /* BE */
27262 {0x00, 0xbf}, /* LE */
27263 {0xbf, 0x00} /* BE */
27266 static unsigned char const wide_thumb_noop
[2][4] =
27267 { /* Wide Thumb-2 */
27268 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
27269 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
27272 unsigned bytes
, fix
, noop_size
;
27274 const unsigned char * noop
;
27275 const unsigned char *narrow_noop
= NULL
;
27280 if (fragP
->fr_type
!= rs_align_code
)
27283 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
27284 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
27287 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27288 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
27290 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
27292 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
27294 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27295 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
27297 narrow_noop
= thumb_noop
[1][target_big_endian
];
27298 noop
= wide_thumb_noop
[target_big_endian
];
27301 noop
= thumb_noop
[0][target_big_endian
];
27309 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27310 ? selected_cpu
: arm_arch_none
,
27312 [target_big_endian
];
27319 fragP
->fr_var
= noop_size
;
27321 if (bytes
& (noop_size
- 1))
27323 fix
= bytes
& (noop_size
- 1);
27325 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
27327 memset (p
, 0, fix
);
27334 if (bytes
& noop_size
)
27336 /* Insert a narrow noop. */
27337 memcpy (p
, narrow_noop
, noop_size
);
27339 bytes
-= noop_size
;
27343 /* Use wide noops for the remainder */
27347 while (bytes
>= noop_size
)
27349 memcpy (p
, noop
, noop_size
);
27351 bytes
-= noop_size
;
27355 fragP
->fr_fix
+= fix
;
27358 /* Called from md_do_align. Used to create an alignment
27359 frag in a code section. */
27362 arm_frag_align_code (int n
, int max
)
27366 /* We assume that there will never be a requirement
27367 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
27368 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27373 _("alignments greater than %d bytes not supported in .text sections."),
27374 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
27375 as_fatal ("%s", err_msg
);
27378 p
= frag_var (rs_align_code
,
27379 MAX_MEM_FOR_RS_ALIGN_CODE
,
27381 (relax_substateT
) max
,
27388 /* Perform target specific initialisation of a frag.
27389 Note - despite the name this initialisation is not done when the frag
27390 is created, but only when its type is assigned. A frag can be created
27391 and used a long time before its type is set, so beware of assuming that
27392 this initialisation is performed first. */
27396 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
27398 /* Record whether this frag is in an ARM or a THUMB area. */
27399 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27402 #else /* OBJ_ELF is defined. */
27404 arm_init_frag (fragS
* fragP
, int max_chars
)
27406 bool frag_thumb_mode
;
27408 /* If the current ARM vs THUMB mode has not already
27409 been recorded into this frag then do so now. */
27410 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
27411 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27413 /* PR 21809: Do not set a mapping state for debug sections
27414 - it just confuses other tools. */
27415 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
27418 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
27420 /* Record a mapping symbol for alignment frags. We will delete this
27421 later if the alignment ends up empty. */
27422 switch (fragP
->fr_type
)
27425 case rs_align_test
:
27427 mapping_state_2 (MAP_DATA
, max_chars
);
27429 case rs_align_code
:
27430 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
27437 /* When we change sections we need to issue a new mapping symbol. */
27440 arm_elf_change_section (void)
27442 /* Link an unlinked unwind index table section to the .text section. */
27443 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
27444 && elf_linked_to_section (now_seg
) == NULL
)
27445 elf_linked_to_section (now_seg
) = text_section
;
27449 arm_elf_section_type (const char * str
, size_t len
)
27451 if (len
== 5 && startswith (str
, "exidx"))
27452 return SHT_ARM_EXIDX
;
27457 /* Code to deal with unwinding tables. */
27459 static void add_unwind_adjustsp (offsetT
);
27461 /* Generate any deferred unwind frame offset. */
27464 flush_pending_unwind (void)
27468 offset
= unwind
.pending_offset
;
27469 unwind
.pending_offset
= 0;
27471 add_unwind_adjustsp (offset
);
27474 /* Add an opcode to this list for this function. Two-byte opcodes should
27475 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
27479 add_unwind_opcode (valueT op
, int length
)
27481 /* Add any deferred stack adjustment. */
27482 if (unwind
.pending_offset
)
27483 flush_pending_unwind ();
27485 unwind
.sp_restored
= 0;
27487 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
27489 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
27490 if (unwind
.opcodes
)
27491 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
27492 unwind
.opcode_alloc
);
27494 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
27499 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
27501 unwind
.opcode_count
++;
27505 /* Add unwind opcodes to adjust the stack pointer. */
27508 add_unwind_adjustsp (offsetT offset
)
27512 if (offset
> 0x200)
27514 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
27519 /* Long form: 0xb2, uleb128. */
27520 /* This might not fit in a word so add the individual bytes,
27521 remembering the list is built in reverse order. */
27522 o
= (valueT
) ((offset
- 0x204) >> 2);
27524 add_unwind_opcode (0, 1);
27526 /* Calculate the uleb128 encoding of the offset. */
27530 bytes
[n
] = o
& 0x7f;
27536 /* Add the insn. */
27538 add_unwind_opcode (bytes
[n
- 1], 1);
27539 add_unwind_opcode (0xb2, 1);
27541 else if (offset
> 0x100)
27543 /* Two short opcodes. */
27544 add_unwind_opcode (0x3f, 1);
27545 op
= (offset
- 0x104) >> 2;
27546 add_unwind_opcode (op
, 1);
27548 else if (offset
> 0)
27550 /* Short opcode. */
27551 op
= (offset
- 4) >> 2;
27552 add_unwind_opcode (op
, 1);
27554 else if (offset
< 0)
27557 while (offset
> 0x100)
27559 add_unwind_opcode (0x7f, 1);
27562 op
= ((offset
- 4) >> 2) | 0x40;
27563 add_unwind_opcode (op
, 1);
27567 /* Finish the list of unwind opcodes for this function. */
27570 finish_unwind_opcodes (void)
27574 if (unwind
.fp_used
)
27576 /* Adjust sp as necessary. */
27577 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
27578 flush_pending_unwind ();
27580 /* After restoring sp from the frame pointer. */
27581 op
= 0x90 | unwind
.fp_reg
;
27582 add_unwind_opcode (op
, 1);
27585 flush_pending_unwind ();
27589 /* Start an exception table entry. If idx is nonzero this is an index table
27593 start_unwind_section (const segT text_seg
, int idx
)
27595 const char * text_name
;
27596 const char * prefix
;
27597 const char * prefix_once
;
27598 struct elf_section_match match
;
27606 prefix
= ELF_STRING_ARM_unwind
;
27607 prefix_once
= ELF_STRING_ARM_unwind_once
;
27608 type
= SHT_ARM_EXIDX
;
27612 prefix
= ELF_STRING_ARM_unwind_info
;
27613 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
27614 type
= SHT_PROGBITS
;
27617 text_name
= segment_name (text_seg
);
27618 if (streq (text_name
, ".text"))
27621 if (startswith (text_name
, ".gnu.linkonce.t."))
27623 prefix
= prefix_once
;
27624 text_name
+= strlen (".gnu.linkonce.t.");
27627 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
27631 memset (&match
, 0, sizeof (match
));
27633 /* Handle COMDAT group. */
27634 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
27636 match
.group_name
= elf_group_name (text_seg
);
27637 if (match
.group_name
== NULL
)
27639 as_bad (_("Group section `%s' has no group signature"),
27640 segment_name (text_seg
));
27641 ignore_rest_of_line ();
27644 flags
|= SHF_GROUP
;
27648 obj_elf_change_section (sec_name
, type
, flags
, 0, &match
,
27651 /* Set the section link for index tables. */
27653 elf_linked_to_section (now_seg
) = text_seg
;
27657 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
27658 personality routine data. Returns zero, or the index table value for
27659 an inline entry. */
27662 create_unwind_entry (int have_data
)
27667 /* The current word of data. */
27669 /* The number of bytes left in this word. */
27672 finish_unwind_opcodes ();
27674 /* Remember the current text section. */
27675 unwind
.saved_seg
= now_seg
;
27676 unwind
.saved_subseg
= now_subseg
;
27678 start_unwind_section (now_seg
, 0);
27680 if (unwind
.personality_routine
== NULL
)
27682 if (unwind
.personality_index
== -2)
27685 as_bad (_("handlerdata in cantunwind frame"));
27686 return 1; /* EXIDX_CANTUNWIND. */
27689 /* Use a default personality routine if none is specified. */
27690 if (unwind
.personality_index
== -1)
27692 if (unwind
.opcode_count
> 3)
27693 unwind
.personality_index
= 1;
27695 unwind
.personality_index
= 0;
27698 /* Space for the personality routine entry. */
27699 if (unwind
.personality_index
== 0)
27701 if (unwind
.opcode_count
> 3)
27702 as_bad (_("too many unwind opcodes for personality routine 0"));
27706 /* All the data is inline in the index table. */
27709 while (unwind
.opcode_count
> 0)
27711 unwind
.opcode_count
--;
27712 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27716 /* Pad with "finish" opcodes. */
27718 data
= (data
<< 8) | 0xb0;
27725 /* We get two opcodes "free" in the first word. */
27726 size
= unwind
.opcode_count
- 2;
27730 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
27731 if (unwind
.personality_index
!= -1)
27733 as_bad (_("attempt to recreate an unwind entry"));
27737 /* An extra byte is required for the opcode count. */
27738 size
= unwind
.opcode_count
+ 1;
27741 size
= (size
+ 3) >> 2;
27743 as_bad (_("too many unwind opcodes"));
27745 frag_align (2, 0, 0);
27746 record_alignment (now_seg
, 2);
27747 unwind
.table_entry
= expr_build_dot ();
27749 /* Allocate the table entry. */
27750 ptr
= frag_more ((size
<< 2) + 4);
27751 /* PR 13449: Zero the table entries in case some of them are not used. */
27752 memset (ptr
, 0, (size
<< 2) + 4);
27753 where
= frag_now_fix () - ((size
<< 2) + 4);
27755 switch (unwind
.personality_index
)
27758 /* ??? Should this be a PLT generating relocation? */
27759 /* Custom personality routine. */
27760 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
27761 BFD_RELOC_ARM_PREL31
);
27766 /* Set the first byte to the number of additional words. */
27767 data
= size
> 0 ? size
- 1 : 0;
27771 /* ABI defined personality routines. */
27773 /* Three opcodes bytes are packed into the first word. */
27780 /* The size and first two opcode bytes go in the first word. */
27781 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
27786 /* Should never happen. */
27790 /* Pack the opcodes into words (MSB first), reversing the list at the same
27792 while (unwind
.opcode_count
> 0)
27796 md_number_to_chars (ptr
, data
, 4);
27801 unwind
.opcode_count
--;
27803 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27806 /* Finish off the last word. */
27809 /* Pad with "finish" opcodes. */
27811 data
= (data
<< 8) | 0xb0;
27813 md_number_to_chars (ptr
, data
, 4);
27818 /* Add an empty descriptor if there is no user-specified data. */
27819 ptr
= frag_more (4);
27820 md_number_to_chars (ptr
, 0, 4);
27827 /* Initialize the DWARF-2 unwind information for this procedure. */
27830 tc_arm_frame_initial_instructions (void)
27832 cfi_add_CFA_def_cfa (REG_SP
, 0);
27834 #endif /* OBJ_ELF */
27836 /* Convert REGNAME to a DWARF-2 register number. */
27839 tc_arm_regname_to_dw2regnum (char *regname
)
27841 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
27845 /* PR 16694: Allow VFP registers as well. */
27846 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
27850 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
27859 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
27863 exp
.X_op
= O_secrel
;
27864 exp
.X_add_symbol
= symbol
;
27865 exp
.X_add_number
= 0;
27866 emit_expr (&exp
, size
);
27870 /* MD interface: Symbol and relocation handling. */
27872 /* Return the address within the segment that a PC-relative fixup is
27873 relative to. For ARM, PC-relative fixups applied to instructions
27874 are generally relative to the location of the fixup plus 8 bytes.
27875 Thumb branches are offset by 4, and Thumb loads relative to PC
27876 require special handling. */
27879 md_pcrel_from_section (fixS
* fixP
, segT seg
)
27881 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27883 /* If this is pc-relative and we are going to emit a relocation
27884 then we just want to put out any pipeline compensation that the linker
27885 will need. Otherwise we want to use the calculated base.
27886 For WinCE we skip the bias for externals as well, since this
27887 is how the MS ARM-CE assembler behaves and we want to be compatible. */
27889 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27890 || (arm_force_relocation (fixP
)
27892 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
27898 switch (fixP
->fx_r_type
)
27900 /* PC relative addressing on the Thumb is slightly odd as the
27901 bottom two bits of the PC are forced to zero for the
27902 calculation. This happens *after* application of the
27903 pipeline offset. However, Thumb adrl already adjusts for
27904 this, so we need not do it again. */
27905 case BFD_RELOC_ARM_THUMB_ADD
:
27908 case BFD_RELOC_ARM_THUMB_OFFSET
:
27909 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27910 case BFD_RELOC_ARM_T32_ADD_PC12
:
27911 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27912 return (base
+ 4) & ~3;
27914 /* Thumb branches are simply offset by +4. */
27915 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27916 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27917 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27918 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27919 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27920 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27921 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27922 case BFD_RELOC_ARM_THUMB_BF17
:
27923 case BFD_RELOC_ARM_THUMB_BF19
:
27924 case BFD_RELOC_ARM_THUMB_BF13
:
27925 case BFD_RELOC_ARM_THUMB_LOOP12
:
27928 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27930 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27931 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
27932 && ARM_IS_FUNC (fixP
->fx_addsy
)
27933 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27934 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27937 /* BLX is like branches above, but forces the low two bits of PC to
27939 case BFD_RELOC_THUMB_PCREL_BLX
:
27941 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27942 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
27943 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27944 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27945 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27946 return (base
+ 4) & ~3;
27948 /* ARM mode branches are offset by +8. However, the Windows CE
27949 loader expects the relocation not to take this into account. */
27950 case BFD_RELOC_ARM_PCREL_BLX
:
27952 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27953 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
27954 && ARM_IS_FUNC (fixP
->fx_addsy
)
27955 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27956 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27959 case BFD_RELOC_ARM_PCREL_CALL
:
27961 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27962 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
27963 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27964 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27965 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27968 case BFD_RELOC_ARM_PCREL_BRANCH
:
27969 case BFD_RELOC_ARM_PCREL_JUMP
:
27970 case BFD_RELOC_ARM_PLT32
:
27972 /* When handling fixups immediately, because we have already
27973 discovered the value of a symbol, or the address of the frag involved
27974 we must account for the offset by +8, as the OS loader will never see the reloc.
27975 see fixup_segment() in write.c
27976 The S_IS_EXTERNAL test handles the case of global symbols.
27977 Those need the calculated base, not just the pipe compensation the linker will need. */
27979 && fixP
->fx_addsy
!= NULL
27980 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27981 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27989 /* ARM mode loads relative to PC are also offset by +8. Unlike
27990 branches, the Windows CE loader *does* expect the relocation
27991 to take this into account. */
27992 case BFD_RELOC_ARM_OFFSET_IMM
:
27993 case BFD_RELOC_ARM_OFFSET_IMM8
:
27994 case BFD_RELOC_ARM_HWLITERAL
:
27995 case BFD_RELOC_ARM_LITERAL
:
27996 case BFD_RELOC_ARM_CP_OFF_IMM
:
28000 /* Other PC-relative relocations are un-offset. */
28006 static bool flag_warn_syms
= true;
28009 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
28011 /* PR 18347 - Warn if the user attempts to create a symbol with the same
28012 name as an ARM instruction. Whilst strictly speaking it is allowed, it
28013 does mean that the resulting code might be very confusing to the reader.
28014 Also this warning can be triggered if the user omits an operand before
28015 an immediate address, eg:
28019 GAS treats this as an assignment of the value of the symbol foo to a
28020 symbol LDR, and so (without this code) it will not issue any kind of
28021 warning or error message.
28023 Note - ARM instructions are case-insensitive but the strings in the hash
28024 table are all stored in lower case, so we must first ensure that name is
28026 if (flag_warn_syms
&& arm_ops_hsh
)
28028 char * nbuf
= strdup (name
);
28031 for (p
= nbuf
; *p
; p
++)
28033 if (str_hash_find (arm_ops_hsh
, nbuf
) != NULL
)
28035 static htab_t already_warned
= NULL
;
28037 if (already_warned
== NULL
)
28038 already_warned
= str_htab_create ();
28039 /* Only warn about the symbol once. To keep the code
28040 simple we let str_hash_insert do the lookup for us. */
28041 if (str_hash_find (already_warned
, nbuf
) == NULL
)
28043 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
28044 str_hash_insert (already_warned
, nbuf
, NULL
, 0);
28054 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
28055 Otherwise we have no need to default values of symbols. */
28058 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
28061 if (name
[0] == '_' && name
[1] == 'G'
28062 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
28066 if (symbol_find (name
))
28067 as_bad (_("GOT already in the symbol table"));
28069 GOT_symbol
= symbol_new (name
, undefined_section
,
28070 &zero_address_frag
, 0);
28080 /* Subroutine of md_apply_fix. Check to see if an immediate can be
28081 computed as two separate immediate values, added together. We
28082 already know that this value cannot be computed by just one ARM
28085 static unsigned int
28086 validate_immediate_twopart (unsigned int val
,
28087 unsigned int * highpart
)
28092 for (i
= 0; i
< 32; i
+= 2)
28093 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
28099 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
28101 else if (a
& 0xff0000)
28103 if (a
& 0xff000000)
28105 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
28109 gas_assert (a
& 0xff000000);
28110 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
28113 return (a
& 0xff) | (i
<< 7);
28120 validate_offset_imm (unsigned int val
, int hwse
)
28122 if ((hwse
&& val
> 255) || val
> 4095)
28127 /* Subroutine of md_apply_fix. Do those data_ops which can take a
28128 negative immediate constant by altering the instruction. A bit of
28133 by inverting the second operand, and
28136 by negating the second operand. */
28139 negate_data_op (unsigned long * instruction
,
28140 unsigned long value
)
28143 unsigned long negated
, inverted
;
28145 negated
= encode_arm_immediate (-value
);
28146 inverted
= encode_arm_immediate (~value
);
28148 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
28151 /* First negates. */
28152 case OPCODE_SUB
: /* ADD <-> SUB */
28153 new_inst
= OPCODE_ADD
;
28158 new_inst
= OPCODE_SUB
;
28162 case OPCODE_CMP
: /* CMP <-> CMN */
28163 new_inst
= OPCODE_CMN
;
28168 new_inst
= OPCODE_CMP
;
28172 /* Now Inverted ops. */
28173 case OPCODE_MOV
: /* MOV <-> MVN */
28174 new_inst
= OPCODE_MVN
;
28179 new_inst
= OPCODE_MOV
;
28183 case OPCODE_AND
: /* AND <-> BIC */
28184 new_inst
= OPCODE_BIC
;
28189 new_inst
= OPCODE_AND
;
28193 case OPCODE_ADC
: /* ADC <-> SBC */
28194 new_inst
= OPCODE_SBC
;
28199 new_inst
= OPCODE_ADC
;
28203 /* We cannot do anything. */
28208 if (value
== (unsigned) FAIL
)
28211 *instruction
&= OPCODE_MASK
;
28212 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
28216 /* Like negate_data_op, but for Thumb-2. */
28218 static unsigned int
28219 thumb32_negate_data_op (valueT
*instruction
, unsigned int value
)
28221 unsigned int op
, new_inst
;
28223 unsigned int negated
, inverted
;
28225 negated
= encode_thumb32_immediate (-value
);
28226 inverted
= encode_thumb32_immediate (~value
);
28228 rd
= (*instruction
>> 8) & 0xf;
28229 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
28232 /* ADD <-> SUB. Includes CMP <-> CMN. */
28233 case T2_OPCODE_SUB
:
28234 new_inst
= T2_OPCODE_ADD
;
28238 case T2_OPCODE_ADD
:
28239 new_inst
= T2_OPCODE_SUB
;
28243 /* ORR <-> ORN. Includes MOV <-> MVN. */
28244 case T2_OPCODE_ORR
:
28245 new_inst
= T2_OPCODE_ORN
;
28249 case T2_OPCODE_ORN
:
28250 new_inst
= T2_OPCODE_ORR
;
28254 /* AND <-> BIC. TST has no inverted equivalent. */
28255 case T2_OPCODE_AND
:
28256 new_inst
= T2_OPCODE_BIC
;
28263 case T2_OPCODE_BIC
:
28264 new_inst
= T2_OPCODE_AND
;
28269 case T2_OPCODE_ADC
:
28270 new_inst
= T2_OPCODE_SBC
;
28274 case T2_OPCODE_SBC
:
28275 new_inst
= T2_OPCODE_ADC
;
28279 /* We cannot do anything. */
28284 if (value
== (unsigned int)FAIL
)
28287 *instruction
&= T2_OPCODE_MASK
;
28288 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
28292 /* Read a 32-bit thumb instruction from buf. */
28294 static unsigned long
28295 get_thumb32_insn (char * buf
)
28297 unsigned long insn
;
28298 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
28299 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28304 /* We usually want to set the low bit on the address of thumb function
28305 symbols. In particular .word foo - . should have the low bit set.
28306 Generic code tries to fold the difference of two symbols to
28307 a constant. Prevent this and force a relocation when the first symbols
28308 is a thumb function. */
28311 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
28313 if (op
== O_subtract
28314 && l
->X_op
== O_symbol
28315 && r
->X_op
== O_symbol
28316 && THUMB_IS_FUNC (l
->X_add_symbol
))
28318 l
->X_op
= O_subtract
;
28319 l
->X_op_symbol
= r
->X_add_symbol
;
28320 l
->X_add_number
-= r
->X_add_number
;
28324 /* Process as normal. */
28328 /* Encode Thumb2 unconditional branches and calls. The encoding
28329 for the 2 are identical for the immediate values. */
28332 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
28334 #define T2I1I2MASK ((1 << 13) | (1 << 11))
28337 addressT S
, I1
, I2
, lo
, hi
;
28339 S
= (value
>> 24) & 0x01;
28340 I1
= (value
>> 23) & 0x01;
28341 I2
= (value
>> 22) & 0x01;
28342 hi
= (value
>> 12) & 0x3ff;
28343 lo
= (value
>> 1) & 0x7ff;
28344 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28345 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28346 newval
|= (S
<< 10) | hi
;
28347 newval2
&= ~T2I1I2MASK
;
28348 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
28349 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28350 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28354 md_apply_fix (fixS
* fixP
,
28358 valueT value
= * valP
;
28360 unsigned int newimm
;
28361 unsigned long temp
;
28363 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
28365 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
28367 /* Note whether this will delete the relocation. */
28369 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
28372 /* On a 64-bit host, silently truncate 'value' to 32 bits for
28373 consistency with the behaviour on 32-bit hosts. Remember value
28375 value
&= 0xffffffff;
28376 value
^= 0x80000000;
28377 value
-= 0x80000000;
28380 fixP
->fx_addnumber
= value
;
28382 /* Same treatment for fixP->fx_offset. */
28383 fixP
->fx_offset
&= 0xffffffff;
28384 fixP
->fx_offset
^= 0x80000000;
28385 fixP
->fx_offset
-= 0x80000000;
28387 switch (fixP
->fx_r_type
)
28389 case BFD_RELOC_NONE
:
28390 /* This will need to go in the object file. */
28394 case BFD_RELOC_ARM_IMMEDIATE
:
28395 /* We claim that this fixup has been processed here,
28396 even if in fact we generate an error because we do
28397 not have a reloc for it, so tc_gen_reloc will reject it. */
28400 if (fixP
->fx_addsy
)
28402 const char *msg
= 0;
28404 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28405 msg
= _("undefined symbol %s used as an immediate value");
28406 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28407 msg
= _("symbol %s is in a different section");
28408 else if (S_IS_WEAK (fixP
->fx_addsy
))
28409 msg
= _("symbol %s is weak and may be overridden later");
28413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28414 msg
, S_GET_NAME (fixP
->fx_addsy
));
28419 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28421 /* If the offset is negative, we should use encoding A2 for ADR. */
28422 if ((temp
& 0xfff0000) == 0x28f0000 && (offsetT
) value
< 0)
28423 newimm
= negate_data_op (&temp
, value
);
28426 newimm
= encode_arm_immediate (value
);
28428 /* If the instruction will fail, see if we can fix things up by
28429 changing the opcode. */
28430 if (newimm
== (unsigned int) FAIL
)
28431 newimm
= negate_data_op (&temp
, value
);
28432 /* MOV accepts both ARM modified immediate (A1 encoding) and
28433 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
28434 When disassembling, MOV is preferred when there is no encoding
28436 if (newimm
== (unsigned int) FAIL
28437 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
28438 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
28439 && !((temp
>> SBIT_SHIFT
) & 0x1)
28440 && value
<= 0xffff)
28442 /* Clear bits[23:20] to change encoding from A1 to A2. */
28443 temp
&= 0xff0fffff;
28444 /* Encoding high 4bits imm. Code below will encode the remaining
28446 temp
|= (value
& 0x0000f000) << 4;
28447 newimm
= value
& 0x00000fff;
28451 if (newimm
== (unsigned int) FAIL
)
28453 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28454 _("invalid constant (%lx) after fixup"),
28455 (unsigned long) value
);
28459 newimm
|= (temp
& 0xfffff000);
28460 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28463 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28465 unsigned int highpart
= 0;
28466 unsigned int newinsn
= 0xe1a00000; /* nop. */
28468 if (fixP
->fx_addsy
)
28470 const char *msg
= 0;
28472 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28473 msg
= _("undefined symbol %s used as an immediate value");
28474 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28475 msg
= _("symbol %s is in a different section");
28476 else if (S_IS_WEAK (fixP
->fx_addsy
))
28477 msg
= _("symbol %s is weak and may be overridden later");
28481 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28482 msg
, S_GET_NAME (fixP
->fx_addsy
));
28487 newimm
= encode_arm_immediate (value
);
28488 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28490 /* If the instruction will fail, see if we can fix things up by
28491 changing the opcode. */
28492 if (newimm
== (unsigned int) FAIL
28493 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
28495 /* No ? OK - try using two ADD instructions to generate
28497 newimm
= validate_immediate_twopart (value
, & highpart
);
28499 /* Yes - then make sure that the second instruction is
28501 if (newimm
!= (unsigned int) FAIL
)
28503 /* Still No ? Try using a negated value. */
28504 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
28505 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
28506 /* Otherwise - give up. */
28509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28510 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
28515 /* Replace the first operand in the 2nd instruction (which
28516 is the PC) with the destination register. We have
28517 already added in the PC in the first instruction and we
28518 do not want to do it again. */
28519 newinsn
&= ~ 0xf0000;
28520 newinsn
|= ((newinsn
& 0x0f000) << 4);
28523 newimm
|= (temp
& 0xfffff000);
28524 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28526 highpart
|= (newinsn
& 0xfffff000);
28527 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
28531 case BFD_RELOC_ARM_OFFSET_IMM
:
28532 if (!fixP
->fx_done
&& seg
->use_rela_p
)
28534 /* Fall through. */
28536 case BFD_RELOC_ARM_LITERAL
:
28537 sign
= (offsetT
) value
> 0;
28539 if ((offsetT
) value
< 0)
28542 if (validate_offset_imm (value
, 0) == FAIL
)
28544 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
28545 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28546 _("invalid literal constant: pool needs to be closer"));
28548 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28549 _("bad immediate value for offset (%ld)"),
28554 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28556 newval
&= 0xfffff000;
28559 newval
&= 0xff7ff000;
28560 newval
|= value
| (sign
? INDEX_UP
: 0);
28562 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28565 case BFD_RELOC_ARM_OFFSET_IMM8
:
28566 case BFD_RELOC_ARM_HWLITERAL
:
28567 sign
= (offsetT
) value
> 0;
28569 if ((offsetT
) value
< 0)
28572 if (validate_offset_imm (value
, 1) == FAIL
)
28574 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
28575 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28576 _("invalid literal constant: pool needs to be closer"));
28578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28579 _("bad immediate value for 8-bit offset (%ld)"),
28584 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28586 newval
&= 0xfffff0f0;
28589 newval
&= 0xff7ff0f0;
28590 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
28592 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28595 case BFD_RELOC_ARM_T32_OFFSET_U8
:
28596 if (value
> 1020 || value
% 4 != 0)
28597 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28598 _("bad immediate value for offset (%ld)"), (long) value
);
28601 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
28603 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
28606 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
28607 /* This is a complicated relocation used for all varieties of Thumb32
28608 load/store instruction with immediate offset:
28610 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
28611 *4, optional writeback(W)
28612 (doubleword load/store)
28614 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
28615 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
28616 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
28617 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
28618 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
28620 Uppercase letters indicate bits that are already encoded at
28621 this point. Lowercase letters are our problem. For the
28622 second block of instructions, the secondary opcode nybble
28623 (bits 8..11) is present, and bit 23 is zero, even if this is
28624 a PC-relative operation. */
28625 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28627 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
28629 if ((newval
& 0xf0000000) == 0xe0000000)
28631 /* Doubleword load/store: 8-bit offset, scaled by 4. */
28632 if ((offsetT
) value
>= 0)
28633 newval
|= (1 << 23);
28636 if (value
% 4 != 0)
28638 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28639 _("offset not a multiple of 4"));
28645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28646 _("offset out of range"));
28651 else if ((newval
& 0x000f0000) == 0x000f0000)
28653 /* PC-relative, 12-bit offset. */
28654 if ((offsetT
) value
>= 0)
28655 newval
|= (1 << 23);
28660 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28661 _("offset out of range"));
28666 else if ((newval
& 0x00000100) == 0x00000100)
28668 /* Writeback: 8-bit, +/- offset. */
28669 if ((offsetT
) value
>= 0)
28670 newval
|= (1 << 9);
28675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28676 _("offset out of range"));
28681 else if ((newval
& 0x00000f00) == 0x00000e00)
28683 /* T-instruction: positive 8-bit offset. */
28686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28687 _("offset out of range"));
28695 /* Positive 12-bit or negative 8-bit offset. */
28696 unsigned int limit
;
28697 if ((offsetT
) value
>= 0)
28699 newval
|= (1 << 23);
28709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28710 _("offset out of range"));
28717 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
28718 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
28721 case BFD_RELOC_ARM_SHIFT_IMM
:
28722 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28725 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
28727 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28728 _("shift expression is too large"));
28733 /* Shifts of zero must be done as lsl. */
28735 else if (value
== 32)
28737 newval
&= 0xfffff07f;
28738 newval
|= (value
& 0x1f) << 7;
28739 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28742 case BFD_RELOC_ARM_T32_IMMEDIATE
:
28743 case BFD_RELOC_ARM_T32_ADD_IMM
:
28744 case BFD_RELOC_ARM_T32_IMM12
:
28745 case BFD_RELOC_ARM_T32_ADD_PC12
:
28746 /* We claim that this fixup has been processed here,
28747 even if in fact we generate an error because we do
28748 not have a reloc for it, so tc_gen_reloc will reject it. */
28752 && ! S_IS_DEFINED (fixP
->fx_addsy
))
28754 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28755 _("undefined symbol %s used as an immediate value"),
28756 S_GET_NAME (fixP
->fx_addsy
));
28760 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28762 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
28765 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28766 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28767 Thumb2 modified immediate encoding (T2). */
28768 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
28769 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28771 newimm
= encode_thumb32_immediate (value
);
28772 if (newimm
== (unsigned int) FAIL
)
28773 newimm
= thumb32_negate_data_op (&newval
, value
);
28775 if (newimm
== (unsigned int) FAIL
)
28777 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
28779 /* Turn add/sum into addw/subw. */
28780 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28781 newval
= (newval
& 0xfeffffff) | 0x02000000;
28782 /* No flat 12-bit imm encoding for addsw/subsw. */
28783 if ((newval
& 0x00100000) == 0)
28785 /* 12 bit immediate for addw/subw. */
28786 if ((offsetT
) value
< 0)
28789 newval
^= 0x00a00000;
28792 newimm
= (unsigned int) FAIL
;
28799 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28800 UINT16 (T3 encoding), MOVW only accepts UINT16. When
28801 disassembling, MOV is preferred when there is no encoding
28803 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
28804 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28805 but with the Rn field [19:16] set to 1111. */
28806 && (((newval
>> 16) & 0xf) == 0xf)
28807 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
28808 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
28809 && value
<= 0xffff)
28811 /* Toggle bit[25] to change encoding from T2 to T3. */
28813 /* Clear bits[19:16]. */
28814 newval
&= 0xfff0ffff;
28815 /* Encoding high 4bits imm. Code below will encode the
28816 remaining low 12bits. */
28817 newval
|= (value
& 0x0000f000) << 4;
28818 newimm
= value
& 0x00000fff;
28823 if (newimm
== (unsigned int)FAIL
)
28825 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28826 _("invalid constant (%lx) after fixup"),
28827 (unsigned long) value
);
28831 newval
|= (newimm
& 0x800) << 15;
28832 newval
|= (newimm
& 0x700) << 4;
28833 newval
|= (newimm
& 0x0ff);
28835 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
28836 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
28839 case BFD_RELOC_ARM_SMC
:
28841 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28842 _("invalid smc expression"));
28844 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28845 newval
|= (value
& 0xf);
28846 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28849 case BFD_RELOC_ARM_HVC
:
28850 if (value
> 0xffff)
28851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28852 _("invalid hvc expression"));
28853 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28854 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
28855 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28858 case BFD_RELOC_ARM_SWI
:
28859 if (fixP
->tc_fix_data
!= 0)
28862 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28863 _("invalid swi expression"));
28864 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28866 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28870 if (value
> 0x00ffffff)
28871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28872 _("invalid swi expression"));
28873 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28875 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28879 case BFD_RELOC_ARM_MULTI
:
28880 if (value
> 0xffff)
28881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28882 _("invalid expression in load/store multiple"));
28883 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
28884 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28888 case BFD_RELOC_ARM_PCREL_CALL
:
28890 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28892 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
28893 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28894 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28895 /* Flip the bl to blx. This is a simple flip
28896 bit here because we generate PCREL_CALL for
28897 unconditional bls. */
28899 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28900 newval
= newval
| 0x10000000;
28901 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28907 goto arm_branch_common
;
28909 case BFD_RELOC_ARM_PCREL_JUMP
:
28910 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28912 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
28913 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28914 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28916 /* This would map to a bl<cond>, b<cond>,
28917 b<always> to a Thumb function. We
28918 need to force a relocation for this particular
28920 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28923 /* Fall through. */
28925 case BFD_RELOC_ARM_PLT32
:
28927 case BFD_RELOC_ARM_PCREL_BRANCH
:
28929 goto arm_branch_common
;
28931 case BFD_RELOC_ARM_PCREL_BLX
:
28934 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28936 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
28937 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28938 && ARM_IS_FUNC (fixP
->fx_addsy
))
28940 /* Flip the blx to a bl and warn. */
28941 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28942 newval
= 0xeb000000;
28943 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28944 _("blx to '%s' an ARM ISA state function changed to bl"),
28946 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28952 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28953 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
28957 /* We are going to store value (shifted right by two) in the
28958 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28959 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28962 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28963 _("misaligned branch destination"));
28964 if ((value
& 0xfe000000) != 0
28965 && (value
& 0xfe000000) != 0xfe000000)
28966 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28968 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28970 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28971 newval
|= (value
>> 2) & 0x00ffffff;
28972 /* Set the H bit on BLX instructions. */
28976 newval
|= 0x01000000;
28978 newval
&= ~0x01000000;
28980 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28984 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28985 /* CBZ can only branch forward. */
28987 /* Attempts to use CBZ to branch to the next instruction
28988 (which, strictly speaking, are prohibited) will be turned into
28991 FIXME: It may be better to remove the instruction completely and
28992 perform relaxation. */
28993 if ((offsetT
) value
== -2)
28995 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28996 newval
= 0xbf00; /* NOP encoding T1 */
28997 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29002 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29004 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29006 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29007 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
29008 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29013 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
29014 if (out_of_range_p (value
, 8))
29015 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29017 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29019 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29020 newval
|= (value
& 0x1ff) >> 1;
29021 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29025 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
29026 if (out_of_range_p (value
, 11))
29027 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29029 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29031 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29032 newval
|= (value
& 0xfff) >> 1;
29033 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29037 /* This relocation is misnamed, it should be BRANCH21. */
29038 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29040 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29041 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
29042 && ARM_IS_FUNC (fixP
->fx_addsy
)
29043 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29045 /* Force a relocation for a branch 20 bits wide. */
29048 if (out_of_range_p (value
, 20))
29049 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29050 _("conditional branch out of range"));
29052 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29055 addressT S
, J1
, J2
, lo
, hi
;
29057 S
= (value
& 0x00100000) >> 20;
29058 J2
= (value
& 0x00080000) >> 19;
29059 J1
= (value
& 0x00040000) >> 18;
29060 hi
= (value
& 0x0003f000) >> 12;
29061 lo
= (value
& 0x00000ffe) >> 1;
29063 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29064 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29065 newval
|= (S
<< 10) | hi
;
29066 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
29067 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29068 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29072 case BFD_RELOC_THUMB_PCREL_BLX
:
29073 /* If there is a blx from a thumb state function to
29074 another thumb function flip this to a bl and warn
29078 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
29079 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29080 && THUMB_IS_FUNC (fixP
->fx_addsy
))
29082 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
29083 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29084 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
29086 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29087 newval
= newval
| 0x1000;
29088 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29089 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29094 goto thumb_bl_common
;
29096 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29097 /* A bl from Thumb state ISA to an internal ARM state function
29098 is converted to a blx. */
29100 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29101 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
29102 && ARM_IS_FUNC (fixP
->fx_addsy
)
29103 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29105 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29106 newval
= newval
& ~0x1000;
29107 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29108 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
29114 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29115 /* For a BLX instruction, make sure that the relocation is rounded up
29116 to a word boundary. This follows the semantics of the instruction
29117 which specifies that bit 1 of the target address will come from bit
29118 1 of the base address. */
29119 value
= (value
+ 3) & ~ 3;
29122 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
29123 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29124 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29127 if (out_of_range_p (value
, 22))
29129 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
29130 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29131 else if (out_of_range_p (value
, 24))
29132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29133 _("Thumb2 branch out of range"));
29136 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29137 encode_thumb2_b_bl_offset (buf
, value
);
29141 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29142 if (out_of_range_p (value
, 24))
29143 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29145 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29146 encode_thumb2_b_bl_offset (buf
, value
);
29151 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29156 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29157 md_number_to_chars (buf
, value
, 2);
29161 case BFD_RELOC_ARM_TLS_CALL
:
29162 case BFD_RELOC_ARM_THM_TLS_CALL
:
29163 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29164 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29165 case BFD_RELOC_ARM_TLS_GOTDESC
:
29166 case BFD_RELOC_ARM_TLS_GD32
:
29167 case BFD_RELOC_ARM_TLS_LE32
:
29168 case BFD_RELOC_ARM_TLS_IE32
:
29169 case BFD_RELOC_ARM_TLS_LDM32
:
29170 case BFD_RELOC_ARM_TLS_LDO32
:
29171 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29174 /* Same handling as above, but with the arm_fdpic guard. */
29175 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29176 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29177 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29180 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29184 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29185 _("Relocation supported only in FDPIC mode"));
29189 case BFD_RELOC_ARM_GOT32
:
29190 case BFD_RELOC_ARM_GOTOFF
:
29193 case BFD_RELOC_ARM_GOT_PREL
:
29194 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29195 md_number_to_chars (buf
, value
, 4);
29198 case BFD_RELOC_ARM_TARGET2
:
29199 /* TARGET2 is not partial-inplace, so we need to write the
29200 addend here for REL targets, because it won't be written out
29201 during reloc processing later. */
29202 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29203 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
29206 /* Relocations for FDPIC. */
29207 case BFD_RELOC_ARM_GOTFUNCDESC
:
29208 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29209 case BFD_RELOC_ARM_FUNCDESC
:
29212 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29213 md_number_to_chars (buf
, 0, 4);
29217 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29218 _("Relocation supported only in FDPIC mode"));
29223 case BFD_RELOC_RVA
:
29225 case BFD_RELOC_ARM_TARGET1
:
29226 case BFD_RELOC_ARM_ROSEGREL32
:
29227 case BFD_RELOC_ARM_SBREL32
:
29228 case BFD_RELOC_32_PCREL
:
29230 case BFD_RELOC_32_SECREL
:
29232 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29234 /* For WinCE we only do this for pcrel fixups. */
29235 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
29237 md_number_to_chars (buf
, value
, 4);
29241 case BFD_RELOC_ARM_PREL31
:
29242 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29244 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
29245 if ((value
^ (value
>> 1)) & 0x40000000)
29247 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29248 _("rel31 relocation overflow"));
29250 newval
|= value
& 0x7fffffff;
29251 md_number_to_chars (buf
, newval
, 4);
29256 case BFD_RELOC_ARM_CP_OFF_IMM
:
29257 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
29258 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
29259 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
29260 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29262 newval
= get_thumb32_insn (buf
);
29263 if ((newval
& 0x0f200f00) == 0x0d000900)
29265 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
29266 has permitted values that are multiples of 2, in the range -510
29268 if (value
+ 510 > 510 + 510 || (value
& 1))
29269 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29270 _("co-processor offset out of range"));
29272 else if ((newval
& 0xfe001f80) == 0xec000f80)
29274 if (value
+ 511 > 512 + 511 || (value
& 3))
29275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29276 _("co-processor offset out of range"));
29278 else if (value
+ 1023 > 1023 + 1023 || (value
& 3))
29279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29280 _("co-processor offset out of range"));
29282 sign
= (offsetT
) value
> 0;
29283 if ((offsetT
) value
< 0)
29285 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29286 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29287 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29289 newval
= get_thumb32_insn (buf
);
29292 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29293 newval
&= 0xffffff80;
29295 newval
&= 0xffffff00;
29299 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29300 newval
&= 0xff7fff80;
29302 newval
&= 0xff7fff00;
29303 if ((newval
& 0x0f200f00) == 0x0d000900)
29305 /* This is a fp16 vstr/vldr.
29307 It requires the immediate offset in the instruction is shifted
29308 left by 1 to be a half-word offset.
29310 Here, left shift by 1 first, and later right shift by 2
29311 should get the right offset. */
29314 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
29316 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29317 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29318 md_number_to_chars (buf
, newval
, INSN_SIZE
);
29320 put_thumb32_insn (buf
, newval
);
29323 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
29324 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
29325 if (value
+ 255 > 255 + 255)
29326 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29327 _("co-processor offset out of range"));
29329 goto cp_off_common
;
29331 case BFD_RELOC_ARM_THUMB_OFFSET
:
29332 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29333 /* Exactly what ranges, and where the offset is inserted depends
29334 on the type of instruction, we can establish this from the
29336 switch (newval
>> 12)
29338 case 4: /* PC load. */
29339 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
29340 forced to zero for these loads; md_pcrel_from has already
29341 compensated for this. */
29343 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29344 _("invalid offset, target not word aligned (0x%08lX)"),
29345 (((unsigned long) fixP
->fx_frag
->fr_address
29346 + (unsigned long) fixP
->fx_where
) & ~3)
29347 + (unsigned long) value
);
29348 else if (get_recorded_alignment (seg
) < 2)
29349 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29350 _("section does not have enough alignment to ensure safe PC-relative loads"));
29352 if (value
& ~0x3fc)
29353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29354 _("invalid offset, value too big (0x%08lX)"),
29357 newval
|= value
>> 2;
29360 case 9: /* SP load/store. */
29361 if (value
& ~0x3fc)
29362 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29363 _("invalid offset, value too big (0x%08lX)"),
29365 newval
|= value
>> 2;
29368 case 6: /* Word load/store. */
29370 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29371 _("invalid offset, value too big (0x%08lX)"),
29373 newval
|= value
<< 4; /* 6 - 2. */
29376 case 7: /* Byte load/store. */
29378 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29379 _("invalid offset, value too big (0x%08lX)"),
29381 newval
|= value
<< 6;
29384 case 8: /* Halfword load/store. */
29386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29387 _("invalid offset, value too big (0x%08lX)"),
29389 newval
|= value
<< 5; /* 6 - 1. */
29393 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29394 "Unable to process relocation for thumb opcode: %lx",
29395 (unsigned long) newval
);
29398 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29401 case BFD_RELOC_ARM_THUMB_ADD
:
29402 /* This is a complicated relocation, since we use it for all of
29403 the following immediate relocations:
29407 9bit ADD/SUB SP word-aligned
29408 10bit ADD PC/SP word-aligned
29410 The type of instruction being processed is encoded in the
29417 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29419 int rd
= (newval
>> 4) & 0xf;
29420 int rs
= newval
& 0xf;
29421 int subtract
= !!(newval
& 0x8000);
29423 /* Check for HI regs, only very restricted cases allowed:
29424 Adjusting SP, and using PC or SP to get an address. */
29425 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
29426 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
29427 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29428 _("invalid Hi register with immediate"));
29430 /* If value is negative, choose the opposite instruction. */
29431 if ((offsetT
) value
< 0)
29434 subtract
= !subtract
;
29435 if ((offsetT
) value
< 0)
29436 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29437 _("immediate value out of range"));
29442 if (value
& ~0x1fc)
29443 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29444 _("invalid immediate for stack address calculation"));
29445 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
29446 newval
|= value
>> 2;
29448 else if (rs
== REG_PC
|| rs
== REG_SP
)
29450 /* PR gas/18541. If the addition is for a defined symbol
29451 within range of an ADR instruction then accept it. */
29454 && fixP
->fx_addsy
!= NULL
)
29458 if (! S_IS_DEFINED (fixP
->fx_addsy
)
29459 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
29460 || S_IS_WEAK (fixP
->fx_addsy
))
29462 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29463 _("address calculation needs a strongly defined nearby symbol"));
29467 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
29469 /* Round up to the next 4-byte boundary. */
29474 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
29478 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29479 _("symbol too far away"));
29489 if (subtract
|| value
& ~0x3fc)
29490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29491 _("invalid immediate for address calculation (value = 0x%08lX)"),
29492 (unsigned long) (subtract
? - value
: value
));
29493 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
29495 newval
|= value
>> 2;
29500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29501 _("immediate value out of range"));
29502 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
29503 newval
|= (rd
<< 8) | value
;
29508 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29509 _("immediate value out of range"));
29510 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
29511 newval
|= rd
| (rs
<< 3) | (value
<< 6);
29514 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29517 case BFD_RELOC_ARM_THUMB_IMM
:
29518 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29520 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29521 _("invalid immediate: %ld is out of range"),
29524 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29527 case BFD_RELOC_ARM_THUMB_SHIFT
:
29528 /* 5bit shift value (0..32). LSL cannot take 32. */
29529 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
29530 temp
= newval
& 0xf800;
29531 if (value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
29532 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29533 _("invalid shift value: %ld"), (long) value
);
29534 /* Shifts of zero must be encoded as LSL. */
29536 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
29537 /* Shifts of 32 are encoded as zero. */
29538 else if (value
== 32)
29540 newval
|= value
<< 6;
29541 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29544 case BFD_RELOC_VTABLE_INHERIT
:
29545 case BFD_RELOC_VTABLE_ENTRY
:
29549 case BFD_RELOC_ARM_MOVW
:
29550 case BFD_RELOC_ARM_MOVT
:
29551 case BFD_RELOC_ARM_THUMB_MOVW
:
29552 case BFD_RELOC_ARM_THUMB_MOVT
:
29553 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29555 /* REL format relocations are limited to a 16-bit addend. */
29556 if (!fixP
->fx_done
)
29558 if (value
+ 0x8000 > 0x7fff + 0x8000)
29559 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29560 _("offset out of range"));
29562 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29563 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29568 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29569 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29571 newval
= get_thumb32_insn (buf
);
29572 newval
&= 0xfbf08f00;
29573 newval
|= (value
& 0xf000) << 4;
29574 newval
|= (value
& 0x0800) << 15;
29575 newval
|= (value
& 0x0700) << 4;
29576 newval
|= (value
& 0x00ff);
29577 put_thumb32_insn (buf
, newval
);
29581 newval
= md_chars_to_number (buf
, 4);
29582 newval
&= 0xfff0f000;
29583 newval
|= value
& 0x0fff;
29584 newval
|= (value
& 0xf000) << 4;
29585 md_number_to_chars (buf
, newval
, 4);
29590 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29591 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29592 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29593 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29594 gas_assert (!fixP
->fx_done
);
29598 bfd_vma encoded_addend
= value
;
29600 /* Check that addend can be encoded in instruction. */
29601 if (!seg
->use_rela_p
&& value
> 255)
29602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29603 _("the offset 0x%08lX is not representable"),
29604 (unsigned long) encoded_addend
);
29606 /* Extract the instruction. */
29607 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
29608 is_mov
= (insn
& 0xf800) == 0x2000;
29613 if (!seg
->use_rela_p
)
29614 insn
|= encoded_addend
;
29620 /* Extract the instruction. */
29621 /* Encoding is the following
29626 /* The following conditions must be true :
29631 rd
= (insn
>> 4) & 0xf;
29633 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
29634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29635 _("Unable to process relocation for thumb opcode: %lx"),
29636 (unsigned long) insn
);
29638 /* Encode as ADD immediate8 thumb 1 code. */
29639 insn
= 0x3000 | (rd
<< 8);
29641 /* Place the encoded addend into the first 8 bits of the
29643 if (!seg
->use_rela_p
)
29644 insn
|= encoded_addend
;
29647 /* Update the instruction. */
29648 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
29652 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29653 case BFD_RELOC_ARM_ALU_PC_G0
:
29654 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29655 case BFD_RELOC_ARM_ALU_PC_G1
:
29656 case BFD_RELOC_ARM_ALU_PC_G2
:
29657 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29658 case BFD_RELOC_ARM_ALU_SB_G0
:
29659 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29660 case BFD_RELOC_ARM_ALU_SB_G1
:
29661 case BFD_RELOC_ARM_ALU_SB_G2
:
29662 gas_assert (!fixP
->fx_done
);
29663 if (!seg
->use_rela_p
)
29666 bfd_vma encoded_addend
;
29667 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29669 /* Check that the absolute value of the addend can be
29670 expressed as an 8-bit constant plus a rotation. */
29671 encoded_addend
= encode_arm_immediate (addend_abs
);
29672 if (encoded_addend
== (unsigned int) FAIL
)
29673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29674 _("the offset 0x%08lX is not representable"),
29675 (unsigned long) addend_abs
);
29677 /* Extract the instruction. */
29678 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29680 /* If the addend is positive, use an ADD instruction.
29681 Otherwise use a SUB. Take care not to destroy the S bit. */
29682 insn
&= 0xff1fffff;
29683 if ((offsetT
) value
< 0)
29688 /* Place the encoded addend into the first 12 bits of the
29690 insn
&= 0xfffff000;
29691 insn
|= encoded_addend
;
29693 /* Update the instruction. */
29694 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29698 case BFD_RELOC_ARM_LDR_PC_G0
:
29699 case BFD_RELOC_ARM_LDR_PC_G1
:
29700 case BFD_RELOC_ARM_LDR_PC_G2
:
29701 case BFD_RELOC_ARM_LDR_SB_G0
:
29702 case BFD_RELOC_ARM_LDR_SB_G1
:
29703 case BFD_RELOC_ARM_LDR_SB_G2
:
29704 gas_assert (!fixP
->fx_done
);
29705 if (!seg
->use_rela_p
)
29708 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29710 /* Check that the absolute value of the addend can be
29711 encoded in 12 bits. */
29712 if (addend_abs
>= 0x1000)
29713 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29714 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
29715 (unsigned long) addend_abs
);
29717 /* Extract the instruction. */
29718 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29720 /* If the addend is negative, clear bit 23 of the instruction.
29721 Otherwise set it. */
29722 if ((offsetT
) value
< 0)
29723 insn
&= ~(1 << 23);
29727 /* Place the absolute value of the addend into the first 12 bits
29728 of the instruction. */
29729 insn
&= 0xfffff000;
29730 insn
|= addend_abs
;
29732 /* Update the instruction. */
29733 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29737 case BFD_RELOC_ARM_LDRS_PC_G0
:
29738 case BFD_RELOC_ARM_LDRS_PC_G1
:
29739 case BFD_RELOC_ARM_LDRS_PC_G2
:
29740 case BFD_RELOC_ARM_LDRS_SB_G0
:
29741 case BFD_RELOC_ARM_LDRS_SB_G1
:
29742 case BFD_RELOC_ARM_LDRS_SB_G2
:
29743 gas_assert (!fixP
->fx_done
);
29744 if (!seg
->use_rela_p
)
29747 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29749 /* Check that the absolute value of the addend can be
29750 encoded in 8 bits. */
29751 if (addend_abs
>= 0x100)
29752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29753 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29754 (unsigned long) addend_abs
);
29756 /* Extract the instruction. */
29757 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29759 /* If the addend is negative, clear bit 23 of the instruction.
29760 Otherwise set it. */
29761 if ((offsetT
) value
< 0)
29762 insn
&= ~(1 << 23);
29766 /* Place the first four bits of the absolute value of the addend
29767 into the first 4 bits of the instruction, and the remaining
29768 four into bits 8 .. 11. */
29769 insn
&= 0xfffff0f0;
29770 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
29772 /* Update the instruction. */
29773 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29777 case BFD_RELOC_ARM_LDC_PC_G0
:
29778 case BFD_RELOC_ARM_LDC_PC_G1
:
29779 case BFD_RELOC_ARM_LDC_PC_G2
:
29780 case BFD_RELOC_ARM_LDC_SB_G0
:
29781 case BFD_RELOC_ARM_LDC_SB_G1
:
29782 case BFD_RELOC_ARM_LDC_SB_G2
:
29783 gas_assert (!fixP
->fx_done
);
29784 if (!seg
->use_rela_p
)
29787 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29789 /* Check that the absolute value of the addend is a multiple of
29790 four and, when divided by four, fits in 8 bits. */
29791 if (addend_abs
& 0x3)
29792 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29793 _("bad offset 0x%08lX (must be word-aligned)"),
29794 (unsigned long) addend_abs
);
29796 if ((addend_abs
>> 2) > 0xff)
29797 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29798 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29799 (unsigned long) addend_abs
);
29801 /* Extract the instruction. */
29802 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29804 /* If the addend is negative, clear bit 23 of the instruction.
29805 Otherwise set it. */
29806 if ((offsetT
) value
< 0)
29807 insn
&= ~(1 << 23);
29811 /* Place the addend (divided by four) into the first eight
29812 bits of the instruction. */
29813 insn
&= 0xfffffff0;
29814 insn
|= addend_abs
>> 2;
29816 /* Update the instruction. */
29817 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29821 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29823 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29824 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
29825 && ARM_IS_FUNC (fixP
->fx_addsy
)
29826 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29828 /* Force a relocation for a branch 5 bits wide. */
29831 if (v8_1_branch_value_check (value
, 5, false) == FAIL
)
29832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29835 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29837 addressT boff
= value
>> 1;
29839 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29840 newval
|= (boff
<< 7);
29841 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29845 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29847 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29848 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
29849 && ARM_IS_FUNC (fixP
->fx_addsy
)
29850 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29854 if ((value
& ~0x7f) && ((value
& ~0x3f) != (valueT
) ~0x3f))
29855 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29856 _("branch out of range"));
29858 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29860 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29862 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
29863 addressT diff
= value
- boff
;
29867 newval
|= 1 << 1; /* T bit. */
29869 else if (diff
!= 2)
29871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29872 _("out of range label-relative fixup value"));
29874 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29878 case BFD_RELOC_ARM_THUMB_BF17
:
29880 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29881 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
29882 && ARM_IS_FUNC (fixP
->fx_addsy
)
29883 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29885 /* Force a relocation for a branch 17 bits wide. */
29889 if (v8_1_branch_value_check (value
, 17, true) == FAIL
)
29890 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29893 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29896 addressT immA
, immB
, immC
;
29898 immA
= (value
& 0x0001f000) >> 12;
29899 immB
= (value
& 0x00000ffc) >> 2;
29900 immC
= (value
& 0x00000002) >> 1;
29902 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29903 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29905 newval2
|= (immC
<< 11) | (immB
<< 1);
29906 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29907 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29911 case BFD_RELOC_ARM_THUMB_BF19
:
29913 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29914 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
29915 && ARM_IS_FUNC (fixP
->fx_addsy
)
29916 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29918 /* Force a relocation for a branch 19 bits wide. */
29922 if (v8_1_branch_value_check (value
, 19, true) == FAIL
)
29923 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29926 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29929 addressT immA
, immB
, immC
;
29931 immA
= (value
& 0x0007f000) >> 12;
29932 immB
= (value
& 0x00000ffc) >> 2;
29933 immC
= (value
& 0x00000002) >> 1;
29935 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29936 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29938 newval2
|= (immC
<< 11) | (immB
<< 1);
29939 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29940 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29944 case BFD_RELOC_ARM_THUMB_BF13
:
29946 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29947 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
29948 && ARM_IS_FUNC (fixP
->fx_addsy
)
29949 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29951 /* Force a relocation for a branch 13 bits wide. */
29955 if (v8_1_branch_value_check (value
, 13, true) == FAIL
)
29956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29959 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29962 addressT immA
, immB
, immC
;
29964 immA
= (value
& 0x00001000) >> 12;
29965 immB
= (value
& 0x00000ffc) >> 2;
29966 immC
= (value
& 0x00000002) >> 1;
29968 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29969 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29971 newval2
|= (immC
<< 11) | (immB
<< 1);
29972 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29973 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29977 case BFD_RELOC_ARM_THUMB_LOOP12
:
29979 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29980 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
29981 && ARM_IS_FUNC (fixP
->fx_addsy
)
29982 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29984 /* Force a relocation for a branch 12 bits wide. */
29988 bfd_vma insn
= get_thumb32_insn (buf
);
29989 /* le lr, <label>, le <label> or letp lr, <label> */
29990 if (((insn
& 0xffffffff) == 0xf00fc001)
29991 || ((insn
& 0xffffffff) == 0xf02fc001)
29992 || ((insn
& 0xffffffff) == 0xf01fc001))
29995 if (v8_1_branch_value_check (value
, 12, false) == FAIL
)
29996 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29998 if (fixP
->fx_done
|| !seg
->use_rela_p
)
30000 addressT imml
, immh
;
30002 immh
= (value
& 0x00000ffc) >> 2;
30003 imml
= (value
& 0x00000002) >> 1;
30005 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
30006 newval
|= (imml
<< 11) | (immh
<< 1);
30007 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
30011 case BFD_RELOC_ARM_V4BX
:
30012 /* This will need to go in the object file. */
30016 case BFD_RELOC_UNUSED
:
30018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
30019 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
30023 /* Translate internal representation of relocation info to BFD target
30027 tc_gen_reloc (asection
*section
, fixS
*fixp
)
30030 bfd_reloc_code_real_type code
;
30032 reloc
= XNEW (arelent
);
30034 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
30035 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
30036 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
30038 if (fixp
->fx_pcrel
)
30040 if (section
->use_rela_p
)
30041 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
30043 fixp
->fx_offset
= reloc
->address
;
30045 reloc
->addend
= fixp
->fx_offset
;
30047 switch (fixp
->fx_r_type
)
30050 if (fixp
->fx_pcrel
)
30052 code
= BFD_RELOC_8_PCREL
;
30055 /* Fall through. */
30058 if (fixp
->fx_pcrel
)
30060 code
= BFD_RELOC_16_PCREL
;
30063 /* Fall through. */
30066 if (fixp
->fx_pcrel
)
30068 code
= BFD_RELOC_32_PCREL
;
30071 /* Fall through. */
30073 case BFD_RELOC_ARM_MOVW
:
30074 if (fixp
->fx_pcrel
)
30076 code
= BFD_RELOC_ARM_MOVW_PCREL
;
30079 /* Fall through. */
30081 case BFD_RELOC_ARM_MOVT
:
30082 if (fixp
->fx_pcrel
)
30084 code
= BFD_RELOC_ARM_MOVT_PCREL
;
30087 /* Fall through. */
30089 case BFD_RELOC_ARM_THUMB_MOVW
:
30090 if (fixp
->fx_pcrel
)
30092 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
30095 /* Fall through. */
30097 case BFD_RELOC_ARM_THUMB_MOVT
:
30098 if (fixp
->fx_pcrel
)
30100 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
30103 /* Fall through. */
30105 case BFD_RELOC_NONE
:
30106 case BFD_RELOC_ARM_PCREL_BRANCH
:
30107 case BFD_RELOC_ARM_PCREL_BLX
:
30108 case BFD_RELOC_RVA
:
30109 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
30110 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
30111 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
30112 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30113 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30114 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30115 case BFD_RELOC_VTABLE_ENTRY
:
30116 case BFD_RELOC_VTABLE_INHERIT
:
30118 case BFD_RELOC_32_SECREL
:
30120 code
= fixp
->fx_r_type
;
30123 case BFD_RELOC_THUMB_PCREL_BLX
:
30125 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
30126 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
30129 code
= BFD_RELOC_THUMB_PCREL_BLX
;
30132 case BFD_RELOC_ARM_LITERAL
:
30133 case BFD_RELOC_ARM_HWLITERAL
:
30134 /* If this is called then the a literal has
30135 been referenced across a section boundary. */
30136 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30137 _("literal referenced across section boundary"));
30141 case BFD_RELOC_ARM_TLS_CALL
:
30142 case BFD_RELOC_ARM_THM_TLS_CALL
:
30143 case BFD_RELOC_ARM_TLS_DESCSEQ
:
30144 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
30145 case BFD_RELOC_ARM_GOT32
:
30146 case BFD_RELOC_ARM_GOTOFF
:
30147 case BFD_RELOC_ARM_GOT_PREL
:
30148 case BFD_RELOC_ARM_PLT32
:
30149 case BFD_RELOC_ARM_TARGET1
:
30150 case BFD_RELOC_ARM_ROSEGREL32
:
30151 case BFD_RELOC_ARM_SBREL32
:
30152 case BFD_RELOC_ARM_PREL31
:
30153 case BFD_RELOC_ARM_TARGET2
:
30154 case BFD_RELOC_ARM_TLS_LDO32
:
30155 case BFD_RELOC_ARM_PCREL_CALL
:
30156 case BFD_RELOC_ARM_PCREL_JUMP
:
30157 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
30158 case BFD_RELOC_ARM_ALU_PC_G0
:
30159 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
30160 case BFD_RELOC_ARM_ALU_PC_G1
:
30161 case BFD_RELOC_ARM_ALU_PC_G2
:
30162 case BFD_RELOC_ARM_LDR_PC_G0
:
30163 case BFD_RELOC_ARM_LDR_PC_G1
:
30164 case BFD_RELOC_ARM_LDR_PC_G2
:
30165 case BFD_RELOC_ARM_LDRS_PC_G0
:
30166 case BFD_RELOC_ARM_LDRS_PC_G1
:
30167 case BFD_RELOC_ARM_LDRS_PC_G2
:
30168 case BFD_RELOC_ARM_LDC_PC_G0
:
30169 case BFD_RELOC_ARM_LDC_PC_G1
:
30170 case BFD_RELOC_ARM_LDC_PC_G2
:
30171 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
30172 case BFD_RELOC_ARM_ALU_SB_G0
:
30173 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
30174 case BFD_RELOC_ARM_ALU_SB_G1
:
30175 case BFD_RELOC_ARM_ALU_SB_G2
:
30176 case BFD_RELOC_ARM_LDR_SB_G0
:
30177 case BFD_RELOC_ARM_LDR_SB_G1
:
30178 case BFD_RELOC_ARM_LDR_SB_G2
:
30179 case BFD_RELOC_ARM_LDRS_SB_G0
:
30180 case BFD_RELOC_ARM_LDRS_SB_G1
:
30181 case BFD_RELOC_ARM_LDRS_SB_G2
:
30182 case BFD_RELOC_ARM_LDC_SB_G0
:
30183 case BFD_RELOC_ARM_LDC_SB_G1
:
30184 case BFD_RELOC_ARM_LDC_SB_G2
:
30185 case BFD_RELOC_ARM_V4BX
:
30186 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
30187 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
30188 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
30189 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
30190 case BFD_RELOC_ARM_GOTFUNCDESC
:
30191 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
30192 case BFD_RELOC_ARM_FUNCDESC
:
30193 case BFD_RELOC_ARM_THUMB_BF17
:
30194 case BFD_RELOC_ARM_THUMB_BF19
:
30195 case BFD_RELOC_ARM_THUMB_BF13
:
30196 code
= fixp
->fx_r_type
;
30199 case BFD_RELOC_ARM_TLS_GOTDESC
:
30200 case BFD_RELOC_ARM_TLS_GD32
:
30201 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
30202 case BFD_RELOC_ARM_TLS_LE32
:
30203 case BFD_RELOC_ARM_TLS_IE32
:
30204 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
30205 case BFD_RELOC_ARM_TLS_LDM32
:
30206 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
30207 /* BFD will include the symbol's address in the addend.
30208 But we don't want that, so subtract it out again here. */
30209 if (!S_IS_COMMON (fixp
->fx_addsy
))
30210 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
30211 code
= fixp
->fx_r_type
;
30215 case BFD_RELOC_ARM_IMMEDIATE
:
30216 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30217 _("internal relocation (type: IMMEDIATE) not fixed up"));
30220 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
30221 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30222 _("ADRL used for a symbol not defined in the same file"));
30225 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
30226 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
30227 case BFD_RELOC_ARM_THUMB_LOOP12
:
30228 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30229 _("%s used for a symbol not defined in the same file"),
30230 bfd_get_reloc_code_name (fixp
->fx_r_type
));
30233 case BFD_RELOC_ARM_OFFSET_IMM
:
30234 if (section
->use_rela_p
)
30236 code
= fixp
->fx_r_type
;
30240 if (fixp
->fx_addsy
!= NULL
30241 && !S_IS_DEFINED (fixp
->fx_addsy
)
30242 && S_IS_LOCAL (fixp
->fx_addsy
))
30244 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30245 _("undefined local label `%s'"),
30246 S_GET_NAME (fixp
->fx_addsy
));
30250 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30251 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
30258 switch (fixp
->fx_r_type
)
30260 case BFD_RELOC_NONE
: type
= "NONE"; break;
30261 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
30262 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
30263 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
30264 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
30265 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
30266 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
30267 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
30268 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
30269 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
30270 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
30271 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
30272 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
30273 default: type
= _("<unknown>"); break;
30275 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30276 _("cannot represent %s relocation in this object file format"),
30283 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
30285 && fixp
->fx_addsy
== GOT_symbol
)
30287 code
= BFD_RELOC_ARM_GOTPC
;
30288 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
30292 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
30294 if (reloc
->howto
== NULL
)
30296 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30297 _("cannot represent %s relocation in this object file format"),
30298 bfd_get_reloc_code_name (code
));
30302 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
30303 vtable entry to be used in the relocation's section offset. */
30304 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30305 reloc
->address
= fixp
->fx_offset
;
30310 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
30313 cons_fix_new_arm (fragS
* frag
,
30317 bfd_reloc_code_real_type reloc
)
30322 FIXME: @@ Should look at CPU word size. */
30326 reloc
= BFD_RELOC_8
;
30329 reloc
= BFD_RELOC_16
;
30333 reloc
= BFD_RELOC_32
;
30336 reloc
= BFD_RELOC_64
;
30341 if (exp
->X_op
== O_secrel
)
30343 exp
->X_op
= O_symbol
;
30344 reloc
= BFD_RELOC_32_SECREL
;
30348 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
30351 #if defined (OBJ_COFF)
30353 arm_validate_fix (fixS
* fixP
)
30355 /* If the destination of the branch is a defined symbol which does not have
30356 the THUMB_FUNC attribute, then we must be calling a function which has
30357 the (interfacearm) attribute. We look for the Thumb entry point to that
30358 function and change the branch to refer to that function instead. */
30359 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
30360 && fixP
->fx_addsy
!= NULL
30361 && S_IS_DEFINED (fixP
->fx_addsy
)
30362 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
30364 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
30371 arm_force_relocation (struct fix
* fixp
)
30373 #if defined (OBJ_COFF) && defined (TE_PE)
30374 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
30378 /* In case we have a call or a branch to a function in ARM ISA mode from
30379 a thumb function or vice-versa force the relocation. These relocations
30380 are cleared off for some cores that might have blx and simple transformations
30384 switch (fixp
->fx_r_type
)
30386 case BFD_RELOC_ARM_PCREL_JUMP
:
30387 case BFD_RELOC_ARM_PCREL_CALL
:
30388 case BFD_RELOC_THUMB_PCREL_BLX
:
30389 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
30393 case BFD_RELOC_ARM_PCREL_BLX
:
30394 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30395 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30396 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30397 if (ARM_IS_FUNC (fixp
->fx_addsy
))
30406 /* Resolve these relocations even if the symbol is extern or weak.
30407 Technically this is probably wrong due to symbol preemption.
30408 In practice these relocations do not have enough range to be useful
30409 at dynamic link time, and some code (e.g. in the Linux kernel)
30410 expects these references to be resolved. */
30411 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
30412 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
30413 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
30414 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
30415 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
30416 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
30417 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
30418 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH12
30419 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
30420 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
30421 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
30422 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
30423 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
30424 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
30425 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
30428 /* Always leave these relocations for the linker. */
30429 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30430 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30431 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30434 /* Always generate relocations against function symbols. */
30435 if (fixp
->fx_r_type
== BFD_RELOC_32
30437 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
30440 return generic_force_reloc (fixp
);
30443 #if defined (OBJ_ELF) || defined (OBJ_COFF)
30444 /* Relocations against function names must be left unadjusted,
30445 so that the linker can use this information to generate interworking
30446 stubs. The MIPS version of this function
30447 also prevents relocations that are mips-16 specific, but I do not
30448 know why it does this.
30451 There is one other problem that ought to be addressed here, but
30452 which currently is not: Taking the address of a label (rather
30453 than a function) and then later jumping to that address. Such
30454 addresses also ought to have their bottom bit set (assuming that
30455 they reside in Thumb code), but at the moment they will not. */
30458 arm_fix_adjustable (fixS
* fixP
)
30460 if (fixP
->fx_addsy
== NULL
)
30463 /* Preserve relocations against symbols with function type. */
30464 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
30467 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
30468 && fixP
->fx_subsy
== NULL
)
30471 /* We need the symbol name for the VTABLE entries. */
30472 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
30473 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30476 /* Don't allow symbols to be discarded on GOT related relocs. */
30477 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
30478 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
30479 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
30480 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
30481 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
30482 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
30483 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
30484 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
30485 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
30486 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
30487 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
30488 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
30489 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
30490 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
30491 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
30492 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
30493 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
30496 /* Similarly for group relocations. */
30497 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30498 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30499 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30502 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
30503 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
30504 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
30505 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
30506 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
30507 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
30508 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
30509 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
30510 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
30513 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
30514 offsets, so keep these symbols. */
30515 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
30516 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
30521 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
30525 elf32_arm_target_format (void)
30527 #if defined (TE_VXWORKS)
30528 return (target_big_endian
30529 ? "elf32-bigarm-vxworks"
30530 : "elf32-littlearm-vxworks");
30531 #elif defined (TE_NACL)
30532 return (target_big_endian
30533 ? "elf32-bigarm-nacl"
30534 : "elf32-littlearm-nacl");
30538 if (target_big_endian
)
30539 return "elf32-bigarm-fdpic";
30541 return "elf32-littlearm-fdpic";
30545 if (target_big_endian
)
30546 return "elf32-bigarm";
30548 return "elf32-littlearm";
30554 armelf_frob_symbol (symbolS
* symp
,
30557 elf_frob_symbol (symp
, puntp
);
30561 /* MD interface: Finalization. */
30566 literal_pool
* pool
;
30568 /* Ensure that all the predication blocks are properly closed. */
30569 check_pred_blocks_finished ();
30571 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
30573 /* Put it at the end of the relevant section. */
30574 subseg_set (pool
->section
, pool
->sub_section
);
30576 arm_elf_change_section ();
30583 /* Remove any excess mapping symbols generated for alignment frags in
30584 SEC. We may have created a mapping symbol before a zero byte
30585 alignment; remove it if there's a mapping symbol after the
30588 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
30589 void *dummy ATTRIBUTE_UNUSED
)
30591 segment_info_type
*seginfo
= seg_info (sec
);
30594 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
30597 for (fragp
= seginfo
->frchainP
->frch_root
;
30599 fragp
= fragp
->fr_next
)
30601 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
30602 fragS
*next
= fragp
->fr_next
;
30604 /* Variable-sized frags have been converted to fixed size by
30605 this point. But if this was variable-sized to start with,
30606 there will be a fixed-size frag after it. So don't handle
30608 if (sym
== NULL
|| next
== NULL
)
30611 if (S_GET_VALUE (sym
) < next
->fr_address
)
30612 /* Not at the end of this frag. */
30614 know (S_GET_VALUE (sym
) == next
->fr_address
);
30618 if (next
->tc_frag_data
.first_map
!= NULL
)
30620 /* Next frag starts with a mapping symbol. Discard this
30622 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30626 if (next
->fr_next
== NULL
)
30628 /* This mapping symbol is at the end of the section. Discard
30630 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
30631 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30635 /* As long as we have empty frags without any mapping symbols,
30637 /* If the next frag is non-empty and does not start with a
30638 mapping symbol, then this mapping symbol is required. */
30639 if (next
->fr_address
!= next
->fr_next
->fr_address
)
30642 next
= next
->fr_next
;
30644 while (next
!= NULL
);
30649 /* Adjust the symbol table. This marks Thumb symbols as distinct from
30653 arm_adjust_symtab (void)
30658 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30660 if (ARM_IS_THUMB (sym
))
30662 if (THUMB_IS_FUNC (sym
))
30664 /* Mark the symbol as a Thumb function. */
30665 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
30666 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
30667 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
30669 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
30670 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
30672 as_bad (_("%s: unexpected function type: %d"),
30673 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
30675 else switch (S_GET_STORAGE_CLASS (sym
))
30678 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
30681 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
30684 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
30692 if (ARM_IS_INTERWORK (sym
))
30693 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
30700 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30702 if (ARM_IS_THUMB (sym
))
30704 elf_symbol_type
* elf_sym
;
30706 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
30707 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
30709 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
30710 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
30712 /* If it's a .thumb_func, declare it as so,
30713 otherwise tag label as .code 16. */
30714 if (THUMB_IS_FUNC (sym
))
30715 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
30716 ST_BRANCH_TO_THUMB
);
30717 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30718 elf_sym
->internal_elf_sym
.st_info
=
30719 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
30724 /* Remove any overlapping mapping symbols generated by alignment frags. */
30725 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
30726 /* Now do generic ELF adjustments. */
30727 elf_adjust_symtab ();
30731 /* MD interface: Initialization. */
30734 set_constant_flonums (void)
30738 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
30739 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
30743 /* Auto-select Thumb mode if it's the only available instruction set for the
30744 given architecture. */
30747 autoselect_thumb_from_cpu_variant (void)
30749 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
30750 opcode_select (16);
30759 arm_ops_hsh
= str_htab_create ();
30760 arm_cond_hsh
= str_htab_create ();
30761 arm_vcond_hsh
= str_htab_create ();
30762 arm_shift_hsh
= str_htab_create ();
30763 arm_psr_hsh
= str_htab_create ();
30764 arm_v7m_psr_hsh
= str_htab_create ();
30765 arm_reg_hsh
= str_htab_create ();
30766 arm_reloc_hsh
= str_htab_create ();
30767 arm_barrier_opt_hsh
= str_htab_create ();
30769 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
30770 if (str_hash_find (arm_ops_hsh
, insns
[i
].template_name
) == NULL
)
30771 str_hash_insert (arm_ops_hsh
, insns
[i
].template_name
, insns
+ i
, 0);
30772 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
30773 str_hash_insert (arm_cond_hsh
, conds
[i
].template_name
, conds
+ i
, 0);
30774 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
30775 str_hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, vconds
+ i
, 0);
30776 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
30777 str_hash_insert (arm_shift_hsh
, shift_names
[i
].name
, shift_names
+ i
, 0);
30778 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
30779 str_hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, psrs
+ i
, 0);
30780 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
30781 str_hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
30783 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
30784 str_hash_insert (arm_reg_hsh
, reg_names
[i
].name
, reg_names
+ i
, 0);
30786 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
30788 str_hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
30789 barrier_opt_names
+ i
, 0);
30791 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
30793 struct reloc_entry
* entry
= reloc_names
+ i
;
30795 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
30796 /* This makes encode_branch() use the EABI versions of this relocation. */
30797 entry
->reloc
= BFD_RELOC_UNUSED
;
30799 str_hash_insert (arm_reloc_hsh
, entry
->name
, entry
, 0);
30803 set_constant_flonums ();
30805 /* Set the cpu variant based on the command-line options. We prefer
30806 -mcpu= over -march= if both are set (as for GCC); and we prefer
30807 -mfpu= over any other way of setting the floating point unit.
30808 Use of legacy options with new options are faulted. */
30811 if (mcpu_cpu_opt
|| march_cpu_opt
)
30812 as_bad (_("use of old and new-style options to set CPU type"));
30814 selected_arch
= *legacy_cpu
;
30816 else if (mcpu_cpu_opt
)
30818 selected_arch
= *mcpu_cpu_opt
;
30819 selected_ext
= *mcpu_ext_opt
;
30821 else if (march_cpu_opt
)
30823 selected_arch
= *march_cpu_opt
;
30824 selected_ext
= *march_ext_opt
;
30826 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30831 as_bad (_("use of old and new-style options to set FPU type"));
30833 selected_fpu
= *legacy_fpu
;
30836 selected_fpu
= *mfpu_opt
;
30839 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30840 || defined (TE_NetBSD) || defined (TE_VXWORKS))
30841 /* Some environments specify a default FPU. If they don't, infer it
30842 from the processor. */
30844 selected_fpu
= *mcpu_fpu_opt
;
30845 else if (march_fpu_opt
)
30846 selected_fpu
= *march_fpu_opt
;
30848 selected_fpu
= fpu_default
;
30852 if (ARM_FEATURE_ZERO (selected_fpu
))
30854 if (!no_cpu_selected ())
30855 selected_fpu
= fpu_default
;
30857 selected_fpu
= fpu_arch_fpa
;
30861 if (ARM_FEATURE_ZERO (selected_arch
))
30863 selected_arch
= cpu_default
;
30864 selected_cpu
= selected_arch
;
30866 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30868 /* Autodection of feature mode: allow all features in cpu_variant but leave
30869 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
30870 after all instruction have been processed and we can decide what CPU
30871 should be selected. */
30872 if (ARM_FEATURE_ZERO (selected_arch
))
30873 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30875 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30878 autoselect_thumb_from_cpu_variant ();
30880 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
30882 #if defined OBJ_COFF || defined OBJ_ELF
30884 unsigned int flags
= 0;
30886 #if defined OBJ_ELF
30887 flags
= meabi_flags
;
30889 switch (meabi_flags
)
30891 case EF_ARM_EABI_UNKNOWN
:
30893 /* Set the flags in the private structure. */
30894 if (uses_apcs_26
) flags
|= F_APCS26
;
30895 if (support_interwork
) flags
|= F_INTERWORK
;
30896 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
30897 if (pic_code
) flags
|= F_PIC
;
30898 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
30899 flags
|= F_SOFT_FLOAT
;
30901 switch (mfloat_abi_opt
)
30903 case ARM_FLOAT_ABI_SOFT
:
30904 case ARM_FLOAT_ABI_SOFTFP
:
30905 flags
|= F_SOFT_FLOAT
;
30908 case ARM_FLOAT_ABI_HARD
:
30909 if (flags
& F_SOFT_FLOAT
)
30910 as_bad (_("hard-float conflicts with specified fpu"));
30914 /* Using pure-endian doubles (even if soft-float). */
30915 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
30916 flags
|= F_VFP_FLOAT
;
30918 #if defined OBJ_ELF
30919 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
30920 flags
|= EF_ARM_MAVERICK_FLOAT
;
30923 case EF_ARM_EABI_VER4
:
30924 case EF_ARM_EABI_VER5
:
30925 /* No additional flags to set. */
30932 bfd_set_private_flags (stdoutput
, flags
);
30934 /* We have run out flags in the COFF header to encode the
30935 status of ATPCS support, so instead we create a dummy,
30936 empty, debug section called .arm.atpcs. */
30941 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
30945 bfd_set_section_flags (sec
, SEC_READONLY
| SEC_DEBUGGING
);
30946 bfd_set_section_size (sec
, 0);
30947 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
30953 /* Record the CPU type as well. */
30954 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
30955 mach
= bfd_mach_arm_iWMMXt2
;
30956 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
30957 mach
= bfd_mach_arm_iWMMXt
;
30958 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
30959 mach
= bfd_mach_arm_XScale
;
30960 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
30961 mach
= bfd_mach_arm_ep9312
;
30962 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
30963 mach
= bfd_mach_arm_5TE
;
30964 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
30966 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30967 mach
= bfd_mach_arm_5T
;
30969 mach
= bfd_mach_arm_5
;
30971 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30973 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30974 mach
= bfd_mach_arm_4T
;
30976 mach
= bfd_mach_arm_4
;
30978 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30979 mach
= bfd_mach_arm_3M
;
30980 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30981 mach
= bfd_mach_arm_3
;
30982 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30983 mach
= bfd_mach_arm_2a
;
30984 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30985 mach
= bfd_mach_arm_2
;
30987 mach
= bfd_mach_arm_unknown
;
30989 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30992 /* Command line processing. */
30995 Invocation line includes a switch not recognized by the base assembler.
30996 See if it's a processor-specific option.
30998 This routine is somewhat complicated by the need for backwards
30999 compatibility (since older releases of gcc can't be changed).
31000 The new options try to make the interface as compatible as
31003 New options (supported) are:
31005 -mcpu=<cpu name> Assemble for selected processor
31006 -march=<architecture name> Assemble for selected architecture
31007 -mfpu=<fpu architecture> Assemble for selected FPU.
31008 -EB/-mbig-endian Big-endian
31009 -EL/-mlittle-endian Little-endian
31010 -k Generate PIC code
31011 -mthumb Start in Thumb mode
31012 -mthumb-interwork Code supports ARM/Thumb interworking
31014 -m[no-]warn-deprecated Warn about deprecated features
31015 -m[no-]warn-syms Warn when symbols match instructions
31017 For now we will also provide support for:
31019 -mapcs-32 32-bit Program counter
31020 -mapcs-26 26-bit Program counter
31021 -macps-float Floats passed in FP registers
31022 -mapcs-reentrant Reentrant code
31024 (sometime these will probably be replaced with -mapcs=<list of options>
31025 and -matpcs=<list of options>)
31027 The remaining options are only supported for back-wards compatibility.
31028 Cpu variants, the arm part is optional:
31029 -m[arm]1 Currently not supported.
31030 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
31031 -m[arm]3 Arm 3 processor
31032 -m[arm]6[xx], Arm 6 processors
31033 -m[arm]7[xx][t][[d]m] Arm 7 processors
31034 -m[arm]8[10] Arm 8 processors
31035 -m[arm]9[20][tdmi] Arm 9 processors
31036 -mstrongarm[110[0]] StrongARM processors
31037 -mxscale XScale processors
31038 -m[arm]v[2345[t[e]]] Arm architectures
31039 -mall All (except the ARM1)
31041 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
31042 -mfpe-old (No float load/store multiples)
31043 -mvfpxd VFP Single precision
31045 -mno-fpu Disable all floating point instructions
31047 The following CPU names are recognized:
31048 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
31049 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
31050 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
31051 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
31052 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
31053 arm10t arm10e, arm1020t, arm1020e, arm10200e,
31054 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
31058 const char * md_shortopts
= "m:k";
31060 #ifdef ARM_BI_ENDIAN
31061 #define OPTION_EB (OPTION_MD_BASE + 0)
31062 #define OPTION_EL (OPTION_MD_BASE + 1)
31064 #if TARGET_BYTES_BIG_ENDIAN
31065 #define OPTION_EB (OPTION_MD_BASE + 0)
31067 #define OPTION_EL (OPTION_MD_BASE + 1)
31070 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
31071 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
31073 struct option md_longopts
[] =
31076 {"EB", no_argument
, NULL
, OPTION_EB
},
31079 {"EL", no_argument
, NULL
, OPTION_EL
},
31081 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
31083 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
31085 {NULL
, no_argument
, NULL
, 0}
31088 size_t md_longopts_size
= sizeof (md_longopts
);
31090 struct arm_option_table
31092 const char * option
; /* Option name to match. */
31093 const char * help
; /* Help information. */
31094 int * var
; /* Variable to change. */
31095 int value
; /* What to change it to. */
31096 const char * deprecated
; /* If non-null, print this message. */
31099 struct arm_option_table arm_opts
[] =
31101 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
31102 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
31103 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
31104 &support_interwork
, 1, NULL
},
31105 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
31106 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
31107 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
31109 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
31110 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
31111 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
31112 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
31115 /* These are recognized by the assembler, but have no affect on code. */
31116 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
31117 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
31119 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
31120 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
31121 &warn_on_deprecated
, 0, NULL
},
31123 {"mwarn-restrict-it", N_("warn about performance deprecated IT instructions"
31124 " in ARMv8-A and ARMv8-R"), &warn_on_restrict_it
, 1, NULL
},
31125 {"mno-warn-restrict-it", NULL
, &warn_on_restrict_it
, 0, NULL
},
31127 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), true, NULL
},
31128 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), false, NULL
},
31129 {NULL
, NULL
, NULL
, 0, NULL
}
31132 struct arm_legacy_option_table
31134 const char * option
; /* Option name to match. */
31135 const arm_feature_set
** var
; /* Variable to change. */
31136 const arm_feature_set value
; /* What to change it to. */
31137 const char * deprecated
; /* If non-null, print this message. */
31140 const struct arm_legacy_option_table arm_legacy_opts
[] =
31142 /* DON'T add any new processors to this list -- we want the whole list
31143 to go away... Add them to the processors table instead. */
31144 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31145 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31146 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31147 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31148 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31149 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31150 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31151 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31152 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31153 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31154 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31155 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31156 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31157 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31158 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31159 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31160 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31161 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31162 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31163 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31164 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31165 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31166 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31167 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31168 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31169 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31170 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31171 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31172 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31173 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31174 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31175 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31176 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31177 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31178 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31179 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31180 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31181 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31182 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31183 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31184 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31185 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31186 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31187 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31188 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31189 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31190 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31191 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31192 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31193 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31194 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31195 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31196 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31197 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31198 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31199 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31200 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31201 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31202 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31203 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31204 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31205 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31206 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31207 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31208 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31209 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31210 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31211 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31212 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
31213 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
31214 N_("use -mcpu=strongarm110")},
31215 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
31216 N_("use -mcpu=strongarm1100")},
31217 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
31218 N_("use -mcpu=strongarm1110")},
31219 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
31220 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
31221 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
31223 /* Architecture variants -- don't add any more to this list either. */
31224 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31225 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31226 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31227 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31228 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31229 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31230 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31231 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31232 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31233 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31234 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31235 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31236 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31237 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31238 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31239 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31240 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31241 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31243 /* Floating point variants -- don't add any more to this list either. */
31244 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
31245 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
31246 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
31247 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
31248 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
31250 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
31253 struct arm_cpu_option_table
31257 const arm_feature_set value
;
31258 const arm_feature_set ext
;
31259 /* For some CPUs we assume an FPU unless the user explicitly sets
31261 const arm_feature_set default_fpu
;
31262 /* The canonical name of the CPU, or NULL to use NAME converted to upper
31264 const char * canonical_name
;
31267 /* This list should, at a minimum, contain all the cpu names
31268 recognized by GCC. */
31269 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
31271 static const struct arm_cpu_option_table arm_cpus
[] =
31273 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
31276 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
31279 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
31282 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
31285 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
31288 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
31291 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
31294 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
31297 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
31300 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
31303 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
31306 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
31309 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
31312 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
31315 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
31318 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
31321 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
31324 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
31327 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
31330 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
31333 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
31336 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
31339 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
31342 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
31345 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
31348 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
31351 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
31354 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
31357 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
31360 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
31363 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
31366 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
31369 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
31372 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
31375 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
31378 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
31381 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
31384 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
31387 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
31390 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
31393 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
31396 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
31399 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
31402 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
31405 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
31408 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
31412 /* For V5 or later processors we default to using VFP; but the user
31413 should really set the FPU type explicitly. */
31414 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
31417 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
31420 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31423 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31426 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
31429 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
31432 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
31435 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
31438 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
31441 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
31444 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
31447 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
31450 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
31453 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
31456 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
31459 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
31462 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
31465 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
31468 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
31471 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
31474 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
31477 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
31480 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
31483 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
31486 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
31489 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
31492 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
31495 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
31498 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
31501 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
31504 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
31507 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
31510 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
31513 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
31516 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
31519 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
31522 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
31523 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31525 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
31527 FPU_ARCH_NEON_VFP_V4
),
31528 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
31529 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31530 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31531 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
31532 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31533 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31534 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
31536 FPU_ARCH_NEON_VFP_V4
),
31537 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
31539 FPU_ARCH_NEON_VFP_V4
),
31540 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
31542 FPU_ARCH_NEON_VFP_V4
),
31543 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
31544 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31545 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31546 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
31547 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31548 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31549 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
31550 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31551 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31552 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
31553 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31554 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31555 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
31556 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31557 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31558 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
31559 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31560 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31561 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
31562 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31563 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31564 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
31565 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31566 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31567 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
31568 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31569 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31570 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
31571 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31572 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31573 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
31574 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31575 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31576 ARM_CPU_OPT ("cortex-a78", "Cortex-A78", ARM_ARCH_V8_2A
,
31577 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_SB
),
31578 FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31579 ARM_CPU_OPT ("cortex-a78ae", "Cortex-A78AE", ARM_ARCH_V8_2A
,
31580 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_SB
),
31581 FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31582 ARM_CPU_OPT ("cortex-a78c", "Cortex-A78C", ARM_ARCH_V8_2A
,
31583 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_SB
),
31584 FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31585 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
31586 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31587 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31588 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
31591 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
31593 FPU_ARCH_VFP_V3D16
),
31594 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
31595 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31597 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
31598 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31599 FPU_ARCH_VFP_V3D16
),
31600 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
31601 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31602 FPU_ARCH_VFP_V3D16
),
31603 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
31604 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31605 FPU_ARCH_NEON_VFP_ARMV8
),
31606 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
31607 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31609 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
31610 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31612 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
31615 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
31618 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
31621 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
31624 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
31627 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
31630 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
31633 ARM_CPU_OPT ("cortex-x1", "Cortex-X1", ARM_ARCH_V8_2A
,
31634 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_SB
),
31635 FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31636 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
31637 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31638 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31639 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
31640 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31641 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31642 ARM_CPU_OPT ("neoverse-n2", "Neoverse N2", ARM_ARCH_V8_5A
,
31643 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31646 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
),
31647 ARM_CPU_OPT ("neoverse-v1", "Neoverse V1", ARM_ARCH_V8_4A
,
31648 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31651 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
),
31652 /* ??? XSCALE is really an architecture. */
31653 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
31657 /* ??? iwmmxt is not a processor. */
31658 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
31661 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
31664 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
31669 ARM_CPU_OPT ("ep9312", "ARM920T",
31670 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
31671 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
31673 /* Marvell processors. */
31674 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
31675 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31676 FPU_ARCH_VFP_V3D16
),
31677 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
31678 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31679 FPU_ARCH_NEON_VFP_V4
),
31681 /* APM X-Gene family. */
31682 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
31684 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31685 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
31686 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31687 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31689 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31693 struct arm_ext_table
31697 const arm_feature_set merge
;
31698 const arm_feature_set clear
;
31701 struct arm_arch_option_table
31705 const arm_feature_set value
;
31706 const arm_feature_set default_fpu
;
31707 const struct arm_ext_table
* ext_table
;
31710 /* Used to add support for +E and +noE extension. */
31711 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
31712 /* Used to add support for a +E extension. */
31713 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
31714 /* Used to add support for a +noE extension. */
31715 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
31717 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
31718 ~0 & ~FPU_ENDIAN_PURE)
31720 static const struct arm_ext_table armv5te_ext_table
[] =
31722 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
31723 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31726 static const struct arm_ext_table armv7_ext_table
[] =
31728 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31729 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31732 static const struct arm_ext_table armv7ve_ext_table
[] =
31734 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
31735 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
31736 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31737 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31738 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31739 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
31740 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31742 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
31743 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31745 /* Aliases for +simd. */
31746 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31748 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31749 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31750 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31752 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31755 static const struct arm_ext_table armv7a_ext_table
[] =
31757 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31758 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31759 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31760 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31761 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31762 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
31763 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31765 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
31766 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31768 /* Aliases for +simd. */
31769 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31770 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31772 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31773 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31775 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
31776 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
31777 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31780 static const struct arm_ext_table armv7r_ext_table
[] =
31782 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
31783 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
31784 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31785 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31786 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
31787 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31788 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31789 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
31790 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31793 static const struct arm_ext_table armv7em_ext_table
[] =
31795 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
31796 /* Alias for +fp, used to be known as fpv4-sp-d16. */
31797 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
31798 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
31799 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31800 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
31801 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31804 static const struct arm_ext_table armv8a_ext_table
[] =
31806 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31807 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31808 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31809 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31811 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31812 should use the +simd option to turn on FP. */
31813 ARM_REMOVE ("fp", ALL_FP
),
31814 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31815 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31816 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31820 static const struct arm_ext_table armv81a_ext_table
[] =
31822 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31823 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31824 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31826 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31827 should use the +simd option to turn on FP. */
31828 ARM_REMOVE ("fp", ALL_FP
),
31829 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31830 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31831 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31834 static const struct arm_ext_table armv82a_ext_table
[] =
31836 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31837 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
31838 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
31839 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31840 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31841 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31842 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31843 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31845 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31846 should use the +simd option to turn on FP. */
31847 ARM_REMOVE ("fp", ALL_FP
),
31848 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31849 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31850 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31853 static const struct arm_ext_table armv84a_ext_table
[] =
31855 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31856 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31857 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31858 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31859 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31860 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31862 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31863 should use the +simd option to turn on FP. */
31864 ARM_REMOVE ("fp", ALL_FP
),
31865 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31866 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31867 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31870 static const struct arm_ext_table armv85a_ext_table
[] =
31872 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31873 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31874 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31875 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31876 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31877 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31879 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31880 should use the +simd option to turn on FP. */
31881 ARM_REMOVE ("fp", ALL_FP
),
31882 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31885 static const struct arm_ext_table armv86a_ext_table
[] =
31887 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31888 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31891 #define CDE_EXTENSIONS \
31892 ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
31893 ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
31894 ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
31895 ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
31896 ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
31897 ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
31898 ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
31899 ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
31901 static const struct arm_ext_table armv8m_main_ext_table
[] =
31903 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31904 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31905 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
31906 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31908 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31912 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
31914 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31915 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31917 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31918 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
31921 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31922 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31923 ARM_EXT ("mve", ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
, ARM_EXT2_MVE
, 0),
31924 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
)),
31926 ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
,
31927 ARM_EXT2_FP16_INST
| ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
,
31928 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31930 ARM_ADD ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_AEXT3_V8_1M_MAIN_PACBTI
)),
31931 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31934 #undef CDE_EXTENSIONS
31936 static const struct arm_ext_table armv8r_ext_table
[] =
31938 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31939 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31940 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31941 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31942 ARM_REMOVE ("fp", ALL_FP
),
31943 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
31944 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31947 /* This list should, at a minimum, contain all the architecture names
31948 recognized by GCC. */
31949 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
31950 #define ARM_ARCH_OPT2(N, V, DF, ext) \
31951 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
31953 static const struct arm_arch_option_table arm_archs
[] =
31955 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
31956 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
31957 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
31958 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31959 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31960 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
31961 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
31962 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
31963 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
31964 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
31965 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
31966 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
31967 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
31968 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
31969 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
31970 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
31971 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
31972 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31973 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31974 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
31975 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
31976 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31977 kept to preserve existing behaviour. */
31978 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31979 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31980 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
31981 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
31982 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
31983 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31984 kept to preserve existing behaviour. */
31985 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31986 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31987 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
31988 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
31989 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
31990 /* The official spelling of the ARMv7 profile variants is the dashed form.
31991 Accept the non-dashed form for compatibility with old toolchains. */
31992 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31993 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
31994 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31995 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31996 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31997 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31998 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31999 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
32000 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
32001 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
32003 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
32005 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
32006 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
32007 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
32008 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
32009 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
32010 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
32011 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
32012 ARM_ARCH_OPT2 ("armv8.6-a", ARM_ARCH_V8_6A
, FPU_ARCH_VFP
, armv86a
),
32013 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
32014 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
32015 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
32016 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
32018 #undef ARM_ARCH_OPT
32020 /* ISA extensions in the co-processor and main instruction set space. */
32022 struct arm_option_extension_value_table
32026 const arm_feature_set merge_value
;
32027 const arm_feature_set clear_value
;
32028 /* List of architectures for which an extension is available. ARM_ARCH_NONE
32029 indicates that an extension is available for all architectures while
32030 ARM_ANY marks an empty entry. */
32031 const arm_feature_set allowed_archs
[2];
32034 /* The following table must be in alphabetical order with a NULL last entry. */
32036 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
32037 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
32039 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
32040 use the context sensitive approach using arm_ext_table's. */
32041 static const struct arm_option_extension_value_table arm_extensions
[] =
32043 ARM_EXT_OPT ("crc", ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
32044 ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
32045 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32046 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
32047 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
32048 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32049 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
32050 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
32052 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
32053 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
32054 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
32055 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
32056 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32057 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
32058 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
32060 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32061 | ARM_EXT2_FP16_FML
),
32062 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32063 | ARM_EXT2_FP16_FML
),
32065 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32066 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32067 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32068 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32069 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
32070 Thumb divide instruction. Due to this having the same name as the
32071 previous entry, this will be ignored when doing command-line parsing and
32072 only considered by build attribute selection code. */
32073 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32074 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32075 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
32076 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
32077 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
32078 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
32079 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
32080 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
32081 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
32082 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32083 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32084 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32085 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32086 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32087 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32088 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
32089 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
32090 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
32091 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32092 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32093 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32095 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
32096 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
32097 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32098 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
32099 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
32100 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32101 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32102 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32104 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32105 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32106 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
32107 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32108 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
32109 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
32110 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32111 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
32113 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
32114 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32115 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
32116 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
32117 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
32121 /* ISA floating-point and Advanced SIMD extensions. */
32122 struct arm_option_fpu_value_table
32125 const arm_feature_set value
;
32128 /* This list should, at a minimum, contain all the fpu names
32129 recognized by GCC. */
32130 static const struct arm_option_fpu_value_table arm_fpus
[] =
32132 {"softfpa", FPU_NONE
},
32133 {"fpe", FPU_ARCH_FPE
},
32134 {"fpe2", FPU_ARCH_FPE
},
32135 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
32136 {"fpa", FPU_ARCH_FPA
},
32137 {"fpa10", FPU_ARCH_FPA
},
32138 {"fpa11", FPU_ARCH_FPA
},
32139 {"arm7500fe", FPU_ARCH_FPA
},
32140 {"softvfp", FPU_ARCH_VFP
},
32141 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
32142 {"vfp", FPU_ARCH_VFP_V2
},
32143 {"vfp9", FPU_ARCH_VFP_V2
},
32144 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
32145 {"vfp10", FPU_ARCH_VFP_V2
},
32146 {"vfp10-r0", FPU_ARCH_VFP_V1
},
32147 {"vfpxd", FPU_ARCH_VFP_V1xD
},
32148 {"vfpv2", FPU_ARCH_VFP_V2
},
32149 {"vfpv3", FPU_ARCH_VFP_V3
},
32150 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
32151 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
32152 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
32153 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
32154 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
32155 {"arm1020t", FPU_ARCH_VFP_V1
},
32156 {"arm1020e", FPU_ARCH_VFP_V2
},
32157 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
32158 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
32159 {"maverick", FPU_ARCH_MAVERICK
},
32160 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32161 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32162 {"neon-fp16", FPU_ARCH_NEON_FP16
},
32163 {"vfpv4", FPU_ARCH_VFP_V4
},
32164 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
32165 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
32166 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
32167 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
32168 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
32169 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
32170 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
32171 {"crypto-neon-fp-armv8",
32172 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
32173 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
32174 {"crypto-neon-fp-armv8.1",
32175 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
32176 {NULL
, ARM_ARCH_NONE
}
32179 struct arm_option_value_table
32185 static const struct arm_option_value_table arm_float_abis
[] =
32187 {"hard", ARM_FLOAT_ABI_HARD
},
32188 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
32189 {"soft", ARM_FLOAT_ABI_SOFT
},
32194 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
32195 static const struct arm_option_value_table arm_eabis
[] =
32197 {"gnu", EF_ARM_EABI_UNKNOWN
},
32198 {"4", EF_ARM_EABI_VER4
},
32199 {"5", EF_ARM_EABI_VER5
},
32204 struct arm_long_option_table
32206 const char *option
; /* Substring to match. */
32207 const char *help
; /* Help information. */
32208 bool (*func
) (const char *subopt
); /* Function to decode sub-option. */
32209 const char *deprecated
; /* If non-null, print this message. */
32213 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
32214 arm_feature_set
*ext_set
,
32215 const struct arm_ext_table
*ext_table
)
32217 /* We insist on extensions being specified in alphabetical order, and with
32218 extensions being added before being removed. We achieve this by having
32219 the global ARM_EXTENSIONS table in alphabetical order, and using the
32220 ADDING_VALUE variable to indicate whether we are adding an extension (1)
32221 or removing it (0) and only allowing it to change in the order
32223 const struct arm_option_extension_value_table
* opt
= NULL
;
32224 const arm_feature_set arm_any
= ARM_ANY
;
32225 int adding_value
= -1;
32227 while (str
!= NULL
&& *str
!= 0)
32234 as_bad (_("invalid architectural extension"));
32239 ext
= strchr (str
, '+');
32244 len
= strlen (str
);
32246 if (len
>= 2 && startswith (str
, "no"))
32248 if (adding_value
!= 0)
32251 opt
= arm_extensions
;
32259 if (adding_value
== -1)
32262 opt
= arm_extensions
;
32264 else if (adding_value
!= 1)
32266 as_bad (_("must specify extensions to add before specifying "
32267 "those to remove"));
32274 as_bad (_("missing architectural extension"));
32278 gas_assert (adding_value
!= -1);
32279 gas_assert (opt
!= NULL
);
32281 if (ext_table
!= NULL
)
32283 const struct arm_ext_table
* ext_opt
= ext_table
;
32284 bool found
= false;
32285 for (; ext_opt
->name
!= NULL
; ext_opt
++)
32286 if (ext_opt
->name_len
== len
32287 && strncmp (ext_opt
->name
, str
, len
) == 0)
32291 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
32292 /* TODO: Option not supported. When we remove the
32293 legacy table this case should error out. */
32296 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
32300 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
32301 /* TODO: Option not supported. When we remove the
32302 legacy table this case should error out. */
32304 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
32316 /* Scan over the options table trying to find an exact match. */
32317 for (; opt
->name
!= NULL
; opt
++)
32318 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32320 int i
, nb_allowed_archs
=
32321 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32322 /* Check we can apply the extension to this architecture. */
32323 for (i
= 0; i
< nb_allowed_archs
; i
++)
32326 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
32328 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
32331 if (i
== nb_allowed_archs
)
32333 as_bad (_("extension does not apply to the base architecture"));
32337 /* Add or remove the extension. */
32339 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
32341 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
32343 /* Allowing Thumb division instructions for ARMv7 in autodetection
32344 rely on this break so that duplicate extensions (extensions
32345 with the same name as a previous extension in the list) are not
32346 considered for command-line parsing. */
32350 if (opt
->name
== NULL
)
32352 /* Did we fail to find an extension because it wasn't specified in
32353 alphabetical order, or because it does not exist? */
32355 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32356 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32359 if (opt
->name
== NULL
)
32360 as_bad (_("unknown architectural extension `%s'"), str
);
32362 as_bad (_("architectural extensions must be specified in "
32363 "alphabetical order"));
32369 /* We should skip the extension we've just matched the next time
32381 arm_parse_fp16_opt (const char *str
)
32383 if (strcasecmp (str
, "ieee") == 0)
32384 fp16_format
= ARM_FP16_FORMAT_IEEE
;
32385 else if (strcasecmp (str
, "alternative") == 0)
32386 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
32389 as_bad (_("unrecognised float16 format \"%s\""), str
);
32397 arm_parse_cpu (const char *str
)
32399 const struct arm_cpu_option_table
*opt
;
32400 const char *ext
= strchr (str
, '+');
32406 len
= strlen (str
);
32410 as_bad (_("missing cpu name `%s'"), str
);
32414 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
32415 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32417 mcpu_cpu_opt
= &opt
->value
;
32418 if (mcpu_ext_opt
== NULL
)
32419 mcpu_ext_opt
= XNEW (arm_feature_set
);
32420 *mcpu_ext_opt
= opt
->ext
;
32421 mcpu_fpu_opt
= &opt
->default_fpu
;
32422 if (opt
->canonical_name
)
32424 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
32425 strcpy (selected_cpu_name
, opt
->canonical_name
);
32431 if (len
>= sizeof selected_cpu_name
)
32432 len
= (sizeof selected_cpu_name
) - 1;
32434 for (i
= 0; i
< len
; i
++)
32435 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32436 selected_cpu_name
[i
] = 0;
32440 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
32445 as_bad (_("unknown cpu `%s'"), str
);
32450 arm_parse_arch (const char *str
)
32452 const struct arm_arch_option_table
*opt
;
32453 const char *ext
= strchr (str
, '+');
32459 len
= strlen (str
);
32463 as_bad (_("missing architecture name `%s'"), str
);
32467 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
32468 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32470 march_cpu_opt
= &opt
->value
;
32471 if (march_ext_opt
== NULL
)
32472 march_ext_opt
= XNEW (arm_feature_set
);
32473 *march_ext_opt
= arm_arch_none
;
32474 march_fpu_opt
= &opt
->default_fpu
;
32475 selected_ctx_ext_table
= opt
->ext_table
;
32476 strcpy (selected_cpu_name
, opt
->name
);
32479 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
32485 as_bad (_("unknown architecture `%s'\n"), str
);
32490 arm_parse_fpu (const char * str
)
32492 const struct arm_option_fpu_value_table
* opt
;
32494 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32495 if (streq (opt
->name
, str
))
32497 mfpu_opt
= &opt
->value
;
32501 as_bad (_("unknown floating point format `%s'\n"), str
);
32506 arm_parse_float_abi (const char * str
)
32508 const struct arm_option_value_table
* opt
;
32510 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
32511 if (streq (opt
->name
, str
))
32513 mfloat_abi_opt
= opt
->value
;
32517 as_bad (_("unknown floating point abi `%s'\n"), str
);
32523 arm_parse_eabi (const char * str
)
32525 const struct arm_option_value_table
*opt
;
32527 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
32528 if (streq (opt
->name
, str
))
32530 meabi_flags
= opt
->value
;
32533 as_bad (_("unknown EABI `%s'\n"), str
);
32539 arm_parse_it_mode (const char * str
)
32543 if (streq ("arm", str
))
32544 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
32545 else if (streq ("thumb", str
))
32546 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
32547 else if (streq ("always", str
))
32548 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
32549 else if (streq ("never", str
))
32550 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
32553 as_bad (_("unknown implicit IT mode `%s', should be "\
32554 "arm, thumb, always, or never."), str
);
32562 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
32564 codecomposer_syntax
= true;
32565 arm_comment_chars
[0] = ';';
32566 arm_line_separator_chars
[0] = 0;
32570 struct arm_long_option_table arm_long_opts
[] =
32572 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
32573 arm_parse_cpu
, NULL
},
32574 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
32575 arm_parse_arch
, NULL
},
32576 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
32577 arm_parse_fpu
, NULL
},
32578 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
32579 arm_parse_float_abi
, NULL
},
32581 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
32582 arm_parse_eabi
, NULL
},
32584 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
32585 arm_parse_it_mode
, NULL
},
32586 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
32587 arm_ccs_mode
, NULL
},
32589 N_("[ieee|alternative]\n\
32590 set the encoding for half precision floating point "
32591 "numbers to IEEE\n\
32592 or Arm alternative format."),
32593 arm_parse_fp16_opt
, NULL
},
32594 {NULL
, NULL
, 0, NULL
}
32598 md_parse_option (int c
, const char * arg
)
32600 struct arm_option_table
*opt
;
32601 const struct arm_legacy_option_table
*fopt
;
32602 struct arm_long_option_table
*lopt
;
32608 target_big_endian
= 1;
32614 target_big_endian
= 0;
32618 case OPTION_FIX_V4BX
:
32626 #endif /* OBJ_ELF */
32629 /* Listing option. Just ignore these, we don't support additional
32634 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32636 if (c
== opt
->option
[0]
32637 && ((arg
== NULL
&& opt
->option
[1] == 0)
32638 || streq (arg
, opt
->option
+ 1)))
32640 /* If the option is deprecated, tell the user. */
32641 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
32642 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32643 arg
? arg
: "", _(opt
->deprecated
));
32645 if (opt
->var
!= NULL
)
32646 *opt
->var
= opt
->value
;
32652 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
32654 if (c
== fopt
->option
[0]
32655 && ((arg
== NULL
&& fopt
->option
[1] == 0)
32656 || streq (arg
, fopt
->option
+ 1)))
32658 /* If the option is deprecated, tell the user. */
32659 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
32660 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32661 arg
? arg
: "", _(fopt
->deprecated
));
32663 if (fopt
->var
!= NULL
)
32664 *fopt
->var
= &fopt
->value
;
32670 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32672 /* These options are expected to have an argument. */
32673 if (c
== lopt
->option
[0]
32675 && strncmp (arg
, lopt
->option
+ 1,
32676 strlen (lopt
->option
+ 1)) == 0)
32678 /* If the option is deprecated, tell the user. */
32679 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
32680 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
32681 _(lopt
->deprecated
));
32683 /* Call the sup-option parser. */
32684 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
32695 md_show_usage (FILE * fp
)
32697 struct arm_option_table
*opt
;
32698 struct arm_long_option_table
*lopt
;
32700 fprintf (fp
, _(" ARM-specific assembler options:\n"));
32702 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32703 if (opt
->help
!= NULL
)
32704 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
32706 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32707 if (lopt
->help
!= NULL
)
32708 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
32712 -EB assemble code for a big-endian cpu\n"));
32717 -EL assemble code for a little-endian cpu\n"));
32721 --fix-v4bx Allow BX in ARMv4 code\n"));
32725 --fdpic generate an FDPIC object file\n"));
32726 #endif /* OBJ_ELF */
32734 arm_feature_set flags
;
32735 } cpu_arch_ver_table
;
32737 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
32738 chronologically for architectures, with an exception for ARMv6-M and
32739 ARMv6S-M due to legacy reasons. No new architecture should have a
32740 special case. This allows for build attribute selection results to be
32741 stable when new architectures are added. */
32742 static const cpu_arch_ver_table cpu_arch_ver
[] =
32744 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
32745 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
32746 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
32747 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
32748 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
32749 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
32750 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
32751 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
32752 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
32753 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
32754 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
32755 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
32756 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
32757 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
32758 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
32759 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
32760 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
32761 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
32762 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
32763 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
32764 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
32765 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
32766 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
32767 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
32769 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
32770 always selected build attributes to match those of ARMv6-M
32771 (resp. ARMv6S-M). However, due to these architectures being a strict
32772 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
32773 would be selected when fully respecting chronology of architectures.
32774 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
32775 move them before ARMv7 architectures. */
32776 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
32777 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
32779 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
32780 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
32781 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
32782 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
32783 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
32784 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
32785 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
32786 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
32787 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
32788 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
32789 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
32790 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
32791 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
32792 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
32793 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
32794 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
32795 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_6A
},
32796 {-1, ARM_ARCH_NONE
}
32799 /* Set an attribute if it has not already been set by the user. */
32802 aeabi_set_attribute_int (int tag
, int value
)
32805 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32806 || !attributes_set_explicitly
[tag
])
32807 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
32811 aeabi_set_attribute_string (int tag
, const char *value
)
32814 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32815 || !attributes_set_explicitly
[tag
])
32816 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
32819 /* Return whether features in the *NEEDED feature set are available via
32820 extensions for the architecture whose feature set is *ARCH_FSET. */
32823 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
32824 const arm_feature_set
*needed
)
32826 int i
, nb_allowed_archs
;
32827 arm_feature_set ext_fset
;
32828 const struct arm_option_extension_value_table
*opt
;
32830 ext_fset
= arm_arch_none
;
32831 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32833 /* Extension does not provide any feature we need. */
32834 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
32838 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32839 for (i
= 0; i
< nb_allowed_archs
; i
++)
32842 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
32845 /* Extension is available, add it. */
32846 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
32847 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
32851 /* Can we enable all features in *needed? */
32852 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
32855 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32856 a given architecture feature set *ARCH_EXT_FSET including extension feature
32857 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
32858 - if true, check for an exact match of the architecture modulo extensions;
32859 - otherwise, select build attribute value of the first superset
32860 architecture released so that results remains stable when new architectures
32862 For -march/-mcpu=all the build attribute value of the most featureful
32863 architecture is returned. Tag_CPU_arch_profile result is returned in
32867 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
32868 const arm_feature_set
*ext_fset
,
32869 char *profile
, int exact_match
)
32871 arm_feature_set arch_fset
;
32872 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
32874 /* Select most featureful architecture with all its extensions if building
32875 for -march=all as the feature sets used to set build attributes. */
32876 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
32878 /* Force revisiting of decision for each new architecture. */
32879 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32881 return TAG_CPU_ARCH_V8
;
32884 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
32886 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
32888 arm_feature_set known_arch_fset
;
32890 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
32893 /* Base architecture match user-specified architecture and
32894 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
32895 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
32900 /* Base architecture match user-specified architecture only
32901 (eg. ARMv6-M in the same case as above). Record it in case we
32902 find a match with above condition. */
32903 else if (p_ver_ret
== NULL
32904 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
32910 /* Architecture has all features wanted. */
32911 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
32913 arm_feature_set added_fset
;
32915 /* Compute features added by this architecture over the one
32916 recorded in p_ver_ret. */
32917 if (p_ver_ret
!= NULL
)
32918 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
32920 /* First architecture that match incl. with extensions, or the
32921 only difference in features over the recorded match is
32922 features that were optional and are now mandatory. */
32923 if (p_ver_ret
== NULL
32924 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
32930 else if (p_ver_ret
== NULL
)
32932 arm_feature_set needed_ext_fset
;
32934 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
32936 /* Architecture has all features needed when using some
32937 extensions. Record it and continue searching in case there
32938 exist an architecture providing all needed features without
32939 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
32941 if (have_ext_for_needed_feat_p (&known_arch_fset
,
32948 if (p_ver_ret
== NULL
)
32952 /* Tag_CPU_arch_profile. */
32953 if (!ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8r
)
32954 && (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
32955 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
32956 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
32957 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
))))
32959 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
)
32960 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8r
))
32962 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
32966 return p_ver_ret
->val
;
32969 /* Set the public EABI object attributes. */
32972 aeabi_set_public_attributes (void)
32974 char profile
= '\0';
32977 int fp16_optional
= 0;
32978 int skip_exact_match
= 0;
32979 arm_feature_set flags
, flags_arch
, flags_ext
;
32981 /* Autodetection mode, choose the architecture based the instructions
32983 if (no_cpu_selected ())
32985 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
32987 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
32988 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
32990 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
32991 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
32993 /* Code run during relaxation relies on selected_cpu being set. */
32994 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32995 flags_ext
= arm_arch_none
;
32996 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
32997 selected_ext
= flags_ext
;
32998 selected_cpu
= flags
;
33000 /* Otherwise, choose the architecture based on the capabilities of the
33004 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
33005 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
33006 flags_ext
= selected_ext
;
33007 flags
= selected_cpu
;
33009 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
33011 /* Allow the user to override the reported architecture. */
33012 if (!ARM_FEATURE_ZERO (selected_object_arch
))
33014 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
33015 flags_ext
= arm_arch_none
;
33018 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
33020 /* When this function is run again after relaxation has happened there is no
33021 way to determine whether an architecture or CPU was specified by the user:
33022 - selected_cpu is set above for relaxation to work;
33023 - march_cpu_opt is not set if only -mcpu or .cpu is used;
33024 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
33025 Therefore, if not in -march=all case we first try an exact match and fall
33026 back to autodetection. */
33027 if (!skip_exact_match
)
33028 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
33030 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
33032 as_bad (_("no architecture contains all the instructions used\n"));
33034 /* Tag_CPU_name. */
33035 if (selected_cpu_name
[0])
33039 q
= selected_cpu_name
;
33040 if (startswith (q
, "armv"))
33045 for (i
= 0; q
[i
]; i
++)
33046 q
[i
] = TOUPPER (q
[i
]);
33048 aeabi_set_attribute_string (Tag_CPU_name
, q
);
33051 /* Tag_CPU_arch. */
33052 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
33054 /* Tag_CPU_arch_profile. */
33055 if (profile
!= '\0')
33056 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
33058 /* Tag_DSP_extension. */
33059 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
33060 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
33062 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
33063 /* Tag_ARM_ISA_use. */
33064 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
33065 || ARM_FEATURE_ZERO (flags_arch
))
33066 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
33068 /* Tag_THUMB_ISA_use. */
33069 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
33070 || ARM_FEATURE_ZERO (flags_arch
))
33074 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33075 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
33077 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
33081 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
33084 /* Tag_VFP_arch. */
33085 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
33086 aeabi_set_attribute_int (Tag_VFP_arch
,
33087 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33089 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
33090 aeabi_set_attribute_int (Tag_VFP_arch
,
33091 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33093 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
33096 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
33098 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
33100 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
33103 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
33104 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
33105 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
33106 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
33107 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
33109 /* Tag_ABI_HardFP_use. */
33110 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
33111 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
33112 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
33114 /* Tag_WMMX_arch. */
33115 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
33116 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
33117 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
33118 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
33120 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
33121 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
33122 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
33123 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
33124 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
33125 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
33127 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
33129 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
33133 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
33138 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
33139 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
33140 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
33141 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
33143 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
33144 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
33145 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
33149 We set Tag_DIV_use to two when integer divide instructions have been used
33150 in ARM state, or when Thumb integer divide instructions have been used,
33151 but we have no architecture profile set, nor have we any ARM instructions.
33153 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
33154 by the base architecture.
33156 For new architectures we will have to check these tests. */
33157 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
33158 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33159 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
33160 aeabi_set_attribute_int (Tag_DIV_use
, 0);
33161 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
33162 || (profile
== '\0'
33163 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
33164 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
33165 aeabi_set_attribute_int (Tag_DIV_use
, 2);
33167 /* Tag_MP_extension_use. */
33168 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
33169 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
33171 /* Tag Virtualization_use. */
33172 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
33174 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
33177 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
33179 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
33180 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
33183 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
33184 finished and free extension feature bits which will not be used anymore. */
33187 arm_md_post_relax (void)
33189 aeabi_set_public_attributes ();
33190 XDELETE (mcpu_ext_opt
);
33191 mcpu_ext_opt
= NULL
;
33192 XDELETE (march_ext_opt
);
33193 march_ext_opt
= NULL
;
33196 /* Add the default contents for the .ARM.attributes section. */
33201 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
33204 aeabi_set_public_attributes ();
33206 #endif /* OBJ_ELF */
33208 /* Parse a .cpu directive. */
33211 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
33213 const struct arm_cpu_option_table
*opt
;
33217 name
= input_line_pointer
;
33218 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33219 input_line_pointer
++;
33220 saved_char
= *input_line_pointer
;
33221 *input_line_pointer
= 0;
33223 /* Skip the first "all" entry. */
33224 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
33225 if (streq (opt
->name
, name
))
33227 selected_arch
= opt
->value
;
33228 selected_ext
= opt
->ext
;
33229 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33230 if (opt
->canonical_name
)
33231 strcpy (selected_cpu_name
, opt
->canonical_name
);
33235 for (i
= 0; opt
->name
[i
]; i
++)
33236 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
33238 selected_cpu_name
[i
] = 0;
33240 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33242 *input_line_pointer
= saved_char
;
33243 demand_empty_rest_of_line ();
33246 as_bad (_("unknown cpu `%s'"), name
);
33247 *input_line_pointer
= saved_char
;
33248 ignore_rest_of_line ();
33251 /* Parse a .arch directive. */
33254 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
33256 const struct arm_arch_option_table
*opt
;
33260 name
= input_line_pointer
;
33261 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33262 input_line_pointer
++;
33263 saved_char
= *input_line_pointer
;
33264 *input_line_pointer
= 0;
33266 /* Skip the first "all" entry. */
33267 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33268 if (streq (opt
->name
, name
))
33270 selected_arch
= opt
->value
;
33271 selected_ctx_ext_table
= opt
->ext_table
;
33272 selected_ext
= arm_arch_none
;
33273 selected_cpu
= selected_arch
;
33274 strcpy (selected_cpu_name
, opt
->name
);
33275 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33276 *input_line_pointer
= saved_char
;
33277 demand_empty_rest_of_line ();
33281 as_bad (_("unknown architecture `%s'\n"), name
);
33282 *input_line_pointer
= saved_char
;
33283 ignore_rest_of_line ();
33286 /* Parse a .object_arch directive. */
33289 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
33291 const struct arm_arch_option_table
*opt
;
33295 name
= input_line_pointer
;
33296 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33297 input_line_pointer
++;
33298 saved_char
= *input_line_pointer
;
33299 *input_line_pointer
= 0;
33301 /* Skip the first "all" entry. */
33302 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33303 if (streq (opt
->name
, name
))
33305 selected_object_arch
= opt
->value
;
33306 *input_line_pointer
= saved_char
;
33307 demand_empty_rest_of_line ();
33311 as_bad (_("unknown architecture `%s'\n"), name
);
33312 *input_line_pointer
= saved_char
;
33313 ignore_rest_of_line ();
33316 /* Parse a .arch_extension directive. */
33319 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
33321 const struct arm_option_extension_value_table
*opt
;
33324 int adding_value
= 1;
33326 name
= input_line_pointer
;
33327 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33328 input_line_pointer
++;
33329 saved_char
= *input_line_pointer
;
33330 *input_line_pointer
= 0;
33332 if (strlen (name
) >= 2
33333 && startswith (name
, "no"))
33339 /* Check the context specific extension table */
33340 if (selected_ctx_ext_table
)
33342 const struct arm_ext_table
* ext_opt
;
33343 for (ext_opt
= selected_ctx_ext_table
; ext_opt
->name
!= NULL
; ext_opt
++)
33345 if (streq (ext_opt
->name
, name
))
33349 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
33350 /* TODO: Option not supported. When we remove the
33351 legacy table this case should error out. */
33353 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33357 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, ext_opt
->clear
);
33359 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33360 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33361 *input_line_pointer
= saved_char
;
33362 demand_empty_rest_of_line ();
33368 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
33369 if (streq (opt
->name
, name
))
33371 int i
, nb_allowed_archs
=
33372 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
33373 for (i
= 0; i
< nb_allowed_archs
; i
++)
33376 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
33378 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
33382 if (i
== nb_allowed_archs
)
33384 as_bad (_("architectural extension `%s' is not allowed for the "
33385 "current base architecture"), name
);
33390 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33393 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
33395 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33396 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33397 *input_line_pointer
= saved_char
;
33398 demand_empty_rest_of_line ();
33399 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
33400 on this return so that duplicate extensions (extensions with the
33401 same name as a previous extension in the list) are not considered
33402 for command-line parsing. */
33406 if (opt
->name
== NULL
)
33407 as_bad (_("unknown architecture extension `%s'\n"), name
);
33409 *input_line_pointer
= saved_char
;
33410 ignore_rest_of_line ();
33413 /* Parse a .fpu directive. */
33416 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
33418 const struct arm_option_fpu_value_table
*opt
;
33422 name
= input_line_pointer
;
33423 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33424 input_line_pointer
++;
33425 saved_char
= *input_line_pointer
;
33426 *input_line_pointer
= 0;
33428 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
33429 if (streq (opt
->name
, name
))
33431 selected_fpu
= opt
->value
;
33432 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, fpu_any
);
33433 #ifndef CPU_DEFAULT
33434 if (no_cpu_selected ())
33435 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
33438 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33439 *input_line_pointer
= saved_char
;
33440 demand_empty_rest_of_line ();
33444 as_bad (_("unknown floating point format `%s'\n"), name
);
33445 *input_line_pointer
= saved_char
;
33446 ignore_rest_of_line ();
33449 /* Copy symbol information. */
33452 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
33454 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
33458 /* Given a symbolic attribute NAME, return the proper integer value.
33459 Returns -1 if the attribute is not known. */
33462 arm_convert_symbolic_attribute (const char *name
)
33464 static const struct
33469 attribute_table
[] =
33471 /* When you modify this table you should
33472 also modify the list in doc/c-arm.texi. */
33473 #define T(tag) {#tag, tag}
33474 T (Tag_CPU_raw_name
),
33477 T (Tag_CPU_arch_profile
),
33478 T (Tag_ARM_ISA_use
),
33479 T (Tag_THUMB_ISA_use
),
33483 T (Tag_Advanced_SIMD_arch
),
33484 T (Tag_PCS_config
),
33485 T (Tag_ABI_PCS_R9_use
),
33486 T (Tag_ABI_PCS_RW_data
),
33487 T (Tag_ABI_PCS_RO_data
),
33488 T (Tag_ABI_PCS_GOT_use
),
33489 T (Tag_ABI_PCS_wchar_t
),
33490 T (Tag_ABI_FP_rounding
),
33491 T (Tag_ABI_FP_denormal
),
33492 T (Tag_ABI_FP_exceptions
),
33493 T (Tag_ABI_FP_user_exceptions
),
33494 T (Tag_ABI_FP_number_model
),
33495 T (Tag_ABI_align_needed
),
33496 T (Tag_ABI_align8_needed
),
33497 T (Tag_ABI_align_preserved
),
33498 T (Tag_ABI_align8_preserved
),
33499 T (Tag_ABI_enum_size
),
33500 T (Tag_ABI_HardFP_use
),
33501 T (Tag_ABI_VFP_args
),
33502 T (Tag_ABI_WMMX_args
),
33503 T (Tag_ABI_optimization_goals
),
33504 T (Tag_ABI_FP_optimization_goals
),
33505 T (Tag_compatibility
),
33506 T (Tag_CPU_unaligned_access
),
33507 T (Tag_FP_HP_extension
),
33508 T (Tag_VFP_HP_extension
),
33509 T (Tag_ABI_FP_16bit_format
),
33510 T (Tag_MPextension_use
),
33512 T (Tag_nodefaults
),
33513 T (Tag_also_compatible_with
),
33514 T (Tag_conformance
),
33516 T (Tag_Virtualization_use
),
33517 T (Tag_DSP_extension
),
33519 /* We deliberately do not include Tag_MPextension_use_legacy. */
33527 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
33528 if (streq (name
, attribute_table
[i
].name
))
33529 return attribute_table
[i
].tag
;
33534 /* Apply sym value for relocations only in the case that they are for
33535 local symbols in the same segment as the fixup and you have the
33536 respective architectural feature for blx and simple switches. */
33539 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
33542 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
33543 /* PR 17444: If the local symbol is in a different section then a reloc
33544 will always be generated for it, so applying the symbol value now
33545 will result in a double offset being stored in the relocation. */
33546 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
33547 && !S_FORCE_RELOC (fixP
->fx_addsy
, true))
33549 switch (fixP
->fx_r_type
)
33551 case BFD_RELOC_ARM_PCREL_BLX
:
33552 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
33553 if (ARM_IS_FUNC (fixP
->fx_addsy
))
33557 case BFD_RELOC_ARM_PCREL_CALL
:
33558 case BFD_RELOC_THUMB_PCREL_BLX
:
33559 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
33570 #endif /* OBJ_ELF */