1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
167 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
170 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
173 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
174 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
175 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
176 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
177 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
178 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
179 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
180 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v4t_5
=
182 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
184 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
185 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
186 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
187 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
188 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
190 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
191 static const arm_feature_set arm_ext_v6_notm
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
193 static const arm_feature_set arm_ext_v6_dsp
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
195 static const arm_feature_set arm_ext_barrier
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
197 static const arm_feature_set arm_ext_msr
=
198 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
199 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
200 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
201 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
202 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
204 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
206 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
207 static const arm_feature_set arm_ext_m
=
208 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
,
209 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
210 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
211 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
212 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
213 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
214 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
215 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
216 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
217 static const arm_feature_set arm_ext_v8m_main
=
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
219 /* Instructions in ARMv8-M only found in M profile architectures. */
220 static const arm_feature_set arm_ext_v8m_m_only
=
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
222 static const arm_feature_set arm_ext_v6t2_v8m
=
223 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
224 /* Instructions shared between ARMv8-A and ARMv8-M. */
225 static const arm_feature_set arm_ext_atomics
=
226 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
228 /* DSP instructions Tag_DSP_extension refers to. */
229 static const arm_feature_set arm_ext_dsp
=
230 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
232 static const arm_feature_set arm_ext_ras
=
233 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
234 /* FP16 instructions. */
235 static const arm_feature_set arm_ext_fp16
=
236 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
237 static const arm_feature_set arm_ext_v8_3
=
238 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
240 static const arm_feature_set arm_arch_any
= ARM_ANY
;
241 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
242 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
243 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
245 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
248 static const arm_feature_set arm_cext_iwmmxt2
=
249 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
250 static const arm_feature_set arm_cext_iwmmxt
=
251 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
252 static const arm_feature_set arm_cext_xscale
=
253 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
254 static const arm_feature_set arm_cext_maverick
=
255 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
256 static const arm_feature_set fpu_fpa_ext_v1
=
257 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
258 static const arm_feature_set fpu_fpa_ext_v2
=
259 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
260 static const arm_feature_set fpu_vfp_ext_v1xd
=
261 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
262 static const arm_feature_set fpu_vfp_ext_v1
=
263 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
264 static const arm_feature_set fpu_vfp_ext_v2
=
265 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
266 static const arm_feature_set fpu_vfp_ext_v3xd
=
267 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
268 static const arm_feature_set fpu_vfp_ext_v3
=
269 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
270 static const arm_feature_set fpu_vfp_ext_d32
=
271 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
272 static const arm_feature_set fpu_neon_ext_v1
=
273 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
274 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
275 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
277 static const arm_feature_set fpu_vfp_fp16
=
278 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
279 static const arm_feature_set fpu_neon_ext_fma
=
280 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
282 static const arm_feature_set fpu_vfp_ext_fma
=
283 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
284 static const arm_feature_set fpu_vfp_ext_armv8
=
285 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
286 static const arm_feature_set fpu_vfp_ext_armv8xd
=
287 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
288 static const arm_feature_set fpu_neon_ext_armv8
=
289 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
290 static const arm_feature_set fpu_crypto_ext_armv8
=
291 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
292 static const arm_feature_set crc_ext_armv8
=
293 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
294 static const arm_feature_set fpu_neon_ext_v8_1
=
295 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
297 static int mfloat_abi_opt
= -1;
298 /* Record user cpu selection for object attributes. */
299 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
300 /* Must be long enough to hold any of the names in arm_cpus. */
301 static char selected_cpu_name
[20];
303 extern FLONUM_TYPE generic_floating_point_number
;
305 /* Return if no cpu was selected on command-line. */
307 no_cpu_selected (void)
309 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
314 static int meabi_flags
= EABI_DEFAULT
;
316 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
319 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
324 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
329 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
330 symbolS
* GOT_symbol
;
333 /* 0: assemble for ARM,
334 1: assemble for Thumb,
335 2: assemble for Thumb even though target CPU does not support thumb
337 static int thumb_mode
= 0;
338 /* A value distinct from the possible values for thumb_mode that we
339 can use to record whether thumb_mode has been copied into the
340 tc_frag_data field of a frag. */
341 #define MODE_RECORDED (1 << 4)
343 /* Specifies the intrinsic IT insn behavior mode. */
344 enum implicit_it_mode
346 IMPLICIT_IT_MODE_NEVER
= 0x00,
347 IMPLICIT_IT_MODE_ARM
= 0x01,
348 IMPLICIT_IT_MODE_THUMB
= 0x02,
349 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
351 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
353 /* If unified_syntax is true, we are processing the new unified
354 ARM/Thumb syntax. Important differences from the old ARM mode:
356 - Immediate operands do not require a # prefix.
357 - Conditional affixes always appear at the end of the
358 instruction. (For backward compatibility, those instructions
359 that formerly had them in the middle, continue to accept them
361 - The IT instruction may appear, and if it does is validated
362 against subsequent conditional affixes. It does not generate
365 Important differences from the old Thumb mode:
367 - Immediate operands do not require a # prefix.
368 - Most of the V6T2 instructions are only available in unified mode.
369 - The .N and .W suffixes are recognized and honored (it is an error
370 if they cannot be honored).
371 - All instructions set the flags if and only if they have an 's' affix.
372 - Conditional affixes may be used. They are validated against
373 preceding IT instructions. Unlike ARM mode, you cannot use a
374 conditional affix except in the scope of an IT instruction. */
376 static bfd_boolean unified_syntax
= FALSE
;
378 /* An immediate operand can start with #, and ld*, st*, pld operands
379 can contain [ and ]. We need to tell APP not to elide whitespace
380 before a [, which can appear as the first operand for pld.
381 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
382 const char arm_symbol_chars
[] = "#[]{}";
397 enum neon_el_type type
;
401 #define NEON_MAX_TYPE_ELS 4
405 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
409 enum it_instruction_type
414 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
415 if inside, should be the last one. */
416 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
417 i.e. BKPT and NOP. */
418 IT_INSN
/* The IT insn has been parsed. */
421 /* The maximum number of operands we need. */
422 #define ARM_IT_MAX_OPERANDS 6
427 unsigned long instruction
;
431 /* "uncond_value" is set to the value in place of the conditional field in
432 unconditional versions of the instruction, or -1 if nothing is
435 struct neon_type vectype
;
436 /* This does not indicate an actual NEON instruction, only that
437 the mnemonic accepts neon-style type suffixes. */
439 /* Set to the opcode if the instruction needs relaxation.
440 Zero if the instruction is not relaxed. */
444 bfd_reloc_code_real_type type
;
449 enum it_instruction_type it_insn_type
;
455 struct neon_type_el vectype
;
456 unsigned present
: 1; /* Operand present. */
457 unsigned isreg
: 1; /* Operand was a register. */
458 unsigned immisreg
: 1; /* .imm field is a second register. */
459 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
460 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
461 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
462 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
463 instructions. This allows us to disambiguate ARM <-> vector insns. */
464 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
465 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
466 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
467 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
468 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
469 unsigned writeback
: 1; /* Operand has trailing ! */
470 unsigned preind
: 1; /* Preindexed address. */
471 unsigned postind
: 1; /* Postindexed address. */
472 unsigned negative
: 1; /* Index register was negated. */
473 unsigned shifted
: 1; /* Shift applied to operation. */
474 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
475 } operands
[ARM_IT_MAX_OPERANDS
];
478 static struct arm_it inst
;
480 #define NUM_FLOAT_VALS 8
482 const char * fp_const
[] =
484 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
487 /* Number of littlenums required to hold an extended precision number. */
488 #define MAX_LITTLENUMS 6
490 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
500 #define CP_T_X 0x00008000
501 #define CP_T_Y 0x00400000
503 #define CONDS_BIT 0x00100000
504 #define LOAD_BIT 0x00100000
506 #define DOUBLE_LOAD_FLAG 0x00000001
510 const char * template_name
;
514 #define COND_ALWAYS 0xE
518 const char * template_name
;
522 struct asm_barrier_opt
524 const char * template_name
;
526 const arm_feature_set arch
;
529 /* The bit that distinguishes CPSR and SPSR. */
530 #define SPSR_BIT (1 << 22)
532 /* The individual PSR flag bits. */
533 #define PSR_c (1 << 16)
534 #define PSR_x (1 << 17)
535 #define PSR_s (1 << 18)
536 #define PSR_f (1 << 19)
541 bfd_reloc_code_real_type reloc
;
546 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
547 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
552 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
555 /* Bits for DEFINED field in neon_typed_alias. */
556 #define NTA_HASTYPE 1
557 #define NTA_HASINDEX 2
559 struct neon_typed_alias
561 unsigned char defined
;
563 struct neon_type_el eltype
;
566 /* ARM register categories. This includes coprocessor numbers and various
567 architecture extensions' registers. */
594 /* Structure for a hash table entry for a register.
595 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
596 information which states whether a vector type or index is specified (for a
597 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
603 unsigned char builtin
;
604 struct neon_typed_alias
* neon
;
607 /* Diagnostics used when we don't get a register of the expected type. */
608 const char * const reg_expected_msgs
[] =
610 N_("ARM register expected"),
611 N_("bad or missing co-processor number"),
612 N_("co-processor register expected"),
613 N_("FPA register expected"),
614 N_("VFP single precision register expected"),
615 N_("VFP/Neon double precision register expected"),
616 N_("Neon quad precision register expected"),
617 N_("VFP single or double precision register expected"),
618 N_("Neon double or quad precision register expected"),
619 N_("VFP single, double or Neon quad precision register expected"),
620 N_("VFP system register expected"),
621 N_("Maverick MVF register expected"),
622 N_("Maverick MVD register expected"),
623 N_("Maverick MVFX register expected"),
624 N_("Maverick MVDX register expected"),
625 N_("Maverick MVAX register expected"),
626 N_("Maverick DSPSC register expected"),
627 N_("iWMMXt data register expected"),
628 N_("iWMMXt control register expected"),
629 N_("iWMMXt scalar register expected"),
630 N_("XScale accumulator register expected"),
633 /* Some well known registers that we refer to directly elsewhere. */
639 /* ARM instructions take 4bytes in the object file, Thumb instructions
645 /* Basic string to match. */
646 const char * template_name
;
648 /* Parameters to instruction. */
649 unsigned int operands
[8];
651 /* Conditional tag - see opcode_lookup. */
652 unsigned int tag
: 4;
654 /* Basic instruction code. */
655 unsigned int avalue
: 28;
657 /* Thumb-format instruction code. */
660 /* Which architecture variant provides this instruction. */
661 const arm_feature_set
* avariant
;
662 const arm_feature_set
* tvariant
;
664 /* Function to call to encode instruction in ARM format. */
665 void (* aencode
) (void);
667 /* Function to call to encode instruction in Thumb format. */
668 void (* tencode
) (void);
671 /* Defines for various bits that we will want to toggle. */
672 #define INST_IMMEDIATE 0x02000000
673 #define OFFSET_REG 0x02000000
674 #define HWOFFSET_IMM 0x00400000
675 #define SHIFT_BY_REG 0x00000010
676 #define PRE_INDEX 0x01000000
677 #define INDEX_UP 0x00800000
678 #define WRITE_BACK 0x00200000
679 #define LDM_TYPE_2_OR_3 0x00400000
680 #define CPSI_MMOD 0x00020000
682 #define LITERAL_MASK 0xf000f000
683 #define OPCODE_MASK 0xfe1fffff
684 #define V4_STR_BIT 0x00000020
685 #define VLDR_VMOV_SAME 0x0040f000
687 #define T2_SUBS_PC_LR 0xf3de8f00
689 #define DATA_OP_SHIFT 21
690 #define SBIT_SHIFT 20
692 #define T2_OPCODE_MASK 0xfe1fffff
693 #define T2_DATA_OP_SHIFT 21
694 #define T2_SBIT_SHIFT 20
696 #define A_COND_MASK 0xf0000000
697 #define A_PUSH_POP_OP_MASK 0x0fff0000
699 /* Opcodes for pushing/poping registers to/from the stack. */
700 #define A1_OPCODE_PUSH 0x092d0000
701 #define A2_OPCODE_PUSH 0x052d0004
702 #define A2_OPCODE_POP 0x049d0004
704 /* Codes to distinguish the arithmetic instructions. */
715 #define OPCODE_CMP 10
716 #define OPCODE_CMN 11
717 #define OPCODE_ORR 12
718 #define OPCODE_MOV 13
719 #define OPCODE_BIC 14
720 #define OPCODE_MVN 15
722 #define T2_OPCODE_AND 0
723 #define T2_OPCODE_BIC 1
724 #define T2_OPCODE_ORR 2
725 #define T2_OPCODE_ORN 3
726 #define T2_OPCODE_EOR 4
727 #define T2_OPCODE_ADD 8
728 #define T2_OPCODE_ADC 10
729 #define T2_OPCODE_SBC 11
730 #define T2_OPCODE_SUB 13
731 #define T2_OPCODE_RSB 14
733 #define T_OPCODE_MUL 0x4340
734 #define T_OPCODE_TST 0x4200
735 #define T_OPCODE_CMN 0x42c0
736 #define T_OPCODE_NEG 0x4240
737 #define T_OPCODE_MVN 0x43c0
739 #define T_OPCODE_ADD_R3 0x1800
740 #define T_OPCODE_SUB_R3 0x1a00
741 #define T_OPCODE_ADD_HI 0x4400
742 #define T_OPCODE_ADD_ST 0xb000
743 #define T_OPCODE_SUB_ST 0xb080
744 #define T_OPCODE_ADD_SP 0xa800
745 #define T_OPCODE_ADD_PC 0xa000
746 #define T_OPCODE_ADD_I8 0x3000
747 #define T_OPCODE_SUB_I8 0x3800
748 #define T_OPCODE_ADD_I3 0x1c00
749 #define T_OPCODE_SUB_I3 0x1e00
751 #define T_OPCODE_ASR_R 0x4100
752 #define T_OPCODE_LSL_R 0x4080
753 #define T_OPCODE_LSR_R 0x40c0
754 #define T_OPCODE_ROR_R 0x41c0
755 #define T_OPCODE_ASR_I 0x1000
756 #define T_OPCODE_LSL_I 0x0000
757 #define T_OPCODE_LSR_I 0x0800
759 #define T_OPCODE_MOV_I8 0x2000
760 #define T_OPCODE_CMP_I8 0x2800
761 #define T_OPCODE_CMP_LR 0x4280
762 #define T_OPCODE_MOV_HR 0x4600
763 #define T_OPCODE_CMP_HR 0x4500
765 #define T_OPCODE_LDR_PC 0x4800
766 #define T_OPCODE_LDR_SP 0x9800
767 #define T_OPCODE_STR_SP 0x9000
768 #define T_OPCODE_LDR_IW 0x6800
769 #define T_OPCODE_STR_IW 0x6000
770 #define T_OPCODE_LDR_IH 0x8800
771 #define T_OPCODE_STR_IH 0x8000
772 #define T_OPCODE_LDR_IB 0x7800
773 #define T_OPCODE_STR_IB 0x7000
774 #define T_OPCODE_LDR_RW 0x5800
775 #define T_OPCODE_STR_RW 0x5000
776 #define T_OPCODE_LDR_RH 0x5a00
777 #define T_OPCODE_STR_RH 0x5200
778 #define T_OPCODE_LDR_RB 0x5c00
779 #define T_OPCODE_STR_RB 0x5400
781 #define T_OPCODE_PUSH 0xb400
782 #define T_OPCODE_POP 0xbc00
784 #define T_OPCODE_BRANCH 0xe000
786 #define THUMB_SIZE 2 /* Size of thumb instruction. */
787 #define THUMB_PP_PC_LR 0x0100
788 #define THUMB_LOAD_BIT 0x0800
789 #define THUMB2_LOAD_BIT 0x00100000
791 #define BAD_ARGS _("bad arguments to instruction")
792 #define BAD_SP _("r13 not allowed here")
793 #define BAD_PC _("r15 not allowed here")
794 #define BAD_COND _("instruction cannot be conditional")
795 #define BAD_OVERLAP _("registers may not be the same")
796 #define BAD_HIREG _("lo register required")
797 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
798 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
799 #define BAD_BRANCH _("branch must be last instruction in IT block")
800 #define BAD_NOT_IT _("instruction not allowed in IT block")
801 #define BAD_FPU _("selected FPU does not support instruction")
802 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
803 #define BAD_IT_COND _("incorrect condition in IT block")
804 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
805 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
806 #define BAD_PC_ADDRESSING \
807 _("cannot use register index with PC-relative addressing")
808 #define BAD_PC_WRITEBACK \
809 _("cannot use writeback with PC-relative addressing")
810 #define BAD_RANGE _("branch out of range")
811 #define BAD_FP16 _("selected processor does not support fp16 instruction")
812 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
813 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
815 static struct hash_control
* arm_ops_hsh
;
816 static struct hash_control
* arm_cond_hsh
;
817 static struct hash_control
* arm_shift_hsh
;
818 static struct hash_control
* arm_psr_hsh
;
819 static struct hash_control
* arm_v7m_psr_hsh
;
820 static struct hash_control
* arm_reg_hsh
;
821 static struct hash_control
* arm_reloc_hsh
;
822 static struct hash_control
* arm_barrier_opt_hsh
;
824 /* Stuff needed to resolve the label ambiguity
833 symbolS
* last_label_seen
;
834 static int label_is_thumb_function_name
= FALSE
;
836 /* Literal pool structure. Held on a per-section
837 and per-sub-section basis. */
839 #define MAX_LITERAL_POOL_SIZE 1024
840 typedef struct literal_pool
842 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
843 unsigned int next_free_entry
;
849 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
851 struct literal_pool
* next
;
852 unsigned int alignment
;
855 /* Pointer to a linked list of literal pools. */
856 literal_pool
* list_of_pools
= NULL
;
858 typedef enum asmfunc_states
861 WAITING_ASMFUNC_NAME
,
865 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
868 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
870 static struct current_it now_it
;
874 now_it_compatible (int cond
)
876 return (cond
& ~1) == (now_it
.cc
& ~1);
880 conditional_insn (void)
882 return inst
.cond
!= COND_ALWAYS
;
885 static int in_it_block (void);
887 static int handle_it_state (void);
889 static void force_automatic_it_block_close (void);
891 static void it_fsm_post_encode (void);
893 #define set_it_insn_type(type) \
896 inst.it_insn_type = type; \
897 if (handle_it_state () == FAIL) \
902 #define set_it_insn_type_nonvoid(type, failret) \
905 inst.it_insn_type = type; \
906 if (handle_it_state () == FAIL) \
911 #define set_it_insn_type_last() \
914 if (inst.cond == COND_ALWAYS) \
915 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
917 set_it_insn_type (INSIDE_IT_LAST_INSN); \
923 /* This array holds the chars that always start a comment. If the
924 pre-processor is disabled, these aren't very useful. */
925 char arm_comment_chars
[] = "@";
927 /* This array holds the chars that only start a comment at the beginning of
928 a line. If the line seems to have the form '# 123 filename'
929 .line and .file directives will appear in the pre-processed output. */
930 /* Note that input_file.c hand checks for '#' at the beginning of the
931 first line of the input file. This is because the compiler outputs
932 #NO_APP at the beginning of its output. */
933 /* Also note that comments like this one will always work. */
934 const char line_comment_chars
[] = "#";
936 char arm_line_separator_chars
[] = ";";
938 /* Chars that can be used to separate mant
939 from exp in floating point numbers. */
940 const char EXP_CHARS
[] = "eE";
942 /* Chars that mean this number is a floating point constant. */
946 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
948 /* Prefix characters that indicate the start of an immediate
950 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
952 /* Separator character handling. */
954 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
957 skip_past_char (char ** str
, char c
)
959 /* PR gas/14987: Allow for whitespace before the expected character. */
960 skip_whitespace (*str
);
971 #define skip_past_comma(str) skip_past_char (str, ',')
973 /* Arithmetic expressions (possibly involving symbols). */
975 /* Return TRUE if anything in the expression is a bignum. */
978 walk_no_bignums (symbolS
* sp
)
980 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
983 if (symbol_get_value_expression (sp
)->X_add_symbol
)
985 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
986 || (symbol_get_value_expression (sp
)->X_op_symbol
987 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
993 static int in_my_get_expression
= 0;
995 /* Third argument to my_get_expression. */
996 #define GE_NO_PREFIX 0
997 #define GE_IMM_PREFIX 1
998 #define GE_OPT_PREFIX 2
999 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1000 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1001 #define GE_OPT_PREFIX_BIG 3
1004 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1009 /* In unified syntax, all prefixes are optional. */
1011 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1014 switch (prefix_mode
)
1016 case GE_NO_PREFIX
: break;
1018 if (!is_immediate_prefix (**str
))
1020 inst
.error
= _("immediate expression requires a # prefix");
1026 case GE_OPT_PREFIX_BIG
:
1027 if (is_immediate_prefix (**str
))
1033 memset (ep
, 0, sizeof (expressionS
));
1035 save_in
= input_line_pointer
;
1036 input_line_pointer
= *str
;
1037 in_my_get_expression
= 1;
1038 seg
= expression (ep
);
1039 in_my_get_expression
= 0;
1041 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1043 /* We found a bad or missing expression in md_operand(). */
1044 *str
= input_line_pointer
;
1045 input_line_pointer
= save_in
;
1046 if (inst
.error
== NULL
)
1047 inst
.error
= (ep
->X_op
== O_absent
1048 ? _("missing expression") :_("bad expression"));
1053 if (seg
!= absolute_section
1054 && seg
!= text_section
1055 && seg
!= data_section
1056 && seg
!= bss_section
1057 && seg
!= undefined_section
)
1059 inst
.error
= _("bad segment");
1060 *str
= input_line_pointer
;
1061 input_line_pointer
= save_in
;
1068 /* Get rid of any bignums now, so that we don't generate an error for which
1069 we can't establish a line number later on. Big numbers are never valid
1070 in instructions, which is where this routine is always called. */
1071 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1072 && (ep
->X_op
== O_big
1073 || (ep
->X_add_symbol
1074 && (walk_no_bignums (ep
->X_add_symbol
)
1076 && walk_no_bignums (ep
->X_op_symbol
))))))
1078 inst
.error
= _("invalid constant");
1079 *str
= input_line_pointer
;
1080 input_line_pointer
= save_in
;
1084 *str
= input_line_pointer
;
1085 input_line_pointer
= save_in
;
1089 /* Turn a string in input_line_pointer into a floating point constant
1090 of type TYPE, and store the appropriate bytes in *LITP. The number
1091 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1092 returned, or NULL on OK.
1094 Note that fp constants aren't represent in the normal way on the ARM.
1095 In big endian mode, things are as expected. However, in little endian
1096 mode fp constants are big-endian word-wise, and little-endian byte-wise
1097 within the words. For example, (double) 1.1 in big endian mode is
1098 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1099 the byte sequence 99 99 f1 3f 9a 99 99 99.
1101 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1104 md_atof (int type
, char * litP
, int * sizeP
)
1107 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1139 return _("Unrecognized or unsupported floating point constant");
1142 t
= atof_ieee (input_line_pointer
, type
, words
);
1144 input_line_pointer
= t
;
1145 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1147 if (target_big_endian
)
1149 for (i
= 0; i
< prec
; i
++)
1151 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1152 litP
+= sizeof (LITTLENUM_TYPE
);
1157 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1158 for (i
= prec
- 1; i
>= 0; i
--)
1160 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1161 litP
+= sizeof (LITTLENUM_TYPE
);
1164 /* For a 4 byte float the order of elements in `words' is 1 0.
1165 For an 8 byte float the order is 1 0 3 2. */
1166 for (i
= 0; i
< prec
; i
+= 2)
1168 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1169 sizeof (LITTLENUM_TYPE
));
1170 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1171 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1172 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1179 /* We handle all bad expressions here, so that we can report the faulty
1180 instruction in the error message. */
1182 md_operand (expressionS
* exp
)
1184 if (in_my_get_expression
)
1185 exp
->X_op
= O_illegal
;
1188 /* Immediate values. */
1190 /* Generic immediate-value read function for use in directives.
1191 Accepts anything that 'expression' can fold to a constant.
1192 *val receives the number. */
1195 immediate_for_directive (int *val
)
1198 exp
.X_op
= O_illegal
;
1200 if (is_immediate_prefix (*input_line_pointer
))
1202 input_line_pointer
++;
1206 if (exp
.X_op
!= O_constant
)
1208 as_bad (_("expected #constant"));
1209 ignore_rest_of_line ();
1212 *val
= exp
.X_add_number
;
1217 /* Register parsing. */
1219 /* Generic register parser. CCP points to what should be the
1220 beginning of a register name. If it is indeed a valid register
1221 name, advance CCP over it and return the reg_entry structure;
1222 otherwise return NULL. Does not issue diagnostics. */
1224 static struct reg_entry
*
1225 arm_reg_parse_multi (char **ccp
)
1229 struct reg_entry
*reg
;
1231 skip_whitespace (start
);
1233 #ifdef REGISTER_PREFIX
1234 if (*start
!= REGISTER_PREFIX
)
1238 #ifdef OPTIONAL_REGISTER_PREFIX
1239 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1244 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1249 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1251 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1261 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1262 enum arm_reg_type type
)
1264 /* Alternative syntaxes are accepted for a few register classes. */
1271 /* Generic coprocessor register names are allowed for these. */
1272 if (reg
&& reg
->type
== REG_TYPE_CN
)
1277 /* For backward compatibility, a bare number is valid here. */
1279 unsigned long processor
= strtoul (start
, ccp
, 10);
1280 if (*ccp
!= start
&& processor
<= 15)
1285 case REG_TYPE_MMXWC
:
1286 /* WC includes WCG. ??? I'm not sure this is true for all
1287 instructions that take WC registers. */
1288 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1299 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1300 return value is the register number or FAIL. */
1303 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1306 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1309 /* Do not allow a scalar (reg+index) to parse as a register. */
1310 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1313 if (reg
&& reg
->type
== type
)
1316 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1323 /* Parse a Neon type specifier. *STR should point at the leading '.'
1324 character. Does no verification at this stage that the type fits the opcode
1331 Can all be legally parsed by this function.
1333 Fills in neon_type struct pointer with parsed information, and updates STR
1334 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1335 type, FAIL if not. */
1338 parse_neon_type (struct neon_type
*type
, char **str
)
1345 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1347 enum neon_el_type thistype
= NT_untyped
;
1348 unsigned thissize
= -1u;
1355 /* Just a size without an explicit type. */
1359 switch (TOLOWER (*ptr
))
1361 case 'i': thistype
= NT_integer
; break;
1362 case 'f': thistype
= NT_float
; break;
1363 case 'p': thistype
= NT_poly
; break;
1364 case 's': thistype
= NT_signed
; break;
1365 case 'u': thistype
= NT_unsigned
; break;
1367 thistype
= NT_float
;
1372 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1378 /* .f is an abbreviation for .f32. */
1379 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1384 thissize
= strtoul (ptr
, &ptr
, 10);
1386 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1389 as_bad (_("bad size %d in type specifier"), thissize
);
1397 type
->el
[type
->elems
].type
= thistype
;
1398 type
->el
[type
->elems
].size
= thissize
;
1403 /* Empty/missing type is not a successful parse. */
1404 if (type
->elems
== 0)
1412 /* Errors may be set multiple times during parsing or bit encoding
1413 (particularly in the Neon bits), but usually the earliest error which is set
1414 will be the most meaningful. Avoid overwriting it with later (cascading)
1415 errors by calling this function. */
1418 first_error (const char *err
)
1424 /* Parse a single type, e.g. ".s32", leading period included. */
1426 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1429 struct neon_type optype
;
1433 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1435 if (optype
.elems
== 1)
1436 *vectype
= optype
.el
[0];
1439 first_error (_("only one type should be specified for operand"));
1445 first_error (_("vector type expected"));
1457 /* Special meanings for indices (which have a range of 0-7), which will fit into
1460 #define NEON_ALL_LANES 15
1461 #define NEON_INTERLEAVE_LANES 14
1463 /* Parse either a register or a scalar, with an optional type. Return the
1464 register number, and optionally fill in the actual type of the register
1465 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1466 type/index information in *TYPEINFO. */
1469 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1470 enum arm_reg_type
*rtype
,
1471 struct neon_typed_alias
*typeinfo
)
1474 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1475 struct neon_typed_alias atype
;
1476 struct neon_type_el parsetype
;
1480 atype
.eltype
.type
= NT_invtype
;
1481 atype
.eltype
.size
= -1;
1483 /* Try alternate syntax for some types of register. Note these are mutually
1484 exclusive with the Neon syntax extensions. */
1487 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1495 /* Undo polymorphism when a set of register types may be accepted. */
1496 if ((type
== REG_TYPE_NDQ
1497 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1498 || (type
== REG_TYPE_VFSD
1499 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1500 || (type
== REG_TYPE_NSDQ
1501 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1502 || reg
->type
== REG_TYPE_NQ
))
1503 || (type
== REG_TYPE_MMXWC
1504 && (reg
->type
== REG_TYPE_MMXWCG
)))
1505 type
= (enum arm_reg_type
) reg
->type
;
1507 if (type
!= reg
->type
)
1513 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1515 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1517 first_error (_("can't redefine type for operand"));
1520 atype
.defined
|= NTA_HASTYPE
;
1521 atype
.eltype
= parsetype
;
1524 if (skip_past_char (&str
, '[') == SUCCESS
)
1526 if (type
!= REG_TYPE_VFD
)
1528 first_error (_("only D registers may be indexed"));
1532 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1534 first_error (_("can't change index for operand"));
1538 atype
.defined
|= NTA_HASINDEX
;
1540 if (skip_past_char (&str
, ']') == SUCCESS
)
1541 atype
.index
= NEON_ALL_LANES
;
1546 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1548 if (exp
.X_op
!= O_constant
)
1550 first_error (_("constant expression required"));
1554 if (skip_past_char (&str
, ']') == FAIL
)
1557 atype
.index
= exp
.X_add_number
;
1572 /* Like arm_reg_parse, but allow allow the following extra features:
1573 - If RTYPE is non-zero, return the (possibly restricted) type of the
1574 register (e.g. Neon double or quad reg when either has been requested).
1575 - If this is a Neon vector type with additional type information, fill
1576 in the struct pointed to by VECTYPE (if non-NULL).
1577 This function will fault on encountering a scalar. */
1580 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1581 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1583 struct neon_typed_alias atype
;
1585 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1590 /* Do not allow regname(... to parse as a register. */
1594 /* Do not allow a scalar (reg+index) to parse as a register. */
1595 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1597 first_error (_("register operand expected, but got scalar"));
1602 *vectype
= atype
.eltype
;
1609 #define NEON_SCALAR_REG(X) ((X) >> 4)
1610 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1612 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1613 have enough information to be able to do a good job bounds-checking. So, we
1614 just do easy checks here, and do further checks later. */
1617 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1621 struct neon_typed_alias atype
;
1623 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1625 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1628 if (atype
.index
== NEON_ALL_LANES
)
1630 first_error (_("scalar must have an index"));
1633 else if (atype
.index
>= 64 / elsize
)
1635 first_error (_("scalar index out of range"));
1640 *type
= atype
.eltype
;
1644 return reg
* 16 + atype
.index
;
1647 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1650 parse_reg_list (char ** strp
)
1652 char * str
= * strp
;
1656 /* We come back here if we get ranges concatenated by '+' or '|'. */
1659 skip_whitespace (str
);
1673 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1675 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1685 first_error (_("bad range in register list"));
1689 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1691 if (range
& (1 << i
))
1693 (_("Warning: duplicated register (r%d) in register list"),
1701 if (range
& (1 << reg
))
1702 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1704 else if (reg
<= cur_reg
)
1705 as_tsktsk (_("Warning: register range not in ascending order"));
1710 while (skip_past_comma (&str
) != FAIL
1711 || (in_range
= 1, *str
++ == '-'));
1714 if (skip_past_char (&str
, '}') == FAIL
)
1716 first_error (_("missing `}'"));
1724 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1727 if (exp
.X_op
== O_constant
)
1729 if (exp
.X_add_number
1730 != (exp
.X_add_number
& 0x0000ffff))
1732 inst
.error
= _("invalid register mask");
1736 if ((range
& exp
.X_add_number
) != 0)
1738 int regno
= range
& exp
.X_add_number
;
1741 regno
= (1 << regno
) - 1;
1743 (_("Warning: duplicated register (r%d) in register list"),
1747 range
|= exp
.X_add_number
;
1751 if (inst
.reloc
.type
!= 0)
1753 inst
.error
= _("expression too complex");
1757 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1758 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1759 inst
.reloc
.pc_rel
= 0;
1763 if (*str
== '|' || *str
== '+')
1769 while (another_range
);
1775 /* Types of registers in a list. */
1784 /* Parse a VFP register list. If the string is invalid return FAIL.
1785 Otherwise return the number of registers, and set PBASE to the first
1786 register. Parses registers of type ETYPE.
1787 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1788 - Q registers can be used to specify pairs of D registers
1789 - { } can be omitted from around a singleton register list
1790 FIXME: This is not implemented, as it would require backtracking in
1793 This could be done (the meaning isn't really ambiguous), but doesn't
1794 fit in well with the current parsing framework.
1795 - 32 D registers may be used (also true for VFPv3).
1796 FIXME: Types are ignored in these register lists, which is probably a
1800 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1805 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1809 unsigned long mask
= 0;
1812 if (skip_past_char (&str
, '{') == FAIL
)
1814 inst
.error
= _("expecting {");
1821 regtype
= REG_TYPE_VFS
;
1826 regtype
= REG_TYPE_VFD
;
1829 case REGLIST_NEON_D
:
1830 regtype
= REG_TYPE_NDQ
;
1834 if (etype
!= REGLIST_VFP_S
)
1836 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1837 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1841 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1844 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1851 base_reg
= max_regs
;
1855 int setmask
= 1, addregs
= 1;
1857 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1859 if (new_base
== FAIL
)
1861 first_error (_(reg_expected_msgs
[regtype
]));
1865 if (new_base
>= max_regs
)
1867 first_error (_("register out of range in list"));
1871 /* Note: a value of 2 * n is returned for the register Q<n>. */
1872 if (regtype
== REG_TYPE_NQ
)
1878 if (new_base
< base_reg
)
1879 base_reg
= new_base
;
1881 if (mask
& (setmask
<< new_base
))
1883 first_error (_("invalid register list"));
1887 if ((mask
>> new_base
) != 0 && ! warned
)
1889 as_tsktsk (_("register list not in ascending order"));
1893 mask
|= setmask
<< new_base
;
1896 if (*str
== '-') /* We have the start of a range expression */
1902 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1905 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1909 if (high_range
>= max_regs
)
1911 first_error (_("register out of range in list"));
1915 if (regtype
== REG_TYPE_NQ
)
1916 high_range
= high_range
+ 1;
1918 if (high_range
<= new_base
)
1920 inst
.error
= _("register range not in ascending order");
1924 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1926 if (mask
& (setmask
<< new_base
))
1928 inst
.error
= _("invalid register list");
1932 mask
|= setmask
<< new_base
;
1937 while (skip_past_comma (&str
) != FAIL
);
1941 /* Sanity check -- should have raised a parse error above. */
1942 if (count
== 0 || count
> max_regs
)
1947 /* Final test -- the registers must be consecutive. */
1949 for (i
= 0; i
< count
; i
++)
1951 if ((mask
& (1u << i
)) == 0)
1953 inst
.error
= _("non-contiguous register range");
1963 /* True if two alias types are the same. */
1966 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1974 if (a
->defined
!= b
->defined
)
1977 if ((a
->defined
& NTA_HASTYPE
) != 0
1978 && (a
->eltype
.type
!= b
->eltype
.type
1979 || a
->eltype
.size
!= b
->eltype
.size
))
1982 if ((a
->defined
& NTA_HASINDEX
) != 0
1983 && (a
->index
!= b
->index
))
1989 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1990 The base register is put in *PBASE.
1991 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1993 The register stride (minus one) is put in bit 4 of the return value.
1994 Bits [6:5] encode the list length (minus one).
1995 The type of the list elements is put in *ELTYPE, if non-NULL. */
1997 #define NEON_LANE(X) ((X) & 0xf)
1998 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1999 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2002 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2003 struct neon_type_el
*eltype
)
2010 int leading_brace
= 0;
2011 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2012 const char *const incr_error
= _("register stride must be 1 or 2");
2013 const char *const type_error
= _("mismatched element/structure types in list");
2014 struct neon_typed_alias firsttype
;
2015 firsttype
.defined
= 0;
2016 firsttype
.eltype
.type
= NT_invtype
;
2017 firsttype
.eltype
.size
= -1;
2018 firsttype
.index
= -1;
2020 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2025 struct neon_typed_alias atype
;
2026 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2030 first_error (_(reg_expected_msgs
[rtype
]));
2037 if (rtype
== REG_TYPE_NQ
)
2043 else if (reg_incr
== -1)
2045 reg_incr
= getreg
- base_reg
;
2046 if (reg_incr
< 1 || reg_incr
> 2)
2048 first_error (_(incr_error
));
2052 else if (getreg
!= base_reg
+ reg_incr
* count
)
2054 first_error (_(incr_error
));
2058 if (! neon_alias_types_same (&atype
, &firsttype
))
2060 first_error (_(type_error
));
2064 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2068 struct neon_typed_alias htype
;
2069 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2071 lane
= NEON_INTERLEAVE_LANES
;
2072 else if (lane
!= NEON_INTERLEAVE_LANES
)
2074 first_error (_(type_error
));
2079 else if (reg_incr
!= 1)
2081 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2085 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2088 first_error (_(reg_expected_msgs
[rtype
]));
2091 if (! neon_alias_types_same (&htype
, &firsttype
))
2093 first_error (_(type_error
));
2096 count
+= hireg
+ dregs
- getreg
;
2100 /* If we're using Q registers, we can't use [] or [n] syntax. */
2101 if (rtype
== REG_TYPE_NQ
)
2107 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2111 else if (lane
!= atype
.index
)
2113 first_error (_(type_error
));
2117 else if (lane
== -1)
2118 lane
= NEON_INTERLEAVE_LANES
;
2119 else if (lane
!= NEON_INTERLEAVE_LANES
)
2121 first_error (_(type_error
));
2126 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2128 /* No lane set by [x]. We must be interleaving structures. */
2130 lane
= NEON_INTERLEAVE_LANES
;
2133 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2134 || (count
> 1 && reg_incr
== -1))
2136 first_error (_("error parsing element/structure list"));
2140 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2142 first_error (_("expected }"));
2150 *eltype
= firsttype
.eltype
;
2155 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2158 /* Parse an explicit relocation suffix on an expression. This is
2159 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2160 arm_reloc_hsh contains no entries, so this function can only
2161 succeed if there is no () after the word. Returns -1 on error,
2162 BFD_RELOC_UNUSED if there wasn't any suffix. */
2165 parse_reloc (char **str
)
2167 struct reloc_entry
*r
;
2171 return BFD_RELOC_UNUSED
;
2176 while (*q
&& *q
!= ')' && *q
!= ',')
2181 if ((r
= (struct reloc_entry
*)
2182 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2189 /* Directives: register aliases. */
2191 static struct reg_entry
*
2192 insert_reg_alias (char *str
, unsigned number
, int type
)
2194 struct reg_entry
*new_reg
;
2197 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2199 if (new_reg
->builtin
)
2200 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2202 /* Only warn about a redefinition if it's not defined as the
2204 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2205 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2210 name
= xstrdup (str
);
2211 new_reg
= XNEW (struct reg_entry
);
2213 new_reg
->name
= name
;
2214 new_reg
->number
= number
;
2215 new_reg
->type
= type
;
2216 new_reg
->builtin
= FALSE
;
2217 new_reg
->neon
= NULL
;
2219 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2226 insert_neon_reg_alias (char *str
, int number
, int type
,
2227 struct neon_typed_alias
*atype
)
2229 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2233 first_error (_("attempt to redefine typed alias"));
2239 reg
->neon
= XNEW (struct neon_typed_alias
);
2240 *reg
->neon
= *atype
;
2244 /* Look for the .req directive. This is of the form:
2246 new_register_name .req existing_register_name
2248 If we find one, or if it looks sufficiently like one that we want to
2249 handle any error here, return TRUE. Otherwise return FALSE. */
2252 create_register_alias (char * newname
, char *p
)
2254 struct reg_entry
*old
;
2255 char *oldname
, *nbuf
;
2258 /* The input scrubber ensures that whitespace after the mnemonic is
2259 collapsed to single spaces. */
2261 if (strncmp (oldname
, " .req ", 6) != 0)
2265 if (*oldname
== '\0')
2268 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2271 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2275 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2276 the desired alias name, and p points to its end. If not, then
2277 the desired alias name is in the global original_case_string. */
2278 #ifdef TC_CASE_SENSITIVE
2281 newname
= original_case_string
;
2282 nlen
= strlen (newname
);
2285 nbuf
= xmemdup0 (newname
, nlen
);
2287 /* Create aliases under the new name as stated; an all-lowercase
2288 version of the new name; and an all-uppercase version of the new
2290 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2292 for (p
= nbuf
; *p
; p
++)
2295 if (strncmp (nbuf
, newname
, nlen
))
2297 /* If this attempt to create an additional alias fails, do not bother
2298 trying to create the all-lower case alias. We will fail and issue
2299 a second, duplicate error message. This situation arises when the
2300 programmer does something like:
2303 The second .req creates the "Foo" alias but then fails to create
2304 the artificial FOO alias because it has already been created by the
2306 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2313 for (p
= nbuf
; *p
; p
++)
2316 if (strncmp (nbuf
, newname
, nlen
))
2317 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2324 /* Create a Neon typed/indexed register alias using directives, e.g.:
2329 These typed registers can be used instead of the types specified after the
2330 Neon mnemonic, so long as all operands given have types. Types can also be
2331 specified directly, e.g.:
2332 vadd d0.s32, d1.s32, d2.s32 */
2335 create_neon_reg_alias (char *newname
, char *p
)
2337 enum arm_reg_type basetype
;
2338 struct reg_entry
*basereg
;
2339 struct reg_entry mybasereg
;
2340 struct neon_type ntype
;
2341 struct neon_typed_alias typeinfo
;
2342 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2345 typeinfo
.defined
= 0;
2346 typeinfo
.eltype
.type
= NT_invtype
;
2347 typeinfo
.eltype
.size
= -1;
2348 typeinfo
.index
= -1;
2352 if (strncmp (p
, " .dn ", 5) == 0)
2353 basetype
= REG_TYPE_VFD
;
2354 else if (strncmp (p
, " .qn ", 5) == 0)
2355 basetype
= REG_TYPE_NQ
;
2364 basereg
= arm_reg_parse_multi (&p
);
2366 if (basereg
&& basereg
->type
!= basetype
)
2368 as_bad (_("bad type for register"));
2372 if (basereg
== NULL
)
2375 /* Try parsing as an integer. */
2376 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2377 if (exp
.X_op
!= O_constant
)
2379 as_bad (_("expression must be constant"));
2382 basereg
= &mybasereg
;
2383 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2389 typeinfo
= *basereg
->neon
;
2391 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2393 /* We got a type. */
2394 if (typeinfo
.defined
& NTA_HASTYPE
)
2396 as_bad (_("can't redefine the type of a register alias"));
2400 typeinfo
.defined
|= NTA_HASTYPE
;
2401 if (ntype
.elems
!= 1)
2403 as_bad (_("you must specify a single type only"));
2406 typeinfo
.eltype
= ntype
.el
[0];
2409 if (skip_past_char (&p
, '[') == SUCCESS
)
2412 /* We got a scalar index. */
2414 if (typeinfo
.defined
& NTA_HASINDEX
)
2416 as_bad (_("can't redefine the index of a scalar alias"));
2420 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2422 if (exp
.X_op
!= O_constant
)
2424 as_bad (_("scalar index must be constant"));
2428 typeinfo
.defined
|= NTA_HASINDEX
;
2429 typeinfo
.index
= exp
.X_add_number
;
2431 if (skip_past_char (&p
, ']') == FAIL
)
2433 as_bad (_("expecting ]"));
2438 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2439 the desired alias name, and p points to its end. If not, then
2440 the desired alias name is in the global original_case_string. */
2441 #ifdef TC_CASE_SENSITIVE
2442 namelen
= nameend
- newname
;
2444 newname
= original_case_string
;
2445 namelen
= strlen (newname
);
2448 namebuf
= xmemdup0 (newname
, namelen
);
2450 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2451 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2453 /* Insert name in all uppercase. */
2454 for (p
= namebuf
; *p
; p
++)
2457 if (strncmp (namebuf
, newname
, namelen
))
2458 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2459 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2461 /* Insert name in all lowercase. */
2462 for (p
= namebuf
; *p
; p
++)
2465 if (strncmp (namebuf
, newname
, namelen
))
2466 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2467 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2473 /* Should never be called, as .req goes between the alias and the
2474 register name, not at the beginning of the line. */
2477 s_req (int a ATTRIBUTE_UNUSED
)
2479 as_bad (_("invalid syntax for .req directive"));
2483 s_dn (int a ATTRIBUTE_UNUSED
)
2485 as_bad (_("invalid syntax for .dn directive"));
2489 s_qn (int a ATTRIBUTE_UNUSED
)
2491 as_bad (_("invalid syntax for .qn directive"));
2494 /* The .unreq directive deletes an alias which was previously defined
2495 by .req. For example:
2501 s_unreq (int a ATTRIBUTE_UNUSED
)
2506 name
= input_line_pointer
;
2508 while (*input_line_pointer
!= 0
2509 && *input_line_pointer
!= ' '
2510 && *input_line_pointer
!= '\n')
2511 ++input_line_pointer
;
2513 saved_char
= *input_line_pointer
;
2514 *input_line_pointer
= 0;
2517 as_bad (_("invalid syntax for .unreq directive"));
2520 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2524 as_bad (_("unknown register alias '%s'"), name
);
2525 else if (reg
->builtin
)
2526 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2533 hash_delete (arm_reg_hsh
, name
, FALSE
);
2534 free ((char *) reg
->name
);
2539 /* Also locate the all upper case and all lower case versions.
2540 Do not complain if we cannot find one or the other as it
2541 was probably deleted above. */
2543 nbuf
= strdup (name
);
2544 for (p
= nbuf
; *p
; p
++)
2546 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2549 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2550 free ((char *) reg
->name
);
2556 for (p
= nbuf
; *p
; p
++)
2558 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2561 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2562 free ((char *) reg
->name
);
2572 *input_line_pointer
= saved_char
;
2573 demand_empty_rest_of_line ();
2576 /* Directives: Instruction set selection. */
2579 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2580 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2581 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2582 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2584 /* Create a new mapping symbol for the transition to STATE. */
2587 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2590 const char * symname
;
2597 type
= BSF_NO_FLAGS
;
2601 type
= BSF_NO_FLAGS
;
2605 type
= BSF_NO_FLAGS
;
2611 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2612 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2617 THUMB_SET_FUNC (symbolP
, 0);
2618 ARM_SET_THUMB (symbolP
, 0);
2619 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2623 THUMB_SET_FUNC (symbolP
, 1);
2624 ARM_SET_THUMB (symbolP
, 1);
2625 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2633 /* Save the mapping symbols for future reference. Also check that
2634 we do not place two mapping symbols at the same offset within a
2635 frag. We'll handle overlap between frags in
2636 check_mapping_symbols.
2638 If .fill or other data filling directive generates zero sized data,
2639 the mapping symbol for the following code will have the same value
2640 as the one generated for the data filling directive. In this case,
2641 we replace the old symbol with the new one at the same address. */
2644 if (frag
->tc_frag_data
.first_map
!= NULL
)
2646 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2647 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2649 frag
->tc_frag_data
.first_map
= symbolP
;
2651 if (frag
->tc_frag_data
.last_map
!= NULL
)
2653 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2654 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2655 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2657 frag
->tc_frag_data
.last_map
= symbolP
;
2660 /* We must sometimes convert a region marked as code to data during
2661 code alignment, if an odd number of bytes have to be padded. The
2662 code mapping symbol is pushed to an aligned address. */
2665 insert_data_mapping_symbol (enum mstate state
,
2666 valueT value
, fragS
*frag
, offsetT bytes
)
2668 /* If there was already a mapping symbol, remove it. */
2669 if (frag
->tc_frag_data
.last_map
!= NULL
2670 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2672 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2676 know (frag
->tc_frag_data
.first_map
== symp
);
2677 frag
->tc_frag_data
.first_map
= NULL
;
2679 frag
->tc_frag_data
.last_map
= NULL
;
2680 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2683 make_mapping_symbol (MAP_DATA
, value
, frag
);
2684 make_mapping_symbol (state
, value
+ bytes
, frag
);
2687 static void mapping_state_2 (enum mstate state
, int max_chars
);
2689 /* Set the mapping state to STATE. Only call this when about to
2690 emit some STATE bytes to the file. */
2692 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2694 mapping_state (enum mstate state
)
2696 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2698 if (mapstate
== state
)
2699 /* The mapping symbol has already been emitted.
2700 There is nothing else to do. */
2703 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2705 All ARM instructions require 4-byte alignment.
2706 (Almost) all Thumb instructions require 2-byte alignment.
2708 When emitting instructions into any section, mark the section
2711 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2712 but themselves require 2-byte alignment; this applies to some
2713 PC- relative forms. However, these cases will invovle implicit
2714 literal pool generation or an explicit .align >=2, both of
2715 which will cause the section to me marked with sufficient
2716 alignment. Thus, we don't handle those cases here. */
2717 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2719 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2720 /* This case will be evaluated later. */
2723 mapping_state_2 (state
, 0);
2726 /* Same as mapping_state, but MAX_CHARS bytes have already been
2727 allocated. Put the mapping symbol that far back. */
2730 mapping_state_2 (enum mstate state
, int max_chars
)
2732 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2734 if (!SEG_NORMAL (now_seg
))
2737 if (mapstate
== state
)
2738 /* The mapping symbol has already been emitted.
2739 There is nothing else to do. */
2742 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2743 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2745 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2746 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2749 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2752 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2753 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2757 #define mapping_state(x) ((void)0)
2758 #define mapping_state_2(x, y) ((void)0)
2761 /* Find the real, Thumb encoded start of a Thumb function. */
2765 find_real_start (symbolS
* symbolP
)
2768 const char * name
= S_GET_NAME (symbolP
);
2769 symbolS
* new_target
;
2771 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2772 #define STUB_NAME ".real_start_of"
2777 /* The compiler may generate BL instructions to local labels because
2778 it needs to perform a branch to a far away location. These labels
2779 do not have a corresponding ".real_start_of" label. We check
2780 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2781 the ".real_start_of" convention for nonlocal branches. */
2782 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2785 real_start
= concat (STUB_NAME
, name
, NULL
);
2786 new_target
= symbol_find (real_start
);
2789 if (new_target
== NULL
)
2791 as_warn (_("Failed to find real start of function: %s\n"), name
);
2792 new_target
= symbolP
;
2800 opcode_select (int width
)
2807 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2808 as_bad (_("selected processor does not support THUMB opcodes"));
2811 /* No need to force the alignment, since we will have been
2812 coming from ARM mode, which is word-aligned. */
2813 record_alignment (now_seg
, 1);
2820 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2821 as_bad (_("selected processor does not support ARM opcodes"));
2826 frag_align (2, 0, 0);
2828 record_alignment (now_seg
, 1);
2833 as_bad (_("invalid instruction size selected (%d)"), width
);
2838 s_arm (int ignore ATTRIBUTE_UNUSED
)
2841 demand_empty_rest_of_line ();
2845 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2848 demand_empty_rest_of_line ();
2852 s_code (int unused ATTRIBUTE_UNUSED
)
2856 temp
= get_absolute_expression ();
2861 opcode_select (temp
);
2865 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2870 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2872 /* If we are not already in thumb mode go into it, EVEN if
2873 the target processor does not support thumb instructions.
2874 This is used by gcc/config/arm/lib1funcs.asm for example
2875 to compile interworking support functions even if the
2876 target processor should not support interworking. */
2880 record_alignment (now_seg
, 1);
2883 demand_empty_rest_of_line ();
2887 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2891 /* The following label is the name/address of the start of a Thumb function.
2892 We need to know this for the interworking support. */
2893 label_is_thumb_function_name
= TRUE
;
2896 /* Perform a .set directive, but also mark the alias as
2897 being a thumb function. */
2900 s_thumb_set (int equiv
)
2902 /* XXX the following is a duplicate of the code for s_set() in read.c
2903 We cannot just call that code as we need to get at the symbol that
2910 /* Especial apologies for the random logic:
2911 This just grew, and could be parsed much more simply!
2913 delim
= get_symbol_name (& name
);
2914 end_name
= input_line_pointer
;
2915 (void) restore_line_pointer (delim
);
2917 if (*input_line_pointer
!= ',')
2920 as_bad (_("expected comma after name \"%s\""), name
);
2922 ignore_rest_of_line ();
2926 input_line_pointer
++;
2929 if (name
[0] == '.' && name
[1] == '\0')
2931 /* XXX - this should not happen to .thumb_set. */
2935 if ((symbolP
= symbol_find (name
)) == NULL
2936 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2939 /* When doing symbol listings, play games with dummy fragments living
2940 outside the normal fragment chain to record the file and line info
2942 if (listing
& LISTING_SYMBOLS
)
2944 extern struct list_info_struct
* listing_tail
;
2945 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2947 memset (dummy_frag
, 0, sizeof (fragS
));
2948 dummy_frag
->fr_type
= rs_fill
;
2949 dummy_frag
->line
= listing_tail
;
2950 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2951 dummy_frag
->fr_symbol
= symbolP
;
2955 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2958 /* "set" symbols are local unless otherwise specified. */
2959 SF_SET_LOCAL (symbolP
);
2960 #endif /* OBJ_COFF */
2961 } /* Make a new symbol. */
2963 symbol_table_insert (symbolP
);
2968 && S_IS_DEFINED (symbolP
)
2969 && S_GET_SEGMENT (symbolP
) != reg_section
)
2970 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2972 pseudo_set (symbolP
);
2974 demand_empty_rest_of_line ();
2976 /* XXX Now we come to the Thumb specific bit of code. */
2978 THUMB_SET_FUNC (symbolP
, 1);
2979 ARM_SET_THUMB (symbolP
, 1);
2980 #if defined OBJ_ELF || defined OBJ_COFF
2981 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2985 /* Directives: Mode selection. */
2987 /* .syntax [unified|divided] - choose the new unified syntax
2988 (same for Arm and Thumb encoding, modulo slight differences in what
2989 can be represented) or the old divergent syntax for each mode. */
2991 s_syntax (int unused ATTRIBUTE_UNUSED
)
2995 delim
= get_symbol_name (& name
);
2997 if (!strcasecmp (name
, "unified"))
2998 unified_syntax
= TRUE
;
2999 else if (!strcasecmp (name
, "divided"))
3000 unified_syntax
= FALSE
;
3003 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3006 (void) restore_line_pointer (delim
);
3007 demand_empty_rest_of_line ();
3010 /* Directives: sectioning and alignment. */
3013 s_bss (int ignore ATTRIBUTE_UNUSED
)
3015 /* We don't support putting frags in the BSS segment, we fake it by
3016 marking in_bss, then looking at s_skip for clues. */
3017 subseg_set (bss_section
, 0);
3018 demand_empty_rest_of_line ();
3020 #ifdef md_elf_section_change_hook
3021 md_elf_section_change_hook ();
3026 s_even (int ignore ATTRIBUTE_UNUSED
)
3028 /* Never make frag if expect extra pass. */
3030 frag_align (1, 0, 0);
3032 record_alignment (now_seg
, 1);
3034 demand_empty_rest_of_line ();
3037 /* Directives: CodeComposer Studio. */
3039 /* .ref (for CodeComposer Studio syntax only). */
3041 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3043 if (codecomposer_syntax
)
3044 ignore_rest_of_line ();
3046 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3049 /* If name is not NULL, then it is used for marking the beginning of a
3050 function, whereas if it is NULL then it means the function end. */
3052 asmfunc_debug (const char * name
)
3054 static const char * last_name
= NULL
;
3058 gas_assert (last_name
== NULL
);
3061 if (debug_type
== DEBUG_STABS
)
3062 stabs_generate_asm_func (name
, name
);
3066 gas_assert (last_name
!= NULL
);
3068 if (debug_type
== DEBUG_STABS
)
3069 stabs_generate_asm_endfunc (last_name
, last_name
);
3076 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3078 if (codecomposer_syntax
)
3080 switch (asmfunc_state
)
3082 case OUTSIDE_ASMFUNC
:
3083 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3086 case WAITING_ASMFUNC_NAME
:
3087 as_bad (_(".asmfunc repeated."));
3090 case WAITING_ENDASMFUNC
:
3091 as_bad (_(".asmfunc without function."));
3094 demand_empty_rest_of_line ();
3097 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3101 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3103 if (codecomposer_syntax
)
3105 switch (asmfunc_state
)
3107 case OUTSIDE_ASMFUNC
:
3108 as_bad (_(".endasmfunc without a .asmfunc."));
3111 case WAITING_ASMFUNC_NAME
:
3112 as_bad (_(".endasmfunc without function."));
3115 case WAITING_ENDASMFUNC
:
3116 asmfunc_state
= OUTSIDE_ASMFUNC
;
3117 asmfunc_debug (NULL
);
3120 demand_empty_rest_of_line ();
3123 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3127 s_ccs_def (int name
)
3129 if (codecomposer_syntax
)
3132 as_bad (_(".def pseudo-op only available with -mccs flag."));
3135 /* Directives: Literal pools. */
3137 static literal_pool
*
3138 find_literal_pool (void)
3140 literal_pool
* pool
;
3142 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3144 if (pool
->section
== now_seg
3145 && pool
->sub_section
== now_subseg
)
3152 static literal_pool
*
3153 find_or_make_literal_pool (void)
3155 /* Next literal pool ID number. */
3156 static unsigned int latest_pool_num
= 1;
3157 literal_pool
* pool
;
3159 pool
= find_literal_pool ();
3163 /* Create a new pool. */
3164 pool
= XNEW (literal_pool
);
3168 pool
->next_free_entry
= 0;
3169 pool
->section
= now_seg
;
3170 pool
->sub_section
= now_subseg
;
3171 pool
->next
= list_of_pools
;
3172 pool
->symbol
= NULL
;
3173 pool
->alignment
= 2;
3175 /* Add it to the list. */
3176 list_of_pools
= pool
;
3179 /* New pools, and emptied pools, will have a NULL symbol. */
3180 if (pool
->symbol
== NULL
)
3182 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3183 (valueT
) 0, &zero_address_frag
);
3184 pool
->id
= latest_pool_num
++;
3191 /* Add the literal in the global 'inst'
3192 structure to the relevant literal pool. */
3195 add_to_lit_pool (unsigned int nbytes
)
3197 #define PADDING_SLOT 0x1
3198 #define LIT_ENTRY_SIZE_MASK 0xFF
3199 literal_pool
* pool
;
3200 unsigned int entry
, pool_size
= 0;
3201 bfd_boolean padding_slot_p
= FALSE
;
3207 imm1
= inst
.operands
[1].imm
;
3208 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3209 : inst
.reloc
.exp
.X_unsigned
? 0
3210 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3211 if (target_big_endian
)
3214 imm2
= inst
.operands
[1].imm
;
3218 pool
= find_or_make_literal_pool ();
3220 /* Check if this literal value is already in the pool. */
3221 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3225 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3226 && (inst
.reloc
.exp
.X_op
== O_constant
)
3227 && (pool
->literals
[entry
].X_add_number
3228 == inst
.reloc
.exp
.X_add_number
)
3229 && (pool
->literals
[entry
].X_md
== nbytes
)
3230 && (pool
->literals
[entry
].X_unsigned
3231 == inst
.reloc
.exp
.X_unsigned
))
3234 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3235 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3236 && (pool
->literals
[entry
].X_add_number
3237 == inst
.reloc
.exp
.X_add_number
)
3238 && (pool
->literals
[entry
].X_add_symbol
3239 == inst
.reloc
.exp
.X_add_symbol
)
3240 && (pool
->literals
[entry
].X_op_symbol
3241 == inst
.reloc
.exp
.X_op_symbol
)
3242 && (pool
->literals
[entry
].X_md
== nbytes
))
3245 else if ((nbytes
== 8)
3246 && !(pool_size
& 0x7)
3247 && ((entry
+ 1) != pool
->next_free_entry
)
3248 && (pool
->literals
[entry
].X_op
== O_constant
)
3249 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3250 && (pool
->literals
[entry
].X_unsigned
3251 == inst
.reloc
.exp
.X_unsigned
)
3252 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3253 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3254 && (pool
->literals
[entry
+ 1].X_unsigned
3255 == inst
.reloc
.exp
.X_unsigned
))
3258 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3259 if (padding_slot_p
&& (nbytes
== 4))
3265 /* Do we need to create a new entry? */
3266 if (entry
== pool
->next_free_entry
)
3268 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3270 inst
.error
= _("literal pool overflow");
3276 /* For 8-byte entries, we align to an 8-byte boundary,
3277 and split it into two 4-byte entries, because on 32-bit
3278 host, 8-byte constants are treated as big num, thus
3279 saved in "generic_bignum" which will be overwritten
3280 by later assignments.
3282 We also need to make sure there is enough space for
3285 We also check to make sure the literal operand is a
3287 if (!(inst
.reloc
.exp
.X_op
== O_constant
3288 || inst
.reloc
.exp
.X_op
== O_big
))
3290 inst
.error
= _("invalid type for literal pool");
3293 else if (pool_size
& 0x7)
3295 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3297 inst
.error
= _("literal pool overflow");
3301 pool
->literals
[entry
] = inst
.reloc
.exp
;
3302 pool
->literals
[entry
].X_op
= O_constant
;
3303 pool
->literals
[entry
].X_add_number
= 0;
3304 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3305 pool
->next_free_entry
+= 1;
3308 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3310 inst
.error
= _("literal pool overflow");
3314 pool
->literals
[entry
] = inst
.reloc
.exp
;
3315 pool
->literals
[entry
].X_op
= O_constant
;
3316 pool
->literals
[entry
].X_add_number
= imm1
;
3317 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3318 pool
->literals
[entry
++].X_md
= 4;
3319 pool
->literals
[entry
] = inst
.reloc
.exp
;
3320 pool
->literals
[entry
].X_op
= O_constant
;
3321 pool
->literals
[entry
].X_add_number
= imm2
;
3322 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3323 pool
->literals
[entry
].X_md
= 4;
3324 pool
->alignment
= 3;
3325 pool
->next_free_entry
+= 1;
3329 pool
->literals
[entry
] = inst
.reloc
.exp
;
3330 pool
->literals
[entry
].X_md
= 4;
3334 /* PR ld/12974: Record the location of the first source line to reference
3335 this entry in the literal pool. If it turns out during linking that the
3336 symbol does not exist we will be able to give an accurate line number for
3337 the (first use of the) missing reference. */
3338 if (debug_type
== DEBUG_DWARF2
)
3339 dwarf2_where (pool
->locs
+ entry
);
3341 pool
->next_free_entry
+= 1;
3343 else if (padding_slot_p
)
3345 pool
->literals
[entry
] = inst
.reloc
.exp
;
3346 pool
->literals
[entry
].X_md
= nbytes
;
3349 inst
.reloc
.exp
.X_op
= O_symbol
;
3350 inst
.reloc
.exp
.X_add_number
= pool_size
;
3351 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3357 tc_start_label_without_colon (void)
3359 bfd_boolean ret
= TRUE
;
3361 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3363 const char *label
= input_line_pointer
;
3365 while (!is_end_of_line
[(int) label
[-1]])
3370 as_bad (_("Invalid label '%s'"), label
);
3374 asmfunc_debug (label
);
3376 asmfunc_state
= WAITING_ENDASMFUNC
;
3382 /* Can't use symbol_new here, so have to create a symbol and then at
3383 a later date assign it a value. Thats what these functions do. */
3386 symbol_locate (symbolS
* symbolP
,
3387 const char * name
, /* It is copied, the caller can modify. */
3388 segT segment
, /* Segment identifier (SEG_<something>). */
3389 valueT valu
, /* Symbol value. */
3390 fragS
* frag
) /* Associated fragment. */
3393 char * preserved_copy_of_name
;
3395 name_length
= strlen (name
) + 1; /* +1 for \0. */
3396 obstack_grow (¬es
, name
, name_length
);
3397 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3399 #ifdef tc_canonicalize_symbol_name
3400 preserved_copy_of_name
=
3401 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3404 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3406 S_SET_SEGMENT (symbolP
, segment
);
3407 S_SET_VALUE (symbolP
, valu
);
3408 symbol_clear_list_pointers (symbolP
);
3410 symbol_set_frag (symbolP
, frag
);
3412 /* Link to end of symbol chain. */
3414 extern int symbol_table_frozen
;
3416 if (symbol_table_frozen
)
3420 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3422 obj_symbol_new_hook (symbolP
);
3424 #ifdef tc_symbol_new_hook
3425 tc_symbol_new_hook (symbolP
);
3429 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3430 #endif /* DEBUG_SYMS */
3434 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3437 literal_pool
* pool
;
3440 pool
= find_literal_pool ();
3442 || pool
->symbol
== NULL
3443 || pool
->next_free_entry
== 0)
3446 /* Align pool as you have word accesses.
3447 Only make a frag if we have to. */
3449 frag_align (pool
->alignment
, 0, 0);
3451 record_alignment (now_seg
, 2);
3454 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3455 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3457 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3459 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3460 (valueT
) frag_now_fix (), frag_now
);
3461 symbol_table_insert (pool
->symbol
);
3463 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3465 #if defined OBJ_COFF || defined OBJ_ELF
3466 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3469 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3472 if (debug_type
== DEBUG_DWARF2
)
3473 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3475 /* First output the expression in the instruction to the pool. */
3476 emit_expr (&(pool
->literals
[entry
]),
3477 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3480 /* Mark the pool as empty. */
3481 pool
->next_free_entry
= 0;
3482 pool
->symbol
= NULL
;
3486 /* Forward declarations for functions below, in the MD interface
3488 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3489 static valueT
create_unwind_entry (int);
3490 static void start_unwind_section (const segT
, int);
3491 static void add_unwind_opcode (valueT
, int);
3492 static void flush_pending_unwind (void);
3494 /* Directives: Data. */
3497 s_arm_elf_cons (int nbytes
)
3501 #ifdef md_flush_pending_output
3502 md_flush_pending_output ();
3505 if (is_it_end_of_statement ())
3507 demand_empty_rest_of_line ();
3511 #ifdef md_cons_align
3512 md_cons_align (nbytes
);
3515 mapping_state (MAP_DATA
);
3519 char *base
= input_line_pointer
;
3523 if (exp
.X_op
!= O_symbol
)
3524 emit_expr (&exp
, (unsigned int) nbytes
);
3527 char *before_reloc
= input_line_pointer
;
3528 reloc
= parse_reloc (&input_line_pointer
);
3531 as_bad (_("unrecognized relocation suffix"));
3532 ignore_rest_of_line ();
3535 else if (reloc
== BFD_RELOC_UNUSED
)
3536 emit_expr (&exp
, (unsigned int) nbytes
);
3539 reloc_howto_type
*howto
= (reloc_howto_type
*)
3540 bfd_reloc_type_lookup (stdoutput
,
3541 (bfd_reloc_code_real_type
) reloc
);
3542 int size
= bfd_get_reloc_size (howto
);
3544 if (reloc
== BFD_RELOC_ARM_PLT32
)
3546 as_bad (_("(plt) is only valid on branch targets"));
3547 reloc
= BFD_RELOC_UNUSED
;
3552 as_bad (_("%s relocations do not fit in %d bytes"),
3553 howto
->name
, nbytes
);
3556 /* We've parsed an expression stopping at O_symbol.
3557 But there may be more expression left now that we
3558 have parsed the relocation marker. Parse it again.
3559 XXX Surely there is a cleaner way to do this. */
3560 char *p
= input_line_pointer
;
3562 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3564 memcpy (save_buf
, base
, input_line_pointer
- base
);
3565 memmove (base
+ (input_line_pointer
- before_reloc
),
3566 base
, before_reloc
- base
);
3568 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3570 memcpy (base
, save_buf
, p
- base
);
3572 offset
= nbytes
- size
;
3573 p
= frag_more (nbytes
);
3574 memset (p
, 0, nbytes
);
3575 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3576 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3582 while (*input_line_pointer
++ == ',');
3584 /* Put terminator back into stream. */
3585 input_line_pointer
--;
3586 demand_empty_rest_of_line ();
3589 /* Emit an expression containing a 32-bit thumb instruction.
3590 Implementation based on put_thumb32_insn. */
3593 emit_thumb32_expr (expressionS
* exp
)
3595 expressionS exp_high
= *exp
;
3597 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3598 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3599 exp
->X_add_number
&= 0xffff;
3600 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3603 /* Guess the instruction size based on the opcode. */
3606 thumb_insn_size (int opcode
)
3608 if ((unsigned int) opcode
< 0xe800u
)
3610 else if ((unsigned int) opcode
>= 0xe8000000u
)
3617 emit_insn (expressionS
*exp
, int nbytes
)
3621 if (exp
->X_op
== O_constant
)
3626 size
= thumb_insn_size (exp
->X_add_number
);
3630 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3632 as_bad (_(".inst.n operand too big. "\
3633 "Use .inst.w instead"));
3638 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3639 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3641 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3643 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3644 emit_thumb32_expr (exp
);
3646 emit_expr (exp
, (unsigned int) size
);
3648 it_fsm_post_encode ();
3652 as_bad (_("cannot determine Thumb instruction size. " \
3653 "Use .inst.n/.inst.w instead"));
3656 as_bad (_("constant expression required"));
3661 /* Like s_arm_elf_cons but do not use md_cons_align and
3662 set the mapping state to MAP_ARM/MAP_THUMB. */
3665 s_arm_elf_inst (int nbytes
)
3667 if (is_it_end_of_statement ())
3669 demand_empty_rest_of_line ();
3673 /* Calling mapping_state () here will not change ARM/THUMB,
3674 but will ensure not to be in DATA state. */
3677 mapping_state (MAP_THUMB
);
3682 as_bad (_("width suffixes are invalid in ARM mode"));
3683 ignore_rest_of_line ();
3689 mapping_state (MAP_ARM
);
3698 if (! emit_insn (& exp
, nbytes
))
3700 ignore_rest_of_line ();
3704 while (*input_line_pointer
++ == ',');
3706 /* Put terminator back into stream. */
3707 input_line_pointer
--;
3708 demand_empty_rest_of_line ();
3711 /* Parse a .rel31 directive. */
3714 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3721 if (*input_line_pointer
== '1')
3722 highbit
= 0x80000000;
3723 else if (*input_line_pointer
!= '0')
3724 as_bad (_("expected 0 or 1"));
3726 input_line_pointer
++;
3727 if (*input_line_pointer
!= ',')
3728 as_bad (_("missing comma"));
3729 input_line_pointer
++;
3731 #ifdef md_flush_pending_output
3732 md_flush_pending_output ();
3735 #ifdef md_cons_align
3739 mapping_state (MAP_DATA
);
3744 md_number_to_chars (p
, highbit
, 4);
3745 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3746 BFD_RELOC_ARM_PREL31
);
3748 demand_empty_rest_of_line ();
3751 /* Directives: AEABI stack-unwind tables. */
3753 /* Parse an unwind_fnstart directive. Simply records the current location. */
3756 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3758 demand_empty_rest_of_line ();
3759 if (unwind
.proc_start
)
3761 as_bad (_("duplicate .fnstart directive"));
3765 /* Mark the start of the function. */
3766 unwind
.proc_start
= expr_build_dot ();
3768 /* Reset the rest of the unwind info. */
3769 unwind
.opcode_count
= 0;
3770 unwind
.table_entry
= NULL
;
3771 unwind
.personality_routine
= NULL
;
3772 unwind
.personality_index
= -1;
3773 unwind
.frame_size
= 0;
3774 unwind
.fp_offset
= 0;
3775 unwind
.fp_reg
= REG_SP
;
3777 unwind
.sp_restored
= 0;
3781 /* Parse a handlerdata directive. Creates the exception handling table entry
3782 for the function. */
3785 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3787 demand_empty_rest_of_line ();
3788 if (!unwind
.proc_start
)
3789 as_bad (MISSING_FNSTART
);
3791 if (unwind
.table_entry
)
3792 as_bad (_("duplicate .handlerdata directive"));
3794 create_unwind_entry (1);
3797 /* Parse an unwind_fnend directive. Generates the index table entry. */
3800 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3805 unsigned int marked_pr_dependency
;
3807 demand_empty_rest_of_line ();
3809 if (!unwind
.proc_start
)
3811 as_bad (_(".fnend directive without .fnstart"));
3815 /* Add eh table entry. */
3816 if (unwind
.table_entry
== NULL
)
3817 val
= create_unwind_entry (0);
3821 /* Add index table entry. This is two words. */
3822 start_unwind_section (unwind
.saved_seg
, 1);
3823 frag_align (2, 0, 0);
3824 record_alignment (now_seg
, 2);
3826 ptr
= frag_more (8);
3828 where
= frag_now_fix () - 8;
3830 /* Self relative offset of the function start. */
3831 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3832 BFD_RELOC_ARM_PREL31
);
3834 /* Indicate dependency on EHABI-defined personality routines to the
3835 linker, if it hasn't been done already. */
3836 marked_pr_dependency
3837 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3838 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3839 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3841 static const char *const name
[] =
3843 "__aeabi_unwind_cpp_pr0",
3844 "__aeabi_unwind_cpp_pr1",
3845 "__aeabi_unwind_cpp_pr2"
3847 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3848 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3849 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3850 |= 1 << unwind
.personality_index
;
3854 /* Inline exception table entry. */
3855 md_number_to_chars (ptr
+ 4, val
, 4);
3857 /* Self relative offset of the table entry. */
3858 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3859 BFD_RELOC_ARM_PREL31
);
3861 /* Restore the original section. */
3862 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3864 unwind
.proc_start
= NULL
;
3868 /* Parse an unwind_cantunwind directive. */
3871 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3873 demand_empty_rest_of_line ();
3874 if (!unwind
.proc_start
)
3875 as_bad (MISSING_FNSTART
);
3877 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3878 as_bad (_("personality routine specified for cantunwind frame"));
3880 unwind
.personality_index
= -2;
3884 /* Parse a personalityindex directive. */
3887 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3891 if (!unwind
.proc_start
)
3892 as_bad (MISSING_FNSTART
);
3894 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3895 as_bad (_("duplicate .personalityindex directive"));
3899 if (exp
.X_op
!= O_constant
3900 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3902 as_bad (_("bad personality routine number"));
3903 ignore_rest_of_line ();
3907 unwind
.personality_index
= exp
.X_add_number
;
3909 demand_empty_rest_of_line ();
3913 /* Parse a personality directive. */
3916 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3920 if (!unwind
.proc_start
)
3921 as_bad (MISSING_FNSTART
);
3923 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3924 as_bad (_("duplicate .personality directive"));
3926 c
= get_symbol_name (& name
);
3927 p
= input_line_pointer
;
3929 ++ input_line_pointer
;
3930 unwind
.personality_routine
= symbol_find_or_make (name
);
3932 demand_empty_rest_of_line ();
3936 /* Parse a directive saving core registers. */
3939 s_arm_unwind_save_core (void)
3945 range
= parse_reg_list (&input_line_pointer
);
3948 as_bad (_("expected register list"));
3949 ignore_rest_of_line ();
3953 demand_empty_rest_of_line ();
3955 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3956 into .unwind_save {..., sp...}. We aren't bothered about the value of
3957 ip because it is clobbered by calls. */
3958 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3959 && (range
& 0x3000) == 0x1000)
3961 unwind
.opcode_count
--;
3962 unwind
.sp_restored
= 0;
3963 range
= (range
| 0x2000) & ~0x1000;
3964 unwind
.pending_offset
= 0;
3970 /* See if we can use the short opcodes. These pop a block of up to 8
3971 registers starting with r4, plus maybe r14. */
3972 for (n
= 0; n
< 8; n
++)
3974 /* Break at the first non-saved register. */
3975 if ((range
& (1 << (n
+ 4))) == 0)
3978 /* See if there are any other bits set. */
3979 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3981 /* Use the long form. */
3982 op
= 0x8000 | ((range
>> 4) & 0xfff);
3983 add_unwind_opcode (op
, 2);
3987 /* Use the short form. */
3989 op
= 0xa8; /* Pop r14. */
3991 op
= 0xa0; /* Do not pop r14. */
3993 add_unwind_opcode (op
, 1);
4000 op
= 0xb100 | (range
& 0xf);
4001 add_unwind_opcode (op
, 2);
4004 /* Record the number of bytes pushed. */
4005 for (n
= 0; n
< 16; n
++)
4007 if (range
& (1 << n
))
4008 unwind
.frame_size
+= 4;
4013 /* Parse a directive saving FPA registers. */
4016 s_arm_unwind_save_fpa (int reg
)
4022 /* Get Number of registers to transfer. */
4023 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4026 exp
.X_op
= O_illegal
;
4028 if (exp
.X_op
!= O_constant
)
4030 as_bad (_("expected , <constant>"));
4031 ignore_rest_of_line ();
4035 num_regs
= exp
.X_add_number
;
4037 if (num_regs
< 1 || num_regs
> 4)
4039 as_bad (_("number of registers must be in the range [1:4]"));
4040 ignore_rest_of_line ();
4044 demand_empty_rest_of_line ();
4049 op
= 0xb4 | (num_regs
- 1);
4050 add_unwind_opcode (op
, 1);
4055 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4056 add_unwind_opcode (op
, 2);
4058 unwind
.frame_size
+= num_regs
* 12;
4062 /* Parse a directive saving VFP registers for ARMv6 and above. */
4065 s_arm_unwind_save_vfp_armv6 (void)
4070 int num_vfpv3_regs
= 0;
4071 int num_regs_below_16
;
4073 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4076 as_bad (_("expected register list"));
4077 ignore_rest_of_line ();
4081 demand_empty_rest_of_line ();
4083 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4084 than FSTMX/FLDMX-style ones). */
4086 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4088 num_vfpv3_regs
= count
;
4089 else if (start
+ count
> 16)
4090 num_vfpv3_regs
= start
+ count
- 16;
4092 if (num_vfpv3_regs
> 0)
4094 int start_offset
= start
> 16 ? start
- 16 : 0;
4095 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4096 add_unwind_opcode (op
, 2);
4099 /* Generate opcode for registers numbered in the range 0 .. 15. */
4100 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4101 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4102 if (num_regs_below_16
> 0)
4104 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4105 add_unwind_opcode (op
, 2);
4108 unwind
.frame_size
+= count
* 8;
4112 /* Parse a directive saving VFP registers for pre-ARMv6. */
4115 s_arm_unwind_save_vfp (void)
4121 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4124 as_bad (_("expected register list"));
4125 ignore_rest_of_line ();
4129 demand_empty_rest_of_line ();
4134 op
= 0xb8 | (count
- 1);
4135 add_unwind_opcode (op
, 1);
4140 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4141 add_unwind_opcode (op
, 2);
4143 unwind
.frame_size
+= count
* 8 + 4;
4147 /* Parse a directive saving iWMMXt data registers. */
4150 s_arm_unwind_save_mmxwr (void)
4158 if (*input_line_pointer
== '{')
4159 input_line_pointer
++;
4163 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4167 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4172 as_tsktsk (_("register list not in ascending order"));
4175 if (*input_line_pointer
== '-')
4177 input_line_pointer
++;
4178 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4181 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4184 else if (reg
>= hi_reg
)
4186 as_bad (_("bad register range"));
4189 for (; reg
< hi_reg
; reg
++)
4193 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4195 skip_past_char (&input_line_pointer
, '}');
4197 demand_empty_rest_of_line ();
4199 /* Generate any deferred opcodes because we're going to be looking at
4201 flush_pending_unwind ();
4203 for (i
= 0; i
< 16; i
++)
4205 if (mask
& (1 << i
))
4206 unwind
.frame_size
+= 8;
4209 /* Attempt to combine with a previous opcode. We do this because gcc
4210 likes to output separate unwind directives for a single block of
4212 if (unwind
.opcode_count
> 0)
4214 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4215 if ((i
& 0xf8) == 0xc0)
4218 /* Only merge if the blocks are contiguous. */
4221 if ((mask
& 0xfe00) == (1 << 9))
4223 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4224 unwind
.opcode_count
--;
4227 else if (i
== 6 && unwind
.opcode_count
>= 2)
4229 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4233 op
= 0xffff << (reg
- 1);
4235 && ((mask
& op
) == (1u << (reg
- 1))))
4237 op
= (1 << (reg
+ i
+ 1)) - 1;
4238 op
&= ~((1 << reg
) - 1);
4240 unwind
.opcode_count
-= 2;
4247 /* We want to generate opcodes in the order the registers have been
4248 saved, ie. descending order. */
4249 for (reg
= 15; reg
>= -1; reg
--)
4251 /* Save registers in blocks. */
4253 || !(mask
& (1 << reg
)))
4255 /* We found an unsaved reg. Generate opcodes to save the
4262 op
= 0xc0 | (hi_reg
- 10);
4263 add_unwind_opcode (op
, 1);
4268 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4269 add_unwind_opcode (op
, 2);
4278 ignore_rest_of_line ();
4282 s_arm_unwind_save_mmxwcg (void)
4289 if (*input_line_pointer
== '{')
4290 input_line_pointer
++;
4292 skip_whitespace (input_line_pointer
);
4296 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4300 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4306 as_tsktsk (_("register list not in ascending order"));
4309 if (*input_line_pointer
== '-')
4311 input_line_pointer
++;
4312 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4315 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4318 else if (reg
>= hi_reg
)
4320 as_bad (_("bad register range"));
4323 for (; reg
< hi_reg
; reg
++)
4327 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4329 skip_past_char (&input_line_pointer
, '}');
4331 demand_empty_rest_of_line ();
4333 /* Generate any deferred opcodes because we're going to be looking at
4335 flush_pending_unwind ();
4337 for (reg
= 0; reg
< 16; reg
++)
4339 if (mask
& (1 << reg
))
4340 unwind
.frame_size
+= 4;
4343 add_unwind_opcode (op
, 2);
4346 ignore_rest_of_line ();
4350 /* Parse an unwind_save directive.
4351 If the argument is non-zero, this is a .vsave directive. */
4354 s_arm_unwind_save (int arch_v6
)
4357 struct reg_entry
*reg
;
4358 bfd_boolean had_brace
= FALSE
;
4360 if (!unwind
.proc_start
)
4361 as_bad (MISSING_FNSTART
);
4363 /* Figure out what sort of save we have. */
4364 peek
= input_line_pointer
;
4372 reg
= arm_reg_parse_multi (&peek
);
4376 as_bad (_("register expected"));
4377 ignore_rest_of_line ();
4386 as_bad (_("FPA .unwind_save does not take a register list"));
4387 ignore_rest_of_line ();
4390 input_line_pointer
= peek
;
4391 s_arm_unwind_save_fpa (reg
->number
);
4395 s_arm_unwind_save_core ();
4400 s_arm_unwind_save_vfp_armv6 ();
4402 s_arm_unwind_save_vfp ();
4405 case REG_TYPE_MMXWR
:
4406 s_arm_unwind_save_mmxwr ();
4409 case REG_TYPE_MMXWCG
:
4410 s_arm_unwind_save_mmxwcg ();
4414 as_bad (_(".unwind_save does not support this kind of register"));
4415 ignore_rest_of_line ();
4420 /* Parse an unwind_movsp directive. */
4423 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4429 if (!unwind
.proc_start
)
4430 as_bad (MISSING_FNSTART
);
4432 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4435 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4436 ignore_rest_of_line ();
4440 /* Optional constant. */
4441 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4443 if (immediate_for_directive (&offset
) == FAIL
)
4449 demand_empty_rest_of_line ();
4451 if (reg
== REG_SP
|| reg
== REG_PC
)
4453 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4457 if (unwind
.fp_reg
!= REG_SP
)
4458 as_bad (_("unexpected .unwind_movsp directive"));
4460 /* Generate opcode to restore the value. */
4462 add_unwind_opcode (op
, 1);
4464 /* Record the information for later. */
4465 unwind
.fp_reg
= reg
;
4466 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4467 unwind
.sp_restored
= 1;
4470 /* Parse an unwind_pad directive. */
4473 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4477 if (!unwind
.proc_start
)
4478 as_bad (MISSING_FNSTART
);
4480 if (immediate_for_directive (&offset
) == FAIL
)
4485 as_bad (_("stack increment must be multiple of 4"));
4486 ignore_rest_of_line ();
4490 /* Don't generate any opcodes, just record the details for later. */
4491 unwind
.frame_size
+= offset
;
4492 unwind
.pending_offset
+= offset
;
4494 demand_empty_rest_of_line ();
4497 /* Parse an unwind_setfp directive. */
4500 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4506 if (!unwind
.proc_start
)
4507 as_bad (MISSING_FNSTART
);
4509 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4510 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4513 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4515 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4517 as_bad (_("expected <reg>, <reg>"));
4518 ignore_rest_of_line ();
4522 /* Optional constant. */
4523 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4525 if (immediate_for_directive (&offset
) == FAIL
)
4531 demand_empty_rest_of_line ();
4533 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4535 as_bad (_("register must be either sp or set by a previous"
4536 "unwind_movsp directive"));
4540 /* Don't generate any opcodes, just record the information for later. */
4541 unwind
.fp_reg
= fp_reg
;
4543 if (sp_reg
== REG_SP
)
4544 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4546 unwind
.fp_offset
-= offset
;
4549 /* Parse an unwind_raw directive. */
4552 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4555 /* This is an arbitrary limit. */
4556 unsigned char op
[16];
4559 if (!unwind
.proc_start
)
4560 as_bad (MISSING_FNSTART
);
4563 if (exp
.X_op
== O_constant
4564 && skip_past_comma (&input_line_pointer
) != FAIL
)
4566 unwind
.frame_size
+= exp
.X_add_number
;
4570 exp
.X_op
= O_illegal
;
4572 if (exp
.X_op
!= O_constant
)
4574 as_bad (_("expected <offset>, <opcode>"));
4575 ignore_rest_of_line ();
4581 /* Parse the opcode. */
4586 as_bad (_("unwind opcode too long"));
4587 ignore_rest_of_line ();
4589 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4591 as_bad (_("invalid unwind opcode"));
4592 ignore_rest_of_line ();
4595 op
[count
++] = exp
.X_add_number
;
4597 /* Parse the next byte. */
4598 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4604 /* Add the opcode bytes in reverse order. */
4606 add_unwind_opcode (op
[count
], 1);
4608 demand_empty_rest_of_line ();
4612 /* Parse a .eabi_attribute directive. */
4615 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4617 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4619 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4620 attributes_set_explicitly
[tag
] = 1;
4623 /* Emit a tls fix for the symbol. */
4626 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4630 #ifdef md_flush_pending_output
4631 md_flush_pending_output ();
4634 #ifdef md_cons_align
4638 /* Since we're just labelling the code, there's no need to define a
4641 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4642 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4643 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4644 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4646 #endif /* OBJ_ELF */
4648 static void s_arm_arch (int);
4649 static void s_arm_object_arch (int);
4650 static void s_arm_cpu (int);
4651 static void s_arm_fpu (int);
4652 static void s_arm_arch_extension (int);
4657 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4664 if (exp
.X_op
== O_symbol
)
4665 exp
.X_op
= O_secrel
;
4667 emit_expr (&exp
, 4);
4669 while (*input_line_pointer
++ == ',');
4671 input_line_pointer
--;
4672 demand_empty_rest_of_line ();
4676 /* This table describes all the machine specific pseudo-ops the assembler
4677 has to support. The fields are:
4678 pseudo-op name without dot
4679 function to call to execute this pseudo-op
4680 Integer arg to pass to the function. */
4682 const pseudo_typeS md_pseudo_table
[] =
4684 /* Never called because '.req' does not start a line. */
4685 { "req", s_req
, 0 },
4686 /* Following two are likewise never called. */
4689 { "unreq", s_unreq
, 0 },
4690 { "bss", s_bss
, 0 },
4691 { "align", s_align_ptwo
, 2 },
4692 { "arm", s_arm
, 0 },
4693 { "thumb", s_thumb
, 0 },
4694 { "code", s_code
, 0 },
4695 { "force_thumb", s_force_thumb
, 0 },
4696 { "thumb_func", s_thumb_func
, 0 },
4697 { "thumb_set", s_thumb_set
, 0 },
4698 { "even", s_even
, 0 },
4699 { "ltorg", s_ltorg
, 0 },
4700 { "pool", s_ltorg
, 0 },
4701 { "syntax", s_syntax
, 0 },
4702 { "cpu", s_arm_cpu
, 0 },
4703 { "arch", s_arm_arch
, 0 },
4704 { "object_arch", s_arm_object_arch
, 0 },
4705 { "fpu", s_arm_fpu
, 0 },
4706 { "arch_extension", s_arm_arch_extension
, 0 },
4708 { "word", s_arm_elf_cons
, 4 },
4709 { "long", s_arm_elf_cons
, 4 },
4710 { "inst.n", s_arm_elf_inst
, 2 },
4711 { "inst.w", s_arm_elf_inst
, 4 },
4712 { "inst", s_arm_elf_inst
, 0 },
4713 { "rel31", s_arm_rel31
, 0 },
4714 { "fnstart", s_arm_unwind_fnstart
, 0 },
4715 { "fnend", s_arm_unwind_fnend
, 0 },
4716 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4717 { "personality", s_arm_unwind_personality
, 0 },
4718 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4719 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4720 { "save", s_arm_unwind_save
, 0 },
4721 { "vsave", s_arm_unwind_save
, 1 },
4722 { "movsp", s_arm_unwind_movsp
, 0 },
4723 { "pad", s_arm_unwind_pad
, 0 },
4724 { "setfp", s_arm_unwind_setfp
, 0 },
4725 { "unwind_raw", s_arm_unwind_raw
, 0 },
4726 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4727 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4731 /* These are used for dwarf. */
4735 /* These are used for dwarf2. */
4736 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4737 { "loc", dwarf2_directive_loc
, 0 },
4738 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4740 { "extend", float_cons
, 'x' },
4741 { "ldouble", float_cons
, 'x' },
4742 { "packed", float_cons
, 'p' },
4744 {"secrel32", pe_directive_secrel
, 0},
4747 /* These are for compatibility with CodeComposer Studio. */
4748 {"ref", s_ccs_ref
, 0},
4749 {"def", s_ccs_def
, 0},
4750 {"asmfunc", s_ccs_asmfunc
, 0},
4751 {"endasmfunc", s_ccs_endasmfunc
, 0},
4756 /* Parser functions used exclusively in instruction operands. */
4758 /* Generic immediate-value read function for use in insn parsing.
4759 STR points to the beginning of the immediate (the leading #);
4760 VAL receives the value; if the value is outside [MIN, MAX]
4761 issue an error. PREFIX_OPT is true if the immediate prefix is
4765 parse_immediate (char **str
, int *val
, int min
, int max
,
4766 bfd_boolean prefix_opt
)
4769 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4770 if (exp
.X_op
!= O_constant
)
4772 inst
.error
= _("constant expression required");
4776 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4778 inst
.error
= _("immediate value out of range");
4782 *val
= exp
.X_add_number
;
4786 /* Less-generic immediate-value read function with the possibility of loading a
4787 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4788 instructions. Puts the result directly in inst.operands[i]. */
4791 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4792 bfd_boolean allow_symbol_p
)
4795 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4798 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4800 if (exp_p
->X_op
== O_constant
)
4802 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4803 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4804 O_constant. We have to be careful not to break compilation for
4805 32-bit X_add_number, though. */
4806 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4808 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4809 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4811 inst
.operands
[i
].regisimm
= 1;
4814 else if (exp_p
->X_op
== O_big
4815 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4817 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4819 /* Bignums have their least significant bits in
4820 generic_bignum[0]. Make sure we put 32 bits in imm and
4821 32 bits in reg, in a (hopefully) portable way. */
4822 gas_assert (parts
!= 0);
4824 /* Make sure that the number is not too big.
4825 PR 11972: Bignums can now be sign-extended to the
4826 size of a .octa so check that the out of range bits
4827 are all zero or all one. */
4828 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4830 LITTLENUM_TYPE m
= -1;
4832 if (generic_bignum
[parts
* 2] != 0
4833 && generic_bignum
[parts
* 2] != m
)
4836 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4837 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4841 inst
.operands
[i
].imm
= 0;
4842 for (j
= 0; j
< parts
; j
++, idx
++)
4843 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4844 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4845 inst
.operands
[i
].reg
= 0;
4846 for (j
= 0; j
< parts
; j
++, idx
++)
4847 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4848 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4849 inst
.operands
[i
].regisimm
= 1;
4851 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4859 /* Returns the pseudo-register number of an FPA immediate constant,
4860 or FAIL if there isn't a valid constant here. */
4863 parse_fpa_immediate (char ** str
)
4865 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4871 /* First try and match exact strings, this is to guarantee
4872 that some formats will work even for cross assembly. */
4874 for (i
= 0; fp_const
[i
]; i
++)
4876 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4880 *str
+= strlen (fp_const
[i
]);
4881 if (is_end_of_line
[(unsigned char) **str
])
4887 /* Just because we didn't get a match doesn't mean that the constant
4888 isn't valid, just that it is in a format that we don't
4889 automatically recognize. Try parsing it with the standard
4890 expression routines. */
4892 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4894 /* Look for a raw floating point number. */
4895 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4896 && is_end_of_line
[(unsigned char) *save_in
])
4898 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4900 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4902 if (words
[j
] != fp_values
[i
][j
])
4906 if (j
== MAX_LITTLENUMS
)
4914 /* Try and parse a more complex expression, this will probably fail
4915 unless the code uses a floating point prefix (eg "0f"). */
4916 save_in
= input_line_pointer
;
4917 input_line_pointer
= *str
;
4918 if (expression (&exp
) == absolute_section
4919 && exp
.X_op
== O_big
4920 && exp
.X_add_number
< 0)
4922 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4924 #define X_PRECISION 5
4925 #define E_PRECISION 15L
4926 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4928 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4930 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4932 if (words
[j
] != fp_values
[i
][j
])
4936 if (j
== MAX_LITTLENUMS
)
4938 *str
= input_line_pointer
;
4939 input_line_pointer
= save_in
;
4946 *str
= input_line_pointer
;
4947 input_line_pointer
= save_in
;
4948 inst
.error
= _("invalid FPA immediate expression");
4952 /* Returns 1 if a number has "quarter-precision" float format
4953 0baBbbbbbc defgh000 00000000 00000000. */
4956 is_quarter_float (unsigned imm
)
4958 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4959 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4963 /* Detect the presence of a floating point or integer zero constant,
4967 parse_ifimm_zero (char **in
)
4971 if (!is_immediate_prefix (**in
))
4976 /* Accept #0x0 as a synonym for #0. */
4977 if (strncmp (*in
, "0x", 2) == 0)
4980 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4985 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4986 &generic_floating_point_number
);
4989 && generic_floating_point_number
.sign
== '+'
4990 && (generic_floating_point_number
.low
4991 > generic_floating_point_number
.leader
))
4997 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4998 0baBbbbbbc defgh000 00000000 00000000.
4999 The zero and minus-zero cases need special handling, since they can't be
5000 encoded in the "quarter-precision" float format, but can nonetheless be
5001 loaded as integer constants. */
5004 parse_qfloat_immediate (char **ccp
, int *immed
)
5008 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5009 int found_fpchar
= 0;
5011 skip_past_char (&str
, '#');
5013 /* We must not accidentally parse an integer as a floating-point number. Make
5014 sure that the value we parse is not an integer by checking for special
5015 characters '.' or 'e'.
5016 FIXME: This is a horrible hack, but doing better is tricky because type
5017 information isn't in a very usable state at parse time. */
5019 skip_whitespace (fpnum
);
5021 if (strncmp (fpnum
, "0x", 2) == 0)
5025 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5026 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5036 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5038 unsigned fpword
= 0;
5041 /* Our FP word must be 32 bits (single-precision FP). */
5042 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5044 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5048 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5061 /* Shift operands. */
5064 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5067 struct asm_shift_name
5070 enum shift_kind kind
;
5073 /* Third argument to parse_shift. */
5074 enum parse_shift_mode
5076 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5077 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5078 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5079 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5080 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5083 /* Parse a <shift> specifier on an ARM data processing instruction.
5084 This has three forms:
5086 (LSL|LSR|ASL|ASR|ROR) Rs
5087 (LSL|LSR|ASL|ASR|ROR) #imm
5090 Note that ASL is assimilated to LSL in the instruction encoding, and
5091 RRX to ROR #0 (which cannot be written as such). */
5094 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5096 const struct asm_shift_name
*shift_name
;
5097 enum shift_kind shift
;
5102 for (p
= *str
; ISALPHA (*p
); p
++)
5107 inst
.error
= _("shift expression expected");
5111 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5114 if (shift_name
== NULL
)
5116 inst
.error
= _("shift expression expected");
5120 shift
= shift_name
->kind
;
5124 case NO_SHIFT_RESTRICT
:
5125 case SHIFT_IMMEDIATE
: break;
5127 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5128 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5130 inst
.error
= _("'LSL' or 'ASR' required");
5135 case SHIFT_LSL_IMMEDIATE
:
5136 if (shift
!= SHIFT_LSL
)
5138 inst
.error
= _("'LSL' required");
5143 case SHIFT_ASR_IMMEDIATE
:
5144 if (shift
!= SHIFT_ASR
)
5146 inst
.error
= _("'ASR' required");
5154 if (shift
!= SHIFT_RRX
)
5156 /* Whitespace can appear here if the next thing is a bare digit. */
5157 skip_whitespace (p
);
5159 if (mode
== NO_SHIFT_RESTRICT
5160 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5162 inst
.operands
[i
].imm
= reg
;
5163 inst
.operands
[i
].immisreg
= 1;
5165 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5168 inst
.operands
[i
].shift_kind
= shift
;
5169 inst
.operands
[i
].shifted
= 1;
5174 /* Parse a <shifter_operand> for an ARM data processing instruction:
5177 #<immediate>, <rotate>
5181 where <shift> is defined by parse_shift above, and <rotate> is a
5182 multiple of 2 between 0 and 30. Validation of immediate operands
5183 is deferred to md_apply_fix. */
5186 parse_shifter_operand (char **str
, int i
)
5191 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5193 inst
.operands
[i
].reg
= value
;
5194 inst
.operands
[i
].isreg
= 1;
5196 /* parse_shift will override this if appropriate */
5197 inst
.reloc
.exp
.X_op
= O_constant
;
5198 inst
.reloc
.exp
.X_add_number
= 0;
5200 if (skip_past_comma (str
) == FAIL
)
5203 /* Shift operation on register. */
5204 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5207 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5210 if (skip_past_comma (str
) == SUCCESS
)
5212 /* #x, y -- ie explicit rotation by Y. */
5213 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5216 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5218 inst
.error
= _("constant expression expected");
5222 value
= exp
.X_add_number
;
5223 if (value
< 0 || value
> 30 || value
% 2 != 0)
5225 inst
.error
= _("invalid rotation");
5228 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5230 inst
.error
= _("invalid constant");
5234 /* Encode as specified. */
5235 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5239 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5240 inst
.reloc
.pc_rel
= 0;
5244 /* Group relocation information. Each entry in the table contains the
5245 textual name of the relocation as may appear in assembler source
5246 and must end with a colon.
5247 Along with this textual name are the relocation codes to be used if
5248 the corresponding instruction is an ALU instruction (ADD or SUB only),
5249 an LDR, an LDRS, or an LDC. */
5251 struct group_reloc_table_entry
5262 /* Varieties of non-ALU group relocation. */
5269 static struct group_reloc_table_entry group_reloc_table
[] =
5270 { /* Program counter relative: */
5272 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5277 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5278 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5279 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5280 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5282 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5287 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5288 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5289 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5290 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5292 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5293 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5294 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5295 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5296 /* Section base relative */
5298 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5303 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5304 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5305 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5306 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5308 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5313 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5314 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5315 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5316 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5318 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5319 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5320 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5321 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5322 /* Absolute thumb alu relocations. */
5324 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5329 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5334 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5339 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5344 /* Given the address of a pointer pointing to the textual name of a group
5345 relocation as may appear in assembler source, attempt to find its details
5346 in group_reloc_table. The pointer will be updated to the character after
5347 the trailing colon. On failure, FAIL will be returned; SUCCESS
5348 otherwise. On success, *entry will be updated to point at the relevant
5349 group_reloc_table entry. */
5352 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5355 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5357 int length
= strlen (group_reloc_table
[i
].name
);
5359 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5360 && (*str
)[length
] == ':')
5362 *out
= &group_reloc_table
[i
];
5363 *str
+= (length
+ 1);
5371 /* Parse a <shifter_operand> for an ARM data processing instruction
5372 (as for parse_shifter_operand) where group relocations are allowed:
5375 #<immediate>, <rotate>
5376 #:<group_reloc>:<expression>
5380 where <group_reloc> is one of the strings defined in group_reloc_table.
5381 The hashes are optional.
5383 Everything else is as for parse_shifter_operand. */
5385 static parse_operand_result
5386 parse_shifter_operand_group_reloc (char **str
, int i
)
5388 /* Determine if we have the sequence of characters #: or just :
5389 coming next. If we do, then we check for a group relocation.
5390 If we don't, punt the whole lot to parse_shifter_operand. */
5392 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5393 || (*str
)[0] == ':')
5395 struct group_reloc_table_entry
*entry
;
5397 if ((*str
)[0] == '#')
5402 /* Try to parse a group relocation. Anything else is an error. */
5403 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5405 inst
.error
= _("unknown group relocation");
5406 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5409 /* We now have the group relocation table entry corresponding to
5410 the name in the assembler source. Next, we parse the expression. */
5411 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5412 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5414 /* Record the relocation type (always the ALU variant here). */
5415 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5416 gas_assert (inst
.reloc
.type
!= 0);
5418 return PARSE_OPERAND_SUCCESS
;
5421 return parse_shifter_operand (str
, i
) == SUCCESS
5422 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5424 /* Never reached. */
5427 /* Parse a Neon alignment expression. Information is written to
5428 inst.operands[i]. We assume the initial ':' has been skipped.
5430 align .imm = align << 8, .immisalign=1, .preind=0 */
5431 static parse_operand_result
5432 parse_neon_alignment (char **str
, int i
)
5437 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5439 if (exp
.X_op
!= O_constant
)
5441 inst
.error
= _("alignment must be constant");
5442 return PARSE_OPERAND_FAIL
;
5445 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5446 inst
.operands
[i
].immisalign
= 1;
5447 /* Alignments are not pre-indexes. */
5448 inst
.operands
[i
].preind
= 0;
5451 return PARSE_OPERAND_SUCCESS
;
5454 /* Parse all forms of an ARM address expression. Information is written
5455 to inst.operands[i] and/or inst.reloc.
5457 Preindexed addressing (.preind=1):
5459 [Rn, #offset] .reg=Rn .reloc.exp=offset
5460 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5461 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5462 .shift_kind=shift .reloc.exp=shift_imm
5464 These three may have a trailing ! which causes .writeback to be set also.
5466 Postindexed addressing (.postind=1, .writeback=1):
5468 [Rn], #offset .reg=Rn .reloc.exp=offset
5469 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5470 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5471 .shift_kind=shift .reloc.exp=shift_imm
5473 Unindexed addressing (.preind=0, .postind=0):
5475 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5479 [Rn]{!} shorthand for [Rn,#0]{!}
5480 =immediate .isreg=0 .reloc.exp=immediate
5481 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5483 It is the caller's responsibility to check for addressing modes not
5484 supported by the instruction, and to set inst.reloc.type. */
5486 static parse_operand_result
5487 parse_address_main (char **str
, int i
, int group_relocations
,
5488 group_reloc_type group_type
)
5493 if (skip_past_char (&p
, '[') == FAIL
)
5495 if (skip_past_char (&p
, '=') == FAIL
)
5497 /* Bare address - translate to PC-relative offset. */
5498 inst
.reloc
.pc_rel
= 1;
5499 inst
.operands
[i
].reg
= REG_PC
;
5500 inst
.operands
[i
].isreg
= 1;
5501 inst
.operands
[i
].preind
= 1;
5503 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5504 return PARSE_OPERAND_FAIL
;
5506 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5507 /*allow_symbol_p=*/TRUE
))
5508 return PARSE_OPERAND_FAIL
;
5511 return PARSE_OPERAND_SUCCESS
;
5514 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5515 skip_whitespace (p
);
5517 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5519 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5520 return PARSE_OPERAND_FAIL
;
5522 inst
.operands
[i
].reg
= reg
;
5523 inst
.operands
[i
].isreg
= 1;
5525 if (skip_past_comma (&p
) == SUCCESS
)
5527 inst
.operands
[i
].preind
= 1;
5530 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5532 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5534 inst
.operands
[i
].imm
= reg
;
5535 inst
.operands
[i
].immisreg
= 1;
5537 if (skip_past_comma (&p
) == SUCCESS
)
5538 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5539 return PARSE_OPERAND_FAIL
;
5541 else if (skip_past_char (&p
, ':') == SUCCESS
)
5543 /* FIXME: '@' should be used here, but it's filtered out by generic
5544 code before we get to see it here. This may be subject to
5546 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5548 if (result
!= PARSE_OPERAND_SUCCESS
)
5553 if (inst
.operands
[i
].negative
)
5555 inst
.operands
[i
].negative
= 0;
5559 if (group_relocations
5560 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5562 struct group_reloc_table_entry
*entry
;
5564 /* Skip over the #: or : sequence. */
5570 /* Try to parse a group relocation. Anything else is an
5572 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5574 inst
.error
= _("unknown group relocation");
5575 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5578 /* We now have the group relocation table entry corresponding to
5579 the name in the assembler source. Next, we parse the
5581 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5582 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5584 /* Record the relocation type. */
5588 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5592 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5596 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5603 if (inst
.reloc
.type
== 0)
5605 inst
.error
= _("this group relocation is not allowed on this instruction");
5606 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5612 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5613 return PARSE_OPERAND_FAIL
;
5614 /* If the offset is 0, find out if it's a +0 or -0. */
5615 if (inst
.reloc
.exp
.X_op
== O_constant
5616 && inst
.reloc
.exp
.X_add_number
== 0)
5618 skip_whitespace (q
);
5622 skip_whitespace (q
);
5625 inst
.operands
[i
].negative
= 1;
5630 else if (skip_past_char (&p
, ':') == SUCCESS
)
5632 /* FIXME: '@' should be used here, but it's filtered out by generic code
5633 before we get to see it here. This may be subject to change. */
5634 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5636 if (result
!= PARSE_OPERAND_SUCCESS
)
5640 if (skip_past_char (&p
, ']') == FAIL
)
5642 inst
.error
= _("']' expected");
5643 return PARSE_OPERAND_FAIL
;
5646 if (skip_past_char (&p
, '!') == SUCCESS
)
5647 inst
.operands
[i
].writeback
= 1;
5649 else if (skip_past_comma (&p
) == SUCCESS
)
5651 if (skip_past_char (&p
, '{') == SUCCESS
)
5653 /* [Rn], {expr} - unindexed, with option */
5654 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5655 0, 255, TRUE
) == FAIL
)
5656 return PARSE_OPERAND_FAIL
;
5658 if (skip_past_char (&p
, '}') == FAIL
)
5660 inst
.error
= _("'}' expected at end of 'option' field");
5661 return PARSE_OPERAND_FAIL
;
5663 if (inst
.operands
[i
].preind
)
5665 inst
.error
= _("cannot combine index with option");
5666 return PARSE_OPERAND_FAIL
;
5669 return PARSE_OPERAND_SUCCESS
;
5673 inst
.operands
[i
].postind
= 1;
5674 inst
.operands
[i
].writeback
= 1;
5676 if (inst
.operands
[i
].preind
)
5678 inst
.error
= _("cannot combine pre- and post-indexing");
5679 return PARSE_OPERAND_FAIL
;
5683 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5685 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5687 /* We might be using the immediate for alignment already. If we
5688 are, OR the register number into the low-order bits. */
5689 if (inst
.operands
[i
].immisalign
)
5690 inst
.operands
[i
].imm
|= reg
;
5692 inst
.operands
[i
].imm
= reg
;
5693 inst
.operands
[i
].immisreg
= 1;
5695 if (skip_past_comma (&p
) == SUCCESS
)
5696 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5697 return PARSE_OPERAND_FAIL
;
5702 if (inst
.operands
[i
].negative
)
5704 inst
.operands
[i
].negative
= 0;
5707 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5708 return PARSE_OPERAND_FAIL
;
5709 /* If the offset is 0, find out if it's a +0 or -0. */
5710 if (inst
.reloc
.exp
.X_op
== O_constant
5711 && inst
.reloc
.exp
.X_add_number
== 0)
5713 skip_whitespace (q
);
5717 skip_whitespace (q
);
5720 inst
.operands
[i
].negative
= 1;
5726 /* If at this point neither .preind nor .postind is set, we have a
5727 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5728 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5730 inst
.operands
[i
].preind
= 1;
5731 inst
.reloc
.exp
.X_op
= O_constant
;
5732 inst
.reloc
.exp
.X_add_number
= 0;
5735 return PARSE_OPERAND_SUCCESS
;
5739 parse_address (char **str
, int i
)
5741 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5745 static parse_operand_result
5746 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5748 return parse_address_main (str
, i
, 1, type
);
5751 /* Parse an operand for a MOVW or MOVT instruction. */
5753 parse_half (char **str
)
5758 skip_past_char (&p
, '#');
5759 if (strncasecmp (p
, ":lower16:", 9) == 0)
5760 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5761 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5762 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5764 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5767 skip_whitespace (p
);
5770 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5773 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5775 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5777 inst
.error
= _("constant expression expected");
5780 if (inst
.reloc
.exp
.X_add_number
< 0
5781 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5783 inst
.error
= _("immediate value out of range");
5791 /* Miscellaneous. */
5793 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5794 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5796 parse_psr (char **str
, bfd_boolean lhs
)
5799 unsigned long psr_field
;
5800 const struct asm_psr
*psr
;
5802 bfd_boolean is_apsr
= FALSE
;
5803 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5805 /* PR gas/12698: If the user has specified -march=all then m_profile will
5806 be TRUE, but we want to ignore it in this case as we are building for any
5807 CPU type, including non-m variants. */
5808 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5811 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5812 feature for ease of use and backwards compatibility. */
5814 if (strncasecmp (p
, "SPSR", 4) == 0)
5817 goto unsupported_psr
;
5819 psr_field
= SPSR_BIT
;
5821 else if (strncasecmp (p
, "CPSR", 4) == 0)
5824 goto unsupported_psr
;
5828 else if (strncasecmp (p
, "APSR", 4) == 0)
5830 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5831 and ARMv7-R architecture CPUs. */
5840 while (ISALNUM (*p
) || *p
== '_');
5842 if (strncasecmp (start
, "iapsr", 5) == 0
5843 || strncasecmp (start
, "eapsr", 5) == 0
5844 || strncasecmp (start
, "xpsr", 4) == 0
5845 || strncasecmp (start
, "psr", 3) == 0)
5846 p
= start
+ strcspn (start
, "rR") + 1;
5848 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5854 /* If APSR is being written, a bitfield may be specified. Note that
5855 APSR itself is handled above. */
5856 if (psr
->field
<= 3)
5858 psr_field
= psr
->field
;
5864 /* M-profile MSR instructions have the mask field set to "10", except
5865 *PSR variants which modify APSR, which may use a different mask (and
5866 have been handled already). Do that by setting the PSR_f field
5868 return psr
->field
| (lhs
? PSR_f
: 0);
5871 goto unsupported_psr
;
5877 /* A suffix follows. */
5883 while (ISALNUM (*p
) || *p
== '_');
5887 /* APSR uses a notation for bits, rather than fields. */
5888 unsigned int nzcvq_bits
= 0;
5889 unsigned int g_bit
= 0;
5892 for (bit
= start
; bit
!= p
; bit
++)
5894 switch (TOLOWER (*bit
))
5897 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5901 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5905 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5909 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5913 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5917 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5921 inst
.error
= _("unexpected bit specified after APSR");
5926 if (nzcvq_bits
== 0x1f)
5931 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5933 inst
.error
= _("selected processor does not "
5934 "support DSP extension");
5941 if ((nzcvq_bits
& 0x20) != 0
5942 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5943 || (g_bit
& 0x2) != 0)
5945 inst
.error
= _("bad bitmask specified after APSR");
5951 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5956 psr_field
|= psr
->field
;
5962 goto error
; /* Garbage after "[CS]PSR". */
5964 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5965 is deprecated, but allow it anyway. */
5969 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5972 else if (!m_profile
)
5973 /* These bits are never right for M-profile devices: don't set them
5974 (only code paths which read/write APSR reach here). */
5975 psr_field
|= (PSR_c
| PSR_f
);
5981 inst
.error
= _("selected processor does not support requested special "
5982 "purpose register");
5986 inst
.error
= _("flag for {c}psr instruction expected");
5990 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5991 value suitable for splatting into the AIF field of the instruction. */
5994 parse_cps_flags (char **str
)
6003 case '\0': case ',':
6006 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6007 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6008 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6011 inst
.error
= _("unrecognized CPS flag");
6016 if (saw_a_flag
== 0)
6018 inst
.error
= _("missing CPS flags");
6026 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6027 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6030 parse_endian_specifier (char **str
)
6035 if (strncasecmp (s
, "BE", 2))
6037 else if (strncasecmp (s
, "LE", 2))
6041 inst
.error
= _("valid endian specifiers are be or le");
6045 if (ISALNUM (s
[2]) || s
[2] == '_')
6047 inst
.error
= _("valid endian specifiers are be or le");
6052 return little_endian
;
6055 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6056 value suitable for poking into the rotate field of an sxt or sxta
6057 instruction, or FAIL on error. */
6060 parse_ror (char **str
)
6065 if (strncasecmp (s
, "ROR", 3) == 0)
6069 inst
.error
= _("missing rotation field after comma");
6073 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6078 case 0: *str
= s
; return 0x0;
6079 case 8: *str
= s
; return 0x1;
6080 case 16: *str
= s
; return 0x2;
6081 case 24: *str
= s
; return 0x3;
6084 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6089 /* Parse a conditional code (from conds[] below). The value returned is in the
6090 range 0 .. 14, or FAIL. */
6092 parse_cond (char **str
)
6095 const struct asm_cond
*c
;
6097 /* Condition codes are always 2 characters, so matching up to
6098 3 characters is sufficient. */
6103 while (ISALPHA (*q
) && n
< 3)
6105 cond
[n
] = TOLOWER (*q
);
6110 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6113 inst
.error
= _("condition required");
6121 /* Record a use of the given feature. */
6123 record_feature_use (const arm_feature_set
*feature
)
6126 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6128 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6131 /* If the given feature available in the selected CPU, mark it as used.
6132 Returns TRUE iff feature is available. */
6134 mark_feature_used (const arm_feature_set
*feature
)
6136 /* Ensure the option is valid on the current architecture. */
6137 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6140 /* Add the appropriate architecture feature for the barrier option used.
6142 record_feature_use (feature
);
6147 /* Parse an option for a barrier instruction. Returns the encoding for the
6150 parse_barrier (char **str
)
6153 const struct asm_barrier_opt
*o
;
6156 while (ISALPHA (*q
))
6159 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6164 if (!mark_feature_used (&o
->arch
))
6171 /* Parse the operands of a table branch instruction. Similar to a memory
6174 parse_tb (char **str
)
6179 if (skip_past_char (&p
, '[') == FAIL
)
6181 inst
.error
= _("'[' expected");
6185 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6187 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6190 inst
.operands
[0].reg
= reg
;
6192 if (skip_past_comma (&p
) == FAIL
)
6194 inst
.error
= _("',' expected");
6198 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6200 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6203 inst
.operands
[0].imm
= reg
;
6205 if (skip_past_comma (&p
) == SUCCESS
)
6207 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6209 if (inst
.reloc
.exp
.X_add_number
!= 1)
6211 inst
.error
= _("invalid shift");
6214 inst
.operands
[0].shifted
= 1;
6217 if (skip_past_char (&p
, ']') == FAIL
)
6219 inst
.error
= _("']' expected");
6226 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6227 information on the types the operands can take and how they are encoded.
6228 Up to four operands may be read; this function handles setting the
6229 ".present" field for each read operand itself.
6230 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6231 else returns FAIL. */
6234 parse_neon_mov (char **str
, int *which_operand
)
6236 int i
= *which_operand
, val
;
6237 enum arm_reg_type rtype
;
6239 struct neon_type_el optype
;
6241 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6243 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6244 inst
.operands
[i
].reg
= val
;
6245 inst
.operands
[i
].isscalar
= 1;
6246 inst
.operands
[i
].vectype
= optype
;
6247 inst
.operands
[i
++].present
= 1;
6249 if (skip_past_comma (&ptr
) == FAIL
)
6252 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6255 inst
.operands
[i
].reg
= val
;
6256 inst
.operands
[i
].isreg
= 1;
6257 inst
.operands
[i
].present
= 1;
6259 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6262 /* Cases 0, 1, 2, 3, 5 (D only). */
6263 if (skip_past_comma (&ptr
) == FAIL
)
6266 inst
.operands
[i
].reg
= val
;
6267 inst
.operands
[i
].isreg
= 1;
6268 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6269 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6270 inst
.operands
[i
].isvec
= 1;
6271 inst
.operands
[i
].vectype
= optype
;
6272 inst
.operands
[i
++].present
= 1;
6274 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6276 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6277 Case 13: VMOV <Sd>, <Rm> */
6278 inst
.operands
[i
].reg
= val
;
6279 inst
.operands
[i
].isreg
= 1;
6280 inst
.operands
[i
].present
= 1;
6282 if (rtype
== REG_TYPE_NQ
)
6284 first_error (_("can't use Neon quad register here"));
6287 else if (rtype
!= REG_TYPE_VFS
)
6290 if (skip_past_comma (&ptr
) == FAIL
)
6292 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6294 inst
.operands
[i
].reg
= val
;
6295 inst
.operands
[i
].isreg
= 1;
6296 inst
.operands
[i
].present
= 1;
6299 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6302 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6303 Case 1: VMOV<c><q> <Dd>, <Dm>
6304 Case 8: VMOV.F32 <Sd>, <Sm>
6305 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6307 inst
.operands
[i
].reg
= val
;
6308 inst
.operands
[i
].isreg
= 1;
6309 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6310 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6311 inst
.operands
[i
].isvec
= 1;
6312 inst
.operands
[i
].vectype
= optype
;
6313 inst
.operands
[i
].present
= 1;
6315 if (skip_past_comma (&ptr
) == SUCCESS
)
6320 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6323 inst
.operands
[i
].reg
= val
;
6324 inst
.operands
[i
].isreg
= 1;
6325 inst
.operands
[i
++].present
= 1;
6327 if (skip_past_comma (&ptr
) == FAIL
)
6330 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6333 inst
.operands
[i
].reg
= val
;
6334 inst
.operands
[i
].isreg
= 1;
6335 inst
.operands
[i
].present
= 1;
6338 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6339 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6340 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6341 Case 10: VMOV.F32 <Sd>, #<imm>
6342 Case 11: VMOV.F64 <Dd>, #<imm> */
6343 inst
.operands
[i
].immisfloat
= 1;
6344 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6346 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6347 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6351 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6355 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6358 inst
.operands
[i
].reg
= val
;
6359 inst
.operands
[i
].isreg
= 1;
6360 inst
.operands
[i
++].present
= 1;
6362 if (skip_past_comma (&ptr
) == FAIL
)
6365 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6367 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6368 inst
.operands
[i
].reg
= val
;
6369 inst
.operands
[i
].isscalar
= 1;
6370 inst
.operands
[i
].present
= 1;
6371 inst
.operands
[i
].vectype
= optype
;
6373 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6375 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6376 inst
.operands
[i
].reg
= val
;
6377 inst
.operands
[i
].isreg
= 1;
6378 inst
.operands
[i
++].present
= 1;
6380 if (skip_past_comma (&ptr
) == FAIL
)
6383 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6386 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6390 inst
.operands
[i
].reg
= val
;
6391 inst
.operands
[i
].isreg
= 1;
6392 inst
.operands
[i
].isvec
= 1;
6393 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6394 inst
.operands
[i
].vectype
= optype
;
6395 inst
.operands
[i
].present
= 1;
6397 if (rtype
== REG_TYPE_VFS
)
6401 if (skip_past_comma (&ptr
) == FAIL
)
6403 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6406 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6409 inst
.operands
[i
].reg
= val
;
6410 inst
.operands
[i
].isreg
= 1;
6411 inst
.operands
[i
].isvec
= 1;
6412 inst
.operands
[i
].issingle
= 1;
6413 inst
.operands
[i
].vectype
= optype
;
6414 inst
.operands
[i
].present
= 1;
6417 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6421 inst
.operands
[i
].reg
= val
;
6422 inst
.operands
[i
].isreg
= 1;
6423 inst
.operands
[i
].isvec
= 1;
6424 inst
.operands
[i
].issingle
= 1;
6425 inst
.operands
[i
].vectype
= optype
;
6426 inst
.operands
[i
].present
= 1;
6431 first_error (_("parse error"));
6435 /* Successfully parsed the operands. Update args. */
6441 first_error (_("expected comma"));
6445 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6449 /* Use this macro when the operand constraints are different
6450 for ARM and THUMB (e.g. ldrd). */
6451 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6452 ((arm_operand) | ((thumb_operand) << 16))
6454 /* Matcher codes for parse_operands. */
6455 enum operand_parse_code
6457 OP_stop
, /* end of line */
6459 OP_RR
, /* ARM register */
6460 OP_RRnpc
, /* ARM register, not r15 */
6461 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6462 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6463 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6464 optional trailing ! */
6465 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6466 OP_RCP
, /* Coprocessor number */
6467 OP_RCN
, /* Coprocessor register */
6468 OP_RF
, /* FPA register */
6469 OP_RVS
, /* VFP single precision register */
6470 OP_RVD
, /* VFP double precision register (0..15) */
6471 OP_RND
, /* Neon double precision register (0..31) */
6472 OP_RNQ
, /* Neon quad precision register */
6473 OP_RVSD
, /* VFP single or double precision register */
6474 OP_RNDQ
, /* Neon double or quad precision register */
6475 OP_RNSDQ
, /* Neon single, double or quad precision register */
6476 OP_RNSC
, /* Neon scalar D[X] */
6477 OP_RVC
, /* VFP control register */
6478 OP_RMF
, /* Maverick F register */
6479 OP_RMD
, /* Maverick D register */
6480 OP_RMFX
, /* Maverick FX register */
6481 OP_RMDX
, /* Maverick DX register */
6482 OP_RMAX
, /* Maverick AX register */
6483 OP_RMDS
, /* Maverick DSPSC register */
6484 OP_RIWR
, /* iWMMXt wR register */
6485 OP_RIWC
, /* iWMMXt wC register */
6486 OP_RIWG
, /* iWMMXt wCG register */
6487 OP_RXA
, /* XScale accumulator register */
6489 OP_REGLST
, /* ARM register list */
6490 OP_VRSLST
, /* VFP single-precision register list */
6491 OP_VRDLST
, /* VFP double-precision register list */
6492 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6493 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6494 OP_NSTRLST
, /* Neon element/structure list */
6496 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6497 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6498 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6499 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6500 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6501 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6502 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6503 OP_VMOV
, /* Neon VMOV operands. */
6504 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6505 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6506 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6508 OP_I0
, /* immediate zero */
6509 OP_I7
, /* immediate value 0 .. 7 */
6510 OP_I15
, /* 0 .. 15 */
6511 OP_I16
, /* 1 .. 16 */
6512 OP_I16z
, /* 0 .. 16 */
6513 OP_I31
, /* 0 .. 31 */
6514 OP_I31w
, /* 0 .. 31, optional trailing ! */
6515 OP_I32
, /* 1 .. 32 */
6516 OP_I32z
, /* 0 .. 32 */
6517 OP_I63
, /* 0 .. 63 */
6518 OP_I63s
, /* -64 .. 63 */
6519 OP_I64
, /* 1 .. 64 */
6520 OP_I64z
, /* 0 .. 64 */
6521 OP_I255
, /* 0 .. 255 */
6523 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6524 OP_I7b
, /* 0 .. 7 */
6525 OP_I15b
, /* 0 .. 15 */
6526 OP_I31b
, /* 0 .. 31 */
6528 OP_SH
, /* shifter operand */
6529 OP_SHG
, /* shifter operand with possible group relocation */
6530 OP_ADDR
, /* Memory address expression (any mode) */
6531 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6532 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6533 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6534 OP_EXP
, /* arbitrary expression */
6535 OP_EXPi
, /* same, with optional immediate prefix */
6536 OP_EXPr
, /* same, with optional relocation suffix */
6537 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6539 OP_CPSF
, /* CPS flags */
6540 OP_ENDI
, /* Endianness specifier */
6541 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6542 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6543 OP_COND
, /* conditional code */
6544 OP_TB
, /* Table branch. */
6546 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6548 OP_RRnpc_I0
, /* ARM register or literal 0 */
6549 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6550 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6551 OP_RF_IF
, /* FPA register or immediate */
6552 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6553 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6555 /* Optional operands. */
6556 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6557 OP_oI31b
, /* 0 .. 31 */
6558 OP_oI32b
, /* 1 .. 32 */
6559 OP_oI32z
, /* 0 .. 32 */
6560 OP_oIffffb
, /* 0 .. 65535 */
6561 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6563 OP_oRR
, /* ARM register */
6564 OP_oRRnpc
, /* ARM register, not the PC */
6565 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6566 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6567 OP_oRND
, /* Optional Neon double precision register */
6568 OP_oRNQ
, /* Optional Neon quad precision register */
6569 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6570 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6571 OP_oSHll
, /* LSL immediate */
6572 OP_oSHar
, /* ASR immediate */
6573 OP_oSHllar
, /* LSL or ASR immediate */
6574 OP_oROR
, /* ROR 0/8/16/24 */
6575 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6577 /* Some pre-defined mixed (ARM/THUMB) operands. */
6578 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6579 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6580 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6582 OP_FIRST_OPTIONAL
= OP_oI7b
6585 /* Generic instruction operand parser. This does no encoding and no
6586 semantic validation; it merely squirrels values away in the inst
6587 structure. Returns SUCCESS or FAIL depending on whether the
6588 specified grammar matched. */
6590 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6592 unsigned const int *upat
= pattern
;
6593 char *backtrack_pos
= 0;
6594 const char *backtrack_error
= 0;
6595 int i
, val
= 0, backtrack_index
= 0;
6596 enum arm_reg_type rtype
;
6597 parse_operand_result result
;
6598 unsigned int op_parse_code
;
6600 #define po_char_or_fail(chr) \
6603 if (skip_past_char (&str, chr) == FAIL) \
6608 #define po_reg_or_fail(regtype) \
6611 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6612 & inst.operands[i].vectype); \
6615 first_error (_(reg_expected_msgs[regtype])); \
6618 inst.operands[i].reg = val; \
6619 inst.operands[i].isreg = 1; \
6620 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6621 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6622 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6623 || rtype == REG_TYPE_VFD \
6624 || rtype == REG_TYPE_NQ); \
6628 #define po_reg_or_goto(regtype, label) \
6631 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6632 & inst.operands[i].vectype); \
6636 inst.operands[i].reg = val; \
6637 inst.operands[i].isreg = 1; \
6638 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6639 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6640 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6641 || rtype == REG_TYPE_VFD \
6642 || rtype == REG_TYPE_NQ); \
6646 #define po_imm_or_fail(min, max, popt) \
6649 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6651 inst.operands[i].imm = val; \
6655 #define po_scalar_or_goto(elsz, label) \
6658 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6661 inst.operands[i].reg = val; \
6662 inst.operands[i].isscalar = 1; \
6666 #define po_misc_or_fail(expr) \
6674 #define po_misc_or_fail_no_backtrack(expr) \
6678 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6679 backtrack_pos = 0; \
6680 if (result != PARSE_OPERAND_SUCCESS) \
6685 #define po_barrier_or_imm(str) \
6688 val = parse_barrier (&str); \
6689 if (val == FAIL && ! ISALPHA (*str)) \
6692 /* ISB can only take SY as an option. */ \
6693 || ((inst.instruction & 0xf0) == 0x60 \
6696 inst.error = _("invalid barrier type"); \
6697 backtrack_pos = 0; \
6703 skip_whitespace (str
);
6705 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6707 op_parse_code
= upat
[i
];
6708 if (op_parse_code
>= 1<<16)
6709 op_parse_code
= thumb
? (op_parse_code
>> 16)
6710 : (op_parse_code
& ((1<<16)-1));
6712 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6714 /* Remember where we are in case we need to backtrack. */
6715 gas_assert (!backtrack_pos
);
6716 backtrack_pos
= str
;
6717 backtrack_error
= inst
.error
;
6718 backtrack_index
= i
;
6721 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6722 po_char_or_fail (',');
6724 switch (op_parse_code
)
6732 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6733 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6734 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6735 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6736 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6737 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6739 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6741 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6743 /* Also accept generic coprocessor regs for unknown registers. */
6745 po_reg_or_fail (REG_TYPE_CN
);
6747 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6748 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6749 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6750 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6751 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6752 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6753 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6754 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6755 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6756 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6758 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6760 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6761 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6763 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6765 /* Neon scalar. Using an element size of 8 means that some invalid
6766 scalars are accepted here, so deal with those in later code. */
6767 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6771 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6774 po_imm_or_fail (0, 0, TRUE
);
6779 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6784 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6787 if (parse_ifimm_zero (&str
))
6788 inst
.operands
[i
].imm
= 0;
6792 = _("only floating point zero is allowed as immediate value");
6800 po_scalar_or_goto (8, try_rr
);
6803 po_reg_or_fail (REG_TYPE_RN
);
6809 po_scalar_or_goto (8, try_nsdq
);
6812 po_reg_or_fail (REG_TYPE_NSDQ
);
6818 po_scalar_or_goto (8, try_ndq
);
6821 po_reg_or_fail (REG_TYPE_NDQ
);
6827 po_scalar_or_goto (8, try_vfd
);
6830 po_reg_or_fail (REG_TYPE_VFD
);
6835 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6836 not careful then bad things might happen. */
6837 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6842 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6845 /* There's a possibility of getting a 64-bit immediate here, so
6846 we need special handling. */
6847 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6850 inst
.error
= _("immediate value is out of range");
6858 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6861 po_imm_or_fail (0, 63, TRUE
);
6866 po_char_or_fail ('[');
6867 po_reg_or_fail (REG_TYPE_RN
);
6868 po_char_or_fail (']');
6874 po_reg_or_fail (REG_TYPE_RN
);
6875 if (skip_past_char (&str
, '!') == SUCCESS
)
6876 inst
.operands
[i
].writeback
= 1;
6880 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6881 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6882 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6883 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6884 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6885 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6886 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6887 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6888 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6889 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6890 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6891 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6893 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6895 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6896 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6898 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6899 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6900 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6901 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6903 /* Immediate variants */
6905 po_char_or_fail ('{');
6906 po_imm_or_fail (0, 255, TRUE
);
6907 po_char_or_fail ('}');
6911 /* The expression parser chokes on a trailing !, so we have
6912 to find it first and zap it. */
6915 while (*s
&& *s
!= ',')
6920 inst
.operands
[i
].writeback
= 1;
6922 po_imm_or_fail (0, 31, TRUE
);
6930 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6935 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6940 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6942 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6944 val
= parse_reloc (&str
);
6947 inst
.error
= _("unrecognized relocation suffix");
6950 else if (val
!= BFD_RELOC_UNUSED
)
6952 inst
.operands
[i
].imm
= val
;
6953 inst
.operands
[i
].hasreloc
= 1;
6958 /* Operand for MOVW or MOVT. */
6960 po_misc_or_fail (parse_half (&str
));
6963 /* Register or expression. */
6964 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6965 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6967 /* Register or immediate. */
6968 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6969 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6971 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6973 if (!is_immediate_prefix (*str
))
6976 val
= parse_fpa_immediate (&str
);
6979 /* FPA immediates are encoded as registers 8-15.
6980 parse_fpa_immediate has already applied the offset. */
6981 inst
.operands
[i
].reg
= val
;
6982 inst
.operands
[i
].isreg
= 1;
6985 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6986 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6988 /* Two kinds of register. */
6991 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6993 || (rege
->type
!= REG_TYPE_MMXWR
6994 && rege
->type
!= REG_TYPE_MMXWC
6995 && rege
->type
!= REG_TYPE_MMXWCG
))
6997 inst
.error
= _("iWMMXt data or control register expected");
7000 inst
.operands
[i
].reg
= rege
->number
;
7001 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7007 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7009 || (rege
->type
!= REG_TYPE_MMXWC
7010 && rege
->type
!= REG_TYPE_MMXWCG
))
7012 inst
.error
= _("iWMMXt control register expected");
7015 inst
.operands
[i
].reg
= rege
->number
;
7016 inst
.operands
[i
].isreg
= 1;
7021 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7022 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7023 case OP_oROR
: val
= parse_ror (&str
); break;
7024 case OP_COND
: val
= parse_cond (&str
); break;
7025 case OP_oBARRIER_I15
:
7026 po_barrier_or_imm (str
); break;
7028 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7034 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7035 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7037 inst
.error
= _("Banked registers are not available with this "
7043 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7047 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7050 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7052 if (strncasecmp (str
, "APSR_", 5) == 0)
7059 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7060 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7061 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7062 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7063 default: found
= 16;
7067 inst
.operands
[i
].isvec
= 1;
7068 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7069 inst
.operands
[i
].reg
= REG_PC
;
7076 po_misc_or_fail (parse_tb (&str
));
7079 /* Register lists. */
7081 val
= parse_reg_list (&str
);
7084 inst
.operands
[i
].writeback
= 1;
7090 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7094 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7098 /* Allow Q registers too. */
7099 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7104 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7106 inst
.operands
[i
].issingle
= 1;
7111 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7116 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7117 &inst
.operands
[i
].vectype
);
7120 /* Addressing modes */
7122 po_misc_or_fail (parse_address (&str
, i
));
7126 po_misc_or_fail_no_backtrack (
7127 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7131 po_misc_or_fail_no_backtrack (
7132 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7136 po_misc_or_fail_no_backtrack (
7137 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7141 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7145 po_misc_or_fail_no_backtrack (
7146 parse_shifter_operand_group_reloc (&str
, i
));
7150 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7154 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7158 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7162 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7165 /* Various value-based sanity checks and shared operations. We
7166 do not signal immediate failures for the register constraints;
7167 this allows a syntax error to take precedence. */
7168 switch (op_parse_code
)
7176 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7177 inst
.error
= BAD_PC
;
7182 if (inst
.operands
[i
].isreg
)
7184 if (inst
.operands
[i
].reg
== REG_PC
)
7185 inst
.error
= BAD_PC
;
7186 else if (inst
.operands
[i
].reg
== REG_SP
)
7187 inst
.error
= BAD_SP
;
7192 if (inst
.operands
[i
].isreg
7193 && inst
.operands
[i
].reg
== REG_PC
7194 && (inst
.operands
[i
].writeback
|| thumb
))
7195 inst
.error
= BAD_PC
;
7204 case OP_oBARRIER_I15
:
7213 inst
.operands
[i
].imm
= val
;
7220 /* If we get here, this operand was successfully parsed. */
7221 inst
.operands
[i
].present
= 1;
7225 inst
.error
= BAD_ARGS
;
7230 /* The parse routine should already have set inst.error, but set a
7231 default here just in case. */
7233 inst
.error
= _("syntax error");
7237 /* Do not backtrack over a trailing optional argument that
7238 absorbed some text. We will only fail again, with the
7239 'garbage following instruction' error message, which is
7240 probably less helpful than the current one. */
7241 if (backtrack_index
== i
&& backtrack_pos
!= str
7242 && upat
[i
+1] == OP_stop
)
7245 inst
.error
= _("syntax error");
7249 /* Try again, skipping the optional argument at backtrack_pos. */
7250 str
= backtrack_pos
;
7251 inst
.error
= backtrack_error
;
7252 inst
.operands
[backtrack_index
].present
= 0;
7253 i
= backtrack_index
;
7257 /* Check that we have parsed all the arguments. */
7258 if (*str
!= '\0' && !inst
.error
)
7259 inst
.error
= _("garbage following instruction");
7261 return inst
.error
? FAIL
: SUCCESS
;
7264 #undef po_char_or_fail
7265 #undef po_reg_or_fail
7266 #undef po_reg_or_goto
7267 #undef po_imm_or_fail
7268 #undef po_scalar_or_fail
7269 #undef po_barrier_or_imm
7271 /* Shorthand macro for instruction encoding functions issuing errors. */
7272 #define constraint(expr, err) \
7283 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7284 instructions are unpredictable if these registers are used. This
7285 is the BadReg predicate in ARM's Thumb-2 documentation. */
7286 #define reject_bad_reg(reg) \
7288 if (reg == REG_SP || reg == REG_PC) \
7290 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7295 /* If REG is R13 (the stack pointer), warn that its use is
7297 #define warn_deprecated_sp(reg) \
7299 if (warn_on_deprecated && reg == REG_SP) \
7300 as_tsktsk (_("use of r13 is deprecated")); \
7303 /* Functions for operand encoding. ARM, then Thumb. */
7305 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7307 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7309 The only binary encoding difference is the Coprocessor number. Coprocessor
7310 9 is used for half-precision calculations or conversions. The format of the
7311 instruction is the same as the equivalent Coprocessor 10 instruction that
7312 exists for Single-Precision operation. */
7315 do_scalar_fp16_v82_encode (void)
7317 if (inst
.cond
!= COND_ALWAYS
)
7318 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7319 " the behaviour is UNPREDICTABLE"));
7320 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7323 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7324 mark_feature_used (&arm_ext_fp16
);
7327 /* If VAL can be encoded in the immediate field of an ARM instruction,
7328 return the encoded form. Otherwise, return FAIL. */
7331 encode_arm_immediate (unsigned int val
)
7338 for (i
= 2; i
< 32; i
+= 2)
7339 if ((a
= rotate_left (val
, i
)) <= 0xff)
7340 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7345 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7346 return the encoded form. Otherwise, return FAIL. */
7348 encode_thumb32_immediate (unsigned int val
)
7355 for (i
= 1; i
<= 24; i
++)
7358 if ((val
& ~(0xff << i
)) == 0)
7359 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7363 if (val
== ((a
<< 16) | a
))
7365 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7369 if (val
== ((a
<< 16) | a
))
7370 return 0x200 | (a
>> 8);
7374 /* Encode a VFP SP or DP register number into inst.instruction. */
7377 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7379 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7382 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7385 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7388 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7393 first_error (_("D register out of range for selected VFP version"));
7401 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7405 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7409 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7413 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7417 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7421 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7429 /* Encode a <shift> in an ARM-format instruction. The immediate,
7430 if any, is handled by md_apply_fix. */
7432 encode_arm_shift (int i
)
7434 /* register-shifted register. */
7435 if (inst
.operands
[i
].immisreg
)
7438 for (index
= 0; index
<= i
; ++index
)
7440 /* Check the operand only when it's presented. In pre-UAL syntax,
7441 if the destination register is the same as the first operand, two
7442 register form of the instruction can be used. */
7443 if (inst
.operands
[index
].present
&& inst
.operands
[index
].isreg
7444 && inst
.operands
[index
].reg
== REG_PC
)
7445 as_warn (UNPRED_REG ("r15"));
7448 if (inst
.operands
[i
].imm
== REG_PC
)
7449 as_warn (UNPRED_REG ("r15"));
7452 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7453 inst
.instruction
|= SHIFT_ROR
<< 5;
7456 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7457 if (inst
.operands
[i
].immisreg
)
7459 inst
.instruction
|= SHIFT_BY_REG
;
7460 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7463 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7468 encode_arm_shifter_operand (int i
)
7470 if (inst
.operands
[i
].isreg
)
7472 inst
.instruction
|= inst
.operands
[i
].reg
;
7473 encode_arm_shift (i
);
7477 inst
.instruction
|= INST_IMMEDIATE
;
7478 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7479 inst
.instruction
|= inst
.operands
[i
].imm
;
7483 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7485 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7488 Generate an error if the operand is not a register. */
7489 constraint (!inst
.operands
[i
].isreg
,
7490 _("Instruction does not support =N addresses"));
7492 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7494 if (inst
.operands
[i
].preind
)
7498 inst
.error
= _("instruction does not accept preindexed addressing");
7501 inst
.instruction
|= PRE_INDEX
;
7502 if (inst
.operands
[i
].writeback
)
7503 inst
.instruction
|= WRITE_BACK
;
7506 else if (inst
.operands
[i
].postind
)
7508 gas_assert (inst
.operands
[i
].writeback
);
7510 inst
.instruction
|= WRITE_BACK
;
7512 else /* unindexed - only for coprocessor */
7514 inst
.error
= _("instruction does not accept unindexed addressing");
7518 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7519 && (((inst
.instruction
& 0x000f0000) >> 16)
7520 == ((inst
.instruction
& 0x0000f000) >> 12)))
7521 as_warn ((inst
.instruction
& LOAD_BIT
)
7522 ? _("destination register same as write-back base")
7523 : _("source register same as write-back base"));
7526 /* inst.operands[i] was set up by parse_address. Encode it into an
7527 ARM-format mode 2 load or store instruction. If is_t is true,
7528 reject forms that cannot be used with a T instruction (i.e. not
7531 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7533 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7535 encode_arm_addr_mode_common (i
, is_t
);
7537 if (inst
.operands
[i
].immisreg
)
7539 constraint ((inst
.operands
[i
].imm
== REG_PC
7540 || (is_pc
&& inst
.operands
[i
].writeback
)),
7542 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7543 inst
.instruction
|= inst
.operands
[i
].imm
;
7544 if (!inst
.operands
[i
].negative
)
7545 inst
.instruction
|= INDEX_UP
;
7546 if (inst
.operands
[i
].shifted
)
7548 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7549 inst
.instruction
|= SHIFT_ROR
<< 5;
7552 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7553 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7557 else /* immediate offset in inst.reloc */
7559 if (is_pc
&& !inst
.reloc
.pc_rel
)
7561 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7563 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7564 cannot use PC in addressing.
7565 PC cannot be used in writeback addressing, either. */
7566 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7569 /* Use of PC in str is deprecated for ARMv7. */
7570 if (warn_on_deprecated
7572 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7573 as_tsktsk (_("use of PC in this instruction is deprecated"));
7576 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7578 /* Prefer + for zero encoded value. */
7579 if (!inst
.operands
[i
].negative
)
7580 inst
.instruction
|= INDEX_UP
;
7581 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7586 /* inst.operands[i] was set up by parse_address. Encode it into an
7587 ARM-format mode 3 load or store instruction. Reject forms that
7588 cannot be used with such instructions. If is_t is true, reject
7589 forms that cannot be used with a T instruction (i.e. not
7592 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7594 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7596 inst
.error
= _("instruction does not accept scaled register index");
7600 encode_arm_addr_mode_common (i
, is_t
);
7602 if (inst
.operands
[i
].immisreg
)
7604 constraint ((inst
.operands
[i
].imm
== REG_PC
7605 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7607 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7609 inst
.instruction
|= inst
.operands
[i
].imm
;
7610 if (!inst
.operands
[i
].negative
)
7611 inst
.instruction
|= INDEX_UP
;
7613 else /* immediate offset in inst.reloc */
7615 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7616 && inst
.operands
[i
].writeback
),
7618 inst
.instruction
|= HWOFFSET_IMM
;
7619 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7621 /* Prefer + for zero encoded value. */
7622 if (!inst
.operands
[i
].negative
)
7623 inst
.instruction
|= INDEX_UP
;
7625 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7630 /* Write immediate bits [7:0] to the following locations:
7632 |28/24|23 19|18 16|15 4|3 0|
7633 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7635 This function is used by VMOV/VMVN/VORR/VBIC. */
7638 neon_write_immbits (unsigned immbits
)
7640 inst
.instruction
|= immbits
& 0xf;
7641 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7642 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7645 /* Invert low-order SIZE bits of XHI:XLO. */
7648 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7650 unsigned immlo
= xlo
? *xlo
: 0;
7651 unsigned immhi
= xhi
? *xhi
: 0;
7656 immlo
= (~immlo
) & 0xff;
7660 immlo
= (~immlo
) & 0xffff;
7664 immhi
= (~immhi
) & 0xffffffff;
7668 immlo
= (~immlo
) & 0xffffffff;
7682 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7686 neon_bits_same_in_bytes (unsigned imm
)
7688 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7689 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7690 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7691 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7694 /* For immediate of above form, return 0bABCD. */
7697 neon_squash_bits (unsigned imm
)
7699 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7700 | ((imm
& 0x01000000) >> 21);
7703 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7706 neon_qfloat_bits (unsigned imm
)
7708 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7711 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7712 the instruction. *OP is passed as the initial value of the op field, and
7713 may be set to a different value depending on the constant (i.e.
7714 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7715 MVN). If the immediate looks like a repeated pattern then also
7716 try smaller element sizes. */
7719 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7720 unsigned *immbits
, int *op
, int size
,
7721 enum neon_el_type type
)
7723 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7725 if (type
== NT_float
&& !float_p
)
7728 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7730 if (size
!= 32 || *op
== 1)
7732 *immbits
= neon_qfloat_bits (immlo
);
7738 if (neon_bits_same_in_bytes (immhi
)
7739 && neon_bits_same_in_bytes (immlo
))
7743 *immbits
= (neon_squash_bits (immhi
) << 4)
7744 | neon_squash_bits (immlo
);
7755 if (immlo
== (immlo
& 0x000000ff))
7760 else if (immlo
== (immlo
& 0x0000ff00))
7762 *immbits
= immlo
>> 8;
7765 else if (immlo
== (immlo
& 0x00ff0000))
7767 *immbits
= immlo
>> 16;
7770 else if (immlo
== (immlo
& 0xff000000))
7772 *immbits
= immlo
>> 24;
7775 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7777 *immbits
= (immlo
>> 8) & 0xff;
7780 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7782 *immbits
= (immlo
>> 16) & 0xff;
7786 if ((immlo
& 0xffff) != (immlo
>> 16))
7793 if (immlo
== (immlo
& 0x000000ff))
7798 else if (immlo
== (immlo
& 0x0000ff00))
7800 *immbits
= immlo
>> 8;
7804 if ((immlo
& 0xff) != (immlo
>> 8))
7809 if (immlo
== (immlo
& 0x000000ff))
7811 /* Don't allow MVN with 8-bit immediate. */
7821 #if defined BFD_HOST_64_BIT
7822 /* Returns TRUE if double precision value V may be cast
7823 to single precision without loss of accuracy. */
7826 is_double_a_single (bfd_int64_t v
)
7828 int exp
= (int)((v
>> 52) & 0x7FF);
7829 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7831 return (exp
== 0 || exp
== 0x7FF
7832 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7833 && (mantissa
& 0x1FFFFFFFl
) == 0;
7836 /* Returns a double precision value casted to single precision
7837 (ignoring the least significant bits in exponent and mantissa). */
7840 double_to_single (bfd_int64_t v
)
7842 int sign
= (int) ((v
>> 63) & 1l);
7843 int exp
= (int) ((v
>> 52) & 0x7FF);
7844 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7850 exp
= exp
- 1023 + 127;
7859 /* No denormalized numbers. */
7865 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7867 #endif /* BFD_HOST_64_BIT */
7876 static void do_vfp_nsyn_opcode (const char *);
7878 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7879 Determine whether it can be performed with a move instruction; if
7880 it can, convert inst.instruction to that move instruction and
7881 return TRUE; if it can't, convert inst.instruction to a literal-pool
7882 load and return FALSE. If this is not a valid thing to do in the
7883 current context, set inst.error and return TRUE.
7885 inst.operands[i] describes the destination register. */
7888 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7891 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7892 bfd_boolean arm_p
= (t
== CONST_ARM
);
7895 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7899 if ((inst
.instruction
& tbit
) == 0)
7901 inst
.error
= _("invalid pseudo operation");
7905 if (inst
.reloc
.exp
.X_op
!= O_constant
7906 && inst
.reloc
.exp
.X_op
!= O_symbol
7907 && inst
.reloc
.exp
.X_op
!= O_big
)
7909 inst
.error
= _("constant expression expected");
7913 if (inst
.reloc
.exp
.X_op
== O_constant
7914 || inst
.reloc
.exp
.X_op
== O_big
)
7916 #if defined BFD_HOST_64_BIT
7921 if (inst
.reloc
.exp
.X_op
== O_big
)
7923 LITTLENUM_TYPE w
[X_PRECISION
];
7926 if (inst
.reloc
.exp
.X_add_number
== -1)
7928 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7930 /* FIXME: Should we check words w[2..5] ? */
7935 #if defined BFD_HOST_64_BIT
7937 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7938 << LITTLENUM_NUMBER_OF_BITS
)
7939 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7940 << LITTLENUM_NUMBER_OF_BITS
)
7941 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7942 << LITTLENUM_NUMBER_OF_BITS
)
7943 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7945 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7946 | (l
[0] & LITTLENUM_MASK
);
7950 v
= inst
.reloc
.exp
.X_add_number
;
7952 if (!inst
.operands
[i
].issingle
)
7956 /* This can be encoded only for a low register. */
7957 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7959 /* This can be done with a mov(1) instruction. */
7960 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7961 inst
.instruction
|= v
;
7965 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7966 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7968 /* Check if on thumb2 it can be done with a mov.w, mvn or
7969 movw instruction. */
7970 unsigned int newimm
;
7971 bfd_boolean isNegated
;
7973 newimm
= encode_thumb32_immediate (v
);
7974 if (newimm
!= (unsigned int) FAIL
)
7978 newimm
= encode_thumb32_immediate (~v
);
7979 if (newimm
!= (unsigned int) FAIL
)
7983 /* The number can be loaded with a mov.w or mvn
7985 if (newimm
!= (unsigned int) FAIL
7986 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7988 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7989 | (inst
.operands
[i
].reg
<< 8));
7990 /* Change to MOVN. */
7991 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7992 inst
.instruction
|= (newimm
& 0x800) << 15;
7993 inst
.instruction
|= (newimm
& 0x700) << 4;
7994 inst
.instruction
|= (newimm
& 0x0ff);
7997 /* The number can be loaded with a movw instruction. */
7998 else if ((v
& ~0xFFFF) == 0
7999 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8001 int imm
= v
& 0xFFFF;
8003 inst
.instruction
= 0xf2400000; /* MOVW. */
8004 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8005 inst
.instruction
|= (imm
& 0xf000) << 4;
8006 inst
.instruction
|= (imm
& 0x0800) << 15;
8007 inst
.instruction
|= (imm
& 0x0700) << 4;
8008 inst
.instruction
|= (imm
& 0x00ff);
8015 int value
= encode_arm_immediate (v
);
8019 /* This can be done with a mov instruction. */
8020 inst
.instruction
&= LITERAL_MASK
;
8021 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8022 inst
.instruction
|= value
& 0xfff;
8026 value
= encode_arm_immediate (~ v
);
8029 /* This can be done with a mvn instruction. */
8030 inst
.instruction
&= LITERAL_MASK
;
8031 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8032 inst
.instruction
|= value
& 0xfff;
8036 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8039 unsigned immbits
= 0;
8040 unsigned immlo
= inst
.operands
[1].imm
;
8041 unsigned immhi
= inst
.operands
[1].regisimm
8042 ? inst
.operands
[1].reg
8043 : inst
.reloc
.exp
.X_unsigned
8045 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8046 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8047 &op
, 64, NT_invtype
);
8051 neon_invert_size (&immlo
, &immhi
, 64);
8053 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8054 &op
, 64, NT_invtype
);
8059 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8065 /* Fill other bits in vmov encoding for both thumb and arm. */
8067 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8069 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8070 neon_write_immbits (immbits
);
8078 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8079 if (inst
.operands
[i
].issingle
8080 && is_quarter_float (inst
.operands
[1].imm
)
8081 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8083 inst
.operands
[1].imm
=
8084 neon_qfloat_bits (v
);
8085 do_vfp_nsyn_opcode ("fconsts");
8089 /* If our host does not support a 64-bit type then we cannot perform
8090 the following optimization. This mean that there will be a
8091 discrepancy between the output produced by an assembler built for
8092 a 32-bit-only host and the output produced from a 64-bit host, but
8093 this cannot be helped. */
8094 #if defined BFD_HOST_64_BIT
8095 else if (!inst
.operands
[1].issingle
8096 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8098 if (is_double_a_single (v
)
8099 && is_quarter_float (double_to_single (v
)))
8101 inst
.operands
[1].imm
=
8102 neon_qfloat_bits (double_to_single (v
));
8103 do_vfp_nsyn_opcode ("fconstd");
8111 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8112 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8115 inst
.operands
[1].reg
= REG_PC
;
8116 inst
.operands
[1].isreg
= 1;
8117 inst
.operands
[1].preind
= 1;
8118 inst
.reloc
.pc_rel
= 1;
8119 inst
.reloc
.type
= (thumb_p
8120 ? BFD_RELOC_ARM_THUMB_OFFSET
8122 ? BFD_RELOC_ARM_HWLITERAL
8123 : BFD_RELOC_ARM_LITERAL
));
8127 /* inst.operands[i] was set up by parse_address. Encode it into an
8128 ARM-format instruction. Reject all forms which cannot be encoded
8129 into a coprocessor load/store instruction. If wb_ok is false,
8130 reject use of writeback; if unind_ok is false, reject use of
8131 unindexed addressing. If reloc_override is not 0, use it instead
8132 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8133 (in which case it is preserved). */
8136 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8138 if (!inst
.operands
[i
].isreg
)
8141 if (! inst
.operands
[0].isvec
)
8143 inst
.error
= _("invalid co-processor operand");
8146 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8150 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8152 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8154 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8156 gas_assert (!inst
.operands
[i
].writeback
);
8159 inst
.error
= _("instruction does not support unindexed addressing");
8162 inst
.instruction
|= inst
.operands
[i
].imm
;
8163 inst
.instruction
|= INDEX_UP
;
8167 if (inst
.operands
[i
].preind
)
8168 inst
.instruction
|= PRE_INDEX
;
8170 if (inst
.operands
[i
].writeback
)
8172 if (inst
.operands
[i
].reg
== REG_PC
)
8174 inst
.error
= _("pc may not be used with write-back");
8179 inst
.error
= _("instruction does not support writeback");
8182 inst
.instruction
|= WRITE_BACK
;
8186 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8187 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8188 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8189 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8192 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8194 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8197 /* Prefer + for zero encoded value. */
8198 if (!inst
.operands
[i
].negative
)
8199 inst
.instruction
|= INDEX_UP
;
8204 /* Functions for instruction encoding, sorted by sub-architecture.
8205 First some generics; their names are taken from the conventional
8206 bit positions for register arguments in ARM format instructions. */
8216 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8222 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8228 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8229 inst
.instruction
|= inst
.operands
[1].reg
;
8235 inst
.instruction
|= inst
.operands
[0].reg
;
8236 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8242 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8243 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8249 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8250 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8256 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8257 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8261 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8263 if (ARM_CPU_IS_ANY (cpu_variant
))
8265 as_tsktsk ("%s", msg
);
8268 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8280 unsigned Rn
= inst
.operands
[2].reg
;
8281 /* Enforce restrictions on SWP instruction. */
8282 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8284 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8285 _("Rn must not overlap other operands"));
8287 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8289 if (!check_obsolete (&arm_ext_v8
,
8290 _("swp{b} use is obsoleted for ARMv8 and later"))
8291 && warn_on_deprecated
8292 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8293 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8296 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8297 inst
.instruction
|= inst
.operands
[1].reg
;
8298 inst
.instruction
|= Rn
<< 16;
8304 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8305 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8306 inst
.instruction
|= inst
.operands
[2].reg
;
8312 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8313 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8314 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8315 || inst
.reloc
.exp
.X_add_number
!= 0),
8317 inst
.instruction
|= inst
.operands
[0].reg
;
8318 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8319 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8325 inst
.instruction
|= inst
.operands
[0].imm
;
8331 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8332 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8335 /* ARM instructions, in alphabetical order by function name (except
8336 that wrapper functions appear immediately after the function they
8339 /* This is a pseudo-op of the form "adr rd, label" to be converted
8340 into a relative address of the form "add rd, pc, #label-.-8". */
8345 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8347 /* Frag hacking will turn this into a sub instruction if the offset turns
8348 out to be negative. */
8349 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8350 inst
.reloc
.pc_rel
= 1;
8351 inst
.reloc
.exp
.X_add_number
-= 8;
8354 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8355 into a relative address of the form:
8356 add rd, pc, #low(label-.-8)"
8357 add rd, rd, #high(label-.-8)" */
8362 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8364 /* Frag hacking will turn this into a sub instruction if the offset turns
8365 out to be negative. */
8366 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8367 inst
.reloc
.pc_rel
= 1;
8368 inst
.size
= INSN_SIZE
* 2;
8369 inst
.reloc
.exp
.X_add_number
-= 8;
8375 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8376 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8378 if (!inst
.operands
[1].present
)
8379 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8380 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8381 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8382 encode_arm_shifter_operand (2);
8388 if (inst
.operands
[0].present
)
8389 inst
.instruction
|= inst
.operands
[0].imm
;
8391 inst
.instruction
|= 0xf;
8397 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8398 constraint (msb
> 32, _("bit-field extends past end of register"));
8399 /* The instruction encoding stores the LSB and MSB,
8400 not the LSB and width. */
8401 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8402 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8403 inst
.instruction
|= (msb
- 1) << 16;
8411 /* #0 in second position is alternative syntax for bfc, which is
8412 the same instruction but with REG_PC in the Rm field. */
8413 if (!inst
.operands
[1].isreg
)
8414 inst
.operands
[1].reg
= REG_PC
;
8416 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8417 constraint (msb
> 32, _("bit-field extends past end of register"));
8418 /* The instruction encoding stores the LSB and MSB,
8419 not the LSB and width. */
8420 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8421 inst
.instruction
|= inst
.operands
[1].reg
;
8422 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8423 inst
.instruction
|= (msb
- 1) << 16;
8429 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8430 _("bit-field extends past end of register"));
8431 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8432 inst
.instruction
|= inst
.operands
[1].reg
;
8433 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8434 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8437 /* ARM V5 breakpoint instruction (argument parse)
8438 BKPT <16 bit unsigned immediate>
8439 Instruction is not conditional.
8440 The bit pattern given in insns[] has the COND_ALWAYS condition,
8441 and it is an error if the caller tried to override that. */
8446 /* Top 12 of 16 bits to bits 19:8. */
8447 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8449 /* Bottom 4 of 16 bits to bits 3:0. */
8450 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8454 encode_branch (int default_reloc
)
8456 if (inst
.operands
[0].hasreloc
)
8458 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8459 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8460 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8461 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8462 ? BFD_RELOC_ARM_PLT32
8463 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8466 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8467 inst
.reloc
.pc_rel
= 1;
8474 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8475 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8478 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8485 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8487 if (inst
.cond
== COND_ALWAYS
)
8488 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8490 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8494 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8497 /* ARM V5 branch-link-exchange instruction (argument parse)
8498 BLX <target_addr> ie BLX(1)
8499 BLX{<condition>} <Rm> ie BLX(2)
8500 Unfortunately, there are two different opcodes for this mnemonic.
8501 So, the insns[].value is not used, and the code here zaps values
8502 into inst.instruction.
8503 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8508 if (inst
.operands
[0].isreg
)
8510 /* Arg is a register; the opcode provided by insns[] is correct.
8511 It is not illegal to do "blx pc", just useless. */
8512 if (inst
.operands
[0].reg
== REG_PC
)
8513 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8515 inst
.instruction
|= inst
.operands
[0].reg
;
8519 /* Arg is an address; this instruction cannot be executed
8520 conditionally, and the opcode must be adjusted.
8521 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8522 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8523 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8524 inst
.instruction
= 0xfa000000;
8525 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8532 bfd_boolean want_reloc
;
8534 if (inst
.operands
[0].reg
== REG_PC
)
8535 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8537 inst
.instruction
|= inst
.operands
[0].reg
;
8538 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8539 it is for ARMv4t or earlier. */
8540 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8541 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8545 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8550 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8554 /* ARM v5TEJ. Jump to Jazelle code. */
8559 if (inst
.operands
[0].reg
== REG_PC
)
8560 as_tsktsk (_("use of r15 in bxj is not really useful"));
8562 inst
.instruction
|= inst
.operands
[0].reg
;
8565 /* Co-processor data operation:
8566 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8567 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8571 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8572 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8573 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8574 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8575 inst
.instruction
|= inst
.operands
[4].reg
;
8576 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8582 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8583 encode_arm_shifter_operand (1);
8586 /* Transfer between coprocessor and ARM registers.
8587 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8592 No special properties. */
8594 struct deprecated_coproc_regs_s
8601 arm_feature_set deprecated
;
8602 arm_feature_set obsoleted
;
8603 const char *dep_msg
;
8604 const char *obs_msg
;
8607 #define DEPR_ACCESS_V8 \
8608 N_("This coprocessor register access is deprecated in ARMv8")
8610 /* Table of all deprecated coprocessor registers. */
8611 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8613 {15, 0, 7, 10, 5, /* CP15DMB. */
8614 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8615 DEPR_ACCESS_V8
, NULL
},
8616 {15, 0, 7, 10, 4, /* CP15DSB. */
8617 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8618 DEPR_ACCESS_V8
, NULL
},
8619 {15, 0, 7, 5, 4, /* CP15ISB. */
8620 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8621 DEPR_ACCESS_V8
, NULL
},
8622 {14, 6, 1, 0, 0, /* TEEHBR. */
8623 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8624 DEPR_ACCESS_V8
, NULL
},
8625 {14, 6, 0, 0, 0, /* TEECR. */
8626 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8627 DEPR_ACCESS_V8
, NULL
},
8630 #undef DEPR_ACCESS_V8
8632 static const size_t deprecated_coproc_reg_count
=
8633 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8641 Rd
= inst
.operands
[2].reg
;
8644 if (inst
.instruction
== 0xee000010
8645 || inst
.instruction
== 0xfe000010)
8647 reject_bad_reg (Rd
);
8650 constraint (Rd
== REG_SP
, BAD_SP
);
8655 if (inst
.instruction
== 0xe000010)
8656 constraint (Rd
== REG_PC
, BAD_PC
);
8659 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8661 const struct deprecated_coproc_regs_s
*r
=
8662 deprecated_coproc_regs
+ i
;
8664 if (inst
.operands
[0].reg
== r
->cp
8665 && inst
.operands
[1].imm
== r
->opc1
8666 && inst
.operands
[3].reg
== r
->crn
8667 && inst
.operands
[4].reg
== r
->crm
8668 && inst
.operands
[5].imm
== r
->opc2
)
8670 if (! ARM_CPU_IS_ANY (cpu_variant
)
8671 && warn_on_deprecated
8672 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8673 as_tsktsk ("%s", r
->dep_msg
);
8677 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8678 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8679 inst
.instruction
|= Rd
<< 12;
8680 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8681 inst
.instruction
|= inst
.operands
[4].reg
;
8682 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8685 /* Transfer between coprocessor register and pair of ARM registers.
8686 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8691 Two XScale instructions are special cases of these:
8693 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8694 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8696 Result unpredictable if Rd or Rn is R15. */
8703 Rd
= inst
.operands
[2].reg
;
8704 Rn
= inst
.operands
[3].reg
;
8708 reject_bad_reg (Rd
);
8709 reject_bad_reg (Rn
);
8713 constraint (Rd
== REG_PC
, BAD_PC
);
8714 constraint (Rn
== REG_PC
, BAD_PC
);
8717 /* Only check the MRRC{2} variants. */
8718 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8720 /* If Rd == Rn, error that the operation is
8721 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8722 constraint (Rd
== Rn
, BAD_OVERLAP
);
8725 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8726 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8727 inst
.instruction
|= Rd
<< 12;
8728 inst
.instruction
|= Rn
<< 16;
8729 inst
.instruction
|= inst
.operands
[4].reg
;
8735 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8736 if (inst
.operands
[1].present
)
8738 inst
.instruction
|= CPSI_MMOD
;
8739 inst
.instruction
|= inst
.operands
[1].imm
;
8746 inst
.instruction
|= inst
.operands
[0].imm
;
8752 unsigned Rd
, Rn
, Rm
;
8754 Rd
= inst
.operands
[0].reg
;
8755 Rn
= (inst
.operands
[1].present
8756 ? inst
.operands
[1].reg
: Rd
);
8757 Rm
= inst
.operands
[2].reg
;
8759 constraint ((Rd
== REG_PC
), BAD_PC
);
8760 constraint ((Rn
== REG_PC
), BAD_PC
);
8761 constraint ((Rm
== REG_PC
), BAD_PC
);
8763 inst
.instruction
|= Rd
<< 16;
8764 inst
.instruction
|= Rn
<< 0;
8765 inst
.instruction
|= Rm
<< 8;
8771 /* There is no IT instruction in ARM mode. We
8772 process it to do the validation as if in
8773 thumb mode, just in case the code gets
8774 assembled for thumb using the unified syntax. */
8779 set_it_insn_type (IT_INSN
);
8780 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8781 now_it
.cc
= inst
.operands
[0].imm
;
8785 /* If there is only one register in the register list,
8786 then return its register number. Otherwise return -1. */
8788 only_one_reg_in_list (int range
)
8790 int i
= ffs (range
) - 1;
8791 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8795 encode_ldmstm(int from_push_pop_mnem
)
8797 int base_reg
= inst
.operands
[0].reg
;
8798 int range
= inst
.operands
[1].imm
;
8801 inst
.instruction
|= base_reg
<< 16;
8802 inst
.instruction
|= range
;
8804 if (inst
.operands
[1].writeback
)
8805 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8807 if (inst
.operands
[0].writeback
)
8809 inst
.instruction
|= WRITE_BACK
;
8810 /* Check for unpredictable uses of writeback. */
8811 if (inst
.instruction
& LOAD_BIT
)
8813 /* Not allowed in LDM type 2. */
8814 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8815 && ((range
& (1 << REG_PC
)) == 0))
8816 as_warn (_("writeback of base register is UNPREDICTABLE"));
8817 /* Only allowed if base reg not in list for other types. */
8818 else if (range
& (1 << base_reg
))
8819 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8823 /* Not allowed for type 2. */
8824 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8825 as_warn (_("writeback of base register is UNPREDICTABLE"));
8826 /* Only allowed if base reg not in list, or first in list. */
8827 else if ((range
& (1 << base_reg
))
8828 && (range
& ((1 << base_reg
) - 1)))
8829 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8833 /* If PUSH/POP has only one register, then use the A2 encoding. */
8834 one_reg
= only_one_reg_in_list (range
);
8835 if (from_push_pop_mnem
&& one_reg
>= 0)
8837 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8839 inst
.instruction
&= A_COND_MASK
;
8840 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8841 inst
.instruction
|= one_reg
<< 12;
8848 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8851 /* ARMv5TE load-consecutive (argument parse)
8860 constraint (inst
.operands
[0].reg
% 2 != 0,
8861 _("first transfer register must be even"));
8862 constraint (inst
.operands
[1].present
8863 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8864 _("can only transfer two consecutive registers"));
8865 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8866 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8868 if (!inst
.operands
[1].present
)
8869 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8871 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8872 register and the first register written; we have to diagnose
8873 overlap between the base and the second register written here. */
8875 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8876 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8877 as_warn (_("base register written back, and overlaps "
8878 "second transfer register"));
8880 if (!(inst
.instruction
& V4_STR_BIT
))
8882 /* For an index-register load, the index register must not overlap the
8883 destination (even if not write-back). */
8884 if (inst
.operands
[2].immisreg
8885 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8886 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8887 as_warn (_("index register overlaps transfer register"));
8889 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8890 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8896 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8897 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8898 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8899 || inst
.operands
[1].negative
8900 /* This can arise if the programmer has written
8902 or if they have mistakenly used a register name as the last
8905 It is very difficult to distinguish between these two cases
8906 because "rX" might actually be a label. ie the register
8907 name has been occluded by a symbol of the same name. So we
8908 just generate a general 'bad addressing mode' type error
8909 message and leave it up to the programmer to discover the
8910 true cause and fix their mistake. */
8911 || (inst
.operands
[1].reg
== REG_PC
),
8914 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8915 || inst
.reloc
.exp
.X_add_number
!= 0,
8916 _("offset must be zero in ARM encoding"));
8918 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8920 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8921 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8922 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8928 constraint (inst
.operands
[0].reg
% 2 != 0,
8929 _("even register required"));
8930 constraint (inst
.operands
[1].present
8931 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8932 _("can only load two consecutive registers"));
8933 /* If op 1 were present and equal to PC, this function wouldn't
8934 have been called in the first place. */
8935 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8937 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8938 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8941 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8942 which is not a multiple of four is UNPREDICTABLE. */
8944 check_ldr_r15_aligned (void)
8946 constraint (!(inst
.operands
[1].immisreg
)
8947 && (inst
.operands
[0].reg
== REG_PC
8948 && inst
.operands
[1].reg
== REG_PC
8949 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8950 _("ldr to register 15 must be 4-byte alligned"));
8956 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8957 if (!inst
.operands
[1].isreg
)
8958 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8960 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8961 check_ldr_r15_aligned ();
8967 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8969 if (inst
.operands
[1].preind
)
8971 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8972 || inst
.reloc
.exp
.X_add_number
!= 0,
8973 _("this instruction requires a post-indexed address"));
8975 inst
.operands
[1].preind
= 0;
8976 inst
.operands
[1].postind
= 1;
8977 inst
.operands
[1].writeback
= 1;
8979 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8980 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8983 /* Halfword and signed-byte load/store operations. */
8988 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8989 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8990 if (!inst
.operands
[1].isreg
)
8991 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8993 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8999 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9001 if (inst
.operands
[1].preind
)
9003 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9004 || inst
.reloc
.exp
.X_add_number
!= 0,
9005 _("this instruction requires a post-indexed address"));
9007 inst
.operands
[1].preind
= 0;
9008 inst
.operands
[1].postind
= 1;
9009 inst
.operands
[1].writeback
= 1;
9011 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9012 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9015 /* Co-processor register load/store.
9016 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9020 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9021 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9022 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9028 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9029 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9030 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9031 && !(inst
.instruction
& 0x00400000))
9032 as_tsktsk (_("Rd and Rm should be different in mla"));
9034 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9035 inst
.instruction
|= inst
.operands
[1].reg
;
9036 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9037 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9043 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9044 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9046 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9047 encode_arm_shifter_operand (1);
9050 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9057 top
= (inst
.instruction
& 0x00400000) != 0;
9058 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9059 _(":lower16: not allowed this instruction"));
9060 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9061 _(":upper16: not allowed instruction"));
9062 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9063 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9065 imm
= inst
.reloc
.exp
.X_add_number
;
9066 /* The value is in two pieces: 0:11, 16:19. */
9067 inst
.instruction
|= (imm
& 0x00000fff);
9068 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9073 do_vfp_nsyn_mrs (void)
9075 if (inst
.operands
[0].isvec
)
9077 if (inst
.operands
[1].reg
!= 1)
9078 first_error (_("operand 1 must be FPSCR"));
9079 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9080 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9081 do_vfp_nsyn_opcode ("fmstat");
9083 else if (inst
.operands
[1].isvec
)
9084 do_vfp_nsyn_opcode ("fmrx");
9092 do_vfp_nsyn_msr (void)
9094 if (inst
.operands
[0].isvec
)
9095 do_vfp_nsyn_opcode ("fmxr");
9105 unsigned Rt
= inst
.operands
[0].reg
;
9107 if (thumb_mode
&& Rt
== REG_SP
)
9109 inst
.error
= BAD_SP
;
9113 /* APSR_ sets isvec. All other refs to PC are illegal. */
9114 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9116 inst
.error
= BAD_PC
;
9120 /* If we get through parsing the register name, we just insert the number
9121 generated into the instruction without further validation. */
9122 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9123 inst
.instruction
|= (Rt
<< 12);
9129 unsigned Rt
= inst
.operands
[1].reg
;
9132 reject_bad_reg (Rt
);
9133 else if (Rt
== REG_PC
)
9135 inst
.error
= BAD_PC
;
9139 /* If we get through parsing the register name, we just insert the number
9140 generated into the instruction without further validation. */
9141 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9142 inst
.instruction
|= (Rt
<< 12);
9150 if (do_vfp_nsyn_mrs () == SUCCESS
)
9153 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9154 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9156 if (inst
.operands
[1].isreg
)
9158 br
= inst
.operands
[1].reg
;
9159 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9160 as_bad (_("bad register for mrs"));
9164 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9165 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9167 _("'APSR', 'CPSR' or 'SPSR' expected"));
9168 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9171 inst
.instruction
|= br
;
9174 /* Two possible forms:
9175 "{C|S}PSR_<field>, Rm",
9176 "{C|S}PSR_f, #expression". */
9181 if (do_vfp_nsyn_msr () == SUCCESS
)
9184 inst
.instruction
|= inst
.operands
[0].imm
;
9185 if (inst
.operands
[1].isreg
)
9186 inst
.instruction
|= inst
.operands
[1].reg
;
9189 inst
.instruction
|= INST_IMMEDIATE
;
9190 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9191 inst
.reloc
.pc_rel
= 0;
9198 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9200 if (!inst
.operands
[2].present
)
9201 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9202 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9203 inst
.instruction
|= inst
.operands
[1].reg
;
9204 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9206 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9207 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9208 as_tsktsk (_("Rd and Rm should be different in mul"));
9211 /* Long Multiply Parser
9212 UMULL RdLo, RdHi, Rm, Rs
9213 SMULL RdLo, RdHi, Rm, Rs
9214 UMLAL RdLo, RdHi, Rm, Rs
9215 SMLAL RdLo, RdHi, Rm, Rs. */
9220 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9221 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9222 inst
.instruction
|= inst
.operands
[2].reg
;
9223 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9225 /* rdhi and rdlo must be different. */
9226 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9227 as_tsktsk (_("rdhi and rdlo must be different"));
9229 /* rdhi, rdlo and rm must all be different before armv6. */
9230 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9231 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9232 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9233 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9239 if (inst
.operands
[0].present
9240 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9242 /* Architectural NOP hints are CPSR sets with no bits selected. */
9243 inst
.instruction
&= 0xf0000000;
9244 inst
.instruction
|= 0x0320f000;
9245 if (inst
.operands
[0].present
)
9246 inst
.instruction
|= inst
.operands
[0].imm
;
9250 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9251 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9252 Condition defaults to COND_ALWAYS.
9253 Error if Rd, Rn or Rm are R15. */
9258 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9259 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9260 inst
.instruction
|= inst
.operands
[2].reg
;
9261 if (inst
.operands
[3].present
)
9262 encode_arm_shift (3);
9265 /* ARM V6 PKHTB (Argument Parse). */
9270 if (!inst
.operands
[3].present
)
9272 /* If the shift specifier is omitted, turn the instruction
9273 into pkhbt rd, rm, rn. */
9274 inst
.instruction
&= 0xfff00010;
9275 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9276 inst
.instruction
|= inst
.operands
[1].reg
;
9277 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9281 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9282 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9283 inst
.instruction
|= inst
.operands
[2].reg
;
9284 encode_arm_shift (3);
9288 /* ARMv5TE: Preload-Cache
9289 MP Extensions: Preload for write
9293 Syntactically, like LDR with B=1, W=0, L=1. */
9298 constraint (!inst
.operands
[0].isreg
,
9299 _("'[' expected after PLD mnemonic"));
9300 constraint (inst
.operands
[0].postind
,
9301 _("post-indexed expression used in preload instruction"));
9302 constraint (inst
.operands
[0].writeback
,
9303 _("writeback used in preload instruction"));
9304 constraint (!inst
.operands
[0].preind
,
9305 _("unindexed addressing used in preload instruction"));
9306 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9309 /* ARMv7: PLI <addr_mode> */
9313 constraint (!inst
.operands
[0].isreg
,
9314 _("'[' expected after PLI mnemonic"));
9315 constraint (inst
.operands
[0].postind
,
9316 _("post-indexed expression used in preload instruction"));
9317 constraint (inst
.operands
[0].writeback
,
9318 _("writeback used in preload instruction"));
9319 constraint (!inst
.operands
[0].preind
,
9320 _("unindexed addressing used in preload instruction"));
9321 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9322 inst
.instruction
&= ~PRE_INDEX
;
9328 constraint (inst
.operands
[0].writeback
,
9329 _("push/pop do not support {reglist}^"));
9330 inst
.operands
[1] = inst
.operands
[0];
9331 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9332 inst
.operands
[0].isreg
= 1;
9333 inst
.operands
[0].writeback
= 1;
9334 inst
.operands
[0].reg
= REG_SP
;
9335 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9338 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9339 word at the specified address and the following word
9341 Unconditionally executed.
9342 Error if Rn is R15. */
9347 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9348 if (inst
.operands
[0].writeback
)
9349 inst
.instruction
|= WRITE_BACK
;
9352 /* ARM V6 ssat (argument parse). */
9357 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9358 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9359 inst
.instruction
|= inst
.operands
[2].reg
;
9361 if (inst
.operands
[3].present
)
9362 encode_arm_shift (3);
9365 /* ARM V6 usat (argument parse). */
9370 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9371 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9372 inst
.instruction
|= inst
.operands
[2].reg
;
9374 if (inst
.operands
[3].present
)
9375 encode_arm_shift (3);
9378 /* ARM V6 ssat16 (argument parse). */
9383 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9384 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9385 inst
.instruction
|= inst
.operands
[2].reg
;
9391 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9392 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9393 inst
.instruction
|= inst
.operands
[2].reg
;
9396 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9397 preserving the other bits.
9399 setend <endian_specifier>, where <endian_specifier> is either
9405 if (warn_on_deprecated
9406 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9407 as_tsktsk (_("setend use is deprecated for ARMv8"));
9409 if (inst
.operands
[0].imm
)
9410 inst
.instruction
|= 0x200;
9416 unsigned int Rm
= (inst
.operands
[1].present
9417 ? inst
.operands
[1].reg
9418 : inst
.operands
[0].reg
);
9420 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9421 inst
.instruction
|= Rm
;
9422 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9424 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9425 inst
.instruction
|= SHIFT_BY_REG
;
9426 /* PR 12854: Error on extraneous shifts. */
9427 constraint (inst
.operands
[2].shifted
,
9428 _("extraneous shift as part of operand to shift insn"));
9431 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9437 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9438 inst
.reloc
.pc_rel
= 0;
9444 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9445 inst
.reloc
.pc_rel
= 0;
9451 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9452 inst
.reloc
.pc_rel
= 0;
9458 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9459 _("selected processor does not support SETPAN instruction"));
9461 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9467 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9468 _("selected processor does not support SETPAN instruction"));
9470 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9473 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9474 SMLAxy{cond} Rd,Rm,Rs,Rn
9475 SMLAWy{cond} Rd,Rm,Rs,Rn
9476 Error if any register is R15. */
9481 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9482 inst
.instruction
|= inst
.operands
[1].reg
;
9483 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9484 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9487 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9488 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9489 Error if any register is R15.
9490 Warning if Rdlo == Rdhi. */
9495 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9496 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9497 inst
.instruction
|= inst
.operands
[2].reg
;
9498 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9500 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9501 as_tsktsk (_("rdhi and rdlo must be different"));
9504 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9505 SMULxy{cond} Rd,Rm,Rs
9506 Error if any register is R15. */
9511 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9512 inst
.instruction
|= inst
.operands
[1].reg
;
9513 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9516 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9517 the same for both ARM and Thumb-2. */
9524 if (inst
.operands
[0].present
)
9526 reg
= inst
.operands
[0].reg
;
9527 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9532 inst
.instruction
|= reg
<< 16;
9533 inst
.instruction
|= inst
.operands
[1].imm
;
9534 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9535 inst
.instruction
|= WRITE_BACK
;
9538 /* ARM V6 strex (argument parse). */
9543 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9544 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9545 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9546 || inst
.operands
[2].negative
9547 /* See comment in do_ldrex(). */
9548 || (inst
.operands
[2].reg
== REG_PC
),
9551 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9552 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9554 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9555 || inst
.reloc
.exp
.X_add_number
!= 0,
9556 _("offset must be zero in ARM encoding"));
9558 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9559 inst
.instruction
|= inst
.operands
[1].reg
;
9560 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9561 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9567 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9568 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9569 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9570 || inst
.operands
[2].negative
,
9573 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9574 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9582 constraint (inst
.operands
[1].reg
% 2 != 0,
9583 _("even register required"));
9584 constraint (inst
.operands
[2].present
9585 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9586 _("can only store two consecutive registers"));
9587 /* If op 2 were present and equal to PC, this function wouldn't
9588 have been called in the first place. */
9589 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9591 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9592 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9593 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9596 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9597 inst
.instruction
|= inst
.operands
[1].reg
;
9598 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9605 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9606 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9614 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9615 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9620 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9621 extends it to 32-bits, and adds the result to a value in another
9622 register. You can specify a rotation by 0, 8, 16, or 24 bits
9623 before extracting the 16-bit value.
9624 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9625 Condition defaults to COND_ALWAYS.
9626 Error if any register uses R15. */
9631 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9632 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9633 inst
.instruction
|= inst
.operands
[2].reg
;
9634 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9639 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9640 Condition defaults to COND_ALWAYS.
9641 Error if any register uses R15. */
9646 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9647 inst
.instruction
|= inst
.operands
[1].reg
;
9648 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9651 /* VFP instructions. In a logical order: SP variant first, monad
9652 before dyad, arithmetic then move then load/store. */
9655 do_vfp_sp_monadic (void)
9657 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9658 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9662 do_vfp_sp_dyadic (void)
9664 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9665 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9666 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9670 do_vfp_sp_compare_z (void)
9672 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9676 do_vfp_dp_sp_cvt (void)
9678 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9679 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9683 do_vfp_sp_dp_cvt (void)
9685 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9686 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9690 do_vfp_reg_from_sp (void)
9692 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9693 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9697 do_vfp_reg2_from_sp2 (void)
9699 constraint (inst
.operands
[2].imm
!= 2,
9700 _("only two consecutive VFP SP registers allowed here"));
9701 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9702 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9703 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9707 do_vfp_sp_from_reg (void)
9709 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9710 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9714 do_vfp_sp2_from_reg2 (void)
9716 constraint (inst
.operands
[0].imm
!= 2,
9717 _("only two consecutive VFP SP registers allowed here"));
9718 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9719 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9720 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9724 do_vfp_sp_ldst (void)
9726 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9727 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9731 do_vfp_dp_ldst (void)
9733 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9734 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9739 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9741 if (inst
.operands
[0].writeback
)
9742 inst
.instruction
|= WRITE_BACK
;
9744 constraint (ldstm_type
!= VFP_LDSTMIA
,
9745 _("this addressing mode requires base-register writeback"));
9746 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9747 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9748 inst
.instruction
|= inst
.operands
[1].imm
;
9752 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9756 if (inst
.operands
[0].writeback
)
9757 inst
.instruction
|= WRITE_BACK
;
9759 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9760 _("this addressing mode requires base-register writeback"));
9762 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9763 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9765 count
= inst
.operands
[1].imm
<< 1;
9766 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9769 inst
.instruction
|= count
;
9773 do_vfp_sp_ldstmia (void)
9775 vfp_sp_ldstm (VFP_LDSTMIA
);
9779 do_vfp_sp_ldstmdb (void)
9781 vfp_sp_ldstm (VFP_LDSTMDB
);
9785 do_vfp_dp_ldstmia (void)
9787 vfp_dp_ldstm (VFP_LDSTMIA
);
9791 do_vfp_dp_ldstmdb (void)
9793 vfp_dp_ldstm (VFP_LDSTMDB
);
9797 do_vfp_xp_ldstmia (void)
9799 vfp_dp_ldstm (VFP_LDSTMIAX
);
9803 do_vfp_xp_ldstmdb (void)
9805 vfp_dp_ldstm (VFP_LDSTMDBX
);
9809 do_vfp_dp_rd_rm (void)
9811 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9812 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9816 do_vfp_dp_rn_rd (void)
9818 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9819 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9823 do_vfp_dp_rd_rn (void)
9825 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9826 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9830 do_vfp_dp_rd_rn_rm (void)
9832 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9833 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9834 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9840 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9844 do_vfp_dp_rm_rd_rn (void)
9846 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9847 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9848 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9851 /* VFPv3 instructions. */
9853 do_vfp_sp_const (void)
9855 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9856 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9857 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9861 do_vfp_dp_const (void)
9863 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9864 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9865 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9869 vfp_conv (int srcsize
)
9871 int immbits
= srcsize
- inst
.operands
[1].imm
;
9873 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9875 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9876 i.e. immbits must be in range 0 - 16. */
9877 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9880 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9882 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9883 i.e. immbits must be in range 0 - 31. */
9884 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9888 inst
.instruction
|= (immbits
& 1) << 5;
9889 inst
.instruction
|= (immbits
>> 1);
9893 do_vfp_sp_conv_16 (void)
9895 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9900 do_vfp_dp_conv_16 (void)
9902 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9907 do_vfp_sp_conv_32 (void)
9909 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9914 do_vfp_dp_conv_32 (void)
9916 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9920 /* FPA instructions. Also in a logical order. */
9925 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9926 inst
.instruction
|= inst
.operands
[1].reg
;
9930 do_fpa_ldmstm (void)
9932 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9933 switch (inst
.operands
[1].imm
)
9935 case 1: inst
.instruction
|= CP_T_X
; break;
9936 case 2: inst
.instruction
|= CP_T_Y
; break;
9937 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9942 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9944 /* The instruction specified "ea" or "fd", so we can only accept
9945 [Rn]{!}. The instruction does not really support stacking or
9946 unstacking, so we have to emulate these by setting appropriate
9947 bits and offsets. */
9948 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9949 || inst
.reloc
.exp
.X_add_number
!= 0,
9950 _("this instruction does not support indexing"));
9952 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9953 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9955 if (!(inst
.instruction
& INDEX_UP
))
9956 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9958 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9960 inst
.operands
[2].preind
= 0;
9961 inst
.operands
[2].postind
= 1;
9965 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9968 /* iWMMXt instructions: strictly in alphabetical order. */
9971 do_iwmmxt_tandorc (void)
9973 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9977 do_iwmmxt_textrc (void)
9979 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9980 inst
.instruction
|= inst
.operands
[1].imm
;
9984 do_iwmmxt_textrm (void)
9986 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9987 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9988 inst
.instruction
|= inst
.operands
[2].imm
;
9992 do_iwmmxt_tinsr (void)
9994 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9995 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9996 inst
.instruction
|= inst
.operands
[2].imm
;
10000 do_iwmmxt_tmia (void)
10002 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10003 inst
.instruction
|= inst
.operands
[1].reg
;
10004 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10008 do_iwmmxt_waligni (void)
10010 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10011 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10012 inst
.instruction
|= inst
.operands
[2].reg
;
10013 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10017 do_iwmmxt_wmerge (void)
10019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10020 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10021 inst
.instruction
|= inst
.operands
[2].reg
;
10022 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10026 do_iwmmxt_wmov (void)
10028 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10029 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10030 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10031 inst
.instruction
|= inst
.operands
[1].reg
;
10035 do_iwmmxt_wldstbh (void)
10038 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10040 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10042 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10043 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10047 do_iwmmxt_wldstw (void)
10049 /* RIWR_RIWC clears .isreg for a control register. */
10050 if (!inst
.operands
[0].isreg
)
10052 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10053 inst
.instruction
|= 0xf0000000;
10056 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10057 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10061 do_iwmmxt_wldstd (void)
10063 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10064 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10065 && inst
.operands
[1].immisreg
)
10067 inst
.instruction
&= ~0x1a000ff;
10068 inst
.instruction
|= (0xfU
<< 28);
10069 if (inst
.operands
[1].preind
)
10070 inst
.instruction
|= PRE_INDEX
;
10071 if (!inst
.operands
[1].negative
)
10072 inst
.instruction
|= INDEX_UP
;
10073 if (inst
.operands
[1].writeback
)
10074 inst
.instruction
|= WRITE_BACK
;
10075 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10076 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10077 inst
.instruction
|= inst
.operands
[1].imm
;
10080 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10084 do_iwmmxt_wshufh (void)
10086 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10087 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10088 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10089 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10093 do_iwmmxt_wzero (void)
10095 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10096 inst
.instruction
|= inst
.operands
[0].reg
;
10097 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10098 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10102 do_iwmmxt_wrwrwr_or_imm5 (void)
10104 if (inst
.operands
[2].isreg
)
10107 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10108 _("immediate operand requires iWMMXt2"));
10110 if (inst
.operands
[2].imm
== 0)
10112 switch ((inst
.instruction
>> 20) & 0xf)
10118 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10119 inst
.operands
[2].imm
= 16;
10120 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10126 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10127 inst
.operands
[2].imm
= 32;
10128 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10135 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10137 wrn
= (inst
.instruction
>> 16) & 0xf;
10138 inst
.instruction
&= 0xff0fff0f;
10139 inst
.instruction
|= wrn
;
10140 /* Bail out here; the instruction is now assembled. */
10145 /* Map 32 -> 0, etc. */
10146 inst
.operands
[2].imm
&= 0x1f;
10147 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10151 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10152 operations first, then control, shift, and load/store. */
10154 /* Insns like "foo X,Y,Z". */
10157 do_mav_triple (void)
10159 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10160 inst
.instruction
|= inst
.operands
[1].reg
;
10161 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10164 /* Insns like "foo W,X,Y,Z".
10165 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10170 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10171 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10172 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10173 inst
.instruction
|= inst
.operands
[3].reg
;
10176 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10178 do_mav_dspsc (void)
10180 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10183 /* Maverick shift immediate instructions.
10184 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10185 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10188 do_mav_shift (void)
10190 int imm
= inst
.operands
[2].imm
;
10192 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10193 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10195 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10196 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10197 Bit 4 should be 0. */
10198 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10200 inst
.instruction
|= imm
;
10203 /* XScale instructions. Also sorted arithmetic before move. */
10205 /* Xscale multiply-accumulate (argument parse)
10208 MIAxycc acc0,Rm,Rs. */
10213 inst
.instruction
|= inst
.operands
[1].reg
;
10214 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10217 /* Xscale move-accumulator-register (argument parse)
10219 MARcc acc0,RdLo,RdHi. */
10224 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10225 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10228 /* Xscale move-register-accumulator (argument parse)
10230 MRAcc RdLo,RdHi,acc0. */
10235 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10236 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10237 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10240 /* Encoding functions relevant only to Thumb. */
10242 /* inst.operands[i] is a shifted-register operand; encode
10243 it into inst.instruction in the format used by Thumb32. */
10246 encode_thumb32_shifted_operand (int i
)
10248 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10249 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10251 constraint (inst
.operands
[i
].immisreg
,
10252 _("shift by register not allowed in thumb mode"));
10253 inst
.instruction
|= inst
.operands
[i
].reg
;
10254 if (shift
== SHIFT_RRX
)
10255 inst
.instruction
|= SHIFT_ROR
<< 4;
10258 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10259 _("expression too complex"));
10261 constraint (value
> 32
10262 || (value
== 32 && (shift
== SHIFT_LSL
10263 || shift
== SHIFT_ROR
)),
10264 _("shift expression is too large"));
10268 else if (value
== 32)
10271 inst
.instruction
|= shift
<< 4;
10272 inst
.instruction
|= (value
& 0x1c) << 10;
10273 inst
.instruction
|= (value
& 0x03) << 6;
10278 /* inst.operands[i] was set up by parse_address. Encode it into a
10279 Thumb32 format load or store instruction. Reject forms that cannot
10280 be used with such instructions. If is_t is true, reject forms that
10281 cannot be used with a T instruction; if is_d is true, reject forms
10282 that cannot be used with a D instruction. If it is a store insn,
10283 reject PC in Rn. */
10286 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10288 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10290 constraint (!inst
.operands
[i
].isreg
,
10291 _("Instruction does not support =N addresses"));
10293 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10294 if (inst
.operands
[i
].immisreg
)
10296 constraint (is_pc
, BAD_PC_ADDRESSING
);
10297 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10298 constraint (inst
.operands
[i
].negative
,
10299 _("Thumb does not support negative register indexing"));
10300 constraint (inst
.operands
[i
].postind
,
10301 _("Thumb does not support register post-indexing"));
10302 constraint (inst
.operands
[i
].writeback
,
10303 _("Thumb does not support register indexing with writeback"));
10304 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10305 _("Thumb supports only LSL in shifted register indexing"));
10307 inst
.instruction
|= inst
.operands
[i
].imm
;
10308 if (inst
.operands
[i
].shifted
)
10310 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10311 _("expression too complex"));
10312 constraint (inst
.reloc
.exp
.X_add_number
< 0
10313 || inst
.reloc
.exp
.X_add_number
> 3,
10314 _("shift out of range"));
10315 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10317 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10319 else if (inst
.operands
[i
].preind
)
10321 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10322 constraint (is_t
&& inst
.operands
[i
].writeback
,
10323 _("cannot use writeback with this instruction"));
10324 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10325 BAD_PC_ADDRESSING
);
10329 inst
.instruction
|= 0x01000000;
10330 if (inst
.operands
[i
].writeback
)
10331 inst
.instruction
|= 0x00200000;
10335 inst
.instruction
|= 0x00000c00;
10336 if (inst
.operands
[i
].writeback
)
10337 inst
.instruction
|= 0x00000100;
10339 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10341 else if (inst
.operands
[i
].postind
)
10343 gas_assert (inst
.operands
[i
].writeback
);
10344 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10345 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10348 inst
.instruction
|= 0x00200000;
10350 inst
.instruction
|= 0x00000900;
10351 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10353 else /* unindexed - only for coprocessor */
10354 inst
.error
= _("instruction does not accept unindexed addressing");
10357 /* Table of Thumb instructions which exist in both 16- and 32-bit
10358 encodings (the latter only in post-V6T2 cores). The index is the
10359 value used in the insns table below. When there is more than one
10360 possible 16-bit encoding for the instruction, this table always
10362 Also contains several pseudo-instructions used during relaxation. */
10363 #define T16_32_TAB \
10364 X(_adc, 4140, eb400000), \
10365 X(_adcs, 4140, eb500000), \
10366 X(_add, 1c00, eb000000), \
10367 X(_adds, 1c00, eb100000), \
10368 X(_addi, 0000, f1000000), \
10369 X(_addis, 0000, f1100000), \
10370 X(_add_pc,000f, f20f0000), \
10371 X(_add_sp,000d, f10d0000), \
10372 X(_adr, 000f, f20f0000), \
10373 X(_and, 4000, ea000000), \
10374 X(_ands, 4000, ea100000), \
10375 X(_asr, 1000, fa40f000), \
10376 X(_asrs, 1000, fa50f000), \
10377 X(_b, e000, f000b000), \
10378 X(_bcond, d000, f0008000), \
10379 X(_bic, 4380, ea200000), \
10380 X(_bics, 4380, ea300000), \
10381 X(_cmn, 42c0, eb100f00), \
10382 X(_cmp, 2800, ebb00f00), \
10383 X(_cpsie, b660, f3af8400), \
10384 X(_cpsid, b670, f3af8600), \
10385 X(_cpy, 4600, ea4f0000), \
10386 X(_dec_sp,80dd, f1ad0d00), \
10387 X(_eor, 4040, ea800000), \
10388 X(_eors, 4040, ea900000), \
10389 X(_inc_sp,00dd, f10d0d00), \
10390 X(_ldmia, c800, e8900000), \
10391 X(_ldr, 6800, f8500000), \
10392 X(_ldrb, 7800, f8100000), \
10393 X(_ldrh, 8800, f8300000), \
10394 X(_ldrsb, 5600, f9100000), \
10395 X(_ldrsh, 5e00, f9300000), \
10396 X(_ldr_pc,4800, f85f0000), \
10397 X(_ldr_pc2,4800, f85f0000), \
10398 X(_ldr_sp,9800, f85d0000), \
10399 X(_lsl, 0000, fa00f000), \
10400 X(_lsls, 0000, fa10f000), \
10401 X(_lsr, 0800, fa20f000), \
10402 X(_lsrs, 0800, fa30f000), \
10403 X(_mov, 2000, ea4f0000), \
10404 X(_movs, 2000, ea5f0000), \
10405 X(_mul, 4340, fb00f000), \
10406 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10407 X(_mvn, 43c0, ea6f0000), \
10408 X(_mvns, 43c0, ea7f0000), \
10409 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10410 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10411 X(_orr, 4300, ea400000), \
10412 X(_orrs, 4300, ea500000), \
10413 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10414 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10415 X(_rev, ba00, fa90f080), \
10416 X(_rev16, ba40, fa90f090), \
10417 X(_revsh, bac0, fa90f0b0), \
10418 X(_ror, 41c0, fa60f000), \
10419 X(_rors, 41c0, fa70f000), \
10420 X(_sbc, 4180, eb600000), \
10421 X(_sbcs, 4180, eb700000), \
10422 X(_stmia, c000, e8800000), \
10423 X(_str, 6000, f8400000), \
10424 X(_strb, 7000, f8000000), \
10425 X(_strh, 8000, f8200000), \
10426 X(_str_sp,9000, f84d0000), \
10427 X(_sub, 1e00, eba00000), \
10428 X(_subs, 1e00, ebb00000), \
10429 X(_subi, 8000, f1a00000), \
10430 X(_subis, 8000, f1b00000), \
10431 X(_sxtb, b240, fa4ff080), \
10432 X(_sxth, b200, fa0ff080), \
10433 X(_tst, 4200, ea100f00), \
10434 X(_uxtb, b2c0, fa5ff080), \
10435 X(_uxth, b280, fa1ff080), \
10436 X(_nop, bf00, f3af8000), \
10437 X(_yield, bf10, f3af8001), \
10438 X(_wfe, bf20, f3af8002), \
10439 X(_wfi, bf30, f3af8003), \
10440 X(_sev, bf40, f3af8004), \
10441 X(_sevl, bf50, f3af8005), \
10442 X(_udf, de00, f7f0a000)
10444 /* To catch errors in encoding functions, the codes are all offset by
10445 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10446 as 16-bit instructions. */
10447 #define X(a,b,c) T_MNEM##a
10448 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10451 #define X(a,b,c) 0x##b
10452 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10453 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10456 #define X(a,b,c) 0x##c
10457 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10458 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10459 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10463 /* Thumb instruction encoders, in alphabetical order. */
10465 /* ADDW or SUBW. */
10468 do_t_add_sub_w (void)
10472 Rd
= inst
.operands
[0].reg
;
10473 Rn
= inst
.operands
[1].reg
;
10475 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10476 is the SP-{plus,minus}-immediate form of the instruction. */
10478 constraint (Rd
== REG_PC
, BAD_PC
);
10480 reject_bad_reg (Rd
);
10482 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10483 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10486 /* Parse an add or subtract instruction. We get here with inst.instruction
10487 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10490 do_t_add_sub (void)
10494 Rd
= inst
.operands
[0].reg
;
10495 Rs
= (inst
.operands
[1].present
10496 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10497 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10500 set_it_insn_type_last ();
10502 if (unified_syntax
)
10505 bfd_boolean narrow
;
10508 flags
= (inst
.instruction
== T_MNEM_adds
10509 || inst
.instruction
== T_MNEM_subs
);
10511 narrow
= !in_it_block ();
10513 narrow
= in_it_block ();
10514 if (!inst
.operands
[2].isreg
)
10518 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10520 add
= (inst
.instruction
== T_MNEM_add
10521 || inst
.instruction
== T_MNEM_adds
);
10523 if (inst
.size_req
!= 4)
10525 /* Attempt to use a narrow opcode, with relaxation if
10527 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10528 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10529 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10530 opcode
= T_MNEM_add_sp
;
10531 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10532 opcode
= T_MNEM_add_pc
;
10533 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10536 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10538 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10542 inst
.instruction
= THUMB_OP16(opcode
);
10543 inst
.instruction
|= (Rd
<< 4) | Rs
;
10544 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10545 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10547 if (inst
.size_req
== 2)
10548 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10550 inst
.relax
= opcode
;
10554 constraint (inst
.size_req
== 2, BAD_HIREG
);
10556 if (inst
.size_req
== 4
10557 || (inst
.size_req
!= 2 && !opcode
))
10559 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10560 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10561 THUMB1_RELOC_ONLY
);
10564 constraint (add
, BAD_PC
);
10565 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10566 _("only SUBS PC, LR, #const allowed"));
10567 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10568 _("expression too complex"));
10569 constraint (inst
.reloc
.exp
.X_add_number
< 0
10570 || inst
.reloc
.exp
.X_add_number
> 0xff,
10571 _("immediate value out of range"));
10572 inst
.instruction
= T2_SUBS_PC_LR
10573 | inst
.reloc
.exp
.X_add_number
;
10574 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10577 else if (Rs
== REG_PC
)
10579 /* Always use addw/subw. */
10580 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10581 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10585 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10586 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10589 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10591 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10593 inst
.instruction
|= Rd
<< 8;
10594 inst
.instruction
|= Rs
<< 16;
10599 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10600 unsigned int shift
= inst
.operands
[2].shift_kind
;
10602 Rn
= inst
.operands
[2].reg
;
10603 /* See if we can do this with a 16-bit instruction. */
10604 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10606 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10611 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10612 || inst
.instruction
== T_MNEM_add
)
10614 : T_OPCODE_SUB_R3
);
10615 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10619 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10621 /* Thumb-1 cores (except v6-M) require at least one high
10622 register in a narrow non flag setting add. */
10623 if (Rd
> 7 || Rn
> 7
10624 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10625 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10632 inst
.instruction
= T_OPCODE_ADD_HI
;
10633 inst
.instruction
|= (Rd
& 8) << 4;
10634 inst
.instruction
|= (Rd
& 7);
10635 inst
.instruction
|= Rn
<< 3;
10641 constraint (Rd
== REG_PC
, BAD_PC
);
10642 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10643 constraint (Rs
== REG_PC
, BAD_PC
);
10644 reject_bad_reg (Rn
);
10646 /* If we get here, it can't be done in 16 bits. */
10647 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10648 _("shift must be constant"));
10649 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10650 inst
.instruction
|= Rd
<< 8;
10651 inst
.instruction
|= Rs
<< 16;
10652 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10653 _("shift value over 3 not allowed in thumb mode"));
10654 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10655 _("only LSL shift allowed in thumb mode"));
10656 encode_thumb32_shifted_operand (2);
10661 constraint (inst
.instruction
== T_MNEM_adds
10662 || inst
.instruction
== T_MNEM_subs
,
10665 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10667 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10668 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10671 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10672 ? 0x0000 : 0x8000);
10673 inst
.instruction
|= (Rd
<< 4) | Rs
;
10674 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10678 Rn
= inst
.operands
[2].reg
;
10679 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10681 /* We now have Rd, Rs, and Rn set to registers. */
10682 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10684 /* Can't do this for SUB. */
10685 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10686 inst
.instruction
= T_OPCODE_ADD_HI
;
10687 inst
.instruction
|= (Rd
& 8) << 4;
10688 inst
.instruction
|= (Rd
& 7);
10690 inst
.instruction
|= Rn
<< 3;
10692 inst
.instruction
|= Rs
<< 3;
10694 constraint (1, _("dest must overlap one source register"));
10698 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10699 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10700 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10710 Rd
= inst
.operands
[0].reg
;
10711 reject_bad_reg (Rd
);
10713 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10715 /* Defer to section relaxation. */
10716 inst
.relax
= inst
.instruction
;
10717 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10718 inst
.instruction
|= Rd
<< 4;
10720 else if (unified_syntax
&& inst
.size_req
!= 2)
10722 /* Generate a 32-bit opcode. */
10723 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10724 inst
.instruction
|= Rd
<< 8;
10725 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10726 inst
.reloc
.pc_rel
= 1;
10730 /* Generate a 16-bit opcode. */
10731 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10732 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10733 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10734 inst
.reloc
.pc_rel
= 1;
10736 inst
.instruction
|= Rd
<< 4;
10740 /* Arithmetic instructions for which there is just one 16-bit
10741 instruction encoding, and it allows only two low registers.
10742 For maximal compatibility with ARM syntax, we allow three register
10743 operands even when Thumb-32 instructions are not available, as long
10744 as the first two are identical. For instance, both "sbc r0,r1" and
10745 "sbc r0,r0,r1" are allowed. */
10751 Rd
= inst
.operands
[0].reg
;
10752 Rs
= (inst
.operands
[1].present
10753 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10754 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10755 Rn
= inst
.operands
[2].reg
;
10757 reject_bad_reg (Rd
);
10758 reject_bad_reg (Rs
);
10759 if (inst
.operands
[2].isreg
)
10760 reject_bad_reg (Rn
);
10762 if (unified_syntax
)
10764 if (!inst
.operands
[2].isreg
)
10766 /* For an immediate, we always generate a 32-bit opcode;
10767 section relaxation will shrink it later if possible. */
10768 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10769 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10770 inst
.instruction
|= Rd
<< 8;
10771 inst
.instruction
|= Rs
<< 16;
10772 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10776 bfd_boolean narrow
;
10778 /* See if we can do this with a 16-bit instruction. */
10779 if (THUMB_SETS_FLAGS (inst
.instruction
))
10780 narrow
= !in_it_block ();
10782 narrow
= in_it_block ();
10784 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10786 if (inst
.operands
[2].shifted
)
10788 if (inst
.size_req
== 4)
10794 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10795 inst
.instruction
|= Rd
;
10796 inst
.instruction
|= Rn
<< 3;
10800 /* If we get here, it can't be done in 16 bits. */
10801 constraint (inst
.operands
[2].shifted
10802 && inst
.operands
[2].immisreg
,
10803 _("shift must be constant"));
10804 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10805 inst
.instruction
|= Rd
<< 8;
10806 inst
.instruction
|= Rs
<< 16;
10807 encode_thumb32_shifted_operand (2);
10812 /* On its face this is a lie - the instruction does set the
10813 flags. However, the only supported mnemonic in this mode
10814 says it doesn't. */
10815 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10817 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10818 _("unshifted register required"));
10819 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10820 constraint (Rd
!= Rs
,
10821 _("dest and source1 must be the same register"));
10823 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10824 inst
.instruction
|= Rd
;
10825 inst
.instruction
|= Rn
<< 3;
10829 /* Similarly, but for instructions where the arithmetic operation is
10830 commutative, so we can allow either of them to be different from
10831 the destination operand in a 16-bit instruction. For instance, all
10832 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10839 Rd
= inst
.operands
[0].reg
;
10840 Rs
= (inst
.operands
[1].present
10841 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10842 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10843 Rn
= inst
.operands
[2].reg
;
10845 reject_bad_reg (Rd
);
10846 reject_bad_reg (Rs
);
10847 if (inst
.operands
[2].isreg
)
10848 reject_bad_reg (Rn
);
10850 if (unified_syntax
)
10852 if (!inst
.operands
[2].isreg
)
10854 /* For an immediate, we always generate a 32-bit opcode;
10855 section relaxation will shrink it later if possible. */
10856 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10857 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10858 inst
.instruction
|= Rd
<< 8;
10859 inst
.instruction
|= Rs
<< 16;
10860 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10864 bfd_boolean narrow
;
10866 /* See if we can do this with a 16-bit instruction. */
10867 if (THUMB_SETS_FLAGS (inst
.instruction
))
10868 narrow
= !in_it_block ();
10870 narrow
= in_it_block ();
10872 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10874 if (inst
.operands
[2].shifted
)
10876 if (inst
.size_req
== 4)
10883 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10884 inst
.instruction
|= Rd
;
10885 inst
.instruction
|= Rn
<< 3;
10890 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10891 inst
.instruction
|= Rd
;
10892 inst
.instruction
|= Rs
<< 3;
10897 /* If we get here, it can't be done in 16 bits. */
10898 constraint (inst
.operands
[2].shifted
10899 && inst
.operands
[2].immisreg
,
10900 _("shift must be constant"));
10901 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10902 inst
.instruction
|= Rd
<< 8;
10903 inst
.instruction
|= Rs
<< 16;
10904 encode_thumb32_shifted_operand (2);
10909 /* On its face this is a lie - the instruction does set the
10910 flags. However, the only supported mnemonic in this mode
10911 says it doesn't. */
10912 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10914 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10915 _("unshifted register required"));
10916 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10918 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10919 inst
.instruction
|= Rd
;
10922 inst
.instruction
|= Rn
<< 3;
10924 inst
.instruction
|= Rs
<< 3;
10926 constraint (1, _("dest must overlap one source register"));
10934 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10935 constraint (msb
> 32, _("bit-field extends past end of register"));
10936 /* The instruction encoding stores the LSB and MSB,
10937 not the LSB and width. */
10938 Rd
= inst
.operands
[0].reg
;
10939 reject_bad_reg (Rd
);
10940 inst
.instruction
|= Rd
<< 8;
10941 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10942 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10943 inst
.instruction
|= msb
- 1;
10952 Rd
= inst
.operands
[0].reg
;
10953 reject_bad_reg (Rd
);
10955 /* #0 in second position is alternative syntax for bfc, which is
10956 the same instruction but with REG_PC in the Rm field. */
10957 if (!inst
.operands
[1].isreg
)
10961 Rn
= inst
.operands
[1].reg
;
10962 reject_bad_reg (Rn
);
10965 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10966 constraint (msb
> 32, _("bit-field extends past end of register"));
10967 /* The instruction encoding stores the LSB and MSB,
10968 not the LSB and width. */
10969 inst
.instruction
|= Rd
<< 8;
10970 inst
.instruction
|= Rn
<< 16;
10971 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10972 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10973 inst
.instruction
|= msb
- 1;
10981 Rd
= inst
.operands
[0].reg
;
10982 Rn
= inst
.operands
[1].reg
;
10984 reject_bad_reg (Rd
);
10985 reject_bad_reg (Rn
);
10987 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10988 _("bit-field extends past end of register"));
10989 inst
.instruction
|= Rd
<< 8;
10990 inst
.instruction
|= Rn
<< 16;
10991 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10992 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10993 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10996 /* ARM V5 Thumb BLX (argument parse)
10997 BLX <target_addr> which is BLX(1)
10998 BLX <Rm> which is BLX(2)
10999 Unfortunately, there are two different opcodes for this mnemonic.
11000 So, the insns[].value is not used, and the code here zaps values
11001 into inst.instruction.
11003 ??? How to take advantage of the additional two bits of displacement
11004 available in Thumb32 mode? Need new relocation? */
11009 set_it_insn_type_last ();
11011 if (inst
.operands
[0].isreg
)
11013 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11014 /* We have a register, so this is BLX(2). */
11015 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11019 /* No register. This must be BLX(1). */
11020 inst
.instruction
= 0xf000e800;
11021 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11030 bfd_reloc_code_real_type reloc
;
11033 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11035 if (in_it_block ())
11037 /* Conditional branches inside IT blocks are encoded as unconditional
11039 cond
= COND_ALWAYS
;
11044 if (cond
!= COND_ALWAYS
)
11045 opcode
= T_MNEM_bcond
;
11047 opcode
= inst
.instruction
;
11050 && (inst
.size_req
== 4
11051 || (inst
.size_req
!= 2
11052 && (inst
.operands
[0].hasreloc
11053 || inst
.reloc
.exp
.X_op
== O_constant
))))
11055 inst
.instruction
= THUMB_OP32(opcode
);
11056 if (cond
== COND_ALWAYS
)
11057 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11060 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11061 _("selected architecture does not support "
11062 "wide conditional branch instruction"));
11064 gas_assert (cond
!= 0xF);
11065 inst
.instruction
|= cond
<< 22;
11066 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11071 inst
.instruction
= THUMB_OP16(opcode
);
11072 if (cond
== COND_ALWAYS
)
11073 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11076 inst
.instruction
|= cond
<< 8;
11077 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11079 /* Allow section relaxation. */
11080 if (unified_syntax
&& inst
.size_req
!= 2)
11081 inst
.relax
= opcode
;
11083 inst
.reloc
.type
= reloc
;
11084 inst
.reloc
.pc_rel
= 1;
11087 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11088 between the two is the maximum immediate allowed - which is passed in
11091 do_t_bkpt_hlt1 (int range
)
11093 constraint (inst
.cond
!= COND_ALWAYS
,
11094 _("instruction is always unconditional"));
11095 if (inst
.operands
[0].present
)
11097 constraint (inst
.operands
[0].imm
> range
,
11098 _("immediate value out of range"));
11099 inst
.instruction
|= inst
.operands
[0].imm
;
11102 set_it_insn_type (NEUTRAL_IT_INSN
);
11108 do_t_bkpt_hlt1 (63);
11114 do_t_bkpt_hlt1 (255);
11118 do_t_branch23 (void)
11120 set_it_insn_type_last ();
11121 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11123 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11124 this file. We used to simply ignore the PLT reloc type here --
11125 the branch encoding is now needed to deal with TLSCALL relocs.
11126 So if we see a PLT reloc now, put it back to how it used to be to
11127 keep the preexisting behaviour. */
11128 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11129 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11131 #if defined(OBJ_COFF)
11132 /* If the destination of the branch is a defined symbol which does not have
11133 the THUMB_FUNC attribute, then we must be calling a function which has
11134 the (interfacearm) attribute. We look for the Thumb entry point to that
11135 function and change the branch to refer to that function instead. */
11136 if ( inst
.reloc
.exp
.X_op
== O_symbol
11137 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11138 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11139 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11140 inst
.reloc
.exp
.X_add_symbol
=
11141 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11148 set_it_insn_type_last ();
11149 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11150 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11151 should cause the alignment to be checked once it is known. This is
11152 because BX PC only works if the instruction is word aligned. */
11160 set_it_insn_type_last ();
11161 Rm
= inst
.operands
[0].reg
;
11162 reject_bad_reg (Rm
);
11163 inst
.instruction
|= Rm
<< 16;
11172 Rd
= inst
.operands
[0].reg
;
11173 Rm
= inst
.operands
[1].reg
;
11175 reject_bad_reg (Rd
);
11176 reject_bad_reg (Rm
);
11178 inst
.instruction
|= Rd
<< 8;
11179 inst
.instruction
|= Rm
<< 16;
11180 inst
.instruction
|= Rm
;
11186 set_it_insn_type (OUTSIDE_IT_INSN
);
11187 inst
.instruction
|= inst
.operands
[0].imm
;
11193 set_it_insn_type (OUTSIDE_IT_INSN
);
11195 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11196 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11198 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11199 inst
.instruction
= 0xf3af8000;
11200 inst
.instruction
|= imod
<< 9;
11201 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11202 if (inst
.operands
[1].present
)
11203 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11207 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11208 && (inst
.operands
[0].imm
& 4),
11209 _("selected processor does not support 'A' form "
11210 "of this instruction"));
11211 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11212 _("Thumb does not support the 2-argument "
11213 "form of this instruction"));
11214 inst
.instruction
|= inst
.operands
[0].imm
;
11218 /* THUMB CPY instruction (argument parse). */
11223 if (inst
.size_req
== 4)
11225 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11226 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11227 inst
.instruction
|= inst
.operands
[1].reg
;
11231 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11232 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11233 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11240 set_it_insn_type (OUTSIDE_IT_INSN
);
11241 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11242 inst
.instruction
|= inst
.operands
[0].reg
;
11243 inst
.reloc
.pc_rel
= 1;
11244 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11250 inst
.instruction
|= inst
.operands
[0].imm
;
11256 unsigned Rd
, Rn
, Rm
;
11258 Rd
= inst
.operands
[0].reg
;
11259 Rn
= (inst
.operands
[1].present
11260 ? inst
.operands
[1].reg
: Rd
);
11261 Rm
= inst
.operands
[2].reg
;
11263 reject_bad_reg (Rd
);
11264 reject_bad_reg (Rn
);
11265 reject_bad_reg (Rm
);
11267 inst
.instruction
|= Rd
<< 8;
11268 inst
.instruction
|= Rn
<< 16;
11269 inst
.instruction
|= Rm
;
11275 if (unified_syntax
&& inst
.size_req
== 4)
11276 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11278 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11284 unsigned int cond
= inst
.operands
[0].imm
;
11286 set_it_insn_type (IT_INSN
);
11287 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11289 now_it
.warn_deprecated
= FALSE
;
11291 /* If the condition is a negative condition, invert the mask. */
11292 if ((cond
& 0x1) == 0x0)
11294 unsigned int mask
= inst
.instruction
& 0x000f;
11296 if ((mask
& 0x7) == 0)
11298 /* No conversion needed. */
11299 now_it
.block_length
= 1;
11301 else if ((mask
& 0x3) == 0)
11304 now_it
.block_length
= 2;
11306 else if ((mask
& 0x1) == 0)
11309 now_it
.block_length
= 3;
11314 now_it
.block_length
= 4;
11317 inst
.instruction
&= 0xfff0;
11318 inst
.instruction
|= mask
;
11321 inst
.instruction
|= cond
<< 4;
11324 /* Helper function used for both push/pop and ldm/stm. */
11326 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11330 load
= (inst
.instruction
& (1 << 20)) != 0;
11332 if (mask
& (1 << 13))
11333 inst
.error
= _("SP not allowed in register list");
11335 if ((mask
& (1 << base
)) != 0
11337 inst
.error
= _("having the base register in the register list when "
11338 "using write back is UNPREDICTABLE");
11342 if (mask
& (1 << 15))
11344 if (mask
& (1 << 14))
11345 inst
.error
= _("LR and PC should not both be in register list");
11347 set_it_insn_type_last ();
11352 if (mask
& (1 << 15))
11353 inst
.error
= _("PC not allowed in register list");
11356 if ((mask
& (mask
- 1)) == 0)
11358 /* Single register transfers implemented as str/ldr. */
11361 if (inst
.instruction
& (1 << 23))
11362 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11364 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11368 if (inst
.instruction
& (1 << 23))
11369 inst
.instruction
= 0x00800000; /* ia -> [base] */
11371 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11374 inst
.instruction
|= 0xf8400000;
11376 inst
.instruction
|= 0x00100000;
11378 mask
= ffs (mask
) - 1;
11381 else if (writeback
)
11382 inst
.instruction
|= WRITE_BACK
;
11384 inst
.instruction
|= mask
;
11385 inst
.instruction
|= base
<< 16;
11391 /* This really doesn't seem worth it. */
11392 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11393 _("expression too complex"));
11394 constraint (inst
.operands
[1].writeback
,
11395 _("Thumb load/store multiple does not support {reglist}^"));
11397 if (unified_syntax
)
11399 bfd_boolean narrow
;
11403 /* See if we can use a 16-bit instruction. */
11404 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11405 && inst
.size_req
!= 4
11406 && !(inst
.operands
[1].imm
& ~0xff))
11408 mask
= 1 << inst
.operands
[0].reg
;
11410 if (inst
.operands
[0].reg
<= 7)
11412 if (inst
.instruction
== T_MNEM_stmia
11413 ? inst
.operands
[0].writeback
11414 : (inst
.operands
[0].writeback
11415 == !(inst
.operands
[1].imm
& mask
)))
11417 if (inst
.instruction
== T_MNEM_stmia
11418 && (inst
.operands
[1].imm
& mask
)
11419 && (inst
.operands
[1].imm
& (mask
- 1)))
11420 as_warn (_("value stored for r%d is UNKNOWN"),
11421 inst
.operands
[0].reg
);
11423 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11424 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11425 inst
.instruction
|= inst
.operands
[1].imm
;
11428 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11430 /* This means 1 register in reg list one of 3 situations:
11431 1. Instruction is stmia, but without writeback.
11432 2. lmdia without writeback, but with Rn not in
11434 3. ldmia with writeback, but with Rn in reglist.
11435 Case 3 is UNPREDICTABLE behaviour, so we handle
11436 case 1 and 2 which can be converted into a 16-bit
11437 str or ldr. The SP cases are handled below. */
11438 unsigned long opcode
;
11439 /* First, record an error for Case 3. */
11440 if (inst
.operands
[1].imm
& mask
11441 && inst
.operands
[0].writeback
)
11443 _("having the base register in the register list when "
11444 "using write back is UNPREDICTABLE");
11446 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11448 inst
.instruction
= THUMB_OP16 (opcode
);
11449 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11450 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11454 else if (inst
.operands
[0] .reg
== REG_SP
)
11456 if (inst
.operands
[0].writeback
)
11459 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11460 ? T_MNEM_push
: T_MNEM_pop
);
11461 inst
.instruction
|= inst
.operands
[1].imm
;
11464 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11467 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11468 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11469 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11477 if (inst
.instruction
< 0xffff)
11478 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11480 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11481 inst
.operands
[0].writeback
);
11486 constraint (inst
.operands
[0].reg
> 7
11487 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11488 constraint (inst
.instruction
!= T_MNEM_ldmia
11489 && inst
.instruction
!= T_MNEM_stmia
,
11490 _("Thumb-2 instruction only valid in unified syntax"));
11491 if (inst
.instruction
== T_MNEM_stmia
)
11493 if (!inst
.operands
[0].writeback
)
11494 as_warn (_("this instruction will write back the base register"));
11495 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11496 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11497 as_warn (_("value stored for r%d is UNKNOWN"),
11498 inst
.operands
[0].reg
);
11502 if (!inst
.operands
[0].writeback
11503 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11504 as_warn (_("this instruction will write back the base register"));
11505 else if (inst
.operands
[0].writeback
11506 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11507 as_warn (_("this instruction will not write back the base register"));
11510 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11511 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11512 inst
.instruction
|= inst
.operands
[1].imm
;
11519 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11520 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11521 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11522 || inst
.operands
[1].negative
,
11525 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11527 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11528 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11529 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11535 if (!inst
.operands
[1].present
)
11537 constraint (inst
.operands
[0].reg
== REG_LR
,
11538 _("r14 not allowed as first register "
11539 "when second register is omitted"));
11540 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11542 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11545 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11546 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11547 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11553 unsigned long opcode
;
11556 if (inst
.operands
[0].isreg
11557 && !inst
.operands
[0].preind
11558 && inst
.operands
[0].reg
== REG_PC
)
11559 set_it_insn_type_last ();
11561 opcode
= inst
.instruction
;
11562 if (unified_syntax
)
11564 if (!inst
.operands
[1].isreg
)
11566 if (opcode
<= 0xffff)
11567 inst
.instruction
= THUMB_OP32 (opcode
);
11568 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11571 if (inst
.operands
[1].isreg
11572 && !inst
.operands
[1].writeback
11573 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11574 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11575 && opcode
<= 0xffff
11576 && inst
.size_req
!= 4)
11578 /* Insn may have a 16-bit form. */
11579 Rn
= inst
.operands
[1].reg
;
11580 if (inst
.operands
[1].immisreg
)
11582 inst
.instruction
= THUMB_OP16 (opcode
);
11584 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11586 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11587 reject_bad_reg (inst
.operands
[1].imm
);
11589 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11590 && opcode
!= T_MNEM_ldrsb
)
11591 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11592 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11599 if (inst
.reloc
.pc_rel
)
11600 opcode
= T_MNEM_ldr_pc2
;
11602 opcode
= T_MNEM_ldr_pc
;
11606 if (opcode
== T_MNEM_ldr
)
11607 opcode
= T_MNEM_ldr_sp
;
11609 opcode
= T_MNEM_str_sp
;
11611 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11615 inst
.instruction
= inst
.operands
[0].reg
;
11616 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11618 inst
.instruction
|= THUMB_OP16 (opcode
);
11619 if (inst
.size_req
== 2)
11620 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11622 inst
.relax
= opcode
;
11626 /* Definitely a 32-bit variant. */
11628 /* Warning for Erratum 752419. */
11629 if (opcode
== T_MNEM_ldr
11630 && inst
.operands
[0].reg
== REG_SP
11631 && inst
.operands
[1].writeback
== 1
11632 && !inst
.operands
[1].immisreg
)
11634 if (no_cpu_selected ()
11635 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11636 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11637 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11638 as_warn (_("This instruction may be unpredictable "
11639 "if executed on M-profile cores "
11640 "with interrupts enabled."));
11643 /* Do some validations regarding addressing modes. */
11644 if (inst
.operands
[1].immisreg
)
11645 reject_bad_reg (inst
.operands
[1].imm
);
11647 constraint (inst
.operands
[1].writeback
== 1
11648 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11651 inst
.instruction
= THUMB_OP32 (opcode
);
11652 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11653 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11654 check_ldr_r15_aligned ();
11658 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11660 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11662 /* Only [Rn,Rm] is acceptable. */
11663 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11664 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11665 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11666 || inst
.operands
[1].negative
,
11667 _("Thumb does not support this addressing mode"));
11668 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11672 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11673 if (!inst
.operands
[1].isreg
)
11674 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11677 constraint (!inst
.operands
[1].preind
11678 || inst
.operands
[1].shifted
11679 || inst
.operands
[1].writeback
,
11680 _("Thumb does not support this addressing mode"));
11681 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11683 constraint (inst
.instruction
& 0x0600,
11684 _("byte or halfword not valid for base register"));
11685 constraint (inst
.operands
[1].reg
== REG_PC
11686 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11687 _("r15 based store not allowed"));
11688 constraint (inst
.operands
[1].immisreg
,
11689 _("invalid base register for register offset"));
11691 if (inst
.operands
[1].reg
== REG_PC
)
11692 inst
.instruction
= T_OPCODE_LDR_PC
;
11693 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11694 inst
.instruction
= T_OPCODE_LDR_SP
;
11696 inst
.instruction
= T_OPCODE_STR_SP
;
11698 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11699 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11703 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11704 if (!inst
.operands
[1].immisreg
)
11706 /* Immediate offset. */
11707 inst
.instruction
|= inst
.operands
[0].reg
;
11708 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11709 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11713 /* Register offset. */
11714 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11715 constraint (inst
.operands
[1].negative
,
11716 _("Thumb does not support this addressing mode"));
11719 switch (inst
.instruction
)
11721 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11722 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11723 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11724 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11725 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11726 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11727 case 0x5600 /* ldrsb */:
11728 case 0x5e00 /* ldrsh */: break;
11732 inst
.instruction
|= inst
.operands
[0].reg
;
11733 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11734 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11740 if (!inst
.operands
[1].present
)
11742 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11743 constraint (inst
.operands
[0].reg
== REG_LR
,
11744 _("r14 not allowed here"));
11745 constraint (inst
.operands
[0].reg
== REG_R12
,
11746 _("r12 not allowed here"));
11749 if (inst
.operands
[2].writeback
11750 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11751 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11752 as_warn (_("base register written back, and overlaps "
11753 "one of transfer registers"));
11755 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11756 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11757 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11763 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11764 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11770 unsigned Rd
, Rn
, Rm
, Ra
;
11772 Rd
= inst
.operands
[0].reg
;
11773 Rn
= inst
.operands
[1].reg
;
11774 Rm
= inst
.operands
[2].reg
;
11775 Ra
= inst
.operands
[3].reg
;
11777 reject_bad_reg (Rd
);
11778 reject_bad_reg (Rn
);
11779 reject_bad_reg (Rm
);
11780 reject_bad_reg (Ra
);
11782 inst
.instruction
|= Rd
<< 8;
11783 inst
.instruction
|= Rn
<< 16;
11784 inst
.instruction
|= Rm
;
11785 inst
.instruction
|= Ra
<< 12;
11791 unsigned RdLo
, RdHi
, Rn
, Rm
;
11793 RdLo
= inst
.operands
[0].reg
;
11794 RdHi
= inst
.operands
[1].reg
;
11795 Rn
= inst
.operands
[2].reg
;
11796 Rm
= inst
.operands
[3].reg
;
11798 reject_bad_reg (RdLo
);
11799 reject_bad_reg (RdHi
);
11800 reject_bad_reg (Rn
);
11801 reject_bad_reg (Rm
);
11803 inst
.instruction
|= RdLo
<< 12;
11804 inst
.instruction
|= RdHi
<< 8;
11805 inst
.instruction
|= Rn
<< 16;
11806 inst
.instruction
|= Rm
;
11810 do_t_mov_cmp (void)
11814 Rn
= inst
.operands
[0].reg
;
11815 Rm
= inst
.operands
[1].reg
;
11818 set_it_insn_type_last ();
11820 if (unified_syntax
)
11822 int r0off
= (inst
.instruction
== T_MNEM_mov
11823 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11824 unsigned long opcode
;
11825 bfd_boolean narrow
;
11826 bfd_boolean low_regs
;
11828 low_regs
= (Rn
<= 7 && Rm
<= 7);
11829 opcode
= inst
.instruction
;
11830 if (in_it_block ())
11831 narrow
= opcode
!= T_MNEM_movs
;
11833 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11834 if (inst
.size_req
== 4
11835 || inst
.operands
[1].shifted
)
11838 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11839 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11840 && !inst
.operands
[1].shifted
11844 inst
.instruction
= T2_SUBS_PC_LR
;
11848 if (opcode
== T_MNEM_cmp
)
11850 constraint (Rn
== REG_PC
, BAD_PC
);
11853 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11855 warn_deprecated_sp (Rm
);
11856 /* R15 was documented as a valid choice for Rm in ARMv6,
11857 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11858 tools reject R15, so we do too. */
11859 constraint (Rm
== REG_PC
, BAD_PC
);
11862 reject_bad_reg (Rm
);
11864 else if (opcode
== T_MNEM_mov
11865 || opcode
== T_MNEM_movs
)
11867 if (inst
.operands
[1].isreg
)
11869 if (opcode
== T_MNEM_movs
)
11871 reject_bad_reg (Rn
);
11872 reject_bad_reg (Rm
);
11876 /* This is mov.n. */
11877 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11878 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11880 as_tsktsk (_("Use of r%u as a source register is "
11881 "deprecated when r%u is the destination "
11882 "register."), Rm
, Rn
);
11887 /* This is mov.w. */
11888 constraint (Rn
== REG_PC
, BAD_PC
);
11889 constraint (Rm
== REG_PC
, BAD_PC
);
11890 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11894 reject_bad_reg (Rn
);
11897 if (!inst
.operands
[1].isreg
)
11899 /* Immediate operand. */
11900 if (!in_it_block () && opcode
== T_MNEM_mov
)
11902 if (low_regs
&& narrow
)
11904 inst
.instruction
= THUMB_OP16 (opcode
);
11905 inst
.instruction
|= Rn
<< 8;
11906 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11907 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11909 if (inst
.size_req
== 2)
11910 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11912 inst
.relax
= opcode
;
11917 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11918 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11919 THUMB1_RELOC_ONLY
);
11921 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11922 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11923 inst
.instruction
|= Rn
<< r0off
;
11924 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11927 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11928 && (inst
.instruction
== T_MNEM_mov
11929 || inst
.instruction
== T_MNEM_movs
))
11931 /* Register shifts are encoded as separate shift instructions. */
11932 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11934 if (in_it_block ())
11939 if (inst
.size_req
== 4)
11942 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11948 switch (inst
.operands
[1].shift_kind
)
11951 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11954 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11957 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11960 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11966 inst
.instruction
= opcode
;
11969 inst
.instruction
|= Rn
;
11970 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11975 inst
.instruction
|= CONDS_BIT
;
11977 inst
.instruction
|= Rn
<< 8;
11978 inst
.instruction
|= Rm
<< 16;
11979 inst
.instruction
|= inst
.operands
[1].imm
;
11984 /* Some mov with immediate shift have narrow variants.
11985 Register shifts are handled above. */
11986 if (low_regs
&& inst
.operands
[1].shifted
11987 && (inst
.instruction
== T_MNEM_mov
11988 || inst
.instruction
== T_MNEM_movs
))
11990 if (in_it_block ())
11991 narrow
= (inst
.instruction
== T_MNEM_mov
);
11993 narrow
= (inst
.instruction
== T_MNEM_movs
);
11998 switch (inst
.operands
[1].shift_kind
)
12000 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12001 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12002 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12003 default: narrow
= FALSE
; break;
12009 inst
.instruction
|= Rn
;
12010 inst
.instruction
|= Rm
<< 3;
12011 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12015 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12016 inst
.instruction
|= Rn
<< r0off
;
12017 encode_thumb32_shifted_operand (1);
12021 switch (inst
.instruction
)
12024 /* In v4t or v5t a move of two lowregs produces unpredictable
12025 results. Don't allow this. */
12028 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12029 "MOV Rd, Rs with two low registers is not "
12030 "permitted on this architecture");
12031 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12035 inst
.instruction
= T_OPCODE_MOV_HR
;
12036 inst
.instruction
|= (Rn
& 0x8) << 4;
12037 inst
.instruction
|= (Rn
& 0x7);
12038 inst
.instruction
|= Rm
<< 3;
12042 /* We know we have low registers at this point.
12043 Generate LSLS Rd, Rs, #0. */
12044 inst
.instruction
= T_OPCODE_LSL_I
;
12045 inst
.instruction
|= Rn
;
12046 inst
.instruction
|= Rm
<< 3;
12052 inst
.instruction
= T_OPCODE_CMP_LR
;
12053 inst
.instruction
|= Rn
;
12054 inst
.instruction
|= Rm
<< 3;
12058 inst
.instruction
= T_OPCODE_CMP_HR
;
12059 inst
.instruction
|= (Rn
& 0x8) << 4;
12060 inst
.instruction
|= (Rn
& 0x7);
12061 inst
.instruction
|= Rm
<< 3;
12068 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12070 /* PR 10443: Do not silently ignore shifted operands. */
12071 constraint (inst
.operands
[1].shifted
,
12072 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12074 if (inst
.operands
[1].isreg
)
12076 if (Rn
< 8 && Rm
< 8)
12078 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12079 since a MOV instruction produces unpredictable results. */
12080 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12081 inst
.instruction
= T_OPCODE_ADD_I3
;
12083 inst
.instruction
= T_OPCODE_CMP_LR
;
12085 inst
.instruction
|= Rn
;
12086 inst
.instruction
|= Rm
<< 3;
12090 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12091 inst
.instruction
= T_OPCODE_MOV_HR
;
12093 inst
.instruction
= T_OPCODE_CMP_HR
;
12099 constraint (Rn
> 7,
12100 _("only lo regs allowed with immediate"));
12101 inst
.instruction
|= Rn
<< 8;
12102 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12113 top
= (inst
.instruction
& 0x00800000) != 0;
12114 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12116 constraint (top
, _(":lower16: not allowed this instruction"));
12117 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12119 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12121 constraint (!top
, _(":upper16: not allowed this instruction"));
12122 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12125 Rd
= inst
.operands
[0].reg
;
12126 reject_bad_reg (Rd
);
12128 inst
.instruction
|= Rd
<< 8;
12129 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12131 imm
= inst
.reloc
.exp
.X_add_number
;
12132 inst
.instruction
|= (imm
& 0xf000) << 4;
12133 inst
.instruction
|= (imm
& 0x0800) << 15;
12134 inst
.instruction
|= (imm
& 0x0700) << 4;
12135 inst
.instruction
|= (imm
& 0x00ff);
12140 do_t_mvn_tst (void)
12144 Rn
= inst
.operands
[0].reg
;
12145 Rm
= inst
.operands
[1].reg
;
12147 if (inst
.instruction
== T_MNEM_cmp
12148 || inst
.instruction
== T_MNEM_cmn
)
12149 constraint (Rn
== REG_PC
, BAD_PC
);
12151 reject_bad_reg (Rn
);
12152 reject_bad_reg (Rm
);
12154 if (unified_syntax
)
12156 int r0off
= (inst
.instruction
== T_MNEM_mvn
12157 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12158 bfd_boolean narrow
;
12160 if (inst
.size_req
== 4
12161 || inst
.instruction
> 0xffff
12162 || inst
.operands
[1].shifted
12163 || Rn
> 7 || Rm
> 7)
12165 else if (inst
.instruction
== T_MNEM_cmn
12166 || inst
.instruction
== T_MNEM_tst
)
12168 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12169 narrow
= !in_it_block ();
12171 narrow
= in_it_block ();
12173 if (!inst
.operands
[1].isreg
)
12175 /* For an immediate, we always generate a 32-bit opcode;
12176 section relaxation will shrink it later if possible. */
12177 if (inst
.instruction
< 0xffff)
12178 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12179 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12180 inst
.instruction
|= Rn
<< r0off
;
12181 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12185 /* See if we can do this with a 16-bit instruction. */
12188 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12189 inst
.instruction
|= Rn
;
12190 inst
.instruction
|= Rm
<< 3;
12194 constraint (inst
.operands
[1].shifted
12195 && inst
.operands
[1].immisreg
,
12196 _("shift must be constant"));
12197 if (inst
.instruction
< 0xffff)
12198 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12199 inst
.instruction
|= Rn
<< r0off
;
12200 encode_thumb32_shifted_operand (1);
12206 constraint (inst
.instruction
> 0xffff
12207 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12208 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12209 _("unshifted register required"));
12210 constraint (Rn
> 7 || Rm
> 7,
12213 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12214 inst
.instruction
|= Rn
;
12215 inst
.instruction
|= Rm
<< 3;
12224 if (do_vfp_nsyn_mrs () == SUCCESS
)
12227 Rd
= inst
.operands
[0].reg
;
12228 reject_bad_reg (Rd
);
12229 inst
.instruction
|= Rd
<< 8;
12231 if (inst
.operands
[1].isreg
)
12233 unsigned br
= inst
.operands
[1].reg
;
12234 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12235 as_bad (_("bad register for mrs"));
12237 inst
.instruction
|= br
& (0xf << 16);
12238 inst
.instruction
|= (br
& 0x300) >> 4;
12239 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12243 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12245 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12247 /* PR gas/12698: The constraint is only applied for m_profile.
12248 If the user has specified -march=all, we want to ignore it as
12249 we are building for any CPU type, including non-m variants. */
12250 bfd_boolean m_profile
=
12251 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12252 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12253 "not support requested special purpose register"));
12256 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12258 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12259 _("'APSR', 'CPSR' or 'SPSR' expected"));
12261 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12262 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12263 inst
.instruction
|= 0xf0000;
12273 if (do_vfp_nsyn_msr () == SUCCESS
)
12276 constraint (!inst
.operands
[1].isreg
,
12277 _("Thumb encoding does not support an immediate here"));
12279 if (inst
.operands
[0].isreg
)
12280 flags
= (int)(inst
.operands
[0].reg
);
12282 flags
= inst
.operands
[0].imm
;
12284 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12286 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12288 /* PR gas/12698: The constraint is only applied for m_profile.
12289 If the user has specified -march=all, we want to ignore it as
12290 we are building for any CPU type, including non-m variants. */
12291 bfd_boolean m_profile
=
12292 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12293 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12294 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12295 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12296 && bits
!= PSR_f
)) && m_profile
,
12297 _("selected processor does not support requested special "
12298 "purpose register"));
12301 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12302 "requested special purpose register"));
12304 Rn
= inst
.operands
[1].reg
;
12305 reject_bad_reg (Rn
);
12307 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12308 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12309 inst
.instruction
|= (flags
& 0x300) >> 4;
12310 inst
.instruction
|= (flags
& 0xff);
12311 inst
.instruction
|= Rn
<< 16;
12317 bfd_boolean narrow
;
12318 unsigned Rd
, Rn
, Rm
;
12320 if (!inst
.operands
[2].present
)
12321 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12323 Rd
= inst
.operands
[0].reg
;
12324 Rn
= inst
.operands
[1].reg
;
12325 Rm
= inst
.operands
[2].reg
;
12327 if (unified_syntax
)
12329 if (inst
.size_req
== 4
12335 else if (inst
.instruction
== T_MNEM_muls
)
12336 narrow
= !in_it_block ();
12338 narrow
= in_it_block ();
12342 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12343 constraint (Rn
> 7 || Rm
> 7,
12350 /* 16-bit MULS/Conditional MUL. */
12351 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12352 inst
.instruction
|= Rd
;
12355 inst
.instruction
|= Rm
<< 3;
12357 inst
.instruction
|= Rn
<< 3;
12359 constraint (1, _("dest must overlap one source register"));
12363 constraint (inst
.instruction
!= T_MNEM_mul
,
12364 _("Thumb-2 MUL must not set flags"));
12366 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12367 inst
.instruction
|= Rd
<< 8;
12368 inst
.instruction
|= Rn
<< 16;
12369 inst
.instruction
|= Rm
<< 0;
12371 reject_bad_reg (Rd
);
12372 reject_bad_reg (Rn
);
12373 reject_bad_reg (Rm
);
12380 unsigned RdLo
, RdHi
, Rn
, Rm
;
12382 RdLo
= inst
.operands
[0].reg
;
12383 RdHi
= inst
.operands
[1].reg
;
12384 Rn
= inst
.operands
[2].reg
;
12385 Rm
= inst
.operands
[3].reg
;
12387 reject_bad_reg (RdLo
);
12388 reject_bad_reg (RdHi
);
12389 reject_bad_reg (Rn
);
12390 reject_bad_reg (Rm
);
12392 inst
.instruction
|= RdLo
<< 12;
12393 inst
.instruction
|= RdHi
<< 8;
12394 inst
.instruction
|= Rn
<< 16;
12395 inst
.instruction
|= Rm
;
12398 as_tsktsk (_("rdhi and rdlo must be different"));
12404 set_it_insn_type (NEUTRAL_IT_INSN
);
12406 if (unified_syntax
)
12408 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12410 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12411 inst
.instruction
|= inst
.operands
[0].imm
;
12415 /* PR9722: Check for Thumb2 availability before
12416 generating a thumb2 nop instruction. */
12417 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12419 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12420 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12423 inst
.instruction
= 0x46c0;
12428 constraint (inst
.operands
[0].present
,
12429 _("Thumb does not support NOP with hints"));
12430 inst
.instruction
= 0x46c0;
12437 if (unified_syntax
)
12439 bfd_boolean narrow
;
12441 if (THUMB_SETS_FLAGS (inst
.instruction
))
12442 narrow
= !in_it_block ();
12444 narrow
= in_it_block ();
12445 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12447 if (inst
.size_req
== 4)
12452 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12453 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12454 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12458 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12459 inst
.instruction
|= inst
.operands
[0].reg
;
12460 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12465 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12467 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12469 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12470 inst
.instruction
|= inst
.operands
[0].reg
;
12471 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12480 Rd
= inst
.operands
[0].reg
;
12481 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12483 reject_bad_reg (Rd
);
12484 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12485 reject_bad_reg (Rn
);
12487 inst
.instruction
|= Rd
<< 8;
12488 inst
.instruction
|= Rn
<< 16;
12490 if (!inst
.operands
[2].isreg
)
12492 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12493 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12499 Rm
= inst
.operands
[2].reg
;
12500 reject_bad_reg (Rm
);
12502 constraint (inst
.operands
[2].shifted
12503 && inst
.operands
[2].immisreg
,
12504 _("shift must be constant"));
12505 encode_thumb32_shifted_operand (2);
12512 unsigned Rd
, Rn
, Rm
;
12514 Rd
= inst
.operands
[0].reg
;
12515 Rn
= inst
.operands
[1].reg
;
12516 Rm
= inst
.operands
[2].reg
;
12518 reject_bad_reg (Rd
);
12519 reject_bad_reg (Rn
);
12520 reject_bad_reg (Rm
);
12522 inst
.instruction
|= Rd
<< 8;
12523 inst
.instruction
|= Rn
<< 16;
12524 inst
.instruction
|= Rm
;
12525 if (inst
.operands
[3].present
)
12527 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12528 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12529 _("expression too complex"));
12530 inst
.instruction
|= (val
& 0x1c) << 10;
12531 inst
.instruction
|= (val
& 0x03) << 6;
12538 if (!inst
.operands
[3].present
)
12542 inst
.instruction
&= ~0x00000020;
12544 /* PR 10168. Swap the Rm and Rn registers. */
12545 Rtmp
= inst
.operands
[1].reg
;
12546 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12547 inst
.operands
[2].reg
= Rtmp
;
12555 if (inst
.operands
[0].immisreg
)
12556 reject_bad_reg (inst
.operands
[0].imm
);
12558 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12562 do_t_push_pop (void)
12566 constraint (inst
.operands
[0].writeback
,
12567 _("push/pop do not support {reglist}^"));
12568 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12569 _("expression too complex"));
12571 mask
= inst
.operands
[0].imm
;
12572 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12573 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12574 else if (inst
.size_req
!= 4
12575 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12576 ? REG_LR
: REG_PC
)))
12578 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12579 inst
.instruction
|= THUMB_PP_PC_LR
;
12580 inst
.instruction
|= mask
& 0xff;
12582 else if (unified_syntax
)
12584 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12585 encode_thumb2_ldmstm (13, mask
, TRUE
);
12589 inst
.error
= _("invalid register list to push/pop instruction");
12599 Rd
= inst
.operands
[0].reg
;
12600 Rm
= inst
.operands
[1].reg
;
12602 reject_bad_reg (Rd
);
12603 reject_bad_reg (Rm
);
12605 inst
.instruction
|= Rd
<< 8;
12606 inst
.instruction
|= Rm
<< 16;
12607 inst
.instruction
|= Rm
;
12615 Rd
= inst
.operands
[0].reg
;
12616 Rm
= inst
.operands
[1].reg
;
12618 reject_bad_reg (Rd
);
12619 reject_bad_reg (Rm
);
12621 if (Rd
<= 7 && Rm
<= 7
12622 && inst
.size_req
!= 4)
12624 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12625 inst
.instruction
|= Rd
;
12626 inst
.instruction
|= Rm
<< 3;
12628 else if (unified_syntax
)
12630 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12631 inst
.instruction
|= Rd
<< 8;
12632 inst
.instruction
|= Rm
<< 16;
12633 inst
.instruction
|= Rm
;
12636 inst
.error
= BAD_HIREG
;
12644 Rd
= inst
.operands
[0].reg
;
12645 Rm
= inst
.operands
[1].reg
;
12647 reject_bad_reg (Rd
);
12648 reject_bad_reg (Rm
);
12650 inst
.instruction
|= Rd
<< 8;
12651 inst
.instruction
|= Rm
;
12659 Rd
= inst
.operands
[0].reg
;
12660 Rs
= (inst
.operands
[1].present
12661 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12662 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12664 reject_bad_reg (Rd
);
12665 reject_bad_reg (Rs
);
12666 if (inst
.operands
[2].isreg
)
12667 reject_bad_reg (inst
.operands
[2].reg
);
12669 inst
.instruction
|= Rd
<< 8;
12670 inst
.instruction
|= Rs
<< 16;
12671 if (!inst
.operands
[2].isreg
)
12673 bfd_boolean narrow
;
12675 if ((inst
.instruction
& 0x00100000) != 0)
12676 narrow
= !in_it_block ();
12678 narrow
= in_it_block ();
12680 if (Rd
> 7 || Rs
> 7)
12683 if (inst
.size_req
== 4 || !unified_syntax
)
12686 if (inst
.reloc
.exp
.X_op
!= O_constant
12687 || inst
.reloc
.exp
.X_add_number
!= 0)
12690 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12691 relaxation, but it doesn't seem worth the hassle. */
12694 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12695 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12696 inst
.instruction
|= Rs
<< 3;
12697 inst
.instruction
|= Rd
;
12701 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12702 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12706 encode_thumb32_shifted_operand (2);
12712 if (warn_on_deprecated
12713 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12714 as_tsktsk (_("setend use is deprecated for ARMv8"));
12716 set_it_insn_type (OUTSIDE_IT_INSN
);
12717 if (inst
.operands
[0].imm
)
12718 inst
.instruction
|= 0x8;
12724 if (!inst
.operands
[1].present
)
12725 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12727 if (unified_syntax
)
12729 bfd_boolean narrow
;
12732 switch (inst
.instruction
)
12735 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12737 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12739 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12741 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12745 if (THUMB_SETS_FLAGS (inst
.instruction
))
12746 narrow
= !in_it_block ();
12748 narrow
= in_it_block ();
12749 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12751 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12753 if (inst
.operands
[2].isreg
12754 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12755 || inst
.operands
[2].reg
> 7))
12757 if (inst
.size_req
== 4)
12760 reject_bad_reg (inst
.operands
[0].reg
);
12761 reject_bad_reg (inst
.operands
[1].reg
);
12765 if (inst
.operands
[2].isreg
)
12767 reject_bad_reg (inst
.operands
[2].reg
);
12768 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12769 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12770 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12771 inst
.instruction
|= inst
.operands
[2].reg
;
12773 /* PR 12854: Error on extraneous shifts. */
12774 constraint (inst
.operands
[2].shifted
,
12775 _("extraneous shift as part of operand to shift insn"));
12779 inst
.operands
[1].shifted
= 1;
12780 inst
.operands
[1].shift_kind
= shift_kind
;
12781 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12782 ? T_MNEM_movs
: T_MNEM_mov
);
12783 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12784 encode_thumb32_shifted_operand (1);
12785 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12786 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12791 if (inst
.operands
[2].isreg
)
12793 switch (shift_kind
)
12795 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12796 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12797 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12798 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12802 inst
.instruction
|= inst
.operands
[0].reg
;
12803 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12805 /* PR 12854: Error on extraneous shifts. */
12806 constraint (inst
.operands
[2].shifted
,
12807 _("extraneous shift as part of operand to shift insn"));
12811 switch (shift_kind
)
12813 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12814 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12815 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12818 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12819 inst
.instruction
|= inst
.operands
[0].reg
;
12820 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12826 constraint (inst
.operands
[0].reg
> 7
12827 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12828 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12830 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12832 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12833 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12834 _("source1 and dest must be same register"));
12836 switch (inst
.instruction
)
12838 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12839 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12840 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12841 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12845 inst
.instruction
|= inst
.operands
[0].reg
;
12846 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12848 /* PR 12854: Error on extraneous shifts. */
12849 constraint (inst
.operands
[2].shifted
,
12850 _("extraneous shift as part of operand to shift insn"));
12854 switch (inst
.instruction
)
12856 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12857 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12858 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12859 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12862 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12863 inst
.instruction
|= inst
.operands
[0].reg
;
12864 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12872 unsigned Rd
, Rn
, Rm
;
12874 Rd
= inst
.operands
[0].reg
;
12875 Rn
= inst
.operands
[1].reg
;
12876 Rm
= inst
.operands
[2].reg
;
12878 reject_bad_reg (Rd
);
12879 reject_bad_reg (Rn
);
12880 reject_bad_reg (Rm
);
12882 inst
.instruction
|= Rd
<< 8;
12883 inst
.instruction
|= Rn
<< 16;
12884 inst
.instruction
|= Rm
;
12890 unsigned Rd
, Rn
, Rm
;
12892 Rd
= inst
.operands
[0].reg
;
12893 Rm
= inst
.operands
[1].reg
;
12894 Rn
= inst
.operands
[2].reg
;
12896 reject_bad_reg (Rd
);
12897 reject_bad_reg (Rn
);
12898 reject_bad_reg (Rm
);
12900 inst
.instruction
|= Rd
<< 8;
12901 inst
.instruction
|= Rn
<< 16;
12902 inst
.instruction
|= Rm
;
12908 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12909 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12910 _("SMC is not permitted on this architecture"));
12911 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12912 _("expression too complex"));
12913 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12914 inst
.instruction
|= (value
& 0xf000) >> 12;
12915 inst
.instruction
|= (value
& 0x0ff0);
12916 inst
.instruction
|= (value
& 0x000f) << 16;
12917 /* PR gas/15623: SMC instructions must be last in an IT block. */
12918 set_it_insn_type_last ();
12924 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12926 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12927 inst
.instruction
|= (value
& 0x0fff);
12928 inst
.instruction
|= (value
& 0xf000) << 4;
12932 do_t_ssat_usat (int bias
)
12936 Rd
= inst
.operands
[0].reg
;
12937 Rn
= inst
.operands
[2].reg
;
12939 reject_bad_reg (Rd
);
12940 reject_bad_reg (Rn
);
12942 inst
.instruction
|= Rd
<< 8;
12943 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12944 inst
.instruction
|= Rn
<< 16;
12946 if (inst
.operands
[3].present
)
12948 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12950 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12952 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12953 _("expression too complex"));
12955 if (shift_amount
!= 0)
12957 constraint (shift_amount
> 31,
12958 _("shift expression is too large"));
12960 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12961 inst
.instruction
|= 0x00200000; /* sh bit. */
12963 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12964 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12972 do_t_ssat_usat (1);
12980 Rd
= inst
.operands
[0].reg
;
12981 Rn
= inst
.operands
[2].reg
;
12983 reject_bad_reg (Rd
);
12984 reject_bad_reg (Rn
);
12986 inst
.instruction
|= Rd
<< 8;
12987 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12988 inst
.instruction
|= Rn
<< 16;
12994 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12995 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12996 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12997 || inst
.operands
[2].negative
,
13000 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13002 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13003 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13004 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13005 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13011 if (!inst
.operands
[2].present
)
13012 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13014 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13015 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13016 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13019 inst
.instruction
|= inst
.operands
[0].reg
;
13020 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13021 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13022 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13028 unsigned Rd
, Rn
, Rm
;
13030 Rd
= inst
.operands
[0].reg
;
13031 Rn
= inst
.operands
[1].reg
;
13032 Rm
= inst
.operands
[2].reg
;
13034 reject_bad_reg (Rd
);
13035 reject_bad_reg (Rn
);
13036 reject_bad_reg (Rm
);
13038 inst
.instruction
|= Rd
<< 8;
13039 inst
.instruction
|= Rn
<< 16;
13040 inst
.instruction
|= Rm
;
13041 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13049 Rd
= inst
.operands
[0].reg
;
13050 Rm
= inst
.operands
[1].reg
;
13052 reject_bad_reg (Rd
);
13053 reject_bad_reg (Rm
);
13055 if (inst
.instruction
<= 0xffff
13056 && inst
.size_req
!= 4
13057 && Rd
<= 7 && Rm
<= 7
13058 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13060 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13061 inst
.instruction
|= Rd
;
13062 inst
.instruction
|= Rm
<< 3;
13064 else if (unified_syntax
)
13066 if (inst
.instruction
<= 0xffff)
13067 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13068 inst
.instruction
|= Rd
<< 8;
13069 inst
.instruction
|= Rm
;
13070 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13074 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13075 _("Thumb encoding does not support rotation"));
13076 constraint (1, BAD_HIREG
);
13083 /* We have to do the following check manually as ARM_EXT_OS only applies
13085 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13087 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13088 /* This only applies to the v6m however, not later architectures. */
13089 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13090 as_bad (_("SVC is not permitted on this architecture"));
13091 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13094 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13103 half
= (inst
.instruction
& 0x10) != 0;
13104 set_it_insn_type_last ();
13105 constraint (inst
.operands
[0].immisreg
,
13106 _("instruction requires register index"));
13108 Rn
= inst
.operands
[0].reg
;
13109 Rm
= inst
.operands
[0].imm
;
13111 constraint (Rn
== REG_SP
, BAD_SP
);
13112 reject_bad_reg (Rm
);
13114 constraint (!half
&& inst
.operands
[0].shifted
,
13115 _("instruction does not allow shifted index"));
13116 inst
.instruction
|= (Rn
<< 16) | Rm
;
13122 if (!inst
.operands
[0].present
)
13123 inst
.operands
[0].imm
= 0;
13125 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13127 constraint (inst
.size_req
== 2,
13128 _("immediate value out of range"));
13129 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13130 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13131 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13135 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13136 inst
.instruction
|= inst
.operands
[0].imm
;
13139 set_it_insn_type (NEUTRAL_IT_INSN
);
13146 do_t_ssat_usat (0);
13154 Rd
= inst
.operands
[0].reg
;
13155 Rn
= inst
.operands
[2].reg
;
13157 reject_bad_reg (Rd
);
13158 reject_bad_reg (Rn
);
13160 inst
.instruction
|= Rd
<< 8;
13161 inst
.instruction
|= inst
.operands
[1].imm
;
13162 inst
.instruction
|= Rn
<< 16;
13165 /* Neon instruction encoder helpers. */
13167 /* Encodings for the different types for various Neon opcodes. */
13169 /* An "invalid" code for the following tables. */
13172 struct neon_tab_entry
13175 unsigned float_or_poly
;
13176 unsigned scalar_or_imm
;
13179 /* Map overloaded Neon opcodes to their respective encodings. */
13180 #define NEON_ENC_TAB \
13181 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13182 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13183 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13184 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13185 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13186 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13187 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13188 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13189 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13190 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13191 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13192 /* Register variants of the following two instructions are encoded as
13193 vcge / vcgt with the operands reversed. */ \
13194 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13195 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13196 X(vfma, N_INV, 0x0000c10, N_INV), \
13197 X(vfms, N_INV, 0x0200c10, N_INV), \
13198 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13199 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13200 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13201 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13202 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13203 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13204 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13205 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13206 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13207 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13208 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13209 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13210 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13211 X(vshl, 0x0000400, N_INV, 0x0800510), \
13212 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13213 X(vand, 0x0000110, N_INV, 0x0800030), \
13214 X(vbic, 0x0100110, N_INV, 0x0800030), \
13215 X(veor, 0x1000110, N_INV, N_INV), \
13216 X(vorn, 0x0300110, N_INV, 0x0800010), \
13217 X(vorr, 0x0200110, N_INV, 0x0800010), \
13218 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13219 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13220 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13221 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13222 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13223 X(vst1, 0x0000000, 0x0800000, N_INV), \
13224 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13225 X(vst2, 0x0000100, 0x0800100, N_INV), \
13226 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13227 X(vst3, 0x0000200, 0x0800200, N_INV), \
13228 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13229 X(vst4, 0x0000300, 0x0800300, N_INV), \
13230 X(vmovn, 0x1b20200, N_INV, N_INV), \
13231 X(vtrn, 0x1b20080, N_INV, N_INV), \
13232 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13233 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13234 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13235 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13236 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13237 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13238 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13239 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13240 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13241 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13242 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13243 X(vseleq, 0xe000a00, N_INV, N_INV), \
13244 X(vselvs, 0xe100a00, N_INV, N_INV), \
13245 X(vselge, 0xe200a00, N_INV, N_INV), \
13246 X(vselgt, 0xe300a00, N_INV, N_INV), \
13247 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13248 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13249 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13250 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13251 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13252 X(aes, 0x3b00300, N_INV, N_INV), \
13253 X(sha3op, 0x2000c00, N_INV, N_INV), \
13254 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13255 X(sha2op, 0x3ba0380, N_INV, N_INV)
13259 #define X(OPC,I,F,S) N_MNEM_##OPC
13264 static const struct neon_tab_entry neon_enc_tab
[] =
13266 #define X(OPC,I,F,S) { (I), (F), (S) }
13271 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13272 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13273 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13274 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13275 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13276 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13277 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13278 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13279 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13280 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13281 #define NEON_ENC_SINGLE_(X) \
13282 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13283 #define NEON_ENC_DOUBLE_(X) \
13284 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13285 #define NEON_ENC_FPV8_(X) \
13286 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13288 #define NEON_ENCODE(type, inst) \
13291 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13292 inst.is_neon = 1; \
13296 #define check_neon_suffixes \
13299 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13301 as_bad (_("invalid neon suffix for non neon instruction")); \
13307 /* Define shapes for instruction operands. The following mnemonic characters
13308 are used in this table:
13310 F - VFP S<n> register
13311 D - Neon D<n> register
13312 Q - Neon Q<n> register
13316 L - D<n> register list
13318 This table is used to generate various data:
13319 - enumerations of the form NS_DDR to be used as arguments to
13321 - a table classifying shapes into single, double, quad, mixed.
13322 - a table used to drive neon_select_shape. */
13324 #define NEON_SHAPE_DEF \
13325 X(3, (D, D, D), DOUBLE), \
13326 X(3, (Q, Q, Q), QUAD), \
13327 X(3, (D, D, I), DOUBLE), \
13328 X(3, (Q, Q, I), QUAD), \
13329 X(3, (D, D, S), DOUBLE), \
13330 X(3, (Q, Q, S), QUAD), \
13331 X(2, (D, D), DOUBLE), \
13332 X(2, (Q, Q), QUAD), \
13333 X(2, (D, S), DOUBLE), \
13334 X(2, (Q, S), QUAD), \
13335 X(2, (D, R), DOUBLE), \
13336 X(2, (Q, R), QUAD), \
13337 X(2, (D, I), DOUBLE), \
13338 X(2, (Q, I), QUAD), \
13339 X(3, (D, L, D), DOUBLE), \
13340 X(2, (D, Q), MIXED), \
13341 X(2, (Q, D), MIXED), \
13342 X(3, (D, Q, I), MIXED), \
13343 X(3, (Q, D, I), MIXED), \
13344 X(3, (Q, D, D), MIXED), \
13345 X(3, (D, Q, Q), MIXED), \
13346 X(3, (Q, Q, D), MIXED), \
13347 X(3, (Q, D, S), MIXED), \
13348 X(3, (D, Q, S), MIXED), \
13349 X(4, (D, D, D, I), DOUBLE), \
13350 X(4, (Q, Q, Q, I), QUAD), \
13351 X(2, (F, F), SINGLE), \
13352 X(3, (F, F, F), SINGLE), \
13353 X(2, (F, I), SINGLE), \
13354 X(2, (F, D), MIXED), \
13355 X(2, (D, F), MIXED), \
13356 X(3, (F, F, I), MIXED), \
13357 X(4, (R, R, F, F), SINGLE), \
13358 X(4, (F, F, R, R), SINGLE), \
13359 X(3, (D, R, R), DOUBLE), \
13360 X(3, (R, R, D), DOUBLE), \
13361 X(2, (S, R), SINGLE), \
13362 X(2, (R, S), SINGLE), \
13363 X(2, (F, R), SINGLE), \
13364 X(2, (R, F), SINGLE), \
13365 /* Half float shape supported so far. */\
13366 X (2, (H, D), MIXED), \
13367 X (2, (D, H), MIXED), \
13368 X (2, (H, F), MIXED), \
13369 X (2, (F, H), MIXED), \
13370 X (2, (H, H), HALF), \
13371 X (2, (H, R), HALF), \
13372 X (2, (R, H), HALF), \
13373 X (2, (H, I), HALF), \
13374 X (3, (H, H, H), HALF), \
13375 X (3, (H, F, I), MIXED), \
13376 X (3, (F, H, I), MIXED)
13378 #define S2(A,B) NS_##A##B
13379 #define S3(A,B,C) NS_##A##B##C
13380 #define S4(A,B,C,D) NS_##A##B##C##D
13382 #define X(N, L, C) S##N L
13395 enum neon_shape_class
13404 #define X(N, L, C) SC_##C
13406 static enum neon_shape_class neon_shape_class
[] =
13425 /* Register widths of above. */
13426 static unsigned neon_shape_el_size
[] =
13438 struct neon_shape_info
13441 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13444 #define S2(A,B) { SE_##A, SE_##B }
13445 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13446 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13448 #define X(N, L, C) { N, S##N L }
13450 static struct neon_shape_info neon_shape_tab
[] =
13460 /* Bit masks used in type checking given instructions.
13461 'N_EQK' means the type must be the same as (or based on in some way) the key
13462 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13463 set, various other bits can be set as well in order to modify the meaning of
13464 the type constraint. */
13466 enum neon_type_mask
13490 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13491 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13492 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13493 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13494 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13495 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13496 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13497 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13498 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13499 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13500 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13502 N_MAX_NONSPECIAL
= N_P64
13505 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13507 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13508 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13509 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13510 #define N_S_32 (N_S8 | N_S16 | N_S32)
13511 #define N_F_16_32 (N_F16 | N_F32)
13512 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13513 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13514 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13515 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13517 /* Pass this as the first type argument to neon_check_type to ignore types
13519 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13521 /* Select a "shape" for the current instruction (describing register types or
13522 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13523 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13524 function of operand parsing, so this function doesn't need to be called.
13525 Shapes should be listed in order of decreasing length. */
13527 static enum neon_shape
13528 neon_select_shape (enum neon_shape shape
, ...)
13531 enum neon_shape first_shape
= shape
;
13533 /* Fix missing optional operands. FIXME: we don't know at this point how
13534 many arguments we should have, so this makes the assumption that we have
13535 > 1. This is true of all current Neon opcodes, I think, but may not be
13536 true in the future. */
13537 if (!inst
.operands
[1].present
)
13538 inst
.operands
[1] = inst
.operands
[0];
13540 va_start (ap
, shape
);
13542 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13547 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13549 if (!inst
.operands
[j
].present
)
13555 switch (neon_shape_tab
[shape
].el
[j
])
13557 /* If a .f16, .16, .u16, .s16 type specifier is given over
13558 a VFP single precision register operand, it's essentially
13559 means only half of the register is used.
13561 If the type specifier is given after the mnemonics, the
13562 information is stored in inst.vectype. If the type specifier
13563 is given after register operand, the information is stored
13564 in inst.operands[].vectype.
13566 When there is only one type specifier, and all the register
13567 operands are the same type of hardware register, the type
13568 specifier applies to all register operands.
13570 If no type specifier is given, the shape is inferred from
13571 operand information.
13574 vadd.f16 s0, s1, s2: NS_HHH
13575 vabs.f16 s0, s1: NS_HH
13576 vmov.f16 s0, r1: NS_HR
13577 vmov.f16 r0, s1: NS_RH
13578 vcvt.f16 r0, s1: NS_RH
13579 vcvt.f16.s32 s2, s2, #29: NS_HFI
13580 vcvt.f16.s32 s2, s2: NS_HF
13583 if (!(inst
.operands
[j
].isreg
13584 && inst
.operands
[j
].isvec
13585 && inst
.operands
[j
].issingle
13586 && !inst
.operands
[j
].isquad
13587 && ((inst
.vectype
.elems
== 1
13588 && inst
.vectype
.el
[0].size
== 16)
13589 || (inst
.vectype
.elems
> 1
13590 && inst
.vectype
.el
[j
].size
== 16)
13591 || (inst
.vectype
.elems
== 0
13592 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13593 && inst
.operands
[j
].vectype
.size
== 16))))
13598 if (!(inst
.operands
[j
].isreg
13599 && inst
.operands
[j
].isvec
13600 && inst
.operands
[j
].issingle
13601 && !inst
.operands
[j
].isquad
13602 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13603 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13604 || (inst
.vectype
.elems
== 0
13605 && (inst
.operands
[j
].vectype
.size
== 32
13606 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13611 if (!(inst
.operands
[j
].isreg
13612 && inst
.operands
[j
].isvec
13613 && !inst
.operands
[j
].isquad
13614 && !inst
.operands
[j
].issingle
))
13619 if (!(inst
.operands
[j
].isreg
13620 && !inst
.operands
[j
].isvec
))
13625 if (!(inst
.operands
[j
].isreg
13626 && inst
.operands
[j
].isvec
13627 && inst
.operands
[j
].isquad
13628 && !inst
.operands
[j
].issingle
))
13633 if (!(!inst
.operands
[j
].isreg
13634 && !inst
.operands
[j
].isscalar
))
13639 if (!(!inst
.operands
[j
].isreg
13640 && inst
.operands
[j
].isscalar
))
13650 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13651 /* We've matched all the entries in the shape table, and we don't
13652 have any left over operands which have not been matched. */
13658 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13659 first_error (_("invalid instruction shape"));
13664 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13665 means the Q bit should be set). */
13668 neon_quad (enum neon_shape shape
)
13670 return neon_shape_class
[shape
] == SC_QUAD
;
13674 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13677 /* Allow modification to be made to types which are constrained to be
13678 based on the key element, based on bits set alongside N_EQK. */
13679 if ((typebits
& N_EQK
) != 0)
13681 if ((typebits
& N_HLF
) != 0)
13683 else if ((typebits
& N_DBL
) != 0)
13685 if ((typebits
& N_SGN
) != 0)
13686 *g_type
= NT_signed
;
13687 else if ((typebits
& N_UNS
) != 0)
13688 *g_type
= NT_unsigned
;
13689 else if ((typebits
& N_INT
) != 0)
13690 *g_type
= NT_integer
;
13691 else if ((typebits
& N_FLT
) != 0)
13692 *g_type
= NT_float
;
13693 else if ((typebits
& N_SIZ
) != 0)
13694 *g_type
= NT_untyped
;
13698 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13699 operand type, i.e. the single type specified in a Neon instruction when it
13700 is the only one given. */
13702 static struct neon_type_el
13703 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13705 struct neon_type_el dest
= *key
;
13707 gas_assert ((thisarg
& N_EQK
) != 0);
13709 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13714 /* Convert Neon type and size into compact bitmask representation. */
13716 static enum neon_type_mask
13717 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13724 case 8: return N_8
;
13725 case 16: return N_16
;
13726 case 32: return N_32
;
13727 case 64: return N_64
;
13735 case 8: return N_I8
;
13736 case 16: return N_I16
;
13737 case 32: return N_I32
;
13738 case 64: return N_I64
;
13746 case 16: return N_F16
;
13747 case 32: return N_F32
;
13748 case 64: return N_F64
;
13756 case 8: return N_P8
;
13757 case 16: return N_P16
;
13758 case 64: return N_P64
;
13766 case 8: return N_S8
;
13767 case 16: return N_S16
;
13768 case 32: return N_S32
;
13769 case 64: return N_S64
;
13777 case 8: return N_U8
;
13778 case 16: return N_U16
;
13779 case 32: return N_U32
;
13780 case 64: return N_U64
;
13791 /* Convert compact Neon bitmask type representation to a type and size. Only
13792 handles the case where a single bit is set in the mask. */
13795 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13796 enum neon_type_mask mask
)
13798 if ((mask
& N_EQK
) != 0)
13801 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13803 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13805 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13807 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13812 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13814 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13815 *type
= NT_unsigned
;
13816 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13817 *type
= NT_integer
;
13818 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13819 *type
= NT_untyped
;
13820 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13822 else if ((mask
& (N_F_ALL
)) != 0)
13830 /* Modify a bitmask of allowed types. This is only needed for type
13834 modify_types_allowed (unsigned allowed
, unsigned mods
)
13837 enum neon_el_type type
;
13843 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13845 if (el_type_of_type_chk (&type
, &size
,
13846 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13848 neon_modify_type_size (mods
, &type
, &size
);
13849 destmask
|= type_chk_of_el_type (type
, size
);
13856 /* Check type and return type classification.
13857 The manual states (paraphrase): If one datatype is given, it indicates the
13859 - the second operand, if there is one
13860 - the operand, if there is no second operand
13861 - the result, if there are no operands.
13862 This isn't quite good enough though, so we use a concept of a "key" datatype
13863 which is set on a per-instruction basis, which is the one which matters when
13864 only one data type is written.
13865 Note: this function has side-effects (e.g. filling in missing operands). All
13866 Neon instructions should call it before performing bit encoding. */
13868 static struct neon_type_el
13869 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13872 unsigned i
, pass
, key_el
= 0;
13873 unsigned types
[NEON_MAX_TYPE_ELS
];
13874 enum neon_el_type k_type
= NT_invtype
;
13875 unsigned k_size
= -1u;
13876 struct neon_type_el badtype
= {NT_invtype
, -1};
13877 unsigned key_allowed
= 0;
13879 /* Optional registers in Neon instructions are always (not) in operand 1.
13880 Fill in the missing operand here, if it was omitted. */
13881 if (els
> 1 && !inst
.operands
[1].present
)
13882 inst
.operands
[1] = inst
.operands
[0];
13884 /* Suck up all the varargs. */
13886 for (i
= 0; i
< els
; i
++)
13888 unsigned thisarg
= va_arg (ap
, unsigned);
13889 if (thisarg
== N_IGNORE_TYPE
)
13894 types
[i
] = thisarg
;
13895 if ((thisarg
& N_KEY
) != 0)
13900 if (inst
.vectype
.elems
> 0)
13901 for (i
= 0; i
< els
; i
++)
13902 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13904 first_error (_("types specified in both the mnemonic and operands"));
13908 /* Duplicate inst.vectype elements here as necessary.
13909 FIXME: No idea if this is exactly the same as the ARM assembler,
13910 particularly when an insn takes one register and one non-register
13912 if (inst
.vectype
.elems
== 1 && els
> 1)
13915 inst
.vectype
.elems
= els
;
13916 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13917 for (j
= 0; j
< els
; j
++)
13919 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13922 else if (inst
.vectype
.elems
== 0 && els
> 0)
13925 /* No types were given after the mnemonic, so look for types specified
13926 after each operand. We allow some flexibility here; as long as the
13927 "key" operand has a type, we can infer the others. */
13928 for (j
= 0; j
< els
; j
++)
13929 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13930 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13932 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13934 for (j
= 0; j
< els
; j
++)
13935 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13936 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13941 first_error (_("operand types can't be inferred"));
13945 else if (inst
.vectype
.elems
!= els
)
13947 first_error (_("type specifier has the wrong number of parts"));
13951 for (pass
= 0; pass
< 2; pass
++)
13953 for (i
= 0; i
< els
; i
++)
13955 unsigned thisarg
= types
[i
];
13956 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13957 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13958 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13959 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13961 /* Decay more-specific signed & unsigned types to sign-insensitive
13962 integer types if sign-specific variants are unavailable. */
13963 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13964 && (types_allowed
& N_SU_ALL
) == 0)
13965 g_type
= NT_integer
;
13967 /* If only untyped args are allowed, decay any more specific types to
13968 them. Some instructions only care about signs for some element
13969 sizes, so handle that properly. */
13970 if (((types_allowed
& N_UNT
) == 0)
13971 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13972 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13973 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13974 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13975 g_type
= NT_untyped
;
13979 if ((thisarg
& N_KEY
) != 0)
13983 key_allowed
= thisarg
& ~N_KEY
;
13985 /* Check architecture constraint on FP16 extension. */
13987 && k_type
== NT_float
13988 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13990 inst
.error
= _(BAD_FP16
);
13997 if ((thisarg
& N_VFP
) != 0)
13999 enum neon_shape_el regshape
;
14000 unsigned regwidth
, match
;
14002 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14005 first_error (_("invalid instruction shape"));
14008 regshape
= neon_shape_tab
[ns
].el
[i
];
14009 regwidth
= neon_shape_el_size
[regshape
];
14011 /* In VFP mode, operands must match register widths. If we
14012 have a key operand, use its width, else use the width of
14013 the current operand. */
14019 /* FP16 will use a single precision register. */
14020 if (regwidth
== 32 && match
== 16)
14022 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14026 inst
.error
= _(BAD_FP16
);
14031 if (regwidth
!= match
)
14033 first_error (_("operand size must match register width"));
14038 if ((thisarg
& N_EQK
) == 0)
14040 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14042 if ((given_type
& types_allowed
) == 0)
14044 first_error (_("bad type in Neon instruction"));
14050 enum neon_el_type mod_k_type
= k_type
;
14051 unsigned mod_k_size
= k_size
;
14052 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14053 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14055 first_error (_("inconsistent types in Neon instruction"));
14063 return inst
.vectype
.el
[key_el
];
14066 /* Neon-style VFP instruction forwarding. */
14068 /* Thumb VFP instructions have 0xE in the condition field. */
14071 do_vfp_cond_or_thumb (void)
14076 inst
.instruction
|= 0xe0000000;
14078 inst
.instruction
|= inst
.cond
<< 28;
14081 /* Look up and encode a simple mnemonic, for use as a helper function for the
14082 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14083 etc. It is assumed that operand parsing has already been done, and that the
14084 operands are in the form expected by the given opcode (this isn't necessarily
14085 the same as the form in which they were parsed, hence some massaging must
14086 take place before this function is called).
14087 Checks current arch version against that in the looked-up opcode. */
14090 do_vfp_nsyn_opcode (const char *opname
)
14092 const struct asm_opcode
*opcode
;
14094 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14099 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14100 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14107 inst
.instruction
= opcode
->tvalue
;
14108 opcode
->tencode ();
14112 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14113 opcode
->aencode ();
14118 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14120 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14122 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14125 do_vfp_nsyn_opcode ("fadds");
14127 do_vfp_nsyn_opcode ("fsubs");
14129 /* ARMv8.2 fp16 instruction. */
14131 do_scalar_fp16_v82_encode ();
14136 do_vfp_nsyn_opcode ("faddd");
14138 do_vfp_nsyn_opcode ("fsubd");
14142 /* Check operand types to see if this is a VFP instruction, and if so call
14146 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14148 enum neon_shape rs
;
14149 struct neon_type_el et
;
14154 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14155 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14159 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14160 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14161 N_F_ALL
| N_KEY
| N_VFP
);
14168 if (et
.type
!= NT_invtype
)
14179 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14181 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14183 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14186 do_vfp_nsyn_opcode ("fmacs");
14188 do_vfp_nsyn_opcode ("fnmacs");
14190 /* ARMv8.2 fp16 instruction. */
14192 do_scalar_fp16_v82_encode ();
14197 do_vfp_nsyn_opcode ("fmacd");
14199 do_vfp_nsyn_opcode ("fnmacd");
14204 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14206 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14208 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14211 do_vfp_nsyn_opcode ("ffmas");
14213 do_vfp_nsyn_opcode ("ffnmas");
14215 /* ARMv8.2 fp16 instruction. */
14217 do_scalar_fp16_v82_encode ();
14222 do_vfp_nsyn_opcode ("ffmad");
14224 do_vfp_nsyn_opcode ("ffnmad");
14229 do_vfp_nsyn_mul (enum neon_shape rs
)
14231 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14233 do_vfp_nsyn_opcode ("fmuls");
14235 /* ARMv8.2 fp16 instruction. */
14237 do_scalar_fp16_v82_encode ();
14240 do_vfp_nsyn_opcode ("fmuld");
14244 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14246 int is_neg
= (inst
.instruction
& 0x80) != 0;
14247 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14249 if (rs
== NS_FF
|| rs
== NS_HH
)
14252 do_vfp_nsyn_opcode ("fnegs");
14254 do_vfp_nsyn_opcode ("fabss");
14256 /* ARMv8.2 fp16 instruction. */
14258 do_scalar_fp16_v82_encode ();
14263 do_vfp_nsyn_opcode ("fnegd");
14265 do_vfp_nsyn_opcode ("fabsd");
14269 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14270 insns belong to Neon, and are handled elsewhere. */
14273 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14275 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14279 do_vfp_nsyn_opcode ("fldmdbs");
14281 do_vfp_nsyn_opcode ("fldmias");
14286 do_vfp_nsyn_opcode ("fstmdbs");
14288 do_vfp_nsyn_opcode ("fstmias");
14293 do_vfp_nsyn_sqrt (void)
14295 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14296 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14298 if (rs
== NS_FF
|| rs
== NS_HH
)
14300 do_vfp_nsyn_opcode ("fsqrts");
14302 /* ARMv8.2 fp16 instruction. */
14304 do_scalar_fp16_v82_encode ();
14307 do_vfp_nsyn_opcode ("fsqrtd");
14311 do_vfp_nsyn_div (void)
14313 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14314 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14315 N_F_ALL
| N_KEY
| N_VFP
);
14317 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14319 do_vfp_nsyn_opcode ("fdivs");
14321 /* ARMv8.2 fp16 instruction. */
14323 do_scalar_fp16_v82_encode ();
14326 do_vfp_nsyn_opcode ("fdivd");
14330 do_vfp_nsyn_nmul (void)
14332 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14333 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14334 N_F_ALL
| N_KEY
| N_VFP
);
14336 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14338 NEON_ENCODE (SINGLE
, inst
);
14339 do_vfp_sp_dyadic ();
14341 /* ARMv8.2 fp16 instruction. */
14343 do_scalar_fp16_v82_encode ();
14347 NEON_ENCODE (DOUBLE
, inst
);
14348 do_vfp_dp_rd_rn_rm ();
14350 do_vfp_cond_or_thumb ();
14355 do_vfp_nsyn_cmp (void)
14357 enum neon_shape rs
;
14358 if (inst
.operands
[1].isreg
)
14360 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14361 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14363 if (rs
== NS_FF
|| rs
== NS_HH
)
14365 NEON_ENCODE (SINGLE
, inst
);
14366 do_vfp_sp_monadic ();
14370 NEON_ENCODE (DOUBLE
, inst
);
14371 do_vfp_dp_rd_rm ();
14376 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14377 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14379 switch (inst
.instruction
& 0x0fffffff)
14382 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14385 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14391 if (rs
== NS_FI
|| rs
== NS_HI
)
14393 NEON_ENCODE (SINGLE
, inst
);
14394 do_vfp_sp_compare_z ();
14398 NEON_ENCODE (DOUBLE
, inst
);
14402 do_vfp_cond_or_thumb ();
14404 /* ARMv8.2 fp16 instruction. */
14405 if (rs
== NS_HI
|| rs
== NS_HH
)
14406 do_scalar_fp16_v82_encode ();
14410 nsyn_insert_sp (void)
14412 inst
.operands
[1] = inst
.operands
[0];
14413 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14414 inst
.operands
[0].reg
= REG_SP
;
14415 inst
.operands
[0].isreg
= 1;
14416 inst
.operands
[0].writeback
= 1;
14417 inst
.operands
[0].present
= 1;
14421 do_vfp_nsyn_push (void)
14425 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14426 _("register list must contain at least 1 and at most 16 "
14429 if (inst
.operands
[1].issingle
)
14430 do_vfp_nsyn_opcode ("fstmdbs");
14432 do_vfp_nsyn_opcode ("fstmdbd");
14436 do_vfp_nsyn_pop (void)
14440 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14441 _("register list must contain at least 1 and at most 16 "
14444 if (inst
.operands
[1].issingle
)
14445 do_vfp_nsyn_opcode ("fldmias");
14447 do_vfp_nsyn_opcode ("fldmiad");
14450 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14451 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14454 neon_dp_fixup (struct arm_it
* insn
)
14456 unsigned int i
= insn
->instruction
;
14461 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14472 insn
->instruction
= i
;
14475 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14479 neon_logbits (unsigned x
)
14481 return ffs (x
) - 4;
14484 #define LOW4(R) ((R) & 0xf)
14485 #define HI1(R) (((R) >> 4) & 1)
14487 /* Encode insns with bit pattern:
14489 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14490 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14492 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14493 different meaning for some instruction. */
14496 neon_three_same (int isquad
, int ubit
, int size
)
14498 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14499 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14500 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14501 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14502 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14503 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14504 inst
.instruction
|= (isquad
!= 0) << 6;
14505 inst
.instruction
|= (ubit
!= 0) << 24;
14507 inst
.instruction
|= neon_logbits (size
) << 20;
14509 neon_dp_fixup (&inst
);
14512 /* Encode instructions of the form:
14514 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14515 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14517 Don't write size if SIZE == -1. */
14520 neon_two_same (int qbit
, int ubit
, int size
)
14522 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14523 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14524 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14525 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14526 inst
.instruction
|= (qbit
!= 0) << 6;
14527 inst
.instruction
|= (ubit
!= 0) << 24;
14530 inst
.instruction
|= neon_logbits (size
) << 18;
14532 neon_dp_fixup (&inst
);
14535 /* Neon instruction encoders, in approximate order of appearance. */
14538 do_neon_dyadic_i_su (void)
14540 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14541 struct neon_type_el et
= neon_check_type (3, rs
,
14542 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14543 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14547 do_neon_dyadic_i64_su (void)
14549 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14550 struct neon_type_el et
= neon_check_type (3, rs
,
14551 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14552 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14556 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14559 unsigned size
= et
.size
>> 3;
14560 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14561 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14562 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14563 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14564 inst
.instruction
|= (isquad
!= 0) << 6;
14565 inst
.instruction
|= immbits
<< 16;
14566 inst
.instruction
|= (size
>> 3) << 7;
14567 inst
.instruction
|= (size
& 0x7) << 19;
14569 inst
.instruction
|= (uval
!= 0) << 24;
14571 neon_dp_fixup (&inst
);
14575 do_neon_shl_imm (void)
14577 if (!inst
.operands
[2].isreg
)
14579 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14580 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14581 int imm
= inst
.operands
[2].imm
;
14583 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14584 _("immediate out of range for shift"));
14585 NEON_ENCODE (IMMED
, inst
);
14586 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14590 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14591 struct neon_type_el et
= neon_check_type (3, rs
,
14592 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14595 /* VSHL/VQSHL 3-register variants have syntax such as:
14597 whereas other 3-register operations encoded by neon_three_same have
14600 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14602 tmp
= inst
.operands
[2].reg
;
14603 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14604 inst
.operands
[1].reg
= tmp
;
14605 NEON_ENCODE (INTEGER
, inst
);
14606 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14611 do_neon_qshl_imm (void)
14613 if (!inst
.operands
[2].isreg
)
14615 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14616 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14617 int imm
= inst
.operands
[2].imm
;
14619 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14620 _("immediate out of range for shift"));
14621 NEON_ENCODE (IMMED
, inst
);
14622 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14626 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14627 struct neon_type_el et
= neon_check_type (3, rs
,
14628 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14631 /* See note in do_neon_shl_imm. */
14632 tmp
= inst
.operands
[2].reg
;
14633 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14634 inst
.operands
[1].reg
= tmp
;
14635 NEON_ENCODE (INTEGER
, inst
);
14636 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14641 do_neon_rshl (void)
14643 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14644 struct neon_type_el et
= neon_check_type (3, rs
,
14645 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14648 tmp
= inst
.operands
[2].reg
;
14649 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14650 inst
.operands
[1].reg
= tmp
;
14651 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14655 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14657 /* Handle .I8 pseudo-instructions. */
14660 /* Unfortunately, this will make everything apart from zero out-of-range.
14661 FIXME is this the intended semantics? There doesn't seem much point in
14662 accepting .I8 if so. */
14663 immediate
|= immediate
<< 8;
14669 if (immediate
== (immediate
& 0x000000ff))
14671 *immbits
= immediate
;
14674 else if (immediate
== (immediate
& 0x0000ff00))
14676 *immbits
= immediate
>> 8;
14679 else if (immediate
== (immediate
& 0x00ff0000))
14681 *immbits
= immediate
>> 16;
14684 else if (immediate
== (immediate
& 0xff000000))
14686 *immbits
= immediate
>> 24;
14689 if ((immediate
& 0xffff) != (immediate
>> 16))
14690 goto bad_immediate
;
14691 immediate
&= 0xffff;
14694 if (immediate
== (immediate
& 0x000000ff))
14696 *immbits
= immediate
;
14699 else if (immediate
== (immediate
& 0x0000ff00))
14701 *immbits
= immediate
>> 8;
14706 first_error (_("immediate value out of range"));
14711 do_neon_logic (void)
14713 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14715 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14716 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14717 /* U bit and size field were set as part of the bitmask. */
14718 NEON_ENCODE (INTEGER
, inst
);
14719 neon_three_same (neon_quad (rs
), 0, -1);
14723 const int three_ops_form
= (inst
.operands
[2].present
14724 && !inst
.operands
[2].isreg
);
14725 const int immoperand
= (three_ops_form
? 2 : 1);
14726 enum neon_shape rs
= (three_ops_form
14727 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14728 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14729 struct neon_type_el et
= neon_check_type (2, rs
,
14730 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14731 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14735 if (et
.type
== NT_invtype
)
14738 if (three_ops_form
)
14739 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14740 _("first and second operands shall be the same register"));
14742 NEON_ENCODE (IMMED
, inst
);
14744 immbits
= inst
.operands
[immoperand
].imm
;
14747 /* .i64 is a pseudo-op, so the immediate must be a repeating
14749 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14750 inst
.operands
[immoperand
].reg
: 0))
14752 /* Set immbits to an invalid constant. */
14753 immbits
= 0xdeadbeef;
14760 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14764 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14768 /* Pseudo-instruction for VBIC. */
14769 neon_invert_size (&immbits
, 0, et
.size
);
14770 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14774 /* Pseudo-instruction for VORR. */
14775 neon_invert_size (&immbits
, 0, et
.size
);
14776 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14786 inst
.instruction
|= neon_quad (rs
) << 6;
14787 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14788 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14789 inst
.instruction
|= cmode
<< 8;
14790 neon_write_immbits (immbits
);
14792 neon_dp_fixup (&inst
);
14797 do_neon_bitfield (void)
14799 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14800 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14801 neon_three_same (neon_quad (rs
), 0, -1);
14805 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14808 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14809 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14811 if (et
.type
== NT_float
)
14813 NEON_ENCODE (FLOAT
, inst
);
14814 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14818 NEON_ENCODE (INTEGER
, inst
);
14819 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14824 do_neon_dyadic_if_su (void)
14826 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14830 do_neon_dyadic_if_su_d (void)
14832 /* This version only allow D registers, but that constraint is enforced during
14833 operand parsing so we don't need to do anything extra here. */
14834 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14838 do_neon_dyadic_if_i_d (void)
14840 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14841 affected if we specify unsigned args. */
14842 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14845 enum vfp_or_neon_is_neon_bits
14848 NEON_CHECK_ARCH
= 2,
14849 NEON_CHECK_ARCH8
= 4
14852 /* Call this function if an instruction which may have belonged to the VFP or
14853 Neon instruction sets, but turned out to be a Neon instruction (due to the
14854 operand types involved, etc.). We have to check and/or fix-up a couple of
14857 - Make sure the user hasn't attempted to make a Neon instruction
14859 - Alter the value in the condition code field if necessary.
14860 - Make sure that the arch supports Neon instructions.
14862 Which of these operations take place depends on bits from enum
14863 vfp_or_neon_is_neon_bits.
14865 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14866 current instruction's condition is COND_ALWAYS, the condition field is
14867 changed to inst.uncond_value. This is necessary because instructions shared
14868 between VFP and Neon may be conditional for the VFP variants only, and the
14869 unconditional Neon version must have, e.g., 0xF in the condition field. */
14872 vfp_or_neon_is_neon (unsigned check
)
14874 /* Conditions are always legal in Thumb mode (IT blocks). */
14875 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14877 if (inst
.cond
!= COND_ALWAYS
)
14879 first_error (_(BAD_COND
));
14882 if (inst
.uncond_value
!= -1)
14883 inst
.instruction
|= inst
.uncond_value
<< 28;
14886 if ((check
& NEON_CHECK_ARCH
)
14887 && !mark_feature_used (&fpu_neon_ext_v1
))
14889 first_error (_(BAD_FPU
));
14893 if ((check
& NEON_CHECK_ARCH8
)
14894 && !mark_feature_used (&fpu_neon_ext_armv8
))
14896 first_error (_(BAD_FPU
));
14904 do_neon_addsub_if_i (void)
14906 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14909 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14912 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14913 affected if we specify unsigned args. */
14914 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14917 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14919 V<op> A,B (A is operand 0, B is operand 2)
14924 so handle that case specially. */
14927 neon_exchange_operands (void)
14929 if (inst
.operands
[1].present
)
14931 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14933 /* Swap operands[1] and operands[2]. */
14934 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14935 inst
.operands
[1] = inst
.operands
[2];
14936 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14941 inst
.operands
[1] = inst
.operands
[2];
14942 inst
.operands
[2] = inst
.operands
[0];
14947 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14949 if (inst
.operands
[2].isreg
)
14952 neon_exchange_operands ();
14953 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14957 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14958 struct neon_type_el et
= neon_check_type (2, rs
,
14959 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14961 NEON_ENCODE (IMMED
, inst
);
14962 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14963 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14964 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14965 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14966 inst
.instruction
|= neon_quad (rs
) << 6;
14967 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14968 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14970 neon_dp_fixup (&inst
);
14977 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
14981 do_neon_cmp_inv (void)
14983 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
14989 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14992 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14993 scalars, which are encoded in 5 bits, M : Rm.
14994 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14995 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14999 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15001 unsigned regno
= NEON_SCALAR_REG (scalar
);
15002 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15007 if (regno
> 7 || elno
> 3)
15009 return regno
| (elno
<< 3);
15012 if (regno
> 15 || elno
> 1)
15014 return regno
| (elno
<< 4);
15018 first_error (_("scalar out of range for multiply instruction"));
15024 /* Encode multiply / multiply-accumulate scalar instructions. */
15027 neon_mul_mac (struct neon_type_el et
, int ubit
)
15031 /* Give a more helpful error message if we have an invalid type. */
15032 if (et
.type
== NT_invtype
)
15035 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15036 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15037 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15038 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15039 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15040 inst
.instruction
|= LOW4 (scalar
);
15041 inst
.instruction
|= HI1 (scalar
) << 5;
15042 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15043 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15044 inst
.instruction
|= (ubit
!= 0) << 24;
15046 neon_dp_fixup (&inst
);
15050 do_neon_mac_maybe_scalar (void)
15052 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15055 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15058 if (inst
.operands
[2].isscalar
)
15060 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15061 struct neon_type_el et
= neon_check_type (3, rs
,
15062 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15063 NEON_ENCODE (SCALAR
, inst
);
15064 neon_mul_mac (et
, neon_quad (rs
));
15068 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15069 affected if we specify unsigned args. */
15070 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15075 do_neon_fmac (void)
15077 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15080 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15083 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15089 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15090 struct neon_type_el et
= neon_check_type (3, rs
,
15091 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15092 neon_three_same (neon_quad (rs
), 0, et
.size
);
15095 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15096 same types as the MAC equivalents. The polynomial type for this instruction
15097 is encoded the same as the integer type. */
15102 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15105 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15108 if (inst
.operands
[2].isscalar
)
15109 do_neon_mac_maybe_scalar ();
15111 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15115 do_neon_qdmulh (void)
15117 if (inst
.operands
[2].isscalar
)
15119 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15120 struct neon_type_el et
= neon_check_type (3, rs
,
15121 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15122 NEON_ENCODE (SCALAR
, inst
);
15123 neon_mul_mac (et
, neon_quad (rs
));
15127 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15128 struct neon_type_el et
= neon_check_type (3, rs
,
15129 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15130 NEON_ENCODE (INTEGER
, inst
);
15131 /* The U bit (rounding) comes from bit mask. */
15132 neon_three_same (neon_quad (rs
), 0, et
.size
);
15137 do_neon_qrdmlah (void)
15139 /* Check we're on the correct architecture. */
15140 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15142 _("instruction form not available on this architecture.");
15143 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15145 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15146 record_feature_use (&fpu_neon_ext_v8_1
);
15149 if (inst
.operands
[2].isscalar
)
15151 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15152 struct neon_type_el et
= neon_check_type (3, rs
,
15153 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15154 NEON_ENCODE (SCALAR
, inst
);
15155 neon_mul_mac (et
, neon_quad (rs
));
15159 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15160 struct neon_type_el et
= neon_check_type (3, rs
,
15161 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15162 NEON_ENCODE (INTEGER
, inst
);
15163 /* The U bit (rounding) comes from bit mask. */
15164 neon_three_same (neon_quad (rs
), 0, et
.size
);
15169 do_neon_fcmp_absolute (void)
15171 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15172 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15173 N_F_16_32
| N_KEY
);
15174 /* Size field comes from bit mask. */
15175 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15179 do_neon_fcmp_absolute_inv (void)
15181 neon_exchange_operands ();
15182 do_neon_fcmp_absolute ();
15186 do_neon_step (void)
15188 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15189 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15190 N_F_16_32
| N_KEY
);
15191 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15195 do_neon_abs_neg (void)
15197 enum neon_shape rs
;
15198 struct neon_type_el et
;
15200 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15203 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15206 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15207 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15209 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15210 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15211 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15212 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15213 inst
.instruction
|= neon_quad (rs
) << 6;
15214 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15215 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15217 neon_dp_fixup (&inst
);
15223 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15224 struct neon_type_el et
= neon_check_type (2, rs
,
15225 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15226 int imm
= inst
.operands
[2].imm
;
15227 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15228 _("immediate out of range for insert"));
15229 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15235 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15236 struct neon_type_el et
= neon_check_type (2, rs
,
15237 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15238 int imm
= inst
.operands
[2].imm
;
15239 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15240 _("immediate out of range for insert"));
15241 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15245 do_neon_qshlu_imm (void)
15247 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15248 struct neon_type_el et
= neon_check_type (2, rs
,
15249 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15250 int imm
= inst
.operands
[2].imm
;
15251 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15252 _("immediate out of range for shift"));
15253 /* Only encodes the 'U present' variant of the instruction.
15254 In this case, signed types have OP (bit 8) set to 0.
15255 Unsigned types have OP set to 1. */
15256 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15257 /* The rest of the bits are the same as other immediate shifts. */
15258 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15262 do_neon_qmovn (void)
15264 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15265 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15266 /* Saturating move where operands can be signed or unsigned, and the
15267 destination has the same signedness. */
15268 NEON_ENCODE (INTEGER
, inst
);
15269 if (et
.type
== NT_unsigned
)
15270 inst
.instruction
|= 0xc0;
15272 inst
.instruction
|= 0x80;
15273 neon_two_same (0, 1, et
.size
/ 2);
15277 do_neon_qmovun (void)
15279 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15280 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15281 /* Saturating move with unsigned results. Operands must be signed. */
15282 NEON_ENCODE (INTEGER
, inst
);
15283 neon_two_same (0, 1, et
.size
/ 2);
15287 do_neon_rshift_sat_narrow (void)
15289 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15290 or unsigned. If operands are unsigned, results must also be unsigned. */
15291 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15292 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15293 int imm
= inst
.operands
[2].imm
;
15294 /* This gets the bounds check, size encoding and immediate bits calculation
15298 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15299 VQMOVN.I<size> <Dd>, <Qm>. */
15302 inst
.operands
[2].present
= 0;
15303 inst
.instruction
= N_MNEM_vqmovn
;
15308 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15309 _("immediate out of range"));
15310 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15314 do_neon_rshift_sat_narrow_u (void)
15316 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15317 or unsigned. If operands are unsigned, results must also be unsigned. */
15318 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15319 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15320 int imm
= inst
.operands
[2].imm
;
15321 /* This gets the bounds check, size encoding and immediate bits calculation
15325 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15326 VQMOVUN.I<size> <Dd>, <Qm>. */
15329 inst
.operands
[2].present
= 0;
15330 inst
.instruction
= N_MNEM_vqmovun
;
15335 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15336 _("immediate out of range"));
15337 /* FIXME: The manual is kind of unclear about what value U should have in
15338 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15340 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15344 do_neon_movn (void)
15346 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15347 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15348 NEON_ENCODE (INTEGER
, inst
);
15349 neon_two_same (0, 1, et
.size
/ 2);
15353 do_neon_rshift_narrow (void)
15355 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15356 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15357 int imm
= inst
.operands
[2].imm
;
15358 /* This gets the bounds check, size encoding and immediate bits calculation
15362 /* If immediate is zero then we are a pseudo-instruction for
15363 VMOVN.I<size> <Dd>, <Qm> */
15366 inst
.operands
[2].present
= 0;
15367 inst
.instruction
= N_MNEM_vmovn
;
15372 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15373 _("immediate out of range for narrowing operation"));
15374 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15378 do_neon_shll (void)
15380 /* FIXME: Type checking when lengthening. */
15381 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15382 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15383 unsigned imm
= inst
.operands
[2].imm
;
15385 if (imm
== et
.size
)
15387 /* Maximum shift variant. */
15388 NEON_ENCODE (INTEGER
, inst
);
15389 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15390 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15391 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15392 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15393 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15395 neon_dp_fixup (&inst
);
15399 /* A more-specific type check for non-max versions. */
15400 et
= neon_check_type (2, NS_QDI
,
15401 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15402 NEON_ENCODE (IMMED
, inst
);
15403 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15407 /* Check the various types for the VCVT instruction, and return which version
15408 the current instruction is. */
15410 #define CVT_FLAVOUR_VAR \
15411 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15412 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15413 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15414 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15415 /* Half-precision conversions. */ \
15416 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15417 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15418 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15419 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15420 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15421 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15422 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15423 Compared with single/double precision variants, only the co-processor \
15424 field is different, so the encoding flow is reused here. */ \
15425 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15426 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15427 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15428 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15429 /* VFP instructions. */ \
15430 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15431 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15432 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15433 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15434 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15435 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15436 /* VFP instructions with bitshift. */ \
15437 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15438 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15439 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15440 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15441 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15442 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15443 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15444 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15446 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15447 neon_cvt_flavour_##C,
15449 /* The different types of conversions we can do. */
15450 enum neon_cvt_flavour
15453 neon_cvt_flavour_invalid
,
15454 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15459 static enum neon_cvt_flavour
15460 get_neon_cvt_flavour (enum neon_shape rs
)
15462 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15463 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15464 if (et.type != NT_invtype) \
15466 inst.error = NULL; \
15467 return (neon_cvt_flavour_##C); \
15470 struct neon_type_el et
;
15471 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15472 || rs
== NS_FF
) ? N_VFP
: 0;
15473 /* The instruction versions which take an immediate take one register
15474 argument, which is extended to the width of the full register. Thus the
15475 "source" and "destination" registers must have the same width. Hack that
15476 here by making the size equal to the key (wider, in this case) operand. */
15477 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15481 return neon_cvt_flavour_invalid
;
15496 /* Neon-syntax VFP conversions. */
15499 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15501 const char *opname
= 0;
15503 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15504 || rs
== NS_FHI
|| rs
== NS_HFI
)
15506 /* Conversions with immediate bitshift. */
15507 const char *enc
[] =
15509 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15515 if (flavour
< (int) ARRAY_SIZE (enc
))
15517 opname
= enc
[flavour
];
15518 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15519 _("operands 0 and 1 must be the same register"));
15520 inst
.operands
[1] = inst
.operands
[2];
15521 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15526 /* Conversions without bitshift. */
15527 const char *enc
[] =
15529 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15535 if (flavour
< (int) ARRAY_SIZE (enc
))
15536 opname
= enc
[flavour
];
15540 do_vfp_nsyn_opcode (opname
);
15542 /* ARMv8.2 fp16 VCVT instruction. */
15543 if (flavour
== neon_cvt_flavour_s32_f16
15544 || flavour
== neon_cvt_flavour_u32_f16
15545 || flavour
== neon_cvt_flavour_f16_u32
15546 || flavour
== neon_cvt_flavour_f16_s32
)
15547 do_scalar_fp16_v82_encode ();
15551 do_vfp_nsyn_cvtz (void)
15553 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15554 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15555 const char *enc
[] =
15557 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15563 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15564 do_vfp_nsyn_opcode (enc
[flavour
]);
15568 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15569 enum neon_cvt_mode mode
)
15574 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15575 D register operands. */
15576 if (flavour
== neon_cvt_flavour_s32_f64
15577 || flavour
== neon_cvt_flavour_u32_f64
)
15578 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15581 if (flavour
== neon_cvt_flavour_s32_f16
15582 || flavour
== neon_cvt_flavour_u32_f16
)
15583 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15586 set_it_insn_type (OUTSIDE_IT_INSN
);
15590 case neon_cvt_flavour_s32_f64
:
15594 case neon_cvt_flavour_s32_f32
:
15598 case neon_cvt_flavour_s32_f16
:
15602 case neon_cvt_flavour_u32_f64
:
15606 case neon_cvt_flavour_u32_f32
:
15610 case neon_cvt_flavour_u32_f16
:
15615 first_error (_("invalid instruction shape"));
15621 case neon_cvt_mode_a
: rm
= 0; break;
15622 case neon_cvt_mode_n
: rm
= 1; break;
15623 case neon_cvt_mode_p
: rm
= 2; break;
15624 case neon_cvt_mode_m
: rm
= 3; break;
15625 default: first_error (_("invalid rounding mode")); return;
15628 NEON_ENCODE (FPV8
, inst
);
15629 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15630 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15631 inst
.instruction
|= sz
<< 8;
15633 /* ARMv8.2 fp16 VCVT instruction. */
15634 if (flavour
== neon_cvt_flavour_s32_f16
15635 ||flavour
== neon_cvt_flavour_u32_f16
)
15636 do_scalar_fp16_v82_encode ();
15637 inst
.instruction
|= op
<< 7;
15638 inst
.instruction
|= rm
<< 16;
15639 inst
.instruction
|= 0xf0000000;
15640 inst
.is_neon
= TRUE
;
15644 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15646 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15647 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15648 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15650 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15652 if (flavour
== neon_cvt_flavour_invalid
)
15655 /* PR11109: Handle round-to-zero for VCVT conversions. */
15656 if (mode
== neon_cvt_mode_z
15657 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15658 && (flavour
== neon_cvt_flavour_s16_f16
15659 || flavour
== neon_cvt_flavour_u16_f16
15660 || flavour
== neon_cvt_flavour_s32_f32
15661 || flavour
== neon_cvt_flavour_u32_f32
15662 || flavour
== neon_cvt_flavour_s32_f64
15663 || flavour
== neon_cvt_flavour_u32_f64
)
15664 && (rs
== NS_FD
|| rs
== NS_FF
))
15666 do_vfp_nsyn_cvtz ();
15670 /* ARMv8.2 fp16 VCVT conversions. */
15671 if (mode
== neon_cvt_mode_z
15672 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15673 && (flavour
== neon_cvt_flavour_s32_f16
15674 || flavour
== neon_cvt_flavour_u32_f16
)
15677 do_vfp_nsyn_cvtz ();
15678 do_scalar_fp16_v82_encode ();
15682 /* VFP rather than Neon conversions. */
15683 if (flavour
>= neon_cvt_flavour_first_fp
)
15685 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15686 do_vfp_nsyn_cvt (rs
, flavour
);
15688 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15699 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15700 0x0000100, 0x1000100, 0x0, 0x1000000};
15702 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15705 /* Fixed-point conversion with #0 immediate is encoded as an
15706 integer conversion. */
15707 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15709 NEON_ENCODE (IMMED
, inst
);
15710 if (flavour
!= neon_cvt_flavour_invalid
)
15711 inst
.instruction
|= enctab
[flavour
];
15712 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15713 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15714 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15715 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15716 inst
.instruction
|= neon_quad (rs
) << 6;
15717 inst
.instruction
|= 1 << 21;
15718 if (flavour
< neon_cvt_flavour_s16_f16
)
15720 inst
.instruction
|= 1 << 21;
15721 immbits
= 32 - inst
.operands
[2].imm
;
15722 inst
.instruction
|= immbits
<< 16;
15726 inst
.instruction
|= 3 << 20;
15727 immbits
= 16 - inst
.operands
[2].imm
;
15728 inst
.instruction
|= immbits
<< 16;
15729 inst
.instruction
&= ~(1 << 9);
15732 neon_dp_fixup (&inst
);
15738 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15740 NEON_ENCODE (FLOAT
, inst
);
15741 set_it_insn_type (OUTSIDE_IT_INSN
);
15743 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15746 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15747 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15748 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15749 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15750 inst
.instruction
|= neon_quad (rs
) << 6;
15751 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15752 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15753 inst
.instruction
|= mode
<< 8;
15754 if (flavour
== neon_cvt_flavour_u16_f16
15755 || flavour
== neon_cvt_flavour_s16_f16
)
15756 /* Mask off the original size bits and reencode them. */
15757 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15760 inst
.instruction
|= 0xfc000000;
15762 inst
.instruction
|= 0xf0000000;
15768 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15769 0x100, 0x180, 0x0, 0x080};
15771 NEON_ENCODE (INTEGER
, inst
);
15773 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15776 if (flavour
!= neon_cvt_flavour_invalid
)
15777 inst
.instruction
|= enctab
[flavour
];
15779 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15780 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15781 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15782 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15783 inst
.instruction
|= neon_quad (rs
) << 6;
15784 if (flavour
>= neon_cvt_flavour_s16_f16
15785 && flavour
<= neon_cvt_flavour_f16_u16
)
15786 /* Half precision. */
15787 inst
.instruction
|= 1 << 18;
15789 inst
.instruction
|= 2 << 18;
15791 neon_dp_fixup (&inst
);
15796 /* Half-precision conversions for Advanced SIMD -- neon. */
15801 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15803 as_bad (_("operand size must match register width"));
15808 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15810 as_bad (_("operand size must match register width"));
15815 inst
.instruction
= 0x3b60600;
15817 inst
.instruction
= 0x3b60700;
15819 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15820 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15821 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15822 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15823 neon_dp_fixup (&inst
);
15827 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15828 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15829 do_vfp_nsyn_cvt (rs
, flavour
);
15831 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15836 do_neon_cvtr (void)
15838 do_neon_cvt_1 (neon_cvt_mode_x
);
15844 do_neon_cvt_1 (neon_cvt_mode_z
);
15848 do_neon_cvta (void)
15850 do_neon_cvt_1 (neon_cvt_mode_a
);
15854 do_neon_cvtn (void)
15856 do_neon_cvt_1 (neon_cvt_mode_n
);
15860 do_neon_cvtp (void)
15862 do_neon_cvt_1 (neon_cvt_mode_p
);
15866 do_neon_cvtm (void)
15868 do_neon_cvt_1 (neon_cvt_mode_m
);
15872 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15875 mark_feature_used (&fpu_vfp_ext_armv8
);
15877 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15878 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15879 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15880 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15881 inst
.instruction
|= to
? 0x10000 : 0;
15882 inst
.instruction
|= t
? 0x80 : 0;
15883 inst
.instruction
|= is_double
? 0x100 : 0;
15884 do_vfp_cond_or_thumb ();
15888 do_neon_cvttb_1 (bfd_boolean t
)
15890 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15891 NS_DF
, NS_DH
, NS_NULL
);
15895 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15898 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15900 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15903 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15905 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15907 /* The VCVTB and VCVTT instructions with D-register operands
15908 don't work for SP only targets. */
15909 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15913 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15915 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15917 /* The VCVTB and VCVTT instructions with D-register operands
15918 don't work for SP only targets. */
15919 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15923 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15930 do_neon_cvtb (void)
15932 do_neon_cvttb_1 (FALSE
);
15937 do_neon_cvtt (void)
15939 do_neon_cvttb_1 (TRUE
);
15943 neon_move_immediate (void)
15945 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15946 struct neon_type_el et
= neon_check_type (2, rs
,
15947 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15948 unsigned immlo
, immhi
= 0, immbits
;
15949 int op
, cmode
, float_p
;
15951 constraint (et
.type
== NT_invtype
,
15952 _("operand size must be specified for immediate VMOV"));
15954 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15955 op
= (inst
.instruction
& (1 << 5)) != 0;
15957 immlo
= inst
.operands
[1].imm
;
15958 if (inst
.operands
[1].regisimm
)
15959 immhi
= inst
.operands
[1].reg
;
15961 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15962 _("immediate has bits set outside the operand size"));
15964 float_p
= inst
.operands
[1].immisfloat
;
15966 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15967 et
.size
, et
.type
)) == FAIL
)
15969 /* Invert relevant bits only. */
15970 neon_invert_size (&immlo
, &immhi
, et
.size
);
15971 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15972 with one or the other; those cases are caught by
15973 neon_cmode_for_move_imm. */
15975 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15976 &op
, et
.size
, et
.type
)) == FAIL
)
15978 first_error (_("immediate out of range"));
15983 inst
.instruction
&= ~(1 << 5);
15984 inst
.instruction
|= op
<< 5;
15986 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15987 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15988 inst
.instruction
|= neon_quad (rs
) << 6;
15989 inst
.instruction
|= cmode
<< 8;
15991 neon_write_immbits (immbits
);
15997 if (inst
.operands
[1].isreg
)
15999 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16001 NEON_ENCODE (INTEGER
, inst
);
16002 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16003 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16004 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16005 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16006 inst
.instruction
|= neon_quad (rs
) << 6;
16010 NEON_ENCODE (IMMED
, inst
);
16011 neon_move_immediate ();
16014 neon_dp_fixup (&inst
);
16017 /* Encode instructions of form:
16019 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16020 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16023 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16025 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16026 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16027 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16028 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16029 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16030 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16031 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16032 inst
.instruction
|= neon_logbits (size
) << 20;
16034 neon_dp_fixup (&inst
);
16038 do_neon_dyadic_long (void)
16040 /* FIXME: Type checking for lengthening op. */
16041 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16042 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16043 neon_mixed_length (et
, et
.size
);
16047 do_neon_abal (void)
16049 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16050 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16051 neon_mixed_length (et
, et
.size
);
16055 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16057 if (inst
.operands
[2].isscalar
)
16059 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16060 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16061 NEON_ENCODE (SCALAR
, inst
);
16062 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16066 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16067 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16068 NEON_ENCODE (INTEGER
, inst
);
16069 neon_mixed_length (et
, et
.size
);
16074 do_neon_mac_maybe_scalar_long (void)
16076 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16080 do_neon_dyadic_wide (void)
16082 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16083 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16084 neon_mixed_length (et
, et
.size
);
16088 do_neon_dyadic_narrow (void)
16090 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16091 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16092 /* Operand sign is unimportant, and the U bit is part of the opcode,
16093 so force the operand type to integer. */
16094 et
.type
= NT_integer
;
16095 neon_mixed_length (et
, et
.size
/ 2);
16099 do_neon_mul_sat_scalar_long (void)
16101 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16105 do_neon_vmull (void)
16107 if (inst
.operands
[2].isscalar
)
16108 do_neon_mac_maybe_scalar_long ();
16111 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16112 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16114 if (et
.type
== NT_poly
)
16115 NEON_ENCODE (POLY
, inst
);
16117 NEON_ENCODE (INTEGER
, inst
);
16119 /* For polynomial encoding the U bit must be zero, and the size must
16120 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16121 obviously, as 0b10). */
16124 /* Check we're on the correct architecture. */
16125 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16127 _("Instruction form not available on this architecture.");
16132 neon_mixed_length (et
, et
.size
);
16139 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16140 struct neon_type_el et
= neon_check_type (3, rs
,
16141 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16142 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16144 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16145 _("shift out of range"));
16146 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16147 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16148 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16149 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16150 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16151 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16152 inst
.instruction
|= neon_quad (rs
) << 6;
16153 inst
.instruction
|= imm
<< 8;
16155 neon_dp_fixup (&inst
);
16161 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16162 struct neon_type_el et
= neon_check_type (2, rs
,
16163 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16164 unsigned op
= (inst
.instruction
>> 7) & 3;
16165 /* N (width of reversed regions) is encoded as part of the bitmask. We
16166 extract it here to check the elements to be reversed are smaller.
16167 Otherwise we'd get a reserved instruction. */
16168 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16169 gas_assert (elsize
!= 0);
16170 constraint (et
.size
>= elsize
,
16171 _("elements must be smaller than reversal region"));
16172 neon_two_same (neon_quad (rs
), 1, et
.size
);
16178 if (inst
.operands
[1].isscalar
)
16180 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16181 struct neon_type_el et
= neon_check_type (2, rs
,
16182 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16183 unsigned sizebits
= et
.size
>> 3;
16184 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16185 int logsize
= neon_logbits (et
.size
);
16186 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16188 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16191 NEON_ENCODE (SCALAR
, inst
);
16192 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16193 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16194 inst
.instruction
|= LOW4 (dm
);
16195 inst
.instruction
|= HI1 (dm
) << 5;
16196 inst
.instruction
|= neon_quad (rs
) << 6;
16197 inst
.instruction
|= x
<< 17;
16198 inst
.instruction
|= sizebits
<< 16;
16200 neon_dp_fixup (&inst
);
16204 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16205 struct neon_type_el et
= neon_check_type (2, rs
,
16206 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16207 /* Duplicate ARM register to lanes of vector. */
16208 NEON_ENCODE (ARMREG
, inst
);
16211 case 8: inst
.instruction
|= 0x400000; break;
16212 case 16: inst
.instruction
|= 0x000020; break;
16213 case 32: inst
.instruction
|= 0x000000; break;
16216 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16217 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16218 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16219 inst
.instruction
|= neon_quad (rs
) << 21;
16220 /* The encoding for this instruction is identical for the ARM and Thumb
16221 variants, except for the condition field. */
16222 do_vfp_cond_or_thumb ();
16226 /* VMOV has particularly many variations. It can be one of:
16227 0. VMOV<c><q> <Qd>, <Qm>
16228 1. VMOV<c><q> <Dd>, <Dm>
16229 (Register operations, which are VORR with Rm = Rn.)
16230 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16231 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16233 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16234 (ARM register to scalar.)
16235 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16236 (Two ARM registers to vector.)
16237 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16238 (Scalar to ARM register.)
16239 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16240 (Vector to two ARM registers.)
16241 8. VMOV.F32 <Sd>, <Sm>
16242 9. VMOV.F64 <Dd>, <Dm>
16243 (VFP register moves.)
16244 10. VMOV.F32 <Sd>, #imm
16245 11. VMOV.F64 <Dd>, #imm
16246 (VFP float immediate load.)
16247 12. VMOV <Rd>, <Sm>
16248 (VFP single to ARM reg.)
16249 13. VMOV <Sd>, <Rm>
16250 (ARM reg to VFP single.)
16251 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16252 (Two ARM regs to two VFP singles.)
16253 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16254 (Two VFP singles to two ARM regs.)
16256 These cases can be disambiguated using neon_select_shape, except cases 1/9
16257 and 3/11 which depend on the operand type too.
16259 All the encoded bits are hardcoded by this function.
16261 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16262 Cases 5, 7 may be used with VFPv2 and above.
16264 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16265 can specify a type where it doesn't make sense to, and is ignored). */
16270 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16271 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16272 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16273 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16274 struct neon_type_el et
;
16275 const char *ldconst
= 0;
16279 case NS_DD
: /* case 1/9. */
16280 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16281 /* It is not an error here if no type is given. */
16283 if (et
.type
== NT_float
&& et
.size
== 64)
16285 do_vfp_nsyn_opcode ("fcpyd");
16288 /* fall through. */
16290 case NS_QQ
: /* case 0/1. */
16292 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16294 /* The architecture manual I have doesn't explicitly state which
16295 value the U bit should have for register->register moves, but
16296 the equivalent VORR instruction has U = 0, so do that. */
16297 inst
.instruction
= 0x0200110;
16298 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16299 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16300 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16301 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16302 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16303 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16304 inst
.instruction
|= neon_quad (rs
) << 6;
16306 neon_dp_fixup (&inst
);
16310 case NS_DI
: /* case 3/11. */
16311 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16313 if (et
.type
== NT_float
&& et
.size
== 64)
16315 /* case 11 (fconstd). */
16316 ldconst
= "fconstd";
16317 goto encode_fconstd
;
16319 /* fall through. */
16321 case NS_QI
: /* case 2/3. */
16322 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16324 inst
.instruction
= 0x0800010;
16325 neon_move_immediate ();
16326 neon_dp_fixup (&inst
);
16329 case NS_SR
: /* case 4. */
16331 unsigned bcdebits
= 0;
16333 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16334 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16336 /* .<size> is optional here, defaulting to .32. */
16337 if (inst
.vectype
.elems
== 0
16338 && inst
.operands
[0].vectype
.type
== NT_invtype
16339 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16341 inst
.vectype
.el
[0].type
= NT_untyped
;
16342 inst
.vectype
.el
[0].size
= 32;
16343 inst
.vectype
.elems
= 1;
16346 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16347 logsize
= neon_logbits (et
.size
);
16349 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16351 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16352 && et
.size
!= 32, _(BAD_FPU
));
16353 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16354 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16358 case 8: bcdebits
= 0x8; break;
16359 case 16: bcdebits
= 0x1; break;
16360 case 32: bcdebits
= 0x0; break;
16364 bcdebits
|= x
<< logsize
;
16366 inst
.instruction
= 0xe000b10;
16367 do_vfp_cond_or_thumb ();
16368 inst
.instruction
|= LOW4 (dn
) << 16;
16369 inst
.instruction
|= HI1 (dn
) << 7;
16370 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16371 inst
.instruction
|= (bcdebits
& 3) << 5;
16372 inst
.instruction
|= (bcdebits
>> 2) << 21;
16376 case NS_DRR
: /* case 5 (fmdrr). */
16377 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16380 inst
.instruction
= 0xc400b10;
16381 do_vfp_cond_or_thumb ();
16382 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16383 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16384 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16385 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16388 case NS_RS
: /* case 6. */
16391 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16392 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16393 unsigned abcdebits
= 0;
16395 /* .<dt> is optional here, defaulting to .32. */
16396 if (inst
.vectype
.elems
== 0
16397 && inst
.operands
[0].vectype
.type
== NT_invtype
16398 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16400 inst
.vectype
.el
[0].type
= NT_untyped
;
16401 inst
.vectype
.el
[0].size
= 32;
16402 inst
.vectype
.elems
= 1;
16405 et
= neon_check_type (2, NS_NULL
,
16406 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16407 logsize
= neon_logbits (et
.size
);
16409 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16411 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16412 && et
.size
!= 32, _(BAD_FPU
));
16413 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16414 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16418 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16419 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16420 case 32: abcdebits
= 0x00; break;
16424 abcdebits
|= x
<< logsize
;
16425 inst
.instruction
= 0xe100b10;
16426 do_vfp_cond_or_thumb ();
16427 inst
.instruction
|= LOW4 (dn
) << 16;
16428 inst
.instruction
|= HI1 (dn
) << 7;
16429 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16430 inst
.instruction
|= (abcdebits
& 3) << 5;
16431 inst
.instruction
|= (abcdebits
>> 2) << 21;
16435 case NS_RRD
: /* case 7 (fmrrd). */
16436 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16439 inst
.instruction
= 0xc500b10;
16440 do_vfp_cond_or_thumb ();
16441 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16442 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16443 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16444 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16447 case NS_FF
: /* case 8 (fcpys). */
16448 do_vfp_nsyn_opcode ("fcpys");
16452 case NS_FI
: /* case 10 (fconsts). */
16453 ldconst
= "fconsts";
16455 if (is_quarter_float (inst
.operands
[1].imm
))
16457 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16458 do_vfp_nsyn_opcode (ldconst
);
16460 /* ARMv8.2 fp16 vmov.f16 instruction. */
16462 do_scalar_fp16_v82_encode ();
16465 first_error (_("immediate out of range"));
16469 case NS_RF
: /* case 12 (fmrs). */
16470 do_vfp_nsyn_opcode ("fmrs");
16471 /* ARMv8.2 fp16 vmov.f16 instruction. */
16473 do_scalar_fp16_v82_encode ();
16477 case NS_FR
: /* case 13 (fmsr). */
16478 do_vfp_nsyn_opcode ("fmsr");
16479 /* ARMv8.2 fp16 vmov.f16 instruction. */
16481 do_scalar_fp16_v82_encode ();
16484 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16485 (one of which is a list), but we have parsed four. Do some fiddling to
16486 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16488 case NS_RRFF
: /* case 14 (fmrrs). */
16489 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16490 _("VFP registers must be adjacent"));
16491 inst
.operands
[2].imm
= 2;
16492 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16493 do_vfp_nsyn_opcode ("fmrrs");
16496 case NS_FFRR
: /* case 15 (fmsrr). */
16497 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16498 _("VFP registers must be adjacent"));
16499 inst
.operands
[1] = inst
.operands
[2];
16500 inst
.operands
[2] = inst
.operands
[3];
16501 inst
.operands
[0].imm
= 2;
16502 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16503 do_vfp_nsyn_opcode ("fmsrr");
16507 /* neon_select_shape has determined that the instruction
16508 shape is wrong and has already set the error message. */
16517 do_neon_rshift_round_imm (void)
16519 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16520 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16521 int imm
= inst
.operands
[2].imm
;
16523 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16526 inst
.operands
[2].present
= 0;
16531 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16532 _("immediate out of range for shift"));
16533 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16538 do_neon_movhf (void)
16540 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16541 constraint (rs
!= NS_HH
, _("invalid suffix"));
16543 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16546 do_vfp_sp_monadic ();
16549 inst
.instruction
|= 0xf0000000;
16553 do_neon_movl (void)
16555 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16556 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16557 unsigned sizebits
= et
.size
>> 3;
16558 inst
.instruction
|= sizebits
<< 19;
16559 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16565 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16566 struct neon_type_el et
= neon_check_type (2, rs
,
16567 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16568 NEON_ENCODE (INTEGER
, inst
);
16569 neon_two_same (neon_quad (rs
), 1, et
.size
);
16573 do_neon_zip_uzp (void)
16575 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16576 struct neon_type_el et
= neon_check_type (2, rs
,
16577 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16578 if (rs
== NS_DD
&& et
.size
== 32)
16580 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16581 inst
.instruction
= N_MNEM_vtrn
;
16585 neon_two_same (neon_quad (rs
), 1, et
.size
);
16589 do_neon_sat_abs_neg (void)
16591 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16592 struct neon_type_el et
= neon_check_type (2, rs
,
16593 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16594 neon_two_same (neon_quad (rs
), 1, et
.size
);
16598 do_neon_pair_long (void)
16600 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16601 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16602 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16603 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16604 neon_two_same (neon_quad (rs
), 1, et
.size
);
16608 do_neon_recip_est (void)
16610 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16611 struct neon_type_el et
= neon_check_type (2, rs
,
16612 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16613 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16614 neon_two_same (neon_quad (rs
), 1, et
.size
);
16620 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16621 struct neon_type_el et
= neon_check_type (2, rs
,
16622 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16623 neon_two_same (neon_quad (rs
), 1, et
.size
);
16629 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16630 struct neon_type_el et
= neon_check_type (2, rs
,
16631 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16632 neon_two_same (neon_quad (rs
), 1, et
.size
);
16638 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16639 struct neon_type_el et
= neon_check_type (2, rs
,
16640 N_EQK
| N_INT
, N_8
| N_KEY
);
16641 neon_two_same (neon_quad (rs
), 1, et
.size
);
16647 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16648 neon_two_same (neon_quad (rs
), 1, -1);
16652 do_neon_tbl_tbx (void)
16654 unsigned listlenbits
;
16655 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16657 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16659 first_error (_("bad list length for table lookup"));
16663 listlenbits
= inst
.operands
[1].imm
- 1;
16664 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16665 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16666 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16667 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16668 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16669 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16670 inst
.instruction
|= listlenbits
<< 8;
16672 neon_dp_fixup (&inst
);
16676 do_neon_ldm_stm (void)
16678 /* P, U and L bits are part of bitmask. */
16679 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16680 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16682 if (inst
.operands
[1].issingle
)
16684 do_vfp_nsyn_ldm_stm (is_dbmode
);
16688 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16689 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16691 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16692 _("register list must contain at least 1 and at most 16 "
16695 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16696 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16697 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16698 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16700 inst
.instruction
|= offsetbits
;
16702 do_vfp_cond_or_thumb ();
16706 do_neon_ldr_str (void)
16708 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16710 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16711 And is UNPREDICTABLE in thumb mode. */
16713 && inst
.operands
[1].reg
== REG_PC
16714 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16717 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16718 else if (warn_on_deprecated
)
16719 as_tsktsk (_("Use of PC here is deprecated"));
16722 if (inst
.operands
[0].issingle
)
16725 do_vfp_nsyn_opcode ("flds");
16727 do_vfp_nsyn_opcode ("fsts");
16729 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16730 if (inst
.vectype
.el
[0].size
== 16)
16731 do_scalar_fp16_v82_encode ();
16736 do_vfp_nsyn_opcode ("fldd");
16738 do_vfp_nsyn_opcode ("fstd");
16742 /* "interleave" version also handles non-interleaving register VLD1/VST1
16746 do_neon_ld_st_interleave (void)
16748 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16749 N_8
| N_16
| N_32
| N_64
);
16750 unsigned alignbits
= 0;
16752 /* The bits in this table go:
16753 0: register stride of one (0) or two (1)
16754 1,2: register list length, minus one (1, 2, 3, 4).
16755 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16756 We use -1 for invalid entries. */
16757 const int typetable
[] =
16759 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16760 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16761 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16762 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16766 if (et
.type
== NT_invtype
)
16769 if (inst
.operands
[1].immisalign
)
16770 switch (inst
.operands
[1].imm
>> 8)
16772 case 64: alignbits
= 1; break;
16774 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16775 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16776 goto bad_alignment
;
16780 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16781 goto bad_alignment
;
16786 first_error (_("bad alignment"));
16790 inst
.instruction
|= alignbits
<< 4;
16791 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16793 /* Bits [4:6] of the immediate in a list specifier encode register stride
16794 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16795 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16796 up the right value for "type" in a table based on this value and the given
16797 list style, then stick it back. */
16798 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16799 | (((inst
.instruction
>> 8) & 3) << 3);
16801 typebits
= typetable
[idx
];
16803 constraint (typebits
== -1, _("bad list type for instruction"));
16804 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16805 _("bad element type for instruction"));
16807 inst
.instruction
&= ~0xf00;
16808 inst
.instruction
|= typebits
<< 8;
16811 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16812 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16813 otherwise. The variable arguments are a list of pairs of legal (size, align)
16814 values, terminated with -1. */
16817 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16820 int result
= FAIL
, thissize
, thisalign
;
16822 if (!inst
.operands
[1].immisalign
)
16828 va_start (ap
, do_alignment
);
16832 thissize
= va_arg (ap
, int);
16833 if (thissize
== -1)
16835 thisalign
= va_arg (ap
, int);
16837 if (size
== thissize
&& align
== thisalign
)
16840 while (result
!= SUCCESS
);
16844 if (result
== SUCCESS
)
16847 first_error (_("unsupported alignment for instruction"));
16853 do_neon_ld_st_lane (void)
16855 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16856 int align_good
, do_alignment
= 0;
16857 int logsize
= neon_logbits (et
.size
);
16858 int align
= inst
.operands
[1].imm
>> 8;
16859 int n
= (inst
.instruction
>> 8) & 3;
16860 int max_el
= 64 / et
.size
;
16862 if (et
.type
== NT_invtype
)
16865 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16866 _("bad list length"));
16867 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16868 _("scalar index out of range"));
16869 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16871 _("stride of 2 unavailable when element size is 8"));
16875 case 0: /* VLD1 / VST1. */
16876 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16878 if (align_good
== FAIL
)
16882 unsigned alignbits
= 0;
16885 case 16: alignbits
= 0x1; break;
16886 case 32: alignbits
= 0x3; break;
16889 inst
.instruction
|= alignbits
<< 4;
16893 case 1: /* VLD2 / VST2. */
16894 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16895 16, 32, 32, 64, -1);
16896 if (align_good
== FAIL
)
16899 inst
.instruction
|= 1 << 4;
16902 case 2: /* VLD3 / VST3. */
16903 constraint (inst
.operands
[1].immisalign
,
16904 _("can't use alignment with this instruction"));
16907 case 3: /* VLD4 / VST4. */
16908 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16909 16, 64, 32, 64, 32, 128, -1);
16910 if (align_good
== FAIL
)
16914 unsigned alignbits
= 0;
16917 case 8: alignbits
= 0x1; break;
16918 case 16: alignbits
= 0x1; break;
16919 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16922 inst
.instruction
|= alignbits
<< 4;
16929 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16930 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16931 inst
.instruction
|= 1 << (4 + logsize
);
16933 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16934 inst
.instruction
|= logsize
<< 10;
16937 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16940 do_neon_ld_dup (void)
16942 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16943 int align_good
, do_alignment
= 0;
16945 if (et
.type
== NT_invtype
)
16948 switch ((inst
.instruction
>> 8) & 3)
16950 case 0: /* VLD1. */
16951 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16952 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16953 &do_alignment
, 16, 16, 32, 32, -1);
16954 if (align_good
== FAIL
)
16956 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16959 case 2: inst
.instruction
|= 1 << 5; break;
16960 default: first_error (_("bad list length")); return;
16962 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16965 case 1: /* VLD2. */
16966 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16967 &do_alignment
, 8, 16, 16, 32, 32, 64,
16969 if (align_good
== FAIL
)
16971 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16972 _("bad list length"));
16973 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16974 inst
.instruction
|= 1 << 5;
16975 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16978 case 2: /* VLD3. */
16979 constraint (inst
.operands
[1].immisalign
,
16980 _("can't use alignment with this instruction"));
16981 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16982 _("bad list length"));
16983 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16984 inst
.instruction
|= 1 << 5;
16985 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16988 case 3: /* VLD4. */
16990 int align
= inst
.operands
[1].imm
>> 8;
16991 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16992 16, 64, 32, 64, 32, 128, -1);
16993 if (align_good
== FAIL
)
16995 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16996 _("bad list length"));
16997 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16998 inst
.instruction
|= 1 << 5;
16999 if (et
.size
== 32 && align
== 128)
17000 inst
.instruction
|= 0x3 << 6;
17002 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17009 inst
.instruction
|= do_alignment
<< 4;
17012 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17013 apart from bits [11:4]. */
17016 do_neon_ldx_stx (void)
17018 if (inst
.operands
[1].isreg
)
17019 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17021 switch (NEON_LANE (inst
.operands
[0].imm
))
17023 case NEON_INTERLEAVE_LANES
:
17024 NEON_ENCODE (INTERLV
, inst
);
17025 do_neon_ld_st_interleave ();
17028 case NEON_ALL_LANES
:
17029 NEON_ENCODE (DUP
, inst
);
17030 if (inst
.instruction
== N_INV
)
17032 first_error ("only loads support such operands");
17039 NEON_ENCODE (LANE
, inst
);
17040 do_neon_ld_st_lane ();
17043 /* L bit comes from bit mask. */
17044 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17045 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17046 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17048 if (inst
.operands
[1].postind
)
17050 int postreg
= inst
.operands
[1].imm
& 0xf;
17051 constraint (!inst
.operands
[1].immisreg
,
17052 _("post-index must be a register"));
17053 constraint (postreg
== 0xd || postreg
== 0xf,
17054 _("bad register for post-index"));
17055 inst
.instruction
|= postreg
;
17059 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17060 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17061 || inst
.reloc
.exp
.X_add_number
!= 0,
17064 if (inst
.operands
[1].writeback
)
17066 inst
.instruction
|= 0xd;
17069 inst
.instruction
|= 0xf;
17073 inst
.instruction
|= 0xf9000000;
17075 inst
.instruction
|= 0xf4000000;
17080 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17082 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17083 D register operands. */
17084 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17085 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17088 NEON_ENCODE (FPV8
, inst
);
17090 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17092 do_vfp_sp_dyadic ();
17094 /* ARMv8.2 fp16 instruction. */
17096 do_scalar_fp16_v82_encode ();
17099 do_vfp_dp_rd_rn_rm ();
17102 inst
.instruction
|= 0x100;
17104 inst
.instruction
|= 0xf0000000;
17110 set_it_insn_type (OUTSIDE_IT_INSN
);
17112 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17113 first_error (_("invalid instruction shape"));
17119 set_it_insn_type (OUTSIDE_IT_INSN
);
17121 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17124 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17127 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17131 do_vrint_1 (enum neon_cvt_mode mode
)
17133 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17134 struct neon_type_el et
;
17139 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17140 D register operands. */
17141 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17142 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17145 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17147 if (et
.type
!= NT_invtype
)
17149 /* VFP encodings. */
17150 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17151 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17152 set_it_insn_type (OUTSIDE_IT_INSN
);
17154 NEON_ENCODE (FPV8
, inst
);
17155 if (rs
== NS_FF
|| rs
== NS_HH
)
17156 do_vfp_sp_monadic ();
17158 do_vfp_dp_rd_rm ();
17162 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17163 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17164 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17165 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17166 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17167 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17168 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17172 inst
.instruction
|= (rs
== NS_DD
) << 8;
17173 do_vfp_cond_or_thumb ();
17175 /* ARMv8.2 fp16 vrint instruction. */
17177 do_scalar_fp16_v82_encode ();
17181 /* Neon encodings (or something broken...). */
17183 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17185 if (et
.type
== NT_invtype
)
17188 set_it_insn_type (OUTSIDE_IT_INSN
);
17189 NEON_ENCODE (FLOAT
, inst
);
17191 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17194 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17195 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17196 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17197 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17198 inst
.instruction
|= neon_quad (rs
) << 6;
17199 /* Mask off the original size bits and reencode them. */
17200 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17201 | neon_logbits (et
.size
) << 18);
17205 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17206 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17207 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17208 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17209 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17210 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17211 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17216 inst
.instruction
|= 0xfc000000;
17218 inst
.instruction
|= 0xf0000000;
17225 do_vrint_1 (neon_cvt_mode_x
);
17231 do_vrint_1 (neon_cvt_mode_z
);
17237 do_vrint_1 (neon_cvt_mode_r
);
17243 do_vrint_1 (neon_cvt_mode_a
);
17249 do_vrint_1 (neon_cvt_mode_n
);
17255 do_vrint_1 (neon_cvt_mode_p
);
17261 do_vrint_1 (neon_cvt_mode_m
);
17264 /* Crypto v1 instructions. */
17266 do_crypto_2op_1 (unsigned elttype
, int op
)
17268 set_it_insn_type (OUTSIDE_IT_INSN
);
17270 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17276 NEON_ENCODE (INTEGER
, inst
);
17277 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17278 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17279 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17280 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17282 inst
.instruction
|= op
<< 6;
17285 inst
.instruction
|= 0xfc000000;
17287 inst
.instruction
|= 0xf0000000;
17291 do_crypto_3op_1 (int u
, int op
)
17293 set_it_insn_type (OUTSIDE_IT_INSN
);
17295 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17296 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17301 NEON_ENCODE (INTEGER
, inst
);
17302 neon_three_same (1, u
, 8 << op
);
17308 do_crypto_2op_1 (N_8
, 0);
17314 do_crypto_2op_1 (N_8
, 1);
17320 do_crypto_2op_1 (N_8
, 2);
17326 do_crypto_2op_1 (N_8
, 3);
17332 do_crypto_3op_1 (0, 0);
17338 do_crypto_3op_1 (0, 1);
17344 do_crypto_3op_1 (0, 2);
17350 do_crypto_3op_1 (0, 3);
17356 do_crypto_3op_1 (1, 0);
17362 do_crypto_3op_1 (1, 1);
17366 do_sha256su1 (void)
17368 do_crypto_3op_1 (1, 2);
17374 do_crypto_2op_1 (N_32
, -1);
17380 do_crypto_2op_1 (N_32
, 0);
17384 do_sha256su0 (void)
17386 do_crypto_2op_1 (N_32
, 1);
17390 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17392 unsigned int Rd
= inst
.operands
[0].reg
;
17393 unsigned int Rn
= inst
.operands
[1].reg
;
17394 unsigned int Rm
= inst
.operands
[2].reg
;
17396 set_it_insn_type (OUTSIDE_IT_INSN
);
17397 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17398 inst
.instruction
|= LOW4 (Rn
) << 16;
17399 inst
.instruction
|= LOW4 (Rm
);
17400 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17401 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17403 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17404 as_warn (UNPRED_REG ("r15"));
17405 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17406 as_warn (UNPRED_REG ("r13"));
17448 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17450 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17451 do_vfp_sp_dp_cvt ();
17452 do_vfp_cond_or_thumb ();
17456 /* Overall per-instruction processing. */
17458 /* We need to be able to fix up arbitrary expressions in some statements.
17459 This is so that we can handle symbols that are an arbitrary distance from
17460 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17461 which returns part of an address in a form which will be valid for
17462 a data instruction. We do this by pushing the expression into a symbol
17463 in the expr_section, and creating a fix for that. */
17466 fix_new_arm (fragS
* frag
,
17480 /* Create an absolute valued symbol, so we have something to
17481 refer to in the object file. Unfortunately for us, gas's
17482 generic expression parsing will already have folded out
17483 any use of .set foo/.type foo %function that may have
17484 been used to set type information of the target location,
17485 that's being specified symbolically. We have to presume
17486 the user knows what they are doing. */
17490 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17492 symbol
= symbol_find_or_make (name
);
17493 S_SET_SEGMENT (symbol
, absolute_section
);
17494 symbol_set_frag (symbol
, &zero_address_frag
);
17495 S_SET_VALUE (symbol
, exp
->X_add_number
);
17496 exp
->X_op
= O_symbol
;
17497 exp
->X_add_symbol
= symbol
;
17498 exp
->X_add_number
= 0;
17504 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17505 (enum bfd_reloc_code_real
) reloc
);
17509 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17510 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17514 /* Mark whether the fix is to a THUMB instruction, or an ARM
17516 new_fix
->tc_fix_data
= thumb_mode
;
17519 /* Create a frg for an instruction requiring relaxation. */
17521 output_relax_insn (void)
17527 /* The size of the instruction is unknown, so tie the debug info to the
17528 start of the instruction. */
17529 dwarf2_emit_insn (0);
17531 switch (inst
.reloc
.exp
.X_op
)
17534 sym
= inst
.reloc
.exp
.X_add_symbol
;
17535 offset
= inst
.reloc
.exp
.X_add_number
;
17539 offset
= inst
.reloc
.exp
.X_add_number
;
17542 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17546 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17547 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17548 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17551 /* Write a 32-bit thumb instruction to buf. */
17553 put_thumb32_insn (char * buf
, unsigned long insn
)
17555 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17556 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17560 output_inst (const char * str
)
17566 as_bad ("%s -- `%s'", inst
.error
, str
);
17571 output_relax_insn ();
17574 if (inst
.size
== 0)
17577 to
= frag_more (inst
.size
);
17578 /* PR 9814: Record the thumb mode into the current frag so that we know
17579 what type of NOP padding to use, if necessary. We override any previous
17580 setting so that if the mode has changed then the NOPS that we use will
17581 match the encoding of the last instruction in the frag. */
17582 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17584 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17586 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17587 put_thumb32_insn (to
, inst
.instruction
);
17589 else if (inst
.size
> INSN_SIZE
)
17591 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17592 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17593 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17596 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17598 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17599 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17600 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17603 dwarf2_emit_insn (inst
.size
);
17607 output_it_inst (int cond
, int mask
, char * to
)
17609 unsigned long instruction
= 0xbf00;
17612 instruction
|= mask
;
17613 instruction
|= cond
<< 4;
17617 to
= frag_more (2);
17619 dwarf2_emit_insn (2);
17623 md_number_to_chars (to
, instruction
, 2);
17628 /* Tag values used in struct asm_opcode's tag field. */
17631 OT_unconditional
, /* Instruction cannot be conditionalized.
17632 The ARM condition field is still 0xE. */
17633 OT_unconditionalF
, /* Instruction cannot be conditionalized
17634 and carries 0xF in its ARM condition field. */
17635 OT_csuffix
, /* Instruction takes a conditional suffix. */
17636 OT_csuffixF
, /* Some forms of the instruction take a conditional
17637 suffix, others place 0xF where the condition field
17639 OT_cinfix3
, /* Instruction takes a conditional infix,
17640 beginning at character index 3. (In
17641 unified mode, it becomes a suffix.) */
17642 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17643 tsts, cmps, cmns, and teqs. */
17644 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17645 character index 3, even in unified mode. Used for
17646 legacy instructions where suffix and infix forms
17647 may be ambiguous. */
17648 OT_csuf_or_in3
, /* Instruction takes either a conditional
17649 suffix or an infix at character index 3. */
17650 OT_odd_infix_unc
, /* This is the unconditional variant of an
17651 instruction that takes a conditional infix
17652 at an unusual position. In unified mode,
17653 this variant will accept a suffix. */
17654 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17655 are the conditional variants of instructions that
17656 take conditional infixes in unusual positions.
17657 The infix appears at character index
17658 (tag - OT_odd_infix_0). These are not accepted
17659 in unified mode. */
17662 /* Subroutine of md_assemble, responsible for looking up the primary
17663 opcode from the mnemonic the user wrote. STR points to the
17664 beginning of the mnemonic.
17666 This is not simply a hash table lookup, because of conditional
17667 variants. Most instructions have conditional variants, which are
17668 expressed with a _conditional affix_ to the mnemonic. If we were
17669 to encode each conditional variant as a literal string in the opcode
17670 table, it would have approximately 20,000 entries.
17672 Most mnemonics take this affix as a suffix, and in unified syntax,
17673 'most' is upgraded to 'all'. However, in the divided syntax, some
17674 instructions take the affix as an infix, notably the s-variants of
17675 the arithmetic instructions. Of those instructions, all but six
17676 have the infix appear after the third character of the mnemonic.
17678 Accordingly, the algorithm for looking up primary opcodes given
17681 1. Look up the identifier in the opcode table.
17682 If we find a match, go to step U.
17684 2. Look up the last two characters of the identifier in the
17685 conditions table. If we find a match, look up the first N-2
17686 characters of the identifier in the opcode table. If we
17687 find a match, go to step CE.
17689 3. Look up the fourth and fifth characters of the identifier in
17690 the conditions table. If we find a match, extract those
17691 characters from the identifier, and look up the remaining
17692 characters in the opcode table. If we find a match, go
17697 U. Examine the tag field of the opcode structure, in case this is
17698 one of the six instructions with its conditional infix in an
17699 unusual place. If it is, the tag tells us where to find the
17700 infix; look it up in the conditions table and set inst.cond
17701 accordingly. Otherwise, this is an unconditional instruction.
17702 Again set inst.cond accordingly. Return the opcode structure.
17704 CE. Examine the tag field to make sure this is an instruction that
17705 should receive a conditional suffix. If it is not, fail.
17706 Otherwise, set inst.cond from the suffix we already looked up,
17707 and return the opcode structure.
17709 CM. Examine the tag field to make sure this is an instruction that
17710 should receive a conditional infix after the third character.
17711 If it is not, fail. Otherwise, undo the edits to the current
17712 line of input and proceed as for case CE. */
17714 static const struct asm_opcode
*
17715 opcode_lookup (char **str
)
17719 const struct asm_opcode
*opcode
;
17720 const struct asm_cond
*cond
;
17723 /* Scan up to the end of the mnemonic, which must end in white space,
17724 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17725 for (base
= end
= *str
; *end
!= '\0'; end
++)
17726 if (*end
== ' ' || *end
== '.')
17732 /* Handle a possible width suffix and/or Neon type suffix. */
17737 /* The .w and .n suffixes are only valid if the unified syntax is in
17739 if (unified_syntax
&& end
[1] == 'w')
17741 else if (unified_syntax
&& end
[1] == 'n')
17746 inst
.vectype
.elems
= 0;
17748 *str
= end
+ offset
;
17750 if (end
[offset
] == '.')
17752 /* See if we have a Neon type suffix (possible in either unified or
17753 non-unified ARM syntax mode). */
17754 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17757 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17763 /* Look for unaffixed or special-case affixed mnemonic. */
17764 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17769 if (opcode
->tag
< OT_odd_infix_0
)
17771 inst
.cond
= COND_ALWAYS
;
17775 if (warn_on_deprecated
&& unified_syntax
)
17776 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17777 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17778 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17781 inst
.cond
= cond
->value
;
17785 /* Cannot have a conditional suffix on a mnemonic of less than two
17787 if (end
- base
< 3)
17790 /* Look for suffixed mnemonic. */
17792 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17793 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17795 if (opcode
&& cond
)
17798 switch (opcode
->tag
)
17800 case OT_cinfix3_legacy
:
17801 /* Ignore conditional suffixes matched on infix only mnemonics. */
17805 case OT_cinfix3_deprecated
:
17806 case OT_odd_infix_unc
:
17807 if (!unified_syntax
)
17809 /* Fall through. */
17813 case OT_csuf_or_in3
:
17814 inst
.cond
= cond
->value
;
17817 case OT_unconditional
:
17818 case OT_unconditionalF
:
17820 inst
.cond
= cond
->value
;
17823 /* Delayed diagnostic. */
17824 inst
.error
= BAD_COND
;
17825 inst
.cond
= COND_ALWAYS
;
17834 /* Cannot have a usual-position infix on a mnemonic of less than
17835 six characters (five would be a suffix). */
17836 if (end
- base
< 6)
17839 /* Look for infixed mnemonic in the usual position. */
17841 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17845 memcpy (save
, affix
, 2);
17846 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17847 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17849 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17850 memcpy (affix
, save
, 2);
17853 && (opcode
->tag
== OT_cinfix3
17854 || opcode
->tag
== OT_cinfix3_deprecated
17855 || opcode
->tag
== OT_csuf_or_in3
17856 || opcode
->tag
== OT_cinfix3_legacy
))
17859 if (warn_on_deprecated
&& unified_syntax
17860 && (opcode
->tag
== OT_cinfix3
17861 || opcode
->tag
== OT_cinfix3_deprecated
))
17862 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17864 inst
.cond
= cond
->value
;
17871 /* This function generates an initial IT instruction, leaving its block
17872 virtually open for the new instructions. Eventually,
17873 the mask will be updated by now_it_add_mask () each time
17874 a new instruction needs to be included in the IT block.
17875 Finally, the block is closed with close_automatic_it_block ().
17876 The block closure can be requested either from md_assemble (),
17877 a tencode (), or due to a label hook. */
17880 new_automatic_it_block (int cond
)
17882 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17883 now_it
.mask
= 0x18;
17885 now_it
.block_length
= 1;
17886 mapping_state (MAP_THUMB
);
17887 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17888 now_it
.warn_deprecated
= FALSE
;
17889 now_it
.insn_cond
= TRUE
;
17892 /* Close an automatic IT block.
17893 See comments in new_automatic_it_block (). */
17896 close_automatic_it_block (void)
17898 now_it
.mask
= 0x10;
17899 now_it
.block_length
= 0;
17902 /* Update the mask of the current automatically-generated IT
17903 instruction. See comments in new_automatic_it_block (). */
17906 now_it_add_mask (int cond
)
17908 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17909 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17910 | ((bitvalue) << (nbit)))
17911 const int resulting_bit
= (cond
& 1);
17913 now_it
.mask
&= 0xf;
17914 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17916 (5 - now_it
.block_length
));
17917 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17919 ((5 - now_it
.block_length
) - 1) );
17920 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17923 #undef SET_BIT_VALUE
17926 /* The IT blocks handling machinery is accessed through the these functions:
17927 it_fsm_pre_encode () from md_assemble ()
17928 set_it_insn_type () optional, from the tencode functions
17929 set_it_insn_type_last () ditto
17930 in_it_block () ditto
17931 it_fsm_post_encode () from md_assemble ()
17932 force_automatic_it_block_close () from label habdling functions
17935 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17936 initializing the IT insn type with a generic initial value depending
17937 on the inst.condition.
17938 2) During the tencode function, two things may happen:
17939 a) The tencode function overrides the IT insn type by
17940 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17941 b) The tencode function queries the IT block state by
17942 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17944 Both set_it_insn_type and in_it_block run the internal FSM state
17945 handling function (handle_it_state), because: a) setting the IT insn
17946 type may incur in an invalid state (exiting the function),
17947 and b) querying the state requires the FSM to be updated.
17948 Specifically we want to avoid creating an IT block for conditional
17949 branches, so it_fsm_pre_encode is actually a guess and we can't
17950 determine whether an IT block is required until the tencode () routine
17951 has decided what type of instruction this actually it.
17952 Because of this, if set_it_insn_type and in_it_block have to be used,
17953 set_it_insn_type has to be called first.
17955 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17956 determines the insn IT type depending on the inst.cond code.
17957 When a tencode () routine encodes an instruction that can be
17958 either outside an IT block, or, in the case of being inside, has to be
17959 the last one, set_it_insn_type_last () will determine the proper
17960 IT instruction type based on the inst.cond code. Otherwise,
17961 set_it_insn_type can be called for overriding that logic or
17962 for covering other cases.
17964 Calling handle_it_state () may not transition the IT block state to
17965 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
17966 still queried. Instead, if the FSM determines that the state should
17967 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17968 after the tencode () function: that's what it_fsm_post_encode () does.
17970 Since in_it_block () calls the state handling function to get an
17971 updated state, an error may occur (due to invalid insns combination).
17972 In that case, inst.error is set.
17973 Therefore, inst.error has to be checked after the execution of
17974 the tencode () routine.
17976 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17977 any pending state change (if any) that didn't take place in
17978 handle_it_state () as explained above. */
17981 it_fsm_pre_encode (void)
17983 if (inst
.cond
!= COND_ALWAYS
)
17984 inst
.it_insn_type
= INSIDE_IT_INSN
;
17986 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17988 now_it
.state_handled
= 0;
17991 /* IT state FSM handling function. */
17994 handle_it_state (void)
17996 now_it
.state_handled
= 1;
17997 now_it
.insn_cond
= FALSE
;
17999 switch (now_it
.state
)
18001 case OUTSIDE_IT_BLOCK
:
18002 switch (inst
.it_insn_type
)
18004 case OUTSIDE_IT_INSN
:
18007 case INSIDE_IT_INSN
:
18008 case INSIDE_IT_LAST_INSN
:
18009 if (thumb_mode
== 0)
18012 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18013 as_tsktsk (_("Warning: conditional outside an IT block"\
18018 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18019 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18021 /* Automatically generate the IT instruction. */
18022 new_automatic_it_block (inst
.cond
);
18023 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18024 close_automatic_it_block ();
18028 inst
.error
= BAD_OUT_IT
;
18034 case IF_INSIDE_IT_LAST_INSN
:
18035 case NEUTRAL_IT_INSN
:
18039 now_it
.state
= MANUAL_IT_BLOCK
;
18040 now_it
.block_length
= 0;
18045 case AUTOMATIC_IT_BLOCK
:
18046 /* Three things may happen now:
18047 a) We should increment current it block size;
18048 b) We should close current it block (closing insn or 4 insns);
18049 c) We should close current it block and start a new one (due
18050 to incompatible conditions or
18051 4 insns-length block reached). */
18053 switch (inst
.it_insn_type
)
18055 case OUTSIDE_IT_INSN
:
18056 /* The closure of the block shall happen immediately,
18057 so any in_it_block () call reports the block as closed. */
18058 force_automatic_it_block_close ();
18061 case INSIDE_IT_INSN
:
18062 case INSIDE_IT_LAST_INSN
:
18063 case IF_INSIDE_IT_LAST_INSN
:
18064 now_it
.block_length
++;
18066 if (now_it
.block_length
> 4
18067 || !now_it_compatible (inst
.cond
))
18069 force_automatic_it_block_close ();
18070 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18071 new_automatic_it_block (inst
.cond
);
18075 now_it
.insn_cond
= TRUE
;
18076 now_it_add_mask (inst
.cond
);
18079 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18080 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18081 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18082 close_automatic_it_block ();
18085 case NEUTRAL_IT_INSN
:
18086 now_it
.block_length
++;
18087 now_it
.insn_cond
= TRUE
;
18089 if (now_it
.block_length
> 4)
18090 force_automatic_it_block_close ();
18092 now_it_add_mask (now_it
.cc
& 1);
18096 close_automatic_it_block ();
18097 now_it
.state
= MANUAL_IT_BLOCK
;
18102 case MANUAL_IT_BLOCK
:
18104 /* Check conditional suffixes. */
18105 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18108 now_it
.mask
&= 0x1f;
18109 is_last
= (now_it
.mask
== 0x10);
18110 now_it
.insn_cond
= TRUE
;
18112 switch (inst
.it_insn_type
)
18114 case OUTSIDE_IT_INSN
:
18115 inst
.error
= BAD_NOT_IT
;
18118 case INSIDE_IT_INSN
:
18119 if (cond
!= inst
.cond
)
18121 inst
.error
= BAD_IT_COND
;
18126 case INSIDE_IT_LAST_INSN
:
18127 case IF_INSIDE_IT_LAST_INSN
:
18128 if (cond
!= inst
.cond
)
18130 inst
.error
= BAD_IT_COND
;
18135 inst
.error
= BAD_BRANCH
;
18140 case NEUTRAL_IT_INSN
:
18141 /* The BKPT instruction is unconditional even in an IT block. */
18145 inst
.error
= BAD_IT_IT
;
18155 struct depr_insn_mask
18157 unsigned long pattern
;
18158 unsigned long mask
;
18159 const char* description
;
18162 /* List of 16-bit instruction patterns deprecated in an IT block in
18164 static const struct depr_insn_mask depr_it_insns
[] = {
18165 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18166 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18167 { 0xa000, 0xb800, N_("ADR") },
18168 { 0x4800, 0xf800, N_("Literal loads") },
18169 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18170 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18171 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18172 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18173 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18178 it_fsm_post_encode (void)
18182 if (!now_it
.state_handled
)
18183 handle_it_state ();
18185 if (now_it
.insn_cond
18186 && !now_it
.warn_deprecated
18187 && warn_on_deprecated
18188 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18190 if (inst
.instruction
>= 0x10000)
18192 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18193 "deprecated in ARMv8"));
18194 now_it
.warn_deprecated
= TRUE
;
18198 const struct depr_insn_mask
*p
= depr_it_insns
;
18200 while (p
->mask
!= 0)
18202 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18204 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18205 "of the following class are deprecated in ARMv8: "
18206 "%s"), p
->description
);
18207 now_it
.warn_deprecated
= TRUE
;
18215 if (now_it
.block_length
> 1)
18217 as_tsktsk (_("IT blocks containing more than one conditional "
18218 "instruction are deprecated in ARMv8"));
18219 now_it
.warn_deprecated
= TRUE
;
18223 is_last
= (now_it
.mask
== 0x10);
18226 now_it
.state
= OUTSIDE_IT_BLOCK
;
18232 force_automatic_it_block_close (void)
18234 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18236 close_automatic_it_block ();
18237 now_it
.state
= OUTSIDE_IT_BLOCK
;
18245 if (!now_it
.state_handled
)
18246 handle_it_state ();
18248 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18251 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18252 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18253 here, hence the "known" in the function name. */
18256 known_t32_only_insn (const struct asm_opcode
*opcode
)
18258 /* Original Thumb-1 wide instruction. */
18259 if (opcode
->tencode
== do_t_blx
18260 || opcode
->tencode
== do_t_branch23
18261 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18262 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18265 /* Wide-only instruction added to ARMv8-M Baseline. */
18266 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18267 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18268 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18269 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18275 /* Whether wide instruction variant can be used if available for a valid OPCODE
18279 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18281 if (known_t32_only_insn (opcode
))
18284 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18285 of variant T3 of B.W is checked in do_t_branch. */
18286 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18287 && opcode
->tencode
== do_t_branch
)
18290 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18291 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18292 && opcode
->tencode
== do_t_mov_cmp
18293 /* Make sure CMP instruction is not affected. */
18294 && opcode
->aencode
== do_mov
)
18297 /* Wide instruction variants of all instructions with narrow *and* wide
18298 variants become available with ARMv6t2. Other opcodes are either
18299 narrow-only or wide-only and are thus available if OPCODE is valid. */
18300 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18303 /* OPCODE with narrow only instruction variant or wide variant not
18309 md_assemble (char *str
)
18312 const struct asm_opcode
* opcode
;
18314 /* Align the previous label if needed. */
18315 if (last_label_seen
!= NULL
)
18317 symbol_set_frag (last_label_seen
, frag_now
);
18318 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18319 S_SET_SEGMENT (last_label_seen
, now_seg
);
18322 memset (&inst
, '\0', sizeof (inst
));
18323 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18325 opcode
= opcode_lookup (&p
);
18328 /* It wasn't an instruction, but it might be a register alias of
18329 the form alias .req reg, or a Neon .dn/.qn directive. */
18330 if (! create_register_alias (str
, p
)
18331 && ! create_neon_reg_alias (str
, p
))
18332 as_bad (_("bad instruction `%s'"), str
);
18337 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18338 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18340 /* The value which unconditional instructions should have in place of the
18341 condition field. */
18342 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18346 arm_feature_set variant
;
18348 variant
= cpu_variant
;
18349 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18350 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18351 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18352 /* Check that this instruction is supported for this CPU. */
18353 if (!opcode
->tvariant
18354 || (thumb_mode
== 1
18355 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18357 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18360 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18361 && opcode
->tencode
!= do_t_branch
)
18363 as_bad (_("Thumb does not support conditional execution"));
18367 /* Two things are addressed here:
18368 1) Implicit require narrow instructions on Thumb-1.
18369 This avoids relaxation accidentally introducing Thumb-2
18371 2) Reject wide instructions in non Thumb-2 cores.
18373 Only instructions with narrow and wide variants need to be handled
18374 but selecting all non wide-only instructions is easier. */
18375 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18376 && !t32_insn_ok (variant
, opcode
))
18378 if (inst
.size_req
== 0)
18380 else if (inst
.size_req
== 4)
18382 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18383 as_bad (_("selected processor does not support 32bit wide "
18384 "variant of instruction `%s'"), str
);
18386 as_bad (_("selected processor does not support `%s' in "
18387 "Thumb-2 mode"), str
);
18392 inst
.instruction
= opcode
->tvalue
;
18394 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18396 /* Prepare the it_insn_type for those encodings that don't set
18398 it_fsm_pre_encode ();
18400 opcode
->tencode ();
18402 it_fsm_post_encode ();
18405 if (!(inst
.error
|| inst
.relax
))
18407 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18408 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18409 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18411 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18416 /* Something has gone badly wrong if we try to relax a fixed size
18418 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18420 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18421 *opcode
->tvariant
);
18422 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18423 set those bits when Thumb-2 32-bit instructions are seen. The impact
18424 of relaxable instructions will be considered later after we finish all
18426 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18427 variant
= arm_arch_none
;
18429 variant
= cpu_variant
;
18430 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18431 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18434 check_neon_suffixes
;
18438 mapping_state (MAP_THUMB
);
18441 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18445 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18446 is_bx
= (opcode
->aencode
== do_bx
);
18448 /* Check that this instruction is supported for this CPU. */
18449 if (!(is_bx
&& fix_v4bx
)
18450 && !(opcode
->avariant
&&
18451 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18453 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18458 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18462 inst
.instruction
= opcode
->avalue
;
18463 if (opcode
->tag
== OT_unconditionalF
)
18464 inst
.instruction
|= 0xFU
<< 28;
18466 inst
.instruction
|= inst
.cond
<< 28;
18467 inst
.size
= INSN_SIZE
;
18468 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18470 it_fsm_pre_encode ();
18471 opcode
->aencode ();
18472 it_fsm_post_encode ();
18474 /* Arm mode bx is marked as both v4T and v5 because it's still required
18475 on a hypothetical non-thumb v5 core. */
18477 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18479 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18480 *opcode
->avariant
);
18482 check_neon_suffixes
;
18486 mapping_state (MAP_ARM
);
18491 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18499 check_it_blocks_finished (void)
18504 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18505 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18506 == MANUAL_IT_BLOCK
)
18508 as_warn (_("section '%s' finished with an open IT block."),
18512 if (now_it
.state
== MANUAL_IT_BLOCK
)
18513 as_warn (_("file finished with an open IT block."));
18517 /* Various frobbings of labels and their addresses. */
18520 arm_start_line_hook (void)
18522 last_label_seen
= NULL
;
18526 arm_frob_label (symbolS
* sym
)
18528 last_label_seen
= sym
;
18530 ARM_SET_THUMB (sym
, thumb_mode
);
18532 #if defined OBJ_COFF || defined OBJ_ELF
18533 ARM_SET_INTERWORK (sym
, support_interwork
);
18536 force_automatic_it_block_close ();
18538 /* Note - do not allow local symbols (.Lxxx) to be labelled
18539 as Thumb functions. This is because these labels, whilst
18540 they exist inside Thumb code, are not the entry points for
18541 possible ARM->Thumb calls. Also, these labels can be used
18542 as part of a computed goto or switch statement. eg gcc
18543 can generate code that looks like this:
18545 ldr r2, [pc, .Laaa]
18555 The first instruction loads the address of the jump table.
18556 The second instruction converts a table index into a byte offset.
18557 The third instruction gets the jump address out of the table.
18558 The fourth instruction performs the jump.
18560 If the address stored at .Laaa is that of a symbol which has the
18561 Thumb_Func bit set, then the linker will arrange for this address
18562 to have the bottom bit set, which in turn would mean that the
18563 address computation performed by the third instruction would end
18564 up with the bottom bit set. Since the ARM is capable of unaligned
18565 word loads, the instruction would then load the incorrect address
18566 out of the jump table, and chaos would ensue. */
18567 if (label_is_thumb_function_name
18568 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18569 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18571 /* When the address of a Thumb function is taken the bottom
18572 bit of that address should be set. This will allow
18573 interworking between Arm and Thumb functions to work
18576 THUMB_SET_FUNC (sym
, 1);
18578 label_is_thumb_function_name
= FALSE
;
18581 dwarf2_emit_label (sym
);
18585 arm_data_in_code (void)
18587 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18589 *input_line_pointer
= '/';
18590 input_line_pointer
+= 5;
18591 *input_line_pointer
= 0;
18599 arm_canonicalize_symbol_name (char * name
)
18603 if (thumb_mode
&& (len
= strlen (name
)) > 5
18604 && streq (name
+ len
- 5, "/data"))
18605 *(name
+ len
- 5) = 0;
18610 /* Table of all register names defined by default. The user can
18611 define additional names with .req. Note that all register names
18612 should appear in both upper and lowercase variants. Some registers
18613 also have mixed-case names. */
18615 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18616 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18617 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18618 #define REGSET(p,t) \
18619 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18620 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18621 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18622 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18623 #define REGSETH(p,t) \
18624 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18625 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18626 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18627 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18628 #define REGSET2(p,t) \
18629 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18630 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18631 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18632 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18633 #define SPLRBANK(base,bank,t) \
18634 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18635 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18636 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18637 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18638 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18639 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18641 static const struct reg_entry reg_names
[] =
18643 /* ARM integer registers. */
18644 REGSET(r
, RN
), REGSET(R
, RN
),
18646 /* ATPCS synonyms. */
18647 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18648 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18649 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18651 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18652 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18653 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18655 /* Well-known aliases. */
18656 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18657 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18659 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18660 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18662 /* Coprocessor numbers. */
18663 REGSET(p
, CP
), REGSET(P
, CP
),
18665 /* Coprocessor register numbers. The "cr" variants are for backward
18667 REGSET(c
, CN
), REGSET(C
, CN
),
18668 REGSET(cr
, CN
), REGSET(CR
, CN
),
18670 /* ARM banked registers. */
18671 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18672 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18673 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18674 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18675 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18676 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18677 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18679 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18680 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18681 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18682 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18683 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18684 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18685 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18686 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18688 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18689 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18690 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18691 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18692 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18693 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18694 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18695 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18696 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18698 /* FPA registers. */
18699 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18700 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18702 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18703 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18705 /* VFP SP registers. */
18706 REGSET(s
,VFS
), REGSET(S
,VFS
),
18707 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18709 /* VFP DP Registers. */
18710 REGSET(d
,VFD
), REGSET(D
,VFD
),
18711 /* Extra Neon DP registers. */
18712 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18714 /* Neon QP registers. */
18715 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18717 /* VFP control registers. */
18718 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18719 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18720 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18721 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18722 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18723 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18725 /* Maverick DSP coprocessor registers. */
18726 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18727 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18729 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18730 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18731 REGDEF(dspsc
,0,DSPSC
),
18733 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18734 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18735 REGDEF(DSPSC
,0,DSPSC
),
18737 /* iWMMXt data registers - p0, c0-15. */
18738 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18740 /* iWMMXt control registers - p1, c0-3. */
18741 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18742 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18743 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18744 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18746 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18747 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18748 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18749 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18750 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18752 /* XScale accumulator registers. */
18753 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18759 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18760 within psr_required_here. */
18761 static const struct asm_psr psrs
[] =
18763 /* Backward compatibility notation. Note that "all" is no longer
18764 truly all possible PSR bits. */
18765 {"all", PSR_c
| PSR_f
},
18769 /* Individual flags. */
18775 /* Combinations of flags. */
18776 {"fs", PSR_f
| PSR_s
},
18777 {"fx", PSR_f
| PSR_x
},
18778 {"fc", PSR_f
| PSR_c
},
18779 {"sf", PSR_s
| PSR_f
},
18780 {"sx", PSR_s
| PSR_x
},
18781 {"sc", PSR_s
| PSR_c
},
18782 {"xf", PSR_x
| PSR_f
},
18783 {"xs", PSR_x
| PSR_s
},
18784 {"xc", PSR_x
| PSR_c
},
18785 {"cf", PSR_c
| PSR_f
},
18786 {"cs", PSR_c
| PSR_s
},
18787 {"cx", PSR_c
| PSR_x
},
18788 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18789 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18790 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18791 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18792 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18793 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18794 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18795 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18796 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18797 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18798 {"scf", PSR_s
| PSR_c
| PSR_f
},
18799 {"scx", PSR_s
| PSR_c
| PSR_x
},
18800 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18801 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18802 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18803 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18804 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18805 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18806 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18807 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18808 {"csf", PSR_c
| PSR_s
| PSR_f
},
18809 {"csx", PSR_c
| PSR_s
| PSR_x
},
18810 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18811 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18812 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18813 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18814 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18815 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18816 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18817 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18818 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18819 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18820 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18821 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18822 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18823 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18824 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18825 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18826 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18827 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18828 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18829 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18830 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18831 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18832 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18833 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18834 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18835 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18838 /* Table of V7M psr names. */
18839 static const struct asm_psr v7m_psrs
[] =
18841 {"apsr", 0x0 }, {"APSR", 0x0 },
18842 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
18843 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
18844 {"psr", 0x3 }, {"PSR", 0x3 },
18845 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
18846 {"ipsr", 0x5 }, {"IPSR", 0x5 },
18847 {"epsr", 0x6 }, {"EPSR", 0x6 },
18848 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
18849 {"msp", 0x8 }, {"MSP", 0x8 },
18850 {"psp", 0x9 }, {"PSP", 0x9 },
18851 {"msplim", 0xa }, {"MSPLIM", 0xa },
18852 {"psplim", 0xb }, {"PSPLIM", 0xb },
18853 {"primask", 0x10}, {"PRIMASK", 0x10},
18854 {"basepri", 0x11}, {"BASEPRI", 0x11},
18855 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
18856 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
18857 {"control", 0x14}, {"CONTROL", 0x14},
18858 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
18859 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
18860 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
18861 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
18862 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
18863 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
18864 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
18865 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
18866 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
18869 /* Table of all shift-in-operand names. */
18870 static const struct asm_shift_name shift_names
[] =
18872 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18873 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18874 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18875 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18876 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18877 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18880 /* Table of all explicit relocation names. */
18882 static struct reloc_entry reloc_names
[] =
18884 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18885 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18886 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18887 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18888 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18889 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18890 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18891 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18892 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18893 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18894 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18895 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18896 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18897 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18898 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18899 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18900 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18901 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18905 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18906 static const struct asm_cond conds
[] =
18910 {"cs", 0x2}, {"hs", 0x2},
18911 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18925 #define UL_BARRIER(L,U,CODE,FEAT) \
18926 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18927 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18929 static struct asm_barrier_opt barrier_opt_names
[] =
18931 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18932 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18933 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18934 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18935 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18936 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18937 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18938 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18939 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18940 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18941 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18942 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18943 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18944 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18945 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18946 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18951 /* Table of ARM-format instructions. */
18953 /* Macros for gluing together operand strings. N.B. In all cases
18954 other than OPS0, the trailing OP_stop comes from default
18955 zero-initialization of the unspecified elements of the array. */
18956 #define OPS0() { OP_stop, }
18957 #define OPS1(a) { OP_##a, }
18958 #define OPS2(a,b) { OP_##a,OP_##b, }
18959 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18960 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18961 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18962 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18964 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18965 This is useful when mixing operands for ARM and THUMB, i.e. using the
18966 MIX_ARM_THUMB_OPERANDS macro.
18967 In order to use these macros, prefix the number of operands with _
18969 #define OPS_1(a) { a, }
18970 #define OPS_2(a,b) { a,b, }
18971 #define OPS_3(a,b,c) { a,b,c, }
18972 #define OPS_4(a,b,c,d) { a,b,c,d, }
18973 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18974 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18976 /* These macros abstract out the exact format of the mnemonic table and
18977 save some repeated characters. */
18979 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18980 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18981 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18982 THUMB_VARIANT, do_##ae, do_##te }
18984 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18985 a T_MNEM_xyz enumerator. */
18986 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18987 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18988 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18989 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18991 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18992 infix after the third character. */
18993 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18994 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18995 THUMB_VARIANT, do_##ae, do_##te }
18996 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18997 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18998 THUMB_VARIANT, do_##ae, do_##te }
18999 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19000 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19001 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19002 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19003 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19004 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19005 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19006 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19008 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19009 field is still 0xE. Many of the Thumb variants can be executed
19010 conditionally, so this is checked separately. */
19011 #define TUE(mnem, op, top, nops, ops, ae, te) \
19012 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19013 THUMB_VARIANT, do_##ae, do_##te }
19015 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19016 Used by mnemonics that have very minimal differences in the encoding for
19017 ARM and Thumb variants and can be handled in a common function. */
19018 #define TUEc(mnem, op, top, nops, ops, en) \
19019 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19020 THUMB_VARIANT, do_##en, do_##en }
19022 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19023 condition code field. */
19024 #define TUF(mnem, op, top, nops, ops, ae, te) \
19025 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19026 THUMB_VARIANT, do_##ae, do_##te }
19028 /* ARM-only variants of all the above. */
19029 #define CE(mnem, op, nops, ops, ae) \
19030 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19032 #define C3(mnem, op, nops, ops, ae) \
19033 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19035 /* Legacy mnemonics that always have conditional infix after the third
19037 #define CL(mnem, op, nops, ops, ae) \
19038 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19039 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19041 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19042 #define cCE(mnem, op, nops, ops, ae) \
19043 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19045 /* Legacy coprocessor instructions where conditional infix and conditional
19046 suffix are ambiguous. For consistency this includes all FPA instructions,
19047 not just the potentially ambiguous ones. */
19048 #define cCL(mnem, op, nops, ops, ae) \
19049 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19050 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19052 /* Coprocessor, takes either a suffix or a position-3 infix
19053 (for an FPA corner case). */
19054 #define C3E(mnem, op, nops, ops, ae) \
19055 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19056 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19058 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19059 { m1 #m2 m3, OPS##nops ops, \
19060 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19061 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19063 #define CM(m1, m2, op, nops, ops, ae) \
19064 xCM_ (m1, , m2, op, nops, ops, ae), \
19065 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19066 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19067 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19068 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19069 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19070 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19071 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19072 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19073 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19074 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19075 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19076 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19077 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19078 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19079 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19080 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19081 xCM_ (m1, le, m2, op, nops, ops, ae), \
19082 xCM_ (m1, al, m2, op, nops, ops, ae)
19084 #define UE(mnem, op, nops, ops, ae) \
19085 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19087 #define UF(mnem, op, nops, ops, ae) \
19088 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19090 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19091 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19092 use the same encoding function for each. */
19093 #define NUF(mnem, op, nops, ops, enc) \
19094 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19095 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19097 /* Neon data processing, version which indirects through neon_enc_tab for
19098 the various overloaded versions of opcodes. */
19099 #define nUF(mnem, op, nops, ops, enc) \
19100 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19101 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19103 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19105 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19106 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19107 THUMB_VARIANT, do_##enc, do_##enc }
19109 #define NCE(mnem, op, nops, ops, enc) \
19110 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19112 #define NCEF(mnem, op, nops, ops, enc) \
19113 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19115 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19116 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19117 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19118 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19120 #define nCE(mnem, op, nops, ops, enc) \
19121 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19123 #define nCEF(mnem, op, nops, ops, enc) \
19124 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19128 static const struct asm_opcode insns
[] =
19130 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19131 #define THUMB_VARIANT & arm_ext_v4t
19132 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19133 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19134 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19135 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19136 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19137 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19138 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19139 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19140 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19141 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19142 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19143 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19144 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19145 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19146 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19147 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19149 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19150 for setting PSR flag bits. They are obsolete in V6 and do not
19151 have Thumb equivalents. */
19152 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19153 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19154 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19155 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19156 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19157 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19158 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19159 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19160 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19162 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19163 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19164 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19165 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19167 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19168 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19169 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19171 OP_ADDRGLDR
),ldst
, t_ldst
),
19172 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19174 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19175 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19176 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19177 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19178 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19179 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19181 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19182 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19183 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19184 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19187 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19188 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19189 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19190 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19192 /* Thumb-compatibility pseudo ops. */
19193 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19194 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19195 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19196 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19197 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19198 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19199 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19200 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19201 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19202 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19203 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19204 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19206 /* These may simplify to neg. */
19207 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19208 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19210 #undef THUMB_VARIANT
19211 #define THUMB_VARIANT & arm_ext_v6
19213 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19215 /* V1 instructions with no Thumb analogue prior to V6T2. */
19216 #undef THUMB_VARIANT
19217 #define THUMB_VARIANT & arm_ext_v6t2
19219 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19220 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19221 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19223 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19224 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19225 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19226 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19228 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19229 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19231 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19232 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19234 /* V1 instructions with no Thumb analogue at all. */
19235 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19236 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19238 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19239 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19240 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19241 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19242 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19243 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19244 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19245 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19248 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19249 #undef THUMB_VARIANT
19250 #define THUMB_VARIANT & arm_ext_v4t
19252 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19253 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19255 #undef THUMB_VARIANT
19256 #define THUMB_VARIANT & arm_ext_v6t2
19258 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19259 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19261 /* Generic coprocessor instructions. */
19262 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19263 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19264 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19265 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19266 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19267 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19268 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19271 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19273 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19274 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19277 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19278 #undef THUMB_VARIANT
19279 #define THUMB_VARIANT & arm_ext_msr
19281 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19282 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19285 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19286 #undef THUMB_VARIANT
19287 #define THUMB_VARIANT & arm_ext_v6t2
19289 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19290 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19291 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19292 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19293 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19294 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19295 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19296 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19299 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19300 #undef THUMB_VARIANT
19301 #define THUMB_VARIANT & arm_ext_v4t
19303 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19304 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19305 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19306 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19307 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19308 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19311 #define ARM_VARIANT & arm_ext_v4t_5
19313 /* ARM Architecture 4T. */
19314 /* Note: bx (and blx) are required on V5, even if the processor does
19315 not support Thumb. */
19316 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19319 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19320 #undef THUMB_VARIANT
19321 #define THUMB_VARIANT & arm_ext_v5t
19323 /* Note: blx has 2 variants; the .value coded here is for
19324 BLX(2). Only this variant has conditional execution. */
19325 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19326 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19328 #undef THUMB_VARIANT
19329 #define THUMB_VARIANT & arm_ext_v6t2
19331 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19332 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19333 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19334 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19335 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19336 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19337 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19338 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19341 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19342 #undef THUMB_VARIANT
19343 #define THUMB_VARIANT & arm_ext_v5exp
19345 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19346 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19347 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19348 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19350 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19351 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19353 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19354 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19355 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19356 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19358 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19359 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19360 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19361 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19363 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19364 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19366 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19367 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19368 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19369 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19372 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19373 #undef THUMB_VARIANT
19374 #define THUMB_VARIANT & arm_ext_v6t2
19376 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19377 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19379 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19380 ADDRGLDRS
), ldrd
, t_ldstd
),
19382 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19383 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19386 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19388 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19391 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19392 #undef THUMB_VARIANT
19393 #define THUMB_VARIANT & arm_ext_v6
19395 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19396 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19397 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19398 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19399 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19400 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19401 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19402 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19403 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19404 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19406 #undef THUMB_VARIANT
19407 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19409 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19410 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19412 #undef THUMB_VARIANT
19413 #define THUMB_VARIANT & arm_ext_v6t2
19415 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19416 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19418 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19419 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19421 /* ARM V6 not included in V7M. */
19422 #undef THUMB_VARIANT
19423 #define THUMB_VARIANT & arm_ext_v6_notm
19424 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19425 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19426 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19427 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19428 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19429 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19430 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19431 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19432 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19433 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19434 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19435 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19436 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19437 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19438 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19439 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19440 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19441 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19442 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19444 /* ARM V6 not included in V7M (eg. integer SIMD). */
19445 #undef THUMB_VARIANT
19446 #define THUMB_VARIANT & arm_ext_v6_dsp
19447 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19448 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19449 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19450 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19451 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19452 /* Old name for QASX. */
19453 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19454 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19455 /* Old name for QSAX. */
19456 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19457 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19458 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19459 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19460 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19461 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19462 /* Old name for SASX. */
19463 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19464 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19465 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19466 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19467 /* Old name for SHASX. */
19468 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19469 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19470 /* Old name for SHSAX. */
19471 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19472 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19473 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19474 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19475 /* Old name for SSAX. */
19476 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19477 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19478 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19479 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19480 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19481 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19482 /* Old name for UASX. */
19483 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19484 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19485 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19486 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19487 /* Old name for UHASX. */
19488 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19489 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19490 /* Old name for UHSAX. */
19491 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19492 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19493 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19494 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19495 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19496 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19497 /* Old name for UQASX. */
19498 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19499 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19500 /* Old name for UQSAX. */
19501 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19502 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19503 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19504 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19505 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19506 /* Old name for USAX. */
19507 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19508 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19509 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19510 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19511 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19512 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19513 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19514 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19515 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19516 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19517 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19518 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19519 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19520 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19521 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19522 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19523 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19524 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19525 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19526 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19527 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19528 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19529 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19530 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19531 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19532 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19533 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19534 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19535 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19536 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19537 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19538 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19539 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19540 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19543 #define ARM_VARIANT & arm_ext_v6k
19544 #undef THUMB_VARIANT
19545 #define THUMB_VARIANT & arm_ext_v6k
19547 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19548 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19549 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19550 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19552 #undef THUMB_VARIANT
19553 #define THUMB_VARIANT & arm_ext_v6_notm
19554 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19556 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19557 RRnpcb
), strexd
, t_strexd
),
19559 #undef THUMB_VARIANT
19560 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19561 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19563 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19565 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19567 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19569 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19572 #define ARM_VARIANT & arm_ext_sec
19573 #undef THUMB_VARIANT
19574 #define THUMB_VARIANT & arm_ext_sec
19576 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19579 #define ARM_VARIANT & arm_ext_virt
19580 #undef THUMB_VARIANT
19581 #define THUMB_VARIANT & arm_ext_virt
19583 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19584 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19587 #define ARM_VARIANT & arm_ext_pan
19588 #undef THUMB_VARIANT
19589 #define THUMB_VARIANT & arm_ext_pan
19591 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19594 #define ARM_VARIANT & arm_ext_v6t2
19595 #undef THUMB_VARIANT
19596 #define THUMB_VARIANT & arm_ext_v6t2
19598 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19599 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19600 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19601 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19603 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19604 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19606 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19607 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19608 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19609 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19611 #undef THUMB_VARIANT
19612 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19613 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19614 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19616 /* Thumb-only instructions. */
19618 #define ARM_VARIANT NULL
19619 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19620 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19622 /* ARM does not really have an IT instruction, so always allow it.
19623 The opcode is copied from Thumb in order to allow warnings in
19624 -mimplicit-it=[never | arm] modes. */
19626 #define ARM_VARIANT & arm_ext_v1
19627 #undef THUMB_VARIANT
19628 #define THUMB_VARIANT & arm_ext_v6t2
19630 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19631 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19632 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19633 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19634 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19635 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19636 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19637 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19638 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19639 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19640 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19641 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19642 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19643 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19644 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19645 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19646 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19647 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19649 /* Thumb2 only instructions. */
19651 #define ARM_VARIANT NULL
19653 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19654 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19655 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19656 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19657 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19658 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19660 /* Hardware division instructions. */
19662 #define ARM_VARIANT & arm_ext_adiv
19663 #undef THUMB_VARIANT
19664 #define THUMB_VARIANT & arm_ext_div
19666 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19667 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19669 /* ARM V6M/V7 instructions. */
19671 #define ARM_VARIANT & arm_ext_barrier
19672 #undef THUMB_VARIANT
19673 #define THUMB_VARIANT & arm_ext_barrier
19675 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19676 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19677 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19679 /* ARM V7 instructions. */
19681 #define ARM_VARIANT & arm_ext_v7
19682 #undef THUMB_VARIANT
19683 #define THUMB_VARIANT & arm_ext_v7
19685 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19686 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19689 #define ARM_VARIANT & arm_ext_mp
19690 #undef THUMB_VARIANT
19691 #define THUMB_VARIANT & arm_ext_mp
19693 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19695 /* AArchv8 instructions. */
19697 #define ARM_VARIANT & arm_ext_v8
19699 /* Instructions shared between armv8-a and armv8-m. */
19700 #undef THUMB_VARIANT
19701 #define THUMB_VARIANT & arm_ext_atomics
19703 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19704 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19705 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19706 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19707 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19708 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19709 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19710 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19711 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19712 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19714 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19716 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19718 #undef THUMB_VARIANT
19719 #define THUMB_VARIANT & arm_ext_v8
19721 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19722 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19723 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19725 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19727 /* ARMv8 T32 only. */
19729 #define ARM_VARIANT NULL
19730 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19731 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19732 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19734 /* FP for ARMv8. */
19736 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19737 #undef THUMB_VARIANT
19738 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19740 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19741 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19742 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19743 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19744 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19745 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19746 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19747 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19748 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19749 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19750 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19751 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19752 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19753 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19754 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19755 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19756 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19758 /* Crypto v1 extensions. */
19760 #define ARM_VARIANT & fpu_crypto_ext_armv8
19761 #undef THUMB_VARIANT
19762 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19764 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19765 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19766 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19767 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19768 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19769 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19770 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19771 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19772 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19773 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19774 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19775 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19776 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19777 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19780 #define ARM_VARIANT & crc_ext_armv8
19781 #undef THUMB_VARIANT
19782 #define THUMB_VARIANT & crc_ext_armv8
19783 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19784 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19785 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19786 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19787 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19788 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19790 /* ARMv8.2 RAS extension. */
19792 #define ARM_VARIANT & arm_ext_ras
19793 #undef THUMB_VARIANT
19794 #define THUMB_VARIANT & arm_ext_ras
19795 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19798 #define ARM_VARIANT & arm_ext_v8_3
19799 #undef THUMB_VARIANT
19800 #define THUMB_VARIANT & arm_ext_v8_3
19801 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
19804 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19805 #undef THUMB_VARIANT
19806 #define THUMB_VARIANT NULL
19808 cCE("wfs", e200110
, 1, (RR
), rd
),
19809 cCE("rfs", e300110
, 1, (RR
), rd
),
19810 cCE("wfc", e400110
, 1, (RR
), rd
),
19811 cCE("rfc", e500110
, 1, (RR
), rd
),
19813 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19814 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19815 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19816 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19818 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19819 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19820 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19821 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19823 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19824 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19825 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19826 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19827 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19828 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19829 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19830 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19831 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19832 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19833 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19834 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19836 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19837 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19838 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19839 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19840 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19841 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19842 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19843 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19844 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19845 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19846 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19847 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19849 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19850 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19851 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19852 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19853 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19854 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19855 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19856 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19857 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19858 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19859 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19860 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19862 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19863 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19864 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19865 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19866 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19867 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19868 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19869 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19870 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19871 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19872 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19873 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19875 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19876 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19877 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19878 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19879 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19880 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19881 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19882 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19883 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19884 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19885 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19886 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19888 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19889 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19890 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19891 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19892 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19893 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19894 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19895 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19896 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19897 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19898 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19899 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19901 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19902 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19903 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19904 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19905 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19906 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19907 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19908 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19909 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19910 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19911 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19912 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19914 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19915 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19916 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19917 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19918 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19919 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19920 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19921 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19922 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19923 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19924 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19925 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19927 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19928 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19929 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19930 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19931 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19932 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19933 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19934 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19935 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19936 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19937 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19938 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19940 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19941 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19942 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19943 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19944 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19945 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19946 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19947 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19948 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19949 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19950 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19951 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19953 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19954 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19955 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19956 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19957 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19958 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19959 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19960 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19961 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19962 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19963 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19964 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19966 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19967 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19968 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19969 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19970 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19971 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19972 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19973 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19974 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19975 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19976 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19977 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19979 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19980 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19981 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19982 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19983 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19984 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19985 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19986 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19987 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19988 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19989 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19990 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19992 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19993 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19994 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19995 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19996 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19997 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19998 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19999 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20000 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20001 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20002 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20003 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20005 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20006 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20007 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20008 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20009 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20010 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20011 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20012 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20013 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20014 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20015 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20016 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20018 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20019 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20020 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20021 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20022 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20023 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20024 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20025 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20026 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20027 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20028 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20029 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20031 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20032 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20033 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20034 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20035 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20036 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20037 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20038 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20039 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20040 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20041 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20042 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20044 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20045 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20046 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20047 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20048 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20049 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20050 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20051 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20052 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20053 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20054 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20055 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20057 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20058 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20059 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20060 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20061 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20062 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20063 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20064 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20065 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20066 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20067 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20068 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20070 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20071 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20072 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20073 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20074 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20075 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20076 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20077 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20078 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20079 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20080 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20081 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20083 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20084 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20085 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20086 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20087 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20088 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20089 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20090 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20091 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20092 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20093 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20094 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20096 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20097 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20098 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20099 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20100 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20101 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20102 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20103 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20104 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20105 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20106 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20107 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20109 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20110 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20111 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20112 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20113 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20114 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20115 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20116 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20117 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20118 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20119 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20120 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20122 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20123 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20124 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20125 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20126 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20127 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20128 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20129 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20130 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20131 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20132 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20133 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20135 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20136 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20137 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20138 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20139 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20140 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20141 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20142 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20143 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20144 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20145 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20146 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20148 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20149 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20150 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20151 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20152 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20153 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20154 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20155 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20156 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20157 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20158 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20159 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20161 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20162 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20163 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20164 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20165 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20166 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20167 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20168 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20169 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20170 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20171 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20172 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20174 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20175 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20176 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20177 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20178 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20179 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20180 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20181 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20182 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20183 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20184 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20185 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20187 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20188 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20189 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20190 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20191 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20192 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20193 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20194 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20195 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20196 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20197 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20198 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20200 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20201 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20202 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20203 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20205 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20206 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20207 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20208 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20209 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20210 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20211 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20212 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20213 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20214 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20215 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20216 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20218 /* The implementation of the FIX instruction is broken on some
20219 assemblers, in that it accepts a precision specifier as well as a
20220 rounding specifier, despite the fact that this is meaningless.
20221 To be more compatible, we accept it as well, though of course it
20222 does not set any bits. */
20223 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20224 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20225 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20226 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20227 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20228 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20229 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20230 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20231 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20232 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20233 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20234 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20235 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20237 /* Instructions that were new with the real FPA, call them V2. */
20239 #define ARM_VARIANT & fpu_fpa_ext_v2
20241 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20242 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20243 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20244 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20245 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20246 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20249 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20251 /* Moves and type conversions. */
20252 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20253 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20254 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20255 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20256 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20257 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20258 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20259 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20260 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20261 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20262 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20263 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20264 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20265 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20267 /* Memory operations. */
20268 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20269 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20270 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20271 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20272 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20273 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20274 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20275 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20276 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20277 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20278 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20279 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20280 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20281 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20282 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20283 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20284 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20285 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20287 /* Monadic operations. */
20288 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20289 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20290 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20292 /* Dyadic operations. */
20293 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20294 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20295 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20296 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20297 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20298 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20299 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20300 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20301 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20304 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20305 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20306 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20307 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20309 /* Double precision load/store are still present on single precision
20310 implementations. */
20311 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20312 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20313 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20314 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20315 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20316 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20317 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20318 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20319 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20320 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20323 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20325 /* Moves and type conversions. */
20326 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20327 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20328 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20329 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20330 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20331 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20332 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20333 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20334 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20335 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20336 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20337 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20338 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20340 /* Monadic operations. */
20341 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20342 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20343 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20345 /* Dyadic operations. */
20346 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20347 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20348 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20349 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20350 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20351 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20352 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20353 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20354 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20357 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20358 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20359 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20360 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20363 #define ARM_VARIANT & fpu_vfp_ext_v2
20365 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20366 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20367 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20368 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20370 /* Instructions which may belong to either the Neon or VFP instruction sets.
20371 Individual encoder functions perform additional architecture checks. */
20373 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20374 #undef THUMB_VARIANT
20375 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20377 /* These mnemonics are unique to VFP. */
20378 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20379 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20380 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20381 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20382 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20383 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20384 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20385 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20386 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20387 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20389 /* Mnemonics shared by Neon and VFP. */
20390 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20391 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20392 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20394 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20395 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20397 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20398 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20400 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20401 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20402 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20403 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20404 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20405 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20406 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20407 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20409 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20410 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20411 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20412 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20415 /* NOTE: All VMOV encoding is special-cased! */
20416 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20417 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20420 #define ARM_VARIANT & arm_ext_fp16
20421 #undef THUMB_VARIANT
20422 #define THUMB_VARIANT & arm_ext_fp16
20423 /* New instructions added from v8.2, allowing the extraction and insertion of
20424 the upper 16 bits of a 32-bit vector register. */
20425 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20426 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20428 #undef THUMB_VARIANT
20429 #define THUMB_VARIANT & fpu_neon_ext_v1
20431 #define ARM_VARIANT & fpu_neon_ext_v1
20433 /* Data processing with three registers of the same length. */
20434 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20435 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20436 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20437 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20438 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20439 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20440 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20441 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20442 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20443 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20444 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20445 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20446 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20447 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20448 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20449 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20450 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20451 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20452 /* If not immediate, fall back to neon_dyadic_i64_su.
20453 shl_imm should accept I8 I16 I32 I64,
20454 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20455 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20456 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20457 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20458 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20459 /* Logic ops, types optional & ignored. */
20460 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20461 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20462 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20463 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20464 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20465 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20466 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20467 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20468 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20469 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20470 /* Bitfield ops, untyped. */
20471 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20472 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20473 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20474 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20475 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20476 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20477 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20478 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20479 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20480 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20481 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20482 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20483 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20484 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20485 back to neon_dyadic_if_su. */
20486 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20487 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20488 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20489 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20490 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20491 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20492 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20493 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20494 /* Comparison. Type I8 I16 I32 F32. */
20495 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20496 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20497 /* As above, D registers only. */
20498 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20499 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20500 /* Int and float variants, signedness unimportant. */
20501 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20502 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20503 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20504 /* Add/sub take types I8 I16 I32 I64 F32. */
20505 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20506 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20507 /* vtst takes sizes 8, 16, 32. */
20508 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20509 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20510 /* VMUL takes I8 I16 I32 F32 P8. */
20511 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20512 /* VQD{R}MULH takes S16 S32. */
20513 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20514 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20515 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20516 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20517 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20518 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20519 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20520 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20521 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20522 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20523 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20524 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20525 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20526 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20527 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20528 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20529 /* ARM v8.1 extension. */
20530 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20531 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20532 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20533 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20535 /* Two address, int/float. Types S8 S16 S32 F32. */
20536 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20537 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20539 /* Data processing with two registers and a shift amount. */
20540 /* Right shifts, and variants with rounding.
20541 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20542 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20543 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20544 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20545 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20546 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20547 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20548 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20549 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20550 /* Shift and insert. Sizes accepted 8 16 32 64. */
20551 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20552 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20553 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20554 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20555 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20556 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20557 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20558 /* Right shift immediate, saturating & narrowing, with rounding variants.
20559 Types accepted S16 S32 S64 U16 U32 U64. */
20560 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20561 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20562 /* As above, unsigned. Types accepted S16 S32 S64. */
20563 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20564 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20565 /* Right shift narrowing. Types accepted I16 I32 I64. */
20566 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20567 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20568 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20569 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20570 /* CVT with optional immediate for fixed-point variant. */
20571 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20573 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20574 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20576 /* Data processing, three registers of different lengths. */
20577 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20578 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20579 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20580 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20581 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20582 /* If not scalar, fall back to neon_dyadic_long.
20583 Vector types as above, scalar types S16 S32 U16 U32. */
20584 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20585 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20586 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20587 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20588 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20589 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20590 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20591 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20592 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20593 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20594 /* Saturating doubling multiplies. Types S16 S32. */
20595 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20596 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20597 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20598 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20599 S16 S32 U16 U32. */
20600 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20602 /* Extract. Size 8. */
20603 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20604 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20606 /* Two registers, miscellaneous. */
20607 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20608 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20609 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20610 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20611 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20612 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20613 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20614 /* Vector replicate. Sizes 8 16 32. */
20615 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20616 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20617 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20618 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20619 /* VMOVN. Types I16 I32 I64. */
20620 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20621 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20622 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20623 /* VQMOVUN. Types S16 S32 S64. */
20624 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20625 /* VZIP / VUZP. Sizes 8 16 32. */
20626 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20627 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20628 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20629 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20630 /* VQABS / VQNEG. Types S8 S16 S32. */
20631 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20632 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20633 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20634 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20635 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20636 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20637 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20638 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20639 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20640 /* Reciprocal estimates. Types U32 F16 F32. */
20641 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20642 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20643 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20644 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20645 /* VCLS. Types S8 S16 S32. */
20646 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20647 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20648 /* VCLZ. Types I8 I16 I32. */
20649 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20650 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20651 /* VCNT. Size 8. */
20652 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20653 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20654 /* Two address, untyped. */
20655 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20656 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20657 /* VTRN. Sizes 8 16 32. */
20658 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20659 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20661 /* Table lookup. Size 8. */
20662 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20663 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20665 #undef THUMB_VARIANT
20666 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20668 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20670 /* Neon element/structure load/store. */
20671 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20672 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20673 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20674 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20675 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20676 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20677 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20678 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20680 #undef THUMB_VARIANT
20681 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20683 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20684 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20685 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20686 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20687 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20688 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20689 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20690 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20691 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20692 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20694 #undef THUMB_VARIANT
20695 #define THUMB_VARIANT & fpu_vfp_ext_v3
20697 #define ARM_VARIANT & fpu_vfp_ext_v3
20699 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20700 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20701 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20702 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20703 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20704 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20705 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20706 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20707 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20710 #define ARM_VARIANT & fpu_vfp_ext_fma
20711 #undef THUMB_VARIANT
20712 #define THUMB_VARIANT & fpu_vfp_ext_fma
20713 /* Mnemonics shared by Neon and VFP. These are included in the
20714 VFP FMA variant; NEON and VFP FMA always includes the NEON
20715 FMA instructions. */
20716 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20717 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20718 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20719 the v form should always be used. */
20720 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20721 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20722 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20723 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20724 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20725 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20727 #undef THUMB_VARIANT
20729 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20731 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20732 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20733 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20734 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20735 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20736 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20737 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20738 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20741 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20743 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20744 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20745 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20746 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20747 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20748 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20749 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20750 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20751 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20752 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20753 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20754 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20755 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20756 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20757 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20758 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20759 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20760 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20761 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20762 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20763 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20764 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20765 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20766 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20767 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20768 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20769 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20770 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20771 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20772 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20773 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20774 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20775 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20776 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20777 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20778 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20779 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20780 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20781 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20782 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20783 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20784 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20785 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20786 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20787 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20788 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20789 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20790 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20791 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20792 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20793 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20794 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20795 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20796 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20797 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20798 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20799 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20800 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20801 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20802 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20803 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20804 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20805 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20806 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20807 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20808 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20809 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20810 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20811 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20812 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20813 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20814 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20815 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20816 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20817 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20818 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20819 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20820 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20821 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20822 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20823 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20824 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20825 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20826 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20827 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20828 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20829 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20830 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20831 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20832 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20833 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20834 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20835 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20836 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20837 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20838 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20839 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20840 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20841 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20842 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20843 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20844 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20845 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20846 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20847 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20848 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20849 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20850 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20851 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20852 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20853 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20854 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20855 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20856 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20857 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20858 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20859 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20860 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20861 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20862 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20863 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20864 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20865 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20866 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20867 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20868 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20869 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20870 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20871 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20872 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20873 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20874 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20875 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20876 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20877 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20878 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20879 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20880 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20881 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20882 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20883 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20884 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20885 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20886 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20887 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20888 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20889 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20890 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20891 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20892 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20893 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20894 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20895 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20896 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20897 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20898 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20899 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20900 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20901 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20902 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20903 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20904 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20907 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20909 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20910 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20911 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20912 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20913 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20914 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20915 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20916 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20917 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20918 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20919 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20920 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20921 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20922 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20923 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20924 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20925 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20926 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20927 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20928 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20929 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20930 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20931 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20932 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20933 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20934 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20935 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20936 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20937 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20938 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20939 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20940 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20941 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20942 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20943 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20944 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20945 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20946 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20947 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20948 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20949 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20950 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20951 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20952 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20953 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20954 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20955 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20956 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20957 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20958 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20959 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20960 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20961 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20962 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20963 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20964 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20965 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20968 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20970 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20971 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20972 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20973 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20974 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20975 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20976 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20977 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20978 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20979 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20980 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20981 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20982 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20983 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20984 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20985 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20986 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20987 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20988 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20989 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20990 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20991 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20992 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20993 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20994 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20995 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20996 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20997 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20998 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20999 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21000 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21001 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21002 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21003 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21004 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21005 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21006 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21007 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21008 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21009 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21010 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21011 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21012 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21013 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21014 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21015 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21016 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21017 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21018 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21019 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21020 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21021 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21022 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21023 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21024 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21025 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21026 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21027 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21028 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21029 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21030 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21031 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21032 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21033 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21034 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21035 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21036 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21037 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21038 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21039 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21040 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21041 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21042 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21043 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21044 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21045 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21047 /* ARMv8-M instructions. */
21049 #define ARM_VARIANT NULL
21050 #undef THUMB_VARIANT
21051 #define THUMB_VARIANT & arm_ext_v8m
21052 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21053 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21054 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21055 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21056 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21057 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21058 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21060 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21061 instructions behave as nop if no VFP is present. */
21062 #undef THUMB_VARIANT
21063 #define THUMB_VARIANT & arm_ext_v8m_main
21064 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21065 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21068 #undef THUMB_VARIANT
21094 /* MD interface: bits in the object file. */
21096 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21097 for use in the a.out file, and stores them in the array pointed to by buf.
21098 This knows about the endian-ness of the target machine and does
21099 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21100 2 (short) and 4 (long) Floating numbers are put out as a series of
21101 LITTLENUMS (shorts, here at least). */
21104 md_number_to_chars (char * buf
, valueT val
, int n
)
21106 if (target_big_endian
)
21107 number_to_chars_bigendian (buf
, val
, n
);
21109 number_to_chars_littleendian (buf
, val
, n
);
21113 md_chars_to_number (char * buf
, int n
)
21116 unsigned char * where
= (unsigned char *) buf
;
21118 if (target_big_endian
)
21123 result
|= (*where
++ & 255);
21131 result
|= (where
[n
] & 255);
21138 /* MD interface: Sections. */
21140 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21141 that an rs_machine_dependent frag may reach. */
21144 arm_frag_max_var (fragS
*fragp
)
21146 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21147 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21149 Note that we generate relaxable instructions even for cases that don't
21150 really need it, like an immediate that's a trivial constant. So we're
21151 overestimating the instruction size for some of those cases. Rather
21152 than putting more intelligence here, it would probably be better to
21153 avoid generating a relaxation frag in the first place when it can be
21154 determined up front that a short instruction will suffice. */
21156 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21160 /* Estimate the size of a frag before relaxing. Assume everything fits in
21164 md_estimate_size_before_relax (fragS
* fragp
,
21165 segT segtype ATTRIBUTE_UNUSED
)
21171 /* Convert a machine dependent frag. */
21174 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21176 unsigned long insn
;
21177 unsigned long old_op
;
21185 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21187 old_op
= bfd_get_16(abfd
, buf
);
21188 if (fragp
->fr_symbol
)
21190 exp
.X_op
= O_symbol
;
21191 exp
.X_add_symbol
= fragp
->fr_symbol
;
21195 exp
.X_op
= O_constant
;
21197 exp
.X_add_number
= fragp
->fr_offset
;
21198 opcode
= fragp
->fr_subtype
;
21201 case T_MNEM_ldr_pc
:
21202 case T_MNEM_ldr_pc2
:
21203 case T_MNEM_ldr_sp
:
21204 case T_MNEM_str_sp
:
21211 if (fragp
->fr_var
== 4)
21213 insn
= THUMB_OP32 (opcode
);
21214 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21216 insn
|= (old_op
& 0x700) << 4;
21220 insn
|= (old_op
& 7) << 12;
21221 insn
|= (old_op
& 0x38) << 13;
21223 insn
|= 0x00000c00;
21224 put_thumb32_insn (buf
, insn
);
21225 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21229 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21231 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21234 if (fragp
->fr_var
== 4)
21236 insn
= THUMB_OP32 (opcode
);
21237 insn
|= (old_op
& 0xf0) << 4;
21238 put_thumb32_insn (buf
, insn
);
21239 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21243 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21244 exp
.X_add_number
-= 4;
21252 if (fragp
->fr_var
== 4)
21254 int r0off
= (opcode
== T_MNEM_mov
21255 || opcode
== T_MNEM_movs
) ? 0 : 8;
21256 insn
= THUMB_OP32 (opcode
);
21257 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21258 insn
|= (old_op
& 0x700) << r0off
;
21259 put_thumb32_insn (buf
, insn
);
21260 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21264 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21269 if (fragp
->fr_var
== 4)
21271 insn
= THUMB_OP32(opcode
);
21272 put_thumb32_insn (buf
, insn
);
21273 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21276 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21280 if (fragp
->fr_var
== 4)
21282 insn
= THUMB_OP32(opcode
);
21283 insn
|= (old_op
& 0xf00) << 14;
21284 put_thumb32_insn (buf
, insn
);
21285 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21288 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21291 case T_MNEM_add_sp
:
21292 case T_MNEM_add_pc
:
21293 case T_MNEM_inc_sp
:
21294 case T_MNEM_dec_sp
:
21295 if (fragp
->fr_var
== 4)
21297 /* ??? Choose between add and addw. */
21298 insn
= THUMB_OP32 (opcode
);
21299 insn
|= (old_op
& 0xf0) << 4;
21300 put_thumb32_insn (buf
, insn
);
21301 if (opcode
== T_MNEM_add_pc
)
21302 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21304 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21307 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21315 if (fragp
->fr_var
== 4)
21317 insn
= THUMB_OP32 (opcode
);
21318 insn
|= (old_op
& 0xf0) << 4;
21319 insn
|= (old_op
& 0xf) << 16;
21320 put_thumb32_insn (buf
, insn
);
21321 if (insn
& (1 << 20))
21322 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21324 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21327 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21333 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21334 (enum bfd_reloc_code_real
) reloc_type
);
21335 fixp
->fx_file
= fragp
->fr_file
;
21336 fixp
->fx_line
= fragp
->fr_line
;
21337 fragp
->fr_fix
+= fragp
->fr_var
;
21339 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21340 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21341 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21342 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21345 /* Return the size of a relaxable immediate operand instruction.
21346 SHIFT and SIZE specify the form of the allowable immediate. */
21348 relax_immediate (fragS
*fragp
, int size
, int shift
)
21354 /* ??? Should be able to do better than this. */
21355 if (fragp
->fr_symbol
)
21358 low
= (1 << shift
) - 1;
21359 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21360 offset
= fragp
->fr_offset
;
21361 /* Force misaligned offsets to 32-bit variant. */
21364 if (offset
& ~mask
)
21369 /* Get the address of a symbol during relaxation. */
21371 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21377 sym
= fragp
->fr_symbol
;
21378 sym_frag
= symbol_get_frag (sym
);
21379 know (S_GET_SEGMENT (sym
) != absolute_section
21380 || sym_frag
== &zero_address_frag
);
21381 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21383 /* If frag has yet to be reached on this pass, assume it will
21384 move by STRETCH just as we did. If this is not so, it will
21385 be because some frag between grows, and that will force
21389 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21393 /* Adjust stretch for any alignment frag. Note that if have
21394 been expanding the earlier code, the symbol may be
21395 defined in what appears to be an earlier frag. FIXME:
21396 This doesn't handle the fr_subtype field, which specifies
21397 a maximum number of bytes to skip when doing an
21399 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21401 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21404 stretch
= - ((- stretch
)
21405 & ~ ((1 << (int) f
->fr_offset
) - 1));
21407 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21419 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21422 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21427 /* Assume worst case for symbols not known to be in the same section. */
21428 if (fragp
->fr_symbol
== NULL
21429 || !S_IS_DEFINED (fragp
->fr_symbol
)
21430 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21431 || S_IS_WEAK (fragp
->fr_symbol
))
21434 val
= relaxed_symbol_addr (fragp
, stretch
);
21435 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21436 addr
= (addr
+ 4) & ~3;
21437 /* Force misaligned targets to 32-bit variant. */
21441 if (val
< 0 || val
> 1020)
21446 /* Return the size of a relaxable add/sub immediate instruction. */
21448 relax_addsub (fragS
*fragp
, asection
*sec
)
21453 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21454 op
= bfd_get_16(sec
->owner
, buf
);
21455 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21456 return relax_immediate (fragp
, 8, 0);
21458 return relax_immediate (fragp
, 3, 0);
21461 /* Return TRUE iff the definition of symbol S could be pre-empted
21462 (overridden) at link or load time. */
21464 symbol_preemptible (symbolS
*s
)
21466 /* Weak symbols can always be pre-empted. */
21470 /* Non-global symbols cannot be pre-empted. */
21471 if (! S_IS_EXTERNAL (s
))
21475 /* In ELF, a global symbol can be marked protected, or private. In that
21476 case it can't be pre-empted (other definitions in the same link unit
21477 would violate the ODR). */
21478 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21482 /* Other global symbols might be pre-empted. */
21486 /* Return the size of a relaxable branch instruction. BITS is the
21487 size of the offset field in the narrow instruction. */
21490 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21496 /* Assume worst case for symbols not known to be in the same section. */
21497 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21498 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21499 || S_IS_WEAK (fragp
->fr_symbol
))
21503 /* A branch to a function in ARM state will require interworking. */
21504 if (S_IS_DEFINED (fragp
->fr_symbol
)
21505 && ARM_IS_FUNC (fragp
->fr_symbol
))
21509 if (symbol_preemptible (fragp
->fr_symbol
))
21512 val
= relaxed_symbol_addr (fragp
, stretch
);
21513 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21516 /* Offset is a signed value *2 */
21518 if (val
>= limit
|| val
< -limit
)
21524 /* Relax a machine dependent frag. This returns the amount by which
21525 the current size of the frag should change. */
21528 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21533 oldsize
= fragp
->fr_var
;
21534 switch (fragp
->fr_subtype
)
21536 case T_MNEM_ldr_pc2
:
21537 newsize
= relax_adr (fragp
, sec
, stretch
);
21539 case T_MNEM_ldr_pc
:
21540 case T_MNEM_ldr_sp
:
21541 case T_MNEM_str_sp
:
21542 newsize
= relax_immediate (fragp
, 8, 2);
21546 newsize
= relax_immediate (fragp
, 5, 2);
21550 newsize
= relax_immediate (fragp
, 5, 1);
21554 newsize
= relax_immediate (fragp
, 5, 0);
21557 newsize
= relax_adr (fragp
, sec
, stretch
);
21563 newsize
= relax_immediate (fragp
, 8, 0);
21566 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21569 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21571 case T_MNEM_add_sp
:
21572 case T_MNEM_add_pc
:
21573 newsize
= relax_immediate (fragp
, 8, 2);
21575 case T_MNEM_inc_sp
:
21576 case T_MNEM_dec_sp
:
21577 newsize
= relax_immediate (fragp
, 7, 2);
21583 newsize
= relax_addsub (fragp
, sec
);
21589 fragp
->fr_var
= newsize
;
21590 /* Freeze wide instructions that are at or before the same location as
21591 in the previous pass. This avoids infinite loops.
21592 Don't freeze them unconditionally because targets may be artificially
21593 misaligned by the expansion of preceding frags. */
21594 if (stretch
<= 0 && newsize
> 2)
21596 md_convert_frag (sec
->owner
, sec
, fragp
);
21600 return newsize
- oldsize
;
21603 /* Round up a section size to the appropriate boundary. */
21606 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21609 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21610 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21612 /* For a.out, force the section size to be aligned. If we don't do
21613 this, BFD will align it for us, but it will not write out the
21614 final bytes of the section. This may be a bug in BFD, but it is
21615 easier to fix it here since that is how the other a.out targets
21619 align
= bfd_get_section_alignment (stdoutput
, segment
);
21620 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21627 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21628 of an rs_align_code fragment. */
21631 arm_handle_align (fragS
* fragP
)
21633 static unsigned char const arm_noop
[2][2][4] =
21636 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21637 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21640 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21641 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21644 static unsigned char const thumb_noop
[2][2][2] =
21647 {0xc0, 0x46}, /* LE */
21648 {0x46, 0xc0}, /* BE */
21651 {0x00, 0xbf}, /* LE */
21652 {0xbf, 0x00} /* BE */
21655 static unsigned char const wide_thumb_noop
[2][4] =
21656 { /* Wide Thumb-2 */
21657 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21658 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21661 unsigned bytes
, fix
, noop_size
;
21663 const unsigned char * noop
;
21664 const unsigned char *narrow_noop
= NULL
;
21669 if (fragP
->fr_type
!= rs_align_code
)
21672 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21673 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21676 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21677 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21679 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21681 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21683 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21684 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21686 narrow_noop
= thumb_noop
[1][target_big_endian
];
21687 noop
= wide_thumb_noop
[target_big_endian
];
21690 noop
= thumb_noop
[0][target_big_endian
];
21698 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21699 ? selected_cpu
: arm_arch_none
,
21701 [target_big_endian
];
21708 fragP
->fr_var
= noop_size
;
21710 if (bytes
& (noop_size
- 1))
21712 fix
= bytes
& (noop_size
- 1);
21714 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21716 memset (p
, 0, fix
);
21723 if (bytes
& noop_size
)
21725 /* Insert a narrow noop. */
21726 memcpy (p
, narrow_noop
, noop_size
);
21728 bytes
-= noop_size
;
21732 /* Use wide noops for the remainder */
21736 while (bytes
>= noop_size
)
21738 memcpy (p
, noop
, noop_size
);
21740 bytes
-= noop_size
;
21744 fragP
->fr_fix
+= fix
;
21747 /* Called from md_do_align. Used to create an alignment
21748 frag in a code section. */
21751 arm_frag_align_code (int n
, int max
)
21755 /* We assume that there will never be a requirement
21756 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21757 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21762 _("alignments greater than %d bytes not supported in .text sections."),
21763 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21764 as_fatal ("%s", err_msg
);
21767 p
= frag_var (rs_align_code
,
21768 MAX_MEM_FOR_RS_ALIGN_CODE
,
21770 (relax_substateT
) max
,
21777 /* Perform target specific initialisation of a frag.
21778 Note - despite the name this initialisation is not done when the frag
21779 is created, but only when its type is assigned. A frag can be created
21780 and used a long time before its type is set, so beware of assuming that
21781 this initialisationis performed first. */
21785 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21787 /* Record whether this frag is in an ARM or a THUMB area. */
21788 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21791 #else /* OBJ_ELF is defined. */
21793 arm_init_frag (fragS
* fragP
, int max_chars
)
21795 int frag_thumb_mode
;
21797 /* If the current ARM vs THUMB mode has not already
21798 been recorded into this frag then do so now. */
21799 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21800 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21802 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21804 /* Record a mapping symbol for alignment frags. We will delete this
21805 later if the alignment ends up empty. */
21806 switch (fragP
->fr_type
)
21809 case rs_align_test
:
21811 mapping_state_2 (MAP_DATA
, max_chars
);
21813 case rs_align_code
:
21814 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21821 /* When we change sections we need to issue a new mapping symbol. */
21824 arm_elf_change_section (void)
21826 /* Link an unlinked unwind index table section to the .text section. */
21827 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21828 && elf_linked_to_section (now_seg
) == NULL
)
21829 elf_linked_to_section (now_seg
) = text_section
;
21833 arm_elf_section_type (const char * str
, size_t len
)
21835 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21836 return SHT_ARM_EXIDX
;
21841 /* Code to deal with unwinding tables. */
21843 static void add_unwind_adjustsp (offsetT
);
21845 /* Generate any deferred unwind frame offset. */
21848 flush_pending_unwind (void)
21852 offset
= unwind
.pending_offset
;
21853 unwind
.pending_offset
= 0;
21855 add_unwind_adjustsp (offset
);
21858 /* Add an opcode to this list for this function. Two-byte opcodes should
21859 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21863 add_unwind_opcode (valueT op
, int length
)
21865 /* Add any deferred stack adjustment. */
21866 if (unwind
.pending_offset
)
21867 flush_pending_unwind ();
21869 unwind
.sp_restored
= 0;
21871 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21873 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21874 if (unwind
.opcodes
)
21875 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21876 unwind
.opcode_alloc
);
21878 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21883 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21885 unwind
.opcode_count
++;
21889 /* Add unwind opcodes to adjust the stack pointer. */
21892 add_unwind_adjustsp (offsetT offset
)
21896 if (offset
> 0x200)
21898 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21903 /* Long form: 0xb2, uleb128. */
21904 /* This might not fit in a word so add the individual bytes,
21905 remembering the list is built in reverse order. */
21906 o
= (valueT
) ((offset
- 0x204) >> 2);
21908 add_unwind_opcode (0, 1);
21910 /* Calculate the uleb128 encoding of the offset. */
21914 bytes
[n
] = o
& 0x7f;
21920 /* Add the insn. */
21922 add_unwind_opcode (bytes
[n
- 1], 1);
21923 add_unwind_opcode (0xb2, 1);
21925 else if (offset
> 0x100)
21927 /* Two short opcodes. */
21928 add_unwind_opcode (0x3f, 1);
21929 op
= (offset
- 0x104) >> 2;
21930 add_unwind_opcode (op
, 1);
21932 else if (offset
> 0)
21934 /* Short opcode. */
21935 op
= (offset
- 4) >> 2;
21936 add_unwind_opcode (op
, 1);
21938 else if (offset
< 0)
21941 while (offset
> 0x100)
21943 add_unwind_opcode (0x7f, 1);
21946 op
= ((offset
- 4) >> 2) | 0x40;
21947 add_unwind_opcode (op
, 1);
21951 /* Finish the list of unwind opcodes for this function. */
21953 finish_unwind_opcodes (void)
21957 if (unwind
.fp_used
)
21959 /* Adjust sp as necessary. */
21960 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21961 flush_pending_unwind ();
21963 /* After restoring sp from the frame pointer. */
21964 op
= 0x90 | unwind
.fp_reg
;
21965 add_unwind_opcode (op
, 1);
21968 flush_pending_unwind ();
21972 /* Start an exception table entry. If idx is nonzero this is an index table
21976 start_unwind_section (const segT text_seg
, int idx
)
21978 const char * text_name
;
21979 const char * prefix
;
21980 const char * prefix_once
;
21981 const char * group_name
;
21989 prefix
= ELF_STRING_ARM_unwind
;
21990 prefix_once
= ELF_STRING_ARM_unwind_once
;
21991 type
= SHT_ARM_EXIDX
;
21995 prefix
= ELF_STRING_ARM_unwind_info
;
21996 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21997 type
= SHT_PROGBITS
;
22000 text_name
= segment_name (text_seg
);
22001 if (streq (text_name
, ".text"))
22004 if (strncmp (text_name
, ".gnu.linkonce.t.",
22005 strlen (".gnu.linkonce.t.")) == 0)
22007 prefix
= prefix_once
;
22008 text_name
+= strlen (".gnu.linkonce.t.");
22011 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22017 /* Handle COMDAT group. */
22018 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22020 group_name
= elf_group_name (text_seg
);
22021 if (group_name
== NULL
)
22023 as_bad (_("Group section `%s' has no group signature"),
22024 segment_name (text_seg
));
22025 ignore_rest_of_line ();
22028 flags
|= SHF_GROUP
;
22032 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
22034 /* Set the section link for index tables. */
22036 elf_linked_to_section (now_seg
) = text_seg
;
22040 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22041 personality routine data. Returns zero, or the index table value for
22042 an inline entry. */
22045 create_unwind_entry (int have_data
)
22050 /* The current word of data. */
22052 /* The number of bytes left in this word. */
22055 finish_unwind_opcodes ();
22057 /* Remember the current text section. */
22058 unwind
.saved_seg
= now_seg
;
22059 unwind
.saved_subseg
= now_subseg
;
22061 start_unwind_section (now_seg
, 0);
22063 if (unwind
.personality_routine
== NULL
)
22065 if (unwind
.personality_index
== -2)
22068 as_bad (_("handlerdata in cantunwind frame"));
22069 return 1; /* EXIDX_CANTUNWIND. */
22072 /* Use a default personality routine if none is specified. */
22073 if (unwind
.personality_index
== -1)
22075 if (unwind
.opcode_count
> 3)
22076 unwind
.personality_index
= 1;
22078 unwind
.personality_index
= 0;
22081 /* Space for the personality routine entry. */
22082 if (unwind
.personality_index
== 0)
22084 if (unwind
.opcode_count
> 3)
22085 as_bad (_("too many unwind opcodes for personality routine 0"));
22089 /* All the data is inline in the index table. */
22092 while (unwind
.opcode_count
> 0)
22094 unwind
.opcode_count
--;
22095 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22099 /* Pad with "finish" opcodes. */
22101 data
= (data
<< 8) | 0xb0;
22108 /* We get two opcodes "free" in the first word. */
22109 size
= unwind
.opcode_count
- 2;
22113 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22114 if (unwind
.personality_index
!= -1)
22116 as_bad (_("attempt to recreate an unwind entry"));
22120 /* An extra byte is required for the opcode count. */
22121 size
= unwind
.opcode_count
+ 1;
22124 size
= (size
+ 3) >> 2;
22126 as_bad (_("too many unwind opcodes"));
22128 frag_align (2, 0, 0);
22129 record_alignment (now_seg
, 2);
22130 unwind
.table_entry
= expr_build_dot ();
22132 /* Allocate the table entry. */
22133 ptr
= frag_more ((size
<< 2) + 4);
22134 /* PR 13449: Zero the table entries in case some of them are not used. */
22135 memset (ptr
, 0, (size
<< 2) + 4);
22136 where
= frag_now_fix () - ((size
<< 2) + 4);
22138 switch (unwind
.personality_index
)
22141 /* ??? Should this be a PLT generating relocation? */
22142 /* Custom personality routine. */
22143 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22144 BFD_RELOC_ARM_PREL31
);
22149 /* Set the first byte to the number of additional words. */
22150 data
= size
> 0 ? size
- 1 : 0;
22154 /* ABI defined personality routines. */
22156 /* Three opcodes bytes are packed into the first word. */
22163 /* The size and first two opcode bytes go in the first word. */
22164 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22169 /* Should never happen. */
22173 /* Pack the opcodes into words (MSB first), reversing the list at the same
22175 while (unwind
.opcode_count
> 0)
22179 md_number_to_chars (ptr
, data
, 4);
22184 unwind
.opcode_count
--;
22186 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22189 /* Finish off the last word. */
22192 /* Pad with "finish" opcodes. */
22194 data
= (data
<< 8) | 0xb0;
22196 md_number_to_chars (ptr
, data
, 4);
22201 /* Add an empty descriptor if there is no user-specified data. */
22202 ptr
= frag_more (4);
22203 md_number_to_chars (ptr
, 0, 4);
22210 /* Initialize the DWARF-2 unwind information for this procedure. */
22213 tc_arm_frame_initial_instructions (void)
22215 cfi_add_CFA_def_cfa (REG_SP
, 0);
22217 #endif /* OBJ_ELF */
22219 /* Convert REGNAME to a DWARF-2 register number. */
22222 tc_arm_regname_to_dw2regnum (char *regname
)
22224 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22228 /* PR 16694: Allow VFP registers as well. */
22229 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22233 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22242 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22246 exp
.X_op
= O_secrel
;
22247 exp
.X_add_symbol
= symbol
;
22248 exp
.X_add_number
= 0;
22249 emit_expr (&exp
, size
);
22253 /* MD interface: Symbol and relocation handling. */
22255 /* Return the address within the segment that a PC-relative fixup is
22256 relative to. For ARM, PC-relative fixups applied to instructions
22257 are generally relative to the location of the fixup plus 8 bytes.
22258 Thumb branches are offset by 4, and Thumb loads relative to PC
22259 require special handling. */
22262 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22264 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22266 /* If this is pc-relative and we are going to emit a relocation
22267 then we just want to put out any pipeline compensation that the linker
22268 will need. Otherwise we want to use the calculated base.
22269 For WinCE we skip the bias for externals as well, since this
22270 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22272 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22273 || (arm_force_relocation (fixP
)
22275 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22281 switch (fixP
->fx_r_type
)
22283 /* PC relative addressing on the Thumb is slightly odd as the
22284 bottom two bits of the PC are forced to zero for the
22285 calculation. This happens *after* application of the
22286 pipeline offset. However, Thumb adrl already adjusts for
22287 this, so we need not do it again. */
22288 case BFD_RELOC_ARM_THUMB_ADD
:
22291 case BFD_RELOC_ARM_THUMB_OFFSET
:
22292 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22293 case BFD_RELOC_ARM_T32_ADD_PC12
:
22294 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22295 return (base
+ 4) & ~3;
22297 /* Thumb branches are simply offset by +4. */
22298 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22299 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22300 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22301 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22302 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22305 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22307 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22308 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22309 && ARM_IS_FUNC (fixP
->fx_addsy
)
22310 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22311 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22314 /* BLX is like branches above, but forces the low two bits of PC to
22316 case BFD_RELOC_THUMB_PCREL_BLX
:
22318 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22319 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22320 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22321 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22322 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22323 return (base
+ 4) & ~3;
22325 /* ARM mode branches are offset by +8. However, the Windows CE
22326 loader expects the relocation not to take this into account. */
22327 case BFD_RELOC_ARM_PCREL_BLX
:
22329 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22330 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22331 && ARM_IS_FUNC (fixP
->fx_addsy
)
22332 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22333 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22336 case BFD_RELOC_ARM_PCREL_CALL
:
22338 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22339 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22340 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22341 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22342 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22345 case BFD_RELOC_ARM_PCREL_BRANCH
:
22346 case BFD_RELOC_ARM_PCREL_JUMP
:
22347 case BFD_RELOC_ARM_PLT32
:
22349 /* When handling fixups immediately, because we have already
22350 discovered the value of a symbol, or the address of the frag involved
22351 we must account for the offset by +8, as the OS loader will never see the reloc.
22352 see fixup_segment() in write.c
22353 The S_IS_EXTERNAL test handles the case of global symbols.
22354 Those need the calculated base, not just the pipe compensation the linker will need. */
22356 && fixP
->fx_addsy
!= NULL
22357 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22358 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22366 /* ARM mode loads relative to PC are also offset by +8. Unlike
22367 branches, the Windows CE loader *does* expect the relocation
22368 to take this into account. */
22369 case BFD_RELOC_ARM_OFFSET_IMM
:
22370 case BFD_RELOC_ARM_OFFSET_IMM8
:
22371 case BFD_RELOC_ARM_HWLITERAL
:
22372 case BFD_RELOC_ARM_LITERAL
:
22373 case BFD_RELOC_ARM_CP_OFF_IMM
:
22377 /* Other PC-relative relocations are un-offset. */
22383 static bfd_boolean flag_warn_syms
= TRUE
;
22386 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22388 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22389 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22390 does mean that the resulting code might be very confusing to the reader.
22391 Also this warning can be triggered if the user omits an operand before
22392 an immediate address, eg:
22396 GAS treats this as an assignment of the value of the symbol foo to a
22397 symbol LDR, and so (without this code) it will not issue any kind of
22398 warning or error message.
22400 Note - ARM instructions are case-insensitive but the strings in the hash
22401 table are all stored in lower case, so we must first ensure that name is
22403 if (flag_warn_syms
&& arm_ops_hsh
)
22405 char * nbuf
= strdup (name
);
22408 for (p
= nbuf
; *p
; p
++)
22410 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22412 static struct hash_control
* already_warned
= NULL
;
22414 if (already_warned
== NULL
)
22415 already_warned
= hash_new ();
22416 /* Only warn about the symbol once. To keep the code
22417 simple we let hash_insert do the lookup for us. */
22418 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22419 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22428 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22429 Otherwise we have no need to default values of symbols. */
22432 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22435 if (name
[0] == '_' && name
[1] == 'G'
22436 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22440 if (symbol_find (name
))
22441 as_bad (_("GOT already in the symbol table"));
22443 GOT_symbol
= symbol_new (name
, undefined_section
,
22444 (valueT
) 0, & zero_address_frag
);
22454 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22455 computed as two separate immediate values, added together. We
22456 already know that this value cannot be computed by just one ARM
22459 static unsigned int
22460 validate_immediate_twopart (unsigned int val
,
22461 unsigned int * highpart
)
22466 for (i
= 0; i
< 32; i
+= 2)
22467 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22473 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22475 else if (a
& 0xff0000)
22477 if (a
& 0xff000000)
22479 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22483 gas_assert (a
& 0xff000000);
22484 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22487 return (a
& 0xff) | (i
<< 7);
22494 validate_offset_imm (unsigned int val
, int hwse
)
22496 if ((hwse
&& val
> 255) || val
> 4095)
22501 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22502 negative immediate constant by altering the instruction. A bit of
22507 by inverting the second operand, and
22510 by negating the second operand. */
22513 negate_data_op (unsigned long * instruction
,
22514 unsigned long value
)
22517 unsigned long negated
, inverted
;
22519 negated
= encode_arm_immediate (-value
);
22520 inverted
= encode_arm_immediate (~value
);
22522 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22525 /* First negates. */
22526 case OPCODE_SUB
: /* ADD <-> SUB */
22527 new_inst
= OPCODE_ADD
;
22532 new_inst
= OPCODE_SUB
;
22536 case OPCODE_CMP
: /* CMP <-> CMN */
22537 new_inst
= OPCODE_CMN
;
22542 new_inst
= OPCODE_CMP
;
22546 /* Now Inverted ops. */
22547 case OPCODE_MOV
: /* MOV <-> MVN */
22548 new_inst
= OPCODE_MVN
;
22553 new_inst
= OPCODE_MOV
;
22557 case OPCODE_AND
: /* AND <-> BIC */
22558 new_inst
= OPCODE_BIC
;
22563 new_inst
= OPCODE_AND
;
22567 case OPCODE_ADC
: /* ADC <-> SBC */
22568 new_inst
= OPCODE_SBC
;
22573 new_inst
= OPCODE_ADC
;
22577 /* We cannot do anything. */
22582 if (value
== (unsigned) FAIL
)
22585 *instruction
&= OPCODE_MASK
;
22586 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22590 /* Like negate_data_op, but for Thumb-2. */
22592 static unsigned int
22593 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22597 unsigned int negated
, inverted
;
22599 negated
= encode_thumb32_immediate (-value
);
22600 inverted
= encode_thumb32_immediate (~value
);
22602 rd
= (*instruction
>> 8) & 0xf;
22603 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22606 /* ADD <-> SUB. Includes CMP <-> CMN. */
22607 case T2_OPCODE_SUB
:
22608 new_inst
= T2_OPCODE_ADD
;
22612 case T2_OPCODE_ADD
:
22613 new_inst
= T2_OPCODE_SUB
;
22617 /* ORR <-> ORN. Includes MOV <-> MVN. */
22618 case T2_OPCODE_ORR
:
22619 new_inst
= T2_OPCODE_ORN
;
22623 case T2_OPCODE_ORN
:
22624 new_inst
= T2_OPCODE_ORR
;
22628 /* AND <-> BIC. TST has no inverted equivalent. */
22629 case T2_OPCODE_AND
:
22630 new_inst
= T2_OPCODE_BIC
;
22637 case T2_OPCODE_BIC
:
22638 new_inst
= T2_OPCODE_AND
;
22643 case T2_OPCODE_ADC
:
22644 new_inst
= T2_OPCODE_SBC
;
22648 case T2_OPCODE_SBC
:
22649 new_inst
= T2_OPCODE_ADC
;
22653 /* We cannot do anything. */
22658 if (value
== (unsigned int)FAIL
)
22661 *instruction
&= T2_OPCODE_MASK
;
22662 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22666 /* Read a 32-bit thumb instruction from buf. */
22667 static unsigned long
22668 get_thumb32_insn (char * buf
)
22670 unsigned long insn
;
22671 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22672 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22678 /* We usually want to set the low bit on the address of thumb function
22679 symbols. In particular .word foo - . should have the low bit set.
22680 Generic code tries to fold the difference of two symbols to
22681 a constant. Prevent this and force a relocation when the first symbols
22682 is a thumb function. */
22685 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22687 if (op
== O_subtract
22688 && l
->X_op
== O_symbol
22689 && r
->X_op
== O_symbol
22690 && THUMB_IS_FUNC (l
->X_add_symbol
))
22692 l
->X_op
= O_subtract
;
22693 l
->X_op_symbol
= r
->X_add_symbol
;
22694 l
->X_add_number
-= r
->X_add_number
;
22698 /* Process as normal. */
22702 /* Encode Thumb2 unconditional branches and calls. The encoding
22703 for the 2 are identical for the immediate values. */
22706 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22708 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22711 addressT S
, I1
, I2
, lo
, hi
;
22713 S
= (value
>> 24) & 0x01;
22714 I1
= (value
>> 23) & 0x01;
22715 I2
= (value
>> 22) & 0x01;
22716 hi
= (value
>> 12) & 0x3ff;
22717 lo
= (value
>> 1) & 0x7ff;
22718 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22719 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22720 newval
|= (S
<< 10) | hi
;
22721 newval2
&= ~T2I1I2MASK
;
22722 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22723 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22724 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22728 md_apply_fix (fixS
* fixP
,
22732 offsetT value
= * valP
;
22734 unsigned int newimm
;
22735 unsigned long temp
;
22737 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22739 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22741 /* Note whether this will delete the relocation. */
22743 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22746 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22747 consistency with the behaviour on 32-bit hosts. Remember value
22749 value
&= 0xffffffff;
22750 value
^= 0x80000000;
22751 value
-= 0x80000000;
22754 fixP
->fx_addnumber
= value
;
22756 /* Same treatment for fixP->fx_offset. */
22757 fixP
->fx_offset
&= 0xffffffff;
22758 fixP
->fx_offset
^= 0x80000000;
22759 fixP
->fx_offset
-= 0x80000000;
22761 switch (fixP
->fx_r_type
)
22763 case BFD_RELOC_NONE
:
22764 /* This will need to go in the object file. */
22768 case BFD_RELOC_ARM_IMMEDIATE
:
22769 /* We claim that this fixup has been processed here,
22770 even if in fact we generate an error because we do
22771 not have a reloc for it, so tc_gen_reloc will reject it. */
22774 if (fixP
->fx_addsy
)
22776 const char *msg
= 0;
22778 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22779 msg
= _("undefined symbol %s used as an immediate value");
22780 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22781 msg
= _("symbol %s is in a different section");
22782 else if (S_IS_WEAK (fixP
->fx_addsy
))
22783 msg
= _("symbol %s is weak and may be overridden later");
22787 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22788 msg
, S_GET_NAME (fixP
->fx_addsy
));
22793 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22795 /* If the offset is negative, we should use encoding A2 for ADR. */
22796 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22797 newimm
= negate_data_op (&temp
, value
);
22800 newimm
= encode_arm_immediate (value
);
22802 /* If the instruction will fail, see if we can fix things up by
22803 changing the opcode. */
22804 if (newimm
== (unsigned int) FAIL
)
22805 newimm
= negate_data_op (&temp
, value
);
22806 /* MOV accepts both ARM modified immediate (A1 encoding) and
22807 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
22808 When disassembling, MOV is preferred when there is no encoding
22810 if (newimm
== (unsigned int) FAIL
22811 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
22812 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
22813 && !((temp
>> SBIT_SHIFT
) & 0x1)
22814 && value
>= 0 && value
<= 0xffff)
22816 /* Clear bits[23:20] to change encoding from A1 to A2. */
22817 temp
&= 0xff0fffff;
22818 /* Encoding high 4bits imm. Code below will encode the remaining
22820 temp
|= (value
& 0x0000f000) << 4;
22821 newimm
= value
& 0x00000fff;
22825 if (newimm
== (unsigned int) FAIL
)
22827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22828 _("invalid constant (%lx) after fixup"),
22829 (unsigned long) value
);
22833 newimm
|= (temp
& 0xfffff000);
22834 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22837 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22839 unsigned int highpart
= 0;
22840 unsigned int newinsn
= 0xe1a00000; /* nop. */
22842 if (fixP
->fx_addsy
)
22844 const char *msg
= 0;
22846 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22847 msg
= _("undefined symbol %s used as an immediate value");
22848 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22849 msg
= _("symbol %s is in a different section");
22850 else if (S_IS_WEAK (fixP
->fx_addsy
))
22851 msg
= _("symbol %s is weak and may be overridden later");
22855 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22856 msg
, S_GET_NAME (fixP
->fx_addsy
));
22861 newimm
= encode_arm_immediate (value
);
22862 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22864 /* If the instruction will fail, see if we can fix things up by
22865 changing the opcode. */
22866 if (newimm
== (unsigned int) FAIL
22867 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22869 /* No ? OK - try using two ADD instructions to generate
22871 newimm
= validate_immediate_twopart (value
, & highpart
);
22873 /* Yes - then make sure that the second instruction is
22875 if (newimm
!= (unsigned int) FAIL
)
22877 /* Still No ? Try using a negated value. */
22878 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22879 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22880 /* Otherwise - give up. */
22883 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22884 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22889 /* Replace the first operand in the 2nd instruction (which
22890 is the PC) with the destination register. We have
22891 already added in the PC in the first instruction and we
22892 do not want to do it again. */
22893 newinsn
&= ~ 0xf0000;
22894 newinsn
|= ((newinsn
& 0x0f000) << 4);
22897 newimm
|= (temp
& 0xfffff000);
22898 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22900 highpart
|= (newinsn
& 0xfffff000);
22901 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22905 case BFD_RELOC_ARM_OFFSET_IMM
:
22906 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22908 /* Fall through. */
22910 case BFD_RELOC_ARM_LITERAL
:
22916 if (validate_offset_imm (value
, 0) == FAIL
)
22918 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22919 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22920 _("invalid literal constant: pool needs to be closer"));
22922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22923 _("bad immediate value for offset (%ld)"),
22928 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22930 newval
&= 0xfffff000;
22933 newval
&= 0xff7ff000;
22934 newval
|= value
| (sign
? INDEX_UP
: 0);
22936 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22939 case BFD_RELOC_ARM_OFFSET_IMM8
:
22940 case BFD_RELOC_ARM_HWLITERAL
:
22946 if (validate_offset_imm (value
, 1) == FAIL
)
22948 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22949 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22950 _("invalid literal constant: pool needs to be closer"));
22952 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22953 _("bad immediate value for 8-bit offset (%ld)"),
22958 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22960 newval
&= 0xfffff0f0;
22963 newval
&= 0xff7ff0f0;
22964 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22966 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22969 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22970 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22972 _("bad immediate value for offset (%ld)"), (long) value
);
22975 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22977 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22980 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22981 /* This is a complicated relocation used for all varieties of Thumb32
22982 load/store instruction with immediate offset:
22984 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22985 *4, optional writeback(W)
22986 (doubleword load/store)
22988 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22989 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22990 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22991 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22992 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22994 Uppercase letters indicate bits that are already encoded at
22995 this point. Lowercase letters are our problem. For the
22996 second block of instructions, the secondary opcode nybble
22997 (bits 8..11) is present, and bit 23 is zero, even if this is
22998 a PC-relative operation. */
22999 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23001 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23003 if ((newval
& 0xf0000000) == 0xe0000000)
23005 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23007 newval
|= (1 << 23);
23010 if (value
% 4 != 0)
23012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23013 _("offset not a multiple of 4"));
23019 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23020 _("offset out of range"));
23025 else if ((newval
& 0x000f0000) == 0x000f0000)
23027 /* PC-relative, 12-bit offset. */
23029 newval
|= (1 << 23);
23034 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23035 _("offset out of range"));
23040 else if ((newval
& 0x00000100) == 0x00000100)
23042 /* Writeback: 8-bit, +/- offset. */
23044 newval
|= (1 << 9);
23049 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23050 _("offset out of range"));
23055 else if ((newval
& 0x00000f00) == 0x00000e00)
23057 /* T-instruction: positive 8-bit offset. */
23058 if (value
< 0 || value
> 0xff)
23060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23061 _("offset out of range"));
23069 /* Positive 12-bit or negative 8-bit offset. */
23073 newval
|= (1 << 23);
23083 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23084 _("offset out of range"));
23091 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23092 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23095 case BFD_RELOC_ARM_SHIFT_IMM
:
23096 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23097 if (((unsigned long) value
) > 32
23099 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23101 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23102 _("shift expression is too large"));
23107 /* Shifts of zero must be done as lsl. */
23109 else if (value
== 32)
23111 newval
&= 0xfffff07f;
23112 newval
|= (value
& 0x1f) << 7;
23113 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23116 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23117 case BFD_RELOC_ARM_T32_ADD_IMM
:
23118 case BFD_RELOC_ARM_T32_IMM12
:
23119 case BFD_RELOC_ARM_T32_ADD_PC12
:
23120 /* We claim that this fixup has been processed here,
23121 even if in fact we generate an error because we do
23122 not have a reloc for it, so tc_gen_reloc will reject it. */
23126 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23128 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23129 _("undefined symbol %s used as an immediate value"),
23130 S_GET_NAME (fixP
->fx_addsy
));
23134 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23136 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23139 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23140 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23141 Thumb2 modified immediate encoding (T2). */
23142 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23143 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23145 newimm
= encode_thumb32_immediate (value
);
23146 if (newimm
== (unsigned int) FAIL
)
23147 newimm
= thumb32_negate_data_op (&newval
, value
);
23149 if (newimm
== (unsigned int) FAIL
)
23151 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23153 /* Turn add/sum into addw/subw. */
23154 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23155 newval
= (newval
& 0xfeffffff) | 0x02000000;
23156 /* No flat 12-bit imm encoding for addsw/subsw. */
23157 if ((newval
& 0x00100000) == 0)
23159 /* 12 bit immediate for addw/subw. */
23163 newval
^= 0x00a00000;
23166 newimm
= (unsigned int) FAIL
;
23173 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23174 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23175 disassembling, MOV is preferred when there is no encoding
23177 NOTE: MOV is using ORR opcode under Thumb 2 mode. */
23178 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23179 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23180 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23181 && value
>= 0 && value
<=0xffff)
23183 /* Toggle bit[25] to change encoding from T2 to T3. */
23185 /* Clear bits[19:16]. */
23186 newval
&= 0xfff0ffff;
23187 /* Encoding high 4bits imm. Code below will encode the
23188 remaining low 12bits. */
23189 newval
|= (value
& 0x0000f000) << 4;
23190 newimm
= value
& 0x00000fff;
23195 if (newimm
== (unsigned int)FAIL
)
23197 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23198 _("invalid constant (%lx) after fixup"),
23199 (unsigned long) value
);
23203 newval
|= (newimm
& 0x800) << 15;
23204 newval
|= (newimm
& 0x700) << 4;
23205 newval
|= (newimm
& 0x0ff);
23207 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23208 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23211 case BFD_RELOC_ARM_SMC
:
23212 if (((unsigned long) value
) > 0xffff)
23213 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23214 _("invalid smc expression"));
23215 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23216 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23217 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23220 case BFD_RELOC_ARM_HVC
:
23221 if (((unsigned long) value
) > 0xffff)
23222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23223 _("invalid hvc expression"));
23224 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23225 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23226 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23229 case BFD_RELOC_ARM_SWI
:
23230 if (fixP
->tc_fix_data
!= 0)
23232 if (((unsigned long) value
) > 0xff)
23233 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23234 _("invalid swi expression"));
23235 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23237 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23241 if (((unsigned long) value
) > 0x00ffffff)
23242 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23243 _("invalid swi expression"));
23244 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23246 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23250 case BFD_RELOC_ARM_MULTI
:
23251 if (((unsigned long) value
) > 0xffff)
23252 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23253 _("invalid expression in load/store multiple"));
23254 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23255 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23259 case BFD_RELOC_ARM_PCREL_CALL
:
23261 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23263 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23264 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23265 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23266 /* Flip the bl to blx. This is a simple flip
23267 bit here because we generate PCREL_CALL for
23268 unconditional bls. */
23270 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23271 newval
= newval
| 0x10000000;
23272 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23278 goto arm_branch_common
;
23280 case BFD_RELOC_ARM_PCREL_JUMP
:
23281 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23283 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23284 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23285 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23287 /* This would map to a bl<cond>, b<cond>,
23288 b<always> to a Thumb function. We
23289 need to force a relocation for this particular
23291 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23294 /* Fall through. */
23296 case BFD_RELOC_ARM_PLT32
:
23298 case BFD_RELOC_ARM_PCREL_BRANCH
:
23300 goto arm_branch_common
;
23302 case BFD_RELOC_ARM_PCREL_BLX
:
23305 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23307 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23308 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23309 && ARM_IS_FUNC (fixP
->fx_addsy
))
23311 /* Flip the blx to a bl and warn. */
23312 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23313 newval
= 0xeb000000;
23314 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23315 _("blx to '%s' an ARM ISA state function changed to bl"),
23317 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23323 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23324 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23328 /* We are going to store value (shifted right by two) in the
23329 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23330 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23331 also be be clear. */
23333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23334 _("misaligned branch destination"));
23335 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23336 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23339 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23341 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23342 newval
|= (value
>> 2) & 0x00ffffff;
23343 /* Set the H bit on BLX instructions. */
23347 newval
|= 0x01000000;
23349 newval
&= ~0x01000000;
23351 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23355 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23356 /* CBZ can only branch forward. */
23358 /* Attempts to use CBZ to branch to the next instruction
23359 (which, strictly speaking, are prohibited) will be turned into
23362 FIXME: It may be better to remove the instruction completely and
23363 perform relaxation. */
23366 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23367 newval
= 0xbf00; /* NOP encoding T1 */
23368 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23373 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23375 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23377 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23378 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23379 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23384 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23385 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23388 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23390 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23391 newval
|= (value
& 0x1ff) >> 1;
23392 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23396 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23397 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23398 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23400 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23402 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23403 newval
|= (value
& 0xfff) >> 1;
23404 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23408 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23410 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23411 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23412 && ARM_IS_FUNC (fixP
->fx_addsy
)
23413 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23415 /* Force a relocation for a branch 20 bits wide. */
23418 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23419 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23420 _("conditional branch out of range"));
23422 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23425 addressT S
, J1
, J2
, lo
, hi
;
23427 S
= (value
& 0x00100000) >> 20;
23428 J2
= (value
& 0x00080000) >> 19;
23429 J1
= (value
& 0x00040000) >> 18;
23430 hi
= (value
& 0x0003f000) >> 12;
23431 lo
= (value
& 0x00000ffe) >> 1;
23433 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23434 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23435 newval
|= (S
<< 10) | hi
;
23436 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23437 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23438 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23442 case BFD_RELOC_THUMB_PCREL_BLX
:
23443 /* If there is a blx from a thumb state function to
23444 another thumb function flip this to a bl and warn
23448 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23449 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23450 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23452 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23453 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23454 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23456 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23457 newval
= newval
| 0x1000;
23458 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23459 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23464 goto thumb_bl_common
;
23466 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23467 /* A bl from Thumb state ISA to an internal ARM state function
23468 is converted to a blx. */
23470 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23471 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23472 && ARM_IS_FUNC (fixP
->fx_addsy
)
23473 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23475 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23476 newval
= newval
& ~0x1000;
23477 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23478 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23484 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23485 /* For a BLX instruction, make sure that the relocation is rounded up
23486 to a word boundary. This follows the semantics of the instruction
23487 which specifies that bit 1 of the target address will come from bit
23488 1 of the base address. */
23489 value
= (value
+ 3) & ~ 3;
23492 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23493 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23494 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23497 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23499 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23501 else if ((value
& ~0x1ffffff)
23502 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23504 _("Thumb2 branch out of range"));
23507 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23508 encode_thumb2_b_bl_offset (buf
, value
);
23512 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23513 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23514 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23516 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23517 encode_thumb2_b_bl_offset (buf
, value
);
23522 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23527 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23528 md_number_to_chars (buf
, value
, 2);
23532 case BFD_RELOC_ARM_TLS_CALL
:
23533 case BFD_RELOC_ARM_THM_TLS_CALL
:
23534 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23535 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23536 case BFD_RELOC_ARM_TLS_GOTDESC
:
23537 case BFD_RELOC_ARM_TLS_GD32
:
23538 case BFD_RELOC_ARM_TLS_LE32
:
23539 case BFD_RELOC_ARM_TLS_IE32
:
23540 case BFD_RELOC_ARM_TLS_LDM32
:
23541 case BFD_RELOC_ARM_TLS_LDO32
:
23542 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23545 case BFD_RELOC_ARM_GOT32
:
23546 case BFD_RELOC_ARM_GOTOFF
:
23549 case BFD_RELOC_ARM_GOT_PREL
:
23550 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23551 md_number_to_chars (buf
, value
, 4);
23554 case BFD_RELOC_ARM_TARGET2
:
23555 /* TARGET2 is not partial-inplace, so we need to write the
23556 addend here for REL targets, because it won't be written out
23557 during reloc processing later. */
23558 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23559 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23563 case BFD_RELOC_RVA
:
23565 case BFD_RELOC_ARM_TARGET1
:
23566 case BFD_RELOC_ARM_ROSEGREL32
:
23567 case BFD_RELOC_ARM_SBREL32
:
23568 case BFD_RELOC_32_PCREL
:
23570 case BFD_RELOC_32_SECREL
:
23572 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23574 /* For WinCE we only do this for pcrel fixups. */
23575 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23577 md_number_to_chars (buf
, value
, 4);
23581 case BFD_RELOC_ARM_PREL31
:
23582 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23584 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23585 if ((value
^ (value
>> 1)) & 0x40000000)
23587 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23588 _("rel31 relocation overflow"));
23590 newval
|= value
& 0x7fffffff;
23591 md_number_to_chars (buf
, newval
, 4);
23596 case BFD_RELOC_ARM_CP_OFF_IMM
:
23597 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23598 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23599 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23601 newval
= get_thumb32_insn (buf
);
23602 if ((newval
& 0x0f200f00) == 0x0d000900)
23604 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23605 has permitted values that are multiples of 2, in the range 0
23607 if (value
< -510 || value
> 510 || (value
& 1))
23608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23609 _("co-processor offset out of range"));
23611 else if (value
< -1023 || value
> 1023 || (value
& 3))
23612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23613 _("co-processor offset out of range"));
23618 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23619 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23620 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23622 newval
= get_thumb32_insn (buf
);
23624 newval
&= 0xffffff00;
23627 newval
&= 0xff7fff00;
23628 if ((newval
& 0x0f200f00) == 0x0d000900)
23630 /* This is a fp16 vstr/vldr.
23632 It requires the immediate offset in the instruction is shifted
23633 left by 1 to be a half-word offset.
23635 Here, left shift by 1 first, and later right shift by 2
23636 should get the right offset. */
23639 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23641 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23642 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23643 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23645 put_thumb32_insn (buf
, newval
);
23648 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23649 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23650 if (value
< -255 || value
> 255)
23651 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23652 _("co-processor offset out of range"));
23654 goto cp_off_common
;
23656 case BFD_RELOC_ARM_THUMB_OFFSET
:
23657 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23658 /* Exactly what ranges, and where the offset is inserted depends
23659 on the type of instruction, we can establish this from the
23661 switch (newval
>> 12)
23663 case 4: /* PC load. */
23664 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23665 forced to zero for these loads; md_pcrel_from has already
23666 compensated for this. */
23668 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23669 _("invalid offset, target not word aligned (0x%08lX)"),
23670 (((unsigned long) fixP
->fx_frag
->fr_address
23671 + (unsigned long) fixP
->fx_where
) & ~3)
23672 + (unsigned long) value
);
23674 if (value
& ~0x3fc)
23675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23676 _("invalid offset, value too big (0x%08lX)"),
23679 newval
|= value
>> 2;
23682 case 9: /* SP load/store. */
23683 if (value
& ~0x3fc)
23684 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23685 _("invalid offset, value too big (0x%08lX)"),
23687 newval
|= value
>> 2;
23690 case 6: /* Word load/store. */
23692 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23693 _("invalid offset, value too big (0x%08lX)"),
23695 newval
|= value
<< 4; /* 6 - 2. */
23698 case 7: /* Byte load/store. */
23700 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23701 _("invalid offset, value too big (0x%08lX)"),
23703 newval
|= value
<< 6;
23706 case 8: /* Halfword load/store. */
23708 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23709 _("invalid offset, value too big (0x%08lX)"),
23711 newval
|= value
<< 5; /* 6 - 1. */
23715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23716 "Unable to process relocation for thumb opcode: %lx",
23717 (unsigned long) newval
);
23720 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23723 case BFD_RELOC_ARM_THUMB_ADD
:
23724 /* This is a complicated relocation, since we use it for all of
23725 the following immediate relocations:
23729 9bit ADD/SUB SP word-aligned
23730 10bit ADD PC/SP word-aligned
23732 The type of instruction being processed is encoded in the
23739 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23741 int rd
= (newval
>> 4) & 0xf;
23742 int rs
= newval
& 0xf;
23743 int subtract
= !!(newval
& 0x8000);
23745 /* Check for HI regs, only very restricted cases allowed:
23746 Adjusting SP, and using PC or SP to get an address. */
23747 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23748 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23749 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23750 _("invalid Hi register with immediate"));
23752 /* If value is negative, choose the opposite instruction. */
23756 subtract
= !subtract
;
23758 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23759 _("immediate value out of range"));
23764 if (value
& ~0x1fc)
23765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23766 _("invalid immediate for stack address calculation"));
23767 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23768 newval
|= value
>> 2;
23770 else if (rs
== REG_PC
|| rs
== REG_SP
)
23772 /* PR gas/18541. If the addition is for a defined symbol
23773 within range of an ADR instruction then accept it. */
23776 && fixP
->fx_addsy
!= NULL
)
23780 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23781 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23782 || S_IS_WEAK (fixP
->fx_addsy
))
23784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23785 _("address calculation needs a strongly defined nearby symbol"));
23789 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23791 /* Round up to the next 4-byte boundary. */
23796 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23800 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23801 _("symbol too far away"));
23811 if (subtract
|| value
& ~0x3fc)
23812 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23813 _("invalid immediate for address calculation (value = 0x%08lX)"),
23814 (unsigned long) (subtract
? - value
: value
));
23815 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23817 newval
|= value
>> 2;
23822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23823 _("immediate value out of range"));
23824 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23825 newval
|= (rd
<< 8) | value
;
23830 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23831 _("immediate value out of range"));
23832 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23833 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23836 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23839 case BFD_RELOC_ARM_THUMB_IMM
:
23840 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23841 if (value
< 0 || value
> 255)
23842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23843 _("invalid immediate: %ld is out of range"),
23846 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23849 case BFD_RELOC_ARM_THUMB_SHIFT
:
23850 /* 5bit shift value (0..32). LSL cannot take 32. */
23851 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23852 temp
= newval
& 0xf800;
23853 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23854 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23855 _("invalid shift value: %ld"), (long) value
);
23856 /* Shifts of zero must be encoded as LSL. */
23858 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23859 /* Shifts of 32 are encoded as zero. */
23860 else if (value
== 32)
23862 newval
|= value
<< 6;
23863 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23866 case BFD_RELOC_VTABLE_INHERIT
:
23867 case BFD_RELOC_VTABLE_ENTRY
:
23871 case BFD_RELOC_ARM_MOVW
:
23872 case BFD_RELOC_ARM_MOVT
:
23873 case BFD_RELOC_ARM_THUMB_MOVW
:
23874 case BFD_RELOC_ARM_THUMB_MOVT
:
23875 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23877 /* REL format relocations are limited to a 16-bit addend. */
23878 if (!fixP
->fx_done
)
23880 if (value
< -0x8000 || value
> 0x7fff)
23881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23882 _("offset out of range"));
23884 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23885 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23890 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23891 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23893 newval
= get_thumb32_insn (buf
);
23894 newval
&= 0xfbf08f00;
23895 newval
|= (value
& 0xf000) << 4;
23896 newval
|= (value
& 0x0800) << 15;
23897 newval
|= (value
& 0x0700) << 4;
23898 newval
|= (value
& 0x00ff);
23899 put_thumb32_insn (buf
, newval
);
23903 newval
= md_chars_to_number (buf
, 4);
23904 newval
&= 0xfff0f000;
23905 newval
|= value
& 0x0fff;
23906 newval
|= (value
& 0xf000) << 4;
23907 md_number_to_chars (buf
, newval
, 4);
23912 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23913 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23914 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23915 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23916 gas_assert (!fixP
->fx_done
);
23919 bfd_boolean is_mov
;
23920 bfd_vma encoded_addend
= value
;
23922 /* Check that addend can be encoded in instruction. */
23923 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
23924 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23925 _("the offset 0x%08lX is not representable"),
23926 (unsigned long) encoded_addend
);
23928 /* Extract the instruction. */
23929 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
23930 is_mov
= (insn
& 0xf800) == 0x2000;
23935 if (!seg
->use_rela_p
)
23936 insn
|= encoded_addend
;
23942 /* Extract the instruction. */
23943 /* Encoding is the following
23948 /* The following conditions must be true :
23953 rd
= (insn
>> 4) & 0xf;
23955 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
23956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23957 _("Unable to process relocation for thumb opcode: %lx"),
23958 (unsigned long) insn
);
23960 /* Encode as ADD immediate8 thumb 1 code. */
23961 insn
= 0x3000 | (rd
<< 8);
23963 /* Place the encoded addend into the first 8 bits of the
23965 if (!seg
->use_rela_p
)
23966 insn
|= encoded_addend
;
23969 /* Update the instruction. */
23970 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
23974 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23975 case BFD_RELOC_ARM_ALU_PC_G0
:
23976 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23977 case BFD_RELOC_ARM_ALU_PC_G1
:
23978 case BFD_RELOC_ARM_ALU_PC_G2
:
23979 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23980 case BFD_RELOC_ARM_ALU_SB_G0
:
23981 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23982 case BFD_RELOC_ARM_ALU_SB_G1
:
23983 case BFD_RELOC_ARM_ALU_SB_G2
:
23984 gas_assert (!fixP
->fx_done
);
23985 if (!seg
->use_rela_p
)
23988 bfd_vma encoded_addend
;
23989 bfd_vma addend_abs
= abs (value
);
23991 /* Check that the absolute value of the addend can be
23992 expressed as an 8-bit constant plus a rotation. */
23993 encoded_addend
= encode_arm_immediate (addend_abs
);
23994 if (encoded_addend
== (unsigned int) FAIL
)
23995 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23996 _("the offset 0x%08lX is not representable"),
23997 (unsigned long) addend_abs
);
23999 /* Extract the instruction. */
24000 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24002 /* If the addend is positive, use an ADD instruction.
24003 Otherwise use a SUB. Take care not to destroy the S bit. */
24004 insn
&= 0xff1fffff;
24010 /* Place the encoded addend into the first 12 bits of the
24012 insn
&= 0xfffff000;
24013 insn
|= encoded_addend
;
24015 /* Update the instruction. */
24016 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24020 case BFD_RELOC_ARM_LDR_PC_G0
:
24021 case BFD_RELOC_ARM_LDR_PC_G1
:
24022 case BFD_RELOC_ARM_LDR_PC_G2
:
24023 case BFD_RELOC_ARM_LDR_SB_G0
:
24024 case BFD_RELOC_ARM_LDR_SB_G1
:
24025 case BFD_RELOC_ARM_LDR_SB_G2
:
24026 gas_assert (!fixP
->fx_done
);
24027 if (!seg
->use_rela_p
)
24030 bfd_vma addend_abs
= abs (value
);
24032 /* Check that the absolute value of the addend can be
24033 encoded in 12 bits. */
24034 if (addend_abs
>= 0x1000)
24035 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24036 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24037 (unsigned long) addend_abs
);
24039 /* Extract the instruction. */
24040 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24042 /* If the addend is negative, clear bit 23 of the instruction.
24043 Otherwise set it. */
24045 insn
&= ~(1 << 23);
24049 /* Place the absolute value of the addend into the first 12 bits
24050 of the instruction. */
24051 insn
&= 0xfffff000;
24052 insn
|= addend_abs
;
24054 /* Update the instruction. */
24055 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24059 case BFD_RELOC_ARM_LDRS_PC_G0
:
24060 case BFD_RELOC_ARM_LDRS_PC_G1
:
24061 case BFD_RELOC_ARM_LDRS_PC_G2
:
24062 case BFD_RELOC_ARM_LDRS_SB_G0
:
24063 case BFD_RELOC_ARM_LDRS_SB_G1
:
24064 case BFD_RELOC_ARM_LDRS_SB_G2
:
24065 gas_assert (!fixP
->fx_done
);
24066 if (!seg
->use_rela_p
)
24069 bfd_vma addend_abs
= abs (value
);
24071 /* Check that the absolute value of the addend can be
24072 encoded in 8 bits. */
24073 if (addend_abs
>= 0x100)
24074 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24075 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24076 (unsigned long) addend_abs
);
24078 /* Extract the instruction. */
24079 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24081 /* If the addend is negative, clear bit 23 of the instruction.
24082 Otherwise set it. */
24084 insn
&= ~(1 << 23);
24088 /* Place the first four bits of the absolute value of the addend
24089 into the first 4 bits of the instruction, and the remaining
24090 four into bits 8 .. 11. */
24091 insn
&= 0xfffff0f0;
24092 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24094 /* Update the instruction. */
24095 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24099 case BFD_RELOC_ARM_LDC_PC_G0
:
24100 case BFD_RELOC_ARM_LDC_PC_G1
:
24101 case BFD_RELOC_ARM_LDC_PC_G2
:
24102 case BFD_RELOC_ARM_LDC_SB_G0
:
24103 case BFD_RELOC_ARM_LDC_SB_G1
:
24104 case BFD_RELOC_ARM_LDC_SB_G2
:
24105 gas_assert (!fixP
->fx_done
);
24106 if (!seg
->use_rela_p
)
24109 bfd_vma addend_abs
= abs (value
);
24111 /* Check that the absolute value of the addend is a multiple of
24112 four and, when divided by four, fits in 8 bits. */
24113 if (addend_abs
& 0x3)
24114 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24115 _("bad offset 0x%08lX (must be word-aligned)"),
24116 (unsigned long) addend_abs
);
24118 if ((addend_abs
>> 2) > 0xff)
24119 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24120 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24121 (unsigned long) addend_abs
);
24123 /* Extract the instruction. */
24124 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24126 /* If the addend is negative, clear bit 23 of the instruction.
24127 Otherwise set it. */
24129 insn
&= ~(1 << 23);
24133 /* Place the addend (divided by four) into the first eight
24134 bits of the instruction. */
24135 insn
&= 0xfffffff0;
24136 insn
|= addend_abs
>> 2;
24138 /* Update the instruction. */
24139 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24143 case BFD_RELOC_ARM_V4BX
:
24144 /* This will need to go in the object file. */
24148 case BFD_RELOC_UNUSED
:
24150 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24151 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24155 /* Translate internal representation of relocation info to BFD target
24159 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24162 bfd_reloc_code_real_type code
;
24164 reloc
= XNEW (arelent
);
24166 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24167 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24168 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24170 if (fixp
->fx_pcrel
)
24172 if (section
->use_rela_p
)
24173 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24175 fixp
->fx_offset
= reloc
->address
;
24177 reloc
->addend
= fixp
->fx_offset
;
24179 switch (fixp
->fx_r_type
)
24182 if (fixp
->fx_pcrel
)
24184 code
= BFD_RELOC_8_PCREL
;
24187 /* Fall through. */
24190 if (fixp
->fx_pcrel
)
24192 code
= BFD_RELOC_16_PCREL
;
24195 /* Fall through. */
24198 if (fixp
->fx_pcrel
)
24200 code
= BFD_RELOC_32_PCREL
;
24203 /* Fall through. */
24205 case BFD_RELOC_ARM_MOVW
:
24206 if (fixp
->fx_pcrel
)
24208 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24211 /* Fall through. */
24213 case BFD_RELOC_ARM_MOVT
:
24214 if (fixp
->fx_pcrel
)
24216 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24219 /* Fall through. */
24221 case BFD_RELOC_ARM_THUMB_MOVW
:
24222 if (fixp
->fx_pcrel
)
24224 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24227 /* Fall through. */
24229 case BFD_RELOC_ARM_THUMB_MOVT
:
24230 if (fixp
->fx_pcrel
)
24232 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24235 /* Fall through. */
24237 case BFD_RELOC_NONE
:
24238 case BFD_RELOC_ARM_PCREL_BRANCH
:
24239 case BFD_RELOC_ARM_PCREL_BLX
:
24240 case BFD_RELOC_RVA
:
24241 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24242 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24243 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24244 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24245 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24246 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24247 case BFD_RELOC_VTABLE_ENTRY
:
24248 case BFD_RELOC_VTABLE_INHERIT
:
24250 case BFD_RELOC_32_SECREL
:
24252 code
= fixp
->fx_r_type
;
24255 case BFD_RELOC_THUMB_PCREL_BLX
:
24257 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24258 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24261 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24264 case BFD_RELOC_ARM_LITERAL
:
24265 case BFD_RELOC_ARM_HWLITERAL
:
24266 /* If this is called then the a literal has
24267 been referenced across a section boundary. */
24268 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24269 _("literal referenced across section boundary"));
24273 case BFD_RELOC_ARM_TLS_CALL
:
24274 case BFD_RELOC_ARM_THM_TLS_CALL
:
24275 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24276 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24277 case BFD_RELOC_ARM_GOT32
:
24278 case BFD_RELOC_ARM_GOTOFF
:
24279 case BFD_RELOC_ARM_GOT_PREL
:
24280 case BFD_RELOC_ARM_PLT32
:
24281 case BFD_RELOC_ARM_TARGET1
:
24282 case BFD_RELOC_ARM_ROSEGREL32
:
24283 case BFD_RELOC_ARM_SBREL32
:
24284 case BFD_RELOC_ARM_PREL31
:
24285 case BFD_RELOC_ARM_TARGET2
:
24286 case BFD_RELOC_ARM_TLS_LDO32
:
24287 case BFD_RELOC_ARM_PCREL_CALL
:
24288 case BFD_RELOC_ARM_PCREL_JUMP
:
24289 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24290 case BFD_RELOC_ARM_ALU_PC_G0
:
24291 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24292 case BFD_RELOC_ARM_ALU_PC_G1
:
24293 case BFD_RELOC_ARM_ALU_PC_G2
:
24294 case BFD_RELOC_ARM_LDR_PC_G0
:
24295 case BFD_RELOC_ARM_LDR_PC_G1
:
24296 case BFD_RELOC_ARM_LDR_PC_G2
:
24297 case BFD_RELOC_ARM_LDRS_PC_G0
:
24298 case BFD_RELOC_ARM_LDRS_PC_G1
:
24299 case BFD_RELOC_ARM_LDRS_PC_G2
:
24300 case BFD_RELOC_ARM_LDC_PC_G0
:
24301 case BFD_RELOC_ARM_LDC_PC_G1
:
24302 case BFD_RELOC_ARM_LDC_PC_G2
:
24303 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24304 case BFD_RELOC_ARM_ALU_SB_G0
:
24305 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24306 case BFD_RELOC_ARM_ALU_SB_G1
:
24307 case BFD_RELOC_ARM_ALU_SB_G2
:
24308 case BFD_RELOC_ARM_LDR_SB_G0
:
24309 case BFD_RELOC_ARM_LDR_SB_G1
:
24310 case BFD_RELOC_ARM_LDR_SB_G2
:
24311 case BFD_RELOC_ARM_LDRS_SB_G0
:
24312 case BFD_RELOC_ARM_LDRS_SB_G1
:
24313 case BFD_RELOC_ARM_LDRS_SB_G2
:
24314 case BFD_RELOC_ARM_LDC_SB_G0
:
24315 case BFD_RELOC_ARM_LDC_SB_G1
:
24316 case BFD_RELOC_ARM_LDC_SB_G2
:
24317 case BFD_RELOC_ARM_V4BX
:
24318 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24319 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24320 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24321 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24322 code
= fixp
->fx_r_type
;
24325 case BFD_RELOC_ARM_TLS_GOTDESC
:
24326 case BFD_RELOC_ARM_TLS_GD32
:
24327 case BFD_RELOC_ARM_TLS_LE32
:
24328 case BFD_RELOC_ARM_TLS_IE32
:
24329 case BFD_RELOC_ARM_TLS_LDM32
:
24330 /* BFD will include the symbol's address in the addend.
24331 But we don't want that, so subtract it out again here. */
24332 if (!S_IS_COMMON (fixp
->fx_addsy
))
24333 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24334 code
= fixp
->fx_r_type
;
24338 case BFD_RELOC_ARM_IMMEDIATE
:
24339 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24340 _("internal relocation (type: IMMEDIATE) not fixed up"));
24343 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24344 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24345 _("ADRL used for a symbol not defined in the same file"));
24348 case BFD_RELOC_ARM_OFFSET_IMM
:
24349 if (section
->use_rela_p
)
24351 code
= fixp
->fx_r_type
;
24355 if (fixp
->fx_addsy
!= NULL
24356 && !S_IS_DEFINED (fixp
->fx_addsy
)
24357 && S_IS_LOCAL (fixp
->fx_addsy
))
24359 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24360 _("undefined local label `%s'"),
24361 S_GET_NAME (fixp
->fx_addsy
));
24365 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24366 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24373 switch (fixp
->fx_r_type
)
24375 case BFD_RELOC_NONE
: type
= "NONE"; break;
24376 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24377 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24378 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24379 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24380 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24381 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24382 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24383 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24384 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24385 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24386 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24387 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24388 default: type
= _("<unknown>"); break;
24390 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24391 _("cannot represent %s relocation in this object file format"),
24398 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24400 && fixp
->fx_addsy
== GOT_symbol
)
24402 code
= BFD_RELOC_ARM_GOTPC
;
24403 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24407 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24409 if (reloc
->howto
== NULL
)
24411 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24412 _("cannot represent %s relocation in this object file format"),
24413 bfd_get_reloc_code_name (code
));
24417 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24418 vtable entry to be used in the relocation's section offset. */
24419 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24420 reloc
->address
= fixp
->fx_offset
;
24425 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24428 cons_fix_new_arm (fragS
* frag
,
24432 bfd_reloc_code_real_type reloc
)
24437 FIXME: @@ Should look at CPU word size. */
24441 reloc
= BFD_RELOC_8
;
24444 reloc
= BFD_RELOC_16
;
24448 reloc
= BFD_RELOC_32
;
24451 reloc
= BFD_RELOC_64
;
24456 if (exp
->X_op
== O_secrel
)
24458 exp
->X_op
= O_symbol
;
24459 reloc
= BFD_RELOC_32_SECREL
;
24463 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24466 #if defined (OBJ_COFF)
24468 arm_validate_fix (fixS
* fixP
)
24470 /* If the destination of the branch is a defined symbol which does not have
24471 the THUMB_FUNC attribute, then we must be calling a function which has
24472 the (interfacearm) attribute. We look for the Thumb entry point to that
24473 function and change the branch to refer to that function instead. */
24474 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24475 && fixP
->fx_addsy
!= NULL
24476 && S_IS_DEFINED (fixP
->fx_addsy
)
24477 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24479 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24486 arm_force_relocation (struct fix
* fixp
)
24488 #if defined (OBJ_COFF) && defined (TE_PE)
24489 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24493 /* In case we have a call or a branch to a function in ARM ISA mode from
24494 a thumb function or vice-versa force the relocation. These relocations
24495 are cleared off for some cores that might have blx and simple transformations
24499 switch (fixp
->fx_r_type
)
24501 case BFD_RELOC_ARM_PCREL_JUMP
:
24502 case BFD_RELOC_ARM_PCREL_CALL
:
24503 case BFD_RELOC_THUMB_PCREL_BLX
:
24504 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24508 case BFD_RELOC_ARM_PCREL_BLX
:
24509 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24510 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24511 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24512 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24521 /* Resolve these relocations even if the symbol is extern or weak.
24522 Technically this is probably wrong due to symbol preemption.
24523 In practice these relocations do not have enough range to be useful
24524 at dynamic link time, and some code (e.g. in the Linux kernel)
24525 expects these references to be resolved. */
24526 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24527 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24528 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24529 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24530 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24531 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24532 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24533 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24534 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24535 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24536 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24537 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24538 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24539 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24542 /* Always leave these relocations for the linker. */
24543 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24544 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24545 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24548 /* Always generate relocations against function symbols. */
24549 if (fixp
->fx_r_type
== BFD_RELOC_32
24551 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24554 return generic_force_reloc (fixp
);
24557 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24558 /* Relocations against function names must be left unadjusted,
24559 so that the linker can use this information to generate interworking
24560 stubs. The MIPS version of this function
24561 also prevents relocations that are mips-16 specific, but I do not
24562 know why it does this.
24565 There is one other problem that ought to be addressed here, but
24566 which currently is not: Taking the address of a label (rather
24567 than a function) and then later jumping to that address. Such
24568 addresses also ought to have their bottom bit set (assuming that
24569 they reside in Thumb code), but at the moment they will not. */
24572 arm_fix_adjustable (fixS
* fixP
)
24574 if (fixP
->fx_addsy
== NULL
)
24577 /* Preserve relocations against symbols with function type. */
24578 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24581 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24582 && fixP
->fx_subsy
== NULL
)
24585 /* We need the symbol name for the VTABLE entries. */
24586 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24587 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24590 /* Don't allow symbols to be discarded on GOT related relocs. */
24591 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24592 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24593 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24594 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24595 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24596 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24597 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24598 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24599 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24600 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24601 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24602 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24603 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24604 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24607 /* Similarly for group relocations. */
24608 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24609 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24610 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24613 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24614 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24615 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24616 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24617 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24618 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24619 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24620 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24621 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24624 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24625 offsets, so keep these symbols. */
24626 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24627 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24632 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24636 elf32_arm_target_format (void)
24639 return (target_big_endian
24640 ? "elf32-bigarm-symbian"
24641 : "elf32-littlearm-symbian");
24642 #elif defined (TE_VXWORKS)
24643 return (target_big_endian
24644 ? "elf32-bigarm-vxworks"
24645 : "elf32-littlearm-vxworks");
24646 #elif defined (TE_NACL)
24647 return (target_big_endian
24648 ? "elf32-bigarm-nacl"
24649 : "elf32-littlearm-nacl");
24651 if (target_big_endian
)
24652 return "elf32-bigarm";
24654 return "elf32-littlearm";
24659 armelf_frob_symbol (symbolS
* symp
,
24662 elf_frob_symbol (symp
, puntp
);
24666 /* MD interface: Finalization. */
24671 literal_pool
* pool
;
24673 /* Ensure that all the IT blocks are properly closed. */
24674 check_it_blocks_finished ();
24676 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24678 /* Put it at the end of the relevant section. */
24679 subseg_set (pool
->section
, pool
->sub_section
);
24681 arm_elf_change_section ();
24688 /* Remove any excess mapping symbols generated for alignment frags in
24689 SEC. We may have created a mapping symbol before a zero byte
24690 alignment; remove it if there's a mapping symbol after the
24693 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24694 void *dummy ATTRIBUTE_UNUSED
)
24696 segment_info_type
*seginfo
= seg_info (sec
);
24699 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24702 for (fragp
= seginfo
->frchainP
->frch_root
;
24704 fragp
= fragp
->fr_next
)
24706 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24707 fragS
*next
= fragp
->fr_next
;
24709 /* Variable-sized frags have been converted to fixed size by
24710 this point. But if this was variable-sized to start with,
24711 there will be a fixed-size frag after it. So don't handle
24713 if (sym
== NULL
|| next
== NULL
)
24716 if (S_GET_VALUE (sym
) < next
->fr_address
)
24717 /* Not at the end of this frag. */
24719 know (S_GET_VALUE (sym
) == next
->fr_address
);
24723 if (next
->tc_frag_data
.first_map
!= NULL
)
24725 /* Next frag starts with a mapping symbol. Discard this
24727 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24731 if (next
->fr_next
== NULL
)
24733 /* This mapping symbol is at the end of the section. Discard
24735 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24736 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24740 /* As long as we have empty frags without any mapping symbols,
24742 /* If the next frag is non-empty and does not start with a
24743 mapping symbol, then this mapping symbol is required. */
24744 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24747 next
= next
->fr_next
;
24749 while (next
!= NULL
);
24754 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24758 arm_adjust_symtab (void)
24763 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24765 if (ARM_IS_THUMB (sym
))
24767 if (THUMB_IS_FUNC (sym
))
24769 /* Mark the symbol as a Thumb function. */
24770 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24771 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24772 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24774 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24775 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24777 as_bad (_("%s: unexpected function type: %d"),
24778 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24780 else switch (S_GET_STORAGE_CLASS (sym
))
24783 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24786 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24789 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24797 if (ARM_IS_INTERWORK (sym
))
24798 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24805 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24807 if (ARM_IS_THUMB (sym
))
24809 elf_symbol_type
* elf_sym
;
24811 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24812 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24814 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24815 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24817 /* If it's a .thumb_func, declare it as so,
24818 otherwise tag label as .code 16. */
24819 if (THUMB_IS_FUNC (sym
))
24820 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
24821 ST_BRANCH_TO_THUMB
);
24822 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24823 elf_sym
->internal_elf_sym
.st_info
=
24824 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24829 /* Remove any overlapping mapping symbols generated by alignment frags. */
24830 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24831 /* Now do generic ELF adjustments. */
24832 elf_adjust_symtab ();
24836 /* MD interface: Initialization. */
24839 set_constant_flonums (void)
24843 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24844 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24848 /* Auto-select Thumb mode if it's the only available instruction set for the
24849 given architecture. */
24852 autoselect_thumb_from_cpu_variant (void)
24854 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24855 opcode_select (16);
24864 if ( (arm_ops_hsh
= hash_new ()) == NULL
24865 || (arm_cond_hsh
= hash_new ()) == NULL
24866 || (arm_shift_hsh
= hash_new ()) == NULL
24867 || (arm_psr_hsh
= hash_new ()) == NULL
24868 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24869 || (arm_reg_hsh
= hash_new ()) == NULL
24870 || (arm_reloc_hsh
= hash_new ()) == NULL
24871 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24872 as_fatal (_("virtual memory exhausted"));
24874 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24875 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24876 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24877 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24878 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24879 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24880 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24881 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24882 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24883 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24884 (void *) (v7m_psrs
+ i
));
24885 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24886 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24888 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24890 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24891 (void *) (barrier_opt_names
+ i
));
24893 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24895 struct reloc_entry
* entry
= reloc_names
+ i
;
24897 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24898 /* This makes encode_branch() use the EABI versions of this relocation. */
24899 entry
->reloc
= BFD_RELOC_UNUSED
;
24901 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24905 set_constant_flonums ();
24907 /* Set the cpu variant based on the command-line options. We prefer
24908 -mcpu= over -march= if both are set (as for GCC); and we prefer
24909 -mfpu= over any other way of setting the floating point unit.
24910 Use of legacy options with new options are faulted. */
24913 if (mcpu_cpu_opt
|| march_cpu_opt
)
24914 as_bad (_("use of old and new-style options to set CPU type"));
24916 mcpu_cpu_opt
= legacy_cpu
;
24918 else if (!mcpu_cpu_opt
)
24919 mcpu_cpu_opt
= march_cpu_opt
;
24924 as_bad (_("use of old and new-style options to set FPU type"));
24926 mfpu_opt
= legacy_fpu
;
24928 else if (!mfpu_opt
)
24930 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24931 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24932 /* Some environments specify a default FPU. If they don't, infer it
24933 from the processor. */
24935 mfpu_opt
= mcpu_fpu_opt
;
24937 mfpu_opt
= march_fpu_opt
;
24939 mfpu_opt
= &fpu_default
;
24945 if (mcpu_cpu_opt
!= NULL
)
24946 mfpu_opt
= &fpu_default
;
24947 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24948 mfpu_opt
= &fpu_arch_vfp_v2
;
24950 mfpu_opt
= &fpu_arch_fpa
;
24956 mcpu_cpu_opt
= &cpu_default
;
24957 selected_cpu
= cpu_default
;
24959 else if (no_cpu_selected ())
24960 selected_cpu
= cpu_default
;
24963 selected_cpu
= *mcpu_cpu_opt
;
24965 mcpu_cpu_opt
= &arm_arch_any
;
24968 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24970 autoselect_thumb_from_cpu_variant ();
24972 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24974 #if defined OBJ_COFF || defined OBJ_ELF
24976 unsigned int flags
= 0;
24978 #if defined OBJ_ELF
24979 flags
= meabi_flags
;
24981 switch (meabi_flags
)
24983 case EF_ARM_EABI_UNKNOWN
:
24985 /* Set the flags in the private structure. */
24986 if (uses_apcs_26
) flags
|= F_APCS26
;
24987 if (support_interwork
) flags
|= F_INTERWORK
;
24988 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24989 if (pic_code
) flags
|= F_PIC
;
24990 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24991 flags
|= F_SOFT_FLOAT
;
24993 switch (mfloat_abi_opt
)
24995 case ARM_FLOAT_ABI_SOFT
:
24996 case ARM_FLOAT_ABI_SOFTFP
:
24997 flags
|= F_SOFT_FLOAT
;
25000 case ARM_FLOAT_ABI_HARD
:
25001 if (flags
& F_SOFT_FLOAT
)
25002 as_bad (_("hard-float conflicts with specified fpu"));
25006 /* Using pure-endian doubles (even if soft-float). */
25007 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25008 flags
|= F_VFP_FLOAT
;
25010 #if defined OBJ_ELF
25011 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25012 flags
|= EF_ARM_MAVERICK_FLOAT
;
25015 case EF_ARM_EABI_VER4
:
25016 case EF_ARM_EABI_VER5
:
25017 /* No additional flags to set. */
25024 bfd_set_private_flags (stdoutput
, flags
);
25026 /* We have run out flags in the COFF header to encode the
25027 status of ATPCS support, so instead we create a dummy,
25028 empty, debug section called .arm.atpcs. */
25033 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25037 bfd_set_section_flags
25038 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25039 bfd_set_section_size (stdoutput
, sec
, 0);
25040 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25046 /* Record the CPU type as well. */
25047 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25048 mach
= bfd_mach_arm_iWMMXt2
;
25049 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25050 mach
= bfd_mach_arm_iWMMXt
;
25051 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25052 mach
= bfd_mach_arm_XScale
;
25053 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25054 mach
= bfd_mach_arm_ep9312
;
25055 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25056 mach
= bfd_mach_arm_5TE
;
25057 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25059 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25060 mach
= bfd_mach_arm_5T
;
25062 mach
= bfd_mach_arm_5
;
25064 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25066 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25067 mach
= bfd_mach_arm_4T
;
25069 mach
= bfd_mach_arm_4
;
25071 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25072 mach
= bfd_mach_arm_3M
;
25073 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25074 mach
= bfd_mach_arm_3
;
25075 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25076 mach
= bfd_mach_arm_2a
;
25077 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25078 mach
= bfd_mach_arm_2
;
25080 mach
= bfd_mach_arm_unknown
;
25082 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25085 /* Command line processing. */
25088 Invocation line includes a switch not recognized by the base assembler.
25089 See if it's a processor-specific option.
25091 This routine is somewhat complicated by the need for backwards
25092 compatibility (since older releases of gcc can't be changed).
25093 The new options try to make the interface as compatible as
25096 New options (supported) are:
25098 -mcpu=<cpu name> Assemble for selected processor
25099 -march=<architecture name> Assemble for selected architecture
25100 -mfpu=<fpu architecture> Assemble for selected FPU.
25101 -EB/-mbig-endian Big-endian
25102 -EL/-mlittle-endian Little-endian
25103 -k Generate PIC code
25104 -mthumb Start in Thumb mode
25105 -mthumb-interwork Code supports ARM/Thumb interworking
25107 -m[no-]warn-deprecated Warn about deprecated features
25108 -m[no-]warn-syms Warn when symbols match instructions
25110 For now we will also provide support for:
25112 -mapcs-32 32-bit Program counter
25113 -mapcs-26 26-bit Program counter
25114 -macps-float Floats passed in FP registers
25115 -mapcs-reentrant Reentrant code
25117 (sometime these will probably be replaced with -mapcs=<list of options>
25118 and -matpcs=<list of options>)
25120 The remaining options are only supported for back-wards compatibility.
25121 Cpu variants, the arm part is optional:
25122 -m[arm]1 Currently not supported.
25123 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25124 -m[arm]3 Arm 3 processor
25125 -m[arm]6[xx], Arm 6 processors
25126 -m[arm]7[xx][t][[d]m] Arm 7 processors
25127 -m[arm]8[10] Arm 8 processors
25128 -m[arm]9[20][tdmi] Arm 9 processors
25129 -mstrongarm[110[0]] StrongARM processors
25130 -mxscale XScale processors
25131 -m[arm]v[2345[t[e]]] Arm architectures
25132 -mall All (except the ARM1)
25134 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25135 -mfpe-old (No float load/store multiples)
25136 -mvfpxd VFP Single precision
25138 -mno-fpu Disable all floating point instructions
25140 The following CPU names are recognized:
25141 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25142 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25143 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25144 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25145 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25146 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25147 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25151 const char * md_shortopts
= "m:k";
25153 #ifdef ARM_BI_ENDIAN
25154 #define OPTION_EB (OPTION_MD_BASE + 0)
25155 #define OPTION_EL (OPTION_MD_BASE + 1)
25157 #if TARGET_BYTES_BIG_ENDIAN
25158 #define OPTION_EB (OPTION_MD_BASE + 0)
25160 #define OPTION_EL (OPTION_MD_BASE + 1)
25163 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25165 struct option md_longopts
[] =
25168 {"EB", no_argument
, NULL
, OPTION_EB
},
25171 {"EL", no_argument
, NULL
, OPTION_EL
},
25173 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25174 {NULL
, no_argument
, NULL
, 0}
25178 size_t md_longopts_size
= sizeof (md_longopts
);
25180 struct arm_option_table
25182 const char *option
; /* Option name to match. */
25183 const char *help
; /* Help information. */
25184 int *var
; /* Variable to change. */
25185 int value
; /* What to change it to. */
25186 const char *deprecated
; /* If non-null, print this message. */
25189 struct arm_option_table arm_opts
[] =
25191 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25192 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25193 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25194 &support_interwork
, 1, NULL
},
25195 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25196 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25197 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25199 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25200 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25201 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25202 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25205 /* These are recognized by the assembler, but have no affect on code. */
25206 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25207 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25209 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25210 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25211 &warn_on_deprecated
, 0, NULL
},
25212 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25213 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25214 {NULL
, NULL
, NULL
, 0, NULL
}
25217 struct arm_legacy_option_table
25219 const char *option
; /* Option name to match. */
25220 const arm_feature_set
**var
; /* Variable to change. */
25221 const arm_feature_set value
; /* What to change it to. */
25222 const char *deprecated
; /* If non-null, print this message. */
25225 const struct arm_legacy_option_table arm_legacy_opts
[] =
25227 /* DON'T add any new processors to this list -- we want the whole list
25228 to go away... Add them to the processors table instead. */
25229 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25230 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25231 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25232 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25233 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25234 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25235 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25236 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25237 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25238 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25239 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25240 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25241 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25242 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25243 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25244 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25245 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25246 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25247 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25248 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25249 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25250 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25251 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25252 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25253 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25254 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25255 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25256 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25257 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25258 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25259 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25260 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25261 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25262 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25263 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25264 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25265 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25266 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25267 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25268 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25269 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25270 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25271 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25272 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25273 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25274 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25275 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25276 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25277 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25278 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25279 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25280 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25281 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25282 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25283 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25284 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25285 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25286 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25287 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25288 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25289 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25290 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25291 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25292 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25293 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25294 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25295 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25296 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25297 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25298 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25299 N_("use -mcpu=strongarm110")},
25300 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25301 N_("use -mcpu=strongarm1100")},
25302 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25303 N_("use -mcpu=strongarm1110")},
25304 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25305 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25306 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25308 /* Architecture variants -- don't add any more to this list either. */
25309 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25310 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25311 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25312 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25313 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25314 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25315 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25316 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25317 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25318 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25319 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25320 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25321 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25322 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25323 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25324 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25325 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25326 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25328 /* Floating point variants -- don't add any more to this list either. */
25329 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25330 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25331 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25332 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25333 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25335 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25338 struct arm_cpu_option_table
25342 const arm_feature_set value
;
25343 /* For some CPUs we assume an FPU unless the user explicitly sets
25345 const arm_feature_set default_fpu
;
25346 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25348 const char *canonical_name
;
25351 /* This list should, at a minimum, contain all the cpu names
25352 recognized by GCC. */
25353 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25354 static const struct arm_cpu_option_table arm_cpus
[] =
25356 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25357 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25358 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25359 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25360 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25361 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25362 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25363 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25364 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25365 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25366 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25367 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25368 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25369 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25370 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25371 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25372 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25373 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25374 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25375 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25376 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25377 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25378 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25379 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25380 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25381 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25382 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25383 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25384 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25385 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25386 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25387 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25388 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25389 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25390 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25391 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25392 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25393 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25394 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25395 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25396 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25397 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25398 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25399 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25400 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25401 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25402 /* For V5 or later processors we default to using VFP; but the user
25403 should really set the FPU type explicitly. */
25404 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25405 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25406 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25407 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25408 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25409 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25410 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25411 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25412 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25413 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25414 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25415 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25416 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25417 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25418 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25419 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25420 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25421 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25422 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25423 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25425 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25426 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25427 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25428 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25429 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25430 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25431 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25432 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25433 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25435 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25436 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25437 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25438 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25439 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25440 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25441 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25442 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25443 FPU_NONE
, "Cortex-A5"),
25444 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25446 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25447 ARM_FEATURE_COPROC (FPU_VFP_V3
25448 | FPU_NEON_EXT_V1
),
25450 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25451 ARM_FEATURE_COPROC (FPU_VFP_V3
25452 | FPU_NEON_EXT_V1
),
25454 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25456 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25458 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25460 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25462 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25464 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25466 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25468 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25470 ARM_CPU_OPT ("cortex-a73", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25472 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25473 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25475 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25476 FPU_NONE
, "Cortex-R5"),
25477 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25478 FPU_ARCH_VFP_V3D16
,
25480 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV
,
25481 FPU_ARCH_VFP_V3D16
,
25483 ARM_CPU_OPT ("cortex-m33", ARM_ARCH_V8M_MAIN_DSP
,
25484 FPU_NONE
, "Cortex-M33"),
25485 ARM_CPU_OPT ("cortex-m23", ARM_ARCH_V8M_BASE
,
25486 FPU_NONE
, "Cortex-M23"),
25487 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25488 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25489 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25490 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25491 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25492 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25493 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25496 ARM_CPU_OPT ("falkor", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25499 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25503 /* ??? XSCALE is really an architecture. */
25504 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25505 /* ??? iwmmxt is not a processor. */
25506 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25507 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25508 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25510 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25511 FPU_ARCH_MAVERICK
, "ARM920T"),
25512 /* Marvell processors. */
25513 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25515 ARM_EXT2_V6T2_V8M
),
25516 FPU_ARCH_VFP_V3D16
, NULL
),
25517 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25519 ARM_EXT2_V6T2_V8M
),
25520 FPU_ARCH_NEON_VFP_V4
, NULL
),
25521 /* APM X-Gene family. */
25522 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25524 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25527 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25531 struct arm_arch_option_table
25535 const arm_feature_set value
;
25536 const arm_feature_set default_fpu
;
25539 /* This list should, at a minimum, contain all the architecture names
25540 recognized by GCC. */
25541 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25542 static const struct arm_arch_option_table arm_archs
[] =
25544 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25545 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25546 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25547 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25548 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25549 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25550 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25551 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25552 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25553 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25554 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25555 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25556 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25557 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25558 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25559 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25560 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25561 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25562 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25563 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25564 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25565 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25566 kept to preserve existing behaviour. */
25567 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25568 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25569 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25570 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25571 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25572 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25573 kept to preserve existing behaviour. */
25574 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25575 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25576 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25577 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25578 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25579 /* The official spelling of the ARMv7 profile variants is the dashed form.
25580 Accept the non-dashed form for compatibility with old toolchains. */
25581 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25582 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25583 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25584 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25585 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25586 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25587 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25588 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25589 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25590 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25591 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25592 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25593 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25594 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
25595 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25596 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25597 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25598 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25600 #undef ARM_ARCH_OPT
25602 /* ISA extensions in the co-processor and main instruction set space. */
25603 struct arm_option_extension_value_table
25607 const arm_feature_set merge_value
;
25608 const arm_feature_set clear_value
;
25609 /* List of architectures for which an extension is available. ARM_ARCH_NONE
25610 indicates that an extension is available for all architectures while
25611 ARM_ANY marks an empty entry. */
25612 const arm_feature_set allowed_archs
[2];
25615 /* The following table must be in alphabetical order with a NULL last entry.
25617 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
25618 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
25619 static const struct arm_option_extension_value_table arm_extensions
[] =
25621 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25622 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25623 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25624 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25625 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25626 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25627 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25628 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
25629 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25630 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25631 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25632 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25634 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25635 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25636 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25637 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25638 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25639 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
25640 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25641 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
25642 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25643 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
25644 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25645 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25646 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25647 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25648 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25649 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25650 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25651 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25652 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25653 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25654 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
25655 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
25656 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25657 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25658 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25659 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25660 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25661 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25662 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
25663 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25664 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25665 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25666 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25667 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25669 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25670 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25671 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25672 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
25673 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
25677 /* ISA floating-point and Advanced SIMD extensions. */
25678 struct arm_option_fpu_value_table
25681 const arm_feature_set value
;
25684 /* This list should, at a minimum, contain all the fpu names
25685 recognized by GCC. */
25686 static const struct arm_option_fpu_value_table arm_fpus
[] =
25688 {"softfpa", FPU_NONE
},
25689 {"fpe", FPU_ARCH_FPE
},
25690 {"fpe2", FPU_ARCH_FPE
},
25691 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25692 {"fpa", FPU_ARCH_FPA
},
25693 {"fpa10", FPU_ARCH_FPA
},
25694 {"fpa11", FPU_ARCH_FPA
},
25695 {"arm7500fe", FPU_ARCH_FPA
},
25696 {"softvfp", FPU_ARCH_VFP
},
25697 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25698 {"vfp", FPU_ARCH_VFP_V2
},
25699 {"vfp9", FPU_ARCH_VFP_V2
},
25700 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25701 {"vfp10", FPU_ARCH_VFP_V2
},
25702 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25703 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25704 {"vfpv2", FPU_ARCH_VFP_V2
},
25705 {"vfpv3", FPU_ARCH_VFP_V3
},
25706 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25707 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25708 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25709 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25710 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25711 {"arm1020t", FPU_ARCH_VFP_V1
},
25712 {"arm1020e", FPU_ARCH_VFP_V2
},
25713 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25714 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25715 {"maverick", FPU_ARCH_MAVERICK
},
25716 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25717 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25718 {"vfpv4", FPU_ARCH_VFP_V4
},
25719 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25720 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25721 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25722 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25723 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25724 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25725 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25726 {"crypto-neon-fp-armv8",
25727 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25728 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25729 {"crypto-neon-fp-armv8.1",
25730 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25731 {NULL
, ARM_ARCH_NONE
}
25734 struct arm_option_value_table
25740 static const struct arm_option_value_table arm_float_abis
[] =
25742 {"hard", ARM_FLOAT_ABI_HARD
},
25743 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25744 {"soft", ARM_FLOAT_ABI_SOFT
},
25749 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25750 static const struct arm_option_value_table arm_eabis
[] =
25752 {"gnu", EF_ARM_EABI_UNKNOWN
},
25753 {"4", EF_ARM_EABI_VER4
},
25754 {"5", EF_ARM_EABI_VER5
},
25759 struct arm_long_option_table
25761 const char * option
; /* Substring to match. */
25762 const char * help
; /* Help information. */
25763 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
25764 const char * deprecated
; /* If non-null, print this message. */
25768 arm_parse_extension (const char *str
, const arm_feature_set
**opt_p
)
25770 arm_feature_set
*ext_set
= XNEW (arm_feature_set
);
25772 /* We insist on extensions being specified in alphabetical order, and with
25773 extensions being added before being removed. We achieve this by having
25774 the global ARM_EXTENSIONS table in alphabetical order, and using the
25775 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25776 or removing it (0) and only allowing it to change in the order
25778 const struct arm_option_extension_value_table
* opt
= NULL
;
25779 const arm_feature_set arm_any
= ARM_ANY
;
25780 int adding_value
= -1;
25782 /* Copy the feature set, so that we can modify it. */
25783 *ext_set
= **opt_p
;
25786 while (str
!= NULL
&& *str
!= 0)
25793 as_bad (_("invalid architectural extension"));
25798 ext
= strchr (str
, '+');
25803 len
= strlen (str
);
25805 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25807 if (adding_value
!= 0)
25810 opt
= arm_extensions
;
25818 if (adding_value
== -1)
25821 opt
= arm_extensions
;
25823 else if (adding_value
!= 1)
25825 as_bad (_("must specify extensions to add before specifying "
25826 "those to remove"));
25833 as_bad (_("missing architectural extension"));
25837 gas_assert (adding_value
!= -1);
25838 gas_assert (opt
!= NULL
);
25840 /* Scan over the options table trying to find an exact match. */
25841 for (; opt
->name
!= NULL
; opt
++)
25842 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25844 int i
, nb_allowed_archs
=
25845 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
25846 /* Check we can apply the extension to this architecture. */
25847 for (i
= 0; i
< nb_allowed_archs
; i
++)
25850 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
25852 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *ext_set
))
25855 if (i
== nb_allowed_archs
)
25857 as_bad (_("extension does not apply to the base architecture"));
25861 /* Add or remove the extension. */
25863 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25865 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25870 if (opt
->name
== NULL
)
25872 /* Did we fail to find an extension because it wasn't specified in
25873 alphabetical order, or because it does not exist? */
25875 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25876 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25879 if (opt
->name
== NULL
)
25880 as_bad (_("unknown architectural extension `%s'"), str
);
25882 as_bad (_("architectural extensions must be specified in "
25883 "alphabetical order"));
25889 /* We should skip the extension we've just matched the next time
25901 arm_parse_cpu (const char *str
)
25903 const struct arm_cpu_option_table
*opt
;
25904 const char *ext
= strchr (str
, '+');
25910 len
= strlen (str
);
25914 as_bad (_("missing cpu name `%s'"), str
);
25918 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25919 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25921 mcpu_cpu_opt
= &opt
->value
;
25922 mcpu_fpu_opt
= &opt
->default_fpu
;
25923 if (opt
->canonical_name
)
25925 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25926 strcpy (selected_cpu_name
, opt
->canonical_name
);
25932 if (len
>= sizeof selected_cpu_name
)
25933 len
= (sizeof selected_cpu_name
) - 1;
25935 for (i
= 0; i
< len
; i
++)
25936 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25937 selected_cpu_name
[i
] = 0;
25941 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25946 as_bad (_("unknown cpu `%s'"), str
);
25951 arm_parse_arch (const char *str
)
25953 const struct arm_arch_option_table
*opt
;
25954 const char *ext
= strchr (str
, '+');
25960 len
= strlen (str
);
25964 as_bad (_("missing architecture name `%s'"), str
);
25968 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25969 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25971 march_cpu_opt
= &opt
->value
;
25972 march_fpu_opt
= &opt
->default_fpu
;
25973 strcpy (selected_cpu_name
, opt
->name
);
25976 return arm_parse_extension (ext
, &march_cpu_opt
);
25981 as_bad (_("unknown architecture `%s'\n"), str
);
25986 arm_parse_fpu (const char * str
)
25988 const struct arm_option_fpu_value_table
* opt
;
25990 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25991 if (streq (opt
->name
, str
))
25993 mfpu_opt
= &opt
->value
;
25997 as_bad (_("unknown floating point format `%s'\n"), str
);
26002 arm_parse_float_abi (const char * str
)
26004 const struct arm_option_value_table
* opt
;
26006 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26007 if (streq (opt
->name
, str
))
26009 mfloat_abi_opt
= opt
->value
;
26013 as_bad (_("unknown floating point abi `%s'\n"), str
);
26019 arm_parse_eabi (const char * str
)
26021 const struct arm_option_value_table
*opt
;
26023 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26024 if (streq (opt
->name
, str
))
26026 meabi_flags
= opt
->value
;
26029 as_bad (_("unknown EABI `%s'\n"), str
);
26035 arm_parse_it_mode (const char * str
)
26037 bfd_boolean ret
= TRUE
;
26039 if (streq ("arm", str
))
26040 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26041 else if (streq ("thumb", str
))
26042 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26043 else if (streq ("always", str
))
26044 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26045 else if (streq ("never", str
))
26046 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26049 as_bad (_("unknown implicit IT mode `%s', should be "\
26050 "arm, thumb, always, or never."), str
);
26058 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26060 codecomposer_syntax
= TRUE
;
26061 arm_comment_chars
[0] = ';';
26062 arm_line_separator_chars
[0] = 0;
26066 struct arm_long_option_table arm_long_opts
[] =
26068 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26069 arm_parse_cpu
, NULL
},
26070 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26071 arm_parse_arch
, NULL
},
26072 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26073 arm_parse_fpu
, NULL
},
26074 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26075 arm_parse_float_abi
, NULL
},
26077 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26078 arm_parse_eabi
, NULL
},
26080 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26081 arm_parse_it_mode
, NULL
},
26082 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26083 arm_ccs_mode
, NULL
},
26084 {NULL
, NULL
, 0, NULL
}
26088 md_parse_option (int c
, const char * arg
)
26090 struct arm_option_table
*opt
;
26091 const struct arm_legacy_option_table
*fopt
;
26092 struct arm_long_option_table
*lopt
;
26098 target_big_endian
= 1;
26104 target_big_endian
= 0;
26108 case OPTION_FIX_V4BX
:
26113 /* Listing option. Just ignore these, we don't support additional
26118 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26120 if (c
== opt
->option
[0]
26121 && ((arg
== NULL
&& opt
->option
[1] == 0)
26122 || streq (arg
, opt
->option
+ 1)))
26124 /* If the option is deprecated, tell the user. */
26125 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26126 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26127 arg
? arg
: "", _(opt
->deprecated
));
26129 if (opt
->var
!= NULL
)
26130 *opt
->var
= opt
->value
;
26136 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26138 if (c
== fopt
->option
[0]
26139 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26140 || streq (arg
, fopt
->option
+ 1)))
26142 /* If the option is deprecated, tell the user. */
26143 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26144 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26145 arg
? arg
: "", _(fopt
->deprecated
));
26147 if (fopt
->var
!= NULL
)
26148 *fopt
->var
= &fopt
->value
;
26154 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26156 /* These options are expected to have an argument. */
26157 if (c
== lopt
->option
[0]
26159 && strncmp (arg
, lopt
->option
+ 1,
26160 strlen (lopt
->option
+ 1)) == 0)
26162 /* If the option is deprecated, tell the user. */
26163 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26164 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26165 _(lopt
->deprecated
));
26167 /* Call the sup-option parser. */
26168 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26179 md_show_usage (FILE * fp
)
26181 struct arm_option_table
*opt
;
26182 struct arm_long_option_table
*lopt
;
26184 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26186 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26187 if (opt
->help
!= NULL
)
26188 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26190 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26191 if (lopt
->help
!= NULL
)
26192 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26196 -EB assemble code for a big-endian cpu\n"));
26201 -EL assemble code for a little-endian cpu\n"));
26205 --fix-v4bx Allow BX in ARMv4 code\n"));
26213 arm_feature_set flags
;
26214 } cpu_arch_ver_table
;
26216 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26217 must be sorted least features first but some reordering is needed, eg. for
26218 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26219 static const cpu_arch_ver_table cpu_arch_ver
[] =
26225 {4, ARM_ARCH_V5TE
},
26226 {5, ARM_ARCH_V5TEJ
},
26230 {11, ARM_ARCH_V6M
},
26231 {12, ARM_ARCH_V6SM
},
26232 {8, ARM_ARCH_V6T2
},
26233 {10, ARM_ARCH_V7VE
},
26234 {10, ARM_ARCH_V7R
},
26235 {10, ARM_ARCH_V7M
},
26236 {14, ARM_ARCH_V8A
},
26237 {16, ARM_ARCH_V8M_BASE
},
26238 {17, ARM_ARCH_V8M_MAIN
},
26242 /* Set an attribute if it has not already been set by the user. */
26244 aeabi_set_attribute_int (int tag
, int value
)
26247 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26248 || !attributes_set_explicitly
[tag
])
26249 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26253 aeabi_set_attribute_string (int tag
, const char *value
)
26256 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26257 || !attributes_set_explicitly
[tag
])
26258 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26261 /* Set the public EABI object attributes. */
26263 aeabi_set_public_attributes (void)
26268 int fp16_optional
= 0;
26269 arm_feature_set arm_arch
= ARM_ARCH_NONE
;
26270 arm_feature_set flags
;
26271 arm_feature_set tmp
;
26272 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26273 const cpu_arch_ver_table
*p
;
26275 /* Choose the architecture based on the capabilities of the requested cpu
26276 (if any) and/or the instructions actually used. */
26277 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26278 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26279 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26281 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26282 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26284 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26285 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26287 selected_cpu
= flags
;
26289 /* Allow the user to override the reported architecture. */
26292 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26293 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26296 /* We need to make sure that the attributes do not identify us as v6S-M
26297 when the only v6S-M feature in use is the Operating System Extensions. */
26298 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26299 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26300 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26304 for (p
= cpu_arch_ver
; p
->val
; p
++)
26306 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26309 arm_arch
= p
->flags
;
26310 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26314 /* The table lookup above finds the last architecture to contribute
26315 a new feature. Unfortunately, Tag13 is a subset of the union of
26316 v6T2 and v7-M, so it is never seen as contributing a new feature.
26317 We can not search for the last entry which is entirely used,
26318 because if no CPU is specified we build up only those flags
26319 actually used. Perhaps we should separate out the specified
26320 and implicit cases. Avoid taking this path for -march=all by
26321 checking for contradictory v7-A / v7-M features. */
26322 if (arch
== TAG_CPU_ARCH_V7
26323 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26324 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26325 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26327 arch
= TAG_CPU_ARCH_V7E_M
;
26328 arm_arch
= (arm_feature_set
) ARM_ARCH_V7EM
;
26331 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26332 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26334 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26335 arm_arch
= (arm_feature_set
) ARM_ARCH_V8M_MAIN
;
26338 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26339 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26340 ARMv8-M, -march=all must be detected as ARMv8-A. */
26341 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26342 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26344 arch
= TAG_CPU_ARCH_V8
;
26345 arm_arch
= (arm_feature_set
) ARM_ARCH_V8A
;
26348 /* Tag_CPU_name. */
26349 if (selected_cpu_name
[0])
26353 q
= selected_cpu_name
;
26354 if (strncmp (q
, "armv", 4) == 0)
26359 for (i
= 0; q
[i
]; i
++)
26360 q
[i
] = TOUPPER (q
[i
]);
26362 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26365 /* Tag_CPU_arch. */
26366 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26368 /* Tag_CPU_arch_profile. */
26369 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26370 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26371 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26372 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
)))
26374 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26376 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26381 if (profile
!= '\0')
26382 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26384 /* Tag_DSP_extension. */
26385 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_dsp
))
26387 arm_feature_set ext
;
26389 /* DSP instructions not in architecture. */
26390 ARM_CLEAR_FEATURE (ext
, flags
, arm_arch
);
26391 if (ARM_CPU_HAS_FEATURE (ext
, arm_ext_dsp
))
26392 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26395 /* Tag_ARM_ISA_use. */
26396 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26398 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26400 /* Tag_THUMB_ISA_use. */
26401 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26406 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26407 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26409 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26413 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26416 /* Tag_VFP_arch. */
26417 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26418 aeabi_set_attribute_int (Tag_VFP_arch
,
26419 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26421 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26422 aeabi_set_attribute_int (Tag_VFP_arch
,
26423 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26425 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26428 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26430 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26432 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26435 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26436 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26437 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26438 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26439 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26441 /* Tag_ABI_HardFP_use. */
26442 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26443 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26444 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26446 /* Tag_WMMX_arch. */
26447 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26448 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26449 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26450 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26452 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26453 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26454 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26455 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26456 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26457 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26459 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26461 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26465 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26470 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26471 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26472 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26476 We set Tag_DIV_use to two when integer divide instructions have been used
26477 in ARM state, or when Thumb integer divide instructions have been used,
26478 but we have no architecture profile set, nor have we any ARM instructions.
26480 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26481 by the base architecture.
26483 For new architectures we will have to check these tests. */
26484 gas_assert (arch
<= TAG_CPU_ARCH_V8
26485 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26486 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26487 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26488 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26489 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26490 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26491 || (profile
== '\0'
26492 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26493 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26494 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26496 /* Tag_MP_extension_use. */
26497 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26498 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26500 /* Tag Virtualization_use. */
26501 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26503 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26506 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26509 /* Add the default contents for the .ARM.attributes section. */
26513 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26516 aeabi_set_public_attributes ();
26518 #endif /* OBJ_ELF */
26521 /* Parse a .cpu directive. */
26524 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26526 const struct arm_cpu_option_table
*opt
;
26530 name
= input_line_pointer
;
26531 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26532 input_line_pointer
++;
26533 saved_char
= *input_line_pointer
;
26534 *input_line_pointer
= 0;
26536 /* Skip the first "all" entry. */
26537 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26538 if (streq (opt
->name
, name
))
26540 mcpu_cpu_opt
= &opt
->value
;
26541 selected_cpu
= opt
->value
;
26542 if (opt
->canonical_name
)
26543 strcpy (selected_cpu_name
, opt
->canonical_name
);
26547 for (i
= 0; opt
->name
[i
]; i
++)
26548 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26550 selected_cpu_name
[i
] = 0;
26552 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26553 *input_line_pointer
= saved_char
;
26554 demand_empty_rest_of_line ();
26557 as_bad (_("unknown cpu `%s'"), name
);
26558 *input_line_pointer
= saved_char
;
26559 ignore_rest_of_line ();
26563 /* Parse a .arch directive. */
26566 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26568 const struct arm_arch_option_table
*opt
;
26572 name
= input_line_pointer
;
26573 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26574 input_line_pointer
++;
26575 saved_char
= *input_line_pointer
;
26576 *input_line_pointer
= 0;
26578 /* Skip the first "all" entry. */
26579 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26580 if (streq (opt
->name
, name
))
26582 mcpu_cpu_opt
= &opt
->value
;
26583 selected_cpu
= opt
->value
;
26584 strcpy (selected_cpu_name
, opt
->name
);
26585 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26586 *input_line_pointer
= saved_char
;
26587 demand_empty_rest_of_line ();
26591 as_bad (_("unknown architecture `%s'\n"), name
);
26592 *input_line_pointer
= saved_char
;
26593 ignore_rest_of_line ();
26597 /* Parse a .object_arch directive. */
26600 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26602 const struct arm_arch_option_table
*opt
;
26606 name
= input_line_pointer
;
26607 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26608 input_line_pointer
++;
26609 saved_char
= *input_line_pointer
;
26610 *input_line_pointer
= 0;
26612 /* Skip the first "all" entry. */
26613 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26614 if (streq (opt
->name
, name
))
26616 object_arch
= &opt
->value
;
26617 *input_line_pointer
= saved_char
;
26618 demand_empty_rest_of_line ();
26622 as_bad (_("unknown architecture `%s'\n"), name
);
26623 *input_line_pointer
= saved_char
;
26624 ignore_rest_of_line ();
26627 /* Parse a .arch_extension directive. */
26630 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26632 const struct arm_option_extension_value_table
*opt
;
26633 const arm_feature_set arm_any
= ARM_ANY
;
26636 int adding_value
= 1;
26638 name
= input_line_pointer
;
26639 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26640 input_line_pointer
++;
26641 saved_char
= *input_line_pointer
;
26642 *input_line_pointer
= 0;
26644 if (strlen (name
) >= 2
26645 && strncmp (name
, "no", 2) == 0)
26651 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26652 if (streq (opt
->name
, name
))
26654 int i
, nb_allowed_archs
=
26655 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
26656 for (i
= 0; i
< nb_allowed_archs
; i
++)
26659 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26661 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
26665 if (i
== nb_allowed_archs
)
26667 as_bad (_("architectural extension `%s' is not allowed for the "
26668 "current base architecture"), name
);
26673 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26676 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26678 mcpu_cpu_opt
= &selected_cpu
;
26679 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26680 *input_line_pointer
= saved_char
;
26681 demand_empty_rest_of_line ();
26685 if (opt
->name
== NULL
)
26686 as_bad (_("unknown architecture extension `%s'\n"), name
);
26688 *input_line_pointer
= saved_char
;
26689 ignore_rest_of_line ();
26692 /* Parse a .fpu directive. */
26695 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26697 const struct arm_option_fpu_value_table
*opt
;
26701 name
= input_line_pointer
;
26702 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26703 input_line_pointer
++;
26704 saved_char
= *input_line_pointer
;
26705 *input_line_pointer
= 0;
26707 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26708 if (streq (opt
->name
, name
))
26710 mfpu_opt
= &opt
->value
;
26711 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26712 *input_line_pointer
= saved_char
;
26713 demand_empty_rest_of_line ();
26717 as_bad (_("unknown floating point format `%s'\n"), name
);
26718 *input_line_pointer
= saved_char
;
26719 ignore_rest_of_line ();
26722 /* Copy symbol information. */
26725 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26727 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26731 /* Given a symbolic attribute NAME, return the proper integer value.
26732 Returns -1 if the attribute is not known. */
26735 arm_convert_symbolic_attribute (const char *name
)
26737 static const struct
26742 attribute_table
[] =
26744 /* When you modify this table you should
26745 also modify the list in doc/c-arm.texi. */
26746 #define T(tag) {#tag, tag}
26747 T (Tag_CPU_raw_name
),
26750 T (Tag_CPU_arch_profile
),
26751 T (Tag_ARM_ISA_use
),
26752 T (Tag_THUMB_ISA_use
),
26756 T (Tag_Advanced_SIMD_arch
),
26757 T (Tag_PCS_config
),
26758 T (Tag_ABI_PCS_R9_use
),
26759 T (Tag_ABI_PCS_RW_data
),
26760 T (Tag_ABI_PCS_RO_data
),
26761 T (Tag_ABI_PCS_GOT_use
),
26762 T (Tag_ABI_PCS_wchar_t
),
26763 T (Tag_ABI_FP_rounding
),
26764 T (Tag_ABI_FP_denormal
),
26765 T (Tag_ABI_FP_exceptions
),
26766 T (Tag_ABI_FP_user_exceptions
),
26767 T (Tag_ABI_FP_number_model
),
26768 T (Tag_ABI_align_needed
),
26769 T (Tag_ABI_align8_needed
),
26770 T (Tag_ABI_align_preserved
),
26771 T (Tag_ABI_align8_preserved
),
26772 T (Tag_ABI_enum_size
),
26773 T (Tag_ABI_HardFP_use
),
26774 T (Tag_ABI_VFP_args
),
26775 T (Tag_ABI_WMMX_args
),
26776 T (Tag_ABI_optimization_goals
),
26777 T (Tag_ABI_FP_optimization_goals
),
26778 T (Tag_compatibility
),
26779 T (Tag_CPU_unaligned_access
),
26780 T (Tag_FP_HP_extension
),
26781 T (Tag_VFP_HP_extension
),
26782 T (Tag_ABI_FP_16bit_format
),
26783 T (Tag_MPextension_use
),
26785 T (Tag_nodefaults
),
26786 T (Tag_also_compatible_with
),
26787 T (Tag_conformance
),
26789 T (Tag_Virtualization_use
),
26790 T (Tag_DSP_extension
),
26791 /* We deliberately do not include Tag_MPextension_use_legacy. */
26799 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26800 if (streq (name
, attribute_table
[i
].name
))
26801 return attribute_table
[i
].tag
;
26807 /* Apply sym value for relocations only in the case that they are for
26808 local symbols in the same segment as the fixup and you have the
26809 respective architectural feature for blx and simple switches. */
26811 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26814 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26815 /* PR 17444: If the local symbol is in a different section then a reloc
26816 will always be generated for it, so applying the symbol value now
26817 will result in a double offset being stored in the relocation. */
26818 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26819 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26821 switch (fixP
->fx_r_type
)
26823 case BFD_RELOC_ARM_PCREL_BLX
:
26824 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26825 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26829 case BFD_RELOC_ARM_PCREL_CALL
:
26830 case BFD_RELOC_THUMB_PCREL_BLX
:
26831 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26842 #endif /* OBJ_ELF */