1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static arm_feature_set
*dyn_mcpu_ext_opt
= NULL
;
151 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
152 static const arm_feature_set
*march_cpu_opt
= NULL
;
153 static arm_feature_set
*dyn_march_ext_opt
= NULL
;
154 static const arm_feature_set
*march_fpu_opt
= NULL
;
155 static const arm_feature_set
*mfpu_opt
= NULL
;
156 static const arm_feature_set
*object_arch
= NULL
;
158 /* Constants for known architecture features. */
159 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
160 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
161 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
162 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
163 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
164 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
165 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
169 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
172 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
175 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
176 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
177 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
178 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
179 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
180 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
181 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
182 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v4t_5
=
184 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
185 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
186 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
187 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
188 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
189 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
190 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
192 static const arm_feature_set arm_ext_v6_notm
=
193 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
194 static const arm_feature_set arm_ext_v6_dsp
=
195 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
196 static const arm_feature_set arm_ext_barrier
=
197 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
198 static const arm_feature_set arm_ext_msr
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
200 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
201 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
202 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
203 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
205 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
207 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
208 static const arm_feature_set arm_ext_m
=
209 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
210 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
211 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
212 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
213 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
214 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
215 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
216 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
217 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
218 static const arm_feature_set arm_ext_v8m_main
=
219 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
220 /* Instructions in ARMv8-M only found in M profile architectures. */
221 static const arm_feature_set arm_ext_v8m_m_only
=
222 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
223 static const arm_feature_set arm_ext_v6t2_v8m
=
224 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
225 /* Instructions shared between ARMv8-A and ARMv8-M. */
226 static const arm_feature_set arm_ext_atomics
=
227 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
229 /* DSP instructions Tag_DSP_extension refers to. */
230 static const arm_feature_set arm_ext_dsp
=
231 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
233 static const arm_feature_set arm_ext_ras
=
234 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
235 /* FP16 instructions. */
236 static const arm_feature_set arm_ext_fp16
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
238 static const arm_feature_set arm_ext_v8_3
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
241 static const arm_feature_set arm_arch_any
= ARM_ANY
;
243 static const arm_feature_set fpu_any
= FPU_ANY
;
245 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
246 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
247 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
249 static const arm_feature_set arm_cext_iwmmxt2
=
250 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
251 static const arm_feature_set arm_cext_iwmmxt
=
252 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
253 static const arm_feature_set arm_cext_xscale
=
254 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
255 static const arm_feature_set arm_cext_maverick
=
256 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
257 static const arm_feature_set fpu_fpa_ext_v1
=
258 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
259 static const arm_feature_set fpu_fpa_ext_v2
=
260 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
261 static const arm_feature_set fpu_vfp_ext_v1xd
=
262 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
263 static const arm_feature_set fpu_vfp_ext_v1
=
264 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
265 static const arm_feature_set fpu_vfp_ext_v2
=
266 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
267 static const arm_feature_set fpu_vfp_ext_v3xd
=
268 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
269 static const arm_feature_set fpu_vfp_ext_v3
=
270 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
271 static const arm_feature_set fpu_vfp_ext_d32
=
272 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
273 static const arm_feature_set fpu_neon_ext_v1
=
274 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
275 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
276 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
278 static const arm_feature_set fpu_vfp_fp16
=
279 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
280 static const arm_feature_set fpu_neon_ext_fma
=
281 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
283 static const arm_feature_set fpu_vfp_ext_fma
=
284 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
285 static const arm_feature_set fpu_vfp_ext_armv8
=
286 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
287 static const arm_feature_set fpu_vfp_ext_armv8xd
=
288 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
289 static const arm_feature_set fpu_neon_ext_armv8
=
290 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
291 static const arm_feature_set fpu_crypto_ext_armv8
=
292 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
293 static const arm_feature_set crc_ext_armv8
=
294 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
295 static const arm_feature_set fpu_neon_ext_v8_1
=
296 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
297 static const arm_feature_set fpu_neon_ext_dotprod
=
298 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
300 static int mfloat_abi_opt
= -1;
301 /* Record user cpu selection for object attributes. */
302 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
303 /* Must be long enough to hold any of the names in arm_cpus. */
304 static char selected_cpu_name
[20];
306 extern FLONUM_TYPE generic_floating_point_number
;
308 /* Return if no cpu was selected on command-line. */
310 no_cpu_selected (void)
312 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
317 static int meabi_flags
= EABI_DEFAULT
;
319 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
322 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
327 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
332 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
333 symbolS
* GOT_symbol
;
336 /* 0: assemble for ARM,
337 1: assemble for Thumb,
338 2: assemble for Thumb even though target CPU does not support thumb
340 static int thumb_mode
= 0;
341 /* A value distinct from the possible values for thumb_mode that we
342 can use to record whether thumb_mode has been copied into the
343 tc_frag_data field of a frag. */
344 #define MODE_RECORDED (1 << 4)
346 /* Specifies the intrinsic IT insn behavior mode. */
347 enum implicit_it_mode
349 IMPLICIT_IT_MODE_NEVER
= 0x00,
350 IMPLICIT_IT_MODE_ARM
= 0x01,
351 IMPLICIT_IT_MODE_THUMB
= 0x02,
352 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
354 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
356 /* If unified_syntax is true, we are processing the new unified
357 ARM/Thumb syntax. Important differences from the old ARM mode:
359 - Immediate operands do not require a # prefix.
360 - Conditional affixes always appear at the end of the
361 instruction. (For backward compatibility, those instructions
362 that formerly had them in the middle, continue to accept them
364 - The IT instruction may appear, and if it does is validated
365 against subsequent conditional affixes. It does not generate
368 Important differences from the old Thumb mode:
370 - Immediate operands do not require a # prefix.
371 - Most of the V6T2 instructions are only available in unified mode.
372 - The .N and .W suffixes are recognized and honored (it is an error
373 if they cannot be honored).
374 - All instructions set the flags if and only if they have an 's' affix.
375 - Conditional affixes may be used. They are validated against
376 preceding IT instructions. Unlike ARM mode, you cannot use a
377 conditional affix except in the scope of an IT instruction. */
379 static bfd_boolean unified_syntax
= FALSE
;
381 /* An immediate operand can start with #, and ld*, st*, pld operands
382 can contain [ and ]. We need to tell APP not to elide whitespace
383 before a [, which can appear as the first operand for pld.
384 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
385 const char arm_symbol_chars
[] = "#[]{}";
400 enum neon_el_type type
;
404 #define NEON_MAX_TYPE_ELS 4
408 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
412 enum it_instruction_type
417 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
418 if inside, should be the last one. */
419 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
420 i.e. BKPT and NOP. */
421 IT_INSN
/* The IT insn has been parsed. */
424 /* The maximum number of operands we need. */
425 #define ARM_IT_MAX_OPERANDS 6
430 unsigned long instruction
;
434 /* "uncond_value" is set to the value in place of the conditional field in
435 unconditional versions of the instruction, or -1 if nothing is
438 struct neon_type vectype
;
439 /* This does not indicate an actual NEON instruction, only that
440 the mnemonic accepts neon-style type suffixes. */
442 /* Set to the opcode if the instruction needs relaxation.
443 Zero if the instruction is not relaxed. */
447 bfd_reloc_code_real_type type
;
452 enum it_instruction_type it_insn_type
;
458 struct neon_type_el vectype
;
459 unsigned present
: 1; /* Operand present. */
460 unsigned isreg
: 1; /* Operand was a register. */
461 unsigned immisreg
: 1; /* .imm field is a second register. */
462 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
463 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
464 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
465 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
466 instructions. This allows us to disambiguate ARM <-> vector insns. */
467 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
468 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
469 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
470 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
471 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
472 unsigned writeback
: 1; /* Operand has trailing ! */
473 unsigned preind
: 1; /* Preindexed address. */
474 unsigned postind
: 1; /* Postindexed address. */
475 unsigned negative
: 1; /* Index register was negated. */
476 unsigned shifted
: 1; /* Shift applied to operation. */
477 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
478 } operands
[ARM_IT_MAX_OPERANDS
];
481 static struct arm_it inst
;
483 #define NUM_FLOAT_VALS 8
485 const char * fp_const
[] =
487 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
490 /* Number of littlenums required to hold an extended precision number. */
491 #define MAX_LITTLENUMS 6
493 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
503 #define CP_T_X 0x00008000
504 #define CP_T_Y 0x00400000
506 #define CONDS_BIT 0x00100000
507 #define LOAD_BIT 0x00100000
509 #define DOUBLE_LOAD_FLAG 0x00000001
513 const char * template_name
;
517 #define COND_ALWAYS 0xE
521 const char * template_name
;
525 struct asm_barrier_opt
527 const char * template_name
;
529 const arm_feature_set arch
;
532 /* The bit that distinguishes CPSR and SPSR. */
533 #define SPSR_BIT (1 << 22)
535 /* The individual PSR flag bits. */
536 #define PSR_c (1 << 16)
537 #define PSR_x (1 << 17)
538 #define PSR_s (1 << 18)
539 #define PSR_f (1 << 19)
544 bfd_reloc_code_real_type reloc
;
549 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
550 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
555 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
558 /* Bits for DEFINED field in neon_typed_alias. */
559 #define NTA_HASTYPE 1
560 #define NTA_HASINDEX 2
562 struct neon_typed_alias
564 unsigned char defined
;
566 struct neon_type_el eltype
;
569 /* ARM register categories. This includes coprocessor numbers and various
570 architecture extensions' registers. */
597 /* Structure for a hash table entry for a register.
598 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
599 information which states whether a vector type or index is specified (for a
600 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
606 unsigned char builtin
;
607 struct neon_typed_alias
* neon
;
610 /* Diagnostics used when we don't get a register of the expected type. */
611 const char * const reg_expected_msgs
[] =
613 N_("ARM register expected"),
614 N_("bad or missing co-processor number"),
615 N_("co-processor register expected"),
616 N_("FPA register expected"),
617 N_("VFP single precision register expected"),
618 N_("VFP/Neon double precision register expected"),
619 N_("Neon quad precision register expected"),
620 N_("VFP single or double precision register expected"),
621 N_("Neon double or quad precision register expected"),
622 N_("VFP single, double or Neon quad precision register expected"),
623 N_("VFP system register expected"),
624 N_("Maverick MVF register expected"),
625 N_("Maverick MVD register expected"),
626 N_("Maverick MVFX register expected"),
627 N_("Maverick MVDX register expected"),
628 N_("Maverick MVAX register expected"),
629 N_("Maverick DSPSC register expected"),
630 N_("iWMMXt data register expected"),
631 N_("iWMMXt control register expected"),
632 N_("iWMMXt scalar register expected"),
633 N_("XScale accumulator register expected"),
636 /* Some well known registers that we refer to directly elsewhere. */
642 /* ARM instructions take 4bytes in the object file, Thumb instructions
648 /* Basic string to match. */
649 const char * template_name
;
651 /* Parameters to instruction. */
652 unsigned int operands
[8];
654 /* Conditional tag - see opcode_lookup. */
655 unsigned int tag
: 4;
657 /* Basic instruction code. */
658 unsigned int avalue
: 28;
660 /* Thumb-format instruction code. */
663 /* Which architecture variant provides this instruction. */
664 const arm_feature_set
* avariant
;
665 const arm_feature_set
* tvariant
;
667 /* Function to call to encode instruction in ARM format. */
668 void (* aencode
) (void);
670 /* Function to call to encode instruction in Thumb format. */
671 void (* tencode
) (void);
674 /* Defines for various bits that we will want to toggle. */
675 #define INST_IMMEDIATE 0x02000000
676 #define OFFSET_REG 0x02000000
677 #define HWOFFSET_IMM 0x00400000
678 #define SHIFT_BY_REG 0x00000010
679 #define PRE_INDEX 0x01000000
680 #define INDEX_UP 0x00800000
681 #define WRITE_BACK 0x00200000
682 #define LDM_TYPE_2_OR_3 0x00400000
683 #define CPSI_MMOD 0x00020000
685 #define LITERAL_MASK 0xf000f000
686 #define OPCODE_MASK 0xfe1fffff
687 #define V4_STR_BIT 0x00000020
688 #define VLDR_VMOV_SAME 0x0040f000
690 #define T2_SUBS_PC_LR 0xf3de8f00
692 #define DATA_OP_SHIFT 21
693 #define SBIT_SHIFT 20
695 #define T2_OPCODE_MASK 0xfe1fffff
696 #define T2_DATA_OP_SHIFT 21
697 #define T2_SBIT_SHIFT 20
699 #define A_COND_MASK 0xf0000000
700 #define A_PUSH_POP_OP_MASK 0x0fff0000
702 /* Opcodes for pushing/poping registers to/from the stack. */
703 #define A1_OPCODE_PUSH 0x092d0000
704 #define A2_OPCODE_PUSH 0x052d0004
705 #define A2_OPCODE_POP 0x049d0004
707 /* Codes to distinguish the arithmetic instructions. */
718 #define OPCODE_CMP 10
719 #define OPCODE_CMN 11
720 #define OPCODE_ORR 12
721 #define OPCODE_MOV 13
722 #define OPCODE_BIC 14
723 #define OPCODE_MVN 15
725 #define T2_OPCODE_AND 0
726 #define T2_OPCODE_BIC 1
727 #define T2_OPCODE_ORR 2
728 #define T2_OPCODE_ORN 3
729 #define T2_OPCODE_EOR 4
730 #define T2_OPCODE_ADD 8
731 #define T2_OPCODE_ADC 10
732 #define T2_OPCODE_SBC 11
733 #define T2_OPCODE_SUB 13
734 #define T2_OPCODE_RSB 14
736 #define T_OPCODE_MUL 0x4340
737 #define T_OPCODE_TST 0x4200
738 #define T_OPCODE_CMN 0x42c0
739 #define T_OPCODE_NEG 0x4240
740 #define T_OPCODE_MVN 0x43c0
742 #define T_OPCODE_ADD_R3 0x1800
743 #define T_OPCODE_SUB_R3 0x1a00
744 #define T_OPCODE_ADD_HI 0x4400
745 #define T_OPCODE_ADD_ST 0xb000
746 #define T_OPCODE_SUB_ST 0xb080
747 #define T_OPCODE_ADD_SP 0xa800
748 #define T_OPCODE_ADD_PC 0xa000
749 #define T_OPCODE_ADD_I8 0x3000
750 #define T_OPCODE_SUB_I8 0x3800
751 #define T_OPCODE_ADD_I3 0x1c00
752 #define T_OPCODE_SUB_I3 0x1e00
754 #define T_OPCODE_ASR_R 0x4100
755 #define T_OPCODE_LSL_R 0x4080
756 #define T_OPCODE_LSR_R 0x40c0
757 #define T_OPCODE_ROR_R 0x41c0
758 #define T_OPCODE_ASR_I 0x1000
759 #define T_OPCODE_LSL_I 0x0000
760 #define T_OPCODE_LSR_I 0x0800
762 #define T_OPCODE_MOV_I8 0x2000
763 #define T_OPCODE_CMP_I8 0x2800
764 #define T_OPCODE_CMP_LR 0x4280
765 #define T_OPCODE_MOV_HR 0x4600
766 #define T_OPCODE_CMP_HR 0x4500
768 #define T_OPCODE_LDR_PC 0x4800
769 #define T_OPCODE_LDR_SP 0x9800
770 #define T_OPCODE_STR_SP 0x9000
771 #define T_OPCODE_LDR_IW 0x6800
772 #define T_OPCODE_STR_IW 0x6000
773 #define T_OPCODE_LDR_IH 0x8800
774 #define T_OPCODE_STR_IH 0x8000
775 #define T_OPCODE_LDR_IB 0x7800
776 #define T_OPCODE_STR_IB 0x7000
777 #define T_OPCODE_LDR_RW 0x5800
778 #define T_OPCODE_STR_RW 0x5000
779 #define T_OPCODE_LDR_RH 0x5a00
780 #define T_OPCODE_STR_RH 0x5200
781 #define T_OPCODE_LDR_RB 0x5c00
782 #define T_OPCODE_STR_RB 0x5400
784 #define T_OPCODE_PUSH 0xb400
785 #define T_OPCODE_POP 0xbc00
787 #define T_OPCODE_BRANCH 0xe000
789 #define THUMB_SIZE 2 /* Size of thumb instruction. */
790 #define THUMB_PP_PC_LR 0x0100
791 #define THUMB_LOAD_BIT 0x0800
792 #define THUMB2_LOAD_BIT 0x00100000
794 #define BAD_ARGS _("bad arguments to instruction")
795 #define BAD_SP _("r13 not allowed here")
796 #define BAD_PC _("r15 not allowed here")
797 #define BAD_COND _("instruction cannot be conditional")
798 #define BAD_OVERLAP _("registers may not be the same")
799 #define BAD_HIREG _("lo register required")
800 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
801 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
802 #define BAD_BRANCH _("branch must be last instruction in IT block")
803 #define BAD_NOT_IT _("instruction not allowed in IT block")
804 #define BAD_FPU _("selected FPU does not support instruction")
805 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
806 #define BAD_IT_COND _("incorrect condition in IT block")
807 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
808 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
809 #define BAD_PC_ADDRESSING \
810 _("cannot use register index with PC-relative addressing")
811 #define BAD_PC_WRITEBACK \
812 _("cannot use writeback with PC-relative addressing")
813 #define BAD_RANGE _("branch out of range")
814 #define BAD_FP16 _("selected processor does not support fp16 instruction")
815 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
816 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
818 static struct hash_control
* arm_ops_hsh
;
819 static struct hash_control
* arm_cond_hsh
;
820 static struct hash_control
* arm_shift_hsh
;
821 static struct hash_control
* arm_psr_hsh
;
822 static struct hash_control
* arm_v7m_psr_hsh
;
823 static struct hash_control
* arm_reg_hsh
;
824 static struct hash_control
* arm_reloc_hsh
;
825 static struct hash_control
* arm_barrier_opt_hsh
;
827 /* Stuff needed to resolve the label ambiguity
836 symbolS
* last_label_seen
;
837 static int label_is_thumb_function_name
= FALSE
;
839 /* Literal pool structure. Held on a per-section
840 and per-sub-section basis. */
842 #define MAX_LITERAL_POOL_SIZE 1024
843 typedef struct literal_pool
845 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
846 unsigned int next_free_entry
;
852 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
854 struct literal_pool
* next
;
855 unsigned int alignment
;
858 /* Pointer to a linked list of literal pools. */
859 literal_pool
* list_of_pools
= NULL
;
861 typedef enum asmfunc_states
864 WAITING_ASMFUNC_NAME
,
868 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
871 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
873 static struct current_it now_it
;
877 now_it_compatible (int cond
)
879 return (cond
& ~1) == (now_it
.cc
& ~1);
883 conditional_insn (void)
885 return inst
.cond
!= COND_ALWAYS
;
888 static int in_it_block (void);
890 static int handle_it_state (void);
892 static void force_automatic_it_block_close (void);
894 static void it_fsm_post_encode (void);
896 #define set_it_insn_type(type) \
899 inst.it_insn_type = type; \
900 if (handle_it_state () == FAIL) \
905 #define set_it_insn_type_nonvoid(type, failret) \
908 inst.it_insn_type = type; \
909 if (handle_it_state () == FAIL) \
914 #define set_it_insn_type_last() \
917 if (inst.cond == COND_ALWAYS) \
918 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
920 set_it_insn_type (INSIDE_IT_LAST_INSN); \
926 /* This array holds the chars that always start a comment. If the
927 pre-processor is disabled, these aren't very useful. */
928 char arm_comment_chars
[] = "@";
930 /* This array holds the chars that only start a comment at the beginning of
931 a line. If the line seems to have the form '# 123 filename'
932 .line and .file directives will appear in the pre-processed output. */
933 /* Note that input_file.c hand checks for '#' at the beginning of the
934 first line of the input file. This is because the compiler outputs
935 #NO_APP at the beginning of its output. */
936 /* Also note that comments like this one will always work. */
937 const char line_comment_chars
[] = "#";
939 char arm_line_separator_chars
[] = ";";
941 /* Chars that can be used to separate mant
942 from exp in floating point numbers. */
943 const char EXP_CHARS
[] = "eE";
945 /* Chars that mean this number is a floating point constant. */
949 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
951 /* Prefix characters that indicate the start of an immediate
953 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
955 /* Separator character handling. */
957 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
960 skip_past_char (char ** str
, char c
)
962 /* PR gas/14987: Allow for whitespace before the expected character. */
963 skip_whitespace (*str
);
974 #define skip_past_comma(str) skip_past_char (str, ',')
976 /* Arithmetic expressions (possibly involving symbols). */
978 /* Return TRUE if anything in the expression is a bignum. */
981 walk_no_bignums (symbolS
* sp
)
983 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
986 if (symbol_get_value_expression (sp
)->X_add_symbol
)
988 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
989 || (symbol_get_value_expression (sp
)->X_op_symbol
990 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
996 static int in_my_get_expression
= 0;
998 /* Third argument to my_get_expression. */
999 #define GE_NO_PREFIX 0
1000 #define GE_IMM_PREFIX 1
1001 #define GE_OPT_PREFIX 2
1002 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1003 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1004 #define GE_OPT_PREFIX_BIG 3
1007 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1012 /* In unified syntax, all prefixes are optional. */
1014 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1017 switch (prefix_mode
)
1019 case GE_NO_PREFIX
: break;
1021 if (!is_immediate_prefix (**str
))
1023 inst
.error
= _("immediate expression requires a # prefix");
1029 case GE_OPT_PREFIX_BIG
:
1030 if (is_immediate_prefix (**str
))
1036 memset (ep
, 0, sizeof (expressionS
));
1038 save_in
= input_line_pointer
;
1039 input_line_pointer
= *str
;
1040 in_my_get_expression
= 1;
1041 seg
= expression (ep
);
1042 in_my_get_expression
= 0;
1044 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1046 /* We found a bad or missing expression in md_operand(). */
1047 *str
= input_line_pointer
;
1048 input_line_pointer
= save_in
;
1049 if (inst
.error
== NULL
)
1050 inst
.error
= (ep
->X_op
== O_absent
1051 ? _("missing expression") :_("bad expression"));
1056 if (seg
!= absolute_section
1057 && seg
!= text_section
1058 && seg
!= data_section
1059 && seg
!= bss_section
1060 && seg
!= undefined_section
)
1062 inst
.error
= _("bad segment");
1063 *str
= input_line_pointer
;
1064 input_line_pointer
= save_in
;
1071 /* Get rid of any bignums now, so that we don't generate an error for which
1072 we can't establish a line number later on. Big numbers are never valid
1073 in instructions, which is where this routine is always called. */
1074 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1075 && (ep
->X_op
== O_big
1076 || (ep
->X_add_symbol
1077 && (walk_no_bignums (ep
->X_add_symbol
)
1079 && walk_no_bignums (ep
->X_op_symbol
))))))
1081 inst
.error
= _("invalid constant");
1082 *str
= input_line_pointer
;
1083 input_line_pointer
= save_in
;
1087 *str
= input_line_pointer
;
1088 input_line_pointer
= save_in
;
1092 /* Turn a string in input_line_pointer into a floating point constant
1093 of type TYPE, and store the appropriate bytes in *LITP. The number
1094 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1095 returned, or NULL on OK.
1097 Note that fp constants aren't represent in the normal way on the ARM.
1098 In big endian mode, things are as expected. However, in little endian
1099 mode fp constants are big-endian word-wise, and little-endian byte-wise
1100 within the words. For example, (double) 1.1 in big endian mode is
1101 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1102 the byte sequence 99 99 f1 3f 9a 99 99 99.
1104 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1107 md_atof (int type
, char * litP
, int * sizeP
)
1110 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1142 return _("Unrecognized or unsupported floating point constant");
1145 t
= atof_ieee (input_line_pointer
, type
, words
);
1147 input_line_pointer
= t
;
1148 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1150 if (target_big_endian
)
1152 for (i
= 0; i
< prec
; i
++)
1154 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1155 litP
+= sizeof (LITTLENUM_TYPE
);
1160 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1161 for (i
= prec
- 1; i
>= 0; i
--)
1163 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1164 litP
+= sizeof (LITTLENUM_TYPE
);
1167 /* For a 4 byte float the order of elements in `words' is 1 0.
1168 For an 8 byte float the order is 1 0 3 2. */
1169 for (i
= 0; i
< prec
; i
+= 2)
1171 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1172 sizeof (LITTLENUM_TYPE
));
1173 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1174 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1175 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1182 /* We handle all bad expressions here, so that we can report the faulty
1183 instruction in the error message. */
1185 md_operand (expressionS
* exp
)
1187 if (in_my_get_expression
)
1188 exp
->X_op
= O_illegal
;
1191 /* Immediate values. */
1193 /* Generic immediate-value read function for use in directives.
1194 Accepts anything that 'expression' can fold to a constant.
1195 *val receives the number. */
1198 immediate_for_directive (int *val
)
1201 exp
.X_op
= O_illegal
;
1203 if (is_immediate_prefix (*input_line_pointer
))
1205 input_line_pointer
++;
1209 if (exp
.X_op
!= O_constant
)
1211 as_bad (_("expected #constant"));
1212 ignore_rest_of_line ();
1215 *val
= exp
.X_add_number
;
1220 /* Register parsing. */
1222 /* Generic register parser. CCP points to what should be the
1223 beginning of a register name. If it is indeed a valid register
1224 name, advance CCP over it and return the reg_entry structure;
1225 otherwise return NULL. Does not issue diagnostics. */
1227 static struct reg_entry
*
1228 arm_reg_parse_multi (char **ccp
)
1232 struct reg_entry
*reg
;
1234 skip_whitespace (start
);
1236 #ifdef REGISTER_PREFIX
1237 if (*start
!= REGISTER_PREFIX
)
1241 #ifdef OPTIONAL_REGISTER_PREFIX
1242 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1247 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1252 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1254 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1264 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1265 enum arm_reg_type type
)
1267 /* Alternative syntaxes are accepted for a few register classes. */
1274 /* Generic coprocessor register names are allowed for these. */
1275 if (reg
&& reg
->type
== REG_TYPE_CN
)
1280 /* For backward compatibility, a bare number is valid here. */
1282 unsigned long processor
= strtoul (start
, ccp
, 10);
1283 if (*ccp
!= start
&& processor
<= 15)
1288 case REG_TYPE_MMXWC
:
1289 /* WC includes WCG. ??? I'm not sure this is true for all
1290 instructions that take WC registers. */
1291 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1302 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1303 return value is the register number or FAIL. */
1306 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1309 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1312 /* Do not allow a scalar (reg+index) to parse as a register. */
1313 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1316 if (reg
&& reg
->type
== type
)
1319 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1326 /* Parse a Neon type specifier. *STR should point at the leading '.'
1327 character. Does no verification at this stage that the type fits the opcode
1334 Can all be legally parsed by this function.
1336 Fills in neon_type struct pointer with parsed information, and updates STR
1337 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1338 type, FAIL if not. */
1341 parse_neon_type (struct neon_type
*type
, char **str
)
1348 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1350 enum neon_el_type thistype
= NT_untyped
;
1351 unsigned thissize
= -1u;
1358 /* Just a size without an explicit type. */
1362 switch (TOLOWER (*ptr
))
1364 case 'i': thistype
= NT_integer
; break;
1365 case 'f': thistype
= NT_float
; break;
1366 case 'p': thistype
= NT_poly
; break;
1367 case 's': thistype
= NT_signed
; break;
1368 case 'u': thistype
= NT_unsigned
; break;
1370 thistype
= NT_float
;
1375 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1381 /* .f is an abbreviation for .f32. */
1382 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1387 thissize
= strtoul (ptr
, &ptr
, 10);
1389 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1392 as_bad (_("bad size %d in type specifier"), thissize
);
1400 type
->el
[type
->elems
].type
= thistype
;
1401 type
->el
[type
->elems
].size
= thissize
;
1406 /* Empty/missing type is not a successful parse. */
1407 if (type
->elems
== 0)
1415 /* Errors may be set multiple times during parsing or bit encoding
1416 (particularly in the Neon bits), but usually the earliest error which is set
1417 will be the most meaningful. Avoid overwriting it with later (cascading)
1418 errors by calling this function. */
1421 first_error (const char *err
)
1427 /* Parse a single type, e.g. ".s32", leading period included. */
1429 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1432 struct neon_type optype
;
1436 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1438 if (optype
.elems
== 1)
1439 *vectype
= optype
.el
[0];
1442 first_error (_("only one type should be specified for operand"));
1448 first_error (_("vector type expected"));
1460 /* Special meanings for indices (which have a range of 0-7), which will fit into
1463 #define NEON_ALL_LANES 15
1464 #define NEON_INTERLEAVE_LANES 14
1466 /* Parse either a register or a scalar, with an optional type. Return the
1467 register number, and optionally fill in the actual type of the register
1468 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1469 type/index information in *TYPEINFO. */
1472 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1473 enum arm_reg_type
*rtype
,
1474 struct neon_typed_alias
*typeinfo
)
1477 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1478 struct neon_typed_alias atype
;
1479 struct neon_type_el parsetype
;
1483 atype
.eltype
.type
= NT_invtype
;
1484 atype
.eltype
.size
= -1;
1486 /* Try alternate syntax for some types of register. Note these are mutually
1487 exclusive with the Neon syntax extensions. */
1490 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1498 /* Undo polymorphism when a set of register types may be accepted. */
1499 if ((type
== REG_TYPE_NDQ
1500 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1501 || (type
== REG_TYPE_VFSD
1502 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1503 || (type
== REG_TYPE_NSDQ
1504 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1505 || reg
->type
== REG_TYPE_NQ
))
1506 || (type
== REG_TYPE_MMXWC
1507 && (reg
->type
== REG_TYPE_MMXWCG
)))
1508 type
= (enum arm_reg_type
) reg
->type
;
1510 if (type
!= reg
->type
)
1516 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1518 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1520 first_error (_("can't redefine type for operand"));
1523 atype
.defined
|= NTA_HASTYPE
;
1524 atype
.eltype
= parsetype
;
1527 if (skip_past_char (&str
, '[') == SUCCESS
)
1529 if (type
!= REG_TYPE_VFD
)
1531 first_error (_("only D registers may be indexed"));
1535 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1537 first_error (_("can't change index for operand"));
1541 atype
.defined
|= NTA_HASINDEX
;
1543 if (skip_past_char (&str
, ']') == SUCCESS
)
1544 atype
.index
= NEON_ALL_LANES
;
1549 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1551 if (exp
.X_op
!= O_constant
)
1553 first_error (_("constant expression required"));
1557 if (skip_past_char (&str
, ']') == FAIL
)
1560 atype
.index
= exp
.X_add_number
;
1575 /* Like arm_reg_parse, but allow allow the following extra features:
1576 - If RTYPE is non-zero, return the (possibly restricted) type of the
1577 register (e.g. Neon double or quad reg when either has been requested).
1578 - If this is a Neon vector type with additional type information, fill
1579 in the struct pointed to by VECTYPE (if non-NULL).
1580 This function will fault on encountering a scalar. */
1583 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1584 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1586 struct neon_typed_alias atype
;
1588 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1593 /* Do not allow regname(... to parse as a register. */
1597 /* Do not allow a scalar (reg+index) to parse as a register. */
1598 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1600 first_error (_("register operand expected, but got scalar"));
1605 *vectype
= atype
.eltype
;
1612 #define NEON_SCALAR_REG(X) ((X) >> 4)
1613 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1615 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1616 have enough information to be able to do a good job bounds-checking. So, we
1617 just do easy checks here, and do further checks later. */
1620 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1624 struct neon_typed_alias atype
;
1626 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1628 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1631 if (atype
.index
== NEON_ALL_LANES
)
1633 first_error (_("scalar must have an index"));
1636 else if (atype
.index
>= 64 / elsize
)
1638 first_error (_("scalar index out of range"));
1643 *type
= atype
.eltype
;
1647 return reg
* 16 + atype
.index
;
1650 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1653 parse_reg_list (char ** strp
)
1655 char * str
= * strp
;
1659 /* We come back here if we get ranges concatenated by '+' or '|'. */
1662 skip_whitespace (str
);
1676 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1678 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1688 first_error (_("bad range in register list"));
1692 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1694 if (range
& (1 << i
))
1696 (_("Warning: duplicated register (r%d) in register list"),
1704 if (range
& (1 << reg
))
1705 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1707 else if (reg
<= cur_reg
)
1708 as_tsktsk (_("Warning: register range not in ascending order"));
1713 while (skip_past_comma (&str
) != FAIL
1714 || (in_range
= 1, *str
++ == '-'));
1717 if (skip_past_char (&str
, '}') == FAIL
)
1719 first_error (_("missing `}'"));
1727 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1730 if (exp
.X_op
== O_constant
)
1732 if (exp
.X_add_number
1733 != (exp
.X_add_number
& 0x0000ffff))
1735 inst
.error
= _("invalid register mask");
1739 if ((range
& exp
.X_add_number
) != 0)
1741 int regno
= range
& exp
.X_add_number
;
1744 regno
= (1 << regno
) - 1;
1746 (_("Warning: duplicated register (r%d) in register list"),
1750 range
|= exp
.X_add_number
;
1754 if (inst
.reloc
.type
!= 0)
1756 inst
.error
= _("expression too complex");
1760 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1761 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1762 inst
.reloc
.pc_rel
= 0;
1766 if (*str
== '|' || *str
== '+')
1772 while (another_range
);
1778 /* Types of registers in a list. */
1787 /* Parse a VFP register list. If the string is invalid return FAIL.
1788 Otherwise return the number of registers, and set PBASE to the first
1789 register. Parses registers of type ETYPE.
1790 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1791 - Q registers can be used to specify pairs of D registers
1792 - { } can be omitted from around a singleton register list
1793 FIXME: This is not implemented, as it would require backtracking in
1796 This could be done (the meaning isn't really ambiguous), but doesn't
1797 fit in well with the current parsing framework.
1798 - 32 D registers may be used (also true for VFPv3).
1799 FIXME: Types are ignored in these register lists, which is probably a
1803 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1808 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1812 unsigned long mask
= 0;
1815 if (skip_past_char (&str
, '{') == FAIL
)
1817 inst
.error
= _("expecting {");
1824 regtype
= REG_TYPE_VFS
;
1829 regtype
= REG_TYPE_VFD
;
1832 case REGLIST_NEON_D
:
1833 regtype
= REG_TYPE_NDQ
;
1837 if (etype
!= REGLIST_VFP_S
)
1839 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1840 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1844 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1847 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1854 base_reg
= max_regs
;
1858 int setmask
= 1, addregs
= 1;
1860 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1862 if (new_base
== FAIL
)
1864 first_error (_(reg_expected_msgs
[regtype
]));
1868 if (new_base
>= max_regs
)
1870 first_error (_("register out of range in list"));
1874 /* Note: a value of 2 * n is returned for the register Q<n>. */
1875 if (regtype
== REG_TYPE_NQ
)
1881 if (new_base
< base_reg
)
1882 base_reg
= new_base
;
1884 if (mask
& (setmask
<< new_base
))
1886 first_error (_("invalid register list"));
1890 if ((mask
>> new_base
) != 0 && ! warned
)
1892 as_tsktsk (_("register list not in ascending order"));
1896 mask
|= setmask
<< new_base
;
1899 if (*str
== '-') /* We have the start of a range expression */
1905 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1908 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1912 if (high_range
>= max_regs
)
1914 first_error (_("register out of range in list"));
1918 if (regtype
== REG_TYPE_NQ
)
1919 high_range
= high_range
+ 1;
1921 if (high_range
<= new_base
)
1923 inst
.error
= _("register range not in ascending order");
1927 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1929 if (mask
& (setmask
<< new_base
))
1931 inst
.error
= _("invalid register list");
1935 mask
|= setmask
<< new_base
;
1940 while (skip_past_comma (&str
) != FAIL
);
1944 /* Sanity check -- should have raised a parse error above. */
1945 if (count
== 0 || count
> max_regs
)
1950 /* Final test -- the registers must be consecutive. */
1952 for (i
= 0; i
< count
; i
++)
1954 if ((mask
& (1u << i
)) == 0)
1956 inst
.error
= _("non-contiguous register range");
1966 /* True if two alias types are the same. */
1969 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1977 if (a
->defined
!= b
->defined
)
1980 if ((a
->defined
& NTA_HASTYPE
) != 0
1981 && (a
->eltype
.type
!= b
->eltype
.type
1982 || a
->eltype
.size
!= b
->eltype
.size
))
1985 if ((a
->defined
& NTA_HASINDEX
) != 0
1986 && (a
->index
!= b
->index
))
1992 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1993 The base register is put in *PBASE.
1994 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1996 The register stride (minus one) is put in bit 4 of the return value.
1997 Bits [6:5] encode the list length (minus one).
1998 The type of the list elements is put in *ELTYPE, if non-NULL. */
2000 #define NEON_LANE(X) ((X) & 0xf)
2001 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2002 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2005 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2006 struct neon_type_el
*eltype
)
2013 int leading_brace
= 0;
2014 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2015 const char *const incr_error
= _("register stride must be 1 or 2");
2016 const char *const type_error
= _("mismatched element/structure types in list");
2017 struct neon_typed_alias firsttype
;
2018 firsttype
.defined
= 0;
2019 firsttype
.eltype
.type
= NT_invtype
;
2020 firsttype
.eltype
.size
= -1;
2021 firsttype
.index
= -1;
2023 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2028 struct neon_typed_alias atype
;
2029 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2033 first_error (_(reg_expected_msgs
[rtype
]));
2040 if (rtype
== REG_TYPE_NQ
)
2046 else if (reg_incr
== -1)
2048 reg_incr
= getreg
- base_reg
;
2049 if (reg_incr
< 1 || reg_incr
> 2)
2051 first_error (_(incr_error
));
2055 else if (getreg
!= base_reg
+ reg_incr
* count
)
2057 first_error (_(incr_error
));
2061 if (! neon_alias_types_same (&atype
, &firsttype
))
2063 first_error (_(type_error
));
2067 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2071 struct neon_typed_alias htype
;
2072 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2074 lane
= NEON_INTERLEAVE_LANES
;
2075 else if (lane
!= NEON_INTERLEAVE_LANES
)
2077 first_error (_(type_error
));
2082 else if (reg_incr
!= 1)
2084 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2088 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2091 first_error (_(reg_expected_msgs
[rtype
]));
2094 if (! neon_alias_types_same (&htype
, &firsttype
))
2096 first_error (_(type_error
));
2099 count
+= hireg
+ dregs
- getreg
;
2103 /* If we're using Q registers, we can't use [] or [n] syntax. */
2104 if (rtype
== REG_TYPE_NQ
)
2110 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2114 else if (lane
!= atype
.index
)
2116 first_error (_(type_error
));
2120 else if (lane
== -1)
2121 lane
= NEON_INTERLEAVE_LANES
;
2122 else if (lane
!= NEON_INTERLEAVE_LANES
)
2124 first_error (_(type_error
));
2129 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2131 /* No lane set by [x]. We must be interleaving structures. */
2133 lane
= NEON_INTERLEAVE_LANES
;
2136 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2137 || (count
> 1 && reg_incr
== -1))
2139 first_error (_("error parsing element/structure list"));
2143 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2145 first_error (_("expected }"));
2153 *eltype
= firsttype
.eltype
;
2158 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2161 /* Parse an explicit relocation suffix on an expression. This is
2162 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2163 arm_reloc_hsh contains no entries, so this function can only
2164 succeed if there is no () after the word. Returns -1 on error,
2165 BFD_RELOC_UNUSED if there wasn't any suffix. */
2168 parse_reloc (char **str
)
2170 struct reloc_entry
*r
;
2174 return BFD_RELOC_UNUSED
;
2179 while (*q
&& *q
!= ')' && *q
!= ',')
2184 if ((r
= (struct reloc_entry
*)
2185 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2192 /* Directives: register aliases. */
2194 static struct reg_entry
*
2195 insert_reg_alias (char *str
, unsigned number
, int type
)
2197 struct reg_entry
*new_reg
;
2200 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2202 if (new_reg
->builtin
)
2203 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2205 /* Only warn about a redefinition if it's not defined as the
2207 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2208 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2213 name
= xstrdup (str
);
2214 new_reg
= XNEW (struct reg_entry
);
2216 new_reg
->name
= name
;
2217 new_reg
->number
= number
;
2218 new_reg
->type
= type
;
2219 new_reg
->builtin
= FALSE
;
2220 new_reg
->neon
= NULL
;
2222 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2229 insert_neon_reg_alias (char *str
, int number
, int type
,
2230 struct neon_typed_alias
*atype
)
2232 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2236 first_error (_("attempt to redefine typed alias"));
2242 reg
->neon
= XNEW (struct neon_typed_alias
);
2243 *reg
->neon
= *atype
;
2247 /* Look for the .req directive. This is of the form:
2249 new_register_name .req existing_register_name
2251 If we find one, or if it looks sufficiently like one that we want to
2252 handle any error here, return TRUE. Otherwise return FALSE. */
2255 create_register_alias (char * newname
, char *p
)
2257 struct reg_entry
*old
;
2258 char *oldname
, *nbuf
;
2261 /* The input scrubber ensures that whitespace after the mnemonic is
2262 collapsed to single spaces. */
2264 if (strncmp (oldname
, " .req ", 6) != 0)
2268 if (*oldname
== '\0')
2271 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2274 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2278 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2279 the desired alias name, and p points to its end. If not, then
2280 the desired alias name is in the global original_case_string. */
2281 #ifdef TC_CASE_SENSITIVE
2284 newname
= original_case_string
;
2285 nlen
= strlen (newname
);
2288 nbuf
= xmemdup0 (newname
, nlen
);
2290 /* Create aliases under the new name as stated; an all-lowercase
2291 version of the new name; and an all-uppercase version of the new
2293 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2295 for (p
= nbuf
; *p
; p
++)
2298 if (strncmp (nbuf
, newname
, nlen
))
2300 /* If this attempt to create an additional alias fails, do not bother
2301 trying to create the all-lower case alias. We will fail and issue
2302 a second, duplicate error message. This situation arises when the
2303 programmer does something like:
2306 The second .req creates the "Foo" alias but then fails to create
2307 the artificial FOO alias because it has already been created by the
2309 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2316 for (p
= nbuf
; *p
; p
++)
2319 if (strncmp (nbuf
, newname
, nlen
))
2320 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2327 /* Create a Neon typed/indexed register alias using directives, e.g.:
2332 These typed registers can be used instead of the types specified after the
2333 Neon mnemonic, so long as all operands given have types. Types can also be
2334 specified directly, e.g.:
2335 vadd d0.s32, d1.s32, d2.s32 */
2338 create_neon_reg_alias (char *newname
, char *p
)
2340 enum arm_reg_type basetype
;
2341 struct reg_entry
*basereg
;
2342 struct reg_entry mybasereg
;
2343 struct neon_type ntype
;
2344 struct neon_typed_alias typeinfo
;
2345 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2348 typeinfo
.defined
= 0;
2349 typeinfo
.eltype
.type
= NT_invtype
;
2350 typeinfo
.eltype
.size
= -1;
2351 typeinfo
.index
= -1;
2355 if (strncmp (p
, " .dn ", 5) == 0)
2356 basetype
= REG_TYPE_VFD
;
2357 else if (strncmp (p
, " .qn ", 5) == 0)
2358 basetype
= REG_TYPE_NQ
;
2367 basereg
= arm_reg_parse_multi (&p
);
2369 if (basereg
&& basereg
->type
!= basetype
)
2371 as_bad (_("bad type for register"));
2375 if (basereg
== NULL
)
2378 /* Try parsing as an integer. */
2379 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2380 if (exp
.X_op
!= O_constant
)
2382 as_bad (_("expression must be constant"));
2385 basereg
= &mybasereg
;
2386 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2392 typeinfo
= *basereg
->neon
;
2394 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2396 /* We got a type. */
2397 if (typeinfo
.defined
& NTA_HASTYPE
)
2399 as_bad (_("can't redefine the type of a register alias"));
2403 typeinfo
.defined
|= NTA_HASTYPE
;
2404 if (ntype
.elems
!= 1)
2406 as_bad (_("you must specify a single type only"));
2409 typeinfo
.eltype
= ntype
.el
[0];
2412 if (skip_past_char (&p
, '[') == SUCCESS
)
2415 /* We got a scalar index. */
2417 if (typeinfo
.defined
& NTA_HASINDEX
)
2419 as_bad (_("can't redefine the index of a scalar alias"));
2423 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2425 if (exp
.X_op
!= O_constant
)
2427 as_bad (_("scalar index must be constant"));
2431 typeinfo
.defined
|= NTA_HASINDEX
;
2432 typeinfo
.index
= exp
.X_add_number
;
2434 if (skip_past_char (&p
, ']') == FAIL
)
2436 as_bad (_("expecting ]"));
2441 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2442 the desired alias name, and p points to its end. If not, then
2443 the desired alias name is in the global original_case_string. */
2444 #ifdef TC_CASE_SENSITIVE
2445 namelen
= nameend
- newname
;
2447 newname
= original_case_string
;
2448 namelen
= strlen (newname
);
2451 namebuf
= xmemdup0 (newname
, namelen
);
2453 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2454 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2456 /* Insert name in all uppercase. */
2457 for (p
= namebuf
; *p
; p
++)
2460 if (strncmp (namebuf
, newname
, namelen
))
2461 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2462 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2464 /* Insert name in all lowercase. */
2465 for (p
= namebuf
; *p
; p
++)
2468 if (strncmp (namebuf
, newname
, namelen
))
2469 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2470 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2476 /* Should never be called, as .req goes between the alias and the
2477 register name, not at the beginning of the line. */
2480 s_req (int a ATTRIBUTE_UNUSED
)
2482 as_bad (_("invalid syntax for .req directive"));
2486 s_dn (int a ATTRIBUTE_UNUSED
)
2488 as_bad (_("invalid syntax for .dn directive"));
2492 s_qn (int a ATTRIBUTE_UNUSED
)
2494 as_bad (_("invalid syntax for .qn directive"));
2497 /* The .unreq directive deletes an alias which was previously defined
2498 by .req. For example:
2504 s_unreq (int a ATTRIBUTE_UNUSED
)
2509 name
= input_line_pointer
;
2511 while (*input_line_pointer
!= 0
2512 && *input_line_pointer
!= ' '
2513 && *input_line_pointer
!= '\n')
2514 ++input_line_pointer
;
2516 saved_char
= *input_line_pointer
;
2517 *input_line_pointer
= 0;
2520 as_bad (_("invalid syntax for .unreq directive"));
2523 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2527 as_bad (_("unknown register alias '%s'"), name
);
2528 else if (reg
->builtin
)
2529 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2536 hash_delete (arm_reg_hsh
, name
, FALSE
);
2537 free ((char *) reg
->name
);
2542 /* Also locate the all upper case and all lower case versions.
2543 Do not complain if we cannot find one or the other as it
2544 was probably deleted above. */
2546 nbuf
= strdup (name
);
2547 for (p
= nbuf
; *p
; p
++)
2549 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2552 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2553 free ((char *) reg
->name
);
2559 for (p
= nbuf
; *p
; p
++)
2561 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2564 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2565 free ((char *) reg
->name
);
2575 *input_line_pointer
= saved_char
;
2576 demand_empty_rest_of_line ();
2579 /* Directives: Instruction set selection. */
2582 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2583 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2584 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2585 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2587 /* Create a new mapping symbol for the transition to STATE. */
2590 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2593 const char * symname
;
2600 type
= BSF_NO_FLAGS
;
2604 type
= BSF_NO_FLAGS
;
2608 type
= BSF_NO_FLAGS
;
2614 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2615 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2620 THUMB_SET_FUNC (symbolP
, 0);
2621 ARM_SET_THUMB (symbolP
, 0);
2622 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2626 THUMB_SET_FUNC (symbolP
, 1);
2627 ARM_SET_THUMB (symbolP
, 1);
2628 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2636 /* Save the mapping symbols for future reference. Also check that
2637 we do not place two mapping symbols at the same offset within a
2638 frag. We'll handle overlap between frags in
2639 check_mapping_symbols.
2641 If .fill or other data filling directive generates zero sized data,
2642 the mapping symbol for the following code will have the same value
2643 as the one generated for the data filling directive. In this case,
2644 we replace the old symbol with the new one at the same address. */
2647 if (frag
->tc_frag_data
.first_map
!= NULL
)
2649 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2650 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2652 frag
->tc_frag_data
.first_map
= symbolP
;
2654 if (frag
->tc_frag_data
.last_map
!= NULL
)
2656 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2657 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2658 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2660 frag
->tc_frag_data
.last_map
= symbolP
;
2663 /* We must sometimes convert a region marked as code to data during
2664 code alignment, if an odd number of bytes have to be padded. The
2665 code mapping symbol is pushed to an aligned address. */
2668 insert_data_mapping_symbol (enum mstate state
,
2669 valueT value
, fragS
*frag
, offsetT bytes
)
2671 /* If there was already a mapping symbol, remove it. */
2672 if (frag
->tc_frag_data
.last_map
!= NULL
2673 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2675 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2679 know (frag
->tc_frag_data
.first_map
== symp
);
2680 frag
->tc_frag_data
.first_map
= NULL
;
2682 frag
->tc_frag_data
.last_map
= NULL
;
2683 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2686 make_mapping_symbol (MAP_DATA
, value
, frag
);
2687 make_mapping_symbol (state
, value
+ bytes
, frag
);
2690 static void mapping_state_2 (enum mstate state
, int max_chars
);
2692 /* Set the mapping state to STATE. Only call this when about to
2693 emit some STATE bytes to the file. */
2695 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2697 mapping_state (enum mstate state
)
2699 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2701 if (mapstate
== state
)
2702 /* The mapping symbol has already been emitted.
2703 There is nothing else to do. */
2706 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2708 All ARM instructions require 4-byte alignment.
2709 (Almost) all Thumb instructions require 2-byte alignment.
2711 When emitting instructions into any section, mark the section
2714 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2715 but themselves require 2-byte alignment; this applies to some
2716 PC- relative forms. However, these cases will involve implicit
2717 literal pool generation or an explicit .align >=2, both of
2718 which will cause the section to me marked with sufficient
2719 alignment. Thus, we don't handle those cases here. */
2720 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2722 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2723 /* This case will be evaluated later. */
2726 mapping_state_2 (state
, 0);
2729 /* Same as mapping_state, but MAX_CHARS bytes have already been
2730 allocated. Put the mapping symbol that far back. */
2733 mapping_state_2 (enum mstate state
, int max_chars
)
2735 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2737 if (!SEG_NORMAL (now_seg
))
2740 if (mapstate
== state
)
2741 /* The mapping symbol has already been emitted.
2742 There is nothing else to do. */
2745 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2746 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2748 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2749 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2752 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2755 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2756 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2760 #define mapping_state(x) ((void)0)
2761 #define mapping_state_2(x, y) ((void)0)
2764 /* Find the real, Thumb encoded start of a Thumb function. */
2768 find_real_start (symbolS
* symbolP
)
2771 const char * name
= S_GET_NAME (symbolP
);
2772 symbolS
* new_target
;
2774 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2775 #define STUB_NAME ".real_start_of"
2780 /* The compiler may generate BL instructions to local labels because
2781 it needs to perform a branch to a far away location. These labels
2782 do not have a corresponding ".real_start_of" label. We check
2783 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2784 the ".real_start_of" convention for nonlocal branches. */
2785 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2788 real_start
= concat (STUB_NAME
, name
, NULL
);
2789 new_target
= symbol_find (real_start
);
2792 if (new_target
== NULL
)
2794 as_warn (_("Failed to find real start of function: %s\n"), name
);
2795 new_target
= symbolP
;
2803 opcode_select (int width
)
2810 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2811 as_bad (_("selected processor does not support THUMB opcodes"));
2814 /* No need to force the alignment, since we will have been
2815 coming from ARM mode, which is word-aligned. */
2816 record_alignment (now_seg
, 1);
2823 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2824 as_bad (_("selected processor does not support ARM opcodes"));
2829 frag_align (2, 0, 0);
2831 record_alignment (now_seg
, 1);
2836 as_bad (_("invalid instruction size selected (%d)"), width
);
2841 s_arm (int ignore ATTRIBUTE_UNUSED
)
2844 demand_empty_rest_of_line ();
2848 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2851 demand_empty_rest_of_line ();
2855 s_code (int unused ATTRIBUTE_UNUSED
)
2859 temp
= get_absolute_expression ();
2864 opcode_select (temp
);
2868 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2873 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2875 /* If we are not already in thumb mode go into it, EVEN if
2876 the target processor does not support thumb instructions.
2877 This is used by gcc/config/arm/lib1funcs.asm for example
2878 to compile interworking support functions even if the
2879 target processor should not support interworking. */
2883 record_alignment (now_seg
, 1);
2886 demand_empty_rest_of_line ();
2890 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2894 /* The following label is the name/address of the start of a Thumb function.
2895 We need to know this for the interworking support. */
2896 label_is_thumb_function_name
= TRUE
;
2899 /* Perform a .set directive, but also mark the alias as
2900 being a thumb function. */
2903 s_thumb_set (int equiv
)
2905 /* XXX the following is a duplicate of the code for s_set() in read.c
2906 We cannot just call that code as we need to get at the symbol that
2913 /* Especial apologies for the random logic:
2914 This just grew, and could be parsed much more simply!
2916 delim
= get_symbol_name (& name
);
2917 end_name
= input_line_pointer
;
2918 (void) restore_line_pointer (delim
);
2920 if (*input_line_pointer
!= ',')
2923 as_bad (_("expected comma after name \"%s\""), name
);
2925 ignore_rest_of_line ();
2929 input_line_pointer
++;
2932 if (name
[0] == '.' && name
[1] == '\0')
2934 /* XXX - this should not happen to .thumb_set. */
2938 if ((symbolP
= symbol_find (name
)) == NULL
2939 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2942 /* When doing symbol listings, play games with dummy fragments living
2943 outside the normal fragment chain to record the file and line info
2945 if (listing
& LISTING_SYMBOLS
)
2947 extern struct list_info_struct
* listing_tail
;
2948 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2950 memset (dummy_frag
, 0, sizeof (fragS
));
2951 dummy_frag
->fr_type
= rs_fill
;
2952 dummy_frag
->line
= listing_tail
;
2953 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2954 dummy_frag
->fr_symbol
= symbolP
;
2958 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2961 /* "set" symbols are local unless otherwise specified. */
2962 SF_SET_LOCAL (symbolP
);
2963 #endif /* OBJ_COFF */
2964 } /* Make a new symbol. */
2966 symbol_table_insert (symbolP
);
2971 && S_IS_DEFINED (symbolP
)
2972 && S_GET_SEGMENT (symbolP
) != reg_section
)
2973 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2975 pseudo_set (symbolP
);
2977 demand_empty_rest_of_line ();
2979 /* XXX Now we come to the Thumb specific bit of code. */
2981 THUMB_SET_FUNC (symbolP
, 1);
2982 ARM_SET_THUMB (symbolP
, 1);
2983 #if defined OBJ_ELF || defined OBJ_COFF
2984 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2988 /* Directives: Mode selection. */
2990 /* .syntax [unified|divided] - choose the new unified syntax
2991 (same for Arm and Thumb encoding, modulo slight differences in what
2992 can be represented) or the old divergent syntax for each mode. */
2994 s_syntax (int unused ATTRIBUTE_UNUSED
)
2998 delim
= get_symbol_name (& name
);
3000 if (!strcasecmp (name
, "unified"))
3001 unified_syntax
= TRUE
;
3002 else if (!strcasecmp (name
, "divided"))
3003 unified_syntax
= FALSE
;
3006 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3009 (void) restore_line_pointer (delim
);
3010 demand_empty_rest_of_line ();
3013 /* Directives: sectioning and alignment. */
3016 s_bss (int ignore ATTRIBUTE_UNUSED
)
3018 /* We don't support putting frags in the BSS segment, we fake it by
3019 marking in_bss, then looking at s_skip for clues. */
3020 subseg_set (bss_section
, 0);
3021 demand_empty_rest_of_line ();
3023 #ifdef md_elf_section_change_hook
3024 md_elf_section_change_hook ();
3029 s_even (int ignore ATTRIBUTE_UNUSED
)
3031 /* Never make frag if expect extra pass. */
3033 frag_align (1, 0, 0);
3035 record_alignment (now_seg
, 1);
3037 demand_empty_rest_of_line ();
3040 /* Directives: CodeComposer Studio. */
3042 /* .ref (for CodeComposer Studio syntax only). */
3044 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3046 if (codecomposer_syntax
)
3047 ignore_rest_of_line ();
3049 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3052 /* If name is not NULL, then it is used for marking the beginning of a
3053 function, whereas if it is NULL then it means the function end. */
3055 asmfunc_debug (const char * name
)
3057 static const char * last_name
= NULL
;
3061 gas_assert (last_name
== NULL
);
3064 if (debug_type
== DEBUG_STABS
)
3065 stabs_generate_asm_func (name
, name
);
3069 gas_assert (last_name
!= NULL
);
3071 if (debug_type
== DEBUG_STABS
)
3072 stabs_generate_asm_endfunc (last_name
, last_name
);
3079 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3081 if (codecomposer_syntax
)
3083 switch (asmfunc_state
)
3085 case OUTSIDE_ASMFUNC
:
3086 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3089 case WAITING_ASMFUNC_NAME
:
3090 as_bad (_(".asmfunc repeated."));
3093 case WAITING_ENDASMFUNC
:
3094 as_bad (_(".asmfunc without function."));
3097 demand_empty_rest_of_line ();
3100 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3104 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3106 if (codecomposer_syntax
)
3108 switch (asmfunc_state
)
3110 case OUTSIDE_ASMFUNC
:
3111 as_bad (_(".endasmfunc without a .asmfunc."));
3114 case WAITING_ASMFUNC_NAME
:
3115 as_bad (_(".endasmfunc without function."));
3118 case WAITING_ENDASMFUNC
:
3119 asmfunc_state
= OUTSIDE_ASMFUNC
;
3120 asmfunc_debug (NULL
);
3123 demand_empty_rest_of_line ();
3126 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3130 s_ccs_def (int name
)
3132 if (codecomposer_syntax
)
3135 as_bad (_(".def pseudo-op only available with -mccs flag."));
3138 /* Directives: Literal pools. */
3140 static literal_pool
*
3141 find_literal_pool (void)
3143 literal_pool
* pool
;
3145 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3147 if (pool
->section
== now_seg
3148 && pool
->sub_section
== now_subseg
)
3155 static literal_pool
*
3156 find_or_make_literal_pool (void)
3158 /* Next literal pool ID number. */
3159 static unsigned int latest_pool_num
= 1;
3160 literal_pool
* pool
;
3162 pool
= find_literal_pool ();
3166 /* Create a new pool. */
3167 pool
= XNEW (literal_pool
);
3171 pool
->next_free_entry
= 0;
3172 pool
->section
= now_seg
;
3173 pool
->sub_section
= now_subseg
;
3174 pool
->next
= list_of_pools
;
3175 pool
->symbol
= NULL
;
3176 pool
->alignment
= 2;
3178 /* Add it to the list. */
3179 list_of_pools
= pool
;
3182 /* New pools, and emptied pools, will have a NULL symbol. */
3183 if (pool
->symbol
== NULL
)
3185 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3186 (valueT
) 0, &zero_address_frag
);
3187 pool
->id
= latest_pool_num
++;
3194 /* Add the literal in the global 'inst'
3195 structure to the relevant literal pool. */
3198 add_to_lit_pool (unsigned int nbytes
)
3200 #define PADDING_SLOT 0x1
3201 #define LIT_ENTRY_SIZE_MASK 0xFF
3202 literal_pool
* pool
;
3203 unsigned int entry
, pool_size
= 0;
3204 bfd_boolean padding_slot_p
= FALSE
;
3210 imm1
= inst
.operands
[1].imm
;
3211 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3212 : inst
.reloc
.exp
.X_unsigned
? 0
3213 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3214 if (target_big_endian
)
3217 imm2
= inst
.operands
[1].imm
;
3221 pool
= find_or_make_literal_pool ();
3223 /* Check if this literal value is already in the pool. */
3224 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3228 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3229 && (inst
.reloc
.exp
.X_op
== O_constant
)
3230 && (pool
->literals
[entry
].X_add_number
3231 == inst
.reloc
.exp
.X_add_number
)
3232 && (pool
->literals
[entry
].X_md
== nbytes
)
3233 && (pool
->literals
[entry
].X_unsigned
3234 == inst
.reloc
.exp
.X_unsigned
))
3237 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3238 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3239 && (pool
->literals
[entry
].X_add_number
3240 == inst
.reloc
.exp
.X_add_number
)
3241 && (pool
->literals
[entry
].X_add_symbol
3242 == inst
.reloc
.exp
.X_add_symbol
)
3243 && (pool
->literals
[entry
].X_op_symbol
3244 == inst
.reloc
.exp
.X_op_symbol
)
3245 && (pool
->literals
[entry
].X_md
== nbytes
))
3248 else if ((nbytes
== 8)
3249 && !(pool_size
& 0x7)
3250 && ((entry
+ 1) != pool
->next_free_entry
)
3251 && (pool
->literals
[entry
].X_op
== O_constant
)
3252 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3253 && (pool
->literals
[entry
].X_unsigned
3254 == inst
.reloc
.exp
.X_unsigned
)
3255 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3256 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3257 && (pool
->literals
[entry
+ 1].X_unsigned
3258 == inst
.reloc
.exp
.X_unsigned
))
3261 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3262 if (padding_slot_p
&& (nbytes
== 4))
3268 /* Do we need to create a new entry? */
3269 if (entry
== pool
->next_free_entry
)
3271 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3273 inst
.error
= _("literal pool overflow");
3279 /* For 8-byte entries, we align to an 8-byte boundary,
3280 and split it into two 4-byte entries, because on 32-bit
3281 host, 8-byte constants are treated as big num, thus
3282 saved in "generic_bignum" which will be overwritten
3283 by later assignments.
3285 We also need to make sure there is enough space for
3288 We also check to make sure the literal operand is a
3290 if (!(inst
.reloc
.exp
.X_op
== O_constant
3291 || inst
.reloc
.exp
.X_op
== O_big
))
3293 inst
.error
= _("invalid type for literal pool");
3296 else if (pool_size
& 0x7)
3298 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3300 inst
.error
= _("literal pool overflow");
3304 pool
->literals
[entry
] = inst
.reloc
.exp
;
3305 pool
->literals
[entry
].X_op
= O_constant
;
3306 pool
->literals
[entry
].X_add_number
= 0;
3307 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3308 pool
->next_free_entry
+= 1;
3311 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3313 inst
.error
= _("literal pool overflow");
3317 pool
->literals
[entry
] = inst
.reloc
.exp
;
3318 pool
->literals
[entry
].X_op
= O_constant
;
3319 pool
->literals
[entry
].X_add_number
= imm1
;
3320 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3321 pool
->literals
[entry
++].X_md
= 4;
3322 pool
->literals
[entry
] = inst
.reloc
.exp
;
3323 pool
->literals
[entry
].X_op
= O_constant
;
3324 pool
->literals
[entry
].X_add_number
= imm2
;
3325 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3326 pool
->literals
[entry
].X_md
= 4;
3327 pool
->alignment
= 3;
3328 pool
->next_free_entry
+= 1;
3332 pool
->literals
[entry
] = inst
.reloc
.exp
;
3333 pool
->literals
[entry
].X_md
= 4;
3337 /* PR ld/12974: Record the location of the first source line to reference
3338 this entry in the literal pool. If it turns out during linking that the
3339 symbol does not exist we will be able to give an accurate line number for
3340 the (first use of the) missing reference. */
3341 if (debug_type
== DEBUG_DWARF2
)
3342 dwarf2_where (pool
->locs
+ entry
);
3344 pool
->next_free_entry
+= 1;
3346 else if (padding_slot_p
)
3348 pool
->literals
[entry
] = inst
.reloc
.exp
;
3349 pool
->literals
[entry
].X_md
= nbytes
;
3352 inst
.reloc
.exp
.X_op
= O_symbol
;
3353 inst
.reloc
.exp
.X_add_number
= pool_size
;
3354 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3360 tc_start_label_without_colon (void)
3362 bfd_boolean ret
= TRUE
;
3364 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3366 const char *label
= input_line_pointer
;
3368 while (!is_end_of_line
[(int) label
[-1]])
3373 as_bad (_("Invalid label '%s'"), label
);
3377 asmfunc_debug (label
);
3379 asmfunc_state
= WAITING_ENDASMFUNC
;
3385 /* Can't use symbol_new here, so have to create a symbol and then at
3386 a later date assign it a value. That's what these functions do. */
3389 symbol_locate (symbolS
* symbolP
,
3390 const char * name
, /* It is copied, the caller can modify. */
3391 segT segment
, /* Segment identifier (SEG_<something>). */
3392 valueT valu
, /* Symbol value. */
3393 fragS
* frag
) /* Associated fragment. */
3396 char * preserved_copy_of_name
;
3398 name_length
= strlen (name
) + 1; /* +1 for \0. */
3399 obstack_grow (¬es
, name
, name_length
);
3400 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3402 #ifdef tc_canonicalize_symbol_name
3403 preserved_copy_of_name
=
3404 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3407 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3409 S_SET_SEGMENT (symbolP
, segment
);
3410 S_SET_VALUE (symbolP
, valu
);
3411 symbol_clear_list_pointers (symbolP
);
3413 symbol_set_frag (symbolP
, frag
);
3415 /* Link to end of symbol chain. */
3417 extern int symbol_table_frozen
;
3419 if (symbol_table_frozen
)
3423 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3425 obj_symbol_new_hook (symbolP
);
3427 #ifdef tc_symbol_new_hook
3428 tc_symbol_new_hook (symbolP
);
3432 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3433 #endif /* DEBUG_SYMS */
3437 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3440 literal_pool
* pool
;
3443 pool
= find_literal_pool ();
3445 || pool
->symbol
== NULL
3446 || pool
->next_free_entry
== 0)
3449 /* Align pool as you have word accesses.
3450 Only make a frag if we have to. */
3452 frag_align (pool
->alignment
, 0, 0);
3454 record_alignment (now_seg
, 2);
3457 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3458 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3460 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3462 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3463 (valueT
) frag_now_fix (), frag_now
);
3464 symbol_table_insert (pool
->symbol
);
3466 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3468 #if defined OBJ_COFF || defined OBJ_ELF
3469 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3472 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3475 if (debug_type
== DEBUG_DWARF2
)
3476 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3478 /* First output the expression in the instruction to the pool. */
3479 emit_expr (&(pool
->literals
[entry
]),
3480 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3483 /* Mark the pool as empty. */
3484 pool
->next_free_entry
= 0;
3485 pool
->symbol
= NULL
;
3489 /* Forward declarations for functions below, in the MD interface
3491 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3492 static valueT
create_unwind_entry (int);
3493 static void start_unwind_section (const segT
, int);
3494 static void add_unwind_opcode (valueT
, int);
3495 static void flush_pending_unwind (void);
3497 /* Directives: Data. */
3500 s_arm_elf_cons (int nbytes
)
3504 #ifdef md_flush_pending_output
3505 md_flush_pending_output ();
3508 if (is_it_end_of_statement ())
3510 demand_empty_rest_of_line ();
3514 #ifdef md_cons_align
3515 md_cons_align (nbytes
);
3518 mapping_state (MAP_DATA
);
3522 char *base
= input_line_pointer
;
3526 if (exp
.X_op
!= O_symbol
)
3527 emit_expr (&exp
, (unsigned int) nbytes
);
3530 char *before_reloc
= input_line_pointer
;
3531 reloc
= parse_reloc (&input_line_pointer
);
3534 as_bad (_("unrecognized relocation suffix"));
3535 ignore_rest_of_line ();
3538 else if (reloc
== BFD_RELOC_UNUSED
)
3539 emit_expr (&exp
, (unsigned int) nbytes
);
3542 reloc_howto_type
*howto
= (reloc_howto_type
*)
3543 bfd_reloc_type_lookup (stdoutput
,
3544 (bfd_reloc_code_real_type
) reloc
);
3545 int size
= bfd_get_reloc_size (howto
);
3547 if (reloc
== BFD_RELOC_ARM_PLT32
)
3549 as_bad (_("(plt) is only valid on branch targets"));
3550 reloc
= BFD_RELOC_UNUSED
;
3555 as_bad (ngettext ("%s relocations do not fit in %d byte",
3556 "%s relocations do not fit in %d bytes",
3558 howto
->name
, nbytes
);
3561 /* We've parsed an expression stopping at O_symbol.
3562 But there may be more expression left now that we
3563 have parsed the relocation marker. Parse it again.
3564 XXX Surely there is a cleaner way to do this. */
3565 char *p
= input_line_pointer
;
3567 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3569 memcpy (save_buf
, base
, input_line_pointer
- base
);
3570 memmove (base
+ (input_line_pointer
- before_reloc
),
3571 base
, before_reloc
- base
);
3573 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3575 memcpy (base
, save_buf
, p
- base
);
3577 offset
= nbytes
- size
;
3578 p
= frag_more (nbytes
);
3579 memset (p
, 0, nbytes
);
3580 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3581 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3587 while (*input_line_pointer
++ == ',');
3589 /* Put terminator back into stream. */
3590 input_line_pointer
--;
3591 demand_empty_rest_of_line ();
3594 /* Emit an expression containing a 32-bit thumb instruction.
3595 Implementation based on put_thumb32_insn. */
3598 emit_thumb32_expr (expressionS
* exp
)
3600 expressionS exp_high
= *exp
;
3602 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3603 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3604 exp
->X_add_number
&= 0xffff;
3605 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3608 /* Guess the instruction size based on the opcode. */
3611 thumb_insn_size (int opcode
)
3613 if ((unsigned int) opcode
< 0xe800u
)
3615 else if ((unsigned int) opcode
>= 0xe8000000u
)
3622 emit_insn (expressionS
*exp
, int nbytes
)
3626 if (exp
->X_op
== O_constant
)
3631 size
= thumb_insn_size (exp
->X_add_number
);
3635 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3637 as_bad (_(".inst.n operand too big. "\
3638 "Use .inst.w instead"));
3643 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3644 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3646 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3648 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3649 emit_thumb32_expr (exp
);
3651 emit_expr (exp
, (unsigned int) size
);
3653 it_fsm_post_encode ();
3657 as_bad (_("cannot determine Thumb instruction size. " \
3658 "Use .inst.n/.inst.w instead"));
3661 as_bad (_("constant expression required"));
3666 /* Like s_arm_elf_cons but do not use md_cons_align and
3667 set the mapping state to MAP_ARM/MAP_THUMB. */
3670 s_arm_elf_inst (int nbytes
)
3672 if (is_it_end_of_statement ())
3674 demand_empty_rest_of_line ();
3678 /* Calling mapping_state () here will not change ARM/THUMB,
3679 but will ensure not to be in DATA state. */
3682 mapping_state (MAP_THUMB
);
3687 as_bad (_("width suffixes are invalid in ARM mode"));
3688 ignore_rest_of_line ();
3694 mapping_state (MAP_ARM
);
3703 if (! emit_insn (& exp
, nbytes
))
3705 ignore_rest_of_line ();
3709 while (*input_line_pointer
++ == ',');
3711 /* Put terminator back into stream. */
3712 input_line_pointer
--;
3713 demand_empty_rest_of_line ();
3716 /* Parse a .rel31 directive. */
3719 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3726 if (*input_line_pointer
== '1')
3727 highbit
= 0x80000000;
3728 else if (*input_line_pointer
!= '0')
3729 as_bad (_("expected 0 or 1"));
3731 input_line_pointer
++;
3732 if (*input_line_pointer
!= ',')
3733 as_bad (_("missing comma"));
3734 input_line_pointer
++;
3736 #ifdef md_flush_pending_output
3737 md_flush_pending_output ();
3740 #ifdef md_cons_align
3744 mapping_state (MAP_DATA
);
3749 md_number_to_chars (p
, highbit
, 4);
3750 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3751 BFD_RELOC_ARM_PREL31
);
3753 demand_empty_rest_of_line ();
3756 /* Directives: AEABI stack-unwind tables. */
3758 /* Parse an unwind_fnstart directive. Simply records the current location. */
3761 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3763 demand_empty_rest_of_line ();
3764 if (unwind
.proc_start
)
3766 as_bad (_("duplicate .fnstart directive"));
3770 /* Mark the start of the function. */
3771 unwind
.proc_start
= expr_build_dot ();
3773 /* Reset the rest of the unwind info. */
3774 unwind
.opcode_count
= 0;
3775 unwind
.table_entry
= NULL
;
3776 unwind
.personality_routine
= NULL
;
3777 unwind
.personality_index
= -1;
3778 unwind
.frame_size
= 0;
3779 unwind
.fp_offset
= 0;
3780 unwind
.fp_reg
= REG_SP
;
3782 unwind
.sp_restored
= 0;
3786 /* Parse a handlerdata directive. Creates the exception handling table entry
3787 for the function. */
3790 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3792 demand_empty_rest_of_line ();
3793 if (!unwind
.proc_start
)
3794 as_bad (MISSING_FNSTART
);
3796 if (unwind
.table_entry
)
3797 as_bad (_("duplicate .handlerdata directive"));
3799 create_unwind_entry (1);
3802 /* Parse an unwind_fnend directive. Generates the index table entry. */
3805 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3810 unsigned int marked_pr_dependency
;
3812 demand_empty_rest_of_line ();
3814 if (!unwind
.proc_start
)
3816 as_bad (_(".fnend directive without .fnstart"));
3820 /* Add eh table entry. */
3821 if (unwind
.table_entry
== NULL
)
3822 val
= create_unwind_entry (0);
3826 /* Add index table entry. This is two words. */
3827 start_unwind_section (unwind
.saved_seg
, 1);
3828 frag_align (2, 0, 0);
3829 record_alignment (now_seg
, 2);
3831 ptr
= frag_more (8);
3833 where
= frag_now_fix () - 8;
3835 /* Self relative offset of the function start. */
3836 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3837 BFD_RELOC_ARM_PREL31
);
3839 /* Indicate dependency on EHABI-defined personality routines to the
3840 linker, if it hasn't been done already. */
3841 marked_pr_dependency
3842 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3843 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3844 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3846 static const char *const name
[] =
3848 "__aeabi_unwind_cpp_pr0",
3849 "__aeabi_unwind_cpp_pr1",
3850 "__aeabi_unwind_cpp_pr2"
3852 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3853 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3854 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3855 |= 1 << unwind
.personality_index
;
3859 /* Inline exception table entry. */
3860 md_number_to_chars (ptr
+ 4, val
, 4);
3862 /* Self relative offset of the table entry. */
3863 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3864 BFD_RELOC_ARM_PREL31
);
3866 /* Restore the original section. */
3867 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3869 unwind
.proc_start
= NULL
;
3873 /* Parse an unwind_cantunwind directive. */
3876 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3878 demand_empty_rest_of_line ();
3879 if (!unwind
.proc_start
)
3880 as_bad (MISSING_FNSTART
);
3882 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3883 as_bad (_("personality routine specified for cantunwind frame"));
3885 unwind
.personality_index
= -2;
3889 /* Parse a personalityindex directive. */
3892 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3896 if (!unwind
.proc_start
)
3897 as_bad (MISSING_FNSTART
);
3899 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3900 as_bad (_("duplicate .personalityindex directive"));
3904 if (exp
.X_op
!= O_constant
3905 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3907 as_bad (_("bad personality routine number"));
3908 ignore_rest_of_line ();
3912 unwind
.personality_index
= exp
.X_add_number
;
3914 demand_empty_rest_of_line ();
3918 /* Parse a personality directive. */
3921 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3925 if (!unwind
.proc_start
)
3926 as_bad (MISSING_FNSTART
);
3928 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3929 as_bad (_("duplicate .personality directive"));
3931 c
= get_symbol_name (& name
);
3932 p
= input_line_pointer
;
3934 ++ input_line_pointer
;
3935 unwind
.personality_routine
= symbol_find_or_make (name
);
3937 demand_empty_rest_of_line ();
3941 /* Parse a directive saving core registers. */
3944 s_arm_unwind_save_core (void)
3950 range
= parse_reg_list (&input_line_pointer
);
3953 as_bad (_("expected register list"));
3954 ignore_rest_of_line ();
3958 demand_empty_rest_of_line ();
3960 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3961 into .unwind_save {..., sp...}. We aren't bothered about the value of
3962 ip because it is clobbered by calls. */
3963 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3964 && (range
& 0x3000) == 0x1000)
3966 unwind
.opcode_count
--;
3967 unwind
.sp_restored
= 0;
3968 range
= (range
| 0x2000) & ~0x1000;
3969 unwind
.pending_offset
= 0;
3975 /* See if we can use the short opcodes. These pop a block of up to 8
3976 registers starting with r4, plus maybe r14. */
3977 for (n
= 0; n
< 8; n
++)
3979 /* Break at the first non-saved register. */
3980 if ((range
& (1 << (n
+ 4))) == 0)
3983 /* See if there are any other bits set. */
3984 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3986 /* Use the long form. */
3987 op
= 0x8000 | ((range
>> 4) & 0xfff);
3988 add_unwind_opcode (op
, 2);
3992 /* Use the short form. */
3994 op
= 0xa8; /* Pop r14. */
3996 op
= 0xa0; /* Do not pop r14. */
3998 add_unwind_opcode (op
, 1);
4005 op
= 0xb100 | (range
& 0xf);
4006 add_unwind_opcode (op
, 2);
4009 /* Record the number of bytes pushed. */
4010 for (n
= 0; n
< 16; n
++)
4012 if (range
& (1 << n
))
4013 unwind
.frame_size
+= 4;
4018 /* Parse a directive saving FPA registers. */
4021 s_arm_unwind_save_fpa (int reg
)
4027 /* Get Number of registers to transfer. */
4028 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4031 exp
.X_op
= O_illegal
;
4033 if (exp
.X_op
!= O_constant
)
4035 as_bad (_("expected , <constant>"));
4036 ignore_rest_of_line ();
4040 num_regs
= exp
.X_add_number
;
4042 if (num_regs
< 1 || num_regs
> 4)
4044 as_bad (_("number of registers must be in the range [1:4]"));
4045 ignore_rest_of_line ();
4049 demand_empty_rest_of_line ();
4054 op
= 0xb4 | (num_regs
- 1);
4055 add_unwind_opcode (op
, 1);
4060 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4061 add_unwind_opcode (op
, 2);
4063 unwind
.frame_size
+= num_regs
* 12;
4067 /* Parse a directive saving VFP registers for ARMv6 and above. */
4070 s_arm_unwind_save_vfp_armv6 (void)
4075 int num_vfpv3_regs
= 0;
4076 int num_regs_below_16
;
4078 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4081 as_bad (_("expected register list"));
4082 ignore_rest_of_line ();
4086 demand_empty_rest_of_line ();
4088 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4089 than FSTMX/FLDMX-style ones). */
4091 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4093 num_vfpv3_regs
= count
;
4094 else if (start
+ count
> 16)
4095 num_vfpv3_regs
= start
+ count
- 16;
4097 if (num_vfpv3_regs
> 0)
4099 int start_offset
= start
> 16 ? start
- 16 : 0;
4100 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4101 add_unwind_opcode (op
, 2);
4104 /* Generate opcode for registers numbered in the range 0 .. 15. */
4105 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4106 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4107 if (num_regs_below_16
> 0)
4109 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4110 add_unwind_opcode (op
, 2);
4113 unwind
.frame_size
+= count
* 8;
4117 /* Parse a directive saving VFP registers for pre-ARMv6. */
4120 s_arm_unwind_save_vfp (void)
4126 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4129 as_bad (_("expected register list"));
4130 ignore_rest_of_line ();
4134 demand_empty_rest_of_line ();
4139 op
= 0xb8 | (count
- 1);
4140 add_unwind_opcode (op
, 1);
4145 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4146 add_unwind_opcode (op
, 2);
4148 unwind
.frame_size
+= count
* 8 + 4;
4152 /* Parse a directive saving iWMMXt data registers. */
4155 s_arm_unwind_save_mmxwr (void)
4163 if (*input_line_pointer
== '{')
4164 input_line_pointer
++;
4168 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4172 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4177 as_tsktsk (_("register list not in ascending order"));
4180 if (*input_line_pointer
== '-')
4182 input_line_pointer
++;
4183 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4186 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4189 else if (reg
>= hi_reg
)
4191 as_bad (_("bad register range"));
4194 for (; reg
< hi_reg
; reg
++)
4198 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4200 skip_past_char (&input_line_pointer
, '}');
4202 demand_empty_rest_of_line ();
4204 /* Generate any deferred opcodes because we're going to be looking at
4206 flush_pending_unwind ();
4208 for (i
= 0; i
< 16; i
++)
4210 if (mask
& (1 << i
))
4211 unwind
.frame_size
+= 8;
4214 /* Attempt to combine with a previous opcode. We do this because gcc
4215 likes to output separate unwind directives for a single block of
4217 if (unwind
.opcode_count
> 0)
4219 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4220 if ((i
& 0xf8) == 0xc0)
4223 /* Only merge if the blocks are contiguous. */
4226 if ((mask
& 0xfe00) == (1 << 9))
4228 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4229 unwind
.opcode_count
--;
4232 else if (i
== 6 && unwind
.opcode_count
>= 2)
4234 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4238 op
= 0xffff << (reg
- 1);
4240 && ((mask
& op
) == (1u << (reg
- 1))))
4242 op
= (1 << (reg
+ i
+ 1)) - 1;
4243 op
&= ~((1 << reg
) - 1);
4245 unwind
.opcode_count
-= 2;
4252 /* We want to generate opcodes in the order the registers have been
4253 saved, ie. descending order. */
4254 for (reg
= 15; reg
>= -1; reg
--)
4256 /* Save registers in blocks. */
4258 || !(mask
& (1 << reg
)))
4260 /* We found an unsaved reg. Generate opcodes to save the
4267 op
= 0xc0 | (hi_reg
- 10);
4268 add_unwind_opcode (op
, 1);
4273 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4274 add_unwind_opcode (op
, 2);
4283 ignore_rest_of_line ();
4287 s_arm_unwind_save_mmxwcg (void)
4294 if (*input_line_pointer
== '{')
4295 input_line_pointer
++;
4297 skip_whitespace (input_line_pointer
);
4301 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4305 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4311 as_tsktsk (_("register list not in ascending order"));
4314 if (*input_line_pointer
== '-')
4316 input_line_pointer
++;
4317 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4320 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4323 else if (reg
>= hi_reg
)
4325 as_bad (_("bad register range"));
4328 for (; reg
< hi_reg
; reg
++)
4332 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4334 skip_past_char (&input_line_pointer
, '}');
4336 demand_empty_rest_of_line ();
4338 /* Generate any deferred opcodes because we're going to be looking at
4340 flush_pending_unwind ();
4342 for (reg
= 0; reg
< 16; reg
++)
4344 if (mask
& (1 << reg
))
4345 unwind
.frame_size
+= 4;
4348 add_unwind_opcode (op
, 2);
4351 ignore_rest_of_line ();
4355 /* Parse an unwind_save directive.
4356 If the argument is non-zero, this is a .vsave directive. */
4359 s_arm_unwind_save (int arch_v6
)
4362 struct reg_entry
*reg
;
4363 bfd_boolean had_brace
= FALSE
;
4365 if (!unwind
.proc_start
)
4366 as_bad (MISSING_FNSTART
);
4368 /* Figure out what sort of save we have. */
4369 peek
= input_line_pointer
;
4377 reg
= arm_reg_parse_multi (&peek
);
4381 as_bad (_("register expected"));
4382 ignore_rest_of_line ();
4391 as_bad (_("FPA .unwind_save does not take a register list"));
4392 ignore_rest_of_line ();
4395 input_line_pointer
= peek
;
4396 s_arm_unwind_save_fpa (reg
->number
);
4400 s_arm_unwind_save_core ();
4405 s_arm_unwind_save_vfp_armv6 ();
4407 s_arm_unwind_save_vfp ();
4410 case REG_TYPE_MMXWR
:
4411 s_arm_unwind_save_mmxwr ();
4414 case REG_TYPE_MMXWCG
:
4415 s_arm_unwind_save_mmxwcg ();
4419 as_bad (_(".unwind_save does not support this kind of register"));
4420 ignore_rest_of_line ();
4425 /* Parse an unwind_movsp directive. */
4428 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4434 if (!unwind
.proc_start
)
4435 as_bad (MISSING_FNSTART
);
4437 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4440 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4441 ignore_rest_of_line ();
4445 /* Optional constant. */
4446 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4448 if (immediate_for_directive (&offset
) == FAIL
)
4454 demand_empty_rest_of_line ();
4456 if (reg
== REG_SP
|| reg
== REG_PC
)
4458 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4462 if (unwind
.fp_reg
!= REG_SP
)
4463 as_bad (_("unexpected .unwind_movsp directive"));
4465 /* Generate opcode to restore the value. */
4467 add_unwind_opcode (op
, 1);
4469 /* Record the information for later. */
4470 unwind
.fp_reg
= reg
;
4471 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4472 unwind
.sp_restored
= 1;
4475 /* Parse an unwind_pad directive. */
4478 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4482 if (!unwind
.proc_start
)
4483 as_bad (MISSING_FNSTART
);
4485 if (immediate_for_directive (&offset
) == FAIL
)
4490 as_bad (_("stack increment must be multiple of 4"));
4491 ignore_rest_of_line ();
4495 /* Don't generate any opcodes, just record the details for later. */
4496 unwind
.frame_size
+= offset
;
4497 unwind
.pending_offset
+= offset
;
4499 demand_empty_rest_of_line ();
4502 /* Parse an unwind_setfp directive. */
4505 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4511 if (!unwind
.proc_start
)
4512 as_bad (MISSING_FNSTART
);
4514 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4515 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4518 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4520 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4522 as_bad (_("expected <reg>, <reg>"));
4523 ignore_rest_of_line ();
4527 /* Optional constant. */
4528 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4530 if (immediate_for_directive (&offset
) == FAIL
)
4536 demand_empty_rest_of_line ();
4538 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4540 as_bad (_("register must be either sp or set by a previous"
4541 "unwind_movsp directive"));
4545 /* Don't generate any opcodes, just record the information for later. */
4546 unwind
.fp_reg
= fp_reg
;
4548 if (sp_reg
== REG_SP
)
4549 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4551 unwind
.fp_offset
-= offset
;
4554 /* Parse an unwind_raw directive. */
4557 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4560 /* This is an arbitrary limit. */
4561 unsigned char op
[16];
4564 if (!unwind
.proc_start
)
4565 as_bad (MISSING_FNSTART
);
4568 if (exp
.X_op
== O_constant
4569 && skip_past_comma (&input_line_pointer
) != FAIL
)
4571 unwind
.frame_size
+= exp
.X_add_number
;
4575 exp
.X_op
= O_illegal
;
4577 if (exp
.X_op
!= O_constant
)
4579 as_bad (_("expected <offset>, <opcode>"));
4580 ignore_rest_of_line ();
4586 /* Parse the opcode. */
4591 as_bad (_("unwind opcode too long"));
4592 ignore_rest_of_line ();
4594 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4596 as_bad (_("invalid unwind opcode"));
4597 ignore_rest_of_line ();
4600 op
[count
++] = exp
.X_add_number
;
4602 /* Parse the next byte. */
4603 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4609 /* Add the opcode bytes in reverse order. */
4611 add_unwind_opcode (op
[count
], 1);
4613 demand_empty_rest_of_line ();
4617 /* Parse a .eabi_attribute directive. */
4620 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4622 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4624 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4625 attributes_set_explicitly
[tag
] = 1;
4628 /* Emit a tls fix for the symbol. */
4631 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4635 #ifdef md_flush_pending_output
4636 md_flush_pending_output ();
4639 #ifdef md_cons_align
4643 /* Since we're just labelling the code, there's no need to define a
4646 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4647 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4648 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4649 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4651 #endif /* OBJ_ELF */
4653 static void s_arm_arch (int);
4654 static void s_arm_object_arch (int);
4655 static void s_arm_cpu (int);
4656 static void s_arm_fpu (int);
4657 static void s_arm_arch_extension (int);
4662 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4669 if (exp
.X_op
== O_symbol
)
4670 exp
.X_op
= O_secrel
;
4672 emit_expr (&exp
, 4);
4674 while (*input_line_pointer
++ == ',');
4676 input_line_pointer
--;
4677 demand_empty_rest_of_line ();
4681 /* This table describes all the machine specific pseudo-ops the assembler
4682 has to support. The fields are:
4683 pseudo-op name without dot
4684 function to call to execute this pseudo-op
4685 Integer arg to pass to the function. */
4687 const pseudo_typeS md_pseudo_table
[] =
4689 /* Never called because '.req' does not start a line. */
4690 { "req", s_req
, 0 },
4691 /* Following two are likewise never called. */
4694 { "unreq", s_unreq
, 0 },
4695 { "bss", s_bss
, 0 },
4696 { "align", s_align_ptwo
, 2 },
4697 { "arm", s_arm
, 0 },
4698 { "thumb", s_thumb
, 0 },
4699 { "code", s_code
, 0 },
4700 { "force_thumb", s_force_thumb
, 0 },
4701 { "thumb_func", s_thumb_func
, 0 },
4702 { "thumb_set", s_thumb_set
, 0 },
4703 { "even", s_even
, 0 },
4704 { "ltorg", s_ltorg
, 0 },
4705 { "pool", s_ltorg
, 0 },
4706 { "syntax", s_syntax
, 0 },
4707 { "cpu", s_arm_cpu
, 0 },
4708 { "arch", s_arm_arch
, 0 },
4709 { "object_arch", s_arm_object_arch
, 0 },
4710 { "fpu", s_arm_fpu
, 0 },
4711 { "arch_extension", s_arm_arch_extension
, 0 },
4713 { "word", s_arm_elf_cons
, 4 },
4714 { "long", s_arm_elf_cons
, 4 },
4715 { "inst.n", s_arm_elf_inst
, 2 },
4716 { "inst.w", s_arm_elf_inst
, 4 },
4717 { "inst", s_arm_elf_inst
, 0 },
4718 { "rel31", s_arm_rel31
, 0 },
4719 { "fnstart", s_arm_unwind_fnstart
, 0 },
4720 { "fnend", s_arm_unwind_fnend
, 0 },
4721 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4722 { "personality", s_arm_unwind_personality
, 0 },
4723 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4724 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4725 { "save", s_arm_unwind_save
, 0 },
4726 { "vsave", s_arm_unwind_save
, 1 },
4727 { "movsp", s_arm_unwind_movsp
, 0 },
4728 { "pad", s_arm_unwind_pad
, 0 },
4729 { "setfp", s_arm_unwind_setfp
, 0 },
4730 { "unwind_raw", s_arm_unwind_raw
, 0 },
4731 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4732 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4736 /* These are used for dwarf. */
4740 /* These are used for dwarf2. */
4741 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4742 { "loc", dwarf2_directive_loc
, 0 },
4743 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4745 { "extend", float_cons
, 'x' },
4746 { "ldouble", float_cons
, 'x' },
4747 { "packed", float_cons
, 'p' },
4749 {"secrel32", pe_directive_secrel
, 0},
4752 /* These are for compatibility with CodeComposer Studio. */
4753 {"ref", s_ccs_ref
, 0},
4754 {"def", s_ccs_def
, 0},
4755 {"asmfunc", s_ccs_asmfunc
, 0},
4756 {"endasmfunc", s_ccs_endasmfunc
, 0},
4761 /* Parser functions used exclusively in instruction operands. */
4763 /* Generic immediate-value read function for use in insn parsing.
4764 STR points to the beginning of the immediate (the leading #);
4765 VAL receives the value; if the value is outside [MIN, MAX]
4766 issue an error. PREFIX_OPT is true if the immediate prefix is
4770 parse_immediate (char **str
, int *val
, int min
, int max
,
4771 bfd_boolean prefix_opt
)
4774 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4775 if (exp
.X_op
!= O_constant
)
4777 inst
.error
= _("constant expression required");
4781 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4783 inst
.error
= _("immediate value out of range");
4787 *val
= exp
.X_add_number
;
4791 /* Less-generic immediate-value read function with the possibility of loading a
4792 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4793 instructions. Puts the result directly in inst.operands[i]. */
4796 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4797 bfd_boolean allow_symbol_p
)
4800 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4803 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4805 if (exp_p
->X_op
== O_constant
)
4807 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4808 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4809 O_constant. We have to be careful not to break compilation for
4810 32-bit X_add_number, though. */
4811 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4813 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4814 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4816 inst
.operands
[i
].regisimm
= 1;
4819 else if (exp_p
->X_op
== O_big
4820 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4822 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4824 /* Bignums have their least significant bits in
4825 generic_bignum[0]. Make sure we put 32 bits in imm and
4826 32 bits in reg, in a (hopefully) portable way. */
4827 gas_assert (parts
!= 0);
4829 /* Make sure that the number is not too big.
4830 PR 11972: Bignums can now be sign-extended to the
4831 size of a .octa so check that the out of range bits
4832 are all zero or all one. */
4833 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4835 LITTLENUM_TYPE m
= -1;
4837 if (generic_bignum
[parts
* 2] != 0
4838 && generic_bignum
[parts
* 2] != m
)
4841 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4842 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4846 inst
.operands
[i
].imm
= 0;
4847 for (j
= 0; j
< parts
; j
++, idx
++)
4848 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4849 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4850 inst
.operands
[i
].reg
= 0;
4851 for (j
= 0; j
< parts
; j
++, idx
++)
4852 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4853 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4854 inst
.operands
[i
].regisimm
= 1;
4856 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4864 /* Returns the pseudo-register number of an FPA immediate constant,
4865 or FAIL if there isn't a valid constant here. */
4868 parse_fpa_immediate (char ** str
)
4870 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4876 /* First try and match exact strings, this is to guarantee
4877 that some formats will work even for cross assembly. */
4879 for (i
= 0; fp_const
[i
]; i
++)
4881 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4885 *str
+= strlen (fp_const
[i
]);
4886 if (is_end_of_line
[(unsigned char) **str
])
4892 /* Just because we didn't get a match doesn't mean that the constant
4893 isn't valid, just that it is in a format that we don't
4894 automatically recognize. Try parsing it with the standard
4895 expression routines. */
4897 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4899 /* Look for a raw floating point number. */
4900 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4901 && is_end_of_line
[(unsigned char) *save_in
])
4903 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4905 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4907 if (words
[j
] != fp_values
[i
][j
])
4911 if (j
== MAX_LITTLENUMS
)
4919 /* Try and parse a more complex expression, this will probably fail
4920 unless the code uses a floating point prefix (eg "0f"). */
4921 save_in
= input_line_pointer
;
4922 input_line_pointer
= *str
;
4923 if (expression (&exp
) == absolute_section
4924 && exp
.X_op
== O_big
4925 && exp
.X_add_number
< 0)
4927 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4929 #define X_PRECISION 5
4930 #define E_PRECISION 15L
4931 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4933 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4935 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4937 if (words
[j
] != fp_values
[i
][j
])
4941 if (j
== MAX_LITTLENUMS
)
4943 *str
= input_line_pointer
;
4944 input_line_pointer
= save_in
;
4951 *str
= input_line_pointer
;
4952 input_line_pointer
= save_in
;
4953 inst
.error
= _("invalid FPA immediate expression");
4957 /* Returns 1 if a number has "quarter-precision" float format
4958 0baBbbbbbc defgh000 00000000 00000000. */
4961 is_quarter_float (unsigned imm
)
4963 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4964 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4968 /* Detect the presence of a floating point or integer zero constant,
4972 parse_ifimm_zero (char **in
)
4976 if (!is_immediate_prefix (**in
))
4978 /* In unified syntax, all prefixes are optional. */
4979 if (!unified_syntax
)
4985 /* Accept #0x0 as a synonym for #0. */
4986 if (strncmp (*in
, "0x", 2) == 0)
4989 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4994 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4995 &generic_floating_point_number
);
4998 && generic_floating_point_number
.sign
== '+'
4999 && (generic_floating_point_number
.low
5000 > generic_floating_point_number
.leader
))
5006 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5007 0baBbbbbbc defgh000 00000000 00000000.
5008 The zero and minus-zero cases need special handling, since they can't be
5009 encoded in the "quarter-precision" float format, but can nonetheless be
5010 loaded as integer constants. */
5013 parse_qfloat_immediate (char **ccp
, int *immed
)
5017 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5018 int found_fpchar
= 0;
5020 skip_past_char (&str
, '#');
5022 /* We must not accidentally parse an integer as a floating-point number. Make
5023 sure that the value we parse is not an integer by checking for special
5024 characters '.' or 'e'.
5025 FIXME: This is a horrible hack, but doing better is tricky because type
5026 information isn't in a very usable state at parse time. */
5028 skip_whitespace (fpnum
);
5030 if (strncmp (fpnum
, "0x", 2) == 0)
5034 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5035 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5045 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5047 unsigned fpword
= 0;
5050 /* Our FP word must be 32 bits (single-precision FP). */
5051 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5053 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5057 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5070 /* Shift operands. */
5073 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5076 struct asm_shift_name
5079 enum shift_kind kind
;
5082 /* Third argument to parse_shift. */
5083 enum parse_shift_mode
5085 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5086 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5087 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5088 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5089 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5092 /* Parse a <shift> specifier on an ARM data processing instruction.
5093 This has three forms:
5095 (LSL|LSR|ASL|ASR|ROR) Rs
5096 (LSL|LSR|ASL|ASR|ROR) #imm
5099 Note that ASL is assimilated to LSL in the instruction encoding, and
5100 RRX to ROR #0 (which cannot be written as such). */
5103 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5105 const struct asm_shift_name
*shift_name
;
5106 enum shift_kind shift
;
5111 for (p
= *str
; ISALPHA (*p
); p
++)
5116 inst
.error
= _("shift expression expected");
5120 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5123 if (shift_name
== NULL
)
5125 inst
.error
= _("shift expression expected");
5129 shift
= shift_name
->kind
;
5133 case NO_SHIFT_RESTRICT
:
5134 case SHIFT_IMMEDIATE
: break;
5136 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5137 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5139 inst
.error
= _("'LSL' or 'ASR' required");
5144 case SHIFT_LSL_IMMEDIATE
:
5145 if (shift
!= SHIFT_LSL
)
5147 inst
.error
= _("'LSL' required");
5152 case SHIFT_ASR_IMMEDIATE
:
5153 if (shift
!= SHIFT_ASR
)
5155 inst
.error
= _("'ASR' required");
5163 if (shift
!= SHIFT_RRX
)
5165 /* Whitespace can appear here if the next thing is a bare digit. */
5166 skip_whitespace (p
);
5168 if (mode
== NO_SHIFT_RESTRICT
5169 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5171 inst
.operands
[i
].imm
= reg
;
5172 inst
.operands
[i
].immisreg
= 1;
5174 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5177 inst
.operands
[i
].shift_kind
= shift
;
5178 inst
.operands
[i
].shifted
= 1;
5183 /* Parse a <shifter_operand> for an ARM data processing instruction:
5186 #<immediate>, <rotate>
5190 where <shift> is defined by parse_shift above, and <rotate> is a
5191 multiple of 2 between 0 and 30. Validation of immediate operands
5192 is deferred to md_apply_fix. */
5195 parse_shifter_operand (char **str
, int i
)
5200 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5202 inst
.operands
[i
].reg
= value
;
5203 inst
.operands
[i
].isreg
= 1;
5205 /* parse_shift will override this if appropriate */
5206 inst
.reloc
.exp
.X_op
= O_constant
;
5207 inst
.reloc
.exp
.X_add_number
= 0;
5209 if (skip_past_comma (str
) == FAIL
)
5212 /* Shift operation on register. */
5213 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5216 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5219 if (skip_past_comma (str
) == SUCCESS
)
5221 /* #x, y -- ie explicit rotation by Y. */
5222 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5225 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5227 inst
.error
= _("constant expression expected");
5231 value
= exp
.X_add_number
;
5232 if (value
< 0 || value
> 30 || value
% 2 != 0)
5234 inst
.error
= _("invalid rotation");
5237 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5239 inst
.error
= _("invalid constant");
5243 /* Encode as specified. */
5244 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5248 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5249 inst
.reloc
.pc_rel
= 0;
5253 /* Group relocation information. Each entry in the table contains the
5254 textual name of the relocation as may appear in assembler source
5255 and must end with a colon.
5256 Along with this textual name are the relocation codes to be used if
5257 the corresponding instruction is an ALU instruction (ADD or SUB only),
5258 an LDR, an LDRS, or an LDC. */
5260 struct group_reloc_table_entry
5271 /* Varieties of non-ALU group relocation. */
5278 static struct group_reloc_table_entry group_reloc_table
[] =
5279 { /* Program counter relative: */
5281 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5286 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5287 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5288 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5289 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5291 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5296 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5297 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5298 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5299 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5301 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5302 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5303 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5304 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5305 /* Section base relative */
5307 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5312 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5313 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5314 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5315 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5317 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5322 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5323 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5324 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5325 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5327 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5328 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5329 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5330 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5331 /* Absolute thumb alu relocations. */
5333 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5338 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5343 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5348 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5353 /* Given the address of a pointer pointing to the textual name of a group
5354 relocation as may appear in assembler source, attempt to find its details
5355 in group_reloc_table. The pointer will be updated to the character after
5356 the trailing colon. On failure, FAIL will be returned; SUCCESS
5357 otherwise. On success, *entry will be updated to point at the relevant
5358 group_reloc_table entry. */
5361 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5364 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5366 int length
= strlen (group_reloc_table
[i
].name
);
5368 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5369 && (*str
)[length
] == ':')
5371 *out
= &group_reloc_table
[i
];
5372 *str
+= (length
+ 1);
5380 /* Parse a <shifter_operand> for an ARM data processing instruction
5381 (as for parse_shifter_operand) where group relocations are allowed:
5384 #<immediate>, <rotate>
5385 #:<group_reloc>:<expression>
5389 where <group_reloc> is one of the strings defined in group_reloc_table.
5390 The hashes are optional.
5392 Everything else is as for parse_shifter_operand. */
5394 static parse_operand_result
5395 parse_shifter_operand_group_reloc (char **str
, int i
)
5397 /* Determine if we have the sequence of characters #: or just :
5398 coming next. If we do, then we check for a group relocation.
5399 If we don't, punt the whole lot to parse_shifter_operand. */
5401 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5402 || (*str
)[0] == ':')
5404 struct group_reloc_table_entry
*entry
;
5406 if ((*str
)[0] == '#')
5411 /* Try to parse a group relocation. Anything else is an error. */
5412 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5414 inst
.error
= _("unknown group relocation");
5415 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5418 /* We now have the group relocation table entry corresponding to
5419 the name in the assembler source. Next, we parse the expression. */
5420 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5421 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5423 /* Record the relocation type (always the ALU variant here). */
5424 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5425 gas_assert (inst
.reloc
.type
!= 0);
5427 return PARSE_OPERAND_SUCCESS
;
5430 return parse_shifter_operand (str
, i
) == SUCCESS
5431 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5433 /* Never reached. */
5436 /* Parse a Neon alignment expression. Information is written to
5437 inst.operands[i]. We assume the initial ':' has been skipped.
5439 align .imm = align << 8, .immisalign=1, .preind=0 */
5440 static parse_operand_result
5441 parse_neon_alignment (char **str
, int i
)
5446 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5448 if (exp
.X_op
!= O_constant
)
5450 inst
.error
= _("alignment must be constant");
5451 return PARSE_OPERAND_FAIL
;
5454 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5455 inst
.operands
[i
].immisalign
= 1;
5456 /* Alignments are not pre-indexes. */
5457 inst
.operands
[i
].preind
= 0;
5460 return PARSE_OPERAND_SUCCESS
;
5463 /* Parse all forms of an ARM address expression. Information is written
5464 to inst.operands[i] and/or inst.reloc.
5466 Preindexed addressing (.preind=1):
5468 [Rn, #offset] .reg=Rn .reloc.exp=offset
5469 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5470 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5471 .shift_kind=shift .reloc.exp=shift_imm
5473 These three may have a trailing ! which causes .writeback to be set also.
5475 Postindexed addressing (.postind=1, .writeback=1):
5477 [Rn], #offset .reg=Rn .reloc.exp=offset
5478 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5479 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5480 .shift_kind=shift .reloc.exp=shift_imm
5482 Unindexed addressing (.preind=0, .postind=0):
5484 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5488 [Rn]{!} shorthand for [Rn,#0]{!}
5489 =immediate .isreg=0 .reloc.exp=immediate
5490 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5492 It is the caller's responsibility to check for addressing modes not
5493 supported by the instruction, and to set inst.reloc.type. */
5495 static parse_operand_result
5496 parse_address_main (char **str
, int i
, int group_relocations
,
5497 group_reloc_type group_type
)
5502 if (skip_past_char (&p
, '[') == FAIL
)
5504 if (skip_past_char (&p
, '=') == FAIL
)
5506 /* Bare address - translate to PC-relative offset. */
5507 inst
.reloc
.pc_rel
= 1;
5508 inst
.operands
[i
].reg
= REG_PC
;
5509 inst
.operands
[i
].isreg
= 1;
5510 inst
.operands
[i
].preind
= 1;
5512 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5513 return PARSE_OPERAND_FAIL
;
5515 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5516 /*allow_symbol_p=*/TRUE
))
5517 return PARSE_OPERAND_FAIL
;
5520 return PARSE_OPERAND_SUCCESS
;
5523 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5524 skip_whitespace (p
);
5526 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5528 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5529 return PARSE_OPERAND_FAIL
;
5531 inst
.operands
[i
].reg
= reg
;
5532 inst
.operands
[i
].isreg
= 1;
5534 if (skip_past_comma (&p
) == SUCCESS
)
5536 inst
.operands
[i
].preind
= 1;
5539 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5541 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5543 inst
.operands
[i
].imm
= reg
;
5544 inst
.operands
[i
].immisreg
= 1;
5546 if (skip_past_comma (&p
) == SUCCESS
)
5547 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5548 return PARSE_OPERAND_FAIL
;
5550 else if (skip_past_char (&p
, ':') == SUCCESS
)
5552 /* FIXME: '@' should be used here, but it's filtered out by generic
5553 code before we get to see it here. This may be subject to
5555 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5557 if (result
!= PARSE_OPERAND_SUCCESS
)
5562 if (inst
.operands
[i
].negative
)
5564 inst
.operands
[i
].negative
= 0;
5568 if (group_relocations
5569 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5571 struct group_reloc_table_entry
*entry
;
5573 /* Skip over the #: or : sequence. */
5579 /* Try to parse a group relocation. Anything else is an
5581 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5583 inst
.error
= _("unknown group relocation");
5584 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5587 /* We now have the group relocation table entry corresponding to
5588 the name in the assembler source. Next, we parse the
5590 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5591 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5593 /* Record the relocation type. */
5597 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5601 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5605 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5612 if (inst
.reloc
.type
== 0)
5614 inst
.error
= _("this group relocation is not allowed on this instruction");
5615 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5621 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5622 return PARSE_OPERAND_FAIL
;
5623 /* If the offset is 0, find out if it's a +0 or -0. */
5624 if (inst
.reloc
.exp
.X_op
== O_constant
5625 && inst
.reloc
.exp
.X_add_number
== 0)
5627 skip_whitespace (q
);
5631 skip_whitespace (q
);
5634 inst
.operands
[i
].negative
= 1;
5639 else if (skip_past_char (&p
, ':') == SUCCESS
)
5641 /* FIXME: '@' should be used here, but it's filtered out by generic code
5642 before we get to see it here. This may be subject to change. */
5643 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5645 if (result
!= PARSE_OPERAND_SUCCESS
)
5649 if (skip_past_char (&p
, ']') == FAIL
)
5651 inst
.error
= _("']' expected");
5652 return PARSE_OPERAND_FAIL
;
5655 if (skip_past_char (&p
, '!') == SUCCESS
)
5656 inst
.operands
[i
].writeback
= 1;
5658 else if (skip_past_comma (&p
) == SUCCESS
)
5660 if (skip_past_char (&p
, '{') == SUCCESS
)
5662 /* [Rn], {expr} - unindexed, with option */
5663 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5664 0, 255, TRUE
) == FAIL
)
5665 return PARSE_OPERAND_FAIL
;
5667 if (skip_past_char (&p
, '}') == FAIL
)
5669 inst
.error
= _("'}' expected at end of 'option' field");
5670 return PARSE_OPERAND_FAIL
;
5672 if (inst
.operands
[i
].preind
)
5674 inst
.error
= _("cannot combine index with option");
5675 return PARSE_OPERAND_FAIL
;
5678 return PARSE_OPERAND_SUCCESS
;
5682 inst
.operands
[i
].postind
= 1;
5683 inst
.operands
[i
].writeback
= 1;
5685 if (inst
.operands
[i
].preind
)
5687 inst
.error
= _("cannot combine pre- and post-indexing");
5688 return PARSE_OPERAND_FAIL
;
5692 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5694 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5696 /* We might be using the immediate for alignment already. If we
5697 are, OR the register number into the low-order bits. */
5698 if (inst
.operands
[i
].immisalign
)
5699 inst
.operands
[i
].imm
|= reg
;
5701 inst
.operands
[i
].imm
= reg
;
5702 inst
.operands
[i
].immisreg
= 1;
5704 if (skip_past_comma (&p
) == SUCCESS
)
5705 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5706 return PARSE_OPERAND_FAIL
;
5711 if (inst
.operands
[i
].negative
)
5713 inst
.operands
[i
].negative
= 0;
5716 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5717 return PARSE_OPERAND_FAIL
;
5718 /* If the offset is 0, find out if it's a +0 or -0. */
5719 if (inst
.reloc
.exp
.X_op
== O_constant
5720 && inst
.reloc
.exp
.X_add_number
== 0)
5722 skip_whitespace (q
);
5726 skip_whitespace (q
);
5729 inst
.operands
[i
].negative
= 1;
5735 /* If at this point neither .preind nor .postind is set, we have a
5736 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5737 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5739 inst
.operands
[i
].preind
= 1;
5740 inst
.reloc
.exp
.X_op
= O_constant
;
5741 inst
.reloc
.exp
.X_add_number
= 0;
5744 return PARSE_OPERAND_SUCCESS
;
5748 parse_address (char **str
, int i
)
5750 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5754 static parse_operand_result
5755 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5757 return parse_address_main (str
, i
, 1, type
);
5760 /* Parse an operand for a MOVW or MOVT instruction. */
5762 parse_half (char **str
)
5767 skip_past_char (&p
, '#');
5768 if (strncasecmp (p
, ":lower16:", 9) == 0)
5769 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5770 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5771 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5773 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5776 skip_whitespace (p
);
5779 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5782 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5784 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5786 inst
.error
= _("constant expression expected");
5789 if (inst
.reloc
.exp
.X_add_number
< 0
5790 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5792 inst
.error
= _("immediate value out of range");
5800 /* Miscellaneous. */
5802 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5803 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5805 parse_psr (char **str
, bfd_boolean lhs
)
5808 unsigned long psr_field
;
5809 const struct asm_psr
*psr
;
5811 bfd_boolean is_apsr
= FALSE
;
5812 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5814 /* PR gas/12698: If the user has specified -march=all then m_profile will
5815 be TRUE, but we want to ignore it in this case as we are building for any
5816 CPU type, including non-m variants. */
5817 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5820 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5821 feature for ease of use and backwards compatibility. */
5823 if (strncasecmp (p
, "SPSR", 4) == 0)
5826 goto unsupported_psr
;
5828 psr_field
= SPSR_BIT
;
5830 else if (strncasecmp (p
, "CPSR", 4) == 0)
5833 goto unsupported_psr
;
5837 else if (strncasecmp (p
, "APSR", 4) == 0)
5839 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5840 and ARMv7-R architecture CPUs. */
5849 while (ISALNUM (*p
) || *p
== '_');
5851 if (strncasecmp (start
, "iapsr", 5) == 0
5852 || strncasecmp (start
, "eapsr", 5) == 0
5853 || strncasecmp (start
, "xpsr", 4) == 0
5854 || strncasecmp (start
, "psr", 3) == 0)
5855 p
= start
+ strcspn (start
, "rR") + 1;
5857 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5863 /* If APSR is being written, a bitfield may be specified. Note that
5864 APSR itself is handled above. */
5865 if (psr
->field
<= 3)
5867 psr_field
= psr
->field
;
5873 /* M-profile MSR instructions have the mask field set to "10", except
5874 *PSR variants which modify APSR, which may use a different mask (and
5875 have been handled already). Do that by setting the PSR_f field
5877 return psr
->field
| (lhs
? PSR_f
: 0);
5880 goto unsupported_psr
;
5886 /* A suffix follows. */
5892 while (ISALNUM (*p
) || *p
== '_');
5896 /* APSR uses a notation for bits, rather than fields. */
5897 unsigned int nzcvq_bits
= 0;
5898 unsigned int g_bit
= 0;
5901 for (bit
= start
; bit
!= p
; bit
++)
5903 switch (TOLOWER (*bit
))
5906 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5910 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5914 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5918 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5922 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5926 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5930 inst
.error
= _("unexpected bit specified after APSR");
5935 if (nzcvq_bits
== 0x1f)
5940 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5942 inst
.error
= _("selected processor does not "
5943 "support DSP extension");
5950 if ((nzcvq_bits
& 0x20) != 0
5951 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5952 || (g_bit
& 0x2) != 0)
5954 inst
.error
= _("bad bitmask specified after APSR");
5960 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5965 psr_field
|= psr
->field
;
5971 goto error
; /* Garbage after "[CS]PSR". */
5973 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5974 is deprecated, but allow it anyway. */
5978 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5981 else if (!m_profile
)
5982 /* These bits are never right for M-profile devices: don't set them
5983 (only code paths which read/write APSR reach here). */
5984 psr_field
|= (PSR_c
| PSR_f
);
5990 inst
.error
= _("selected processor does not support requested special "
5991 "purpose register");
5995 inst
.error
= _("flag for {c}psr instruction expected");
5999 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6000 value suitable for splatting into the AIF field of the instruction. */
6003 parse_cps_flags (char **str
)
6012 case '\0': case ',':
6015 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6016 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6017 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6020 inst
.error
= _("unrecognized CPS flag");
6025 if (saw_a_flag
== 0)
6027 inst
.error
= _("missing CPS flags");
6035 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6036 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6039 parse_endian_specifier (char **str
)
6044 if (strncasecmp (s
, "BE", 2))
6046 else if (strncasecmp (s
, "LE", 2))
6050 inst
.error
= _("valid endian specifiers are be or le");
6054 if (ISALNUM (s
[2]) || s
[2] == '_')
6056 inst
.error
= _("valid endian specifiers are be or le");
6061 return little_endian
;
6064 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6065 value suitable for poking into the rotate field of an sxt or sxta
6066 instruction, or FAIL on error. */
6069 parse_ror (char **str
)
6074 if (strncasecmp (s
, "ROR", 3) == 0)
6078 inst
.error
= _("missing rotation field after comma");
6082 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6087 case 0: *str
= s
; return 0x0;
6088 case 8: *str
= s
; return 0x1;
6089 case 16: *str
= s
; return 0x2;
6090 case 24: *str
= s
; return 0x3;
6093 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6098 /* Parse a conditional code (from conds[] below). The value returned is in the
6099 range 0 .. 14, or FAIL. */
6101 parse_cond (char **str
)
6104 const struct asm_cond
*c
;
6106 /* Condition codes are always 2 characters, so matching up to
6107 3 characters is sufficient. */
6112 while (ISALPHA (*q
) && n
< 3)
6114 cond
[n
] = TOLOWER (*q
);
6119 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6122 inst
.error
= _("condition required");
6130 /* Record a use of the given feature. */
6132 record_feature_use (const arm_feature_set
*feature
)
6135 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6137 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6140 /* If the given feature available in the selected CPU, mark it as used.
6141 Returns TRUE iff feature is available. */
6143 mark_feature_used (const arm_feature_set
*feature
)
6145 /* Ensure the option is valid on the current architecture. */
6146 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6149 /* Add the appropriate architecture feature for the barrier option used.
6151 record_feature_use (feature
);
6156 /* Parse an option for a barrier instruction. Returns the encoding for the
6159 parse_barrier (char **str
)
6162 const struct asm_barrier_opt
*o
;
6165 while (ISALPHA (*q
))
6168 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6173 if (!mark_feature_used (&o
->arch
))
6180 /* Parse the operands of a table branch instruction. Similar to a memory
6183 parse_tb (char **str
)
6188 if (skip_past_char (&p
, '[') == FAIL
)
6190 inst
.error
= _("'[' expected");
6194 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6196 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6199 inst
.operands
[0].reg
= reg
;
6201 if (skip_past_comma (&p
) == FAIL
)
6203 inst
.error
= _("',' expected");
6207 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6209 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6212 inst
.operands
[0].imm
= reg
;
6214 if (skip_past_comma (&p
) == SUCCESS
)
6216 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6218 if (inst
.reloc
.exp
.X_add_number
!= 1)
6220 inst
.error
= _("invalid shift");
6223 inst
.operands
[0].shifted
= 1;
6226 if (skip_past_char (&p
, ']') == FAIL
)
6228 inst
.error
= _("']' expected");
6235 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6236 information on the types the operands can take and how they are encoded.
6237 Up to four operands may be read; this function handles setting the
6238 ".present" field for each read operand itself.
6239 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6240 else returns FAIL. */
6243 parse_neon_mov (char **str
, int *which_operand
)
6245 int i
= *which_operand
, val
;
6246 enum arm_reg_type rtype
;
6248 struct neon_type_el optype
;
6250 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6252 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6253 inst
.operands
[i
].reg
= val
;
6254 inst
.operands
[i
].isscalar
= 1;
6255 inst
.operands
[i
].vectype
= optype
;
6256 inst
.operands
[i
++].present
= 1;
6258 if (skip_past_comma (&ptr
) == FAIL
)
6261 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6264 inst
.operands
[i
].reg
= val
;
6265 inst
.operands
[i
].isreg
= 1;
6266 inst
.operands
[i
].present
= 1;
6268 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6271 /* Cases 0, 1, 2, 3, 5 (D only). */
6272 if (skip_past_comma (&ptr
) == FAIL
)
6275 inst
.operands
[i
].reg
= val
;
6276 inst
.operands
[i
].isreg
= 1;
6277 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6278 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6279 inst
.operands
[i
].isvec
= 1;
6280 inst
.operands
[i
].vectype
= optype
;
6281 inst
.operands
[i
++].present
= 1;
6283 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6285 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6286 Case 13: VMOV <Sd>, <Rm> */
6287 inst
.operands
[i
].reg
= val
;
6288 inst
.operands
[i
].isreg
= 1;
6289 inst
.operands
[i
].present
= 1;
6291 if (rtype
== REG_TYPE_NQ
)
6293 first_error (_("can't use Neon quad register here"));
6296 else if (rtype
!= REG_TYPE_VFS
)
6299 if (skip_past_comma (&ptr
) == FAIL
)
6301 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6303 inst
.operands
[i
].reg
= val
;
6304 inst
.operands
[i
].isreg
= 1;
6305 inst
.operands
[i
].present
= 1;
6308 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6311 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6312 Case 1: VMOV<c><q> <Dd>, <Dm>
6313 Case 8: VMOV.F32 <Sd>, <Sm>
6314 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6316 inst
.operands
[i
].reg
= val
;
6317 inst
.operands
[i
].isreg
= 1;
6318 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6319 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6320 inst
.operands
[i
].isvec
= 1;
6321 inst
.operands
[i
].vectype
= optype
;
6322 inst
.operands
[i
].present
= 1;
6324 if (skip_past_comma (&ptr
) == SUCCESS
)
6329 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6332 inst
.operands
[i
].reg
= val
;
6333 inst
.operands
[i
].isreg
= 1;
6334 inst
.operands
[i
++].present
= 1;
6336 if (skip_past_comma (&ptr
) == FAIL
)
6339 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6342 inst
.operands
[i
].reg
= val
;
6343 inst
.operands
[i
].isreg
= 1;
6344 inst
.operands
[i
].present
= 1;
6347 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6348 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6349 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6350 Case 10: VMOV.F32 <Sd>, #<imm>
6351 Case 11: VMOV.F64 <Dd>, #<imm> */
6352 inst
.operands
[i
].immisfloat
= 1;
6353 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6355 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6356 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6360 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6364 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6367 inst
.operands
[i
].reg
= val
;
6368 inst
.operands
[i
].isreg
= 1;
6369 inst
.operands
[i
++].present
= 1;
6371 if (skip_past_comma (&ptr
) == FAIL
)
6374 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6376 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6377 inst
.operands
[i
].reg
= val
;
6378 inst
.operands
[i
].isscalar
= 1;
6379 inst
.operands
[i
].present
= 1;
6380 inst
.operands
[i
].vectype
= optype
;
6382 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6384 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6385 inst
.operands
[i
].reg
= val
;
6386 inst
.operands
[i
].isreg
= 1;
6387 inst
.operands
[i
++].present
= 1;
6389 if (skip_past_comma (&ptr
) == FAIL
)
6392 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6395 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6399 inst
.operands
[i
].reg
= val
;
6400 inst
.operands
[i
].isreg
= 1;
6401 inst
.operands
[i
].isvec
= 1;
6402 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6403 inst
.operands
[i
].vectype
= optype
;
6404 inst
.operands
[i
].present
= 1;
6406 if (rtype
== REG_TYPE_VFS
)
6410 if (skip_past_comma (&ptr
) == FAIL
)
6412 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6415 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6418 inst
.operands
[i
].reg
= val
;
6419 inst
.operands
[i
].isreg
= 1;
6420 inst
.operands
[i
].isvec
= 1;
6421 inst
.operands
[i
].issingle
= 1;
6422 inst
.operands
[i
].vectype
= optype
;
6423 inst
.operands
[i
].present
= 1;
6426 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6430 inst
.operands
[i
].reg
= val
;
6431 inst
.operands
[i
].isreg
= 1;
6432 inst
.operands
[i
].isvec
= 1;
6433 inst
.operands
[i
].issingle
= 1;
6434 inst
.operands
[i
].vectype
= optype
;
6435 inst
.operands
[i
].present
= 1;
6440 first_error (_("parse error"));
6444 /* Successfully parsed the operands. Update args. */
6450 first_error (_("expected comma"));
6454 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6458 /* Use this macro when the operand constraints are different
6459 for ARM and THUMB (e.g. ldrd). */
6460 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6461 ((arm_operand) | ((thumb_operand) << 16))
6463 /* Matcher codes for parse_operands. */
6464 enum operand_parse_code
6466 OP_stop
, /* end of line */
6468 OP_RR
, /* ARM register */
6469 OP_RRnpc
, /* ARM register, not r15 */
6470 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6471 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6472 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6473 optional trailing ! */
6474 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6475 OP_RCP
, /* Coprocessor number */
6476 OP_RCN
, /* Coprocessor register */
6477 OP_RF
, /* FPA register */
6478 OP_RVS
, /* VFP single precision register */
6479 OP_RVD
, /* VFP double precision register (0..15) */
6480 OP_RND
, /* Neon double precision register (0..31) */
6481 OP_RNQ
, /* Neon quad precision register */
6482 OP_RVSD
, /* VFP single or double precision register */
6483 OP_RNDQ
, /* Neon double or quad precision register */
6484 OP_RNSDQ
, /* Neon single, double or quad precision register */
6485 OP_RNSC
, /* Neon scalar D[X] */
6486 OP_RVC
, /* VFP control register */
6487 OP_RMF
, /* Maverick F register */
6488 OP_RMD
, /* Maverick D register */
6489 OP_RMFX
, /* Maverick FX register */
6490 OP_RMDX
, /* Maverick DX register */
6491 OP_RMAX
, /* Maverick AX register */
6492 OP_RMDS
, /* Maverick DSPSC register */
6493 OP_RIWR
, /* iWMMXt wR register */
6494 OP_RIWC
, /* iWMMXt wC register */
6495 OP_RIWG
, /* iWMMXt wCG register */
6496 OP_RXA
, /* XScale accumulator register */
6498 OP_REGLST
, /* ARM register list */
6499 OP_VRSLST
, /* VFP single-precision register list */
6500 OP_VRDLST
, /* VFP double-precision register list */
6501 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6502 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6503 OP_NSTRLST
, /* Neon element/structure list */
6505 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6506 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6507 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6508 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6509 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6510 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6511 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6512 OP_VMOV
, /* Neon VMOV operands. */
6513 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6514 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6515 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6517 OP_I0
, /* immediate zero */
6518 OP_I7
, /* immediate value 0 .. 7 */
6519 OP_I15
, /* 0 .. 15 */
6520 OP_I16
, /* 1 .. 16 */
6521 OP_I16z
, /* 0 .. 16 */
6522 OP_I31
, /* 0 .. 31 */
6523 OP_I31w
, /* 0 .. 31, optional trailing ! */
6524 OP_I32
, /* 1 .. 32 */
6525 OP_I32z
, /* 0 .. 32 */
6526 OP_I63
, /* 0 .. 63 */
6527 OP_I63s
, /* -64 .. 63 */
6528 OP_I64
, /* 1 .. 64 */
6529 OP_I64z
, /* 0 .. 64 */
6530 OP_I255
, /* 0 .. 255 */
6532 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6533 OP_I7b
, /* 0 .. 7 */
6534 OP_I15b
, /* 0 .. 15 */
6535 OP_I31b
, /* 0 .. 31 */
6537 OP_SH
, /* shifter operand */
6538 OP_SHG
, /* shifter operand with possible group relocation */
6539 OP_ADDR
, /* Memory address expression (any mode) */
6540 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6541 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6542 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6543 OP_EXP
, /* arbitrary expression */
6544 OP_EXPi
, /* same, with optional immediate prefix */
6545 OP_EXPr
, /* same, with optional relocation suffix */
6546 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6547 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6548 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6550 OP_CPSF
, /* CPS flags */
6551 OP_ENDI
, /* Endianness specifier */
6552 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6553 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6554 OP_COND
, /* conditional code */
6555 OP_TB
, /* Table branch. */
6557 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6559 OP_RRnpc_I0
, /* ARM register or literal 0 */
6560 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6561 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6562 OP_RF_IF
, /* FPA register or immediate */
6563 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6564 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6566 /* Optional operands. */
6567 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6568 OP_oI31b
, /* 0 .. 31 */
6569 OP_oI32b
, /* 1 .. 32 */
6570 OP_oI32z
, /* 0 .. 32 */
6571 OP_oIffffb
, /* 0 .. 65535 */
6572 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6574 OP_oRR
, /* ARM register */
6575 OP_oRRnpc
, /* ARM register, not the PC */
6576 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6577 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6578 OP_oRND
, /* Optional Neon double precision register */
6579 OP_oRNQ
, /* Optional Neon quad precision register */
6580 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6581 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6582 OP_oSHll
, /* LSL immediate */
6583 OP_oSHar
, /* ASR immediate */
6584 OP_oSHllar
, /* LSL or ASR immediate */
6585 OP_oROR
, /* ROR 0/8/16/24 */
6586 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6588 /* Some pre-defined mixed (ARM/THUMB) operands. */
6589 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6590 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6591 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6593 OP_FIRST_OPTIONAL
= OP_oI7b
6596 /* Generic instruction operand parser. This does no encoding and no
6597 semantic validation; it merely squirrels values away in the inst
6598 structure. Returns SUCCESS or FAIL depending on whether the
6599 specified grammar matched. */
6601 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6603 unsigned const int *upat
= pattern
;
6604 char *backtrack_pos
= 0;
6605 const char *backtrack_error
= 0;
6606 int i
, val
= 0, backtrack_index
= 0;
6607 enum arm_reg_type rtype
;
6608 parse_operand_result result
;
6609 unsigned int op_parse_code
;
6611 #define po_char_or_fail(chr) \
6614 if (skip_past_char (&str, chr) == FAIL) \
6619 #define po_reg_or_fail(regtype) \
6622 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6623 & inst.operands[i].vectype); \
6626 first_error (_(reg_expected_msgs[regtype])); \
6629 inst.operands[i].reg = val; \
6630 inst.operands[i].isreg = 1; \
6631 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6632 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6633 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6634 || rtype == REG_TYPE_VFD \
6635 || rtype == REG_TYPE_NQ); \
6639 #define po_reg_or_goto(regtype, label) \
6642 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6643 & inst.operands[i].vectype); \
6647 inst.operands[i].reg = val; \
6648 inst.operands[i].isreg = 1; \
6649 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6650 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6651 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6652 || rtype == REG_TYPE_VFD \
6653 || rtype == REG_TYPE_NQ); \
6657 #define po_imm_or_fail(min, max, popt) \
6660 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6662 inst.operands[i].imm = val; \
6666 #define po_scalar_or_goto(elsz, label) \
6669 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6672 inst.operands[i].reg = val; \
6673 inst.operands[i].isscalar = 1; \
6677 #define po_misc_or_fail(expr) \
6685 #define po_misc_or_fail_no_backtrack(expr) \
6689 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6690 backtrack_pos = 0; \
6691 if (result != PARSE_OPERAND_SUCCESS) \
6696 #define po_barrier_or_imm(str) \
6699 val = parse_barrier (&str); \
6700 if (val == FAIL && ! ISALPHA (*str)) \
6703 /* ISB can only take SY as an option. */ \
6704 || ((inst.instruction & 0xf0) == 0x60 \
6707 inst.error = _("invalid barrier type"); \
6708 backtrack_pos = 0; \
6714 skip_whitespace (str
);
6716 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6718 op_parse_code
= upat
[i
];
6719 if (op_parse_code
>= 1<<16)
6720 op_parse_code
= thumb
? (op_parse_code
>> 16)
6721 : (op_parse_code
& ((1<<16)-1));
6723 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6725 /* Remember where we are in case we need to backtrack. */
6726 gas_assert (!backtrack_pos
);
6727 backtrack_pos
= str
;
6728 backtrack_error
= inst
.error
;
6729 backtrack_index
= i
;
6732 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6733 po_char_or_fail (',');
6735 switch (op_parse_code
)
6743 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6744 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6745 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6746 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6747 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6748 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6750 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6752 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6754 /* Also accept generic coprocessor regs for unknown registers. */
6756 po_reg_or_fail (REG_TYPE_CN
);
6758 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6759 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6760 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6761 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6762 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6763 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6764 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6765 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6766 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6767 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6769 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6771 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6772 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6774 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6776 /* Neon scalar. Using an element size of 8 means that some invalid
6777 scalars are accepted here, so deal with those in later code. */
6778 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6782 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6785 po_imm_or_fail (0, 0, TRUE
);
6790 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6795 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6798 if (parse_ifimm_zero (&str
))
6799 inst
.operands
[i
].imm
= 0;
6803 = _("only floating point zero is allowed as immediate value");
6811 po_scalar_or_goto (8, try_rr
);
6814 po_reg_or_fail (REG_TYPE_RN
);
6820 po_scalar_or_goto (8, try_nsdq
);
6823 po_reg_or_fail (REG_TYPE_NSDQ
);
6829 po_scalar_or_goto (8, try_ndq
);
6832 po_reg_or_fail (REG_TYPE_NDQ
);
6838 po_scalar_or_goto (8, try_vfd
);
6841 po_reg_or_fail (REG_TYPE_VFD
);
6846 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6847 not careful then bad things might happen. */
6848 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6853 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6856 /* There's a possibility of getting a 64-bit immediate here, so
6857 we need special handling. */
6858 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6861 inst
.error
= _("immediate value is out of range");
6869 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6872 po_imm_or_fail (0, 63, TRUE
);
6877 po_char_or_fail ('[');
6878 po_reg_or_fail (REG_TYPE_RN
);
6879 po_char_or_fail (']');
6885 po_reg_or_fail (REG_TYPE_RN
);
6886 if (skip_past_char (&str
, '!') == SUCCESS
)
6887 inst
.operands
[i
].writeback
= 1;
6891 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6892 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6893 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6894 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6895 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6896 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6897 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6898 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6899 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6900 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6901 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6902 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6904 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6906 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6907 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6909 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6910 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6911 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6912 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6914 /* Immediate variants */
6916 po_char_or_fail ('{');
6917 po_imm_or_fail (0, 255, TRUE
);
6918 po_char_or_fail ('}');
6922 /* The expression parser chokes on a trailing !, so we have
6923 to find it first and zap it. */
6926 while (*s
&& *s
!= ',')
6931 inst
.operands
[i
].writeback
= 1;
6933 po_imm_or_fail (0, 31, TRUE
);
6941 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6946 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6951 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6953 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6955 val
= parse_reloc (&str
);
6958 inst
.error
= _("unrecognized relocation suffix");
6961 else if (val
!= BFD_RELOC_UNUSED
)
6963 inst
.operands
[i
].imm
= val
;
6964 inst
.operands
[i
].hasreloc
= 1;
6969 /* Operand for MOVW or MOVT. */
6971 po_misc_or_fail (parse_half (&str
));
6974 /* Register or expression. */
6975 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6976 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6978 /* Register or immediate. */
6979 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6980 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6982 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6984 if (!is_immediate_prefix (*str
))
6987 val
= parse_fpa_immediate (&str
);
6990 /* FPA immediates are encoded as registers 8-15.
6991 parse_fpa_immediate has already applied the offset. */
6992 inst
.operands
[i
].reg
= val
;
6993 inst
.operands
[i
].isreg
= 1;
6996 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6997 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6999 /* Two kinds of register. */
7002 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7004 || (rege
->type
!= REG_TYPE_MMXWR
7005 && rege
->type
!= REG_TYPE_MMXWC
7006 && rege
->type
!= REG_TYPE_MMXWCG
))
7008 inst
.error
= _("iWMMXt data or control register expected");
7011 inst
.operands
[i
].reg
= rege
->number
;
7012 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7018 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7020 || (rege
->type
!= REG_TYPE_MMXWC
7021 && rege
->type
!= REG_TYPE_MMXWCG
))
7023 inst
.error
= _("iWMMXt control register expected");
7026 inst
.operands
[i
].reg
= rege
->number
;
7027 inst
.operands
[i
].isreg
= 1;
7032 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7033 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7034 case OP_oROR
: val
= parse_ror (&str
); break;
7035 case OP_COND
: val
= parse_cond (&str
); break;
7036 case OP_oBARRIER_I15
:
7037 po_barrier_or_imm (str
); break;
7039 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7045 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7046 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7048 inst
.error
= _("Banked registers are not available with this "
7054 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7058 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7061 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7063 if (strncasecmp (str
, "APSR_", 5) == 0)
7070 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7071 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7072 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7073 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7074 default: found
= 16;
7078 inst
.operands
[i
].isvec
= 1;
7079 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7080 inst
.operands
[i
].reg
= REG_PC
;
7087 po_misc_or_fail (parse_tb (&str
));
7090 /* Register lists. */
7092 val
= parse_reg_list (&str
);
7095 inst
.operands
[i
].writeback
= 1;
7101 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7105 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7109 /* Allow Q registers too. */
7110 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7115 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7117 inst
.operands
[i
].issingle
= 1;
7122 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7127 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7128 &inst
.operands
[i
].vectype
);
7131 /* Addressing modes */
7133 po_misc_or_fail (parse_address (&str
, i
));
7137 po_misc_or_fail_no_backtrack (
7138 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7142 po_misc_or_fail_no_backtrack (
7143 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7147 po_misc_or_fail_no_backtrack (
7148 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7152 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7156 po_misc_or_fail_no_backtrack (
7157 parse_shifter_operand_group_reloc (&str
, i
));
7161 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7165 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7169 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7173 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7176 /* Various value-based sanity checks and shared operations. We
7177 do not signal immediate failures for the register constraints;
7178 this allows a syntax error to take precedence. */
7179 switch (op_parse_code
)
7187 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7188 inst
.error
= BAD_PC
;
7193 if (inst
.operands
[i
].isreg
)
7195 if (inst
.operands
[i
].reg
== REG_PC
)
7196 inst
.error
= BAD_PC
;
7197 else if (inst
.operands
[i
].reg
== REG_SP
7198 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7199 relaxed since ARMv8-A. */
7200 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7203 inst
.error
= BAD_SP
;
7209 if (inst
.operands
[i
].isreg
7210 && inst
.operands
[i
].reg
== REG_PC
7211 && (inst
.operands
[i
].writeback
|| thumb
))
7212 inst
.error
= BAD_PC
;
7221 case OP_oBARRIER_I15
:
7230 inst
.operands
[i
].imm
= val
;
7237 /* If we get here, this operand was successfully parsed. */
7238 inst
.operands
[i
].present
= 1;
7242 inst
.error
= BAD_ARGS
;
7247 /* The parse routine should already have set inst.error, but set a
7248 default here just in case. */
7250 inst
.error
= _("syntax error");
7254 /* Do not backtrack over a trailing optional argument that
7255 absorbed some text. We will only fail again, with the
7256 'garbage following instruction' error message, which is
7257 probably less helpful than the current one. */
7258 if (backtrack_index
== i
&& backtrack_pos
!= str
7259 && upat
[i
+1] == OP_stop
)
7262 inst
.error
= _("syntax error");
7266 /* Try again, skipping the optional argument at backtrack_pos. */
7267 str
= backtrack_pos
;
7268 inst
.error
= backtrack_error
;
7269 inst
.operands
[backtrack_index
].present
= 0;
7270 i
= backtrack_index
;
7274 /* Check that we have parsed all the arguments. */
7275 if (*str
!= '\0' && !inst
.error
)
7276 inst
.error
= _("garbage following instruction");
7278 return inst
.error
? FAIL
: SUCCESS
;
7281 #undef po_char_or_fail
7282 #undef po_reg_or_fail
7283 #undef po_reg_or_goto
7284 #undef po_imm_or_fail
7285 #undef po_scalar_or_fail
7286 #undef po_barrier_or_imm
7288 /* Shorthand macro for instruction encoding functions issuing errors. */
7289 #define constraint(expr, err) \
7300 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7301 instructions are unpredictable if these registers are used. This
7302 is the BadReg predicate in ARM's Thumb-2 documentation.
7304 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7305 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7306 #define reject_bad_reg(reg) \
7308 if (reg == REG_PC) \
7310 inst.error = BAD_PC; \
7313 else if (reg == REG_SP \
7314 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7316 inst.error = BAD_SP; \
7321 /* If REG is R13 (the stack pointer), warn that its use is
7323 #define warn_deprecated_sp(reg) \
7325 if (warn_on_deprecated && reg == REG_SP) \
7326 as_tsktsk (_("use of r13 is deprecated")); \
7329 /* Functions for operand encoding. ARM, then Thumb. */
7331 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7333 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7335 The only binary encoding difference is the Coprocessor number. Coprocessor
7336 9 is used for half-precision calculations or conversions. The format of the
7337 instruction is the same as the equivalent Coprocessor 10 instruction that
7338 exists for Single-Precision operation. */
7341 do_scalar_fp16_v82_encode (void)
7343 if (inst
.cond
!= COND_ALWAYS
)
7344 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7345 " the behaviour is UNPREDICTABLE"));
7346 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7349 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7350 mark_feature_used (&arm_ext_fp16
);
7353 /* If VAL can be encoded in the immediate field of an ARM instruction,
7354 return the encoded form. Otherwise, return FAIL. */
7357 encode_arm_immediate (unsigned int val
)
7364 for (i
= 2; i
< 32; i
+= 2)
7365 if ((a
= rotate_left (val
, i
)) <= 0xff)
7366 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7371 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7372 return the encoded form. Otherwise, return FAIL. */
7374 encode_thumb32_immediate (unsigned int val
)
7381 for (i
= 1; i
<= 24; i
++)
7384 if ((val
& ~(0xff << i
)) == 0)
7385 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7389 if (val
== ((a
<< 16) | a
))
7391 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7395 if (val
== ((a
<< 16) | a
))
7396 return 0x200 | (a
>> 8);
7400 /* Encode a VFP SP or DP register number into inst.instruction. */
7403 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7405 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7408 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7411 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7414 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7419 first_error (_("D register out of range for selected VFP version"));
7427 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7431 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7435 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7439 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7443 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7447 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7455 /* Encode a <shift> in an ARM-format instruction. The immediate,
7456 if any, is handled by md_apply_fix. */
7458 encode_arm_shift (int i
)
7460 /* register-shifted register. */
7461 if (inst
.operands
[i
].immisreg
)
7464 for (op_index
= 0; op_index
<= i
; ++op_index
)
7466 /* Check the operand only when it's presented. In pre-UAL syntax,
7467 if the destination register is the same as the first operand, two
7468 register form of the instruction can be used. */
7469 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7470 && inst
.operands
[op_index
].reg
== REG_PC
)
7471 as_warn (UNPRED_REG ("r15"));
7474 if (inst
.operands
[i
].imm
== REG_PC
)
7475 as_warn (UNPRED_REG ("r15"));
7478 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7479 inst
.instruction
|= SHIFT_ROR
<< 5;
7482 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7483 if (inst
.operands
[i
].immisreg
)
7485 inst
.instruction
|= SHIFT_BY_REG
;
7486 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7489 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7494 encode_arm_shifter_operand (int i
)
7496 if (inst
.operands
[i
].isreg
)
7498 inst
.instruction
|= inst
.operands
[i
].reg
;
7499 encode_arm_shift (i
);
7503 inst
.instruction
|= INST_IMMEDIATE
;
7504 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7505 inst
.instruction
|= inst
.operands
[i
].imm
;
7509 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7511 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7514 Generate an error if the operand is not a register. */
7515 constraint (!inst
.operands
[i
].isreg
,
7516 _("Instruction does not support =N addresses"));
7518 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7520 if (inst
.operands
[i
].preind
)
7524 inst
.error
= _("instruction does not accept preindexed addressing");
7527 inst
.instruction
|= PRE_INDEX
;
7528 if (inst
.operands
[i
].writeback
)
7529 inst
.instruction
|= WRITE_BACK
;
7532 else if (inst
.operands
[i
].postind
)
7534 gas_assert (inst
.operands
[i
].writeback
);
7536 inst
.instruction
|= WRITE_BACK
;
7538 else /* unindexed - only for coprocessor */
7540 inst
.error
= _("instruction does not accept unindexed addressing");
7544 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7545 && (((inst
.instruction
& 0x000f0000) >> 16)
7546 == ((inst
.instruction
& 0x0000f000) >> 12)))
7547 as_warn ((inst
.instruction
& LOAD_BIT
)
7548 ? _("destination register same as write-back base")
7549 : _("source register same as write-back base"));
7552 /* inst.operands[i] was set up by parse_address. Encode it into an
7553 ARM-format mode 2 load or store instruction. If is_t is true,
7554 reject forms that cannot be used with a T instruction (i.e. not
7557 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7559 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7561 encode_arm_addr_mode_common (i
, is_t
);
7563 if (inst
.operands
[i
].immisreg
)
7565 constraint ((inst
.operands
[i
].imm
== REG_PC
7566 || (is_pc
&& inst
.operands
[i
].writeback
)),
7568 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7569 inst
.instruction
|= inst
.operands
[i
].imm
;
7570 if (!inst
.operands
[i
].negative
)
7571 inst
.instruction
|= INDEX_UP
;
7572 if (inst
.operands
[i
].shifted
)
7574 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7575 inst
.instruction
|= SHIFT_ROR
<< 5;
7578 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7579 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7583 else /* immediate offset in inst.reloc */
7585 if (is_pc
&& !inst
.reloc
.pc_rel
)
7587 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7589 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7590 cannot use PC in addressing.
7591 PC cannot be used in writeback addressing, either. */
7592 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7595 /* Use of PC in str is deprecated for ARMv7. */
7596 if (warn_on_deprecated
7598 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7599 as_tsktsk (_("use of PC in this instruction is deprecated"));
7602 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7604 /* Prefer + for zero encoded value. */
7605 if (!inst
.operands
[i
].negative
)
7606 inst
.instruction
|= INDEX_UP
;
7607 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7612 /* inst.operands[i] was set up by parse_address. Encode it into an
7613 ARM-format mode 3 load or store instruction. Reject forms that
7614 cannot be used with such instructions. If is_t is true, reject
7615 forms that cannot be used with a T instruction (i.e. not
7618 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7620 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7622 inst
.error
= _("instruction does not accept scaled register index");
7626 encode_arm_addr_mode_common (i
, is_t
);
7628 if (inst
.operands
[i
].immisreg
)
7630 constraint ((inst
.operands
[i
].imm
== REG_PC
7631 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7633 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7635 inst
.instruction
|= inst
.operands
[i
].imm
;
7636 if (!inst
.operands
[i
].negative
)
7637 inst
.instruction
|= INDEX_UP
;
7639 else /* immediate offset in inst.reloc */
7641 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7642 && inst
.operands
[i
].writeback
),
7644 inst
.instruction
|= HWOFFSET_IMM
;
7645 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7647 /* Prefer + for zero encoded value. */
7648 if (!inst
.operands
[i
].negative
)
7649 inst
.instruction
|= INDEX_UP
;
7651 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7656 /* Write immediate bits [7:0] to the following locations:
7658 |28/24|23 19|18 16|15 4|3 0|
7659 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7661 This function is used by VMOV/VMVN/VORR/VBIC. */
7664 neon_write_immbits (unsigned immbits
)
7666 inst
.instruction
|= immbits
& 0xf;
7667 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7668 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7671 /* Invert low-order SIZE bits of XHI:XLO. */
7674 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7676 unsigned immlo
= xlo
? *xlo
: 0;
7677 unsigned immhi
= xhi
? *xhi
: 0;
7682 immlo
= (~immlo
) & 0xff;
7686 immlo
= (~immlo
) & 0xffff;
7690 immhi
= (~immhi
) & 0xffffffff;
7694 immlo
= (~immlo
) & 0xffffffff;
7708 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7712 neon_bits_same_in_bytes (unsigned imm
)
7714 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7715 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7716 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7717 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7720 /* For immediate of above form, return 0bABCD. */
7723 neon_squash_bits (unsigned imm
)
7725 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7726 | ((imm
& 0x01000000) >> 21);
7729 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7732 neon_qfloat_bits (unsigned imm
)
7734 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7737 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7738 the instruction. *OP is passed as the initial value of the op field, and
7739 may be set to a different value depending on the constant (i.e.
7740 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7741 MVN). If the immediate looks like a repeated pattern then also
7742 try smaller element sizes. */
7745 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7746 unsigned *immbits
, int *op
, int size
,
7747 enum neon_el_type type
)
7749 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7751 if (type
== NT_float
&& !float_p
)
7754 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7756 if (size
!= 32 || *op
== 1)
7758 *immbits
= neon_qfloat_bits (immlo
);
7764 if (neon_bits_same_in_bytes (immhi
)
7765 && neon_bits_same_in_bytes (immlo
))
7769 *immbits
= (neon_squash_bits (immhi
) << 4)
7770 | neon_squash_bits (immlo
);
7781 if (immlo
== (immlo
& 0x000000ff))
7786 else if (immlo
== (immlo
& 0x0000ff00))
7788 *immbits
= immlo
>> 8;
7791 else if (immlo
== (immlo
& 0x00ff0000))
7793 *immbits
= immlo
>> 16;
7796 else if (immlo
== (immlo
& 0xff000000))
7798 *immbits
= immlo
>> 24;
7801 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7803 *immbits
= (immlo
>> 8) & 0xff;
7806 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7808 *immbits
= (immlo
>> 16) & 0xff;
7812 if ((immlo
& 0xffff) != (immlo
>> 16))
7819 if (immlo
== (immlo
& 0x000000ff))
7824 else if (immlo
== (immlo
& 0x0000ff00))
7826 *immbits
= immlo
>> 8;
7830 if ((immlo
& 0xff) != (immlo
>> 8))
7835 if (immlo
== (immlo
& 0x000000ff))
7837 /* Don't allow MVN with 8-bit immediate. */
7847 #if defined BFD_HOST_64_BIT
7848 /* Returns TRUE if double precision value V may be cast
7849 to single precision without loss of accuracy. */
7852 is_double_a_single (bfd_int64_t v
)
7854 int exp
= (int)((v
>> 52) & 0x7FF);
7855 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7857 return (exp
== 0 || exp
== 0x7FF
7858 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7859 && (mantissa
& 0x1FFFFFFFl
) == 0;
7862 /* Returns a double precision value casted to single precision
7863 (ignoring the least significant bits in exponent and mantissa). */
7866 double_to_single (bfd_int64_t v
)
7868 int sign
= (int) ((v
>> 63) & 1l);
7869 int exp
= (int) ((v
>> 52) & 0x7FF);
7870 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7876 exp
= exp
- 1023 + 127;
7885 /* No denormalized numbers. */
7891 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7893 #endif /* BFD_HOST_64_BIT */
7902 static void do_vfp_nsyn_opcode (const char *);
7904 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7905 Determine whether it can be performed with a move instruction; if
7906 it can, convert inst.instruction to that move instruction and
7907 return TRUE; if it can't, convert inst.instruction to a literal-pool
7908 load and return FALSE. If this is not a valid thing to do in the
7909 current context, set inst.error and return TRUE.
7911 inst.operands[i] describes the destination register. */
7914 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7917 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7918 bfd_boolean arm_p
= (t
== CONST_ARM
);
7921 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7925 if ((inst
.instruction
& tbit
) == 0)
7927 inst
.error
= _("invalid pseudo operation");
7931 if (inst
.reloc
.exp
.X_op
!= O_constant
7932 && inst
.reloc
.exp
.X_op
!= O_symbol
7933 && inst
.reloc
.exp
.X_op
!= O_big
)
7935 inst
.error
= _("constant expression expected");
7939 if (inst
.reloc
.exp
.X_op
== O_constant
7940 || inst
.reloc
.exp
.X_op
== O_big
)
7942 #if defined BFD_HOST_64_BIT
7947 if (inst
.reloc
.exp
.X_op
== O_big
)
7949 LITTLENUM_TYPE w
[X_PRECISION
];
7952 if (inst
.reloc
.exp
.X_add_number
== -1)
7954 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7956 /* FIXME: Should we check words w[2..5] ? */
7961 #if defined BFD_HOST_64_BIT
7963 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7964 << LITTLENUM_NUMBER_OF_BITS
)
7965 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7966 << LITTLENUM_NUMBER_OF_BITS
)
7967 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7968 << LITTLENUM_NUMBER_OF_BITS
)
7969 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7971 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7972 | (l
[0] & LITTLENUM_MASK
);
7976 v
= inst
.reloc
.exp
.X_add_number
;
7978 if (!inst
.operands
[i
].issingle
)
7982 /* LDR should not use lead in a flag-setting instruction being
7983 chosen so we do not check whether movs can be used. */
7985 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7986 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7987 && inst
.operands
[i
].reg
!= 13
7988 && inst
.operands
[i
].reg
!= 15)
7990 /* Check if on thumb2 it can be done with a mov.w, mvn or
7991 movw instruction. */
7992 unsigned int newimm
;
7993 bfd_boolean isNegated
;
7995 newimm
= encode_thumb32_immediate (v
);
7996 if (newimm
!= (unsigned int) FAIL
)
8000 newimm
= encode_thumb32_immediate (~v
);
8001 if (newimm
!= (unsigned int) FAIL
)
8005 /* The number can be loaded with a mov.w or mvn
8007 if (newimm
!= (unsigned int) FAIL
8008 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8010 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8011 | (inst
.operands
[i
].reg
<< 8));
8012 /* Change to MOVN. */
8013 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8014 inst
.instruction
|= (newimm
& 0x800) << 15;
8015 inst
.instruction
|= (newimm
& 0x700) << 4;
8016 inst
.instruction
|= (newimm
& 0x0ff);
8019 /* The number can be loaded with a movw instruction. */
8020 else if ((v
& ~0xFFFF) == 0
8021 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8023 int imm
= v
& 0xFFFF;
8025 inst
.instruction
= 0xf2400000; /* MOVW. */
8026 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8027 inst
.instruction
|= (imm
& 0xf000) << 4;
8028 inst
.instruction
|= (imm
& 0x0800) << 15;
8029 inst
.instruction
|= (imm
& 0x0700) << 4;
8030 inst
.instruction
|= (imm
& 0x00ff);
8037 int value
= encode_arm_immediate (v
);
8041 /* This can be done with a mov instruction. */
8042 inst
.instruction
&= LITERAL_MASK
;
8043 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8044 inst
.instruction
|= value
& 0xfff;
8048 value
= encode_arm_immediate (~ v
);
8051 /* This can be done with a mvn instruction. */
8052 inst
.instruction
&= LITERAL_MASK
;
8053 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8054 inst
.instruction
|= value
& 0xfff;
8058 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8061 unsigned immbits
= 0;
8062 unsigned immlo
= inst
.operands
[1].imm
;
8063 unsigned immhi
= inst
.operands
[1].regisimm
8064 ? inst
.operands
[1].reg
8065 : inst
.reloc
.exp
.X_unsigned
8067 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8068 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8069 &op
, 64, NT_invtype
);
8073 neon_invert_size (&immlo
, &immhi
, 64);
8075 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8076 &op
, 64, NT_invtype
);
8081 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8087 /* Fill other bits in vmov encoding for both thumb and arm. */
8089 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8091 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8092 neon_write_immbits (immbits
);
8100 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8101 if (inst
.operands
[i
].issingle
8102 && is_quarter_float (inst
.operands
[1].imm
)
8103 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8105 inst
.operands
[1].imm
=
8106 neon_qfloat_bits (v
);
8107 do_vfp_nsyn_opcode ("fconsts");
8111 /* If our host does not support a 64-bit type then we cannot perform
8112 the following optimization. This mean that there will be a
8113 discrepancy between the output produced by an assembler built for
8114 a 32-bit-only host and the output produced from a 64-bit host, but
8115 this cannot be helped. */
8116 #if defined BFD_HOST_64_BIT
8117 else if (!inst
.operands
[1].issingle
8118 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8120 if (is_double_a_single (v
)
8121 && is_quarter_float (double_to_single (v
)))
8123 inst
.operands
[1].imm
=
8124 neon_qfloat_bits (double_to_single (v
));
8125 do_vfp_nsyn_opcode ("fconstd");
8133 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8134 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8137 inst
.operands
[1].reg
= REG_PC
;
8138 inst
.operands
[1].isreg
= 1;
8139 inst
.operands
[1].preind
= 1;
8140 inst
.reloc
.pc_rel
= 1;
8141 inst
.reloc
.type
= (thumb_p
8142 ? BFD_RELOC_ARM_THUMB_OFFSET
8144 ? BFD_RELOC_ARM_HWLITERAL
8145 : BFD_RELOC_ARM_LITERAL
));
8149 /* inst.operands[i] was set up by parse_address. Encode it into an
8150 ARM-format instruction. Reject all forms which cannot be encoded
8151 into a coprocessor load/store instruction. If wb_ok is false,
8152 reject use of writeback; if unind_ok is false, reject use of
8153 unindexed addressing. If reloc_override is not 0, use it instead
8154 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8155 (in which case it is preserved). */
8158 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8160 if (!inst
.operands
[i
].isreg
)
8163 if (! inst
.operands
[0].isvec
)
8165 inst
.error
= _("invalid co-processor operand");
8168 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8172 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8174 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8176 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8178 gas_assert (!inst
.operands
[i
].writeback
);
8181 inst
.error
= _("instruction does not support unindexed addressing");
8184 inst
.instruction
|= inst
.operands
[i
].imm
;
8185 inst
.instruction
|= INDEX_UP
;
8189 if (inst
.operands
[i
].preind
)
8190 inst
.instruction
|= PRE_INDEX
;
8192 if (inst
.operands
[i
].writeback
)
8194 if (inst
.operands
[i
].reg
== REG_PC
)
8196 inst
.error
= _("pc may not be used with write-back");
8201 inst
.error
= _("instruction does not support writeback");
8204 inst
.instruction
|= WRITE_BACK
;
8208 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8209 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8210 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8211 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8214 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8216 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8219 /* Prefer + for zero encoded value. */
8220 if (!inst
.operands
[i
].negative
)
8221 inst
.instruction
|= INDEX_UP
;
8226 /* Functions for instruction encoding, sorted by sub-architecture.
8227 First some generics; their names are taken from the conventional
8228 bit positions for register arguments in ARM format instructions. */
8238 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8244 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8250 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8251 inst
.instruction
|= inst
.operands
[1].reg
;
8257 inst
.instruction
|= inst
.operands
[0].reg
;
8258 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8264 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8265 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8271 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8272 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8278 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8279 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8283 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8285 if (ARM_CPU_IS_ANY (cpu_variant
))
8287 as_tsktsk ("%s", msg
);
8290 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8302 unsigned Rn
= inst
.operands
[2].reg
;
8303 /* Enforce restrictions on SWP instruction. */
8304 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8306 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8307 _("Rn must not overlap other operands"));
8309 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8311 if (!check_obsolete (&arm_ext_v8
,
8312 _("swp{b} use is obsoleted for ARMv8 and later"))
8313 && warn_on_deprecated
8314 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8315 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8318 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8319 inst
.instruction
|= inst
.operands
[1].reg
;
8320 inst
.instruction
|= Rn
<< 16;
8326 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8327 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8328 inst
.instruction
|= inst
.operands
[2].reg
;
8334 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8335 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8336 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8337 || inst
.reloc
.exp
.X_add_number
!= 0),
8339 inst
.instruction
|= inst
.operands
[0].reg
;
8340 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8341 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8347 inst
.instruction
|= inst
.operands
[0].imm
;
8353 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8354 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8357 /* ARM instructions, in alphabetical order by function name (except
8358 that wrapper functions appear immediately after the function they
8361 /* This is a pseudo-op of the form "adr rd, label" to be converted
8362 into a relative address of the form "add rd, pc, #label-.-8". */
8367 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8369 /* Frag hacking will turn this into a sub instruction if the offset turns
8370 out to be negative. */
8371 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8372 inst
.reloc
.pc_rel
= 1;
8373 inst
.reloc
.exp
.X_add_number
-= 8;
8375 if (inst
.reloc
.exp
.X_op
== O_symbol
8376 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8377 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8378 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8379 inst
.reloc
.exp
.X_add_number
+= 1;
8382 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8383 into a relative address of the form:
8384 add rd, pc, #low(label-.-8)"
8385 add rd, rd, #high(label-.-8)" */
8390 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8392 /* Frag hacking will turn this into a sub instruction if the offset turns
8393 out to be negative. */
8394 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8395 inst
.reloc
.pc_rel
= 1;
8396 inst
.size
= INSN_SIZE
* 2;
8397 inst
.reloc
.exp
.X_add_number
-= 8;
8399 if (inst
.reloc
.exp
.X_op
== O_symbol
8400 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8401 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8402 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8403 inst
.reloc
.exp
.X_add_number
+= 1;
8409 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8410 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8412 if (!inst
.operands
[1].present
)
8413 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8414 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8415 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8416 encode_arm_shifter_operand (2);
8422 if (inst
.operands
[0].present
)
8423 inst
.instruction
|= inst
.operands
[0].imm
;
8425 inst
.instruction
|= 0xf;
8431 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8432 constraint (msb
> 32, _("bit-field extends past end of register"));
8433 /* The instruction encoding stores the LSB and MSB,
8434 not the LSB and width. */
8435 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8436 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8437 inst
.instruction
|= (msb
- 1) << 16;
8445 /* #0 in second position is alternative syntax for bfc, which is
8446 the same instruction but with REG_PC in the Rm field. */
8447 if (!inst
.operands
[1].isreg
)
8448 inst
.operands
[1].reg
= REG_PC
;
8450 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8451 constraint (msb
> 32, _("bit-field extends past end of register"));
8452 /* The instruction encoding stores the LSB and MSB,
8453 not the LSB and width. */
8454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8455 inst
.instruction
|= inst
.operands
[1].reg
;
8456 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8457 inst
.instruction
|= (msb
- 1) << 16;
8463 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8464 _("bit-field extends past end of register"));
8465 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8466 inst
.instruction
|= inst
.operands
[1].reg
;
8467 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8468 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8471 /* ARM V5 breakpoint instruction (argument parse)
8472 BKPT <16 bit unsigned immediate>
8473 Instruction is not conditional.
8474 The bit pattern given in insns[] has the COND_ALWAYS condition,
8475 and it is an error if the caller tried to override that. */
8480 /* Top 12 of 16 bits to bits 19:8. */
8481 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8483 /* Bottom 4 of 16 bits to bits 3:0. */
8484 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8488 encode_branch (int default_reloc
)
8490 if (inst
.operands
[0].hasreloc
)
8492 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8493 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8494 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8495 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8496 ? BFD_RELOC_ARM_PLT32
8497 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8500 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8501 inst
.reloc
.pc_rel
= 1;
8508 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8509 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8512 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8519 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8521 if (inst
.cond
== COND_ALWAYS
)
8522 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8524 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8528 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8531 /* ARM V5 branch-link-exchange instruction (argument parse)
8532 BLX <target_addr> ie BLX(1)
8533 BLX{<condition>} <Rm> ie BLX(2)
8534 Unfortunately, there are two different opcodes for this mnemonic.
8535 So, the insns[].value is not used, and the code here zaps values
8536 into inst.instruction.
8537 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8542 if (inst
.operands
[0].isreg
)
8544 /* Arg is a register; the opcode provided by insns[] is correct.
8545 It is not illegal to do "blx pc", just useless. */
8546 if (inst
.operands
[0].reg
== REG_PC
)
8547 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8549 inst
.instruction
|= inst
.operands
[0].reg
;
8553 /* Arg is an address; this instruction cannot be executed
8554 conditionally, and the opcode must be adjusted.
8555 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8556 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8557 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8558 inst
.instruction
= 0xfa000000;
8559 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8566 bfd_boolean want_reloc
;
8568 if (inst
.operands
[0].reg
== REG_PC
)
8569 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8571 inst
.instruction
|= inst
.operands
[0].reg
;
8572 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8573 it is for ARMv4t or earlier. */
8574 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8575 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8579 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8584 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8588 /* ARM v5TEJ. Jump to Jazelle code. */
8593 if (inst
.operands
[0].reg
== REG_PC
)
8594 as_tsktsk (_("use of r15 in bxj is not really useful"));
8596 inst
.instruction
|= inst
.operands
[0].reg
;
8599 /* Co-processor data operation:
8600 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8601 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8605 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8606 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8607 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8608 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8609 inst
.instruction
|= inst
.operands
[4].reg
;
8610 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8616 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8617 encode_arm_shifter_operand (1);
8620 /* Transfer between coprocessor and ARM registers.
8621 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8626 No special properties. */
8628 struct deprecated_coproc_regs_s
8635 arm_feature_set deprecated
;
8636 arm_feature_set obsoleted
;
8637 const char *dep_msg
;
8638 const char *obs_msg
;
8641 #define DEPR_ACCESS_V8 \
8642 N_("This coprocessor register access is deprecated in ARMv8")
8644 /* Table of all deprecated coprocessor registers. */
8645 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8647 {15, 0, 7, 10, 5, /* CP15DMB. */
8648 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8649 DEPR_ACCESS_V8
, NULL
},
8650 {15, 0, 7, 10, 4, /* CP15DSB. */
8651 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8652 DEPR_ACCESS_V8
, NULL
},
8653 {15, 0, 7, 5, 4, /* CP15ISB. */
8654 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8655 DEPR_ACCESS_V8
, NULL
},
8656 {14, 6, 1, 0, 0, /* TEEHBR. */
8657 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8658 DEPR_ACCESS_V8
, NULL
},
8659 {14, 6, 0, 0, 0, /* TEECR. */
8660 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8661 DEPR_ACCESS_V8
, NULL
},
8664 #undef DEPR_ACCESS_V8
8666 static const size_t deprecated_coproc_reg_count
=
8667 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8675 Rd
= inst
.operands
[2].reg
;
8678 if (inst
.instruction
== 0xee000010
8679 || inst
.instruction
== 0xfe000010)
8681 reject_bad_reg (Rd
);
8682 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8684 constraint (Rd
== REG_SP
, BAD_SP
);
8689 if (inst
.instruction
== 0xe000010)
8690 constraint (Rd
== REG_PC
, BAD_PC
);
8693 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8695 const struct deprecated_coproc_regs_s
*r
=
8696 deprecated_coproc_regs
+ i
;
8698 if (inst
.operands
[0].reg
== r
->cp
8699 && inst
.operands
[1].imm
== r
->opc1
8700 && inst
.operands
[3].reg
== r
->crn
8701 && inst
.operands
[4].reg
== r
->crm
8702 && inst
.operands
[5].imm
== r
->opc2
)
8704 if (! ARM_CPU_IS_ANY (cpu_variant
)
8705 && warn_on_deprecated
8706 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8707 as_tsktsk ("%s", r
->dep_msg
);
8711 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8712 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8713 inst
.instruction
|= Rd
<< 12;
8714 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8715 inst
.instruction
|= inst
.operands
[4].reg
;
8716 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8719 /* Transfer between coprocessor register and pair of ARM registers.
8720 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8725 Two XScale instructions are special cases of these:
8727 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8728 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8730 Result unpredictable if Rd or Rn is R15. */
8737 Rd
= inst
.operands
[2].reg
;
8738 Rn
= inst
.operands
[3].reg
;
8742 reject_bad_reg (Rd
);
8743 reject_bad_reg (Rn
);
8747 constraint (Rd
== REG_PC
, BAD_PC
);
8748 constraint (Rn
== REG_PC
, BAD_PC
);
8751 /* Only check the MRRC{2} variants. */
8752 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8754 /* If Rd == Rn, error that the operation is
8755 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8756 constraint (Rd
== Rn
, BAD_OVERLAP
);
8759 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8760 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8761 inst
.instruction
|= Rd
<< 12;
8762 inst
.instruction
|= Rn
<< 16;
8763 inst
.instruction
|= inst
.operands
[4].reg
;
8769 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8770 if (inst
.operands
[1].present
)
8772 inst
.instruction
|= CPSI_MMOD
;
8773 inst
.instruction
|= inst
.operands
[1].imm
;
8780 inst
.instruction
|= inst
.operands
[0].imm
;
8786 unsigned Rd
, Rn
, Rm
;
8788 Rd
= inst
.operands
[0].reg
;
8789 Rn
= (inst
.operands
[1].present
8790 ? inst
.operands
[1].reg
: Rd
);
8791 Rm
= inst
.operands
[2].reg
;
8793 constraint ((Rd
== REG_PC
), BAD_PC
);
8794 constraint ((Rn
== REG_PC
), BAD_PC
);
8795 constraint ((Rm
== REG_PC
), BAD_PC
);
8797 inst
.instruction
|= Rd
<< 16;
8798 inst
.instruction
|= Rn
<< 0;
8799 inst
.instruction
|= Rm
<< 8;
8805 /* There is no IT instruction in ARM mode. We
8806 process it to do the validation as if in
8807 thumb mode, just in case the code gets
8808 assembled for thumb using the unified syntax. */
8813 set_it_insn_type (IT_INSN
);
8814 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8815 now_it
.cc
= inst
.operands
[0].imm
;
8819 /* If there is only one register in the register list,
8820 then return its register number. Otherwise return -1. */
8822 only_one_reg_in_list (int range
)
8824 int i
= ffs (range
) - 1;
8825 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8829 encode_ldmstm(int from_push_pop_mnem
)
8831 int base_reg
= inst
.operands
[0].reg
;
8832 int range
= inst
.operands
[1].imm
;
8835 inst
.instruction
|= base_reg
<< 16;
8836 inst
.instruction
|= range
;
8838 if (inst
.operands
[1].writeback
)
8839 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8841 if (inst
.operands
[0].writeback
)
8843 inst
.instruction
|= WRITE_BACK
;
8844 /* Check for unpredictable uses of writeback. */
8845 if (inst
.instruction
& LOAD_BIT
)
8847 /* Not allowed in LDM type 2. */
8848 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8849 && ((range
& (1 << REG_PC
)) == 0))
8850 as_warn (_("writeback of base register is UNPREDICTABLE"));
8851 /* Only allowed if base reg not in list for other types. */
8852 else if (range
& (1 << base_reg
))
8853 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8857 /* Not allowed for type 2. */
8858 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8859 as_warn (_("writeback of base register is UNPREDICTABLE"));
8860 /* Only allowed if base reg not in list, or first in list. */
8861 else if ((range
& (1 << base_reg
))
8862 && (range
& ((1 << base_reg
) - 1)))
8863 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8867 /* If PUSH/POP has only one register, then use the A2 encoding. */
8868 one_reg
= only_one_reg_in_list (range
);
8869 if (from_push_pop_mnem
&& one_reg
>= 0)
8871 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8873 inst
.instruction
&= A_COND_MASK
;
8874 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8875 inst
.instruction
|= one_reg
<< 12;
8882 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8885 /* ARMv5TE load-consecutive (argument parse)
8894 constraint (inst
.operands
[0].reg
% 2 != 0,
8895 _("first transfer register must be even"));
8896 constraint (inst
.operands
[1].present
8897 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8898 _("can only transfer two consecutive registers"));
8899 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8900 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8902 if (!inst
.operands
[1].present
)
8903 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8905 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8906 register and the first register written; we have to diagnose
8907 overlap between the base and the second register written here. */
8909 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8910 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8911 as_warn (_("base register written back, and overlaps "
8912 "second transfer register"));
8914 if (!(inst
.instruction
& V4_STR_BIT
))
8916 /* For an index-register load, the index register must not overlap the
8917 destination (even if not write-back). */
8918 if (inst
.operands
[2].immisreg
8919 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8920 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8921 as_warn (_("index register overlaps transfer register"));
8923 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8924 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8930 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8931 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8932 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8933 || inst
.operands
[1].negative
8934 /* This can arise if the programmer has written
8936 or if they have mistakenly used a register name as the last
8939 It is very difficult to distinguish between these two cases
8940 because "rX" might actually be a label. ie the register
8941 name has been occluded by a symbol of the same name. So we
8942 just generate a general 'bad addressing mode' type error
8943 message and leave it up to the programmer to discover the
8944 true cause and fix their mistake. */
8945 || (inst
.operands
[1].reg
== REG_PC
),
8948 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8949 || inst
.reloc
.exp
.X_add_number
!= 0,
8950 _("offset must be zero in ARM encoding"));
8952 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8955 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8956 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8962 constraint (inst
.operands
[0].reg
% 2 != 0,
8963 _("even register required"));
8964 constraint (inst
.operands
[1].present
8965 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8966 _("can only load two consecutive registers"));
8967 /* If op 1 were present and equal to PC, this function wouldn't
8968 have been called in the first place. */
8969 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8971 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8972 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8975 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8976 which is not a multiple of four is UNPREDICTABLE. */
8978 check_ldr_r15_aligned (void)
8980 constraint (!(inst
.operands
[1].immisreg
)
8981 && (inst
.operands
[0].reg
== REG_PC
8982 && inst
.operands
[1].reg
== REG_PC
8983 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8984 _("ldr to register 15 must be 4-byte aligned"));
8990 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8991 if (!inst
.operands
[1].isreg
)
8992 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8994 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8995 check_ldr_r15_aligned ();
9001 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9003 if (inst
.operands
[1].preind
)
9005 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9006 || inst
.reloc
.exp
.X_add_number
!= 0,
9007 _("this instruction requires a post-indexed address"));
9009 inst
.operands
[1].preind
= 0;
9010 inst
.operands
[1].postind
= 1;
9011 inst
.operands
[1].writeback
= 1;
9013 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9014 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9017 /* Halfword and signed-byte load/store operations. */
9022 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9023 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9024 if (!inst
.operands
[1].isreg
)
9025 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9027 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9033 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9035 if (inst
.operands
[1].preind
)
9037 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9038 || inst
.reloc
.exp
.X_add_number
!= 0,
9039 _("this instruction requires a post-indexed address"));
9041 inst
.operands
[1].preind
= 0;
9042 inst
.operands
[1].postind
= 1;
9043 inst
.operands
[1].writeback
= 1;
9045 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9046 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9049 /* Co-processor register load/store.
9050 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9054 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9055 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9056 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9062 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9063 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9064 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9065 && !(inst
.instruction
& 0x00400000))
9066 as_tsktsk (_("Rd and Rm should be different in mla"));
9068 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9069 inst
.instruction
|= inst
.operands
[1].reg
;
9070 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9071 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9077 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9078 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9080 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9081 encode_arm_shifter_operand (1);
9084 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9091 top
= (inst
.instruction
& 0x00400000) != 0;
9092 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9093 _(":lower16: not allowed in this instruction"));
9094 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9095 _(":upper16: not allowed in this instruction"));
9096 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9097 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9099 imm
= inst
.reloc
.exp
.X_add_number
;
9100 /* The value is in two pieces: 0:11, 16:19. */
9101 inst
.instruction
|= (imm
& 0x00000fff);
9102 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9107 do_vfp_nsyn_mrs (void)
9109 if (inst
.operands
[0].isvec
)
9111 if (inst
.operands
[1].reg
!= 1)
9112 first_error (_("operand 1 must be FPSCR"));
9113 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9114 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9115 do_vfp_nsyn_opcode ("fmstat");
9117 else if (inst
.operands
[1].isvec
)
9118 do_vfp_nsyn_opcode ("fmrx");
9126 do_vfp_nsyn_msr (void)
9128 if (inst
.operands
[0].isvec
)
9129 do_vfp_nsyn_opcode ("fmxr");
9139 unsigned Rt
= inst
.operands
[0].reg
;
9141 if (thumb_mode
&& Rt
== REG_SP
)
9143 inst
.error
= BAD_SP
;
9147 /* MVFR2 is only valid at ARMv8-A. */
9148 if (inst
.operands
[1].reg
== 5)
9149 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9152 /* APSR_ sets isvec. All other refs to PC are illegal. */
9153 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9155 inst
.error
= BAD_PC
;
9159 /* If we get through parsing the register name, we just insert the number
9160 generated into the instruction without further validation. */
9161 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9162 inst
.instruction
|= (Rt
<< 12);
9168 unsigned Rt
= inst
.operands
[1].reg
;
9171 reject_bad_reg (Rt
);
9172 else if (Rt
== REG_PC
)
9174 inst
.error
= BAD_PC
;
9178 /* MVFR2 is only valid for ARMv8-A. */
9179 if (inst
.operands
[0].reg
== 5)
9180 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9183 /* If we get through parsing the register name, we just insert the number
9184 generated into the instruction without further validation. */
9185 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9186 inst
.instruction
|= (Rt
<< 12);
9194 if (do_vfp_nsyn_mrs () == SUCCESS
)
9197 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9198 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9200 if (inst
.operands
[1].isreg
)
9202 br
= inst
.operands
[1].reg
;
9203 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9204 as_bad (_("bad register for mrs"));
9208 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9209 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9211 _("'APSR', 'CPSR' or 'SPSR' expected"));
9212 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9215 inst
.instruction
|= br
;
9218 /* Two possible forms:
9219 "{C|S}PSR_<field>, Rm",
9220 "{C|S}PSR_f, #expression". */
9225 if (do_vfp_nsyn_msr () == SUCCESS
)
9228 inst
.instruction
|= inst
.operands
[0].imm
;
9229 if (inst
.operands
[1].isreg
)
9230 inst
.instruction
|= inst
.operands
[1].reg
;
9233 inst
.instruction
|= INST_IMMEDIATE
;
9234 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9235 inst
.reloc
.pc_rel
= 0;
9242 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9244 if (!inst
.operands
[2].present
)
9245 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9246 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9247 inst
.instruction
|= inst
.operands
[1].reg
;
9248 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9250 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9251 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9252 as_tsktsk (_("Rd and Rm should be different in mul"));
9255 /* Long Multiply Parser
9256 UMULL RdLo, RdHi, Rm, Rs
9257 SMULL RdLo, RdHi, Rm, Rs
9258 UMLAL RdLo, RdHi, Rm, Rs
9259 SMLAL RdLo, RdHi, Rm, Rs. */
9264 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9265 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9266 inst
.instruction
|= inst
.operands
[2].reg
;
9267 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9269 /* rdhi and rdlo must be different. */
9270 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9271 as_tsktsk (_("rdhi and rdlo must be different"));
9273 /* rdhi, rdlo and rm must all be different before armv6. */
9274 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9275 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9276 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9277 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9283 if (inst
.operands
[0].present
9284 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9286 /* Architectural NOP hints are CPSR sets with no bits selected. */
9287 inst
.instruction
&= 0xf0000000;
9288 inst
.instruction
|= 0x0320f000;
9289 if (inst
.operands
[0].present
)
9290 inst
.instruction
|= inst
.operands
[0].imm
;
9294 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9295 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9296 Condition defaults to COND_ALWAYS.
9297 Error if Rd, Rn or Rm are R15. */
9302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9303 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9304 inst
.instruction
|= inst
.operands
[2].reg
;
9305 if (inst
.operands
[3].present
)
9306 encode_arm_shift (3);
9309 /* ARM V6 PKHTB (Argument Parse). */
9314 if (!inst
.operands
[3].present
)
9316 /* If the shift specifier is omitted, turn the instruction
9317 into pkhbt rd, rm, rn. */
9318 inst
.instruction
&= 0xfff00010;
9319 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9320 inst
.instruction
|= inst
.operands
[1].reg
;
9321 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9325 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9326 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9327 inst
.instruction
|= inst
.operands
[2].reg
;
9328 encode_arm_shift (3);
9332 /* ARMv5TE: Preload-Cache
9333 MP Extensions: Preload for write
9337 Syntactically, like LDR with B=1, W=0, L=1. */
9342 constraint (!inst
.operands
[0].isreg
,
9343 _("'[' expected after PLD mnemonic"));
9344 constraint (inst
.operands
[0].postind
,
9345 _("post-indexed expression used in preload instruction"));
9346 constraint (inst
.operands
[0].writeback
,
9347 _("writeback used in preload instruction"));
9348 constraint (!inst
.operands
[0].preind
,
9349 _("unindexed addressing used in preload instruction"));
9350 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9353 /* ARMv7: PLI <addr_mode> */
9357 constraint (!inst
.operands
[0].isreg
,
9358 _("'[' expected after PLI mnemonic"));
9359 constraint (inst
.operands
[0].postind
,
9360 _("post-indexed expression used in preload instruction"));
9361 constraint (inst
.operands
[0].writeback
,
9362 _("writeback used in preload instruction"));
9363 constraint (!inst
.operands
[0].preind
,
9364 _("unindexed addressing used in preload instruction"));
9365 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9366 inst
.instruction
&= ~PRE_INDEX
;
9372 constraint (inst
.operands
[0].writeback
,
9373 _("push/pop do not support {reglist}^"));
9374 inst
.operands
[1] = inst
.operands
[0];
9375 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9376 inst
.operands
[0].isreg
= 1;
9377 inst
.operands
[0].writeback
= 1;
9378 inst
.operands
[0].reg
= REG_SP
;
9379 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9382 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9383 word at the specified address and the following word
9385 Unconditionally executed.
9386 Error if Rn is R15. */
9391 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9392 if (inst
.operands
[0].writeback
)
9393 inst
.instruction
|= WRITE_BACK
;
9396 /* ARM V6 ssat (argument parse). */
9401 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9402 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9403 inst
.instruction
|= inst
.operands
[2].reg
;
9405 if (inst
.operands
[3].present
)
9406 encode_arm_shift (3);
9409 /* ARM V6 usat (argument parse). */
9414 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9415 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9416 inst
.instruction
|= inst
.operands
[2].reg
;
9418 if (inst
.operands
[3].present
)
9419 encode_arm_shift (3);
9422 /* ARM V6 ssat16 (argument parse). */
9427 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9428 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9429 inst
.instruction
|= inst
.operands
[2].reg
;
9435 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9436 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9437 inst
.instruction
|= inst
.operands
[2].reg
;
9440 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9441 preserving the other bits.
9443 setend <endian_specifier>, where <endian_specifier> is either
9449 if (warn_on_deprecated
9450 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9451 as_tsktsk (_("setend use is deprecated for ARMv8"));
9453 if (inst
.operands
[0].imm
)
9454 inst
.instruction
|= 0x200;
9460 unsigned int Rm
= (inst
.operands
[1].present
9461 ? inst
.operands
[1].reg
9462 : inst
.operands
[0].reg
);
9464 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9465 inst
.instruction
|= Rm
;
9466 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9468 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9469 inst
.instruction
|= SHIFT_BY_REG
;
9470 /* PR 12854: Error on extraneous shifts. */
9471 constraint (inst
.operands
[2].shifted
,
9472 _("extraneous shift as part of operand to shift insn"));
9475 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9481 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9482 inst
.reloc
.pc_rel
= 0;
9488 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9489 inst
.reloc
.pc_rel
= 0;
9495 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9496 inst
.reloc
.pc_rel
= 0;
9502 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9503 _("selected processor does not support SETPAN instruction"));
9505 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9511 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9512 _("selected processor does not support SETPAN instruction"));
9514 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9517 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9518 SMLAxy{cond} Rd,Rm,Rs,Rn
9519 SMLAWy{cond} Rd,Rm,Rs,Rn
9520 Error if any register is R15. */
9525 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9526 inst
.instruction
|= inst
.operands
[1].reg
;
9527 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9528 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9531 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9532 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9533 Error if any register is R15.
9534 Warning if Rdlo == Rdhi. */
9539 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9540 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9541 inst
.instruction
|= inst
.operands
[2].reg
;
9542 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9544 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9545 as_tsktsk (_("rdhi and rdlo must be different"));
9548 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9549 SMULxy{cond} Rd,Rm,Rs
9550 Error if any register is R15. */
9555 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9556 inst
.instruction
|= inst
.operands
[1].reg
;
9557 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9560 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9561 the same for both ARM and Thumb-2. */
9568 if (inst
.operands
[0].present
)
9570 reg
= inst
.operands
[0].reg
;
9571 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9576 inst
.instruction
|= reg
<< 16;
9577 inst
.instruction
|= inst
.operands
[1].imm
;
9578 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9579 inst
.instruction
|= WRITE_BACK
;
9582 /* ARM V6 strex (argument parse). */
9587 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9588 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9589 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9590 || inst
.operands
[2].negative
9591 /* See comment in do_ldrex(). */
9592 || (inst
.operands
[2].reg
== REG_PC
),
9595 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9596 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9598 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9599 || inst
.reloc
.exp
.X_add_number
!= 0,
9600 _("offset must be zero in ARM encoding"));
9602 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9603 inst
.instruction
|= inst
.operands
[1].reg
;
9604 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9605 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9611 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9612 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9613 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9614 || inst
.operands
[2].negative
,
9617 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9618 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9626 constraint (inst
.operands
[1].reg
% 2 != 0,
9627 _("even register required"));
9628 constraint (inst
.operands
[2].present
9629 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9630 _("can only store two consecutive registers"));
9631 /* If op 2 were present and equal to PC, this function wouldn't
9632 have been called in the first place. */
9633 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9635 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9636 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9637 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9640 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9641 inst
.instruction
|= inst
.operands
[1].reg
;
9642 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9649 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9650 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9658 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9659 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9664 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9665 extends it to 32-bits, and adds the result to a value in another
9666 register. You can specify a rotation by 0, 8, 16, or 24 bits
9667 before extracting the 16-bit value.
9668 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9669 Condition defaults to COND_ALWAYS.
9670 Error if any register uses R15. */
9675 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9676 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9677 inst
.instruction
|= inst
.operands
[2].reg
;
9678 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9683 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9684 Condition defaults to COND_ALWAYS.
9685 Error if any register uses R15. */
9690 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9691 inst
.instruction
|= inst
.operands
[1].reg
;
9692 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9695 /* VFP instructions. In a logical order: SP variant first, monad
9696 before dyad, arithmetic then move then load/store. */
9699 do_vfp_sp_monadic (void)
9701 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9702 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9706 do_vfp_sp_dyadic (void)
9708 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9709 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9710 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9714 do_vfp_sp_compare_z (void)
9716 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9720 do_vfp_dp_sp_cvt (void)
9722 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9723 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9727 do_vfp_sp_dp_cvt (void)
9729 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9730 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9734 do_vfp_reg_from_sp (void)
9736 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9737 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9741 do_vfp_reg2_from_sp2 (void)
9743 constraint (inst
.operands
[2].imm
!= 2,
9744 _("only two consecutive VFP SP registers allowed here"));
9745 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9746 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9747 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9751 do_vfp_sp_from_reg (void)
9753 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9754 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9758 do_vfp_sp2_from_reg2 (void)
9760 constraint (inst
.operands
[0].imm
!= 2,
9761 _("only two consecutive VFP SP registers allowed here"));
9762 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9763 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9764 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9768 do_vfp_sp_ldst (void)
9770 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9771 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9775 do_vfp_dp_ldst (void)
9777 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9778 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9783 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9785 if (inst
.operands
[0].writeback
)
9786 inst
.instruction
|= WRITE_BACK
;
9788 constraint (ldstm_type
!= VFP_LDSTMIA
,
9789 _("this addressing mode requires base-register writeback"));
9790 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9791 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9792 inst
.instruction
|= inst
.operands
[1].imm
;
9796 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9800 if (inst
.operands
[0].writeback
)
9801 inst
.instruction
|= WRITE_BACK
;
9803 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9804 _("this addressing mode requires base-register writeback"));
9806 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9807 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9809 count
= inst
.operands
[1].imm
<< 1;
9810 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9813 inst
.instruction
|= count
;
9817 do_vfp_sp_ldstmia (void)
9819 vfp_sp_ldstm (VFP_LDSTMIA
);
9823 do_vfp_sp_ldstmdb (void)
9825 vfp_sp_ldstm (VFP_LDSTMDB
);
9829 do_vfp_dp_ldstmia (void)
9831 vfp_dp_ldstm (VFP_LDSTMIA
);
9835 do_vfp_dp_ldstmdb (void)
9837 vfp_dp_ldstm (VFP_LDSTMDB
);
9841 do_vfp_xp_ldstmia (void)
9843 vfp_dp_ldstm (VFP_LDSTMIAX
);
9847 do_vfp_xp_ldstmdb (void)
9849 vfp_dp_ldstm (VFP_LDSTMDBX
);
9853 do_vfp_dp_rd_rm (void)
9855 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9856 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9860 do_vfp_dp_rn_rd (void)
9862 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9863 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9867 do_vfp_dp_rd_rn (void)
9869 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9870 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9874 do_vfp_dp_rd_rn_rm (void)
9876 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9877 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9878 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9884 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9888 do_vfp_dp_rm_rd_rn (void)
9890 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9891 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9892 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9895 /* VFPv3 instructions. */
9897 do_vfp_sp_const (void)
9899 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9900 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9901 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9905 do_vfp_dp_const (void)
9907 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9908 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9909 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9913 vfp_conv (int srcsize
)
9915 int immbits
= srcsize
- inst
.operands
[1].imm
;
9917 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9919 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9920 i.e. immbits must be in range 0 - 16. */
9921 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9924 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9926 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9927 i.e. immbits must be in range 0 - 31. */
9928 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9932 inst
.instruction
|= (immbits
& 1) << 5;
9933 inst
.instruction
|= (immbits
>> 1);
9937 do_vfp_sp_conv_16 (void)
9939 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9944 do_vfp_dp_conv_16 (void)
9946 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9951 do_vfp_sp_conv_32 (void)
9953 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9958 do_vfp_dp_conv_32 (void)
9960 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9964 /* FPA instructions. Also in a logical order. */
9969 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9970 inst
.instruction
|= inst
.operands
[1].reg
;
9974 do_fpa_ldmstm (void)
9976 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9977 switch (inst
.operands
[1].imm
)
9979 case 1: inst
.instruction
|= CP_T_X
; break;
9980 case 2: inst
.instruction
|= CP_T_Y
; break;
9981 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9986 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9988 /* The instruction specified "ea" or "fd", so we can only accept
9989 [Rn]{!}. The instruction does not really support stacking or
9990 unstacking, so we have to emulate these by setting appropriate
9991 bits and offsets. */
9992 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9993 || inst
.reloc
.exp
.X_add_number
!= 0,
9994 _("this instruction does not support indexing"));
9996 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9997 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9999 if (!(inst
.instruction
& INDEX_UP
))
10000 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
10002 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10004 inst
.operands
[2].preind
= 0;
10005 inst
.operands
[2].postind
= 1;
10009 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10012 /* iWMMXt instructions: strictly in alphabetical order. */
10015 do_iwmmxt_tandorc (void)
10017 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10021 do_iwmmxt_textrc (void)
10023 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10024 inst
.instruction
|= inst
.operands
[1].imm
;
10028 do_iwmmxt_textrm (void)
10030 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10031 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10032 inst
.instruction
|= inst
.operands
[2].imm
;
10036 do_iwmmxt_tinsr (void)
10038 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10039 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10040 inst
.instruction
|= inst
.operands
[2].imm
;
10044 do_iwmmxt_tmia (void)
10046 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10047 inst
.instruction
|= inst
.operands
[1].reg
;
10048 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10052 do_iwmmxt_waligni (void)
10054 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10055 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10056 inst
.instruction
|= inst
.operands
[2].reg
;
10057 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10061 do_iwmmxt_wmerge (void)
10063 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10064 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10065 inst
.instruction
|= inst
.operands
[2].reg
;
10066 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10070 do_iwmmxt_wmov (void)
10072 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10073 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10074 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10075 inst
.instruction
|= inst
.operands
[1].reg
;
10079 do_iwmmxt_wldstbh (void)
10082 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10084 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10086 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10087 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10091 do_iwmmxt_wldstw (void)
10093 /* RIWR_RIWC clears .isreg for a control register. */
10094 if (!inst
.operands
[0].isreg
)
10096 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10097 inst
.instruction
|= 0xf0000000;
10100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10101 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10105 do_iwmmxt_wldstd (void)
10107 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10108 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10109 && inst
.operands
[1].immisreg
)
10111 inst
.instruction
&= ~0x1a000ff;
10112 inst
.instruction
|= (0xfU
<< 28);
10113 if (inst
.operands
[1].preind
)
10114 inst
.instruction
|= PRE_INDEX
;
10115 if (!inst
.operands
[1].negative
)
10116 inst
.instruction
|= INDEX_UP
;
10117 if (inst
.operands
[1].writeback
)
10118 inst
.instruction
|= WRITE_BACK
;
10119 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10120 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10121 inst
.instruction
|= inst
.operands
[1].imm
;
10124 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10128 do_iwmmxt_wshufh (void)
10130 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10131 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10132 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10133 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10137 do_iwmmxt_wzero (void)
10139 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10140 inst
.instruction
|= inst
.operands
[0].reg
;
10141 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10142 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10146 do_iwmmxt_wrwrwr_or_imm5 (void)
10148 if (inst
.operands
[2].isreg
)
10151 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10152 _("immediate operand requires iWMMXt2"));
10154 if (inst
.operands
[2].imm
== 0)
10156 switch ((inst
.instruction
>> 20) & 0xf)
10162 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10163 inst
.operands
[2].imm
= 16;
10164 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10170 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10171 inst
.operands
[2].imm
= 32;
10172 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10179 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10181 wrn
= (inst
.instruction
>> 16) & 0xf;
10182 inst
.instruction
&= 0xff0fff0f;
10183 inst
.instruction
|= wrn
;
10184 /* Bail out here; the instruction is now assembled. */
10189 /* Map 32 -> 0, etc. */
10190 inst
.operands
[2].imm
&= 0x1f;
10191 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10195 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10196 operations first, then control, shift, and load/store. */
10198 /* Insns like "foo X,Y,Z". */
10201 do_mav_triple (void)
10203 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10204 inst
.instruction
|= inst
.operands
[1].reg
;
10205 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10208 /* Insns like "foo W,X,Y,Z".
10209 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10214 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10215 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10216 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10217 inst
.instruction
|= inst
.operands
[3].reg
;
10220 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10222 do_mav_dspsc (void)
10224 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10227 /* Maverick shift immediate instructions.
10228 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10229 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10232 do_mav_shift (void)
10234 int imm
= inst
.operands
[2].imm
;
10236 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10237 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10239 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10240 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10241 Bit 4 should be 0. */
10242 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10244 inst
.instruction
|= imm
;
10247 /* XScale instructions. Also sorted arithmetic before move. */
10249 /* Xscale multiply-accumulate (argument parse)
10252 MIAxycc acc0,Rm,Rs. */
10257 inst
.instruction
|= inst
.operands
[1].reg
;
10258 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10261 /* Xscale move-accumulator-register (argument parse)
10263 MARcc acc0,RdLo,RdHi. */
10268 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10269 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10272 /* Xscale move-register-accumulator (argument parse)
10274 MRAcc RdLo,RdHi,acc0. */
10279 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10280 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10281 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10284 /* Encoding functions relevant only to Thumb. */
10286 /* inst.operands[i] is a shifted-register operand; encode
10287 it into inst.instruction in the format used by Thumb32. */
10290 encode_thumb32_shifted_operand (int i
)
10292 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10293 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10295 constraint (inst
.operands
[i
].immisreg
,
10296 _("shift by register not allowed in thumb mode"));
10297 inst
.instruction
|= inst
.operands
[i
].reg
;
10298 if (shift
== SHIFT_RRX
)
10299 inst
.instruction
|= SHIFT_ROR
<< 4;
10302 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10303 _("expression too complex"));
10305 constraint (value
> 32
10306 || (value
== 32 && (shift
== SHIFT_LSL
10307 || shift
== SHIFT_ROR
)),
10308 _("shift expression is too large"));
10312 else if (value
== 32)
10315 inst
.instruction
|= shift
<< 4;
10316 inst
.instruction
|= (value
& 0x1c) << 10;
10317 inst
.instruction
|= (value
& 0x03) << 6;
10322 /* inst.operands[i] was set up by parse_address. Encode it into a
10323 Thumb32 format load or store instruction. Reject forms that cannot
10324 be used with such instructions. If is_t is true, reject forms that
10325 cannot be used with a T instruction; if is_d is true, reject forms
10326 that cannot be used with a D instruction. If it is a store insn,
10327 reject PC in Rn. */
10330 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10332 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10334 constraint (!inst
.operands
[i
].isreg
,
10335 _("Instruction does not support =N addresses"));
10337 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10338 if (inst
.operands
[i
].immisreg
)
10340 constraint (is_pc
, BAD_PC_ADDRESSING
);
10341 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10342 constraint (inst
.operands
[i
].negative
,
10343 _("Thumb does not support negative register indexing"));
10344 constraint (inst
.operands
[i
].postind
,
10345 _("Thumb does not support register post-indexing"));
10346 constraint (inst
.operands
[i
].writeback
,
10347 _("Thumb does not support register indexing with writeback"));
10348 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10349 _("Thumb supports only LSL in shifted register indexing"));
10351 inst
.instruction
|= inst
.operands
[i
].imm
;
10352 if (inst
.operands
[i
].shifted
)
10354 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10355 _("expression too complex"));
10356 constraint (inst
.reloc
.exp
.X_add_number
< 0
10357 || inst
.reloc
.exp
.X_add_number
> 3,
10358 _("shift out of range"));
10359 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10361 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10363 else if (inst
.operands
[i
].preind
)
10365 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10366 constraint (is_t
&& inst
.operands
[i
].writeback
,
10367 _("cannot use writeback with this instruction"));
10368 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10369 BAD_PC_ADDRESSING
);
10373 inst
.instruction
|= 0x01000000;
10374 if (inst
.operands
[i
].writeback
)
10375 inst
.instruction
|= 0x00200000;
10379 inst
.instruction
|= 0x00000c00;
10380 if (inst
.operands
[i
].writeback
)
10381 inst
.instruction
|= 0x00000100;
10383 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10385 else if (inst
.operands
[i
].postind
)
10387 gas_assert (inst
.operands
[i
].writeback
);
10388 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10389 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10392 inst
.instruction
|= 0x00200000;
10394 inst
.instruction
|= 0x00000900;
10395 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10397 else /* unindexed - only for coprocessor */
10398 inst
.error
= _("instruction does not accept unindexed addressing");
10401 /* Table of Thumb instructions which exist in both 16- and 32-bit
10402 encodings (the latter only in post-V6T2 cores). The index is the
10403 value used in the insns table below. When there is more than one
10404 possible 16-bit encoding for the instruction, this table always
10406 Also contains several pseudo-instructions used during relaxation. */
10407 #define T16_32_TAB \
10408 X(_adc, 4140, eb400000), \
10409 X(_adcs, 4140, eb500000), \
10410 X(_add, 1c00, eb000000), \
10411 X(_adds, 1c00, eb100000), \
10412 X(_addi, 0000, f1000000), \
10413 X(_addis, 0000, f1100000), \
10414 X(_add_pc,000f, f20f0000), \
10415 X(_add_sp,000d, f10d0000), \
10416 X(_adr, 000f, f20f0000), \
10417 X(_and, 4000, ea000000), \
10418 X(_ands, 4000, ea100000), \
10419 X(_asr, 1000, fa40f000), \
10420 X(_asrs, 1000, fa50f000), \
10421 X(_b, e000, f000b000), \
10422 X(_bcond, d000, f0008000), \
10423 X(_bic, 4380, ea200000), \
10424 X(_bics, 4380, ea300000), \
10425 X(_cmn, 42c0, eb100f00), \
10426 X(_cmp, 2800, ebb00f00), \
10427 X(_cpsie, b660, f3af8400), \
10428 X(_cpsid, b670, f3af8600), \
10429 X(_cpy, 4600, ea4f0000), \
10430 X(_dec_sp,80dd, f1ad0d00), \
10431 X(_eor, 4040, ea800000), \
10432 X(_eors, 4040, ea900000), \
10433 X(_inc_sp,00dd, f10d0d00), \
10434 X(_ldmia, c800, e8900000), \
10435 X(_ldr, 6800, f8500000), \
10436 X(_ldrb, 7800, f8100000), \
10437 X(_ldrh, 8800, f8300000), \
10438 X(_ldrsb, 5600, f9100000), \
10439 X(_ldrsh, 5e00, f9300000), \
10440 X(_ldr_pc,4800, f85f0000), \
10441 X(_ldr_pc2,4800, f85f0000), \
10442 X(_ldr_sp,9800, f85d0000), \
10443 X(_lsl, 0000, fa00f000), \
10444 X(_lsls, 0000, fa10f000), \
10445 X(_lsr, 0800, fa20f000), \
10446 X(_lsrs, 0800, fa30f000), \
10447 X(_mov, 2000, ea4f0000), \
10448 X(_movs, 2000, ea5f0000), \
10449 X(_mul, 4340, fb00f000), \
10450 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10451 X(_mvn, 43c0, ea6f0000), \
10452 X(_mvns, 43c0, ea7f0000), \
10453 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10454 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10455 X(_orr, 4300, ea400000), \
10456 X(_orrs, 4300, ea500000), \
10457 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10458 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10459 X(_rev, ba00, fa90f080), \
10460 X(_rev16, ba40, fa90f090), \
10461 X(_revsh, bac0, fa90f0b0), \
10462 X(_ror, 41c0, fa60f000), \
10463 X(_rors, 41c0, fa70f000), \
10464 X(_sbc, 4180, eb600000), \
10465 X(_sbcs, 4180, eb700000), \
10466 X(_stmia, c000, e8800000), \
10467 X(_str, 6000, f8400000), \
10468 X(_strb, 7000, f8000000), \
10469 X(_strh, 8000, f8200000), \
10470 X(_str_sp,9000, f84d0000), \
10471 X(_sub, 1e00, eba00000), \
10472 X(_subs, 1e00, ebb00000), \
10473 X(_subi, 8000, f1a00000), \
10474 X(_subis, 8000, f1b00000), \
10475 X(_sxtb, b240, fa4ff080), \
10476 X(_sxth, b200, fa0ff080), \
10477 X(_tst, 4200, ea100f00), \
10478 X(_uxtb, b2c0, fa5ff080), \
10479 X(_uxth, b280, fa1ff080), \
10480 X(_nop, bf00, f3af8000), \
10481 X(_yield, bf10, f3af8001), \
10482 X(_wfe, bf20, f3af8002), \
10483 X(_wfi, bf30, f3af8003), \
10484 X(_sev, bf40, f3af8004), \
10485 X(_sevl, bf50, f3af8005), \
10486 X(_udf, de00, f7f0a000)
10488 /* To catch errors in encoding functions, the codes are all offset by
10489 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10490 as 16-bit instructions. */
10491 #define X(a,b,c) T_MNEM##a
10492 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10495 #define X(a,b,c) 0x##b
10496 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10497 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10500 #define X(a,b,c) 0x##c
10501 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10502 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10503 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10507 /* Thumb instruction encoders, in alphabetical order. */
10509 /* ADDW or SUBW. */
10512 do_t_add_sub_w (void)
10516 Rd
= inst
.operands
[0].reg
;
10517 Rn
= inst
.operands
[1].reg
;
10519 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10520 is the SP-{plus,minus}-immediate form of the instruction. */
10522 constraint (Rd
== REG_PC
, BAD_PC
);
10524 reject_bad_reg (Rd
);
10526 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10527 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10530 /* Parse an add or subtract instruction. We get here with inst.instruction
10531 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10534 do_t_add_sub (void)
10538 Rd
= inst
.operands
[0].reg
;
10539 Rs
= (inst
.operands
[1].present
10540 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10541 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10544 set_it_insn_type_last ();
10546 if (unified_syntax
)
10549 bfd_boolean narrow
;
10552 flags
= (inst
.instruction
== T_MNEM_adds
10553 || inst
.instruction
== T_MNEM_subs
);
10555 narrow
= !in_it_block ();
10557 narrow
= in_it_block ();
10558 if (!inst
.operands
[2].isreg
)
10562 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10563 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10565 add
= (inst
.instruction
== T_MNEM_add
10566 || inst
.instruction
== T_MNEM_adds
);
10568 if (inst
.size_req
!= 4)
10570 /* Attempt to use a narrow opcode, with relaxation if
10572 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10573 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10574 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10575 opcode
= T_MNEM_add_sp
;
10576 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10577 opcode
= T_MNEM_add_pc
;
10578 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10581 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10583 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10587 inst
.instruction
= THUMB_OP16(opcode
);
10588 inst
.instruction
|= (Rd
<< 4) | Rs
;
10589 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10590 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10592 if (inst
.size_req
== 2)
10593 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10595 inst
.relax
= opcode
;
10599 constraint (inst
.size_req
== 2, BAD_HIREG
);
10601 if (inst
.size_req
== 4
10602 || (inst
.size_req
!= 2 && !opcode
))
10604 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10605 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10606 THUMB1_RELOC_ONLY
);
10609 constraint (add
, BAD_PC
);
10610 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10611 _("only SUBS PC, LR, #const allowed"));
10612 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10613 _("expression too complex"));
10614 constraint (inst
.reloc
.exp
.X_add_number
< 0
10615 || inst
.reloc
.exp
.X_add_number
> 0xff,
10616 _("immediate value out of range"));
10617 inst
.instruction
= T2_SUBS_PC_LR
10618 | inst
.reloc
.exp
.X_add_number
;
10619 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10622 else if (Rs
== REG_PC
)
10624 /* Always use addw/subw. */
10625 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10626 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10630 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10631 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10634 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10636 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10638 inst
.instruction
|= Rd
<< 8;
10639 inst
.instruction
|= Rs
<< 16;
10644 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10645 unsigned int shift
= inst
.operands
[2].shift_kind
;
10647 Rn
= inst
.operands
[2].reg
;
10648 /* See if we can do this with a 16-bit instruction. */
10649 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10651 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10656 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10657 || inst
.instruction
== T_MNEM_add
)
10659 : T_OPCODE_SUB_R3
);
10660 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10664 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10666 /* Thumb-1 cores (except v6-M) require at least one high
10667 register in a narrow non flag setting add. */
10668 if (Rd
> 7 || Rn
> 7
10669 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10670 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10677 inst
.instruction
= T_OPCODE_ADD_HI
;
10678 inst
.instruction
|= (Rd
& 8) << 4;
10679 inst
.instruction
|= (Rd
& 7);
10680 inst
.instruction
|= Rn
<< 3;
10686 constraint (Rd
== REG_PC
, BAD_PC
);
10687 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10688 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10689 constraint (Rs
== REG_PC
, BAD_PC
);
10690 reject_bad_reg (Rn
);
10692 /* If we get here, it can't be done in 16 bits. */
10693 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10694 _("shift must be constant"));
10695 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10696 inst
.instruction
|= Rd
<< 8;
10697 inst
.instruction
|= Rs
<< 16;
10698 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10699 _("shift value over 3 not allowed in thumb mode"));
10700 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10701 _("only LSL shift allowed in thumb mode"));
10702 encode_thumb32_shifted_operand (2);
10707 constraint (inst
.instruction
== T_MNEM_adds
10708 || inst
.instruction
== T_MNEM_subs
,
10711 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10713 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10714 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10717 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10718 ? 0x0000 : 0x8000);
10719 inst
.instruction
|= (Rd
<< 4) | Rs
;
10720 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10724 Rn
= inst
.operands
[2].reg
;
10725 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10727 /* We now have Rd, Rs, and Rn set to registers. */
10728 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10730 /* Can't do this for SUB. */
10731 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10732 inst
.instruction
= T_OPCODE_ADD_HI
;
10733 inst
.instruction
|= (Rd
& 8) << 4;
10734 inst
.instruction
|= (Rd
& 7);
10736 inst
.instruction
|= Rn
<< 3;
10738 inst
.instruction
|= Rs
<< 3;
10740 constraint (1, _("dest must overlap one source register"));
10744 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10745 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10746 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10756 Rd
= inst
.operands
[0].reg
;
10757 reject_bad_reg (Rd
);
10759 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10761 /* Defer to section relaxation. */
10762 inst
.relax
= inst
.instruction
;
10763 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10764 inst
.instruction
|= Rd
<< 4;
10766 else if (unified_syntax
&& inst
.size_req
!= 2)
10768 /* Generate a 32-bit opcode. */
10769 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10770 inst
.instruction
|= Rd
<< 8;
10771 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10772 inst
.reloc
.pc_rel
= 1;
10776 /* Generate a 16-bit opcode. */
10777 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10778 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10779 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10780 inst
.reloc
.pc_rel
= 1;
10781 inst
.instruction
|= Rd
<< 4;
10784 if (inst
.reloc
.exp
.X_op
== O_symbol
10785 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10786 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10787 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10788 inst
.reloc
.exp
.X_add_number
+= 1;
10791 /* Arithmetic instructions for which there is just one 16-bit
10792 instruction encoding, and it allows only two low registers.
10793 For maximal compatibility with ARM syntax, we allow three register
10794 operands even when Thumb-32 instructions are not available, as long
10795 as the first two are identical. For instance, both "sbc r0,r1" and
10796 "sbc r0,r0,r1" are allowed. */
10802 Rd
= inst
.operands
[0].reg
;
10803 Rs
= (inst
.operands
[1].present
10804 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10805 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10806 Rn
= inst
.operands
[2].reg
;
10808 reject_bad_reg (Rd
);
10809 reject_bad_reg (Rs
);
10810 if (inst
.operands
[2].isreg
)
10811 reject_bad_reg (Rn
);
10813 if (unified_syntax
)
10815 if (!inst
.operands
[2].isreg
)
10817 /* For an immediate, we always generate a 32-bit opcode;
10818 section relaxation will shrink it later if possible. */
10819 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10820 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10821 inst
.instruction
|= Rd
<< 8;
10822 inst
.instruction
|= Rs
<< 16;
10823 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10827 bfd_boolean narrow
;
10829 /* See if we can do this with a 16-bit instruction. */
10830 if (THUMB_SETS_FLAGS (inst
.instruction
))
10831 narrow
= !in_it_block ();
10833 narrow
= in_it_block ();
10835 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10837 if (inst
.operands
[2].shifted
)
10839 if (inst
.size_req
== 4)
10845 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10846 inst
.instruction
|= Rd
;
10847 inst
.instruction
|= Rn
<< 3;
10851 /* If we get here, it can't be done in 16 bits. */
10852 constraint (inst
.operands
[2].shifted
10853 && inst
.operands
[2].immisreg
,
10854 _("shift must be constant"));
10855 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10856 inst
.instruction
|= Rd
<< 8;
10857 inst
.instruction
|= Rs
<< 16;
10858 encode_thumb32_shifted_operand (2);
10863 /* On its face this is a lie - the instruction does set the
10864 flags. However, the only supported mnemonic in this mode
10865 says it doesn't. */
10866 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10868 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10869 _("unshifted register required"));
10870 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10871 constraint (Rd
!= Rs
,
10872 _("dest and source1 must be the same register"));
10874 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10875 inst
.instruction
|= Rd
;
10876 inst
.instruction
|= Rn
<< 3;
10880 /* Similarly, but for instructions where the arithmetic operation is
10881 commutative, so we can allow either of them to be different from
10882 the destination operand in a 16-bit instruction. For instance, all
10883 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10890 Rd
= inst
.operands
[0].reg
;
10891 Rs
= (inst
.operands
[1].present
10892 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10893 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10894 Rn
= inst
.operands
[2].reg
;
10896 reject_bad_reg (Rd
);
10897 reject_bad_reg (Rs
);
10898 if (inst
.operands
[2].isreg
)
10899 reject_bad_reg (Rn
);
10901 if (unified_syntax
)
10903 if (!inst
.operands
[2].isreg
)
10905 /* For an immediate, we always generate a 32-bit opcode;
10906 section relaxation will shrink it later if possible. */
10907 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10908 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10909 inst
.instruction
|= Rd
<< 8;
10910 inst
.instruction
|= Rs
<< 16;
10911 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10915 bfd_boolean narrow
;
10917 /* See if we can do this with a 16-bit instruction. */
10918 if (THUMB_SETS_FLAGS (inst
.instruction
))
10919 narrow
= !in_it_block ();
10921 narrow
= in_it_block ();
10923 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10925 if (inst
.operands
[2].shifted
)
10927 if (inst
.size_req
== 4)
10934 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10935 inst
.instruction
|= Rd
;
10936 inst
.instruction
|= Rn
<< 3;
10941 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10942 inst
.instruction
|= Rd
;
10943 inst
.instruction
|= Rs
<< 3;
10948 /* If we get here, it can't be done in 16 bits. */
10949 constraint (inst
.operands
[2].shifted
10950 && inst
.operands
[2].immisreg
,
10951 _("shift must be constant"));
10952 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10953 inst
.instruction
|= Rd
<< 8;
10954 inst
.instruction
|= Rs
<< 16;
10955 encode_thumb32_shifted_operand (2);
10960 /* On its face this is a lie - the instruction does set the
10961 flags. However, the only supported mnemonic in this mode
10962 says it doesn't. */
10963 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10965 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10966 _("unshifted register required"));
10967 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10969 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10970 inst
.instruction
|= Rd
;
10973 inst
.instruction
|= Rn
<< 3;
10975 inst
.instruction
|= Rs
<< 3;
10977 constraint (1, _("dest must overlap one source register"));
10985 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10986 constraint (msb
> 32, _("bit-field extends past end of register"));
10987 /* The instruction encoding stores the LSB and MSB,
10988 not the LSB and width. */
10989 Rd
= inst
.operands
[0].reg
;
10990 reject_bad_reg (Rd
);
10991 inst
.instruction
|= Rd
<< 8;
10992 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10993 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10994 inst
.instruction
|= msb
- 1;
11003 Rd
= inst
.operands
[0].reg
;
11004 reject_bad_reg (Rd
);
11006 /* #0 in second position is alternative syntax for bfc, which is
11007 the same instruction but with REG_PC in the Rm field. */
11008 if (!inst
.operands
[1].isreg
)
11012 Rn
= inst
.operands
[1].reg
;
11013 reject_bad_reg (Rn
);
11016 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11017 constraint (msb
> 32, _("bit-field extends past end of register"));
11018 /* The instruction encoding stores the LSB and MSB,
11019 not the LSB and width. */
11020 inst
.instruction
|= Rd
<< 8;
11021 inst
.instruction
|= Rn
<< 16;
11022 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11023 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11024 inst
.instruction
|= msb
- 1;
11032 Rd
= inst
.operands
[0].reg
;
11033 Rn
= inst
.operands
[1].reg
;
11035 reject_bad_reg (Rd
);
11036 reject_bad_reg (Rn
);
11038 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11039 _("bit-field extends past end of register"));
11040 inst
.instruction
|= Rd
<< 8;
11041 inst
.instruction
|= Rn
<< 16;
11042 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11043 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11044 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11047 /* ARM V5 Thumb BLX (argument parse)
11048 BLX <target_addr> which is BLX(1)
11049 BLX <Rm> which is BLX(2)
11050 Unfortunately, there are two different opcodes for this mnemonic.
11051 So, the insns[].value is not used, and the code here zaps values
11052 into inst.instruction.
11054 ??? How to take advantage of the additional two bits of displacement
11055 available in Thumb32 mode? Need new relocation? */
11060 set_it_insn_type_last ();
11062 if (inst
.operands
[0].isreg
)
11064 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11065 /* We have a register, so this is BLX(2). */
11066 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11070 /* No register. This must be BLX(1). */
11071 inst
.instruction
= 0xf000e800;
11072 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11081 bfd_reloc_code_real_type reloc
;
11084 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11086 if (in_it_block ())
11088 /* Conditional branches inside IT blocks are encoded as unconditional
11090 cond
= COND_ALWAYS
;
11095 if (cond
!= COND_ALWAYS
)
11096 opcode
= T_MNEM_bcond
;
11098 opcode
= inst
.instruction
;
11101 && (inst
.size_req
== 4
11102 || (inst
.size_req
!= 2
11103 && (inst
.operands
[0].hasreloc
11104 || inst
.reloc
.exp
.X_op
== O_constant
))))
11106 inst
.instruction
= THUMB_OP32(opcode
);
11107 if (cond
== COND_ALWAYS
)
11108 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11111 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11112 _("selected architecture does not support "
11113 "wide conditional branch instruction"));
11115 gas_assert (cond
!= 0xF);
11116 inst
.instruction
|= cond
<< 22;
11117 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11122 inst
.instruction
= THUMB_OP16(opcode
);
11123 if (cond
== COND_ALWAYS
)
11124 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11127 inst
.instruction
|= cond
<< 8;
11128 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11130 /* Allow section relaxation. */
11131 if (unified_syntax
&& inst
.size_req
!= 2)
11132 inst
.relax
= opcode
;
11134 inst
.reloc
.type
= reloc
;
11135 inst
.reloc
.pc_rel
= 1;
11138 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11139 between the two is the maximum immediate allowed - which is passed in
11142 do_t_bkpt_hlt1 (int range
)
11144 constraint (inst
.cond
!= COND_ALWAYS
,
11145 _("instruction is always unconditional"));
11146 if (inst
.operands
[0].present
)
11148 constraint (inst
.operands
[0].imm
> range
,
11149 _("immediate value out of range"));
11150 inst
.instruction
|= inst
.operands
[0].imm
;
11153 set_it_insn_type (NEUTRAL_IT_INSN
);
11159 do_t_bkpt_hlt1 (63);
11165 do_t_bkpt_hlt1 (255);
11169 do_t_branch23 (void)
11171 set_it_insn_type_last ();
11172 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11174 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11175 this file. We used to simply ignore the PLT reloc type here --
11176 the branch encoding is now needed to deal with TLSCALL relocs.
11177 So if we see a PLT reloc now, put it back to how it used to be to
11178 keep the preexisting behaviour. */
11179 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11180 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11182 #if defined(OBJ_COFF)
11183 /* If the destination of the branch is a defined symbol which does not have
11184 the THUMB_FUNC attribute, then we must be calling a function which has
11185 the (interfacearm) attribute. We look for the Thumb entry point to that
11186 function and change the branch to refer to that function instead. */
11187 if ( inst
.reloc
.exp
.X_op
== O_symbol
11188 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11189 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11190 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11191 inst
.reloc
.exp
.X_add_symbol
=
11192 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11199 set_it_insn_type_last ();
11200 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11201 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11202 should cause the alignment to be checked once it is known. This is
11203 because BX PC only works if the instruction is word aligned. */
11211 set_it_insn_type_last ();
11212 Rm
= inst
.operands
[0].reg
;
11213 reject_bad_reg (Rm
);
11214 inst
.instruction
|= Rm
<< 16;
11223 Rd
= inst
.operands
[0].reg
;
11224 Rm
= inst
.operands
[1].reg
;
11226 reject_bad_reg (Rd
);
11227 reject_bad_reg (Rm
);
11229 inst
.instruction
|= Rd
<< 8;
11230 inst
.instruction
|= Rm
<< 16;
11231 inst
.instruction
|= Rm
;
11237 set_it_insn_type (OUTSIDE_IT_INSN
);
11238 inst
.instruction
|= inst
.operands
[0].imm
;
11244 set_it_insn_type (OUTSIDE_IT_INSN
);
11246 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11247 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11249 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11250 inst
.instruction
= 0xf3af8000;
11251 inst
.instruction
|= imod
<< 9;
11252 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11253 if (inst
.operands
[1].present
)
11254 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11258 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11259 && (inst
.operands
[0].imm
& 4),
11260 _("selected processor does not support 'A' form "
11261 "of this instruction"));
11262 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11263 _("Thumb does not support the 2-argument "
11264 "form of this instruction"));
11265 inst
.instruction
|= inst
.operands
[0].imm
;
11269 /* THUMB CPY instruction (argument parse). */
11274 if (inst
.size_req
== 4)
11276 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11277 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11278 inst
.instruction
|= inst
.operands
[1].reg
;
11282 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11283 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11284 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11291 set_it_insn_type (OUTSIDE_IT_INSN
);
11292 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11293 inst
.instruction
|= inst
.operands
[0].reg
;
11294 inst
.reloc
.pc_rel
= 1;
11295 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11301 inst
.instruction
|= inst
.operands
[0].imm
;
11307 unsigned Rd
, Rn
, Rm
;
11309 Rd
= inst
.operands
[0].reg
;
11310 Rn
= (inst
.operands
[1].present
11311 ? inst
.operands
[1].reg
: Rd
);
11312 Rm
= inst
.operands
[2].reg
;
11314 reject_bad_reg (Rd
);
11315 reject_bad_reg (Rn
);
11316 reject_bad_reg (Rm
);
11318 inst
.instruction
|= Rd
<< 8;
11319 inst
.instruction
|= Rn
<< 16;
11320 inst
.instruction
|= Rm
;
11326 if (unified_syntax
&& inst
.size_req
== 4)
11327 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11329 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11335 unsigned int cond
= inst
.operands
[0].imm
;
11337 set_it_insn_type (IT_INSN
);
11338 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11340 now_it
.warn_deprecated
= FALSE
;
11342 /* If the condition is a negative condition, invert the mask. */
11343 if ((cond
& 0x1) == 0x0)
11345 unsigned int mask
= inst
.instruction
& 0x000f;
11347 if ((mask
& 0x7) == 0)
11349 /* No conversion needed. */
11350 now_it
.block_length
= 1;
11352 else if ((mask
& 0x3) == 0)
11355 now_it
.block_length
= 2;
11357 else if ((mask
& 0x1) == 0)
11360 now_it
.block_length
= 3;
11365 now_it
.block_length
= 4;
11368 inst
.instruction
&= 0xfff0;
11369 inst
.instruction
|= mask
;
11372 inst
.instruction
|= cond
<< 4;
11375 /* Helper function used for both push/pop and ldm/stm. */
11377 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11381 load
= (inst
.instruction
& (1 << 20)) != 0;
11383 if (mask
& (1 << 13))
11384 inst
.error
= _("SP not allowed in register list");
11386 if ((mask
& (1 << base
)) != 0
11388 inst
.error
= _("having the base register in the register list when "
11389 "using write back is UNPREDICTABLE");
11393 if (mask
& (1 << 15))
11395 if (mask
& (1 << 14))
11396 inst
.error
= _("LR and PC should not both be in register list");
11398 set_it_insn_type_last ();
11403 if (mask
& (1 << 15))
11404 inst
.error
= _("PC not allowed in register list");
11407 if ((mask
& (mask
- 1)) == 0)
11409 /* Single register transfers implemented as str/ldr. */
11412 if (inst
.instruction
& (1 << 23))
11413 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11415 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11419 if (inst
.instruction
& (1 << 23))
11420 inst
.instruction
= 0x00800000; /* ia -> [base] */
11422 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11425 inst
.instruction
|= 0xf8400000;
11427 inst
.instruction
|= 0x00100000;
11429 mask
= ffs (mask
) - 1;
11432 else if (writeback
)
11433 inst
.instruction
|= WRITE_BACK
;
11435 inst
.instruction
|= mask
;
11436 inst
.instruction
|= base
<< 16;
11442 /* This really doesn't seem worth it. */
11443 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11444 _("expression too complex"));
11445 constraint (inst
.operands
[1].writeback
,
11446 _("Thumb load/store multiple does not support {reglist}^"));
11448 if (unified_syntax
)
11450 bfd_boolean narrow
;
11454 /* See if we can use a 16-bit instruction. */
11455 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11456 && inst
.size_req
!= 4
11457 && !(inst
.operands
[1].imm
& ~0xff))
11459 mask
= 1 << inst
.operands
[0].reg
;
11461 if (inst
.operands
[0].reg
<= 7)
11463 if (inst
.instruction
== T_MNEM_stmia
11464 ? inst
.operands
[0].writeback
11465 : (inst
.operands
[0].writeback
11466 == !(inst
.operands
[1].imm
& mask
)))
11468 if (inst
.instruction
== T_MNEM_stmia
11469 && (inst
.operands
[1].imm
& mask
)
11470 && (inst
.operands
[1].imm
& (mask
- 1)))
11471 as_warn (_("value stored for r%d is UNKNOWN"),
11472 inst
.operands
[0].reg
);
11474 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11475 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11476 inst
.instruction
|= inst
.operands
[1].imm
;
11479 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11481 /* This means 1 register in reg list one of 3 situations:
11482 1. Instruction is stmia, but without writeback.
11483 2. lmdia without writeback, but with Rn not in
11485 3. ldmia with writeback, but with Rn in reglist.
11486 Case 3 is UNPREDICTABLE behaviour, so we handle
11487 case 1 and 2 which can be converted into a 16-bit
11488 str or ldr. The SP cases are handled below. */
11489 unsigned long opcode
;
11490 /* First, record an error for Case 3. */
11491 if (inst
.operands
[1].imm
& mask
11492 && inst
.operands
[0].writeback
)
11494 _("having the base register in the register list when "
11495 "using write back is UNPREDICTABLE");
11497 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11499 inst
.instruction
= THUMB_OP16 (opcode
);
11500 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11501 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11505 else if (inst
.operands
[0] .reg
== REG_SP
)
11507 if (inst
.operands
[0].writeback
)
11510 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11511 ? T_MNEM_push
: T_MNEM_pop
);
11512 inst
.instruction
|= inst
.operands
[1].imm
;
11515 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11518 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11519 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11520 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11528 if (inst
.instruction
< 0xffff)
11529 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11531 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11532 inst
.operands
[0].writeback
);
11537 constraint (inst
.operands
[0].reg
> 7
11538 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11539 constraint (inst
.instruction
!= T_MNEM_ldmia
11540 && inst
.instruction
!= T_MNEM_stmia
,
11541 _("Thumb-2 instruction only valid in unified syntax"));
11542 if (inst
.instruction
== T_MNEM_stmia
)
11544 if (!inst
.operands
[0].writeback
)
11545 as_warn (_("this instruction will write back the base register"));
11546 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11547 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11548 as_warn (_("value stored for r%d is UNKNOWN"),
11549 inst
.operands
[0].reg
);
11553 if (!inst
.operands
[0].writeback
11554 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11555 as_warn (_("this instruction will write back the base register"));
11556 else if (inst
.operands
[0].writeback
11557 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11558 as_warn (_("this instruction will not write back the base register"));
11561 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11562 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11563 inst
.instruction
|= inst
.operands
[1].imm
;
11570 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11571 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11572 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11573 || inst
.operands
[1].negative
,
11576 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11578 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11579 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11580 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11586 if (!inst
.operands
[1].present
)
11588 constraint (inst
.operands
[0].reg
== REG_LR
,
11589 _("r14 not allowed as first register "
11590 "when second register is omitted"));
11591 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11593 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11596 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11597 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11598 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11604 unsigned long opcode
;
11607 if (inst
.operands
[0].isreg
11608 && !inst
.operands
[0].preind
11609 && inst
.operands
[0].reg
== REG_PC
)
11610 set_it_insn_type_last ();
11612 opcode
= inst
.instruction
;
11613 if (unified_syntax
)
11615 if (!inst
.operands
[1].isreg
)
11617 if (opcode
<= 0xffff)
11618 inst
.instruction
= THUMB_OP32 (opcode
);
11619 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11622 if (inst
.operands
[1].isreg
11623 && !inst
.operands
[1].writeback
11624 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11625 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11626 && opcode
<= 0xffff
11627 && inst
.size_req
!= 4)
11629 /* Insn may have a 16-bit form. */
11630 Rn
= inst
.operands
[1].reg
;
11631 if (inst
.operands
[1].immisreg
)
11633 inst
.instruction
= THUMB_OP16 (opcode
);
11635 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11637 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11638 reject_bad_reg (inst
.operands
[1].imm
);
11640 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11641 && opcode
!= T_MNEM_ldrsb
)
11642 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11643 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11650 if (inst
.reloc
.pc_rel
)
11651 opcode
= T_MNEM_ldr_pc2
;
11653 opcode
= T_MNEM_ldr_pc
;
11657 if (opcode
== T_MNEM_ldr
)
11658 opcode
= T_MNEM_ldr_sp
;
11660 opcode
= T_MNEM_str_sp
;
11662 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11666 inst
.instruction
= inst
.operands
[0].reg
;
11667 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11669 inst
.instruction
|= THUMB_OP16 (opcode
);
11670 if (inst
.size_req
== 2)
11671 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11673 inst
.relax
= opcode
;
11677 /* Definitely a 32-bit variant. */
11679 /* Warning for Erratum 752419. */
11680 if (opcode
== T_MNEM_ldr
11681 && inst
.operands
[0].reg
== REG_SP
11682 && inst
.operands
[1].writeback
== 1
11683 && !inst
.operands
[1].immisreg
)
11685 if (no_cpu_selected ()
11686 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11687 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11688 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11689 as_warn (_("This instruction may be unpredictable "
11690 "if executed on M-profile cores "
11691 "with interrupts enabled."));
11694 /* Do some validations regarding addressing modes. */
11695 if (inst
.operands
[1].immisreg
)
11696 reject_bad_reg (inst
.operands
[1].imm
);
11698 constraint (inst
.operands
[1].writeback
== 1
11699 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11702 inst
.instruction
= THUMB_OP32 (opcode
);
11703 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11704 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11705 check_ldr_r15_aligned ();
11709 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11711 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11713 /* Only [Rn,Rm] is acceptable. */
11714 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11715 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11716 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11717 || inst
.operands
[1].negative
,
11718 _("Thumb does not support this addressing mode"));
11719 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11723 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11724 if (!inst
.operands
[1].isreg
)
11725 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11728 constraint (!inst
.operands
[1].preind
11729 || inst
.operands
[1].shifted
11730 || inst
.operands
[1].writeback
,
11731 _("Thumb does not support this addressing mode"));
11732 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11734 constraint (inst
.instruction
& 0x0600,
11735 _("byte or halfword not valid for base register"));
11736 constraint (inst
.operands
[1].reg
== REG_PC
11737 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11738 _("r15 based store not allowed"));
11739 constraint (inst
.operands
[1].immisreg
,
11740 _("invalid base register for register offset"));
11742 if (inst
.operands
[1].reg
== REG_PC
)
11743 inst
.instruction
= T_OPCODE_LDR_PC
;
11744 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11745 inst
.instruction
= T_OPCODE_LDR_SP
;
11747 inst
.instruction
= T_OPCODE_STR_SP
;
11749 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11750 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11754 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11755 if (!inst
.operands
[1].immisreg
)
11757 /* Immediate offset. */
11758 inst
.instruction
|= inst
.operands
[0].reg
;
11759 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11760 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11764 /* Register offset. */
11765 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11766 constraint (inst
.operands
[1].negative
,
11767 _("Thumb does not support this addressing mode"));
11770 switch (inst
.instruction
)
11772 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11773 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11774 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11775 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11776 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11777 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11778 case 0x5600 /* ldrsb */:
11779 case 0x5e00 /* ldrsh */: break;
11783 inst
.instruction
|= inst
.operands
[0].reg
;
11784 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11785 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11791 if (!inst
.operands
[1].present
)
11793 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11794 constraint (inst
.operands
[0].reg
== REG_LR
,
11795 _("r14 not allowed here"));
11796 constraint (inst
.operands
[0].reg
== REG_R12
,
11797 _("r12 not allowed here"));
11800 if (inst
.operands
[2].writeback
11801 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11802 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11803 as_warn (_("base register written back, and overlaps "
11804 "one of transfer registers"));
11806 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11807 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11808 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11814 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11815 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11821 unsigned Rd
, Rn
, Rm
, Ra
;
11823 Rd
= inst
.operands
[0].reg
;
11824 Rn
= inst
.operands
[1].reg
;
11825 Rm
= inst
.operands
[2].reg
;
11826 Ra
= inst
.operands
[3].reg
;
11828 reject_bad_reg (Rd
);
11829 reject_bad_reg (Rn
);
11830 reject_bad_reg (Rm
);
11831 reject_bad_reg (Ra
);
11833 inst
.instruction
|= Rd
<< 8;
11834 inst
.instruction
|= Rn
<< 16;
11835 inst
.instruction
|= Rm
;
11836 inst
.instruction
|= Ra
<< 12;
11842 unsigned RdLo
, RdHi
, Rn
, Rm
;
11844 RdLo
= inst
.operands
[0].reg
;
11845 RdHi
= inst
.operands
[1].reg
;
11846 Rn
= inst
.operands
[2].reg
;
11847 Rm
= inst
.operands
[3].reg
;
11849 reject_bad_reg (RdLo
);
11850 reject_bad_reg (RdHi
);
11851 reject_bad_reg (Rn
);
11852 reject_bad_reg (Rm
);
11854 inst
.instruction
|= RdLo
<< 12;
11855 inst
.instruction
|= RdHi
<< 8;
11856 inst
.instruction
|= Rn
<< 16;
11857 inst
.instruction
|= Rm
;
11861 do_t_mov_cmp (void)
11865 Rn
= inst
.operands
[0].reg
;
11866 Rm
= inst
.operands
[1].reg
;
11869 set_it_insn_type_last ();
11871 if (unified_syntax
)
11873 int r0off
= (inst
.instruction
== T_MNEM_mov
11874 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11875 unsigned long opcode
;
11876 bfd_boolean narrow
;
11877 bfd_boolean low_regs
;
11879 low_regs
= (Rn
<= 7 && Rm
<= 7);
11880 opcode
= inst
.instruction
;
11881 if (in_it_block ())
11882 narrow
= opcode
!= T_MNEM_movs
;
11884 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11885 if (inst
.size_req
== 4
11886 || inst
.operands
[1].shifted
)
11889 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11890 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11891 && !inst
.operands
[1].shifted
11895 inst
.instruction
= T2_SUBS_PC_LR
;
11899 if (opcode
== T_MNEM_cmp
)
11901 constraint (Rn
== REG_PC
, BAD_PC
);
11904 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11906 warn_deprecated_sp (Rm
);
11907 /* R15 was documented as a valid choice for Rm in ARMv6,
11908 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11909 tools reject R15, so we do too. */
11910 constraint (Rm
== REG_PC
, BAD_PC
);
11913 reject_bad_reg (Rm
);
11915 else if (opcode
== T_MNEM_mov
11916 || opcode
== T_MNEM_movs
)
11918 if (inst
.operands
[1].isreg
)
11920 if (opcode
== T_MNEM_movs
)
11922 reject_bad_reg (Rn
);
11923 reject_bad_reg (Rm
);
11927 /* This is mov.n. */
11928 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11929 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11931 as_tsktsk (_("Use of r%u as a source register is "
11932 "deprecated when r%u is the destination "
11933 "register."), Rm
, Rn
);
11938 /* This is mov.w. */
11939 constraint (Rn
== REG_PC
, BAD_PC
);
11940 constraint (Rm
== REG_PC
, BAD_PC
);
11941 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11942 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11946 reject_bad_reg (Rn
);
11949 if (!inst
.operands
[1].isreg
)
11951 /* Immediate operand. */
11952 if (!in_it_block () && opcode
== T_MNEM_mov
)
11954 if (low_regs
&& narrow
)
11956 inst
.instruction
= THUMB_OP16 (opcode
);
11957 inst
.instruction
|= Rn
<< 8;
11958 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11959 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11961 if (inst
.size_req
== 2)
11962 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11964 inst
.relax
= opcode
;
11969 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11970 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11971 THUMB1_RELOC_ONLY
);
11973 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11974 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11975 inst
.instruction
|= Rn
<< r0off
;
11976 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11979 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11980 && (inst
.instruction
== T_MNEM_mov
11981 || inst
.instruction
== T_MNEM_movs
))
11983 /* Register shifts are encoded as separate shift instructions. */
11984 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11986 if (in_it_block ())
11991 if (inst
.size_req
== 4)
11994 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12000 switch (inst
.operands
[1].shift_kind
)
12003 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12006 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12009 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12012 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12018 inst
.instruction
= opcode
;
12021 inst
.instruction
|= Rn
;
12022 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12027 inst
.instruction
|= CONDS_BIT
;
12029 inst
.instruction
|= Rn
<< 8;
12030 inst
.instruction
|= Rm
<< 16;
12031 inst
.instruction
|= inst
.operands
[1].imm
;
12036 /* Some mov with immediate shift have narrow variants.
12037 Register shifts are handled above. */
12038 if (low_regs
&& inst
.operands
[1].shifted
12039 && (inst
.instruction
== T_MNEM_mov
12040 || inst
.instruction
== T_MNEM_movs
))
12042 if (in_it_block ())
12043 narrow
= (inst
.instruction
== T_MNEM_mov
);
12045 narrow
= (inst
.instruction
== T_MNEM_movs
);
12050 switch (inst
.operands
[1].shift_kind
)
12052 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12053 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12054 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12055 default: narrow
= FALSE
; break;
12061 inst
.instruction
|= Rn
;
12062 inst
.instruction
|= Rm
<< 3;
12063 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12067 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12068 inst
.instruction
|= Rn
<< r0off
;
12069 encode_thumb32_shifted_operand (1);
12073 switch (inst
.instruction
)
12076 /* In v4t or v5t a move of two lowregs produces unpredictable
12077 results. Don't allow this. */
12080 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12081 "MOV Rd, Rs with two low registers is not "
12082 "permitted on this architecture");
12083 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12087 inst
.instruction
= T_OPCODE_MOV_HR
;
12088 inst
.instruction
|= (Rn
& 0x8) << 4;
12089 inst
.instruction
|= (Rn
& 0x7);
12090 inst
.instruction
|= Rm
<< 3;
12094 /* We know we have low registers at this point.
12095 Generate LSLS Rd, Rs, #0. */
12096 inst
.instruction
= T_OPCODE_LSL_I
;
12097 inst
.instruction
|= Rn
;
12098 inst
.instruction
|= Rm
<< 3;
12104 inst
.instruction
= T_OPCODE_CMP_LR
;
12105 inst
.instruction
|= Rn
;
12106 inst
.instruction
|= Rm
<< 3;
12110 inst
.instruction
= T_OPCODE_CMP_HR
;
12111 inst
.instruction
|= (Rn
& 0x8) << 4;
12112 inst
.instruction
|= (Rn
& 0x7);
12113 inst
.instruction
|= Rm
<< 3;
12120 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12122 /* PR 10443: Do not silently ignore shifted operands. */
12123 constraint (inst
.operands
[1].shifted
,
12124 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12126 if (inst
.operands
[1].isreg
)
12128 if (Rn
< 8 && Rm
< 8)
12130 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12131 since a MOV instruction produces unpredictable results. */
12132 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12133 inst
.instruction
= T_OPCODE_ADD_I3
;
12135 inst
.instruction
= T_OPCODE_CMP_LR
;
12137 inst
.instruction
|= Rn
;
12138 inst
.instruction
|= Rm
<< 3;
12142 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12143 inst
.instruction
= T_OPCODE_MOV_HR
;
12145 inst
.instruction
= T_OPCODE_CMP_HR
;
12151 constraint (Rn
> 7,
12152 _("only lo regs allowed with immediate"));
12153 inst
.instruction
|= Rn
<< 8;
12154 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12165 top
= (inst
.instruction
& 0x00800000) != 0;
12166 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12168 constraint (top
, _(":lower16: not allowed in this instruction"));
12169 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12171 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12173 constraint (!top
, _(":upper16: not allowed in this instruction"));
12174 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12177 Rd
= inst
.operands
[0].reg
;
12178 reject_bad_reg (Rd
);
12180 inst
.instruction
|= Rd
<< 8;
12181 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12183 imm
= inst
.reloc
.exp
.X_add_number
;
12184 inst
.instruction
|= (imm
& 0xf000) << 4;
12185 inst
.instruction
|= (imm
& 0x0800) << 15;
12186 inst
.instruction
|= (imm
& 0x0700) << 4;
12187 inst
.instruction
|= (imm
& 0x00ff);
12192 do_t_mvn_tst (void)
12196 Rn
= inst
.operands
[0].reg
;
12197 Rm
= inst
.operands
[1].reg
;
12199 if (inst
.instruction
== T_MNEM_cmp
12200 || inst
.instruction
== T_MNEM_cmn
)
12201 constraint (Rn
== REG_PC
, BAD_PC
);
12203 reject_bad_reg (Rn
);
12204 reject_bad_reg (Rm
);
12206 if (unified_syntax
)
12208 int r0off
= (inst
.instruction
== T_MNEM_mvn
12209 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12210 bfd_boolean narrow
;
12212 if (inst
.size_req
== 4
12213 || inst
.instruction
> 0xffff
12214 || inst
.operands
[1].shifted
12215 || Rn
> 7 || Rm
> 7)
12217 else if (inst
.instruction
== T_MNEM_cmn
12218 || inst
.instruction
== T_MNEM_tst
)
12220 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12221 narrow
= !in_it_block ();
12223 narrow
= in_it_block ();
12225 if (!inst
.operands
[1].isreg
)
12227 /* For an immediate, we always generate a 32-bit opcode;
12228 section relaxation will shrink it later if possible. */
12229 if (inst
.instruction
< 0xffff)
12230 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12231 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12232 inst
.instruction
|= Rn
<< r0off
;
12233 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12237 /* See if we can do this with a 16-bit instruction. */
12240 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12241 inst
.instruction
|= Rn
;
12242 inst
.instruction
|= Rm
<< 3;
12246 constraint (inst
.operands
[1].shifted
12247 && inst
.operands
[1].immisreg
,
12248 _("shift must be constant"));
12249 if (inst
.instruction
< 0xffff)
12250 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12251 inst
.instruction
|= Rn
<< r0off
;
12252 encode_thumb32_shifted_operand (1);
12258 constraint (inst
.instruction
> 0xffff
12259 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12260 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12261 _("unshifted register required"));
12262 constraint (Rn
> 7 || Rm
> 7,
12265 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12266 inst
.instruction
|= Rn
;
12267 inst
.instruction
|= Rm
<< 3;
12276 if (do_vfp_nsyn_mrs () == SUCCESS
)
12279 Rd
= inst
.operands
[0].reg
;
12280 reject_bad_reg (Rd
);
12281 inst
.instruction
|= Rd
<< 8;
12283 if (inst
.operands
[1].isreg
)
12285 unsigned br
= inst
.operands
[1].reg
;
12286 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12287 as_bad (_("bad register for mrs"));
12289 inst
.instruction
|= br
& (0xf << 16);
12290 inst
.instruction
|= (br
& 0x300) >> 4;
12291 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12295 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12297 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12299 /* PR gas/12698: The constraint is only applied for m_profile.
12300 If the user has specified -march=all, we want to ignore it as
12301 we are building for any CPU type, including non-m variants. */
12302 bfd_boolean m_profile
=
12303 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12304 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12305 "not support requested special purpose register"));
12308 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12310 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12311 _("'APSR', 'CPSR' or 'SPSR' expected"));
12313 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12314 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12315 inst
.instruction
|= 0xf0000;
12325 if (do_vfp_nsyn_msr () == SUCCESS
)
12328 constraint (!inst
.operands
[1].isreg
,
12329 _("Thumb encoding does not support an immediate here"));
12331 if (inst
.operands
[0].isreg
)
12332 flags
= (int)(inst
.operands
[0].reg
);
12334 flags
= inst
.operands
[0].imm
;
12336 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12338 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12340 /* PR gas/12698: The constraint is only applied for m_profile.
12341 If the user has specified -march=all, we want to ignore it as
12342 we are building for any CPU type, including non-m variants. */
12343 bfd_boolean m_profile
=
12344 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12345 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12346 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12347 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12348 && bits
!= PSR_f
)) && m_profile
,
12349 _("selected processor does not support requested special "
12350 "purpose register"));
12353 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12354 "requested special purpose register"));
12356 Rn
= inst
.operands
[1].reg
;
12357 reject_bad_reg (Rn
);
12359 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12360 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12361 inst
.instruction
|= (flags
& 0x300) >> 4;
12362 inst
.instruction
|= (flags
& 0xff);
12363 inst
.instruction
|= Rn
<< 16;
12369 bfd_boolean narrow
;
12370 unsigned Rd
, Rn
, Rm
;
12372 if (!inst
.operands
[2].present
)
12373 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12375 Rd
= inst
.operands
[0].reg
;
12376 Rn
= inst
.operands
[1].reg
;
12377 Rm
= inst
.operands
[2].reg
;
12379 if (unified_syntax
)
12381 if (inst
.size_req
== 4
12387 else if (inst
.instruction
== T_MNEM_muls
)
12388 narrow
= !in_it_block ();
12390 narrow
= in_it_block ();
12394 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12395 constraint (Rn
> 7 || Rm
> 7,
12402 /* 16-bit MULS/Conditional MUL. */
12403 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12404 inst
.instruction
|= Rd
;
12407 inst
.instruction
|= Rm
<< 3;
12409 inst
.instruction
|= Rn
<< 3;
12411 constraint (1, _("dest must overlap one source register"));
12415 constraint (inst
.instruction
!= T_MNEM_mul
,
12416 _("Thumb-2 MUL must not set flags"));
12418 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12419 inst
.instruction
|= Rd
<< 8;
12420 inst
.instruction
|= Rn
<< 16;
12421 inst
.instruction
|= Rm
<< 0;
12423 reject_bad_reg (Rd
);
12424 reject_bad_reg (Rn
);
12425 reject_bad_reg (Rm
);
12432 unsigned RdLo
, RdHi
, Rn
, Rm
;
12434 RdLo
= inst
.operands
[0].reg
;
12435 RdHi
= inst
.operands
[1].reg
;
12436 Rn
= inst
.operands
[2].reg
;
12437 Rm
= inst
.operands
[3].reg
;
12439 reject_bad_reg (RdLo
);
12440 reject_bad_reg (RdHi
);
12441 reject_bad_reg (Rn
);
12442 reject_bad_reg (Rm
);
12444 inst
.instruction
|= RdLo
<< 12;
12445 inst
.instruction
|= RdHi
<< 8;
12446 inst
.instruction
|= Rn
<< 16;
12447 inst
.instruction
|= Rm
;
12450 as_tsktsk (_("rdhi and rdlo must be different"));
12456 set_it_insn_type (NEUTRAL_IT_INSN
);
12458 if (unified_syntax
)
12460 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12462 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12463 inst
.instruction
|= inst
.operands
[0].imm
;
12467 /* PR9722: Check for Thumb2 availability before
12468 generating a thumb2 nop instruction. */
12469 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12471 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12472 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12475 inst
.instruction
= 0x46c0;
12480 constraint (inst
.operands
[0].present
,
12481 _("Thumb does not support NOP with hints"));
12482 inst
.instruction
= 0x46c0;
12489 if (unified_syntax
)
12491 bfd_boolean narrow
;
12493 if (THUMB_SETS_FLAGS (inst
.instruction
))
12494 narrow
= !in_it_block ();
12496 narrow
= in_it_block ();
12497 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12499 if (inst
.size_req
== 4)
12504 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12505 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12506 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12510 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12511 inst
.instruction
|= inst
.operands
[0].reg
;
12512 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12517 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12519 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12521 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12522 inst
.instruction
|= inst
.operands
[0].reg
;
12523 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12532 Rd
= inst
.operands
[0].reg
;
12533 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12535 reject_bad_reg (Rd
);
12536 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12537 reject_bad_reg (Rn
);
12539 inst
.instruction
|= Rd
<< 8;
12540 inst
.instruction
|= Rn
<< 16;
12542 if (!inst
.operands
[2].isreg
)
12544 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12545 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12551 Rm
= inst
.operands
[2].reg
;
12552 reject_bad_reg (Rm
);
12554 constraint (inst
.operands
[2].shifted
12555 && inst
.operands
[2].immisreg
,
12556 _("shift must be constant"));
12557 encode_thumb32_shifted_operand (2);
12564 unsigned Rd
, Rn
, Rm
;
12566 Rd
= inst
.operands
[0].reg
;
12567 Rn
= inst
.operands
[1].reg
;
12568 Rm
= inst
.operands
[2].reg
;
12570 reject_bad_reg (Rd
);
12571 reject_bad_reg (Rn
);
12572 reject_bad_reg (Rm
);
12574 inst
.instruction
|= Rd
<< 8;
12575 inst
.instruction
|= Rn
<< 16;
12576 inst
.instruction
|= Rm
;
12577 if (inst
.operands
[3].present
)
12579 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12580 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12581 _("expression too complex"));
12582 inst
.instruction
|= (val
& 0x1c) << 10;
12583 inst
.instruction
|= (val
& 0x03) << 6;
12590 if (!inst
.operands
[3].present
)
12594 inst
.instruction
&= ~0x00000020;
12596 /* PR 10168. Swap the Rm and Rn registers. */
12597 Rtmp
= inst
.operands
[1].reg
;
12598 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12599 inst
.operands
[2].reg
= Rtmp
;
12607 if (inst
.operands
[0].immisreg
)
12608 reject_bad_reg (inst
.operands
[0].imm
);
12610 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12614 do_t_push_pop (void)
12618 constraint (inst
.operands
[0].writeback
,
12619 _("push/pop do not support {reglist}^"));
12620 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12621 _("expression too complex"));
12623 mask
= inst
.operands
[0].imm
;
12624 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12625 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12626 else if (inst
.size_req
!= 4
12627 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12628 ? REG_LR
: REG_PC
)))
12630 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12631 inst
.instruction
|= THUMB_PP_PC_LR
;
12632 inst
.instruction
|= mask
& 0xff;
12634 else if (unified_syntax
)
12636 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12637 encode_thumb2_ldmstm (13, mask
, TRUE
);
12641 inst
.error
= _("invalid register list to push/pop instruction");
12651 Rd
= inst
.operands
[0].reg
;
12652 Rm
= inst
.operands
[1].reg
;
12654 reject_bad_reg (Rd
);
12655 reject_bad_reg (Rm
);
12657 inst
.instruction
|= Rd
<< 8;
12658 inst
.instruction
|= Rm
<< 16;
12659 inst
.instruction
|= Rm
;
12667 Rd
= inst
.operands
[0].reg
;
12668 Rm
= inst
.operands
[1].reg
;
12670 reject_bad_reg (Rd
);
12671 reject_bad_reg (Rm
);
12673 if (Rd
<= 7 && Rm
<= 7
12674 && inst
.size_req
!= 4)
12676 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12677 inst
.instruction
|= Rd
;
12678 inst
.instruction
|= Rm
<< 3;
12680 else if (unified_syntax
)
12682 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12683 inst
.instruction
|= Rd
<< 8;
12684 inst
.instruction
|= Rm
<< 16;
12685 inst
.instruction
|= Rm
;
12688 inst
.error
= BAD_HIREG
;
12696 Rd
= inst
.operands
[0].reg
;
12697 Rm
= inst
.operands
[1].reg
;
12699 reject_bad_reg (Rd
);
12700 reject_bad_reg (Rm
);
12702 inst
.instruction
|= Rd
<< 8;
12703 inst
.instruction
|= Rm
;
12711 Rd
= inst
.operands
[0].reg
;
12712 Rs
= (inst
.operands
[1].present
12713 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12714 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12716 reject_bad_reg (Rd
);
12717 reject_bad_reg (Rs
);
12718 if (inst
.operands
[2].isreg
)
12719 reject_bad_reg (inst
.operands
[2].reg
);
12721 inst
.instruction
|= Rd
<< 8;
12722 inst
.instruction
|= Rs
<< 16;
12723 if (!inst
.operands
[2].isreg
)
12725 bfd_boolean narrow
;
12727 if ((inst
.instruction
& 0x00100000) != 0)
12728 narrow
= !in_it_block ();
12730 narrow
= in_it_block ();
12732 if (Rd
> 7 || Rs
> 7)
12735 if (inst
.size_req
== 4 || !unified_syntax
)
12738 if (inst
.reloc
.exp
.X_op
!= O_constant
12739 || inst
.reloc
.exp
.X_add_number
!= 0)
12742 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12743 relaxation, but it doesn't seem worth the hassle. */
12746 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12747 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12748 inst
.instruction
|= Rs
<< 3;
12749 inst
.instruction
|= Rd
;
12753 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12754 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12758 encode_thumb32_shifted_operand (2);
12764 if (warn_on_deprecated
12765 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12766 as_tsktsk (_("setend use is deprecated for ARMv8"));
12768 set_it_insn_type (OUTSIDE_IT_INSN
);
12769 if (inst
.operands
[0].imm
)
12770 inst
.instruction
|= 0x8;
12776 if (!inst
.operands
[1].present
)
12777 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12779 if (unified_syntax
)
12781 bfd_boolean narrow
;
12784 switch (inst
.instruction
)
12787 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12789 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12791 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12793 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12797 if (THUMB_SETS_FLAGS (inst
.instruction
))
12798 narrow
= !in_it_block ();
12800 narrow
= in_it_block ();
12801 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12803 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12805 if (inst
.operands
[2].isreg
12806 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12807 || inst
.operands
[2].reg
> 7))
12809 if (inst
.size_req
== 4)
12812 reject_bad_reg (inst
.operands
[0].reg
);
12813 reject_bad_reg (inst
.operands
[1].reg
);
12817 if (inst
.operands
[2].isreg
)
12819 reject_bad_reg (inst
.operands
[2].reg
);
12820 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12821 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12822 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12823 inst
.instruction
|= inst
.operands
[2].reg
;
12825 /* PR 12854: Error on extraneous shifts. */
12826 constraint (inst
.operands
[2].shifted
,
12827 _("extraneous shift as part of operand to shift insn"));
12831 inst
.operands
[1].shifted
= 1;
12832 inst
.operands
[1].shift_kind
= shift_kind
;
12833 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12834 ? T_MNEM_movs
: T_MNEM_mov
);
12835 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12836 encode_thumb32_shifted_operand (1);
12837 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12838 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12843 if (inst
.operands
[2].isreg
)
12845 switch (shift_kind
)
12847 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12848 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12849 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12850 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12854 inst
.instruction
|= inst
.operands
[0].reg
;
12855 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12857 /* PR 12854: Error on extraneous shifts. */
12858 constraint (inst
.operands
[2].shifted
,
12859 _("extraneous shift as part of operand to shift insn"));
12863 switch (shift_kind
)
12865 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12866 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12867 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12870 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12871 inst
.instruction
|= inst
.operands
[0].reg
;
12872 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12878 constraint (inst
.operands
[0].reg
> 7
12879 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12880 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12882 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12884 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12885 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12886 _("source1 and dest must be same register"));
12888 switch (inst
.instruction
)
12890 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12891 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12892 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12893 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12897 inst
.instruction
|= inst
.operands
[0].reg
;
12898 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12900 /* PR 12854: Error on extraneous shifts. */
12901 constraint (inst
.operands
[2].shifted
,
12902 _("extraneous shift as part of operand to shift insn"));
12906 switch (inst
.instruction
)
12908 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12909 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12910 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12911 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12914 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12915 inst
.instruction
|= inst
.operands
[0].reg
;
12916 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12924 unsigned Rd
, Rn
, Rm
;
12926 Rd
= inst
.operands
[0].reg
;
12927 Rn
= inst
.operands
[1].reg
;
12928 Rm
= inst
.operands
[2].reg
;
12930 reject_bad_reg (Rd
);
12931 reject_bad_reg (Rn
);
12932 reject_bad_reg (Rm
);
12934 inst
.instruction
|= Rd
<< 8;
12935 inst
.instruction
|= Rn
<< 16;
12936 inst
.instruction
|= Rm
;
12942 unsigned Rd
, Rn
, Rm
;
12944 Rd
= inst
.operands
[0].reg
;
12945 Rm
= inst
.operands
[1].reg
;
12946 Rn
= inst
.operands
[2].reg
;
12948 reject_bad_reg (Rd
);
12949 reject_bad_reg (Rn
);
12950 reject_bad_reg (Rm
);
12952 inst
.instruction
|= Rd
<< 8;
12953 inst
.instruction
|= Rn
<< 16;
12954 inst
.instruction
|= Rm
;
12960 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12961 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12962 _("SMC is not permitted on this architecture"));
12963 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12964 _("expression too complex"));
12965 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12966 inst
.instruction
|= (value
& 0xf000) >> 12;
12967 inst
.instruction
|= (value
& 0x0ff0);
12968 inst
.instruction
|= (value
& 0x000f) << 16;
12969 /* PR gas/15623: SMC instructions must be last in an IT block. */
12970 set_it_insn_type_last ();
12976 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12978 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12979 inst
.instruction
|= (value
& 0x0fff);
12980 inst
.instruction
|= (value
& 0xf000) << 4;
12984 do_t_ssat_usat (int bias
)
12988 Rd
= inst
.operands
[0].reg
;
12989 Rn
= inst
.operands
[2].reg
;
12991 reject_bad_reg (Rd
);
12992 reject_bad_reg (Rn
);
12994 inst
.instruction
|= Rd
<< 8;
12995 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12996 inst
.instruction
|= Rn
<< 16;
12998 if (inst
.operands
[3].present
)
13000 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
13002 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13004 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13005 _("expression too complex"));
13007 if (shift_amount
!= 0)
13009 constraint (shift_amount
> 31,
13010 _("shift expression is too large"));
13012 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13013 inst
.instruction
|= 0x00200000; /* sh bit. */
13015 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13016 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13024 do_t_ssat_usat (1);
13032 Rd
= inst
.operands
[0].reg
;
13033 Rn
= inst
.operands
[2].reg
;
13035 reject_bad_reg (Rd
);
13036 reject_bad_reg (Rn
);
13038 inst
.instruction
|= Rd
<< 8;
13039 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13040 inst
.instruction
|= Rn
<< 16;
13046 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13047 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13048 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13049 || inst
.operands
[2].negative
,
13052 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13054 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13055 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13056 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13057 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13063 if (!inst
.operands
[2].present
)
13064 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13066 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13067 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13068 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13071 inst
.instruction
|= inst
.operands
[0].reg
;
13072 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13073 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13074 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13080 unsigned Rd
, Rn
, Rm
;
13082 Rd
= inst
.operands
[0].reg
;
13083 Rn
= inst
.operands
[1].reg
;
13084 Rm
= inst
.operands
[2].reg
;
13086 reject_bad_reg (Rd
);
13087 reject_bad_reg (Rn
);
13088 reject_bad_reg (Rm
);
13090 inst
.instruction
|= Rd
<< 8;
13091 inst
.instruction
|= Rn
<< 16;
13092 inst
.instruction
|= Rm
;
13093 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13101 Rd
= inst
.operands
[0].reg
;
13102 Rm
= inst
.operands
[1].reg
;
13104 reject_bad_reg (Rd
);
13105 reject_bad_reg (Rm
);
13107 if (inst
.instruction
<= 0xffff
13108 && inst
.size_req
!= 4
13109 && Rd
<= 7 && Rm
<= 7
13110 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13112 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13113 inst
.instruction
|= Rd
;
13114 inst
.instruction
|= Rm
<< 3;
13116 else if (unified_syntax
)
13118 if (inst
.instruction
<= 0xffff)
13119 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13120 inst
.instruction
|= Rd
<< 8;
13121 inst
.instruction
|= Rm
;
13122 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13126 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13127 _("Thumb encoding does not support rotation"));
13128 constraint (1, BAD_HIREG
);
13135 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13144 half
= (inst
.instruction
& 0x10) != 0;
13145 set_it_insn_type_last ();
13146 constraint (inst
.operands
[0].immisreg
,
13147 _("instruction requires register index"));
13149 Rn
= inst
.operands
[0].reg
;
13150 Rm
= inst
.operands
[0].imm
;
13152 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13153 constraint (Rn
== REG_SP
, BAD_SP
);
13154 reject_bad_reg (Rm
);
13156 constraint (!half
&& inst
.operands
[0].shifted
,
13157 _("instruction does not allow shifted index"));
13158 inst
.instruction
|= (Rn
<< 16) | Rm
;
13164 if (!inst
.operands
[0].present
)
13165 inst
.operands
[0].imm
= 0;
13167 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13169 constraint (inst
.size_req
== 2,
13170 _("immediate value out of range"));
13171 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13172 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13173 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13177 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13178 inst
.instruction
|= inst
.operands
[0].imm
;
13181 set_it_insn_type (NEUTRAL_IT_INSN
);
13188 do_t_ssat_usat (0);
13196 Rd
= inst
.operands
[0].reg
;
13197 Rn
= inst
.operands
[2].reg
;
13199 reject_bad_reg (Rd
);
13200 reject_bad_reg (Rn
);
13202 inst
.instruction
|= Rd
<< 8;
13203 inst
.instruction
|= inst
.operands
[1].imm
;
13204 inst
.instruction
|= Rn
<< 16;
13207 /* Neon instruction encoder helpers. */
13209 /* Encodings for the different types for various Neon opcodes. */
13211 /* An "invalid" code for the following tables. */
13214 struct neon_tab_entry
13217 unsigned float_or_poly
;
13218 unsigned scalar_or_imm
;
13221 /* Map overloaded Neon opcodes to their respective encodings. */
13222 #define NEON_ENC_TAB \
13223 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13224 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13225 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13226 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13227 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13228 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13229 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13230 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13231 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13232 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13233 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13234 /* Register variants of the following two instructions are encoded as
13235 vcge / vcgt with the operands reversed. */ \
13236 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13237 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13238 X(vfma, N_INV, 0x0000c10, N_INV), \
13239 X(vfms, N_INV, 0x0200c10, N_INV), \
13240 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13241 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13242 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13243 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13244 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13245 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13246 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13247 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13248 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13249 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13250 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13251 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13252 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13253 X(vshl, 0x0000400, N_INV, 0x0800510), \
13254 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13255 X(vand, 0x0000110, N_INV, 0x0800030), \
13256 X(vbic, 0x0100110, N_INV, 0x0800030), \
13257 X(veor, 0x1000110, N_INV, N_INV), \
13258 X(vorn, 0x0300110, N_INV, 0x0800010), \
13259 X(vorr, 0x0200110, N_INV, 0x0800010), \
13260 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13261 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13262 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13263 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13264 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13265 X(vst1, 0x0000000, 0x0800000, N_INV), \
13266 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13267 X(vst2, 0x0000100, 0x0800100, N_INV), \
13268 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13269 X(vst3, 0x0000200, 0x0800200, N_INV), \
13270 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13271 X(vst4, 0x0000300, 0x0800300, N_INV), \
13272 X(vmovn, 0x1b20200, N_INV, N_INV), \
13273 X(vtrn, 0x1b20080, N_INV, N_INV), \
13274 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13275 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13276 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13277 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13278 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13279 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13280 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13281 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13282 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13283 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13284 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13285 X(vseleq, 0xe000a00, N_INV, N_INV), \
13286 X(vselvs, 0xe100a00, N_INV, N_INV), \
13287 X(vselge, 0xe200a00, N_INV, N_INV), \
13288 X(vselgt, 0xe300a00, N_INV, N_INV), \
13289 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13290 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13291 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13292 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13293 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13294 X(aes, 0x3b00300, N_INV, N_INV), \
13295 X(sha3op, 0x2000c00, N_INV, N_INV), \
13296 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13297 X(sha2op, 0x3ba0380, N_INV, N_INV)
13301 #define X(OPC,I,F,S) N_MNEM_##OPC
13306 static const struct neon_tab_entry neon_enc_tab
[] =
13308 #define X(OPC,I,F,S) { (I), (F), (S) }
13313 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13314 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13315 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13316 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13317 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13318 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13319 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13320 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13321 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13322 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13323 #define NEON_ENC_SINGLE_(X) \
13324 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13325 #define NEON_ENC_DOUBLE_(X) \
13326 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13327 #define NEON_ENC_FPV8_(X) \
13328 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13330 #define NEON_ENCODE(type, inst) \
13333 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13334 inst.is_neon = 1; \
13338 #define check_neon_suffixes \
13341 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13343 as_bad (_("invalid neon suffix for non neon instruction")); \
13349 /* Define shapes for instruction operands. The following mnemonic characters
13350 are used in this table:
13352 F - VFP S<n> register
13353 D - Neon D<n> register
13354 Q - Neon Q<n> register
13358 L - D<n> register list
13360 This table is used to generate various data:
13361 - enumerations of the form NS_DDR to be used as arguments to
13363 - a table classifying shapes into single, double, quad, mixed.
13364 - a table used to drive neon_select_shape. */
13366 #define NEON_SHAPE_DEF \
13367 X(3, (D, D, D), DOUBLE), \
13368 X(3, (Q, Q, Q), QUAD), \
13369 X(3, (D, D, I), DOUBLE), \
13370 X(3, (Q, Q, I), QUAD), \
13371 X(3, (D, D, S), DOUBLE), \
13372 X(3, (Q, Q, S), QUAD), \
13373 X(2, (D, D), DOUBLE), \
13374 X(2, (Q, Q), QUAD), \
13375 X(2, (D, S), DOUBLE), \
13376 X(2, (Q, S), QUAD), \
13377 X(2, (D, R), DOUBLE), \
13378 X(2, (Q, R), QUAD), \
13379 X(2, (D, I), DOUBLE), \
13380 X(2, (Q, I), QUAD), \
13381 X(3, (D, L, D), DOUBLE), \
13382 X(2, (D, Q), MIXED), \
13383 X(2, (Q, D), MIXED), \
13384 X(3, (D, Q, I), MIXED), \
13385 X(3, (Q, D, I), MIXED), \
13386 X(3, (Q, D, D), MIXED), \
13387 X(3, (D, Q, Q), MIXED), \
13388 X(3, (Q, Q, D), MIXED), \
13389 X(3, (Q, D, S), MIXED), \
13390 X(3, (D, Q, S), MIXED), \
13391 X(4, (D, D, D, I), DOUBLE), \
13392 X(4, (Q, Q, Q, I), QUAD), \
13393 X(4, (D, D, S, I), DOUBLE), \
13394 X(4, (Q, Q, S, I), QUAD), \
13395 X(2, (F, F), SINGLE), \
13396 X(3, (F, F, F), SINGLE), \
13397 X(2, (F, I), SINGLE), \
13398 X(2, (F, D), MIXED), \
13399 X(2, (D, F), MIXED), \
13400 X(3, (F, F, I), MIXED), \
13401 X(4, (R, R, F, F), SINGLE), \
13402 X(4, (F, F, R, R), SINGLE), \
13403 X(3, (D, R, R), DOUBLE), \
13404 X(3, (R, R, D), DOUBLE), \
13405 X(2, (S, R), SINGLE), \
13406 X(2, (R, S), SINGLE), \
13407 X(2, (F, R), SINGLE), \
13408 X(2, (R, F), SINGLE), \
13409 /* Half float shape supported so far. */\
13410 X (2, (H, D), MIXED), \
13411 X (2, (D, H), MIXED), \
13412 X (2, (H, F), MIXED), \
13413 X (2, (F, H), MIXED), \
13414 X (2, (H, H), HALF), \
13415 X (2, (H, R), HALF), \
13416 X (2, (R, H), HALF), \
13417 X (2, (H, I), HALF), \
13418 X (3, (H, H, H), HALF), \
13419 X (3, (H, F, I), MIXED), \
13420 X (3, (F, H, I), MIXED)
13422 #define S2(A,B) NS_##A##B
13423 #define S3(A,B,C) NS_##A##B##C
13424 #define S4(A,B,C,D) NS_##A##B##C##D
13426 #define X(N, L, C) S##N L
13439 enum neon_shape_class
13448 #define X(N, L, C) SC_##C
13450 static enum neon_shape_class neon_shape_class
[] =
13469 /* Register widths of above. */
13470 static unsigned neon_shape_el_size
[] =
13482 struct neon_shape_info
13485 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13488 #define S2(A,B) { SE_##A, SE_##B }
13489 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13490 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13492 #define X(N, L, C) { N, S##N L }
13494 static struct neon_shape_info neon_shape_tab
[] =
13504 /* Bit masks used in type checking given instructions.
13505 'N_EQK' means the type must be the same as (or based on in some way) the key
13506 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13507 set, various other bits can be set as well in order to modify the meaning of
13508 the type constraint. */
13510 enum neon_type_mask
13534 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13535 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13536 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13537 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13538 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13539 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13540 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13541 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13542 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13543 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13544 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13546 N_MAX_NONSPECIAL
= N_P64
13549 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13551 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13552 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13553 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13554 #define N_S_32 (N_S8 | N_S16 | N_S32)
13555 #define N_F_16_32 (N_F16 | N_F32)
13556 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13557 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13558 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13559 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13561 /* Pass this as the first type argument to neon_check_type to ignore types
13563 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13565 /* Select a "shape" for the current instruction (describing register types or
13566 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13567 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13568 function of operand parsing, so this function doesn't need to be called.
13569 Shapes should be listed in order of decreasing length. */
13571 static enum neon_shape
13572 neon_select_shape (enum neon_shape shape
, ...)
13575 enum neon_shape first_shape
= shape
;
13577 /* Fix missing optional operands. FIXME: we don't know at this point how
13578 many arguments we should have, so this makes the assumption that we have
13579 > 1. This is true of all current Neon opcodes, I think, but may not be
13580 true in the future. */
13581 if (!inst
.operands
[1].present
)
13582 inst
.operands
[1] = inst
.operands
[0];
13584 va_start (ap
, shape
);
13586 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13591 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13593 if (!inst
.operands
[j
].present
)
13599 switch (neon_shape_tab
[shape
].el
[j
])
13601 /* If a .f16, .16, .u16, .s16 type specifier is given over
13602 a VFP single precision register operand, it's essentially
13603 means only half of the register is used.
13605 If the type specifier is given after the mnemonics, the
13606 information is stored in inst.vectype. If the type specifier
13607 is given after register operand, the information is stored
13608 in inst.operands[].vectype.
13610 When there is only one type specifier, and all the register
13611 operands are the same type of hardware register, the type
13612 specifier applies to all register operands.
13614 If no type specifier is given, the shape is inferred from
13615 operand information.
13618 vadd.f16 s0, s1, s2: NS_HHH
13619 vabs.f16 s0, s1: NS_HH
13620 vmov.f16 s0, r1: NS_HR
13621 vmov.f16 r0, s1: NS_RH
13622 vcvt.f16 r0, s1: NS_RH
13623 vcvt.f16.s32 s2, s2, #29: NS_HFI
13624 vcvt.f16.s32 s2, s2: NS_HF
13627 if (!(inst
.operands
[j
].isreg
13628 && inst
.operands
[j
].isvec
13629 && inst
.operands
[j
].issingle
13630 && !inst
.operands
[j
].isquad
13631 && ((inst
.vectype
.elems
== 1
13632 && inst
.vectype
.el
[0].size
== 16)
13633 || (inst
.vectype
.elems
> 1
13634 && inst
.vectype
.el
[j
].size
== 16)
13635 || (inst
.vectype
.elems
== 0
13636 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13637 && inst
.operands
[j
].vectype
.size
== 16))))
13642 if (!(inst
.operands
[j
].isreg
13643 && inst
.operands
[j
].isvec
13644 && inst
.operands
[j
].issingle
13645 && !inst
.operands
[j
].isquad
13646 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13647 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13648 || (inst
.vectype
.elems
== 0
13649 && (inst
.operands
[j
].vectype
.size
== 32
13650 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13655 if (!(inst
.operands
[j
].isreg
13656 && inst
.operands
[j
].isvec
13657 && !inst
.operands
[j
].isquad
13658 && !inst
.operands
[j
].issingle
))
13663 if (!(inst
.operands
[j
].isreg
13664 && !inst
.operands
[j
].isvec
))
13669 if (!(inst
.operands
[j
].isreg
13670 && inst
.operands
[j
].isvec
13671 && inst
.operands
[j
].isquad
13672 && !inst
.operands
[j
].issingle
))
13677 if (!(!inst
.operands
[j
].isreg
13678 && !inst
.operands
[j
].isscalar
))
13683 if (!(!inst
.operands
[j
].isreg
13684 && inst
.operands
[j
].isscalar
))
13694 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13695 /* We've matched all the entries in the shape table, and we don't
13696 have any left over operands which have not been matched. */
13702 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13703 first_error (_("invalid instruction shape"));
13708 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13709 means the Q bit should be set). */
13712 neon_quad (enum neon_shape shape
)
13714 return neon_shape_class
[shape
] == SC_QUAD
;
13718 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13721 /* Allow modification to be made to types which are constrained to be
13722 based on the key element, based on bits set alongside N_EQK. */
13723 if ((typebits
& N_EQK
) != 0)
13725 if ((typebits
& N_HLF
) != 0)
13727 else if ((typebits
& N_DBL
) != 0)
13729 if ((typebits
& N_SGN
) != 0)
13730 *g_type
= NT_signed
;
13731 else if ((typebits
& N_UNS
) != 0)
13732 *g_type
= NT_unsigned
;
13733 else if ((typebits
& N_INT
) != 0)
13734 *g_type
= NT_integer
;
13735 else if ((typebits
& N_FLT
) != 0)
13736 *g_type
= NT_float
;
13737 else if ((typebits
& N_SIZ
) != 0)
13738 *g_type
= NT_untyped
;
13742 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13743 operand type, i.e. the single type specified in a Neon instruction when it
13744 is the only one given. */
13746 static struct neon_type_el
13747 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13749 struct neon_type_el dest
= *key
;
13751 gas_assert ((thisarg
& N_EQK
) != 0);
13753 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13758 /* Convert Neon type and size into compact bitmask representation. */
13760 static enum neon_type_mask
13761 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13768 case 8: return N_8
;
13769 case 16: return N_16
;
13770 case 32: return N_32
;
13771 case 64: return N_64
;
13779 case 8: return N_I8
;
13780 case 16: return N_I16
;
13781 case 32: return N_I32
;
13782 case 64: return N_I64
;
13790 case 16: return N_F16
;
13791 case 32: return N_F32
;
13792 case 64: return N_F64
;
13800 case 8: return N_P8
;
13801 case 16: return N_P16
;
13802 case 64: return N_P64
;
13810 case 8: return N_S8
;
13811 case 16: return N_S16
;
13812 case 32: return N_S32
;
13813 case 64: return N_S64
;
13821 case 8: return N_U8
;
13822 case 16: return N_U16
;
13823 case 32: return N_U32
;
13824 case 64: return N_U64
;
13835 /* Convert compact Neon bitmask type representation to a type and size. Only
13836 handles the case where a single bit is set in the mask. */
13839 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13840 enum neon_type_mask mask
)
13842 if ((mask
& N_EQK
) != 0)
13845 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13847 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13849 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13851 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13856 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13858 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13859 *type
= NT_unsigned
;
13860 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13861 *type
= NT_integer
;
13862 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13863 *type
= NT_untyped
;
13864 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13866 else if ((mask
& (N_F_ALL
)) != 0)
13874 /* Modify a bitmask of allowed types. This is only needed for type
13878 modify_types_allowed (unsigned allowed
, unsigned mods
)
13881 enum neon_el_type type
;
13887 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13889 if (el_type_of_type_chk (&type
, &size
,
13890 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13892 neon_modify_type_size (mods
, &type
, &size
);
13893 destmask
|= type_chk_of_el_type (type
, size
);
13900 /* Check type and return type classification.
13901 The manual states (paraphrase): If one datatype is given, it indicates the
13903 - the second operand, if there is one
13904 - the operand, if there is no second operand
13905 - the result, if there are no operands.
13906 This isn't quite good enough though, so we use a concept of a "key" datatype
13907 which is set on a per-instruction basis, which is the one which matters when
13908 only one data type is written.
13909 Note: this function has side-effects (e.g. filling in missing operands). All
13910 Neon instructions should call it before performing bit encoding. */
13912 static struct neon_type_el
13913 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13916 unsigned i
, pass
, key_el
= 0;
13917 unsigned types
[NEON_MAX_TYPE_ELS
];
13918 enum neon_el_type k_type
= NT_invtype
;
13919 unsigned k_size
= -1u;
13920 struct neon_type_el badtype
= {NT_invtype
, -1};
13921 unsigned key_allowed
= 0;
13923 /* Optional registers in Neon instructions are always (not) in operand 1.
13924 Fill in the missing operand here, if it was omitted. */
13925 if (els
> 1 && !inst
.operands
[1].present
)
13926 inst
.operands
[1] = inst
.operands
[0];
13928 /* Suck up all the varargs. */
13930 for (i
= 0; i
< els
; i
++)
13932 unsigned thisarg
= va_arg (ap
, unsigned);
13933 if (thisarg
== N_IGNORE_TYPE
)
13938 types
[i
] = thisarg
;
13939 if ((thisarg
& N_KEY
) != 0)
13944 if (inst
.vectype
.elems
> 0)
13945 for (i
= 0; i
< els
; i
++)
13946 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13948 first_error (_("types specified in both the mnemonic and operands"));
13952 /* Duplicate inst.vectype elements here as necessary.
13953 FIXME: No idea if this is exactly the same as the ARM assembler,
13954 particularly when an insn takes one register and one non-register
13956 if (inst
.vectype
.elems
== 1 && els
> 1)
13959 inst
.vectype
.elems
= els
;
13960 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13961 for (j
= 0; j
< els
; j
++)
13963 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13966 else if (inst
.vectype
.elems
== 0 && els
> 0)
13969 /* No types were given after the mnemonic, so look for types specified
13970 after each operand. We allow some flexibility here; as long as the
13971 "key" operand has a type, we can infer the others. */
13972 for (j
= 0; j
< els
; j
++)
13973 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13974 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13976 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13978 for (j
= 0; j
< els
; j
++)
13979 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13980 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13985 first_error (_("operand types can't be inferred"));
13989 else if (inst
.vectype
.elems
!= els
)
13991 first_error (_("type specifier has the wrong number of parts"));
13995 for (pass
= 0; pass
< 2; pass
++)
13997 for (i
= 0; i
< els
; i
++)
13999 unsigned thisarg
= types
[i
];
14000 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14001 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14002 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14003 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14005 /* Decay more-specific signed & unsigned types to sign-insensitive
14006 integer types if sign-specific variants are unavailable. */
14007 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14008 && (types_allowed
& N_SU_ALL
) == 0)
14009 g_type
= NT_integer
;
14011 /* If only untyped args are allowed, decay any more specific types to
14012 them. Some instructions only care about signs for some element
14013 sizes, so handle that properly. */
14014 if (((types_allowed
& N_UNT
) == 0)
14015 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14016 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14017 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14018 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14019 g_type
= NT_untyped
;
14023 if ((thisarg
& N_KEY
) != 0)
14027 key_allowed
= thisarg
& ~N_KEY
;
14029 /* Check architecture constraint on FP16 extension. */
14031 && k_type
== NT_float
14032 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14034 inst
.error
= _(BAD_FP16
);
14041 if ((thisarg
& N_VFP
) != 0)
14043 enum neon_shape_el regshape
;
14044 unsigned regwidth
, match
;
14046 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14049 first_error (_("invalid instruction shape"));
14052 regshape
= neon_shape_tab
[ns
].el
[i
];
14053 regwidth
= neon_shape_el_size
[regshape
];
14055 /* In VFP mode, operands must match register widths. If we
14056 have a key operand, use its width, else use the width of
14057 the current operand. */
14063 /* FP16 will use a single precision register. */
14064 if (regwidth
== 32 && match
== 16)
14066 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14070 inst
.error
= _(BAD_FP16
);
14075 if (regwidth
!= match
)
14077 first_error (_("operand size must match register width"));
14082 if ((thisarg
& N_EQK
) == 0)
14084 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14086 if ((given_type
& types_allowed
) == 0)
14088 first_error (_("bad type in Neon instruction"));
14094 enum neon_el_type mod_k_type
= k_type
;
14095 unsigned mod_k_size
= k_size
;
14096 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14097 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14099 first_error (_("inconsistent types in Neon instruction"));
14107 return inst
.vectype
.el
[key_el
];
14110 /* Neon-style VFP instruction forwarding. */
14112 /* Thumb VFP instructions have 0xE in the condition field. */
14115 do_vfp_cond_or_thumb (void)
14120 inst
.instruction
|= 0xe0000000;
14122 inst
.instruction
|= inst
.cond
<< 28;
14125 /* Look up and encode a simple mnemonic, for use as a helper function for the
14126 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14127 etc. It is assumed that operand parsing has already been done, and that the
14128 operands are in the form expected by the given opcode (this isn't necessarily
14129 the same as the form in which they were parsed, hence some massaging must
14130 take place before this function is called).
14131 Checks current arch version against that in the looked-up opcode. */
14134 do_vfp_nsyn_opcode (const char *opname
)
14136 const struct asm_opcode
*opcode
;
14138 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14143 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14144 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14151 inst
.instruction
= opcode
->tvalue
;
14152 opcode
->tencode ();
14156 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14157 opcode
->aencode ();
14162 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14164 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14166 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14169 do_vfp_nsyn_opcode ("fadds");
14171 do_vfp_nsyn_opcode ("fsubs");
14173 /* ARMv8.2 fp16 instruction. */
14175 do_scalar_fp16_v82_encode ();
14180 do_vfp_nsyn_opcode ("faddd");
14182 do_vfp_nsyn_opcode ("fsubd");
14186 /* Check operand types to see if this is a VFP instruction, and if so call
14190 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14192 enum neon_shape rs
;
14193 struct neon_type_el et
;
14198 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14199 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14203 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14204 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14205 N_F_ALL
| N_KEY
| N_VFP
);
14212 if (et
.type
!= NT_invtype
)
14223 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14225 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14227 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14230 do_vfp_nsyn_opcode ("fmacs");
14232 do_vfp_nsyn_opcode ("fnmacs");
14234 /* ARMv8.2 fp16 instruction. */
14236 do_scalar_fp16_v82_encode ();
14241 do_vfp_nsyn_opcode ("fmacd");
14243 do_vfp_nsyn_opcode ("fnmacd");
14248 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14250 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14252 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14255 do_vfp_nsyn_opcode ("ffmas");
14257 do_vfp_nsyn_opcode ("ffnmas");
14259 /* ARMv8.2 fp16 instruction. */
14261 do_scalar_fp16_v82_encode ();
14266 do_vfp_nsyn_opcode ("ffmad");
14268 do_vfp_nsyn_opcode ("ffnmad");
14273 do_vfp_nsyn_mul (enum neon_shape rs
)
14275 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14277 do_vfp_nsyn_opcode ("fmuls");
14279 /* ARMv8.2 fp16 instruction. */
14281 do_scalar_fp16_v82_encode ();
14284 do_vfp_nsyn_opcode ("fmuld");
14288 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14290 int is_neg
= (inst
.instruction
& 0x80) != 0;
14291 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14293 if (rs
== NS_FF
|| rs
== NS_HH
)
14296 do_vfp_nsyn_opcode ("fnegs");
14298 do_vfp_nsyn_opcode ("fabss");
14300 /* ARMv8.2 fp16 instruction. */
14302 do_scalar_fp16_v82_encode ();
14307 do_vfp_nsyn_opcode ("fnegd");
14309 do_vfp_nsyn_opcode ("fabsd");
14313 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14314 insns belong to Neon, and are handled elsewhere. */
14317 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14319 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14323 do_vfp_nsyn_opcode ("fldmdbs");
14325 do_vfp_nsyn_opcode ("fldmias");
14330 do_vfp_nsyn_opcode ("fstmdbs");
14332 do_vfp_nsyn_opcode ("fstmias");
14337 do_vfp_nsyn_sqrt (void)
14339 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14340 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14342 if (rs
== NS_FF
|| rs
== NS_HH
)
14344 do_vfp_nsyn_opcode ("fsqrts");
14346 /* ARMv8.2 fp16 instruction. */
14348 do_scalar_fp16_v82_encode ();
14351 do_vfp_nsyn_opcode ("fsqrtd");
14355 do_vfp_nsyn_div (void)
14357 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14358 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14359 N_F_ALL
| N_KEY
| N_VFP
);
14361 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14363 do_vfp_nsyn_opcode ("fdivs");
14365 /* ARMv8.2 fp16 instruction. */
14367 do_scalar_fp16_v82_encode ();
14370 do_vfp_nsyn_opcode ("fdivd");
14374 do_vfp_nsyn_nmul (void)
14376 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14377 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14378 N_F_ALL
| N_KEY
| N_VFP
);
14380 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14382 NEON_ENCODE (SINGLE
, inst
);
14383 do_vfp_sp_dyadic ();
14385 /* ARMv8.2 fp16 instruction. */
14387 do_scalar_fp16_v82_encode ();
14391 NEON_ENCODE (DOUBLE
, inst
);
14392 do_vfp_dp_rd_rn_rm ();
14394 do_vfp_cond_or_thumb ();
14399 do_vfp_nsyn_cmp (void)
14401 enum neon_shape rs
;
14402 if (inst
.operands
[1].isreg
)
14404 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14405 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14407 if (rs
== NS_FF
|| rs
== NS_HH
)
14409 NEON_ENCODE (SINGLE
, inst
);
14410 do_vfp_sp_monadic ();
14414 NEON_ENCODE (DOUBLE
, inst
);
14415 do_vfp_dp_rd_rm ();
14420 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14421 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14423 switch (inst
.instruction
& 0x0fffffff)
14426 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14429 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14435 if (rs
== NS_FI
|| rs
== NS_HI
)
14437 NEON_ENCODE (SINGLE
, inst
);
14438 do_vfp_sp_compare_z ();
14442 NEON_ENCODE (DOUBLE
, inst
);
14446 do_vfp_cond_or_thumb ();
14448 /* ARMv8.2 fp16 instruction. */
14449 if (rs
== NS_HI
|| rs
== NS_HH
)
14450 do_scalar_fp16_v82_encode ();
14454 nsyn_insert_sp (void)
14456 inst
.operands
[1] = inst
.operands
[0];
14457 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14458 inst
.operands
[0].reg
= REG_SP
;
14459 inst
.operands
[0].isreg
= 1;
14460 inst
.operands
[0].writeback
= 1;
14461 inst
.operands
[0].present
= 1;
14465 do_vfp_nsyn_push (void)
14469 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14470 _("register list must contain at least 1 and at most 16 "
14473 if (inst
.operands
[1].issingle
)
14474 do_vfp_nsyn_opcode ("fstmdbs");
14476 do_vfp_nsyn_opcode ("fstmdbd");
14480 do_vfp_nsyn_pop (void)
14484 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14485 _("register list must contain at least 1 and at most 16 "
14488 if (inst
.operands
[1].issingle
)
14489 do_vfp_nsyn_opcode ("fldmias");
14491 do_vfp_nsyn_opcode ("fldmiad");
14494 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14495 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14498 neon_dp_fixup (struct arm_it
* insn
)
14500 unsigned int i
= insn
->instruction
;
14505 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14516 insn
->instruction
= i
;
14519 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14523 neon_logbits (unsigned x
)
14525 return ffs (x
) - 4;
14528 #define LOW4(R) ((R) & 0xf)
14529 #define HI1(R) (((R) >> 4) & 1)
14531 /* Encode insns with bit pattern:
14533 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14534 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14536 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14537 different meaning for some instruction. */
14540 neon_three_same (int isquad
, int ubit
, int size
)
14542 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14543 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14544 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14545 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14546 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14547 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14548 inst
.instruction
|= (isquad
!= 0) << 6;
14549 inst
.instruction
|= (ubit
!= 0) << 24;
14551 inst
.instruction
|= neon_logbits (size
) << 20;
14553 neon_dp_fixup (&inst
);
14556 /* Encode instructions of the form:
14558 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14559 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14561 Don't write size if SIZE == -1. */
14564 neon_two_same (int qbit
, int ubit
, int size
)
14566 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14567 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14568 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14569 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14570 inst
.instruction
|= (qbit
!= 0) << 6;
14571 inst
.instruction
|= (ubit
!= 0) << 24;
14574 inst
.instruction
|= neon_logbits (size
) << 18;
14576 neon_dp_fixup (&inst
);
14579 /* Neon instruction encoders, in approximate order of appearance. */
14582 do_neon_dyadic_i_su (void)
14584 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14585 struct neon_type_el et
= neon_check_type (3, rs
,
14586 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14587 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14591 do_neon_dyadic_i64_su (void)
14593 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14594 struct neon_type_el et
= neon_check_type (3, rs
,
14595 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14596 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14600 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14603 unsigned size
= et
.size
>> 3;
14604 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14605 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14606 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14607 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14608 inst
.instruction
|= (isquad
!= 0) << 6;
14609 inst
.instruction
|= immbits
<< 16;
14610 inst
.instruction
|= (size
>> 3) << 7;
14611 inst
.instruction
|= (size
& 0x7) << 19;
14613 inst
.instruction
|= (uval
!= 0) << 24;
14615 neon_dp_fixup (&inst
);
14619 do_neon_shl_imm (void)
14621 if (!inst
.operands
[2].isreg
)
14623 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14624 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14625 int imm
= inst
.operands
[2].imm
;
14627 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14628 _("immediate out of range for shift"));
14629 NEON_ENCODE (IMMED
, inst
);
14630 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14634 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14635 struct neon_type_el et
= neon_check_type (3, rs
,
14636 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14639 /* VSHL/VQSHL 3-register variants have syntax such as:
14641 whereas other 3-register operations encoded by neon_three_same have
14644 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14646 tmp
= inst
.operands
[2].reg
;
14647 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14648 inst
.operands
[1].reg
= tmp
;
14649 NEON_ENCODE (INTEGER
, inst
);
14650 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14655 do_neon_qshl_imm (void)
14657 if (!inst
.operands
[2].isreg
)
14659 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14660 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14661 int imm
= inst
.operands
[2].imm
;
14663 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14664 _("immediate out of range for shift"));
14665 NEON_ENCODE (IMMED
, inst
);
14666 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14670 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14671 struct neon_type_el et
= neon_check_type (3, rs
,
14672 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14675 /* See note in do_neon_shl_imm. */
14676 tmp
= inst
.operands
[2].reg
;
14677 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14678 inst
.operands
[1].reg
= tmp
;
14679 NEON_ENCODE (INTEGER
, inst
);
14680 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14685 do_neon_rshl (void)
14687 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14688 struct neon_type_el et
= neon_check_type (3, rs
,
14689 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14692 tmp
= inst
.operands
[2].reg
;
14693 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14694 inst
.operands
[1].reg
= tmp
;
14695 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14699 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14701 /* Handle .I8 pseudo-instructions. */
14704 /* Unfortunately, this will make everything apart from zero out-of-range.
14705 FIXME is this the intended semantics? There doesn't seem much point in
14706 accepting .I8 if so. */
14707 immediate
|= immediate
<< 8;
14713 if (immediate
== (immediate
& 0x000000ff))
14715 *immbits
= immediate
;
14718 else if (immediate
== (immediate
& 0x0000ff00))
14720 *immbits
= immediate
>> 8;
14723 else if (immediate
== (immediate
& 0x00ff0000))
14725 *immbits
= immediate
>> 16;
14728 else if (immediate
== (immediate
& 0xff000000))
14730 *immbits
= immediate
>> 24;
14733 if ((immediate
& 0xffff) != (immediate
>> 16))
14734 goto bad_immediate
;
14735 immediate
&= 0xffff;
14738 if (immediate
== (immediate
& 0x000000ff))
14740 *immbits
= immediate
;
14743 else if (immediate
== (immediate
& 0x0000ff00))
14745 *immbits
= immediate
>> 8;
14750 first_error (_("immediate value out of range"));
14755 do_neon_logic (void)
14757 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14759 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14760 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14761 /* U bit and size field were set as part of the bitmask. */
14762 NEON_ENCODE (INTEGER
, inst
);
14763 neon_three_same (neon_quad (rs
), 0, -1);
14767 const int three_ops_form
= (inst
.operands
[2].present
14768 && !inst
.operands
[2].isreg
);
14769 const int immoperand
= (three_ops_form
? 2 : 1);
14770 enum neon_shape rs
= (three_ops_form
14771 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14772 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14773 struct neon_type_el et
= neon_check_type (2, rs
,
14774 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14775 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14779 if (et
.type
== NT_invtype
)
14782 if (three_ops_form
)
14783 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14784 _("first and second operands shall be the same register"));
14786 NEON_ENCODE (IMMED
, inst
);
14788 immbits
= inst
.operands
[immoperand
].imm
;
14791 /* .i64 is a pseudo-op, so the immediate must be a repeating
14793 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14794 inst
.operands
[immoperand
].reg
: 0))
14796 /* Set immbits to an invalid constant. */
14797 immbits
= 0xdeadbeef;
14804 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14808 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14812 /* Pseudo-instruction for VBIC. */
14813 neon_invert_size (&immbits
, 0, et
.size
);
14814 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14818 /* Pseudo-instruction for VORR. */
14819 neon_invert_size (&immbits
, 0, et
.size
);
14820 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14830 inst
.instruction
|= neon_quad (rs
) << 6;
14831 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14832 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14833 inst
.instruction
|= cmode
<< 8;
14834 neon_write_immbits (immbits
);
14836 neon_dp_fixup (&inst
);
14841 do_neon_bitfield (void)
14843 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14844 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14845 neon_three_same (neon_quad (rs
), 0, -1);
14849 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14852 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14853 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14855 if (et
.type
== NT_float
)
14857 NEON_ENCODE (FLOAT
, inst
);
14858 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14862 NEON_ENCODE (INTEGER
, inst
);
14863 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14868 do_neon_dyadic_if_su (void)
14870 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14874 do_neon_dyadic_if_su_d (void)
14876 /* This version only allow D registers, but that constraint is enforced during
14877 operand parsing so we don't need to do anything extra here. */
14878 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14882 do_neon_dyadic_if_i_d (void)
14884 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14885 affected if we specify unsigned args. */
14886 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14889 enum vfp_or_neon_is_neon_bits
14892 NEON_CHECK_ARCH
= 2,
14893 NEON_CHECK_ARCH8
= 4
14896 /* Call this function if an instruction which may have belonged to the VFP or
14897 Neon instruction sets, but turned out to be a Neon instruction (due to the
14898 operand types involved, etc.). We have to check and/or fix-up a couple of
14901 - Make sure the user hasn't attempted to make a Neon instruction
14903 - Alter the value in the condition code field if necessary.
14904 - Make sure that the arch supports Neon instructions.
14906 Which of these operations take place depends on bits from enum
14907 vfp_or_neon_is_neon_bits.
14909 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14910 current instruction's condition is COND_ALWAYS, the condition field is
14911 changed to inst.uncond_value. This is necessary because instructions shared
14912 between VFP and Neon may be conditional for the VFP variants only, and the
14913 unconditional Neon version must have, e.g., 0xF in the condition field. */
14916 vfp_or_neon_is_neon (unsigned check
)
14918 /* Conditions are always legal in Thumb mode (IT blocks). */
14919 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14921 if (inst
.cond
!= COND_ALWAYS
)
14923 first_error (_(BAD_COND
));
14926 if (inst
.uncond_value
!= -1)
14927 inst
.instruction
|= inst
.uncond_value
<< 28;
14930 if ((check
& NEON_CHECK_ARCH
)
14931 && !mark_feature_used (&fpu_neon_ext_v1
))
14933 first_error (_(BAD_FPU
));
14937 if ((check
& NEON_CHECK_ARCH8
)
14938 && !mark_feature_used (&fpu_neon_ext_armv8
))
14940 first_error (_(BAD_FPU
));
14948 do_neon_addsub_if_i (void)
14950 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14953 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14956 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14957 affected if we specify unsigned args. */
14958 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14961 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14963 V<op> A,B (A is operand 0, B is operand 2)
14968 so handle that case specially. */
14971 neon_exchange_operands (void)
14973 if (inst
.operands
[1].present
)
14975 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14977 /* Swap operands[1] and operands[2]. */
14978 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14979 inst
.operands
[1] = inst
.operands
[2];
14980 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14985 inst
.operands
[1] = inst
.operands
[2];
14986 inst
.operands
[2] = inst
.operands
[0];
14991 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14993 if (inst
.operands
[2].isreg
)
14996 neon_exchange_operands ();
14997 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15001 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15002 struct neon_type_el et
= neon_check_type (2, rs
,
15003 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15005 NEON_ENCODE (IMMED
, inst
);
15006 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15007 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15008 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15009 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15010 inst
.instruction
|= neon_quad (rs
) << 6;
15011 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15012 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15014 neon_dp_fixup (&inst
);
15021 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15025 do_neon_cmp_inv (void)
15027 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15033 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15036 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15037 scalars, which are encoded in 5 bits, M : Rm.
15038 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15039 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15042 Dot Product instructions are similar to multiply instructions except elsize
15043 should always be 32.
15045 This function translates SCALAR, which is GAS's internal encoding of indexed
15046 scalar register, to raw encoding. There is also register and index range
15047 check based on ELSIZE. */
15050 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15052 unsigned regno
= NEON_SCALAR_REG (scalar
);
15053 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15058 if (regno
> 7 || elno
> 3)
15060 return regno
| (elno
<< 3);
15063 if (regno
> 15 || elno
> 1)
15065 return regno
| (elno
<< 4);
15069 first_error (_("scalar out of range for multiply instruction"));
15075 /* Encode multiply / multiply-accumulate scalar instructions. */
15078 neon_mul_mac (struct neon_type_el et
, int ubit
)
15082 /* Give a more helpful error message if we have an invalid type. */
15083 if (et
.type
== NT_invtype
)
15086 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15087 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15088 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15089 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15090 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15091 inst
.instruction
|= LOW4 (scalar
);
15092 inst
.instruction
|= HI1 (scalar
) << 5;
15093 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15094 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15095 inst
.instruction
|= (ubit
!= 0) << 24;
15097 neon_dp_fixup (&inst
);
15101 do_neon_mac_maybe_scalar (void)
15103 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15106 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15109 if (inst
.operands
[2].isscalar
)
15111 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15112 struct neon_type_el et
= neon_check_type (3, rs
,
15113 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15114 NEON_ENCODE (SCALAR
, inst
);
15115 neon_mul_mac (et
, neon_quad (rs
));
15119 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15120 affected if we specify unsigned args. */
15121 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15126 do_neon_fmac (void)
15128 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15131 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15134 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15140 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15141 struct neon_type_el et
= neon_check_type (3, rs
,
15142 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15143 neon_three_same (neon_quad (rs
), 0, et
.size
);
15146 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15147 same types as the MAC equivalents. The polynomial type for this instruction
15148 is encoded the same as the integer type. */
15153 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15156 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15159 if (inst
.operands
[2].isscalar
)
15160 do_neon_mac_maybe_scalar ();
15162 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15166 do_neon_qdmulh (void)
15168 if (inst
.operands
[2].isscalar
)
15170 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15171 struct neon_type_el et
= neon_check_type (3, rs
,
15172 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15173 NEON_ENCODE (SCALAR
, inst
);
15174 neon_mul_mac (et
, neon_quad (rs
));
15178 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15179 struct neon_type_el et
= neon_check_type (3, rs
,
15180 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15181 NEON_ENCODE (INTEGER
, inst
);
15182 /* The U bit (rounding) comes from bit mask. */
15183 neon_three_same (neon_quad (rs
), 0, et
.size
);
15188 do_neon_qrdmlah (void)
15190 /* Check we're on the correct architecture. */
15191 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15193 _("instruction form not available on this architecture.");
15194 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15196 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15197 record_feature_use (&fpu_neon_ext_v8_1
);
15200 if (inst
.operands
[2].isscalar
)
15202 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15203 struct neon_type_el et
= neon_check_type (3, rs
,
15204 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15205 NEON_ENCODE (SCALAR
, inst
);
15206 neon_mul_mac (et
, neon_quad (rs
));
15210 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15211 struct neon_type_el et
= neon_check_type (3, rs
,
15212 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15213 NEON_ENCODE (INTEGER
, inst
);
15214 /* The U bit (rounding) comes from bit mask. */
15215 neon_three_same (neon_quad (rs
), 0, et
.size
);
15220 do_neon_fcmp_absolute (void)
15222 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15223 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15224 N_F_16_32
| N_KEY
);
15225 /* Size field comes from bit mask. */
15226 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15230 do_neon_fcmp_absolute_inv (void)
15232 neon_exchange_operands ();
15233 do_neon_fcmp_absolute ();
15237 do_neon_step (void)
15239 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15240 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15241 N_F_16_32
| N_KEY
);
15242 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15246 do_neon_abs_neg (void)
15248 enum neon_shape rs
;
15249 struct neon_type_el et
;
15251 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15254 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15257 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15258 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15260 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15261 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15262 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15263 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15264 inst
.instruction
|= neon_quad (rs
) << 6;
15265 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15266 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15268 neon_dp_fixup (&inst
);
15274 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15275 struct neon_type_el et
= neon_check_type (2, rs
,
15276 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15277 int imm
= inst
.operands
[2].imm
;
15278 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15279 _("immediate out of range for insert"));
15280 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15286 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15287 struct neon_type_el et
= neon_check_type (2, rs
,
15288 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15289 int imm
= inst
.operands
[2].imm
;
15290 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15291 _("immediate out of range for insert"));
15292 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15296 do_neon_qshlu_imm (void)
15298 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15299 struct neon_type_el et
= neon_check_type (2, rs
,
15300 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15301 int imm
= inst
.operands
[2].imm
;
15302 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15303 _("immediate out of range for shift"));
15304 /* Only encodes the 'U present' variant of the instruction.
15305 In this case, signed types have OP (bit 8) set to 0.
15306 Unsigned types have OP set to 1. */
15307 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15308 /* The rest of the bits are the same as other immediate shifts. */
15309 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15313 do_neon_qmovn (void)
15315 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15316 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15317 /* Saturating move where operands can be signed or unsigned, and the
15318 destination has the same signedness. */
15319 NEON_ENCODE (INTEGER
, inst
);
15320 if (et
.type
== NT_unsigned
)
15321 inst
.instruction
|= 0xc0;
15323 inst
.instruction
|= 0x80;
15324 neon_two_same (0, 1, et
.size
/ 2);
15328 do_neon_qmovun (void)
15330 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15331 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15332 /* Saturating move with unsigned results. Operands must be signed. */
15333 NEON_ENCODE (INTEGER
, inst
);
15334 neon_two_same (0, 1, et
.size
/ 2);
15338 do_neon_rshift_sat_narrow (void)
15340 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15341 or unsigned. If operands are unsigned, results must also be unsigned. */
15342 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15343 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15344 int imm
= inst
.operands
[2].imm
;
15345 /* This gets the bounds check, size encoding and immediate bits calculation
15349 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15350 VQMOVN.I<size> <Dd>, <Qm>. */
15353 inst
.operands
[2].present
= 0;
15354 inst
.instruction
= N_MNEM_vqmovn
;
15359 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15360 _("immediate out of range"));
15361 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15365 do_neon_rshift_sat_narrow_u (void)
15367 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15368 or unsigned. If operands are unsigned, results must also be unsigned. */
15369 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15370 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15371 int imm
= inst
.operands
[2].imm
;
15372 /* This gets the bounds check, size encoding and immediate bits calculation
15376 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15377 VQMOVUN.I<size> <Dd>, <Qm>. */
15380 inst
.operands
[2].present
= 0;
15381 inst
.instruction
= N_MNEM_vqmovun
;
15386 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15387 _("immediate out of range"));
15388 /* FIXME: The manual is kind of unclear about what value U should have in
15389 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15391 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15395 do_neon_movn (void)
15397 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15398 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15399 NEON_ENCODE (INTEGER
, inst
);
15400 neon_two_same (0, 1, et
.size
/ 2);
15404 do_neon_rshift_narrow (void)
15406 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15407 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15408 int imm
= inst
.operands
[2].imm
;
15409 /* This gets the bounds check, size encoding and immediate bits calculation
15413 /* If immediate is zero then we are a pseudo-instruction for
15414 VMOVN.I<size> <Dd>, <Qm> */
15417 inst
.operands
[2].present
= 0;
15418 inst
.instruction
= N_MNEM_vmovn
;
15423 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15424 _("immediate out of range for narrowing operation"));
15425 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15429 do_neon_shll (void)
15431 /* FIXME: Type checking when lengthening. */
15432 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15433 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15434 unsigned imm
= inst
.operands
[2].imm
;
15436 if (imm
== et
.size
)
15438 /* Maximum shift variant. */
15439 NEON_ENCODE (INTEGER
, inst
);
15440 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15441 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15442 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15443 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15444 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15446 neon_dp_fixup (&inst
);
15450 /* A more-specific type check for non-max versions. */
15451 et
= neon_check_type (2, NS_QDI
,
15452 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15453 NEON_ENCODE (IMMED
, inst
);
15454 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15458 /* Check the various types for the VCVT instruction, and return which version
15459 the current instruction is. */
15461 #define CVT_FLAVOUR_VAR \
15462 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15463 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15464 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15465 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15466 /* Half-precision conversions. */ \
15467 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15468 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15469 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15470 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15471 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15472 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15473 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15474 Compared with single/double precision variants, only the co-processor \
15475 field is different, so the encoding flow is reused here. */ \
15476 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15477 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15478 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15479 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15480 /* VFP instructions. */ \
15481 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15482 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15483 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15484 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15485 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15486 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15487 /* VFP instructions with bitshift. */ \
15488 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15489 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15490 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15491 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15492 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15493 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15494 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15495 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15497 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15498 neon_cvt_flavour_##C,
15500 /* The different types of conversions we can do. */
15501 enum neon_cvt_flavour
15504 neon_cvt_flavour_invalid
,
15505 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15510 static enum neon_cvt_flavour
15511 get_neon_cvt_flavour (enum neon_shape rs
)
15513 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15514 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15515 if (et.type != NT_invtype) \
15517 inst.error = NULL; \
15518 return (neon_cvt_flavour_##C); \
15521 struct neon_type_el et
;
15522 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15523 || rs
== NS_FF
) ? N_VFP
: 0;
15524 /* The instruction versions which take an immediate take one register
15525 argument, which is extended to the width of the full register. Thus the
15526 "source" and "destination" registers must have the same width. Hack that
15527 here by making the size equal to the key (wider, in this case) operand. */
15528 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15532 return neon_cvt_flavour_invalid
;
15547 /* Neon-syntax VFP conversions. */
15550 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15552 const char *opname
= 0;
15554 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15555 || rs
== NS_FHI
|| rs
== NS_HFI
)
15557 /* Conversions with immediate bitshift. */
15558 const char *enc
[] =
15560 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15566 if (flavour
< (int) ARRAY_SIZE (enc
))
15568 opname
= enc
[flavour
];
15569 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15570 _("operands 0 and 1 must be the same register"));
15571 inst
.operands
[1] = inst
.operands
[2];
15572 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15577 /* Conversions without bitshift. */
15578 const char *enc
[] =
15580 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15586 if (flavour
< (int) ARRAY_SIZE (enc
))
15587 opname
= enc
[flavour
];
15591 do_vfp_nsyn_opcode (opname
);
15593 /* ARMv8.2 fp16 VCVT instruction. */
15594 if (flavour
== neon_cvt_flavour_s32_f16
15595 || flavour
== neon_cvt_flavour_u32_f16
15596 || flavour
== neon_cvt_flavour_f16_u32
15597 || flavour
== neon_cvt_flavour_f16_s32
)
15598 do_scalar_fp16_v82_encode ();
15602 do_vfp_nsyn_cvtz (void)
15604 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15605 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15606 const char *enc
[] =
15608 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15614 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15615 do_vfp_nsyn_opcode (enc
[flavour
]);
15619 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15620 enum neon_cvt_mode mode
)
15625 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15626 D register operands. */
15627 if (flavour
== neon_cvt_flavour_s32_f64
15628 || flavour
== neon_cvt_flavour_u32_f64
)
15629 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15632 if (flavour
== neon_cvt_flavour_s32_f16
15633 || flavour
== neon_cvt_flavour_u32_f16
)
15634 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15637 set_it_insn_type (OUTSIDE_IT_INSN
);
15641 case neon_cvt_flavour_s32_f64
:
15645 case neon_cvt_flavour_s32_f32
:
15649 case neon_cvt_flavour_s32_f16
:
15653 case neon_cvt_flavour_u32_f64
:
15657 case neon_cvt_flavour_u32_f32
:
15661 case neon_cvt_flavour_u32_f16
:
15666 first_error (_("invalid instruction shape"));
15672 case neon_cvt_mode_a
: rm
= 0; break;
15673 case neon_cvt_mode_n
: rm
= 1; break;
15674 case neon_cvt_mode_p
: rm
= 2; break;
15675 case neon_cvt_mode_m
: rm
= 3; break;
15676 default: first_error (_("invalid rounding mode")); return;
15679 NEON_ENCODE (FPV8
, inst
);
15680 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15681 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15682 inst
.instruction
|= sz
<< 8;
15684 /* ARMv8.2 fp16 VCVT instruction. */
15685 if (flavour
== neon_cvt_flavour_s32_f16
15686 ||flavour
== neon_cvt_flavour_u32_f16
)
15687 do_scalar_fp16_v82_encode ();
15688 inst
.instruction
|= op
<< 7;
15689 inst
.instruction
|= rm
<< 16;
15690 inst
.instruction
|= 0xf0000000;
15691 inst
.is_neon
= TRUE
;
15695 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15697 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15698 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15699 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15701 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15703 if (flavour
== neon_cvt_flavour_invalid
)
15706 /* PR11109: Handle round-to-zero for VCVT conversions. */
15707 if (mode
== neon_cvt_mode_z
15708 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15709 && (flavour
== neon_cvt_flavour_s16_f16
15710 || flavour
== neon_cvt_flavour_u16_f16
15711 || flavour
== neon_cvt_flavour_s32_f32
15712 || flavour
== neon_cvt_flavour_u32_f32
15713 || flavour
== neon_cvt_flavour_s32_f64
15714 || flavour
== neon_cvt_flavour_u32_f64
)
15715 && (rs
== NS_FD
|| rs
== NS_FF
))
15717 do_vfp_nsyn_cvtz ();
15721 /* ARMv8.2 fp16 VCVT conversions. */
15722 if (mode
== neon_cvt_mode_z
15723 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15724 && (flavour
== neon_cvt_flavour_s32_f16
15725 || flavour
== neon_cvt_flavour_u32_f16
)
15728 do_vfp_nsyn_cvtz ();
15729 do_scalar_fp16_v82_encode ();
15733 /* VFP rather than Neon conversions. */
15734 if (flavour
>= neon_cvt_flavour_first_fp
)
15736 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15737 do_vfp_nsyn_cvt (rs
, flavour
);
15739 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15750 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15751 0x0000100, 0x1000100, 0x0, 0x1000000};
15753 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15756 /* Fixed-point conversion with #0 immediate is encoded as an
15757 integer conversion. */
15758 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15760 NEON_ENCODE (IMMED
, inst
);
15761 if (flavour
!= neon_cvt_flavour_invalid
)
15762 inst
.instruction
|= enctab
[flavour
];
15763 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15764 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15765 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15766 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15767 inst
.instruction
|= neon_quad (rs
) << 6;
15768 inst
.instruction
|= 1 << 21;
15769 if (flavour
< neon_cvt_flavour_s16_f16
)
15771 inst
.instruction
|= 1 << 21;
15772 immbits
= 32 - inst
.operands
[2].imm
;
15773 inst
.instruction
|= immbits
<< 16;
15777 inst
.instruction
|= 3 << 20;
15778 immbits
= 16 - inst
.operands
[2].imm
;
15779 inst
.instruction
|= immbits
<< 16;
15780 inst
.instruction
&= ~(1 << 9);
15783 neon_dp_fixup (&inst
);
15789 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15791 NEON_ENCODE (FLOAT
, inst
);
15792 set_it_insn_type (OUTSIDE_IT_INSN
);
15794 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15797 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15798 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15799 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15800 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15801 inst
.instruction
|= neon_quad (rs
) << 6;
15802 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15803 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15804 inst
.instruction
|= mode
<< 8;
15805 if (flavour
== neon_cvt_flavour_u16_f16
15806 || flavour
== neon_cvt_flavour_s16_f16
)
15807 /* Mask off the original size bits and reencode them. */
15808 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15811 inst
.instruction
|= 0xfc000000;
15813 inst
.instruction
|= 0xf0000000;
15819 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15820 0x100, 0x180, 0x0, 0x080};
15822 NEON_ENCODE (INTEGER
, inst
);
15824 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15827 if (flavour
!= neon_cvt_flavour_invalid
)
15828 inst
.instruction
|= enctab
[flavour
];
15830 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15831 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15832 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15833 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15834 inst
.instruction
|= neon_quad (rs
) << 6;
15835 if (flavour
>= neon_cvt_flavour_s16_f16
15836 && flavour
<= neon_cvt_flavour_f16_u16
)
15837 /* Half precision. */
15838 inst
.instruction
|= 1 << 18;
15840 inst
.instruction
|= 2 << 18;
15842 neon_dp_fixup (&inst
);
15847 /* Half-precision conversions for Advanced SIMD -- neon. */
15852 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15854 as_bad (_("operand size must match register width"));
15859 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15861 as_bad (_("operand size must match register width"));
15866 inst
.instruction
= 0x3b60600;
15868 inst
.instruction
= 0x3b60700;
15870 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15871 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15872 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15873 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15874 neon_dp_fixup (&inst
);
15878 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15879 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15880 do_vfp_nsyn_cvt (rs
, flavour
);
15882 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15887 do_neon_cvtr (void)
15889 do_neon_cvt_1 (neon_cvt_mode_x
);
15895 do_neon_cvt_1 (neon_cvt_mode_z
);
15899 do_neon_cvta (void)
15901 do_neon_cvt_1 (neon_cvt_mode_a
);
15905 do_neon_cvtn (void)
15907 do_neon_cvt_1 (neon_cvt_mode_n
);
15911 do_neon_cvtp (void)
15913 do_neon_cvt_1 (neon_cvt_mode_p
);
15917 do_neon_cvtm (void)
15919 do_neon_cvt_1 (neon_cvt_mode_m
);
15923 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15926 mark_feature_used (&fpu_vfp_ext_armv8
);
15928 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15929 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15930 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15931 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15932 inst
.instruction
|= to
? 0x10000 : 0;
15933 inst
.instruction
|= t
? 0x80 : 0;
15934 inst
.instruction
|= is_double
? 0x100 : 0;
15935 do_vfp_cond_or_thumb ();
15939 do_neon_cvttb_1 (bfd_boolean t
)
15941 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15942 NS_DF
, NS_DH
, NS_NULL
);
15946 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15949 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15951 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15954 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15956 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15958 /* The VCVTB and VCVTT instructions with D-register operands
15959 don't work for SP only targets. */
15960 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15964 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15966 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15968 /* The VCVTB and VCVTT instructions with D-register operands
15969 don't work for SP only targets. */
15970 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15974 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15981 do_neon_cvtb (void)
15983 do_neon_cvttb_1 (FALSE
);
15988 do_neon_cvtt (void)
15990 do_neon_cvttb_1 (TRUE
);
15994 neon_move_immediate (void)
15996 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15997 struct neon_type_el et
= neon_check_type (2, rs
,
15998 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15999 unsigned immlo
, immhi
= 0, immbits
;
16000 int op
, cmode
, float_p
;
16002 constraint (et
.type
== NT_invtype
,
16003 _("operand size must be specified for immediate VMOV"));
16005 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16006 op
= (inst
.instruction
& (1 << 5)) != 0;
16008 immlo
= inst
.operands
[1].imm
;
16009 if (inst
.operands
[1].regisimm
)
16010 immhi
= inst
.operands
[1].reg
;
16012 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16013 _("immediate has bits set outside the operand size"));
16015 float_p
= inst
.operands
[1].immisfloat
;
16017 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16018 et
.size
, et
.type
)) == FAIL
)
16020 /* Invert relevant bits only. */
16021 neon_invert_size (&immlo
, &immhi
, et
.size
);
16022 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16023 with one or the other; those cases are caught by
16024 neon_cmode_for_move_imm. */
16026 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16027 &op
, et
.size
, et
.type
)) == FAIL
)
16029 first_error (_("immediate out of range"));
16034 inst
.instruction
&= ~(1 << 5);
16035 inst
.instruction
|= op
<< 5;
16037 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16038 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16039 inst
.instruction
|= neon_quad (rs
) << 6;
16040 inst
.instruction
|= cmode
<< 8;
16042 neon_write_immbits (immbits
);
16048 if (inst
.operands
[1].isreg
)
16050 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16052 NEON_ENCODE (INTEGER
, inst
);
16053 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16054 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16055 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16056 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16057 inst
.instruction
|= neon_quad (rs
) << 6;
16061 NEON_ENCODE (IMMED
, inst
);
16062 neon_move_immediate ();
16065 neon_dp_fixup (&inst
);
16068 /* Encode instructions of form:
16070 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16071 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16074 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16076 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16077 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16078 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16079 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16080 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16081 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16082 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16083 inst
.instruction
|= neon_logbits (size
) << 20;
16085 neon_dp_fixup (&inst
);
16089 do_neon_dyadic_long (void)
16091 /* FIXME: Type checking for lengthening op. */
16092 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16093 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16094 neon_mixed_length (et
, et
.size
);
16098 do_neon_abal (void)
16100 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16101 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16102 neon_mixed_length (et
, et
.size
);
16106 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16108 if (inst
.operands
[2].isscalar
)
16110 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16111 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16112 NEON_ENCODE (SCALAR
, inst
);
16113 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16117 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16118 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16119 NEON_ENCODE (INTEGER
, inst
);
16120 neon_mixed_length (et
, et
.size
);
16125 do_neon_mac_maybe_scalar_long (void)
16127 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16131 do_neon_dyadic_wide (void)
16133 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16134 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16135 neon_mixed_length (et
, et
.size
);
16139 do_neon_dyadic_narrow (void)
16141 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16142 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16143 /* Operand sign is unimportant, and the U bit is part of the opcode,
16144 so force the operand type to integer. */
16145 et
.type
= NT_integer
;
16146 neon_mixed_length (et
, et
.size
/ 2);
16150 do_neon_mul_sat_scalar_long (void)
16152 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16156 do_neon_vmull (void)
16158 if (inst
.operands
[2].isscalar
)
16159 do_neon_mac_maybe_scalar_long ();
16162 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16163 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16165 if (et
.type
== NT_poly
)
16166 NEON_ENCODE (POLY
, inst
);
16168 NEON_ENCODE (INTEGER
, inst
);
16170 /* For polynomial encoding the U bit must be zero, and the size must
16171 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16172 obviously, as 0b10). */
16175 /* Check we're on the correct architecture. */
16176 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16178 _("Instruction form not available on this architecture.");
16183 neon_mixed_length (et
, et
.size
);
16190 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16191 struct neon_type_el et
= neon_check_type (3, rs
,
16192 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16193 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16195 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16196 _("shift out of range"));
16197 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16198 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16199 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16200 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16201 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16202 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16203 inst
.instruction
|= neon_quad (rs
) << 6;
16204 inst
.instruction
|= imm
<< 8;
16206 neon_dp_fixup (&inst
);
16212 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16213 struct neon_type_el et
= neon_check_type (2, rs
,
16214 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16215 unsigned op
= (inst
.instruction
>> 7) & 3;
16216 /* N (width of reversed regions) is encoded as part of the bitmask. We
16217 extract it here to check the elements to be reversed are smaller.
16218 Otherwise we'd get a reserved instruction. */
16219 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16220 gas_assert (elsize
!= 0);
16221 constraint (et
.size
>= elsize
,
16222 _("elements must be smaller than reversal region"));
16223 neon_two_same (neon_quad (rs
), 1, et
.size
);
16229 if (inst
.operands
[1].isscalar
)
16231 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16232 struct neon_type_el et
= neon_check_type (2, rs
,
16233 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16234 unsigned sizebits
= et
.size
>> 3;
16235 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16236 int logsize
= neon_logbits (et
.size
);
16237 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16239 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16242 NEON_ENCODE (SCALAR
, inst
);
16243 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16244 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16245 inst
.instruction
|= LOW4 (dm
);
16246 inst
.instruction
|= HI1 (dm
) << 5;
16247 inst
.instruction
|= neon_quad (rs
) << 6;
16248 inst
.instruction
|= x
<< 17;
16249 inst
.instruction
|= sizebits
<< 16;
16251 neon_dp_fixup (&inst
);
16255 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16256 struct neon_type_el et
= neon_check_type (2, rs
,
16257 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16258 /* Duplicate ARM register to lanes of vector. */
16259 NEON_ENCODE (ARMREG
, inst
);
16262 case 8: inst
.instruction
|= 0x400000; break;
16263 case 16: inst
.instruction
|= 0x000020; break;
16264 case 32: inst
.instruction
|= 0x000000; break;
16267 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16268 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16269 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16270 inst
.instruction
|= neon_quad (rs
) << 21;
16271 /* The encoding for this instruction is identical for the ARM and Thumb
16272 variants, except for the condition field. */
16273 do_vfp_cond_or_thumb ();
16277 /* VMOV has particularly many variations. It can be one of:
16278 0. VMOV<c><q> <Qd>, <Qm>
16279 1. VMOV<c><q> <Dd>, <Dm>
16280 (Register operations, which are VORR with Rm = Rn.)
16281 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16282 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16284 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16285 (ARM register to scalar.)
16286 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16287 (Two ARM registers to vector.)
16288 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16289 (Scalar to ARM register.)
16290 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16291 (Vector to two ARM registers.)
16292 8. VMOV.F32 <Sd>, <Sm>
16293 9. VMOV.F64 <Dd>, <Dm>
16294 (VFP register moves.)
16295 10. VMOV.F32 <Sd>, #imm
16296 11. VMOV.F64 <Dd>, #imm
16297 (VFP float immediate load.)
16298 12. VMOV <Rd>, <Sm>
16299 (VFP single to ARM reg.)
16300 13. VMOV <Sd>, <Rm>
16301 (ARM reg to VFP single.)
16302 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16303 (Two ARM regs to two VFP singles.)
16304 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16305 (Two VFP singles to two ARM regs.)
16307 These cases can be disambiguated using neon_select_shape, except cases 1/9
16308 and 3/11 which depend on the operand type too.
16310 All the encoded bits are hardcoded by this function.
16312 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16313 Cases 5, 7 may be used with VFPv2 and above.
16315 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16316 can specify a type where it doesn't make sense to, and is ignored). */
16321 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16322 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16323 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16324 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16325 struct neon_type_el et
;
16326 const char *ldconst
= 0;
16330 case NS_DD
: /* case 1/9. */
16331 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16332 /* It is not an error here if no type is given. */
16334 if (et
.type
== NT_float
&& et
.size
== 64)
16336 do_vfp_nsyn_opcode ("fcpyd");
16339 /* fall through. */
16341 case NS_QQ
: /* case 0/1. */
16343 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16345 /* The architecture manual I have doesn't explicitly state which
16346 value the U bit should have for register->register moves, but
16347 the equivalent VORR instruction has U = 0, so do that. */
16348 inst
.instruction
= 0x0200110;
16349 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16350 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16351 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16352 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16353 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16354 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16355 inst
.instruction
|= neon_quad (rs
) << 6;
16357 neon_dp_fixup (&inst
);
16361 case NS_DI
: /* case 3/11. */
16362 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16364 if (et
.type
== NT_float
&& et
.size
== 64)
16366 /* case 11 (fconstd). */
16367 ldconst
= "fconstd";
16368 goto encode_fconstd
;
16370 /* fall through. */
16372 case NS_QI
: /* case 2/3. */
16373 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16375 inst
.instruction
= 0x0800010;
16376 neon_move_immediate ();
16377 neon_dp_fixup (&inst
);
16380 case NS_SR
: /* case 4. */
16382 unsigned bcdebits
= 0;
16384 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16385 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16387 /* .<size> is optional here, defaulting to .32. */
16388 if (inst
.vectype
.elems
== 0
16389 && inst
.operands
[0].vectype
.type
== NT_invtype
16390 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16392 inst
.vectype
.el
[0].type
= NT_untyped
;
16393 inst
.vectype
.el
[0].size
= 32;
16394 inst
.vectype
.elems
= 1;
16397 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16398 logsize
= neon_logbits (et
.size
);
16400 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16402 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16403 && et
.size
!= 32, _(BAD_FPU
));
16404 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16405 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16409 case 8: bcdebits
= 0x8; break;
16410 case 16: bcdebits
= 0x1; break;
16411 case 32: bcdebits
= 0x0; break;
16415 bcdebits
|= x
<< logsize
;
16417 inst
.instruction
= 0xe000b10;
16418 do_vfp_cond_or_thumb ();
16419 inst
.instruction
|= LOW4 (dn
) << 16;
16420 inst
.instruction
|= HI1 (dn
) << 7;
16421 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16422 inst
.instruction
|= (bcdebits
& 3) << 5;
16423 inst
.instruction
|= (bcdebits
>> 2) << 21;
16427 case NS_DRR
: /* case 5 (fmdrr). */
16428 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16431 inst
.instruction
= 0xc400b10;
16432 do_vfp_cond_or_thumb ();
16433 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16434 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16435 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16436 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16439 case NS_RS
: /* case 6. */
16442 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16443 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16444 unsigned abcdebits
= 0;
16446 /* .<dt> is optional here, defaulting to .32. */
16447 if (inst
.vectype
.elems
== 0
16448 && inst
.operands
[0].vectype
.type
== NT_invtype
16449 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16451 inst
.vectype
.el
[0].type
= NT_untyped
;
16452 inst
.vectype
.el
[0].size
= 32;
16453 inst
.vectype
.elems
= 1;
16456 et
= neon_check_type (2, NS_NULL
,
16457 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16458 logsize
= neon_logbits (et
.size
);
16460 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16462 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16463 && et
.size
!= 32, _(BAD_FPU
));
16464 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16465 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16469 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16470 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16471 case 32: abcdebits
= 0x00; break;
16475 abcdebits
|= x
<< logsize
;
16476 inst
.instruction
= 0xe100b10;
16477 do_vfp_cond_or_thumb ();
16478 inst
.instruction
|= LOW4 (dn
) << 16;
16479 inst
.instruction
|= HI1 (dn
) << 7;
16480 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16481 inst
.instruction
|= (abcdebits
& 3) << 5;
16482 inst
.instruction
|= (abcdebits
>> 2) << 21;
16486 case NS_RRD
: /* case 7 (fmrrd). */
16487 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16490 inst
.instruction
= 0xc500b10;
16491 do_vfp_cond_or_thumb ();
16492 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16493 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16494 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16495 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16498 case NS_FF
: /* case 8 (fcpys). */
16499 do_vfp_nsyn_opcode ("fcpys");
16503 case NS_FI
: /* case 10 (fconsts). */
16504 ldconst
= "fconsts";
16506 if (is_quarter_float (inst
.operands
[1].imm
))
16508 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16509 do_vfp_nsyn_opcode (ldconst
);
16511 /* ARMv8.2 fp16 vmov.f16 instruction. */
16513 do_scalar_fp16_v82_encode ();
16516 first_error (_("immediate out of range"));
16520 case NS_RF
: /* case 12 (fmrs). */
16521 do_vfp_nsyn_opcode ("fmrs");
16522 /* ARMv8.2 fp16 vmov.f16 instruction. */
16524 do_scalar_fp16_v82_encode ();
16528 case NS_FR
: /* case 13 (fmsr). */
16529 do_vfp_nsyn_opcode ("fmsr");
16530 /* ARMv8.2 fp16 vmov.f16 instruction. */
16532 do_scalar_fp16_v82_encode ();
16535 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16536 (one of which is a list), but we have parsed four. Do some fiddling to
16537 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16539 case NS_RRFF
: /* case 14 (fmrrs). */
16540 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16541 _("VFP registers must be adjacent"));
16542 inst
.operands
[2].imm
= 2;
16543 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16544 do_vfp_nsyn_opcode ("fmrrs");
16547 case NS_FFRR
: /* case 15 (fmsrr). */
16548 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16549 _("VFP registers must be adjacent"));
16550 inst
.operands
[1] = inst
.operands
[2];
16551 inst
.operands
[2] = inst
.operands
[3];
16552 inst
.operands
[0].imm
= 2;
16553 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16554 do_vfp_nsyn_opcode ("fmsrr");
16558 /* neon_select_shape has determined that the instruction
16559 shape is wrong and has already set the error message. */
16568 do_neon_rshift_round_imm (void)
16570 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16571 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16572 int imm
= inst
.operands
[2].imm
;
16574 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16577 inst
.operands
[2].present
= 0;
16582 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16583 _("immediate out of range for shift"));
16584 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16589 do_neon_movhf (void)
16591 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16592 constraint (rs
!= NS_HH
, _("invalid suffix"));
16594 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16597 do_vfp_sp_monadic ();
16600 inst
.instruction
|= 0xf0000000;
16604 do_neon_movl (void)
16606 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16607 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16608 unsigned sizebits
= et
.size
>> 3;
16609 inst
.instruction
|= sizebits
<< 19;
16610 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16616 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16617 struct neon_type_el et
= neon_check_type (2, rs
,
16618 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16619 NEON_ENCODE (INTEGER
, inst
);
16620 neon_two_same (neon_quad (rs
), 1, et
.size
);
16624 do_neon_zip_uzp (void)
16626 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16627 struct neon_type_el et
= neon_check_type (2, rs
,
16628 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16629 if (rs
== NS_DD
&& et
.size
== 32)
16631 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16632 inst
.instruction
= N_MNEM_vtrn
;
16636 neon_two_same (neon_quad (rs
), 1, et
.size
);
16640 do_neon_sat_abs_neg (void)
16642 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16643 struct neon_type_el et
= neon_check_type (2, rs
,
16644 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16645 neon_two_same (neon_quad (rs
), 1, et
.size
);
16649 do_neon_pair_long (void)
16651 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16652 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16653 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16654 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16655 neon_two_same (neon_quad (rs
), 1, et
.size
);
16659 do_neon_recip_est (void)
16661 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16662 struct neon_type_el et
= neon_check_type (2, rs
,
16663 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16664 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16665 neon_two_same (neon_quad (rs
), 1, et
.size
);
16671 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16672 struct neon_type_el et
= neon_check_type (2, rs
,
16673 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16674 neon_two_same (neon_quad (rs
), 1, et
.size
);
16680 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16681 struct neon_type_el et
= neon_check_type (2, rs
,
16682 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16683 neon_two_same (neon_quad (rs
), 1, et
.size
);
16689 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16690 struct neon_type_el et
= neon_check_type (2, rs
,
16691 N_EQK
| N_INT
, N_8
| N_KEY
);
16692 neon_two_same (neon_quad (rs
), 1, et
.size
);
16698 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16699 neon_two_same (neon_quad (rs
), 1, -1);
16703 do_neon_tbl_tbx (void)
16705 unsigned listlenbits
;
16706 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16708 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16710 first_error (_("bad list length for table lookup"));
16714 listlenbits
= inst
.operands
[1].imm
- 1;
16715 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16716 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16717 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16718 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16719 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16720 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16721 inst
.instruction
|= listlenbits
<< 8;
16723 neon_dp_fixup (&inst
);
16727 do_neon_ldm_stm (void)
16729 /* P, U and L bits are part of bitmask. */
16730 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16731 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16733 if (inst
.operands
[1].issingle
)
16735 do_vfp_nsyn_ldm_stm (is_dbmode
);
16739 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16740 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16742 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16743 _("register list must contain at least 1 and at most 16 "
16746 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16747 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16748 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16749 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16751 inst
.instruction
|= offsetbits
;
16753 do_vfp_cond_or_thumb ();
16757 do_neon_ldr_str (void)
16759 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16761 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16762 And is UNPREDICTABLE in thumb mode. */
16764 && inst
.operands
[1].reg
== REG_PC
16765 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16768 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16769 else if (warn_on_deprecated
)
16770 as_tsktsk (_("Use of PC here is deprecated"));
16773 if (inst
.operands
[0].issingle
)
16776 do_vfp_nsyn_opcode ("flds");
16778 do_vfp_nsyn_opcode ("fsts");
16780 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16781 if (inst
.vectype
.el
[0].size
== 16)
16782 do_scalar_fp16_v82_encode ();
16787 do_vfp_nsyn_opcode ("fldd");
16789 do_vfp_nsyn_opcode ("fstd");
16793 /* "interleave" version also handles non-interleaving register VLD1/VST1
16797 do_neon_ld_st_interleave (void)
16799 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16800 N_8
| N_16
| N_32
| N_64
);
16801 unsigned alignbits
= 0;
16803 /* The bits in this table go:
16804 0: register stride of one (0) or two (1)
16805 1,2: register list length, minus one (1, 2, 3, 4).
16806 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16807 We use -1 for invalid entries. */
16808 const int typetable
[] =
16810 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16811 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16812 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16813 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16817 if (et
.type
== NT_invtype
)
16820 if (inst
.operands
[1].immisalign
)
16821 switch (inst
.operands
[1].imm
>> 8)
16823 case 64: alignbits
= 1; break;
16825 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16826 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16827 goto bad_alignment
;
16831 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16832 goto bad_alignment
;
16837 first_error (_("bad alignment"));
16841 inst
.instruction
|= alignbits
<< 4;
16842 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16844 /* Bits [4:6] of the immediate in a list specifier encode register stride
16845 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16846 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16847 up the right value for "type" in a table based on this value and the given
16848 list style, then stick it back. */
16849 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16850 | (((inst
.instruction
>> 8) & 3) << 3);
16852 typebits
= typetable
[idx
];
16854 constraint (typebits
== -1, _("bad list type for instruction"));
16855 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16856 _("bad element type for instruction"));
16858 inst
.instruction
&= ~0xf00;
16859 inst
.instruction
|= typebits
<< 8;
16862 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16863 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16864 otherwise. The variable arguments are a list of pairs of legal (size, align)
16865 values, terminated with -1. */
16868 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16871 int result
= FAIL
, thissize
, thisalign
;
16873 if (!inst
.operands
[1].immisalign
)
16879 va_start (ap
, do_alignment
);
16883 thissize
= va_arg (ap
, int);
16884 if (thissize
== -1)
16886 thisalign
= va_arg (ap
, int);
16888 if (size
== thissize
&& align
== thisalign
)
16891 while (result
!= SUCCESS
);
16895 if (result
== SUCCESS
)
16898 first_error (_("unsupported alignment for instruction"));
16904 do_neon_ld_st_lane (void)
16906 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16907 int align_good
, do_alignment
= 0;
16908 int logsize
= neon_logbits (et
.size
);
16909 int align
= inst
.operands
[1].imm
>> 8;
16910 int n
= (inst
.instruction
>> 8) & 3;
16911 int max_el
= 64 / et
.size
;
16913 if (et
.type
== NT_invtype
)
16916 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16917 _("bad list length"));
16918 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16919 _("scalar index out of range"));
16920 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16922 _("stride of 2 unavailable when element size is 8"));
16926 case 0: /* VLD1 / VST1. */
16927 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16929 if (align_good
== FAIL
)
16933 unsigned alignbits
= 0;
16936 case 16: alignbits
= 0x1; break;
16937 case 32: alignbits
= 0x3; break;
16940 inst
.instruction
|= alignbits
<< 4;
16944 case 1: /* VLD2 / VST2. */
16945 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16946 16, 32, 32, 64, -1);
16947 if (align_good
== FAIL
)
16950 inst
.instruction
|= 1 << 4;
16953 case 2: /* VLD3 / VST3. */
16954 constraint (inst
.operands
[1].immisalign
,
16955 _("can't use alignment with this instruction"));
16958 case 3: /* VLD4 / VST4. */
16959 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16960 16, 64, 32, 64, 32, 128, -1);
16961 if (align_good
== FAIL
)
16965 unsigned alignbits
= 0;
16968 case 8: alignbits
= 0x1; break;
16969 case 16: alignbits
= 0x1; break;
16970 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16973 inst
.instruction
|= alignbits
<< 4;
16980 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16981 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16982 inst
.instruction
|= 1 << (4 + logsize
);
16984 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16985 inst
.instruction
|= logsize
<< 10;
16988 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16991 do_neon_ld_dup (void)
16993 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16994 int align_good
, do_alignment
= 0;
16996 if (et
.type
== NT_invtype
)
16999 switch ((inst
.instruction
>> 8) & 3)
17001 case 0: /* VLD1. */
17002 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17003 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17004 &do_alignment
, 16, 16, 32, 32, -1);
17005 if (align_good
== FAIL
)
17007 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17010 case 2: inst
.instruction
|= 1 << 5; break;
17011 default: first_error (_("bad list length")); return;
17013 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17016 case 1: /* VLD2. */
17017 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17018 &do_alignment
, 8, 16, 16, 32, 32, 64,
17020 if (align_good
== FAIL
)
17022 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17023 _("bad list length"));
17024 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17025 inst
.instruction
|= 1 << 5;
17026 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17029 case 2: /* VLD3. */
17030 constraint (inst
.operands
[1].immisalign
,
17031 _("can't use alignment with this instruction"));
17032 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17033 _("bad list length"));
17034 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17035 inst
.instruction
|= 1 << 5;
17036 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17039 case 3: /* VLD4. */
17041 int align
= inst
.operands
[1].imm
>> 8;
17042 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17043 16, 64, 32, 64, 32, 128, -1);
17044 if (align_good
== FAIL
)
17046 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17047 _("bad list length"));
17048 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17049 inst
.instruction
|= 1 << 5;
17050 if (et
.size
== 32 && align
== 128)
17051 inst
.instruction
|= 0x3 << 6;
17053 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17060 inst
.instruction
|= do_alignment
<< 4;
17063 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17064 apart from bits [11:4]. */
17067 do_neon_ldx_stx (void)
17069 if (inst
.operands
[1].isreg
)
17070 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17072 switch (NEON_LANE (inst
.operands
[0].imm
))
17074 case NEON_INTERLEAVE_LANES
:
17075 NEON_ENCODE (INTERLV
, inst
);
17076 do_neon_ld_st_interleave ();
17079 case NEON_ALL_LANES
:
17080 NEON_ENCODE (DUP
, inst
);
17081 if (inst
.instruction
== N_INV
)
17083 first_error ("only loads support such operands");
17090 NEON_ENCODE (LANE
, inst
);
17091 do_neon_ld_st_lane ();
17094 /* L bit comes from bit mask. */
17095 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17096 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17097 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17099 if (inst
.operands
[1].postind
)
17101 int postreg
= inst
.operands
[1].imm
& 0xf;
17102 constraint (!inst
.operands
[1].immisreg
,
17103 _("post-index must be a register"));
17104 constraint (postreg
== 0xd || postreg
== 0xf,
17105 _("bad register for post-index"));
17106 inst
.instruction
|= postreg
;
17110 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17111 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17112 || inst
.reloc
.exp
.X_add_number
!= 0,
17115 if (inst
.operands
[1].writeback
)
17117 inst
.instruction
|= 0xd;
17120 inst
.instruction
|= 0xf;
17124 inst
.instruction
|= 0xf9000000;
17126 inst
.instruction
|= 0xf4000000;
17131 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17133 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17134 D register operands. */
17135 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17136 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17139 NEON_ENCODE (FPV8
, inst
);
17141 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17143 do_vfp_sp_dyadic ();
17145 /* ARMv8.2 fp16 instruction. */
17147 do_scalar_fp16_v82_encode ();
17150 do_vfp_dp_rd_rn_rm ();
17153 inst
.instruction
|= 0x100;
17155 inst
.instruction
|= 0xf0000000;
17161 set_it_insn_type (OUTSIDE_IT_INSN
);
17163 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17164 first_error (_("invalid instruction shape"));
17170 set_it_insn_type (OUTSIDE_IT_INSN
);
17172 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17175 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17178 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17182 do_vrint_1 (enum neon_cvt_mode mode
)
17184 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17185 struct neon_type_el et
;
17190 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17191 D register operands. */
17192 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17193 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17196 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17198 if (et
.type
!= NT_invtype
)
17200 /* VFP encodings. */
17201 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17202 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17203 set_it_insn_type (OUTSIDE_IT_INSN
);
17205 NEON_ENCODE (FPV8
, inst
);
17206 if (rs
== NS_FF
|| rs
== NS_HH
)
17207 do_vfp_sp_monadic ();
17209 do_vfp_dp_rd_rm ();
17213 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17214 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17215 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17216 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17217 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17218 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17219 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17223 inst
.instruction
|= (rs
== NS_DD
) << 8;
17224 do_vfp_cond_or_thumb ();
17226 /* ARMv8.2 fp16 vrint instruction. */
17228 do_scalar_fp16_v82_encode ();
17232 /* Neon encodings (or something broken...). */
17234 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17236 if (et
.type
== NT_invtype
)
17239 set_it_insn_type (OUTSIDE_IT_INSN
);
17240 NEON_ENCODE (FLOAT
, inst
);
17242 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17245 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17246 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17247 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17248 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17249 inst
.instruction
|= neon_quad (rs
) << 6;
17250 /* Mask off the original size bits and reencode them. */
17251 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17252 | neon_logbits (et
.size
) << 18);
17256 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17257 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17258 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17259 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17260 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17261 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17262 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17267 inst
.instruction
|= 0xfc000000;
17269 inst
.instruction
|= 0xf0000000;
17276 do_vrint_1 (neon_cvt_mode_x
);
17282 do_vrint_1 (neon_cvt_mode_z
);
17288 do_vrint_1 (neon_cvt_mode_r
);
17294 do_vrint_1 (neon_cvt_mode_a
);
17300 do_vrint_1 (neon_cvt_mode_n
);
17306 do_vrint_1 (neon_cvt_mode_p
);
17312 do_vrint_1 (neon_cvt_mode_m
);
17316 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17318 unsigned regno
= NEON_SCALAR_REG (opnd
);
17319 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17321 if (elsize
== 16 && elno
< 2 && regno
< 16)
17322 return regno
| (elno
<< 4);
17323 else if (elsize
== 32 && elno
== 0)
17326 first_error (_("scalar out of range"));
17333 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17335 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17336 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17337 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17338 _("immediate out of range"));
17340 if (inst
.operands
[2].isscalar
)
17342 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17343 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17344 N_KEY
| N_F16
| N_F32
).size
;
17345 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17347 inst
.instruction
= 0xfe000800;
17348 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17349 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17350 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17351 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17352 inst
.instruction
|= LOW4 (m
);
17353 inst
.instruction
|= HI1 (m
) << 5;
17354 inst
.instruction
|= neon_quad (rs
) << 6;
17355 inst
.instruction
|= rot
<< 20;
17356 inst
.instruction
|= (size
== 32) << 23;
17360 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17361 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17362 N_KEY
| N_F16
| N_F32
).size
;
17363 neon_three_same (neon_quad (rs
), 0, -1);
17364 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17365 inst
.instruction
|= 0xfc200800;
17366 inst
.instruction
|= rot
<< 23;
17367 inst
.instruction
|= (size
== 32) << 20;
17374 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17376 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17377 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17378 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17379 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17380 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17381 N_KEY
| N_F16
| N_F32
).size
;
17382 neon_three_same (neon_quad (rs
), 0, -1);
17383 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17384 inst
.instruction
|= 0xfc800800;
17385 inst
.instruction
|= (rot
== 270) << 24;
17386 inst
.instruction
|= (size
== 32) << 20;
17389 /* Dot Product instructions encoding support. */
17392 do_neon_dotproduct (int unsigned_p
)
17394 enum neon_shape rs
;
17395 unsigned scalar_oprd2
= 0;
17398 if (inst
.cond
!= COND_ALWAYS
)
17399 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17400 "is UNPREDICTABLE"));
17402 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17405 /* Dot Product instructions are in three-same D/Q register format or the third
17406 operand can be a scalar index register. */
17407 if (inst
.operands
[2].isscalar
)
17409 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
17410 high8
= 0xfe000000;
17411 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17415 high8
= 0xfc000000;
17416 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17420 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
17422 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
17424 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17425 Product instruction, so we pass 0 as the "ubit" parameter. And the
17426 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17427 neon_three_same (neon_quad (rs
), 0, 32);
17429 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17430 different NEON three-same encoding. */
17431 inst
.instruction
&= 0x00ffffff;
17432 inst
.instruction
|= high8
;
17433 /* Encode 'U' bit which indicates signedness. */
17434 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
17435 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17436 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17437 the instruction encoding. */
17438 if (inst
.operands
[2].isscalar
)
17440 inst
.instruction
&= 0xffffffd0;
17441 inst
.instruction
|= LOW4 (scalar_oprd2
);
17442 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
17446 /* Dot Product instructions for signed integer. */
17449 do_neon_dotproduct_s (void)
17451 return do_neon_dotproduct (0);
17454 /* Dot Product instructions for unsigned integer. */
17457 do_neon_dotproduct_u (void)
17459 return do_neon_dotproduct (1);
17462 /* Crypto v1 instructions. */
17464 do_crypto_2op_1 (unsigned elttype
, int op
)
17466 set_it_insn_type (OUTSIDE_IT_INSN
);
17468 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17474 NEON_ENCODE (INTEGER
, inst
);
17475 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17476 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17477 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17478 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17480 inst
.instruction
|= op
<< 6;
17483 inst
.instruction
|= 0xfc000000;
17485 inst
.instruction
|= 0xf0000000;
17489 do_crypto_3op_1 (int u
, int op
)
17491 set_it_insn_type (OUTSIDE_IT_INSN
);
17493 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17494 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17499 NEON_ENCODE (INTEGER
, inst
);
17500 neon_three_same (1, u
, 8 << op
);
17506 do_crypto_2op_1 (N_8
, 0);
17512 do_crypto_2op_1 (N_8
, 1);
17518 do_crypto_2op_1 (N_8
, 2);
17524 do_crypto_2op_1 (N_8
, 3);
17530 do_crypto_3op_1 (0, 0);
17536 do_crypto_3op_1 (0, 1);
17542 do_crypto_3op_1 (0, 2);
17548 do_crypto_3op_1 (0, 3);
17554 do_crypto_3op_1 (1, 0);
17560 do_crypto_3op_1 (1, 1);
17564 do_sha256su1 (void)
17566 do_crypto_3op_1 (1, 2);
17572 do_crypto_2op_1 (N_32
, -1);
17578 do_crypto_2op_1 (N_32
, 0);
17582 do_sha256su0 (void)
17584 do_crypto_2op_1 (N_32
, 1);
17588 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17590 unsigned int Rd
= inst
.operands
[0].reg
;
17591 unsigned int Rn
= inst
.operands
[1].reg
;
17592 unsigned int Rm
= inst
.operands
[2].reg
;
17594 set_it_insn_type (OUTSIDE_IT_INSN
);
17595 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17596 inst
.instruction
|= LOW4 (Rn
) << 16;
17597 inst
.instruction
|= LOW4 (Rm
);
17598 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17599 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17601 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17602 as_warn (UNPRED_REG ("r15"));
17644 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17646 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17647 do_vfp_sp_dp_cvt ();
17648 do_vfp_cond_or_thumb ();
17652 /* Overall per-instruction processing. */
17654 /* We need to be able to fix up arbitrary expressions in some statements.
17655 This is so that we can handle symbols that are an arbitrary distance from
17656 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17657 which returns part of an address in a form which will be valid for
17658 a data instruction. We do this by pushing the expression into a symbol
17659 in the expr_section, and creating a fix for that. */
17662 fix_new_arm (fragS
* frag
,
17676 /* Create an absolute valued symbol, so we have something to
17677 refer to in the object file. Unfortunately for us, gas's
17678 generic expression parsing will already have folded out
17679 any use of .set foo/.type foo %function that may have
17680 been used to set type information of the target location,
17681 that's being specified symbolically. We have to presume
17682 the user knows what they are doing. */
17686 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17688 symbol
= symbol_find_or_make (name
);
17689 S_SET_SEGMENT (symbol
, absolute_section
);
17690 symbol_set_frag (symbol
, &zero_address_frag
);
17691 S_SET_VALUE (symbol
, exp
->X_add_number
);
17692 exp
->X_op
= O_symbol
;
17693 exp
->X_add_symbol
= symbol
;
17694 exp
->X_add_number
= 0;
17700 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17701 (enum bfd_reloc_code_real
) reloc
);
17705 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17706 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17710 /* Mark whether the fix is to a THUMB instruction, or an ARM
17712 new_fix
->tc_fix_data
= thumb_mode
;
17715 /* Create a frg for an instruction requiring relaxation. */
17717 output_relax_insn (void)
17723 /* The size of the instruction is unknown, so tie the debug info to the
17724 start of the instruction. */
17725 dwarf2_emit_insn (0);
17727 switch (inst
.reloc
.exp
.X_op
)
17730 sym
= inst
.reloc
.exp
.X_add_symbol
;
17731 offset
= inst
.reloc
.exp
.X_add_number
;
17735 offset
= inst
.reloc
.exp
.X_add_number
;
17738 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17742 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17743 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17744 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17747 /* Write a 32-bit thumb instruction to buf. */
17749 put_thumb32_insn (char * buf
, unsigned long insn
)
17751 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17752 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17756 output_inst (const char * str
)
17762 as_bad ("%s -- `%s'", inst
.error
, str
);
17767 output_relax_insn ();
17770 if (inst
.size
== 0)
17773 to
= frag_more (inst
.size
);
17774 /* PR 9814: Record the thumb mode into the current frag so that we know
17775 what type of NOP padding to use, if necessary. We override any previous
17776 setting so that if the mode has changed then the NOPS that we use will
17777 match the encoding of the last instruction in the frag. */
17778 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17780 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17782 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17783 put_thumb32_insn (to
, inst
.instruction
);
17785 else if (inst
.size
> INSN_SIZE
)
17787 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17788 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17789 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17792 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17794 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17795 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17796 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17799 dwarf2_emit_insn (inst
.size
);
17803 output_it_inst (int cond
, int mask
, char * to
)
17805 unsigned long instruction
= 0xbf00;
17808 instruction
|= mask
;
17809 instruction
|= cond
<< 4;
17813 to
= frag_more (2);
17815 dwarf2_emit_insn (2);
17819 md_number_to_chars (to
, instruction
, 2);
17824 /* Tag values used in struct asm_opcode's tag field. */
17827 OT_unconditional
, /* Instruction cannot be conditionalized.
17828 The ARM condition field is still 0xE. */
17829 OT_unconditionalF
, /* Instruction cannot be conditionalized
17830 and carries 0xF in its ARM condition field. */
17831 OT_csuffix
, /* Instruction takes a conditional suffix. */
17832 OT_csuffixF
, /* Some forms of the instruction take a conditional
17833 suffix, others place 0xF where the condition field
17835 OT_cinfix3
, /* Instruction takes a conditional infix,
17836 beginning at character index 3. (In
17837 unified mode, it becomes a suffix.) */
17838 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17839 tsts, cmps, cmns, and teqs. */
17840 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17841 character index 3, even in unified mode. Used for
17842 legacy instructions where suffix and infix forms
17843 may be ambiguous. */
17844 OT_csuf_or_in3
, /* Instruction takes either a conditional
17845 suffix or an infix at character index 3. */
17846 OT_odd_infix_unc
, /* This is the unconditional variant of an
17847 instruction that takes a conditional infix
17848 at an unusual position. In unified mode,
17849 this variant will accept a suffix. */
17850 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17851 are the conditional variants of instructions that
17852 take conditional infixes in unusual positions.
17853 The infix appears at character index
17854 (tag - OT_odd_infix_0). These are not accepted
17855 in unified mode. */
17858 /* Subroutine of md_assemble, responsible for looking up the primary
17859 opcode from the mnemonic the user wrote. STR points to the
17860 beginning of the mnemonic.
17862 This is not simply a hash table lookup, because of conditional
17863 variants. Most instructions have conditional variants, which are
17864 expressed with a _conditional affix_ to the mnemonic. If we were
17865 to encode each conditional variant as a literal string in the opcode
17866 table, it would have approximately 20,000 entries.
17868 Most mnemonics take this affix as a suffix, and in unified syntax,
17869 'most' is upgraded to 'all'. However, in the divided syntax, some
17870 instructions take the affix as an infix, notably the s-variants of
17871 the arithmetic instructions. Of those instructions, all but six
17872 have the infix appear after the third character of the mnemonic.
17874 Accordingly, the algorithm for looking up primary opcodes given
17877 1. Look up the identifier in the opcode table.
17878 If we find a match, go to step U.
17880 2. Look up the last two characters of the identifier in the
17881 conditions table. If we find a match, look up the first N-2
17882 characters of the identifier in the opcode table. If we
17883 find a match, go to step CE.
17885 3. Look up the fourth and fifth characters of the identifier in
17886 the conditions table. If we find a match, extract those
17887 characters from the identifier, and look up the remaining
17888 characters in the opcode table. If we find a match, go
17893 U. Examine the tag field of the opcode structure, in case this is
17894 one of the six instructions with its conditional infix in an
17895 unusual place. If it is, the tag tells us where to find the
17896 infix; look it up in the conditions table and set inst.cond
17897 accordingly. Otherwise, this is an unconditional instruction.
17898 Again set inst.cond accordingly. Return the opcode structure.
17900 CE. Examine the tag field to make sure this is an instruction that
17901 should receive a conditional suffix. If it is not, fail.
17902 Otherwise, set inst.cond from the suffix we already looked up,
17903 and return the opcode structure.
17905 CM. Examine the tag field to make sure this is an instruction that
17906 should receive a conditional infix after the third character.
17907 If it is not, fail. Otherwise, undo the edits to the current
17908 line of input and proceed as for case CE. */
17910 static const struct asm_opcode
*
17911 opcode_lookup (char **str
)
17915 const struct asm_opcode
*opcode
;
17916 const struct asm_cond
*cond
;
17919 /* Scan up to the end of the mnemonic, which must end in white space,
17920 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17921 for (base
= end
= *str
; *end
!= '\0'; end
++)
17922 if (*end
== ' ' || *end
== '.')
17928 /* Handle a possible width suffix and/or Neon type suffix. */
17933 /* The .w and .n suffixes are only valid if the unified syntax is in
17935 if (unified_syntax
&& end
[1] == 'w')
17937 else if (unified_syntax
&& end
[1] == 'n')
17942 inst
.vectype
.elems
= 0;
17944 *str
= end
+ offset
;
17946 if (end
[offset
] == '.')
17948 /* See if we have a Neon type suffix (possible in either unified or
17949 non-unified ARM syntax mode). */
17950 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17953 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17959 /* Look for unaffixed or special-case affixed mnemonic. */
17960 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17965 if (opcode
->tag
< OT_odd_infix_0
)
17967 inst
.cond
= COND_ALWAYS
;
17971 if (warn_on_deprecated
&& unified_syntax
)
17972 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17973 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17974 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17977 inst
.cond
= cond
->value
;
17981 /* Cannot have a conditional suffix on a mnemonic of less than two
17983 if (end
- base
< 3)
17986 /* Look for suffixed mnemonic. */
17988 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17989 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17991 if (opcode
&& cond
)
17994 switch (opcode
->tag
)
17996 case OT_cinfix3_legacy
:
17997 /* Ignore conditional suffixes matched on infix only mnemonics. */
18001 case OT_cinfix3_deprecated
:
18002 case OT_odd_infix_unc
:
18003 if (!unified_syntax
)
18005 /* Fall through. */
18009 case OT_csuf_or_in3
:
18010 inst
.cond
= cond
->value
;
18013 case OT_unconditional
:
18014 case OT_unconditionalF
:
18016 inst
.cond
= cond
->value
;
18019 /* Delayed diagnostic. */
18020 inst
.error
= BAD_COND
;
18021 inst
.cond
= COND_ALWAYS
;
18030 /* Cannot have a usual-position infix on a mnemonic of less than
18031 six characters (five would be a suffix). */
18032 if (end
- base
< 6)
18035 /* Look for infixed mnemonic in the usual position. */
18037 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18041 memcpy (save
, affix
, 2);
18042 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18043 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18045 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18046 memcpy (affix
, save
, 2);
18049 && (opcode
->tag
== OT_cinfix3
18050 || opcode
->tag
== OT_cinfix3_deprecated
18051 || opcode
->tag
== OT_csuf_or_in3
18052 || opcode
->tag
== OT_cinfix3_legacy
))
18055 if (warn_on_deprecated
&& unified_syntax
18056 && (opcode
->tag
== OT_cinfix3
18057 || opcode
->tag
== OT_cinfix3_deprecated
))
18058 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18060 inst
.cond
= cond
->value
;
18067 /* This function generates an initial IT instruction, leaving its block
18068 virtually open for the new instructions. Eventually,
18069 the mask will be updated by now_it_add_mask () each time
18070 a new instruction needs to be included in the IT block.
18071 Finally, the block is closed with close_automatic_it_block ().
18072 The block closure can be requested either from md_assemble (),
18073 a tencode (), or due to a label hook. */
18076 new_automatic_it_block (int cond
)
18078 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18079 now_it
.mask
= 0x18;
18081 now_it
.block_length
= 1;
18082 mapping_state (MAP_THUMB
);
18083 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18084 now_it
.warn_deprecated
= FALSE
;
18085 now_it
.insn_cond
= TRUE
;
18088 /* Close an automatic IT block.
18089 See comments in new_automatic_it_block (). */
18092 close_automatic_it_block (void)
18094 now_it
.mask
= 0x10;
18095 now_it
.block_length
= 0;
18098 /* Update the mask of the current automatically-generated IT
18099 instruction. See comments in new_automatic_it_block (). */
18102 now_it_add_mask (int cond
)
18104 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18105 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18106 | ((bitvalue) << (nbit)))
18107 const int resulting_bit
= (cond
& 1);
18109 now_it
.mask
&= 0xf;
18110 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18112 (5 - now_it
.block_length
));
18113 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18115 ((5 - now_it
.block_length
) - 1) );
18116 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18119 #undef SET_BIT_VALUE
18122 /* The IT blocks handling machinery is accessed through the these functions:
18123 it_fsm_pre_encode () from md_assemble ()
18124 set_it_insn_type () optional, from the tencode functions
18125 set_it_insn_type_last () ditto
18126 in_it_block () ditto
18127 it_fsm_post_encode () from md_assemble ()
18128 force_automatic_it_block_close () from label handling functions
18131 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18132 initializing the IT insn type with a generic initial value depending
18133 on the inst.condition.
18134 2) During the tencode function, two things may happen:
18135 a) The tencode function overrides the IT insn type by
18136 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18137 b) The tencode function queries the IT block state by
18138 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18140 Both set_it_insn_type and in_it_block run the internal FSM state
18141 handling function (handle_it_state), because: a) setting the IT insn
18142 type may incur in an invalid state (exiting the function),
18143 and b) querying the state requires the FSM to be updated.
18144 Specifically we want to avoid creating an IT block for conditional
18145 branches, so it_fsm_pre_encode is actually a guess and we can't
18146 determine whether an IT block is required until the tencode () routine
18147 has decided what type of instruction this actually it.
18148 Because of this, if set_it_insn_type and in_it_block have to be used,
18149 set_it_insn_type has to be called first.
18151 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18152 determines the insn IT type depending on the inst.cond code.
18153 When a tencode () routine encodes an instruction that can be
18154 either outside an IT block, or, in the case of being inside, has to be
18155 the last one, set_it_insn_type_last () will determine the proper
18156 IT instruction type based on the inst.cond code. Otherwise,
18157 set_it_insn_type can be called for overriding that logic or
18158 for covering other cases.
18160 Calling handle_it_state () may not transition the IT block state to
18161 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18162 still queried. Instead, if the FSM determines that the state should
18163 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18164 after the tencode () function: that's what it_fsm_post_encode () does.
18166 Since in_it_block () calls the state handling function to get an
18167 updated state, an error may occur (due to invalid insns combination).
18168 In that case, inst.error is set.
18169 Therefore, inst.error has to be checked after the execution of
18170 the tencode () routine.
18172 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18173 any pending state change (if any) that didn't take place in
18174 handle_it_state () as explained above. */
18177 it_fsm_pre_encode (void)
18179 if (inst
.cond
!= COND_ALWAYS
)
18180 inst
.it_insn_type
= INSIDE_IT_INSN
;
18182 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18184 now_it
.state_handled
= 0;
18187 /* IT state FSM handling function. */
18190 handle_it_state (void)
18192 now_it
.state_handled
= 1;
18193 now_it
.insn_cond
= FALSE
;
18195 switch (now_it
.state
)
18197 case OUTSIDE_IT_BLOCK
:
18198 switch (inst
.it_insn_type
)
18200 case OUTSIDE_IT_INSN
:
18203 case INSIDE_IT_INSN
:
18204 case INSIDE_IT_LAST_INSN
:
18205 if (thumb_mode
== 0)
18208 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18209 as_tsktsk (_("Warning: conditional outside an IT block"\
18214 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18215 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18217 /* Automatically generate the IT instruction. */
18218 new_automatic_it_block (inst
.cond
);
18219 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18220 close_automatic_it_block ();
18224 inst
.error
= BAD_OUT_IT
;
18230 case IF_INSIDE_IT_LAST_INSN
:
18231 case NEUTRAL_IT_INSN
:
18235 now_it
.state
= MANUAL_IT_BLOCK
;
18236 now_it
.block_length
= 0;
18241 case AUTOMATIC_IT_BLOCK
:
18242 /* Three things may happen now:
18243 a) We should increment current it block size;
18244 b) We should close current it block (closing insn or 4 insns);
18245 c) We should close current it block and start a new one (due
18246 to incompatible conditions or
18247 4 insns-length block reached). */
18249 switch (inst
.it_insn_type
)
18251 case OUTSIDE_IT_INSN
:
18252 /* The closure of the block shall happen immediately,
18253 so any in_it_block () call reports the block as closed. */
18254 force_automatic_it_block_close ();
18257 case INSIDE_IT_INSN
:
18258 case INSIDE_IT_LAST_INSN
:
18259 case IF_INSIDE_IT_LAST_INSN
:
18260 now_it
.block_length
++;
18262 if (now_it
.block_length
> 4
18263 || !now_it_compatible (inst
.cond
))
18265 force_automatic_it_block_close ();
18266 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18267 new_automatic_it_block (inst
.cond
);
18271 now_it
.insn_cond
= TRUE
;
18272 now_it_add_mask (inst
.cond
);
18275 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18276 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18277 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18278 close_automatic_it_block ();
18281 case NEUTRAL_IT_INSN
:
18282 now_it
.block_length
++;
18283 now_it
.insn_cond
= TRUE
;
18285 if (now_it
.block_length
> 4)
18286 force_automatic_it_block_close ();
18288 now_it_add_mask (now_it
.cc
& 1);
18292 close_automatic_it_block ();
18293 now_it
.state
= MANUAL_IT_BLOCK
;
18298 case MANUAL_IT_BLOCK
:
18300 /* Check conditional suffixes. */
18301 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18304 now_it
.mask
&= 0x1f;
18305 is_last
= (now_it
.mask
== 0x10);
18306 now_it
.insn_cond
= TRUE
;
18308 switch (inst
.it_insn_type
)
18310 case OUTSIDE_IT_INSN
:
18311 inst
.error
= BAD_NOT_IT
;
18314 case INSIDE_IT_INSN
:
18315 if (cond
!= inst
.cond
)
18317 inst
.error
= BAD_IT_COND
;
18322 case INSIDE_IT_LAST_INSN
:
18323 case IF_INSIDE_IT_LAST_INSN
:
18324 if (cond
!= inst
.cond
)
18326 inst
.error
= BAD_IT_COND
;
18331 inst
.error
= BAD_BRANCH
;
18336 case NEUTRAL_IT_INSN
:
18337 /* The BKPT instruction is unconditional even in an IT block. */
18341 inst
.error
= BAD_IT_IT
;
18351 struct depr_insn_mask
18353 unsigned long pattern
;
18354 unsigned long mask
;
18355 const char* description
;
18358 /* List of 16-bit instruction patterns deprecated in an IT block in
18360 static const struct depr_insn_mask depr_it_insns
[] = {
18361 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18362 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18363 { 0xa000, 0xb800, N_("ADR") },
18364 { 0x4800, 0xf800, N_("Literal loads") },
18365 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18366 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18367 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18368 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18369 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18374 it_fsm_post_encode (void)
18378 if (!now_it
.state_handled
)
18379 handle_it_state ();
18381 if (now_it
.insn_cond
18382 && !now_it
.warn_deprecated
18383 && warn_on_deprecated
18384 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18386 if (inst
.instruction
>= 0x10000)
18388 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18389 "deprecated in ARMv8"));
18390 now_it
.warn_deprecated
= TRUE
;
18394 const struct depr_insn_mask
*p
= depr_it_insns
;
18396 while (p
->mask
!= 0)
18398 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18400 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18401 "of the following class are deprecated in ARMv8: "
18402 "%s"), p
->description
);
18403 now_it
.warn_deprecated
= TRUE
;
18411 if (now_it
.block_length
> 1)
18413 as_tsktsk (_("IT blocks containing more than one conditional "
18414 "instruction are deprecated in ARMv8"));
18415 now_it
.warn_deprecated
= TRUE
;
18419 is_last
= (now_it
.mask
== 0x10);
18422 now_it
.state
= OUTSIDE_IT_BLOCK
;
18428 force_automatic_it_block_close (void)
18430 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18432 close_automatic_it_block ();
18433 now_it
.state
= OUTSIDE_IT_BLOCK
;
18441 if (!now_it
.state_handled
)
18442 handle_it_state ();
18444 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18447 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18448 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18449 here, hence the "known" in the function name. */
18452 known_t32_only_insn (const struct asm_opcode
*opcode
)
18454 /* Original Thumb-1 wide instruction. */
18455 if (opcode
->tencode
== do_t_blx
18456 || opcode
->tencode
== do_t_branch23
18457 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18458 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18461 /* Wide-only instruction added to ARMv8-M Baseline. */
18462 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18463 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18464 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18465 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18471 /* Whether wide instruction variant can be used if available for a valid OPCODE
18475 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18477 if (known_t32_only_insn (opcode
))
18480 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18481 of variant T3 of B.W is checked in do_t_branch. */
18482 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18483 && opcode
->tencode
== do_t_branch
)
18486 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18487 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18488 && opcode
->tencode
== do_t_mov_cmp
18489 /* Make sure CMP instruction is not affected. */
18490 && opcode
->aencode
== do_mov
)
18493 /* Wide instruction variants of all instructions with narrow *and* wide
18494 variants become available with ARMv6t2. Other opcodes are either
18495 narrow-only or wide-only and are thus available if OPCODE is valid. */
18496 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18499 /* OPCODE with narrow only instruction variant or wide variant not
18505 md_assemble (char *str
)
18508 const struct asm_opcode
* opcode
;
18510 /* Align the previous label if needed. */
18511 if (last_label_seen
!= NULL
)
18513 symbol_set_frag (last_label_seen
, frag_now
);
18514 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18515 S_SET_SEGMENT (last_label_seen
, now_seg
);
18518 memset (&inst
, '\0', sizeof (inst
));
18519 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18521 opcode
= opcode_lookup (&p
);
18524 /* It wasn't an instruction, but it might be a register alias of
18525 the form alias .req reg, or a Neon .dn/.qn directive. */
18526 if (! create_register_alias (str
, p
)
18527 && ! create_neon_reg_alias (str
, p
))
18528 as_bad (_("bad instruction `%s'"), str
);
18533 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18534 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18536 /* The value which unconditional instructions should have in place of the
18537 condition field. */
18538 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18542 arm_feature_set variant
;
18544 variant
= cpu_variant
;
18545 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18546 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18547 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18548 /* Check that this instruction is supported for this CPU. */
18549 if (!opcode
->tvariant
18550 || (thumb_mode
== 1
18551 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18553 if (opcode
->tencode
== do_t_swi
)
18554 as_bad (_("SVC is not permitted on this architecture"));
18556 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18559 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18560 && opcode
->tencode
!= do_t_branch
)
18562 as_bad (_("Thumb does not support conditional execution"));
18566 /* Two things are addressed here:
18567 1) Implicit require narrow instructions on Thumb-1.
18568 This avoids relaxation accidentally introducing Thumb-2
18570 2) Reject wide instructions in non Thumb-2 cores.
18572 Only instructions with narrow and wide variants need to be handled
18573 but selecting all non wide-only instructions is easier. */
18574 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18575 && !t32_insn_ok (variant
, opcode
))
18577 if (inst
.size_req
== 0)
18579 else if (inst
.size_req
== 4)
18581 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18582 as_bad (_("selected processor does not support 32bit wide "
18583 "variant of instruction `%s'"), str
);
18585 as_bad (_("selected processor does not support `%s' in "
18586 "Thumb-2 mode"), str
);
18591 inst
.instruction
= opcode
->tvalue
;
18593 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18595 /* Prepare the it_insn_type for those encodings that don't set
18597 it_fsm_pre_encode ();
18599 opcode
->tencode ();
18601 it_fsm_post_encode ();
18604 if (!(inst
.error
|| inst
.relax
))
18606 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18607 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18608 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18610 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18615 /* Something has gone badly wrong if we try to relax a fixed size
18617 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18619 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18620 *opcode
->tvariant
);
18621 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18622 set those bits when Thumb-2 32-bit instructions are seen. The impact
18623 of relaxable instructions will be considered later after we finish all
18625 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18626 variant
= arm_arch_none
;
18628 variant
= cpu_variant
;
18629 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18630 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18633 check_neon_suffixes
;
18637 mapping_state (MAP_THUMB
);
18640 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18644 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18645 is_bx
= (opcode
->aencode
== do_bx
);
18647 /* Check that this instruction is supported for this CPU. */
18648 if (!(is_bx
&& fix_v4bx
)
18649 && !(opcode
->avariant
&&
18650 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18652 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18657 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18661 inst
.instruction
= opcode
->avalue
;
18662 if (opcode
->tag
== OT_unconditionalF
)
18663 inst
.instruction
|= 0xFU
<< 28;
18665 inst
.instruction
|= inst
.cond
<< 28;
18666 inst
.size
= INSN_SIZE
;
18667 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18669 it_fsm_pre_encode ();
18670 opcode
->aencode ();
18671 it_fsm_post_encode ();
18673 /* Arm mode bx is marked as both v4T and v5 because it's still required
18674 on a hypothetical non-thumb v5 core. */
18676 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18678 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18679 *opcode
->avariant
);
18681 check_neon_suffixes
;
18685 mapping_state (MAP_ARM
);
18690 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18698 check_it_blocks_finished (void)
18703 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18704 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18705 == MANUAL_IT_BLOCK
)
18707 as_warn (_("section '%s' finished with an open IT block."),
18711 if (now_it
.state
== MANUAL_IT_BLOCK
)
18712 as_warn (_("file finished with an open IT block."));
18716 /* Various frobbings of labels and their addresses. */
18719 arm_start_line_hook (void)
18721 last_label_seen
= NULL
;
18725 arm_frob_label (symbolS
* sym
)
18727 last_label_seen
= sym
;
18729 ARM_SET_THUMB (sym
, thumb_mode
);
18731 #if defined OBJ_COFF || defined OBJ_ELF
18732 ARM_SET_INTERWORK (sym
, support_interwork
);
18735 force_automatic_it_block_close ();
18737 /* Note - do not allow local symbols (.Lxxx) to be labelled
18738 as Thumb functions. This is because these labels, whilst
18739 they exist inside Thumb code, are not the entry points for
18740 possible ARM->Thumb calls. Also, these labels can be used
18741 as part of a computed goto or switch statement. eg gcc
18742 can generate code that looks like this:
18744 ldr r2, [pc, .Laaa]
18754 The first instruction loads the address of the jump table.
18755 The second instruction converts a table index into a byte offset.
18756 The third instruction gets the jump address out of the table.
18757 The fourth instruction performs the jump.
18759 If the address stored at .Laaa is that of a symbol which has the
18760 Thumb_Func bit set, then the linker will arrange for this address
18761 to have the bottom bit set, which in turn would mean that the
18762 address computation performed by the third instruction would end
18763 up with the bottom bit set. Since the ARM is capable of unaligned
18764 word loads, the instruction would then load the incorrect address
18765 out of the jump table, and chaos would ensue. */
18766 if (label_is_thumb_function_name
18767 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18768 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18770 /* When the address of a Thumb function is taken the bottom
18771 bit of that address should be set. This will allow
18772 interworking between Arm and Thumb functions to work
18775 THUMB_SET_FUNC (sym
, 1);
18777 label_is_thumb_function_name
= FALSE
;
18780 dwarf2_emit_label (sym
);
18784 arm_data_in_code (void)
18786 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18788 *input_line_pointer
= '/';
18789 input_line_pointer
+= 5;
18790 *input_line_pointer
= 0;
18798 arm_canonicalize_symbol_name (char * name
)
18802 if (thumb_mode
&& (len
= strlen (name
)) > 5
18803 && streq (name
+ len
- 5, "/data"))
18804 *(name
+ len
- 5) = 0;
18809 /* Table of all register names defined by default. The user can
18810 define additional names with .req. Note that all register names
18811 should appear in both upper and lowercase variants. Some registers
18812 also have mixed-case names. */
18814 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18815 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18816 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18817 #define REGSET(p,t) \
18818 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18819 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18820 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18821 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18822 #define REGSETH(p,t) \
18823 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18824 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18825 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18826 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18827 #define REGSET2(p,t) \
18828 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18829 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18830 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18831 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18832 #define SPLRBANK(base,bank,t) \
18833 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18834 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18835 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18836 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18837 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18838 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18840 static const struct reg_entry reg_names
[] =
18842 /* ARM integer registers. */
18843 REGSET(r
, RN
), REGSET(R
, RN
),
18845 /* ATPCS synonyms. */
18846 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18847 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18848 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18850 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18851 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18852 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18854 /* Well-known aliases. */
18855 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18856 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18858 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18859 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18861 /* Coprocessor numbers. */
18862 REGSET(p
, CP
), REGSET(P
, CP
),
18864 /* Coprocessor register numbers. The "cr" variants are for backward
18866 REGSET(c
, CN
), REGSET(C
, CN
),
18867 REGSET(cr
, CN
), REGSET(CR
, CN
),
18869 /* ARM banked registers. */
18870 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18871 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18872 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18873 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18874 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18875 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18876 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18878 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18879 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18880 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18881 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18882 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18883 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18884 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18885 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18887 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18888 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18889 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18890 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18891 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18892 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18893 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18894 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18895 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18897 /* FPA registers. */
18898 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18899 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18901 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18902 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18904 /* VFP SP registers. */
18905 REGSET(s
,VFS
), REGSET(S
,VFS
),
18906 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18908 /* VFP DP Registers. */
18909 REGSET(d
,VFD
), REGSET(D
,VFD
),
18910 /* Extra Neon DP registers. */
18911 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18913 /* Neon QP registers. */
18914 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18916 /* VFP control registers. */
18917 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18918 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18919 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18920 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18921 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18922 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18923 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
18925 /* Maverick DSP coprocessor registers. */
18926 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18927 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18929 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18930 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18931 REGDEF(dspsc
,0,DSPSC
),
18933 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18934 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18935 REGDEF(DSPSC
,0,DSPSC
),
18937 /* iWMMXt data registers - p0, c0-15. */
18938 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18940 /* iWMMXt control registers - p1, c0-3. */
18941 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18942 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18943 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18944 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18946 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18947 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18948 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18949 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18950 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18952 /* XScale accumulator registers. */
18953 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18959 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18960 within psr_required_here. */
18961 static const struct asm_psr psrs
[] =
18963 /* Backward compatibility notation. Note that "all" is no longer
18964 truly all possible PSR bits. */
18965 {"all", PSR_c
| PSR_f
},
18969 /* Individual flags. */
18975 /* Combinations of flags. */
18976 {"fs", PSR_f
| PSR_s
},
18977 {"fx", PSR_f
| PSR_x
},
18978 {"fc", PSR_f
| PSR_c
},
18979 {"sf", PSR_s
| PSR_f
},
18980 {"sx", PSR_s
| PSR_x
},
18981 {"sc", PSR_s
| PSR_c
},
18982 {"xf", PSR_x
| PSR_f
},
18983 {"xs", PSR_x
| PSR_s
},
18984 {"xc", PSR_x
| PSR_c
},
18985 {"cf", PSR_c
| PSR_f
},
18986 {"cs", PSR_c
| PSR_s
},
18987 {"cx", PSR_c
| PSR_x
},
18988 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18989 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18990 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18991 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18992 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18993 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18994 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18995 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18996 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18997 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18998 {"scf", PSR_s
| PSR_c
| PSR_f
},
18999 {"scx", PSR_s
| PSR_c
| PSR_x
},
19000 {"xfs", PSR_x
| PSR_f
| PSR_s
},
19001 {"xfc", PSR_x
| PSR_f
| PSR_c
},
19002 {"xsf", PSR_x
| PSR_s
| PSR_f
},
19003 {"xsc", PSR_x
| PSR_s
| PSR_c
},
19004 {"xcf", PSR_x
| PSR_c
| PSR_f
},
19005 {"xcs", PSR_x
| PSR_c
| PSR_s
},
19006 {"cfs", PSR_c
| PSR_f
| PSR_s
},
19007 {"cfx", PSR_c
| PSR_f
| PSR_x
},
19008 {"csf", PSR_c
| PSR_s
| PSR_f
},
19009 {"csx", PSR_c
| PSR_s
| PSR_x
},
19010 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19011 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19012 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19013 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19014 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19015 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19016 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19017 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19018 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19019 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19020 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19021 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19022 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19023 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19024 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19025 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19026 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19027 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19028 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19029 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19030 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19031 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19032 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19033 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19034 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19035 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19038 /* Table of V7M psr names. */
19039 static const struct asm_psr v7m_psrs
[] =
19041 {"apsr", 0x0 }, {"APSR", 0x0 },
19042 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19043 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19044 {"psr", 0x3 }, {"PSR", 0x3 },
19045 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19046 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19047 {"epsr", 0x6 }, {"EPSR", 0x6 },
19048 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19049 {"msp", 0x8 }, {"MSP", 0x8 },
19050 {"psp", 0x9 }, {"PSP", 0x9 },
19051 {"msplim", 0xa }, {"MSPLIM", 0xa },
19052 {"psplim", 0xb }, {"PSPLIM", 0xb },
19053 {"primask", 0x10}, {"PRIMASK", 0x10},
19054 {"basepri", 0x11}, {"BASEPRI", 0x11},
19055 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19056 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19057 {"control", 0x14}, {"CONTROL", 0x14},
19058 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19059 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19060 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19061 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19062 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19063 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19064 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19065 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19066 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19069 /* Table of all shift-in-operand names. */
19070 static const struct asm_shift_name shift_names
[] =
19072 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19073 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19074 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19075 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19076 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19077 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19080 /* Table of all explicit relocation names. */
19082 static struct reloc_entry reloc_names
[] =
19084 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19085 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19086 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19087 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19088 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19089 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19090 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19091 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19092 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19093 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19094 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19095 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19096 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19097 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19098 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19099 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19100 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19101 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
19105 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19106 static const struct asm_cond conds
[] =
19110 {"cs", 0x2}, {"hs", 0x2},
19111 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19125 #define UL_BARRIER(L,U,CODE,FEAT) \
19126 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19127 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19129 static struct asm_barrier_opt barrier_opt_names
[] =
19131 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19132 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19133 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19134 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19135 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19136 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19137 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19138 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19139 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19140 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19141 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19142 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19143 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19144 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19145 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19146 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19151 /* Table of ARM-format instructions. */
19153 /* Macros for gluing together operand strings. N.B. In all cases
19154 other than OPS0, the trailing OP_stop comes from default
19155 zero-initialization of the unspecified elements of the array. */
19156 #define OPS0() { OP_stop, }
19157 #define OPS1(a) { OP_##a, }
19158 #define OPS2(a,b) { OP_##a,OP_##b, }
19159 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19160 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19161 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19162 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19164 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19165 This is useful when mixing operands for ARM and THUMB, i.e. using the
19166 MIX_ARM_THUMB_OPERANDS macro.
19167 In order to use these macros, prefix the number of operands with _
19169 #define OPS_1(a) { a, }
19170 #define OPS_2(a,b) { a,b, }
19171 #define OPS_3(a,b,c) { a,b,c, }
19172 #define OPS_4(a,b,c,d) { a,b,c,d, }
19173 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19174 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19176 /* These macros abstract out the exact format of the mnemonic table and
19177 save some repeated characters. */
19179 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19180 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19181 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19182 THUMB_VARIANT, do_##ae, do_##te }
19184 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19185 a T_MNEM_xyz enumerator. */
19186 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19187 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19188 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19189 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19191 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19192 infix after the third character. */
19193 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19194 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19195 THUMB_VARIANT, do_##ae, do_##te }
19196 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19197 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19198 THUMB_VARIANT, do_##ae, do_##te }
19199 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19200 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19201 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19202 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19203 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19204 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19205 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19206 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19208 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19209 field is still 0xE. Many of the Thumb variants can be executed
19210 conditionally, so this is checked separately. */
19211 #define TUE(mnem, op, top, nops, ops, ae, te) \
19212 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19213 THUMB_VARIANT, do_##ae, do_##te }
19215 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19216 Used by mnemonics that have very minimal differences in the encoding for
19217 ARM and Thumb variants and can be handled in a common function. */
19218 #define TUEc(mnem, op, top, nops, ops, en) \
19219 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19220 THUMB_VARIANT, do_##en, do_##en }
19222 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19223 condition code field. */
19224 #define TUF(mnem, op, top, nops, ops, ae, te) \
19225 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19226 THUMB_VARIANT, do_##ae, do_##te }
19228 /* ARM-only variants of all the above. */
19229 #define CE(mnem, op, nops, ops, ae) \
19230 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19232 #define C3(mnem, op, nops, ops, ae) \
19233 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19235 /* Legacy mnemonics that always have conditional infix after the third
19237 #define CL(mnem, op, nops, ops, ae) \
19238 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19239 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19241 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19242 #define cCE(mnem, op, nops, ops, ae) \
19243 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19245 /* Legacy coprocessor instructions where conditional infix and conditional
19246 suffix are ambiguous. For consistency this includes all FPA instructions,
19247 not just the potentially ambiguous ones. */
19248 #define cCL(mnem, op, nops, ops, ae) \
19249 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19250 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19252 /* Coprocessor, takes either a suffix or a position-3 infix
19253 (for an FPA corner case). */
19254 #define C3E(mnem, op, nops, ops, ae) \
19255 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19256 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19258 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19259 { m1 #m2 m3, OPS##nops ops, \
19260 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19261 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19263 #define CM(m1, m2, op, nops, ops, ae) \
19264 xCM_ (m1, , m2, op, nops, ops, ae), \
19265 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19266 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19267 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19268 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19269 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19270 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19271 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19272 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19273 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19274 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19275 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19276 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19277 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19278 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19279 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19280 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19281 xCM_ (m1, le, m2, op, nops, ops, ae), \
19282 xCM_ (m1, al, m2, op, nops, ops, ae)
19284 #define UE(mnem, op, nops, ops, ae) \
19285 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19287 #define UF(mnem, op, nops, ops, ae) \
19288 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19290 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19291 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19292 use the same encoding function for each. */
19293 #define NUF(mnem, op, nops, ops, enc) \
19294 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19295 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19297 /* Neon data processing, version which indirects through neon_enc_tab for
19298 the various overloaded versions of opcodes. */
19299 #define nUF(mnem, op, nops, ops, enc) \
19300 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19301 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19303 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19305 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19306 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19307 THUMB_VARIANT, do_##enc, do_##enc }
19309 #define NCE(mnem, op, nops, ops, enc) \
19310 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19312 #define NCEF(mnem, op, nops, ops, enc) \
19313 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19315 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19316 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19317 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19318 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19320 #define nCE(mnem, op, nops, ops, enc) \
19321 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19323 #define nCEF(mnem, op, nops, ops, enc) \
19324 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19328 static const struct asm_opcode insns
[] =
19330 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19331 #define THUMB_VARIANT & arm_ext_v4t
19332 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19333 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19334 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19335 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19336 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19337 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19338 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19339 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19340 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19341 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19342 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19343 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19344 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19345 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19346 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19347 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19349 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19350 for setting PSR flag bits. They are obsolete in V6 and do not
19351 have Thumb equivalents. */
19352 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19353 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19354 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19355 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19356 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19357 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19358 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19359 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19360 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19362 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19363 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19364 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19365 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19367 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19368 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19369 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19371 OP_ADDRGLDR
),ldst
, t_ldst
),
19372 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19374 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19375 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19376 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19377 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19378 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19379 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19381 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19382 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19385 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19386 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19387 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19388 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19390 /* Thumb-compatibility pseudo ops. */
19391 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19392 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19393 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19394 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19395 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19396 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19397 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19398 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19399 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19400 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19401 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19402 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19404 /* These may simplify to neg. */
19405 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19406 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19408 #undef THUMB_VARIANT
19409 #define THUMB_VARIANT & arm_ext_os
19411 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19412 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19414 #undef THUMB_VARIANT
19415 #define THUMB_VARIANT & arm_ext_v6
19417 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19419 /* V1 instructions with no Thumb analogue prior to V6T2. */
19420 #undef THUMB_VARIANT
19421 #define THUMB_VARIANT & arm_ext_v6t2
19423 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19424 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19425 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19427 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19428 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19429 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19430 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19432 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19433 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19435 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19436 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19438 /* V1 instructions with no Thumb analogue at all. */
19439 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19440 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19442 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19443 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19444 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19445 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19446 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19447 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19448 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19449 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19452 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19453 #undef THUMB_VARIANT
19454 #define THUMB_VARIANT & arm_ext_v4t
19456 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19457 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19459 #undef THUMB_VARIANT
19460 #define THUMB_VARIANT & arm_ext_v6t2
19462 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19463 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19465 /* Generic coprocessor instructions. */
19466 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19467 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19468 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19469 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19470 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19471 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19472 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19475 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19477 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19478 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19481 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19482 #undef THUMB_VARIANT
19483 #define THUMB_VARIANT & arm_ext_msr
19485 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19486 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19489 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19490 #undef THUMB_VARIANT
19491 #define THUMB_VARIANT & arm_ext_v6t2
19493 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19494 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19495 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19496 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19497 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19498 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19499 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19500 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19503 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19504 #undef THUMB_VARIANT
19505 #define THUMB_VARIANT & arm_ext_v4t
19507 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19508 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19509 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19510 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19511 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19512 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19515 #define ARM_VARIANT & arm_ext_v4t_5
19517 /* ARM Architecture 4T. */
19518 /* Note: bx (and blx) are required on V5, even if the processor does
19519 not support Thumb. */
19520 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19523 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19524 #undef THUMB_VARIANT
19525 #define THUMB_VARIANT & arm_ext_v5t
19527 /* Note: blx has 2 variants; the .value coded here is for
19528 BLX(2). Only this variant has conditional execution. */
19529 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19530 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19532 #undef THUMB_VARIANT
19533 #define THUMB_VARIANT & arm_ext_v6t2
19535 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19536 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19537 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19538 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19539 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19540 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19541 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19542 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19545 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19546 #undef THUMB_VARIANT
19547 #define THUMB_VARIANT & arm_ext_v5exp
19549 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19550 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19551 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19552 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19554 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19555 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19557 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19558 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19559 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19560 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19562 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19563 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19564 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19565 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19567 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19568 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19570 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19571 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19572 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19573 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19576 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19577 #undef THUMB_VARIANT
19578 #define THUMB_VARIANT & arm_ext_v6t2
19580 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19581 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19583 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19584 ADDRGLDRS
), ldrd
, t_ldstd
),
19586 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19587 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19590 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19592 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19595 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19596 #undef THUMB_VARIANT
19597 #define THUMB_VARIANT & arm_ext_v6
19599 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19600 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19601 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19602 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19603 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19604 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19605 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19606 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19607 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19608 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19610 #undef THUMB_VARIANT
19611 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19613 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19614 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19616 #undef THUMB_VARIANT
19617 #define THUMB_VARIANT & arm_ext_v6t2
19619 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19620 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19622 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19623 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19625 /* ARM V6 not included in V7M. */
19626 #undef THUMB_VARIANT
19627 #define THUMB_VARIANT & arm_ext_v6_notm
19628 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19629 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19630 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19631 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19632 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19633 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19634 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19635 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19636 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19637 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19638 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19639 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19640 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19641 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19642 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19643 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19644 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19645 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19646 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19648 /* ARM V6 not included in V7M (eg. integer SIMD). */
19649 #undef THUMB_VARIANT
19650 #define THUMB_VARIANT & arm_ext_v6_dsp
19651 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19652 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19653 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19654 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19655 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19656 /* Old name for QASX. */
19657 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19658 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19659 /* Old name for QSAX. */
19660 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19661 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19662 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19663 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19664 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19665 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19666 /* Old name for SASX. */
19667 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19668 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19669 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19670 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19671 /* Old name for SHASX. */
19672 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19673 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19674 /* Old name for SHSAX. */
19675 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19676 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19677 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19678 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19679 /* Old name for SSAX. */
19680 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19681 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19682 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19683 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19684 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19685 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19686 /* Old name for UASX. */
19687 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19688 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19689 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19690 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19691 /* Old name for UHASX. */
19692 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19693 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19694 /* Old name for UHSAX. */
19695 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19696 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19697 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19698 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19699 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19700 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19701 /* Old name for UQASX. */
19702 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19703 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19704 /* Old name for UQSAX. */
19705 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19706 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19707 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19708 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19709 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19710 /* Old name for USAX. */
19711 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19712 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19713 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19714 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19715 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19716 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19717 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19718 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19719 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19720 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19721 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19722 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19723 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19724 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19725 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19726 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19727 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19728 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19729 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19730 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19731 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19732 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19733 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19734 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19735 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19736 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19737 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19738 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19739 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19740 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19741 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19742 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19743 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19744 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19747 #define ARM_VARIANT & arm_ext_v6k
19748 #undef THUMB_VARIANT
19749 #define THUMB_VARIANT & arm_ext_v6k
19751 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19752 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19753 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19754 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19756 #undef THUMB_VARIANT
19757 #define THUMB_VARIANT & arm_ext_v6_notm
19758 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19760 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19761 RRnpcb
), strexd
, t_strexd
),
19763 #undef THUMB_VARIANT
19764 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19765 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19767 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19769 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19771 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19773 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19776 #define ARM_VARIANT & arm_ext_sec
19777 #undef THUMB_VARIANT
19778 #define THUMB_VARIANT & arm_ext_sec
19780 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19783 #define ARM_VARIANT & arm_ext_virt
19784 #undef THUMB_VARIANT
19785 #define THUMB_VARIANT & arm_ext_virt
19787 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19788 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19791 #define ARM_VARIANT & arm_ext_pan
19792 #undef THUMB_VARIANT
19793 #define THUMB_VARIANT & arm_ext_pan
19795 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19798 #define ARM_VARIANT & arm_ext_v6t2
19799 #undef THUMB_VARIANT
19800 #define THUMB_VARIANT & arm_ext_v6t2
19802 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19803 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19804 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19805 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19807 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19808 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19810 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19811 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19812 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19813 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19815 #undef THUMB_VARIANT
19816 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19817 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19818 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19820 /* Thumb-only instructions. */
19822 #define ARM_VARIANT NULL
19823 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19824 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19826 /* ARM does not really have an IT instruction, so always allow it.
19827 The opcode is copied from Thumb in order to allow warnings in
19828 -mimplicit-it=[never | arm] modes. */
19830 #define ARM_VARIANT & arm_ext_v1
19831 #undef THUMB_VARIANT
19832 #define THUMB_VARIANT & arm_ext_v6t2
19834 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19835 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19836 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19837 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19838 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19839 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19840 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19841 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19842 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19843 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19844 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19845 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19846 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19847 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19848 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19849 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19850 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19851 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19853 /* Thumb2 only instructions. */
19855 #define ARM_VARIANT NULL
19857 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19858 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19859 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19860 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19861 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19862 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19864 /* Hardware division instructions. */
19866 #define ARM_VARIANT & arm_ext_adiv
19867 #undef THUMB_VARIANT
19868 #define THUMB_VARIANT & arm_ext_div
19870 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19871 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19873 /* ARM V6M/V7 instructions. */
19875 #define ARM_VARIANT & arm_ext_barrier
19876 #undef THUMB_VARIANT
19877 #define THUMB_VARIANT & arm_ext_barrier
19879 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19880 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19881 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19883 /* ARM V7 instructions. */
19885 #define ARM_VARIANT & arm_ext_v7
19886 #undef THUMB_VARIANT
19887 #define THUMB_VARIANT & arm_ext_v7
19889 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19890 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19893 #define ARM_VARIANT & arm_ext_mp
19894 #undef THUMB_VARIANT
19895 #define THUMB_VARIANT & arm_ext_mp
19897 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19899 /* AArchv8 instructions. */
19901 #define ARM_VARIANT & arm_ext_v8
19903 /* Instructions shared between armv8-a and armv8-m. */
19904 #undef THUMB_VARIANT
19905 #define THUMB_VARIANT & arm_ext_atomics
19907 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19908 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19909 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19910 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19911 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19912 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19913 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19914 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19915 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19916 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19918 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19920 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19922 #undef THUMB_VARIANT
19923 #define THUMB_VARIANT & arm_ext_v8
19925 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19926 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19927 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19929 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19931 /* ARMv8 T32 only. */
19933 #define ARM_VARIANT NULL
19934 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19935 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19936 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19938 /* FP for ARMv8. */
19940 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19941 #undef THUMB_VARIANT
19942 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19944 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19945 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19946 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19947 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19948 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19949 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19950 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19951 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19952 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19953 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19954 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19955 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19956 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19957 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19958 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19959 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19960 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19962 /* Crypto v1 extensions. */
19964 #define ARM_VARIANT & fpu_crypto_ext_armv8
19965 #undef THUMB_VARIANT
19966 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19968 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19969 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19970 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19971 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19972 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19973 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19974 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19975 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19976 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19977 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19978 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19979 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19980 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19981 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19984 #define ARM_VARIANT & crc_ext_armv8
19985 #undef THUMB_VARIANT
19986 #define THUMB_VARIANT & crc_ext_armv8
19987 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19988 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19989 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19990 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19991 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19992 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19994 /* ARMv8.2 RAS extension. */
19996 #define ARM_VARIANT & arm_ext_ras
19997 #undef THUMB_VARIANT
19998 #define THUMB_VARIANT & arm_ext_ras
19999 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
20002 #define ARM_VARIANT & arm_ext_v8_3
20003 #undef THUMB_VARIANT
20004 #define THUMB_VARIANT & arm_ext_v8_3
20005 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
20006 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
20007 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
20010 #define ARM_VARIANT & fpu_neon_ext_dotprod
20011 #undef THUMB_VARIANT
20012 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20013 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20014 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20017 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20018 #undef THUMB_VARIANT
20019 #define THUMB_VARIANT NULL
20021 cCE("wfs", e200110
, 1, (RR
), rd
),
20022 cCE("rfs", e300110
, 1, (RR
), rd
),
20023 cCE("wfc", e400110
, 1, (RR
), rd
),
20024 cCE("rfc", e500110
, 1, (RR
), rd
),
20026 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20027 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20028 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20029 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20031 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20032 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20033 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20034 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20036 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20037 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20038 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20039 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20040 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20041 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20042 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20043 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20044 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20045 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20046 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20047 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20049 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20050 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20051 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20052 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20053 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20054 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20055 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20056 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20057 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20058 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20059 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20060 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20062 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20063 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20064 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20065 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20066 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20067 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20068 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20069 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20070 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20071 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20072 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20073 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20075 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20076 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20077 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20078 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20079 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20080 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20081 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20082 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20083 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20084 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20085 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20086 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20088 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20089 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20090 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20091 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20092 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20093 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20094 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20095 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20096 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20097 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20098 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20099 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20101 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20102 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20103 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20104 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20105 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20106 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20107 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20108 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20109 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20110 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20111 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20112 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20114 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20115 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20116 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20117 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20118 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20119 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20120 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20121 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20122 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20123 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20124 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20125 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20127 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20128 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20129 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20130 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20131 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20132 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20133 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20134 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20135 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20136 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20137 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20138 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20140 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20141 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20142 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20143 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20144 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20145 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20146 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20147 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20148 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20149 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20150 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20151 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20153 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20154 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20155 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20156 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20157 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20158 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20159 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20160 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20161 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20162 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20163 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20164 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20166 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20167 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20168 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20169 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20170 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20171 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20172 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20173 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20174 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20175 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20176 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20177 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20179 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20180 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20181 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20182 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20183 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20184 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20185 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20186 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20187 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20188 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20189 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20190 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20192 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20193 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20194 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20195 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20196 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20197 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20198 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20199 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20200 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20201 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20202 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20203 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20205 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20206 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20207 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20208 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20209 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20210 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20211 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20212 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20213 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20214 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20215 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20216 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20218 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20219 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20220 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20221 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20222 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20223 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20224 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20225 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20226 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20227 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20228 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20229 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20231 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20232 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20233 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20234 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20235 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20236 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20237 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20238 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20239 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20240 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20241 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20242 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20244 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20245 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20246 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20247 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20248 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20249 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20250 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20251 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20252 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20253 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20254 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20255 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20257 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20258 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20259 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20260 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20261 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20262 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20263 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20264 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20265 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20266 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20267 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20268 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20270 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20271 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20272 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20273 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20274 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20275 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20276 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20277 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20278 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20279 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20280 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20281 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20283 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20284 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20285 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20286 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20287 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20288 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20289 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20290 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20291 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20292 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20293 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20294 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20296 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20297 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20298 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20299 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20300 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20301 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20302 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20303 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20304 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20305 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20306 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20307 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20309 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20310 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20311 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20312 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20313 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20314 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20315 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20316 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20317 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20318 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20319 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20320 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20322 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20323 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20324 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20325 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20326 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20327 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20328 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20329 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20330 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20331 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20332 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20333 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20335 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20336 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20337 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20338 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20339 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20340 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20341 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20342 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20343 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20344 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20345 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20346 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20348 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20349 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20350 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20351 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20352 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20353 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20354 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20355 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20356 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20357 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20358 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20359 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20361 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20362 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20363 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20364 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20365 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20366 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20367 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20368 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20369 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20370 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20371 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20372 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20374 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20375 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20376 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20377 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20378 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20379 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20380 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20381 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20382 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20383 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20384 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20385 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20387 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20388 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20389 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20390 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20391 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20392 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20393 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20394 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20395 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20396 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20397 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20398 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20400 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20401 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20402 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20403 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20404 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20405 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20406 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20407 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20408 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20409 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20410 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20411 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20413 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20414 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20415 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20416 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20418 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20419 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20420 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20421 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20422 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20423 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20424 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20425 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20426 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20427 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20428 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20429 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20431 /* The implementation of the FIX instruction is broken on some
20432 assemblers, in that it accepts a precision specifier as well as a
20433 rounding specifier, despite the fact that this is meaningless.
20434 To be more compatible, we accept it as well, though of course it
20435 does not set any bits. */
20436 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20437 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20438 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20439 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20440 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20441 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20442 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20443 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20444 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20445 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20446 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20447 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20448 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20450 /* Instructions that were new with the real FPA, call them V2. */
20452 #define ARM_VARIANT & fpu_fpa_ext_v2
20454 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20455 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20456 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20457 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20458 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20459 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20462 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20464 /* Moves and type conversions. */
20465 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20466 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20467 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20468 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20469 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20470 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20471 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20472 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20473 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20474 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20475 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20476 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20477 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20478 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20480 /* Memory operations. */
20481 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20482 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20483 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20484 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20485 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20486 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20487 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20488 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20489 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20490 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20491 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20492 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20493 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20494 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20495 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20496 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20497 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20498 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20500 /* Monadic operations. */
20501 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20502 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20503 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20505 /* Dyadic operations. */
20506 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20507 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20508 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20509 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20510 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20511 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20512 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20513 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20514 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20517 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20518 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20519 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20520 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20522 /* Double precision load/store are still present on single precision
20523 implementations. */
20524 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20525 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20526 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20527 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20528 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20529 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20530 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20531 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20532 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20533 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20536 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20538 /* Moves and type conversions. */
20539 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20540 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20541 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20542 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20543 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20544 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20545 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20546 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20547 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20548 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20549 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20550 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20551 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20553 /* Monadic operations. */
20554 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20555 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20556 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20558 /* Dyadic operations. */
20559 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20560 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20561 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20562 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20563 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20564 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20565 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20566 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20567 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20570 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20571 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20572 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20573 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20576 #define ARM_VARIANT & fpu_vfp_ext_v2
20578 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20579 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20580 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20581 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20583 /* Instructions which may belong to either the Neon or VFP instruction sets.
20584 Individual encoder functions perform additional architecture checks. */
20586 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20587 #undef THUMB_VARIANT
20588 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20590 /* These mnemonics are unique to VFP. */
20591 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20592 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20593 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20594 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20595 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20596 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20597 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20598 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20599 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20600 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20602 /* Mnemonics shared by Neon and VFP. */
20603 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20604 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20605 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20607 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20608 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20610 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20611 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20613 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20614 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20615 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20616 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20617 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20618 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20619 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20620 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20622 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20623 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20624 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20625 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20628 /* NOTE: All VMOV encoding is special-cased! */
20629 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20630 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20633 #define ARM_VARIANT & arm_ext_fp16
20634 #undef THUMB_VARIANT
20635 #define THUMB_VARIANT & arm_ext_fp16
20636 /* New instructions added from v8.2, allowing the extraction and insertion of
20637 the upper 16 bits of a 32-bit vector register. */
20638 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20639 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20641 #undef THUMB_VARIANT
20642 #define THUMB_VARIANT & fpu_neon_ext_v1
20644 #define ARM_VARIANT & fpu_neon_ext_v1
20646 /* Data processing with three registers of the same length. */
20647 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20648 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20649 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20650 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20651 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20652 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20653 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20654 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20655 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20656 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20657 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20658 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20659 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20660 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20661 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20662 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20663 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20664 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20665 /* If not immediate, fall back to neon_dyadic_i64_su.
20666 shl_imm should accept I8 I16 I32 I64,
20667 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20668 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20669 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20670 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20671 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20672 /* Logic ops, types optional & ignored. */
20673 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20674 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20675 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20676 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20677 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20678 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20679 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20680 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20681 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20682 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20683 /* Bitfield ops, untyped. */
20684 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20685 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20686 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20687 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20688 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20689 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20690 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20691 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20692 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20693 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20694 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20695 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20696 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20697 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20698 back to neon_dyadic_if_su. */
20699 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20700 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20701 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20702 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20703 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20704 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20705 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20706 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20707 /* Comparison. Type I8 I16 I32 F32. */
20708 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20709 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20710 /* As above, D registers only. */
20711 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20712 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20713 /* Int and float variants, signedness unimportant. */
20714 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20715 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20716 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20717 /* Add/sub take types I8 I16 I32 I64 F32. */
20718 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20719 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20720 /* vtst takes sizes 8, 16, 32. */
20721 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20722 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20723 /* VMUL takes I8 I16 I32 F32 P8. */
20724 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20725 /* VQD{R}MULH takes S16 S32. */
20726 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20727 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20728 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20729 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20730 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20731 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20732 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20733 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20734 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20735 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20736 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20737 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20738 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20739 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20740 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20741 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20742 /* ARM v8.1 extension. */
20743 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20744 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20745 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20746 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20748 /* Two address, int/float. Types S8 S16 S32 F32. */
20749 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20750 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20752 /* Data processing with two registers and a shift amount. */
20753 /* Right shifts, and variants with rounding.
20754 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20755 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20756 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20757 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20758 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20759 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20760 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20761 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20762 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20763 /* Shift and insert. Sizes accepted 8 16 32 64. */
20764 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20765 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20766 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20767 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20768 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20769 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20770 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20771 /* Right shift immediate, saturating & narrowing, with rounding variants.
20772 Types accepted S16 S32 S64 U16 U32 U64. */
20773 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20774 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20775 /* As above, unsigned. Types accepted S16 S32 S64. */
20776 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20777 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20778 /* Right shift narrowing. Types accepted I16 I32 I64. */
20779 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20780 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20781 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20782 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20783 /* CVT with optional immediate for fixed-point variant. */
20784 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20786 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20787 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20789 /* Data processing, three registers of different lengths. */
20790 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20791 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20792 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20793 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20794 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20795 /* If not scalar, fall back to neon_dyadic_long.
20796 Vector types as above, scalar types S16 S32 U16 U32. */
20797 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20798 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20799 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20800 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20801 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20802 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20803 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20804 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20805 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20806 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20807 /* Saturating doubling multiplies. Types S16 S32. */
20808 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20809 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20810 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20811 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20812 S16 S32 U16 U32. */
20813 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20815 /* Extract. Size 8. */
20816 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20817 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20819 /* Two registers, miscellaneous. */
20820 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20821 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20822 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20823 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20824 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20825 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20826 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20827 /* Vector replicate. Sizes 8 16 32. */
20828 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20829 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20830 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20831 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20832 /* VMOVN. Types I16 I32 I64. */
20833 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20834 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20835 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20836 /* VQMOVUN. Types S16 S32 S64. */
20837 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20838 /* VZIP / VUZP. Sizes 8 16 32. */
20839 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20840 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20841 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20842 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20843 /* VQABS / VQNEG. Types S8 S16 S32. */
20844 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20845 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20846 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20847 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20848 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20849 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20850 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20851 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20852 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20853 /* Reciprocal estimates. Types U32 F16 F32. */
20854 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20855 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20856 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20857 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20858 /* VCLS. Types S8 S16 S32. */
20859 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20860 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20861 /* VCLZ. Types I8 I16 I32. */
20862 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20863 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20864 /* VCNT. Size 8. */
20865 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20866 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20867 /* Two address, untyped. */
20868 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20869 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20870 /* VTRN. Sizes 8 16 32. */
20871 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20872 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20874 /* Table lookup. Size 8. */
20875 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20876 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20878 #undef THUMB_VARIANT
20879 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20881 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20883 /* Neon element/structure load/store. */
20884 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20885 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20886 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20887 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20888 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20889 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20890 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20891 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20893 #undef THUMB_VARIANT
20894 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20896 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20897 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20898 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20899 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20900 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20901 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20902 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20903 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20904 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20905 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20907 #undef THUMB_VARIANT
20908 #define THUMB_VARIANT & fpu_vfp_ext_v3
20910 #define ARM_VARIANT & fpu_vfp_ext_v3
20912 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20913 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20914 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20915 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20916 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20917 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20918 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20919 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20920 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20923 #define ARM_VARIANT & fpu_vfp_ext_fma
20924 #undef THUMB_VARIANT
20925 #define THUMB_VARIANT & fpu_vfp_ext_fma
20926 /* Mnemonics shared by Neon and VFP. These are included in the
20927 VFP FMA variant; NEON and VFP FMA always includes the NEON
20928 FMA instructions. */
20929 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20930 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20931 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20932 the v form should always be used. */
20933 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20934 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20935 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20936 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20937 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20938 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20940 #undef THUMB_VARIANT
20942 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20944 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20945 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20946 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20947 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20948 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20949 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20950 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20951 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20954 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20956 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20957 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20958 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20959 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20960 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20961 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20962 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20963 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20964 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20965 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20966 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20967 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20968 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20969 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20970 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20971 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20972 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20973 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20974 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20975 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20976 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20977 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20978 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20979 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20980 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20981 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20982 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20983 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20984 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20985 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20986 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20987 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20988 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20989 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20990 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20991 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20992 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20993 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20994 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20995 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20996 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20997 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20998 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20999 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21000 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21001 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21002 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
21003 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21004 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21005 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21006 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21007 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21008 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21009 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21010 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21011 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21012 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21013 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21014 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21015 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21016 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21017 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21018 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21019 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21020 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21021 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21022 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21023 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21024 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21025 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21026 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21027 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21028 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21029 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21030 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21031 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21032 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21033 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21034 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21035 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21036 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21037 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21038 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21039 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21040 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21041 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21042 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21043 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21044 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21045 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21046 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21047 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21048 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21049 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21050 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21051 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21052 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21053 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21054 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21055 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21056 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21057 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21058 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21059 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21060 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21061 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21062 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21063 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21064 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21065 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21066 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21067 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21068 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21069 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21070 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21071 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21072 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21073 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21074 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21075 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21076 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21077 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21078 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21079 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21080 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21081 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21082 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21083 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21084 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21085 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21086 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21087 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21088 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21089 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21090 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21091 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21092 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21093 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21094 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21095 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21096 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21097 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21098 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21099 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21100 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21101 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21102 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21103 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21104 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21105 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21106 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21107 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21108 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21109 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21110 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21111 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21112 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21113 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21114 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21115 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21116 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21117 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21120 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21122 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21123 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21124 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21125 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21126 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21127 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21128 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21129 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21130 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21131 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21132 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21133 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21134 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21135 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21136 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21137 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21138 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21139 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21140 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21141 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21142 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21143 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21144 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21145 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21146 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21147 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21148 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21149 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21150 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21151 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21152 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21153 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21154 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21155 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21156 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21157 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21158 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21159 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21160 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21161 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21162 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21163 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21164 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21165 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21166 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21167 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21168 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21169 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21170 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21171 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21172 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21173 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21174 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21175 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21176 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21177 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21178 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21181 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21183 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21184 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21185 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21186 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21187 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21188 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21189 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21190 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21191 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21192 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21193 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21194 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21195 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21196 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21197 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21198 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21199 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21200 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21201 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21202 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21203 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21204 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21205 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21206 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21207 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21208 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21209 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21210 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21211 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21212 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21213 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21214 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21215 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21216 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21217 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21218 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21219 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21220 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21221 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21222 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21223 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21224 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21225 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21226 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21227 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21228 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21229 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21230 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21231 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21232 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21233 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21234 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21235 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21236 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21237 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21238 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21239 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21240 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21241 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21242 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21243 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21244 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21245 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21246 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21247 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21248 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21249 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21250 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21251 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21252 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21253 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21254 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21255 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21256 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21257 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21258 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21260 /* ARMv8-M instructions. */
21262 #define ARM_VARIANT NULL
21263 #undef THUMB_VARIANT
21264 #define THUMB_VARIANT & arm_ext_v8m
21265 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21266 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21267 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21268 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21269 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21270 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21271 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21273 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21274 instructions behave as nop if no VFP is present. */
21275 #undef THUMB_VARIANT
21276 #define THUMB_VARIANT & arm_ext_v8m_main
21277 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21278 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21281 #undef THUMB_VARIANT
21307 /* MD interface: bits in the object file. */
21309 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21310 for use in the a.out file, and stores them in the array pointed to by buf.
21311 This knows about the endian-ness of the target machine and does
21312 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21313 2 (short) and 4 (long) Floating numbers are put out as a series of
21314 LITTLENUMS (shorts, here at least). */
21317 md_number_to_chars (char * buf
, valueT val
, int n
)
21319 if (target_big_endian
)
21320 number_to_chars_bigendian (buf
, val
, n
);
21322 number_to_chars_littleendian (buf
, val
, n
);
21326 md_chars_to_number (char * buf
, int n
)
21329 unsigned char * where
= (unsigned char *) buf
;
21331 if (target_big_endian
)
21336 result
|= (*where
++ & 255);
21344 result
|= (where
[n
] & 255);
21351 /* MD interface: Sections. */
21353 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21354 that an rs_machine_dependent frag may reach. */
21357 arm_frag_max_var (fragS
*fragp
)
21359 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21360 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21362 Note that we generate relaxable instructions even for cases that don't
21363 really need it, like an immediate that's a trivial constant. So we're
21364 overestimating the instruction size for some of those cases. Rather
21365 than putting more intelligence here, it would probably be better to
21366 avoid generating a relaxation frag in the first place when it can be
21367 determined up front that a short instruction will suffice. */
21369 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21373 /* Estimate the size of a frag before relaxing. Assume everything fits in
21377 md_estimate_size_before_relax (fragS
* fragp
,
21378 segT segtype ATTRIBUTE_UNUSED
)
21384 /* Convert a machine dependent frag. */
21387 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21389 unsigned long insn
;
21390 unsigned long old_op
;
21398 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21400 old_op
= bfd_get_16(abfd
, buf
);
21401 if (fragp
->fr_symbol
)
21403 exp
.X_op
= O_symbol
;
21404 exp
.X_add_symbol
= fragp
->fr_symbol
;
21408 exp
.X_op
= O_constant
;
21410 exp
.X_add_number
= fragp
->fr_offset
;
21411 opcode
= fragp
->fr_subtype
;
21414 case T_MNEM_ldr_pc
:
21415 case T_MNEM_ldr_pc2
:
21416 case T_MNEM_ldr_sp
:
21417 case T_MNEM_str_sp
:
21424 if (fragp
->fr_var
== 4)
21426 insn
= THUMB_OP32 (opcode
);
21427 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21429 insn
|= (old_op
& 0x700) << 4;
21433 insn
|= (old_op
& 7) << 12;
21434 insn
|= (old_op
& 0x38) << 13;
21436 insn
|= 0x00000c00;
21437 put_thumb32_insn (buf
, insn
);
21438 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21442 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21444 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21447 if (fragp
->fr_var
== 4)
21449 insn
= THUMB_OP32 (opcode
);
21450 insn
|= (old_op
& 0xf0) << 4;
21451 put_thumb32_insn (buf
, insn
);
21452 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21456 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21457 exp
.X_add_number
-= 4;
21465 if (fragp
->fr_var
== 4)
21467 int r0off
= (opcode
== T_MNEM_mov
21468 || opcode
== T_MNEM_movs
) ? 0 : 8;
21469 insn
= THUMB_OP32 (opcode
);
21470 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21471 insn
|= (old_op
& 0x700) << r0off
;
21472 put_thumb32_insn (buf
, insn
);
21473 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21477 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21482 if (fragp
->fr_var
== 4)
21484 insn
= THUMB_OP32(opcode
);
21485 put_thumb32_insn (buf
, insn
);
21486 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21489 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21493 if (fragp
->fr_var
== 4)
21495 insn
= THUMB_OP32(opcode
);
21496 insn
|= (old_op
& 0xf00) << 14;
21497 put_thumb32_insn (buf
, insn
);
21498 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21501 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21504 case T_MNEM_add_sp
:
21505 case T_MNEM_add_pc
:
21506 case T_MNEM_inc_sp
:
21507 case T_MNEM_dec_sp
:
21508 if (fragp
->fr_var
== 4)
21510 /* ??? Choose between add and addw. */
21511 insn
= THUMB_OP32 (opcode
);
21512 insn
|= (old_op
& 0xf0) << 4;
21513 put_thumb32_insn (buf
, insn
);
21514 if (opcode
== T_MNEM_add_pc
)
21515 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21517 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21520 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21528 if (fragp
->fr_var
== 4)
21530 insn
= THUMB_OP32 (opcode
);
21531 insn
|= (old_op
& 0xf0) << 4;
21532 insn
|= (old_op
& 0xf) << 16;
21533 put_thumb32_insn (buf
, insn
);
21534 if (insn
& (1 << 20))
21535 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21537 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21540 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21546 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21547 (enum bfd_reloc_code_real
) reloc_type
);
21548 fixp
->fx_file
= fragp
->fr_file
;
21549 fixp
->fx_line
= fragp
->fr_line
;
21550 fragp
->fr_fix
+= fragp
->fr_var
;
21552 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21553 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21554 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21555 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21558 /* Return the size of a relaxable immediate operand instruction.
21559 SHIFT and SIZE specify the form of the allowable immediate. */
21561 relax_immediate (fragS
*fragp
, int size
, int shift
)
21567 /* ??? Should be able to do better than this. */
21568 if (fragp
->fr_symbol
)
21571 low
= (1 << shift
) - 1;
21572 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21573 offset
= fragp
->fr_offset
;
21574 /* Force misaligned offsets to 32-bit variant. */
21577 if (offset
& ~mask
)
21582 /* Get the address of a symbol during relaxation. */
21584 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21590 sym
= fragp
->fr_symbol
;
21591 sym_frag
= symbol_get_frag (sym
);
21592 know (S_GET_SEGMENT (sym
) != absolute_section
21593 || sym_frag
== &zero_address_frag
);
21594 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21596 /* If frag has yet to be reached on this pass, assume it will
21597 move by STRETCH just as we did. If this is not so, it will
21598 be because some frag between grows, and that will force
21602 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21606 /* Adjust stretch for any alignment frag. Note that if have
21607 been expanding the earlier code, the symbol may be
21608 defined in what appears to be an earlier frag. FIXME:
21609 This doesn't handle the fr_subtype field, which specifies
21610 a maximum number of bytes to skip when doing an
21612 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21614 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21617 stretch
= - ((- stretch
)
21618 & ~ ((1 << (int) f
->fr_offset
) - 1));
21620 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21632 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21635 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21640 /* Assume worst case for symbols not known to be in the same section. */
21641 if (fragp
->fr_symbol
== NULL
21642 || !S_IS_DEFINED (fragp
->fr_symbol
)
21643 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21644 || S_IS_WEAK (fragp
->fr_symbol
))
21647 val
= relaxed_symbol_addr (fragp
, stretch
);
21648 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21649 addr
= (addr
+ 4) & ~3;
21650 /* Force misaligned targets to 32-bit variant. */
21654 if (val
< 0 || val
> 1020)
21659 /* Return the size of a relaxable add/sub immediate instruction. */
21661 relax_addsub (fragS
*fragp
, asection
*sec
)
21666 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21667 op
= bfd_get_16(sec
->owner
, buf
);
21668 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21669 return relax_immediate (fragp
, 8, 0);
21671 return relax_immediate (fragp
, 3, 0);
21674 /* Return TRUE iff the definition of symbol S could be pre-empted
21675 (overridden) at link or load time. */
21677 symbol_preemptible (symbolS
*s
)
21679 /* Weak symbols can always be pre-empted. */
21683 /* Non-global symbols cannot be pre-empted. */
21684 if (! S_IS_EXTERNAL (s
))
21688 /* In ELF, a global symbol can be marked protected, or private. In that
21689 case it can't be pre-empted (other definitions in the same link unit
21690 would violate the ODR). */
21691 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21695 /* Other global symbols might be pre-empted. */
21699 /* Return the size of a relaxable branch instruction. BITS is the
21700 size of the offset field in the narrow instruction. */
21703 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21709 /* Assume worst case for symbols not known to be in the same section. */
21710 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21711 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21712 || S_IS_WEAK (fragp
->fr_symbol
))
21716 /* A branch to a function in ARM state will require interworking. */
21717 if (S_IS_DEFINED (fragp
->fr_symbol
)
21718 && ARM_IS_FUNC (fragp
->fr_symbol
))
21722 if (symbol_preemptible (fragp
->fr_symbol
))
21725 val
= relaxed_symbol_addr (fragp
, stretch
);
21726 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21729 /* Offset is a signed value *2 */
21731 if (val
>= limit
|| val
< -limit
)
21737 /* Relax a machine dependent frag. This returns the amount by which
21738 the current size of the frag should change. */
21741 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21746 oldsize
= fragp
->fr_var
;
21747 switch (fragp
->fr_subtype
)
21749 case T_MNEM_ldr_pc2
:
21750 newsize
= relax_adr (fragp
, sec
, stretch
);
21752 case T_MNEM_ldr_pc
:
21753 case T_MNEM_ldr_sp
:
21754 case T_MNEM_str_sp
:
21755 newsize
= relax_immediate (fragp
, 8, 2);
21759 newsize
= relax_immediate (fragp
, 5, 2);
21763 newsize
= relax_immediate (fragp
, 5, 1);
21767 newsize
= relax_immediate (fragp
, 5, 0);
21770 newsize
= relax_adr (fragp
, sec
, stretch
);
21776 newsize
= relax_immediate (fragp
, 8, 0);
21779 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21782 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21784 case T_MNEM_add_sp
:
21785 case T_MNEM_add_pc
:
21786 newsize
= relax_immediate (fragp
, 8, 2);
21788 case T_MNEM_inc_sp
:
21789 case T_MNEM_dec_sp
:
21790 newsize
= relax_immediate (fragp
, 7, 2);
21796 newsize
= relax_addsub (fragp
, sec
);
21802 fragp
->fr_var
= newsize
;
21803 /* Freeze wide instructions that are at or before the same location as
21804 in the previous pass. This avoids infinite loops.
21805 Don't freeze them unconditionally because targets may be artificially
21806 misaligned by the expansion of preceding frags. */
21807 if (stretch
<= 0 && newsize
> 2)
21809 md_convert_frag (sec
->owner
, sec
, fragp
);
21813 return newsize
- oldsize
;
21816 /* Round up a section size to the appropriate boundary. */
21819 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21822 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21823 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21825 /* For a.out, force the section size to be aligned. If we don't do
21826 this, BFD will align it for us, but it will not write out the
21827 final bytes of the section. This may be a bug in BFD, but it is
21828 easier to fix it here since that is how the other a.out targets
21832 align
= bfd_get_section_alignment (stdoutput
, segment
);
21833 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21840 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21841 of an rs_align_code fragment. */
21844 arm_handle_align (fragS
* fragP
)
21846 static unsigned char const arm_noop
[2][2][4] =
21849 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21850 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21853 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21854 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21857 static unsigned char const thumb_noop
[2][2][2] =
21860 {0xc0, 0x46}, /* LE */
21861 {0x46, 0xc0}, /* BE */
21864 {0x00, 0xbf}, /* LE */
21865 {0xbf, 0x00} /* BE */
21868 static unsigned char const wide_thumb_noop
[2][4] =
21869 { /* Wide Thumb-2 */
21870 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21871 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21874 unsigned bytes
, fix
, noop_size
;
21876 const unsigned char * noop
;
21877 const unsigned char *narrow_noop
= NULL
;
21882 if (fragP
->fr_type
!= rs_align_code
)
21885 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21886 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21889 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21890 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21892 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21894 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21896 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21897 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21899 narrow_noop
= thumb_noop
[1][target_big_endian
];
21900 noop
= wide_thumb_noop
[target_big_endian
];
21903 noop
= thumb_noop
[0][target_big_endian
];
21911 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21912 ? selected_cpu
: arm_arch_none
,
21914 [target_big_endian
];
21921 fragP
->fr_var
= noop_size
;
21923 if (bytes
& (noop_size
- 1))
21925 fix
= bytes
& (noop_size
- 1);
21927 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21929 memset (p
, 0, fix
);
21936 if (bytes
& noop_size
)
21938 /* Insert a narrow noop. */
21939 memcpy (p
, narrow_noop
, noop_size
);
21941 bytes
-= noop_size
;
21945 /* Use wide noops for the remainder */
21949 while (bytes
>= noop_size
)
21951 memcpy (p
, noop
, noop_size
);
21953 bytes
-= noop_size
;
21957 fragP
->fr_fix
+= fix
;
21960 /* Called from md_do_align. Used to create an alignment
21961 frag in a code section. */
21964 arm_frag_align_code (int n
, int max
)
21968 /* We assume that there will never be a requirement
21969 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21970 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21975 _("alignments greater than %d bytes not supported in .text sections."),
21976 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21977 as_fatal ("%s", err_msg
);
21980 p
= frag_var (rs_align_code
,
21981 MAX_MEM_FOR_RS_ALIGN_CODE
,
21983 (relax_substateT
) max
,
21990 /* Perform target specific initialisation of a frag.
21991 Note - despite the name this initialisation is not done when the frag
21992 is created, but only when its type is assigned. A frag can be created
21993 and used a long time before its type is set, so beware of assuming that
21994 this initialisation is performed first. */
21998 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
22000 /* Record whether this frag is in an ARM or a THUMB area. */
22001 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22004 #else /* OBJ_ELF is defined. */
22006 arm_init_frag (fragS
* fragP
, int max_chars
)
22008 bfd_boolean frag_thumb_mode
;
22010 /* If the current ARM vs THUMB mode has not already
22011 been recorded into this frag then do so now. */
22012 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22013 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22015 /* PR 21809: Do not set a mapping state for debug sections
22016 - it just confuses other tools. */
22017 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
22020 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22022 /* Record a mapping symbol for alignment frags. We will delete this
22023 later if the alignment ends up empty. */
22024 switch (fragP
->fr_type
)
22027 case rs_align_test
:
22029 mapping_state_2 (MAP_DATA
, max_chars
);
22031 case rs_align_code
:
22032 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22039 /* When we change sections we need to issue a new mapping symbol. */
22042 arm_elf_change_section (void)
22044 /* Link an unlinked unwind index table section to the .text section. */
22045 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22046 && elf_linked_to_section (now_seg
) == NULL
)
22047 elf_linked_to_section (now_seg
) = text_section
;
22051 arm_elf_section_type (const char * str
, size_t len
)
22053 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22054 return SHT_ARM_EXIDX
;
22059 /* Code to deal with unwinding tables. */
22061 static void add_unwind_adjustsp (offsetT
);
22063 /* Generate any deferred unwind frame offset. */
22066 flush_pending_unwind (void)
22070 offset
= unwind
.pending_offset
;
22071 unwind
.pending_offset
= 0;
22073 add_unwind_adjustsp (offset
);
22076 /* Add an opcode to this list for this function. Two-byte opcodes should
22077 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22081 add_unwind_opcode (valueT op
, int length
)
22083 /* Add any deferred stack adjustment. */
22084 if (unwind
.pending_offset
)
22085 flush_pending_unwind ();
22087 unwind
.sp_restored
= 0;
22089 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22091 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22092 if (unwind
.opcodes
)
22093 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22094 unwind
.opcode_alloc
);
22096 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22101 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22103 unwind
.opcode_count
++;
22107 /* Add unwind opcodes to adjust the stack pointer. */
22110 add_unwind_adjustsp (offsetT offset
)
22114 if (offset
> 0x200)
22116 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22121 /* Long form: 0xb2, uleb128. */
22122 /* This might not fit in a word so add the individual bytes,
22123 remembering the list is built in reverse order. */
22124 o
= (valueT
) ((offset
- 0x204) >> 2);
22126 add_unwind_opcode (0, 1);
22128 /* Calculate the uleb128 encoding of the offset. */
22132 bytes
[n
] = o
& 0x7f;
22138 /* Add the insn. */
22140 add_unwind_opcode (bytes
[n
- 1], 1);
22141 add_unwind_opcode (0xb2, 1);
22143 else if (offset
> 0x100)
22145 /* Two short opcodes. */
22146 add_unwind_opcode (0x3f, 1);
22147 op
= (offset
- 0x104) >> 2;
22148 add_unwind_opcode (op
, 1);
22150 else if (offset
> 0)
22152 /* Short opcode. */
22153 op
= (offset
- 4) >> 2;
22154 add_unwind_opcode (op
, 1);
22156 else if (offset
< 0)
22159 while (offset
> 0x100)
22161 add_unwind_opcode (0x7f, 1);
22164 op
= ((offset
- 4) >> 2) | 0x40;
22165 add_unwind_opcode (op
, 1);
22169 /* Finish the list of unwind opcodes for this function. */
22171 finish_unwind_opcodes (void)
22175 if (unwind
.fp_used
)
22177 /* Adjust sp as necessary. */
22178 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22179 flush_pending_unwind ();
22181 /* After restoring sp from the frame pointer. */
22182 op
= 0x90 | unwind
.fp_reg
;
22183 add_unwind_opcode (op
, 1);
22186 flush_pending_unwind ();
22190 /* Start an exception table entry. If idx is nonzero this is an index table
22194 start_unwind_section (const segT text_seg
, int idx
)
22196 const char * text_name
;
22197 const char * prefix
;
22198 const char * prefix_once
;
22199 const char * group_name
;
22207 prefix
= ELF_STRING_ARM_unwind
;
22208 prefix_once
= ELF_STRING_ARM_unwind_once
;
22209 type
= SHT_ARM_EXIDX
;
22213 prefix
= ELF_STRING_ARM_unwind_info
;
22214 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22215 type
= SHT_PROGBITS
;
22218 text_name
= segment_name (text_seg
);
22219 if (streq (text_name
, ".text"))
22222 if (strncmp (text_name
, ".gnu.linkonce.t.",
22223 strlen (".gnu.linkonce.t.")) == 0)
22225 prefix
= prefix_once
;
22226 text_name
+= strlen (".gnu.linkonce.t.");
22229 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22235 /* Handle COMDAT group. */
22236 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22238 group_name
= elf_group_name (text_seg
);
22239 if (group_name
== NULL
)
22241 as_bad (_("Group section `%s' has no group signature"),
22242 segment_name (text_seg
));
22243 ignore_rest_of_line ();
22246 flags
|= SHF_GROUP
;
22250 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22253 /* Set the section link for index tables. */
22255 elf_linked_to_section (now_seg
) = text_seg
;
22259 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22260 personality routine data. Returns zero, or the index table value for
22261 an inline entry. */
22264 create_unwind_entry (int have_data
)
22269 /* The current word of data. */
22271 /* The number of bytes left in this word. */
22274 finish_unwind_opcodes ();
22276 /* Remember the current text section. */
22277 unwind
.saved_seg
= now_seg
;
22278 unwind
.saved_subseg
= now_subseg
;
22280 start_unwind_section (now_seg
, 0);
22282 if (unwind
.personality_routine
== NULL
)
22284 if (unwind
.personality_index
== -2)
22287 as_bad (_("handlerdata in cantunwind frame"));
22288 return 1; /* EXIDX_CANTUNWIND. */
22291 /* Use a default personality routine if none is specified. */
22292 if (unwind
.personality_index
== -1)
22294 if (unwind
.opcode_count
> 3)
22295 unwind
.personality_index
= 1;
22297 unwind
.personality_index
= 0;
22300 /* Space for the personality routine entry. */
22301 if (unwind
.personality_index
== 0)
22303 if (unwind
.opcode_count
> 3)
22304 as_bad (_("too many unwind opcodes for personality routine 0"));
22308 /* All the data is inline in the index table. */
22311 while (unwind
.opcode_count
> 0)
22313 unwind
.opcode_count
--;
22314 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22318 /* Pad with "finish" opcodes. */
22320 data
= (data
<< 8) | 0xb0;
22327 /* We get two opcodes "free" in the first word. */
22328 size
= unwind
.opcode_count
- 2;
22332 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22333 if (unwind
.personality_index
!= -1)
22335 as_bad (_("attempt to recreate an unwind entry"));
22339 /* An extra byte is required for the opcode count. */
22340 size
= unwind
.opcode_count
+ 1;
22343 size
= (size
+ 3) >> 2;
22345 as_bad (_("too many unwind opcodes"));
22347 frag_align (2, 0, 0);
22348 record_alignment (now_seg
, 2);
22349 unwind
.table_entry
= expr_build_dot ();
22351 /* Allocate the table entry. */
22352 ptr
= frag_more ((size
<< 2) + 4);
22353 /* PR 13449: Zero the table entries in case some of them are not used. */
22354 memset (ptr
, 0, (size
<< 2) + 4);
22355 where
= frag_now_fix () - ((size
<< 2) + 4);
22357 switch (unwind
.personality_index
)
22360 /* ??? Should this be a PLT generating relocation? */
22361 /* Custom personality routine. */
22362 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22363 BFD_RELOC_ARM_PREL31
);
22368 /* Set the first byte to the number of additional words. */
22369 data
= size
> 0 ? size
- 1 : 0;
22373 /* ABI defined personality routines. */
22375 /* Three opcodes bytes are packed into the first word. */
22382 /* The size and first two opcode bytes go in the first word. */
22383 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22388 /* Should never happen. */
22392 /* Pack the opcodes into words (MSB first), reversing the list at the same
22394 while (unwind
.opcode_count
> 0)
22398 md_number_to_chars (ptr
, data
, 4);
22403 unwind
.opcode_count
--;
22405 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22408 /* Finish off the last word. */
22411 /* Pad with "finish" opcodes. */
22413 data
= (data
<< 8) | 0xb0;
22415 md_number_to_chars (ptr
, data
, 4);
22420 /* Add an empty descriptor if there is no user-specified data. */
22421 ptr
= frag_more (4);
22422 md_number_to_chars (ptr
, 0, 4);
22429 /* Initialize the DWARF-2 unwind information for this procedure. */
22432 tc_arm_frame_initial_instructions (void)
22434 cfi_add_CFA_def_cfa (REG_SP
, 0);
22436 #endif /* OBJ_ELF */
22438 /* Convert REGNAME to a DWARF-2 register number. */
22441 tc_arm_regname_to_dw2regnum (char *regname
)
22443 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22447 /* PR 16694: Allow VFP registers as well. */
22448 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22452 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22461 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22465 exp
.X_op
= O_secrel
;
22466 exp
.X_add_symbol
= symbol
;
22467 exp
.X_add_number
= 0;
22468 emit_expr (&exp
, size
);
22472 /* MD interface: Symbol and relocation handling. */
22474 /* Return the address within the segment that a PC-relative fixup is
22475 relative to. For ARM, PC-relative fixups applied to instructions
22476 are generally relative to the location of the fixup plus 8 bytes.
22477 Thumb branches are offset by 4, and Thumb loads relative to PC
22478 require special handling. */
22481 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22483 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22485 /* If this is pc-relative and we are going to emit a relocation
22486 then we just want to put out any pipeline compensation that the linker
22487 will need. Otherwise we want to use the calculated base.
22488 For WinCE we skip the bias for externals as well, since this
22489 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22491 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22492 || (arm_force_relocation (fixP
)
22494 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22500 switch (fixP
->fx_r_type
)
22502 /* PC relative addressing on the Thumb is slightly odd as the
22503 bottom two bits of the PC are forced to zero for the
22504 calculation. This happens *after* application of the
22505 pipeline offset. However, Thumb adrl already adjusts for
22506 this, so we need not do it again. */
22507 case BFD_RELOC_ARM_THUMB_ADD
:
22510 case BFD_RELOC_ARM_THUMB_OFFSET
:
22511 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22512 case BFD_RELOC_ARM_T32_ADD_PC12
:
22513 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22514 return (base
+ 4) & ~3;
22516 /* Thumb branches are simply offset by +4. */
22517 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22518 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22519 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22520 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22521 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22524 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22526 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22527 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22528 && ARM_IS_FUNC (fixP
->fx_addsy
)
22529 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22530 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22533 /* BLX is like branches above, but forces the low two bits of PC to
22535 case BFD_RELOC_THUMB_PCREL_BLX
:
22537 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22538 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22539 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22540 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22541 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22542 return (base
+ 4) & ~3;
22544 /* ARM mode branches are offset by +8. However, the Windows CE
22545 loader expects the relocation not to take this into account. */
22546 case BFD_RELOC_ARM_PCREL_BLX
:
22548 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22549 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22550 && ARM_IS_FUNC (fixP
->fx_addsy
)
22551 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22552 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22555 case BFD_RELOC_ARM_PCREL_CALL
:
22557 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22558 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22559 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22560 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22561 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22564 case BFD_RELOC_ARM_PCREL_BRANCH
:
22565 case BFD_RELOC_ARM_PCREL_JUMP
:
22566 case BFD_RELOC_ARM_PLT32
:
22568 /* When handling fixups immediately, because we have already
22569 discovered the value of a symbol, or the address of the frag involved
22570 we must account for the offset by +8, as the OS loader will never see the reloc.
22571 see fixup_segment() in write.c
22572 The S_IS_EXTERNAL test handles the case of global symbols.
22573 Those need the calculated base, not just the pipe compensation the linker will need. */
22575 && fixP
->fx_addsy
!= NULL
22576 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22577 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22585 /* ARM mode loads relative to PC are also offset by +8. Unlike
22586 branches, the Windows CE loader *does* expect the relocation
22587 to take this into account. */
22588 case BFD_RELOC_ARM_OFFSET_IMM
:
22589 case BFD_RELOC_ARM_OFFSET_IMM8
:
22590 case BFD_RELOC_ARM_HWLITERAL
:
22591 case BFD_RELOC_ARM_LITERAL
:
22592 case BFD_RELOC_ARM_CP_OFF_IMM
:
22596 /* Other PC-relative relocations are un-offset. */
22602 static bfd_boolean flag_warn_syms
= TRUE
;
22605 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22607 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22608 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22609 does mean that the resulting code might be very confusing to the reader.
22610 Also this warning can be triggered if the user omits an operand before
22611 an immediate address, eg:
22615 GAS treats this as an assignment of the value of the symbol foo to a
22616 symbol LDR, and so (without this code) it will not issue any kind of
22617 warning or error message.
22619 Note - ARM instructions are case-insensitive but the strings in the hash
22620 table are all stored in lower case, so we must first ensure that name is
22622 if (flag_warn_syms
&& arm_ops_hsh
)
22624 char * nbuf
= strdup (name
);
22627 for (p
= nbuf
; *p
; p
++)
22629 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22631 static struct hash_control
* already_warned
= NULL
;
22633 if (already_warned
== NULL
)
22634 already_warned
= hash_new ();
22635 /* Only warn about the symbol once. To keep the code
22636 simple we let hash_insert do the lookup for us. */
22637 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22638 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22647 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22648 Otherwise we have no need to default values of symbols. */
22651 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22654 if (name
[0] == '_' && name
[1] == 'G'
22655 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22659 if (symbol_find (name
))
22660 as_bad (_("GOT already in the symbol table"));
22662 GOT_symbol
= symbol_new (name
, undefined_section
,
22663 (valueT
) 0, & zero_address_frag
);
22673 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22674 computed as two separate immediate values, added together. We
22675 already know that this value cannot be computed by just one ARM
22678 static unsigned int
22679 validate_immediate_twopart (unsigned int val
,
22680 unsigned int * highpart
)
22685 for (i
= 0; i
< 32; i
+= 2)
22686 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22692 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22694 else if (a
& 0xff0000)
22696 if (a
& 0xff000000)
22698 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22702 gas_assert (a
& 0xff000000);
22703 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22706 return (a
& 0xff) | (i
<< 7);
22713 validate_offset_imm (unsigned int val
, int hwse
)
22715 if ((hwse
&& val
> 255) || val
> 4095)
22720 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22721 negative immediate constant by altering the instruction. A bit of
22726 by inverting the second operand, and
22729 by negating the second operand. */
22732 negate_data_op (unsigned long * instruction
,
22733 unsigned long value
)
22736 unsigned long negated
, inverted
;
22738 negated
= encode_arm_immediate (-value
);
22739 inverted
= encode_arm_immediate (~value
);
22741 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22744 /* First negates. */
22745 case OPCODE_SUB
: /* ADD <-> SUB */
22746 new_inst
= OPCODE_ADD
;
22751 new_inst
= OPCODE_SUB
;
22755 case OPCODE_CMP
: /* CMP <-> CMN */
22756 new_inst
= OPCODE_CMN
;
22761 new_inst
= OPCODE_CMP
;
22765 /* Now Inverted ops. */
22766 case OPCODE_MOV
: /* MOV <-> MVN */
22767 new_inst
= OPCODE_MVN
;
22772 new_inst
= OPCODE_MOV
;
22776 case OPCODE_AND
: /* AND <-> BIC */
22777 new_inst
= OPCODE_BIC
;
22782 new_inst
= OPCODE_AND
;
22786 case OPCODE_ADC
: /* ADC <-> SBC */
22787 new_inst
= OPCODE_SBC
;
22792 new_inst
= OPCODE_ADC
;
22796 /* We cannot do anything. */
22801 if (value
== (unsigned) FAIL
)
22804 *instruction
&= OPCODE_MASK
;
22805 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22809 /* Like negate_data_op, but for Thumb-2. */
22811 static unsigned int
22812 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22816 unsigned int negated
, inverted
;
22818 negated
= encode_thumb32_immediate (-value
);
22819 inverted
= encode_thumb32_immediate (~value
);
22821 rd
= (*instruction
>> 8) & 0xf;
22822 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22825 /* ADD <-> SUB. Includes CMP <-> CMN. */
22826 case T2_OPCODE_SUB
:
22827 new_inst
= T2_OPCODE_ADD
;
22831 case T2_OPCODE_ADD
:
22832 new_inst
= T2_OPCODE_SUB
;
22836 /* ORR <-> ORN. Includes MOV <-> MVN. */
22837 case T2_OPCODE_ORR
:
22838 new_inst
= T2_OPCODE_ORN
;
22842 case T2_OPCODE_ORN
:
22843 new_inst
= T2_OPCODE_ORR
;
22847 /* AND <-> BIC. TST has no inverted equivalent. */
22848 case T2_OPCODE_AND
:
22849 new_inst
= T2_OPCODE_BIC
;
22856 case T2_OPCODE_BIC
:
22857 new_inst
= T2_OPCODE_AND
;
22862 case T2_OPCODE_ADC
:
22863 new_inst
= T2_OPCODE_SBC
;
22867 case T2_OPCODE_SBC
:
22868 new_inst
= T2_OPCODE_ADC
;
22872 /* We cannot do anything. */
22877 if (value
== (unsigned int)FAIL
)
22880 *instruction
&= T2_OPCODE_MASK
;
22881 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22885 /* Read a 32-bit thumb instruction from buf. */
22886 static unsigned long
22887 get_thumb32_insn (char * buf
)
22889 unsigned long insn
;
22890 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22891 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22897 /* We usually want to set the low bit on the address of thumb function
22898 symbols. In particular .word foo - . should have the low bit set.
22899 Generic code tries to fold the difference of two symbols to
22900 a constant. Prevent this and force a relocation when the first symbols
22901 is a thumb function. */
22904 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22906 if (op
== O_subtract
22907 && l
->X_op
== O_symbol
22908 && r
->X_op
== O_symbol
22909 && THUMB_IS_FUNC (l
->X_add_symbol
))
22911 l
->X_op
= O_subtract
;
22912 l
->X_op_symbol
= r
->X_add_symbol
;
22913 l
->X_add_number
-= r
->X_add_number
;
22917 /* Process as normal. */
22921 /* Encode Thumb2 unconditional branches and calls. The encoding
22922 for the 2 are identical for the immediate values. */
22925 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22927 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22930 addressT S
, I1
, I2
, lo
, hi
;
22932 S
= (value
>> 24) & 0x01;
22933 I1
= (value
>> 23) & 0x01;
22934 I2
= (value
>> 22) & 0x01;
22935 hi
= (value
>> 12) & 0x3ff;
22936 lo
= (value
>> 1) & 0x7ff;
22937 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22938 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22939 newval
|= (S
<< 10) | hi
;
22940 newval2
&= ~T2I1I2MASK
;
22941 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22942 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22943 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22947 md_apply_fix (fixS
* fixP
,
22951 offsetT value
= * valP
;
22953 unsigned int newimm
;
22954 unsigned long temp
;
22956 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22958 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22960 /* Note whether this will delete the relocation. */
22962 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22965 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22966 consistency with the behaviour on 32-bit hosts. Remember value
22968 value
&= 0xffffffff;
22969 value
^= 0x80000000;
22970 value
-= 0x80000000;
22973 fixP
->fx_addnumber
= value
;
22975 /* Same treatment for fixP->fx_offset. */
22976 fixP
->fx_offset
&= 0xffffffff;
22977 fixP
->fx_offset
^= 0x80000000;
22978 fixP
->fx_offset
-= 0x80000000;
22980 switch (fixP
->fx_r_type
)
22982 case BFD_RELOC_NONE
:
22983 /* This will need to go in the object file. */
22987 case BFD_RELOC_ARM_IMMEDIATE
:
22988 /* We claim that this fixup has been processed here,
22989 even if in fact we generate an error because we do
22990 not have a reloc for it, so tc_gen_reloc will reject it. */
22993 if (fixP
->fx_addsy
)
22995 const char *msg
= 0;
22997 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22998 msg
= _("undefined symbol %s used as an immediate value");
22999 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23000 msg
= _("symbol %s is in a different section");
23001 else if (S_IS_WEAK (fixP
->fx_addsy
))
23002 msg
= _("symbol %s is weak and may be overridden later");
23006 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23007 msg
, S_GET_NAME (fixP
->fx_addsy
));
23012 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23014 /* If the offset is negative, we should use encoding A2 for ADR. */
23015 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23016 newimm
= negate_data_op (&temp
, value
);
23019 newimm
= encode_arm_immediate (value
);
23021 /* If the instruction will fail, see if we can fix things up by
23022 changing the opcode. */
23023 if (newimm
== (unsigned int) FAIL
)
23024 newimm
= negate_data_op (&temp
, value
);
23025 /* MOV accepts both ARM modified immediate (A1 encoding) and
23026 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23027 When disassembling, MOV is preferred when there is no encoding
23029 if (newimm
== (unsigned int) FAIL
23030 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23031 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23032 && !((temp
>> SBIT_SHIFT
) & 0x1)
23033 && value
>= 0 && value
<= 0xffff)
23035 /* Clear bits[23:20] to change encoding from A1 to A2. */
23036 temp
&= 0xff0fffff;
23037 /* Encoding high 4bits imm. Code below will encode the remaining
23039 temp
|= (value
& 0x0000f000) << 4;
23040 newimm
= value
& 0x00000fff;
23044 if (newimm
== (unsigned int) FAIL
)
23046 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23047 _("invalid constant (%lx) after fixup"),
23048 (unsigned long) value
);
23052 newimm
|= (temp
& 0xfffff000);
23053 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23056 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23058 unsigned int highpart
= 0;
23059 unsigned int newinsn
= 0xe1a00000; /* nop. */
23061 if (fixP
->fx_addsy
)
23063 const char *msg
= 0;
23065 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23066 msg
= _("undefined symbol %s used as an immediate value");
23067 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23068 msg
= _("symbol %s is in a different section");
23069 else if (S_IS_WEAK (fixP
->fx_addsy
))
23070 msg
= _("symbol %s is weak and may be overridden later");
23074 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23075 msg
, S_GET_NAME (fixP
->fx_addsy
));
23080 newimm
= encode_arm_immediate (value
);
23081 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23083 /* If the instruction will fail, see if we can fix things up by
23084 changing the opcode. */
23085 if (newimm
== (unsigned int) FAIL
23086 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23088 /* No ? OK - try using two ADD instructions to generate
23090 newimm
= validate_immediate_twopart (value
, & highpart
);
23092 /* Yes - then make sure that the second instruction is
23094 if (newimm
!= (unsigned int) FAIL
)
23096 /* Still No ? Try using a negated value. */
23097 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23098 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23099 /* Otherwise - give up. */
23102 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23103 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23108 /* Replace the first operand in the 2nd instruction (which
23109 is the PC) with the destination register. We have
23110 already added in the PC in the first instruction and we
23111 do not want to do it again. */
23112 newinsn
&= ~ 0xf0000;
23113 newinsn
|= ((newinsn
& 0x0f000) << 4);
23116 newimm
|= (temp
& 0xfffff000);
23117 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23119 highpart
|= (newinsn
& 0xfffff000);
23120 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23124 case BFD_RELOC_ARM_OFFSET_IMM
:
23125 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23127 /* Fall through. */
23129 case BFD_RELOC_ARM_LITERAL
:
23135 if (validate_offset_imm (value
, 0) == FAIL
)
23137 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23138 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23139 _("invalid literal constant: pool needs to be closer"));
23141 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23142 _("bad immediate value for offset (%ld)"),
23147 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23149 newval
&= 0xfffff000;
23152 newval
&= 0xff7ff000;
23153 newval
|= value
| (sign
? INDEX_UP
: 0);
23155 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23158 case BFD_RELOC_ARM_OFFSET_IMM8
:
23159 case BFD_RELOC_ARM_HWLITERAL
:
23165 if (validate_offset_imm (value
, 1) == FAIL
)
23167 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23168 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23169 _("invalid literal constant: pool needs to be closer"));
23171 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23172 _("bad immediate value for 8-bit offset (%ld)"),
23177 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23179 newval
&= 0xfffff0f0;
23182 newval
&= 0xff7ff0f0;
23183 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23185 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23188 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23189 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23191 _("bad immediate value for offset (%ld)"), (long) value
);
23194 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23196 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23199 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23200 /* This is a complicated relocation used for all varieties of Thumb32
23201 load/store instruction with immediate offset:
23203 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23204 *4, optional writeback(W)
23205 (doubleword load/store)
23207 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23208 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23209 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23210 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23211 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23213 Uppercase letters indicate bits that are already encoded at
23214 this point. Lowercase letters are our problem. For the
23215 second block of instructions, the secondary opcode nybble
23216 (bits 8..11) is present, and bit 23 is zero, even if this is
23217 a PC-relative operation. */
23218 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23220 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23222 if ((newval
& 0xf0000000) == 0xe0000000)
23224 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23226 newval
|= (1 << 23);
23229 if (value
% 4 != 0)
23231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23232 _("offset not a multiple of 4"));
23238 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23239 _("offset out of range"));
23244 else if ((newval
& 0x000f0000) == 0x000f0000)
23246 /* PC-relative, 12-bit offset. */
23248 newval
|= (1 << 23);
23253 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23254 _("offset out of range"));
23259 else if ((newval
& 0x00000100) == 0x00000100)
23261 /* Writeback: 8-bit, +/- offset. */
23263 newval
|= (1 << 9);
23268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23269 _("offset out of range"));
23274 else if ((newval
& 0x00000f00) == 0x00000e00)
23276 /* T-instruction: positive 8-bit offset. */
23277 if (value
< 0 || value
> 0xff)
23279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23280 _("offset out of range"));
23288 /* Positive 12-bit or negative 8-bit offset. */
23292 newval
|= (1 << 23);
23302 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23303 _("offset out of range"));
23310 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23311 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23314 case BFD_RELOC_ARM_SHIFT_IMM
:
23315 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23316 if (((unsigned long) value
) > 32
23318 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23320 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23321 _("shift expression is too large"));
23326 /* Shifts of zero must be done as lsl. */
23328 else if (value
== 32)
23330 newval
&= 0xfffff07f;
23331 newval
|= (value
& 0x1f) << 7;
23332 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23335 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23336 case BFD_RELOC_ARM_T32_ADD_IMM
:
23337 case BFD_RELOC_ARM_T32_IMM12
:
23338 case BFD_RELOC_ARM_T32_ADD_PC12
:
23339 /* We claim that this fixup has been processed here,
23340 even if in fact we generate an error because we do
23341 not have a reloc for it, so tc_gen_reloc will reject it. */
23345 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23348 _("undefined symbol %s used as an immediate value"),
23349 S_GET_NAME (fixP
->fx_addsy
));
23353 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23355 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23358 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23359 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23360 Thumb2 modified immediate encoding (T2). */
23361 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23362 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23364 newimm
= encode_thumb32_immediate (value
);
23365 if (newimm
== (unsigned int) FAIL
)
23366 newimm
= thumb32_negate_data_op (&newval
, value
);
23368 if (newimm
== (unsigned int) FAIL
)
23370 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23372 /* Turn add/sum into addw/subw. */
23373 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23374 newval
= (newval
& 0xfeffffff) | 0x02000000;
23375 /* No flat 12-bit imm encoding for addsw/subsw. */
23376 if ((newval
& 0x00100000) == 0)
23378 /* 12 bit immediate for addw/subw. */
23382 newval
^= 0x00a00000;
23385 newimm
= (unsigned int) FAIL
;
23392 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23393 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23394 disassembling, MOV is preferred when there is no encoding
23396 NOTE: MOV is using ORR opcode under Thumb 2 mode. */
23397 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23398 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23399 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23400 && value
>= 0 && value
<=0xffff)
23402 /* Toggle bit[25] to change encoding from T2 to T3. */
23404 /* Clear bits[19:16]. */
23405 newval
&= 0xfff0ffff;
23406 /* Encoding high 4bits imm. Code below will encode the
23407 remaining low 12bits. */
23408 newval
|= (value
& 0x0000f000) << 4;
23409 newimm
= value
& 0x00000fff;
23414 if (newimm
== (unsigned int)FAIL
)
23416 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23417 _("invalid constant (%lx) after fixup"),
23418 (unsigned long) value
);
23422 newval
|= (newimm
& 0x800) << 15;
23423 newval
|= (newimm
& 0x700) << 4;
23424 newval
|= (newimm
& 0x0ff);
23426 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23427 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23430 case BFD_RELOC_ARM_SMC
:
23431 if (((unsigned long) value
) > 0xffff)
23432 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23433 _("invalid smc expression"));
23434 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23435 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23436 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23439 case BFD_RELOC_ARM_HVC
:
23440 if (((unsigned long) value
) > 0xffff)
23441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23442 _("invalid hvc expression"));
23443 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23444 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23445 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23448 case BFD_RELOC_ARM_SWI
:
23449 if (fixP
->tc_fix_data
!= 0)
23451 if (((unsigned long) value
) > 0xff)
23452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23453 _("invalid swi expression"));
23454 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23456 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23460 if (((unsigned long) value
) > 0x00ffffff)
23461 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23462 _("invalid swi expression"));
23463 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23465 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23469 case BFD_RELOC_ARM_MULTI
:
23470 if (((unsigned long) value
) > 0xffff)
23471 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23472 _("invalid expression in load/store multiple"));
23473 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23474 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23478 case BFD_RELOC_ARM_PCREL_CALL
:
23480 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23482 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23483 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23484 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23485 /* Flip the bl to blx. This is a simple flip
23486 bit here because we generate PCREL_CALL for
23487 unconditional bls. */
23489 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23490 newval
= newval
| 0x10000000;
23491 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23497 goto arm_branch_common
;
23499 case BFD_RELOC_ARM_PCREL_JUMP
:
23500 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23502 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23503 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23504 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23506 /* This would map to a bl<cond>, b<cond>,
23507 b<always> to a Thumb function. We
23508 need to force a relocation for this particular
23510 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23513 /* Fall through. */
23515 case BFD_RELOC_ARM_PLT32
:
23517 case BFD_RELOC_ARM_PCREL_BRANCH
:
23519 goto arm_branch_common
;
23521 case BFD_RELOC_ARM_PCREL_BLX
:
23524 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23526 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23527 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23528 && ARM_IS_FUNC (fixP
->fx_addsy
))
23530 /* Flip the blx to a bl and warn. */
23531 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23532 newval
= 0xeb000000;
23533 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23534 _("blx to '%s' an ARM ISA state function changed to bl"),
23536 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23542 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23543 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23547 /* We are going to store value (shifted right by two) in the
23548 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23549 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23552 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23553 _("misaligned branch destination"));
23554 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23555 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23558 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23560 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23561 newval
|= (value
>> 2) & 0x00ffffff;
23562 /* Set the H bit on BLX instructions. */
23566 newval
|= 0x01000000;
23568 newval
&= ~0x01000000;
23570 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23574 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23575 /* CBZ can only branch forward. */
23577 /* Attempts to use CBZ to branch to the next instruction
23578 (which, strictly speaking, are prohibited) will be turned into
23581 FIXME: It may be better to remove the instruction completely and
23582 perform relaxation. */
23585 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23586 newval
= 0xbf00; /* NOP encoding T1 */
23587 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23594 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23596 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23597 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23598 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23603 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23604 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23605 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23607 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23609 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23610 newval
|= (value
& 0x1ff) >> 1;
23611 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23615 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23616 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23619 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23621 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23622 newval
|= (value
& 0xfff) >> 1;
23623 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23627 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23629 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23630 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23631 && ARM_IS_FUNC (fixP
->fx_addsy
)
23632 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23634 /* Force a relocation for a branch 20 bits wide. */
23637 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23638 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23639 _("conditional branch out of range"));
23641 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23644 addressT S
, J1
, J2
, lo
, hi
;
23646 S
= (value
& 0x00100000) >> 20;
23647 J2
= (value
& 0x00080000) >> 19;
23648 J1
= (value
& 0x00040000) >> 18;
23649 hi
= (value
& 0x0003f000) >> 12;
23650 lo
= (value
& 0x00000ffe) >> 1;
23652 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23653 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23654 newval
|= (S
<< 10) | hi
;
23655 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23656 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23657 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23661 case BFD_RELOC_THUMB_PCREL_BLX
:
23662 /* If there is a blx from a thumb state function to
23663 another thumb function flip this to a bl and warn
23667 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23668 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23669 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23671 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23672 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23673 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23675 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23676 newval
= newval
| 0x1000;
23677 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23678 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23683 goto thumb_bl_common
;
23685 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23686 /* A bl from Thumb state ISA to an internal ARM state function
23687 is converted to a blx. */
23689 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23690 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23691 && ARM_IS_FUNC (fixP
->fx_addsy
)
23692 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23694 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23695 newval
= newval
& ~0x1000;
23696 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23697 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23703 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23704 /* For a BLX instruction, make sure that the relocation is rounded up
23705 to a word boundary. This follows the semantics of the instruction
23706 which specifies that bit 1 of the target address will come from bit
23707 1 of the base address. */
23708 value
= (value
+ 3) & ~ 3;
23711 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23712 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23713 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23716 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23718 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23720 else if ((value
& ~0x1ffffff)
23721 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23723 _("Thumb2 branch out of range"));
23726 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23727 encode_thumb2_b_bl_offset (buf
, value
);
23731 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23732 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23733 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23735 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23736 encode_thumb2_b_bl_offset (buf
, value
);
23741 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23746 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23747 md_number_to_chars (buf
, value
, 2);
23751 case BFD_RELOC_ARM_TLS_CALL
:
23752 case BFD_RELOC_ARM_THM_TLS_CALL
:
23753 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23754 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23755 case BFD_RELOC_ARM_TLS_GOTDESC
:
23756 case BFD_RELOC_ARM_TLS_GD32
:
23757 case BFD_RELOC_ARM_TLS_LE32
:
23758 case BFD_RELOC_ARM_TLS_IE32
:
23759 case BFD_RELOC_ARM_TLS_LDM32
:
23760 case BFD_RELOC_ARM_TLS_LDO32
:
23761 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23764 case BFD_RELOC_ARM_GOT32
:
23765 case BFD_RELOC_ARM_GOTOFF
:
23768 case BFD_RELOC_ARM_GOT_PREL
:
23769 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23770 md_number_to_chars (buf
, value
, 4);
23773 case BFD_RELOC_ARM_TARGET2
:
23774 /* TARGET2 is not partial-inplace, so we need to write the
23775 addend here for REL targets, because it won't be written out
23776 during reloc processing later. */
23777 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23778 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23782 case BFD_RELOC_RVA
:
23784 case BFD_RELOC_ARM_TARGET1
:
23785 case BFD_RELOC_ARM_ROSEGREL32
:
23786 case BFD_RELOC_ARM_SBREL32
:
23787 case BFD_RELOC_32_PCREL
:
23789 case BFD_RELOC_32_SECREL
:
23791 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23793 /* For WinCE we only do this for pcrel fixups. */
23794 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23796 md_number_to_chars (buf
, value
, 4);
23800 case BFD_RELOC_ARM_PREL31
:
23801 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23803 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23804 if ((value
^ (value
>> 1)) & 0x40000000)
23806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23807 _("rel31 relocation overflow"));
23809 newval
|= value
& 0x7fffffff;
23810 md_number_to_chars (buf
, newval
, 4);
23815 case BFD_RELOC_ARM_CP_OFF_IMM
:
23816 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23817 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23818 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23820 newval
= get_thumb32_insn (buf
);
23821 if ((newval
& 0x0f200f00) == 0x0d000900)
23823 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23824 has permitted values that are multiples of 2, in the range 0
23826 if (value
< -510 || value
> 510 || (value
& 1))
23827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23828 _("co-processor offset out of range"));
23830 else if (value
< -1023 || value
> 1023 || (value
& 3))
23831 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23832 _("co-processor offset out of range"));
23837 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23838 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23839 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23841 newval
= get_thumb32_insn (buf
);
23843 newval
&= 0xffffff00;
23846 newval
&= 0xff7fff00;
23847 if ((newval
& 0x0f200f00) == 0x0d000900)
23849 /* This is a fp16 vstr/vldr.
23851 It requires the immediate offset in the instruction is shifted
23852 left by 1 to be a half-word offset.
23854 Here, left shift by 1 first, and later right shift by 2
23855 should get the right offset. */
23858 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23860 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23861 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23862 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23864 put_thumb32_insn (buf
, newval
);
23867 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23868 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23869 if (value
< -255 || value
> 255)
23870 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23871 _("co-processor offset out of range"));
23873 goto cp_off_common
;
23875 case BFD_RELOC_ARM_THUMB_OFFSET
:
23876 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23877 /* Exactly what ranges, and where the offset is inserted depends
23878 on the type of instruction, we can establish this from the
23880 switch (newval
>> 12)
23882 case 4: /* PC load. */
23883 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23884 forced to zero for these loads; md_pcrel_from has already
23885 compensated for this. */
23887 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23888 _("invalid offset, target not word aligned (0x%08lX)"),
23889 (((unsigned long) fixP
->fx_frag
->fr_address
23890 + (unsigned long) fixP
->fx_where
) & ~3)
23891 + (unsigned long) value
);
23893 if (value
& ~0x3fc)
23894 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23895 _("invalid offset, value too big (0x%08lX)"),
23898 newval
|= value
>> 2;
23901 case 9: /* SP load/store. */
23902 if (value
& ~0x3fc)
23903 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23904 _("invalid offset, value too big (0x%08lX)"),
23906 newval
|= value
>> 2;
23909 case 6: /* Word load/store. */
23911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23912 _("invalid offset, value too big (0x%08lX)"),
23914 newval
|= value
<< 4; /* 6 - 2. */
23917 case 7: /* Byte load/store. */
23919 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23920 _("invalid offset, value too big (0x%08lX)"),
23922 newval
|= value
<< 6;
23925 case 8: /* Halfword load/store. */
23927 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23928 _("invalid offset, value too big (0x%08lX)"),
23930 newval
|= value
<< 5; /* 6 - 1. */
23934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23935 "Unable to process relocation for thumb opcode: %lx",
23936 (unsigned long) newval
);
23939 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23942 case BFD_RELOC_ARM_THUMB_ADD
:
23943 /* This is a complicated relocation, since we use it for all of
23944 the following immediate relocations:
23948 9bit ADD/SUB SP word-aligned
23949 10bit ADD PC/SP word-aligned
23951 The type of instruction being processed is encoded in the
23958 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23960 int rd
= (newval
>> 4) & 0xf;
23961 int rs
= newval
& 0xf;
23962 int subtract
= !!(newval
& 0x8000);
23964 /* Check for HI regs, only very restricted cases allowed:
23965 Adjusting SP, and using PC or SP to get an address. */
23966 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23967 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23969 _("invalid Hi register with immediate"));
23971 /* If value is negative, choose the opposite instruction. */
23975 subtract
= !subtract
;
23977 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23978 _("immediate value out of range"));
23983 if (value
& ~0x1fc)
23984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23985 _("invalid immediate for stack address calculation"));
23986 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23987 newval
|= value
>> 2;
23989 else if (rs
== REG_PC
|| rs
== REG_SP
)
23991 /* PR gas/18541. If the addition is for a defined symbol
23992 within range of an ADR instruction then accept it. */
23995 && fixP
->fx_addsy
!= NULL
)
23999 if (! S_IS_DEFINED (fixP
->fx_addsy
)
24000 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
24001 || S_IS_WEAK (fixP
->fx_addsy
))
24003 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24004 _("address calculation needs a strongly defined nearby symbol"));
24008 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24010 /* Round up to the next 4-byte boundary. */
24015 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24019 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24020 _("symbol too far away"));
24030 if (subtract
|| value
& ~0x3fc)
24031 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24032 _("invalid immediate for address calculation (value = 0x%08lX)"),
24033 (unsigned long) (subtract
? - value
: value
));
24034 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24036 newval
|= value
>> 2;
24041 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24042 _("immediate value out of range"));
24043 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24044 newval
|= (rd
<< 8) | value
;
24049 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24050 _("immediate value out of range"));
24051 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24052 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24055 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24058 case BFD_RELOC_ARM_THUMB_IMM
:
24059 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24060 if (value
< 0 || value
> 255)
24061 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24062 _("invalid immediate: %ld is out of range"),
24065 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24068 case BFD_RELOC_ARM_THUMB_SHIFT
:
24069 /* 5bit shift value (0..32). LSL cannot take 32. */
24070 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24071 temp
= newval
& 0xf800;
24072 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24073 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24074 _("invalid shift value: %ld"), (long) value
);
24075 /* Shifts of zero must be encoded as LSL. */
24077 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24078 /* Shifts of 32 are encoded as zero. */
24079 else if (value
== 32)
24081 newval
|= value
<< 6;
24082 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24085 case BFD_RELOC_VTABLE_INHERIT
:
24086 case BFD_RELOC_VTABLE_ENTRY
:
24090 case BFD_RELOC_ARM_MOVW
:
24091 case BFD_RELOC_ARM_MOVT
:
24092 case BFD_RELOC_ARM_THUMB_MOVW
:
24093 case BFD_RELOC_ARM_THUMB_MOVT
:
24094 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24096 /* REL format relocations are limited to a 16-bit addend. */
24097 if (!fixP
->fx_done
)
24099 if (value
< -0x8000 || value
> 0x7fff)
24100 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24101 _("offset out of range"));
24103 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24104 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24109 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24110 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24112 newval
= get_thumb32_insn (buf
);
24113 newval
&= 0xfbf08f00;
24114 newval
|= (value
& 0xf000) << 4;
24115 newval
|= (value
& 0x0800) << 15;
24116 newval
|= (value
& 0x0700) << 4;
24117 newval
|= (value
& 0x00ff);
24118 put_thumb32_insn (buf
, newval
);
24122 newval
= md_chars_to_number (buf
, 4);
24123 newval
&= 0xfff0f000;
24124 newval
|= value
& 0x0fff;
24125 newval
|= (value
& 0xf000) << 4;
24126 md_number_to_chars (buf
, newval
, 4);
24131 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24132 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24133 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24134 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24135 gas_assert (!fixP
->fx_done
);
24138 bfd_boolean is_mov
;
24139 bfd_vma encoded_addend
= value
;
24141 /* Check that addend can be encoded in instruction. */
24142 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24143 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24144 _("the offset 0x%08lX is not representable"),
24145 (unsigned long) encoded_addend
);
24147 /* Extract the instruction. */
24148 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24149 is_mov
= (insn
& 0xf800) == 0x2000;
24154 if (!seg
->use_rela_p
)
24155 insn
|= encoded_addend
;
24161 /* Extract the instruction. */
24162 /* Encoding is the following
24167 /* The following conditions must be true :
24172 rd
= (insn
>> 4) & 0xf;
24174 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24176 _("Unable to process relocation for thumb opcode: %lx"),
24177 (unsigned long) insn
);
24179 /* Encode as ADD immediate8 thumb 1 code. */
24180 insn
= 0x3000 | (rd
<< 8);
24182 /* Place the encoded addend into the first 8 bits of the
24184 if (!seg
->use_rela_p
)
24185 insn
|= encoded_addend
;
24188 /* Update the instruction. */
24189 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24193 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24194 case BFD_RELOC_ARM_ALU_PC_G0
:
24195 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24196 case BFD_RELOC_ARM_ALU_PC_G1
:
24197 case BFD_RELOC_ARM_ALU_PC_G2
:
24198 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24199 case BFD_RELOC_ARM_ALU_SB_G0
:
24200 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24201 case BFD_RELOC_ARM_ALU_SB_G1
:
24202 case BFD_RELOC_ARM_ALU_SB_G2
:
24203 gas_assert (!fixP
->fx_done
);
24204 if (!seg
->use_rela_p
)
24207 bfd_vma encoded_addend
;
24208 bfd_vma addend_abs
= abs (value
);
24210 /* Check that the absolute value of the addend can be
24211 expressed as an 8-bit constant plus a rotation. */
24212 encoded_addend
= encode_arm_immediate (addend_abs
);
24213 if (encoded_addend
== (unsigned int) FAIL
)
24214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24215 _("the offset 0x%08lX is not representable"),
24216 (unsigned long) addend_abs
);
24218 /* Extract the instruction. */
24219 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24221 /* If the addend is positive, use an ADD instruction.
24222 Otherwise use a SUB. Take care not to destroy the S bit. */
24223 insn
&= 0xff1fffff;
24229 /* Place the encoded addend into the first 12 bits of the
24231 insn
&= 0xfffff000;
24232 insn
|= encoded_addend
;
24234 /* Update the instruction. */
24235 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24239 case BFD_RELOC_ARM_LDR_PC_G0
:
24240 case BFD_RELOC_ARM_LDR_PC_G1
:
24241 case BFD_RELOC_ARM_LDR_PC_G2
:
24242 case BFD_RELOC_ARM_LDR_SB_G0
:
24243 case BFD_RELOC_ARM_LDR_SB_G1
:
24244 case BFD_RELOC_ARM_LDR_SB_G2
:
24245 gas_assert (!fixP
->fx_done
);
24246 if (!seg
->use_rela_p
)
24249 bfd_vma addend_abs
= abs (value
);
24251 /* Check that the absolute value of the addend can be
24252 encoded in 12 bits. */
24253 if (addend_abs
>= 0x1000)
24254 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24255 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24256 (unsigned long) addend_abs
);
24258 /* Extract the instruction. */
24259 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24261 /* If the addend is negative, clear bit 23 of the instruction.
24262 Otherwise set it. */
24264 insn
&= ~(1 << 23);
24268 /* Place the absolute value of the addend into the first 12 bits
24269 of the instruction. */
24270 insn
&= 0xfffff000;
24271 insn
|= addend_abs
;
24273 /* Update the instruction. */
24274 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24278 case BFD_RELOC_ARM_LDRS_PC_G0
:
24279 case BFD_RELOC_ARM_LDRS_PC_G1
:
24280 case BFD_RELOC_ARM_LDRS_PC_G2
:
24281 case BFD_RELOC_ARM_LDRS_SB_G0
:
24282 case BFD_RELOC_ARM_LDRS_SB_G1
:
24283 case BFD_RELOC_ARM_LDRS_SB_G2
:
24284 gas_assert (!fixP
->fx_done
);
24285 if (!seg
->use_rela_p
)
24288 bfd_vma addend_abs
= abs (value
);
24290 /* Check that the absolute value of the addend can be
24291 encoded in 8 bits. */
24292 if (addend_abs
>= 0x100)
24293 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24294 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24295 (unsigned long) addend_abs
);
24297 /* Extract the instruction. */
24298 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24300 /* If the addend is negative, clear bit 23 of the instruction.
24301 Otherwise set it. */
24303 insn
&= ~(1 << 23);
24307 /* Place the first four bits of the absolute value of the addend
24308 into the first 4 bits of the instruction, and the remaining
24309 four into bits 8 .. 11. */
24310 insn
&= 0xfffff0f0;
24311 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24313 /* Update the instruction. */
24314 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24318 case BFD_RELOC_ARM_LDC_PC_G0
:
24319 case BFD_RELOC_ARM_LDC_PC_G1
:
24320 case BFD_RELOC_ARM_LDC_PC_G2
:
24321 case BFD_RELOC_ARM_LDC_SB_G0
:
24322 case BFD_RELOC_ARM_LDC_SB_G1
:
24323 case BFD_RELOC_ARM_LDC_SB_G2
:
24324 gas_assert (!fixP
->fx_done
);
24325 if (!seg
->use_rela_p
)
24328 bfd_vma addend_abs
= abs (value
);
24330 /* Check that the absolute value of the addend is a multiple of
24331 four and, when divided by four, fits in 8 bits. */
24332 if (addend_abs
& 0x3)
24333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24334 _("bad offset 0x%08lX (must be word-aligned)"),
24335 (unsigned long) addend_abs
);
24337 if ((addend_abs
>> 2) > 0xff)
24338 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24339 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24340 (unsigned long) addend_abs
);
24342 /* Extract the instruction. */
24343 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24345 /* If the addend is negative, clear bit 23 of the instruction.
24346 Otherwise set it. */
24348 insn
&= ~(1 << 23);
24352 /* Place the addend (divided by four) into the first eight
24353 bits of the instruction. */
24354 insn
&= 0xfffffff0;
24355 insn
|= addend_abs
>> 2;
24357 /* Update the instruction. */
24358 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24362 case BFD_RELOC_ARM_V4BX
:
24363 /* This will need to go in the object file. */
24367 case BFD_RELOC_UNUSED
:
24369 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24370 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24374 /* Translate internal representation of relocation info to BFD target
24378 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24381 bfd_reloc_code_real_type code
;
24383 reloc
= XNEW (arelent
);
24385 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24386 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24387 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24389 if (fixp
->fx_pcrel
)
24391 if (section
->use_rela_p
)
24392 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24394 fixp
->fx_offset
= reloc
->address
;
24396 reloc
->addend
= fixp
->fx_offset
;
24398 switch (fixp
->fx_r_type
)
24401 if (fixp
->fx_pcrel
)
24403 code
= BFD_RELOC_8_PCREL
;
24406 /* Fall through. */
24409 if (fixp
->fx_pcrel
)
24411 code
= BFD_RELOC_16_PCREL
;
24414 /* Fall through. */
24417 if (fixp
->fx_pcrel
)
24419 code
= BFD_RELOC_32_PCREL
;
24422 /* Fall through. */
24424 case BFD_RELOC_ARM_MOVW
:
24425 if (fixp
->fx_pcrel
)
24427 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24430 /* Fall through. */
24432 case BFD_RELOC_ARM_MOVT
:
24433 if (fixp
->fx_pcrel
)
24435 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24438 /* Fall through. */
24440 case BFD_RELOC_ARM_THUMB_MOVW
:
24441 if (fixp
->fx_pcrel
)
24443 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24446 /* Fall through. */
24448 case BFD_RELOC_ARM_THUMB_MOVT
:
24449 if (fixp
->fx_pcrel
)
24451 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24454 /* Fall through. */
24456 case BFD_RELOC_NONE
:
24457 case BFD_RELOC_ARM_PCREL_BRANCH
:
24458 case BFD_RELOC_ARM_PCREL_BLX
:
24459 case BFD_RELOC_RVA
:
24460 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24461 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24462 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24463 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24464 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24465 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24466 case BFD_RELOC_VTABLE_ENTRY
:
24467 case BFD_RELOC_VTABLE_INHERIT
:
24469 case BFD_RELOC_32_SECREL
:
24471 code
= fixp
->fx_r_type
;
24474 case BFD_RELOC_THUMB_PCREL_BLX
:
24476 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24477 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24480 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24483 case BFD_RELOC_ARM_LITERAL
:
24484 case BFD_RELOC_ARM_HWLITERAL
:
24485 /* If this is called then the a literal has
24486 been referenced across a section boundary. */
24487 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24488 _("literal referenced across section boundary"));
24492 case BFD_RELOC_ARM_TLS_CALL
:
24493 case BFD_RELOC_ARM_THM_TLS_CALL
:
24494 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24495 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24496 case BFD_RELOC_ARM_GOT32
:
24497 case BFD_RELOC_ARM_GOTOFF
:
24498 case BFD_RELOC_ARM_GOT_PREL
:
24499 case BFD_RELOC_ARM_PLT32
:
24500 case BFD_RELOC_ARM_TARGET1
:
24501 case BFD_RELOC_ARM_ROSEGREL32
:
24502 case BFD_RELOC_ARM_SBREL32
:
24503 case BFD_RELOC_ARM_PREL31
:
24504 case BFD_RELOC_ARM_TARGET2
:
24505 case BFD_RELOC_ARM_TLS_LDO32
:
24506 case BFD_RELOC_ARM_PCREL_CALL
:
24507 case BFD_RELOC_ARM_PCREL_JUMP
:
24508 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24509 case BFD_RELOC_ARM_ALU_PC_G0
:
24510 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24511 case BFD_RELOC_ARM_ALU_PC_G1
:
24512 case BFD_RELOC_ARM_ALU_PC_G2
:
24513 case BFD_RELOC_ARM_LDR_PC_G0
:
24514 case BFD_RELOC_ARM_LDR_PC_G1
:
24515 case BFD_RELOC_ARM_LDR_PC_G2
:
24516 case BFD_RELOC_ARM_LDRS_PC_G0
:
24517 case BFD_RELOC_ARM_LDRS_PC_G1
:
24518 case BFD_RELOC_ARM_LDRS_PC_G2
:
24519 case BFD_RELOC_ARM_LDC_PC_G0
:
24520 case BFD_RELOC_ARM_LDC_PC_G1
:
24521 case BFD_RELOC_ARM_LDC_PC_G2
:
24522 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24523 case BFD_RELOC_ARM_ALU_SB_G0
:
24524 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24525 case BFD_RELOC_ARM_ALU_SB_G1
:
24526 case BFD_RELOC_ARM_ALU_SB_G2
:
24527 case BFD_RELOC_ARM_LDR_SB_G0
:
24528 case BFD_RELOC_ARM_LDR_SB_G1
:
24529 case BFD_RELOC_ARM_LDR_SB_G2
:
24530 case BFD_RELOC_ARM_LDRS_SB_G0
:
24531 case BFD_RELOC_ARM_LDRS_SB_G1
:
24532 case BFD_RELOC_ARM_LDRS_SB_G2
:
24533 case BFD_RELOC_ARM_LDC_SB_G0
:
24534 case BFD_RELOC_ARM_LDC_SB_G1
:
24535 case BFD_RELOC_ARM_LDC_SB_G2
:
24536 case BFD_RELOC_ARM_V4BX
:
24537 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24538 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24539 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24540 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24541 code
= fixp
->fx_r_type
;
24544 case BFD_RELOC_ARM_TLS_GOTDESC
:
24545 case BFD_RELOC_ARM_TLS_GD32
:
24546 case BFD_RELOC_ARM_TLS_LE32
:
24547 case BFD_RELOC_ARM_TLS_IE32
:
24548 case BFD_RELOC_ARM_TLS_LDM32
:
24549 /* BFD will include the symbol's address in the addend.
24550 But we don't want that, so subtract it out again here. */
24551 if (!S_IS_COMMON (fixp
->fx_addsy
))
24552 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24553 code
= fixp
->fx_r_type
;
24557 case BFD_RELOC_ARM_IMMEDIATE
:
24558 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24559 _("internal relocation (type: IMMEDIATE) not fixed up"));
24562 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24563 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24564 _("ADRL used for a symbol not defined in the same file"));
24567 case BFD_RELOC_ARM_OFFSET_IMM
:
24568 if (section
->use_rela_p
)
24570 code
= fixp
->fx_r_type
;
24574 if (fixp
->fx_addsy
!= NULL
24575 && !S_IS_DEFINED (fixp
->fx_addsy
)
24576 && S_IS_LOCAL (fixp
->fx_addsy
))
24578 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24579 _("undefined local label `%s'"),
24580 S_GET_NAME (fixp
->fx_addsy
));
24584 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24585 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24592 switch (fixp
->fx_r_type
)
24594 case BFD_RELOC_NONE
: type
= "NONE"; break;
24595 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24596 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24597 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24598 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24599 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24600 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24601 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24602 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24603 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24604 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24605 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24606 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24607 default: type
= _("<unknown>"); break;
24609 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24610 _("cannot represent %s relocation in this object file format"),
24617 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24619 && fixp
->fx_addsy
== GOT_symbol
)
24621 code
= BFD_RELOC_ARM_GOTPC
;
24622 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24626 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24628 if (reloc
->howto
== NULL
)
24630 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24631 _("cannot represent %s relocation in this object file format"),
24632 bfd_get_reloc_code_name (code
));
24636 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24637 vtable entry to be used in the relocation's section offset. */
24638 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24639 reloc
->address
= fixp
->fx_offset
;
24644 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24647 cons_fix_new_arm (fragS
* frag
,
24651 bfd_reloc_code_real_type reloc
)
24656 FIXME: @@ Should look at CPU word size. */
24660 reloc
= BFD_RELOC_8
;
24663 reloc
= BFD_RELOC_16
;
24667 reloc
= BFD_RELOC_32
;
24670 reloc
= BFD_RELOC_64
;
24675 if (exp
->X_op
== O_secrel
)
24677 exp
->X_op
= O_symbol
;
24678 reloc
= BFD_RELOC_32_SECREL
;
24682 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24685 #if defined (OBJ_COFF)
24687 arm_validate_fix (fixS
* fixP
)
24689 /* If the destination of the branch is a defined symbol which does not have
24690 the THUMB_FUNC attribute, then we must be calling a function which has
24691 the (interfacearm) attribute. We look for the Thumb entry point to that
24692 function and change the branch to refer to that function instead. */
24693 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24694 && fixP
->fx_addsy
!= NULL
24695 && S_IS_DEFINED (fixP
->fx_addsy
)
24696 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24698 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24705 arm_force_relocation (struct fix
* fixp
)
24707 #if defined (OBJ_COFF) && defined (TE_PE)
24708 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24712 /* In case we have a call or a branch to a function in ARM ISA mode from
24713 a thumb function or vice-versa force the relocation. These relocations
24714 are cleared off for some cores that might have blx and simple transformations
24718 switch (fixp
->fx_r_type
)
24720 case BFD_RELOC_ARM_PCREL_JUMP
:
24721 case BFD_RELOC_ARM_PCREL_CALL
:
24722 case BFD_RELOC_THUMB_PCREL_BLX
:
24723 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24727 case BFD_RELOC_ARM_PCREL_BLX
:
24728 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24729 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24730 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24731 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24740 /* Resolve these relocations even if the symbol is extern or weak.
24741 Technically this is probably wrong due to symbol preemption.
24742 In practice these relocations do not have enough range to be useful
24743 at dynamic link time, and some code (e.g. in the Linux kernel)
24744 expects these references to be resolved. */
24745 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24746 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24747 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24748 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24749 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24750 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24751 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24752 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24753 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24754 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24755 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24756 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24757 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24758 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24761 /* Always leave these relocations for the linker. */
24762 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24763 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24764 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24767 /* Always generate relocations against function symbols. */
24768 if (fixp
->fx_r_type
== BFD_RELOC_32
24770 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24773 return generic_force_reloc (fixp
);
24776 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24777 /* Relocations against function names must be left unadjusted,
24778 so that the linker can use this information to generate interworking
24779 stubs. The MIPS version of this function
24780 also prevents relocations that are mips-16 specific, but I do not
24781 know why it does this.
24784 There is one other problem that ought to be addressed here, but
24785 which currently is not: Taking the address of a label (rather
24786 than a function) and then later jumping to that address. Such
24787 addresses also ought to have their bottom bit set (assuming that
24788 they reside in Thumb code), but at the moment they will not. */
24791 arm_fix_adjustable (fixS
* fixP
)
24793 if (fixP
->fx_addsy
== NULL
)
24796 /* Preserve relocations against symbols with function type. */
24797 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24800 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24801 && fixP
->fx_subsy
== NULL
)
24804 /* We need the symbol name for the VTABLE entries. */
24805 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24806 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24809 /* Don't allow symbols to be discarded on GOT related relocs. */
24810 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24811 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24812 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24813 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24814 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24815 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24816 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24817 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24818 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24819 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24820 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24821 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24822 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24823 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24826 /* Similarly for group relocations. */
24827 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24828 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24829 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24832 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24833 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24834 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24835 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24836 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24837 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24838 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24839 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24840 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24843 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24844 offsets, so keep these symbols. */
24845 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24846 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24851 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24855 elf32_arm_target_format (void)
24858 return (target_big_endian
24859 ? "elf32-bigarm-symbian"
24860 : "elf32-littlearm-symbian");
24861 #elif defined (TE_VXWORKS)
24862 return (target_big_endian
24863 ? "elf32-bigarm-vxworks"
24864 : "elf32-littlearm-vxworks");
24865 #elif defined (TE_NACL)
24866 return (target_big_endian
24867 ? "elf32-bigarm-nacl"
24868 : "elf32-littlearm-nacl");
24870 if (target_big_endian
)
24871 return "elf32-bigarm";
24873 return "elf32-littlearm";
24878 armelf_frob_symbol (symbolS
* symp
,
24881 elf_frob_symbol (symp
, puntp
);
24885 /* MD interface: Finalization. */
24890 literal_pool
* pool
;
24892 /* Ensure that all the IT blocks are properly closed. */
24893 check_it_blocks_finished ();
24895 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24897 /* Put it at the end of the relevant section. */
24898 subseg_set (pool
->section
, pool
->sub_section
);
24900 arm_elf_change_section ();
24907 /* Remove any excess mapping symbols generated for alignment frags in
24908 SEC. We may have created a mapping symbol before a zero byte
24909 alignment; remove it if there's a mapping symbol after the
24912 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24913 void *dummy ATTRIBUTE_UNUSED
)
24915 segment_info_type
*seginfo
= seg_info (sec
);
24918 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24921 for (fragp
= seginfo
->frchainP
->frch_root
;
24923 fragp
= fragp
->fr_next
)
24925 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24926 fragS
*next
= fragp
->fr_next
;
24928 /* Variable-sized frags have been converted to fixed size by
24929 this point. But if this was variable-sized to start with,
24930 there will be a fixed-size frag after it. So don't handle
24932 if (sym
== NULL
|| next
== NULL
)
24935 if (S_GET_VALUE (sym
) < next
->fr_address
)
24936 /* Not at the end of this frag. */
24938 know (S_GET_VALUE (sym
) == next
->fr_address
);
24942 if (next
->tc_frag_data
.first_map
!= NULL
)
24944 /* Next frag starts with a mapping symbol. Discard this
24946 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24950 if (next
->fr_next
== NULL
)
24952 /* This mapping symbol is at the end of the section. Discard
24954 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24955 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24959 /* As long as we have empty frags without any mapping symbols,
24961 /* If the next frag is non-empty and does not start with a
24962 mapping symbol, then this mapping symbol is required. */
24963 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24966 next
= next
->fr_next
;
24968 while (next
!= NULL
);
24973 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24977 arm_adjust_symtab (void)
24982 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24984 if (ARM_IS_THUMB (sym
))
24986 if (THUMB_IS_FUNC (sym
))
24988 /* Mark the symbol as a Thumb function. */
24989 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24990 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24991 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24993 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24994 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24996 as_bad (_("%s: unexpected function type: %d"),
24997 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24999 else switch (S_GET_STORAGE_CLASS (sym
))
25002 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
25005 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
25008 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25016 if (ARM_IS_INTERWORK (sym
))
25017 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25024 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25026 if (ARM_IS_THUMB (sym
))
25028 elf_symbol_type
* elf_sym
;
25030 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25031 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25033 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25034 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25036 /* If it's a .thumb_func, declare it as so,
25037 otherwise tag label as .code 16. */
25038 if (THUMB_IS_FUNC (sym
))
25039 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25040 ST_BRANCH_TO_THUMB
);
25041 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25042 elf_sym
->internal_elf_sym
.st_info
=
25043 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
25048 /* Remove any overlapping mapping symbols generated by alignment frags. */
25049 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
25050 /* Now do generic ELF adjustments. */
25051 elf_adjust_symtab ();
25055 /* MD interface: Initialization. */
25058 set_constant_flonums (void)
25062 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
25063 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
25067 /* Auto-select Thumb mode if it's the only available instruction set for the
25068 given architecture. */
25071 autoselect_thumb_from_cpu_variant (void)
25073 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
25074 opcode_select (16);
25083 if ( (arm_ops_hsh
= hash_new ()) == NULL
25084 || (arm_cond_hsh
= hash_new ()) == NULL
25085 || (arm_shift_hsh
= hash_new ()) == NULL
25086 || (arm_psr_hsh
= hash_new ()) == NULL
25087 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
25088 || (arm_reg_hsh
= hash_new ()) == NULL
25089 || (arm_reloc_hsh
= hash_new ()) == NULL
25090 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
25091 as_fatal (_("virtual memory exhausted"));
25093 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
25094 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
25095 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
25096 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
25097 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
25098 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
25099 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
25100 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
25101 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25102 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25103 (void *) (v7m_psrs
+ i
));
25104 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25105 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25107 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25109 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25110 (void *) (barrier_opt_names
+ i
));
25112 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25114 struct reloc_entry
* entry
= reloc_names
+ i
;
25116 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25117 /* This makes encode_branch() use the EABI versions of this relocation. */
25118 entry
->reloc
= BFD_RELOC_UNUSED
;
25120 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25124 set_constant_flonums ();
25126 /* Set the cpu variant based on the command-line options. We prefer
25127 -mcpu= over -march= if both are set (as for GCC); and we prefer
25128 -mfpu= over any other way of setting the floating point unit.
25129 Use of legacy options with new options are faulted. */
25132 if (mcpu_cpu_opt
|| march_cpu_opt
)
25133 as_bad (_("use of old and new-style options to set CPU type"));
25135 mcpu_cpu_opt
= legacy_cpu
;
25137 else if (!mcpu_cpu_opt
)
25139 mcpu_cpu_opt
= march_cpu_opt
;
25140 dyn_mcpu_ext_opt
= dyn_march_ext_opt
;
25141 /* Avoid double free in arm_md_end. */
25142 dyn_march_ext_opt
= NULL
;
25148 as_bad (_("use of old and new-style options to set FPU type"));
25150 mfpu_opt
= legacy_fpu
;
25152 else if (!mfpu_opt
)
25154 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25155 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25156 /* Some environments specify a default FPU. If they don't, infer it
25157 from the processor. */
25159 mfpu_opt
= mcpu_fpu_opt
;
25161 mfpu_opt
= march_fpu_opt
;
25163 mfpu_opt
= &fpu_default
;
25169 if (mcpu_cpu_opt
!= NULL
)
25170 mfpu_opt
= &fpu_default
;
25171 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
25172 mfpu_opt
= &fpu_arch_vfp_v2
;
25174 mfpu_opt
= &fpu_arch_fpa
;
25180 mcpu_cpu_opt
= &cpu_default
;
25181 selected_cpu
= cpu_default
;
25183 else if (dyn_mcpu_ext_opt
)
25184 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25186 selected_cpu
= *mcpu_cpu_opt
;
25188 if (mcpu_cpu_opt
&& dyn_mcpu_ext_opt
)
25189 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25190 else if (mcpu_cpu_opt
)
25191 selected_cpu
= *mcpu_cpu_opt
;
25193 mcpu_cpu_opt
= &arm_arch_any
;
25196 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25197 if (dyn_mcpu_ext_opt
)
25198 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
25200 autoselect_thumb_from_cpu_variant ();
25202 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25204 #if defined OBJ_COFF || defined OBJ_ELF
25206 unsigned int flags
= 0;
25208 #if defined OBJ_ELF
25209 flags
= meabi_flags
;
25211 switch (meabi_flags
)
25213 case EF_ARM_EABI_UNKNOWN
:
25215 /* Set the flags in the private structure. */
25216 if (uses_apcs_26
) flags
|= F_APCS26
;
25217 if (support_interwork
) flags
|= F_INTERWORK
;
25218 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25219 if (pic_code
) flags
|= F_PIC
;
25220 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25221 flags
|= F_SOFT_FLOAT
;
25223 switch (mfloat_abi_opt
)
25225 case ARM_FLOAT_ABI_SOFT
:
25226 case ARM_FLOAT_ABI_SOFTFP
:
25227 flags
|= F_SOFT_FLOAT
;
25230 case ARM_FLOAT_ABI_HARD
:
25231 if (flags
& F_SOFT_FLOAT
)
25232 as_bad (_("hard-float conflicts with specified fpu"));
25236 /* Using pure-endian doubles (even if soft-float). */
25237 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25238 flags
|= F_VFP_FLOAT
;
25240 #if defined OBJ_ELF
25241 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25242 flags
|= EF_ARM_MAVERICK_FLOAT
;
25245 case EF_ARM_EABI_VER4
:
25246 case EF_ARM_EABI_VER5
:
25247 /* No additional flags to set. */
25254 bfd_set_private_flags (stdoutput
, flags
);
25256 /* We have run out flags in the COFF header to encode the
25257 status of ATPCS support, so instead we create a dummy,
25258 empty, debug section called .arm.atpcs. */
25263 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25267 bfd_set_section_flags
25268 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25269 bfd_set_section_size (stdoutput
, sec
, 0);
25270 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25276 /* Record the CPU type as well. */
25277 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25278 mach
= bfd_mach_arm_iWMMXt2
;
25279 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25280 mach
= bfd_mach_arm_iWMMXt
;
25281 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25282 mach
= bfd_mach_arm_XScale
;
25283 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25284 mach
= bfd_mach_arm_ep9312
;
25285 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25286 mach
= bfd_mach_arm_5TE
;
25287 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25289 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25290 mach
= bfd_mach_arm_5T
;
25292 mach
= bfd_mach_arm_5
;
25294 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25296 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25297 mach
= bfd_mach_arm_4T
;
25299 mach
= bfd_mach_arm_4
;
25301 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25302 mach
= bfd_mach_arm_3M
;
25303 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25304 mach
= bfd_mach_arm_3
;
25305 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25306 mach
= bfd_mach_arm_2a
;
25307 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25308 mach
= bfd_mach_arm_2
;
25310 mach
= bfd_mach_arm_unknown
;
25312 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25315 /* Command line processing. */
25318 Invocation line includes a switch not recognized by the base assembler.
25319 See if it's a processor-specific option.
25321 This routine is somewhat complicated by the need for backwards
25322 compatibility (since older releases of gcc can't be changed).
25323 The new options try to make the interface as compatible as
25326 New options (supported) are:
25328 -mcpu=<cpu name> Assemble for selected processor
25329 -march=<architecture name> Assemble for selected architecture
25330 -mfpu=<fpu architecture> Assemble for selected FPU.
25331 -EB/-mbig-endian Big-endian
25332 -EL/-mlittle-endian Little-endian
25333 -k Generate PIC code
25334 -mthumb Start in Thumb mode
25335 -mthumb-interwork Code supports ARM/Thumb interworking
25337 -m[no-]warn-deprecated Warn about deprecated features
25338 -m[no-]warn-syms Warn when symbols match instructions
25340 For now we will also provide support for:
25342 -mapcs-32 32-bit Program counter
25343 -mapcs-26 26-bit Program counter
25344 -macps-float Floats passed in FP registers
25345 -mapcs-reentrant Reentrant code
25347 (sometime these will probably be replaced with -mapcs=<list of options>
25348 and -matpcs=<list of options>)
25350 The remaining options are only supported for back-wards compatibility.
25351 Cpu variants, the arm part is optional:
25352 -m[arm]1 Currently not supported.
25353 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25354 -m[arm]3 Arm 3 processor
25355 -m[arm]6[xx], Arm 6 processors
25356 -m[arm]7[xx][t][[d]m] Arm 7 processors
25357 -m[arm]8[10] Arm 8 processors
25358 -m[arm]9[20][tdmi] Arm 9 processors
25359 -mstrongarm[110[0]] StrongARM processors
25360 -mxscale XScale processors
25361 -m[arm]v[2345[t[e]]] Arm architectures
25362 -mall All (except the ARM1)
25364 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25365 -mfpe-old (No float load/store multiples)
25366 -mvfpxd VFP Single precision
25368 -mno-fpu Disable all floating point instructions
25370 The following CPU names are recognized:
25371 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25372 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25373 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25374 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25375 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25376 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25377 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25381 const char * md_shortopts
= "m:k";
25383 #ifdef ARM_BI_ENDIAN
25384 #define OPTION_EB (OPTION_MD_BASE + 0)
25385 #define OPTION_EL (OPTION_MD_BASE + 1)
25387 #if TARGET_BYTES_BIG_ENDIAN
25388 #define OPTION_EB (OPTION_MD_BASE + 0)
25390 #define OPTION_EL (OPTION_MD_BASE + 1)
25393 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25395 struct option md_longopts
[] =
25398 {"EB", no_argument
, NULL
, OPTION_EB
},
25401 {"EL", no_argument
, NULL
, OPTION_EL
},
25403 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25404 {NULL
, no_argument
, NULL
, 0}
25408 size_t md_longopts_size
= sizeof (md_longopts
);
25410 struct arm_option_table
25412 const char *option
; /* Option name to match. */
25413 const char *help
; /* Help information. */
25414 int *var
; /* Variable to change. */
25415 int value
; /* What to change it to. */
25416 const char *deprecated
; /* If non-null, print this message. */
25419 struct arm_option_table arm_opts
[] =
25421 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25422 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25423 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25424 &support_interwork
, 1, NULL
},
25425 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25426 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25427 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25429 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25430 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25431 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25432 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25435 /* These are recognized by the assembler, but have no affect on code. */
25436 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25437 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25439 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25440 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25441 &warn_on_deprecated
, 0, NULL
},
25442 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25443 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25444 {NULL
, NULL
, NULL
, 0, NULL
}
25447 struct arm_legacy_option_table
25449 const char *option
; /* Option name to match. */
25450 const arm_feature_set
**var
; /* Variable to change. */
25451 const arm_feature_set value
; /* What to change it to. */
25452 const char *deprecated
; /* If non-null, print this message. */
25455 const struct arm_legacy_option_table arm_legacy_opts
[] =
25457 /* DON'T add any new processors to this list -- we want the whole list
25458 to go away... Add them to the processors table instead. */
25459 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25460 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25461 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25462 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25463 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25464 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25465 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25466 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25467 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25468 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25469 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25470 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25471 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25472 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25473 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25474 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25475 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25476 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25477 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25478 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25479 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25480 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25481 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25482 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25483 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25484 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25485 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25486 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25487 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25488 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25489 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25490 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25491 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25492 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25493 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25494 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25495 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25496 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25497 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25498 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25499 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25500 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25501 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25502 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25503 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25504 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25505 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25506 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25507 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25508 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25509 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25510 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25511 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25512 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25513 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25514 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25515 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25516 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25517 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25518 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25519 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25520 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25521 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25522 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25523 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25524 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25525 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25526 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25527 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25528 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25529 N_("use -mcpu=strongarm110")},
25530 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25531 N_("use -mcpu=strongarm1100")},
25532 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25533 N_("use -mcpu=strongarm1110")},
25534 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25535 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25536 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25538 /* Architecture variants -- don't add any more to this list either. */
25539 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25540 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25541 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25542 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25543 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25544 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25545 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25546 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25547 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25548 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25549 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25550 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25551 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25552 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25553 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25554 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25555 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25556 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25558 /* Floating point variants -- don't add any more to this list either. */
25559 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25560 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25561 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25562 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25563 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25565 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25568 struct arm_cpu_option_table
25572 const arm_feature_set value
;
25573 const arm_feature_set ext
;
25574 /* For some CPUs we assume an FPU unless the user explicitly sets
25576 const arm_feature_set default_fpu
;
25577 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25579 const char *canonical_name
;
25582 /* This list should, at a minimum, contain all the cpu names
25583 recognized by GCC. */
25584 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25585 static const struct arm_cpu_option_table arm_cpus
[] =
25587 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
25590 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
25593 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
25596 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
25599 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
25602 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
25605 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
25608 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
25611 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
25614 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
25617 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
25620 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
25623 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
25626 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
25629 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
25632 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
25635 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
25638 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
25641 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
25644 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
25647 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
25650 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
25653 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
25656 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
25659 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
25662 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
25665 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
25668 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
25671 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
25674 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
25677 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
25680 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
25683 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
25686 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
25689 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
25692 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
25695 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
25698 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
25701 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
25704 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
25707 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
25710 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
25713 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
25716 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
25719 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
25722 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
25726 /* For V5 or later processors we default to using VFP; but the user
25727 should really set the FPU type explicitly. */
25728 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
25731 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
25734 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25737 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25740 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
25743 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
25746 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
25749 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
25752 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
25755 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
25758 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
25761 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
25764 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
25767 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
25770 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
25773 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
25776 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
25779 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
25782 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
25785 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
25788 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
25791 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
25794 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
25797 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
25800 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
25803 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
25806 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
25809 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
25812 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
25815 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
25818 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
25821 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
25824 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
25827 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
25830 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
25833 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
25836 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
25837 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25839 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
25841 FPU_ARCH_NEON_VFP_V4
),
25842 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
25843 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25844 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
25845 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
25846 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25847 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
25848 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
25850 FPU_ARCH_NEON_VFP_V4
),
25851 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
25853 FPU_ARCH_NEON_VFP_V4
),
25854 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
25856 FPU_ARCH_NEON_VFP_V4
),
25857 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
25858 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25859 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25860 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
25861 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25862 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25863 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
25864 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25865 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25866 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
25867 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25868 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25869 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
25870 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25871 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25872 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
25873 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25874 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25875 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
25876 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25877 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25878 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
25879 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25880 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25881 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
25884 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
25886 FPU_ARCH_VFP_V3D16
),
25887 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
25888 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25890 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
25891 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25892 FPU_ARCH_VFP_V3D16
),
25893 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
25894 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
25895 FPU_ARCH_VFP_V3D16
),
25896 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
25897 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25898 FPU_ARCH_NEON_VFP_ARMV8
),
25899 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
25900 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25902 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
25905 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
25908 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
25911 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
25914 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
25917 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
25920 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
25923 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
25924 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25925 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25927 /* ??? XSCALE is really an architecture. */
25928 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
25932 /* ??? iwmmxt is not a processor. */
25933 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
25936 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
25939 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
25944 ARM_CPU_OPT ("ep9312", "ARM920T",
25945 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25946 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
25948 /* Marvell processors. */
25949 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
25950 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25951 FPU_ARCH_VFP_V3D16
),
25952 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
25953 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
25954 FPU_ARCH_NEON_VFP_V4
),
25956 /* APM X-Gene family. */
25957 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
25959 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25960 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
25961 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25962 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
25964 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25968 struct arm_arch_option_table
25972 const arm_feature_set value
;
25973 const arm_feature_set default_fpu
;
25976 /* This list should, at a minimum, contain all the architecture names
25977 recognized by GCC. */
25978 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25979 static const struct arm_arch_option_table arm_archs
[] =
25981 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25982 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25983 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25984 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25985 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25986 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25987 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25988 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25989 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25990 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25991 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25992 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25993 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25994 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25995 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25996 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25997 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25998 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25999 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
26000 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
26001 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
26002 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
26003 kept to preserve existing behaviour. */
26004 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26005 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26006 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
26007 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
26008 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
26009 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
26010 kept to preserve existing behaviour. */
26011 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26012 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26013 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
26014 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
26015 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
26016 /* The official spelling of the ARMv7 profile variants is the dashed form.
26017 Accept the non-dashed form for compatibility with old toolchains. */
26018 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26019 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
26020 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26021 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26022 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26023 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26024 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26025 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
26026 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
26027 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
26028 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
26029 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
26030 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
26031 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
26032 ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
),
26033 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
26034 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
26035 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
26036 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26038 #undef ARM_ARCH_OPT
26040 /* ISA extensions in the co-processor and main instruction set space. */
26041 struct arm_option_extension_value_table
26045 const arm_feature_set merge_value
;
26046 const arm_feature_set clear_value
;
26047 /* List of architectures for which an extension is available. ARM_ARCH_NONE
26048 indicates that an extension is available for all architectures while
26049 ARM_ANY marks an empty entry. */
26050 const arm_feature_set allowed_archs
[2];
26053 /* The following table must be in alphabetical order with a NULL last entry.
26055 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
26056 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
26057 static const struct arm_option_extension_value_table arm_extensions
[] =
26059 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26060 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26061 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26062 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
26063 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26064 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
26065 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
26067 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26068 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26069 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
26070 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
26071 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26072 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26073 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26075 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26076 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26077 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26078 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26079 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
26080 Thumb divide instruction. Due to this having the same name as the
26081 previous entry, this will be ignored when doing command-line parsing and
26082 only considered by build attribute selection code. */
26083 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26084 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26085 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
26086 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
26087 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
26088 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
26089 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
26090 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
26091 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
26092 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26093 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26094 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26095 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26096 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26097 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26098 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
26099 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
26100 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
26101 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26102 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
26103 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
26104 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26105 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
26106 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
26107 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26108 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26109 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26110 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
26111 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26112 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
26113 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
26114 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26115 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
26117 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
26118 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26119 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
26120 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
26121 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
26125 /* ISA floating-point and Advanced SIMD extensions. */
26126 struct arm_option_fpu_value_table
26129 const arm_feature_set value
;
26132 /* This list should, at a minimum, contain all the fpu names
26133 recognized by GCC. */
26134 static const struct arm_option_fpu_value_table arm_fpus
[] =
26136 {"softfpa", FPU_NONE
},
26137 {"fpe", FPU_ARCH_FPE
},
26138 {"fpe2", FPU_ARCH_FPE
},
26139 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26140 {"fpa", FPU_ARCH_FPA
},
26141 {"fpa10", FPU_ARCH_FPA
},
26142 {"fpa11", FPU_ARCH_FPA
},
26143 {"arm7500fe", FPU_ARCH_FPA
},
26144 {"softvfp", FPU_ARCH_VFP
},
26145 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
26146 {"vfp", FPU_ARCH_VFP_V2
},
26147 {"vfp9", FPU_ARCH_VFP_V2
},
26148 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
26149 {"vfp10", FPU_ARCH_VFP_V2
},
26150 {"vfp10-r0", FPU_ARCH_VFP_V1
},
26151 {"vfpxd", FPU_ARCH_VFP_V1xD
},
26152 {"vfpv2", FPU_ARCH_VFP_V2
},
26153 {"vfpv3", FPU_ARCH_VFP_V3
},
26154 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
26155 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
26156 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
26157 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
26158 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
26159 {"arm1020t", FPU_ARCH_VFP_V1
},
26160 {"arm1020e", FPU_ARCH_VFP_V2
},
26161 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
26162 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
26163 {"maverick", FPU_ARCH_MAVERICK
},
26164 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26165 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26166 {"neon-fp16", FPU_ARCH_NEON_FP16
},
26167 {"vfpv4", FPU_ARCH_VFP_V4
},
26168 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
26169 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
26170 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
26171 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
26172 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
26173 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
26174 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
26175 {"crypto-neon-fp-armv8",
26176 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
26177 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
26178 {"crypto-neon-fp-armv8.1",
26179 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
26180 {NULL
, ARM_ARCH_NONE
}
26183 struct arm_option_value_table
26189 static const struct arm_option_value_table arm_float_abis
[] =
26191 {"hard", ARM_FLOAT_ABI_HARD
},
26192 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
26193 {"soft", ARM_FLOAT_ABI_SOFT
},
26198 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26199 static const struct arm_option_value_table arm_eabis
[] =
26201 {"gnu", EF_ARM_EABI_UNKNOWN
},
26202 {"4", EF_ARM_EABI_VER4
},
26203 {"5", EF_ARM_EABI_VER5
},
26208 struct arm_long_option_table
26210 const char * option
; /* Substring to match. */
26211 const char * help
; /* Help information. */
26212 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
26213 const char * deprecated
; /* If non-null, print this message. */
26217 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
26218 arm_feature_set
**ext_set_p
)
26220 /* We insist on extensions being specified in alphabetical order, and with
26221 extensions being added before being removed. We achieve this by having
26222 the global ARM_EXTENSIONS table in alphabetical order, and using the
26223 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26224 or removing it (0) and only allowing it to change in the order
26226 const struct arm_option_extension_value_table
* opt
= NULL
;
26227 const arm_feature_set arm_any
= ARM_ANY
;
26228 int adding_value
= -1;
26232 *ext_set_p
= XNEW (arm_feature_set
);
26233 **ext_set_p
= arm_arch_none
;
26236 while (str
!= NULL
&& *str
!= 0)
26243 as_bad (_("invalid architectural extension"));
26248 ext
= strchr (str
, '+');
26253 len
= strlen (str
);
26255 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
26257 if (adding_value
!= 0)
26260 opt
= arm_extensions
;
26268 if (adding_value
== -1)
26271 opt
= arm_extensions
;
26273 else if (adding_value
!= 1)
26275 as_bad (_("must specify extensions to add before specifying "
26276 "those to remove"));
26283 as_bad (_("missing architectural extension"));
26287 gas_assert (adding_value
!= -1);
26288 gas_assert (opt
!= NULL
);
26290 /* Scan over the options table trying to find an exact match. */
26291 for (; opt
->name
!= NULL
; opt
++)
26292 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26294 int i
, nb_allowed_archs
=
26295 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26296 /* Check we can apply the extension to this architecture. */
26297 for (i
= 0; i
< nb_allowed_archs
; i
++)
26300 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26302 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
26305 if (i
== nb_allowed_archs
)
26307 as_bad (_("extension does not apply to the base architecture"));
26311 /* Add or remove the extension. */
26313 ARM_MERGE_FEATURE_SETS (**ext_set_p
, **ext_set_p
,
26316 ARM_CLEAR_FEATURE (**ext_set_p
, **ext_set_p
, opt
->clear_value
);
26318 /* Allowing Thumb division instructions for ARMv7 in autodetection
26319 rely on this break so that duplicate extensions (extensions
26320 with the same name as a previous extension in the list) are not
26321 considered for command-line parsing. */
26325 if (opt
->name
== NULL
)
26327 /* Did we fail to find an extension because it wasn't specified in
26328 alphabetical order, or because it does not exist? */
26330 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26331 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26334 if (opt
->name
== NULL
)
26335 as_bad (_("unknown architectural extension `%s'"), str
);
26337 as_bad (_("architectural extensions must be specified in "
26338 "alphabetical order"));
26344 /* We should skip the extension we've just matched the next time
26356 arm_parse_cpu (const char *str
)
26358 const struct arm_cpu_option_table
*opt
;
26359 const char *ext
= strchr (str
, '+');
26365 len
= strlen (str
);
26369 as_bad (_("missing cpu name `%s'"), str
);
26373 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26374 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26376 mcpu_cpu_opt
= &opt
->value
;
26377 if (!dyn_mcpu_ext_opt
)
26378 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
26379 *dyn_mcpu_ext_opt
= opt
->ext
;
26380 mcpu_fpu_opt
= &opt
->default_fpu
;
26381 if (opt
->canonical_name
)
26383 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26384 strcpy (selected_cpu_name
, opt
->canonical_name
);
26390 if (len
>= sizeof selected_cpu_name
)
26391 len
= (sizeof selected_cpu_name
) - 1;
26393 for (i
= 0; i
< len
; i
++)
26394 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26395 selected_cpu_name
[i
] = 0;
26399 return arm_parse_extension (ext
, mcpu_cpu_opt
, &dyn_mcpu_ext_opt
);
26404 as_bad (_("unknown cpu `%s'"), str
);
26409 arm_parse_arch (const char *str
)
26411 const struct arm_arch_option_table
*opt
;
26412 const char *ext
= strchr (str
, '+');
26418 len
= strlen (str
);
26422 as_bad (_("missing architecture name `%s'"), str
);
26426 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26427 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26429 march_cpu_opt
= &opt
->value
;
26430 march_fpu_opt
= &opt
->default_fpu
;
26431 strcpy (selected_cpu_name
, opt
->name
);
26434 return arm_parse_extension (ext
, march_cpu_opt
, &dyn_march_ext_opt
);
26439 as_bad (_("unknown architecture `%s'\n"), str
);
26444 arm_parse_fpu (const char * str
)
26446 const struct arm_option_fpu_value_table
* opt
;
26448 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26449 if (streq (opt
->name
, str
))
26451 mfpu_opt
= &opt
->value
;
26455 as_bad (_("unknown floating point format `%s'\n"), str
);
26460 arm_parse_float_abi (const char * str
)
26462 const struct arm_option_value_table
* opt
;
26464 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26465 if (streq (opt
->name
, str
))
26467 mfloat_abi_opt
= opt
->value
;
26471 as_bad (_("unknown floating point abi `%s'\n"), str
);
26477 arm_parse_eabi (const char * str
)
26479 const struct arm_option_value_table
*opt
;
26481 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26482 if (streq (opt
->name
, str
))
26484 meabi_flags
= opt
->value
;
26487 as_bad (_("unknown EABI `%s'\n"), str
);
26493 arm_parse_it_mode (const char * str
)
26495 bfd_boolean ret
= TRUE
;
26497 if (streq ("arm", str
))
26498 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26499 else if (streq ("thumb", str
))
26500 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26501 else if (streq ("always", str
))
26502 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26503 else if (streq ("never", str
))
26504 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26507 as_bad (_("unknown implicit IT mode `%s', should be "\
26508 "arm, thumb, always, or never."), str
);
26516 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26518 codecomposer_syntax
= TRUE
;
26519 arm_comment_chars
[0] = ';';
26520 arm_line_separator_chars
[0] = 0;
26524 struct arm_long_option_table arm_long_opts
[] =
26526 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26527 arm_parse_cpu
, NULL
},
26528 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26529 arm_parse_arch
, NULL
},
26530 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26531 arm_parse_fpu
, NULL
},
26532 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26533 arm_parse_float_abi
, NULL
},
26535 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26536 arm_parse_eabi
, NULL
},
26538 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26539 arm_parse_it_mode
, NULL
},
26540 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26541 arm_ccs_mode
, NULL
},
26542 {NULL
, NULL
, 0, NULL
}
26546 md_parse_option (int c
, const char * arg
)
26548 struct arm_option_table
*opt
;
26549 const struct arm_legacy_option_table
*fopt
;
26550 struct arm_long_option_table
*lopt
;
26556 target_big_endian
= 1;
26562 target_big_endian
= 0;
26566 case OPTION_FIX_V4BX
:
26571 /* Listing option. Just ignore these, we don't support additional
26576 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26578 if (c
== opt
->option
[0]
26579 && ((arg
== NULL
&& opt
->option
[1] == 0)
26580 || streq (arg
, opt
->option
+ 1)))
26582 /* If the option is deprecated, tell the user. */
26583 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26584 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26585 arg
? arg
: "", _(opt
->deprecated
));
26587 if (opt
->var
!= NULL
)
26588 *opt
->var
= opt
->value
;
26594 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26596 if (c
== fopt
->option
[0]
26597 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26598 || streq (arg
, fopt
->option
+ 1)))
26600 /* If the option is deprecated, tell the user. */
26601 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26602 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26603 arg
? arg
: "", _(fopt
->deprecated
));
26605 if (fopt
->var
!= NULL
)
26606 *fopt
->var
= &fopt
->value
;
26612 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26614 /* These options are expected to have an argument. */
26615 if (c
== lopt
->option
[0]
26617 && strncmp (arg
, lopt
->option
+ 1,
26618 strlen (lopt
->option
+ 1)) == 0)
26620 /* If the option is deprecated, tell the user. */
26621 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26622 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26623 _(lopt
->deprecated
));
26625 /* Call the sup-option parser. */
26626 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26637 md_show_usage (FILE * fp
)
26639 struct arm_option_table
*opt
;
26640 struct arm_long_option_table
*lopt
;
26642 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26644 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26645 if (opt
->help
!= NULL
)
26646 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26648 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26649 if (lopt
->help
!= NULL
)
26650 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26654 -EB assemble code for a big-endian cpu\n"));
26659 -EL assemble code for a little-endian cpu\n"));
26663 --fix-v4bx Allow BX in ARMv4 code\n"));
26671 arm_feature_set flags
;
26672 } cpu_arch_ver_table
;
26674 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
26675 chronologically for architectures, with an exception for ARMv6-M and
26676 ARMv6S-M due to legacy reasons. No new architecture should have a
26677 special case. This allows for build attribute selection results to be
26678 stable when new architectures are added. */
26679 static const cpu_arch_ver_table cpu_arch_ver
[] =
26686 {1, ARM_ARCH_V4xM
},
26688 {2, ARM_ARCH_V4TxM
},
26690 {3, ARM_ARCH_V5xM
},
26692 {3, ARM_ARCH_V5TxM
},
26694 {4, ARM_ARCH_V5TExP
},
26695 {4, ARM_ARCH_V5TE
},
26696 {5, ARM_ARCH_V5TEJ
},
26699 {7, ARM_ARCH_V6KZ
},
26701 {8, ARM_ARCH_V6T2
},
26702 {8, ARM_ARCH_V6KT2
},
26703 {8, ARM_ARCH_V6ZT2
},
26704 {8, ARM_ARCH_V6KZT2
},
26706 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
26707 always selected build attributes to match those of ARMv6-M
26708 (resp. ARMv6S-M). However, due to these architectures being a strict
26709 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
26710 would be selected when fully respecting chronology of architectures.
26711 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
26712 move them before ARMv7 architectures. */
26713 {11, ARM_ARCH_V6M
},
26714 {12, ARM_ARCH_V6SM
},
26717 {10, ARM_ARCH_V7A
},
26718 {10, ARM_ARCH_V7R
},
26719 {10, ARM_ARCH_V7M
},
26720 {10, ARM_ARCH_V7VE
},
26721 {13, ARM_ARCH_V7EM
},
26722 {14, ARM_ARCH_V8A
},
26723 {14, ARM_ARCH_V8_1A
},
26724 {14, ARM_ARCH_V8_2A
},
26725 {14, ARM_ARCH_V8_3A
},
26726 {16, ARM_ARCH_V8M_BASE
},
26727 {17, ARM_ARCH_V8M_MAIN
},
26728 {15, ARM_ARCH_V8R
},
26729 {-1, ARM_ARCH_NONE
}
26732 /* Set an attribute if it has not already been set by the user. */
26734 aeabi_set_attribute_int (int tag
, int value
)
26737 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26738 || !attributes_set_explicitly
[tag
])
26739 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26743 aeabi_set_attribute_string (int tag
, const char *value
)
26746 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26747 || !attributes_set_explicitly
[tag
])
26748 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26751 /* Return whether features in the *NEEDED feature set are available via
26752 extensions for the architecture whose feature set is *ARCH_FSET. */
26754 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
26755 const arm_feature_set
*needed
)
26757 int i
, nb_allowed_archs
;
26758 arm_feature_set ext_fset
;
26759 const struct arm_option_extension_value_table
*opt
;
26761 ext_fset
= arm_arch_none
;
26762 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26764 /* Extension does not provide any feature we need. */
26765 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
26769 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26770 for (i
= 0; i
< nb_allowed_archs
; i
++)
26773 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
26776 /* Extension is available, add it. */
26777 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
26778 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
26782 /* Can we enable all features in *needed? */
26783 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
26786 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
26787 a given architecture feature set *ARCH_EXT_FSET including extension feature
26788 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
26789 - if true, check for an exact match of the architecture modulo extensions;
26790 - otherwise, select build attribute value of the first superset
26791 architecture released so that results remains stable when new architectures
26793 For -march/-mcpu=all the build attribute value of the most featureful
26794 architecture is returned. Tag_CPU_arch_profile result is returned in
26797 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
26798 const arm_feature_set
*ext_fset
,
26799 char *profile
, int exact_match
)
26801 arm_feature_set arch_fset
;
26802 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
26804 /* Select most featureful architecture with all its extensions if building
26805 for -march=all as the feature sets used to set build attributes. */
26806 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
26808 /* Force revisiting of decision for each new architecture. */
26809 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8M_MAIN
);
26811 return TAG_CPU_ARCH_V8
;
26814 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
26816 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
26818 arm_feature_set known_arch_fset
;
26820 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
26823 /* Base architecture match user-specified architecture and
26824 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
26825 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
26830 /* Base architecture match user-specified architecture only
26831 (eg. ARMv6-M in the same case as above). Record it in case we
26832 find a match with above condition. */
26833 else if (p_ver_ret
== NULL
26834 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
26840 /* Architecture has all features wanted. */
26841 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
26843 arm_feature_set added_fset
;
26845 /* Compute features added by this architecture over the one
26846 recorded in p_ver_ret. */
26847 if (p_ver_ret
!= NULL
)
26848 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
26850 /* First architecture that match incl. with extensions, or the
26851 only difference in features over the recorded match is
26852 features that were optional and are now mandatory. */
26853 if (p_ver_ret
== NULL
26854 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
26860 else if (p_ver_ret
== NULL
)
26862 arm_feature_set needed_ext_fset
;
26864 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
26866 /* Architecture has all features needed when using some
26867 extensions. Record it and continue searching in case there
26868 exist an architecture providing all needed features without
26869 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
26871 if (have_ext_for_needed_feat_p (&known_arch_fset
,
26878 if (p_ver_ret
== NULL
)
26882 /* Tag_CPU_arch_profile. */
26883 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
26884 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
26885 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
26886 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
26888 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
26890 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
26894 return p_ver_ret
->val
;
26897 /* Set the public EABI object attributes. */
26899 aeabi_set_public_attributes (void)
26904 int fp16_optional
= 0;
26905 int skip_exact_match
= 0;
26906 arm_feature_set flags
, flags_arch
, flags_ext
;
26908 /* Autodetection mode, choose the architecture based the instructions
26910 if (no_cpu_selected ())
26912 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26914 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26915 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26917 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26918 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26920 /* Code run during relaxation relies on selected_cpu being set. */
26921 selected_cpu
= flags
;
26923 /* Otherwise, choose the architecture based on the capabilities of the
26926 flags
= selected_cpu
;
26927 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26929 /* Allow the user to override the reported architecture. */
26932 ARM_CLEAR_FEATURE (flags_arch
, *object_arch
, fpu_any
);
26933 flags_ext
= arm_arch_none
;
26937 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
26938 flags_ext
= dyn_mcpu_ext_opt
? *dyn_mcpu_ext_opt
: arm_arch_none
;
26939 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
26942 /* When this function is run again after relaxation has happened there is no
26943 way to determine whether an architecture or CPU was specified by the user:
26944 - selected_cpu is set above for relaxation to work;
26945 - march_cpu_opt is not set if only -mcpu or .cpu is used;
26946 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
26947 Therefore, if not in -march=all case we first try an exact match and fall
26948 back to autodetection. */
26949 if (!skip_exact_match
)
26950 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
26952 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
26954 as_bad (_("no architecture contains all the instructions used\n"));
26956 /* Tag_CPU_name. */
26957 if (selected_cpu_name
[0])
26961 q
= selected_cpu_name
;
26962 if (strncmp (q
, "armv", 4) == 0)
26967 for (i
= 0; q
[i
]; i
++)
26968 q
[i
] = TOUPPER (q
[i
]);
26970 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26973 /* Tag_CPU_arch. */
26974 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26976 /* Tag_CPU_arch_profile. */
26977 if (profile
!= '\0')
26978 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26980 /* Tag_DSP_extension. */
26981 if (dyn_mcpu_ext_opt
&& ARM_CPU_HAS_FEATURE (*dyn_mcpu_ext_opt
, arm_ext_dsp
))
26982 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26984 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
26985 /* Tag_ARM_ISA_use. */
26986 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26987 || ARM_FEATURE_ZERO (flags_arch
))
26988 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26990 /* Tag_THUMB_ISA_use. */
26991 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26992 || ARM_FEATURE_ZERO (flags_arch
))
26996 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26997 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26999 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
27003 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
27006 /* Tag_VFP_arch. */
27007 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
27008 aeabi_set_attribute_int (Tag_VFP_arch
,
27009 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27011 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
27012 aeabi_set_attribute_int (Tag_VFP_arch
,
27013 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27015 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
27018 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
27020 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
27022 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
27025 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
27026 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
27027 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
27028 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
27029 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
27031 /* Tag_ABI_HardFP_use. */
27032 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
27033 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
27034 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
27036 /* Tag_WMMX_arch. */
27037 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
27038 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
27039 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
27040 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
27042 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
27043 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
27044 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
27045 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
27046 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
27047 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
27049 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
27051 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
27055 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
27060 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
27061 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
27062 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
27066 We set Tag_DIV_use to two when integer divide instructions have been used
27067 in ARM state, or when Thumb integer divide instructions have been used,
27068 but we have no architecture profile set, nor have we any ARM instructions.
27070 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
27071 by the base architecture.
27073 For new architectures we will have to check these tests. */
27074 gas_assert (arch
<= TAG_CPU_ARCH_V8M_MAIN
);
27075 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27076 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
27077 aeabi_set_attribute_int (Tag_DIV_use
, 0);
27078 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
27079 || (profile
== '\0'
27080 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
27081 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
27082 aeabi_set_attribute_int (Tag_DIV_use
, 2);
27084 /* Tag_MP_extension_use. */
27085 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
27086 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
27088 /* Tag Virtualization_use. */
27089 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
27091 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
27094 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
27097 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
27098 finished and free extension feature bits which will not be used anymore. */
27100 arm_md_post_relax (void)
27102 aeabi_set_public_attributes ();
27103 XDELETE (dyn_mcpu_ext_opt
);
27104 dyn_mcpu_ext_opt
= NULL
;
27105 XDELETE (dyn_march_ext_opt
);
27106 dyn_march_ext_opt
= NULL
;
27109 /* Add the default contents for the .ARM.attributes section. */
27113 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
27116 aeabi_set_public_attributes ();
27118 #endif /* OBJ_ELF */
27121 /* Parse a .cpu directive. */
27124 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
27126 const struct arm_cpu_option_table
*opt
;
27130 name
= input_line_pointer
;
27131 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27132 input_line_pointer
++;
27133 saved_char
= *input_line_pointer
;
27134 *input_line_pointer
= 0;
27136 /* Skip the first "all" entry. */
27137 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
27138 if (streq (opt
->name
, name
))
27140 mcpu_cpu_opt
= &opt
->value
;
27141 if (!dyn_mcpu_ext_opt
)
27142 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27143 *dyn_mcpu_ext_opt
= opt
->ext
;
27144 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27145 if (opt
->canonical_name
)
27146 strcpy (selected_cpu_name
, opt
->canonical_name
);
27150 for (i
= 0; opt
->name
[i
]; i
++)
27151 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27153 selected_cpu_name
[i
] = 0;
27155 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27156 if (dyn_mcpu_ext_opt
)
27157 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27158 *input_line_pointer
= saved_char
;
27159 demand_empty_rest_of_line ();
27162 as_bad (_("unknown cpu `%s'"), name
);
27163 *input_line_pointer
= saved_char
;
27164 ignore_rest_of_line ();
27168 /* Parse a .arch directive. */
27171 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
27173 const struct arm_arch_option_table
*opt
;
27177 name
= input_line_pointer
;
27178 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27179 input_line_pointer
++;
27180 saved_char
= *input_line_pointer
;
27181 *input_line_pointer
= 0;
27183 /* Skip the first "all" entry. */
27184 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27185 if (streq (opt
->name
, name
))
27187 mcpu_cpu_opt
= &opt
->value
;
27188 XDELETE (dyn_mcpu_ext_opt
);
27189 dyn_mcpu_ext_opt
= NULL
;
27190 selected_cpu
= *mcpu_cpu_opt
;
27191 strcpy (selected_cpu_name
, opt
->name
);
27192 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27193 *input_line_pointer
= saved_char
;
27194 demand_empty_rest_of_line ();
27198 as_bad (_("unknown architecture `%s'\n"), name
);
27199 *input_line_pointer
= saved_char
;
27200 ignore_rest_of_line ();
27204 /* Parse a .object_arch directive. */
27207 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
27209 const struct arm_arch_option_table
*opt
;
27213 name
= input_line_pointer
;
27214 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27215 input_line_pointer
++;
27216 saved_char
= *input_line_pointer
;
27217 *input_line_pointer
= 0;
27219 /* Skip the first "all" entry. */
27220 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27221 if (streq (opt
->name
, name
))
27223 object_arch
= &opt
->value
;
27224 *input_line_pointer
= saved_char
;
27225 demand_empty_rest_of_line ();
27229 as_bad (_("unknown architecture `%s'\n"), name
);
27230 *input_line_pointer
= saved_char
;
27231 ignore_rest_of_line ();
27234 /* Parse a .arch_extension directive. */
27237 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
27239 const struct arm_option_extension_value_table
*opt
;
27240 const arm_feature_set arm_any
= ARM_ANY
;
27243 int adding_value
= 1;
27245 name
= input_line_pointer
;
27246 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27247 input_line_pointer
++;
27248 saved_char
= *input_line_pointer
;
27249 *input_line_pointer
= 0;
27251 if (strlen (name
) >= 2
27252 && strncmp (name
, "no", 2) == 0)
27258 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27259 if (streq (opt
->name
, name
))
27261 int i
, nb_allowed_archs
=
27262 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
27263 for (i
= 0; i
< nb_allowed_archs
; i
++)
27266 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
27268 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
27272 if (i
== nb_allowed_archs
)
27274 as_bad (_("architectural extension `%s' is not allowed for the "
27275 "current base architecture"), name
);
27279 if (!dyn_mcpu_ext_opt
)
27281 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27282 *dyn_mcpu_ext_opt
= arm_arch_none
;
27285 ARM_MERGE_FEATURE_SETS (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27288 ARM_CLEAR_FEATURE (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27291 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27292 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27293 *input_line_pointer
= saved_char
;
27294 demand_empty_rest_of_line ();
27295 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
27296 on this return so that duplicate extensions (extensions with the
27297 same name as a previous extension in the list) are not considered
27298 for command-line parsing. */
27302 if (opt
->name
== NULL
)
27303 as_bad (_("unknown architecture extension `%s'\n"), name
);
27305 *input_line_pointer
= saved_char
;
27306 ignore_rest_of_line ();
27309 /* Parse a .fpu directive. */
27312 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
27314 const struct arm_option_fpu_value_table
*opt
;
27318 name
= input_line_pointer
;
27319 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27320 input_line_pointer
++;
27321 saved_char
= *input_line_pointer
;
27322 *input_line_pointer
= 0;
27324 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27325 if (streq (opt
->name
, name
))
27327 mfpu_opt
= &opt
->value
;
27328 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27329 if (dyn_mcpu_ext_opt
)
27330 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27331 *input_line_pointer
= saved_char
;
27332 demand_empty_rest_of_line ();
27336 as_bad (_("unknown floating point format `%s'\n"), name
);
27337 *input_line_pointer
= saved_char
;
27338 ignore_rest_of_line ();
27341 /* Copy symbol information. */
27344 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
27346 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
27350 /* Given a symbolic attribute NAME, return the proper integer value.
27351 Returns -1 if the attribute is not known. */
27354 arm_convert_symbolic_attribute (const char *name
)
27356 static const struct
27361 attribute_table
[] =
27363 /* When you modify this table you should
27364 also modify the list in doc/c-arm.texi. */
27365 #define T(tag) {#tag, tag}
27366 T (Tag_CPU_raw_name
),
27369 T (Tag_CPU_arch_profile
),
27370 T (Tag_ARM_ISA_use
),
27371 T (Tag_THUMB_ISA_use
),
27375 T (Tag_Advanced_SIMD_arch
),
27376 T (Tag_PCS_config
),
27377 T (Tag_ABI_PCS_R9_use
),
27378 T (Tag_ABI_PCS_RW_data
),
27379 T (Tag_ABI_PCS_RO_data
),
27380 T (Tag_ABI_PCS_GOT_use
),
27381 T (Tag_ABI_PCS_wchar_t
),
27382 T (Tag_ABI_FP_rounding
),
27383 T (Tag_ABI_FP_denormal
),
27384 T (Tag_ABI_FP_exceptions
),
27385 T (Tag_ABI_FP_user_exceptions
),
27386 T (Tag_ABI_FP_number_model
),
27387 T (Tag_ABI_align_needed
),
27388 T (Tag_ABI_align8_needed
),
27389 T (Tag_ABI_align_preserved
),
27390 T (Tag_ABI_align8_preserved
),
27391 T (Tag_ABI_enum_size
),
27392 T (Tag_ABI_HardFP_use
),
27393 T (Tag_ABI_VFP_args
),
27394 T (Tag_ABI_WMMX_args
),
27395 T (Tag_ABI_optimization_goals
),
27396 T (Tag_ABI_FP_optimization_goals
),
27397 T (Tag_compatibility
),
27398 T (Tag_CPU_unaligned_access
),
27399 T (Tag_FP_HP_extension
),
27400 T (Tag_VFP_HP_extension
),
27401 T (Tag_ABI_FP_16bit_format
),
27402 T (Tag_MPextension_use
),
27404 T (Tag_nodefaults
),
27405 T (Tag_also_compatible_with
),
27406 T (Tag_conformance
),
27408 T (Tag_Virtualization_use
),
27409 T (Tag_DSP_extension
),
27410 /* We deliberately do not include Tag_MPextension_use_legacy. */
27418 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
27419 if (streq (name
, attribute_table
[i
].name
))
27420 return attribute_table
[i
].tag
;
27426 /* Apply sym value for relocations only in the case that they are for
27427 local symbols in the same segment as the fixup and you have the
27428 respective architectural feature for blx and simple switches. */
27430 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
27433 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27434 /* PR 17444: If the local symbol is in a different section then a reloc
27435 will always be generated for it, so applying the symbol value now
27436 will result in a double offset being stored in the relocation. */
27437 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
27438 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
27440 switch (fixP
->fx_r_type
)
27442 case BFD_RELOC_ARM_PCREL_BLX
:
27443 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27444 if (ARM_IS_FUNC (fixP
->fx_addsy
))
27448 case BFD_RELOC_ARM_PCREL_CALL
:
27449 case BFD_RELOC_THUMB_PCREL_BLX
:
27450 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
27461 #endif /* OBJ_ELF */