1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set
*legacy_cpu
= NULL
;
151 static const arm_feature_set
*legacy_fpu
= NULL
;
153 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
154 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
155 static const arm_feature_set
*march_cpu_opt
= NULL
;
156 static const arm_feature_set
*march_fpu_opt
= NULL
;
157 static const arm_feature_set
*mfpu_opt
= NULL
;
159 /* Constants for known architecture features. */
160 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
161 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
162 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
163 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
164 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
165 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
166 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
168 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
171 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
174 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
175 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
176 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
177 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
178 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
179 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
180 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
181 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
182 static const arm_feature_set arm_ext_v4t_5
=
183 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
184 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
185 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
186 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
187 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
188 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
189 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
190 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
192 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
199 static const arm_feature_set arm_arch_any
= ARM_ANY
;
200 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
201 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
202 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
204 static const arm_feature_set arm_cext_iwmmxt
=
205 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
206 static const arm_feature_set arm_cext_xscale
=
207 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
208 static const arm_feature_set arm_cext_maverick
=
209 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
210 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
211 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
212 static const arm_feature_set fpu_vfp_ext_v1xd
=
213 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
214 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
215 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
217 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
218 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
219 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
221 static int mfloat_abi_opt
= -1;
222 /* Record user cpu selection for object attributes. */
223 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
224 /* Must be long enough to hold any of the names in arm_cpus. */
225 static char selected_cpu_name
[16];
228 static int meabi_flags
= EABI_DEFAULT
;
230 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
235 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
236 symbolS
* GOT_symbol
;
239 /* 0: assemble for ARM,
240 1: assemble for Thumb,
241 2: assemble for Thumb even though target CPU does not support thumb
243 static int thumb_mode
= 0;
245 /* If unified_syntax is true, we are processing the new unified
246 ARM/Thumb syntax. Important differences from the old ARM mode:
248 - Immediate operands do not require a # prefix.
249 - Conditional affixes always appear at the end of the
250 instruction. (For backward compatibility, those instructions
251 that formerly had them in the middle, continue to accept them
253 - The IT instruction may appear, and if it does is validated
254 against subsequent conditional affixes. It does not generate
257 Important differences from the old Thumb mode:
259 - Immediate operands do not require a # prefix.
260 - Most of the V6T2 instructions are only available in unified mode.
261 - The .N and .W suffixes are recognized and honored (it is an error
262 if they cannot be honored).
263 - All instructions set the flags if and only if they have an 's' affix.
264 - Conditional affixes may be used. They are validated against
265 preceding IT instructions. Unlike ARM mode, you cannot use a
266 conditional affix except in the scope of an IT instruction. */
268 static bfd_boolean unified_syntax
= FALSE
;
283 enum neon_el_type type
;
287 #define NEON_MAX_TYPE_ELS 4
291 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
298 unsigned long instruction
;
302 /* "uncond_value" is set to the value in place of the conditional field in
303 unconditional versions of the instruction, or -1 if nothing is
306 struct neon_type vectype
;
307 /* Set to the opcode if the instruction needs relaxation.
308 Zero if the instruction is not relaxed. */
312 bfd_reloc_code_real_type type
;
321 struct neon_type_el vectype
;
322 unsigned present
: 1; /* Operand present. */
323 unsigned isreg
: 1; /* Operand was a register. */
324 unsigned immisreg
: 1; /* .imm field is a second register. */
325 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
326 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
327 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
328 instructions. This allows us to disambiguate ARM <-> vector insns. */
329 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
330 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
331 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
332 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
333 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
334 unsigned writeback
: 1; /* Operand has trailing ! */
335 unsigned preind
: 1; /* Preindexed address. */
336 unsigned postind
: 1; /* Postindexed address. */
337 unsigned negative
: 1; /* Index register was negated. */
338 unsigned shifted
: 1; /* Shift applied to operation. */
339 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
343 static struct arm_it inst
;
345 #define NUM_FLOAT_VALS 8
347 const char * fp_const
[] =
349 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
352 /* Number of littlenums required to hold an extended precision number. */
353 #define MAX_LITTLENUMS 6
355 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
365 #define CP_T_X 0x00008000
366 #define CP_T_Y 0x00400000
368 #define CONDS_BIT 0x00100000
369 #define LOAD_BIT 0x00100000
371 #define DOUBLE_LOAD_FLAG 0x00000001
375 const char * template;
379 #define COND_ALWAYS 0xE
383 const char *template;
387 struct asm_barrier_opt
389 const char *template;
393 /* The bit that distinguishes CPSR and SPSR. */
394 #define SPSR_BIT (1 << 22)
396 /* The individual PSR flag bits. */
397 #define PSR_c (1 << 16)
398 #define PSR_x (1 << 17)
399 #define PSR_s (1 << 18)
400 #define PSR_f (1 << 19)
405 bfd_reloc_code_real_type reloc
;
410 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
411 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
416 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
419 /* Bits for DEFINED field in neon_typed_alias. */
420 #define NTA_HASTYPE 1
421 #define NTA_HASINDEX 2
423 struct neon_typed_alias
425 unsigned char defined
;
427 struct neon_type_el eltype
;
430 /* ARM register categories. This includes coprocessor numbers and various
431 architecture extensions' registers. */
457 /* Structure for a hash table entry for a register.
458 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
459 information which states whether a vector type or index is specified (for a
460 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
464 unsigned char number
;
466 unsigned char builtin
;
467 struct neon_typed_alias
*neon
;
470 /* Diagnostics used when we don't get a register of the expected type. */
471 const char *const reg_expected_msgs
[] =
473 N_("ARM register expected"),
474 N_("bad or missing co-processor number"),
475 N_("co-processor register expected"),
476 N_("FPA register expected"),
477 N_("VFP single precision register expected"),
478 N_("VFP/Neon double precision register expected"),
479 N_("Neon quad precision register expected"),
480 N_("VFP single or double precision register expected"),
481 N_("Neon double or quad precision register expected"),
482 N_("VFP single, double or Neon quad precision register expected"),
483 N_("VFP system register expected"),
484 N_("Maverick MVF register expected"),
485 N_("Maverick MVD register expected"),
486 N_("Maverick MVFX register expected"),
487 N_("Maverick MVDX register expected"),
488 N_("Maverick MVAX register expected"),
489 N_("Maverick DSPSC register expected"),
490 N_("iWMMXt data register expected"),
491 N_("iWMMXt control register expected"),
492 N_("iWMMXt scalar register expected"),
493 N_("XScale accumulator register expected"),
496 /* Some well known registers that we refer to directly elsewhere. */
501 /* ARM instructions take 4bytes in the object file, Thumb instructions
507 /* Basic string to match. */
508 const char *template;
510 /* Parameters to instruction. */
511 unsigned char operands
[8];
513 /* Conditional tag - see opcode_lookup. */
514 unsigned int tag
: 4;
516 /* Basic instruction code. */
517 unsigned int avalue
: 28;
519 /* Thumb-format instruction code. */
522 /* Which architecture variant provides this instruction. */
523 const arm_feature_set
*avariant
;
524 const arm_feature_set
*tvariant
;
526 /* Function to call to encode instruction in ARM format. */
527 void (* aencode
) (void);
529 /* Function to call to encode instruction in Thumb format. */
530 void (* tencode
) (void);
533 /* Defines for various bits that we will want to toggle. */
534 #define INST_IMMEDIATE 0x02000000
535 #define OFFSET_REG 0x02000000
536 #define HWOFFSET_IMM 0x00400000
537 #define SHIFT_BY_REG 0x00000010
538 #define PRE_INDEX 0x01000000
539 #define INDEX_UP 0x00800000
540 #define WRITE_BACK 0x00200000
541 #define LDM_TYPE_2_OR_3 0x00400000
543 #define LITERAL_MASK 0xf000f000
544 #define OPCODE_MASK 0xfe1fffff
545 #define V4_STR_BIT 0x00000020
547 #define DATA_OP_SHIFT 21
549 #define T2_OPCODE_MASK 0xfe1fffff
550 #define T2_DATA_OP_SHIFT 21
552 /* Codes to distinguish the arithmetic instructions. */
563 #define OPCODE_CMP 10
564 #define OPCODE_CMN 11
565 #define OPCODE_ORR 12
566 #define OPCODE_MOV 13
567 #define OPCODE_BIC 14
568 #define OPCODE_MVN 15
570 #define T2_OPCODE_AND 0
571 #define T2_OPCODE_BIC 1
572 #define T2_OPCODE_ORR 2
573 #define T2_OPCODE_ORN 3
574 #define T2_OPCODE_EOR 4
575 #define T2_OPCODE_ADD 8
576 #define T2_OPCODE_ADC 10
577 #define T2_OPCODE_SBC 11
578 #define T2_OPCODE_SUB 13
579 #define T2_OPCODE_RSB 14
581 #define T_OPCODE_MUL 0x4340
582 #define T_OPCODE_TST 0x4200
583 #define T_OPCODE_CMN 0x42c0
584 #define T_OPCODE_NEG 0x4240
585 #define T_OPCODE_MVN 0x43c0
587 #define T_OPCODE_ADD_R3 0x1800
588 #define T_OPCODE_SUB_R3 0x1a00
589 #define T_OPCODE_ADD_HI 0x4400
590 #define T_OPCODE_ADD_ST 0xb000
591 #define T_OPCODE_SUB_ST 0xb080
592 #define T_OPCODE_ADD_SP 0xa800
593 #define T_OPCODE_ADD_PC 0xa000
594 #define T_OPCODE_ADD_I8 0x3000
595 #define T_OPCODE_SUB_I8 0x3800
596 #define T_OPCODE_ADD_I3 0x1c00
597 #define T_OPCODE_SUB_I3 0x1e00
599 #define T_OPCODE_ASR_R 0x4100
600 #define T_OPCODE_LSL_R 0x4080
601 #define T_OPCODE_LSR_R 0x40c0
602 #define T_OPCODE_ROR_R 0x41c0
603 #define T_OPCODE_ASR_I 0x1000
604 #define T_OPCODE_LSL_I 0x0000
605 #define T_OPCODE_LSR_I 0x0800
607 #define T_OPCODE_MOV_I8 0x2000
608 #define T_OPCODE_CMP_I8 0x2800
609 #define T_OPCODE_CMP_LR 0x4280
610 #define T_OPCODE_MOV_HR 0x4600
611 #define T_OPCODE_CMP_HR 0x4500
613 #define T_OPCODE_LDR_PC 0x4800
614 #define T_OPCODE_LDR_SP 0x9800
615 #define T_OPCODE_STR_SP 0x9000
616 #define T_OPCODE_LDR_IW 0x6800
617 #define T_OPCODE_STR_IW 0x6000
618 #define T_OPCODE_LDR_IH 0x8800
619 #define T_OPCODE_STR_IH 0x8000
620 #define T_OPCODE_LDR_IB 0x7800
621 #define T_OPCODE_STR_IB 0x7000
622 #define T_OPCODE_LDR_RW 0x5800
623 #define T_OPCODE_STR_RW 0x5000
624 #define T_OPCODE_LDR_RH 0x5a00
625 #define T_OPCODE_STR_RH 0x5200
626 #define T_OPCODE_LDR_RB 0x5c00
627 #define T_OPCODE_STR_RB 0x5400
629 #define T_OPCODE_PUSH 0xb400
630 #define T_OPCODE_POP 0xbc00
632 #define T_OPCODE_BRANCH 0xe000
634 #define THUMB_SIZE 2 /* Size of thumb instruction. */
635 #define THUMB_PP_PC_LR 0x0100
636 #define THUMB_LOAD_BIT 0x0800
637 #define THUMB2_LOAD_BIT 0x00100000
639 #define BAD_ARGS _("bad arguments to instruction")
640 #define BAD_PC _("r15 not allowed here")
641 #define BAD_COND _("instruction cannot be conditional")
642 #define BAD_OVERLAP _("registers may not be the same")
643 #define BAD_HIREG _("lo register required")
644 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
645 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
646 #define BAD_BRANCH _("branch must be last instruction in IT block")
647 #define BAD_NOT_IT _("instruction not allowed in IT block")
648 #define BAD_FPU _("selected FPU does not support instruction")
650 static struct hash_control
*arm_ops_hsh
;
651 static struct hash_control
*arm_cond_hsh
;
652 static struct hash_control
*arm_shift_hsh
;
653 static struct hash_control
*arm_psr_hsh
;
654 static struct hash_control
*arm_v7m_psr_hsh
;
655 static struct hash_control
*arm_reg_hsh
;
656 static struct hash_control
*arm_reloc_hsh
;
657 static struct hash_control
*arm_barrier_opt_hsh
;
659 /* Stuff needed to resolve the label ambiguity
669 symbolS
* last_label_seen
;
670 static int label_is_thumb_function_name
= FALSE
;
672 /* Literal pool structure. Held on a per-section
673 and per-sub-section basis. */
675 #define MAX_LITERAL_POOL_SIZE 1024
676 typedef struct literal_pool
678 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
679 unsigned int next_free_entry
;
684 struct literal_pool
* next
;
687 /* Pointer to a linked list of literal pools. */
688 literal_pool
* list_of_pools
= NULL
;
690 /* State variables for IT block handling. */
691 static bfd_boolean current_it_mask
= 0;
692 static int current_cc
;
697 /* This array holds the chars that always start a comment. If the
698 pre-processor is disabled, these aren't very useful. */
699 const char comment_chars
[] = "@";
701 /* This array holds the chars that only start a comment at the beginning of
702 a line. If the line seems to have the form '# 123 filename'
703 .line and .file directives will appear in the pre-processed output. */
704 /* Note that input_file.c hand checks for '#' at the beginning of the
705 first line of the input file. This is because the compiler outputs
706 #NO_APP at the beginning of its output. */
707 /* Also note that comments like this one will always work. */
708 const char line_comment_chars
[] = "#";
710 const char line_separator_chars
[] = ";";
712 /* Chars that can be used to separate mant
713 from exp in floating point numbers. */
714 const char EXP_CHARS
[] = "eE";
716 /* Chars that mean this number is a floating point constant. */
720 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
722 /* Prefix characters that indicate the start of an immediate
724 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
726 /* Separator character handling. */
728 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
731 skip_past_char (char ** str
, char c
)
741 #define skip_past_comma(str) skip_past_char (str, ',')
743 /* Arithmetic expressions (possibly involving symbols). */
745 /* Return TRUE if anything in the expression is a bignum. */
748 walk_no_bignums (symbolS
* sp
)
750 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
753 if (symbol_get_value_expression (sp
)->X_add_symbol
)
755 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
756 || (symbol_get_value_expression (sp
)->X_op_symbol
757 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
763 static int in_my_get_expression
= 0;
765 /* Third argument to my_get_expression. */
766 #define GE_NO_PREFIX 0
767 #define GE_IMM_PREFIX 1
768 #define GE_OPT_PREFIX 2
769 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
770 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
771 #define GE_OPT_PREFIX_BIG 3
774 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
779 /* In unified syntax, all prefixes are optional. */
781 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
786 case GE_NO_PREFIX
: break;
788 if (!is_immediate_prefix (**str
))
790 inst
.error
= _("immediate expression requires a # prefix");
796 case GE_OPT_PREFIX_BIG
:
797 if (is_immediate_prefix (**str
))
803 memset (ep
, 0, sizeof (expressionS
));
805 save_in
= input_line_pointer
;
806 input_line_pointer
= *str
;
807 in_my_get_expression
= 1;
808 seg
= expression (ep
);
809 in_my_get_expression
= 0;
811 if (ep
->X_op
== O_illegal
)
813 /* We found a bad expression in md_operand(). */
814 *str
= input_line_pointer
;
815 input_line_pointer
= save_in
;
816 if (inst
.error
== NULL
)
817 inst
.error
= _("bad expression");
822 if (seg
!= absolute_section
823 && seg
!= text_section
824 && seg
!= data_section
825 && seg
!= bss_section
826 && seg
!= undefined_section
)
828 inst
.error
= _("bad segment");
829 *str
= input_line_pointer
;
830 input_line_pointer
= save_in
;
835 /* Get rid of any bignums now, so that we don't generate an error for which
836 we can't establish a line number later on. Big numbers are never valid
837 in instructions, which is where this routine is always called. */
838 if (prefix_mode
!= GE_OPT_PREFIX_BIG
839 && (ep
->X_op
== O_big
841 && (walk_no_bignums (ep
->X_add_symbol
)
843 && walk_no_bignums (ep
->X_op_symbol
))))))
845 inst
.error
= _("invalid constant");
846 *str
= input_line_pointer
;
847 input_line_pointer
= save_in
;
851 *str
= input_line_pointer
;
852 input_line_pointer
= save_in
;
856 /* Turn a string in input_line_pointer into a floating point constant
857 of type TYPE, and store the appropriate bytes in *LITP. The number
858 of LITTLENUMS emitted is stored in *SIZEP. An error message is
859 returned, or NULL on OK.
861 Note that fp constants aren't represent in the normal way on the ARM.
862 In big endian mode, things are as expected. However, in little endian
863 mode fp constants are big-endian word-wise, and little-endian byte-wise
864 within the words. For example, (double) 1.1 in big endian mode is
865 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
866 the byte sequence 99 99 f1 3f 9a 99 99 99.
868 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
871 md_atof (int type
, char * litP
, int * sizeP
)
874 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
906 return _("bad call to MD_ATOF()");
909 t
= atof_ieee (input_line_pointer
, type
, words
);
911 input_line_pointer
= t
;
914 if (target_big_endian
)
916 for (i
= 0; i
< prec
; i
++)
918 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
924 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
925 for (i
= prec
- 1; i
>= 0; i
--)
927 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
931 /* For a 4 byte float the order of elements in `words' is 1 0.
932 For an 8 byte float the order is 1 0 3 2. */
933 for (i
= 0; i
< prec
; i
+= 2)
935 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
936 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
944 /* We handle all bad expressions here, so that we can report the faulty
945 instruction in the error message. */
947 md_operand (expressionS
* expr
)
949 if (in_my_get_expression
)
950 expr
->X_op
= O_illegal
;
953 /* Immediate values. */
955 /* Generic immediate-value read function for use in directives.
956 Accepts anything that 'expression' can fold to a constant.
957 *val receives the number. */
960 immediate_for_directive (int *val
)
963 exp
.X_op
= O_illegal
;
965 if (is_immediate_prefix (*input_line_pointer
))
967 input_line_pointer
++;
971 if (exp
.X_op
!= O_constant
)
973 as_bad (_("expected #constant"));
974 ignore_rest_of_line ();
977 *val
= exp
.X_add_number
;
982 /* Register parsing. */
984 /* Generic register parser. CCP points to what should be the
985 beginning of a register name. If it is indeed a valid register
986 name, advance CCP over it and return the reg_entry structure;
987 otherwise return NULL. Does not issue diagnostics. */
989 static struct reg_entry
*
990 arm_reg_parse_multi (char **ccp
)
994 struct reg_entry
*reg
;
996 #ifdef REGISTER_PREFIX
997 if (*start
!= REGISTER_PREFIX
)
1001 #ifdef OPTIONAL_REGISTER_PREFIX
1002 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1007 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1012 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1014 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1024 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1025 enum arm_reg_type type
)
1027 /* Alternative syntaxes are accepted for a few register classes. */
1034 /* Generic coprocessor register names are allowed for these. */
1035 if (reg
&& reg
->type
== REG_TYPE_CN
)
1040 /* For backward compatibility, a bare number is valid here. */
1042 unsigned long processor
= strtoul (start
, ccp
, 10);
1043 if (*ccp
!= start
&& processor
<= 15)
1047 case REG_TYPE_MMXWC
:
1048 /* WC includes WCG. ??? I'm not sure this is true for all
1049 instructions that take WC registers. */
1050 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1061 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1062 return value is the register number or FAIL. */
1065 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1068 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1071 /* Do not allow a scalar (reg+index) to parse as a register. */
1072 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1075 if (reg
&& reg
->type
== type
)
1078 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1085 /* Parse a Neon type specifier. *STR should point at the leading '.'
1086 character. Does no verification at this stage that the type fits the opcode
1093 Can all be legally parsed by this function.
1095 Fills in neon_type struct pointer with parsed information, and updates STR
1096 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1097 type, FAIL if not. */
1100 parse_neon_type (struct neon_type
*type
, char **str
)
1107 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1109 enum neon_el_type thistype
= NT_untyped
;
1110 unsigned thissize
= -1u;
1117 /* Just a size without an explicit type. */
1121 switch (TOLOWER (*ptr
))
1123 case 'i': thistype
= NT_integer
; break;
1124 case 'f': thistype
= NT_float
; break;
1125 case 'p': thistype
= NT_poly
; break;
1126 case 's': thistype
= NT_signed
; break;
1127 case 'u': thistype
= NT_unsigned
; break;
1129 thistype
= NT_float
;
1134 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1140 /* .f is an abbreviation for .f32. */
1141 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1146 thissize
= strtoul (ptr
, &ptr
, 10);
1148 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1151 as_bad (_("bad size %d in type specifier"), thissize
);
1159 type
->el
[type
->elems
].type
= thistype
;
1160 type
->el
[type
->elems
].size
= thissize
;
1165 /* Empty/missing type is not a successful parse. */
1166 if (type
->elems
== 0)
1174 /* Errors may be set multiple times during parsing or bit encoding
1175 (particularly in the Neon bits), but usually the earliest error which is set
1176 will be the most meaningful. Avoid overwriting it with later (cascading)
1177 errors by calling this function. */
1180 first_error (const char *err
)
1186 /* Parse a single type, e.g. ".s32", leading period included. */
1188 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1191 struct neon_type optype
;
1195 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1197 if (optype
.elems
== 1)
1198 *vectype
= optype
.el
[0];
1201 first_error (_("only one type should be specified for operand"));
1207 first_error (_("vector type expected"));
1219 /* Special meanings for indices (which have a range of 0-7), which will fit into
1222 #define NEON_ALL_LANES 15
1223 #define NEON_INTERLEAVE_LANES 14
1225 /* Parse either a register or a scalar, with an optional type. Return the
1226 register number, and optionally fill in the actual type of the register
1227 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1228 type/index information in *TYPEINFO. */
1231 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1232 enum arm_reg_type
*rtype
,
1233 struct neon_typed_alias
*typeinfo
)
1236 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1237 struct neon_typed_alias atype
;
1238 struct neon_type_el parsetype
;
1242 atype
.eltype
.type
= NT_invtype
;
1243 atype
.eltype
.size
= -1;
1245 /* Try alternate syntax for some types of register. Note these are mutually
1246 exclusive with the Neon syntax extensions. */
1249 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1257 /* Undo polymorphism when a set of register types may be accepted. */
1258 if ((type
== REG_TYPE_NDQ
1259 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1260 || (type
== REG_TYPE_VFSD
1261 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1262 || (type
== REG_TYPE_NSDQ
1263 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1264 || reg
->type
== REG_TYPE_NQ
)))
1267 if (type
!= reg
->type
)
1273 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1275 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1277 first_error (_("can't redefine type for operand"));
1280 atype
.defined
|= NTA_HASTYPE
;
1281 atype
.eltype
= parsetype
;
1284 if (skip_past_char (&str
, '[') == SUCCESS
)
1286 if (type
!= REG_TYPE_VFD
)
1288 first_error (_("only D registers may be indexed"));
1292 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1294 first_error (_("can't change index for operand"));
1298 atype
.defined
|= NTA_HASINDEX
;
1300 if (skip_past_char (&str
, ']') == SUCCESS
)
1301 atype
.index
= NEON_ALL_LANES
;
1306 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1308 if (exp
.X_op
!= O_constant
)
1310 first_error (_("constant expression required"));
1314 if (skip_past_char (&str
, ']') == FAIL
)
1317 atype
.index
= exp
.X_add_number
;
1332 /* Like arm_reg_parse, but allow allow the following extra features:
1333 - If RTYPE is non-zero, return the (possibly restricted) type of the
1334 register (e.g. Neon double or quad reg when either has been requested).
1335 - If this is a Neon vector type with additional type information, fill
1336 in the struct pointed to by VECTYPE (if non-NULL).
1337 This function will fault on encountering a scalar.
1341 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1342 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1344 struct neon_typed_alias atype
;
1346 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1351 /* Do not allow a scalar (reg+index) to parse as a register. */
1352 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1354 first_error (_("register operand expected, but got scalar"));
1359 *vectype
= atype
.eltype
;
1366 #define NEON_SCALAR_REG(X) ((X) >> 4)
1367 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1369 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1370 have enough information to be able to do a good job bounds-checking. So, we
1371 just do easy checks here, and do further checks later. */
1374 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1378 struct neon_typed_alias atype
;
1380 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1382 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1385 if (atype
.index
== NEON_ALL_LANES
)
1387 first_error (_("scalar must have an index"));
1390 else if (atype
.index
>= 64 / elsize
)
1392 first_error (_("scalar index out of range"));
1397 *type
= atype
.eltype
;
1401 return reg
* 16 + atype
.index
;
1404 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1406 parse_reg_list (char ** strp
)
1408 char * str
= * strp
;
1412 /* We come back here if we get ranges concatenated by '+' or '|'. */
1427 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1429 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1439 first_error (_("bad range in register list"));
1443 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1445 if (range
& (1 << i
))
1447 (_("Warning: duplicated register (r%d) in register list"),
1455 if (range
& (1 << reg
))
1456 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1458 else if (reg
<= cur_reg
)
1459 as_tsktsk (_("Warning: register range not in ascending order"));
1464 while (skip_past_comma (&str
) != FAIL
1465 || (in_range
= 1, *str
++ == '-'));
1470 first_error (_("missing `}'"));
1478 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1481 if (expr
.X_op
== O_constant
)
1483 if (expr
.X_add_number
1484 != (expr
.X_add_number
& 0x0000ffff))
1486 inst
.error
= _("invalid register mask");
1490 if ((range
& expr
.X_add_number
) != 0)
1492 int regno
= range
& expr
.X_add_number
;
1495 regno
= (1 << regno
) - 1;
1497 (_("Warning: duplicated register (r%d) in register list"),
1501 range
|= expr
.X_add_number
;
1505 if (inst
.reloc
.type
!= 0)
1507 inst
.error
= _("expression too complex");
1511 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1512 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1513 inst
.reloc
.pc_rel
= 0;
1517 if (*str
== '|' || *str
== '+')
1523 while (another_range
);
1529 /* Types of registers in a list. */
1538 /* Parse a VFP register list. If the string is invalid return FAIL.
1539 Otherwise return the number of registers, and set PBASE to the first
1540 register. Parses registers of type ETYPE.
1541 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1542 - Q registers can be used to specify pairs of D registers
1543 - { } can be omitted from around a singleton register list
1544 FIXME: This is not implemented, as it would require backtracking in
1547 This could be done (the meaning isn't really ambiguous), but doesn't
1548 fit in well with the current parsing framework.
1549 - 32 D registers may be used (also true for VFPv3).
1550 FIXME: Types are ignored in these register lists, which is probably a
1554 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1559 enum arm_reg_type regtype
= 0;
1563 unsigned long mask
= 0;
1568 inst
.error
= _("expecting {");
1577 regtype
= REG_TYPE_VFS
;
1582 regtype
= REG_TYPE_VFD
;
1585 case REGLIST_NEON_D
:
1586 regtype
= REG_TYPE_NDQ
;
1590 if (etype
!= REGLIST_VFP_S
)
1592 /* VFPv3 allows 32 D registers. */
1593 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1597 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1600 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1607 base_reg
= max_regs
;
1611 int setmask
= 1, addregs
= 1;
1613 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1615 if (new_base
== FAIL
)
1617 first_error (_(reg_expected_msgs
[regtype
]));
1621 if (new_base
>= max_regs
)
1623 first_error (_("register out of range in list"));
1627 /* Note: a value of 2 * n is returned for the register Q<n>. */
1628 if (regtype
== REG_TYPE_NQ
)
1634 if (new_base
< base_reg
)
1635 base_reg
= new_base
;
1637 if (mask
& (setmask
<< new_base
))
1639 first_error (_("invalid register list"));
1643 if ((mask
>> new_base
) != 0 && ! warned
)
1645 as_tsktsk (_("register list not in ascending order"));
1649 mask
|= setmask
<< new_base
;
1652 if (*str
== '-') /* We have the start of a range expression */
1658 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1661 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1665 if (high_range
>= max_regs
)
1667 first_error (_("register out of range in list"));
1671 if (regtype
== REG_TYPE_NQ
)
1672 high_range
= high_range
+ 1;
1674 if (high_range
<= new_base
)
1676 inst
.error
= _("register range not in ascending order");
1680 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1682 if (mask
& (setmask
<< new_base
))
1684 inst
.error
= _("invalid register list");
1688 mask
|= setmask
<< new_base
;
1693 while (skip_past_comma (&str
) != FAIL
);
1697 /* Sanity check -- should have raised a parse error above. */
1698 if (count
== 0 || count
> max_regs
)
1703 /* Final test -- the registers must be consecutive. */
1705 for (i
= 0; i
< count
; i
++)
1707 if ((mask
& (1u << i
)) == 0)
1709 inst
.error
= _("non-contiguous register range");
1719 /* True if two alias types are the same. */
1722 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1730 if (a
->defined
!= b
->defined
)
1733 if ((a
->defined
& NTA_HASTYPE
) != 0
1734 && (a
->eltype
.type
!= b
->eltype
.type
1735 || a
->eltype
.size
!= b
->eltype
.size
))
1738 if ((a
->defined
& NTA_HASINDEX
) != 0
1739 && (a
->index
!= b
->index
))
1745 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1746 The base register is put in *PBASE.
1747 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1749 The register stride (minus one) is put in bit 4 of the return value.
1750 Bits [6:5] encode the list length (minus one).
1751 The type of the list elements is put in *ELTYPE, if non-NULL. */
1753 #define NEON_LANE(X) ((X) & 0xf)
1754 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1755 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1758 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1759 struct neon_type_el
*eltype
)
1766 int leading_brace
= 0;
1767 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1769 const char *const incr_error
= "register stride must be 1 or 2";
1770 const char *const type_error
= "mismatched element/structure types in list";
1771 struct neon_typed_alias firsttype
;
1773 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1778 struct neon_typed_alias atype
;
1779 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1783 first_error (_(reg_expected_msgs
[rtype
]));
1790 if (rtype
== REG_TYPE_NQ
)
1797 else if (reg_incr
== -1)
1799 reg_incr
= getreg
- base_reg
;
1800 if (reg_incr
< 1 || reg_incr
> 2)
1802 first_error (_(incr_error
));
1806 else if (getreg
!= base_reg
+ reg_incr
* count
)
1808 first_error (_(incr_error
));
1812 if (!neon_alias_types_same (&atype
, &firsttype
))
1814 first_error (_(type_error
));
1818 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1822 struct neon_typed_alias htype
;
1823 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1825 lane
= NEON_INTERLEAVE_LANES
;
1826 else if (lane
!= NEON_INTERLEAVE_LANES
)
1828 first_error (_(type_error
));
1833 else if (reg_incr
!= 1)
1835 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1839 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1842 first_error (_(reg_expected_msgs
[rtype
]));
1845 if (!neon_alias_types_same (&htype
, &firsttype
))
1847 first_error (_(type_error
));
1850 count
+= hireg
+ dregs
- getreg
;
1854 /* If we're using Q registers, we can't use [] or [n] syntax. */
1855 if (rtype
== REG_TYPE_NQ
)
1861 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1865 else if (lane
!= atype
.index
)
1867 first_error (_(type_error
));
1871 else if (lane
== -1)
1872 lane
= NEON_INTERLEAVE_LANES
;
1873 else if (lane
!= NEON_INTERLEAVE_LANES
)
1875 first_error (_(type_error
));
1880 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1882 /* No lane set by [x]. We must be interleaving structures. */
1884 lane
= NEON_INTERLEAVE_LANES
;
1887 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1888 || (count
> 1 && reg_incr
== -1))
1890 first_error (_("error parsing element/structure list"));
1894 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1896 first_error (_("expected }"));
1904 *eltype
= firsttype
.eltype
;
1909 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1912 /* Parse an explicit relocation suffix on an expression. This is
1913 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1914 arm_reloc_hsh contains no entries, so this function can only
1915 succeed if there is no () after the word. Returns -1 on error,
1916 BFD_RELOC_UNUSED if there wasn't any suffix. */
1918 parse_reloc (char **str
)
1920 struct reloc_entry
*r
;
1924 return BFD_RELOC_UNUSED
;
1929 while (*q
&& *q
!= ')' && *q
!= ',')
1934 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1941 /* Directives: register aliases. */
1943 static struct reg_entry
*
1944 insert_reg_alias (char *str
, int number
, int type
)
1946 struct reg_entry
*new;
1949 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1952 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1954 /* Only warn about a redefinition if it's not defined as the
1956 else if (new->number
!= number
|| new->type
!= type
)
1957 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1962 name
= xstrdup (str
);
1963 new = xmalloc (sizeof (struct reg_entry
));
1966 new->number
= number
;
1968 new->builtin
= FALSE
;
1971 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1978 insert_neon_reg_alias (char *str
, int number
, int type
,
1979 struct neon_typed_alias
*atype
)
1981 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
1985 first_error (_("attempt to redefine typed alias"));
1991 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
1992 *reg
->neon
= *atype
;
1996 /* Look for the .req directive. This is of the form:
1998 new_register_name .req existing_register_name
2000 If we find one, or if it looks sufficiently like one that we want to
2001 handle any error here, return non-zero. Otherwise return zero. */
2004 create_register_alias (char * newname
, char *p
)
2006 struct reg_entry
*old
;
2007 char *oldname
, *nbuf
;
2010 /* The input scrubber ensures that whitespace after the mnemonic is
2011 collapsed to single spaces. */
2013 if (strncmp (oldname
, " .req ", 6) != 0)
2017 if (*oldname
== '\0')
2020 old
= hash_find (arm_reg_hsh
, oldname
);
2023 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2027 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2028 the desired alias name, and p points to its end. If not, then
2029 the desired alias name is in the global original_case_string. */
2030 #ifdef TC_CASE_SENSITIVE
2033 newname
= original_case_string
;
2034 nlen
= strlen (newname
);
2037 nbuf
= alloca (nlen
+ 1);
2038 memcpy (nbuf
, newname
, nlen
);
2041 /* Create aliases under the new name as stated; an all-lowercase
2042 version of the new name; and an all-uppercase version of the new
2044 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2046 for (p
= nbuf
; *p
; p
++)
2049 if (strncmp (nbuf
, newname
, nlen
))
2050 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2052 for (p
= nbuf
; *p
; p
++)
2055 if (strncmp (nbuf
, newname
, nlen
))
2056 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2061 /* Create a Neon typed/indexed register alias using directives, e.g.:
2066 These typed registers can be used instead of the types specified after the
2067 Neon mnemonic, so long as all operands given have types. Types can also be
2068 specified directly, e.g.:
2069 vadd d0.s32, d1.s32, d2.s32
2073 create_neon_reg_alias (char *newname
, char *p
)
2075 enum arm_reg_type basetype
;
2076 struct reg_entry
*basereg
;
2077 struct reg_entry mybasereg
;
2078 struct neon_type ntype
;
2079 struct neon_typed_alias typeinfo
;
2080 char *namebuf
, *nameend
;
2083 typeinfo
.defined
= 0;
2084 typeinfo
.eltype
.type
= NT_invtype
;
2085 typeinfo
.eltype
.size
= -1;
2086 typeinfo
.index
= -1;
2090 if (strncmp (p
, " .dn ", 5) == 0)
2091 basetype
= REG_TYPE_VFD
;
2092 else if (strncmp (p
, " .qn ", 5) == 0)
2093 basetype
= REG_TYPE_NQ
;
2102 basereg
= arm_reg_parse_multi (&p
);
2104 if (basereg
&& basereg
->type
!= basetype
)
2106 as_bad (_("bad type for register"));
2110 if (basereg
== NULL
)
2113 /* Try parsing as an integer. */
2114 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2115 if (exp
.X_op
!= O_constant
)
2117 as_bad (_("expression must be constant"));
2120 basereg
= &mybasereg
;
2121 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2127 typeinfo
= *basereg
->neon
;
2129 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2131 /* We got a type. */
2132 if (typeinfo
.defined
& NTA_HASTYPE
)
2134 as_bad (_("can't redefine the type of a register alias"));
2138 typeinfo
.defined
|= NTA_HASTYPE
;
2139 if (ntype
.elems
!= 1)
2141 as_bad (_("you must specify a single type only"));
2144 typeinfo
.eltype
= ntype
.el
[0];
2147 if (skip_past_char (&p
, '[') == SUCCESS
)
2150 /* We got a scalar index. */
2152 if (typeinfo
.defined
& NTA_HASINDEX
)
2154 as_bad (_("can't redefine the index of a scalar alias"));
2158 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2160 if (exp
.X_op
!= O_constant
)
2162 as_bad (_("scalar index must be constant"));
2166 typeinfo
.defined
|= NTA_HASINDEX
;
2167 typeinfo
.index
= exp
.X_add_number
;
2169 if (skip_past_char (&p
, ']') == FAIL
)
2171 as_bad (_("expecting ]"));
2176 namelen
= nameend
- newname
;
2177 namebuf
= alloca (namelen
+ 1);
2178 strncpy (namebuf
, newname
, namelen
);
2179 namebuf
[namelen
] = '\0';
2181 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2182 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2184 /* Insert name in all uppercase. */
2185 for (p
= namebuf
; *p
; p
++)
2188 if (strncmp (namebuf
, newname
, namelen
))
2189 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2190 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2192 /* Insert name in all lowercase. */
2193 for (p
= namebuf
; *p
; p
++)
2196 if (strncmp (namebuf
, newname
, namelen
))
2197 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2198 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2203 /* Should never be called, as .req goes between the alias and the
2204 register name, not at the beginning of the line. */
2206 s_req (int a ATTRIBUTE_UNUSED
)
2208 as_bad (_("invalid syntax for .req directive"));
2212 s_dn (int a ATTRIBUTE_UNUSED
)
2214 as_bad (_("invalid syntax for .dn directive"));
2218 s_qn (int a ATTRIBUTE_UNUSED
)
2220 as_bad (_("invalid syntax for .qn directive"));
2223 /* The .unreq directive deletes an alias which was previously defined
2224 by .req. For example:
2230 s_unreq (int a ATTRIBUTE_UNUSED
)
2235 name
= input_line_pointer
;
2237 while (*input_line_pointer
!= 0
2238 && *input_line_pointer
!= ' '
2239 && *input_line_pointer
!= '\n')
2240 ++input_line_pointer
;
2242 saved_char
= *input_line_pointer
;
2243 *input_line_pointer
= 0;
2246 as_bad (_("invalid syntax for .unreq directive"));
2249 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2252 as_bad (_("unknown register alias '%s'"), name
);
2253 else if (reg
->builtin
)
2254 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2258 hash_delete (arm_reg_hsh
, name
);
2259 free ((char *) reg
->name
);
2266 *input_line_pointer
= saved_char
;
2267 demand_empty_rest_of_line ();
2270 /* Directives: Instruction set selection. */
2273 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2274 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2275 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2276 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2278 static enum mstate mapstate
= MAP_UNDEFINED
;
2281 mapping_state (enum mstate state
)
2284 const char * symname
;
2287 if (mapstate
== state
)
2288 /* The mapping symbol has already been emitted.
2289 There is nothing else to do. */
2298 type
= BSF_NO_FLAGS
;
2302 type
= BSF_NO_FLAGS
;
2306 type
= BSF_NO_FLAGS
;
2314 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2316 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2317 symbol_table_insert (symbolP
);
2318 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2323 THUMB_SET_FUNC (symbolP
, 0);
2324 ARM_SET_THUMB (symbolP
, 0);
2325 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2329 THUMB_SET_FUNC (symbolP
, 1);
2330 ARM_SET_THUMB (symbolP
, 1);
2331 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2340 #define mapping_state(x) /* nothing */
2343 /* Find the real, Thumb encoded start of a Thumb function. */
2346 find_real_start (symbolS
* symbolP
)
2349 const char * name
= S_GET_NAME (symbolP
);
2350 symbolS
* new_target
;
2352 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2353 #define STUB_NAME ".real_start_of"
2358 /* The compiler may generate BL instructions to local labels because
2359 it needs to perform a branch to a far away location. These labels
2360 do not have a corresponding ".real_start_of" label. We check
2361 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2362 the ".real_start_of" convention for nonlocal branches. */
2363 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2366 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2367 new_target
= symbol_find (real_start
);
2369 if (new_target
== NULL
)
2371 as_warn ("Failed to find real start of function: %s\n", name
);
2372 new_target
= symbolP
;
2379 opcode_select (int width
)
2386 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2387 as_bad (_("selected processor does not support THUMB opcodes"));
2390 /* No need to force the alignment, since we will have been
2391 coming from ARM mode, which is word-aligned. */
2392 record_alignment (now_seg
, 1);
2394 mapping_state (MAP_THUMB
);
2400 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2401 as_bad (_("selected processor does not support ARM opcodes"));
2406 frag_align (2, 0, 0);
2408 record_alignment (now_seg
, 1);
2410 mapping_state (MAP_ARM
);
2414 as_bad (_("invalid instruction size selected (%d)"), width
);
2419 s_arm (int ignore ATTRIBUTE_UNUSED
)
2422 demand_empty_rest_of_line ();
2426 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2429 demand_empty_rest_of_line ();
2433 s_code (int unused ATTRIBUTE_UNUSED
)
2437 temp
= get_absolute_expression ();
2442 opcode_select (temp
);
2446 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2451 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2453 /* If we are not already in thumb mode go into it, EVEN if
2454 the target processor does not support thumb instructions.
2455 This is used by gcc/config/arm/lib1funcs.asm for example
2456 to compile interworking support functions even if the
2457 target processor should not support interworking. */
2461 record_alignment (now_seg
, 1);
2464 demand_empty_rest_of_line ();
2468 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2472 /* The following label is the name/address of the start of a Thumb function.
2473 We need to know this for the interworking support. */
2474 label_is_thumb_function_name
= TRUE
;
2477 /* Perform a .set directive, but also mark the alias as
2478 being a thumb function. */
2481 s_thumb_set (int equiv
)
2483 /* XXX the following is a duplicate of the code for s_set() in read.c
2484 We cannot just call that code as we need to get at the symbol that
2491 /* Especial apologies for the random logic:
2492 This just grew, and could be parsed much more simply!
2494 name
= input_line_pointer
;
2495 delim
= get_symbol_end ();
2496 end_name
= input_line_pointer
;
2499 if (*input_line_pointer
!= ',')
2502 as_bad (_("expected comma after name \"%s\""), name
);
2504 ignore_rest_of_line ();
2508 input_line_pointer
++;
2511 if (name
[0] == '.' && name
[1] == '\0')
2513 /* XXX - this should not happen to .thumb_set. */
2517 if ((symbolP
= symbol_find (name
)) == NULL
2518 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2521 /* When doing symbol listings, play games with dummy fragments living
2522 outside the normal fragment chain to record the file and line info
2524 if (listing
& LISTING_SYMBOLS
)
2526 extern struct list_info_struct
* listing_tail
;
2527 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2529 memset (dummy_frag
, 0, sizeof (fragS
));
2530 dummy_frag
->fr_type
= rs_fill
;
2531 dummy_frag
->line
= listing_tail
;
2532 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2533 dummy_frag
->fr_symbol
= symbolP
;
2537 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2540 /* "set" symbols are local unless otherwise specified. */
2541 SF_SET_LOCAL (symbolP
);
2542 #endif /* OBJ_COFF */
2543 } /* Make a new symbol. */
2545 symbol_table_insert (symbolP
);
2550 && S_IS_DEFINED (symbolP
)
2551 && S_GET_SEGMENT (symbolP
) != reg_section
)
2552 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2554 pseudo_set (symbolP
);
2556 demand_empty_rest_of_line ();
2558 /* XXX Now we come to the Thumb specific bit of code. */
2560 THUMB_SET_FUNC (symbolP
, 1);
2561 ARM_SET_THUMB (symbolP
, 1);
2562 #if defined OBJ_ELF || defined OBJ_COFF
2563 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2567 /* Directives: Mode selection. */
2569 /* .syntax [unified|divided] - choose the new unified syntax
2570 (same for Arm and Thumb encoding, modulo slight differences in what
2571 can be represented) or the old divergent syntax for each mode. */
2573 s_syntax (int unused ATTRIBUTE_UNUSED
)
2577 name
= input_line_pointer
;
2578 delim
= get_symbol_end ();
2580 if (!strcasecmp (name
, "unified"))
2581 unified_syntax
= TRUE
;
2582 else if (!strcasecmp (name
, "divided"))
2583 unified_syntax
= FALSE
;
2586 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2589 *input_line_pointer
= delim
;
2590 demand_empty_rest_of_line ();
2593 /* Directives: sectioning and alignment. */
2595 /* Same as s_align_ptwo but align 0 => align 2. */
2598 s_align (int unused ATTRIBUTE_UNUSED
)
2602 long max_alignment
= 15;
2604 temp
= get_absolute_expression ();
2605 if (temp
> max_alignment
)
2606 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2609 as_bad (_("alignment negative. 0 assumed."));
2613 if (*input_line_pointer
== ',')
2615 input_line_pointer
++;
2616 temp_fill
= get_absolute_expression ();
2624 /* Only make a frag if we HAVE to. */
2625 if (temp
&& !need_pass_2
)
2626 frag_align (temp
, (int) temp_fill
, 0);
2627 demand_empty_rest_of_line ();
2629 record_alignment (now_seg
, temp
);
2633 s_bss (int ignore ATTRIBUTE_UNUSED
)
2635 /* We don't support putting frags in the BSS segment, we fake it by
2636 marking in_bss, then looking at s_skip for clues. */
2637 subseg_set (bss_section
, 0);
2638 demand_empty_rest_of_line ();
2639 mapping_state (MAP_DATA
);
2643 s_even (int ignore ATTRIBUTE_UNUSED
)
2645 /* Never make frag if expect extra pass. */
2647 frag_align (1, 0, 0);
2649 record_alignment (now_seg
, 1);
2651 demand_empty_rest_of_line ();
2654 /* Directives: Literal pools. */
2656 static literal_pool
*
2657 find_literal_pool (void)
2659 literal_pool
* pool
;
2661 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2663 if (pool
->section
== now_seg
2664 && pool
->sub_section
== now_subseg
)
2671 static literal_pool
*
2672 find_or_make_literal_pool (void)
2674 /* Next literal pool ID number. */
2675 static unsigned int latest_pool_num
= 1;
2676 literal_pool
* pool
;
2678 pool
= find_literal_pool ();
2682 /* Create a new pool. */
2683 pool
= xmalloc (sizeof (* pool
));
2687 pool
->next_free_entry
= 0;
2688 pool
->section
= now_seg
;
2689 pool
->sub_section
= now_subseg
;
2690 pool
->next
= list_of_pools
;
2691 pool
->symbol
= NULL
;
2693 /* Add it to the list. */
2694 list_of_pools
= pool
;
2697 /* New pools, and emptied pools, will have a NULL symbol. */
2698 if (pool
->symbol
== NULL
)
2700 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2701 (valueT
) 0, &zero_address_frag
);
2702 pool
->id
= latest_pool_num
++;
2709 /* Add the literal in the global 'inst'
2710 structure to the relevent literal pool. */
2713 add_to_lit_pool (void)
2715 literal_pool
* pool
;
2718 pool
= find_or_make_literal_pool ();
2720 /* Check if this literal value is already in the pool. */
2721 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2723 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2724 && (inst
.reloc
.exp
.X_op
== O_constant
)
2725 && (pool
->literals
[entry
].X_add_number
2726 == inst
.reloc
.exp
.X_add_number
)
2727 && (pool
->literals
[entry
].X_unsigned
2728 == inst
.reloc
.exp
.X_unsigned
))
2731 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2732 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2733 && (pool
->literals
[entry
].X_add_number
2734 == inst
.reloc
.exp
.X_add_number
)
2735 && (pool
->literals
[entry
].X_add_symbol
2736 == inst
.reloc
.exp
.X_add_symbol
)
2737 && (pool
->literals
[entry
].X_op_symbol
2738 == inst
.reloc
.exp
.X_op_symbol
))
2742 /* Do we need to create a new entry? */
2743 if (entry
== pool
->next_free_entry
)
2745 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2747 inst
.error
= _("literal pool overflow");
2751 pool
->literals
[entry
] = inst
.reloc
.exp
;
2752 pool
->next_free_entry
+= 1;
2755 inst
.reloc
.exp
.X_op
= O_symbol
;
2756 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2757 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2762 /* Can't use symbol_new here, so have to create a symbol and then at
2763 a later date assign it a value. Thats what these functions do. */
2766 symbol_locate (symbolS
* symbolP
,
2767 const char * name
, /* It is copied, the caller can modify. */
2768 segT segment
, /* Segment identifier (SEG_<something>). */
2769 valueT valu
, /* Symbol value. */
2770 fragS
* frag
) /* Associated fragment. */
2772 unsigned int name_length
;
2773 char * preserved_copy_of_name
;
2775 name_length
= strlen (name
) + 1; /* +1 for \0. */
2776 obstack_grow (¬es
, name
, name_length
);
2777 preserved_copy_of_name
= obstack_finish (¬es
);
2779 #ifdef tc_canonicalize_symbol_name
2780 preserved_copy_of_name
=
2781 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2784 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2786 S_SET_SEGMENT (symbolP
, segment
);
2787 S_SET_VALUE (symbolP
, valu
);
2788 symbol_clear_list_pointers (symbolP
);
2790 symbol_set_frag (symbolP
, frag
);
2792 /* Link to end of symbol chain. */
2794 extern int symbol_table_frozen
;
2796 if (symbol_table_frozen
)
2800 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2802 obj_symbol_new_hook (symbolP
);
2804 #ifdef tc_symbol_new_hook
2805 tc_symbol_new_hook (symbolP
);
2809 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2810 #endif /* DEBUG_SYMS */
2815 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2818 literal_pool
* pool
;
2821 pool
= find_literal_pool ();
2823 || pool
->symbol
== NULL
2824 || pool
->next_free_entry
== 0)
2827 mapping_state (MAP_DATA
);
2829 /* Align pool as you have word accesses.
2830 Only make a frag if we have to. */
2832 frag_align (2, 0, 0);
2834 record_alignment (now_seg
, 2);
2836 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2838 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2839 (valueT
) frag_now_fix (), frag_now
);
2840 symbol_table_insert (pool
->symbol
);
2842 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2844 #if defined OBJ_COFF || defined OBJ_ELF
2845 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2848 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2849 /* First output the expression in the instruction to the pool. */
2850 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2852 /* Mark the pool as empty. */
2853 pool
->next_free_entry
= 0;
2854 pool
->symbol
= NULL
;
2858 /* Forward declarations for functions below, in the MD interface
2860 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2861 static valueT
create_unwind_entry (int);
2862 static void start_unwind_section (const segT
, int);
2863 static void add_unwind_opcode (valueT
, int);
2864 static void flush_pending_unwind (void);
2866 /* Directives: Data. */
2869 s_arm_elf_cons (int nbytes
)
2873 #ifdef md_flush_pending_output
2874 md_flush_pending_output ();
2877 if (is_it_end_of_statement ())
2879 demand_empty_rest_of_line ();
2883 #ifdef md_cons_align
2884 md_cons_align (nbytes
);
2887 mapping_state (MAP_DATA
);
2891 char *base
= input_line_pointer
;
2895 if (exp
.X_op
!= O_symbol
)
2896 emit_expr (&exp
, (unsigned int) nbytes
);
2899 char *before_reloc
= input_line_pointer
;
2900 reloc
= parse_reloc (&input_line_pointer
);
2903 as_bad (_("unrecognized relocation suffix"));
2904 ignore_rest_of_line ();
2907 else if (reloc
== BFD_RELOC_UNUSED
)
2908 emit_expr (&exp
, (unsigned int) nbytes
);
2911 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2912 int size
= bfd_get_reloc_size (howto
);
2914 if (reloc
== BFD_RELOC_ARM_PLT32
)
2916 as_bad (_("(plt) is only valid on branch targets"));
2917 reloc
= BFD_RELOC_UNUSED
;
2922 as_bad (_("%s relocations do not fit in %d bytes"),
2923 howto
->name
, nbytes
);
2926 /* We've parsed an expression stopping at O_symbol.
2927 But there may be more expression left now that we
2928 have parsed the relocation marker. Parse it again.
2929 XXX Surely there is a cleaner way to do this. */
2930 char *p
= input_line_pointer
;
2932 char *save_buf
= alloca (input_line_pointer
- base
);
2933 memcpy (save_buf
, base
, input_line_pointer
- base
);
2934 memmove (base
+ (input_line_pointer
- before_reloc
),
2935 base
, before_reloc
- base
);
2937 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
2939 memcpy (base
, save_buf
, p
- base
);
2941 offset
= nbytes
- size
;
2942 p
= frag_more ((int) nbytes
);
2943 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2944 size
, &exp
, 0, reloc
);
2949 while (*input_line_pointer
++ == ',');
2951 /* Put terminator back into stream. */
2952 input_line_pointer
--;
2953 demand_empty_rest_of_line ();
2957 /* Parse a .rel31 directive. */
2960 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2967 if (*input_line_pointer
== '1')
2968 highbit
= 0x80000000;
2969 else if (*input_line_pointer
!= '0')
2970 as_bad (_("expected 0 or 1"));
2972 input_line_pointer
++;
2973 if (*input_line_pointer
!= ',')
2974 as_bad (_("missing comma"));
2975 input_line_pointer
++;
2977 #ifdef md_flush_pending_output
2978 md_flush_pending_output ();
2981 #ifdef md_cons_align
2985 mapping_state (MAP_DATA
);
2990 md_number_to_chars (p
, highbit
, 4);
2991 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
2992 BFD_RELOC_ARM_PREL31
);
2994 demand_empty_rest_of_line ();
2997 /* Directives: AEABI stack-unwind tables. */
2999 /* Parse an unwind_fnstart directive. Simply records the current location. */
3002 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3004 demand_empty_rest_of_line ();
3005 /* Mark the start of the function. */
3006 unwind
.proc_start
= expr_build_dot ();
3008 /* Reset the rest of the unwind info. */
3009 unwind
.opcode_count
= 0;
3010 unwind
.table_entry
= NULL
;
3011 unwind
.personality_routine
= NULL
;
3012 unwind
.personality_index
= -1;
3013 unwind
.frame_size
= 0;
3014 unwind
.fp_offset
= 0;
3017 unwind
.sp_restored
= 0;
3021 /* Parse a handlerdata directive. Creates the exception handling table entry
3022 for the function. */
3025 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3027 demand_empty_rest_of_line ();
3028 if (unwind
.table_entry
)
3029 as_bad (_("dupicate .handlerdata directive"));
3031 create_unwind_entry (1);
3034 /* Parse an unwind_fnend directive. Generates the index table entry. */
3037 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3043 demand_empty_rest_of_line ();
3045 /* Add eh table entry. */
3046 if (unwind
.table_entry
== NULL
)
3047 val
= create_unwind_entry (0);
3051 /* Add index table entry. This is two words. */
3052 start_unwind_section (unwind
.saved_seg
, 1);
3053 frag_align (2, 0, 0);
3054 record_alignment (now_seg
, 2);
3056 ptr
= frag_more (8);
3057 where
= frag_now_fix () - 8;
3059 /* Self relative offset of the function start. */
3060 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3061 BFD_RELOC_ARM_PREL31
);
3063 /* Indicate dependency on EHABI-defined personality routines to the
3064 linker, if it hasn't been done already. */
3065 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3066 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3068 static const char *const name
[] = {
3069 "__aeabi_unwind_cpp_pr0",
3070 "__aeabi_unwind_cpp_pr1",
3071 "__aeabi_unwind_cpp_pr2"
3073 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3074 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3075 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3076 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3077 = marked_pr_dependency
;
3081 /* Inline exception table entry. */
3082 md_number_to_chars (ptr
+ 4, val
, 4);
3084 /* Self relative offset of the table entry. */
3085 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3086 BFD_RELOC_ARM_PREL31
);
3088 /* Restore the original section. */
3089 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3093 /* Parse an unwind_cantunwind directive. */
3096 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3098 demand_empty_rest_of_line ();
3099 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3100 as_bad (_("personality routine specified for cantunwind frame"));
3102 unwind
.personality_index
= -2;
3106 /* Parse a personalityindex directive. */
3109 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3113 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3114 as_bad (_("duplicate .personalityindex directive"));
3118 if (exp
.X_op
!= O_constant
3119 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3121 as_bad (_("bad personality routine number"));
3122 ignore_rest_of_line ();
3126 unwind
.personality_index
= exp
.X_add_number
;
3128 demand_empty_rest_of_line ();
3132 /* Parse a personality directive. */
3135 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3140 as_bad (_("duplicate .personality directive"));
3142 name
= input_line_pointer
;
3143 c
= get_symbol_end ();
3144 p
= input_line_pointer
;
3145 unwind
.personality_routine
= symbol_find_or_make (name
);
3147 demand_empty_rest_of_line ();
3151 /* Parse a directive saving core registers. */
3154 s_arm_unwind_save_core (void)
3160 range
= parse_reg_list (&input_line_pointer
);
3163 as_bad (_("expected register list"));
3164 ignore_rest_of_line ();
3168 demand_empty_rest_of_line ();
3170 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3171 into .unwind_save {..., sp...}. We aren't bothered about the value of
3172 ip because it is clobbered by calls. */
3173 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3174 && (range
& 0x3000) == 0x1000)
3176 unwind
.opcode_count
--;
3177 unwind
.sp_restored
= 0;
3178 range
= (range
| 0x2000) & ~0x1000;
3179 unwind
.pending_offset
= 0;
3185 /* See if we can use the short opcodes. These pop a block of up to 8
3186 registers starting with r4, plus maybe r14. */
3187 for (n
= 0; n
< 8; n
++)
3189 /* Break at the first non-saved register. */
3190 if ((range
& (1 << (n
+ 4))) == 0)
3193 /* See if there are any other bits set. */
3194 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3196 /* Use the long form. */
3197 op
= 0x8000 | ((range
>> 4) & 0xfff);
3198 add_unwind_opcode (op
, 2);
3202 /* Use the short form. */
3204 op
= 0xa8; /* Pop r14. */
3206 op
= 0xa0; /* Do not pop r14. */
3208 add_unwind_opcode (op
, 1);
3215 op
= 0xb100 | (range
& 0xf);
3216 add_unwind_opcode (op
, 2);
3219 /* Record the number of bytes pushed. */
3220 for (n
= 0; n
< 16; n
++)
3222 if (range
& (1 << n
))
3223 unwind
.frame_size
+= 4;
3228 /* Parse a directive saving FPA registers. */
3231 s_arm_unwind_save_fpa (int reg
)
3237 /* Get Number of registers to transfer. */
3238 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3241 exp
.X_op
= O_illegal
;
3243 if (exp
.X_op
!= O_constant
)
3245 as_bad (_("expected , <constant>"));
3246 ignore_rest_of_line ();
3250 num_regs
= exp
.X_add_number
;
3252 if (num_regs
< 1 || num_regs
> 4)
3254 as_bad (_("number of registers must be in the range [1:4]"));
3255 ignore_rest_of_line ();
3259 demand_empty_rest_of_line ();
3264 op
= 0xb4 | (num_regs
- 1);
3265 add_unwind_opcode (op
, 1);
3270 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3271 add_unwind_opcode (op
, 2);
3273 unwind
.frame_size
+= num_regs
* 12;
3277 /* Parse a directive saving VFP registers for ARMv6 and above. */
3280 s_arm_unwind_save_vfp_armv6 (void)
3285 int num_vfpv3_regs
= 0;
3286 int num_regs_below_16
;
3288 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3291 as_bad (_("expected register list"));
3292 ignore_rest_of_line ();
3296 demand_empty_rest_of_line ();
3298 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3299 than FSTMX/FLDMX-style ones). */
3301 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3303 num_vfpv3_regs
= count
;
3304 else if (start
+ count
> 16)
3305 num_vfpv3_regs
= start
+ count
- 16;
3307 if (num_vfpv3_regs
> 0)
3309 int start_offset
= start
> 16 ? start
- 16 : 0;
3310 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3311 add_unwind_opcode (op
, 2);
3314 /* Generate opcode for registers numbered in the range 0 .. 15. */
3315 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3316 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3317 if (num_regs_below_16
> 0)
3319 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3320 add_unwind_opcode (op
, 2);
3323 unwind
.frame_size
+= count
* 8;
3327 /* Parse a directive saving VFP registers for pre-ARMv6. */
3330 s_arm_unwind_save_vfp (void)
3336 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3339 as_bad (_("expected register list"));
3340 ignore_rest_of_line ();
3344 demand_empty_rest_of_line ();
3349 op
= 0xb8 | (count
- 1);
3350 add_unwind_opcode (op
, 1);
3355 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3356 add_unwind_opcode (op
, 2);
3358 unwind
.frame_size
+= count
* 8 + 4;
3362 /* Parse a directive saving iWMMXt data registers. */
3365 s_arm_unwind_save_mmxwr (void)
3373 if (*input_line_pointer
== '{')
3374 input_line_pointer
++;
3378 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3382 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3387 as_tsktsk (_("register list not in ascending order"));
3390 if (*input_line_pointer
== '-')
3392 input_line_pointer
++;
3393 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3396 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3399 else if (reg
>= hi_reg
)
3401 as_bad (_("bad register range"));
3404 for (; reg
< hi_reg
; reg
++)
3408 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3410 if (*input_line_pointer
== '}')
3411 input_line_pointer
++;
3413 demand_empty_rest_of_line ();
3415 /* Generate any deferred opcodes because we're going to be looking at
3417 flush_pending_unwind ();
3419 for (i
= 0; i
< 16; i
++)
3421 if (mask
& (1 << i
))
3422 unwind
.frame_size
+= 8;
3425 /* Attempt to combine with a previous opcode. We do this because gcc
3426 likes to output separate unwind directives for a single block of
3428 if (unwind
.opcode_count
> 0)
3430 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3431 if ((i
& 0xf8) == 0xc0)
3434 /* Only merge if the blocks are contiguous. */
3437 if ((mask
& 0xfe00) == (1 << 9))
3439 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3440 unwind
.opcode_count
--;
3443 else if (i
== 6 && unwind
.opcode_count
>= 2)
3445 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3449 op
= 0xffff << (reg
- 1);
3451 && ((mask
& op
) == (1u << (reg
- 1))))
3453 op
= (1 << (reg
+ i
+ 1)) - 1;
3454 op
&= ~((1 << reg
) - 1);
3456 unwind
.opcode_count
-= 2;
3463 /* We want to generate opcodes in the order the registers have been
3464 saved, ie. descending order. */
3465 for (reg
= 15; reg
>= -1; reg
--)
3467 /* Save registers in blocks. */
3469 || !(mask
& (1 << reg
)))
3471 /* We found an unsaved reg. Generate opcodes to save the
3472 preceeding block. */
3478 op
= 0xc0 | (hi_reg
- 10);
3479 add_unwind_opcode (op
, 1);
3484 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3485 add_unwind_opcode (op
, 2);
3494 ignore_rest_of_line ();
3498 s_arm_unwind_save_mmxwcg (void)
3505 if (*input_line_pointer
== '{')
3506 input_line_pointer
++;
3510 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3514 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3520 as_tsktsk (_("register list not in ascending order"));
3523 if (*input_line_pointer
== '-')
3525 input_line_pointer
++;
3526 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3529 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3532 else if (reg
>= hi_reg
)
3534 as_bad (_("bad register range"));
3537 for (; reg
< hi_reg
; reg
++)
3541 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3543 if (*input_line_pointer
== '}')
3544 input_line_pointer
++;
3546 demand_empty_rest_of_line ();
3548 /* Generate any deferred opcodes because we're going to be looking at
3550 flush_pending_unwind ();
3552 for (reg
= 0; reg
< 16; reg
++)
3554 if (mask
& (1 << reg
))
3555 unwind
.frame_size
+= 4;
3558 add_unwind_opcode (op
, 2);
3561 ignore_rest_of_line ();
3565 /* Parse an unwind_save directive.
3566 If the argument is non-zero, this is a .vsave directive. */
3569 s_arm_unwind_save (int arch_v6
)
3572 struct reg_entry
*reg
;
3573 bfd_boolean had_brace
= FALSE
;
3575 /* Figure out what sort of save we have. */
3576 peek
= input_line_pointer
;
3584 reg
= arm_reg_parse_multi (&peek
);
3588 as_bad (_("register expected"));
3589 ignore_rest_of_line ();
3598 as_bad (_("FPA .unwind_save does not take a register list"));
3599 ignore_rest_of_line ();
3602 s_arm_unwind_save_fpa (reg
->number
);
3605 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3608 s_arm_unwind_save_vfp_armv6 ();
3610 s_arm_unwind_save_vfp ();
3612 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3613 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3616 as_bad (_(".unwind_save does not support this kind of register"));
3617 ignore_rest_of_line ();
3622 /* Parse an unwind_movsp directive. */
3625 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3630 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3633 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3634 ignore_rest_of_line ();
3637 demand_empty_rest_of_line ();
3639 if (reg
== REG_SP
|| reg
== REG_PC
)
3641 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3645 if (unwind
.fp_reg
!= REG_SP
)
3646 as_bad (_("unexpected .unwind_movsp directive"));
3648 /* Generate opcode to restore the value. */
3650 add_unwind_opcode (op
, 1);
3652 /* Record the information for later. */
3653 unwind
.fp_reg
= reg
;
3654 unwind
.fp_offset
= unwind
.frame_size
;
3655 unwind
.sp_restored
= 1;
3658 /* Parse an unwind_pad directive. */
3661 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3665 if (immediate_for_directive (&offset
) == FAIL
)
3670 as_bad (_("stack increment must be multiple of 4"));
3671 ignore_rest_of_line ();
3675 /* Don't generate any opcodes, just record the details for later. */
3676 unwind
.frame_size
+= offset
;
3677 unwind
.pending_offset
+= offset
;
3679 demand_empty_rest_of_line ();
3682 /* Parse an unwind_setfp directive. */
3685 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3691 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3692 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3695 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3697 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3699 as_bad (_("expected <reg>, <reg>"));
3700 ignore_rest_of_line ();
3704 /* Optional constant. */
3705 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3707 if (immediate_for_directive (&offset
) == FAIL
)
3713 demand_empty_rest_of_line ();
3715 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3717 as_bad (_("register must be either sp or set by a previous"
3718 "unwind_movsp directive"));
3722 /* Don't generate any opcodes, just record the information for later. */
3723 unwind
.fp_reg
= fp_reg
;
3726 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3728 unwind
.fp_offset
-= offset
;
3731 /* Parse an unwind_raw directive. */
3734 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3737 /* This is an arbitrary limit. */
3738 unsigned char op
[16];
3742 if (exp
.X_op
== O_constant
3743 && skip_past_comma (&input_line_pointer
) != FAIL
)
3745 unwind
.frame_size
+= exp
.X_add_number
;
3749 exp
.X_op
= O_illegal
;
3751 if (exp
.X_op
!= O_constant
)
3753 as_bad (_("expected <offset>, <opcode>"));
3754 ignore_rest_of_line ();
3760 /* Parse the opcode. */
3765 as_bad (_("unwind opcode too long"));
3766 ignore_rest_of_line ();
3768 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3770 as_bad (_("invalid unwind opcode"));
3771 ignore_rest_of_line ();
3774 op
[count
++] = exp
.X_add_number
;
3776 /* Parse the next byte. */
3777 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3783 /* Add the opcode bytes in reverse order. */
3785 add_unwind_opcode (op
[count
], 1);
3787 demand_empty_rest_of_line ();
3791 /* Parse a .eabi_attribute directive. */
3794 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3797 bfd_boolean is_string
;
3804 if (exp
.X_op
!= O_constant
)
3807 tag
= exp
.X_add_number
;
3808 if (tag
== 4 || tag
== 5 || tag
== 32 || (tag
> 32 && (tag
& 1) != 0))
3813 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3815 if (tag
== 32 || !is_string
)
3818 if (exp
.X_op
!= O_constant
)
3820 as_bad (_("expected numeric constant"));
3821 ignore_rest_of_line ();
3824 i
= exp
.X_add_number
;
3826 if (tag
== Tag_compatibility
3827 && skip_past_comma (&input_line_pointer
) == FAIL
)
3829 as_bad (_("expected comma"));
3830 ignore_rest_of_line ();
3835 skip_whitespace(input_line_pointer
);
3836 if (*input_line_pointer
!= '"')
3838 input_line_pointer
++;
3839 s
= input_line_pointer
;
3840 while (*input_line_pointer
&& *input_line_pointer
!= '"')
3841 input_line_pointer
++;
3842 if (*input_line_pointer
!= '"')
3844 saved_char
= *input_line_pointer
;
3845 *input_line_pointer
= 0;
3853 if (tag
== Tag_compatibility
)
3854 elf32_arm_add_eabi_attr_compat (stdoutput
, i
, s
);
3856 elf32_arm_add_eabi_attr_string (stdoutput
, tag
, s
);
3858 elf32_arm_add_eabi_attr_int (stdoutput
, tag
, i
);
3862 *input_line_pointer
= saved_char
;
3863 input_line_pointer
++;
3865 demand_empty_rest_of_line ();
3868 as_bad (_("bad string constant"));
3869 ignore_rest_of_line ();
3872 as_bad (_("expected <tag> , <value>"));
3873 ignore_rest_of_line ();
3875 #endif /* OBJ_ELF */
3877 static void s_arm_arch (int);
3878 static void s_arm_cpu (int);
3879 static void s_arm_fpu (int);
3884 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3891 if (exp
.X_op
== O_symbol
)
3892 exp
.X_op
= O_secrel
;
3894 emit_expr (&exp
, 4);
3896 while (*input_line_pointer
++ == ',');
3898 input_line_pointer
--;
3899 demand_empty_rest_of_line ();
3903 /* This table describes all the machine specific pseudo-ops the assembler
3904 has to support. The fields are:
3905 pseudo-op name without dot
3906 function to call to execute this pseudo-op
3907 Integer arg to pass to the function. */
3909 const pseudo_typeS md_pseudo_table
[] =
3911 /* Never called because '.req' does not start a line. */
3912 { "req", s_req
, 0 },
3913 /* Following two are likewise never called. */
3916 { "unreq", s_unreq
, 0 },
3917 { "bss", s_bss
, 0 },
3918 { "align", s_align
, 0 },
3919 { "arm", s_arm
, 0 },
3920 { "thumb", s_thumb
, 0 },
3921 { "code", s_code
, 0 },
3922 { "force_thumb", s_force_thumb
, 0 },
3923 { "thumb_func", s_thumb_func
, 0 },
3924 { "thumb_set", s_thumb_set
, 0 },
3925 { "even", s_even
, 0 },
3926 { "ltorg", s_ltorg
, 0 },
3927 { "pool", s_ltorg
, 0 },
3928 { "syntax", s_syntax
, 0 },
3929 { "cpu", s_arm_cpu
, 0 },
3930 { "arch", s_arm_arch
, 0 },
3931 { "fpu", s_arm_fpu
, 0 },
3933 { "word", s_arm_elf_cons
, 4 },
3934 { "long", s_arm_elf_cons
, 4 },
3935 { "rel31", s_arm_rel31
, 0 },
3936 { "fnstart", s_arm_unwind_fnstart
, 0 },
3937 { "fnend", s_arm_unwind_fnend
, 0 },
3938 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3939 { "personality", s_arm_unwind_personality
, 0 },
3940 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3941 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3942 { "save", s_arm_unwind_save
, 0 },
3943 { "vsave", s_arm_unwind_save
, 1 },
3944 { "movsp", s_arm_unwind_movsp
, 0 },
3945 { "pad", s_arm_unwind_pad
, 0 },
3946 { "setfp", s_arm_unwind_setfp
, 0 },
3947 { "unwind_raw", s_arm_unwind_raw
, 0 },
3948 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3952 /* These are used for dwarf. */
3956 /* These are used for dwarf2. */
3957 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3958 { "loc", dwarf2_directive_loc
, 0 },
3959 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3961 { "extend", float_cons
, 'x' },
3962 { "ldouble", float_cons
, 'x' },
3963 { "packed", float_cons
, 'p' },
3965 {"secrel32", pe_directive_secrel
, 0},
3970 /* Parser functions used exclusively in instruction operands. */
3972 /* Generic immediate-value read function for use in insn parsing.
3973 STR points to the beginning of the immediate (the leading #);
3974 VAL receives the value; if the value is outside [MIN, MAX]
3975 issue an error. PREFIX_OPT is true if the immediate prefix is
3979 parse_immediate (char **str
, int *val
, int min
, int max
,
3980 bfd_boolean prefix_opt
)
3983 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3984 if (exp
.X_op
!= O_constant
)
3986 inst
.error
= _("constant expression required");
3990 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
3992 inst
.error
= _("immediate value out of range");
3996 *val
= exp
.X_add_number
;
4000 /* Less-generic immediate-value read function with the possibility of loading a
4001 big (64-bit) immediate, as required by Neon VMOV and VMVN immediate
4002 instructions. Puts the result directly in inst.operands[i]. */
4005 parse_big_immediate (char **str
, int i
)
4010 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4012 if (exp
.X_op
== O_constant
)
4013 inst
.operands
[i
].imm
= exp
.X_add_number
;
4014 else if (exp
.X_op
== O_big
4015 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4016 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4018 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4019 /* Bignums have their least significant bits in
4020 generic_bignum[0]. Make sure we put 32 bits in imm and
4021 32 bits in reg, in a (hopefully) portable way. */
4022 assert (parts
!= 0);
4023 inst
.operands
[i
].imm
= 0;
4024 for (j
= 0; j
< parts
; j
++, idx
++)
4025 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4026 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4027 inst
.operands
[i
].reg
= 0;
4028 for (j
= 0; j
< parts
; j
++, idx
++)
4029 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4030 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4031 inst
.operands
[i
].regisimm
= 1;
4041 /* Returns the pseudo-register number of an FPA immediate constant,
4042 or FAIL if there isn't a valid constant here. */
4045 parse_fpa_immediate (char ** str
)
4047 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4053 /* First try and match exact strings, this is to guarantee
4054 that some formats will work even for cross assembly. */
4056 for (i
= 0; fp_const
[i
]; i
++)
4058 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4062 *str
+= strlen (fp_const
[i
]);
4063 if (is_end_of_line
[(unsigned char) **str
])
4069 /* Just because we didn't get a match doesn't mean that the constant
4070 isn't valid, just that it is in a format that we don't
4071 automatically recognize. Try parsing it with the standard
4072 expression routines. */
4074 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4076 /* Look for a raw floating point number. */
4077 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4078 && is_end_of_line
[(unsigned char) *save_in
])
4080 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4082 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4084 if (words
[j
] != fp_values
[i
][j
])
4088 if (j
== MAX_LITTLENUMS
)
4096 /* Try and parse a more complex expression, this will probably fail
4097 unless the code uses a floating point prefix (eg "0f"). */
4098 save_in
= input_line_pointer
;
4099 input_line_pointer
= *str
;
4100 if (expression (&exp
) == absolute_section
4101 && exp
.X_op
== O_big
4102 && exp
.X_add_number
< 0)
4104 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4106 if (gen_to_words (words
, 5, (long) 15) == 0)
4108 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4110 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4112 if (words
[j
] != fp_values
[i
][j
])
4116 if (j
== MAX_LITTLENUMS
)
4118 *str
= input_line_pointer
;
4119 input_line_pointer
= save_in
;
4126 *str
= input_line_pointer
;
4127 input_line_pointer
= save_in
;
4128 inst
.error
= _("invalid FPA immediate expression");
4132 /* Returns 1 if a number has "quarter-precision" float format
4133 0baBbbbbbc defgh000 00000000 00000000. */
4136 is_quarter_float (unsigned imm
)
4138 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4139 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4142 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4143 0baBbbbbbc defgh000 00000000 00000000.
4144 The minus-zero case needs special handling, since it can't be encoded in the
4145 "quarter-precision" float format, but can nonetheless be loaded as an integer
4149 parse_qfloat_immediate (char **ccp
, int *immed
)
4152 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4154 skip_past_char (&str
, '#');
4156 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4158 unsigned fpword
= 0;
4161 /* Our FP word must be 32 bits (single-precision FP). */
4162 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4164 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4168 if (is_quarter_float (fpword
) || fpword
== 0x80000000)
4181 /* Shift operands. */
4184 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4187 struct asm_shift_name
4190 enum shift_kind kind
;
4193 /* Third argument to parse_shift. */
4194 enum parse_shift_mode
4196 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4197 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4198 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4199 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4200 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4203 /* Parse a <shift> specifier on an ARM data processing instruction.
4204 This has three forms:
4206 (LSL|LSR|ASL|ASR|ROR) Rs
4207 (LSL|LSR|ASL|ASR|ROR) #imm
4210 Note that ASL is assimilated to LSL in the instruction encoding, and
4211 RRX to ROR #0 (which cannot be written as such). */
4214 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4216 const struct asm_shift_name
*shift_name
;
4217 enum shift_kind shift
;
4222 for (p
= *str
; ISALPHA (*p
); p
++)
4227 inst
.error
= _("shift expression expected");
4231 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4233 if (shift_name
== NULL
)
4235 inst
.error
= _("shift expression expected");
4239 shift
= shift_name
->kind
;
4243 case NO_SHIFT_RESTRICT
:
4244 case SHIFT_IMMEDIATE
: break;
4246 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4247 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4249 inst
.error
= _("'LSL' or 'ASR' required");
4254 case SHIFT_LSL_IMMEDIATE
:
4255 if (shift
!= SHIFT_LSL
)
4257 inst
.error
= _("'LSL' required");
4262 case SHIFT_ASR_IMMEDIATE
:
4263 if (shift
!= SHIFT_ASR
)
4265 inst
.error
= _("'ASR' required");
4273 if (shift
!= SHIFT_RRX
)
4275 /* Whitespace can appear here if the next thing is a bare digit. */
4276 skip_whitespace (p
);
4278 if (mode
== NO_SHIFT_RESTRICT
4279 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4281 inst
.operands
[i
].imm
= reg
;
4282 inst
.operands
[i
].immisreg
= 1;
4284 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4287 inst
.operands
[i
].shift_kind
= shift
;
4288 inst
.operands
[i
].shifted
= 1;
4293 /* Parse a <shifter_operand> for an ARM data processing instruction:
4296 #<immediate>, <rotate>
4300 where <shift> is defined by parse_shift above, and <rotate> is a
4301 multiple of 2 between 0 and 30. Validation of immediate operands
4302 is deferred to md_apply_fix. */
4305 parse_shifter_operand (char **str
, int i
)
4310 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4312 inst
.operands
[i
].reg
= value
;
4313 inst
.operands
[i
].isreg
= 1;
4315 /* parse_shift will override this if appropriate */
4316 inst
.reloc
.exp
.X_op
= O_constant
;
4317 inst
.reloc
.exp
.X_add_number
= 0;
4319 if (skip_past_comma (str
) == FAIL
)
4322 /* Shift operation on register. */
4323 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4326 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4329 if (skip_past_comma (str
) == SUCCESS
)
4331 /* #x, y -- ie explicit rotation by Y. */
4332 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4335 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4337 inst
.error
= _("constant expression expected");
4341 value
= expr
.X_add_number
;
4342 if (value
< 0 || value
> 30 || value
% 2 != 0)
4344 inst
.error
= _("invalid rotation");
4347 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4349 inst
.error
= _("invalid constant");
4353 /* Convert to decoded value. md_apply_fix will put it back. */
4354 inst
.reloc
.exp
.X_add_number
4355 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4356 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4359 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4360 inst
.reloc
.pc_rel
= 0;
4364 /* Group relocation information. Each entry in the table contains the
4365 textual name of the relocation as may appear in assembler source
4366 and must end with a colon.
4367 Along with this textual name are the relocation codes to be used if
4368 the corresponding instruction is an ALU instruction (ADD or SUB only),
4369 an LDR, an LDRS, or an LDC. */
4371 struct group_reloc_table_entry
4382 /* Varieties of non-ALU group relocation. */
4389 static struct group_reloc_table_entry group_reloc_table
[] =
4390 { /* Program counter relative: */
4392 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4397 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4398 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4399 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4400 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4402 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4407 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4408 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4409 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4410 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4412 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4413 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4414 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4415 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4416 /* Section base relative */
4418 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4423 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4424 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4425 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4426 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4428 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4433 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4434 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4435 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4436 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4438 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4439 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4440 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4441 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4443 /* Given the address of a pointer pointing to the textual name of a group
4444 relocation as may appear in assembler source, attempt to find its details
4445 in group_reloc_table. The pointer will be updated to the character after
4446 the trailing colon. On failure, FAIL will be returned; SUCCESS
4447 otherwise. On success, *entry will be updated to point at the relevant
4448 group_reloc_table entry. */
4451 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4454 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4456 int length
= strlen (group_reloc_table
[i
].name
);
4458 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0 &&
4459 (*str
)[length
] == ':')
4461 *out
= &group_reloc_table
[i
];
4462 *str
+= (length
+ 1);
4470 /* Parse a <shifter_operand> for an ARM data processing instruction
4471 (as for parse_shifter_operand) where group relocations are allowed:
4474 #<immediate>, <rotate>
4475 #:<group_reloc>:<expression>
4479 where <group_reloc> is one of the strings defined in group_reloc_table.
4480 The hashes are optional.
4482 Everything else is as for parse_shifter_operand. */
4484 static parse_operand_result
4485 parse_shifter_operand_group_reloc (char **str
, int i
)
4487 /* Determine if we have the sequence of characters #: or just :
4488 coming next. If we do, then we check for a group relocation.
4489 If we don't, punt the whole lot to parse_shifter_operand. */
4491 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4492 || (*str
)[0] == ':')
4494 struct group_reloc_table_entry
*entry
;
4496 if ((*str
)[0] == '#')
4501 /* Try to parse a group relocation. Anything else is an error. */
4502 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4504 inst
.error
= _("unknown group relocation");
4505 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4508 /* We now have the group relocation table entry corresponding to
4509 the name in the assembler source. Next, we parse the expression. */
4510 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4511 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4513 /* Record the relocation type (always the ALU variant here). */
4514 inst
.reloc
.type
= entry
->alu_code
;
4515 assert (inst
.reloc
.type
!= 0);
4517 return PARSE_OPERAND_SUCCESS
;
4520 return parse_shifter_operand (str
, i
) == SUCCESS
4521 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4523 /* Never reached. */
4526 /* Parse all forms of an ARM address expression. Information is written
4527 to inst.operands[i] and/or inst.reloc.
4529 Preindexed addressing (.preind=1):
4531 [Rn, #offset] .reg=Rn .reloc.exp=offset
4532 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4533 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4534 .shift_kind=shift .reloc.exp=shift_imm
4536 These three may have a trailing ! which causes .writeback to be set also.
4538 Postindexed addressing (.postind=1, .writeback=1):
4540 [Rn], #offset .reg=Rn .reloc.exp=offset
4541 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4542 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4543 .shift_kind=shift .reloc.exp=shift_imm
4545 Unindexed addressing (.preind=0, .postind=0):
4547 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4551 [Rn]{!} shorthand for [Rn,#0]{!}
4552 =immediate .isreg=0 .reloc.exp=immediate
4553 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4555 It is the caller's responsibility to check for addressing modes not
4556 supported by the instruction, and to set inst.reloc.type. */
4558 static parse_operand_result
4559 parse_address_main (char **str
, int i
, int group_relocations
,
4560 group_reloc_type group_type
)
4565 if (skip_past_char (&p
, '[') == FAIL
)
4567 if (skip_past_char (&p
, '=') == FAIL
)
4569 /* bare address - translate to PC-relative offset */
4570 inst
.reloc
.pc_rel
= 1;
4571 inst
.operands
[i
].reg
= REG_PC
;
4572 inst
.operands
[i
].isreg
= 1;
4573 inst
.operands
[i
].preind
= 1;
4575 /* else a load-constant pseudo op, no special treatment needed here */
4577 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4578 return PARSE_OPERAND_FAIL
;
4581 return PARSE_OPERAND_SUCCESS
;
4584 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4586 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4587 return PARSE_OPERAND_FAIL
;
4589 inst
.operands
[i
].reg
= reg
;
4590 inst
.operands
[i
].isreg
= 1;
4592 if (skip_past_comma (&p
) == SUCCESS
)
4594 inst
.operands
[i
].preind
= 1;
4597 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4599 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4601 inst
.operands
[i
].imm
= reg
;
4602 inst
.operands
[i
].immisreg
= 1;
4604 if (skip_past_comma (&p
) == SUCCESS
)
4605 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4606 return PARSE_OPERAND_FAIL
;
4608 else if (skip_past_char (&p
, ':') == SUCCESS
)
4610 /* FIXME: '@' should be used here, but it's filtered out by generic
4611 code before we get to see it here. This may be subject to
4614 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4615 if (exp
.X_op
!= O_constant
)
4617 inst
.error
= _("alignment must be constant");
4618 return PARSE_OPERAND_FAIL
;
4620 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4621 inst
.operands
[i
].immisalign
= 1;
4622 /* Alignments are not pre-indexes. */
4623 inst
.operands
[i
].preind
= 0;
4627 if (inst
.operands
[i
].negative
)
4629 inst
.operands
[i
].negative
= 0;
4633 if (group_relocations
&&
4634 ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4637 struct group_reloc_table_entry
*entry
;
4639 /* Skip over the #: or : sequence. */
4645 /* Try to parse a group relocation. Anything else is an
4647 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4649 inst
.error
= _("unknown group relocation");
4650 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4653 /* We now have the group relocation table entry corresponding to
4654 the name in the assembler source. Next, we parse the
4656 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4657 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4659 /* Record the relocation type. */
4663 inst
.reloc
.type
= entry
->ldr_code
;
4667 inst
.reloc
.type
= entry
->ldrs_code
;
4671 inst
.reloc
.type
= entry
->ldc_code
;
4678 if (inst
.reloc
.type
== 0)
4680 inst
.error
= _("this group relocation is not allowed on this instruction");
4681 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4685 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4686 return PARSE_OPERAND_FAIL
;
4690 if (skip_past_char (&p
, ']') == FAIL
)
4692 inst
.error
= _("']' expected");
4693 return PARSE_OPERAND_FAIL
;
4696 if (skip_past_char (&p
, '!') == SUCCESS
)
4697 inst
.operands
[i
].writeback
= 1;
4699 else if (skip_past_comma (&p
) == SUCCESS
)
4701 if (skip_past_char (&p
, '{') == SUCCESS
)
4703 /* [Rn], {expr} - unindexed, with option */
4704 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4705 0, 255, TRUE
) == FAIL
)
4706 return PARSE_OPERAND_FAIL
;
4708 if (skip_past_char (&p
, '}') == FAIL
)
4710 inst
.error
= _("'}' expected at end of 'option' field");
4711 return PARSE_OPERAND_FAIL
;
4713 if (inst
.operands
[i
].preind
)
4715 inst
.error
= _("cannot combine index with option");
4716 return PARSE_OPERAND_FAIL
;
4719 return PARSE_OPERAND_SUCCESS
;
4723 inst
.operands
[i
].postind
= 1;
4724 inst
.operands
[i
].writeback
= 1;
4726 if (inst
.operands
[i
].preind
)
4728 inst
.error
= _("cannot combine pre- and post-indexing");
4729 return PARSE_OPERAND_FAIL
;
4733 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4735 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4737 /* We might be using the immediate for alignment already. If we
4738 are, OR the register number into the low-order bits. */
4739 if (inst
.operands
[i
].immisalign
)
4740 inst
.operands
[i
].imm
|= reg
;
4742 inst
.operands
[i
].imm
= reg
;
4743 inst
.operands
[i
].immisreg
= 1;
4745 if (skip_past_comma (&p
) == SUCCESS
)
4746 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4747 return PARSE_OPERAND_FAIL
;
4751 if (inst
.operands
[i
].negative
)
4753 inst
.operands
[i
].negative
= 0;
4756 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4757 return PARSE_OPERAND_FAIL
;
4762 /* If at this point neither .preind nor .postind is set, we have a
4763 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4764 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4766 inst
.operands
[i
].preind
= 1;
4767 inst
.reloc
.exp
.X_op
= O_constant
;
4768 inst
.reloc
.exp
.X_add_number
= 0;
4771 return PARSE_OPERAND_SUCCESS
;
4775 parse_address (char **str
, int i
)
4777 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4781 static parse_operand_result
4782 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4784 return parse_address_main (str
, i
, 1, type
);
4787 /* Parse an operand for a MOVW or MOVT instruction. */
4789 parse_half (char **str
)
4794 skip_past_char (&p
, '#');
4795 if (strncasecmp (p
, ":lower16:", 9) == 0)
4796 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4797 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4798 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4800 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4806 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4809 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4811 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4813 inst
.error
= _("constant expression expected");
4816 if (inst
.reloc
.exp
.X_add_number
< 0
4817 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4819 inst
.error
= _("immediate value out of range");
4827 /* Miscellaneous. */
4829 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4830 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4832 parse_psr (char **str
)
4835 unsigned long psr_field
;
4836 const struct asm_psr
*psr
;
4839 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4840 feature for ease of use and backwards compatibility. */
4842 if (strncasecmp (p
, "SPSR", 4) == 0)
4843 psr_field
= SPSR_BIT
;
4844 else if (strncasecmp (p
, "CPSR", 4) == 0)
4851 while (ISALNUM (*p
) || *p
== '_');
4853 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4864 /* A suffix follows. */
4870 while (ISALNUM (*p
) || *p
== '_');
4872 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4876 psr_field
|= psr
->field
;
4881 goto error
; /* Garbage after "[CS]PSR". */
4883 psr_field
|= (PSR_c
| PSR_f
);
4889 inst
.error
= _("flag for {c}psr instruction expected");
4893 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4894 value suitable for splatting into the AIF field of the instruction. */
4897 parse_cps_flags (char **str
)
4906 case '\0': case ',':
4909 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4910 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4911 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4914 inst
.error
= _("unrecognized CPS flag");
4919 if (saw_a_flag
== 0)
4921 inst
.error
= _("missing CPS flags");
4929 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4930 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4933 parse_endian_specifier (char **str
)
4938 if (strncasecmp (s
, "BE", 2))
4940 else if (strncasecmp (s
, "LE", 2))
4944 inst
.error
= _("valid endian specifiers are be or le");
4948 if (ISALNUM (s
[2]) || s
[2] == '_')
4950 inst
.error
= _("valid endian specifiers are be or le");
4955 return little_endian
;
4958 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
4959 value suitable for poking into the rotate field of an sxt or sxta
4960 instruction, or FAIL on error. */
4963 parse_ror (char **str
)
4968 if (strncasecmp (s
, "ROR", 3) == 0)
4972 inst
.error
= _("missing rotation field after comma");
4976 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
4981 case 0: *str
= s
; return 0x0;
4982 case 8: *str
= s
; return 0x1;
4983 case 16: *str
= s
; return 0x2;
4984 case 24: *str
= s
; return 0x3;
4987 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
4992 /* Parse a conditional code (from conds[] below). The value returned is in the
4993 range 0 .. 14, or FAIL. */
4995 parse_cond (char **str
)
4998 const struct asm_cond
*c
;
5001 while (ISALPHA (*q
))
5004 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
5007 inst
.error
= _("condition required");
5015 /* Parse an option for a barrier instruction. Returns the encoding for the
5018 parse_barrier (char **str
)
5021 const struct asm_barrier_opt
*o
;
5024 while (ISALPHA (*q
))
5027 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5035 /* Parse the operands of a table branch instruction. Similar to a memory
5038 parse_tb (char **str
)
5043 if (skip_past_char (&p
, '[') == FAIL
)
5045 inst
.error
= _("'[' expected");
5049 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5051 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5054 inst
.operands
[0].reg
= reg
;
5056 if (skip_past_comma (&p
) == FAIL
)
5058 inst
.error
= _("',' expected");
5062 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5064 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5067 inst
.operands
[0].imm
= reg
;
5069 if (skip_past_comma (&p
) == SUCCESS
)
5071 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5073 if (inst
.reloc
.exp
.X_add_number
!= 1)
5075 inst
.error
= _("invalid shift");
5078 inst
.operands
[0].shifted
= 1;
5081 if (skip_past_char (&p
, ']') == FAIL
)
5083 inst
.error
= _("']' expected");
5090 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5091 information on the types the operands can take and how they are encoded.
5092 Up to four operands may be read; this function handles setting the
5093 ".present" field for each read operand itself.
5094 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5095 else returns FAIL. */
5098 parse_neon_mov (char **str
, int *which_operand
)
5100 int i
= *which_operand
, val
;
5101 enum arm_reg_type rtype
;
5103 struct neon_type_el optype
;
5105 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5107 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5108 inst
.operands
[i
].reg
= val
;
5109 inst
.operands
[i
].isscalar
= 1;
5110 inst
.operands
[i
].vectype
= optype
;
5111 inst
.operands
[i
++].present
= 1;
5113 if (skip_past_comma (&ptr
) == FAIL
)
5116 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5119 inst
.operands
[i
].reg
= val
;
5120 inst
.operands
[i
].isreg
= 1;
5121 inst
.operands
[i
].present
= 1;
5123 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5126 /* Cases 0, 1, 2, 3, 5 (D only). */
5127 if (skip_past_comma (&ptr
) == FAIL
)
5130 inst
.operands
[i
].reg
= val
;
5131 inst
.operands
[i
].isreg
= 1;
5132 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5133 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5134 inst
.operands
[i
].isvec
= 1;
5135 inst
.operands
[i
].vectype
= optype
;
5136 inst
.operands
[i
++].present
= 1;
5138 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5140 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5141 Case 13: VMOV <Sd>, <Rm> */
5142 inst
.operands
[i
].reg
= val
;
5143 inst
.operands
[i
].isreg
= 1;
5144 inst
.operands
[i
].present
= 1;
5146 if (rtype
== REG_TYPE_NQ
)
5148 first_error (_("can't use Neon quad register here"));
5151 else if (rtype
!= REG_TYPE_VFS
)
5154 if (skip_past_comma (&ptr
) == FAIL
)
5156 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5158 inst
.operands
[i
].reg
= val
;
5159 inst
.operands
[i
].isreg
= 1;
5160 inst
.operands
[i
].present
= 1;
5163 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5164 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5165 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5166 Case 10: VMOV.F32 <Sd>, #<imm>
5167 Case 11: VMOV.F64 <Dd>, #<imm> */
5169 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5170 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5171 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5173 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5176 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5177 Case 1: VMOV<c><q> <Dd>, <Dm>
5178 Case 8: VMOV.F32 <Sd>, <Sm>
5179 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5181 inst
.operands
[i
].reg
= val
;
5182 inst
.operands
[i
].isreg
= 1;
5183 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5184 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5185 inst
.operands
[i
].isvec
= 1;
5186 inst
.operands
[i
].vectype
= optype
;
5187 inst
.operands
[i
].present
= 1;
5189 if (skip_past_comma (&ptr
) == SUCCESS
)
5194 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5197 inst
.operands
[i
].reg
= val
;
5198 inst
.operands
[i
].isreg
= 1;
5199 inst
.operands
[i
++].present
= 1;
5201 if (skip_past_comma (&ptr
) == FAIL
)
5204 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5207 inst
.operands
[i
].reg
= val
;
5208 inst
.operands
[i
].isreg
= 1;
5209 inst
.operands
[i
++].present
= 1;
5214 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5218 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5221 inst
.operands
[i
].reg
= val
;
5222 inst
.operands
[i
].isreg
= 1;
5223 inst
.operands
[i
++].present
= 1;
5225 if (skip_past_comma (&ptr
) == FAIL
)
5228 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5230 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5231 inst
.operands
[i
].reg
= val
;
5232 inst
.operands
[i
].isscalar
= 1;
5233 inst
.operands
[i
].present
= 1;
5234 inst
.operands
[i
].vectype
= optype
;
5236 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5238 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5239 inst
.operands
[i
].reg
= val
;
5240 inst
.operands
[i
].isreg
= 1;
5241 inst
.operands
[i
++].present
= 1;
5243 if (skip_past_comma (&ptr
) == FAIL
)
5246 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5249 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5253 inst
.operands
[i
].reg
= val
;
5254 inst
.operands
[i
].isreg
= 1;
5255 inst
.operands
[i
].isvec
= 1;
5256 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5257 inst
.operands
[i
].vectype
= optype
;
5258 inst
.operands
[i
].present
= 1;
5260 if (rtype
== REG_TYPE_VFS
)
5264 if (skip_past_comma (&ptr
) == FAIL
)
5266 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5269 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5272 inst
.operands
[i
].reg
= val
;
5273 inst
.operands
[i
].isreg
= 1;
5274 inst
.operands
[i
].isvec
= 1;
5275 inst
.operands
[i
].issingle
= 1;
5276 inst
.operands
[i
].vectype
= optype
;
5277 inst
.operands
[i
].present
= 1;
5280 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5284 inst
.operands
[i
].reg
= val
;
5285 inst
.operands
[i
].isreg
= 1;
5286 inst
.operands
[i
].isvec
= 1;
5287 inst
.operands
[i
].issingle
= 1;
5288 inst
.operands
[i
].vectype
= optype
;
5289 inst
.operands
[i
++].present
= 1;
5294 first_error (_("parse error"));
5298 /* Successfully parsed the operands. Update args. */
5304 first_error (_("expected comma"));
5308 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5312 /* Matcher codes for parse_operands. */
5313 enum operand_parse_code
5315 OP_stop
, /* end of line */
5317 OP_RR
, /* ARM register */
5318 OP_RRnpc
, /* ARM register, not r15 */
5319 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5320 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5321 OP_RCP
, /* Coprocessor number */
5322 OP_RCN
, /* Coprocessor register */
5323 OP_RF
, /* FPA register */
5324 OP_RVS
, /* VFP single precision register */
5325 OP_RVD
, /* VFP double precision register (0..15) */
5326 OP_RND
, /* Neon double precision register (0..31) */
5327 OP_RNQ
, /* Neon quad precision register */
5328 OP_RVSD
, /* VFP single or double precision register */
5329 OP_RNDQ
, /* Neon double or quad precision register */
5330 OP_RNSDQ
, /* Neon single, double or quad precision register */
5331 OP_RNSC
, /* Neon scalar D[X] */
5332 OP_RVC
, /* VFP control register */
5333 OP_RMF
, /* Maverick F register */
5334 OP_RMD
, /* Maverick D register */
5335 OP_RMFX
, /* Maverick FX register */
5336 OP_RMDX
, /* Maverick DX register */
5337 OP_RMAX
, /* Maverick AX register */
5338 OP_RMDS
, /* Maverick DSPSC register */
5339 OP_RIWR
, /* iWMMXt wR register */
5340 OP_RIWC
, /* iWMMXt wC register */
5341 OP_RIWG
, /* iWMMXt wCG register */
5342 OP_RXA
, /* XScale accumulator register */
5344 OP_REGLST
, /* ARM register list */
5345 OP_VRSLST
, /* VFP single-precision register list */
5346 OP_VRDLST
, /* VFP double-precision register list */
5347 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5348 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5349 OP_NSTRLST
, /* Neon element/structure list */
5351 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5352 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5353 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5354 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5355 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5356 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5357 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5358 OP_VMOV
, /* Neon VMOV operands. */
5359 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5360 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5362 OP_I0
, /* immediate zero */
5363 OP_I7
, /* immediate value 0 .. 7 */
5364 OP_I15
, /* 0 .. 15 */
5365 OP_I16
, /* 1 .. 16 */
5366 OP_I16z
, /* 0 .. 16 */
5367 OP_I31
, /* 0 .. 31 */
5368 OP_I31w
, /* 0 .. 31, optional trailing ! */
5369 OP_I32
, /* 1 .. 32 */
5370 OP_I32z
, /* 0 .. 32 */
5371 OP_I63
, /* 0 .. 63 */
5372 OP_I63s
, /* -64 .. 63 */
5373 OP_I64
, /* 1 .. 64 */
5374 OP_I64z
, /* 0 .. 64 */
5375 OP_I255
, /* 0 .. 255 */
5377 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5378 OP_I7b
, /* 0 .. 7 */
5379 OP_I15b
, /* 0 .. 15 */
5380 OP_I31b
, /* 0 .. 31 */
5382 OP_SH
, /* shifter operand */
5383 OP_SHG
, /* shifter operand with possible group relocation */
5384 OP_ADDR
, /* Memory address expression (any mode) */
5385 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5386 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5387 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5388 OP_EXP
, /* arbitrary expression */
5389 OP_EXPi
, /* same, with optional immediate prefix */
5390 OP_EXPr
, /* same, with optional relocation suffix */
5391 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5393 OP_CPSF
, /* CPS flags */
5394 OP_ENDI
, /* Endianness specifier */
5395 OP_PSR
, /* CPSR/SPSR mask for msr */
5396 OP_COND
, /* conditional code */
5397 OP_TB
, /* Table branch. */
5399 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5400 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5402 OP_RRnpc_I0
, /* ARM register or literal 0 */
5403 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5404 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5405 OP_RF_IF
, /* FPA register or immediate */
5406 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5407 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5409 /* Optional operands. */
5410 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5411 OP_oI31b
, /* 0 .. 31 */
5412 OP_oI32b
, /* 1 .. 32 */
5413 OP_oIffffb
, /* 0 .. 65535 */
5414 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5416 OP_oRR
, /* ARM register */
5417 OP_oRRnpc
, /* ARM register, not the PC */
5418 OP_oRND
, /* Optional Neon double precision register */
5419 OP_oRNQ
, /* Optional Neon quad precision register */
5420 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5421 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5422 OP_oSHll
, /* LSL immediate */
5423 OP_oSHar
, /* ASR immediate */
5424 OP_oSHllar
, /* LSL or ASR immediate */
5425 OP_oROR
, /* ROR 0/8/16/24 */
5426 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5428 OP_FIRST_OPTIONAL
= OP_oI7b
5431 /* Generic instruction operand parser. This does no encoding and no
5432 semantic validation; it merely squirrels values away in the inst
5433 structure. Returns SUCCESS or FAIL depending on whether the
5434 specified grammar matched. */
5436 parse_operands (char *str
, const unsigned char *pattern
)
5438 unsigned const char *upat
= pattern
;
5439 char *backtrack_pos
= 0;
5440 const char *backtrack_error
= 0;
5441 int i
, val
, backtrack_index
= 0;
5442 enum arm_reg_type rtype
;
5443 parse_operand_result result
;
5445 #define po_char_or_fail(chr) do { \
5446 if (skip_past_char (&str, chr) == FAIL) \
5450 #define po_reg_or_fail(regtype) do { \
5451 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5452 &inst.operands[i].vectype); \
5455 first_error (_(reg_expected_msgs[regtype])); \
5458 inst.operands[i].reg = val; \
5459 inst.operands[i].isreg = 1; \
5460 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5461 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5462 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5463 || rtype == REG_TYPE_VFD \
5464 || rtype == REG_TYPE_NQ); \
5467 #define po_reg_or_goto(regtype, label) do { \
5468 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5469 &inst.operands[i].vectype); \
5473 inst.operands[i].reg = val; \
5474 inst.operands[i].isreg = 1; \
5475 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5476 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5477 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5478 || rtype == REG_TYPE_VFD \
5479 || rtype == REG_TYPE_NQ); \
5482 #define po_imm_or_fail(min, max, popt) do { \
5483 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5485 inst.operands[i].imm = val; \
5488 #define po_scalar_or_goto(elsz, label) do { \
5489 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5492 inst.operands[i].reg = val; \
5493 inst.operands[i].isscalar = 1; \
5496 #define po_misc_or_fail(expr) do { \
5501 #define po_misc_or_fail_no_backtrack(expr) do { \
5503 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5504 backtrack_pos = 0; \
5505 if (result != PARSE_OPERAND_SUCCESS) \
5509 skip_whitespace (str
);
5511 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5513 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5515 /* Remember where we are in case we need to backtrack. */
5516 assert (!backtrack_pos
);
5517 backtrack_pos
= str
;
5518 backtrack_error
= inst
.error
;
5519 backtrack_index
= i
;
5523 po_char_or_fail (',');
5531 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5532 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5533 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5534 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5535 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5536 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5538 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5539 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
5540 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5541 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5542 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5543 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5544 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5545 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5546 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5547 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5548 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5549 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5551 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5553 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5554 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5556 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5558 /* Neon scalar. Using an element size of 8 means that some invalid
5559 scalars are accepted here, so deal with those in later code. */
5560 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5562 /* WARNING: We can expand to two operands here. This has the potential
5563 to totally confuse the backtracking mechanism! It will be OK at
5564 least as long as we don't try to use optional args as well,
5568 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5569 inst
.operands
[i
].present
= 1;
5571 skip_past_comma (&str
);
5572 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5575 /* Optional register operand was omitted. Unfortunately, it's in
5576 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5577 here (this is a bit grotty). */
5578 inst
.operands
[i
] = inst
.operands
[i
-1];
5579 inst
.operands
[i
-1].present
= 0;
5582 /* Immediate gets verified properly later, so accept any now. */
5583 po_imm_or_fail (INT_MIN
, INT_MAX
, TRUE
);
5589 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5592 po_imm_or_fail (0, 0, TRUE
);
5597 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5602 po_scalar_or_goto (8, try_rr
);
5605 po_reg_or_fail (REG_TYPE_RN
);
5611 po_scalar_or_goto (8, try_nsdq
);
5614 po_reg_or_fail (REG_TYPE_NSDQ
);
5620 po_scalar_or_goto (8, try_ndq
);
5623 po_reg_or_fail (REG_TYPE_NDQ
);
5629 po_scalar_or_goto (8, try_vfd
);
5632 po_reg_or_fail (REG_TYPE_VFD
);
5637 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5638 not careful then bad things might happen. */
5639 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5644 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5647 /* There's a possibility of getting a 64-bit immediate here, so
5648 we need special handling. */
5649 if (parse_big_immediate (&str
, i
) == FAIL
)
5651 inst
.error
= _("immediate value is out of range");
5659 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5662 po_imm_or_fail (0, 63, TRUE
);
5667 po_char_or_fail ('[');
5668 po_reg_or_fail (REG_TYPE_RN
);
5669 po_char_or_fail (']');
5673 po_reg_or_fail (REG_TYPE_RN
);
5674 if (skip_past_char (&str
, '!') == SUCCESS
)
5675 inst
.operands
[i
].writeback
= 1;
5679 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5680 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5681 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5682 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5683 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5684 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5685 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5686 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5687 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5688 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5689 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5690 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5692 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5694 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5695 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5697 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5698 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5699 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5701 /* Immediate variants */
5703 po_char_or_fail ('{');
5704 po_imm_or_fail (0, 255, TRUE
);
5705 po_char_or_fail ('}');
5709 /* The expression parser chokes on a trailing !, so we have
5710 to find it first and zap it. */
5713 while (*s
&& *s
!= ',')
5718 inst
.operands
[i
].writeback
= 1;
5720 po_imm_or_fail (0, 31, TRUE
);
5728 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5733 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5738 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5740 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5742 val
= parse_reloc (&str
);
5745 inst
.error
= _("unrecognized relocation suffix");
5748 else if (val
!= BFD_RELOC_UNUSED
)
5750 inst
.operands
[i
].imm
= val
;
5751 inst
.operands
[i
].hasreloc
= 1;
5756 /* Operand for MOVW or MOVT. */
5758 po_misc_or_fail (parse_half (&str
));
5761 /* Register or expression */
5762 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5763 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5765 /* Register or immediate */
5766 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5767 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5769 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5771 if (!is_immediate_prefix (*str
))
5774 val
= parse_fpa_immediate (&str
);
5777 /* FPA immediates are encoded as registers 8-15.
5778 parse_fpa_immediate has already applied the offset. */
5779 inst
.operands
[i
].reg
= val
;
5780 inst
.operands
[i
].isreg
= 1;
5783 /* Two kinds of register */
5786 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5788 || (rege
->type
!= REG_TYPE_MMXWR
5789 && rege
->type
!= REG_TYPE_MMXWC
5790 && rege
->type
!= REG_TYPE_MMXWCG
))
5792 inst
.error
= _("iWMMXt data or control register expected");
5795 inst
.operands
[i
].reg
= rege
->number
;
5796 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5802 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5804 || (rege
->type
!= REG_TYPE_MMXWC
5805 && rege
->type
!= REG_TYPE_MMXWCG
))
5807 inst
.error
= _("iWMMXt control register expected");
5810 inst
.operands
[i
].reg
= rege
->number
;
5811 inst
.operands
[i
].isreg
= 1;
5816 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5817 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5818 case OP_oROR
: val
= parse_ror (&str
); break;
5819 case OP_PSR
: val
= parse_psr (&str
); break;
5820 case OP_COND
: val
= parse_cond (&str
); break;
5821 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5824 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5825 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5828 val
= parse_psr (&str
);
5832 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5835 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5837 if (strncasecmp (str
, "APSR_", 5) == 0)
5844 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5845 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5846 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5847 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5848 default: found
= 16;
5852 inst
.operands
[i
].isvec
= 1;
5859 po_misc_or_fail (parse_tb (&str
));
5862 /* Register lists */
5864 val
= parse_reg_list (&str
);
5867 inst
.operands
[1].writeback
= 1;
5873 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5877 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5881 /* Allow Q registers too. */
5882 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5887 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5889 inst
.operands
[i
].issingle
= 1;
5894 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5899 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5900 &inst
.operands
[i
].vectype
);
5903 /* Addressing modes */
5905 po_misc_or_fail (parse_address (&str
, i
));
5909 po_misc_or_fail_no_backtrack (
5910 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5914 po_misc_or_fail_no_backtrack (
5915 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5919 po_misc_or_fail_no_backtrack (
5920 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5924 po_misc_or_fail (parse_shifter_operand (&str
, i
));
5928 po_misc_or_fail_no_backtrack (
5929 parse_shifter_operand_group_reloc (&str
, i
));
5933 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
5937 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
5941 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
5945 as_fatal ("unhandled operand code %d", upat
[i
]);
5948 /* Various value-based sanity checks and shared operations. We
5949 do not signal immediate failures for the register constraints;
5950 this allows a syntax error to take precedence. */
5958 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
5959 inst
.error
= BAD_PC
;
5977 inst
.operands
[i
].imm
= val
;
5984 /* If we get here, this operand was successfully parsed. */
5985 inst
.operands
[i
].present
= 1;
5989 inst
.error
= BAD_ARGS
;
5994 /* The parse routine should already have set inst.error, but set a
5995 defaut here just in case. */
5997 inst
.error
= _("syntax error");
6001 /* Do not backtrack over a trailing optional argument that
6002 absorbed some text. We will only fail again, with the
6003 'garbage following instruction' error message, which is
6004 probably less helpful than the current one. */
6005 if (backtrack_index
== i
&& backtrack_pos
!= str
6006 && upat
[i
+1] == OP_stop
)
6009 inst
.error
= _("syntax error");
6013 /* Try again, skipping the optional argument at backtrack_pos. */
6014 str
= backtrack_pos
;
6015 inst
.error
= backtrack_error
;
6016 inst
.operands
[backtrack_index
].present
= 0;
6017 i
= backtrack_index
;
6021 /* Check that we have parsed all the arguments. */
6022 if (*str
!= '\0' && !inst
.error
)
6023 inst
.error
= _("garbage following instruction");
6025 return inst
.error
? FAIL
: SUCCESS
;
6028 #undef po_char_or_fail
6029 #undef po_reg_or_fail
6030 #undef po_reg_or_goto
6031 #undef po_imm_or_fail
6032 #undef po_scalar_or_fail
6034 /* Shorthand macro for instruction encoding functions issuing errors. */
6035 #define constraint(expr, err) do { \
6043 /* Functions for operand encoding. ARM, then Thumb. */
6045 #define rotate_left(v, n) (v << n | v >> (32 - n))
6047 /* If VAL can be encoded in the immediate field of an ARM instruction,
6048 return the encoded form. Otherwise, return FAIL. */
6051 encode_arm_immediate (unsigned int val
)
6055 for (i
= 0; i
< 32; i
+= 2)
6056 if ((a
= rotate_left (val
, i
)) <= 0xff)
6057 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6062 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6063 return the encoded form. Otherwise, return FAIL. */
6065 encode_thumb32_immediate (unsigned int val
)
6072 for (i
= 1; i
<= 24; i
++)
6075 if ((val
& ~(0xff << i
)) == 0)
6076 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6080 if (val
== ((a
<< 16) | a
))
6082 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6086 if (val
== ((a
<< 16) | a
))
6087 return 0x200 | (a
>> 8);
6091 /* Encode a VFP SP or DP register number into inst.instruction. */
6094 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6096 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6099 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6102 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6105 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6110 first_error (_("D register out of range for selected VFP version"));
6118 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6122 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6126 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6130 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6134 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6138 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6146 /* Encode a <shift> in an ARM-format instruction. The immediate,
6147 if any, is handled by md_apply_fix. */
6149 encode_arm_shift (int i
)
6151 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6152 inst
.instruction
|= SHIFT_ROR
<< 5;
6155 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6156 if (inst
.operands
[i
].immisreg
)
6158 inst
.instruction
|= SHIFT_BY_REG
;
6159 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6162 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6167 encode_arm_shifter_operand (int i
)
6169 if (inst
.operands
[i
].isreg
)
6171 inst
.instruction
|= inst
.operands
[i
].reg
;
6172 encode_arm_shift (i
);
6175 inst
.instruction
|= INST_IMMEDIATE
;
6178 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6180 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6182 assert (inst
.operands
[i
].isreg
);
6183 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6185 if (inst
.operands
[i
].preind
)
6189 inst
.error
= _("instruction does not accept preindexed addressing");
6192 inst
.instruction
|= PRE_INDEX
;
6193 if (inst
.operands
[i
].writeback
)
6194 inst
.instruction
|= WRITE_BACK
;
6197 else if (inst
.operands
[i
].postind
)
6199 assert (inst
.operands
[i
].writeback
);
6201 inst
.instruction
|= WRITE_BACK
;
6203 else /* unindexed - only for coprocessor */
6205 inst
.error
= _("instruction does not accept unindexed addressing");
6209 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6210 && (((inst
.instruction
& 0x000f0000) >> 16)
6211 == ((inst
.instruction
& 0x0000f000) >> 12)))
6212 as_warn ((inst
.instruction
& LOAD_BIT
)
6213 ? _("destination register same as write-back base")
6214 : _("source register same as write-back base"));
6217 /* inst.operands[i] was set up by parse_address. Encode it into an
6218 ARM-format mode 2 load or store instruction. If is_t is true,
6219 reject forms that cannot be used with a T instruction (i.e. not
6222 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6224 encode_arm_addr_mode_common (i
, is_t
);
6226 if (inst
.operands
[i
].immisreg
)
6228 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6229 inst
.instruction
|= inst
.operands
[i
].imm
;
6230 if (!inst
.operands
[i
].negative
)
6231 inst
.instruction
|= INDEX_UP
;
6232 if (inst
.operands
[i
].shifted
)
6234 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6235 inst
.instruction
|= SHIFT_ROR
<< 5;
6238 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6239 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6243 else /* immediate offset in inst.reloc */
6245 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6246 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6250 /* inst.operands[i] was set up by parse_address. Encode it into an
6251 ARM-format mode 3 load or store instruction. Reject forms that
6252 cannot be used with such instructions. If is_t is true, reject
6253 forms that cannot be used with a T instruction (i.e. not
6256 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6258 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6260 inst
.error
= _("instruction does not accept scaled register index");
6264 encode_arm_addr_mode_common (i
, is_t
);
6266 if (inst
.operands
[i
].immisreg
)
6268 inst
.instruction
|= inst
.operands
[i
].imm
;
6269 if (!inst
.operands
[i
].negative
)
6270 inst
.instruction
|= INDEX_UP
;
6272 else /* immediate offset in inst.reloc */
6274 inst
.instruction
|= HWOFFSET_IMM
;
6275 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6276 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6280 /* inst.operands[i] was set up by parse_address. Encode it into an
6281 ARM-format instruction. Reject all forms which cannot be encoded
6282 into a coprocessor load/store instruction. If wb_ok is false,
6283 reject use of writeback; if unind_ok is false, reject use of
6284 unindexed addressing. If reloc_override is not 0, use it instead
6285 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6286 (in which case it is preserved). */
6289 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6291 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6293 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6295 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6297 assert (!inst
.operands
[i
].writeback
);
6300 inst
.error
= _("instruction does not support unindexed addressing");
6303 inst
.instruction
|= inst
.operands
[i
].imm
;
6304 inst
.instruction
|= INDEX_UP
;
6308 if (inst
.operands
[i
].preind
)
6309 inst
.instruction
|= PRE_INDEX
;
6311 if (inst
.operands
[i
].writeback
)
6313 if (inst
.operands
[i
].reg
== REG_PC
)
6315 inst
.error
= _("pc may not be used with write-back");
6320 inst
.error
= _("instruction does not support writeback");
6323 inst
.instruction
|= WRITE_BACK
;
6327 inst
.reloc
.type
= reloc_override
;
6328 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6329 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6330 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6333 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6335 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6341 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6342 Determine whether it can be performed with a move instruction; if
6343 it can, convert inst.instruction to that move instruction and
6344 return 1; if it can't, convert inst.instruction to a literal-pool
6345 load and return 0. If this is not a valid thing to do in the
6346 current context, set inst.error and return 1.
6348 inst.operands[i] describes the destination register. */
6351 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6356 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6360 if ((inst
.instruction
& tbit
) == 0)
6362 inst
.error
= _("invalid pseudo operation");
6365 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6367 inst
.error
= _("constant expression expected");
6370 if (inst
.reloc
.exp
.X_op
== O_constant
)
6374 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6376 /* This can be done with a mov(1) instruction. */
6377 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6378 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6384 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6387 /* This can be done with a mov instruction. */
6388 inst
.instruction
&= LITERAL_MASK
;
6389 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6390 inst
.instruction
|= value
& 0xfff;
6394 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6397 /* This can be done with a mvn instruction. */
6398 inst
.instruction
&= LITERAL_MASK
;
6399 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6400 inst
.instruction
|= value
& 0xfff;
6406 if (add_to_lit_pool () == FAIL
)
6408 inst
.error
= _("literal pool insertion failed");
6411 inst
.operands
[1].reg
= REG_PC
;
6412 inst
.operands
[1].isreg
= 1;
6413 inst
.operands
[1].preind
= 1;
6414 inst
.reloc
.pc_rel
= 1;
6415 inst
.reloc
.type
= (thumb_p
6416 ? BFD_RELOC_ARM_THUMB_OFFSET
6418 ? BFD_RELOC_ARM_HWLITERAL
6419 : BFD_RELOC_ARM_LITERAL
));
6423 /* Functions for instruction encoding, sorted by subarchitecture.
6424 First some generics; their names are taken from the conventional
6425 bit positions for register arguments in ARM format instructions. */
6435 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6441 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6442 inst
.instruction
|= inst
.operands
[1].reg
;
6448 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6449 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6455 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6456 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6462 unsigned Rn
= inst
.operands
[2].reg
;
6463 /* Enforce restrictions on SWP instruction. */
6464 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6465 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6466 _("Rn must not overlap other operands"));
6467 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6468 inst
.instruction
|= inst
.operands
[1].reg
;
6469 inst
.instruction
|= Rn
<< 16;
6475 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6476 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6477 inst
.instruction
|= inst
.operands
[2].reg
;
6483 inst
.instruction
|= inst
.operands
[0].reg
;
6484 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6485 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6491 inst
.instruction
|= inst
.operands
[0].imm
;
6497 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6498 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6501 /* ARM instructions, in alphabetical order by function name (except
6502 that wrapper functions appear immediately after the function they
6505 /* This is a pseudo-op of the form "adr rd, label" to be converted
6506 into a relative address of the form "add rd, pc, #label-.-8". */
6511 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6513 /* Frag hacking will turn this into a sub instruction if the offset turns
6514 out to be negative. */
6515 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6516 inst
.reloc
.pc_rel
= 1;
6517 inst
.reloc
.exp
.X_add_number
-= 8;
6520 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6521 into a relative address of the form:
6522 add rd, pc, #low(label-.-8)"
6523 add rd, rd, #high(label-.-8)" */
6528 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6530 /* Frag hacking will turn this into a sub instruction if the offset turns
6531 out to be negative. */
6532 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6533 inst
.reloc
.pc_rel
= 1;
6534 inst
.size
= INSN_SIZE
* 2;
6535 inst
.reloc
.exp
.X_add_number
-= 8;
6541 if (!inst
.operands
[1].present
)
6542 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6543 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6544 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6545 encode_arm_shifter_operand (2);
6551 if (inst
.operands
[0].present
)
6553 constraint ((inst
.instruction
& 0xf0) != 0x40
6554 && inst
.operands
[0].imm
!= 0xf,
6555 "bad barrier type");
6556 inst
.instruction
|= inst
.operands
[0].imm
;
6559 inst
.instruction
|= 0xf;
6565 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6566 constraint (msb
> 32, _("bit-field extends past end of register"));
6567 /* The instruction encoding stores the LSB and MSB,
6568 not the LSB and width. */
6569 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6570 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6571 inst
.instruction
|= (msb
- 1) << 16;
6579 /* #0 in second position is alternative syntax for bfc, which is
6580 the same instruction but with REG_PC in the Rm field. */
6581 if (!inst
.operands
[1].isreg
)
6582 inst
.operands
[1].reg
= REG_PC
;
6584 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6585 constraint (msb
> 32, _("bit-field extends past end of register"));
6586 /* The instruction encoding stores the LSB and MSB,
6587 not the LSB and width. */
6588 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6589 inst
.instruction
|= inst
.operands
[1].reg
;
6590 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6591 inst
.instruction
|= (msb
- 1) << 16;
6597 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6598 _("bit-field extends past end of register"));
6599 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6600 inst
.instruction
|= inst
.operands
[1].reg
;
6601 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6602 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6605 /* ARM V5 breakpoint instruction (argument parse)
6606 BKPT <16 bit unsigned immediate>
6607 Instruction is not conditional.
6608 The bit pattern given in insns[] has the COND_ALWAYS condition,
6609 and it is an error if the caller tried to override that. */
6614 /* Top 12 of 16 bits to bits 19:8. */
6615 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6617 /* Bottom 4 of 16 bits to bits 3:0. */
6618 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6622 encode_branch (int default_reloc
)
6624 if (inst
.operands
[0].hasreloc
)
6626 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6627 _("the only suffix valid here is '(plt)'"));
6628 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6632 inst
.reloc
.type
= default_reloc
;
6634 inst
.reloc
.pc_rel
= 1;
6641 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6642 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6645 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6652 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6654 if (inst
.cond
== COND_ALWAYS
)
6655 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6657 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6661 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6664 /* ARM V5 branch-link-exchange instruction (argument parse)
6665 BLX <target_addr> ie BLX(1)
6666 BLX{<condition>} <Rm> ie BLX(2)
6667 Unfortunately, there are two different opcodes for this mnemonic.
6668 So, the insns[].value is not used, and the code here zaps values
6669 into inst.instruction.
6670 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6675 if (inst
.operands
[0].isreg
)
6677 /* Arg is a register; the opcode provided by insns[] is correct.
6678 It is not illegal to do "blx pc", just useless. */
6679 if (inst
.operands
[0].reg
== REG_PC
)
6680 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6682 inst
.instruction
|= inst
.operands
[0].reg
;
6686 /* Arg is an address; this instruction cannot be executed
6687 conditionally, and the opcode must be adjusted. */
6688 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6689 inst
.instruction
= 0xfa000000;
6691 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6692 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6695 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6702 if (inst
.operands
[0].reg
== REG_PC
)
6703 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6705 inst
.instruction
|= inst
.operands
[0].reg
;
6709 /* ARM v5TEJ. Jump to Jazelle code. */
6714 if (inst
.operands
[0].reg
== REG_PC
)
6715 as_tsktsk (_("use of r15 in bxj is not really useful"));
6717 inst
.instruction
|= inst
.operands
[0].reg
;
6720 /* Co-processor data operation:
6721 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6722 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6726 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6727 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6728 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6729 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6730 inst
.instruction
|= inst
.operands
[4].reg
;
6731 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6737 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6738 encode_arm_shifter_operand (1);
6741 /* Transfer between coprocessor and ARM registers.
6742 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6747 No special properties. */
6752 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6753 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6754 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6755 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6756 inst
.instruction
|= inst
.operands
[4].reg
;
6757 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6760 /* Transfer between coprocessor register and pair of ARM registers.
6761 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6766 Two XScale instructions are special cases of these:
6768 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6769 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6771 Result unpredicatable if Rd or Rn is R15. */
6776 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6777 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6778 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6779 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6780 inst
.instruction
|= inst
.operands
[4].reg
;
6786 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6787 inst
.instruction
|= inst
.operands
[1].imm
;
6793 inst
.instruction
|= inst
.operands
[0].imm
;
6799 /* There is no IT instruction in ARM mode. We
6800 process it but do not generate code for it. */
6807 int base_reg
= inst
.operands
[0].reg
;
6808 int range
= inst
.operands
[1].imm
;
6810 inst
.instruction
|= base_reg
<< 16;
6811 inst
.instruction
|= range
;
6813 if (inst
.operands
[1].writeback
)
6814 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6816 if (inst
.operands
[0].writeback
)
6818 inst
.instruction
|= WRITE_BACK
;
6819 /* Check for unpredictable uses of writeback. */
6820 if (inst
.instruction
& LOAD_BIT
)
6822 /* Not allowed in LDM type 2. */
6823 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6824 && ((range
& (1 << REG_PC
)) == 0))
6825 as_warn (_("writeback of base register is UNPREDICTABLE"));
6826 /* Only allowed if base reg not in list for other types. */
6827 else if (range
& (1 << base_reg
))
6828 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6832 /* Not allowed for type 2. */
6833 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6834 as_warn (_("writeback of base register is UNPREDICTABLE"));
6835 /* Only allowed if base reg not in list, or first in list. */
6836 else if ((range
& (1 << base_reg
))
6837 && (range
& ((1 << base_reg
) - 1)))
6838 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6843 /* ARMv5TE load-consecutive (argument parse)
6852 constraint (inst
.operands
[0].reg
% 2 != 0,
6853 _("first destination register must be even"));
6854 constraint (inst
.operands
[1].present
6855 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6856 _("can only load two consecutive registers"));
6857 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6858 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6860 if (!inst
.operands
[1].present
)
6861 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6863 if (inst
.instruction
& LOAD_BIT
)
6865 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6866 register and the first register written; we have to diagnose
6867 overlap between the base and the second register written here. */
6869 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6870 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6871 as_warn (_("base register written back, and overlaps "
6872 "second destination register"));
6874 /* For an index-register load, the index register must not overlap the
6875 destination (even if not write-back). */
6876 else if (inst
.operands
[2].immisreg
6877 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6878 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6879 as_warn (_("index register overlaps destination register"));
6882 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6883 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6889 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6890 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6891 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6892 || inst
.operands
[1].negative
6893 /* This can arise if the programmer has written
6895 or if they have mistakenly used a register name as the last
6898 It is very difficult to distinguish between these two cases
6899 because "rX" might actually be a label. ie the register
6900 name has been occluded by a symbol of the same name. So we
6901 just generate a general 'bad addressing mode' type error
6902 message and leave it up to the programmer to discover the
6903 true cause and fix their mistake. */
6904 || (inst
.operands
[1].reg
== REG_PC
),
6907 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6908 || inst
.reloc
.exp
.X_add_number
!= 0,
6909 _("offset must be zero in ARM encoding"));
6911 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6912 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6913 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6919 constraint (inst
.operands
[0].reg
% 2 != 0,
6920 _("even register required"));
6921 constraint (inst
.operands
[1].present
6922 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6923 _("can only load two consecutive registers"));
6924 /* If op 1 were present and equal to PC, this function wouldn't
6925 have been called in the first place. */
6926 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6928 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6929 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6935 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6936 if (!inst
.operands
[1].isreg
)
6937 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
6939 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
6945 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6947 if (inst
.operands
[1].preind
)
6949 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
6950 inst
.reloc
.exp
.X_add_number
!= 0,
6951 _("this instruction requires a post-indexed address"));
6953 inst
.operands
[1].preind
= 0;
6954 inst
.operands
[1].postind
= 1;
6955 inst
.operands
[1].writeback
= 1;
6957 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6958 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
6961 /* Halfword and signed-byte load/store operations. */
6966 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6967 if (!inst
.operands
[1].isreg
)
6968 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
6970 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
6976 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6978 if (inst
.operands
[1].preind
)
6980 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
6981 inst
.reloc
.exp
.X_add_number
!= 0,
6982 _("this instruction requires a post-indexed address"));
6984 inst
.operands
[1].preind
= 0;
6985 inst
.operands
[1].postind
= 1;
6986 inst
.operands
[1].writeback
= 1;
6988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6989 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
6992 /* Co-processor register load/store.
6993 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
6997 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6998 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6999 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7005 /* This restriction does not apply to mls (nor to mla in v6, but
7006 that's hard to detect at present). */
7007 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7008 && !(inst
.instruction
& 0x00400000))
7009 as_tsktsk (_("rd and rm should be different in mla"));
7011 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7012 inst
.instruction
|= inst
.operands
[1].reg
;
7013 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7014 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7022 encode_arm_shifter_operand (1);
7025 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7032 top
= (inst
.instruction
& 0x00400000) != 0;
7033 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7034 _(":lower16: not allowed this instruction"));
7035 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7036 _(":upper16: not allowed instruction"));
7037 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7038 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7040 imm
= inst
.reloc
.exp
.X_add_number
;
7041 /* The value is in two pieces: 0:11, 16:19. */
7042 inst
.instruction
|= (imm
& 0x00000fff);
7043 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7047 static void do_vfp_nsyn_opcode (const char *);
7050 do_vfp_nsyn_mrs (void)
7052 if (inst
.operands
[0].isvec
)
7054 if (inst
.operands
[1].reg
!= 1)
7055 first_error (_("operand 1 must be FPSCR"));
7056 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7057 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7058 do_vfp_nsyn_opcode ("fmstat");
7060 else if (inst
.operands
[1].isvec
)
7061 do_vfp_nsyn_opcode ("fmrx");
7069 do_vfp_nsyn_msr (void)
7071 if (inst
.operands
[0].isvec
)
7072 do_vfp_nsyn_opcode ("fmxr");
7082 if (do_vfp_nsyn_mrs () == SUCCESS
)
7085 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7086 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7088 _("'CPSR' or 'SPSR' expected"));
7089 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7090 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7093 /* Two possible forms:
7094 "{C|S}PSR_<field>, Rm",
7095 "{C|S}PSR_f, #expression". */
7100 if (do_vfp_nsyn_msr () == SUCCESS
)
7103 inst
.instruction
|= inst
.operands
[0].imm
;
7104 if (inst
.operands
[1].isreg
)
7105 inst
.instruction
|= inst
.operands
[1].reg
;
7108 inst
.instruction
|= INST_IMMEDIATE
;
7109 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7110 inst
.reloc
.pc_rel
= 0;
7117 if (!inst
.operands
[2].present
)
7118 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7119 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7120 inst
.instruction
|= inst
.operands
[1].reg
;
7121 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7123 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7124 as_tsktsk (_("rd and rm should be different in mul"));
7127 /* Long Multiply Parser
7128 UMULL RdLo, RdHi, Rm, Rs
7129 SMULL RdLo, RdHi, Rm, Rs
7130 UMLAL RdLo, RdHi, Rm, Rs
7131 SMLAL RdLo, RdHi, Rm, Rs. */
7136 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7137 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7138 inst
.instruction
|= inst
.operands
[2].reg
;
7139 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7141 /* rdhi, rdlo and rm must all be different. */
7142 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7143 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7144 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7145 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7151 if (inst
.operands
[0].present
)
7153 /* Architectural NOP hints are CPSR sets with no bits selected. */
7154 inst
.instruction
&= 0xf0000000;
7155 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7159 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7160 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7161 Condition defaults to COND_ALWAYS.
7162 Error if Rd, Rn or Rm are R15. */
7167 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7168 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7169 inst
.instruction
|= inst
.operands
[2].reg
;
7170 if (inst
.operands
[3].present
)
7171 encode_arm_shift (3);
7174 /* ARM V6 PKHTB (Argument Parse). */
7179 if (!inst
.operands
[3].present
)
7181 /* If the shift specifier is omitted, turn the instruction
7182 into pkhbt rd, rm, rn. */
7183 inst
.instruction
&= 0xfff00010;
7184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7185 inst
.instruction
|= inst
.operands
[1].reg
;
7186 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7190 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7191 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7192 inst
.instruction
|= inst
.operands
[2].reg
;
7193 encode_arm_shift (3);
7197 /* ARMv5TE: Preload-Cache
7201 Syntactically, like LDR with B=1, W=0, L=1. */
7206 constraint (!inst
.operands
[0].isreg
,
7207 _("'[' expected after PLD mnemonic"));
7208 constraint (inst
.operands
[0].postind
,
7209 _("post-indexed expression used in preload instruction"));
7210 constraint (inst
.operands
[0].writeback
,
7211 _("writeback used in preload instruction"));
7212 constraint (!inst
.operands
[0].preind
,
7213 _("unindexed addressing used in preload instruction"));
7214 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7217 /* ARMv7: PLI <addr_mode> */
7221 constraint (!inst
.operands
[0].isreg
,
7222 _("'[' expected after PLI mnemonic"));
7223 constraint (inst
.operands
[0].postind
,
7224 _("post-indexed expression used in preload instruction"));
7225 constraint (inst
.operands
[0].writeback
,
7226 _("writeback used in preload instruction"));
7227 constraint (!inst
.operands
[0].preind
,
7228 _("unindexed addressing used in preload instruction"));
7229 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7230 inst
.instruction
&= ~PRE_INDEX
;
7236 inst
.operands
[1] = inst
.operands
[0];
7237 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7238 inst
.operands
[0].isreg
= 1;
7239 inst
.operands
[0].writeback
= 1;
7240 inst
.operands
[0].reg
= REG_SP
;
7244 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7245 word at the specified address and the following word
7247 Unconditionally executed.
7248 Error if Rn is R15. */
7253 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7254 if (inst
.operands
[0].writeback
)
7255 inst
.instruction
|= WRITE_BACK
;
7258 /* ARM V6 ssat (argument parse). */
7263 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7264 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7265 inst
.instruction
|= inst
.operands
[2].reg
;
7267 if (inst
.operands
[3].present
)
7268 encode_arm_shift (3);
7271 /* ARM V6 usat (argument parse). */
7276 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7277 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7278 inst
.instruction
|= inst
.operands
[2].reg
;
7280 if (inst
.operands
[3].present
)
7281 encode_arm_shift (3);
7284 /* ARM V6 ssat16 (argument parse). */
7289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7290 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7291 inst
.instruction
|= inst
.operands
[2].reg
;
7297 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7298 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7299 inst
.instruction
|= inst
.operands
[2].reg
;
7302 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7303 preserving the other bits.
7305 setend <endian_specifier>, where <endian_specifier> is either
7311 if (inst
.operands
[0].imm
)
7312 inst
.instruction
|= 0x200;
7318 unsigned int Rm
= (inst
.operands
[1].present
7319 ? inst
.operands
[1].reg
7320 : inst
.operands
[0].reg
);
7322 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7323 inst
.instruction
|= Rm
;
7324 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7326 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7327 inst
.instruction
|= SHIFT_BY_REG
;
7330 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7336 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7337 inst
.reloc
.pc_rel
= 0;
7343 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7344 inst
.reloc
.pc_rel
= 0;
7347 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7348 SMLAxy{cond} Rd,Rm,Rs,Rn
7349 SMLAWy{cond} Rd,Rm,Rs,Rn
7350 Error if any register is R15. */
7355 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7356 inst
.instruction
|= inst
.operands
[1].reg
;
7357 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7358 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7361 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7362 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7363 Error if any register is R15.
7364 Warning if Rdlo == Rdhi. */
7369 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7370 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7371 inst
.instruction
|= inst
.operands
[2].reg
;
7372 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7374 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7375 as_tsktsk (_("rdhi and rdlo must be different"));
7378 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7379 SMULxy{cond} Rd,Rm,Rs
7380 Error if any register is R15. */
7385 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7386 inst
.instruction
|= inst
.operands
[1].reg
;
7387 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7390 /* ARM V6 srs (argument parse). */
7395 inst
.instruction
|= inst
.operands
[0].imm
;
7396 if (inst
.operands
[0].writeback
)
7397 inst
.instruction
|= WRITE_BACK
;
7400 /* ARM V6 strex (argument parse). */
7405 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7406 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7407 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7408 || inst
.operands
[2].negative
7409 /* See comment in do_ldrex(). */
7410 || (inst
.operands
[2].reg
== REG_PC
),
7413 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7414 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7416 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7417 || inst
.reloc
.exp
.X_add_number
!= 0,
7418 _("offset must be zero in ARM encoding"));
7420 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7421 inst
.instruction
|= inst
.operands
[1].reg
;
7422 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7423 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7429 constraint (inst
.operands
[1].reg
% 2 != 0,
7430 _("even register required"));
7431 constraint (inst
.operands
[2].present
7432 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7433 _("can only store two consecutive registers"));
7434 /* If op 2 were present and equal to PC, this function wouldn't
7435 have been called in the first place. */
7436 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7438 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7439 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7440 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7443 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7444 inst
.instruction
|= inst
.operands
[1].reg
;
7445 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7448 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7449 extends it to 32-bits, and adds the result to a value in another
7450 register. You can specify a rotation by 0, 8, 16, or 24 bits
7451 before extracting the 16-bit value.
7452 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7453 Condition defaults to COND_ALWAYS.
7454 Error if any register uses R15. */
7459 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7460 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7461 inst
.instruction
|= inst
.operands
[2].reg
;
7462 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7467 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7468 Condition defaults to COND_ALWAYS.
7469 Error if any register uses R15. */
7474 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7475 inst
.instruction
|= inst
.operands
[1].reg
;
7476 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7479 /* VFP instructions. In a logical order: SP variant first, monad
7480 before dyad, arithmetic then move then load/store. */
7483 do_vfp_sp_monadic (void)
7485 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7486 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7490 do_vfp_sp_dyadic (void)
7492 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7493 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7494 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7498 do_vfp_sp_compare_z (void)
7500 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7504 do_vfp_dp_sp_cvt (void)
7506 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7507 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7511 do_vfp_sp_dp_cvt (void)
7513 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7514 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7518 do_vfp_reg_from_sp (void)
7520 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7521 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7525 do_vfp_reg2_from_sp2 (void)
7527 constraint (inst
.operands
[2].imm
!= 2,
7528 _("only two consecutive VFP SP registers allowed here"));
7529 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7530 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7531 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7535 do_vfp_sp_from_reg (void)
7537 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7538 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7542 do_vfp_sp2_from_reg2 (void)
7544 constraint (inst
.operands
[0].imm
!= 2,
7545 _("only two consecutive VFP SP registers allowed here"));
7546 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7547 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7548 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7552 do_vfp_sp_ldst (void)
7554 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7555 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7559 do_vfp_dp_ldst (void)
7561 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7562 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7567 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7569 if (inst
.operands
[0].writeback
)
7570 inst
.instruction
|= WRITE_BACK
;
7572 constraint (ldstm_type
!= VFP_LDSTMIA
,
7573 _("this addressing mode requires base-register writeback"));
7574 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7575 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7576 inst
.instruction
|= inst
.operands
[1].imm
;
7580 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7584 if (inst
.operands
[0].writeback
)
7585 inst
.instruction
|= WRITE_BACK
;
7587 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7588 _("this addressing mode requires base-register writeback"));
7590 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7591 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7593 count
= inst
.operands
[1].imm
<< 1;
7594 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7597 inst
.instruction
|= count
;
7601 do_vfp_sp_ldstmia (void)
7603 vfp_sp_ldstm (VFP_LDSTMIA
);
7607 do_vfp_sp_ldstmdb (void)
7609 vfp_sp_ldstm (VFP_LDSTMDB
);
7613 do_vfp_dp_ldstmia (void)
7615 vfp_dp_ldstm (VFP_LDSTMIA
);
7619 do_vfp_dp_ldstmdb (void)
7621 vfp_dp_ldstm (VFP_LDSTMDB
);
7625 do_vfp_xp_ldstmia (void)
7627 vfp_dp_ldstm (VFP_LDSTMIAX
);
7631 do_vfp_xp_ldstmdb (void)
7633 vfp_dp_ldstm (VFP_LDSTMDBX
);
7637 do_vfp_dp_rd_rm (void)
7639 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7640 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7644 do_vfp_dp_rn_rd (void)
7646 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7647 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7651 do_vfp_dp_rd_rn (void)
7653 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7654 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7658 do_vfp_dp_rd_rn_rm (void)
7660 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7661 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7662 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7668 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7672 do_vfp_dp_rm_rd_rn (void)
7674 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7675 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7676 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7679 /* VFPv3 instructions. */
7681 do_vfp_sp_const (void)
7683 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7684 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7685 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7689 do_vfp_dp_const (void)
7691 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7692 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7693 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7697 vfp_conv (int srcsize
)
7699 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7700 inst
.instruction
|= (immbits
& 1) << 5;
7701 inst
.instruction
|= (immbits
>> 1);
7705 do_vfp_sp_conv_16 (void)
7707 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7712 do_vfp_dp_conv_16 (void)
7714 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7719 do_vfp_sp_conv_32 (void)
7721 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7726 do_vfp_dp_conv_32 (void)
7728 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7733 /* FPA instructions. Also in a logical order. */
7738 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7739 inst
.instruction
|= inst
.operands
[1].reg
;
7743 do_fpa_ldmstm (void)
7745 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7746 switch (inst
.operands
[1].imm
)
7748 case 1: inst
.instruction
|= CP_T_X
; break;
7749 case 2: inst
.instruction
|= CP_T_Y
; break;
7750 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7755 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7757 /* The instruction specified "ea" or "fd", so we can only accept
7758 [Rn]{!}. The instruction does not really support stacking or
7759 unstacking, so we have to emulate these by setting appropriate
7760 bits and offsets. */
7761 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7762 || inst
.reloc
.exp
.X_add_number
!= 0,
7763 _("this instruction does not support indexing"));
7765 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7766 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7768 if (!(inst
.instruction
& INDEX_UP
))
7769 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7771 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7773 inst
.operands
[2].preind
= 0;
7774 inst
.operands
[2].postind
= 1;
7778 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7782 /* iWMMXt instructions: strictly in alphabetical order. */
7785 do_iwmmxt_tandorc (void)
7787 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7791 do_iwmmxt_textrc (void)
7793 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7794 inst
.instruction
|= inst
.operands
[1].imm
;
7798 do_iwmmxt_textrm (void)
7800 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7801 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7802 inst
.instruction
|= inst
.operands
[2].imm
;
7806 do_iwmmxt_tinsr (void)
7808 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7809 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7810 inst
.instruction
|= inst
.operands
[2].imm
;
7814 do_iwmmxt_tmia (void)
7816 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7817 inst
.instruction
|= inst
.operands
[1].reg
;
7818 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7822 do_iwmmxt_waligni (void)
7824 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7825 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7826 inst
.instruction
|= inst
.operands
[2].reg
;
7827 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7831 do_iwmmxt_wmov (void)
7833 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7834 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7835 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7836 inst
.instruction
|= inst
.operands
[1].reg
;
7840 do_iwmmxt_wldstbh (void)
7843 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7845 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7847 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7848 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7852 do_iwmmxt_wldstw (void)
7854 /* RIWR_RIWC clears .isreg for a control register. */
7855 if (!inst
.operands
[0].isreg
)
7857 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7858 inst
.instruction
|= 0xf0000000;
7861 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7862 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7866 do_iwmmxt_wldstd (void)
7868 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7869 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7873 do_iwmmxt_wshufh (void)
7875 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7876 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7877 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
7878 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
7882 do_iwmmxt_wzero (void)
7884 /* WZERO reg is an alias for WANDN reg, reg, reg. */
7885 inst
.instruction
|= inst
.operands
[0].reg
;
7886 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7887 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7890 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
7891 operations first, then control, shift, and load/store. */
7893 /* Insns like "foo X,Y,Z". */
7896 do_mav_triple (void)
7898 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7899 inst
.instruction
|= inst
.operands
[1].reg
;
7900 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7903 /* Insns like "foo W,X,Y,Z".
7904 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
7909 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7910 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7911 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7912 inst
.instruction
|= inst
.operands
[3].reg
;
7915 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
7919 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7922 /* Maverick shift immediate instructions.
7923 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
7924 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
7929 int imm
= inst
.operands
[2].imm
;
7931 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7932 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7934 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
7935 Bits 5-7 of the insn should have bits 4-6 of the immediate.
7936 Bit 4 should be 0. */
7937 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
7939 inst
.instruction
|= imm
;
7942 /* XScale instructions. Also sorted arithmetic before move. */
7944 /* Xscale multiply-accumulate (argument parse)
7947 MIAxycc acc0,Rm,Rs. */
7952 inst
.instruction
|= inst
.operands
[1].reg
;
7953 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7956 /* Xscale move-accumulator-register (argument parse)
7958 MARcc acc0,RdLo,RdHi. */
7963 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7964 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7967 /* Xscale move-register-accumulator (argument parse)
7969 MRAcc RdLo,RdHi,acc0. */
7974 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
7975 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7976 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7979 /* Encoding functions relevant only to Thumb. */
7981 /* inst.operands[i] is a shifted-register operand; encode
7982 it into inst.instruction in the format used by Thumb32. */
7985 encode_thumb32_shifted_operand (int i
)
7987 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
7988 unsigned int shift
= inst
.operands
[i
].shift_kind
;
7990 constraint (inst
.operands
[i
].immisreg
,
7991 _("shift by register not allowed in thumb mode"));
7992 inst
.instruction
|= inst
.operands
[i
].reg
;
7993 if (shift
== SHIFT_RRX
)
7994 inst
.instruction
|= SHIFT_ROR
<< 4;
7997 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7998 _("expression too complex"));
8000 constraint (value
> 32
8001 || (value
== 32 && (shift
== SHIFT_LSL
8002 || shift
== SHIFT_ROR
)),
8003 _("shift expression is too large"));
8007 else if (value
== 32)
8010 inst
.instruction
|= shift
<< 4;
8011 inst
.instruction
|= (value
& 0x1c) << 10;
8012 inst
.instruction
|= (value
& 0x03) << 6;
8017 /* inst.operands[i] was set up by parse_address. Encode it into a
8018 Thumb32 format load or store instruction. Reject forms that cannot
8019 be used with such instructions. If is_t is true, reject forms that
8020 cannot be used with a T instruction; if is_d is true, reject forms
8021 that cannot be used with a D instruction. */
8024 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8026 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8028 constraint (!inst
.operands
[i
].isreg
,
8029 _("Instruction does not support =N addresses"));
8031 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8032 if (inst
.operands
[i
].immisreg
)
8034 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8035 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8036 constraint (inst
.operands
[i
].negative
,
8037 _("Thumb does not support negative register indexing"));
8038 constraint (inst
.operands
[i
].postind
,
8039 _("Thumb does not support register post-indexing"));
8040 constraint (inst
.operands
[i
].writeback
,
8041 _("Thumb does not support register indexing with writeback"));
8042 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8043 _("Thumb supports only LSL in shifted register indexing"));
8045 inst
.instruction
|= inst
.operands
[i
].imm
;
8046 if (inst
.operands
[i
].shifted
)
8048 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8049 _("expression too complex"));
8050 constraint (inst
.reloc
.exp
.X_add_number
< 0
8051 || inst
.reloc
.exp
.X_add_number
> 3,
8052 _("shift out of range"));
8053 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8055 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8057 else if (inst
.operands
[i
].preind
)
8059 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8060 _("cannot use writeback with PC-relative addressing"));
8061 constraint (is_t
&& inst
.operands
[i
].writeback
,
8062 _("cannot use writeback with this instruction"));
8066 inst
.instruction
|= 0x01000000;
8067 if (inst
.operands
[i
].writeback
)
8068 inst
.instruction
|= 0x00200000;
8072 inst
.instruction
|= 0x00000c00;
8073 if (inst
.operands
[i
].writeback
)
8074 inst
.instruction
|= 0x00000100;
8076 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8078 else if (inst
.operands
[i
].postind
)
8080 assert (inst
.operands
[i
].writeback
);
8081 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8082 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8085 inst
.instruction
|= 0x00200000;
8087 inst
.instruction
|= 0x00000900;
8088 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8090 else /* unindexed - only for coprocessor */
8091 inst
.error
= _("instruction does not accept unindexed addressing");
8094 /* Table of Thumb instructions which exist in both 16- and 32-bit
8095 encodings (the latter only in post-V6T2 cores). The index is the
8096 value used in the insns table below. When there is more than one
8097 possible 16-bit encoding for the instruction, this table always
8099 Also contains several pseudo-instructions used during relaxation. */
8100 #define T16_32_TAB \
8101 X(adc, 4140, eb400000), \
8102 X(adcs, 4140, eb500000), \
8103 X(add, 1c00, eb000000), \
8104 X(adds, 1c00, eb100000), \
8105 X(addi, 0000, f1000000), \
8106 X(addis, 0000, f1100000), \
8107 X(add_pc,000f, f20f0000), \
8108 X(add_sp,000d, f10d0000), \
8109 X(adr, 000f, f20f0000), \
8110 X(and, 4000, ea000000), \
8111 X(ands, 4000, ea100000), \
8112 X(asr, 1000, fa40f000), \
8113 X(asrs, 1000, fa50f000), \
8114 X(b, e000, f000b000), \
8115 X(bcond, d000, f0008000), \
8116 X(bic, 4380, ea200000), \
8117 X(bics, 4380, ea300000), \
8118 X(cmn, 42c0, eb100f00), \
8119 X(cmp, 2800, ebb00f00), \
8120 X(cpsie, b660, f3af8400), \
8121 X(cpsid, b670, f3af8600), \
8122 X(cpy, 4600, ea4f0000), \
8123 X(dec_sp,80dd, f1bd0d00), \
8124 X(eor, 4040, ea800000), \
8125 X(eors, 4040, ea900000), \
8126 X(inc_sp,00dd, f10d0d00), \
8127 X(ldmia, c800, e8900000), \
8128 X(ldr, 6800, f8500000), \
8129 X(ldrb, 7800, f8100000), \
8130 X(ldrh, 8800, f8300000), \
8131 X(ldrsb, 5600, f9100000), \
8132 X(ldrsh, 5e00, f9300000), \
8133 X(ldr_pc,4800, f85f0000), \
8134 X(ldr_pc2,4800, f85f0000), \
8135 X(ldr_sp,9800, f85d0000), \
8136 X(lsl, 0000, fa00f000), \
8137 X(lsls, 0000, fa10f000), \
8138 X(lsr, 0800, fa20f000), \
8139 X(lsrs, 0800, fa30f000), \
8140 X(mov, 2000, ea4f0000), \
8141 X(movs, 2000, ea5f0000), \
8142 X(mul, 4340, fb00f000), \
8143 X(muls, 4340, ffffffff), /* no 32b muls */ \
8144 X(mvn, 43c0, ea6f0000), \
8145 X(mvns, 43c0, ea7f0000), \
8146 X(neg, 4240, f1c00000), /* rsb #0 */ \
8147 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8148 X(orr, 4300, ea400000), \
8149 X(orrs, 4300, ea500000), \
8150 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8151 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8152 X(rev, ba00, fa90f080), \
8153 X(rev16, ba40, fa90f090), \
8154 X(revsh, bac0, fa90f0b0), \
8155 X(ror, 41c0, fa60f000), \
8156 X(rors, 41c0, fa70f000), \
8157 X(sbc, 4180, eb600000), \
8158 X(sbcs, 4180, eb700000), \
8159 X(stmia, c000, e8800000), \
8160 X(str, 6000, f8400000), \
8161 X(strb, 7000, f8000000), \
8162 X(strh, 8000, f8200000), \
8163 X(str_sp,9000, f84d0000), \
8164 X(sub, 1e00, eba00000), \
8165 X(subs, 1e00, ebb00000), \
8166 X(subi, 8000, f1a00000), \
8167 X(subis, 8000, f1b00000), \
8168 X(sxtb, b240, fa4ff080), \
8169 X(sxth, b200, fa0ff080), \
8170 X(tst, 4200, ea100f00), \
8171 X(uxtb, b2c0, fa5ff080), \
8172 X(uxth, b280, fa1ff080), \
8173 X(nop, bf00, f3af8000), \
8174 X(yield, bf10, f3af8001), \
8175 X(wfe, bf20, f3af8002), \
8176 X(wfi, bf30, f3af8003), \
8177 X(sev, bf40, f3af9004), /* typo, 8004? */
8179 /* To catch errors in encoding functions, the codes are all offset by
8180 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8181 as 16-bit instructions. */
8182 #define X(a,b,c) T_MNEM_##a
8183 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8186 #define X(a,b,c) 0x##b
8187 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8188 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8191 #define X(a,b,c) 0x##c
8192 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8193 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8194 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8198 /* Thumb instruction encoders, in alphabetical order. */
8202 do_t_add_sub_w (void)
8206 Rd
= inst
.operands
[0].reg
;
8207 Rn
= inst
.operands
[1].reg
;
8209 constraint (Rd
== 15, _("PC not allowed as destination"));
8210 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8211 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8214 /* Parse an add or subtract instruction. We get here with inst.instruction
8215 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8222 Rd
= inst
.operands
[0].reg
;
8223 Rs
= (inst
.operands
[1].present
8224 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8225 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8233 flags
= (inst
.instruction
== T_MNEM_adds
8234 || inst
.instruction
== T_MNEM_subs
);
8236 narrow
= (current_it_mask
== 0);
8238 narrow
= (current_it_mask
!= 0);
8239 if (!inst
.operands
[2].isreg
)
8243 add
= (inst
.instruction
== T_MNEM_add
8244 || inst
.instruction
== T_MNEM_adds
);
8246 if (inst
.size_req
!= 4)
8248 /* Attempt to use a narrow opcode, with relaxation if
8250 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8251 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8252 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8253 opcode
= T_MNEM_add_sp
;
8254 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8255 opcode
= T_MNEM_add_pc
;
8256 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8259 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8261 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8265 inst
.instruction
= THUMB_OP16(opcode
);
8266 inst
.instruction
|= (Rd
<< 4) | Rs
;
8267 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8268 if (inst
.size_req
!= 2)
8269 inst
.relax
= opcode
;
8272 constraint (inst
.size_req
== 2, BAD_HIREG
);
8274 if (inst
.size_req
== 4
8275 || (inst
.size_req
!= 2 && !opcode
))
8279 /* Always use addw/subw. */
8280 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8281 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8285 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8286 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8289 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8291 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8293 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8294 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8299 Rn
= inst
.operands
[2].reg
;
8300 /* See if we can do this with a 16-bit instruction. */
8301 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8303 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8308 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8309 || inst
.instruction
== T_MNEM_add
)
8312 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8316 if (inst
.instruction
== T_MNEM_add
)
8320 inst
.instruction
= T_OPCODE_ADD_HI
;
8321 inst
.instruction
|= (Rd
& 8) << 4;
8322 inst
.instruction
|= (Rd
& 7);
8323 inst
.instruction
|= Rn
<< 3;
8326 /* ... because addition is commutative! */
8329 inst
.instruction
= T_OPCODE_ADD_HI
;
8330 inst
.instruction
|= (Rd
& 8) << 4;
8331 inst
.instruction
|= (Rd
& 7);
8332 inst
.instruction
|= Rs
<< 3;
8337 /* If we get here, it can't be done in 16 bits. */
8338 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8339 _("shift must be constant"));
8340 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8341 inst
.instruction
|= Rd
<< 8;
8342 inst
.instruction
|= Rs
<< 16;
8343 encode_thumb32_shifted_operand (2);
8348 constraint (inst
.instruction
== T_MNEM_adds
8349 || inst
.instruction
== T_MNEM_subs
,
8352 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8354 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8355 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8358 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8360 inst
.instruction
|= (Rd
<< 4) | Rs
;
8361 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8365 Rn
= inst
.operands
[2].reg
;
8366 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8368 /* We now have Rd, Rs, and Rn set to registers. */
8369 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8371 /* Can't do this for SUB. */
8372 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8373 inst
.instruction
= T_OPCODE_ADD_HI
;
8374 inst
.instruction
|= (Rd
& 8) << 4;
8375 inst
.instruction
|= (Rd
& 7);
8377 inst
.instruction
|= Rn
<< 3;
8379 inst
.instruction
|= Rs
<< 3;
8381 constraint (1, _("dest must overlap one source register"));
8385 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8386 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8387 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8395 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8397 /* Defer to section relaxation. */
8398 inst
.relax
= inst
.instruction
;
8399 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8400 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8402 else if (unified_syntax
&& inst
.size_req
!= 2)
8404 /* Generate a 32-bit opcode. */
8405 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8406 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8407 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8408 inst
.reloc
.pc_rel
= 1;
8412 /* Generate a 16-bit opcode. */
8413 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8414 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8415 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8416 inst
.reloc
.pc_rel
= 1;
8418 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8422 /* Arithmetic instructions for which there is just one 16-bit
8423 instruction encoding, and it allows only two low registers.
8424 For maximal compatibility with ARM syntax, we allow three register
8425 operands even when Thumb-32 instructions are not available, as long
8426 as the first two are identical. For instance, both "sbc r0,r1" and
8427 "sbc r0,r0,r1" are allowed. */
8433 Rd
= inst
.operands
[0].reg
;
8434 Rs
= (inst
.operands
[1].present
8435 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8436 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8437 Rn
= inst
.operands
[2].reg
;
8441 if (!inst
.operands
[2].isreg
)
8443 /* For an immediate, we always generate a 32-bit opcode;
8444 section relaxation will shrink it later if possible. */
8445 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8446 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8447 inst
.instruction
|= Rd
<< 8;
8448 inst
.instruction
|= Rs
<< 16;
8449 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8455 /* See if we can do this with a 16-bit instruction. */
8456 if (THUMB_SETS_FLAGS (inst
.instruction
))
8457 narrow
= current_it_mask
== 0;
8459 narrow
= current_it_mask
!= 0;
8461 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8463 if (inst
.operands
[2].shifted
)
8465 if (inst
.size_req
== 4)
8471 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8472 inst
.instruction
|= Rd
;
8473 inst
.instruction
|= Rn
<< 3;
8477 /* If we get here, it can't be done in 16 bits. */
8478 constraint (inst
.operands
[2].shifted
8479 && inst
.operands
[2].immisreg
,
8480 _("shift must be constant"));
8481 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8482 inst
.instruction
|= Rd
<< 8;
8483 inst
.instruction
|= Rs
<< 16;
8484 encode_thumb32_shifted_operand (2);
8489 /* On its face this is a lie - the instruction does set the
8490 flags. However, the only supported mnemonic in this mode
8492 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8494 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8495 _("unshifted register required"));
8496 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8497 constraint (Rd
!= Rs
,
8498 _("dest and source1 must be the same register"));
8500 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8501 inst
.instruction
|= Rd
;
8502 inst
.instruction
|= Rn
<< 3;
8506 /* Similarly, but for instructions where the arithmetic operation is
8507 commutative, so we can allow either of them to be different from
8508 the destination operand in a 16-bit instruction. For instance, all
8509 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8516 Rd
= inst
.operands
[0].reg
;
8517 Rs
= (inst
.operands
[1].present
8518 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8519 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8520 Rn
= inst
.operands
[2].reg
;
8524 if (!inst
.operands
[2].isreg
)
8526 /* For an immediate, we always generate a 32-bit opcode;
8527 section relaxation will shrink it later if possible. */
8528 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8529 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8530 inst
.instruction
|= Rd
<< 8;
8531 inst
.instruction
|= Rs
<< 16;
8532 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8538 /* See if we can do this with a 16-bit instruction. */
8539 if (THUMB_SETS_FLAGS (inst
.instruction
))
8540 narrow
= current_it_mask
== 0;
8542 narrow
= current_it_mask
!= 0;
8544 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8546 if (inst
.operands
[2].shifted
)
8548 if (inst
.size_req
== 4)
8555 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8556 inst
.instruction
|= Rd
;
8557 inst
.instruction
|= Rn
<< 3;
8562 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8563 inst
.instruction
|= Rd
;
8564 inst
.instruction
|= Rs
<< 3;
8569 /* If we get here, it can't be done in 16 bits. */
8570 constraint (inst
.operands
[2].shifted
8571 && inst
.operands
[2].immisreg
,
8572 _("shift must be constant"));
8573 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8574 inst
.instruction
|= Rd
<< 8;
8575 inst
.instruction
|= Rs
<< 16;
8576 encode_thumb32_shifted_operand (2);
8581 /* On its face this is a lie - the instruction does set the
8582 flags. However, the only supported mnemonic in this mode
8584 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8586 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8587 _("unshifted register required"));
8588 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8590 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8591 inst
.instruction
|= Rd
;
8594 inst
.instruction
|= Rn
<< 3;
8596 inst
.instruction
|= Rs
<< 3;
8598 constraint (1, _("dest must overlap one source register"));
8605 if (inst
.operands
[0].present
)
8607 constraint ((inst
.instruction
& 0xf0) != 0x40
8608 && inst
.operands
[0].imm
!= 0xf,
8609 "bad barrier type");
8610 inst
.instruction
|= inst
.operands
[0].imm
;
8613 inst
.instruction
|= 0xf;
8619 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8620 constraint (msb
> 32, _("bit-field extends past end of register"));
8621 /* The instruction encoding stores the LSB and MSB,
8622 not the LSB and width. */
8623 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8624 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8625 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8626 inst
.instruction
|= msb
- 1;
8634 /* #0 in second position is alternative syntax for bfc, which is
8635 the same instruction but with REG_PC in the Rm field. */
8636 if (!inst
.operands
[1].isreg
)
8637 inst
.operands
[1].reg
= REG_PC
;
8639 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8640 constraint (msb
> 32, _("bit-field extends past end of register"));
8641 /* The instruction encoding stores the LSB and MSB,
8642 not the LSB and width. */
8643 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8644 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8645 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8646 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8647 inst
.instruction
|= msb
- 1;
8653 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8654 _("bit-field extends past end of register"));
8655 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8656 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8657 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8658 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8659 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8662 /* ARM V5 Thumb BLX (argument parse)
8663 BLX <target_addr> which is BLX(1)
8664 BLX <Rm> which is BLX(2)
8665 Unfortunately, there are two different opcodes for this mnemonic.
8666 So, the insns[].value is not used, and the code here zaps values
8667 into inst.instruction.
8669 ??? How to take advantage of the additional two bits of displacement
8670 available in Thumb32 mode? Need new relocation? */
8675 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8676 if (inst
.operands
[0].isreg
)
8677 /* We have a register, so this is BLX(2). */
8678 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8681 /* No register. This must be BLX(1). */
8682 inst
.instruction
= 0xf000e800;
8684 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8685 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8688 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8689 inst
.reloc
.pc_rel
= 1;
8699 if (current_it_mask
)
8701 /* Conditional branches inside IT blocks are encoded as unconditional
8704 /* A branch must be the last instruction in an IT block. */
8705 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8710 if (cond
!= COND_ALWAYS
)
8711 opcode
= T_MNEM_bcond
;
8713 opcode
= inst
.instruction
;
8715 if (unified_syntax
&& inst
.size_req
== 4)
8717 inst
.instruction
= THUMB_OP32(opcode
);
8718 if (cond
== COND_ALWAYS
)
8719 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8722 assert (cond
!= 0xF);
8723 inst
.instruction
|= cond
<< 22;
8724 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8729 inst
.instruction
= THUMB_OP16(opcode
);
8730 if (cond
== COND_ALWAYS
)
8731 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8734 inst
.instruction
|= cond
<< 8;
8735 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8737 /* Allow section relaxation. */
8738 if (unified_syntax
&& inst
.size_req
!= 2)
8739 inst
.relax
= opcode
;
8742 inst
.reloc
.pc_rel
= 1;
8748 constraint (inst
.cond
!= COND_ALWAYS
,
8749 _("instruction is always unconditional"));
8750 if (inst
.operands
[0].present
)
8752 constraint (inst
.operands
[0].imm
> 255,
8753 _("immediate value out of range"));
8754 inst
.instruction
|= inst
.operands
[0].imm
;
8759 do_t_branch23 (void)
8761 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8762 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8763 inst
.reloc
.pc_rel
= 1;
8765 /* If the destination of the branch is a defined symbol which does not have
8766 the THUMB_FUNC attribute, then we must be calling a function which has
8767 the (interfacearm) attribute. We look for the Thumb entry point to that
8768 function and change the branch to refer to that function instead. */
8769 if ( inst
.reloc
.exp
.X_op
== O_symbol
8770 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8771 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8772 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8773 inst
.reloc
.exp
.X_add_symbol
=
8774 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8780 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8781 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8782 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8783 should cause the alignment to be checked once it is known. This is
8784 because BX PC only works if the instruction is word aligned. */
8790 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8791 if (inst
.operands
[0].reg
== REG_PC
)
8792 as_tsktsk (_("use of r15 in bxj is not really useful"));
8794 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8800 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8801 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8802 inst
.instruction
|= inst
.operands
[1].reg
;
8808 constraint (current_it_mask
, BAD_NOT_IT
);
8809 inst
.instruction
|= inst
.operands
[0].imm
;
8815 constraint (current_it_mask
, BAD_NOT_IT
);
8817 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
8818 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
8820 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
8821 inst
.instruction
= 0xf3af8000;
8822 inst
.instruction
|= imod
<< 9;
8823 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
8824 if (inst
.operands
[1].present
)
8825 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
8829 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
8830 && (inst
.operands
[0].imm
& 4),
8831 _("selected processor does not support 'A' form "
8832 "of this instruction"));
8833 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
8834 _("Thumb does not support the 2-argument "
8835 "form of this instruction"));
8836 inst
.instruction
|= inst
.operands
[0].imm
;
8840 /* THUMB CPY instruction (argument parse). */
8845 if (inst
.size_req
== 4)
8847 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
8848 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8849 inst
.instruction
|= inst
.operands
[1].reg
;
8853 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
8854 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
8855 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
8862 constraint (current_it_mask
, BAD_NOT_IT
);
8863 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
8864 inst
.instruction
|= inst
.operands
[0].reg
;
8865 inst
.reloc
.pc_rel
= 1;
8866 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
8872 inst
.instruction
|= inst
.operands
[0].imm
;
8878 if (!inst
.operands
[1].present
)
8879 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8880 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8881 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8882 inst
.instruction
|= inst
.operands
[2].reg
;
8888 if (unified_syntax
&& inst
.size_req
== 4)
8889 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8891 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8897 unsigned int cond
= inst
.operands
[0].imm
;
8899 constraint (current_it_mask
, BAD_NOT_IT
);
8900 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
8903 /* If the condition is a negative condition, invert the mask. */
8904 if ((cond
& 0x1) == 0x0)
8906 unsigned int mask
= inst
.instruction
& 0x000f;
8908 if ((mask
& 0x7) == 0)
8909 /* no conversion needed */;
8910 else if ((mask
& 0x3) == 0)
8912 else if ((mask
& 0x1) == 0)
8917 inst
.instruction
&= 0xfff0;
8918 inst
.instruction
|= mask
;
8921 inst
.instruction
|= cond
<< 4;
8927 /* This really doesn't seem worth it. */
8928 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
8929 _("expression too complex"));
8930 constraint (inst
.operands
[1].writeback
,
8931 _("Thumb load/store multiple does not support {reglist}^"));
8935 /* See if we can use a 16-bit instruction. */
8936 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
8937 && inst
.size_req
!= 4
8938 && inst
.operands
[0].reg
<= 7
8939 && !(inst
.operands
[1].imm
& ~0xff)
8940 && (inst
.instruction
== T_MNEM_stmia
8941 ? inst
.operands
[0].writeback
8942 : (inst
.operands
[0].writeback
8943 == !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))))
8945 if (inst
.instruction
== T_MNEM_stmia
8946 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8947 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
8948 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8949 inst
.operands
[0].reg
);
8951 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8952 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8953 inst
.instruction
|= inst
.operands
[1].imm
;
8957 if (inst
.operands
[1].imm
& (1 << 13))
8958 as_warn (_("SP should not be in register list"));
8959 if (inst
.instruction
== T_MNEM_stmia
)
8961 if (inst
.operands
[1].imm
& (1 << 15))
8962 as_warn (_("PC should not be in register list"));
8963 if (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8964 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8965 inst
.operands
[0].reg
);
8969 if (inst
.operands
[1].imm
& (1 << 14)
8970 && inst
.operands
[1].imm
& (1 << 15))
8971 as_warn (_("LR and PC should not both be in register list"));
8972 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8973 && inst
.operands
[0].writeback
)
8974 as_warn (_("base register should not be in register list "
8975 "when written back"));
8977 if (inst
.instruction
< 0xffff)
8978 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8979 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8980 inst
.instruction
|= inst
.operands
[1].imm
;
8981 if (inst
.operands
[0].writeback
)
8982 inst
.instruction
|= WRITE_BACK
;
8987 constraint (inst
.operands
[0].reg
> 7
8988 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
8989 if (inst
.instruction
== T_MNEM_stmia
)
8991 if (!inst
.operands
[0].writeback
)
8992 as_warn (_("this instruction will write back the base register"));
8993 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8994 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
8995 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8996 inst
.operands
[0].reg
);
9000 if (!inst
.operands
[0].writeback
9001 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9002 as_warn (_("this instruction will write back the base register"));
9003 else if (inst
.operands
[0].writeback
9004 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9005 as_warn (_("this instruction will not write back the base register"));
9008 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9009 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9010 inst
.instruction
|= inst
.operands
[1].imm
;
9017 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9018 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9019 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9020 || inst
.operands
[1].negative
,
9023 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9024 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9025 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9031 if (!inst
.operands
[1].present
)
9033 constraint (inst
.operands
[0].reg
== REG_LR
,
9034 _("r14 not allowed as first register "
9035 "when second register is omitted"));
9036 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9038 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9041 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9042 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9043 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9049 unsigned long opcode
;
9052 opcode
= inst
.instruction
;
9055 if (!inst
.operands
[1].isreg
)
9057 if (opcode
<= 0xffff)
9058 inst
.instruction
= THUMB_OP32 (opcode
);
9059 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9062 if (inst
.operands
[1].isreg
9063 && !inst
.operands
[1].writeback
9064 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9065 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9067 && inst
.size_req
!= 4)
9069 /* Insn may have a 16-bit form. */
9070 Rn
= inst
.operands
[1].reg
;
9071 if (inst
.operands
[1].immisreg
)
9073 inst
.instruction
= THUMB_OP16 (opcode
);
9075 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9078 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9079 && opcode
!= T_MNEM_ldrsb
)
9080 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9081 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9088 if (inst
.reloc
.pc_rel
)
9089 opcode
= T_MNEM_ldr_pc2
;
9091 opcode
= T_MNEM_ldr_pc
;
9095 if (opcode
== T_MNEM_ldr
)
9096 opcode
= T_MNEM_ldr_sp
;
9098 opcode
= T_MNEM_str_sp
;
9100 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9104 inst
.instruction
= inst
.operands
[0].reg
;
9105 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9107 inst
.instruction
|= THUMB_OP16 (opcode
);
9108 if (inst
.size_req
== 2)
9109 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9111 inst
.relax
= opcode
;
9115 /* Definitely a 32-bit variant. */
9116 inst
.instruction
= THUMB_OP32 (opcode
);
9117 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9118 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9122 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9124 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9126 /* Only [Rn,Rm] is acceptable. */
9127 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9128 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9129 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9130 || inst
.operands
[1].negative
,
9131 _("Thumb does not support this addressing mode"));
9132 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9136 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9137 if (!inst
.operands
[1].isreg
)
9138 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9141 constraint (!inst
.operands
[1].preind
9142 || inst
.operands
[1].shifted
9143 || inst
.operands
[1].writeback
,
9144 _("Thumb does not support this addressing mode"));
9145 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9147 constraint (inst
.instruction
& 0x0600,
9148 _("byte or halfword not valid for base register"));
9149 constraint (inst
.operands
[1].reg
== REG_PC
9150 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9151 _("r15 based store not allowed"));
9152 constraint (inst
.operands
[1].immisreg
,
9153 _("invalid base register for register offset"));
9155 if (inst
.operands
[1].reg
== REG_PC
)
9156 inst
.instruction
= T_OPCODE_LDR_PC
;
9157 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9158 inst
.instruction
= T_OPCODE_LDR_SP
;
9160 inst
.instruction
= T_OPCODE_STR_SP
;
9162 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9163 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9167 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9168 if (!inst
.operands
[1].immisreg
)
9170 /* Immediate offset. */
9171 inst
.instruction
|= inst
.operands
[0].reg
;
9172 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9173 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9177 /* Register offset. */
9178 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9179 constraint (inst
.operands
[1].negative
,
9180 _("Thumb does not support this addressing mode"));
9183 switch (inst
.instruction
)
9185 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9186 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9187 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9188 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9189 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9190 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9191 case 0x5600 /* ldrsb */:
9192 case 0x5e00 /* ldrsh */: break;
9196 inst
.instruction
|= inst
.operands
[0].reg
;
9197 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9198 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9204 if (!inst
.operands
[1].present
)
9206 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9207 constraint (inst
.operands
[0].reg
== REG_LR
,
9208 _("r14 not allowed here"));
9210 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9211 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9212 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9220 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9226 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9227 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9228 inst
.instruction
|= inst
.operands
[2].reg
;
9229 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9235 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9236 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9237 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9238 inst
.instruction
|= inst
.operands
[3].reg
;
9246 int r0off
= (inst
.instruction
== T_MNEM_mov
9247 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9248 unsigned long opcode
;
9250 bfd_boolean low_regs
;
9252 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9253 opcode
= inst
.instruction
;
9254 if (current_it_mask
)
9255 narrow
= opcode
!= T_MNEM_movs
;
9257 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9258 if (inst
.size_req
== 4
9259 || inst
.operands
[1].shifted
)
9262 if (!inst
.operands
[1].isreg
)
9264 /* Immediate operand. */
9265 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9267 if (low_regs
&& narrow
)
9269 inst
.instruction
= THUMB_OP16 (opcode
);
9270 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9271 if (inst
.size_req
== 2)
9272 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9274 inst
.relax
= opcode
;
9278 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9279 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9280 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9281 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9286 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9287 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9288 encode_thumb32_shifted_operand (1);
9291 switch (inst
.instruction
)
9294 inst
.instruction
= T_OPCODE_MOV_HR
;
9295 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9296 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9297 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9301 /* We know we have low registers at this point.
9302 Generate ADD Rd, Rs, #0. */
9303 inst
.instruction
= T_OPCODE_ADD_I3
;
9304 inst
.instruction
|= inst
.operands
[0].reg
;
9305 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9311 inst
.instruction
= T_OPCODE_CMP_LR
;
9312 inst
.instruction
|= inst
.operands
[0].reg
;
9313 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9317 inst
.instruction
= T_OPCODE_CMP_HR
;
9318 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9319 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9320 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9327 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9328 if (inst
.operands
[1].isreg
)
9330 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9332 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9333 since a MOV instruction produces unpredictable results. */
9334 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9335 inst
.instruction
= T_OPCODE_ADD_I3
;
9337 inst
.instruction
= T_OPCODE_CMP_LR
;
9339 inst
.instruction
|= inst
.operands
[0].reg
;
9340 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9344 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9345 inst
.instruction
= T_OPCODE_MOV_HR
;
9347 inst
.instruction
= T_OPCODE_CMP_HR
;
9353 constraint (inst
.operands
[0].reg
> 7,
9354 _("only lo regs allowed with immediate"));
9355 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9356 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9366 top
= (inst
.instruction
& 0x00800000) != 0;
9367 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9369 constraint (top
, _(":lower16: not allowed this instruction"));
9370 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9372 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9374 constraint (!top
, _(":upper16: not allowed this instruction"));
9375 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9378 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9379 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9381 imm
= inst
.reloc
.exp
.X_add_number
;
9382 inst
.instruction
|= (imm
& 0xf000) << 4;
9383 inst
.instruction
|= (imm
& 0x0800) << 15;
9384 inst
.instruction
|= (imm
& 0x0700) << 4;
9385 inst
.instruction
|= (imm
& 0x00ff);
9394 int r0off
= (inst
.instruction
== T_MNEM_mvn
9395 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9398 if (inst
.size_req
== 4
9399 || inst
.instruction
> 0xffff
9400 || inst
.operands
[1].shifted
9401 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9403 else if (inst
.instruction
== T_MNEM_cmn
)
9405 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9406 narrow
= (current_it_mask
== 0);
9408 narrow
= (current_it_mask
!= 0);
9410 if (!inst
.operands
[1].isreg
)
9412 /* For an immediate, we always generate a 32-bit opcode;
9413 section relaxation will shrink it later if possible. */
9414 if (inst
.instruction
< 0xffff)
9415 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9416 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9417 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9418 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9422 /* See if we can do this with a 16-bit instruction. */
9425 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9426 inst
.instruction
|= inst
.operands
[0].reg
;
9427 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9431 constraint (inst
.operands
[1].shifted
9432 && inst
.operands
[1].immisreg
,
9433 _("shift must be constant"));
9434 if (inst
.instruction
< 0xffff)
9435 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9436 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9437 encode_thumb32_shifted_operand (1);
9443 constraint (inst
.instruction
> 0xffff
9444 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9445 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9446 _("unshifted register required"));
9447 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9450 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9451 inst
.instruction
|= inst
.operands
[0].reg
;
9452 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9461 if (do_vfp_nsyn_mrs () == SUCCESS
)
9464 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9467 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9468 _("selected processor does not support "
9469 "requested special purpose register"));
9473 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9474 _("selected processor does not support "
9475 "requested special purpose register %x"));
9476 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9477 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9478 _("'CPSR' or 'SPSR' expected"));
9481 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9482 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9483 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9491 if (do_vfp_nsyn_msr () == SUCCESS
)
9494 constraint (!inst
.operands
[1].isreg
,
9495 _("Thumb encoding does not support an immediate here"));
9496 flags
= inst
.operands
[0].imm
;
9499 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9500 _("selected processor does not support "
9501 "requested special purpose register"));
9505 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9506 _("selected processor does not support "
9507 "requested special purpose register"));
9510 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9511 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9512 inst
.instruction
|= (flags
& 0xff);
9513 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9519 if (!inst
.operands
[2].present
)
9520 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9522 /* There is no 32-bit MULS and no 16-bit MUL. */
9523 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9525 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9526 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9527 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9528 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9532 constraint (!unified_syntax
9533 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9534 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9537 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9538 inst
.instruction
|= inst
.operands
[0].reg
;
9540 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9541 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9542 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9543 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9545 constraint (1, _("dest must overlap one source register"));
9552 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9553 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9554 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9555 inst
.instruction
|= inst
.operands
[3].reg
;
9557 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9558 as_tsktsk (_("rdhi and rdlo must be different"));
9566 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9568 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9569 inst
.instruction
|= inst
.operands
[0].imm
;
9573 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9574 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9579 constraint (inst
.operands
[0].present
,
9580 _("Thumb does not support NOP with hints"));
9581 inst
.instruction
= 0x46c0;
9592 if (THUMB_SETS_FLAGS (inst
.instruction
))
9593 narrow
= (current_it_mask
== 0);
9595 narrow
= (current_it_mask
!= 0);
9596 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9598 if (inst
.size_req
== 4)
9603 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9604 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9605 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9609 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9610 inst
.instruction
|= inst
.operands
[0].reg
;
9611 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9616 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9618 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9620 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9621 inst
.instruction
|= inst
.operands
[0].reg
;
9622 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9629 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9630 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9631 inst
.instruction
|= inst
.operands
[2].reg
;
9632 if (inst
.operands
[3].present
)
9634 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9635 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9636 _("expression too complex"));
9637 inst
.instruction
|= (val
& 0x1c) << 10;
9638 inst
.instruction
|= (val
& 0x03) << 6;
9645 if (!inst
.operands
[3].present
)
9646 inst
.instruction
&= ~0x00000020;
9653 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9657 do_t_push_pop (void)
9661 constraint (inst
.operands
[0].writeback
,
9662 _("push/pop do not support {reglist}^"));
9663 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9664 _("expression too complex"));
9666 mask
= inst
.operands
[0].imm
;
9667 if ((mask
& ~0xff) == 0)
9668 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9669 else if ((inst
.instruction
== T_MNEM_push
9670 && (mask
& ~0xff) == 1 << REG_LR
)
9671 || (inst
.instruction
== T_MNEM_pop
9672 && (mask
& ~0xff) == 1 << REG_PC
))
9674 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9675 inst
.instruction
|= THUMB_PP_PC_LR
;
9678 else if (unified_syntax
)
9680 if (mask
& (1 << 13))
9681 inst
.error
= _("SP not allowed in register list");
9682 if (inst
.instruction
== T_MNEM_push
)
9684 if (mask
& (1 << 15))
9685 inst
.error
= _("PC not allowed in register list");
9689 if (mask
& (1 << 14)
9690 && mask
& (1 << 15))
9691 inst
.error
= _("LR and PC should not both be in register list");
9693 if ((mask
& (mask
- 1)) == 0)
9695 /* Single register push/pop implemented as str/ldr. */
9696 if (inst
.instruction
== T_MNEM_push
)
9697 inst
.instruction
= 0xf84d0d04; /* str reg, [sp, #-4]! */
9699 inst
.instruction
= 0xf85d0b04; /* ldr reg, [sp], #4 */
9700 mask
= ffs(mask
) - 1;
9704 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9708 inst
.error
= _("invalid register list to push/pop instruction");
9712 inst
.instruction
|= mask
;
9718 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9719 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9725 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
9726 && inst
.size_req
!= 4)
9728 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9729 inst
.instruction
|= inst
.operands
[0].reg
;
9730 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9732 else if (unified_syntax
)
9734 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9735 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9736 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9737 inst
.instruction
|= inst
.operands
[1].reg
;
9740 inst
.error
= BAD_HIREG
;
9748 Rd
= inst
.operands
[0].reg
;
9749 Rs
= (inst
.operands
[1].present
9750 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9751 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9753 inst
.instruction
|= Rd
<< 8;
9754 inst
.instruction
|= Rs
<< 16;
9755 if (!inst
.operands
[2].isreg
)
9757 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9758 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9761 encode_thumb32_shifted_operand (2);
9767 constraint (current_it_mask
, BAD_NOT_IT
);
9768 if (inst
.operands
[0].imm
)
9769 inst
.instruction
|= 0x8;
9775 if (!inst
.operands
[1].present
)
9776 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9783 switch (inst
.instruction
)
9786 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
9788 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
9790 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
9792 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
9796 if (THUMB_SETS_FLAGS (inst
.instruction
))
9797 narrow
= (current_it_mask
== 0);
9799 narrow
= (current_it_mask
!= 0);
9800 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9802 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
9804 if (inst
.operands
[2].isreg
9805 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
9806 || inst
.operands
[2].reg
> 7))
9808 if (inst
.size_req
== 4)
9813 if (inst
.operands
[2].isreg
)
9815 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9816 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9817 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9818 inst
.instruction
|= inst
.operands
[2].reg
;
9822 inst
.operands
[1].shifted
= 1;
9823 inst
.operands
[1].shift_kind
= shift_kind
;
9824 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
9825 ? T_MNEM_movs
: T_MNEM_mov
);
9826 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9827 encode_thumb32_shifted_operand (1);
9828 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
9829 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9834 if (inst
.operands
[2].isreg
)
9838 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9839 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9840 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9841 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9845 inst
.instruction
|= inst
.operands
[0].reg
;
9846 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9852 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9853 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9854 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9857 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9858 inst
.instruction
|= inst
.operands
[0].reg
;
9859 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9865 constraint (inst
.operands
[0].reg
> 7
9866 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
9867 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9869 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
9871 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
9872 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
9873 _("source1 and dest must be same register"));
9875 switch (inst
.instruction
)
9877 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9878 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9879 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9880 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9884 inst
.instruction
|= inst
.operands
[0].reg
;
9885 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9889 switch (inst
.instruction
)
9891 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9892 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9893 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9894 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
9897 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9898 inst
.instruction
|= inst
.operands
[0].reg
;
9899 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9907 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9908 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9909 inst
.instruction
|= inst
.operands
[2].reg
;
9915 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9916 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9917 _("expression too complex"));
9918 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9919 inst
.instruction
|= (value
& 0xf000) >> 12;
9920 inst
.instruction
|= (value
& 0x0ff0);
9921 inst
.instruction
|= (value
& 0x000f) << 16;
9927 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9928 inst
.instruction
|= inst
.operands
[1].imm
- 1;
9929 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9931 if (inst
.operands
[3].present
)
9933 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9934 _("expression too complex"));
9936 if (inst
.reloc
.exp
.X_add_number
!= 0)
9938 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
9939 inst
.instruction
|= 0x00200000; /* sh bit */
9940 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
9941 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
9943 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9950 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9951 inst
.instruction
|= inst
.operands
[1].imm
- 1;
9952 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9958 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9959 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9960 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9961 || inst
.operands
[2].negative
,
9964 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9965 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9966 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9967 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9973 if (!inst
.operands
[2].present
)
9974 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
9976 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9977 || inst
.operands
[0].reg
== inst
.operands
[2].reg
9978 || inst
.operands
[0].reg
== inst
.operands
[3].reg
9979 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
9982 inst
.instruction
|= inst
.operands
[0].reg
;
9983 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9984 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9985 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9991 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9992 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9993 inst
.instruction
|= inst
.operands
[2].reg
;
9994 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10000 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10001 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10002 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10004 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10005 inst
.instruction
|= inst
.operands
[0].reg
;
10006 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10008 else if (unified_syntax
)
10010 if (inst
.instruction
<= 0xffff)
10011 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10012 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10013 inst
.instruction
|= inst
.operands
[1].reg
;
10014 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10018 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10019 _("Thumb encoding does not support rotation"));
10020 constraint (1, BAD_HIREG
);
10027 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10035 half
= (inst
.instruction
& 0x10) != 0;
10036 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10037 constraint (inst
.operands
[0].immisreg
,
10038 _("instruction requires register index"));
10039 constraint (inst
.operands
[0].imm
== 15,
10040 _("PC is not a valid index register"));
10041 constraint (!half
&& inst
.operands
[0].shifted
,
10042 _("instruction does not allow shifted index"));
10043 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10049 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10050 inst
.instruction
|= inst
.operands
[1].imm
;
10051 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10053 if (inst
.operands
[3].present
)
10055 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10056 _("expression too complex"));
10057 if (inst
.reloc
.exp
.X_add_number
!= 0)
10059 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10060 inst
.instruction
|= 0x00200000; /* sh bit */
10062 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10063 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10065 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10072 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10073 inst
.instruction
|= inst
.operands
[1].imm
;
10074 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10077 /* Neon instruction encoder helpers. */
10079 /* Encodings for the different types for various Neon opcodes. */
10081 /* An "invalid" code for the following tables. */
10084 struct neon_tab_entry
10087 unsigned float_or_poly
;
10088 unsigned scalar_or_imm
;
10091 /* Map overloaded Neon opcodes to their respective encodings. */
10092 #define NEON_ENC_TAB \
10093 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10094 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10095 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10096 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10097 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10098 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10099 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10100 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10101 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10102 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10103 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10104 /* Register variants of the following two instructions are encoded as
10105 vcge / vcgt with the operands reversed. */ \
10106 X(vclt, 0x0000310, 0x1000e00, 0x1b10200), \
10107 X(vcle, 0x0000300, 0x1200e00, 0x1b10180), \
10108 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10109 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10110 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10111 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10112 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10113 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10114 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10115 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10116 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10117 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10118 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10119 X(vshl, 0x0000400, N_INV, 0x0800510), \
10120 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10121 X(vand, 0x0000110, N_INV, 0x0800030), \
10122 X(vbic, 0x0100110, N_INV, 0x0800030), \
10123 X(veor, 0x1000110, N_INV, N_INV), \
10124 X(vorn, 0x0300110, N_INV, 0x0800010), \
10125 X(vorr, 0x0200110, N_INV, 0x0800010), \
10126 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10127 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10128 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10129 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10130 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10131 X(vst1, 0x0000000, 0x0800000, N_INV), \
10132 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10133 X(vst2, 0x0000100, 0x0800100, N_INV), \
10134 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10135 X(vst3, 0x0000200, 0x0800200, N_INV), \
10136 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10137 X(vst4, 0x0000300, 0x0800300, N_INV), \
10138 X(vmovn, 0x1b20200, N_INV, N_INV), \
10139 X(vtrn, 0x1b20080, N_INV, N_INV), \
10140 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10141 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10142 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10143 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10144 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10145 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10146 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10147 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10148 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10152 #define X(OPC,I,F,S) N_MNEM_##OPC
10157 static const struct neon_tab_entry neon_enc_tab
[] =
10159 #define X(OPC,I,F,S) { (I), (F), (S) }
10164 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10165 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10166 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10167 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10168 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10169 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10170 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10171 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10172 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10173 #define NEON_ENC_SINGLE(X) \
10174 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10175 #define NEON_ENC_DOUBLE(X) \
10176 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10178 /* Define shapes for instruction operands. The following mnemonic characters
10179 are used in this table:
10181 F - VFP S<n> register
10182 D - Neon D<n> register
10183 Q - Neon Q<n> register
10187 L - D<n> register list
10189 This table is used to generate various data:
10190 - enumerations of the form NS_DDR to be used as arguments to
10192 - a table classifying shapes into single, double, quad, mixed.
10193 - a table used to drive neon_select_shape.
10196 #define NEON_SHAPE_DEF \
10197 X(3, (D, D, D), DOUBLE), \
10198 X(3, (Q, Q, Q), QUAD), \
10199 X(3, (D, D, I), DOUBLE), \
10200 X(3, (Q, Q, I), QUAD), \
10201 X(3, (D, D, S), DOUBLE), \
10202 X(3, (Q, Q, S), QUAD), \
10203 X(2, (D, D), DOUBLE), \
10204 X(2, (Q, Q), QUAD), \
10205 X(2, (D, S), DOUBLE), \
10206 X(2, (Q, S), QUAD), \
10207 X(2, (D, R), DOUBLE), \
10208 X(2, (Q, R), QUAD), \
10209 X(2, (D, I), DOUBLE), \
10210 X(2, (Q, I), QUAD), \
10211 X(3, (D, L, D), DOUBLE), \
10212 X(2, (D, Q), MIXED), \
10213 X(2, (Q, D), MIXED), \
10214 X(3, (D, Q, I), MIXED), \
10215 X(3, (Q, D, I), MIXED), \
10216 X(3, (Q, D, D), MIXED), \
10217 X(3, (D, Q, Q), MIXED), \
10218 X(3, (Q, Q, D), MIXED), \
10219 X(3, (Q, D, S), MIXED), \
10220 X(3, (D, Q, S), MIXED), \
10221 X(4, (D, D, D, I), DOUBLE), \
10222 X(4, (Q, Q, Q, I), QUAD), \
10223 X(2, (F, F), SINGLE), \
10224 X(3, (F, F, F), SINGLE), \
10225 X(2, (F, I), SINGLE), \
10226 X(2, (F, D), MIXED), \
10227 X(2, (D, F), MIXED), \
10228 X(3, (F, F, I), MIXED), \
10229 X(4, (R, R, F, F), SINGLE), \
10230 X(4, (F, F, R, R), SINGLE), \
10231 X(3, (D, R, R), DOUBLE), \
10232 X(3, (R, R, D), DOUBLE), \
10233 X(2, (S, R), SINGLE), \
10234 X(2, (R, S), SINGLE), \
10235 X(2, (F, R), SINGLE), \
10236 X(2, (R, F), SINGLE)
10238 #define S2(A,B) NS_##A##B
10239 #define S3(A,B,C) NS_##A##B##C
10240 #define S4(A,B,C,D) NS_##A##B##C##D
10242 #define X(N, L, C) S##N L
10255 enum neon_shape_class
10263 #define X(N, L, C) SC_##C
10265 static enum neon_shape_class neon_shape_class
[] =
10283 /* Register widths of above. */
10284 static unsigned neon_shape_el_size
[] =
10295 struct neon_shape_info
10298 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10301 #define S2(A,B) { SE_##A, SE_##B }
10302 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10303 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10305 #define X(N, L, C) { N, S##N L }
10307 static struct neon_shape_info neon_shape_tab
[] =
10317 /* Bit masks used in type checking given instructions.
10318 'N_EQK' means the type must be the same as (or based on in some way) the key
10319 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10320 set, various other bits can be set as well in order to modify the meaning of
10321 the type constraint. */
10323 enum neon_type_mask
10345 N_KEY
= 0x100000, /* key element (main type specifier). */
10346 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10347 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10348 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10349 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10350 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10351 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10352 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10353 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10354 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10356 N_MAX_NONSPECIAL
= N_F64
10359 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10361 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10362 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10363 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10364 #define N_SUF_32 (N_SU_32 | N_F32)
10365 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10366 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10368 /* Pass this as the first type argument to neon_check_type to ignore types
10370 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10372 /* Select a "shape" for the current instruction (describing register types or
10373 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10374 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10375 function of operand parsing, so this function doesn't need to be called.
10376 Shapes should be listed in order of decreasing length. */
10378 static enum neon_shape
10379 neon_select_shape (enum neon_shape shape
, ...)
10382 enum neon_shape first_shape
= shape
;
10384 /* Fix missing optional operands. FIXME: we don't know at this point how
10385 many arguments we should have, so this makes the assumption that we have
10386 > 1. This is true of all current Neon opcodes, I think, but may not be
10387 true in the future. */
10388 if (!inst
.operands
[1].present
)
10389 inst
.operands
[1] = inst
.operands
[0];
10391 va_start (ap
, shape
);
10393 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10398 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10400 if (!inst
.operands
[j
].present
)
10406 switch (neon_shape_tab
[shape
].el
[j
])
10409 if (!(inst
.operands
[j
].isreg
10410 && inst
.operands
[j
].isvec
10411 && inst
.operands
[j
].issingle
10412 && !inst
.operands
[j
].isquad
))
10417 if (!(inst
.operands
[j
].isreg
10418 && inst
.operands
[j
].isvec
10419 && !inst
.operands
[j
].isquad
10420 && !inst
.operands
[j
].issingle
))
10425 if (!(inst
.operands
[j
].isreg
10426 && !inst
.operands
[j
].isvec
))
10431 if (!(inst
.operands
[j
].isreg
10432 && inst
.operands
[j
].isvec
10433 && inst
.operands
[j
].isquad
10434 && !inst
.operands
[j
].issingle
))
10439 if (!(!inst
.operands
[j
].isreg
10440 && !inst
.operands
[j
].isscalar
))
10445 if (!(!inst
.operands
[j
].isreg
10446 && inst
.operands
[j
].isscalar
))
10460 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10461 first_error (_("invalid instruction shape"));
10466 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10467 means the Q bit should be set). */
10470 neon_quad (enum neon_shape shape
)
10472 return neon_shape_class
[shape
] == SC_QUAD
;
10476 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10479 /* Allow modification to be made to types which are constrained to be
10480 based on the key element, based on bits set alongside N_EQK. */
10481 if ((typebits
& N_EQK
) != 0)
10483 if ((typebits
& N_HLF
) != 0)
10485 else if ((typebits
& N_DBL
) != 0)
10487 if ((typebits
& N_SGN
) != 0)
10488 *g_type
= NT_signed
;
10489 else if ((typebits
& N_UNS
) != 0)
10490 *g_type
= NT_unsigned
;
10491 else if ((typebits
& N_INT
) != 0)
10492 *g_type
= NT_integer
;
10493 else if ((typebits
& N_FLT
) != 0)
10494 *g_type
= NT_float
;
10495 else if ((typebits
& N_SIZ
) != 0)
10496 *g_type
= NT_untyped
;
10500 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10501 operand type, i.e. the single type specified in a Neon instruction when it
10502 is the only one given. */
10504 static struct neon_type_el
10505 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10507 struct neon_type_el dest
= *key
;
10509 assert ((thisarg
& N_EQK
) != 0);
10511 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10516 /* Convert Neon type and size into compact bitmask representation. */
10518 static enum neon_type_mask
10519 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10526 case 8: return N_8
;
10527 case 16: return N_16
;
10528 case 32: return N_32
;
10529 case 64: return N_64
;
10537 case 8: return N_I8
;
10538 case 16: return N_I16
;
10539 case 32: return N_I32
;
10540 case 64: return N_I64
;
10548 case 32: return N_F32
;
10549 case 64: return N_F64
;
10557 case 8: return N_P8
;
10558 case 16: return N_P16
;
10566 case 8: return N_S8
;
10567 case 16: return N_S16
;
10568 case 32: return N_S32
;
10569 case 64: return N_S64
;
10577 case 8: return N_U8
;
10578 case 16: return N_U16
;
10579 case 32: return N_U32
;
10580 case 64: return N_U64
;
10591 /* Convert compact Neon bitmask type representation to a type and size. Only
10592 handles the case where a single bit is set in the mask. */
10595 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10596 enum neon_type_mask mask
)
10598 if ((mask
& N_EQK
) != 0)
10601 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10603 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10605 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10607 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10612 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10614 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10615 *type
= NT_unsigned
;
10616 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10617 *type
= NT_integer
;
10618 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10619 *type
= NT_untyped
;
10620 else if ((mask
& (N_P8
| N_P16
)) != 0)
10622 else if ((mask
& (N_F32
| N_F64
)) != 0)
10630 /* Modify a bitmask of allowed types. This is only needed for type
10634 modify_types_allowed (unsigned allowed
, unsigned mods
)
10637 enum neon_el_type type
;
10643 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10645 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10647 neon_modify_type_size (mods
, &type
, &size
);
10648 destmask
|= type_chk_of_el_type (type
, size
);
10655 /* Check type and return type classification.
10656 The manual states (paraphrase): If one datatype is given, it indicates the
10658 - the second operand, if there is one
10659 - the operand, if there is no second operand
10660 - the result, if there are no operands.
10661 This isn't quite good enough though, so we use a concept of a "key" datatype
10662 which is set on a per-instruction basis, which is the one which matters when
10663 only one data type is written.
10664 Note: this function has side-effects (e.g. filling in missing operands). All
10665 Neon instructions should call it before performing bit encoding. */
10667 static struct neon_type_el
10668 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
10671 unsigned i
, pass
, key_el
= 0;
10672 unsigned types
[NEON_MAX_TYPE_ELS
];
10673 enum neon_el_type k_type
= NT_invtype
;
10674 unsigned k_size
= -1u;
10675 struct neon_type_el badtype
= {NT_invtype
, -1};
10676 unsigned key_allowed
= 0;
10678 /* Optional registers in Neon instructions are always (not) in operand 1.
10679 Fill in the missing operand here, if it was omitted. */
10680 if (els
> 1 && !inst
.operands
[1].present
)
10681 inst
.operands
[1] = inst
.operands
[0];
10683 /* Suck up all the varargs. */
10685 for (i
= 0; i
< els
; i
++)
10687 unsigned thisarg
= va_arg (ap
, unsigned);
10688 if (thisarg
== N_IGNORE_TYPE
)
10693 types
[i
] = thisarg
;
10694 if ((thisarg
& N_KEY
) != 0)
10699 if (inst
.vectype
.elems
> 0)
10700 for (i
= 0; i
< els
; i
++)
10701 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
10703 first_error (_("types specified in both the mnemonic and operands"));
10707 /* Duplicate inst.vectype elements here as necessary.
10708 FIXME: No idea if this is exactly the same as the ARM assembler,
10709 particularly when an insn takes one register and one non-register
10711 if (inst
.vectype
.elems
== 1 && els
> 1)
10714 inst
.vectype
.elems
= els
;
10715 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
10716 for (j
= 0; j
< els
; j
++)
10718 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10721 else if (inst
.vectype
.elems
== 0 && els
> 0)
10724 /* No types were given after the mnemonic, so look for types specified
10725 after each operand. We allow some flexibility here; as long as the
10726 "key" operand has a type, we can infer the others. */
10727 for (j
= 0; j
< els
; j
++)
10728 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
10729 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
10731 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
10733 for (j
= 0; j
< els
; j
++)
10734 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
10735 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10740 first_error (_("operand types can't be inferred"));
10744 else if (inst
.vectype
.elems
!= els
)
10746 first_error (_("type specifier has the wrong number of parts"));
10750 for (pass
= 0; pass
< 2; pass
++)
10752 for (i
= 0; i
< els
; i
++)
10754 unsigned thisarg
= types
[i
];
10755 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
10756 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
10757 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
10758 unsigned g_size
= inst
.vectype
.el
[i
].size
;
10760 /* Decay more-specific signed & unsigned types to sign-insensitive
10761 integer types if sign-specific variants are unavailable. */
10762 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
10763 && (types_allowed
& N_SU_ALL
) == 0)
10764 g_type
= NT_integer
;
10766 /* If only untyped args are allowed, decay any more specific types to
10767 them. Some instructions only care about signs for some element
10768 sizes, so handle that properly. */
10769 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
10770 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
10771 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
10772 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
10773 g_type
= NT_untyped
;
10777 if ((thisarg
& N_KEY
) != 0)
10781 key_allowed
= thisarg
& ~N_KEY
;
10786 if ((thisarg
& N_VFP
) != 0)
10788 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
10789 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
10791 /* In VFP mode, operands must match register widths. If we
10792 have a key operand, use its width, else use the width of
10793 the current operand. */
10799 if (regwidth
!= match
)
10801 first_error (_("operand size must match register width"));
10806 if ((thisarg
& N_EQK
) == 0)
10808 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
10810 if ((given_type
& types_allowed
) == 0)
10812 first_error (_("bad type in Neon instruction"));
10818 enum neon_el_type mod_k_type
= k_type
;
10819 unsigned mod_k_size
= k_size
;
10820 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
10821 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
10823 first_error (_("inconsistent types in Neon instruction"));
10831 return inst
.vectype
.el
[key_el
];
10834 /* Neon-style VFP instruction forwarding. */
10836 /* Thumb VFP instructions have 0xE in the condition field. */
10839 do_vfp_cond_or_thumb (void)
10842 inst
.instruction
|= 0xe0000000;
10844 inst
.instruction
|= inst
.cond
<< 28;
10847 /* Look up and encode a simple mnemonic, for use as a helper function for the
10848 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
10849 etc. It is assumed that operand parsing has already been done, and that the
10850 operands are in the form expected by the given opcode (this isn't necessarily
10851 the same as the form in which they were parsed, hence some massaging must
10852 take place before this function is called).
10853 Checks current arch version against that in the looked-up opcode. */
10856 do_vfp_nsyn_opcode (const char *opname
)
10858 const struct asm_opcode
*opcode
;
10860 opcode
= hash_find (arm_ops_hsh
, opname
);
10865 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
10866 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
10871 inst
.instruction
= opcode
->tvalue
;
10872 opcode
->tencode ();
10876 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
10877 opcode
->aencode ();
10882 do_vfp_nsyn_add_sub (enum neon_shape rs
)
10884 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
10889 do_vfp_nsyn_opcode ("fadds");
10891 do_vfp_nsyn_opcode ("fsubs");
10896 do_vfp_nsyn_opcode ("faddd");
10898 do_vfp_nsyn_opcode ("fsubd");
10902 /* Check operand types to see if this is a VFP instruction, and if so call
10906 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
10908 enum neon_shape rs
;
10909 struct neon_type_el et
;
10914 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
10915 et
= neon_check_type (2, rs
,
10916 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10920 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
10921 et
= neon_check_type (3, rs
,
10922 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10929 if (et
.type
!= NT_invtype
)
10941 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
10943 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
10948 do_vfp_nsyn_opcode ("fmacs");
10950 do_vfp_nsyn_opcode ("fmscs");
10955 do_vfp_nsyn_opcode ("fmacd");
10957 do_vfp_nsyn_opcode ("fmscd");
10962 do_vfp_nsyn_mul (enum neon_shape rs
)
10965 do_vfp_nsyn_opcode ("fmuls");
10967 do_vfp_nsyn_opcode ("fmuld");
10971 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
10973 int is_neg
= (inst
.instruction
& 0x80) != 0;
10974 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
10979 do_vfp_nsyn_opcode ("fnegs");
10981 do_vfp_nsyn_opcode ("fabss");
10986 do_vfp_nsyn_opcode ("fnegd");
10988 do_vfp_nsyn_opcode ("fabsd");
10992 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
10993 insns belong to Neon, and are handled elsewhere. */
10996 do_vfp_nsyn_ldm_stm (int is_dbmode
)
10998 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11002 do_vfp_nsyn_opcode ("fldmdbs");
11004 do_vfp_nsyn_opcode ("fldmias");
11009 do_vfp_nsyn_opcode ("fstmdbs");
11011 do_vfp_nsyn_opcode ("fstmias");
11016 do_vfp_nsyn_sqrt (void)
11018 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11019 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11022 do_vfp_nsyn_opcode ("fsqrts");
11024 do_vfp_nsyn_opcode ("fsqrtd");
11028 do_vfp_nsyn_div (void)
11030 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11031 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11032 N_F32
| N_F64
| N_KEY
| N_VFP
);
11035 do_vfp_nsyn_opcode ("fdivs");
11037 do_vfp_nsyn_opcode ("fdivd");
11041 do_vfp_nsyn_nmul (void)
11043 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11044 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11045 N_F32
| N_F64
| N_KEY
| N_VFP
);
11049 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11050 do_vfp_sp_dyadic ();
11054 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11055 do_vfp_dp_rd_rn_rm ();
11057 do_vfp_cond_or_thumb ();
11061 do_vfp_nsyn_cmp (void)
11063 if (inst
.operands
[1].isreg
)
11065 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11066 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11070 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11071 do_vfp_sp_monadic ();
11075 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11076 do_vfp_dp_rd_rm ();
11081 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11082 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11084 switch (inst
.instruction
& 0x0fffffff)
11087 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11090 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11098 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11099 do_vfp_sp_compare_z ();
11103 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11107 do_vfp_cond_or_thumb ();
11111 nsyn_insert_sp (void)
11113 inst
.operands
[1] = inst
.operands
[0];
11114 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11115 inst
.operands
[0].reg
= 13;
11116 inst
.operands
[0].isreg
= 1;
11117 inst
.operands
[0].writeback
= 1;
11118 inst
.operands
[0].present
= 1;
11122 do_vfp_nsyn_push (void)
11125 if (inst
.operands
[1].issingle
)
11126 do_vfp_nsyn_opcode ("fstmdbs");
11128 do_vfp_nsyn_opcode ("fstmdbd");
11132 do_vfp_nsyn_pop (void)
11135 if (inst
.operands
[1].issingle
)
11136 do_vfp_nsyn_opcode ("fldmdbs");
11138 do_vfp_nsyn_opcode ("fldmdbd");
11141 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11142 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11145 neon_dp_fixup (unsigned i
)
11149 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11163 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11167 neon_logbits (unsigned x
)
11169 return ffs (x
) - 4;
11172 #define LOW4(R) ((R) & 0xf)
11173 #define HI1(R) (((R) >> 4) & 1)
11175 /* Encode insns with bit pattern:
11177 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11178 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11180 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11181 different meaning for some instruction. */
11184 neon_three_same (int isquad
, int ubit
, int size
)
11186 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11187 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11188 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11189 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11190 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11191 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11192 inst
.instruction
|= (isquad
!= 0) << 6;
11193 inst
.instruction
|= (ubit
!= 0) << 24;
11195 inst
.instruction
|= neon_logbits (size
) << 20;
11197 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11200 /* Encode instructions of the form:
11202 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11203 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11205 Don't write size if SIZE == -1. */
11208 neon_two_same (int qbit
, int ubit
, int size
)
11210 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11211 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11212 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11213 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11214 inst
.instruction
|= (qbit
!= 0) << 6;
11215 inst
.instruction
|= (ubit
!= 0) << 24;
11218 inst
.instruction
|= neon_logbits (size
) << 18;
11220 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11223 /* Neon instruction encoders, in approximate order of appearance. */
11226 do_neon_dyadic_i_su (void)
11228 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11229 struct neon_type_el et
= neon_check_type (3, rs
,
11230 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11231 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11235 do_neon_dyadic_i64_su (void)
11237 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11238 struct neon_type_el et
= neon_check_type (3, rs
,
11239 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11240 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11244 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11247 unsigned size
= et
.size
>> 3;
11248 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11249 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11250 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11251 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11252 inst
.instruction
|= (isquad
!= 0) << 6;
11253 inst
.instruction
|= immbits
<< 16;
11254 inst
.instruction
|= (size
>> 3) << 7;
11255 inst
.instruction
|= (size
& 0x7) << 19;
11257 inst
.instruction
|= (uval
!= 0) << 24;
11259 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11263 do_neon_shl_imm (void)
11265 if (!inst
.operands
[2].isreg
)
11267 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11268 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11269 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11270 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11274 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11275 struct neon_type_el et
= neon_check_type (3, rs
,
11276 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11277 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11278 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11283 do_neon_qshl_imm (void)
11285 if (!inst
.operands
[2].isreg
)
11287 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11288 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11289 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11290 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11291 inst
.operands
[2].imm
);
11295 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11296 struct neon_type_el et
= neon_check_type (3, rs
,
11297 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11298 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11299 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11304 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11306 /* Handle .I8 and .I64 as pseudo-instructions. */
11310 /* Unfortunately, this will make everything apart from zero out-of-range.
11311 FIXME is this the intended semantics? There doesn't seem much point in
11312 accepting .I8 if so. */
11313 immediate
|= immediate
<< 8;
11317 /* Similarly, anything other than zero will be replicated in bits [63:32],
11318 which probably isn't want we want if we specified .I64. */
11319 if (immediate
!= 0)
11320 goto bad_immediate
;
11326 if (immediate
== (immediate
& 0x000000ff))
11328 *immbits
= immediate
;
11329 return (size
== 16) ? 0x9 : 0x1;
11331 else if (immediate
== (immediate
& 0x0000ff00))
11333 *immbits
= immediate
>> 8;
11334 return (size
== 16) ? 0xb : 0x3;
11336 else if (immediate
== (immediate
& 0x00ff0000))
11338 *immbits
= immediate
>> 16;
11341 else if (immediate
== (immediate
& 0xff000000))
11343 *immbits
= immediate
>> 24;
11348 first_error (_("immediate value out of range"));
11352 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11356 neon_bits_same_in_bytes (unsigned imm
)
11358 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11359 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11360 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11361 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11364 /* For immediate of above form, return 0bABCD. */
11367 neon_squash_bits (unsigned imm
)
11369 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11370 | ((imm
& 0x01000000) >> 21);
11373 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11376 neon_qfloat_bits (unsigned imm
)
11378 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11381 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11382 the instruction. *OP is passed as the initial value of the op field, and
11383 may be set to a different value depending on the constant (i.e.
11384 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11388 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, unsigned *immbits
,
11389 int *op
, int size
, enum neon_el_type type
)
11391 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11393 if (size
!= 32 || *op
== 1)
11395 *immbits
= neon_qfloat_bits (immlo
);
11398 else if (size
== 64 && neon_bits_same_in_bytes (immhi
)
11399 && neon_bits_same_in_bytes (immlo
))
11401 /* Check this one first so we don't have to bother with immhi in later
11405 *immbits
= (neon_squash_bits (immhi
) << 4) | neon_squash_bits (immlo
);
11409 else if (immhi
!= 0)
11411 else if (immlo
== (immlo
& 0x000000ff))
11413 /* 64-bit case was already handled. Don't allow MVN with 8-bit
11415 if ((size
!= 8 && size
!= 16 && size
!= 32)
11416 || (size
== 8 && *op
== 1))
11419 return (size
== 8) ? 0xe : (size
== 16) ? 0x8 : 0x0;
11421 else if (immlo
== (immlo
& 0x0000ff00))
11423 if (size
!= 16 && size
!= 32)
11425 *immbits
= immlo
>> 8;
11426 return (size
== 16) ? 0xa : 0x2;
11428 else if (immlo
== (immlo
& 0x00ff0000))
11432 *immbits
= immlo
>> 16;
11435 else if (immlo
== (immlo
& 0xff000000))
11439 *immbits
= immlo
>> 24;
11442 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11446 *immbits
= (immlo
>> 8) & 0xff;
11449 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11453 *immbits
= (immlo
>> 16) & 0xff;
11460 /* Write immediate bits [7:0] to the following locations:
11462 |28/24|23 19|18 16|15 4|3 0|
11463 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11465 This function is used by VMOV/VMVN/VORR/VBIC. */
11468 neon_write_immbits (unsigned immbits
)
11470 inst
.instruction
|= immbits
& 0xf;
11471 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11472 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11475 /* Invert low-order SIZE bits of XHI:XLO. */
11478 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11480 unsigned immlo
= xlo
? *xlo
: 0;
11481 unsigned immhi
= xhi
? *xhi
: 0;
11486 immlo
= (~immlo
) & 0xff;
11490 immlo
= (~immlo
) & 0xffff;
11494 immhi
= (~immhi
) & 0xffffffff;
11495 /* fall through. */
11498 immlo
= (~immlo
) & 0xffffffff;
11513 do_neon_logic (void)
11515 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11517 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11518 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11519 /* U bit and size field were set as part of the bitmask. */
11520 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11521 neon_three_same (neon_quad (rs
), 0, -1);
11525 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11526 struct neon_type_el et
= neon_check_type (2, rs
,
11527 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11528 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11532 if (et
.type
== NT_invtype
)
11535 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11540 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11545 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11550 /* Pseudo-instruction for VBIC. */
11551 immbits
= inst
.operands
[1].imm
;
11552 neon_invert_size (&immbits
, 0, et
.size
);
11553 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11557 /* Pseudo-instruction for VORR. */
11558 immbits
= inst
.operands
[1].imm
;
11559 neon_invert_size (&immbits
, 0, et
.size
);
11560 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11570 inst
.instruction
|= neon_quad (rs
) << 6;
11571 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11572 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11573 inst
.instruction
|= cmode
<< 8;
11574 neon_write_immbits (immbits
);
11576 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11581 do_neon_bitfield (void)
11583 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11584 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11585 neon_three_same (neon_quad (rs
), 0, -1);
11589 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
11592 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11593 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
11595 if (et
.type
== NT_float
)
11597 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
11598 neon_three_same (neon_quad (rs
), 0, -1);
11602 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11603 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
11608 do_neon_dyadic_if_su (void)
11610 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11614 do_neon_dyadic_if_su_d (void)
11616 /* This version only allow D registers, but that constraint is enforced during
11617 operand parsing so we don't need to do anything extra here. */
11618 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11622 do_neon_dyadic_if_i_d (void)
11624 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11625 affected if we specify unsigned args. */
11626 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
11629 enum vfp_or_neon_is_neon_bits
11632 NEON_CHECK_ARCH
= 2
11635 /* Call this function if an instruction which may have belonged to the VFP or
11636 Neon instruction sets, but turned out to be a Neon instruction (due to the
11637 operand types involved, etc.). We have to check and/or fix-up a couple of
11640 - Make sure the user hasn't attempted to make a Neon instruction
11642 - Alter the value in the condition code field if necessary.
11643 - Make sure that the arch supports Neon instructions.
11645 Which of these operations take place depends on bits from enum
11646 vfp_or_neon_is_neon_bits.
11648 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
11649 current instruction's condition is COND_ALWAYS, the condition field is
11650 changed to inst.uncond_value. This is necessary because instructions shared
11651 between VFP and Neon may be conditional for the VFP variants only, and the
11652 unconditional Neon version must have, e.g., 0xF in the condition field. */
11655 vfp_or_neon_is_neon (unsigned check
)
11657 /* Conditions are always legal in Thumb mode (IT blocks). */
11658 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
11660 if (inst
.cond
!= COND_ALWAYS
)
11662 first_error (_(BAD_COND
));
11665 if (inst
.uncond_value
!= -1)
11666 inst
.instruction
|= inst
.uncond_value
<< 28;
11669 if ((check
& NEON_CHECK_ARCH
)
11670 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
11672 first_error (_(BAD_FPU
));
11680 do_neon_addsub_if_i (void)
11682 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
11685 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11688 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11689 affected if we specify unsigned args. */
11690 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
11693 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
11695 V<op> A,B (A is operand 0, B is operand 2)
11700 so handle that case specially. */
11703 neon_exchange_operands (void)
11705 void *scratch
= alloca (sizeof (inst
.operands
[0]));
11706 if (inst
.operands
[1].present
)
11708 /* Swap operands[1] and operands[2]. */
11709 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
11710 inst
.operands
[1] = inst
.operands
[2];
11711 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
11715 inst
.operands
[1] = inst
.operands
[2];
11716 inst
.operands
[2] = inst
.operands
[0];
11721 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
11723 if (inst
.operands
[2].isreg
)
11726 neon_exchange_operands ();
11727 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
11731 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11732 struct neon_type_el et
= neon_check_type (2, rs
,
11733 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
11735 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11736 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11737 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11738 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11739 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11740 inst
.instruction
|= neon_quad (rs
) << 6;
11741 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11742 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11744 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11751 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
11755 do_neon_cmp_inv (void)
11757 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
11763 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
11766 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
11767 scalars, which are encoded in 5 bits, M : Rm.
11768 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
11769 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
11773 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
11775 unsigned regno
= NEON_SCALAR_REG (scalar
);
11776 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
11781 if (regno
> 7 || elno
> 3)
11783 return regno
| (elno
<< 3);
11786 if (regno
> 15 || elno
> 1)
11788 return regno
| (elno
<< 4);
11792 first_error (_("scalar out of range for multiply instruction"));
11798 /* Encode multiply / multiply-accumulate scalar instructions. */
11801 neon_mul_mac (struct neon_type_el et
, int ubit
)
11805 /* Give a more helpful error message if we have an invalid type. */
11806 if (et
.type
== NT_invtype
)
11809 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
11810 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11811 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11812 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11813 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11814 inst
.instruction
|= LOW4 (scalar
);
11815 inst
.instruction
|= HI1 (scalar
) << 5;
11816 inst
.instruction
|= (et
.type
== NT_float
) << 8;
11817 inst
.instruction
|= neon_logbits (et
.size
) << 20;
11818 inst
.instruction
|= (ubit
!= 0) << 24;
11820 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11824 do_neon_mac_maybe_scalar (void)
11826 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
11829 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11832 if (inst
.operands
[2].isscalar
)
11834 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11835 struct neon_type_el et
= neon_check_type (3, rs
,
11836 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
11837 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11838 neon_mul_mac (et
, neon_quad (rs
));
11842 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11843 affected if we specify unsigned args. */
11844 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
11851 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11852 struct neon_type_el et
= neon_check_type (3, rs
,
11853 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
11854 neon_three_same (neon_quad (rs
), 0, et
.size
);
11857 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
11858 same types as the MAC equivalents. The polynomial type for this instruction
11859 is encoded the same as the integer type. */
11864 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
11867 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11870 if (inst
.operands
[2].isscalar
)
11871 do_neon_mac_maybe_scalar ();
11873 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
11877 do_neon_qdmulh (void)
11879 if (inst
.operands
[2].isscalar
)
11881 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11882 struct neon_type_el et
= neon_check_type (3, rs
,
11883 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11884 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11885 neon_mul_mac (et
, neon_quad (rs
));
11889 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11890 struct neon_type_el et
= neon_check_type (3, rs
,
11891 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11892 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11893 /* The U bit (rounding) comes from bit mask. */
11894 neon_three_same (neon_quad (rs
), 0, et
.size
);
11899 do_neon_fcmp_absolute (void)
11901 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11902 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
11903 /* Size field comes from bit mask. */
11904 neon_three_same (neon_quad (rs
), 1, -1);
11908 do_neon_fcmp_absolute_inv (void)
11910 neon_exchange_operands ();
11911 do_neon_fcmp_absolute ();
11915 do_neon_step (void)
11917 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11918 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
11919 neon_three_same (neon_quad (rs
), 0, -1);
11923 do_neon_abs_neg (void)
11925 enum neon_shape rs
;
11926 struct neon_type_el et
;
11928 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
11931 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11934 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
11935 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
11937 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11938 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11939 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11940 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11941 inst
.instruction
|= neon_quad (rs
) << 6;
11942 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11943 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11945 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11951 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11952 struct neon_type_el et
= neon_check_type (2, rs
,
11953 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
11954 int imm
= inst
.operands
[2].imm
;
11955 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
11956 _("immediate out of range for insert"));
11957 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
11963 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11964 struct neon_type_el et
= neon_check_type (2, rs
,
11965 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
11966 int imm
= inst
.operands
[2].imm
;
11967 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
11968 _("immediate out of range for insert"));
11969 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
11973 do_neon_qshlu_imm (void)
11975 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11976 struct neon_type_el et
= neon_check_type (2, rs
,
11977 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
11978 int imm
= inst
.operands
[2].imm
;
11979 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
11980 _("immediate out of range for shift"));
11981 /* Only encodes the 'U present' variant of the instruction.
11982 In this case, signed types have OP (bit 8) set to 0.
11983 Unsigned types have OP set to 1. */
11984 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
11985 /* The rest of the bits are the same as other immediate shifts. */
11986 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
11990 do_neon_qmovn (void)
11992 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
11993 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
11994 /* Saturating move where operands can be signed or unsigned, and the
11995 destination has the same signedness. */
11996 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11997 if (et
.type
== NT_unsigned
)
11998 inst
.instruction
|= 0xc0;
12000 inst
.instruction
|= 0x80;
12001 neon_two_same (0, 1, et
.size
/ 2);
12005 do_neon_qmovun (void)
12007 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12008 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12009 /* Saturating move with unsigned results. Operands must be signed. */
12010 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12011 neon_two_same (0, 1, et
.size
/ 2);
12015 do_neon_rshift_sat_narrow (void)
12017 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12018 or unsigned. If operands are unsigned, results must also be unsigned. */
12019 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12020 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12021 int imm
= inst
.operands
[2].imm
;
12022 /* This gets the bounds check, size encoding and immediate bits calculation
12026 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12027 VQMOVN.I<size> <Dd>, <Qm>. */
12030 inst
.operands
[2].present
= 0;
12031 inst
.instruction
= N_MNEM_vqmovn
;
12036 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12037 _("immediate out of range"));
12038 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12042 do_neon_rshift_sat_narrow_u (void)
12044 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12045 or unsigned. If operands are unsigned, results must also be unsigned. */
12046 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12047 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12048 int imm
= inst
.operands
[2].imm
;
12049 /* This gets the bounds check, size encoding and immediate bits calculation
12053 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12054 VQMOVUN.I<size> <Dd>, <Qm>. */
12057 inst
.operands
[2].present
= 0;
12058 inst
.instruction
= N_MNEM_vqmovun
;
12063 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12064 _("immediate out of range"));
12065 /* FIXME: The manual is kind of unclear about what value U should have in
12066 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12068 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12072 do_neon_movn (void)
12074 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12075 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12076 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12077 neon_two_same (0, 1, et
.size
/ 2);
12081 do_neon_rshift_narrow (void)
12083 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12084 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12085 int imm
= inst
.operands
[2].imm
;
12086 /* This gets the bounds check, size encoding and immediate bits calculation
12090 /* If immediate is zero then we are a pseudo-instruction for
12091 VMOVN.I<size> <Dd>, <Qm> */
12094 inst
.operands
[2].present
= 0;
12095 inst
.instruction
= N_MNEM_vmovn
;
12100 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12101 _("immediate out of range for narrowing operation"));
12102 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12106 do_neon_shll (void)
12108 /* FIXME: Type checking when lengthening. */
12109 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12110 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12111 unsigned imm
= inst
.operands
[2].imm
;
12113 if (imm
== et
.size
)
12115 /* Maximum shift variant. */
12116 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12117 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12118 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12119 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12120 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12121 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12123 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12127 /* A more-specific type check for non-max versions. */
12128 et
= neon_check_type (2, NS_QDI
,
12129 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12130 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12131 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12135 /* Check the various types for the VCVT instruction, and return which version
12136 the current instruction is. */
12139 neon_cvt_flavour (enum neon_shape rs
)
12141 #define CVT_VAR(C,X,Y) \
12142 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12143 if (et.type != NT_invtype) \
12145 inst.error = NULL; \
12148 struct neon_type_el et
;
12149 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12150 || rs
== NS_FF
) ? N_VFP
: 0;
12151 /* The instruction versions which take an immediate take one register
12152 argument, which is extended to the width of the full register. Thus the
12153 "source" and "destination" registers must have the same width. Hack that
12154 here by making the size equal to the key (wider, in this case) operand. */
12155 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12157 CVT_VAR (0, N_S32
, N_F32
);
12158 CVT_VAR (1, N_U32
, N_F32
);
12159 CVT_VAR (2, N_F32
, N_S32
);
12160 CVT_VAR (3, N_F32
, N_U32
);
12164 /* VFP instructions. */
12165 CVT_VAR (4, N_F32
, N_F64
);
12166 CVT_VAR (5, N_F64
, N_F32
);
12167 CVT_VAR (6, N_S32
, N_F64
| key
);
12168 CVT_VAR (7, N_U32
, N_F64
| key
);
12169 CVT_VAR (8, N_F64
| key
, N_S32
);
12170 CVT_VAR (9, N_F64
| key
, N_U32
);
12171 /* VFP instructions with bitshift. */
12172 CVT_VAR (10, N_F32
| key
, N_S16
);
12173 CVT_VAR (11, N_F32
| key
, N_U16
);
12174 CVT_VAR (12, N_F64
| key
, N_S16
);
12175 CVT_VAR (13, N_F64
| key
, N_U16
);
12176 CVT_VAR (14, N_S16
, N_F32
| key
);
12177 CVT_VAR (15, N_U16
, N_F32
| key
);
12178 CVT_VAR (16, N_S16
, N_F64
| key
);
12179 CVT_VAR (17, N_U16
, N_F64
| key
);
12185 /* Neon-syntax VFP conversions. */
12188 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12190 const char *opname
= 0;
12192 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12194 /* Conversions with immediate bitshift. */
12195 const char *enc
[] =
12217 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12219 opname
= enc
[flavour
];
12220 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12221 _("operands 0 and 1 must be the same register"));
12222 inst
.operands
[1] = inst
.operands
[2];
12223 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12228 /* Conversions without bitshift. */
12229 const char *enc
[] =
12243 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12244 opname
= enc
[flavour
];
12248 do_vfp_nsyn_opcode (opname
);
12252 do_vfp_nsyn_cvtz (void)
12254 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12255 int flavour
= neon_cvt_flavour (rs
);
12256 const char *enc
[] =
12268 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12269 do_vfp_nsyn_opcode (enc
[flavour
]);
12275 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12276 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12277 int flavour
= neon_cvt_flavour (rs
);
12279 /* VFP rather than Neon conversions. */
12282 do_vfp_nsyn_cvt (rs
, flavour
);
12291 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12294 /* Fixed-point conversion with #0 immediate is encoded as an
12295 integer conversion. */
12296 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12298 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12299 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12300 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12302 inst
.instruction
|= enctab
[flavour
];
12303 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12304 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12305 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12306 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12307 inst
.instruction
|= neon_quad (rs
) << 6;
12308 inst
.instruction
|= 1 << 21;
12309 inst
.instruction
|= immbits
<< 16;
12311 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12319 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12321 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12323 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12327 inst
.instruction
|= enctab
[flavour
];
12329 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12330 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12331 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12332 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12333 inst
.instruction
|= neon_quad (rs
) << 6;
12334 inst
.instruction
|= 2 << 18;
12336 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12341 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12342 do_vfp_nsyn_cvt (rs
, flavour
);
12347 neon_move_immediate (void)
12349 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12350 struct neon_type_el et
= neon_check_type (2, rs
,
12351 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12352 unsigned immlo
, immhi
= 0, immbits
;
12355 constraint (et
.type
== NT_invtype
,
12356 _("operand size must be specified for immediate VMOV"));
12358 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12359 op
= (inst
.instruction
& (1 << 5)) != 0;
12361 immlo
= inst
.operands
[1].imm
;
12362 if (inst
.operands
[1].regisimm
)
12363 immhi
= inst
.operands
[1].reg
;
12365 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12366 _("immediate has bits set outside the operand size"));
12368 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12369 et
.size
, et
.type
)) == FAIL
)
12371 /* Invert relevant bits only. */
12372 neon_invert_size (&immlo
, &immhi
, et
.size
);
12373 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12374 with one or the other; those cases are caught by
12375 neon_cmode_for_move_imm. */
12377 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12378 et
.size
, et
.type
)) == FAIL
)
12380 first_error (_("immediate out of range"));
12385 inst
.instruction
&= ~(1 << 5);
12386 inst
.instruction
|= op
<< 5;
12388 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12389 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12390 inst
.instruction
|= neon_quad (rs
) << 6;
12391 inst
.instruction
|= cmode
<< 8;
12393 neon_write_immbits (immbits
);
12399 if (inst
.operands
[1].isreg
)
12401 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12403 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12404 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12405 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12406 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12407 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12408 inst
.instruction
|= neon_quad (rs
) << 6;
12412 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12413 neon_move_immediate ();
12416 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12419 /* Encode instructions of form:
12421 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12422 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12427 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12429 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12430 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12431 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12432 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12433 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12434 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12435 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12436 inst
.instruction
|= neon_logbits (size
) << 20;
12438 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12442 do_neon_dyadic_long (void)
12444 /* FIXME: Type checking for lengthening op. */
12445 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12446 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12447 neon_mixed_length (et
, et
.size
);
12451 do_neon_abal (void)
12453 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12454 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12455 neon_mixed_length (et
, et
.size
);
12459 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12461 if (inst
.operands
[2].isscalar
)
12463 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12464 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12465 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12466 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12470 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12471 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12472 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12473 neon_mixed_length (et
, et
.size
);
12478 do_neon_mac_maybe_scalar_long (void)
12480 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12484 do_neon_dyadic_wide (void)
12486 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12487 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12488 neon_mixed_length (et
, et
.size
);
12492 do_neon_dyadic_narrow (void)
12494 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12495 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12496 /* Operand sign is unimportant, and the U bit is part of the opcode,
12497 so force the operand type to integer. */
12498 et
.type
= NT_integer
;
12499 neon_mixed_length (et
, et
.size
/ 2);
12503 do_neon_mul_sat_scalar_long (void)
12505 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12509 do_neon_vmull (void)
12511 if (inst
.operands
[2].isscalar
)
12512 do_neon_mac_maybe_scalar_long ();
12515 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12516 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12517 if (et
.type
== NT_poly
)
12518 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12520 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12521 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12522 zero. Should be OK as-is. */
12523 neon_mixed_length (et
, et
.size
);
12530 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12531 struct neon_type_el et
= neon_check_type (3, rs
,
12532 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12533 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12534 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12535 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12536 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12537 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12538 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12539 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12540 inst
.instruction
|= neon_quad (rs
) << 6;
12541 inst
.instruction
|= imm
<< 8;
12543 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12549 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12550 struct neon_type_el et
= neon_check_type (2, rs
,
12551 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12552 unsigned op
= (inst
.instruction
>> 7) & 3;
12553 /* N (width of reversed regions) is encoded as part of the bitmask. We
12554 extract it here to check the elements to be reversed are smaller.
12555 Otherwise we'd get a reserved instruction. */
12556 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12557 assert (elsize
!= 0);
12558 constraint (et
.size
>= elsize
,
12559 _("elements must be smaller than reversal region"));
12560 neon_two_same (neon_quad (rs
), 1, et
.size
);
12566 if (inst
.operands
[1].isscalar
)
12568 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12569 struct neon_type_el et
= neon_check_type (2, rs
,
12570 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12571 unsigned sizebits
= et
.size
>> 3;
12572 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12573 int logsize
= neon_logbits (et
.size
);
12574 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
12576 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
12579 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12580 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12581 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12582 inst
.instruction
|= LOW4 (dm
);
12583 inst
.instruction
|= HI1 (dm
) << 5;
12584 inst
.instruction
|= neon_quad (rs
) << 6;
12585 inst
.instruction
|= x
<< 17;
12586 inst
.instruction
|= sizebits
<< 16;
12588 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12592 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
12593 struct neon_type_el et
= neon_check_type (2, rs
,
12594 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12595 /* Duplicate ARM register to lanes of vector. */
12596 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
12599 case 8: inst
.instruction
|= 0x400000; break;
12600 case 16: inst
.instruction
|= 0x000020; break;
12601 case 32: inst
.instruction
|= 0x000000; break;
12604 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
12605 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
12606 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
12607 inst
.instruction
|= neon_quad (rs
) << 21;
12608 /* The encoding for this instruction is identical for the ARM and Thumb
12609 variants, except for the condition field. */
12610 do_vfp_cond_or_thumb ();
12614 /* VMOV has particularly many variations. It can be one of:
12615 0. VMOV<c><q> <Qd>, <Qm>
12616 1. VMOV<c><q> <Dd>, <Dm>
12617 (Register operations, which are VORR with Rm = Rn.)
12618 2. VMOV<c><q>.<dt> <Qd>, #<imm>
12619 3. VMOV<c><q>.<dt> <Dd>, #<imm>
12621 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
12622 (ARM register to scalar.)
12623 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
12624 (Two ARM registers to vector.)
12625 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
12626 (Scalar to ARM register.)
12627 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
12628 (Vector to two ARM registers.)
12629 8. VMOV.F32 <Sd>, <Sm>
12630 9. VMOV.F64 <Dd>, <Dm>
12631 (VFP register moves.)
12632 10. VMOV.F32 <Sd>, #imm
12633 11. VMOV.F64 <Dd>, #imm
12634 (VFP float immediate load.)
12635 12. VMOV <Rd>, <Sm>
12636 (VFP single to ARM reg.)
12637 13. VMOV <Sd>, <Rm>
12638 (ARM reg to VFP single.)
12639 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
12640 (Two ARM regs to two VFP singles.)
12641 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
12642 (Two VFP singles to two ARM regs.)
12644 These cases can be disambiguated using neon_select_shape, except cases 1/9
12645 and 3/11 which depend on the operand type too.
12647 All the encoded bits are hardcoded by this function.
12649 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
12650 Cases 5, 7 may be used with VFPv2 and above.
12652 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
12653 can specify a type where it doesn't make sense to, and is ignored).
12659 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
12660 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
12662 struct neon_type_el et
;
12663 const char *ldconst
= 0;
12667 case NS_DD
: /* case 1/9. */
12668 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12669 /* It is not an error here if no type is given. */
12671 if (et
.type
== NT_float
&& et
.size
== 64)
12673 do_vfp_nsyn_opcode ("fcpyd");
12676 /* fall through. */
12678 case NS_QQ
: /* case 0/1. */
12680 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12682 /* The architecture manual I have doesn't explicitly state which
12683 value the U bit should have for register->register moves, but
12684 the equivalent VORR instruction has U = 0, so do that. */
12685 inst
.instruction
= 0x0200110;
12686 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12687 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12688 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12689 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12690 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12691 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12692 inst
.instruction
|= neon_quad (rs
) << 6;
12694 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12698 case NS_DI
: /* case 3/11. */
12699 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12701 if (et
.type
== NT_float
&& et
.size
== 64)
12703 /* case 11 (fconstd). */
12704 ldconst
= "fconstd";
12705 goto encode_fconstd
;
12707 /* fall through. */
12709 case NS_QI
: /* case 2/3. */
12710 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12712 inst
.instruction
= 0x0800010;
12713 neon_move_immediate ();
12714 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12717 case NS_SR
: /* case 4. */
12719 unsigned bcdebits
= 0;
12720 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12721 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12722 int logsize
= neon_logbits (et
.size
);
12723 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
12724 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
12726 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12728 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12729 && et
.size
!= 32, _(BAD_FPU
));
12730 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12731 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12735 case 8: bcdebits
= 0x8; break;
12736 case 16: bcdebits
= 0x1; break;
12737 case 32: bcdebits
= 0x0; break;
12741 bcdebits
|= x
<< logsize
;
12743 inst
.instruction
= 0xe000b10;
12744 do_vfp_cond_or_thumb ();
12745 inst
.instruction
|= LOW4 (dn
) << 16;
12746 inst
.instruction
|= HI1 (dn
) << 7;
12747 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12748 inst
.instruction
|= (bcdebits
& 3) << 5;
12749 inst
.instruction
|= (bcdebits
>> 2) << 21;
12753 case NS_DRR
: /* case 5 (fmdrr). */
12754 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12757 inst
.instruction
= 0xc400b10;
12758 do_vfp_cond_or_thumb ();
12759 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
12760 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
12761 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12762 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12765 case NS_RS
: /* case 6. */
12767 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12768 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
12769 unsigned logsize
= neon_logbits (et
.size
);
12770 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12771 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
12772 unsigned abcdebits
= 0;
12774 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12776 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12777 && et
.size
!= 32, _(BAD_FPU
));
12778 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12779 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12783 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
12784 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
12785 case 32: abcdebits
= 0x00; break;
12789 abcdebits
|= x
<< logsize
;
12790 inst
.instruction
= 0xe100b10;
12791 do_vfp_cond_or_thumb ();
12792 inst
.instruction
|= LOW4 (dn
) << 16;
12793 inst
.instruction
|= HI1 (dn
) << 7;
12794 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12795 inst
.instruction
|= (abcdebits
& 3) << 5;
12796 inst
.instruction
|= (abcdebits
>> 2) << 21;
12800 case NS_RRD
: /* case 7 (fmrrd). */
12801 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12804 inst
.instruction
= 0xc500b10;
12805 do_vfp_cond_or_thumb ();
12806 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12807 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12808 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12809 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12812 case NS_FF
: /* case 8 (fcpys). */
12813 do_vfp_nsyn_opcode ("fcpys");
12816 case NS_FI
: /* case 10 (fconsts). */
12817 ldconst
= "fconsts";
12819 if (is_quarter_float (inst
.operands
[1].imm
))
12821 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
12822 do_vfp_nsyn_opcode (ldconst
);
12825 first_error (_("immediate out of range"));
12828 case NS_RF
: /* case 12 (fmrs). */
12829 do_vfp_nsyn_opcode ("fmrs");
12832 case NS_FR
: /* case 13 (fmsr). */
12833 do_vfp_nsyn_opcode ("fmsr");
12836 /* The encoders for the fmrrs and fmsrr instructions expect three operands
12837 (one of which is a list), but we have parsed four. Do some fiddling to
12838 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
12840 case NS_RRFF
: /* case 14 (fmrrs). */
12841 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
12842 _("VFP registers must be adjacent"));
12843 inst
.operands
[2].imm
= 2;
12844 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12845 do_vfp_nsyn_opcode ("fmrrs");
12848 case NS_FFRR
: /* case 15 (fmsrr). */
12849 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
12850 _("VFP registers must be adjacent"));
12851 inst
.operands
[1] = inst
.operands
[2];
12852 inst
.operands
[2] = inst
.operands
[3];
12853 inst
.operands
[0].imm
= 2;
12854 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12855 do_vfp_nsyn_opcode ("fmsrr");
12864 do_neon_rshift_round_imm (void)
12866 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12867 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12868 int imm
= inst
.operands
[2].imm
;
12870 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
12873 inst
.operands
[2].present
= 0;
12878 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12879 _("immediate out of range for shift"));
12880 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12885 do_neon_movl (void)
12887 struct neon_type_el et
= neon_check_type (2, NS_QD
,
12888 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12889 unsigned sizebits
= et
.size
>> 3;
12890 inst
.instruction
|= sizebits
<< 19;
12891 neon_two_same (0, et
.type
== NT_unsigned
, -1);
12897 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12898 struct neon_type_el et
= neon_check_type (2, rs
,
12899 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12900 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12901 neon_two_same (neon_quad (rs
), 1, et
.size
);
12905 do_neon_zip_uzp (void)
12907 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12908 struct neon_type_el et
= neon_check_type (2, rs
,
12909 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12910 if (rs
== NS_DD
&& et
.size
== 32)
12912 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
12913 inst
.instruction
= N_MNEM_vtrn
;
12917 neon_two_same (neon_quad (rs
), 1, et
.size
);
12921 do_neon_sat_abs_neg (void)
12923 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12924 struct neon_type_el et
= neon_check_type (2, rs
,
12925 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
12926 neon_two_same (neon_quad (rs
), 1, et
.size
);
12930 do_neon_pair_long (void)
12932 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12933 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
12934 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
12935 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
12936 neon_two_same (neon_quad (rs
), 1, et
.size
);
12940 do_neon_recip_est (void)
12942 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12943 struct neon_type_el et
= neon_check_type (2, rs
,
12944 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
12945 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12946 neon_two_same (neon_quad (rs
), 1, et
.size
);
12952 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12953 struct neon_type_el et
= neon_check_type (2, rs
,
12954 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
12955 neon_two_same (neon_quad (rs
), 1, et
.size
);
12961 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12962 struct neon_type_el et
= neon_check_type (2, rs
,
12963 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
12964 neon_two_same (neon_quad (rs
), 1, et
.size
);
12970 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12971 struct neon_type_el et
= neon_check_type (2, rs
,
12972 N_EQK
| N_INT
, N_8
| N_KEY
);
12973 neon_two_same (neon_quad (rs
), 1, et
.size
);
12979 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12980 neon_two_same (neon_quad (rs
), 1, -1);
12984 do_neon_tbl_tbx (void)
12986 unsigned listlenbits
;
12987 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
12989 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
12991 first_error (_("bad list length for table lookup"));
12995 listlenbits
= inst
.operands
[1].imm
- 1;
12996 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12997 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12998 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12999 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13000 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13001 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13002 inst
.instruction
|= listlenbits
<< 8;
13004 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13008 do_neon_ldm_stm (void)
13010 /* P, U and L bits are part of bitmask. */
13011 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13012 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13014 if (inst
.operands
[1].issingle
)
13016 do_vfp_nsyn_ldm_stm (is_dbmode
);
13020 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13021 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13023 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13024 _("register list must contain at least 1 and at most 16 "
13027 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13028 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13029 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13030 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13032 inst
.instruction
|= offsetbits
;
13034 do_vfp_cond_or_thumb ();
13038 do_neon_ldr_str (void)
13040 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13042 if (inst
.operands
[0].issingle
)
13045 do_vfp_nsyn_opcode ("flds");
13047 do_vfp_nsyn_opcode ("fsts");
13052 do_vfp_nsyn_opcode ("fldd");
13054 do_vfp_nsyn_opcode ("fstd");
13058 /* "interleave" version also handles non-interleaving register VLD1/VST1
13062 do_neon_ld_st_interleave (void)
13064 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13065 N_8
| N_16
| N_32
| N_64
);
13066 unsigned alignbits
= 0;
13068 /* The bits in this table go:
13069 0: register stride of one (0) or two (1)
13070 1,2: register list length, minus one (1, 2, 3, 4).
13071 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13072 We use -1 for invalid entries. */
13073 const int typetable
[] =
13075 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13076 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13077 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13078 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13082 if (et
.type
== NT_invtype
)
13085 if (inst
.operands
[1].immisalign
)
13086 switch (inst
.operands
[1].imm
>> 8)
13088 case 64: alignbits
= 1; break;
13090 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13091 goto bad_alignment
;
13095 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13096 goto bad_alignment
;
13101 first_error (_("bad alignment"));
13105 inst
.instruction
|= alignbits
<< 4;
13106 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13108 /* Bits [4:6] of the immediate in a list specifier encode register stride
13109 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13110 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13111 up the right value for "type" in a table based on this value and the given
13112 list style, then stick it back. */
13113 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13114 | (((inst
.instruction
>> 8) & 3) << 3);
13116 typebits
= typetable
[idx
];
13118 constraint (typebits
== -1, _("bad list type for instruction"));
13120 inst
.instruction
&= ~0xf00;
13121 inst
.instruction
|= typebits
<< 8;
13124 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13125 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13126 otherwise. The variable arguments are a list of pairs of legal (size, align)
13127 values, terminated with -1. */
13130 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13133 int result
= FAIL
, thissize
, thisalign
;
13135 if (!inst
.operands
[1].immisalign
)
13141 va_start (ap
, do_align
);
13145 thissize
= va_arg (ap
, int);
13146 if (thissize
== -1)
13148 thisalign
= va_arg (ap
, int);
13150 if (size
== thissize
&& align
== thisalign
)
13153 while (result
!= SUCCESS
);
13157 if (result
== SUCCESS
)
13160 first_error (_("unsupported alignment for instruction"));
13166 do_neon_ld_st_lane (void)
13168 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13169 int align_good
, do_align
= 0;
13170 int logsize
= neon_logbits (et
.size
);
13171 int align
= inst
.operands
[1].imm
>> 8;
13172 int n
= (inst
.instruction
>> 8) & 3;
13173 int max_el
= 64 / et
.size
;
13175 if (et
.type
== NT_invtype
)
13178 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13179 _("bad list length"));
13180 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13181 _("scalar index out of range"));
13182 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13184 _("stride of 2 unavailable when element size is 8"));
13188 case 0: /* VLD1 / VST1. */
13189 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13191 if (align_good
== FAIL
)
13195 unsigned alignbits
= 0;
13198 case 16: alignbits
= 0x1; break;
13199 case 32: alignbits
= 0x3; break;
13202 inst
.instruction
|= alignbits
<< 4;
13206 case 1: /* VLD2 / VST2. */
13207 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13209 if (align_good
== FAIL
)
13212 inst
.instruction
|= 1 << 4;
13215 case 2: /* VLD3 / VST3. */
13216 constraint (inst
.operands
[1].immisalign
,
13217 _("can't use alignment with this instruction"));
13220 case 3: /* VLD4 / VST4. */
13221 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13222 16, 64, 32, 64, 32, 128, -1);
13223 if (align_good
== FAIL
)
13227 unsigned alignbits
= 0;
13230 case 8: alignbits
= 0x1; break;
13231 case 16: alignbits
= 0x1; break;
13232 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13235 inst
.instruction
|= alignbits
<< 4;
13242 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13243 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13244 inst
.instruction
|= 1 << (4 + logsize
);
13246 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13247 inst
.instruction
|= logsize
<< 10;
13250 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13253 do_neon_ld_dup (void)
13255 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13256 int align_good
, do_align
= 0;
13258 if (et
.type
== NT_invtype
)
13261 switch ((inst
.instruction
>> 8) & 3)
13263 case 0: /* VLD1. */
13264 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13265 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13266 &do_align
, 16, 16, 32, 32, -1);
13267 if (align_good
== FAIL
)
13269 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13272 case 2: inst
.instruction
|= 1 << 5; break;
13273 default: first_error (_("bad list length")); return;
13275 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13278 case 1: /* VLD2. */
13279 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13280 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13281 if (align_good
== FAIL
)
13283 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13284 _("bad list length"));
13285 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13286 inst
.instruction
|= 1 << 5;
13287 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13290 case 2: /* VLD3. */
13291 constraint (inst
.operands
[1].immisalign
,
13292 _("can't use alignment with this instruction"));
13293 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13294 _("bad list length"));
13295 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13296 inst
.instruction
|= 1 << 5;
13297 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13300 case 3: /* VLD4. */
13302 int align
= inst
.operands
[1].imm
>> 8;
13303 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13304 16, 64, 32, 64, 32, 128, -1);
13305 if (align_good
== FAIL
)
13307 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13308 _("bad list length"));
13309 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13310 inst
.instruction
|= 1 << 5;
13311 if (et
.size
== 32 && align
== 128)
13312 inst
.instruction
|= 0x3 << 6;
13314 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13321 inst
.instruction
|= do_align
<< 4;
13324 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13325 apart from bits [11:4]. */
13328 do_neon_ldx_stx (void)
13330 switch (NEON_LANE (inst
.operands
[0].imm
))
13332 case NEON_INTERLEAVE_LANES
:
13333 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13334 do_neon_ld_st_interleave ();
13337 case NEON_ALL_LANES
:
13338 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13343 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13344 do_neon_ld_st_lane ();
13347 /* L bit comes from bit mask. */
13348 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13349 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13350 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13352 if (inst
.operands
[1].postind
)
13354 int postreg
= inst
.operands
[1].imm
& 0xf;
13355 constraint (!inst
.operands
[1].immisreg
,
13356 _("post-index must be a register"));
13357 constraint (postreg
== 0xd || postreg
== 0xf,
13358 _("bad register for post-index"));
13359 inst
.instruction
|= postreg
;
13361 else if (inst
.operands
[1].writeback
)
13363 inst
.instruction
|= 0xd;
13366 inst
.instruction
|= 0xf;
13369 inst
.instruction
|= 0xf9000000;
13371 inst
.instruction
|= 0xf4000000;
13375 /* Overall per-instruction processing. */
13377 /* We need to be able to fix up arbitrary expressions in some statements.
13378 This is so that we can handle symbols that are an arbitrary distance from
13379 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13380 which returns part of an address in a form which will be valid for
13381 a data instruction. We do this by pushing the expression into a symbol
13382 in the expr_section, and creating a fix for that. */
13385 fix_new_arm (fragS
* frag
,
13400 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13404 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13409 /* Mark whether the fix is to a THUMB instruction, or an ARM
13411 new_fix
->tc_fix_data
= thumb_mode
;
13414 /* Create a frg for an instruction requiring relaxation. */
13416 output_relax_insn (void)
13422 /* The size of the instruction is unknown, so tie the debug info to the
13423 start of the instruction. */
13424 dwarf2_emit_insn (0);
13426 switch (inst
.reloc
.exp
.X_op
)
13429 sym
= inst
.reloc
.exp
.X_add_symbol
;
13430 offset
= inst
.reloc
.exp
.X_add_number
;
13434 offset
= inst
.reloc
.exp
.X_add_number
;
13437 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13441 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13442 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13443 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13446 /* Write a 32-bit thumb instruction to buf. */
13448 put_thumb32_insn (char * buf
, unsigned long insn
)
13450 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13451 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13455 output_inst (const char * str
)
13461 as_bad ("%s -- `%s'", inst
.error
, str
);
13465 output_relax_insn();
13468 if (inst
.size
== 0)
13471 to
= frag_more (inst
.size
);
13473 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13475 assert (inst
.size
== (2 * THUMB_SIZE
));
13476 put_thumb32_insn (to
, inst
.instruction
);
13478 else if (inst
.size
> INSN_SIZE
)
13480 assert (inst
.size
== (2 * INSN_SIZE
));
13481 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13482 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13485 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13487 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13488 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13489 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13492 dwarf2_emit_insn (inst
.size
);
13495 /* Tag values used in struct asm_opcode's tag field. */
13498 OT_unconditional
, /* Instruction cannot be conditionalized.
13499 The ARM condition field is still 0xE. */
13500 OT_unconditionalF
, /* Instruction cannot be conditionalized
13501 and carries 0xF in its ARM condition field. */
13502 OT_csuffix
, /* Instruction takes a conditional suffix. */
13503 OT_csuffixF
, /* Some forms of the instruction take a conditional
13504 suffix, others place 0xF where the condition field
13506 OT_cinfix3
, /* Instruction takes a conditional infix,
13507 beginning at character index 3. (In
13508 unified mode, it becomes a suffix.) */
13509 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13510 tsts, cmps, cmns, and teqs. */
13511 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13512 character index 3, even in unified mode. Used for
13513 legacy instructions where suffix and infix forms
13514 may be ambiguous. */
13515 OT_csuf_or_in3
, /* Instruction takes either a conditional
13516 suffix or an infix at character index 3. */
13517 OT_odd_infix_unc
, /* This is the unconditional variant of an
13518 instruction that takes a conditional infix
13519 at an unusual position. In unified mode,
13520 this variant will accept a suffix. */
13521 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13522 are the conditional variants of instructions that
13523 take conditional infixes in unusual positions.
13524 The infix appears at character index
13525 (tag - OT_odd_infix_0). These are not accepted
13526 in unified mode. */
13529 /* Subroutine of md_assemble, responsible for looking up the primary
13530 opcode from the mnemonic the user wrote. STR points to the
13531 beginning of the mnemonic.
13533 This is not simply a hash table lookup, because of conditional
13534 variants. Most instructions have conditional variants, which are
13535 expressed with a _conditional affix_ to the mnemonic. If we were
13536 to encode each conditional variant as a literal string in the opcode
13537 table, it would have approximately 20,000 entries.
13539 Most mnemonics take this affix as a suffix, and in unified syntax,
13540 'most' is upgraded to 'all'. However, in the divided syntax, some
13541 instructions take the affix as an infix, notably the s-variants of
13542 the arithmetic instructions. Of those instructions, all but six
13543 have the infix appear after the third character of the mnemonic.
13545 Accordingly, the algorithm for looking up primary opcodes given
13548 1. Look up the identifier in the opcode table.
13549 If we find a match, go to step U.
13551 2. Look up the last two characters of the identifier in the
13552 conditions table. If we find a match, look up the first N-2
13553 characters of the identifier in the opcode table. If we
13554 find a match, go to step CE.
13556 3. Look up the fourth and fifth characters of the identifier in
13557 the conditions table. If we find a match, extract those
13558 characters from the identifier, and look up the remaining
13559 characters in the opcode table. If we find a match, go
13564 U. Examine the tag field of the opcode structure, in case this is
13565 one of the six instructions with its conditional infix in an
13566 unusual place. If it is, the tag tells us where to find the
13567 infix; look it up in the conditions table and set inst.cond
13568 accordingly. Otherwise, this is an unconditional instruction.
13569 Again set inst.cond accordingly. Return the opcode structure.
13571 CE. Examine the tag field to make sure this is an instruction that
13572 should receive a conditional suffix. If it is not, fail.
13573 Otherwise, set inst.cond from the suffix we already looked up,
13574 and return the opcode structure.
13576 CM. Examine the tag field to make sure this is an instruction that
13577 should receive a conditional infix after the third character.
13578 If it is not, fail. Otherwise, undo the edits to the current
13579 line of input and proceed as for case CE. */
13581 static const struct asm_opcode
*
13582 opcode_lookup (char **str
)
13586 const struct asm_opcode
*opcode
;
13587 const struct asm_cond
*cond
;
13589 bfd_boolean neon_supported
;
13591 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
13593 /* Scan up to the end of the mnemonic, which must end in white space,
13594 '.' (in unified mode, or for Neon instructions), or end of string. */
13595 for (base
= end
= *str
; *end
!= '\0'; end
++)
13596 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
13602 /* Handle a possible width suffix and/or Neon type suffix. */
13607 /* The .w and .n suffixes are only valid if the unified syntax is in
13609 if (unified_syntax
&& end
[1] == 'w')
13611 else if (unified_syntax
&& end
[1] == 'n')
13616 inst
.vectype
.elems
= 0;
13618 *str
= end
+ offset
;
13620 if (end
[offset
] == '.')
13622 /* See if we have a Neon type suffix (possible in either unified or
13623 non-unified ARM syntax mode). */
13624 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
13627 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
13633 /* Look for unaffixed or special-case affixed mnemonic. */
13634 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
13638 if (opcode
->tag
< OT_odd_infix_0
)
13640 inst
.cond
= COND_ALWAYS
;
13644 if (unified_syntax
)
13645 as_warn (_("conditional infixes are deprecated in unified syntax"));
13646 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
13647 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13650 inst
.cond
= cond
->value
;
13654 /* Cannot have a conditional suffix on a mnemonic of less than two
13656 if (end
- base
< 3)
13659 /* Look for suffixed mnemonic. */
13661 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13662 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
13663 if (opcode
&& cond
)
13666 switch (opcode
->tag
)
13668 case OT_cinfix3_legacy
:
13669 /* Ignore conditional suffixes matched on infix only mnemonics. */
13673 case OT_cinfix3_deprecated
:
13674 case OT_odd_infix_unc
:
13675 if (!unified_syntax
)
13677 /* else fall through */
13681 case OT_csuf_or_in3
:
13682 inst
.cond
= cond
->value
;
13685 case OT_unconditional
:
13686 case OT_unconditionalF
:
13689 inst
.cond
= cond
->value
;
13693 /* delayed diagnostic */
13694 inst
.error
= BAD_COND
;
13695 inst
.cond
= COND_ALWAYS
;
13704 /* Cannot have a usual-position infix on a mnemonic of less than
13705 six characters (five would be a suffix). */
13706 if (end
- base
< 6)
13709 /* Look for infixed mnemonic in the usual position. */
13711 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13715 memcpy (save
, affix
, 2);
13716 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
13717 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
13718 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
13719 memcpy (affix
, save
, 2);
13722 && (opcode
->tag
== OT_cinfix3
13723 || opcode
->tag
== OT_cinfix3_deprecated
13724 || opcode
->tag
== OT_csuf_or_in3
13725 || opcode
->tag
== OT_cinfix3_legacy
))
13729 && (opcode
->tag
== OT_cinfix3
13730 || opcode
->tag
== OT_cinfix3_deprecated
))
13731 as_warn (_("conditional infixes are deprecated in unified syntax"));
13733 inst
.cond
= cond
->value
;
13741 md_assemble (char *str
)
13744 const struct asm_opcode
* opcode
;
13746 /* Align the previous label if needed. */
13747 if (last_label_seen
!= NULL
)
13749 symbol_set_frag (last_label_seen
, frag_now
);
13750 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
13751 S_SET_SEGMENT (last_label_seen
, now_seg
);
13754 memset (&inst
, '\0', sizeof (inst
));
13755 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13757 opcode
= opcode_lookup (&p
);
13760 /* It wasn't an instruction, but it might be a register alias of
13761 the form alias .req reg, or a Neon .dn/.qn directive. */
13762 if (!create_register_alias (str
, p
)
13763 && !create_neon_reg_alias (str
, p
))
13764 as_bad (_("bad instruction `%s'"), str
);
13769 if (opcode
->tag
== OT_cinfix3_deprecated
)
13770 as_warn (_("s suffix on comparison instruction is deprecated"));
13772 /* The value which unconditional instructions should have in place of the
13773 condition field. */
13774 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
13778 arm_feature_set variant
;
13780 variant
= cpu_variant
;
13781 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
13782 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
13783 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
13784 /* Check that this instruction is supported for this CPU. */
13785 if (!opcode
->tvariant
13786 || (thumb_mode
== 1
13787 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
13789 as_bad (_("selected processor does not support `%s'"), str
);
13792 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
13793 && opcode
->tencode
!= do_t_branch
)
13795 as_bad (_("Thumb does not support conditional execution"));
13799 /* Check conditional suffixes. */
13800 if (current_it_mask
)
13803 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
13804 current_it_mask
<<= 1;
13805 current_it_mask
&= 0x1f;
13806 /* The BKPT instruction is unconditional even in an IT block. */
13808 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
13810 as_bad (_("incorrect condition in IT block"));
13814 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
13816 as_bad (_("thumb conditional instrunction not in IT block"));
13820 mapping_state (MAP_THUMB
);
13821 inst
.instruction
= opcode
->tvalue
;
13823 if (!parse_operands (p
, opcode
->operands
))
13824 opcode
->tencode ();
13826 /* Clear current_it_mask at the end of an IT block. */
13827 if (current_it_mask
== 0x10)
13828 current_it_mask
= 0;
13830 if (!(inst
.error
|| inst
.relax
))
13832 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
13833 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
13834 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
13836 as_bad (_("cannot honor width suffix -- `%s'"), str
);
13840 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13841 *opcode
->tvariant
);
13842 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
13843 set those bits when Thumb-2 32-bit instructions are seen. ie.
13844 anything other than bl/blx.
13845 This is overly pessimistic for relaxable instructions. */
13846 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
13848 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13851 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
13853 /* Check that this instruction is supported for this CPU. */
13854 if (!opcode
->avariant
||
13855 !ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
13857 as_bad (_("selected processor does not support `%s'"), str
);
13862 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
13866 mapping_state (MAP_ARM
);
13867 inst
.instruction
= opcode
->avalue
;
13868 if (opcode
->tag
== OT_unconditionalF
)
13869 inst
.instruction
|= 0xF << 28;
13871 inst
.instruction
|= inst
.cond
<< 28;
13872 inst
.size
= INSN_SIZE
;
13873 if (!parse_operands (p
, opcode
->operands
))
13874 opcode
->aencode ();
13875 /* Arm mode bx is marked as both v4T and v5 because it's still required
13876 on a hypothetical non-thumb v5 core. */
13877 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
13878 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
13879 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
13881 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
13882 *opcode
->avariant
);
13886 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
13893 /* Various frobbings of labels and their addresses. */
13896 arm_start_line_hook (void)
13898 last_label_seen
= NULL
;
13902 arm_frob_label (symbolS
* sym
)
13904 last_label_seen
= sym
;
13906 ARM_SET_THUMB (sym
, thumb_mode
);
13908 #if defined OBJ_COFF || defined OBJ_ELF
13909 ARM_SET_INTERWORK (sym
, support_interwork
);
13912 /* Note - do not allow local symbols (.Lxxx) to be labeled
13913 as Thumb functions. This is because these labels, whilst
13914 they exist inside Thumb code, are not the entry points for
13915 possible ARM->Thumb calls. Also, these labels can be used
13916 as part of a computed goto or switch statement. eg gcc
13917 can generate code that looks like this:
13919 ldr r2, [pc, .Laaa]
13929 The first instruction loads the address of the jump table.
13930 The second instruction converts a table index into a byte offset.
13931 The third instruction gets the jump address out of the table.
13932 The fourth instruction performs the jump.
13934 If the address stored at .Laaa is that of a symbol which has the
13935 Thumb_Func bit set, then the linker will arrange for this address
13936 to have the bottom bit set, which in turn would mean that the
13937 address computation performed by the third instruction would end
13938 up with the bottom bit set. Since the ARM is capable of unaligned
13939 word loads, the instruction would then load the incorrect address
13940 out of the jump table, and chaos would ensue. */
13941 if (label_is_thumb_function_name
13942 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
13943 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13945 /* When the address of a Thumb function is taken the bottom
13946 bit of that address should be set. This will allow
13947 interworking between Arm and Thumb functions to work
13950 THUMB_SET_FUNC (sym
, 1);
13952 label_is_thumb_function_name
= FALSE
;
13955 dwarf2_emit_label (sym
);
13959 arm_data_in_code (void)
13961 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
13963 *input_line_pointer
= '/';
13964 input_line_pointer
+= 5;
13965 *input_line_pointer
= 0;
13973 arm_canonicalize_symbol_name (char * name
)
13977 if (thumb_mode
&& (len
= strlen (name
)) > 5
13978 && streq (name
+ len
- 5, "/data"))
13979 *(name
+ len
- 5) = 0;
13984 /* Table of all register names defined by default. The user can
13985 define additional names with .req. Note that all register names
13986 should appear in both upper and lowercase variants. Some registers
13987 also have mixed-case names. */
13989 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
13990 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
13991 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
13992 #define REGSET(p,t) \
13993 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
13994 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
13995 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
13996 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
13997 #define REGSETH(p,t) \
13998 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
13999 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14000 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14001 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14002 #define REGSET2(p,t) \
14003 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14004 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14005 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14006 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14008 static const struct reg_entry reg_names
[] =
14010 /* ARM integer registers. */
14011 REGSET(r
, RN
), REGSET(R
, RN
),
14013 /* ATPCS synonyms. */
14014 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14015 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14016 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14018 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14019 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14020 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14022 /* Well-known aliases. */
14023 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14024 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14026 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14027 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14029 /* Coprocessor numbers. */
14030 REGSET(p
, CP
), REGSET(P
, CP
),
14032 /* Coprocessor register numbers. The "cr" variants are for backward
14034 REGSET(c
, CN
), REGSET(C
, CN
),
14035 REGSET(cr
, CN
), REGSET(CR
, CN
),
14037 /* FPA registers. */
14038 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14039 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14041 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14042 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14044 /* VFP SP registers. */
14045 REGSET(s
,VFS
), REGSET(S
,VFS
),
14046 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14048 /* VFP DP Registers. */
14049 REGSET(d
,VFD
), REGSET(D
,VFD
),
14050 /* Extra Neon DP registers. */
14051 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14053 /* Neon QP registers. */
14054 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14056 /* VFP control registers. */
14057 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14058 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14060 /* Maverick DSP coprocessor registers. */
14061 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14062 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14064 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14065 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14066 REGDEF(dspsc
,0,DSPSC
),
14068 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14069 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14070 REGDEF(DSPSC
,0,DSPSC
),
14072 /* iWMMXt data registers - p0, c0-15. */
14073 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14075 /* iWMMXt control registers - p1, c0-3. */
14076 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14077 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14078 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14079 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14081 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14082 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14083 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14084 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14085 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14087 /* XScale accumulator registers. */
14088 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14094 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14095 within psr_required_here. */
14096 static const struct asm_psr psrs
[] =
14098 /* Backward compatibility notation. Note that "all" is no longer
14099 truly all possible PSR bits. */
14100 {"all", PSR_c
| PSR_f
},
14104 /* Individual flags. */
14109 /* Combinations of flags. */
14110 {"fs", PSR_f
| PSR_s
},
14111 {"fx", PSR_f
| PSR_x
},
14112 {"fc", PSR_f
| PSR_c
},
14113 {"sf", PSR_s
| PSR_f
},
14114 {"sx", PSR_s
| PSR_x
},
14115 {"sc", PSR_s
| PSR_c
},
14116 {"xf", PSR_x
| PSR_f
},
14117 {"xs", PSR_x
| PSR_s
},
14118 {"xc", PSR_x
| PSR_c
},
14119 {"cf", PSR_c
| PSR_f
},
14120 {"cs", PSR_c
| PSR_s
},
14121 {"cx", PSR_c
| PSR_x
},
14122 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14123 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14124 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14125 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14126 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14127 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14128 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14129 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14130 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14131 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14132 {"scf", PSR_s
| PSR_c
| PSR_f
},
14133 {"scx", PSR_s
| PSR_c
| PSR_x
},
14134 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14135 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14136 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14137 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14138 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14139 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14140 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14141 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14142 {"csf", PSR_c
| PSR_s
| PSR_f
},
14143 {"csx", PSR_c
| PSR_s
| PSR_x
},
14144 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14145 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14146 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14147 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14148 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14149 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14150 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14151 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14152 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14153 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14154 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14155 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14156 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14157 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14158 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14159 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14160 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14161 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14162 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14163 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14164 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14165 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14166 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14167 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14168 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14169 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14172 /* Table of V7M psr names. */
14173 static const struct asm_psr v7m_psrs
[] =
14186 {"basepri_max", 18},
14191 /* Table of all shift-in-operand names. */
14192 static const struct asm_shift_name shift_names
[] =
14194 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14195 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14196 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14197 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14198 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14199 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14202 /* Table of all explicit relocation names. */
14204 static struct reloc_entry reloc_names
[] =
14206 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14207 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14208 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14209 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14210 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14211 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14212 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14213 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14214 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14215 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14216 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14220 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14221 static const struct asm_cond conds
[] =
14225 {"cs", 0x2}, {"hs", 0x2},
14226 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14240 static struct asm_barrier_opt barrier_opt_names
[] =
14248 /* Table of ARM-format instructions. */
14250 /* Macros for gluing together operand strings. N.B. In all cases
14251 other than OPS0, the trailing OP_stop comes from default
14252 zero-initialization of the unspecified elements of the array. */
14253 #define OPS0() { OP_stop, }
14254 #define OPS1(a) { OP_##a, }
14255 #define OPS2(a,b) { OP_##a,OP_##b, }
14256 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14257 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14258 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14259 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14261 /* These macros abstract out the exact format of the mnemonic table and
14262 save some repeated characters. */
14264 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14265 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14266 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14267 THUMB_VARIANT, do_##ae, do_##te }
14269 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14270 a T_MNEM_xyz enumerator. */
14271 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14272 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14273 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14274 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14276 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14277 infix after the third character. */
14278 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14279 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14280 THUMB_VARIANT, do_##ae, do_##te }
14281 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14282 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14283 THUMB_VARIANT, do_##ae, do_##te }
14284 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14285 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14286 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14287 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14288 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14289 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14290 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14291 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14293 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14294 appear in the condition table. */
14295 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14296 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14297 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14299 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14300 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14301 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14302 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14303 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14304 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14305 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14306 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14307 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14308 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14309 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14310 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14311 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14312 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14313 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14314 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14315 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14316 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14317 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14318 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14320 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14321 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14322 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14323 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14325 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14326 field is still 0xE. Many of the Thumb variants can be executed
14327 conditionally, so this is checked separately. */
14328 #define TUE(mnem, op, top, nops, ops, ae, te) \
14329 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14330 THUMB_VARIANT, do_##ae, do_##te }
14332 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14333 condition code field. */
14334 #define TUF(mnem, op, top, nops, ops, ae, te) \
14335 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14336 THUMB_VARIANT, do_##ae, do_##te }
14338 /* ARM-only variants of all the above. */
14339 #define CE(mnem, op, nops, ops, ae) \
14340 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14342 #define C3(mnem, op, nops, ops, ae) \
14343 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14345 /* Legacy mnemonics that always have conditional infix after the third
14347 #define CL(mnem, op, nops, ops, ae) \
14348 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14349 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14351 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14352 #define cCE(mnem, op, nops, ops, ae) \
14353 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14355 /* Legacy coprocessor instructions where conditional infix and conditional
14356 suffix are ambiguous. For consistency this includes all FPA instructions,
14357 not just the potentially ambiguous ones. */
14358 #define cCL(mnem, op, nops, ops, ae) \
14359 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14360 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14362 /* Coprocessor, takes either a suffix or a position-3 infix
14363 (for an FPA corner case). */
14364 #define C3E(mnem, op, nops, ops, ae) \
14365 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14366 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14368 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14369 { #m1 #m2 #m3, OPS##nops ops, \
14370 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14371 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14373 #define CM(m1, m2, op, nops, ops, ae) \
14374 xCM_(m1, , m2, op, nops, ops, ae), \
14375 xCM_(m1, eq, m2, op, nops, ops, ae), \
14376 xCM_(m1, ne, m2, op, nops, ops, ae), \
14377 xCM_(m1, cs, m2, op, nops, ops, ae), \
14378 xCM_(m1, hs, m2, op, nops, ops, ae), \
14379 xCM_(m1, cc, m2, op, nops, ops, ae), \
14380 xCM_(m1, ul, m2, op, nops, ops, ae), \
14381 xCM_(m1, lo, m2, op, nops, ops, ae), \
14382 xCM_(m1, mi, m2, op, nops, ops, ae), \
14383 xCM_(m1, pl, m2, op, nops, ops, ae), \
14384 xCM_(m1, vs, m2, op, nops, ops, ae), \
14385 xCM_(m1, vc, m2, op, nops, ops, ae), \
14386 xCM_(m1, hi, m2, op, nops, ops, ae), \
14387 xCM_(m1, ls, m2, op, nops, ops, ae), \
14388 xCM_(m1, ge, m2, op, nops, ops, ae), \
14389 xCM_(m1, lt, m2, op, nops, ops, ae), \
14390 xCM_(m1, gt, m2, op, nops, ops, ae), \
14391 xCM_(m1, le, m2, op, nops, ops, ae), \
14392 xCM_(m1, al, m2, op, nops, ops, ae)
14394 #define UE(mnem, op, nops, ops, ae) \
14395 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14397 #define UF(mnem, op, nops, ops, ae) \
14398 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14400 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14401 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14402 use the same encoding function for each. */
14403 #define NUF(mnem, op, nops, ops, enc) \
14404 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14405 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14407 /* Neon data processing, version which indirects through neon_enc_tab for
14408 the various overloaded versions of opcodes. */
14409 #define nUF(mnem, op, nops, ops, enc) \
14410 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14411 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14413 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14415 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14416 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14417 THUMB_VARIANT, do_##enc, do_##enc }
14419 #define NCE(mnem, op, nops, ops, enc) \
14420 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14422 #define NCEF(mnem, op, nops, ops, enc) \
14423 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14425 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14426 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14427 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14428 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14430 #define nCE(mnem, op, nops, ops, enc) \
14431 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14433 #define nCEF(mnem, op, nops, ops, enc) \
14434 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14438 /* Thumb-only, unconditional. */
14439 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14441 static const struct asm_opcode insns
[] =
14443 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14444 #define THUMB_VARIANT &arm_ext_v4t
14445 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14446 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14447 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14448 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14449 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14450 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14451 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14452 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14453 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14454 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14455 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14456 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14457 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14458 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14459 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14460 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14462 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14463 for setting PSR flag bits. They are obsolete in V6 and do not
14464 have Thumb equivalents. */
14465 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14466 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14467 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14468 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14469 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14470 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14471 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14472 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14473 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14475 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14476 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14477 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14478 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14480 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14481 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14482 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14483 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14485 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14486 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14487 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14488 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14489 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14490 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14492 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14493 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14494 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14495 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14498 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14499 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14500 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14502 /* Thumb-compatibility pseudo ops. */
14503 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14504 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14505 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14506 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14507 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14508 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14509 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14510 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14511 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14512 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14513 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14514 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14516 #undef THUMB_VARIANT
14517 #define THUMB_VARIANT &arm_ext_v6
14518 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14520 /* V1 instructions with no Thumb analogue prior to V6T2. */
14521 #undef THUMB_VARIANT
14522 #define THUMB_VARIANT &arm_ext_v6t2
14523 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14524 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14525 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14526 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14527 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14529 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14530 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14531 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14532 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14534 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14535 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14537 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14538 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14540 /* V1 instructions with no Thumb analogue at all. */
14541 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14542 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14544 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14545 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14546 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14547 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14548 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14549 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14550 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14551 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14554 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
14555 #undef THUMB_VARIANT
14556 #define THUMB_VARIANT &arm_ext_v4t
14557 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14558 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14560 #undef THUMB_VARIANT
14561 #define THUMB_VARIANT &arm_ext_v6t2
14562 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14563 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
14565 /* Generic coprocessor instructions. */
14566 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14567 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14568 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14569 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14570 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14571 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14572 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14575 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
14576 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14577 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14580 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
14581 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
14582 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
14585 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
14586 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14587 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14588 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14589 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14590 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14591 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14592 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14593 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14596 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
14597 #undef THUMB_VARIANT
14598 #define THUMB_VARIANT &arm_ext_v4t
14599 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14600 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14601 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14602 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14603 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14604 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14607 #define ARM_VARIANT &arm_ext_v4t_5
14608 /* ARM Architecture 4T. */
14609 /* Note: bx (and blx) are required on V5, even if the processor does
14610 not support Thumb. */
14611 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
14614 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
14615 #undef THUMB_VARIANT
14616 #define THUMB_VARIANT &arm_ext_v5t
14617 /* Note: blx has 2 variants; the .value coded here is for
14618 BLX(2). Only this variant has conditional execution. */
14619 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
14620 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
14622 #undef THUMB_VARIANT
14623 #define THUMB_VARIANT &arm_ext_v6t2
14624 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
14625 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14626 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14627 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14628 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14629 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14630 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14631 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14634 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
14635 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14636 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14637 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14638 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14640 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14641 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14643 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14644 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14645 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14646 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14648 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14649 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14650 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14651 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14653 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14654 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14656 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14657 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14658 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14659 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14662 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
14663 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
14664 TC3(ldrd
, 00000d0
, e9500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14665 TC3(strd
, 00000f0
, e9400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14667 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14668 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14671 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
14672 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
14675 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
14676 #undef THUMB_VARIANT
14677 #define THUMB_VARIANT &arm_ext_v6
14678 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14679 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14680 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14681 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14682 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14683 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14684 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14685 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14686 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14687 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
14689 #undef THUMB_VARIANT
14690 #define THUMB_VARIANT &arm_ext_v6t2
14691 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
14692 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14693 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14695 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
14696 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
14698 /* ARM V6 not included in V7M (eg. integer SIMD). */
14699 #undef THUMB_VARIANT
14700 #define THUMB_VARIANT &arm_ext_v6_notm
14701 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
14702 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
14703 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
14704 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14705 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14706 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14707 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14708 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14709 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14710 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14711 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14712 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14713 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14714 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14715 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14716 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14717 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14718 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14719 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14720 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14721 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14722 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14723 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14724 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14725 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14726 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14727 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14728 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14729 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14730 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14731 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14732 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14733 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14734 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14735 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14736 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14737 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14738 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14739 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14740 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14741 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
14742 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
14743 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14744 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14745 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
14746 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
14747 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14748 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14749 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14750 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14751 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14752 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14753 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14754 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14755 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14756 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14757 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14758 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14759 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14760 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14761 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14762 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14763 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14764 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14765 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14766 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14767 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14768 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14769 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14770 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14771 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14772 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14773 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14774 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14775 TUF(srsia
, 8cd0500
, e980c000
, 1, (I31w
), srs
, srs
),
14776 UF(srsib
, 9cd0500
, 1, (I31w
), srs
),
14777 UF(srsda
, 84d0500
, 1, (I31w
), srs
),
14778 TUF(srsdb
, 94d0500
, e800c000
, 1, (I31w
), srs
, srs
),
14779 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
14780 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
14781 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
14782 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14783 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14784 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
14787 #define ARM_VARIANT &arm_ext_v6k
14788 #undef THUMB_VARIANT
14789 #define THUMB_VARIANT &arm_ext_v6k
14790 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
14791 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
14792 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
14793 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
14795 #undef THUMB_VARIANT
14796 #define THUMB_VARIANT &arm_ext_v6_notm
14797 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
14798 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
14800 #undef THUMB_VARIANT
14801 #define THUMB_VARIANT &arm_ext_v6t2
14802 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14803 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14804 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14805 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14806 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
14809 #define ARM_VARIANT &arm_ext_v6z
14810 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
14813 #define ARM_VARIANT &arm_ext_v6t2
14814 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
14815 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
14816 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14817 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14819 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14820 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14821 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14822 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
14824 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14825 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14826 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14827 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14829 UT(cbnz
, b900
, 2, (RR
, EXP
), t_czb
),
14830 UT(cbz
, b100
, 2, (RR
, EXP
), t_czb
),
14831 /* ARM does not really have an IT instruction, so always allow it. */
14833 #define ARM_VARIANT &arm_ext_v1
14834 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
14835 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
14836 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
14837 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
14838 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
14839 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
14840 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
14841 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
14842 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
14843 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
14844 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
14845 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
14846 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
14847 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
14848 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
14850 /* Thumb2 only instructions. */
14852 #define ARM_VARIANT NULL
14854 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14855 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14856 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
14857 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
14859 /* Thumb-2 hardware division instructions (R and M profiles only). */
14860 #undef THUMB_VARIANT
14861 #define THUMB_VARIANT &arm_ext_div
14862 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14863 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14865 /* ARM V7 instructions. */
14867 #define ARM_VARIANT &arm_ext_v7
14868 #undef THUMB_VARIANT
14869 #define THUMB_VARIANT &arm_ext_v7
14870 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
14871 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
14872 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
14873 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
14874 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
14877 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
14878 cCE(wfs
, e200110
, 1, (RR
), rd
),
14879 cCE(rfs
, e300110
, 1, (RR
), rd
),
14880 cCE(wfc
, e400110
, 1, (RR
), rd
),
14881 cCE(rfc
, e500110
, 1, (RR
), rd
),
14883 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14884 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14885 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14886 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14888 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14889 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14890 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14891 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14893 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
14894 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
14895 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
14896 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
14897 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
14898 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
14899 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
14900 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
14901 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
14902 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
14903 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
14904 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
14906 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
14907 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
14908 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
14909 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
14910 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
14911 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
14912 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
14913 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
14914 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
14915 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
14916 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
14917 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
14919 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
14920 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
14921 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
14922 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
14923 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
14924 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
14925 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
14926 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
14927 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
14928 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
14929 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
14930 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
14932 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
14933 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
14934 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
14935 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
14936 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
14937 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
14938 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
14939 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
14940 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
14941 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
14942 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
14943 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
14945 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
14946 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
14947 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
14948 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
14949 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
14950 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
14951 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
14952 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
14953 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
14954 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
14955 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
14956 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
14958 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
14959 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
14960 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
14961 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
14962 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
14963 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
14964 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
14965 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
14966 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
14967 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
14968 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
14969 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
14971 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
14972 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
14973 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
14974 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
14975 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
14976 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
14977 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
14978 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
14979 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
14980 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
14981 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
14982 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
14984 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
14985 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
14986 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
14987 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
14988 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
14989 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
14990 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
14991 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
14992 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
14993 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
14994 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
14995 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
14997 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
14998 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
14999 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15000 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15001 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15002 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15003 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15004 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15005 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15006 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15007 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15008 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15010 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15011 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15012 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15013 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15014 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15015 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15016 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15017 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15018 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15019 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15020 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15021 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15023 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15024 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15025 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15026 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15027 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15028 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15029 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15030 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15031 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15032 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15033 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15034 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15036 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15037 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15038 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15039 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15040 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15041 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15042 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15043 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15044 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15045 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15046 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15047 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15049 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15050 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15051 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15052 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15053 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15054 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15055 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15056 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15057 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15058 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15059 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15060 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15062 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15063 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15064 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15065 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15066 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15067 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15068 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15069 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15070 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15071 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15072 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15073 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15075 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15076 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15077 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15078 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15079 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15080 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15081 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15082 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15083 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15084 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15085 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15086 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15088 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15089 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15090 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15091 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15092 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15093 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15094 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15095 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15096 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15097 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15098 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15099 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15101 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15102 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15103 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15104 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15105 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15106 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15107 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15108 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15109 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15110 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15111 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15112 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15114 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15115 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15116 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15117 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15118 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15119 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15120 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15121 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15122 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15123 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15124 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15125 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15127 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15128 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15129 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15130 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15131 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15132 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15133 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15134 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15135 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15136 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15137 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15138 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15140 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15141 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15142 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15143 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15144 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15145 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15146 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15147 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15148 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15149 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15150 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15151 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15153 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15154 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15155 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15156 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15157 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15158 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15159 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15160 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15161 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15162 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15163 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15164 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15166 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15167 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15168 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15169 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15170 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15171 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15172 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15173 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15174 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15175 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15176 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15177 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15179 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15180 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15181 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15182 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15183 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15184 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15185 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15186 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15187 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15188 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15189 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15190 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15192 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15193 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15194 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15195 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15196 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15197 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15198 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15199 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15200 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15201 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15202 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15203 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15205 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15206 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15207 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15208 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15209 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15210 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15211 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15212 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15213 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15214 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15215 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15216 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15218 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15219 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15220 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15221 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15222 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15223 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15224 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15225 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15226 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15227 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15228 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15229 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15231 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15232 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15233 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15234 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15235 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15236 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15237 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15238 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15239 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15240 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15241 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15242 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15244 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15245 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15246 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15247 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15248 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15249 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15250 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15251 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15252 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15253 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15254 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15255 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15257 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15258 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15259 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15260 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15261 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15262 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15263 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15264 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15265 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15266 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15267 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15268 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15270 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15271 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15272 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15273 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15275 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15276 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15277 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15278 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15279 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15280 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15281 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15282 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15283 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15284 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15285 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15286 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15288 /* The implementation of the FIX instruction is broken on some
15289 assemblers, in that it accepts a precision specifier as well as a
15290 rounding specifier, despite the fact that this is meaningless.
15291 To be more compatible, we accept it as well, though of course it
15292 does not set any bits. */
15293 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15294 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15295 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15296 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15297 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15298 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15299 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15300 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15301 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15302 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15303 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15304 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15305 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15307 /* Instructions that were new with the real FPA, call them V2. */
15309 #define ARM_VARIANT &fpu_fpa_ext_v2
15310 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15311 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15312 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15313 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15314 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15315 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15318 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15319 /* Moves and type conversions. */
15320 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15321 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15322 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15323 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15324 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15325 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15326 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15327 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15328 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15329 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15330 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15331 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15333 /* Memory operations. */
15334 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15335 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15336 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15337 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15338 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15339 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15340 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15341 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15342 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15343 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15344 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15345 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15346 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15347 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15348 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15349 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15350 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15351 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15353 /* Monadic operations. */
15354 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15355 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15356 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15358 /* Dyadic operations. */
15359 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15360 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15361 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15362 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15363 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15364 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15365 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15366 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15367 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15370 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15371 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15372 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15373 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15376 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15377 /* Moves and type conversions. */
15378 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15379 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15380 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15381 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15382 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15383 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15384 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15385 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15386 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15387 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15388 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15389 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15390 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15392 /* Memory operations. */
15393 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15394 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15395 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15396 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15397 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15398 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15399 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15400 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15401 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15402 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15404 /* Monadic operations. */
15405 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15406 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15407 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15409 /* Dyadic operations. */
15410 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15411 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15412 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15413 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15414 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15415 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15416 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15417 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15418 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15421 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15422 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15423 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15424 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15427 #define ARM_VARIANT &fpu_vfp_ext_v2
15428 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15429 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15430 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15431 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15433 /* Instructions which may belong to either the Neon or VFP instruction sets.
15434 Individual encoder functions perform additional architecture checks. */
15436 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15437 #undef THUMB_VARIANT
15438 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15439 /* These mnemonics are unique to VFP. */
15440 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15441 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15442 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15443 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15444 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15445 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15446 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15447 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15448 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15449 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15451 /* Mnemonics shared by Neon and VFP. */
15452 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15453 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15454 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15456 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15457 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15459 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15460 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15462 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15463 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15464 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15465 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15466 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15467 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15468 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15469 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15471 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15473 /* NOTE: All VMOV encoding is special-cased! */
15474 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15475 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15477 #undef THUMB_VARIANT
15478 #define THUMB_VARIANT &fpu_neon_ext_v1
15480 #define ARM_VARIANT &fpu_neon_ext_v1
15481 /* Data processing with three registers of the same length. */
15482 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15483 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15484 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15485 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15486 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15487 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15488 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15489 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15490 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15491 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15492 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15493 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15494 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15495 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15496 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15497 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15498 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15499 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15500 /* If not immediate, fall back to neon_dyadic_i64_su.
15501 shl_imm should accept I8 I16 I32 I64,
15502 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15503 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15504 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15505 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15506 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15507 /* Logic ops, types optional & ignored. */
15508 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15509 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15510 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15511 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15512 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15513 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15514 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15515 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15516 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15517 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15518 /* Bitfield ops, untyped. */
15519 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15520 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15521 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15522 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15523 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15524 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15525 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15526 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15527 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15528 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15529 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15530 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15531 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15532 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15533 back to neon_dyadic_if_su. */
15534 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15535 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15536 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15537 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15538 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15539 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15540 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15541 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15542 /* Comparison. Type I8 I16 I32 F32. */
15543 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15544 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15545 /* As above, D registers only. */
15546 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15547 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15548 /* Int and float variants, signedness unimportant. */
15549 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15550 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15551 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
15552 /* Add/sub take types I8 I16 I32 I64 F32. */
15553 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15554 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15555 /* vtst takes sizes 8, 16, 32. */
15556 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
15557 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
15558 /* VMUL takes I8 I16 I32 F32 P8. */
15559 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
15560 /* VQD{R}MULH takes S16 S32. */
15561 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15562 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15563 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15564 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15565 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15566 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15567 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15568 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15569 NUF(vaclt
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15570 NUF(vacltq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15571 NUF(vacle
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15572 NUF(vacleq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15573 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15574 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15575 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15576 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15578 /* Two address, int/float. Types S8 S16 S32 F32. */
15579 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15580 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15582 /* Data processing with two registers and a shift amount. */
15583 /* Right shifts, and variants with rounding.
15584 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
15585 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15586 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15587 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15588 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15589 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15590 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15591 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15592 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15593 /* Shift and insert. Sizes accepted 8 16 32 64. */
15594 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
15595 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
15596 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
15597 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
15598 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
15599 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
15600 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
15601 /* Right shift immediate, saturating & narrowing, with rounding variants.
15602 Types accepted S16 S32 S64 U16 U32 U64. */
15603 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15604 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15605 /* As above, unsigned. Types accepted S16 S32 S64. */
15606 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15607 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15608 /* Right shift narrowing. Types accepted I16 I32 I64. */
15609 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15610 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15611 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
15612 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
15613 /* CVT with optional immediate for fixed-point variant. */
15614 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
15616 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
15617 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
15619 /* Data processing, three registers of different lengths. */
15620 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
15621 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
15622 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15623 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15624 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15625 /* If not scalar, fall back to neon_dyadic_long.
15626 Vector types as above, scalar types S16 S32 U16 U32. */
15627 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15628 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15629 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
15630 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15631 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15632 /* Dyadic, narrowing insns. Types I16 I32 I64. */
15633 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15634 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15635 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15636 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15637 /* Saturating doubling multiplies. Types S16 S32. */
15638 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15639 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15640 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15641 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
15642 S16 S32 U16 U32. */
15643 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
15645 /* Extract. Size 8. */
15646 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I7
), neon_ext
),
15647 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I7
), neon_ext
),
15649 /* Two registers, miscellaneous. */
15650 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
15651 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
15652 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
15653 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
15654 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
15655 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
15656 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
15657 /* Vector replicate. Sizes 8 16 32. */
15658 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
15659 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
15660 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
15661 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
15662 /* VMOVN. Types I16 I32 I64. */
15663 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
15664 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
15665 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
15666 /* VQMOVUN. Types S16 S32 S64. */
15667 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
15668 /* VZIP / VUZP. Sizes 8 16 32. */
15669 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15670 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15671 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15672 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15673 /* VQABS / VQNEG. Types S8 S16 S32. */
15674 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15675 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15676 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15677 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15678 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
15679 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15680 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
15681 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15682 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
15683 /* Reciprocal estimates. Types U32 F32. */
15684 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15685 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
15686 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15687 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
15688 /* VCLS. Types S8 S16 S32. */
15689 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
15690 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
15691 /* VCLZ. Types I8 I16 I32. */
15692 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
15693 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
15694 /* VCNT. Size 8. */
15695 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
15696 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
15697 /* Two address, untyped. */
15698 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
15699 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
15700 /* VTRN. Sizes 8 16 32. */
15701 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
15702 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
15704 /* Table lookup. Size 8. */
15705 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15706 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15708 #undef THUMB_VARIANT
15709 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
15711 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
15712 /* Neon element/structure load/store. */
15713 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15714 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15715 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15716 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15717 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15718 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15719 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15720 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15722 #undef THUMB_VARIANT
15723 #define THUMB_VARIANT &fpu_vfp_ext_v3
15725 #define ARM_VARIANT &fpu_vfp_ext_v3
15726 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
15727 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
15728 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15729 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15730 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15731 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15732 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15733 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15734 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15735 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15736 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15737 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15738 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15739 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15740 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15741 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15742 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15743 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15745 #undef THUMB_VARIANT
15747 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
15748 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15749 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15750 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15751 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15752 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15753 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15754 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
15755 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
15758 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
15759 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
15760 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
15761 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
15762 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
15763 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
15764 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
15765 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
15766 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
15767 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
15768 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15769 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15770 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15771 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15772 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15773 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15774 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15775 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15776 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15777 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
15778 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
15779 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15780 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15781 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15782 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15783 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15784 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15785 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
15786 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
15787 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
15788 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
15789 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
15790 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
15791 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
15792 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
15793 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15794 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15795 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15796 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15797 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15798 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15799 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15800 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15801 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15802 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15803 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15804 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15805 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
15806 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15807 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15808 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15809 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15810 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15811 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15812 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15813 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15814 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15815 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15816 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15817 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15818 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15819 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15820 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15821 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15822 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15823 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15824 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15825 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15826 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15827 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15828 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15829 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15830 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15831 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15832 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15833 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15834 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15835 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15836 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15837 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15838 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15839 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15840 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15841 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15842 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15843 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15844 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15845 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15846 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15847 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
15848 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15849 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15850 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15851 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15852 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15853 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15854 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15855 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15856 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15857 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15858 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15859 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15860 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15861 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15862 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15863 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15864 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15865 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15866 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15867 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15868 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15869 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
15870 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15871 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15872 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15873 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15874 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15875 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15876 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15877 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15878 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15879 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15880 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15881 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15882 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15883 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15884 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15885 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15886 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15887 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15888 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15889 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15890 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15891 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15892 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15893 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15894 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15895 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15896 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15897 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15898 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15899 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15900 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15901 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15902 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15903 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15904 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15905 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15906 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15907 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15908 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15909 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15910 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15911 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15912 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15913 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15914 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15915 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15916 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15917 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15918 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15919 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15920 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
15923 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
15924 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
15925 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
15926 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
15927 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
15928 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
15929 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
15930 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
15931 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
15932 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
15933 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
15934 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
15935 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
15936 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
15937 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
15938 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
15939 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
15940 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
15941 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
15942 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
15943 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
15944 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
15945 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
15946 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
15947 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
15948 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
15949 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
15950 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
15951 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
15952 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
15953 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
15954 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
15955 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
15956 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
15957 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
15958 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
15959 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
15960 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
15961 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
15962 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
15963 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
15964 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
15965 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
15966 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
15967 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
15968 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
15969 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
15970 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
15971 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
15972 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
15973 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
15974 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
15975 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
15976 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
15977 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
15978 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15979 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15980 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15981 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15982 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15983 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15984 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
15985 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
15986 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
15987 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
15988 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15989 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15990 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15991 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15992 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15993 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15994 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15995 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15996 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
15997 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
15998 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
15999 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16002 #undef THUMB_VARIANT
16029 /* MD interface: bits in the object file. */
16031 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16032 for use in the a.out file, and stores them in the array pointed to by buf.
16033 This knows about the endian-ness of the target machine and does
16034 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16035 2 (short) and 4 (long) Floating numbers are put out as a series of
16036 LITTLENUMS (shorts, here at least). */
16039 md_number_to_chars (char * buf
, valueT val
, int n
)
16041 if (target_big_endian
)
16042 number_to_chars_bigendian (buf
, val
, n
);
16044 number_to_chars_littleendian (buf
, val
, n
);
16048 md_chars_to_number (char * buf
, int n
)
16051 unsigned char * where
= (unsigned char *) buf
;
16053 if (target_big_endian
)
16058 result
|= (*where
++ & 255);
16066 result
|= (where
[n
] & 255);
16073 /* MD interface: Sections. */
16075 /* Estimate the size of a frag before relaxing. Assume everything fits in
16079 md_estimate_size_before_relax (fragS
* fragp
,
16080 segT segtype ATTRIBUTE_UNUSED
)
16086 /* Convert a machine dependent frag. */
16089 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16091 unsigned long insn
;
16092 unsigned long old_op
;
16100 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16102 old_op
= bfd_get_16(abfd
, buf
);
16103 if (fragp
->fr_symbol
) {
16104 exp
.X_op
= O_symbol
;
16105 exp
.X_add_symbol
= fragp
->fr_symbol
;
16107 exp
.X_op
= O_constant
;
16109 exp
.X_add_number
= fragp
->fr_offset
;
16110 opcode
= fragp
->fr_subtype
;
16113 case T_MNEM_ldr_pc
:
16114 case T_MNEM_ldr_pc2
:
16115 case T_MNEM_ldr_sp
:
16116 case T_MNEM_str_sp
:
16123 if (fragp
->fr_var
== 4)
16125 insn
= THUMB_OP32(opcode
);
16126 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16128 insn
|= (old_op
& 0x700) << 4;
16132 insn
|= (old_op
& 7) << 12;
16133 insn
|= (old_op
& 0x38) << 13;
16135 insn
|= 0x00000c00;
16136 put_thumb32_insn (buf
, insn
);
16137 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16141 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16143 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16146 if (fragp
->fr_var
== 4)
16148 insn
= THUMB_OP32 (opcode
);
16149 insn
|= (old_op
& 0xf0) << 4;
16150 put_thumb32_insn (buf
, insn
);
16151 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16155 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16156 exp
.X_add_number
-= 4;
16164 if (fragp
->fr_var
== 4)
16166 int r0off
= (opcode
== T_MNEM_mov
16167 || opcode
== T_MNEM_movs
) ? 0 : 8;
16168 insn
= THUMB_OP32 (opcode
);
16169 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16170 insn
|= (old_op
& 0x700) << r0off
;
16171 put_thumb32_insn (buf
, insn
);
16172 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16176 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16181 if (fragp
->fr_var
== 4)
16183 insn
= THUMB_OP32(opcode
);
16184 put_thumb32_insn (buf
, insn
);
16185 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16188 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16192 if (fragp
->fr_var
== 4)
16194 insn
= THUMB_OP32(opcode
);
16195 insn
|= (old_op
& 0xf00) << 14;
16196 put_thumb32_insn (buf
, insn
);
16197 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16200 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16203 case T_MNEM_add_sp
:
16204 case T_MNEM_add_pc
:
16205 case T_MNEM_inc_sp
:
16206 case T_MNEM_dec_sp
:
16207 if (fragp
->fr_var
== 4)
16209 /* ??? Choose between add and addw. */
16210 insn
= THUMB_OP32 (opcode
);
16211 insn
|= (old_op
& 0xf0) << 4;
16212 put_thumb32_insn (buf
, insn
);
16213 if (opcode
== T_MNEM_add_pc
)
16214 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16216 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16219 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16227 if (fragp
->fr_var
== 4)
16229 insn
= THUMB_OP32 (opcode
);
16230 insn
|= (old_op
& 0xf0) << 4;
16231 insn
|= (old_op
& 0xf) << 16;
16232 put_thumb32_insn (buf
, insn
);
16233 if (insn
& (1 << 20))
16234 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16236 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16239 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16245 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16247 fixp
->fx_file
= fragp
->fr_file
;
16248 fixp
->fx_line
= fragp
->fr_line
;
16249 fragp
->fr_fix
+= fragp
->fr_var
;
16252 /* Return the size of a relaxable immediate operand instruction.
16253 SHIFT and SIZE specify the form of the allowable immediate. */
16255 relax_immediate (fragS
*fragp
, int size
, int shift
)
16261 /* ??? Should be able to do better than this. */
16262 if (fragp
->fr_symbol
)
16265 low
= (1 << shift
) - 1;
16266 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16267 offset
= fragp
->fr_offset
;
16268 /* Force misaligned offsets to 32-bit variant. */
16271 if (offset
& ~mask
)
16276 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16279 relax_adr (fragS
*fragp
, asection
*sec
)
16284 /* Assume worst case for symbols not known to be in the same section. */
16285 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16286 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16289 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16290 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16291 addr
= (addr
+ 4) & ~3;
16292 /* Fix the insn as the 4-byte version if the target address is not
16293 sufficiently aligned. This is prevents an infinite loop when two
16294 instructions have contradictory range/alignment requirements. */
16298 if (val
< 0 || val
> 1020)
16303 /* Return the size of a relaxable add/sub immediate instruction. */
16305 relax_addsub (fragS
*fragp
, asection
*sec
)
16310 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16311 op
= bfd_get_16(sec
->owner
, buf
);
16312 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16313 return relax_immediate (fragp
, 8, 0);
16315 return relax_immediate (fragp
, 3, 0);
16319 /* Return the size of a relaxable branch instruction. BITS is the
16320 size of the offset field in the narrow instruction. */
16323 relax_branch (fragS
*fragp
, asection
*sec
, int bits
)
16329 /* Assume worst case for symbols not known to be in the same section. */
16330 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16331 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16334 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16335 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16338 /* Offset is a signed value *2 */
16340 if (val
>= limit
|| val
< -limit
)
16346 /* Relax a machine dependent frag. This returns the amount by which
16347 the current size of the frag should change. */
16350 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
16355 oldsize
= fragp
->fr_var
;
16356 switch (fragp
->fr_subtype
)
16358 case T_MNEM_ldr_pc2
:
16359 newsize
= relax_adr(fragp
, sec
);
16361 case T_MNEM_ldr_pc
:
16362 case T_MNEM_ldr_sp
:
16363 case T_MNEM_str_sp
:
16364 newsize
= relax_immediate(fragp
, 8, 2);
16368 newsize
= relax_immediate(fragp
, 5, 2);
16372 newsize
= relax_immediate(fragp
, 5, 1);
16376 newsize
= relax_immediate(fragp
, 5, 0);
16379 newsize
= relax_adr(fragp
, sec
);
16385 newsize
= relax_immediate(fragp
, 8, 0);
16388 newsize
= relax_branch(fragp
, sec
, 11);
16391 newsize
= relax_branch(fragp
, sec
, 8);
16393 case T_MNEM_add_sp
:
16394 case T_MNEM_add_pc
:
16395 newsize
= relax_immediate (fragp
, 8, 2);
16397 case T_MNEM_inc_sp
:
16398 case T_MNEM_dec_sp
:
16399 newsize
= relax_immediate (fragp
, 7, 2);
16405 newsize
= relax_addsub (fragp
, sec
);
16412 fragp
->fr_var
= -newsize
;
16413 md_convert_frag (sec
->owner
, sec
, fragp
);
16415 return -(newsize
+ oldsize
);
16417 fragp
->fr_var
= newsize
;
16418 return newsize
- oldsize
;
16421 /* Round up a section size to the appropriate boundary. */
16424 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16427 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16428 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
16430 /* For a.out, force the section size to be aligned. If we don't do
16431 this, BFD will align it for us, but it will not write out the
16432 final bytes of the section. This may be a bug in BFD, but it is
16433 easier to fix it here since that is how the other a.out targets
16437 align
= bfd_get_section_alignment (stdoutput
, segment
);
16438 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
16445 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16446 of an rs_align_code fragment. */
16449 arm_handle_align (fragS
* fragP
)
16451 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16452 static char const thumb_noop
[2] = { 0xc0, 0x46 };
16453 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16454 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
16456 int bytes
, fix
, noop_size
;
16460 if (fragP
->fr_type
!= rs_align_code
)
16463 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
16464 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
16467 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16468 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
16470 if (fragP
->tc_frag_data
)
16472 if (target_big_endian
)
16473 noop
= thumb_bigend_noop
;
16476 noop_size
= sizeof (thumb_noop
);
16480 if (target_big_endian
)
16481 noop
= arm_bigend_noop
;
16484 noop_size
= sizeof (arm_noop
);
16487 if (bytes
& (noop_size
- 1))
16489 fix
= bytes
& (noop_size
- 1);
16490 memset (p
, 0, fix
);
16495 while (bytes
>= noop_size
)
16497 memcpy (p
, noop
, noop_size
);
16499 bytes
-= noop_size
;
16503 fragP
->fr_fix
+= fix
;
16504 fragP
->fr_var
= noop_size
;
16507 /* Called from md_do_align. Used to create an alignment
16508 frag in a code section. */
16511 arm_frag_align_code (int n
, int max
)
16515 /* We assume that there will never be a requirement
16516 to support alignments greater than 32 bytes. */
16517 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16518 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
16520 p
= frag_var (rs_align_code
,
16521 MAX_MEM_FOR_RS_ALIGN_CODE
,
16523 (relax_substateT
) max
,
16530 /* Perform target specific initialisation of a frag. */
16533 arm_init_frag (fragS
* fragP
)
16535 /* Record whether this frag is in an ARM or a THUMB area. */
16536 fragP
->tc_frag_data
= thumb_mode
;
16540 /* When we change sections we need to issue a new mapping symbol. */
16543 arm_elf_change_section (void)
16546 segment_info_type
*seginfo
;
16548 /* Link an unlinked unwind index table section to the .text section. */
16549 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
16550 && elf_linked_to_section (now_seg
) == NULL
)
16551 elf_linked_to_section (now_seg
) = text_section
;
16553 if (!SEG_NORMAL (now_seg
))
16556 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
16558 /* We can ignore sections that only contain debug info. */
16559 if ((flags
& SEC_ALLOC
) == 0)
16562 seginfo
= seg_info (now_seg
);
16563 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
16564 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
16568 arm_elf_section_type (const char * str
, size_t len
)
16570 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
16571 return SHT_ARM_EXIDX
;
16576 /* Code to deal with unwinding tables. */
16578 static void add_unwind_adjustsp (offsetT
);
16580 /* Cenerate and deferred unwind frame offset. */
16583 flush_pending_unwind (void)
16587 offset
= unwind
.pending_offset
;
16588 unwind
.pending_offset
= 0;
16590 add_unwind_adjustsp (offset
);
16593 /* Add an opcode to this list for this function. Two-byte opcodes should
16594 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
16598 add_unwind_opcode (valueT op
, int length
)
16600 /* Add any deferred stack adjustment. */
16601 if (unwind
.pending_offset
)
16602 flush_pending_unwind ();
16604 unwind
.sp_restored
= 0;
16606 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
16608 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
16609 if (unwind
.opcodes
)
16610 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
16611 unwind
.opcode_alloc
);
16613 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
16618 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
16620 unwind
.opcode_count
++;
16624 /* Add unwind opcodes to adjust the stack pointer. */
16627 add_unwind_adjustsp (offsetT offset
)
16631 if (offset
> 0x200)
16633 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
16638 /* Long form: 0xb2, uleb128. */
16639 /* This might not fit in a word so add the individual bytes,
16640 remembering the list is built in reverse order. */
16641 o
= (valueT
) ((offset
- 0x204) >> 2);
16643 add_unwind_opcode (0, 1);
16645 /* Calculate the uleb128 encoding of the offset. */
16649 bytes
[n
] = o
& 0x7f;
16655 /* Add the insn. */
16657 add_unwind_opcode (bytes
[n
- 1], 1);
16658 add_unwind_opcode (0xb2, 1);
16660 else if (offset
> 0x100)
16662 /* Two short opcodes. */
16663 add_unwind_opcode (0x3f, 1);
16664 op
= (offset
- 0x104) >> 2;
16665 add_unwind_opcode (op
, 1);
16667 else if (offset
> 0)
16669 /* Short opcode. */
16670 op
= (offset
- 4) >> 2;
16671 add_unwind_opcode (op
, 1);
16673 else if (offset
< 0)
16676 while (offset
> 0x100)
16678 add_unwind_opcode (0x7f, 1);
16681 op
= ((offset
- 4) >> 2) | 0x40;
16682 add_unwind_opcode (op
, 1);
16686 /* Finish the list of unwind opcodes for this function. */
16688 finish_unwind_opcodes (void)
16692 if (unwind
.fp_used
)
16694 /* Adjust sp as necessary. */
16695 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
16696 flush_pending_unwind ();
16698 /* After restoring sp from the frame pointer. */
16699 op
= 0x90 | unwind
.fp_reg
;
16700 add_unwind_opcode (op
, 1);
16703 flush_pending_unwind ();
16707 /* Start an exception table entry. If idx is nonzero this is an index table
16711 start_unwind_section (const segT text_seg
, int idx
)
16713 const char * text_name
;
16714 const char * prefix
;
16715 const char * prefix_once
;
16716 const char * group_name
;
16720 size_t sec_name_len
;
16727 prefix
= ELF_STRING_ARM_unwind
;
16728 prefix_once
= ELF_STRING_ARM_unwind_once
;
16729 type
= SHT_ARM_EXIDX
;
16733 prefix
= ELF_STRING_ARM_unwind_info
;
16734 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
16735 type
= SHT_PROGBITS
;
16738 text_name
= segment_name (text_seg
);
16739 if (streq (text_name
, ".text"))
16742 if (strncmp (text_name
, ".gnu.linkonce.t.",
16743 strlen (".gnu.linkonce.t.")) == 0)
16745 prefix
= prefix_once
;
16746 text_name
+= strlen (".gnu.linkonce.t.");
16749 prefix_len
= strlen (prefix
);
16750 text_len
= strlen (text_name
);
16751 sec_name_len
= prefix_len
+ text_len
;
16752 sec_name
= xmalloc (sec_name_len
+ 1);
16753 memcpy (sec_name
, prefix
, prefix_len
);
16754 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
16755 sec_name
[prefix_len
+ text_len
] = '\0';
16761 /* Handle COMDAT group. */
16762 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
16764 group_name
= elf_group_name (text_seg
);
16765 if (group_name
== NULL
)
16767 as_bad ("Group section `%s' has no group signature",
16768 segment_name (text_seg
));
16769 ignore_rest_of_line ();
16772 flags
|= SHF_GROUP
;
16776 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
16778 /* Set the setion link for index tables. */
16780 elf_linked_to_section (now_seg
) = text_seg
;
16784 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
16785 personality routine data. Returns zero, or the index table value for
16786 and inline entry. */
16789 create_unwind_entry (int have_data
)
16794 /* The current word of data. */
16796 /* The number of bytes left in this word. */
16799 finish_unwind_opcodes ();
16801 /* Remember the current text section. */
16802 unwind
.saved_seg
= now_seg
;
16803 unwind
.saved_subseg
= now_subseg
;
16805 start_unwind_section (now_seg
, 0);
16807 if (unwind
.personality_routine
== NULL
)
16809 if (unwind
.personality_index
== -2)
16812 as_bad (_("handerdata in cantunwind frame"));
16813 return 1; /* EXIDX_CANTUNWIND. */
16816 /* Use a default personality routine if none is specified. */
16817 if (unwind
.personality_index
== -1)
16819 if (unwind
.opcode_count
> 3)
16820 unwind
.personality_index
= 1;
16822 unwind
.personality_index
= 0;
16825 /* Space for the personality routine entry. */
16826 if (unwind
.personality_index
== 0)
16828 if (unwind
.opcode_count
> 3)
16829 as_bad (_("too many unwind opcodes for personality routine 0"));
16833 /* All the data is inline in the index table. */
16836 while (unwind
.opcode_count
> 0)
16838 unwind
.opcode_count
--;
16839 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
16843 /* Pad with "finish" opcodes. */
16845 data
= (data
<< 8) | 0xb0;
16852 /* We get two opcodes "free" in the first word. */
16853 size
= unwind
.opcode_count
- 2;
16856 /* An extra byte is required for the opcode count. */
16857 size
= unwind
.opcode_count
+ 1;
16859 size
= (size
+ 3) >> 2;
16861 as_bad (_("too many unwind opcodes"));
16863 frag_align (2, 0, 0);
16864 record_alignment (now_seg
, 2);
16865 unwind
.table_entry
= expr_build_dot ();
16867 /* Allocate the table entry. */
16868 ptr
= frag_more ((size
<< 2) + 4);
16869 where
= frag_now_fix () - ((size
<< 2) + 4);
16871 switch (unwind
.personality_index
)
16874 /* ??? Should this be a PLT generating relocation? */
16875 /* Custom personality routine. */
16876 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
16877 BFD_RELOC_ARM_PREL31
);
16882 /* Set the first byte to the number of additional words. */
16887 /* ABI defined personality routines. */
16889 /* Three opcodes bytes are packed into the first word. */
16896 /* The size and first two opcode bytes go in the first word. */
16897 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
16902 /* Should never happen. */
16906 /* Pack the opcodes into words (MSB first), reversing the list at the same
16908 while (unwind
.opcode_count
> 0)
16912 md_number_to_chars (ptr
, data
, 4);
16917 unwind
.opcode_count
--;
16919 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
16922 /* Finish off the last word. */
16925 /* Pad with "finish" opcodes. */
16927 data
= (data
<< 8) | 0xb0;
16929 md_number_to_chars (ptr
, data
, 4);
16934 /* Add an empty descriptor if there is no user-specified data. */
16935 ptr
= frag_more (4);
16936 md_number_to_chars (ptr
, 0, 4);
16943 /* Initialize the DWARF-2 unwind information for this procedure. */
16946 tc_arm_frame_initial_instructions (void)
16948 cfi_add_CFA_def_cfa (REG_SP
, 0);
16950 #endif /* OBJ_ELF */
16952 /* Convert REGNAME to a DWARF-2 register number. */
16955 tc_arm_regname_to_dw2regnum (char *regname
)
16957 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
16967 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
16971 expr
.X_op
= O_secrel
;
16972 expr
.X_add_symbol
= symbol
;
16973 expr
.X_add_number
= 0;
16974 emit_expr (&expr
, size
);
16978 /* MD interface: Symbol and relocation handling. */
16980 /* Return the address within the segment that a PC-relative fixup is
16981 relative to. For ARM, PC-relative fixups applied to instructions
16982 are generally relative to the location of the fixup plus 8 bytes.
16983 Thumb branches are offset by 4, and Thumb loads relative to PC
16984 require special handling. */
16987 md_pcrel_from_section (fixS
* fixP
, segT seg
)
16989 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
16991 /* If this is pc-relative and we are going to emit a relocation
16992 then we just want to put out any pipeline compensation that the linker
16993 will need. Otherwise we want to use the calculated base.
16994 For WinCE we skip the bias for externals as well, since this
16995 is how the MS ARM-CE assembler behaves and we want to be compatible. */
16997 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
16998 || (arm_force_relocation (fixP
)
17000 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17005 switch (fixP
->fx_r_type
)
17007 /* PC relative addressing on the Thumb is slightly odd as the
17008 bottom two bits of the PC are forced to zero for the
17009 calculation. This happens *after* application of the
17010 pipeline offset. However, Thumb adrl already adjusts for
17011 this, so we need not do it again. */
17012 case BFD_RELOC_ARM_THUMB_ADD
:
17015 case BFD_RELOC_ARM_THUMB_OFFSET
:
17016 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17017 case BFD_RELOC_ARM_T32_ADD_PC12
:
17018 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17019 return (base
+ 4) & ~3;
17021 /* Thumb branches are simply offset by +4. */
17022 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17023 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17024 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17025 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17026 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17027 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17028 case BFD_RELOC_THUMB_PCREL_BLX
:
17031 /* ARM mode branches are offset by +8. However, the Windows CE
17032 loader expects the relocation not to take this into account. */
17033 case BFD_RELOC_ARM_PCREL_BRANCH
:
17034 case BFD_RELOC_ARM_PCREL_CALL
:
17035 case BFD_RELOC_ARM_PCREL_JUMP
:
17036 case BFD_RELOC_ARM_PCREL_BLX
:
17037 case BFD_RELOC_ARM_PLT32
:
17039 /* When handling fixups immediately, because we have already
17040 discovered the value of a symbol, or the address of the frag involved
17041 we must account for the offset by +8, as the OS loader will never see the reloc.
17042 see fixup_segment() in write.c
17043 The S_IS_EXTERNAL test handles the case of global symbols.
17044 Those need the calculated base, not just the pipe compensation the linker will need. */
17046 && fixP
->fx_addsy
!= NULL
17047 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17048 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17055 /* ARM mode loads relative to PC are also offset by +8. Unlike
17056 branches, the Windows CE loader *does* expect the relocation
17057 to take this into account. */
17058 case BFD_RELOC_ARM_OFFSET_IMM
:
17059 case BFD_RELOC_ARM_OFFSET_IMM8
:
17060 case BFD_RELOC_ARM_HWLITERAL
:
17061 case BFD_RELOC_ARM_LITERAL
:
17062 case BFD_RELOC_ARM_CP_OFF_IMM
:
17066 /* Other PC-relative relocations are un-offset. */
17072 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17073 Otherwise we have no need to default values of symbols. */
17076 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17079 if (name
[0] == '_' && name
[1] == 'G'
17080 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17084 if (symbol_find (name
))
17085 as_bad ("GOT already in the symbol table");
17087 GOT_symbol
= symbol_new (name
, undefined_section
,
17088 (valueT
) 0, & zero_address_frag
);
17098 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17099 computed as two separate immediate values, added together. We
17100 already know that this value cannot be computed by just one ARM
17103 static unsigned int
17104 validate_immediate_twopart (unsigned int val
,
17105 unsigned int * highpart
)
17110 for (i
= 0; i
< 32; i
+= 2)
17111 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17117 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17119 else if (a
& 0xff0000)
17121 if (a
& 0xff000000)
17123 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17127 assert (a
& 0xff000000);
17128 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17131 return (a
& 0xff) | (i
<< 7);
17138 validate_offset_imm (unsigned int val
, int hwse
)
17140 if ((hwse
&& val
> 255) || val
> 4095)
17145 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17146 negative immediate constant by altering the instruction. A bit of
17151 by inverting the second operand, and
17154 by negating the second operand. */
17157 negate_data_op (unsigned long * instruction
,
17158 unsigned long value
)
17161 unsigned long negated
, inverted
;
17163 negated
= encode_arm_immediate (-value
);
17164 inverted
= encode_arm_immediate (~value
);
17166 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17169 /* First negates. */
17170 case OPCODE_SUB
: /* ADD <-> SUB */
17171 new_inst
= OPCODE_ADD
;
17176 new_inst
= OPCODE_SUB
;
17180 case OPCODE_CMP
: /* CMP <-> CMN */
17181 new_inst
= OPCODE_CMN
;
17186 new_inst
= OPCODE_CMP
;
17190 /* Now Inverted ops. */
17191 case OPCODE_MOV
: /* MOV <-> MVN */
17192 new_inst
= OPCODE_MVN
;
17197 new_inst
= OPCODE_MOV
;
17201 case OPCODE_AND
: /* AND <-> BIC */
17202 new_inst
= OPCODE_BIC
;
17207 new_inst
= OPCODE_AND
;
17211 case OPCODE_ADC
: /* ADC <-> SBC */
17212 new_inst
= OPCODE_SBC
;
17217 new_inst
= OPCODE_ADC
;
17221 /* We cannot do anything. */
17226 if (value
== (unsigned) FAIL
)
17229 *instruction
&= OPCODE_MASK
;
17230 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17234 /* Like negate_data_op, but for Thumb-2. */
17236 static unsigned int
17237 thumb32_negate_data_op (offsetT
*instruction
, offsetT value
)
17241 offsetT negated
, inverted
;
17243 negated
= encode_thumb32_immediate (-value
);
17244 inverted
= encode_thumb32_immediate (~value
);
17246 rd
= (*instruction
>> 8) & 0xf;
17247 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17250 /* ADD <-> SUB. Includes CMP <-> CMN. */
17251 case T2_OPCODE_SUB
:
17252 new_inst
= T2_OPCODE_ADD
;
17256 case T2_OPCODE_ADD
:
17257 new_inst
= T2_OPCODE_SUB
;
17261 /* ORR <-> ORN. Includes MOV <-> MVN. */
17262 case T2_OPCODE_ORR
:
17263 new_inst
= T2_OPCODE_ORN
;
17267 case T2_OPCODE_ORN
:
17268 new_inst
= T2_OPCODE_ORR
;
17272 /* AND <-> BIC. TST has no inverted equivalent. */
17273 case T2_OPCODE_AND
:
17274 new_inst
= T2_OPCODE_BIC
;
17281 case T2_OPCODE_BIC
:
17282 new_inst
= T2_OPCODE_AND
;
17287 case T2_OPCODE_ADC
:
17288 new_inst
= T2_OPCODE_SBC
;
17292 case T2_OPCODE_SBC
:
17293 new_inst
= T2_OPCODE_ADC
;
17297 /* We cannot do anything. */
17305 *instruction
&= T2_OPCODE_MASK
;
17306 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17310 /* Read a 32-bit thumb instruction from buf. */
17311 static unsigned long
17312 get_thumb32_insn (char * buf
)
17314 unsigned long insn
;
17315 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17316 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17322 /* We usually want to set the low bit on the address of thumb function
17323 symbols. In particular .word foo - . should have the low bit set.
17324 Generic code tries to fold the difference of two symbols to
17325 a constant. Prevent this and force a relocation when the first symbols
17326 is a thumb function. */
17328 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17330 if (op
== O_subtract
17331 && l
->X_op
== O_symbol
17332 && r
->X_op
== O_symbol
17333 && THUMB_IS_FUNC (l
->X_add_symbol
))
17335 l
->X_op
= O_subtract
;
17336 l
->X_op_symbol
= r
->X_add_symbol
;
17337 l
->X_add_number
-= r
->X_add_number
;
17340 /* Process as normal. */
17345 md_apply_fix (fixS
* fixP
,
17349 offsetT value
= * valP
;
17351 unsigned int newimm
;
17352 unsigned long temp
;
17354 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17356 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17358 /* Note whether this will delete the relocation. */
17360 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17363 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17364 consistency with the behavior on 32-bit hosts. Remember value
17366 value
&= 0xffffffff;
17367 value
^= 0x80000000;
17368 value
-= 0x80000000;
17371 fixP
->fx_addnumber
= value
;
17373 /* Same treatment for fixP->fx_offset. */
17374 fixP
->fx_offset
&= 0xffffffff;
17375 fixP
->fx_offset
^= 0x80000000;
17376 fixP
->fx_offset
-= 0x80000000;
17378 switch (fixP
->fx_r_type
)
17380 case BFD_RELOC_NONE
:
17381 /* This will need to go in the object file. */
17385 case BFD_RELOC_ARM_IMMEDIATE
:
17386 /* We claim that this fixup has been processed here,
17387 even if in fact we generate an error because we do
17388 not have a reloc for it, so tc_gen_reloc will reject it. */
17392 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17394 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17395 _("undefined symbol %s used as an immediate value"),
17396 S_GET_NAME (fixP
->fx_addsy
));
17400 newimm
= encode_arm_immediate (value
);
17401 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17403 /* If the instruction will fail, see if we can fix things up by
17404 changing the opcode. */
17405 if (newimm
== (unsigned int) FAIL
17406 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17408 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17409 _("invalid constant (%lx) after fixup"),
17410 (unsigned long) value
);
17414 newimm
|= (temp
& 0xfffff000);
17415 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17418 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17420 unsigned int highpart
= 0;
17421 unsigned int newinsn
= 0xe1a00000; /* nop. */
17423 newimm
= encode_arm_immediate (value
);
17424 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17426 /* If the instruction will fail, see if we can fix things up by
17427 changing the opcode. */
17428 if (newimm
== (unsigned int) FAIL
17429 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17431 /* No ? OK - try using two ADD instructions to generate
17433 newimm
= validate_immediate_twopart (value
, & highpart
);
17435 /* Yes - then make sure that the second instruction is
17437 if (newimm
!= (unsigned int) FAIL
)
17439 /* Still No ? Try using a negated value. */
17440 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
17441 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
17442 /* Otherwise - give up. */
17445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17446 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17451 /* Replace the first operand in the 2nd instruction (which
17452 is the PC) with the destination register. We have
17453 already added in the PC in the first instruction and we
17454 do not want to do it again. */
17455 newinsn
&= ~ 0xf0000;
17456 newinsn
|= ((newinsn
& 0x0f000) << 4);
17459 newimm
|= (temp
& 0xfffff000);
17460 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17462 highpart
|= (newinsn
& 0xfffff000);
17463 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
17467 case BFD_RELOC_ARM_OFFSET_IMM
:
17468 if (!fixP
->fx_done
&& seg
->use_rela_p
)
17471 case BFD_RELOC_ARM_LITERAL
:
17477 if (validate_offset_imm (value
, 0) == FAIL
)
17479 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
17480 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17481 _("invalid literal constant: pool needs to be closer"));
17483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17484 _("bad immediate value for offset (%ld)"),
17489 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17490 newval
&= 0xff7ff000;
17491 newval
|= value
| (sign
? INDEX_UP
: 0);
17492 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17495 case BFD_RELOC_ARM_OFFSET_IMM8
:
17496 case BFD_RELOC_ARM_HWLITERAL
:
17502 if (validate_offset_imm (value
, 1) == FAIL
)
17504 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
17505 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17506 _("invalid literal constant: pool needs to be closer"));
17508 as_bad (_("bad immediate value for half-word offset (%ld)"),
17513 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17514 newval
&= 0xff7ff0f0;
17515 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
17516 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17519 case BFD_RELOC_ARM_T32_OFFSET_U8
:
17520 if (value
< 0 || value
> 1020 || value
% 4 != 0)
17521 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17522 _("bad immediate value for offset (%ld)"), (long) value
);
17525 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
17527 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
17530 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17531 /* This is a complicated relocation used for all varieties of Thumb32
17532 load/store instruction with immediate offset:
17534 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
17535 *4, optional writeback(W)
17536 (doubleword load/store)
17538 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
17539 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
17540 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
17541 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
17542 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
17544 Uppercase letters indicate bits that are already encoded at
17545 this point. Lowercase letters are our problem. For the
17546 second block of instructions, the secondary opcode nybble
17547 (bits 8..11) is present, and bit 23 is zero, even if this is
17548 a PC-relative operation. */
17549 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17551 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
17553 if ((newval
& 0xf0000000) == 0xe0000000)
17555 /* Doubleword load/store: 8-bit offset, scaled by 4. */
17557 newval
|= (1 << 23);
17560 if (value
% 4 != 0)
17562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17563 _("offset not a multiple of 4"));
17569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17570 _("offset out of range"));
17575 else if ((newval
& 0x000f0000) == 0x000f0000)
17577 /* PC-relative, 12-bit offset. */
17579 newval
|= (1 << 23);
17584 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17585 _("offset out of range"));
17590 else if ((newval
& 0x00000100) == 0x00000100)
17592 /* Writeback: 8-bit, +/- offset. */
17594 newval
|= (1 << 9);
17599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17600 _("offset out of range"));
17605 else if ((newval
& 0x00000f00) == 0x00000e00)
17607 /* T-instruction: positive 8-bit offset. */
17608 if (value
< 0 || value
> 0xff)
17610 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17611 _("offset out of range"));
17619 /* Positive 12-bit or negative 8-bit offset. */
17623 newval
|= (1 << 23);
17633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17634 _("offset out of range"));
17641 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
17642 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
17645 case BFD_RELOC_ARM_SHIFT_IMM
:
17646 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17647 if (((unsigned long) value
) > 32
17649 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
17651 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17652 _("shift expression is too large"));
17657 /* Shifts of zero must be done as lsl. */
17659 else if (value
== 32)
17661 newval
&= 0xfffff07f;
17662 newval
|= (value
& 0x1f) << 7;
17663 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17666 case BFD_RELOC_ARM_T32_IMMEDIATE
:
17667 case BFD_RELOC_ARM_T32_ADD_IMM
:
17668 case BFD_RELOC_ARM_T32_IMM12
:
17669 case BFD_RELOC_ARM_T32_ADD_PC12
:
17670 /* We claim that this fixup has been processed here,
17671 even if in fact we generate an error because we do
17672 not have a reloc for it, so tc_gen_reloc will reject it. */
17676 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17678 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17679 _("undefined symbol %s used as an immediate value"),
17680 S_GET_NAME (fixP
->fx_addsy
));
17684 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17686 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
17689 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
17690 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
17692 newimm
= encode_thumb32_immediate (value
);
17693 if (newimm
== (unsigned int) FAIL
)
17694 newimm
= thumb32_negate_data_op (&newval
, value
);
17696 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
17697 && newimm
== (unsigned int) FAIL
)
17699 /* Turn add/sum into addw/subw. */
17700 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
17701 newval
= (newval
& 0xfeffffff) | 0x02000000;
17703 /* 12 bit immediate for addw/subw. */
17707 newval
^= 0x00a00000;
17710 newimm
= (unsigned int) FAIL
;
17715 if (newimm
== (unsigned int)FAIL
)
17717 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17718 _("invalid constant (%lx) after fixup"),
17719 (unsigned long) value
);
17723 newval
|= (newimm
& 0x800) << 15;
17724 newval
|= (newimm
& 0x700) << 4;
17725 newval
|= (newimm
& 0x0ff);
17727 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
17728 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
17731 case BFD_RELOC_ARM_SMC
:
17732 if (((unsigned long) value
) > 0xffff)
17733 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17734 _("invalid smc expression"));
17735 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17736 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
17737 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17740 case BFD_RELOC_ARM_SWI
:
17741 if (fixP
->tc_fix_data
!= 0)
17743 if (((unsigned long) value
) > 0xff)
17744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17745 _("invalid swi expression"));
17746 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17748 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17752 if (((unsigned long) value
) > 0x00ffffff)
17753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17754 _("invalid swi expression"));
17755 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17757 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17761 case BFD_RELOC_ARM_MULTI
:
17762 if (((unsigned long) value
) > 0xffff)
17763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17764 _("invalid expression in load/store multiple"));
17765 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
17766 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17770 case BFD_RELOC_ARM_PCREL_CALL
:
17771 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17772 if ((newval
& 0xf0000000) == 0xf0000000)
17776 goto arm_branch_common
;
17778 case BFD_RELOC_ARM_PCREL_JUMP
:
17779 case BFD_RELOC_ARM_PLT32
:
17781 case BFD_RELOC_ARM_PCREL_BRANCH
:
17783 goto arm_branch_common
;
17785 case BFD_RELOC_ARM_PCREL_BLX
:
17788 /* We are going to store value (shifted right by two) in the
17789 instruction, in a 24 bit, signed field. Bits 26 through 32 either
17790 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
17791 also be be clear. */
17793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17794 _("misaligned branch destination"));
17795 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
17796 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
17797 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17798 _("branch out of range"));
17800 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17802 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17803 newval
|= (value
>> 2) & 0x00ffffff;
17804 /* Set the H bit on BLX instructions. */
17808 newval
|= 0x01000000;
17810 newval
&= ~0x01000000;
17812 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17816 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CZB */
17817 /* CZB can only branch forward. */
17819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17820 _("branch out of range"));
17822 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17824 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17825 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
17826 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17830 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
17831 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
17832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17833 _("branch out of range"));
17835 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17837 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17838 newval
|= (value
& 0x1ff) >> 1;
17839 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17843 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
17844 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
17845 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17846 _("branch out of range"));
17848 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17850 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17851 newval
|= (value
& 0xfff) >> 1;
17852 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17856 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17857 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
17858 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17859 _("conditional branch out of range"));
17861 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17864 addressT S
, J1
, J2
, lo
, hi
;
17866 S
= (value
& 0x00100000) >> 20;
17867 J2
= (value
& 0x00080000) >> 19;
17868 J1
= (value
& 0x00040000) >> 18;
17869 hi
= (value
& 0x0003f000) >> 12;
17870 lo
= (value
& 0x00000ffe) >> 1;
17872 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17873 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17874 newval
|= (S
<< 10) | hi
;
17875 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
17876 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17877 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17881 case BFD_RELOC_THUMB_PCREL_BLX
:
17882 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17883 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
17884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17885 _("branch out of range"));
17887 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
17888 /* For a BLX instruction, make sure that the relocation is rounded up
17889 to a word boundary. This follows the semantics of the instruction
17890 which specifies that bit 1 of the target address will come from bit
17891 1 of the base address. */
17892 value
= (value
+ 1) & ~ 1;
17894 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17898 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17899 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17900 newval
|= (value
& 0x7fffff) >> 12;
17901 newval2
|= (value
& 0xfff) >> 1;
17902 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17903 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17907 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17908 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
17909 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17910 _("branch out of range"));
17912 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17915 addressT S
, I1
, I2
, lo
, hi
;
17917 S
= (value
& 0x01000000) >> 24;
17918 I1
= (value
& 0x00800000) >> 23;
17919 I2
= (value
& 0x00400000) >> 22;
17920 hi
= (value
& 0x003ff000) >> 12;
17921 lo
= (value
& 0x00000ffe) >> 1;
17926 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17927 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17928 newval
|= (S
<< 10) | hi
;
17929 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
17930 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17931 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17936 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17937 md_number_to_chars (buf
, value
, 1);
17941 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17942 md_number_to_chars (buf
, value
, 2);
17946 case BFD_RELOC_ARM_TLS_GD32
:
17947 case BFD_RELOC_ARM_TLS_LE32
:
17948 case BFD_RELOC_ARM_TLS_IE32
:
17949 case BFD_RELOC_ARM_TLS_LDM32
:
17950 case BFD_RELOC_ARM_TLS_LDO32
:
17951 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
17954 case BFD_RELOC_ARM_GOT32
:
17955 case BFD_RELOC_ARM_GOTOFF
:
17956 case BFD_RELOC_ARM_TARGET2
:
17957 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17958 md_number_to_chars (buf
, 0, 4);
17962 case BFD_RELOC_RVA
:
17964 case BFD_RELOC_ARM_TARGET1
:
17965 case BFD_RELOC_ARM_ROSEGREL32
:
17966 case BFD_RELOC_ARM_SBREL32
:
17967 case BFD_RELOC_32_PCREL
:
17969 case BFD_RELOC_32_SECREL
:
17971 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17973 /* For WinCE we only do this for pcrel fixups. */
17974 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
17976 md_number_to_chars (buf
, value
, 4);
17980 case BFD_RELOC_ARM_PREL31
:
17981 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17983 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
17984 if ((value
^ (value
>> 1)) & 0x40000000)
17986 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17987 _("rel31 relocation overflow"));
17989 newval
|= value
& 0x7fffffff;
17990 md_number_to_chars (buf
, newval
, 4);
17995 case BFD_RELOC_ARM_CP_OFF_IMM
:
17996 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17997 if (value
< -1023 || value
> 1023 || (value
& 3))
17998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17999 _("co-processor offset out of range"));
18004 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18005 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18006 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18008 newval
= get_thumb32_insn (buf
);
18009 newval
&= 0xff7fff00;
18010 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18012 newval
&= ~WRITE_BACK
;
18013 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18014 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18015 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18017 put_thumb32_insn (buf
, newval
);
18020 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18021 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18022 if (value
< -255 || value
> 255)
18023 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18024 _("co-processor offset out of range"));
18026 goto cp_off_common
;
18028 case BFD_RELOC_ARM_THUMB_OFFSET
:
18029 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18030 /* Exactly what ranges, and where the offset is inserted depends
18031 on the type of instruction, we can establish this from the
18033 switch (newval
>> 12)
18035 case 4: /* PC load. */
18036 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18037 forced to zero for these loads; md_pcrel_from has already
18038 compensated for this. */
18040 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18041 _("invalid offset, target not word aligned (0x%08lX)"),
18042 (((unsigned long) fixP
->fx_frag
->fr_address
18043 + (unsigned long) fixP
->fx_where
) & ~3)
18044 + (unsigned long) value
);
18046 if (value
& ~0x3fc)
18047 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18048 _("invalid offset, value too big (0x%08lX)"),
18051 newval
|= value
>> 2;
18054 case 9: /* SP load/store. */
18055 if (value
& ~0x3fc)
18056 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18057 _("invalid offset, value too big (0x%08lX)"),
18059 newval
|= value
>> 2;
18062 case 6: /* Word load/store. */
18064 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18065 _("invalid offset, value too big (0x%08lX)"),
18067 newval
|= value
<< 4; /* 6 - 2. */
18070 case 7: /* Byte load/store. */
18072 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18073 _("invalid offset, value too big (0x%08lX)"),
18075 newval
|= value
<< 6;
18078 case 8: /* Halfword load/store. */
18080 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18081 _("invalid offset, value too big (0x%08lX)"),
18083 newval
|= value
<< 5; /* 6 - 1. */
18087 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18088 "Unable to process relocation for thumb opcode: %lx",
18089 (unsigned long) newval
);
18092 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18095 case BFD_RELOC_ARM_THUMB_ADD
:
18096 /* This is a complicated relocation, since we use it for all of
18097 the following immediate relocations:
18101 9bit ADD/SUB SP word-aligned
18102 10bit ADD PC/SP word-aligned
18104 The type of instruction being processed is encoded in the
18111 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18113 int rd
= (newval
>> 4) & 0xf;
18114 int rs
= newval
& 0xf;
18115 int subtract
= !!(newval
& 0x8000);
18117 /* Check for HI regs, only very restricted cases allowed:
18118 Adjusting SP, and using PC or SP to get an address. */
18119 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18120 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18121 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18122 _("invalid Hi register with immediate"));
18124 /* If value is negative, choose the opposite instruction. */
18128 subtract
= !subtract
;
18130 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18131 _("immediate value out of range"));
18136 if (value
& ~0x1fc)
18137 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18138 _("invalid immediate for stack address calculation"));
18139 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18140 newval
|= value
>> 2;
18142 else if (rs
== REG_PC
|| rs
== REG_SP
)
18144 if (subtract
|| value
& ~0x3fc)
18145 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18146 _("invalid immediate for address calculation (value = 0x%08lX)"),
18147 (unsigned long) value
);
18148 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18150 newval
|= value
>> 2;
18155 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18156 _("immediate value out of range"));
18157 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18158 newval
|= (rd
<< 8) | value
;
18163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18164 _("immediate value out of range"));
18165 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18166 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18169 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18172 case BFD_RELOC_ARM_THUMB_IMM
:
18173 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18174 if (value
< 0 || value
> 255)
18175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18176 _("invalid immediate: %ld is too large"),
18179 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18182 case BFD_RELOC_ARM_THUMB_SHIFT
:
18183 /* 5bit shift value (0..32). LSL cannot take 32. */
18184 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18185 temp
= newval
& 0xf800;
18186 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18187 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18188 _("invalid shift value: %ld"), (long) value
);
18189 /* Shifts of zero must be encoded as LSL. */
18191 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18192 /* Shifts of 32 are encoded as zero. */
18193 else if (value
== 32)
18195 newval
|= value
<< 6;
18196 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18199 case BFD_RELOC_VTABLE_INHERIT
:
18200 case BFD_RELOC_VTABLE_ENTRY
:
18204 case BFD_RELOC_ARM_MOVW
:
18205 case BFD_RELOC_ARM_MOVT
:
18206 case BFD_RELOC_ARM_THUMB_MOVW
:
18207 case BFD_RELOC_ARM_THUMB_MOVT
:
18208 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18210 /* REL format relocations are limited to a 16-bit addend. */
18211 if (!fixP
->fx_done
)
18213 if (value
< -0x1000 || value
> 0xffff)
18214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18215 _("offset too big"));
18217 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18218 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18223 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18224 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18226 newval
= get_thumb32_insn (buf
);
18227 newval
&= 0xfbf08f00;
18228 newval
|= (value
& 0xf000) << 4;
18229 newval
|= (value
& 0x0800) << 15;
18230 newval
|= (value
& 0x0700) << 4;
18231 newval
|= (value
& 0x00ff);
18232 put_thumb32_insn (buf
, newval
);
18236 newval
= md_chars_to_number (buf
, 4);
18237 newval
&= 0xfff0f000;
18238 newval
|= value
& 0x0fff;
18239 newval
|= (value
& 0xf000) << 4;
18240 md_number_to_chars (buf
, newval
, 4);
18245 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18246 case BFD_RELOC_ARM_ALU_PC_G0
:
18247 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18248 case BFD_RELOC_ARM_ALU_PC_G1
:
18249 case BFD_RELOC_ARM_ALU_PC_G2
:
18250 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18251 case BFD_RELOC_ARM_ALU_SB_G0
:
18252 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18253 case BFD_RELOC_ARM_ALU_SB_G1
:
18254 case BFD_RELOC_ARM_ALU_SB_G2
:
18255 assert (!fixP
->fx_done
);
18256 if (!seg
->use_rela_p
)
18259 bfd_vma encoded_addend
;
18260 bfd_vma addend_abs
= abs (value
);
18262 /* Check that the absolute value of the addend can be
18263 expressed as an 8-bit constant plus a rotation. */
18264 encoded_addend
= encode_arm_immediate (addend_abs
);
18265 if (encoded_addend
== (unsigned int) FAIL
)
18266 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18267 _("the offset 0x%08lX is not representable"),
18270 /* Extract the instruction. */
18271 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18273 /* If the addend is positive, use an ADD instruction.
18274 Otherwise use a SUB. Take care not to destroy the S bit. */
18275 insn
&= 0xff1fffff;
18281 /* Place the encoded addend into the first 12 bits of the
18283 insn
&= 0xfffff000;
18284 insn
|= encoded_addend
;
18286 /* Update the instruction. */
18287 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18291 case BFD_RELOC_ARM_LDR_PC_G0
:
18292 case BFD_RELOC_ARM_LDR_PC_G1
:
18293 case BFD_RELOC_ARM_LDR_PC_G2
:
18294 case BFD_RELOC_ARM_LDR_SB_G0
:
18295 case BFD_RELOC_ARM_LDR_SB_G1
:
18296 case BFD_RELOC_ARM_LDR_SB_G2
:
18297 assert (!fixP
->fx_done
);
18298 if (!seg
->use_rela_p
)
18301 bfd_vma addend_abs
= abs (value
);
18303 /* Check that the absolute value of the addend can be
18304 encoded in 12 bits. */
18305 if (addend_abs
>= 0x1000)
18306 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18307 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18310 /* Extract the instruction. */
18311 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18313 /* If the addend is negative, clear bit 23 of the instruction.
18314 Otherwise set it. */
18316 insn
&= ~(1 << 23);
18320 /* Place the absolute value of the addend into the first 12 bits
18321 of the instruction. */
18322 insn
&= 0xfffff000;
18323 insn
|= addend_abs
;
18325 /* Update the instruction. */
18326 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18330 case BFD_RELOC_ARM_LDRS_PC_G0
:
18331 case BFD_RELOC_ARM_LDRS_PC_G1
:
18332 case BFD_RELOC_ARM_LDRS_PC_G2
:
18333 case BFD_RELOC_ARM_LDRS_SB_G0
:
18334 case BFD_RELOC_ARM_LDRS_SB_G1
:
18335 case BFD_RELOC_ARM_LDRS_SB_G2
:
18336 assert (!fixP
->fx_done
);
18337 if (!seg
->use_rela_p
)
18340 bfd_vma addend_abs
= abs (value
);
18342 /* Check that the absolute value of the addend can be
18343 encoded in 8 bits. */
18344 if (addend_abs
>= 0x100)
18345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18346 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18349 /* Extract the instruction. */
18350 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18352 /* If the addend is negative, clear bit 23 of the instruction.
18353 Otherwise set it. */
18355 insn
&= ~(1 << 23);
18359 /* Place the first four bits of the absolute value of the addend
18360 into the first 4 bits of the instruction, and the remaining
18361 four into bits 8 .. 11. */
18362 insn
&= 0xfffff0f0;
18363 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18365 /* Update the instruction. */
18366 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18370 case BFD_RELOC_ARM_LDC_PC_G0
:
18371 case BFD_RELOC_ARM_LDC_PC_G1
:
18372 case BFD_RELOC_ARM_LDC_PC_G2
:
18373 case BFD_RELOC_ARM_LDC_SB_G0
:
18374 case BFD_RELOC_ARM_LDC_SB_G1
:
18375 case BFD_RELOC_ARM_LDC_SB_G2
:
18376 assert (!fixP
->fx_done
);
18377 if (!seg
->use_rela_p
)
18380 bfd_vma addend_abs
= abs (value
);
18382 /* Check that the absolute value of the addend is a multiple of
18383 four and, when divided by four, fits in 8 bits. */
18384 if (addend_abs
& 0x3)
18385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18386 _("bad offset 0x%08lX (must be word-aligned)"),
18389 if ((addend_abs
>> 2) > 0xff)
18390 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18391 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18394 /* Extract the instruction. */
18395 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18397 /* If the addend is negative, clear bit 23 of the instruction.
18398 Otherwise set it. */
18400 insn
&= ~(1 << 23);
18404 /* Place the addend (divided by four) into the first eight
18405 bits of the instruction. */
18406 insn
&= 0xfffffff0;
18407 insn
|= addend_abs
>> 2;
18409 /* Update the instruction. */
18410 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18414 case BFD_RELOC_UNUSED
:
18416 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18417 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
18421 /* Translate internal representation of relocation info to BFD target
18425 tc_gen_reloc (asection
*section
, fixS
*fixp
)
18428 bfd_reloc_code_real_type code
;
18430 reloc
= xmalloc (sizeof (arelent
));
18432 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
18433 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18434 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18436 if (fixp
->fx_pcrel
)
18438 if (section
->use_rela_p
)
18439 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
18441 fixp
->fx_offset
= reloc
->address
;
18443 reloc
->addend
= fixp
->fx_offset
;
18445 switch (fixp
->fx_r_type
)
18448 if (fixp
->fx_pcrel
)
18450 code
= BFD_RELOC_8_PCREL
;
18455 if (fixp
->fx_pcrel
)
18457 code
= BFD_RELOC_16_PCREL
;
18462 if (fixp
->fx_pcrel
)
18464 code
= BFD_RELOC_32_PCREL
;
18468 case BFD_RELOC_ARM_MOVW
:
18469 if (fixp
->fx_pcrel
)
18471 code
= BFD_RELOC_ARM_MOVW_PCREL
;
18475 case BFD_RELOC_ARM_MOVT
:
18476 if (fixp
->fx_pcrel
)
18478 code
= BFD_RELOC_ARM_MOVT_PCREL
;
18482 case BFD_RELOC_ARM_THUMB_MOVW
:
18483 if (fixp
->fx_pcrel
)
18485 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
18489 case BFD_RELOC_ARM_THUMB_MOVT
:
18490 if (fixp
->fx_pcrel
)
18492 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
18496 case BFD_RELOC_NONE
:
18497 case BFD_RELOC_ARM_PCREL_BRANCH
:
18498 case BFD_RELOC_ARM_PCREL_BLX
:
18499 case BFD_RELOC_RVA
:
18500 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
18501 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
18502 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
18503 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18504 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18505 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18506 case BFD_RELOC_THUMB_PCREL_BLX
:
18507 case BFD_RELOC_VTABLE_ENTRY
:
18508 case BFD_RELOC_VTABLE_INHERIT
:
18510 case BFD_RELOC_32_SECREL
:
18512 code
= fixp
->fx_r_type
;
18515 case BFD_RELOC_ARM_LITERAL
:
18516 case BFD_RELOC_ARM_HWLITERAL
:
18517 /* If this is called then the a literal has
18518 been referenced across a section boundary. */
18519 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18520 _("literal referenced across section boundary"));
18524 case BFD_RELOC_ARM_GOT32
:
18525 case BFD_RELOC_ARM_GOTOFF
:
18526 case BFD_RELOC_ARM_PLT32
:
18527 case BFD_RELOC_ARM_TARGET1
:
18528 case BFD_RELOC_ARM_ROSEGREL32
:
18529 case BFD_RELOC_ARM_SBREL32
:
18530 case BFD_RELOC_ARM_PREL31
:
18531 case BFD_RELOC_ARM_TARGET2
:
18532 case BFD_RELOC_ARM_TLS_LE32
:
18533 case BFD_RELOC_ARM_TLS_LDO32
:
18534 case BFD_RELOC_ARM_PCREL_CALL
:
18535 case BFD_RELOC_ARM_PCREL_JUMP
:
18536 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18537 case BFD_RELOC_ARM_ALU_PC_G0
:
18538 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18539 case BFD_RELOC_ARM_ALU_PC_G1
:
18540 case BFD_RELOC_ARM_ALU_PC_G2
:
18541 case BFD_RELOC_ARM_LDR_PC_G0
:
18542 case BFD_RELOC_ARM_LDR_PC_G1
:
18543 case BFD_RELOC_ARM_LDR_PC_G2
:
18544 case BFD_RELOC_ARM_LDRS_PC_G0
:
18545 case BFD_RELOC_ARM_LDRS_PC_G1
:
18546 case BFD_RELOC_ARM_LDRS_PC_G2
:
18547 case BFD_RELOC_ARM_LDC_PC_G0
:
18548 case BFD_RELOC_ARM_LDC_PC_G1
:
18549 case BFD_RELOC_ARM_LDC_PC_G2
:
18550 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18551 case BFD_RELOC_ARM_ALU_SB_G0
:
18552 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18553 case BFD_RELOC_ARM_ALU_SB_G1
:
18554 case BFD_RELOC_ARM_ALU_SB_G2
:
18555 case BFD_RELOC_ARM_LDR_SB_G0
:
18556 case BFD_RELOC_ARM_LDR_SB_G1
:
18557 case BFD_RELOC_ARM_LDR_SB_G2
:
18558 case BFD_RELOC_ARM_LDRS_SB_G0
:
18559 case BFD_RELOC_ARM_LDRS_SB_G1
:
18560 case BFD_RELOC_ARM_LDRS_SB_G2
:
18561 case BFD_RELOC_ARM_LDC_SB_G0
:
18562 case BFD_RELOC_ARM_LDC_SB_G1
:
18563 case BFD_RELOC_ARM_LDC_SB_G2
:
18564 code
= fixp
->fx_r_type
;
18567 case BFD_RELOC_ARM_TLS_GD32
:
18568 case BFD_RELOC_ARM_TLS_IE32
:
18569 case BFD_RELOC_ARM_TLS_LDM32
:
18570 /* BFD will include the symbol's address in the addend.
18571 But we don't want that, so subtract it out again here. */
18572 if (!S_IS_COMMON (fixp
->fx_addsy
))
18573 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
18574 code
= fixp
->fx_r_type
;
18578 case BFD_RELOC_ARM_IMMEDIATE
:
18579 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18580 _("internal relocation (type: IMMEDIATE) not fixed up"));
18583 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18584 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18585 _("ADRL used for a symbol not defined in the same file"));
18588 case BFD_RELOC_ARM_OFFSET_IMM
:
18589 if (section
->use_rela_p
)
18591 code
= fixp
->fx_r_type
;
18595 if (fixp
->fx_addsy
!= NULL
18596 && !S_IS_DEFINED (fixp
->fx_addsy
)
18597 && S_IS_LOCAL (fixp
->fx_addsy
))
18599 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18600 _("undefined local label `%s'"),
18601 S_GET_NAME (fixp
->fx_addsy
));
18605 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18606 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
18613 switch (fixp
->fx_r_type
)
18615 case BFD_RELOC_NONE
: type
= "NONE"; break;
18616 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
18617 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
18618 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
18619 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
18620 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
18621 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
18622 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
18623 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
18624 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
18625 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
18626 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
18627 default: type
= _("<unknown>"); break;
18629 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18630 _("cannot represent %s relocation in this object file format"),
18637 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
18639 && fixp
->fx_addsy
== GOT_symbol
)
18641 code
= BFD_RELOC_ARM_GOTPC
;
18642 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
18646 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18648 if (reloc
->howto
== NULL
)
18650 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18651 _("cannot represent %s relocation in this object file format"),
18652 bfd_get_reloc_code_name (code
));
18656 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
18657 vtable entry to be used in the relocation's section offset. */
18658 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18659 reloc
->address
= fixp
->fx_offset
;
18664 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
18667 cons_fix_new_arm (fragS
* frag
,
18672 bfd_reloc_code_real_type type
;
18676 FIXME: @@ Should look at CPU word size. */
18680 type
= BFD_RELOC_8
;
18683 type
= BFD_RELOC_16
;
18687 type
= BFD_RELOC_32
;
18690 type
= BFD_RELOC_64
;
18695 if (exp
->X_op
== O_secrel
)
18697 exp
->X_op
= O_symbol
;
18698 type
= BFD_RELOC_32_SECREL
;
18702 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
18705 #if defined OBJ_COFF || defined OBJ_ELF
18707 arm_validate_fix (fixS
* fixP
)
18709 /* If the destination of the branch is a defined symbol which does not have
18710 the THUMB_FUNC attribute, then we must be calling a function which has
18711 the (interfacearm) attribute. We look for the Thumb entry point to that
18712 function and change the branch to refer to that function instead. */
18713 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
18714 && fixP
->fx_addsy
!= NULL
18715 && S_IS_DEFINED (fixP
->fx_addsy
)
18716 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
18718 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
18724 arm_force_relocation (struct fix
* fixp
)
18726 #if defined (OBJ_COFF) && defined (TE_PE)
18727 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
18731 /* Resolve these relocations even if the symbol is extern or weak. */
18732 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
18733 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
18734 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
18735 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
18736 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18737 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
18738 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
18741 /* Always leave these relocations for the linker. */
18742 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18743 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18744 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18747 return generic_force_reloc (fixp
);
18752 arm_fix_adjustable (fixS
* fixP
)
18754 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
18755 local labels from being added to the output symbol table when they
18756 are used with the ADRL pseudo op. The ADRL relocation should always
18757 be resolved before the binbary is emitted, so it is safe to say that
18758 it is adjustable. */
18759 if (fixP
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
18762 /* This is a hack for the gas/all/redef2.s test. This test causes symbols
18763 to be cloned, and without this test relocs would still be generated
18764 against the original, pre-cloned symbol. Such symbols would not appear
18765 in the symbol table however, and so a valid reloc could not be
18766 generated. So check to see if the fixup is against a symbol which has
18767 been removed from the symbol chain, and if it is, then allow it to be
18768 adjusted into a reloc against a section symbol. */
18769 if (fixP
->fx_addsy
!= NULL
18770 && ! S_IS_LOCAL (fixP
->fx_addsy
)
18771 && symbol_next (fixP
->fx_addsy
) == NULL
18772 && symbol_next (fixP
->fx_addsy
) == symbol_previous (fixP
->fx_addsy
))
18780 /* Relocations against function names must be left unadjusted,
18781 so that the linker can use this information to generate interworking
18782 stubs. The MIPS version of this function
18783 also prevents relocations that are mips-16 specific, but I do not
18784 know why it does this.
18787 There is one other problem that ought to be addressed here, but
18788 which currently is not: Taking the address of a label (rather
18789 than a function) and then later jumping to that address. Such
18790 addresses also ought to have their bottom bit set (assuming that
18791 they reside in Thumb code), but at the moment they will not. */
18794 arm_fix_adjustable (fixS
* fixP
)
18796 if (fixP
->fx_addsy
== NULL
)
18799 /* Preserve relocations against symbols with function type. */
18800 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
18803 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
18804 && fixP
->fx_subsy
== NULL
)
18807 /* We need the symbol name for the VTABLE entries. */
18808 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18809 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18812 /* Don't allow symbols to be discarded on GOT related relocs. */
18813 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
18814 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
18815 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
18816 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
18817 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
18818 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
18819 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
18820 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
18821 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
18824 /* Similarly for group relocations. */
18825 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18826 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18827 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18834 elf32_arm_target_format (void)
18837 return (target_big_endian
18838 ? "elf32-bigarm-symbian"
18839 : "elf32-littlearm-symbian");
18840 #elif defined (TE_VXWORKS)
18841 return (target_big_endian
18842 ? "elf32-bigarm-vxworks"
18843 : "elf32-littlearm-vxworks");
18845 if (target_big_endian
)
18846 return "elf32-bigarm";
18848 return "elf32-littlearm";
18853 armelf_frob_symbol (symbolS
* symp
,
18856 elf_frob_symbol (symp
, puntp
);
18860 /* MD interface: Finalization. */
18862 /* A good place to do this, although this was probably not intended
18863 for this kind of use. We need to dump the literal pool before
18864 references are made to a null symbol pointer. */
18869 literal_pool
* pool
;
18871 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
18873 /* Put it at the end of the relevent section. */
18874 subseg_set (pool
->section
, pool
->sub_section
);
18876 arm_elf_change_section ();
18882 /* Adjust the symbol table. This marks Thumb symbols as distinct from
18886 arm_adjust_symtab (void)
18891 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
18893 if (ARM_IS_THUMB (sym
))
18895 if (THUMB_IS_FUNC (sym
))
18897 /* Mark the symbol as a Thumb function. */
18898 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
18899 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
18900 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
18902 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
18903 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
18905 as_bad (_("%s: unexpected function type: %d"),
18906 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
18908 else switch (S_GET_STORAGE_CLASS (sym
))
18911 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
18914 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
18917 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
18925 if (ARM_IS_INTERWORK (sym
))
18926 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
18933 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
18935 if (ARM_IS_THUMB (sym
))
18937 elf_symbol_type
* elf_sym
;
18939 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
18940 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
18942 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
18943 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
18945 /* If it's a .thumb_func, declare it as so,
18946 otherwise tag label as .code 16. */
18947 if (THUMB_IS_FUNC (sym
))
18948 elf_sym
->internal_elf_sym
.st_info
=
18949 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
18951 elf_sym
->internal_elf_sym
.st_info
=
18952 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
18959 /* MD interface: Initialization. */
18962 set_constant_flonums (void)
18966 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
18967 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
18971 /* Auto-select Thumb mode if it's the only available instruction set for the
18972 given architecture. */
18975 autoselect_thumb_from_cpu_variant (void)
18977 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18978 opcode_select (16);
18987 if ( (arm_ops_hsh
= hash_new ()) == NULL
18988 || (arm_cond_hsh
= hash_new ()) == NULL
18989 || (arm_shift_hsh
= hash_new ()) == NULL
18990 || (arm_psr_hsh
= hash_new ()) == NULL
18991 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
18992 || (arm_reg_hsh
= hash_new ()) == NULL
18993 || (arm_reloc_hsh
= hash_new ()) == NULL
18994 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
18995 as_fatal (_("virtual memory exhausted"));
18997 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
18998 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
18999 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19000 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
19001 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19002 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
19003 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19004 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
19005 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19006 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
19007 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19008 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
19010 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19012 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19013 (PTR
) (barrier_opt_names
+ i
));
19015 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19016 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
19019 set_constant_flonums ();
19021 /* Set the cpu variant based on the command-line options. We prefer
19022 -mcpu= over -march= if both are set (as for GCC); and we prefer
19023 -mfpu= over any other way of setting the floating point unit.
19024 Use of legacy options with new options are faulted. */
19027 if (mcpu_cpu_opt
|| march_cpu_opt
)
19028 as_bad (_("use of old and new-style options to set CPU type"));
19030 mcpu_cpu_opt
= legacy_cpu
;
19032 else if (!mcpu_cpu_opt
)
19033 mcpu_cpu_opt
= march_cpu_opt
;
19038 as_bad (_("use of old and new-style options to set FPU type"));
19040 mfpu_opt
= legacy_fpu
;
19042 else if (!mfpu_opt
)
19044 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19045 /* Some environments specify a default FPU. If they don't, infer it
19046 from the processor. */
19048 mfpu_opt
= mcpu_fpu_opt
;
19050 mfpu_opt
= march_fpu_opt
;
19052 mfpu_opt
= &fpu_default
;
19059 mfpu_opt
= &fpu_default
;
19060 else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19061 mfpu_opt
= &fpu_arch_vfp_v2
;
19063 mfpu_opt
= &fpu_arch_fpa
;
19069 mcpu_cpu_opt
= &cpu_default
;
19070 selected_cpu
= cpu_default
;
19074 selected_cpu
= *mcpu_cpu_opt
;
19076 mcpu_cpu_opt
= &arm_arch_any
;
19079 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19081 autoselect_thumb_from_cpu_variant ();
19083 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19085 #if defined OBJ_COFF || defined OBJ_ELF
19087 unsigned int flags
= 0;
19089 #if defined OBJ_ELF
19090 flags
= meabi_flags
;
19092 switch (meabi_flags
)
19094 case EF_ARM_EABI_UNKNOWN
:
19096 /* Set the flags in the private structure. */
19097 if (uses_apcs_26
) flags
|= F_APCS26
;
19098 if (support_interwork
) flags
|= F_INTERWORK
;
19099 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19100 if (pic_code
) flags
|= F_PIC
;
19101 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19102 flags
|= F_SOFT_FLOAT
;
19104 switch (mfloat_abi_opt
)
19106 case ARM_FLOAT_ABI_SOFT
:
19107 case ARM_FLOAT_ABI_SOFTFP
:
19108 flags
|= F_SOFT_FLOAT
;
19111 case ARM_FLOAT_ABI_HARD
:
19112 if (flags
& F_SOFT_FLOAT
)
19113 as_bad (_("hard-float conflicts with specified fpu"));
19117 /* Using pure-endian doubles (even if soft-float). */
19118 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19119 flags
|= F_VFP_FLOAT
;
19121 #if defined OBJ_ELF
19122 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19123 flags
|= EF_ARM_MAVERICK_FLOAT
;
19126 case EF_ARM_EABI_VER4
:
19127 case EF_ARM_EABI_VER5
:
19128 /* No additional flags to set. */
19135 bfd_set_private_flags (stdoutput
, flags
);
19137 /* We have run out flags in the COFF header to encode the
19138 status of ATPCS support, so instead we create a dummy,
19139 empty, debug section called .arm.atpcs. */
19144 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19148 bfd_set_section_flags
19149 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19150 bfd_set_section_size (stdoutput
, sec
, 0);
19151 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19157 /* Record the CPU type as well. */
19158 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19159 mach
= bfd_mach_arm_iWMMXt
;
19160 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19161 mach
= bfd_mach_arm_XScale
;
19162 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19163 mach
= bfd_mach_arm_ep9312
;
19164 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19165 mach
= bfd_mach_arm_5TE
;
19166 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19168 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19169 mach
= bfd_mach_arm_5T
;
19171 mach
= bfd_mach_arm_5
;
19173 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19175 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19176 mach
= bfd_mach_arm_4T
;
19178 mach
= bfd_mach_arm_4
;
19180 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19181 mach
= bfd_mach_arm_3M
;
19182 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19183 mach
= bfd_mach_arm_3
;
19184 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19185 mach
= bfd_mach_arm_2a
;
19186 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19187 mach
= bfd_mach_arm_2
;
19189 mach
= bfd_mach_arm_unknown
;
19191 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19194 /* Command line processing. */
19197 Invocation line includes a switch not recognized by the base assembler.
19198 See if it's a processor-specific option.
19200 This routine is somewhat complicated by the need for backwards
19201 compatibility (since older releases of gcc can't be changed).
19202 The new options try to make the interface as compatible as
19205 New options (supported) are:
19207 -mcpu=<cpu name> Assemble for selected processor
19208 -march=<architecture name> Assemble for selected architecture
19209 -mfpu=<fpu architecture> Assemble for selected FPU.
19210 -EB/-mbig-endian Big-endian
19211 -EL/-mlittle-endian Little-endian
19212 -k Generate PIC code
19213 -mthumb Start in Thumb mode
19214 -mthumb-interwork Code supports ARM/Thumb interworking
19216 For now we will also provide support for:
19218 -mapcs-32 32-bit Program counter
19219 -mapcs-26 26-bit Program counter
19220 -macps-float Floats passed in FP registers
19221 -mapcs-reentrant Reentrant code
19223 (sometime these will probably be replaced with -mapcs=<list of options>
19224 and -matpcs=<list of options>)
19226 The remaining options are only supported for back-wards compatibility.
19227 Cpu variants, the arm part is optional:
19228 -m[arm]1 Currently not supported.
19229 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19230 -m[arm]3 Arm 3 processor
19231 -m[arm]6[xx], Arm 6 processors
19232 -m[arm]7[xx][t][[d]m] Arm 7 processors
19233 -m[arm]8[10] Arm 8 processors
19234 -m[arm]9[20][tdmi] Arm 9 processors
19235 -mstrongarm[110[0]] StrongARM processors
19236 -mxscale XScale processors
19237 -m[arm]v[2345[t[e]]] Arm architectures
19238 -mall All (except the ARM1)
19240 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19241 -mfpe-old (No float load/store multiples)
19242 -mvfpxd VFP Single precision
19244 -mno-fpu Disable all floating point instructions
19246 The following CPU names are recognized:
19247 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19248 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19249 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19250 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19251 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19252 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19253 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19257 const char * md_shortopts
= "m:k";
19259 #ifdef ARM_BI_ENDIAN
19260 #define OPTION_EB (OPTION_MD_BASE + 0)
19261 #define OPTION_EL (OPTION_MD_BASE + 1)
19263 #if TARGET_BYTES_BIG_ENDIAN
19264 #define OPTION_EB (OPTION_MD_BASE + 0)
19266 #define OPTION_EL (OPTION_MD_BASE + 1)
19270 struct option md_longopts
[] =
19273 {"EB", no_argument
, NULL
, OPTION_EB
},
19276 {"EL", no_argument
, NULL
, OPTION_EL
},
19278 {NULL
, no_argument
, NULL
, 0}
19281 size_t md_longopts_size
= sizeof (md_longopts
);
19283 struct arm_option_table
19285 char *option
; /* Option name to match. */
19286 char *help
; /* Help information. */
19287 int *var
; /* Variable to change. */
19288 int value
; /* What to change it to. */
19289 char *deprecated
; /* If non-null, print this message. */
19292 struct arm_option_table arm_opts
[] =
19294 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19295 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19296 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19297 &support_interwork
, 1, NULL
},
19298 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19299 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19300 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19302 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19303 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19304 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19305 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19308 /* These are recognized by the assembler, but have no affect on code. */
19309 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19310 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19311 {NULL
, NULL
, NULL
, 0, NULL
}
19314 struct arm_legacy_option_table
19316 char *option
; /* Option name to match. */
19317 const arm_feature_set
**var
; /* Variable to change. */
19318 const arm_feature_set value
; /* What to change it to. */
19319 char *deprecated
; /* If non-null, print this message. */
19322 const struct arm_legacy_option_table arm_legacy_opts
[] =
19324 /* DON'T add any new processors to this list -- we want the whole list
19325 to go away... Add them to the processors table instead. */
19326 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19327 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19328 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19329 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19330 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19331 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19332 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19333 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19334 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19335 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19336 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19337 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19338 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19339 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19340 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19341 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19342 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19343 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19344 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19345 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19346 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19347 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19348 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19349 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19350 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19351 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19352 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19353 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19354 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19355 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19356 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19357 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19358 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19359 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19360 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19361 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19362 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19363 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19364 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19365 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19366 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19367 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19368 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19369 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19370 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19371 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19372 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19373 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19374 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19375 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19376 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19377 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19378 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19379 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19380 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19381 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19382 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19383 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19384 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19385 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19386 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19387 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19388 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19389 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19390 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19391 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19392 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19393 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19394 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19395 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19396 N_("use -mcpu=strongarm110")},
19397 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19398 N_("use -mcpu=strongarm1100")},
19399 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19400 N_("use -mcpu=strongarm1110")},
19401 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19402 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19403 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19405 /* Architecture variants -- don't add any more to this list either. */
19406 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19407 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19408 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19409 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19410 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19411 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19412 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19413 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19414 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19415 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19416 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19417 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19418 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19419 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19420 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19421 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19422 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19423 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19425 /* Floating point variants -- don't add any more to this list either. */
19426 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19427 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19428 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19429 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19430 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19432 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
19435 struct arm_cpu_option_table
19438 const arm_feature_set value
;
19439 /* For some CPUs we assume an FPU unless the user explicitly sets
19441 const arm_feature_set default_fpu
;
19442 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19444 const char *canonical_name
;
19447 /* This list should, at a minimum, contain all the cpu names
19448 recognized by GCC. */
19449 static const struct arm_cpu_option_table arm_cpus
[] =
19451 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
19452 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
19453 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
19454 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19455 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19456 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19457 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19458 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19459 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19460 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19461 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19462 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19463 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19464 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19465 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19466 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19467 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19468 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19469 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19470 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19471 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19472 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19473 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19474 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19475 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19476 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19477 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19478 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19479 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19480 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19481 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19482 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19483 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19484 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19485 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19486 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19487 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19488 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19489 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19490 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
19491 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19492 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19493 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19494 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19495 /* For V5 or later processors we default to using VFP; but the user
19496 should really set the FPU type explicitly. */
19497 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19498 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19499 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19500 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19501 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19502 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19503 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
19504 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19505 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19506 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
19507 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19508 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19509 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19510 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19511 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19512 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
19513 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19514 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19515 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19516 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
19517 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19518 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
19519 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
19520 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
19521 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
19522 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
19523 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
19524 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
19525 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
19526 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
19527 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
19528 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
19529 | FPU_NEON_EXT_V1
),
19531 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
19532 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
19533 /* ??? XSCALE is really an architecture. */
19534 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19535 /* ??? iwmmxt is not a processor. */
19536 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
19537 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19539 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
19540 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
19543 struct arm_arch_option_table
19546 const arm_feature_set value
;
19547 const arm_feature_set default_fpu
;
19550 /* This list should, at a minimum, contain all the architecture names
19551 recognized by GCC. */
19552 static const struct arm_arch_option_table arm_archs
[] =
19554 {"all", ARM_ANY
, FPU_ARCH_FPA
},
19555 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
19556 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
19557 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19558 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19559 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
19560 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
19561 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
19562 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
19563 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
19564 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
19565 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
19566 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
19567 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
19568 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
19569 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
19570 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
19571 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19572 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19573 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
19574 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
19575 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
19576 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
19577 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
19578 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
19579 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
19580 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
19581 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
19582 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
19583 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
19584 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
19585 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
19586 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
19589 /* ISA extensions in the co-processor space. */
19590 struct arm_option_cpu_value_table
19593 const arm_feature_set value
;
19596 static const struct arm_option_cpu_value_table arm_extensions
[] =
19598 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
19599 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
19600 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
19601 {NULL
, ARM_ARCH_NONE
}
19604 /* This list should, at a minimum, contain all the fpu names
19605 recognized by GCC. */
19606 static const struct arm_option_cpu_value_table arm_fpus
[] =
19608 {"softfpa", FPU_NONE
},
19609 {"fpe", FPU_ARCH_FPE
},
19610 {"fpe2", FPU_ARCH_FPE
},
19611 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
19612 {"fpa", FPU_ARCH_FPA
},
19613 {"fpa10", FPU_ARCH_FPA
},
19614 {"fpa11", FPU_ARCH_FPA
},
19615 {"arm7500fe", FPU_ARCH_FPA
},
19616 {"softvfp", FPU_ARCH_VFP
},
19617 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
19618 {"vfp", FPU_ARCH_VFP_V2
},
19619 {"vfp9", FPU_ARCH_VFP_V2
},
19620 {"vfp3", FPU_ARCH_VFP_V3
},
19621 {"vfp10", FPU_ARCH_VFP_V2
},
19622 {"vfp10-r0", FPU_ARCH_VFP_V1
},
19623 {"vfpxd", FPU_ARCH_VFP_V1xD
},
19624 {"arm1020t", FPU_ARCH_VFP_V1
},
19625 {"arm1020e", FPU_ARCH_VFP_V2
},
19626 {"arm1136jfs", FPU_ARCH_VFP_V2
},
19627 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
19628 {"maverick", FPU_ARCH_MAVERICK
},
19629 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
19630 {NULL
, ARM_ARCH_NONE
}
19633 struct arm_option_value_table
19639 static const struct arm_option_value_table arm_float_abis
[] =
19641 {"hard", ARM_FLOAT_ABI_HARD
},
19642 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
19643 {"soft", ARM_FLOAT_ABI_SOFT
},
19648 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
19649 static const struct arm_option_value_table arm_eabis
[] =
19651 {"gnu", EF_ARM_EABI_UNKNOWN
},
19652 {"4", EF_ARM_EABI_VER4
},
19653 {"5", EF_ARM_EABI_VER5
},
19658 struct arm_long_option_table
19660 char * option
; /* Substring to match. */
19661 char * help
; /* Help information. */
19662 int (* func
) (char * subopt
); /* Function to decode sub-option. */
19663 char * deprecated
; /* If non-null, print this message. */
19667 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
19669 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
19671 /* Copy the feature set, so that we can modify it. */
19672 *ext_set
= **opt_p
;
19675 while (str
!= NULL
&& *str
!= 0)
19677 const struct arm_option_cpu_value_table
* opt
;
19683 as_bad (_("invalid architectural extension"));
19688 ext
= strchr (str
, '+');
19691 optlen
= ext
- str
;
19693 optlen
= strlen (str
);
19697 as_bad (_("missing architectural extension"));
19701 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
19702 if (strncmp (opt
->name
, str
, optlen
) == 0)
19704 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
19708 if (opt
->name
== NULL
)
19710 as_bad (_("unknown architectural extnsion `%s'"), str
);
19721 arm_parse_cpu (char * str
)
19723 const struct arm_cpu_option_table
* opt
;
19724 char * ext
= strchr (str
, '+');
19728 optlen
= ext
- str
;
19730 optlen
= strlen (str
);
19734 as_bad (_("missing cpu name `%s'"), str
);
19738 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
19739 if (strncmp (opt
->name
, str
, optlen
) == 0)
19741 mcpu_cpu_opt
= &opt
->value
;
19742 mcpu_fpu_opt
= &opt
->default_fpu
;
19743 if (opt
->canonical_name
)
19744 strcpy(selected_cpu_name
, opt
->canonical_name
);
19748 for (i
= 0; i
< optlen
; i
++)
19749 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
19750 selected_cpu_name
[i
] = 0;
19754 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
19759 as_bad (_("unknown cpu `%s'"), str
);
19764 arm_parse_arch (char * str
)
19766 const struct arm_arch_option_table
*opt
;
19767 char *ext
= strchr (str
, '+');
19771 optlen
= ext
- str
;
19773 optlen
= strlen (str
);
19777 as_bad (_("missing architecture name `%s'"), str
);
19781 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
19782 if (streq (opt
->name
, str
))
19784 march_cpu_opt
= &opt
->value
;
19785 march_fpu_opt
= &opt
->default_fpu
;
19786 strcpy(selected_cpu_name
, opt
->name
);
19789 return arm_parse_extension (ext
, &march_cpu_opt
);
19794 as_bad (_("unknown architecture `%s'\n"), str
);
19799 arm_parse_fpu (char * str
)
19801 const struct arm_option_cpu_value_table
* opt
;
19803 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
19804 if (streq (opt
->name
, str
))
19806 mfpu_opt
= &opt
->value
;
19810 as_bad (_("unknown floating point format `%s'\n"), str
);
19815 arm_parse_float_abi (char * str
)
19817 const struct arm_option_value_table
* opt
;
19819 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
19820 if (streq (opt
->name
, str
))
19822 mfloat_abi_opt
= opt
->value
;
19826 as_bad (_("unknown floating point abi `%s'\n"), str
);
19832 arm_parse_eabi (char * str
)
19834 const struct arm_option_value_table
*opt
;
19836 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
19837 if (streq (opt
->name
, str
))
19839 meabi_flags
= opt
->value
;
19842 as_bad (_("unknown EABI `%s'\n"), str
);
19847 struct arm_long_option_table arm_long_opts
[] =
19849 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
19850 arm_parse_cpu
, NULL
},
19851 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
19852 arm_parse_arch
, NULL
},
19853 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
19854 arm_parse_fpu
, NULL
},
19855 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
19856 arm_parse_float_abi
, NULL
},
19858 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
19859 arm_parse_eabi
, NULL
},
19861 {NULL
, NULL
, 0, NULL
}
19865 md_parse_option (int c
, char * arg
)
19867 struct arm_option_table
*opt
;
19868 const struct arm_legacy_option_table
*fopt
;
19869 struct arm_long_option_table
*lopt
;
19875 target_big_endian
= 1;
19881 target_big_endian
= 0;
19886 /* Listing option. Just ignore these, we don't support additional
19891 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
19893 if (c
== opt
->option
[0]
19894 && ((arg
== NULL
&& opt
->option
[1] == 0)
19895 || streq (arg
, opt
->option
+ 1)))
19897 #if WARN_DEPRECATED
19898 /* If the option is deprecated, tell the user. */
19899 if (opt
->deprecated
!= NULL
)
19900 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
19901 arg
? arg
: "", _(opt
->deprecated
));
19904 if (opt
->var
!= NULL
)
19905 *opt
->var
= opt
->value
;
19911 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
19913 if (c
== fopt
->option
[0]
19914 && ((arg
== NULL
&& fopt
->option
[1] == 0)
19915 || streq (arg
, fopt
->option
+ 1)))
19917 #if WARN_DEPRECATED
19918 /* If the option is deprecated, tell the user. */
19919 if (fopt
->deprecated
!= NULL
)
19920 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
19921 arg
? arg
: "", _(fopt
->deprecated
));
19924 if (fopt
->var
!= NULL
)
19925 *fopt
->var
= &fopt
->value
;
19931 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
19933 /* These options are expected to have an argument. */
19934 if (c
== lopt
->option
[0]
19936 && strncmp (arg
, lopt
->option
+ 1,
19937 strlen (lopt
->option
+ 1)) == 0)
19939 #if WARN_DEPRECATED
19940 /* If the option is deprecated, tell the user. */
19941 if (lopt
->deprecated
!= NULL
)
19942 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
19943 _(lopt
->deprecated
));
19946 /* Call the sup-option parser. */
19947 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
19958 md_show_usage (FILE * fp
)
19960 struct arm_option_table
*opt
;
19961 struct arm_long_option_table
*lopt
;
19963 fprintf (fp
, _(" ARM-specific assembler options:\n"));
19965 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
19966 if (opt
->help
!= NULL
)
19967 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
19969 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
19970 if (lopt
->help
!= NULL
)
19971 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
19975 -EB assemble code for a big-endian cpu\n"));
19980 -EL assemble code for a little-endian cpu\n"));
19989 arm_feature_set flags
;
19990 } cpu_arch_ver_table
;
19992 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
19993 least features first. */
19994 static const cpu_arch_ver_table cpu_arch_ver
[] =
19999 {4, ARM_ARCH_V5TE
},
20000 {5, ARM_ARCH_V5TEJ
},
20004 {9, ARM_ARCH_V6T2
},
20005 {10, ARM_ARCH_V7A
},
20006 {10, ARM_ARCH_V7R
},
20007 {10, ARM_ARCH_V7M
},
20011 /* Set the public EABI object attributes. */
20013 aeabi_set_public_attributes (void)
20016 arm_feature_set flags
;
20017 arm_feature_set tmp
;
20018 const cpu_arch_ver_table
*p
;
20020 /* Choose the architecture based on the capabilities of the requested cpu
20021 (if any) and/or the instructions actually used. */
20022 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20023 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20024 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20028 for (p
= cpu_arch_ver
; p
->val
; p
++)
20030 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20033 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20037 /* Tag_CPU_name. */
20038 if (selected_cpu_name
[0])
20042 p
= selected_cpu_name
;
20043 if (strncmp(p
, "armv", 4) == 0)
20048 for (i
= 0; p
[i
]; i
++)
20049 p
[i
] = TOUPPER (p
[i
]);
20051 elf32_arm_add_eabi_attr_string (stdoutput
, 5, p
);
20053 /* Tag_CPU_arch. */
20054 elf32_arm_add_eabi_attr_int (stdoutput
, 6, arch
);
20055 /* Tag_CPU_arch_profile. */
20056 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20057 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'A');
20058 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20059 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'R');
20060 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
20061 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'M');
20062 /* Tag_ARM_ISA_use. */
20063 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20064 elf32_arm_add_eabi_attr_int (stdoutput
, 8, 1);
20065 /* Tag_THUMB_ISA_use. */
20066 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20067 elf32_arm_add_eabi_attr_int (stdoutput
, 9,
20068 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20069 /* Tag_VFP_arch. */
20070 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20071 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20072 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 3);
20073 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20074 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20075 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 2);
20076 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20077 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20078 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20079 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20080 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 1);
20081 /* Tag_WMMX_arch. */
20082 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20083 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20084 elf32_arm_add_eabi_attr_int (stdoutput
, 11, 1);
20085 /* Tag_NEON_arch. */
20086 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
20087 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
20088 elf32_arm_add_eabi_attr_int (stdoutput
, 12, 1);
20091 /* Add the .ARM.attributes section. */
20100 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20103 aeabi_set_public_attributes ();
20104 size
= elf32_arm_eabi_attr_size (stdoutput
);
20105 s
= subseg_new (".ARM.attributes", 0);
20106 bfd_set_section_flags (stdoutput
, s
, SEC_READONLY
| SEC_DATA
);
20107 addr
= frag_now_fix ();
20108 p
= frag_more (size
);
20109 elf32_arm_set_eabi_attr_contents (stdoutput
, (bfd_byte
*)p
, size
);
20111 #endif /* OBJ_ELF */
20114 /* Parse a .cpu directive. */
20117 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20119 const struct arm_cpu_option_table
*opt
;
20123 name
= input_line_pointer
;
20124 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20125 input_line_pointer
++;
20126 saved_char
= *input_line_pointer
;
20127 *input_line_pointer
= 0;
20129 /* Skip the first "all" entry. */
20130 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20131 if (streq (opt
->name
, name
))
20133 mcpu_cpu_opt
= &opt
->value
;
20134 selected_cpu
= opt
->value
;
20135 if (opt
->canonical_name
)
20136 strcpy(selected_cpu_name
, opt
->canonical_name
);
20140 for (i
= 0; opt
->name
[i
]; i
++)
20141 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20142 selected_cpu_name
[i
] = 0;
20144 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20145 *input_line_pointer
= saved_char
;
20146 demand_empty_rest_of_line ();
20149 as_bad (_("unknown cpu `%s'"), name
);
20150 *input_line_pointer
= saved_char
;
20151 ignore_rest_of_line ();
20155 /* Parse a .arch directive. */
20158 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20160 const struct arm_arch_option_table
*opt
;
20164 name
= input_line_pointer
;
20165 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20166 input_line_pointer
++;
20167 saved_char
= *input_line_pointer
;
20168 *input_line_pointer
= 0;
20170 /* Skip the first "all" entry. */
20171 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20172 if (streq (opt
->name
, name
))
20174 mcpu_cpu_opt
= &opt
->value
;
20175 selected_cpu
= opt
->value
;
20176 strcpy(selected_cpu_name
, opt
->name
);
20177 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20178 *input_line_pointer
= saved_char
;
20179 demand_empty_rest_of_line ();
20183 as_bad (_("unknown architecture `%s'\n"), name
);
20184 *input_line_pointer
= saved_char
;
20185 ignore_rest_of_line ();
20189 /* Parse a .fpu directive. */
20192 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20194 const struct arm_option_cpu_value_table
*opt
;
20198 name
= input_line_pointer
;
20199 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20200 input_line_pointer
++;
20201 saved_char
= *input_line_pointer
;
20202 *input_line_pointer
= 0;
20204 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20205 if (streq (opt
->name
, name
))
20207 mfpu_opt
= &opt
->value
;
20208 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20209 *input_line_pointer
= saved_char
;
20210 demand_empty_rest_of_line ();
20214 as_bad (_("unknown floating point format `%s'\n"), name
);
20215 *input_line_pointer
= saved_char
;
20216 ignore_rest_of_line ();