1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
306 static const arm_feature_set fpu_vfp_fp16
=
307 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
308 static const arm_feature_set fpu_neon_ext_fma
=
309 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
311 static const arm_feature_set fpu_vfp_ext_fma
=
312 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
313 static const arm_feature_set fpu_vfp_ext_armv8
=
314 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
315 static const arm_feature_set fpu_vfp_ext_armv8xd
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
317 static const arm_feature_set fpu_neon_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
319 static const arm_feature_set fpu_crypto_ext_armv8
=
320 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
321 static const arm_feature_set crc_ext_armv8
=
322 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
323 static const arm_feature_set fpu_neon_ext_v8_1
=
324 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
325 static const arm_feature_set fpu_neon_ext_dotprod
=
326 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
328 static int mfloat_abi_opt
= -1;
329 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
331 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
332 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
334 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
335 /* Feature bits selected by the last -mcpu/-march or by the combination of the
336 last .cpu/.arch directive .arch_extension directives since that
338 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
339 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
340 static arm_feature_set selected_fpu
= FPU_NONE
;
341 /* Feature bits selected by the last .object_arch directive. */
342 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
343 /* Must be long enough to hold any of the names in arm_cpus. */
344 static char selected_cpu_name
[20];
346 extern FLONUM_TYPE generic_floating_point_number
;
348 /* Return if no cpu was selected on command-line. */
350 no_cpu_selected (void)
352 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
357 static int meabi_flags
= EABI_DEFAULT
;
359 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
362 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
367 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
372 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
373 symbolS
* GOT_symbol
;
376 /* 0: assemble for ARM,
377 1: assemble for Thumb,
378 2: assemble for Thumb even though target CPU does not support thumb
380 static int thumb_mode
= 0;
381 /* A value distinct from the possible values for thumb_mode that we
382 can use to record whether thumb_mode has been copied into the
383 tc_frag_data field of a frag. */
384 #define MODE_RECORDED (1 << 4)
386 /* Specifies the intrinsic IT insn behavior mode. */
387 enum implicit_it_mode
389 IMPLICIT_IT_MODE_NEVER
= 0x00,
390 IMPLICIT_IT_MODE_ARM
= 0x01,
391 IMPLICIT_IT_MODE_THUMB
= 0x02,
392 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
394 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
396 /* If unified_syntax is true, we are processing the new unified
397 ARM/Thumb syntax. Important differences from the old ARM mode:
399 - Immediate operands do not require a # prefix.
400 - Conditional affixes always appear at the end of the
401 instruction. (For backward compatibility, those instructions
402 that formerly had them in the middle, continue to accept them
404 - The IT instruction may appear, and if it does is validated
405 against subsequent conditional affixes. It does not generate
408 Important differences from the old Thumb mode:
410 - Immediate operands do not require a # prefix.
411 - Most of the V6T2 instructions are only available in unified mode.
412 - The .N and .W suffixes are recognized and honored (it is an error
413 if they cannot be honored).
414 - All instructions set the flags if and only if they have an 's' affix.
415 - Conditional affixes may be used. They are validated against
416 preceding IT instructions. Unlike ARM mode, you cannot use a
417 conditional affix except in the scope of an IT instruction. */
419 static bfd_boolean unified_syntax
= FALSE
;
421 /* An immediate operand can start with #, and ld*, st*, pld operands
422 can contain [ and ]. We need to tell APP not to elide whitespace
423 before a [, which can appear as the first operand for pld.
424 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
425 const char arm_symbol_chars
[] = "#[]{}";
440 enum neon_el_type type
;
444 #define NEON_MAX_TYPE_ELS 4
448 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
452 enum it_instruction_type
457 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
458 if inside, should be the last one. */
459 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
460 i.e. BKPT and NOP. */
461 IT_INSN
/* The IT insn has been parsed. */
464 /* The maximum number of operands we need. */
465 #define ARM_IT_MAX_OPERANDS 6
466 #define ARM_IT_MAX_RELOCS 3
471 unsigned long instruction
;
475 /* "uncond_value" is set to the value in place of the conditional field in
476 unconditional versions of the instruction, or -1 if nothing is
479 struct neon_type vectype
;
480 /* This does not indicate an actual NEON instruction, only that
481 the mnemonic accepts neon-style type suffixes. */
483 /* Set to the opcode if the instruction needs relaxation.
484 Zero if the instruction is not relaxed. */
488 bfd_reloc_code_real_type type
;
491 } relocs
[ARM_IT_MAX_RELOCS
];
493 enum it_instruction_type it_insn_type
;
499 struct neon_type_el vectype
;
500 unsigned present
: 1; /* Operand present. */
501 unsigned isreg
: 1; /* Operand was a register. */
502 unsigned immisreg
: 1; /* .imm field is a second register. */
503 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
504 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
505 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
506 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
507 instructions. This allows us to disambiguate ARM <-> vector insns. */
508 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
509 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
510 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
511 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
512 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
513 unsigned writeback
: 1; /* Operand has trailing ! */
514 unsigned preind
: 1; /* Preindexed address. */
515 unsigned postind
: 1; /* Postindexed address. */
516 unsigned negative
: 1; /* Index register was negated. */
517 unsigned shifted
: 1; /* Shift applied to operation. */
518 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
519 } operands
[ARM_IT_MAX_OPERANDS
];
522 static struct arm_it inst
;
524 #define NUM_FLOAT_VALS 8
526 const char * fp_const
[] =
528 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
531 /* Number of littlenums required to hold an extended precision number. */
532 #define MAX_LITTLENUMS 6
534 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
544 #define CP_T_X 0x00008000
545 #define CP_T_Y 0x00400000
547 #define CONDS_BIT 0x00100000
548 #define LOAD_BIT 0x00100000
550 #define DOUBLE_LOAD_FLAG 0x00000001
554 const char * template_name
;
558 #define COND_ALWAYS 0xE
562 const char * template_name
;
566 struct asm_barrier_opt
568 const char * template_name
;
570 const arm_feature_set arch
;
573 /* The bit that distinguishes CPSR and SPSR. */
574 #define SPSR_BIT (1 << 22)
576 /* The individual PSR flag bits. */
577 #define PSR_c (1 << 16)
578 #define PSR_x (1 << 17)
579 #define PSR_s (1 << 18)
580 #define PSR_f (1 << 19)
585 bfd_reloc_code_real_type reloc
;
590 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
591 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
596 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
599 /* Bits for DEFINED field in neon_typed_alias. */
600 #define NTA_HASTYPE 1
601 #define NTA_HASINDEX 2
603 struct neon_typed_alias
605 unsigned char defined
;
607 struct neon_type_el eltype
;
610 /* ARM register categories. This includes coprocessor numbers and various
611 architecture extensions' registers. Each entry should have an error message
612 in reg_expected_msgs below. */
640 /* Structure for a hash table entry for a register.
641 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
642 information which states whether a vector type or index is specified (for a
643 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
649 unsigned char builtin
;
650 struct neon_typed_alias
* neon
;
653 /* Diagnostics used when we don't get a register of the expected type. */
654 const char * const reg_expected_msgs
[] =
656 [REG_TYPE_RN
] = N_("ARM register expected"),
657 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
658 [REG_TYPE_CN
] = N_("co-processor register expected"),
659 [REG_TYPE_FN
] = N_("FPA register expected"),
660 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
661 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
662 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
663 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
664 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
665 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
666 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
668 [REG_TYPE_VFC
] = N_("VFP system register expected"),
669 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
670 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
671 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
672 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
673 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
674 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
675 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
676 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
677 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
678 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
679 [REG_TYPE_RNB
] = N_("")
682 /* Some well known registers that we refer to directly elsewhere. */
688 /* ARM instructions take 4bytes in the object file, Thumb instructions
694 /* Basic string to match. */
695 const char * template_name
;
697 /* Parameters to instruction. */
698 unsigned int operands
[8];
700 /* Conditional tag - see opcode_lookup. */
701 unsigned int tag
: 4;
703 /* Basic instruction code. */
704 unsigned int avalue
: 28;
706 /* Thumb-format instruction code. */
709 /* Which architecture variant provides this instruction. */
710 const arm_feature_set
* avariant
;
711 const arm_feature_set
* tvariant
;
713 /* Function to call to encode instruction in ARM format. */
714 void (* aencode
) (void);
716 /* Function to call to encode instruction in Thumb format. */
717 void (* tencode
) (void);
720 /* Defines for various bits that we will want to toggle. */
721 #define INST_IMMEDIATE 0x02000000
722 #define OFFSET_REG 0x02000000
723 #define HWOFFSET_IMM 0x00400000
724 #define SHIFT_BY_REG 0x00000010
725 #define PRE_INDEX 0x01000000
726 #define INDEX_UP 0x00800000
727 #define WRITE_BACK 0x00200000
728 #define LDM_TYPE_2_OR_3 0x00400000
729 #define CPSI_MMOD 0x00020000
731 #define LITERAL_MASK 0xf000f000
732 #define OPCODE_MASK 0xfe1fffff
733 #define V4_STR_BIT 0x00000020
734 #define VLDR_VMOV_SAME 0x0040f000
736 #define T2_SUBS_PC_LR 0xf3de8f00
738 #define DATA_OP_SHIFT 21
739 #define SBIT_SHIFT 20
741 #define T2_OPCODE_MASK 0xfe1fffff
742 #define T2_DATA_OP_SHIFT 21
743 #define T2_SBIT_SHIFT 20
745 #define A_COND_MASK 0xf0000000
746 #define A_PUSH_POP_OP_MASK 0x0fff0000
748 /* Opcodes for pushing/poping registers to/from the stack. */
749 #define A1_OPCODE_PUSH 0x092d0000
750 #define A2_OPCODE_PUSH 0x052d0004
751 #define A2_OPCODE_POP 0x049d0004
753 /* Codes to distinguish the arithmetic instructions. */
764 #define OPCODE_CMP 10
765 #define OPCODE_CMN 11
766 #define OPCODE_ORR 12
767 #define OPCODE_MOV 13
768 #define OPCODE_BIC 14
769 #define OPCODE_MVN 15
771 #define T2_OPCODE_AND 0
772 #define T2_OPCODE_BIC 1
773 #define T2_OPCODE_ORR 2
774 #define T2_OPCODE_ORN 3
775 #define T2_OPCODE_EOR 4
776 #define T2_OPCODE_ADD 8
777 #define T2_OPCODE_ADC 10
778 #define T2_OPCODE_SBC 11
779 #define T2_OPCODE_SUB 13
780 #define T2_OPCODE_RSB 14
782 #define T_OPCODE_MUL 0x4340
783 #define T_OPCODE_TST 0x4200
784 #define T_OPCODE_CMN 0x42c0
785 #define T_OPCODE_NEG 0x4240
786 #define T_OPCODE_MVN 0x43c0
788 #define T_OPCODE_ADD_R3 0x1800
789 #define T_OPCODE_SUB_R3 0x1a00
790 #define T_OPCODE_ADD_HI 0x4400
791 #define T_OPCODE_ADD_ST 0xb000
792 #define T_OPCODE_SUB_ST 0xb080
793 #define T_OPCODE_ADD_SP 0xa800
794 #define T_OPCODE_ADD_PC 0xa000
795 #define T_OPCODE_ADD_I8 0x3000
796 #define T_OPCODE_SUB_I8 0x3800
797 #define T_OPCODE_ADD_I3 0x1c00
798 #define T_OPCODE_SUB_I3 0x1e00
800 #define T_OPCODE_ASR_R 0x4100
801 #define T_OPCODE_LSL_R 0x4080
802 #define T_OPCODE_LSR_R 0x40c0
803 #define T_OPCODE_ROR_R 0x41c0
804 #define T_OPCODE_ASR_I 0x1000
805 #define T_OPCODE_LSL_I 0x0000
806 #define T_OPCODE_LSR_I 0x0800
808 #define T_OPCODE_MOV_I8 0x2000
809 #define T_OPCODE_CMP_I8 0x2800
810 #define T_OPCODE_CMP_LR 0x4280
811 #define T_OPCODE_MOV_HR 0x4600
812 #define T_OPCODE_CMP_HR 0x4500
814 #define T_OPCODE_LDR_PC 0x4800
815 #define T_OPCODE_LDR_SP 0x9800
816 #define T_OPCODE_STR_SP 0x9000
817 #define T_OPCODE_LDR_IW 0x6800
818 #define T_OPCODE_STR_IW 0x6000
819 #define T_OPCODE_LDR_IH 0x8800
820 #define T_OPCODE_STR_IH 0x8000
821 #define T_OPCODE_LDR_IB 0x7800
822 #define T_OPCODE_STR_IB 0x7000
823 #define T_OPCODE_LDR_RW 0x5800
824 #define T_OPCODE_STR_RW 0x5000
825 #define T_OPCODE_LDR_RH 0x5a00
826 #define T_OPCODE_STR_RH 0x5200
827 #define T_OPCODE_LDR_RB 0x5c00
828 #define T_OPCODE_STR_RB 0x5400
830 #define T_OPCODE_PUSH 0xb400
831 #define T_OPCODE_POP 0xbc00
833 #define T_OPCODE_BRANCH 0xe000
835 #define THUMB_SIZE 2 /* Size of thumb instruction. */
836 #define THUMB_PP_PC_LR 0x0100
837 #define THUMB_LOAD_BIT 0x0800
838 #define THUMB2_LOAD_BIT 0x00100000
840 #define BAD_ARGS _("bad arguments to instruction")
841 #define BAD_SP _("r13 not allowed here")
842 #define BAD_PC _("r15 not allowed here")
843 #define BAD_COND _("instruction cannot be conditional")
844 #define BAD_OVERLAP _("registers may not be the same")
845 #define BAD_HIREG _("lo register required")
846 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
847 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
848 #define BAD_BRANCH _("branch must be last instruction in IT block")
849 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
850 #define BAD_NOT_IT _("instruction not allowed in IT block")
851 #define BAD_FPU _("selected FPU does not support instruction")
852 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
853 #define BAD_IT_COND _("incorrect condition in IT block")
854 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
855 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
856 #define BAD_PC_ADDRESSING \
857 _("cannot use register index with PC-relative addressing")
858 #define BAD_PC_WRITEBACK \
859 _("cannot use writeback with PC-relative addressing")
860 #define BAD_RANGE _("branch out of range")
861 #define BAD_FP16 _("selected processor does not support fp16 instruction")
862 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
863 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
865 static struct hash_control
* arm_ops_hsh
;
866 static struct hash_control
* arm_cond_hsh
;
867 static struct hash_control
* arm_shift_hsh
;
868 static struct hash_control
* arm_psr_hsh
;
869 static struct hash_control
* arm_v7m_psr_hsh
;
870 static struct hash_control
* arm_reg_hsh
;
871 static struct hash_control
* arm_reloc_hsh
;
872 static struct hash_control
* arm_barrier_opt_hsh
;
874 /* Stuff needed to resolve the label ambiguity
883 symbolS
* last_label_seen
;
884 static int label_is_thumb_function_name
= FALSE
;
886 /* Literal pool structure. Held on a per-section
887 and per-sub-section basis. */
889 #define MAX_LITERAL_POOL_SIZE 1024
890 typedef struct literal_pool
892 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
893 unsigned int next_free_entry
;
899 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
901 struct literal_pool
* next
;
902 unsigned int alignment
;
905 /* Pointer to a linked list of literal pools. */
906 literal_pool
* list_of_pools
= NULL
;
908 typedef enum asmfunc_states
911 WAITING_ASMFUNC_NAME
,
915 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
918 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
920 static struct current_it now_it
;
924 now_it_compatible (int cond
)
926 return (cond
& ~1) == (now_it
.cc
& ~1);
930 conditional_insn (void)
932 return inst
.cond
!= COND_ALWAYS
;
935 static int in_it_block (void);
937 static int handle_it_state (void);
939 static void force_automatic_it_block_close (void);
941 static void it_fsm_post_encode (void);
943 #define set_it_insn_type(type) \
946 inst.it_insn_type = type; \
947 if (handle_it_state () == FAIL) \
952 #define set_it_insn_type_nonvoid(type, failret) \
955 inst.it_insn_type = type; \
956 if (handle_it_state () == FAIL) \
961 #define set_it_insn_type_last() \
964 if (inst.cond == COND_ALWAYS) \
965 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
967 set_it_insn_type (INSIDE_IT_LAST_INSN); \
973 /* This array holds the chars that always start a comment. If the
974 pre-processor is disabled, these aren't very useful. */
975 char arm_comment_chars
[] = "@";
977 /* This array holds the chars that only start a comment at the beginning of
978 a line. If the line seems to have the form '# 123 filename'
979 .line and .file directives will appear in the pre-processed output. */
980 /* Note that input_file.c hand checks for '#' at the beginning of the
981 first line of the input file. This is because the compiler outputs
982 #NO_APP at the beginning of its output. */
983 /* Also note that comments like this one will always work. */
984 const char line_comment_chars
[] = "#";
986 char arm_line_separator_chars
[] = ";";
988 /* Chars that can be used to separate mant
989 from exp in floating point numbers. */
990 const char EXP_CHARS
[] = "eE";
992 /* Chars that mean this number is a floating point constant. */
996 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
998 /* Prefix characters that indicate the start of an immediate
1000 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1002 /* Separator character handling. */
1004 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1007 skip_past_char (char ** str
, char c
)
1009 /* PR gas/14987: Allow for whitespace before the expected character. */
1010 skip_whitespace (*str
);
1021 #define skip_past_comma(str) skip_past_char (str, ',')
1023 /* Arithmetic expressions (possibly involving symbols). */
1025 /* Return TRUE if anything in the expression is a bignum. */
1028 walk_no_bignums (symbolS
* sp
)
1030 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1033 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1035 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1036 || (symbol_get_value_expression (sp
)->X_op_symbol
1037 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1043 static bfd_boolean in_my_get_expression
= FALSE
;
1045 /* Third argument to my_get_expression. */
1046 #define GE_NO_PREFIX 0
1047 #define GE_IMM_PREFIX 1
1048 #define GE_OPT_PREFIX 2
1049 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1050 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1051 #define GE_OPT_PREFIX_BIG 3
1054 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1058 /* In unified syntax, all prefixes are optional. */
1060 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1063 switch (prefix_mode
)
1065 case GE_NO_PREFIX
: break;
1067 if (!is_immediate_prefix (**str
))
1069 inst
.error
= _("immediate expression requires a # prefix");
1075 case GE_OPT_PREFIX_BIG
:
1076 if (is_immediate_prefix (**str
))
1083 memset (ep
, 0, sizeof (expressionS
));
1085 save_in
= input_line_pointer
;
1086 input_line_pointer
= *str
;
1087 in_my_get_expression
= TRUE
;
1089 in_my_get_expression
= FALSE
;
1091 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1093 /* We found a bad or missing expression in md_operand(). */
1094 *str
= input_line_pointer
;
1095 input_line_pointer
= save_in
;
1096 if (inst
.error
== NULL
)
1097 inst
.error
= (ep
->X_op
== O_absent
1098 ? _("missing expression") :_("bad expression"));
1102 /* Get rid of any bignums now, so that we don't generate an error for which
1103 we can't establish a line number later on. Big numbers are never valid
1104 in instructions, which is where this routine is always called. */
1105 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1106 && (ep
->X_op
== O_big
1107 || (ep
->X_add_symbol
1108 && (walk_no_bignums (ep
->X_add_symbol
)
1110 && walk_no_bignums (ep
->X_op_symbol
))))))
1112 inst
.error
= _("invalid constant");
1113 *str
= input_line_pointer
;
1114 input_line_pointer
= save_in
;
1118 *str
= input_line_pointer
;
1119 input_line_pointer
= save_in
;
1123 /* Turn a string in input_line_pointer into a floating point constant
1124 of type TYPE, and store the appropriate bytes in *LITP. The number
1125 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1126 returned, or NULL on OK.
1128 Note that fp constants aren't represent in the normal way on the ARM.
1129 In big endian mode, things are as expected. However, in little endian
1130 mode fp constants are big-endian word-wise, and little-endian byte-wise
1131 within the words. For example, (double) 1.1 in big endian mode is
1132 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1133 the byte sequence 99 99 f1 3f 9a 99 99 99.
1135 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1138 md_atof (int type
, char * litP
, int * sizeP
)
1141 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1173 return _("Unrecognized or unsupported floating point constant");
1176 t
= atof_ieee (input_line_pointer
, type
, words
);
1178 input_line_pointer
= t
;
1179 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1181 if (target_big_endian
)
1183 for (i
= 0; i
< prec
; i
++)
1185 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1186 litP
+= sizeof (LITTLENUM_TYPE
);
1191 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1192 for (i
= prec
- 1; i
>= 0; i
--)
1194 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1195 litP
+= sizeof (LITTLENUM_TYPE
);
1198 /* For a 4 byte float the order of elements in `words' is 1 0.
1199 For an 8 byte float the order is 1 0 3 2. */
1200 for (i
= 0; i
< prec
; i
+= 2)
1202 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1203 sizeof (LITTLENUM_TYPE
));
1204 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1205 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1206 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1213 /* We handle all bad expressions here, so that we can report the faulty
1214 instruction in the error message. */
1217 md_operand (expressionS
* exp
)
1219 if (in_my_get_expression
)
1220 exp
->X_op
= O_illegal
;
1223 /* Immediate values. */
1226 /* Generic immediate-value read function for use in directives.
1227 Accepts anything that 'expression' can fold to a constant.
1228 *val receives the number. */
1231 immediate_for_directive (int *val
)
1234 exp
.X_op
= O_illegal
;
1236 if (is_immediate_prefix (*input_line_pointer
))
1238 input_line_pointer
++;
1242 if (exp
.X_op
!= O_constant
)
1244 as_bad (_("expected #constant"));
1245 ignore_rest_of_line ();
1248 *val
= exp
.X_add_number
;
1253 /* Register parsing. */
1255 /* Generic register parser. CCP points to what should be the
1256 beginning of a register name. If it is indeed a valid register
1257 name, advance CCP over it and return the reg_entry structure;
1258 otherwise return NULL. Does not issue diagnostics. */
1260 static struct reg_entry
*
1261 arm_reg_parse_multi (char **ccp
)
1265 struct reg_entry
*reg
;
1267 skip_whitespace (start
);
1269 #ifdef REGISTER_PREFIX
1270 if (*start
!= REGISTER_PREFIX
)
1274 #ifdef OPTIONAL_REGISTER_PREFIX
1275 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1280 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1285 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1287 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1297 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1298 enum arm_reg_type type
)
1300 /* Alternative syntaxes are accepted for a few register classes. */
1307 /* Generic coprocessor register names are allowed for these. */
1308 if (reg
&& reg
->type
== REG_TYPE_CN
)
1313 /* For backward compatibility, a bare number is valid here. */
1315 unsigned long processor
= strtoul (start
, ccp
, 10);
1316 if (*ccp
!= start
&& processor
<= 15)
1321 case REG_TYPE_MMXWC
:
1322 /* WC includes WCG. ??? I'm not sure this is true for all
1323 instructions that take WC registers. */
1324 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1335 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1336 return value is the register number or FAIL. */
1339 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1342 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1345 /* Do not allow a scalar (reg+index) to parse as a register. */
1346 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1349 if (reg
&& reg
->type
== type
)
1352 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1359 /* Parse a Neon type specifier. *STR should point at the leading '.'
1360 character. Does no verification at this stage that the type fits the opcode
1367 Can all be legally parsed by this function.
1369 Fills in neon_type struct pointer with parsed information, and updates STR
1370 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1371 type, FAIL if not. */
1374 parse_neon_type (struct neon_type
*type
, char **str
)
1381 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1383 enum neon_el_type thistype
= NT_untyped
;
1384 unsigned thissize
= -1u;
1391 /* Just a size without an explicit type. */
1395 switch (TOLOWER (*ptr
))
1397 case 'i': thistype
= NT_integer
; break;
1398 case 'f': thistype
= NT_float
; break;
1399 case 'p': thistype
= NT_poly
; break;
1400 case 's': thistype
= NT_signed
; break;
1401 case 'u': thistype
= NT_unsigned
; break;
1403 thistype
= NT_float
;
1408 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1414 /* .f is an abbreviation for .f32. */
1415 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1420 thissize
= strtoul (ptr
, &ptr
, 10);
1422 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1425 as_bad (_("bad size %d in type specifier"), thissize
);
1433 type
->el
[type
->elems
].type
= thistype
;
1434 type
->el
[type
->elems
].size
= thissize
;
1439 /* Empty/missing type is not a successful parse. */
1440 if (type
->elems
== 0)
1448 /* Errors may be set multiple times during parsing or bit encoding
1449 (particularly in the Neon bits), but usually the earliest error which is set
1450 will be the most meaningful. Avoid overwriting it with later (cascading)
1451 errors by calling this function. */
1454 first_error (const char *err
)
1460 /* Parse a single type, e.g. ".s32", leading period included. */
1462 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1465 struct neon_type optype
;
1469 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1471 if (optype
.elems
== 1)
1472 *vectype
= optype
.el
[0];
1475 first_error (_("only one type should be specified for operand"));
1481 first_error (_("vector type expected"));
1493 /* Special meanings for indices (which have a range of 0-7), which will fit into
1496 #define NEON_ALL_LANES 15
1497 #define NEON_INTERLEAVE_LANES 14
1499 /* Parse either a register or a scalar, with an optional type. Return the
1500 register number, and optionally fill in the actual type of the register
1501 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1502 type/index information in *TYPEINFO. */
1505 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1506 enum arm_reg_type
*rtype
,
1507 struct neon_typed_alias
*typeinfo
)
1510 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1511 struct neon_typed_alias atype
;
1512 struct neon_type_el parsetype
;
1516 atype
.eltype
.type
= NT_invtype
;
1517 atype
.eltype
.size
= -1;
1519 /* Try alternate syntax for some types of register. Note these are mutually
1520 exclusive with the Neon syntax extensions. */
1523 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1531 /* Undo polymorphism when a set of register types may be accepted. */
1532 if ((type
== REG_TYPE_NDQ
1533 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1534 || (type
== REG_TYPE_VFSD
1535 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1536 || (type
== REG_TYPE_NSDQ
1537 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1538 || reg
->type
== REG_TYPE_NQ
))
1539 || (type
== REG_TYPE_NSD
1540 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1541 || (type
== REG_TYPE_MMXWC
1542 && (reg
->type
== REG_TYPE_MMXWCG
)))
1543 type
= (enum arm_reg_type
) reg
->type
;
1545 if (type
!= reg
->type
)
1551 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1553 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1555 first_error (_("can't redefine type for operand"));
1558 atype
.defined
|= NTA_HASTYPE
;
1559 atype
.eltype
= parsetype
;
1562 if (skip_past_char (&str
, '[') == SUCCESS
)
1564 if (type
!= REG_TYPE_VFD
1565 && !(type
== REG_TYPE_VFS
1566 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
)))
1568 first_error (_("only D registers may be indexed"));
1572 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1574 first_error (_("can't change index for operand"));
1578 atype
.defined
|= NTA_HASINDEX
;
1580 if (skip_past_char (&str
, ']') == SUCCESS
)
1581 atype
.index
= NEON_ALL_LANES
;
1586 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1588 if (exp
.X_op
!= O_constant
)
1590 first_error (_("constant expression required"));
1594 if (skip_past_char (&str
, ']') == FAIL
)
1597 atype
.index
= exp
.X_add_number
;
1612 /* Like arm_reg_parse, but also allow the following extra features:
1613 - If RTYPE is non-zero, return the (possibly restricted) type of the
1614 register (e.g. Neon double or quad reg when either has been requested).
1615 - If this is a Neon vector type with additional type information, fill
1616 in the struct pointed to by VECTYPE (if non-NULL).
1617 This function will fault on encountering a scalar. */
1620 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1621 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1623 struct neon_typed_alias atype
;
1625 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1630 /* Do not allow regname(... to parse as a register. */
1634 /* Do not allow a scalar (reg+index) to parse as a register. */
1635 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1637 first_error (_("register operand expected, but got scalar"));
1642 *vectype
= atype
.eltype
;
1649 #define NEON_SCALAR_REG(X) ((X) >> 4)
1650 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1652 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1653 have enough information to be able to do a good job bounds-checking. So, we
1654 just do easy checks here, and do further checks later. */
1657 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1661 struct neon_typed_alias atype
;
1662 enum arm_reg_type reg_type
= REG_TYPE_VFD
;
1665 reg_type
= REG_TYPE_VFS
;
1667 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1669 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1672 if (atype
.index
== NEON_ALL_LANES
)
1674 first_error (_("scalar must have an index"));
1677 else if (atype
.index
>= 64 / elsize
)
1679 first_error (_("scalar index out of range"));
1684 *type
= atype
.eltype
;
1688 return reg
* 16 + atype
.index
;
1691 /* Types of registers in a list. */
1704 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1707 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1713 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1715 /* We come back here if we get ranges concatenated by '+' or '|'. */
1718 skip_whitespace (str
);
1731 const char apsr_str
[] = "apsr";
1732 int apsr_str_len
= strlen (apsr_str
);
1734 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1735 if (etype
== REGLIST_CLRM
)
1737 if (reg
== REG_SP
|| reg
== REG_PC
)
1739 else if (reg
== FAIL
1740 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1741 && !ISALPHA (*(str
+ apsr_str_len
)))
1744 str
+= apsr_str_len
;
1749 first_error (_("r0-r12, lr or APSR expected"));
1753 else /* etype == REGLIST_RN. */
1757 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1768 first_error (_("bad range in register list"));
1772 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1774 if (range
& (1 << i
))
1776 (_("Warning: duplicated register (r%d) in register list"),
1784 if (range
& (1 << reg
))
1785 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1787 else if (reg
<= cur_reg
)
1788 as_tsktsk (_("Warning: register range not in ascending order"));
1793 while (skip_past_comma (&str
) != FAIL
1794 || (in_range
= 1, *str
++ == '-'));
1797 if (skip_past_char (&str
, '}') == FAIL
)
1799 first_error (_("missing `}'"));
1803 else if (etype
== REGLIST_RN
)
1807 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1810 if (exp
.X_op
== O_constant
)
1812 if (exp
.X_add_number
1813 != (exp
.X_add_number
& 0x0000ffff))
1815 inst
.error
= _("invalid register mask");
1819 if ((range
& exp
.X_add_number
) != 0)
1821 int regno
= range
& exp
.X_add_number
;
1824 regno
= (1 << regno
) - 1;
1826 (_("Warning: duplicated register (r%d) in register list"),
1830 range
|= exp
.X_add_number
;
1834 if (inst
.relocs
[0].type
!= 0)
1836 inst
.error
= _("expression too complex");
1840 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1841 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1842 inst
.relocs
[0].pc_rel
= 0;
1846 if (*str
== '|' || *str
== '+')
1852 while (another_range
);
1858 /* Parse a VFP register list. If the string is invalid return FAIL.
1859 Otherwise return the number of registers, and set PBASE to the first
1860 register. Parses registers of type ETYPE.
1861 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1862 - Q registers can be used to specify pairs of D registers
1863 - { } can be omitted from around a singleton register list
1864 FIXME: This is not implemented, as it would require backtracking in
1867 This could be done (the meaning isn't really ambiguous), but doesn't
1868 fit in well with the current parsing framework.
1869 - 32 D registers may be used (also true for VFPv3).
1870 FIXME: Types are ignored in these register lists, which is probably a
1874 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1875 bfd_boolean
*partial_match
)
1880 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1884 unsigned long mask
= 0;
1886 bfd_boolean vpr_seen
= FALSE
;
1887 bfd_boolean expect_vpr
=
1888 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
1890 if (skip_past_char (&str
, '{') == FAIL
)
1892 inst
.error
= _("expecting {");
1899 case REGLIST_VFP_S_VPR
:
1900 regtype
= REG_TYPE_VFS
;
1905 case REGLIST_VFP_D_VPR
:
1906 regtype
= REG_TYPE_VFD
;
1909 case REGLIST_NEON_D
:
1910 regtype
= REG_TYPE_NDQ
;
1917 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
1919 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1920 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1924 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1927 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1934 base_reg
= max_regs
;
1935 *partial_match
= FALSE
;
1939 int setmask
= 1, addregs
= 1;
1940 const char vpr_str
[] = "vpr";
1941 int vpr_str_len
= strlen (vpr_str
);
1943 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1947 if (new_base
== FAIL
1948 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
1949 && !ISALPHA (*(str
+ vpr_str_len
))
1955 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
1959 first_error (_("VPR expected last"));
1962 else if (new_base
== FAIL
)
1964 if (regtype
== REG_TYPE_VFS
)
1965 first_error (_("VFP single precision register or VPR "
1967 else /* regtype == REG_TYPE_VFD. */
1968 first_error (_("VFP/Neon double precision register or VPR "
1973 else if (new_base
== FAIL
)
1975 first_error (_(reg_expected_msgs
[regtype
]));
1979 *partial_match
= TRUE
;
1983 if (new_base
>= max_regs
)
1985 first_error (_("register out of range in list"));
1989 /* Note: a value of 2 * n is returned for the register Q<n>. */
1990 if (regtype
== REG_TYPE_NQ
)
1996 if (new_base
< base_reg
)
1997 base_reg
= new_base
;
1999 if (mask
& (setmask
<< new_base
))
2001 first_error (_("invalid register list"));
2005 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2007 as_tsktsk (_("register list not in ascending order"));
2011 mask
|= setmask
<< new_base
;
2014 if (*str
== '-') /* We have the start of a range expression */
2020 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2023 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2027 if (high_range
>= max_regs
)
2029 first_error (_("register out of range in list"));
2033 if (regtype
== REG_TYPE_NQ
)
2034 high_range
= high_range
+ 1;
2036 if (high_range
<= new_base
)
2038 inst
.error
= _("register range not in ascending order");
2042 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2044 if (mask
& (setmask
<< new_base
))
2046 inst
.error
= _("invalid register list");
2050 mask
|= setmask
<< new_base
;
2055 while (skip_past_comma (&str
) != FAIL
);
2059 /* Sanity check -- should have raised a parse error above. */
2060 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2065 if (expect_vpr
&& !vpr_seen
)
2067 first_error (_("VPR expected last"));
2071 /* Final test -- the registers must be consecutive. */
2073 for (i
= 0; i
< count
; i
++)
2075 if ((mask
& (1u << i
)) == 0)
2077 inst
.error
= _("non-contiguous register range");
2087 /* True if two alias types are the same. */
2090 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2098 if (a
->defined
!= b
->defined
)
2101 if ((a
->defined
& NTA_HASTYPE
) != 0
2102 && (a
->eltype
.type
!= b
->eltype
.type
2103 || a
->eltype
.size
!= b
->eltype
.size
))
2106 if ((a
->defined
& NTA_HASINDEX
) != 0
2107 && (a
->index
!= b
->index
))
2113 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2114 The base register is put in *PBASE.
2115 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2117 The register stride (minus one) is put in bit 4 of the return value.
2118 Bits [6:5] encode the list length (minus one).
2119 The type of the list elements is put in *ELTYPE, if non-NULL. */
2121 #define NEON_LANE(X) ((X) & 0xf)
2122 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2123 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2126 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2127 struct neon_type_el
*eltype
)
2134 int leading_brace
= 0;
2135 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2136 const char *const incr_error
= _("register stride must be 1 or 2");
2137 const char *const type_error
= _("mismatched element/structure types in list");
2138 struct neon_typed_alias firsttype
;
2139 firsttype
.defined
= 0;
2140 firsttype
.eltype
.type
= NT_invtype
;
2141 firsttype
.eltype
.size
= -1;
2142 firsttype
.index
= -1;
2144 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2149 struct neon_typed_alias atype
;
2150 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2154 first_error (_(reg_expected_msgs
[rtype
]));
2161 if (rtype
== REG_TYPE_NQ
)
2167 else if (reg_incr
== -1)
2169 reg_incr
= getreg
- base_reg
;
2170 if (reg_incr
< 1 || reg_incr
> 2)
2172 first_error (_(incr_error
));
2176 else if (getreg
!= base_reg
+ reg_incr
* count
)
2178 first_error (_(incr_error
));
2182 if (! neon_alias_types_same (&atype
, &firsttype
))
2184 first_error (_(type_error
));
2188 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2192 struct neon_typed_alias htype
;
2193 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2195 lane
= NEON_INTERLEAVE_LANES
;
2196 else if (lane
!= NEON_INTERLEAVE_LANES
)
2198 first_error (_(type_error
));
2203 else if (reg_incr
!= 1)
2205 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2209 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2212 first_error (_(reg_expected_msgs
[rtype
]));
2215 if (! neon_alias_types_same (&htype
, &firsttype
))
2217 first_error (_(type_error
));
2220 count
+= hireg
+ dregs
- getreg
;
2224 /* If we're using Q registers, we can't use [] or [n] syntax. */
2225 if (rtype
== REG_TYPE_NQ
)
2231 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2235 else if (lane
!= atype
.index
)
2237 first_error (_(type_error
));
2241 else if (lane
== -1)
2242 lane
= NEON_INTERLEAVE_LANES
;
2243 else if (lane
!= NEON_INTERLEAVE_LANES
)
2245 first_error (_(type_error
));
2250 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2252 /* No lane set by [x]. We must be interleaving structures. */
2254 lane
= NEON_INTERLEAVE_LANES
;
2257 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2258 || (count
> 1 && reg_incr
== -1))
2260 first_error (_("error parsing element/structure list"));
2264 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2266 first_error (_("expected }"));
2274 *eltype
= firsttype
.eltype
;
2279 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2282 /* Parse an explicit relocation suffix on an expression. This is
2283 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2284 arm_reloc_hsh contains no entries, so this function can only
2285 succeed if there is no () after the word. Returns -1 on error,
2286 BFD_RELOC_UNUSED if there wasn't any suffix. */
2289 parse_reloc (char **str
)
2291 struct reloc_entry
*r
;
2295 return BFD_RELOC_UNUSED
;
2300 while (*q
&& *q
!= ')' && *q
!= ',')
2305 if ((r
= (struct reloc_entry
*)
2306 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2313 /* Directives: register aliases. */
2315 static struct reg_entry
*
2316 insert_reg_alias (char *str
, unsigned number
, int type
)
2318 struct reg_entry
*new_reg
;
2321 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2323 if (new_reg
->builtin
)
2324 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2326 /* Only warn about a redefinition if it's not defined as the
2328 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2329 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2334 name
= xstrdup (str
);
2335 new_reg
= XNEW (struct reg_entry
);
2337 new_reg
->name
= name
;
2338 new_reg
->number
= number
;
2339 new_reg
->type
= type
;
2340 new_reg
->builtin
= FALSE
;
2341 new_reg
->neon
= NULL
;
2343 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2350 insert_neon_reg_alias (char *str
, int number
, int type
,
2351 struct neon_typed_alias
*atype
)
2353 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2357 first_error (_("attempt to redefine typed alias"));
2363 reg
->neon
= XNEW (struct neon_typed_alias
);
2364 *reg
->neon
= *atype
;
2368 /* Look for the .req directive. This is of the form:
2370 new_register_name .req existing_register_name
2372 If we find one, or if it looks sufficiently like one that we want to
2373 handle any error here, return TRUE. Otherwise return FALSE. */
2376 create_register_alias (char * newname
, char *p
)
2378 struct reg_entry
*old
;
2379 char *oldname
, *nbuf
;
2382 /* The input scrubber ensures that whitespace after the mnemonic is
2383 collapsed to single spaces. */
2385 if (strncmp (oldname
, " .req ", 6) != 0)
2389 if (*oldname
== '\0')
2392 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2395 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2399 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2400 the desired alias name, and p points to its end. If not, then
2401 the desired alias name is in the global original_case_string. */
2402 #ifdef TC_CASE_SENSITIVE
2405 newname
= original_case_string
;
2406 nlen
= strlen (newname
);
2409 nbuf
= xmemdup0 (newname
, nlen
);
2411 /* Create aliases under the new name as stated; an all-lowercase
2412 version of the new name; and an all-uppercase version of the new
2414 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2416 for (p
= nbuf
; *p
; p
++)
2419 if (strncmp (nbuf
, newname
, nlen
))
2421 /* If this attempt to create an additional alias fails, do not bother
2422 trying to create the all-lower case alias. We will fail and issue
2423 a second, duplicate error message. This situation arises when the
2424 programmer does something like:
2427 The second .req creates the "Foo" alias but then fails to create
2428 the artificial FOO alias because it has already been created by the
2430 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2437 for (p
= nbuf
; *p
; p
++)
2440 if (strncmp (nbuf
, newname
, nlen
))
2441 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2448 /* Create a Neon typed/indexed register alias using directives, e.g.:
2453 These typed registers can be used instead of the types specified after the
2454 Neon mnemonic, so long as all operands given have types. Types can also be
2455 specified directly, e.g.:
2456 vadd d0.s32, d1.s32, d2.s32 */
2459 create_neon_reg_alias (char *newname
, char *p
)
2461 enum arm_reg_type basetype
;
2462 struct reg_entry
*basereg
;
2463 struct reg_entry mybasereg
;
2464 struct neon_type ntype
;
2465 struct neon_typed_alias typeinfo
;
2466 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2469 typeinfo
.defined
= 0;
2470 typeinfo
.eltype
.type
= NT_invtype
;
2471 typeinfo
.eltype
.size
= -1;
2472 typeinfo
.index
= -1;
2476 if (strncmp (p
, " .dn ", 5) == 0)
2477 basetype
= REG_TYPE_VFD
;
2478 else if (strncmp (p
, " .qn ", 5) == 0)
2479 basetype
= REG_TYPE_NQ
;
2488 basereg
= arm_reg_parse_multi (&p
);
2490 if (basereg
&& basereg
->type
!= basetype
)
2492 as_bad (_("bad type for register"));
2496 if (basereg
== NULL
)
2499 /* Try parsing as an integer. */
2500 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2501 if (exp
.X_op
!= O_constant
)
2503 as_bad (_("expression must be constant"));
2506 basereg
= &mybasereg
;
2507 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2513 typeinfo
= *basereg
->neon
;
2515 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2517 /* We got a type. */
2518 if (typeinfo
.defined
& NTA_HASTYPE
)
2520 as_bad (_("can't redefine the type of a register alias"));
2524 typeinfo
.defined
|= NTA_HASTYPE
;
2525 if (ntype
.elems
!= 1)
2527 as_bad (_("you must specify a single type only"));
2530 typeinfo
.eltype
= ntype
.el
[0];
2533 if (skip_past_char (&p
, '[') == SUCCESS
)
2536 /* We got a scalar index. */
2538 if (typeinfo
.defined
& NTA_HASINDEX
)
2540 as_bad (_("can't redefine the index of a scalar alias"));
2544 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2546 if (exp
.X_op
!= O_constant
)
2548 as_bad (_("scalar index must be constant"));
2552 typeinfo
.defined
|= NTA_HASINDEX
;
2553 typeinfo
.index
= exp
.X_add_number
;
2555 if (skip_past_char (&p
, ']') == FAIL
)
2557 as_bad (_("expecting ]"));
2562 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2563 the desired alias name, and p points to its end. If not, then
2564 the desired alias name is in the global original_case_string. */
2565 #ifdef TC_CASE_SENSITIVE
2566 namelen
= nameend
- newname
;
2568 newname
= original_case_string
;
2569 namelen
= strlen (newname
);
2572 namebuf
= xmemdup0 (newname
, namelen
);
2574 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2575 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2577 /* Insert name in all uppercase. */
2578 for (p
= namebuf
; *p
; p
++)
2581 if (strncmp (namebuf
, newname
, namelen
))
2582 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2583 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2585 /* Insert name in all lowercase. */
2586 for (p
= namebuf
; *p
; p
++)
2589 if (strncmp (namebuf
, newname
, namelen
))
2590 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2591 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2597 /* Should never be called, as .req goes between the alias and the
2598 register name, not at the beginning of the line. */
2601 s_req (int a ATTRIBUTE_UNUSED
)
2603 as_bad (_("invalid syntax for .req directive"));
2607 s_dn (int a ATTRIBUTE_UNUSED
)
2609 as_bad (_("invalid syntax for .dn directive"));
2613 s_qn (int a ATTRIBUTE_UNUSED
)
2615 as_bad (_("invalid syntax for .qn directive"));
2618 /* The .unreq directive deletes an alias which was previously defined
2619 by .req. For example:
2625 s_unreq (int a ATTRIBUTE_UNUSED
)
2630 name
= input_line_pointer
;
2632 while (*input_line_pointer
!= 0
2633 && *input_line_pointer
!= ' '
2634 && *input_line_pointer
!= '\n')
2635 ++input_line_pointer
;
2637 saved_char
= *input_line_pointer
;
2638 *input_line_pointer
= 0;
2641 as_bad (_("invalid syntax for .unreq directive"));
2644 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2648 as_bad (_("unknown register alias '%s'"), name
);
2649 else if (reg
->builtin
)
2650 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2657 hash_delete (arm_reg_hsh
, name
, FALSE
);
2658 free ((char *) reg
->name
);
2663 /* Also locate the all upper case and all lower case versions.
2664 Do not complain if we cannot find one or the other as it
2665 was probably deleted above. */
2667 nbuf
= strdup (name
);
2668 for (p
= nbuf
; *p
; p
++)
2670 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2673 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2674 free ((char *) reg
->name
);
2680 for (p
= nbuf
; *p
; p
++)
2682 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2685 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2686 free ((char *) reg
->name
);
2696 *input_line_pointer
= saved_char
;
2697 demand_empty_rest_of_line ();
2700 /* Directives: Instruction set selection. */
2703 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2704 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2705 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2706 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2708 /* Create a new mapping symbol for the transition to STATE. */
2711 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2714 const char * symname
;
2721 type
= BSF_NO_FLAGS
;
2725 type
= BSF_NO_FLAGS
;
2729 type
= BSF_NO_FLAGS
;
2735 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2736 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2741 THUMB_SET_FUNC (symbolP
, 0);
2742 ARM_SET_THUMB (symbolP
, 0);
2743 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2747 THUMB_SET_FUNC (symbolP
, 1);
2748 ARM_SET_THUMB (symbolP
, 1);
2749 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2757 /* Save the mapping symbols for future reference. Also check that
2758 we do not place two mapping symbols at the same offset within a
2759 frag. We'll handle overlap between frags in
2760 check_mapping_symbols.
2762 If .fill or other data filling directive generates zero sized data,
2763 the mapping symbol for the following code will have the same value
2764 as the one generated for the data filling directive. In this case,
2765 we replace the old symbol with the new one at the same address. */
2768 if (frag
->tc_frag_data
.first_map
!= NULL
)
2770 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2771 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2773 frag
->tc_frag_data
.first_map
= symbolP
;
2775 if (frag
->tc_frag_data
.last_map
!= NULL
)
2777 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2778 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2779 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2781 frag
->tc_frag_data
.last_map
= symbolP
;
2784 /* We must sometimes convert a region marked as code to data during
2785 code alignment, if an odd number of bytes have to be padded. The
2786 code mapping symbol is pushed to an aligned address. */
2789 insert_data_mapping_symbol (enum mstate state
,
2790 valueT value
, fragS
*frag
, offsetT bytes
)
2792 /* If there was already a mapping symbol, remove it. */
2793 if (frag
->tc_frag_data
.last_map
!= NULL
2794 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2796 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2800 know (frag
->tc_frag_data
.first_map
== symp
);
2801 frag
->tc_frag_data
.first_map
= NULL
;
2803 frag
->tc_frag_data
.last_map
= NULL
;
2804 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2807 make_mapping_symbol (MAP_DATA
, value
, frag
);
2808 make_mapping_symbol (state
, value
+ bytes
, frag
);
2811 static void mapping_state_2 (enum mstate state
, int max_chars
);
2813 /* Set the mapping state to STATE. Only call this when about to
2814 emit some STATE bytes to the file. */
2816 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2818 mapping_state (enum mstate state
)
2820 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2822 if (mapstate
== state
)
2823 /* The mapping symbol has already been emitted.
2824 There is nothing else to do. */
2827 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2829 All ARM instructions require 4-byte alignment.
2830 (Almost) all Thumb instructions require 2-byte alignment.
2832 When emitting instructions into any section, mark the section
2835 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2836 but themselves require 2-byte alignment; this applies to some
2837 PC- relative forms. However, these cases will involve implicit
2838 literal pool generation or an explicit .align >=2, both of
2839 which will cause the section to me marked with sufficient
2840 alignment. Thus, we don't handle those cases here. */
2841 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2843 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2844 /* This case will be evaluated later. */
2847 mapping_state_2 (state
, 0);
2850 /* Same as mapping_state, but MAX_CHARS bytes have already been
2851 allocated. Put the mapping symbol that far back. */
2854 mapping_state_2 (enum mstate state
, int max_chars
)
2856 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2858 if (!SEG_NORMAL (now_seg
))
2861 if (mapstate
== state
)
2862 /* The mapping symbol has already been emitted.
2863 There is nothing else to do. */
2866 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2867 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2869 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2870 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2873 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2876 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2877 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2881 #define mapping_state(x) ((void)0)
2882 #define mapping_state_2(x, y) ((void)0)
2885 /* Find the real, Thumb encoded start of a Thumb function. */
2889 find_real_start (symbolS
* symbolP
)
2892 const char * name
= S_GET_NAME (symbolP
);
2893 symbolS
* new_target
;
2895 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2896 #define STUB_NAME ".real_start_of"
2901 /* The compiler may generate BL instructions to local labels because
2902 it needs to perform a branch to a far away location. These labels
2903 do not have a corresponding ".real_start_of" label. We check
2904 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2905 the ".real_start_of" convention for nonlocal branches. */
2906 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2909 real_start
= concat (STUB_NAME
, name
, NULL
);
2910 new_target
= symbol_find (real_start
);
2913 if (new_target
== NULL
)
2915 as_warn (_("Failed to find real start of function: %s\n"), name
);
2916 new_target
= symbolP
;
2924 opcode_select (int width
)
2931 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2932 as_bad (_("selected processor does not support THUMB opcodes"));
2935 /* No need to force the alignment, since we will have been
2936 coming from ARM mode, which is word-aligned. */
2937 record_alignment (now_seg
, 1);
2944 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2945 as_bad (_("selected processor does not support ARM opcodes"));
2950 frag_align (2, 0, 0);
2952 record_alignment (now_seg
, 1);
2957 as_bad (_("invalid instruction size selected (%d)"), width
);
2962 s_arm (int ignore ATTRIBUTE_UNUSED
)
2965 demand_empty_rest_of_line ();
2969 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2972 demand_empty_rest_of_line ();
2976 s_code (int unused ATTRIBUTE_UNUSED
)
2980 temp
= get_absolute_expression ();
2985 opcode_select (temp
);
2989 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2994 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2996 /* If we are not already in thumb mode go into it, EVEN if
2997 the target processor does not support thumb instructions.
2998 This is used by gcc/config/arm/lib1funcs.asm for example
2999 to compile interworking support functions even if the
3000 target processor should not support interworking. */
3004 record_alignment (now_seg
, 1);
3007 demand_empty_rest_of_line ();
3011 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3015 /* The following label is the name/address of the start of a Thumb function.
3016 We need to know this for the interworking support. */
3017 label_is_thumb_function_name
= TRUE
;
3020 /* Perform a .set directive, but also mark the alias as
3021 being a thumb function. */
3024 s_thumb_set (int equiv
)
3026 /* XXX the following is a duplicate of the code for s_set() in read.c
3027 We cannot just call that code as we need to get at the symbol that
3034 /* Especial apologies for the random logic:
3035 This just grew, and could be parsed much more simply!
3037 delim
= get_symbol_name (& name
);
3038 end_name
= input_line_pointer
;
3039 (void) restore_line_pointer (delim
);
3041 if (*input_line_pointer
!= ',')
3044 as_bad (_("expected comma after name \"%s\""), name
);
3046 ignore_rest_of_line ();
3050 input_line_pointer
++;
3053 if (name
[0] == '.' && name
[1] == '\0')
3055 /* XXX - this should not happen to .thumb_set. */
3059 if ((symbolP
= symbol_find (name
)) == NULL
3060 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3063 /* When doing symbol listings, play games with dummy fragments living
3064 outside the normal fragment chain to record the file and line info
3066 if (listing
& LISTING_SYMBOLS
)
3068 extern struct list_info_struct
* listing_tail
;
3069 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3071 memset (dummy_frag
, 0, sizeof (fragS
));
3072 dummy_frag
->fr_type
= rs_fill
;
3073 dummy_frag
->line
= listing_tail
;
3074 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3075 dummy_frag
->fr_symbol
= symbolP
;
3079 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3082 /* "set" symbols are local unless otherwise specified. */
3083 SF_SET_LOCAL (symbolP
);
3084 #endif /* OBJ_COFF */
3085 } /* Make a new symbol. */
3087 symbol_table_insert (symbolP
);
3092 && S_IS_DEFINED (symbolP
)
3093 && S_GET_SEGMENT (symbolP
) != reg_section
)
3094 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3096 pseudo_set (symbolP
);
3098 demand_empty_rest_of_line ();
3100 /* XXX Now we come to the Thumb specific bit of code. */
3102 THUMB_SET_FUNC (symbolP
, 1);
3103 ARM_SET_THUMB (symbolP
, 1);
3104 #if defined OBJ_ELF || defined OBJ_COFF
3105 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3109 /* Directives: Mode selection. */
3111 /* .syntax [unified|divided] - choose the new unified syntax
3112 (same for Arm and Thumb encoding, modulo slight differences in what
3113 can be represented) or the old divergent syntax for each mode. */
3115 s_syntax (int unused ATTRIBUTE_UNUSED
)
3119 delim
= get_symbol_name (& name
);
3121 if (!strcasecmp (name
, "unified"))
3122 unified_syntax
= TRUE
;
3123 else if (!strcasecmp (name
, "divided"))
3124 unified_syntax
= FALSE
;
3127 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3130 (void) restore_line_pointer (delim
);
3131 demand_empty_rest_of_line ();
3134 /* Directives: sectioning and alignment. */
3137 s_bss (int ignore ATTRIBUTE_UNUSED
)
3139 /* We don't support putting frags in the BSS segment, we fake it by
3140 marking in_bss, then looking at s_skip for clues. */
3141 subseg_set (bss_section
, 0);
3142 demand_empty_rest_of_line ();
3144 #ifdef md_elf_section_change_hook
3145 md_elf_section_change_hook ();
3150 s_even (int ignore ATTRIBUTE_UNUSED
)
3152 /* Never make frag if expect extra pass. */
3154 frag_align (1, 0, 0);
3156 record_alignment (now_seg
, 1);
3158 demand_empty_rest_of_line ();
3161 /* Directives: CodeComposer Studio. */
3163 /* .ref (for CodeComposer Studio syntax only). */
3165 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3167 if (codecomposer_syntax
)
3168 ignore_rest_of_line ();
3170 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3173 /* If name is not NULL, then it is used for marking the beginning of a
3174 function, whereas if it is NULL then it means the function end. */
3176 asmfunc_debug (const char * name
)
3178 static const char * last_name
= NULL
;
3182 gas_assert (last_name
== NULL
);
3185 if (debug_type
== DEBUG_STABS
)
3186 stabs_generate_asm_func (name
, name
);
3190 gas_assert (last_name
!= NULL
);
3192 if (debug_type
== DEBUG_STABS
)
3193 stabs_generate_asm_endfunc (last_name
, last_name
);
3200 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3202 if (codecomposer_syntax
)
3204 switch (asmfunc_state
)
3206 case OUTSIDE_ASMFUNC
:
3207 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3210 case WAITING_ASMFUNC_NAME
:
3211 as_bad (_(".asmfunc repeated."));
3214 case WAITING_ENDASMFUNC
:
3215 as_bad (_(".asmfunc without function."));
3218 demand_empty_rest_of_line ();
3221 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3225 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3227 if (codecomposer_syntax
)
3229 switch (asmfunc_state
)
3231 case OUTSIDE_ASMFUNC
:
3232 as_bad (_(".endasmfunc without a .asmfunc."));
3235 case WAITING_ASMFUNC_NAME
:
3236 as_bad (_(".endasmfunc without function."));
3239 case WAITING_ENDASMFUNC
:
3240 asmfunc_state
= OUTSIDE_ASMFUNC
;
3241 asmfunc_debug (NULL
);
3244 demand_empty_rest_of_line ();
3247 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3251 s_ccs_def (int name
)
3253 if (codecomposer_syntax
)
3256 as_bad (_(".def pseudo-op only available with -mccs flag."));
3259 /* Directives: Literal pools. */
3261 static literal_pool
*
3262 find_literal_pool (void)
3264 literal_pool
* pool
;
3266 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3268 if (pool
->section
== now_seg
3269 && pool
->sub_section
== now_subseg
)
3276 static literal_pool
*
3277 find_or_make_literal_pool (void)
3279 /* Next literal pool ID number. */
3280 static unsigned int latest_pool_num
= 1;
3281 literal_pool
* pool
;
3283 pool
= find_literal_pool ();
3287 /* Create a new pool. */
3288 pool
= XNEW (literal_pool
);
3292 pool
->next_free_entry
= 0;
3293 pool
->section
= now_seg
;
3294 pool
->sub_section
= now_subseg
;
3295 pool
->next
= list_of_pools
;
3296 pool
->symbol
= NULL
;
3297 pool
->alignment
= 2;
3299 /* Add it to the list. */
3300 list_of_pools
= pool
;
3303 /* New pools, and emptied pools, will have a NULL symbol. */
3304 if (pool
->symbol
== NULL
)
3306 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3307 (valueT
) 0, &zero_address_frag
);
3308 pool
->id
= latest_pool_num
++;
3315 /* Add the literal in the global 'inst'
3316 structure to the relevant literal pool. */
3319 add_to_lit_pool (unsigned int nbytes
)
3321 #define PADDING_SLOT 0x1
3322 #define LIT_ENTRY_SIZE_MASK 0xFF
3323 literal_pool
* pool
;
3324 unsigned int entry
, pool_size
= 0;
3325 bfd_boolean padding_slot_p
= FALSE
;
3331 imm1
= inst
.operands
[1].imm
;
3332 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3333 : inst
.relocs
[0].exp
.X_unsigned
? 0
3334 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3335 if (target_big_endian
)
3338 imm2
= inst
.operands
[1].imm
;
3342 pool
= find_or_make_literal_pool ();
3344 /* Check if this literal value is already in the pool. */
3345 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3349 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3350 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3351 && (pool
->literals
[entry
].X_add_number
3352 == inst
.relocs
[0].exp
.X_add_number
)
3353 && (pool
->literals
[entry
].X_md
== nbytes
)
3354 && (pool
->literals
[entry
].X_unsigned
3355 == inst
.relocs
[0].exp
.X_unsigned
))
3358 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3359 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3360 && (pool
->literals
[entry
].X_add_number
3361 == inst
.relocs
[0].exp
.X_add_number
)
3362 && (pool
->literals
[entry
].X_add_symbol
3363 == inst
.relocs
[0].exp
.X_add_symbol
)
3364 && (pool
->literals
[entry
].X_op_symbol
3365 == inst
.relocs
[0].exp
.X_op_symbol
)
3366 && (pool
->literals
[entry
].X_md
== nbytes
))
3369 else if ((nbytes
== 8)
3370 && !(pool_size
& 0x7)
3371 && ((entry
+ 1) != pool
->next_free_entry
)
3372 && (pool
->literals
[entry
].X_op
== O_constant
)
3373 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3374 && (pool
->literals
[entry
].X_unsigned
3375 == inst
.relocs
[0].exp
.X_unsigned
)
3376 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3377 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3378 && (pool
->literals
[entry
+ 1].X_unsigned
3379 == inst
.relocs
[0].exp
.X_unsigned
))
3382 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3383 if (padding_slot_p
&& (nbytes
== 4))
3389 /* Do we need to create a new entry? */
3390 if (entry
== pool
->next_free_entry
)
3392 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3394 inst
.error
= _("literal pool overflow");
3400 /* For 8-byte entries, we align to an 8-byte boundary,
3401 and split it into two 4-byte entries, because on 32-bit
3402 host, 8-byte constants are treated as big num, thus
3403 saved in "generic_bignum" which will be overwritten
3404 by later assignments.
3406 We also need to make sure there is enough space for
3409 We also check to make sure the literal operand is a
3411 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3412 || inst
.relocs
[0].exp
.X_op
== O_big
))
3414 inst
.error
= _("invalid type for literal pool");
3417 else if (pool_size
& 0x7)
3419 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3421 inst
.error
= _("literal pool overflow");
3425 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3426 pool
->literals
[entry
].X_op
= O_constant
;
3427 pool
->literals
[entry
].X_add_number
= 0;
3428 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3429 pool
->next_free_entry
+= 1;
3432 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3434 inst
.error
= _("literal pool overflow");
3438 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3439 pool
->literals
[entry
].X_op
= O_constant
;
3440 pool
->literals
[entry
].X_add_number
= imm1
;
3441 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3442 pool
->literals
[entry
++].X_md
= 4;
3443 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3444 pool
->literals
[entry
].X_op
= O_constant
;
3445 pool
->literals
[entry
].X_add_number
= imm2
;
3446 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3447 pool
->literals
[entry
].X_md
= 4;
3448 pool
->alignment
= 3;
3449 pool
->next_free_entry
+= 1;
3453 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3454 pool
->literals
[entry
].X_md
= 4;
3458 /* PR ld/12974: Record the location of the first source line to reference
3459 this entry in the literal pool. If it turns out during linking that the
3460 symbol does not exist we will be able to give an accurate line number for
3461 the (first use of the) missing reference. */
3462 if (debug_type
== DEBUG_DWARF2
)
3463 dwarf2_where (pool
->locs
+ entry
);
3465 pool
->next_free_entry
+= 1;
3467 else if (padding_slot_p
)
3469 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3470 pool
->literals
[entry
].X_md
= nbytes
;
3473 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3474 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3475 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3481 tc_start_label_without_colon (void)
3483 bfd_boolean ret
= TRUE
;
3485 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3487 const char *label
= input_line_pointer
;
3489 while (!is_end_of_line
[(int) label
[-1]])
3494 as_bad (_("Invalid label '%s'"), label
);
3498 asmfunc_debug (label
);
3500 asmfunc_state
= WAITING_ENDASMFUNC
;
3506 /* Can't use symbol_new here, so have to create a symbol and then at
3507 a later date assign it a value. That's what these functions do. */
3510 symbol_locate (symbolS
* symbolP
,
3511 const char * name
, /* It is copied, the caller can modify. */
3512 segT segment
, /* Segment identifier (SEG_<something>). */
3513 valueT valu
, /* Symbol value. */
3514 fragS
* frag
) /* Associated fragment. */
3517 char * preserved_copy_of_name
;
3519 name_length
= strlen (name
) + 1; /* +1 for \0. */
3520 obstack_grow (¬es
, name
, name_length
);
3521 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3523 #ifdef tc_canonicalize_symbol_name
3524 preserved_copy_of_name
=
3525 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3528 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3530 S_SET_SEGMENT (symbolP
, segment
);
3531 S_SET_VALUE (symbolP
, valu
);
3532 symbol_clear_list_pointers (symbolP
);
3534 symbol_set_frag (symbolP
, frag
);
3536 /* Link to end of symbol chain. */
3538 extern int symbol_table_frozen
;
3540 if (symbol_table_frozen
)
3544 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3546 obj_symbol_new_hook (symbolP
);
3548 #ifdef tc_symbol_new_hook
3549 tc_symbol_new_hook (symbolP
);
3553 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3554 #endif /* DEBUG_SYMS */
3558 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3561 literal_pool
* pool
;
3564 pool
= find_literal_pool ();
3566 || pool
->symbol
== NULL
3567 || pool
->next_free_entry
== 0)
3570 /* Align pool as you have word accesses.
3571 Only make a frag if we have to. */
3573 frag_align (pool
->alignment
, 0, 0);
3575 record_alignment (now_seg
, 2);
3578 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3579 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3581 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3583 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3584 (valueT
) frag_now_fix (), frag_now
);
3585 symbol_table_insert (pool
->symbol
);
3587 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3589 #if defined OBJ_COFF || defined OBJ_ELF
3590 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3593 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3596 if (debug_type
== DEBUG_DWARF2
)
3597 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3599 /* First output the expression in the instruction to the pool. */
3600 emit_expr (&(pool
->literals
[entry
]),
3601 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3604 /* Mark the pool as empty. */
3605 pool
->next_free_entry
= 0;
3606 pool
->symbol
= NULL
;
3610 /* Forward declarations for functions below, in the MD interface
3612 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3613 static valueT
create_unwind_entry (int);
3614 static void start_unwind_section (const segT
, int);
3615 static void add_unwind_opcode (valueT
, int);
3616 static void flush_pending_unwind (void);
3618 /* Directives: Data. */
3621 s_arm_elf_cons (int nbytes
)
3625 #ifdef md_flush_pending_output
3626 md_flush_pending_output ();
3629 if (is_it_end_of_statement ())
3631 demand_empty_rest_of_line ();
3635 #ifdef md_cons_align
3636 md_cons_align (nbytes
);
3639 mapping_state (MAP_DATA
);
3643 char *base
= input_line_pointer
;
3647 if (exp
.X_op
!= O_symbol
)
3648 emit_expr (&exp
, (unsigned int) nbytes
);
3651 char *before_reloc
= input_line_pointer
;
3652 reloc
= parse_reloc (&input_line_pointer
);
3655 as_bad (_("unrecognized relocation suffix"));
3656 ignore_rest_of_line ();
3659 else if (reloc
== BFD_RELOC_UNUSED
)
3660 emit_expr (&exp
, (unsigned int) nbytes
);
3663 reloc_howto_type
*howto
= (reloc_howto_type
*)
3664 bfd_reloc_type_lookup (stdoutput
,
3665 (bfd_reloc_code_real_type
) reloc
);
3666 int size
= bfd_get_reloc_size (howto
);
3668 if (reloc
== BFD_RELOC_ARM_PLT32
)
3670 as_bad (_("(plt) is only valid on branch targets"));
3671 reloc
= BFD_RELOC_UNUSED
;
3676 as_bad (ngettext ("%s relocations do not fit in %d byte",
3677 "%s relocations do not fit in %d bytes",
3679 howto
->name
, nbytes
);
3682 /* We've parsed an expression stopping at O_symbol.
3683 But there may be more expression left now that we
3684 have parsed the relocation marker. Parse it again.
3685 XXX Surely there is a cleaner way to do this. */
3686 char *p
= input_line_pointer
;
3688 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3690 memcpy (save_buf
, base
, input_line_pointer
- base
);
3691 memmove (base
+ (input_line_pointer
- before_reloc
),
3692 base
, before_reloc
- base
);
3694 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3696 memcpy (base
, save_buf
, p
- base
);
3698 offset
= nbytes
- size
;
3699 p
= frag_more (nbytes
);
3700 memset (p
, 0, nbytes
);
3701 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3702 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3708 while (*input_line_pointer
++ == ',');
3710 /* Put terminator back into stream. */
3711 input_line_pointer
--;
3712 demand_empty_rest_of_line ();
3715 /* Emit an expression containing a 32-bit thumb instruction.
3716 Implementation based on put_thumb32_insn. */
3719 emit_thumb32_expr (expressionS
* exp
)
3721 expressionS exp_high
= *exp
;
3723 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3724 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3725 exp
->X_add_number
&= 0xffff;
3726 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3729 /* Guess the instruction size based on the opcode. */
3732 thumb_insn_size (int opcode
)
3734 if ((unsigned int) opcode
< 0xe800u
)
3736 else if ((unsigned int) opcode
>= 0xe8000000u
)
3743 emit_insn (expressionS
*exp
, int nbytes
)
3747 if (exp
->X_op
== O_constant
)
3752 size
= thumb_insn_size (exp
->X_add_number
);
3756 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3758 as_bad (_(".inst.n operand too big. "\
3759 "Use .inst.w instead"));
3764 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3765 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3767 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3769 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3770 emit_thumb32_expr (exp
);
3772 emit_expr (exp
, (unsigned int) size
);
3774 it_fsm_post_encode ();
3778 as_bad (_("cannot determine Thumb instruction size. " \
3779 "Use .inst.n/.inst.w instead"));
3782 as_bad (_("constant expression required"));
3787 /* Like s_arm_elf_cons but do not use md_cons_align and
3788 set the mapping state to MAP_ARM/MAP_THUMB. */
3791 s_arm_elf_inst (int nbytes
)
3793 if (is_it_end_of_statement ())
3795 demand_empty_rest_of_line ();
3799 /* Calling mapping_state () here will not change ARM/THUMB,
3800 but will ensure not to be in DATA state. */
3803 mapping_state (MAP_THUMB
);
3808 as_bad (_("width suffixes are invalid in ARM mode"));
3809 ignore_rest_of_line ();
3815 mapping_state (MAP_ARM
);
3824 if (! emit_insn (& exp
, nbytes
))
3826 ignore_rest_of_line ();
3830 while (*input_line_pointer
++ == ',');
3832 /* Put terminator back into stream. */
3833 input_line_pointer
--;
3834 demand_empty_rest_of_line ();
3837 /* Parse a .rel31 directive. */
3840 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3847 if (*input_line_pointer
== '1')
3848 highbit
= 0x80000000;
3849 else if (*input_line_pointer
!= '0')
3850 as_bad (_("expected 0 or 1"));
3852 input_line_pointer
++;
3853 if (*input_line_pointer
!= ',')
3854 as_bad (_("missing comma"));
3855 input_line_pointer
++;
3857 #ifdef md_flush_pending_output
3858 md_flush_pending_output ();
3861 #ifdef md_cons_align
3865 mapping_state (MAP_DATA
);
3870 md_number_to_chars (p
, highbit
, 4);
3871 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3872 BFD_RELOC_ARM_PREL31
);
3874 demand_empty_rest_of_line ();
3877 /* Directives: AEABI stack-unwind tables. */
3879 /* Parse an unwind_fnstart directive. Simply records the current location. */
3882 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3884 demand_empty_rest_of_line ();
3885 if (unwind
.proc_start
)
3887 as_bad (_("duplicate .fnstart directive"));
3891 /* Mark the start of the function. */
3892 unwind
.proc_start
= expr_build_dot ();
3894 /* Reset the rest of the unwind info. */
3895 unwind
.opcode_count
= 0;
3896 unwind
.table_entry
= NULL
;
3897 unwind
.personality_routine
= NULL
;
3898 unwind
.personality_index
= -1;
3899 unwind
.frame_size
= 0;
3900 unwind
.fp_offset
= 0;
3901 unwind
.fp_reg
= REG_SP
;
3903 unwind
.sp_restored
= 0;
3907 /* Parse a handlerdata directive. Creates the exception handling table entry
3908 for the function. */
3911 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3913 demand_empty_rest_of_line ();
3914 if (!unwind
.proc_start
)
3915 as_bad (MISSING_FNSTART
);
3917 if (unwind
.table_entry
)
3918 as_bad (_("duplicate .handlerdata directive"));
3920 create_unwind_entry (1);
3923 /* Parse an unwind_fnend directive. Generates the index table entry. */
3926 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3931 unsigned int marked_pr_dependency
;
3933 demand_empty_rest_of_line ();
3935 if (!unwind
.proc_start
)
3937 as_bad (_(".fnend directive without .fnstart"));
3941 /* Add eh table entry. */
3942 if (unwind
.table_entry
== NULL
)
3943 val
= create_unwind_entry (0);
3947 /* Add index table entry. This is two words. */
3948 start_unwind_section (unwind
.saved_seg
, 1);
3949 frag_align (2, 0, 0);
3950 record_alignment (now_seg
, 2);
3952 ptr
= frag_more (8);
3954 where
= frag_now_fix () - 8;
3956 /* Self relative offset of the function start. */
3957 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3958 BFD_RELOC_ARM_PREL31
);
3960 /* Indicate dependency on EHABI-defined personality routines to the
3961 linker, if it hasn't been done already. */
3962 marked_pr_dependency
3963 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3964 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3965 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3967 static const char *const name
[] =
3969 "__aeabi_unwind_cpp_pr0",
3970 "__aeabi_unwind_cpp_pr1",
3971 "__aeabi_unwind_cpp_pr2"
3973 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3974 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3975 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3976 |= 1 << unwind
.personality_index
;
3980 /* Inline exception table entry. */
3981 md_number_to_chars (ptr
+ 4, val
, 4);
3983 /* Self relative offset of the table entry. */
3984 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3985 BFD_RELOC_ARM_PREL31
);
3987 /* Restore the original section. */
3988 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3990 unwind
.proc_start
= NULL
;
3994 /* Parse an unwind_cantunwind directive. */
3997 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3999 demand_empty_rest_of_line ();
4000 if (!unwind
.proc_start
)
4001 as_bad (MISSING_FNSTART
);
4003 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4004 as_bad (_("personality routine specified for cantunwind frame"));
4006 unwind
.personality_index
= -2;
4010 /* Parse a personalityindex directive. */
4013 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4017 if (!unwind
.proc_start
)
4018 as_bad (MISSING_FNSTART
);
4020 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4021 as_bad (_("duplicate .personalityindex directive"));
4025 if (exp
.X_op
!= O_constant
4026 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4028 as_bad (_("bad personality routine number"));
4029 ignore_rest_of_line ();
4033 unwind
.personality_index
= exp
.X_add_number
;
4035 demand_empty_rest_of_line ();
4039 /* Parse a personality directive. */
4042 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4046 if (!unwind
.proc_start
)
4047 as_bad (MISSING_FNSTART
);
4049 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4050 as_bad (_("duplicate .personality directive"));
4052 c
= get_symbol_name (& name
);
4053 p
= input_line_pointer
;
4055 ++ input_line_pointer
;
4056 unwind
.personality_routine
= symbol_find_or_make (name
);
4058 demand_empty_rest_of_line ();
4062 /* Parse a directive saving core registers. */
4065 s_arm_unwind_save_core (void)
4071 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4074 as_bad (_("expected register list"));
4075 ignore_rest_of_line ();
4079 demand_empty_rest_of_line ();
4081 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4082 into .unwind_save {..., sp...}. We aren't bothered about the value of
4083 ip because it is clobbered by calls. */
4084 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4085 && (range
& 0x3000) == 0x1000)
4087 unwind
.opcode_count
--;
4088 unwind
.sp_restored
= 0;
4089 range
= (range
| 0x2000) & ~0x1000;
4090 unwind
.pending_offset
= 0;
4096 /* See if we can use the short opcodes. These pop a block of up to 8
4097 registers starting with r4, plus maybe r14. */
4098 for (n
= 0; n
< 8; n
++)
4100 /* Break at the first non-saved register. */
4101 if ((range
& (1 << (n
+ 4))) == 0)
4104 /* See if there are any other bits set. */
4105 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4107 /* Use the long form. */
4108 op
= 0x8000 | ((range
>> 4) & 0xfff);
4109 add_unwind_opcode (op
, 2);
4113 /* Use the short form. */
4115 op
= 0xa8; /* Pop r14. */
4117 op
= 0xa0; /* Do not pop r14. */
4119 add_unwind_opcode (op
, 1);
4126 op
= 0xb100 | (range
& 0xf);
4127 add_unwind_opcode (op
, 2);
4130 /* Record the number of bytes pushed. */
4131 for (n
= 0; n
< 16; n
++)
4133 if (range
& (1 << n
))
4134 unwind
.frame_size
+= 4;
4139 /* Parse a directive saving FPA registers. */
4142 s_arm_unwind_save_fpa (int reg
)
4148 /* Get Number of registers to transfer. */
4149 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4152 exp
.X_op
= O_illegal
;
4154 if (exp
.X_op
!= O_constant
)
4156 as_bad (_("expected , <constant>"));
4157 ignore_rest_of_line ();
4161 num_regs
= exp
.X_add_number
;
4163 if (num_regs
< 1 || num_regs
> 4)
4165 as_bad (_("number of registers must be in the range [1:4]"));
4166 ignore_rest_of_line ();
4170 demand_empty_rest_of_line ();
4175 op
= 0xb4 | (num_regs
- 1);
4176 add_unwind_opcode (op
, 1);
4181 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4182 add_unwind_opcode (op
, 2);
4184 unwind
.frame_size
+= num_regs
* 12;
4188 /* Parse a directive saving VFP registers for ARMv6 and above. */
4191 s_arm_unwind_save_vfp_armv6 (void)
4196 int num_vfpv3_regs
= 0;
4197 int num_regs_below_16
;
4198 bfd_boolean partial_match
;
4200 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4204 as_bad (_("expected register list"));
4205 ignore_rest_of_line ();
4209 demand_empty_rest_of_line ();
4211 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4212 than FSTMX/FLDMX-style ones). */
4214 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4216 num_vfpv3_regs
= count
;
4217 else if (start
+ count
> 16)
4218 num_vfpv3_regs
= start
+ count
- 16;
4220 if (num_vfpv3_regs
> 0)
4222 int start_offset
= start
> 16 ? start
- 16 : 0;
4223 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4224 add_unwind_opcode (op
, 2);
4227 /* Generate opcode for registers numbered in the range 0 .. 15. */
4228 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4229 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4230 if (num_regs_below_16
> 0)
4232 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4233 add_unwind_opcode (op
, 2);
4236 unwind
.frame_size
+= count
* 8;
4240 /* Parse a directive saving VFP registers for pre-ARMv6. */
4243 s_arm_unwind_save_vfp (void)
4248 bfd_boolean partial_match
;
4250 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4254 as_bad (_("expected register list"));
4255 ignore_rest_of_line ();
4259 demand_empty_rest_of_line ();
4264 op
= 0xb8 | (count
- 1);
4265 add_unwind_opcode (op
, 1);
4270 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4271 add_unwind_opcode (op
, 2);
4273 unwind
.frame_size
+= count
* 8 + 4;
4277 /* Parse a directive saving iWMMXt data registers. */
4280 s_arm_unwind_save_mmxwr (void)
4288 if (*input_line_pointer
== '{')
4289 input_line_pointer
++;
4293 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4297 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4302 as_tsktsk (_("register list not in ascending order"));
4305 if (*input_line_pointer
== '-')
4307 input_line_pointer
++;
4308 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4311 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4314 else if (reg
>= hi_reg
)
4316 as_bad (_("bad register range"));
4319 for (; reg
< hi_reg
; reg
++)
4323 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4325 skip_past_char (&input_line_pointer
, '}');
4327 demand_empty_rest_of_line ();
4329 /* Generate any deferred opcodes because we're going to be looking at
4331 flush_pending_unwind ();
4333 for (i
= 0; i
< 16; i
++)
4335 if (mask
& (1 << i
))
4336 unwind
.frame_size
+= 8;
4339 /* Attempt to combine with a previous opcode. We do this because gcc
4340 likes to output separate unwind directives for a single block of
4342 if (unwind
.opcode_count
> 0)
4344 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4345 if ((i
& 0xf8) == 0xc0)
4348 /* Only merge if the blocks are contiguous. */
4351 if ((mask
& 0xfe00) == (1 << 9))
4353 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4354 unwind
.opcode_count
--;
4357 else if (i
== 6 && unwind
.opcode_count
>= 2)
4359 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4363 op
= 0xffff << (reg
- 1);
4365 && ((mask
& op
) == (1u << (reg
- 1))))
4367 op
= (1 << (reg
+ i
+ 1)) - 1;
4368 op
&= ~((1 << reg
) - 1);
4370 unwind
.opcode_count
-= 2;
4377 /* We want to generate opcodes in the order the registers have been
4378 saved, ie. descending order. */
4379 for (reg
= 15; reg
>= -1; reg
--)
4381 /* Save registers in blocks. */
4383 || !(mask
& (1 << reg
)))
4385 /* We found an unsaved reg. Generate opcodes to save the
4392 op
= 0xc0 | (hi_reg
- 10);
4393 add_unwind_opcode (op
, 1);
4398 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4399 add_unwind_opcode (op
, 2);
4408 ignore_rest_of_line ();
4412 s_arm_unwind_save_mmxwcg (void)
4419 if (*input_line_pointer
== '{')
4420 input_line_pointer
++;
4422 skip_whitespace (input_line_pointer
);
4426 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4430 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4436 as_tsktsk (_("register list not in ascending order"));
4439 if (*input_line_pointer
== '-')
4441 input_line_pointer
++;
4442 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4445 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4448 else if (reg
>= hi_reg
)
4450 as_bad (_("bad register range"));
4453 for (; reg
< hi_reg
; reg
++)
4457 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4459 skip_past_char (&input_line_pointer
, '}');
4461 demand_empty_rest_of_line ();
4463 /* Generate any deferred opcodes because we're going to be looking at
4465 flush_pending_unwind ();
4467 for (reg
= 0; reg
< 16; reg
++)
4469 if (mask
& (1 << reg
))
4470 unwind
.frame_size
+= 4;
4473 add_unwind_opcode (op
, 2);
4476 ignore_rest_of_line ();
4480 /* Parse an unwind_save directive.
4481 If the argument is non-zero, this is a .vsave directive. */
4484 s_arm_unwind_save (int arch_v6
)
4487 struct reg_entry
*reg
;
4488 bfd_boolean had_brace
= FALSE
;
4490 if (!unwind
.proc_start
)
4491 as_bad (MISSING_FNSTART
);
4493 /* Figure out what sort of save we have. */
4494 peek
= input_line_pointer
;
4502 reg
= arm_reg_parse_multi (&peek
);
4506 as_bad (_("register expected"));
4507 ignore_rest_of_line ();
4516 as_bad (_("FPA .unwind_save does not take a register list"));
4517 ignore_rest_of_line ();
4520 input_line_pointer
= peek
;
4521 s_arm_unwind_save_fpa (reg
->number
);
4525 s_arm_unwind_save_core ();
4530 s_arm_unwind_save_vfp_armv6 ();
4532 s_arm_unwind_save_vfp ();
4535 case REG_TYPE_MMXWR
:
4536 s_arm_unwind_save_mmxwr ();
4539 case REG_TYPE_MMXWCG
:
4540 s_arm_unwind_save_mmxwcg ();
4544 as_bad (_(".unwind_save does not support this kind of register"));
4545 ignore_rest_of_line ();
4550 /* Parse an unwind_movsp directive. */
4553 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4559 if (!unwind
.proc_start
)
4560 as_bad (MISSING_FNSTART
);
4562 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4565 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4566 ignore_rest_of_line ();
4570 /* Optional constant. */
4571 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4573 if (immediate_for_directive (&offset
) == FAIL
)
4579 demand_empty_rest_of_line ();
4581 if (reg
== REG_SP
|| reg
== REG_PC
)
4583 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4587 if (unwind
.fp_reg
!= REG_SP
)
4588 as_bad (_("unexpected .unwind_movsp directive"));
4590 /* Generate opcode to restore the value. */
4592 add_unwind_opcode (op
, 1);
4594 /* Record the information for later. */
4595 unwind
.fp_reg
= reg
;
4596 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4597 unwind
.sp_restored
= 1;
4600 /* Parse an unwind_pad directive. */
4603 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4607 if (!unwind
.proc_start
)
4608 as_bad (MISSING_FNSTART
);
4610 if (immediate_for_directive (&offset
) == FAIL
)
4615 as_bad (_("stack increment must be multiple of 4"));
4616 ignore_rest_of_line ();
4620 /* Don't generate any opcodes, just record the details for later. */
4621 unwind
.frame_size
+= offset
;
4622 unwind
.pending_offset
+= offset
;
4624 demand_empty_rest_of_line ();
4627 /* Parse an unwind_setfp directive. */
4630 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4636 if (!unwind
.proc_start
)
4637 as_bad (MISSING_FNSTART
);
4639 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4640 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4643 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4645 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4647 as_bad (_("expected <reg>, <reg>"));
4648 ignore_rest_of_line ();
4652 /* Optional constant. */
4653 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4655 if (immediate_for_directive (&offset
) == FAIL
)
4661 demand_empty_rest_of_line ();
4663 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4665 as_bad (_("register must be either sp or set by a previous"
4666 "unwind_movsp directive"));
4670 /* Don't generate any opcodes, just record the information for later. */
4671 unwind
.fp_reg
= fp_reg
;
4673 if (sp_reg
== REG_SP
)
4674 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4676 unwind
.fp_offset
-= offset
;
4679 /* Parse an unwind_raw directive. */
4682 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4685 /* This is an arbitrary limit. */
4686 unsigned char op
[16];
4689 if (!unwind
.proc_start
)
4690 as_bad (MISSING_FNSTART
);
4693 if (exp
.X_op
== O_constant
4694 && skip_past_comma (&input_line_pointer
) != FAIL
)
4696 unwind
.frame_size
+= exp
.X_add_number
;
4700 exp
.X_op
= O_illegal
;
4702 if (exp
.X_op
!= O_constant
)
4704 as_bad (_("expected <offset>, <opcode>"));
4705 ignore_rest_of_line ();
4711 /* Parse the opcode. */
4716 as_bad (_("unwind opcode too long"));
4717 ignore_rest_of_line ();
4719 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4721 as_bad (_("invalid unwind opcode"));
4722 ignore_rest_of_line ();
4725 op
[count
++] = exp
.X_add_number
;
4727 /* Parse the next byte. */
4728 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4734 /* Add the opcode bytes in reverse order. */
4736 add_unwind_opcode (op
[count
], 1);
4738 demand_empty_rest_of_line ();
4742 /* Parse a .eabi_attribute directive. */
4745 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4747 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4749 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4750 attributes_set_explicitly
[tag
] = 1;
4753 /* Emit a tls fix for the symbol. */
4756 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4760 #ifdef md_flush_pending_output
4761 md_flush_pending_output ();
4764 #ifdef md_cons_align
4768 /* Since we're just labelling the code, there's no need to define a
4771 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4772 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4773 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4774 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4776 #endif /* OBJ_ELF */
4778 static void s_arm_arch (int);
4779 static void s_arm_object_arch (int);
4780 static void s_arm_cpu (int);
4781 static void s_arm_fpu (int);
4782 static void s_arm_arch_extension (int);
4787 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4794 if (exp
.X_op
== O_symbol
)
4795 exp
.X_op
= O_secrel
;
4797 emit_expr (&exp
, 4);
4799 while (*input_line_pointer
++ == ',');
4801 input_line_pointer
--;
4802 demand_empty_rest_of_line ();
4806 /* This table describes all the machine specific pseudo-ops the assembler
4807 has to support. The fields are:
4808 pseudo-op name without dot
4809 function to call to execute this pseudo-op
4810 Integer arg to pass to the function. */
4812 const pseudo_typeS md_pseudo_table
[] =
4814 /* Never called because '.req' does not start a line. */
4815 { "req", s_req
, 0 },
4816 /* Following two are likewise never called. */
4819 { "unreq", s_unreq
, 0 },
4820 { "bss", s_bss
, 0 },
4821 { "align", s_align_ptwo
, 2 },
4822 { "arm", s_arm
, 0 },
4823 { "thumb", s_thumb
, 0 },
4824 { "code", s_code
, 0 },
4825 { "force_thumb", s_force_thumb
, 0 },
4826 { "thumb_func", s_thumb_func
, 0 },
4827 { "thumb_set", s_thumb_set
, 0 },
4828 { "even", s_even
, 0 },
4829 { "ltorg", s_ltorg
, 0 },
4830 { "pool", s_ltorg
, 0 },
4831 { "syntax", s_syntax
, 0 },
4832 { "cpu", s_arm_cpu
, 0 },
4833 { "arch", s_arm_arch
, 0 },
4834 { "object_arch", s_arm_object_arch
, 0 },
4835 { "fpu", s_arm_fpu
, 0 },
4836 { "arch_extension", s_arm_arch_extension
, 0 },
4838 { "word", s_arm_elf_cons
, 4 },
4839 { "long", s_arm_elf_cons
, 4 },
4840 { "inst.n", s_arm_elf_inst
, 2 },
4841 { "inst.w", s_arm_elf_inst
, 4 },
4842 { "inst", s_arm_elf_inst
, 0 },
4843 { "rel31", s_arm_rel31
, 0 },
4844 { "fnstart", s_arm_unwind_fnstart
, 0 },
4845 { "fnend", s_arm_unwind_fnend
, 0 },
4846 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4847 { "personality", s_arm_unwind_personality
, 0 },
4848 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4849 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4850 { "save", s_arm_unwind_save
, 0 },
4851 { "vsave", s_arm_unwind_save
, 1 },
4852 { "movsp", s_arm_unwind_movsp
, 0 },
4853 { "pad", s_arm_unwind_pad
, 0 },
4854 { "setfp", s_arm_unwind_setfp
, 0 },
4855 { "unwind_raw", s_arm_unwind_raw
, 0 },
4856 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4857 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4861 /* These are used for dwarf. */
4865 /* These are used for dwarf2. */
4866 { "file", dwarf2_directive_file
, 0 },
4867 { "loc", dwarf2_directive_loc
, 0 },
4868 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4870 { "extend", float_cons
, 'x' },
4871 { "ldouble", float_cons
, 'x' },
4872 { "packed", float_cons
, 'p' },
4874 {"secrel32", pe_directive_secrel
, 0},
4877 /* These are for compatibility with CodeComposer Studio. */
4878 {"ref", s_ccs_ref
, 0},
4879 {"def", s_ccs_def
, 0},
4880 {"asmfunc", s_ccs_asmfunc
, 0},
4881 {"endasmfunc", s_ccs_endasmfunc
, 0},
4886 /* Parser functions used exclusively in instruction operands. */
4888 /* Generic immediate-value read function for use in insn parsing.
4889 STR points to the beginning of the immediate (the leading #);
4890 VAL receives the value; if the value is outside [MIN, MAX]
4891 issue an error. PREFIX_OPT is true if the immediate prefix is
4895 parse_immediate (char **str
, int *val
, int min
, int max
,
4896 bfd_boolean prefix_opt
)
4900 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4901 if (exp
.X_op
!= O_constant
)
4903 inst
.error
= _("constant expression required");
4907 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4909 inst
.error
= _("immediate value out of range");
4913 *val
= exp
.X_add_number
;
4917 /* Less-generic immediate-value read function with the possibility of loading a
4918 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4919 instructions. Puts the result directly in inst.operands[i]. */
4922 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4923 bfd_boolean allow_symbol_p
)
4926 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4929 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4931 if (exp_p
->X_op
== O_constant
)
4933 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4934 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4935 O_constant. We have to be careful not to break compilation for
4936 32-bit X_add_number, though. */
4937 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4939 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4940 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4942 inst
.operands
[i
].regisimm
= 1;
4945 else if (exp_p
->X_op
== O_big
4946 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4948 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4950 /* Bignums have their least significant bits in
4951 generic_bignum[0]. Make sure we put 32 bits in imm and
4952 32 bits in reg, in a (hopefully) portable way. */
4953 gas_assert (parts
!= 0);
4955 /* Make sure that the number is not too big.
4956 PR 11972: Bignums can now be sign-extended to the
4957 size of a .octa so check that the out of range bits
4958 are all zero or all one. */
4959 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4961 LITTLENUM_TYPE m
= -1;
4963 if (generic_bignum
[parts
* 2] != 0
4964 && generic_bignum
[parts
* 2] != m
)
4967 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4968 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4972 inst
.operands
[i
].imm
= 0;
4973 for (j
= 0; j
< parts
; j
++, idx
++)
4974 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4975 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4976 inst
.operands
[i
].reg
= 0;
4977 for (j
= 0; j
< parts
; j
++, idx
++)
4978 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4979 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4980 inst
.operands
[i
].regisimm
= 1;
4982 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4990 /* Returns the pseudo-register number of an FPA immediate constant,
4991 or FAIL if there isn't a valid constant here. */
4994 parse_fpa_immediate (char ** str
)
4996 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5002 /* First try and match exact strings, this is to guarantee
5003 that some formats will work even for cross assembly. */
5005 for (i
= 0; fp_const
[i
]; i
++)
5007 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5011 *str
+= strlen (fp_const
[i
]);
5012 if (is_end_of_line
[(unsigned char) **str
])
5018 /* Just because we didn't get a match doesn't mean that the constant
5019 isn't valid, just that it is in a format that we don't
5020 automatically recognize. Try parsing it with the standard
5021 expression routines. */
5023 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5025 /* Look for a raw floating point number. */
5026 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5027 && is_end_of_line
[(unsigned char) *save_in
])
5029 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5031 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5033 if (words
[j
] != fp_values
[i
][j
])
5037 if (j
== MAX_LITTLENUMS
)
5045 /* Try and parse a more complex expression, this will probably fail
5046 unless the code uses a floating point prefix (eg "0f"). */
5047 save_in
= input_line_pointer
;
5048 input_line_pointer
= *str
;
5049 if (expression (&exp
) == absolute_section
5050 && exp
.X_op
== O_big
5051 && exp
.X_add_number
< 0)
5053 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5055 #define X_PRECISION 5
5056 #define E_PRECISION 15L
5057 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5059 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5061 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5063 if (words
[j
] != fp_values
[i
][j
])
5067 if (j
== MAX_LITTLENUMS
)
5069 *str
= input_line_pointer
;
5070 input_line_pointer
= save_in
;
5077 *str
= input_line_pointer
;
5078 input_line_pointer
= save_in
;
5079 inst
.error
= _("invalid FPA immediate expression");
5083 /* Returns 1 if a number has "quarter-precision" float format
5084 0baBbbbbbc defgh000 00000000 00000000. */
5087 is_quarter_float (unsigned imm
)
5089 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5090 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5094 /* Detect the presence of a floating point or integer zero constant,
5098 parse_ifimm_zero (char **in
)
5102 if (!is_immediate_prefix (**in
))
5104 /* In unified syntax, all prefixes are optional. */
5105 if (!unified_syntax
)
5111 /* Accept #0x0 as a synonym for #0. */
5112 if (strncmp (*in
, "0x", 2) == 0)
5115 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5120 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5121 &generic_floating_point_number
);
5124 && generic_floating_point_number
.sign
== '+'
5125 && (generic_floating_point_number
.low
5126 > generic_floating_point_number
.leader
))
5132 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5133 0baBbbbbbc defgh000 00000000 00000000.
5134 The zero and minus-zero cases need special handling, since they can't be
5135 encoded in the "quarter-precision" float format, but can nonetheless be
5136 loaded as integer constants. */
5139 parse_qfloat_immediate (char **ccp
, int *immed
)
5143 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5144 int found_fpchar
= 0;
5146 skip_past_char (&str
, '#');
5148 /* We must not accidentally parse an integer as a floating-point number. Make
5149 sure that the value we parse is not an integer by checking for special
5150 characters '.' or 'e'.
5151 FIXME: This is a horrible hack, but doing better is tricky because type
5152 information isn't in a very usable state at parse time. */
5154 skip_whitespace (fpnum
);
5156 if (strncmp (fpnum
, "0x", 2) == 0)
5160 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5161 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5171 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5173 unsigned fpword
= 0;
5176 /* Our FP word must be 32 bits (single-precision FP). */
5177 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5179 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5183 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5196 /* Shift operands. */
5199 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5202 struct asm_shift_name
5205 enum shift_kind kind
;
5208 /* Third argument to parse_shift. */
5209 enum parse_shift_mode
5211 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5212 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5213 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5214 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5215 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5218 /* Parse a <shift> specifier on an ARM data processing instruction.
5219 This has three forms:
5221 (LSL|LSR|ASL|ASR|ROR) Rs
5222 (LSL|LSR|ASL|ASR|ROR) #imm
5225 Note that ASL is assimilated to LSL in the instruction encoding, and
5226 RRX to ROR #0 (which cannot be written as such). */
5229 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5231 const struct asm_shift_name
*shift_name
;
5232 enum shift_kind shift
;
5237 for (p
= *str
; ISALPHA (*p
); p
++)
5242 inst
.error
= _("shift expression expected");
5246 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5249 if (shift_name
== NULL
)
5251 inst
.error
= _("shift expression expected");
5255 shift
= shift_name
->kind
;
5259 case NO_SHIFT_RESTRICT
:
5260 case SHIFT_IMMEDIATE
: break;
5262 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5263 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5265 inst
.error
= _("'LSL' or 'ASR' required");
5270 case SHIFT_LSL_IMMEDIATE
:
5271 if (shift
!= SHIFT_LSL
)
5273 inst
.error
= _("'LSL' required");
5278 case SHIFT_ASR_IMMEDIATE
:
5279 if (shift
!= SHIFT_ASR
)
5281 inst
.error
= _("'ASR' required");
5289 if (shift
!= SHIFT_RRX
)
5291 /* Whitespace can appear here if the next thing is a bare digit. */
5292 skip_whitespace (p
);
5294 if (mode
== NO_SHIFT_RESTRICT
5295 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5297 inst
.operands
[i
].imm
= reg
;
5298 inst
.operands
[i
].immisreg
= 1;
5300 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5303 inst
.operands
[i
].shift_kind
= shift
;
5304 inst
.operands
[i
].shifted
= 1;
5309 /* Parse a <shifter_operand> for an ARM data processing instruction:
5312 #<immediate>, <rotate>
5316 where <shift> is defined by parse_shift above, and <rotate> is a
5317 multiple of 2 between 0 and 30. Validation of immediate operands
5318 is deferred to md_apply_fix. */
5321 parse_shifter_operand (char **str
, int i
)
5326 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5328 inst
.operands
[i
].reg
= value
;
5329 inst
.operands
[i
].isreg
= 1;
5331 /* parse_shift will override this if appropriate */
5332 inst
.relocs
[0].exp
.X_op
= O_constant
;
5333 inst
.relocs
[0].exp
.X_add_number
= 0;
5335 if (skip_past_comma (str
) == FAIL
)
5338 /* Shift operation on register. */
5339 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5342 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5345 if (skip_past_comma (str
) == SUCCESS
)
5347 /* #x, y -- ie explicit rotation by Y. */
5348 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5351 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5353 inst
.error
= _("constant expression expected");
5357 value
= exp
.X_add_number
;
5358 if (value
< 0 || value
> 30 || value
% 2 != 0)
5360 inst
.error
= _("invalid rotation");
5363 if (inst
.relocs
[0].exp
.X_add_number
< 0
5364 || inst
.relocs
[0].exp
.X_add_number
> 255)
5366 inst
.error
= _("invalid constant");
5370 /* Encode as specified. */
5371 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5375 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5376 inst
.relocs
[0].pc_rel
= 0;
5380 /* Group relocation information. Each entry in the table contains the
5381 textual name of the relocation as may appear in assembler source
5382 and must end with a colon.
5383 Along with this textual name are the relocation codes to be used if
5384 the corresponding instruction is an ALU instruction (ADD or SUB only),
5385 an LDR, an LDRS, or an LDC. */
5387 struct group_reloc_table_entry
5398 /* Varieties of non-ALU group relocation. */
5405 static struct group_reloc_table_entry group_reloc_table
[] =
5406 { /* Program counter relative: */
5408 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5413 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5414 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5415 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5416 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5418 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5423 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5424 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5425 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5426 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5428 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5429 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5430 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5431 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5432 /* Section base relative */
5434 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5439 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5440 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5441 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5442 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5444 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5449 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5450 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5451 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5452 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5454 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5455 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5456 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5457 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5458 /* Absolute thumb alu relocations. */
5460 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5465 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5470 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5475 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5480 /* Given the address of a pointer pointing to the textual name of a group
5481 relocation as may appear in assembler source, attempt to find its details
5482 in group_reloc_table. The pointer will be updated to the character after
5483 the trailing colon. On failure, FAIL will be returned; SUCCESS
5484 otherwise. On success, *entry will be updated to point at the relevant
5485 group_reloc_table entry. */
5488 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5491 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5493 int length
= strlen (group_reloc_table
[i
].name
);
5495 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5496 && (*str
)[length
] == ':')
5498 *out
= &group_reloc_table
[i
];
5499 *str
+= (length
+ 1);
5507 /* Parse a <shifter_operand> for an ARM data processing instruction
5508 (as for parse_shifter_operand) where group relocations are allowed:
5511 #<immediate>, <rotate>
5512 #:<group_reloc>:<expression>
5516 where <group_reloc> is one of the strings defined in group_reloc_table.
5517 The hashes are optional.
5519 Everything else is as for parse_shifter_operand. */
5521 static parse_operand_result
5522 parse_shifter_operand_group_reloc (char **str
, int i
)
5524 /* Determine if we have the sequence of characters #: or just :
5525 coming next. If we do, then we check for a group relocation.
5526 If we don't, punt the whole lot to parse_shifter_operand. */
5528 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5529 || (*str
)[0] == ':')
5531 struct group_reloc_table_entry
*entry
;
5533 if ((*str
)[0] == '#')
5538 /* Try to parse a group relocation. Anything else is an error. */
5539 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5541 inst
.error
= _("unknown group relocation");
5542 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5545 /* We now have the group relocation table entry corresponding to
5546 the name in the assembler source. Next, we parse the expression. */
5547 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5548 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5550 /* Record the relocation type (always the ALU variant here). */
5551 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5552 gas_assert (inst
.relocs
[0].type
!= 0);
5554 return PARSE_OPERAND_SUCCESS
;
5557 return parse_shifter_operand (str
, i
) == SUCCESS
5558 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5560 /* Never reached. */
5563 /* Parse a Neon alignment expression. Information is written to
5564 inst.operands[i]. We assume the initial ':' has been skipped.
5566 align .imm = align << 8, .immisalign=1, .preind=0 */
5567 static parse_operand_result
5568 parse_neon_alignment (char **str
, int i
)
5573 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5575 if (exp
.X_op
!= O_constant
)
5577 inst
.error
= _("alignment must be constant");
5578 return PARSE_OPERAND_FAIL
;
5581 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5582 inst
.operands
[i
].immisalign
= 1;
5583 /* Alignments are not pre-indexes. */
5584 inst
.operands
[i
].preind
= 0;
5587 return PARSE_OPERAND_SUCCESS
;
5590 /* Parse all forms of an ARM address expression. Information is written
5591 to inst.operands[i] and/or inst.relocs[0].
5593 Preindexed addressing (.preind=1):
5595 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5596 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5597 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5598 .shift_kind=shift .relocs[0].exp=shift_imm
5600 These three may have a trailing ! which causes .writeback to be set also.
5602 Postindexed addressing (.postind=1, .writeback=1):
5604 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5605 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5606 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5607 .shift_kind=shift .relocs[0].exp=shift_imm
5609 Unindexed addressing (.preind=0, .postind=0):
5611 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5615 [Rn]{!} shorthand for [Rn,#0]{!}
5616 =immediate .isreg=0 .relocs[0].exp=immediate
5617 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5619 It is the caller's responsibility to check for addressing modes not
5620 supported by the instruction, and to set inst.relocs[0].type. */
5622 static parse_operand_result
5623 parse_address_main (char **str
, int i
, int group_relocations
,
5624 group_reloc_type group_type
)
5629 if (skip_past_char (&p
, '[') == FAIL
)
5631 if (skip_past_char (&p
, '=') == FAIL
)
5633 /* Bare address - translate to PC-relative offset. */
5634 inst
.relocs
[0].pc_rel
= 1;
5635 inst
.operands
[i
].reg
= REG_PC
;
5636 inst
.operands
[i
].isreg
= 1;
5637 inst
.operands
[i
].preind
= 1;
5639 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5640 return PARSE_OPERAND_FAIL
;
5642 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5643 /*allow_symbol_p=*/TRUE
))
5644 return PARSE_OPERAND_FAIL
;
5647 return PARSE_OPERAND_SUCCESS
;
5650 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5651 skip_whitespace (p
);
5653 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5655 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5656 return PARSE_OPERAND_FAIL
;
5658 inst
.operands
[i
].reg
= reg
;
5659 inst
.operands
[i
].isreg
= 1;
5661 if (skip_past_comma (&p
) == SUCCESS
)
5663 inst
.operands
[i
].preind
= 1;
5666 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5668 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5670 inst
.operands
[i
].imm
= reg
;
5671 inst
.operands
[i
].immisreg
= 1;
5673 if (skip_past_comma (&p
) == SUCCESS
)
5674 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5675 return PARSE_OPERAND_FAIL
;
5677 else if (skip_past_char (&p
, ':') == SUCCESS
)
5679 /* FIXME: '@' should be used here, but it's filtered out by generic
5680 code before we get to see it here. This may be subject to
5682 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5684 if (result
!= PARSE_OPERAND_SUCCESS
)
5689 if (inst
.operands
[i
].negative
)
5691 inst
.operands
[i
].negative
= 0;
5695 if (group_relocations
5696 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5698 struct group_reloc_table_entry
*entry
;
5700 /* Skip over the #: or : sequence. */
5706 /* Try to parse a group relocation. Anything else is an
5708 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5710 inst
.error
= _("unknown group relocation");
5711 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5714 /* We now have the group relocation table entry corresponding to
5715 the name in the assembler source. Next, we parse the
5717 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5718 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5720 /* Record the relocation type. */
5725 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5730 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5735 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5742 if (inst
.relocs
[0].type
== 0)
5744 inst
.error
= _("this group relocation is not allowed on this instruction");
5745 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5752 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5753 return PARSE_OPERAND_FAIL
;
5754 /* If the offset is 0, find out if it's a +0 or -0. */
5755 if (inst
.relocs
[0].exp
.X_op
== O_constant
5756 && inst
.relocs
[0].exp
.X_add_number
== 0)
5758 skip_whitespace (q
);
5762 skip_whitespace (q
);
5765 inst
.operands
[i
].negative
= 1;
5770 else if (skip_past_char (&p
, ':') == SUCCESS
)
5772 /* FIXME: '@' should be used here, but it's filtered out by generic code
5773 before we get to see it here. This may be subject to change. */
5774 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5776 if (result
!= PARSE_OPERAND_SUCCESS
)
5780 if (skip_past_char (&p
, ']') == FAIL
)
5782 inst
.error
= _("']' expected");
5783 return PARSE_OPERAND_FAIL
;
5786 if (skip_past_char (&p
, '!') == SUCCESS
)
5787 inst
.operands
[i
].writeback
= 1;
5789 else if (skip_past_comma (&p
) == SUCCESS
)
5791 if (skip_past_char (&p
, '{') == SUCCESS
)
5793 /* [Rn], {expr} - unindexed, with option */
5794 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5795 0, 255, TRUE
) == FAIL
)
5796 return PARSE_OPERAND_FAIL
;
5798 if (skip_past_char (&p
, '}') == FAIL
)
5800 inst
.error
= _("'}' expected at end of 'option' field");
5801 return PARSE_OPERAND_FAIL
;
5803 if (inst
.operands
[i
].preind
)
5805 inst
.error
= _("cannot combine index with option");
5806 return PARSE_OPERAND_FAIL
;
5809 return PARSE_OPERAND_SUCCESS
;
5813 inst
.operands
[i
].postind
= 1;
5814 inst
.operands
[i
].writeback
= 1;
5816 if (inst
.operands
[i
].preind
)
5818 inst
.error
= _("cannot combine pre- and post-indexing");
5819 return PARSE_OPERAND_FAIL
;
5823 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5825 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5827 /* We might be using the immediate for alignment already. If we
5828 are, OR the register number into the low-order bits. */
5829 if (inst
.operands
[i
].immisalign
)
5830 inst
.operands
[i
].imm
|= reg
;
5832 inst
.operands
[i
].imm
= reg
;
5833 inst
.operands
[i
].immisreg
= 1;
5835 if (skip_past_comma (&p
) == SUCCESS
)
5836 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5837 return PARSE_OPERAND_FAIL
;
5843 if (inst
.operands
[i
].negative
)
5845 inst
.operands
[i
].negative
= 0;
5848 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5849 return PARSE_OPERAND_FAIL
;
5850 /* If the offset is 0, find out if it's a +0 or -0. */
5851 if (inst
.relocs
[0].exp
.X_op
== O_constant
5852 && inst
.relocs
[0].exp
.X_add_number
== 0)
5854 skip_whitespace (q
);
5858 skip_whitespace (q
);
5861 inst
.operands
[i
].negative
= 1;
5867 /* If at this point neither .preind nor .postind is set, we have a
5868 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5869 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5871 inst
.operands
[i
].preind
= 1;
5872 inst
.relocs
[0].exp
.X_op
= O_constant
;
5873 inst
.relocs
[0].exp
.X_add_number
= 0;
5876 return PARSE_OPERAND_SUCCESS
;
5880 parse_address (char **str
, int i
)
5882 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5886 static parse_operand_result
5887 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5889 return parse_address_main (str
, i
, 1, type
);
5892 /* Parse an operand for a MOVW or MOVT instruction. */
5894 parse_half (char **str
)
5899 skip_past_char (&p
, '#');
5900 if (strncasecmp (p
, ":lower16:", 9) == 0)
5901 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
5902 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5903 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
5905 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
5908 skip_whitespace (p
);
5911 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5914 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
5916 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
5918 inst
.error
= _("constant expression expected");
5921 if (inst
.relocs
[0].exp
.X_add_number
< 0
5922 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
5924 inst
.error
= _("immediate value out of range");
5932 /* Miscellaneous. */
5934 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5935 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5937 parse_psr (char **str
, bfd_boolean lhs
)
5940 unsigned long psr_field
;
5941 const struct asm_psr
*psr
;
5943 bfd_boolean is_apsr
= FALSE
;
5944 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5946 /* PR gas/12698: If the user has specified -march=all then m_profile will
5947 be TRUE, but we want to ignore it in this case as we are building for any
5948 CPU type, including non-m variants. */
5949 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5952 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5953 feature for ease of use and backwards compatibility. */
5955 if (strncasecmp (p
, "SPSR", 4) == 0)
5958 goto unsupported_psr
;
5960 psr_field
= SPSR_BIT
;
5962 else if (strncasecmp (p
, "CPSR", 4) == 0)
5965 goto unsupported_psr
;
5969 else if (strncasecmp (p
, "APSR", 4) == 0)
5971 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5972 and ARMv7-R architecture CPUs. */
5981 while (ISALNUM (*p
) || *p
== '_');
5983 if (strncasecmp (start
, "iapsr", 5) == 0
5984 || strncasecmp (start
, "eapsr", 5) == 0
5985 || strncasecmp (start
, "xpsr", 4) == 0
5986 || strncasecmp (start
, "psr", 3) == 0)
5987 p
= start
+ strcspn (start
, "rR") + 1;
5989 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5995 /* If APSR is being written, a bitfield may be specified. Note that
5996 APSR itself is handled above. */
5997 if (psr
->field
<= 3)
5999 psr_field
= psr
->field
;
6005 /* M-profile MSR instructions have the mask field set to "10", except
6006 *PSR variants which modify APSR, which may use a different mask (and
6007 have been handled already). Do that by setting the PSR_f field
6009 return psr
->field
| (lhs
? PSR_f
: 0);
6012 goto unsupported_psr
;
6018 /* A suffix follows. */
6024 while (ISALNUM (*p
) || *p
== '_');
6028 /* APSR uses a notation for bits, rather than fields. */
6029 unsigned int nzcvq_bits
= 0;
6030 unsigned int g_bit
= 0;
6033 for (bit
= start
; bit
!= p
; bit
++)
6035 switch (TOLOWER (*bit
))
6038 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6042 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6046 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6050 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6054 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6058 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6062 inst
.error
= _("unexpected bit specified after APSR");
6067 if (nzcvq_bits
== 0x1f)
6072 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6074 inst
.error
= _("selected processor does not "
6075 "support DSP extension");
6082 if ((nzcvq_bits
& 0x20) != 0
6083 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6084 || (g_bit
& 0x2) != 0)
6086 inst
.error
= _("bad bitmask specified after APSR");
6092 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6097 psr_field
|= psr
->field
;
6103 goto error
; /* Garbage after "[CS]PSR". */
6105 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6106 is deprecated, but allow it anyway. */
6110 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6113 else if (!m_profile
)
6114 /* These bits are never right for M-profile devices: don't set them
6115 (only code paths which read/write APSR reach here). */
6116 psr_field
|= (PSR_c
| PSR_f
);
6122 inst
.error
= _("selected processor does not support requested special "
6123 "purpose register");
6127 inst
.error
= _("flag for {c}psr instruction expected");
6131 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6132 value suitable for splatting into the AIF field of the instruction. */
6135 parse_cps_flags (char **str
)
6144 case '\0': case ',':
6147 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6148 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6149 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6152 inst
.error
= _("unrecognized CPS flag");
6157 if (saw_a_flag
== 0)
6159 inst
.error
= _("missing CPS flags");
6167 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6168 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6171 parse_endian_specifier (char **str
)
6176 if (strncasecmp (s
, "BE", 2))
6178 else if (strncasecmp (s
, "LE", 2))
6182 inst
.error
= _("valid endian specifiers are be or le");
6186 if (ISALNUM (s
[2]) || s
[2] == '_')
6188 inst
.error
= _("valid endian specifiers are be or le");
6193 return little_endian
;
6196 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6197 value suitable for poking into the rotate field of an sxt or sxta
6198 instruction, or FAIL on error. */
6201 parse_ror (char **str
)
6206 if (strncasecmp (s
, "ROR", 3) == 0)
6210 inst
.error
= _("missing rotation field after comma");
6214 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6219 case 0: *str
= s
; return 0x0;
6220 case 8: *str
= s
; return 0x1;
6221 case 16: *str
= s
; return 0x2;
6222 case 24: *str
= s
; return 0x3;
6225 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6230 /* Parse a conditional code (from conds[] below). The value returned is in the
6231 range 0 .. 14, or FAIL. */
6233 parse_cond (char **str
)
6236 const struct asm_cond
*c
;
6238 /* Condition codes are always 2 characters, so matching up to
6239 3 characters is sufficient. */
6244 while (ISALPHA (*q
) && n
< 3)
6246 cond
[n
] = TOLOWER (*q
);
6251 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6254 inst
.error
= _("condition required");
6262 /* Record a use of the given feature. */
6264 record_feature_use (const arm_feature_set
*feature
)
6267 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6269 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6272 /* If the given feature is currently allowed, mark it as used and return TRUE.
6273 Return FALSE otherwise. */
6275 mark_feature_used (const arm_feature_set
*feature
)
6277 /* Ensure the option is currently allowed. */
6278 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6281 /* Add the appropriate architecture feature for the barrier option used. */
6282 record_feature_use (feature
);
6287 /* Parse an option for a barrier instruction. Returns the encoding for the
6290 parse_barrier (char **str
)
6293 const struct asm_barrier_opt
*o
;
6296 while (ISALPHA (*q
))
6299 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6304 if (!mark_feature_used (&o
->arch
))
6311 /* Parse the operands of a table branch instruction. Similar to a memory
6314 parse_tb (char **str
)
6319 if (skip_past_char (&p
, '[') == FAIL
)
6321 inst
.error
= _("'[' expected");
6325 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6327 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6330 inst
.operands
[0].reg
= reg
;
6332 if (skip_past_comma (&p
) == FAIL
)
6334 inst
.error
= _("',' expected");
6338 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6340 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6343 inst
.operands
[0].imm
= reg
;
6345 if (skip_past_comma (&p
) == SUCCESS
)
6347 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6349 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6351 inst
.error
= _("invalid shift");
6354 inst
.operands
[0].shifted
= 1;
6357 if (skip_past_char (&p
, ']') == FAIL
)
6359 inst
.error
= _("']' expected");
6366 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6367 information on the types the operands can take and how they are encoded.
6368 Up to four operands may be read; this function handles setting the
6369 ".present" field for each read operand itself.
6370 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6371 else returns FAIL. */
6374 parse_neon_mov (char **str
, int *which_operand
)
6376 int i
= *which_operand
, val
;
6377 enum arm_reg_type rtype
;
6379 struct neon_type_el optype
;
6381 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6383 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6384 inst
.operands
[i
].reg
= val
;
6385 inst
.operands
[i
].isscalar
= 1;
6386 inst
.operands
[i
].vectype
= optype
;
6387 inst
.operands
[i
++].present
= 1;
6389 if (skip_past_comma (&ptr
) == FAIL
)
6392 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6395 inst
.operands
[i
].reg
= val
;
6396 inst
.operands
[i
].isreg
= 1;
6397 inst
.operands
[i
].present
= 1;
6399 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6402 /* Cases 0, 1, 2, 3, 5 (D only). */
6403 if (skip_past_comma (&ptr
) == FAIL
)
6406 inst
.operands
[i
].reg
= val
;
6407 inst
.operands
[i
].isreg
= 1;
6408 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6409 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6410 inst
.operands
[i
].isvec
= 1;
6411 inst
.operands
[i
].vectype
= optype
;
6412 inst
.operands
[i
++].present
= 1;
6414 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6416 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6417 Case 13: VMOV <Sd>, <Rm> */
6418 inst
.operands
[i
].reg
= val
;
6419 inst
.operands
[i
].isreg
= 1;
6420 inst
.operands
[i
].present
= 1;
6422 if (rtype
== REG_TYPE_NQ
)
6424 first_error (_("can't use Neon quad register here"));
6427 else if (rtype
!= REG_TYPE_VFS
)
6430 if (skip_past_comma (&ptr
) == FAIL
)
6432 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6434 inst
.operands
[i
].reg
= val
;
6435 inst
.operands
[i
].isreg
= 1;
6436 inst
.operands
[i
].present
= 1;
6439 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6442 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6443 Case 1: VMOV<c><q> <Dd>, <Dm>
6444 Case 8: VMOV.F32 <Sd>, <Sm>
6445 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6447 inst
.operands
[i
].reg
= val
;
6448 inst
.operands
[i
].isreg
= 1;
6449 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6450 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6451 inst
.operands
[i
].isvec
= 1;
6452 inst
.operands
[i
].vectype
= optype
;
6453 inst
.operands
[i
].present
= 1;
6455 if (skip_past_comma (&ptr
) == SUCCESS
)
6460 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6463 inst
.operands
[i
].reg
= val
;
6464 inst
.operands
[i
].isreg
= 1;
6465 inst
.operands
[i
++].present
= 1;
6467 if (skip_past_comma (&ptr
) == FAIL
)
6470 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6473 inst
.operands
[i
].reg
= val
;
6474 inst
.operands
[i
].isreg
= 1;
6475 inst
.operands
[i
].present
= 1;
6478 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6479 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6480 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6481 Case 10: VMOV.F32 <Sd>, #<imm>
6482 Case 11: VMOV.F64 <Dd>, #<imm> */
6483 inst
.operands
[i
].immisfloat
= 1;
6484 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6486 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6487 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6491 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6495 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6498 inst
.operands
[i
].reg
= val
;
6499 inst
.operands
[i
].isreg
= 1;
6500 inst
.operands
[i
++].present
= 1;
6502 if (skip_past_comma (&ptr
) == FAIL
)
6505 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6507 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6508 inst
.operands
[i
].reg
= val
;
6509 inst
.operands
[i
].isscalar
= 1;
6510 inst
.operands
[i
].present
= 1;
6511 inst
.operands
[i
].vectype
= optype
;
6513 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6515 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6516 inst
.operands
[i
].reg
= val
;
6517 inst
.operands
[i
].isreg
= 1;
6518 inst
.operands
[i
++].present
= 1;
6520 if (skip_past_comma (&ptr
) == FAIL
)
6523 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6526 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6530 inst
.operands
[i
].reg
= val
;
6531 inst
.operands
[i
].isreg
= 1;
6532 inst
.operands
[i
].isvec
= 1;
6533 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6534 inst
.operands
[i
].vectype
= optype
;
6535 inst
.operands
[i
].present
= 1;
6537 if (rtype
== REG_TYPE_VFS
)
6541 if (skip_past_comma (&ptr
) == FAIL
)
6543 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6546 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6549 inst
.operands
[i
].reg
= val
;
6550 inst
.operands
[i
].isreg
= 1;
6551 inst
.operands
[i
].isvec
= 1;
6552 inst
.operands
[i
].issingle
= 1;
6553 inst
.operands
[i
].vectype
= optype
;
6554 inst
.operands
[i
].present
= 1;
6557 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6561 inst
.operands
[i
].reg
= val
;
6562 inst
.operands
[i
].isreg
= 1;
6563 inst
.operands
[i
].isvec
= 1;
6564 inst
.operands
[i
].issingle
= 1;
6565 inst
.operands
[i
].vectype
= optype
;
6566 inst
.operands
[i
].present
= 1;
6571 first_error (_("parse error"));
6575 /* Successfully parsed the operands. Update args. */
6581 first_error (_("expected comma"));
6585 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6589 /* Use this macro when the operand constraints are different
6590 for ARM and THUMB (e.g. ldrd). */
6591 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6592 ((arm_operand) | ((thumb_operand) << 16))
6594 /* Matcher codes for parse_operands. */
6595 enum operand_parse_code
6597 OP_stop
, /* end of line */
6599 OP_RR
, /* ARM register */
6600 OP_RRnpc
, /* ARM register, not r15 */
6601 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6602 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6603 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6604 optional trailing ! */
6605 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6606 OP_RCP
, /* Coprocessor number */
6607 OP_RCN
, /* Coprocessor register */
6608 OP_RF
, /* FPA register */
6609 OP_RVS
, /* VFP single precision register */
6610 OP_RVD
, /* VFP double precision register (0..15) */
6611 OP_RND
, /* Neon double precision register (0..31) */
6612 OP_RNQ
, /* Neon quad precision register */
6613 OP_RVSD
, /* VFP single or double precision register */
6614 OP_RNSD
, /* Neon single or double precision register */
6615 OP_RNDQ
, /* Neon double or quad precision register */
6616 OP_RNSDQ
, /* Neon single, double or quad precision register */
6617 OP_RNSC
, /* Neon scalar D[X] */
6618 OP_RVC
, /* VFP control register */
6619 OP_RMF
, /* Maverick F register */
6620 OP_RMD
, /* Maverick D register */
6621 OP_RMFX
, /* Maverick FX register */
6622 OP_RMDX
, /* Maverick DX register */
6623 OP_RMAX
, /* Maverick AX register */
6624 OP_RMDS
, /* Maverick DSPSC register */
6625 OP_RIWR
, /* iWMMXt wR register */
6626 OP_RIWC
, /* iWMMXt wC register */
6627 OP_RIWG
, /* iWMMXt wCG register */
6628 OP_RXA
, /* XScale accumulator register */
6630 /* New operands for Armv8.1-M Mainline. */
6631 OP_LR
, /* ARM LR register */
6632 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6634 OP_REGLST
, /* ARM register list */
6635 OP_CLRMLST
, /* CLRM register list */
6636 OP_VRSLST
, /* VFP single-precision register list */
6637 OP_VRDLST
, /* VFP double-precision register list */
6638 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6639 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6640 OP_NSTRLST
, /* Neon element/structure list */
6641 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6643 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6644 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6645 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6646 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6647 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6648 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6649 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6650 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6651 OP_VMOV
, /* Neon VMOV operands. */
6652 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6653 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6654 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6656 OP_I0
, /* immediate zero */
6657 OP_I7
, /* immediate value 0 .. 7 */
6658 OP_I15
, /* 0 .. 15 */
6659 OP_I16
, /* 1 .. 16 */
6660 OP_I16z
, /* 0 .. 16 */
6661 OP_I31
, /* 0 .. 31 */
6662 OP_I31w
, /* 0 .. 31, optional trailing ! */
6663 OP_I32
, /* 1 .. 32 */
6664 OP_I32z
, /* 0 .. 32 */
6665 OP_I63
, /* 0 .. 63 */
6666 OP_I63s
, /* -64 .. 63 */
6667 OP_I64
, /* 1 .. 64 */
6668 OP_I64z
, /* 0 .. 64 */
6669 OP_I255
, /* 0 .. 255 */
6671 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6672 OP_I7b
, /* 0 .. 7 */
6673 OP_I15b
, /* 0 .. 15 */
6674 OP_I31b
, /* 0 .. 31 */
6676 OP_SH
, /* shifter operand */
6677 OP_SHG
, /* shifter operand with possible group relocation */
6678 OP_ADDR
, /* Memory address expression (any mode) */
6679 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6680 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6681 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6682 OP_EXP
, /* arbitrary expression */
6683 OP_EXPi
, /* same, with optional immediate prefix */
6684 OP_EXPr
, /* same, with optional relocation suffix */
6685 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
6686 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6687 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6688 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6690 OP_CPSF
, /* CPS flags */
6691 OP_ENDI
, /* Endianness specifier */
6692 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6693 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6694 OP_COND
, /* conditional code */
6695 OP_TB
, /* Table branch. */
6697 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6699 OP_RRnpc_I0
, /* ARM register or literal 0 */
6700 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6701 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6702 OP_RF_IF
, /* FPA register or immediate */
6703 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6704 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6706 /* Optional operands. */
6707 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6708 OP_oI31b
, /* 0 .. 31 */
6709 OP_oI32b
, /* 1 .. 32 */
6710 OP_oI32z
, /* 0 .. 32 */
6711 OP_oIffffb
, /* 0 .. 65535 */
6712 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6714 OP_oRR
, /* ARM register */
6715 OP_oLR
, /* ARM LR register */
6716 OP_oRRnpc
, /* ARM register, not the PC */
6717 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6718 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6719 OP_oRND
, /* Optional Neon double precision register */
6720 OP_oRNQ
, /* Optional Neon quad precision register */
6721 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6722 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6723 OP_oSHll
, /* LSL immediate */
6724 OP_oSHar
, /* ASR immediate */
6725 OP_oSHllar
, /* LSL or ASR immediate */
6726 OP_oROR
, /* ROR 0/8/16/24 */
6727 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6729 /* Some pre-defined mixed (ARM/THUMB) operands. */
6730 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6731 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6732 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6734 OP_FIRST_OPTIONAL
= OP_oI7b
6737 /* Generic instruction operand parser. This does no encoding and no
6738 semantic validation; it merely squirrels values away in the inst
6739 structure. Returns SUCCESS or FAIL depending on whether the
6740 specified grammar matched. */
6742 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6744 unsigned const int *upat
= pattern
;
6745 char *backtrack_pos
= 0;
6746 const char *backtrack_error
= 0;
6747 int i
, val
= 0, backtrack_index
= 0;
6748 enum arm_reg_type rtype
;
6749 parse_operand_result result
;
6750 unsigned int op_parse_code
;
6751 bfd_boolean partial_match
;
6753 #define po_char_or_fail(chr) \
6756 if (skip_past_char (&str, chr) == FAIL) \
6761 #define po_reg_or_fail(regtype) \
6764 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6765 & inst.operands[i].vectype); \
6768 first_error (_(reg_expected_msgs[regtype])); \
6771 inst.operands[i].reg = val; \
6772 inst.operands[i].isreg = 1; \
6773 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6774 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6775 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6776 || rtype == REG_TYPE_VFD \
6777 || rtype == REG_TYPE_NQ); \
6781 #define po_reg_or_goto(regtype, label) \
6784 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6785 & inst.operands[i].vectype); \
6789 inst.operands[i].reg = val; \
6790 inst.operands[i].isreg = 1; \
6791 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6792 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6793 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6794 || rtype == REG_TYPE_VFD \
6795 || rtype == REG_TYPE_NQ); \
6799 #define po_imm_or_fail(min, max, popt) \
6802 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6804 inst.operands[i].imm = val; \
6808 #define po_scalar_or_goto(elsz, label) \
6811 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6814 inst.operands[i].reg = val; \
6815 inst.operands[i].isscalar = 1; \
6819 #define po_misc_or_fail(expr) \
6827 #define po_misc_or_fail_no_backtrack(expr) \
6831 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6832 backtrack_pos = 0; \
6833 if (result != PARSE_OPERAND_SUCCESS) \
6838 #define po_barrier_or_imm(str) \
6841 val = parse_barrier (&str); \
6842 if (val == FAIL && ! ISALPHA (*str)) \
6845 /* ISB can only take SY as an option. */ \
6846 || ((inst.instruction & 0xf0) == 0x60 \
6849 inst.error = _("invalid barrier type"); \
6850 backtrack_pos = 0; \
6856 skip_whitespace (str
);
6858 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6860 op_parse_code
= upat
[i
];
6861 if (op_parse_code
>= 1<<16)
6862 op_parse_code
= thumb
? (op_parse_code
>> 16)
6863 : (op_parse_code
& ((1<<16)-1));
6865 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6867 /* Remember where we are in case we need to backtrack. */
6868 gas_assert (!backtrack_pos
);
6869 backtrack_pos
= str
;
6870 backtrack_error
= inst
.error
;
6871 backtrack_index
= i
;
6874 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6875 po_char_or_fail (',');
6877 switch (op_parse_code
)
6887 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6888 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6889 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6890 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6891 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6892 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6894 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6896 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6898 /* Also accept generic coprocessor regs for unknown registers. */
6900 po_reg_or_fail (REG_TYPE_CN
);
6902 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6903 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6904 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6905 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6906 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6907 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6908 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6909 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6910 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6911 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6913 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6914 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
6916 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6917 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6919 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6921 /* Neon scalar. Using an element size of 8 means that some invalid
6922 scalars are accepted here, so deal with those in later code. */
6923 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6927 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6930 po_imm_or_fail (0, 0, TRUE
);
6935 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6940 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6943 if (parse_ifimm_zero (&str
))
6944 inst
.operands
[i
].imm
= 0;
6948 = _("only floating point zero is allowed as immediate value");
6956 po_scalar_or_goto (8, try_rr
);
6959 po_reg_or_fail (REG_TYPE_RN
);
6965 po_scalar_or_goto (8, try_nsdq
);
6968 po_reg_or_fail (REG_TYPE_NSDQ
);
6974 po_scalar_or_goto (8, try_s_scalar
);
6977 po_scalar_or_goto (4, try_nsd
);
6980 po_reg_or_fail (REG_TYPE_NSD
);
6986 po_scalar_or_goto (8, try_ndq
);
6989 po_reg_or_fail (REG_TYPE_NDQ
);
6995 po_scalar_or_goto (8, try_vfd
);
6998 po_reg_or_fail (REG_TYPE_VFD
);
7003 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7004 not careful then bad things might happen. */
7005 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7010 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7013 /* There's a possibility of getting a 64-bit immediate here, so
7014 we need special handling. */
7015 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7018 inst
.error
= _("immediate value is out of range");
7026 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7029 po_imm_or_fail (0, 63, TRUE
);
7034 po_char_or_fail ('[');
7035 po_reg_or_fail (REG_TYPE_RN
);
7036 po_char_or_fail (']');
7042 po_reg_or_fail (REG_TYPE_RN
);
7043 if (skip_past_char (&str
, '!') == SUCCESS
)
7044 inst
.operands
[i
].writeback
= 1;
7048 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7049 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7050 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7051 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7052 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7053 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7054 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7055 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7056 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7057 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7058 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7059 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7061 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7063 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7064 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7066 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7067 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7068 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7069 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7071 /* Immediate variants */
7073 po_char_or_fail ('{');
7074 po_imm_or_fail (0, 255, TRUE
);
7075 po_char_or_fail ('}');
7079 /* The expression parser chokes on a trailing !, so we have
7080 to find it first and zap it. */
7083 while (*s
&& *s
!= ',')
7088 inst
.operands
[i
].writeback
= 1;
7090 po_imm_or_fail (0, 31, TRUE
);
7098 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7103 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7108 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7110 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7112 val
= parse_reloc (&str
);
7115 inst
.error
= _("unrecognized relocation suffix");
7118 else if (val
!= BFD_RELOC_UNUSED
)
7120 inst
.operands
[i
].imm
= val
;
7121 inst
.operands
[i
].hasreloc
= 1;
7127 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7129 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7131 inst
.operands
[i
].hasreloc
= 1;
7133 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7135 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7136 inst
.operands
[i
].hasreloc
= 0;
7140 /* Operand for MOVW or MOVT. */
7142 po_misc_or_fail (parse_half (&str
));
7145 /* Register or expression. */
7146 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7147 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7149 /* Register or immediate. */
7150 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7151 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7153 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7155 if (!is_immediate_prefix (*str
))
7158 val
= parse_fpa_immediate (&str
);
7161 /* FPA immediates are encoded as registers 8-15.
7162 parse_fpa_immediate has already applied the offset. */
7163 inst
.operands
[i
].reg
= val
;
7164 inst
.operands
[i
].isreg
= 1;
7167 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7168 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7170 /* Two kinds of register. */
7173 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7175 || (rege
->type
!= REG_TYPE_MMXWR
7176 && rege
->type
!= REG_TYPE_MMXWC
7177 && rege
->type
!= REG_TYPE_MMXWCG
))
7179 inst
.error
= _("iWMMXt data or control register expected");
7182 inst
.operands
[i
].reg
= rege
->number
;
7183 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7189 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7191 || (rege
->type
!= REG_TYPE_MMXWC
7192 && rege
->type
!= REG_TYPE_MMXWCG
))
7194 inst
.error
= _("iWMMXt control register expected");
7197 inst
.operands
[i
].reg
= rege
->number
;
7198 inst
.operands
[i
].isreg
= 1;
7203 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7204 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7205 case OP_oROR
: val
= parse_ror (&str
); break;
7206 case OP_COND
: val
= parse_cond (&str
); break;
7207 case OP_oBARRIER_I15
:
7208 po_barrier_or_imm (str
); break;
7210 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7216 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7217 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7219 inst
.error
= _("Banked registers are not available with this "
7225 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7229 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7232 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7234 if (strncasecmp (str
, "APSR_", 5) == 0)
7241 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7242 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7243 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7244 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7245 default: found
= 16;
7249 inst
.operands
[i
].isvec
= 1;
7250 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7251 inst
.operands
[i
].reg
= REG_PC
;
7258 po_misc_or_fail (parse_tb (&str
));
7261 /* Register lists. */
7263 val
= parse_reg_list (&str
, REGLIST_RN
);
7266 inst
.operands
[i
].writeback
= 1;
7272 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7276 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7281 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7286 /* Allow Q registers too. */
7287 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7288 REGLIST_NEON_D
, &partial_match
);
7292 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7293 REGLIST_VFP_S
, &partial_match
);
7294 inst
.operands
[i
].issingle
= 1;
7299 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7300 REGLIST_VFP_D_VPR
, &partial_match
);
7301 if (val
== FAIL
&& !partial_match
)
7304 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7305 REGLIST_VFP_S_VPR
, &partial_match
);
7306 inst
.operands
[i
].issingle
= 1;
7311 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7312 REGLIST_NEON_D
, &partial_match
);
7316 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7317 &inst
.operands
[i
].vectype
);
7320 /* Addressing modes */
7322 po_misc_or_fail (parse_address (&str
, i
));
7326 po_misc_or_fail_no_backtrack (
7327 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7331 po_misc_or_fail_no_backtrack (
7332 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7336 po_misc_or_fail_no_backtrack (
7337 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7341 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7345 po_misc_or_fail_no_backtrack (
7346 parse_shifter_operand_group_reloc (&str
, i
));
7350 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7354 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7358 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7362 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7365 /* Various value-based sanity checks and shared operations. We
7366 do not signal immediate failures for the register constraints;
7367 this allows a syntax error to take precedence. */
7368 switch (op_parse_code
)
7376 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7377 inst
.error
= BAD_PC
;
7382 if (inst
.operands
[i
].isreg
)
7384 if (inst
.operands
[i
].reg
== REG_PC
)
7385 inst
.error
= BAD_PC
;
7386 else if (inst
.operands
[i
].reg
== REG_SP
7387 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7388 relaxed since ARMv8-A. */
7389 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7392 inst
.error
= BAD_SP
;
7398 if (inst
.operands
[i
].isreg
7399 && inst
.operands
[i
].reg
== REG_PC
7400 && (inst
.operands
[i
].writeback
|| thumb
))
7401 inst
.error
= BAD_PC
;
7410 case OP_oBARRIER_I15
:
7421 inst
.operands
[i
].imm
= val
;
7426 if (inst
.operands
[i
].reg
!= REG_LR
)
7427 inst
.error
= _("operand must be LR register");
7434 /* If we get here, this operand was successfully parsed. */
7435 inst
.operands
[i
].present
= 1;
7439 inst
.error
= BAD_ARGS
;
7444 /* The parse routine should already have set inst.error, but set a
7445 default here just in case. */
7447 inst
.error
= _("syntax error");
7451 /* Do not backtrack over a trailing optional argument that
7452 absorbed some text. We will only fail again, with the
7453 'garbage following instruction' error message, which is
7454 probably less helpful than the current one. */
7455 if (backtrack_index
== i
&& backtrack_pos
!= str
7456 && upat
[i
+1] == OP_stop
)
7459 inst
.error
= _("syntax error");
7463 /* Try again, skipping the optional argument at backtrack_pos. */
7464 str
= backtrack_pos
;
7465 inst
.error
= backtrack_error
;
7466 inst
.operands
[backtrack_index
].present
= 0;
7467 i
= backtrack_index
;
7471 /* Check that we have parsed all the arguments. */
7472 if (*str
!= '\0' && !inst
.error
)
7473 inst
.error
= _("garbage following instruction");
7475 return inst
.error
? FAIL
: SUCCESS
;
7478 #undef po_char_or_fail
7479 #undef po_reg_or_fail
7480 #undef po_reg_or_goto
7481 #undef po_imm_or_fail
7482 #undef po_scalar_or_fail
7483 #undef po_barrier_or_imm
7485 /* Shorthand macro for instruction encoding functions issuing errors. */
7486 #define constraint(expr, err) \
7497 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7498 instructions are unpredictable if these registers are used. This
7499 is the BadReg predicate in ARM's Thumb-2 documentation.
7501 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7502 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7503 #define reject_bad_reg(reg) \
7505 if (reg == REG_PC) \
7507 inst.error = BAD_PC; \
7510 else if (reg == REG_SP \
7511 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7513 inst.error = BAD_SP; \
7518 /* If REG is R13 (the stack pointer), warn that its use is
7520 #define warn_deprecated_sp(reg) \
7522 if (warn_on_deprecated && reg == REG_SP) \
7523 as_tsktsk (_("use of r13 is deprecated")); \
7526 /* Functions for operand encoding. ARM, then Thumb. */
7528 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7530 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7532 The only binary encoding difference is the Coprocessor number. Coprocessor
7533 9 is used for half-precision calculations or conversions. The format of the
7534 instruction is the same as the equivalent Coprocessor 10 instruction that
7535 exists for Single-Precision operation. */
7538 do_scalar_fp16_v82_encode (void)
7540 if (inst
.cond
!= COND_ALWAYS
)
7541 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7542 " the behaviour is UNPREDICTABLE"));
7543 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7546 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7547 mark_feature_used (&arm_ext_fp16
);
7550 /* If VAL can be encoded in the immediate field of an ARM instruction,
7551 return the encoded form. Otherwise, return FAIL. */
7554 encode_arm_immediate (unsigned int val
)
7561 for (i
= 2; i
< 32; i
+= 2)
7562 if ((a
= rotate_left (val
, i
)) <= 0xff)
7563 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7568 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7569 return the encoded form. Otherwise, return FAIL. */
7571 encode_thumb32_immediate (unsigned int val
)
7578 for (i
= 1; i
<= 24; i
++)
7581 if ((val
& ~(0xff << i
)) == 0)
7582 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7586 if (val
== ((a
<< 16) | a
))
7588 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7592 if (val
== ((a
<< 16) | a
))
7593 return 0x200 | (a
>> 8);
7597 /* Encode a VFP SP or DP register number into inst.instruction. */
7600 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7602 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7605 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7608 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7611 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7616 first_error (_("D register out of range for selected VFP version"));
7624 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7628 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7632 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7636 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7640 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7644 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7652 /* Encode a <shift> in an ARM-format instruction. The immediate,
7653 if any, is handled by md_apply_fix. */
7655 encode_arm_shift (int i
)
7657 /* register-shifted register. */
7658 if (inst
.operands
[i
].immisreg
)
7661 for (op_index
= 0; op_index
<= i
; ++op_index
)
7663 /* Check the operand only when it's presented. In pre-UAL syntax,
7664 if the destination register is the same as the first operand, two
7665 register form of the instruction can be used. */
7666 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7667 && inst
.operands
[op_index
].reg
== REG_PC
)
7668 as_warn (UNPRED_REG ("r15"));
7671 if (inst
.operands
[i
].imm
== REG_PC
)
7672 as_warn (UNPRED_REG ("r15"));
7675 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7676 inst
.instruction
|= SHIFT_ROR
<< 5;
7679 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7680 if (inst
.operands
[i
].immisreg
)
7682 inst
.instruction
|= SHIFT_BY_REG
;
7683 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7686 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
7691 encode_arm_shifter_operand (int i
)
7693 if (inst
.operands
[i
].isreg
)
7695 inst
.instruction
|= inst
.operands
[i
].reg
;
7696 encode_arm_shift (i
);
7700 inst
.instruction
|= INST_IMMEDIATE
;
7701 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
7702 inst
.instruction
|= inst
.operands
[i
].imm
;
7706 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7708 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7711 Generate an error if the operand is not a register. */
7712 constraint (!inst
.operands
[i
].isreg
,
7713 _("Instruction does not support =N addresses"));
7715 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7717 if (inst
.operands
[i
].preind
)
7721 inst
.error
= _("instruction does not accept preindexed addressing");
7724 inst
.instruction
|= PRE_INDEX
;
7725 if (inst
.operands
[i
].writeback
)
7726 inst
.instruction
|= WRITE_BACK
;
7729 else if (inst
.operands
[i
].postind
)
7731 gas_assert (inst
.operands
[i
].writeback
);
7733 inst
.instruction
|= WRITE_BACK
;
7735 else /* unindexed - only for coprocessor */
7737 inst
.error
= _("instruction does not accept unindexed addressing");
7741 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7742 && (((inst
.instruction
& 0x000f0000) >> 16)
7743 == ((inst
.instruction
& 0x0000f000) >> 12)))
7744 as_warn ((inst
.instruction
& LOAD_BIT
)
7745 ? _("destination register same as write-back base")
7746 : _("source register same as write-back base"));
7749 /* inst.operands[i] was set up by parse_address. Encode it into an
7750 ARM-format mode 2 load or store instruction. If is_t is true,
7751 reject forms that cannot be used with a T instruction (i.e. not
7754 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7756 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7758 encode_arm_addr_mode_common (i
, is_t
);
7760 if (inst
.operands
[i
].immisreg
)
7762 constraint ((inst
.operands
[i
].imm
== REG_PC
7763 || (is_pc
&& inst
.operands
[i
].writeback
)),
7765 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7766 inst
.instruction
|= inst
.operands
[i
].imm
;
7767 if (!inst
.operands
[i
].negative
)
7768 inst
.instruction
|= INDEX_UP
;
7769 if (inst
.operands
[i
].shifted
)
7771 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7772 inst
.instruction
|= SHIFT_ROR
<< 5;
7775 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7776 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
7780 else /* immediate offset in inst.relocs[0] */
7782 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
7784 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7786 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7787 cannot use PC in addressing.
7788 PC cannot be used in writeback addressing, either. */
7789 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7792 /* Use of PC in str is deprecated for ARMv7. */
7793 if (warn_on_deprecated
7795 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7796 as_tsktsk (_("use of PC in this instruction is deprecated"));
7799 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
7801 /* Prefer + for zero encoded value. */
7802 if (!inst
.operands
[i
].negative
)
7803 inst
.instruction
|= INDEX_UP
;
7804 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
7809 /* inst.operands[i] was set up by parse_address. Encode it into an
7810 ARM-format mode 3 load or store instruction. Reject forms that
7811 cannot be used with such instructions. If is_t is true, reject
7812 forms that cannot be used with a T instruction (i.e. not
7815 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7817 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7819 inst
.error
= _("instruction does not accept scaled register index");
7823 encode_arm_addr_mode_common (i
, is_t
);
7825 if (inst
.operands
[i
].immisreg
)
7827 constraint ((inst
.operands
[i
].imm
== REG_PC
7828 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7830 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7832 inst
.instruction
|= inst
.operands
[i
].imm
;
7833 if (!inst
.operands
[i
].negative
)
7834 inst
.instruction
|= INDEX_UP
;
7836 else /* immediate offset in inst.relocs[0] */
7838 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
7839 && inst
.operands
[i
].writeback
),
7841 inst
.instruction
|= HWOFFSET_IMM
;
7842 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
7844 /* Prefer + for zero encoded value. */
7845 if (!inst
.operands
[i
].negative
)
7846 inst
.instruction
|= INDEX_UP
;
7848 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7853 /* Write immediate bits [7:0] to the following locations:
7855 |28/24|23 19|18 16|15 4|3 0|
7856 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7858 This function is used by VMOV/VMVN/VORR/VBIC. */
7861 neon_write_immbits (unsigned immbits
)
7863 inst
.instruction
|= immbits
& 0xf;
7864 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7865 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7868 /* Invert low-order SIZE bits of XHI:XLO. */
7871 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7873 unsigned immlo
= xlo
? *xlo
: 0;
7874 unsigned immhi
= xhi
? *xhi
: 0;
7879 immlo
= (~immlo
) & 0xff;
7883 immlo
= (~immlo
) & 0xffff;
7887 immhi
= (~immhi
) & 0xffffffff;
7891 immlo
= (~immlo
) & 0xffffffff;
7905 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7909 neon_bits_same_in_bytes (unsigned imm
)
7911 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7912 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7913 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7914 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7917 /* For immediate of above form, return 0bABCD. */
7920 neon_squash_bits (unsigned imm
)
7922 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7923 | ((imm
& 0x01000000) >> 21);
7926 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7929 neon_qfloat_bits (unsigned imm
)
7931 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7934 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7935 the instruction. *OP is passed as the initial value of the op field, and
7936 may be set to a different value depending on the constant (i.e.
7937 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7938 MVN). If the immediate looks like a repeated pattern then also
7939 try smaller element sizes. */
7942 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7943 unsigned *immbits
, int *op
, int size
,
7944 enum neon_el_type type
)
7946 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7948 if (type
== NT_float
&& !float_p
)
7951 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7953 if (size
!= 32 || *op
== 1)
7955 *immbits
= neon_qfloat_bits (immlo
);
7961 if (neon_bits_same_in_bytes (immhi
)
7962 && neon_bits_same_in_bytes (immlo
))
7966 *immbits
= (neon_squash_bits (immhi
) << 4)
7967 | neon_squash_bits (immlo
);
7978 if (immlo
== (immlo
& 0x000000ff))
7983 else if (immlo
== (immlo
& 0x0000ff00))
7985 *immbits
= immlo
>> 8;
7988 else if (immlo
== (immlo
& 0x00ff0000))
7990 *immbits
= immlo
>> 16;
7993 else if (immlo
== (immlo
& 0xff000000))
7995 *immbits
= immlo
>> 24;
7998 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8000 *immbits
= (immlo
>> 8) & 0xff;
8003 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8005 *immbits
= (immlo
>> 16) & 0xff;
8009 if ((immlo
& 0xffff) != (immlo
>> 16))
8016 if (immlo
== (immlo
& 0x000000ff))
8021 else if (immlo
== (immlo
& 0x0000ff00))
8023 *immbits
= immlo
>> 8;
8027 if ((immlo
& 0xff) != (immlo
>> 8))
8032 if (immlo
== (immlo
& 0x000000ff))
8034 /* Don't allow MVN with 8-bit immediate. */
8044 #if defined BFD_HOST_64_BIT
8045 /* Returns TRUE if double precision value V may be cast
8046 to single precision without loss of accuracy. */
8049 is_double_a_single (bfd_int64_t v
)
8051 int exp
= (int)((v
>> 52) & 0x7FF);
8052 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8054 return (exp
== 0 || exp
== 0x7FF
8055 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8056 && (mantissa
& 0x1FFFFFFFl
) == 0;
8059 /* Returns a double precision value casted to single precision
8060 (ignoring the least significant bits in exponent and mantissa). */
8063 double_to_single (bfd_int64_t v
)
8065 int sign
= (int) ((v
>> 63) & 1l);
8066 int exp
= (int) ((v
>> 52) & 0x7FF);
8067 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8073 exp
= exp
- 1023 + 127;
8082 /* No denormalized numbers. */
8088 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8090 #endif /* BFD_HOST_64_BIT */
8099 static void do_vfp_nsyn_opcode (const char *);
8101 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8102 Determine whether it can be performed with a move instruction; if
8103 it can, convert inst.instruction to that move instruction and
8104 return TRUE; if it can't, convert inst.instruction to a literal-pool
8105 load and return FALSE. If this is not a valid thing to do in the
8106 current context, set inst.error and return TRUE.
8108 inst.operands[i] describes the destination register. */
8111 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8114 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8115 bfd_boolean arm_p
= (t
== CONST_ARM
);
8118 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8122 if ((inst
.instruction
& tbit
) == 0)
8124 inst
.error
= _("invalid pseudo operation");
8128 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8129 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8130 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8132 inst
.error
= _("constant expression expected");
8136 if (inst
.relocs
[0].exp
.X_op
== O_constant
8137 || inst
.relocs
[0].exp
.X_op
== O_big
)
8139 #if defined BFD_HOST_64_BIT
8144 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8146 LITTLENUM_TYPE w
[X_PRECISION
];
8149 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8151 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8153 /* FIXME: Should we check words w[2..5] ? */
8158 #if defined BFD_HOST_64_BIT
8160 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8161 << LITTLENUM_NUMBER_OF_BITS
)
8162 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8163 << LITTLENUM_NUMBER_OF_BITS
)
8164 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8165 << LITTLENUM_NUMBER_OF_BITS
)
8166 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8168 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8169 | (l
[0] & LITTLENUM_MASK
);
8173 v
= inst
.relocs
[0].exp
.X_add_number
;
8175 if (!inst
.operands
[i
].issingle
)
8179 /* LDR should not use lead in a flag-setting instruction being
8180 chosen so we do not check whether movs can be used. */
8182 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8183 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8184 && inst
.operands
[i
].reg
!= 13
8185 && inst
.operands
[i
].reg
!= 15)
8187 /* Check if on thumb2 it can be done with a mov.w, mvn or
8188 movw instruction. */
8189 unsigned int newimm
;
8190 bfd_boolean isNegated
;
8192 newimm
= encode_thumb32_immediate (v
);
8193 if (newimm
!= (unsigned int) FAIL
)
8197 newimm
= encode_thumb32_immediate (~v
);
8198 if (newimm
!= (unsigned int) FAIL
)
8202 /* The number can be loaded with a mov.w or mvn
8204 if (newimm
!= (unsigned int) FAIL
8205 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8207 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8208 | (inst
.operands
[i
].reg
<< 8));
8209 /* Change to MOVN. */
8210 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8211 inst
.instruction
|= (newimm
& 0x800) << 15;
8212 inst
.instruction
|= (newimm
& 0x700) << 4;
8213 inst
.instruction
|= (newimm
& 0x0ff);
8216 /* The number can be loaded with a movw instruction. */
8217 else if ((v
& ~0xFFFF) == 0
8218 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8220 int imm
= v
& 0xFFFF;
8222 inst
.instruction
= 0xf2400000; /* MOVW. */
8223 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8224 inst
.instruction
|= (imm
& 0xf000) << 4;
8225 inst
.instruction
|= (imm
& 0x0800) << 15;
8226 inst
.instruction
|= (imm
& 0x0700) << 4;
8227 inst
.instruction
|= (imm
& 0x00ff);
8234 int value
= encode_arm_immediate (v
);
8238 /* This can be done with a mov instruction. */
8239 inst
.instruction
&= LITERAL_MASK
;
8240 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8241 inst
.instruction
|= value
& 0xfff;
8245 value
= encode_arm_immediate (~ v
);
8248 /* This can be done with a mvn instruction. */
8249 inst
.instruction
&= LITERAL_MASK
;
8250 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8251 inst
.instruction
|= value
& 0xfff;
8255 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8258 unsigned immbits
= 0;
8259 unsigned immlo
= inst
.operands
[1].imm
;
8260 unsigned immhi
= inst
.operands
[1].regisimm
8261 ? inst
.operands
[1].reg
8262 : inst
.relocs
[0].exp
.X_unsigned
8264 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8265 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8266 &op
, 64, NT_invtype
);
8270 neon_invert_size (&immlo
, &immhi
, 64);
8272 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8273 &op
, 64, NT_invtype
);
8278 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8284 /* Fill other bits in vmov encoding for both thumb and arm. */
8286 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8288 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8289 neon_write_immbits (immbits
);
8297 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8298 if (inst
.operands
[i
].issingle
8299 && is_quarter_float (inst
.operands
[1].imm
)
8300 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8302 inst
.operands
[1].imm
=
8303 neon_qfloat_bits (v
);
8304 do_vfp_nsyn_opcode ("fconsts");
8308 /* If our host does not support a 64-bit type then we cannot perform
8309 the following optimization. This mean that there will be a
8310 discrepancy between the output produced by an assembler built for
8311 a 32-bit-only host and the output produced from a 64-bit host, but
8312 this cannot be helped. */
8313 #if defined BFD_HOST_64_BIT
8314 else if (!inst
.operands
[1].issingle
8315 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8317 if (is_double_a_single (v
)
8318 && is_quarter_float (double_to_single (v
)))
8320 inst
.operands
[1].imm
=
8321 neon_qfloat_bits (double_to_single (v
));
8322 do_vfp_nsyn_opcode ("fconstd");
8330 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8331 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8334 inst
.operands
[1].reg
= REG_PC
;
8335 inst
.operands
[1].isreg
= 1;
8336 inst
.operands
[1].preind
= 1;
8337 inst
.relocs
[0].pc_rel
= 1;
8338 inst
.relocs
[0].type
= (thumb_p
8339 ? BFD_RELOC_ARM_THUMB_OFFSET
8341 ? BFD_RELOC_ARM_HWLITERAL
8342 : BFD_RELOC_ARM_LITERAL
));
8346 /* inst.operands[i] was set up by parse_address. Encode it into an
8347 ARM-format instruction. Reject all forms which cannot be encoded
8348 into a coprocessor load/store instruction. If wb_ok is false,
8349 reject use of writeback; if unind_ok is false, reject use of
8350 unindexed addressing. If reloc_override is not 0, use it instead
8351 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8352 (in which case it is preserved). */
8355 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8357 if (!inst
.operands
[i
].isreg
)
8360 if (! inst
.operands
[0].isvec
)
8362 inst
.error
= _("invalid co-processor operand");
8365 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8369 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8371 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8373 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8375 gas_assert (!inst
.operands
[i
].writeback
);
8378 inst
.error
= _("instruction does not support unindexed addressing");
8381 inst
.instruction
|= inst
.operands
[i
].imm
;
8382 inst
.instruction
|= INDEX_UP
;
8386 if (inst
.operands
[i
].preind
)
8387 inst
.instruction
|= PRE_INDEX
;
8389 if (inst
.operands
[i
].writeback
)
8391 if (inst
.operands
[i
].reg
== REG_PC
)
8393 inst
.error
= _("pc may not be used with write-back");
8398 inst
.error
= _("instruction does not support writeback");
8401 inst
.instruction
|= WRITE_BACK
;
8405 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8406 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8407 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8408 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8411 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8413 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8416 /* Prefer + for zero encoded value. */
8417 if (!inst
.operands
[i
].negative
)
8418 inst
.instruction
|= INDEX_UP
;
8423 /* Functions for instruction encoding, sorted by sub-architecture.
8424 First some generics; their names are taken from the conventional
8425 bit positions for register arguments in ARM format instructions. */
8435 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8441 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8447 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8448 inst
.instruction
|= inst
.operands
[1].reg
;
8454 inst
.instruction
|= inst
.operands
[0].reg
;
8455 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8461 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8462 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8468 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8469 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8475 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8476 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8480 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8482 if (ARM_CPU_IS_ANY (cpu_variant
))
8484 as_tsktsk ("%s", msg
);
8487 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8499 unsigned Rn
= inst
.operands
[2].reg
;
8500 /* Enforce restrictions on SWP instruction. */
8501 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8503 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8504 _("Rn must not overlap other operands"));
8506 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8508 if (!check_obsolete (&arm_ext_v8
,
8509 _("swp{b} use is obsoleted for ARMv8 and later"))
8510 && warn_on_deprecated
8511 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8512 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8515 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8516 inst
.instruction
|= inst
.operands
[1].reg
;
8517 inst
.instruction
|= Rn
<< 16;
8523 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8524 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8525 inst
.instruction
|= inst
.operands
[2].reg
;
8531 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8532 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
8533 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
8534 || inst
.relocs
[0].exp
.X_add_number
!= 0),
8536 inst
.instruction
|= inst
.operands
[0].reg
;
8537 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8538 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8544 inst
.instruction
|= inst
.operands
[0].imm
;
8550 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8551 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8554 /* ARM instructions, in alphabetical order by function name (except
8555 that wrapper functions appear immediately after the function they
8558 /* This is a pseudo-op of the form "adr rd, label" to be converted
8559 into a relative address of the form "add rd, pc, #label-.-8". */
8564 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8566 /* Frag hacking will turn this into a sub instruction if the offset turns
8567 out to be negative. */
8568 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
8569 inst
.relocs
[0].pc_rel
= 1;
8570 inst
.relocs
[0].exp
.X_add_number
-= 8;
8572 if (support_interwork
8573 && inst
.relocs
[0].exp
.X_op
== O_symbol
8574 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
8575 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
8576 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
8577 inst
.relocs
[0].exp
.X_add_number
|= 1;
8580 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8581 into a relative address of the form:
8582 add rd, pc, #low(label-.-8)"
8583 add rd, rd, #high(label-.-8)" */
8588 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8590 /* Frag hacking will turn this into a sub instruction if the offset turns
8591 out to be negative. */
8592 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8593 inst
.relocs
[0].pc_rel
= 1;
8594 inst
.size
= INSN_SIZE
* 2;
8595 inst
.relocs
[0].exp
.X_add_number
-= 8;
8597 if (support_interwork
8598 && inst
.relocs
[0].exp
.X_op
== O_symbol
8599 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
8600 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
8601 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
8602 inst
.relocs
[0].exp
.X_add_number
|= 1;
8608 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8609 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8611 if (!inst
.operands
[1].present
)
8612 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8613 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8614 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8615 encode_arm_shifter_operand (2);
8621 if (inst
.operands
[0].present
)
8622 inst
.instruction
|= inst
.operands
[0].imm
;
8624 inst
.instruction
|= 0xf;
8630 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8631 constraint (msb
> 32, _("bit-field extends past end of register"));
8632 /* The instruction encoding stores the LSB and MSB,
8633 not the LSB and width. */
8634 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8635 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8636 inst
.instruction
|= (msb
- 1) << 16;
8644 /* #0 in second position is alternative syntax for bfc, which is
8645 the same instruction but with REG_PC in the Rm field. */
8646 if (!inst
.operands
[1].isreg
)
8647 inst
.operands
[1].reg
= REG_PC
;
8649 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8650 constraint (msb
> 32, _("bit-field extends past end of register"));
8651 /* The instruction encoding stores the LSB and MSB,
8652 not the LSB and width. */
8653 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8654 inst
.instruction
|= inst
.operands
[1].reg
;
8655 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8656 inst
.instruction
|= (msb
- 1) << 16;
8662 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8663 _("bit-field extends past end of register"));
8664 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8665 inst
.instruction
|= inst
.operands
[1].reg
;
8666 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8667 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8670 /* ARM V5 breakpoint instruction (argument parse)
8671 BKPT <16 bit unsigned immediate>
8672 Instruction is not conditional.
8673 The bit pattern given in insns[] has the COND_ALWAYS condition,
8674 and it is an error if the caller tried to override that. */
8679 /* Top 12 of 16 bits to bits 19:8. */
8680 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8682 /* Bottom 4 of 16 bits to bits 3:0. */
8683 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8687 encode_branch (int default_reloc
)
8689 if (inst
.operands
[0].hasreloc
)
8691 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8692 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8693 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8694 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8695 ? BFD_RELOC_ARM_PLT32
8696 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8699 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
8700 inst
.relocs
[0].pc_rel
= 1;
8707 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8708 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8711 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8718 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8720 if (inst
.cond
== COND_ALWAYS
)
8721 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8723 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8727 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8730 /* ARM V5 branch-link-exchange instruction (argument parse)
8731 BLX <target_addr> ie BLX(1)
8732 BLX{<condition>} <Rm> ie BLX(2)
8733 Unfortunately, there are two different opcodes for this mnemonic.
8734 So, the insns[].value is not used, and the code here zaps values
8735 into inst.instruction.
8736 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8741 if (inst
.operands
[0].isreg
)
8743 /* Arg is a register; the opcode provided by insns[] is correct.
8744 It is not illegal to do "blx pc", just useless. */
8745 if (inst
.operands
[0].reg
== REG_PC
)
8746 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8748 inst
.instruction
|= inst
.operands
[0].reg
;
8752 /* Arg is an address; this instruction cannot be executed
8753 conditionally, and the opcode must be adjusted.
8754 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8755 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8756 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8757 inst
.instruction
= 0xfa000000;
8758 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8765 bfd_boolean want_reloc
;
8767 if (inst
.operands
[0].reg
== REG_PC
)
8768 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8770 inst
.instruction
|= inst
.operands
[0].reg
;
8771 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8772 it is for ARMv4t or earlier. */
8773 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8774 if (!ARM_FEATURE_ZERO (selected_object_arch
)
8775 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
8779 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8784 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
8788 /* ARM v5TEJ. Jump to Jazelle code. */
8793 if (inst
.operands
[0].reg
== REG_PC
)
8794 as_tsktsk (_("use of r15 in bxj is not really useful"));
8796 inst
.instruction
|= inst
.operands
[0].reg
;
8799 /* Co-processor data operation:
8800 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8801 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8805 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8806 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8807 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8808 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8809 inst
.instruction
|= inst
.operands
[4].reg
;
8810 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8816 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8817 encode_arm_shifter_operand (1);
8820 /* Transfer between coprocessor and ARM registers.
8821 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8826 No special properties. */
8828 struct deprecated_coproc_regs_s
8835 arm_feature_set deprecated
;
8836 arm_feature_set obsoleted
;
8837 const char *dep_msg
;
8838 const char *obs_msg
;
8841 #define DEPR_ACCESS_V8 \
8842 N_("This coprocessor register access is deprecated in ARMv8")
8844 /* Table of all deprecated coprocessor registers. */
8845 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8847 {15, 0, 7, 10, 5, /* CP15DMB. */
8848 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8849 DEPR_ACCESS_V8
, NULL
},
8850 {15, 0, 7, 10, 4, /* CP15DSB. */
8851 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8852 DEPR_ACCESS_V8
, NULL
},
8853 {15, 0, 7, 5, 4, /* CP15ISB. */
8854 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8855 DEPR_ACCESS_V8
, NULL
},
8856 {14, 6, 1, 0, 0, /* TEEHBR. */
8857 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8858 DEPR_ACCESS_V8
, NULL
},
8859 {14, 6, 0, 0, 0, /* TEECR. */
8860 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8861 DEPR_ACCESS_V8
, NULL
},
8864 #undef DEPR_ACCESS_V8
8866 static const size_t deprecated_coproc_reg_count
=
8867 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8875 Rd
= inst
.operands
[2].reg
;
8878 if (inst
.instruction
== 0xee000010
8879 || inst
.instruction
== 0xfe000010)
8881 reject_bad_reg (Rd
);
8882 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8884 constraint (Rd
== REG_SP
, BAD_SP
);
8889 if (inst
.instruction
== 0xe000010)
8890 constraint (Rd
== REG_PC
, BAD_PC
);
8893 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8895 const struct deprecated_coproc_regs_s
*r
=
8896 deprecated_coproc_regs
+ i
;
8898 if (inst
.operands
[0].reg
== r
->cp
8899 && inst
.operands
[1].imm
== r
->opc1
8900 && inst
.operands
[3].reg
== r
->crn
8901 && inst
.operands
[4].reg
== r
->crm
8902 && inst
.operands
[5].imm
== r
->opc2
)
8904 if (! ARM_CPU_IS_ANY (cpu_variant
)
8905 && warn_on_deprecated
8906 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8907 as_tsktsk ("%s", r
->dep_msg
);
8911 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8912 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8913 inst
.instruction
|= Rd
<< 12;
8914 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8915 inst
.instruction
|= inst
.operands
[4].reg
;
8916 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8919 /* Transfer between coprocessor register and pair of ARM registers.
8920 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8925 Two XScale instructions are special cases of these:
8927 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8928 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8930 Result unpredictable if Rd or Rn is R15. */
8937 Rd
= inst
.operands
[2].reg
;
8938 Rn
= inst
.operands
[3].reg
;
8942 reject_bad_reg (Rd
);
8943 reject_bad_reg (Rn
);
8947 constraint (Rd
== REG_PC
, BAD_PC
);
8948 constraint (Rn
== REG_PC
, BAD_PC
);
8951 /* Only check the MRRC{2} variants. */
8952 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8954 /* If Rd == Rn, error that the operation is
8955 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8956 constraint (Rd
== Rn
, BAD_OVERLAP
);
8959 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8960 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8961 inst
.instruction
|= Rd
<< 12;
8962 inst
.instruction
|= Rn
<< 16;
8963 inst
.instruction
|= inst
.operands
[4].reg
;
8969 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8970 if (inst
.operands
[1].present
)
8972 inst
.instruction
|= CPSI_MMOD
;
8973 inst
.instruction
|= inst
.operands
[1].imm
;
8980 inst
.instruction
|= inst
.operands
[0].imm
;
8986 unsigned Rd
, Rn
, Rm
;
8988 Rd
= inst
.operands
[0].reg
;
8989 Rn
= (inst
.operands
[1].present
8990 ? inst
.operands
[1].reg
: Rd
);
8991 Rm
= inst
.operands
[2].reg
;
8993 constraint ((Rd
== REG_PC
), BAD_PC
);
8994 constraint ((Rn
== REG_PC
), BAD_PC
);
8995 constraint ((Rm
== REG_PC
), BAD_PC
);
8997 inst
.instruction
|= Rd
<< 16;
8998 inst
.instruction
|= Rn
<< 0;
8999 inst
.instruction
|= Rm
<< 8;
9005 /* There is no IT instruction in ARM mode. We
9006 process it to do the validation as if in
9007 thumb mode, just in case the code gets
9008 assembled for thumb using the unified syntax. */
9013 set_it_insn_type (IT_INSN
);
9014 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9015 now_it
.cc
= inst
.operands
[0].imm
;
9019 /* If there is only one register in the register list,
9020 then return its register number. Otherwise return -1. */
9022 only_one_reg_in_list (int range
)
9024 int i
= ffs (range
) - 1;
9025 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9029 encode_ldmstm(int from_push_pop_mnem
)
9031 int base_reg
= inst
.operands
[0].reg
;
9032 int range
= inst
.operands
[1].imm
;
9035 inst
.instruction
|= base_reg
<< 16;
9036 inst
.instruction
|= range
;
9038 if (inst
.operands
[1].writeback
)
9039 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9041 if (inst
.operands
[0].writeback
)
9043 inst
.instruction
|= WRITE_BACK
;
9044 /* Check for unpredictable uses of writeback. */
9045 if (inst
.instruction
& LOAD_BIT
)
9047 /* Not allowed in LDM type 2. */
9048 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9049 && ((range
& (1 << REG_PC
)) == 0))
9050 as_warn (_("writeback of base register is UNPREDICTABLE"));
9051 /* Only allowed if base reg not in list for other types. */
9052 else if (range
& (1 << base_reg
))
9053 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9057 /* Not allowed for type 2. */
9058 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9059 as_warn (_("writeback of base register is UNPREDICTABLE"));
9060 /* Only allowed if base reg not in list, or first in list. */
9061 else if ((range
& (1 << base_reg
))
9062 && (range
& ((1 << base_reg
) - 1)))
9063 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9067 /* If PUSH/POP has only one register, then use the A2 encoding. */
9068 one_reg
= only_one_reg_in_list (range
);
9069 if (from_push_pop_mnem
&& one_reg
>= 0)
9071 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9073 if (is_push
&& one_reg
== 13 /* SP */)
9074 /* PR 22483: The A2 encoding cannot be used when
9075 pushing the stack pointer as this is UNPREDICTABLE. */
9078 inst
.instruction
&= A_COND_MASK
;
9079 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9080 inst
.instruction
|= one_reg
<< 12;
9087 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9090 /* ARMv5TE load-consecutive (argument parse)
9099 constraint (inst
.operands
[0].reg
% 2 != 0,
9100 _("first transfer register must be even"));
9101 constraint (inst
.operands
[1].present
9102 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9103 _("can only transfer two consecutive registers"));
9104 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9105 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9107 if (!inst
.operands
[1].present
)
9108 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9110 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9111 register and the first register written; we have to diagnose
9112 overlap between the base and the second register written here. */
9114 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9115 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9116 as_warn (_("base register written back, and overlaps "
9117 "second transfer register"));
9119 if (!(inst
.instruction
& V4_STR_BIT
))
9121 /* For an index-register load, the index register must not overlap the
9122 destination (even if not write-back). */
9123 if (inst
.operands
[2].immisreg
9124 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9125 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9126 as_warn (_("index register overlaps transfer register"));
9128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9129 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9135 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9136 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9137 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9138 || inst
.operands
[1].negative
9139 /* This can arise if the programmer has written
9141 or if they have mistakenly used a register name as the last
9144 It is very difficult to distinguish between these two cases
9145 because "rX" might actually be a label. ie the register
9146 name has been occluded by a symbol of the same name. So we
9147 just generate a general 'bad addressing mode' type error
9148 message and leave it up to the programmer to discover the
9149 true cause and fix their mistake. */
9150 || (inst
.operands
[1].reg
== REG_PC
),
9153 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9154 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9155 _("offset must be zero in ARM encoding"));
9157 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9159 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9160 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9161 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9167 constraint (inst
.operands
[0].reg
% 2 != 0,
9168 _("even register required"));
9169 constraint (inst
.operands
[1].present
9170 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9171 _("can only load two consecutive registers"));
9172 /* If op 1 were present and equal to PC, this function wouldn't
9173 have been called in the first place. */
9174 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9176 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9177 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9180 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9181 which is not a multiple of four is UNPREDICTABLE. */
9183 check_ldr_r15_aligned (void)
9185 constraint (!(inst
.operands
[1].immisreg
)
9186 && (inst
.operands
[0].reg
== REG_PC
9187 && inst
.operands
[1].reg
== REG_PC
9188 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9189 _("ldr to register 15 must be 4-byte aligned"));
9195 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9196 if (!inst
.operands
[1].isreg
)
9197 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9199 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9200 check_ldr_r15_aligned ();
9206 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9208 if (inst
.operands
[1].preind
)
9210 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9211 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9212 _("this instruction requires a post-indexed address"));
9214 inst
.operands
[1].preind
= 0;
9215 inst
.operands
[1].postind
= 1;
9216 inst
.operands
[1].writeback
= 1;
9218 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9219 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9222 /* Halfword and signed-byte load/store operations. */
9227 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9228 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9229 if (!inst
.operands
[1].isreg
)
9230 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9232 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9238 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9240 if (inst
.operands
[1].preind
)
9242 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9243 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9244 _("this instruction requires a post-indexed address"));
9246 inst
.operands
[1].preind
= 0;
9247 inst
.operands
[1].postind
= 1;
9248 inst
.operands
[1].writeback
= 1;
9250 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9251 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9254 /* Co-processor register load/store.
9255 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9259 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9260 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9261 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9267 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9268 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9269 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9270 && !(inst
.instruction
& 0x00400000))
9271 as_tsktsk (_("Rd and Rm should be different in mla"));
9273 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9274 inst
.instruction
|= inst
.operands
[1].reg
;
9275 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9276 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9282 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9283 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9285 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9286 encode_arm_shifter_operand (1);
9289 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9296 top
= (inst
.instruction
& 0x00400000) != 0;
9297 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9298 _(":lower16: not allowed in this instruction"));
9299 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9300 _(":upper16: not allowed in this instruction"));
9301 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9302 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9304 imm
= inst
.relocs
[0].exp
.X_add_number
;
9305 /* The value is in two pieces: 0:11, 16:19. */
9306 inst
.instruction
|= (imm
& 0x00000fff);
9307 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9312 do_vfp_nsyn_mrs (void)
9314 if (inst
.operands
[0].isvec
)
9316 if (inst
.operands
[1].reg
!= 1)
9317 first_error (_("operand 1 must be FPSCR"));
9318 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9319 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9320 do_vfp_nsyn_opcode ("fmstat");
9322 else if (inst
.operands
[1].isvec
)
9323 do_vfp_nsyn_opcode ("fmrx");
9331 do_vfp_nsyn_msr (void)
9333 if (inst
.operands
[0].isvec
)
9334 do_vfp_nsyn_opcode ("fmxr");
9344 unsigned Rt
= inst
.operands
[0].reg
;
9346 if (thumb_mode
&& Rt
== REG_SP
)
9348 inst
.error
= BAD_SP
;
9352 /* MVFR2 is only valid at ARMv8-A. */
9353 if (inst
.operands
[1].reg
== 5)
9354 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9357 /* APSR_ sets isvec. All other refs to PC are illegal. */
9358 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9360 inst
.error
= BAD_PC
;
9364 /* If we get through parsing the register name, we just insert the number
9365 generated into the instruction without further validation. */
9366 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9367 inst
.instruction
|= (Rt
<< 12);
9373 unsigned Rt
= inst
.operands
[1].reg
;
9376 reject_bad_reg (Rt
);
9377 else if (Rt
== REG_PC
)
9379 inst
.error
= BAD_PC
;
9383 /* MVFR2 is only valid for ARMv8-A. */
9384 if (inst
.operands
[0].reg
== 5)
9385 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9388 /* If we get through parsing the register name, we just insert the number
9389 generated into the instruction without further validation. */
9390 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9391 inst
.instruction
|= (Rt
<< 12);
9399 if (do_vfp_nsyn_mrs () == SUCCESS
)
9402 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9403 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9405 if (inst
.operands
[1].isreg
)
9407 br
= inst
.operands
[1].reg
;
9408 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9409 as_bad (_("bad register for mrs"));
9413 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9414 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9416 _("'APSR', 'CPSR' or 'SPSR' expected"));
9417 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9420 inst
.instruction
|= br
;
9423 /* Two possible forms:
9424 "{C|S}PSR_<field>, Rm",
9425 "{C|S}PSR_f, #expression". */
9430 if (do_vfp_nsyn_msr () == SUCCESS
)
9433 inst
.instruction
|= inst
.operands
[0].imm
;
9434 if (inst
.operands
[1].isreg
)
9435 inst
.instruction
|= inst
.operands
[1].reg
;
9438 inst
.instruction
|= INST_IMMEDIATE
;
9439 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9440 inst
.relocs
[0].pc_rel
= 0;
9447 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9449 if (!inst
.operands
[2].present
)
9450 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9451 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9452 inst
.instruction
|= inst
.operands
[1].reg
;
9453 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9455 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9456 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9457 as_tsktsk (_("Rd and Rm should be different in mul"));
9460 /* Long Multiply Parser
9461 UMULL RdLo, RdHi, Rm, Rs
9462 SMULL RdLo, RdHi, Rm, Rs
9463 UMLAL RdLo, RdHi, Rm, Rs
9464 SMLAL RdLo, RdHi, Rm, Rs. */
9469 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9470 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9471 inst
.instruction
|= inst
.operands
[2].reg
;
9472 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9474 /* rdhi and rdlo must be different. */
9475 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9476 as_tsktsk (_("rdhi and rdlo must be different"));
9478 /* rdhi, rdlo and rm must all be different before armv6. */
9479 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9480 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9481 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9482 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9488 if (inst
.operands
[0].present
9489 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9491 /* Architectural NOP hints are CPSR sets with no bits selected. */
9492 inst
.instruction
&= 0xf0000000;
9493 inst
.instruction
|= 0x0320f000;
9494 if (inst
.operands
[0].present
)
9495 inst
.instruction
|= inst
.operands
[0].imm
;
9499 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9500 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9501 Condition defaults to COND_ALWAYS.
9502 Error if Rd, Rn or Rm are R15. */
9507 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9508 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9509 inst
.instruction
|= inst
.operands
[2].reg
;
9510 if (inst
.operands
[3].present
)
9511 encode_arm_shift (3);
9514 /* ARM V6 PKHTB (Argument Parse). */
9519 if (!inst
.operands
[3].present
)
9521 /* If the shift specifier is omitted, turn the instruction
9522 into pkhbt rd, rm, rn. */
9523 inst
.instruction
&= 0xfff00010;
9524 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9525 inst
.instruction
|= inst
.operands
[1].reg
;
9526 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9530 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9531 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9532 inst
.instruction
|= inst
.operands
[2].reg
;
9533 encode_arm_shift (3);
9537 /* ARMv5TE: Preload-Cache
9538 MP Extensions: Preload for write
9542 Syntactically, like LDR with B=1, W=0, L=1. */
9547 constraint (!inst
.operands
[0].isreg
,
9548 _("'[' expected after PLD mnemonic"));
9549 constraint (inst
.operands
[0].postind
,
9550 _("post-indexed expression used in preload instruction"));
9551 constraint (inst
.operands
[0].writeback
,
9552 _("writeback used in preload instruction"));
9553 constraint (!inst
.operands
[0].preind
,
9554 _("unindexed addressing used in preload instruction"));
9555 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9558 /* ARMv7: PLI <addr_mode> */
9562 constraint (!inst
.operands
[0].isreg
,
9563 _("'[' expected after PLI mnemonic"));
9564 constraint (inst
.operands
[0].postind
,
9565 _("post-indexed expression used in preload instruction"));
9566 constraint (inst
.operands
[0].writeback
,
9567 _("writeback used in preload instruction"));
9568 constraint (!inst
.operands
[0].preind
,
9569 _("unindexed addressing used in preload instruction"));
9570 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9571 inst
.instruction
&= ~PRE_INDEX
;
9577 constraint (inst
.operands
[0].writeback
,
9578 _("push/pop do not support {reglist}^"));
9579 inst
.operands
[1] = inst
.operands
[0];
9580 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9581 inst
.operands
[0].isreg
= 1;
9582 inst
.operands
[0].writeback
= 1;
9583 inst
.operands
[0].reg
= REG_SP
;
9584 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9587 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9588 word at the specified address and the following word
9590 Unconditionally executed.
9591 Error if Rn is R15. */
9596 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9597 if (inst
.operands
[0].writeback
)
9598 inst
.instruction
|= WRITE_BACK
;
9601 /* ARM V6 ssat (argument parse). */
9606 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9607 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9608 inst
.instruction
|= inst
.operands
[2].reg
;
9610 if (inst
.operands
[3].present
)
9611 encode_arm_shift (3);
9614 /* ARM V6 usat (argument parse). */
9619 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9620 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9621 inst
.instruction
|= inst
.operands
[2].reg
;
9623 if (inst
.operands
[3].present
)
9624 encode_arm_shift (3);
9627 /* ARM V6 ssat16 (argument parse). */
9632 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9633 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9634 inst
.instruction
|= inst
.operands
[2].reg
;
9640 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9641 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9642 inst
.instruction
|= inst
.operands
[2].reg
;
9645 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9646 preserving the other bits.
9648 setend <endian_specifier>, where <endian_specifier> is either
9654 if (warn_on_deprecated
9655 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9656 as_tsktsk (_("setend use is deprecated for ARMv8"));
9658 if (inst
.operands
[0].imm
)
9659 inst
.instruction
|= 0x200;
9665 unsigned int Rm
= (inst
.operands
[1].present
9666 ? inst
.operands
[1].reg
9667 : inst
.operands
[0].reg
);
9669 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9670 inst
.instruction
|= Rm
;
9671 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9673 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9674 inst
.instruction
|= SHIFT_BY_REG
;
9675 /* PR 12854: Error on extraneous shifts. */
9676 constraint (inst
.operands
[2].shifted
,
9677 _("extraneous shift as part of operand to shift insn"));
9680 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
9686 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
9687 inst
.relocs
[0].pc_rel
= 0;
9693 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
9694 inst
.relocs
[0].pc_rel
= 0;
9700 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
9701 inst
.relocs
[0].pc_rel
= 0;
9707 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9708 _("selected processor does not support SETPAN instruction"));
9710 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9716 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9717 _("selected processor does not support SETPAN instruction"));
9719 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9722 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9723 SMLAxy{cond} Rd,Rm,Rs,Rn
9724 SMLAWy{cond} Rd,Rm,Rs,Rn
9725 Error if any register is R15. */
9730 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9731 inst
.instruction
|= inst
.operands
[1].reg
;
9732 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9733 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9736 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9737 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9738 Error if any register is R15.
9739 Warning if Rdlo == Rdhi. */
9744 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9745 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9746 inst
.instruction
|= inst
.operands
[2].reg
;
9747 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9749 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9750 as_tsktsk (_("rdhi and rdlo must be different"));
9753 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9754 SMULxy{cond} Rd,Rm,Rs
9755 Error if any register is R15. */
9760 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9761 inst
.instruction
|= inst
.operands
[1].reg
;
9762 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9765 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9766 the same for both ARM and Thumb-2. */
9773 if (inst
.operands
[0].present
)
9775 reg
= inst
.operands
[0].reg
;
9776 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9781 inst
.instruction
|= reg
<< 16;
9782 inst
.instruction
|= inst
.operands
[1].imm
;
9783 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9784 inst
.instruction
|= WRITE_BACK
;
9787 /* ARM V6 strex (argument parse). */
9792 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9793 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9794 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9795 || inst
.operands
[2].negative
9796 /* See comment in do_ldrex(). */
9797 || (inst
.operands
[2].reg
== REG_PC
),
9800 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9801 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9803 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9804 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9805 _("offset must be zero in ARM encoding"));
9807 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9808 inst
.instruction
|= inst
.operands
[1].reg
;
9809 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9810 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9816 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9817 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9818 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9819 || inst
.operands
[2].negative
,
9822 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9823 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9831 constraint (inst
.operands
[1].reg
% 2 != 0,
9832 _("even register required"));
9833 constraint (inst
.operands
[2].present
9834 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9835 _("can only store two consecutive registers"));
9836 /* If op 2 were present and equal to PC, this function wouldn't
9837 have been called in the first place. */
9838 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9840 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9841 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9842 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9845 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9846 inst
.instruction
|= inst
.operands
[1].reg
;
9847 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9854 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9855 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9863 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9864 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9869 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9870 extends it to 32-bits, and adds the result to a value in another
9871 register. You can specify a rotation by 0, 8, 16, or 24 bits
9872 before extracting the 16-bit value.
9873 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9874 Condition defaults to COND_ALWAYS.
9875 Error if any register uses R15. */
9880 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9881 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9882 inst
.instruction
|= inst
.operands
[2].reg
;
9883 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9888 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9889 Condition defaults to COND_ALWAYS.
9890 Error if any register uses R15. */
9895 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9896 inst
.instruction
|= inst
.operands
[1].reg
;
9897 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9900 /* VFP instructions. In a logical order: SP variant first, monad
9901 before dyad, arithmetic then move then load/store. */
9904 do_vfp_sp_monadic (void)
9906 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9907 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9911 do_vfp_sp_dyadic (void)
9913 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9914 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9915 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9919 do_vfp_sp_compare_z (void)
9921 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9925 do_vfp_dp_sp_cvt (void)
9927 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9928 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9932 do_vfp_sp_dp_cvt (void)
9934 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9935 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9939 do_vfp_reg_from_sp (void)
9941 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9942 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9946 do_vfp_reg2_from_sp2 (void)
9948 constraint (inst
.operands
[2].imm
!= 2,
9949 _("only two consecutive VFP SP registers allowed here"));
9950 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9951 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9952 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9956 do_vfp_sp_from_reg (void)
9958 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9959 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9963 do_vfp_sp2_from_reg2 (void)
9965 constraint (inst
.operands
[0].imm
!= 2,
9966 _("only two consecutive VFP SP registers allowed here"));
9967 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9968 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9969 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9973 do_vfp_sp_ldst (void)
9975 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9976 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9980 do_vfp_dp_ldst (void)
9982 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9983 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9988 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9990 if (inst
.operands
[0].writeback
)
9991 inst
.instruction
|= WRITE_BACK
;
9993 constraint (ldstm_type
!= VFP_LDSTMIA
,
9994 _("this addressing mode requires base-register writeback"));
9995 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9996 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9997 inst
.instruction
|= inst
.operands
[1].imm
;
10001 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10005 if (inst
.operands
[0].writeback
)
10006 inst
.instruction
|= WRITE_BACK
;
10008 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10009 _("this addressing mode requires base-register writeback"));
10011 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10012 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10014 count
= inst
.operands
[1].imm
<< 1;
10015 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10018 inst
.instruction
|= count
;
10022 do_vfp_sp_ldstmia (void)
10024 vfp_sp_ldstm (VFP_LDSTMIA
);
10028 do_vfp_sp_ldstmdb (void)
10030 vfp_sp_ldstm (VFP_LDSTMDB
);
10034 do_vfp_dp_ldstmia (void)
10036 vfp_dp_ldstm (VFP_LDSTMIA
);
10040 do_vfp_dp_ldstmdb (void)
10042 vfp_dp_ldstm (VFP_LDSTMDB
);
10046 do_vfp_xp_ldstmia (void)
10048 vfp_dp_ldstm (VFP_LDSTMIAX
);
10052 do_vfp_xp_ldstmdb (void)
10054 vfp_dp_ldstm (VFP_LDSTMDBX
);
10058 do_vfp_dp_rd_rm (void)
10060 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10061 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10065 do_vfp_dp_rn_rd (void)
10067 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10068 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10072 do_vfp_dp_rd_rn (void)
10074 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10075 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10079 do_vfp_dp_rd_rn_rm (void)
10081 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10082 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10083 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10087 do_vfp_dp_rd (void)
10089 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10093 do_vfp_dp_rm_rd_rn (void)
10095 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10096 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10097 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10100 /* VFPv3 instructions. */
10102 do_vfp_sp_const (void)
10104 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10105 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10106 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10110 do_vfp_dp_const (void)
10112 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10113 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10114 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10118 vfp_conv (int srcsize
)
10120 int immbits
= srcsize
- inst
.operands
[1].imm
;
10122 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10124 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10125 i.e. immbits must be in range 0 - 16. */
10126 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10129 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10131 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10132 i.e. immbits must be in range 0 - 31. */
10133 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10137 inst
.instruction
|= (immbits
& 1) << 5;
10138 inst
.instruction
|= (immbits
>> 1);
10142 do_vfp_sp_conv_16 (void)
10144 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10149 do_vfp_dp_conv_16 (void)
10151 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10156 do_vfp_sp_conv_32 (void)
10158 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10163 do_vfp_dp_conv_32 (void)
10165 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10169 /* FPA instructions. Also in a logical order. */
10174 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10175 inst
.instruction
|= inst
.operands
[1].reg
;
10179 do_fpa_ldmstm (void)
10181 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10182 switch (inst
.operands
[1].imm
)
10184 case 1: inst
.instruction
|= CP_T_X
; break;
10185 case 2: inst
.instruction
|= CP_T_Y
; break;
10186 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10191 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10193 /* The instruction specified "ea" or "fd", so we can only accept
10194 [Rn]{!}. The instruction does not really support stacking or
10195 unstacking, so we have to emulate these by setting appropriate
10196 bits and offsets. */
10197 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10198 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10199 _("this instruction does not support indexing"));
10201 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10202 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10204 if (!(inst
.instruction
& INDEX_UP
))
10205 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10207 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10209 inst
.operands
[2].preind
= 0;
10210 inst
.operands
[2].postind
= 1;
10214 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10217 /* iWMMXt instructions: strictly in alphabetical order. */
10220 do_iwmmxt_tandorc (void)
10222 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10226 do_iwmmxt_textrc (void)
10228 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10229 inst
.instruction
|= inst
.operands
[1].imm
;
10233 do_iwmmxt_textrm (void)
10235 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10236 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10237 inst
.instruction
|= inst
.operands
[2].imm
;
10241 do_iwmmxt_tinsr (void)
10243 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10244 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10245 inst
.instruction
|= inst
.operands
[2].imm
;
10249 do_iwmmxt_tmia (void)
10251 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10252 inst
.instruction
|= inst
.operands
[1].reg
;
10253 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10257 do_iwmmxt_waligni (void)
10259 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10260 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10261 inst
.instruction
|= inst
.operands
[2].reg
;
10262 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10266 do_iwmmxt_wmerge (void)
10268 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10269 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10270 inst
.instruction
|= inst
.operands
[2].reg
;
10271 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10275 do_iwmmxt_wmov (void)
10277 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10278 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10279 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10280 inst
.instruction
|= inst
.operands
[1].reg
;
10284 do_iwmmxt_wldstbh (void)
10287 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10289 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10291 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10292 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10296 do_iwmmxt_wldstw (void)
10298 /* RIWR_RIWC clears .isreg for a control register. */
10299 if (!inst
.operands
[0].isreg
)
10301 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10302 inst
.instruction
|= 0xf0000000;
10305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10306 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10310 do_iwmmxt_wldstd (void)
10312 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10313 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10314 && inst
.operands
[1].immisreg
)
10316 inst
.instruction
&= ~0x1a000ff;
10317 inst
.instruction
|= (0xfU
<< 28);
10318 if (inst
.operands
[1].preind
)
10319 inst
.instruction
|= PRE_INDEX
;
10320 if (!inst
.operands
[1].negative
)
10321 inst
.instruction
|= INDEX_UP
;
10322 if (inst
.operands
[1].writeback
)
10323 inst
.instruction
|= WRITE_BACK
;
10324 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10325 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10326 inst
.instruction
|= inst
.operands
[1].imm
;
10329 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10333 do_iwmmxt_wshufh (void)
10335 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10336 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10337 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10338 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10342 do_iwmmxt_wzero (void)
10344 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10345 inst
.instruction
|= inst
.operands
[0].reg
;
10346 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10347 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10351 do_iwmmxt_wrwrwr_or_imm5 (void)
10353 if (inst
.operands
[2].isreg
)
10356 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10357 _("immediate operand requires iWMMXt2"));
10359 if (inst
.operands
[2].imm
== 0)
10361 switch ((inst
.instruction
>> 20) & 0xf)
10367 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10368 inst
.operands
[2].imm
= 16;
10369 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10375 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10376 inst
.operands
[2].imm
= 32;
10377 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10384 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10386 wrn
= (inst
.instruction
>> 16) & 0xf;
10387 inst
.instruction
&= 0xff0fff0f;
10388 inst
.instruction
|= wrn
;
10389 /* Bail out here; the instruction is now assembled. */
10394 /* Map 32 -> 0, etc. */
10395 inst
.operands
[2].imm
&= 0x1f;
10396 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10400 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10401 operations first, then control, shift, and load/store. */
10403 /* Insns like "foo X,Y,Z". */
10406 do_mav_triple (void)
10408 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10409 inst
.instruction
|= inst
.operands
[1].reg
;
10410 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10413 /* Insns like "foo W,X,Y,Z".
10414 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10419 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10420 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10421 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10422 inst
.instruction
|= inst
.operands
[3].reg
;
10425 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10427 do_mav_dspsc (void)
10429 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10432 /* Maverick shift immediate instructions.
10433 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10434 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10437 do_mav_shift (void)
10439 int imm
= inst
.operands
[2].imm
;
10441 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10442 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10444 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10445 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10446 Bit 4 should be 0. */
10447 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10449 inst
.instruction
|= imm
;
10452 /* XScale instructions. Also sorted arithmetic before move. */
10454 /* Xscale multiply-accumulate (argument parse)
10457 MIAxycc acc0,Rm,Rs. */
10462 inst
.instruction
|= inst
.operands
[1].reg
;
10463 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10466 /* Xscale move-accumulator-register (argument parse)
10468 MARcc acc0,RdLo,RdHi. */
10473 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10474 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10477 /* Xscale move-register-accumulator (argument parse)
10479 MRAcc RdLo,RdHi,acc0. */
10484 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10485 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10486 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10489 /* Encoding functions relevant only to Thumb. */
10491 /* inst.operands[i] is a shifted-register operand; encode
10492 it into inst.instruction in the format used by Thumb32. */
10495 encode_thumb32_shifted_operand (int i
)
10497 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10498 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10500 constraint (inst
.operands
[i
].immisreg
,
10501 _("shift by register not allowed in thumb mode"));
10502 inst
.instruction
|= inst
.operands
[i
].reg
;
10503 if (shift
== SHIFT_RRX
)
10504 inst
.instruction
|= SHIFT_ROR
<< 4;
10507 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10508 _("expression too complex"));
10510 constraint (value
> 32
10511 || (value
== 32 && (shift
== SHIFT_LSL
10512 || shift
== SHIFT_ROR
)),
10513 _("shift expression is too large"));
10517 else if (value
== 32)
10520 inst
.instruction
|= shift
<< 4;
10521 inst
.instruction
|= (value
& 0x1c) << 10;
10522 inst
.instruction
|= (value
& 0x03) << 6;
10527 /* inst.operands[i] was set up by parse_address. Encode it into a
10528 Thumb32 format load or store instruction. Reject forms that cannot
10529 be used with such instructions. If is_t is true, reject forms that
10530 cannot be used with a T instruction; if is_d is true, reject forms
10531 that cannot be used with a D instruction. If it is a store insn,
10532 reject PC in Rn. */
10535 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10537 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10539 constraint (!inst
.operands
[i
].isreg
,
10540 _("Instruction does not support =N addresses"));
10542 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10543 if (inst
.operands
[i
].immisreg
)
10545 constraint (is_pc
, BAD_PC_ADDRESSING
);
10546 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10547 constraint (inst
.operands
[i
].negative
,
10548 _("Thumb does not support negative register indexing"));
10549 constraint (inst
.operands
[i
].postind
,
10550 _("Thumb does not support register post-indexing"));
10551 constraint (inst
.operands
[i
].writeback
,
10552 _("Thumb does not support register indexing with writeback"));
10553 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10554 _("Thumb supports only LSL in shifted register indexing"));
10556 inst
.instruction
|= inst
.operands
[i
].imm
;
10557 if (inst
.operands
[i
].shifted
)
10559 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10560 _("expression too complex"));
10561 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
10562 || inst
.relocs
[0].exp
.X_add_number
> 3,
10563 _("shift out of range"));
10564 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10566 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10568 else if (inst
.operands
[i
].preind
)
10570 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10571 constraint (is_t
&& inst
.operands
[i
].writeback
,
10572 _("cannot use writeback with this instruction"));
10573 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10574 BAD_PC_ADDRESSING
);
10578 inst
.instruction
|= 0x01000000;
10579 if (inst
.operands
[i
].writeback
)
10580 inst
.instruction
|= 0x00200000;
10584 inst
.instruction
|= 0x00000c00;
10585 if (inst
.operands
[i
].writeback
)
10586 inst
.instruction
|= 0x00000100;
10588 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10590 else if (inst
.operands
[i
].postind
)
10592 gas_assert (inst
.operands
[i
].writeback
);
10593 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10594 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10597 inst
.instruction
|= 0x00200000;
10599 inst
.instruction
|= 0x00000900;
10600 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10602 else /* unindexed - only for coprocessor */
10603 inst
.error
= _("instruction does not accept unindexed addressing");
10606 /* Table of Thumb instructions which exist in both 16- and 32-bit
10607 encodings (the latter only in post-V6T2 cores). The index is the
10608 value used in the insns table below. When there is more than one
10609 possible 16-bit encoding for the instruction, this table always
10611 Also contains several pseudo-instructions used during relaxation. */
10612 #define T16_32_TAB \
10613 X(_adc, 4140, eb400000), \
10614 X(_adcs, 4140, eb500000), \
10615 X(_add, 1c00, eb000000), \
10616 X(_adds, 1c00, eb100000), \
10617 X(_addi, 0000, f1000000), \
10618 X(_addis, 0000, f1100000), \
10619 X(_add_pc,000f, f20f0000), \
10620 X(_add_sp,000d, f10d0000), \
10621 X(_adr, 000f, f20f0000), \
10622 X(_and, 4000, ea000000), \
10623 X(_ands, 4000, ea100000), \
10624 X(_asr, 1000, fa40f000), \
10625 X(_asrs, 1000, fa50f000), \
10626 X(_b, e000, f000b000), \
10627 X(_bcond, d000, f0008000), \
10628 X(_bf, 0000, f040e001), \
10629 X(_bfcsel,0000, f000e001), \
10630 X(_bfx, 0000, f060e001), \
10631 X(_bfl, 0000, f000c001), \
10632 X(_bflx, 0000, f070e001), \
10633 X(_bic, 4380, ea200000), \
10634 X(_bics, 4380, ea300000), \
10635 X(_cmn, 42c0, eb100f00), \
10636 X(_cmp, 2800, ebb00f00), \
10637 X(_cpsie, b660, f3af8400), \
10638 X(_cpsid, b670, f3af8600), \
10639 X(_cpy, 4600, ea4f0000), \
10640 X(_dec_sp,80dd, f1ad0d00), \
10641 X(_dls, 0000, f040e001), \
10642 X(_eor, 4040, ea800000), \
10643 X(_eors, 4040, ea900000), \
10644 X(_inc_sp,00dd, f10d0d00), \
10645 X(_ldmia, c800, e8900000), \
10646 X(_ldr, 6800, f8500000), \
10647 X(_ldrb, 7800, f8100000), \
10648 X(_ldrh, 8800, f8300000), \
10649 X(_ldrsb, 5600, f9100000), \
10650 X(_ldrsh, 5e00, f9300000), \
10651 X(_ldr_pc,4800, f85f0000), \
10652 X(_ldr_pc2,4800, f85f0000), \
10653 X(_ldr_sp,9800, f85d0000), \
10654 X(_le, 0000, f00fc001), \
10655 X(_lsl, 0000, fa00f000), \
10656 X(_lsls, 0000, fa10f000), \
10657 X(_lsr, 0800, fa20f000), \
10658 X(_lsrs, 0800, fa30f000), \
10659 X(_mov, 2000, ea4f0000), \
10660 X(_movs, 2000, ea5f0000), \
10661 X(_mul, 4340, fb00f000), \
10662 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10663 X(_mvn, 43c0, ea6f0000), \
10664 X(_mvns, 43c0, ea7f0000), \
10665 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10666 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10667 X(_orr, 4300, ea400000), \
10668 X(_orrs, 4300, ea500000), \
10669 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10670 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10671 X(_rev, ba00, fa90f080), \
10672 X(_rev16, ba40, fa90f090), \
10673 X(_revsh, bac0, fa90f0b0), \
10674 X(_ror, 41c0, fa60f000), \
10675 X(_rors, 41c0, fa70f000), \
10676 X(_sbc, 4180, eb600000), \
10677 X(_sbcs, 4180, eb700000), \
10678 X(_stmia, c000, e8800000), \
10679 X(_str, 6000, f8400000), \
10680 X(_strb, 7000, f8000000), \
10681 X(_strh, 8000, f8200000), \
10682 X(_str_sp,9000, f84d0000), \
10683 X(_sub, 1e00, eba00000), \
10684 X(_subs, 1e00, ebb00000), \
10685 X(_subi, 8000, f1a00000), \
10686 X(_subis, 8000, f1b00000), \
10687 X(_sxtb, b240, fa4ff080), \
10688 X(_sxth, b200, fa0ff080), \
10689 X(_tst, 4200, ea100f00), \
10690 X(_uxtb, b2c0, fa5ff080), \
10691 X(_uxth, b280, fa1ff080), \
10692 X(_nop, bf00, f3af8000), \
10693 X(_yield, bf10, f3af8001), \
10694 X(_wfe, bf20, f3af8002), \
10695 X(_wfi, bf30, f3af8003), \
10696 X(_wls, 0000, f040c001), \
10697 X(_sev, bf40, f3af8004), \
10698 X(_sevl, bf50, f3af8005), \
10699 X(_udf, de00, f7f0a000)
10701 /* To catch errors in encoding functions, the codes are all offset by
10702 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10703 as 16-bit instructions. */
10704 #define X(a,b,c) T_MNEM##a
10705 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10708 #define X(a,b,c) 0x##b
10709 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10710 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10713 #define X(a,b,c) 0x##c
10714 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10715 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10716 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10720 /* Thumb instruction encoders, in alphabetical order. */
10722 /* ADDW or SUBW. */
10725 do_t_add_sub_w (void)
10729 Rd
= inst
.operands
[0].reg
;
10730 Rn
= inst
.operands
[1].reg
;
10732 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10733 is the SP-{plus,minus}-immediate form of the instruction. */
10735 constraint (Rd
== REG_PC
, BAD_PC
);
10737 reject_bad_reg (Rd
);
10739 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10740 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
10743 /* Parse an add or subtract instruction. We get here with inst.instruction
10744 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10747 do_t_add_sub (void)
10751 Rd
= inst
.operands
[0].reg
;
10752 Rs
= (inst
.operands
[1].present
10753 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10754 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10757 set_it_insn_type_last ();
10759 if (unified_syntax
)
10762 bfd_boolean narrow
;
10765 flags
= (inst
.instruction
== T_MNEM_adds
10766 || inst
.instruction
== T_MNEM_subs
);
10768 narrow
= !in_it_block ();
10770 narrow
= in_it_block ();
10771 if (!inst
.operands
[2].isreg
)
10775 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10776 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10778 add
= (inst
.instruction
== T_MNEM_add
10779 || inst
.instruction
== T_MNEM_adds
);
10781 if (inst
.size_req
!= 4)
10783 /* Attempt to use a narrow opcode, with relaxation if
10785 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10786 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10787 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10788 opcode
= T_MNEM_add_sp
;
10789 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10790 opcode
= T_MNEM_add_pc
;
10791 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10794 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10796 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10800 inst
.instruction
= THUMB_OP16(opcode
);
10801 inst
.instruction
|= (Rd
<< 4) | Rs
;
10802 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10803 || (inst
.relocs
[0].type
10804 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
10806 if (inst
.size_req
== 2)
10807 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
10809 inst
.relax
= opcode
;
10813 constraint (inst
.size_req
== 2, BAD_HIREG
);
10815 if (inst
.size_req
== 4
10816 || (inst
.size_req
!= 2 && !opcode
))
10818 constraint ((inst
.relocs
[0].type
10819 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
10820 && (inst
.relocs
[0].type
10821 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
10822 THUMB1_RELOC_ONLY
);
10825 constraint (add
, BAD_PC
);
10826 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10827 _("only SUBS PC, LR, #const allowed"));
10828 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10829 _("expression too complex"));
10830 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
10831 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
10832 _("immediate value out of range"));
10833 inst
.instruction
= T2_SUBS_PC_LR
10834 | inst
.relocs
[0].exp
.X_add_number
;
10835 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10838 else if (Rs
== REG_PC
)
10840 /* Always use addw/subw. */
10841 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10842 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
10846 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10847 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10850 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10852 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10854 inst
.instruction
|= Rd
<< 8;
10855 inst
.instruction
|= Rs
<< 16;
10860 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10861 unsigned int shift
= inst
.operands
[2].shift_kind
;
10863 Rn
= inst
.operands
[2].reg
;
10864 /* See if we can do this with a 16-bit instruction. */
10865 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10867 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10872 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10873 || inst
.instruction
== T_MNEM_add
)
10875 : T_OPCODE_SUB_R3
);
10876 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10880 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10882 /* Thumb-1 cores (except v6-M) require at least one high
10883 register in a narrow non flag setting add. */
10884 if (Rd
> 7 || Rn
> 7
10885 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10886 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10893 inst
.instruction
= T_OPCODE_ADD_HI
;
10894 inst
.instruction
|= (Rd
& 8) << 4;
10895 inst
.instruction
|= (Rd
& 7);
10896 inst
.instruction
|= Rn
<< 3;
10902 constraint (Rd
== REG_PC
, BAD_PC
);
10903 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10904 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10905 constraint (Rs
== REG_PC
, BAD_PC
);
10906 reject_bad_reg (Rn
);
10908 /* If we get here, it can't be done in 16 bits. */
10909 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10910 _("shift must be constant"));
10911 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10912 inst
.instruction
|= Rd
<< 8;
10913 inst
.instruction
|= Rs
<< 16;
10914 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10915 _("shift value over 3 not allowed in thumb mode"));
10916 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10917 _("only LSL shift allowed in thumb mode"));
10918 encode_thumb32_shifted_operand (2);
10923 constraint (inst
.instruction
== T_MNEM_adds
10924 || inst
.instruction
== T_MNEM_subs
,
10927 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10929 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10930 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10933 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10934 ? 0x0000 : 0x8000);
10935 inst
.instruction
|= (Rd
<< 4) | Rs
;
10936 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
10940 Rn
= inst
.operands
[2].reg
;
10941 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10943 /* We now have Rd, Rs, and Rn set to registers. */
10944 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10946 /* Can't do this for SUB. */
10947 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10948 inst
.instruction
= T_OPCODE_ADD_HI
;
10949 inst
.instruction
|= (Rd
& 8) << 4;
10950 inst
.instruction
|= (Rd
& 7);
10952 inst
.instruction
|= Rn
<< 3;
10954 inst
.instruction
|= Rs
<< 3;
10956 constraint (1, _("dest must overlap one source register"));
10960 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10961 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10962 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10972 Rd
= inst
.operands
[0].reg
;
10973 reject_bad_reg (Rd
);
10975 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10977 /* Defer to section relaxation. */
10978 inst
.relax
= inst
.instruction
;
10979 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10980 inst
.instruction
|= Rd
<< 4;
10982 else if (unified_syntax
&& inst
.size_req
!= 2)
10984 /* Generate a 32-bit opcode. */
10985 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10986 inst
.instruction
|= Rd
<< 8;
10987 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10988 inst
.relocs
[0].pc_rel
= 1;
10992 /* Generate a 16-bit opcode. */
10993 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10994 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
10995 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
10996 inst
.relocs
[0].pc_rel
= 1;
10997 inst
.instruction
|= Rd
<< 4;
11000 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11001 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11002 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11003 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11004 inst
.relocs
[0].exp
.X_add_number
+= 1;
11007 /* Arithmetic instructions for which there is just one 16-bit
11008 instruction encoding, and it allows only two low registers.
11009 For maximal compatibility with ARM syntax, we allow three register
11010 operands even when Thumb-32 instructions are not available, as long
11011 as the first two are identical. For instance, both "sbc r0,r1" and
11012 "sbc r0,r0,r1" are allowed. */
11018 Rd
= inst
.operands
[0].reg
;
11019 Rs
= (inst
.operands
[1].present
11020 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11021 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11022 Rn
= inst
.operands
[2].reg
;
11024 reject_bad_reg (Rd
);
11025 reject_bad_reg (Rs
);
11026 if (inst
.operands
[2].isreg
)
11027 reject_bad_reg (Rn
);
11029 if (unified_syntax
)
11031 if (!inst
.operands
[2].isreg
)
11033 /* For an immediate, we always generate a 32-bit opcode;
11034 section relaxation will shrink it later if possible. */
11035 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11036 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11037 inst
.instruction
|= Rd
<< 8;
11038 inst
.instruction
|= Rs
<< 16;
11039 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11043 bfd_boolean narrow
;
11045 /* See if we can do this with a 16-bit instruction. */
11046 if (THUMB_SETS_FLAGS (inst
.instruction
))
11047 narrow
= !in_it_block ();
11049 narrow
= in_it_block ();
11051 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11053 if (inst
.operands
[2].shifted
)
11055 if (inst
.size_req
== 4)
11061 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11062 inst
.instruction
|= Rd
;
11063 inst
.instruction
|= Rn
<< 3;
11067 /* If we get here, it can't be done in 16 bits. */
11068 constraint (inst
.operands
[2].shifted
11069 && inst
.operands
[2].immisreg
,
11070 _("shift must be constant"));
11071 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11072 inst
.instruction
|= Rd
<< 8;
11073 inst
.instruction
|= Rs
<< 16;
11074 encode_thumb32_shifted_operand (2);
11079 /* On its face this is a lie - the instruction does set the
11080 flags. However, the only supported mnemonic in this mode
11081 says it doesn't. */
11082 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11084 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11085 _("unshifted register required"));
11086 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11087 constraint (Rd
!= Rs
,
11088 _("dest and source1 must be the same register"));
11090 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11091 inst
.instruction
|= Rd
;
11092 inst
.instruction
|= Rn
<< 3;
11096 /* Similarly, but for instructions where the arithmetic operation is
11097 commutative, so we can allow either of them to be different from
11098 the destination operand in a 16-bit instruction. For instance, all
11099 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11106 Rd
= inst
.operands
[0].reg
;
11107 Rs
= (inst
.operands
[1].present
11108 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11109 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11110 Rn
= inst
.operands
[2].reg
;
11112 reject_bad_reg (Rd
);
11113 reject_bad_reg (Rs
);
11114 if (inst
.operands
[2].isreg
)
11115 reject_bad_reg (Rn
);
11117 if (unified_syntax
)
11119 if (!inst
.operands
[2].isreg
)
11121 /* For an immediate, we always generate a 32-bit opcode;
11122 section relaxation will shrink it later if possible. */
11123 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11124 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11125 inst
.instruction
|= Rd
<< 8;
11126 inst
.instruction
|= Rs
<< 16;
11127 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11131 bfd_boolean narrow
;
11133 /* See if we can do this with a 16-bit instruction. */
11134 if (THUMB_SETS_FLAGS (inst
.instruction
))
11135 narrow
= !in_it_block ();
11137 narrow
= in_it_block ();
11139 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11141 if (inst
.operands
[2].shifted
)
11143 if (inst
.size_req
== 4)
11150 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11151 inst
.instruction
|= Rd
;
11152 inst
.instruction
|= Rn
<< 3;
11157 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11158 inst
.instruction
|= Rd
;
11159 inst
.instruction
|= Rs
<< 3;
11164 /* If we get here, it can't be done in 16 bits. */
11165 constraint (inst
.operands
[2].shifted
11166 && inst
.operands
[2].immisreg
,
11167 _("shift must be constant"));
11168 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11169 inst
.instruction
|= Rd
<< 8;
11170 inst
.instruction
|= Rs
<< 16;
11171 encode_thumb32_shifted_operand (2);
11176 /* On its face this is a lie - the instruction does set the
11177 flags. However, the only supported mnemonic in this mode
11178 says it doesn't. */
11179 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11181 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11182 _("unshifted register required"));
11183 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11185 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11186 inst
.instruction
|= Rd
;
11189 inst
.instruction
|= Rn
<< 3;
11191 inst
.instruction
|= Rs
<< 3;
11193 constraint (1, _("dest must overlap one source register"));
11201 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11202 constraint (msb
> 32, _("bit-field extends past end of register"));
11203 /* The instruction encoding stores the LSB and MSB,
11204 not the LSB and width. */
11205 Rd
= inst
.operands
[0].reg
;
11206 reject_bad_reg (Rd
);
11207 inst
.instruction
|= Rd
<< 8;
11208 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11209 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11210 inst
.instruction
|= msb
- 1;
11219 Rd
= inst
.operands
[0].reg
;
11220 reject_bad_reg (Rd
);
11222 /* #0 in second position is alternative syntax for bfc, which is
11223 the same instruction but with REG_PC in the Rm field. */
11224 if (!inst
.operands
[1].isreg
)
11228 Rn
= inst
.operands
[1].reg
;
11229 reject_bad_reg (Rn
);
11232 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11233 constraint (msb
> 32, _("bit-field extends past end of register"));
11234 /* The instruction encoding stores the LSB and MSB,
11235 not the LSB and width. */
11236 inst
.instruction
|= Rd
<< 8;
11237 inst
.instruction
|= Rn
<< 16;
11238 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11239 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11240 inst
.instruction
|= msb
- 1;
11248 Rd
= inst
.operands
[0].reg
;
11249 Rn
= inst
.operands
[1].reg
;
11251 reject_bad_reg (Rd
);
11252 reject_bad_reg (Rn
);
11254 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11255 _("bit-field extends past end of register"));
11256 inst
.instruction
|= Rd
<< 8;
11257 inst
.instruction
|= Rn
<< 16;
11258 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11259 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11260 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11263 /* ARM V5 Thumb BLX (argument parse)
11264 BLX <target_addr> which is BLX(1)
11265 BLX <Rm> which is BLX(2)
11266 Unfortunately, there are two different opcodes for this mnemonic.
11267 So, the insns[].value is not used, and the code here zaps values
11268 into inst.instruction.
11270 ??? How to take advantage of the additional two bits of displacement
11271 available in Thumb32 mode? Need new relocation? */
11276 set_it_insn_type_last ();
11278 if (inst
.operands
[0].isreg
)
11280 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11281 /* We have a register, so this is BLX(2). */
11282 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11286 /* No register. This must be BLX(1). */
11287 inst
.instruction
= 0xf000e800;
11288 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11297 bfd_reloc_code_real_type reloc
;
11300 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11302 if (in_it_block ())
11304 /* Conditional branches inside IT blocks are encoded as unconditional
11306 cond
= COND_ALWAYS
;
11311 if (cond
!= COND_ALWAYS
)
11312 opcode
= T_MNEM_bcond
;
11314 opcode
= inst
.instruction
;
11317 && (inst
.size_req
== 4
11318 || (inst
.size_req
!= 2
11319 && (inst
.operands
[0].hasreloc
11320 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11322 inst
.instruction
= THUMB_OP32(opcode
);
11323 if (cond
== COND_ALWAYS
)
11324 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11327 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11328 _("selected architecture does not support "
11329 "wide conditional branch instruction"));
11331 gas_assert (cond
!= 0xF);
11332 inst
.instruction
|= cond
<< 22;
11333 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11338 inst
.instruction
= THUMB_OP16(opcode
);
11339 if (cond
== COND_ALWAYS
)
11340 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11343 inst
.instruction
|= cond
<< 8;
11344 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11346 /* Allow section relaxation. */
11347 if (unified_syntax
&& inst
.size_req
!= 2)
11348 inst
.relax
= opcode
;
11350 inst
.relocs
[0].type
= reloc
;
11351 inst
.relocs
[0].pc_rel
= 1;
11354 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11355 between the two is the maximum immediate allowed - which is passed in
11358 do_t_bkpt_hlt1 (int range
)
11360 constraint (inst
.cond
!= COND_ALWAYS
,
11361 _("instruction is always unconditional"));
11362 if (inst
.operands
[0].present
)
11364 constraint (inst
.operands
[0].imm
> range
,
11365 _("immediate value out of range"));
11366 inst
.instruction
|= inst
.operands
[0].imm
;
11369 set_it_insn_type (NEUTRAL_IT_INSN
);
11375 do_t_bkpt_hlt1 (63);
11381 do_t_bkpt_hlt1 (255);
11385 do_t_branch23 (void)
11387 set_it_insn_type_last ();
11388 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11390 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11391 this file. We used to simply ignore the PLT reloc type here --
11392 the branch encoding is now needed to deal with TLSCALL relocs.
11393 So if we see a PLT reloc now, put it back to how it used to be to
11394 keep the preexisting behaviour. */
11395 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11396 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11398 #if defined(OBJ_COFF)
11399 /* If the destination of the branch is a defined symbol which does not have
11400 the THUMB_FUNC attribute, then we must be calling a function which has
11401 the (interfacearm) attribute. We look for the Thumb entry point to that
11402 function and change the branch to refer to that function instead. */
11403 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11404 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11405 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11406 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11407 inst
.relocs
[0].exp
.X_add_symbol
11408 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11415 set_it_insn_type_last ();
11416 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11417 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11418 should cause the alignment to be checked once it is known. This is
11419 because BX PC only works if the instruction is word aligned. */
11427 set_it_insn_type_last ();
11428 Rm
= inst
.operands
[0].reg
;
11429 reject_bad_reg (Rm
);
11430 inst
.instruction
|= Rm
<< 16;
11439 Rd
= inst
.operands
[0].reg
;
11440 Rm
= inst
.operands
[1].reg
;
11442 reject_bad_reg (Rd
);
11443 reject_bad_reg (Rm
);
11445 inst
.instruction
|= Rd
<< 8;
11446 inst
.instruction
|= Rm
<< 16;
11447 inst
.instruction
|= Rm
;
11453 set_it_insn_type (OUTSIDE_IT_INSN
);
11459 set_it_insn_type (OUTSIDE_IT_INSN
);
11460 inst
.instruction
|= inst
.operands
[0].imm
;
11466 set_it_insn_type (OUTSIDE_IT_INSN
);
11468 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11469 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11471 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11472 inst
.instruction
= 0xf3af8000;
11473 inst
.instruction
|= imod
<< 9;
11474 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11475 if (inst
.operands
[1].present
)
11476 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11480 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11481 && (inst
.operands
[0].imm
& 4),
11482 _("selected processor does not support 'A' form "
11483 "of this instruction"));
11484 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11485 _("Thumb does not support the 2-argument "
11486 "form of this instruction"));
11487 inst
.instruction
|= inst
.operands
[0].imm
;
11491 /* THUMB CPY instruction (argument parse). */
11496 if (inst
.size_req
== 4)
11498 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11499 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11500 inst
.instruction
|= inst
.operands
[1].reg
;
11504 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11505 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11506 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11513 set_it_insn_type (OUTSIDE_IT_INSN
);
11514 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11515 inst
.instruction
|= inst
.operands
[0].reg
;
11516 inst
.relocs
[0].pc_rel
= 1;
11517 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11523 inst
.instruction
|= inst
.operands
[0].imm
;
11529 unsigned Rd
, Rn
, Rm
;
11531 Rd
= inst
.operands
[0].reg
;
11532 Rn
= (inst
.operands
[1].present
11533 ? inst
.operands
[1].reg
: Rd
);
11534 Rm
= inst
.operands
[2].reg
;
11536 reject_bad_reg (Rd
);
11537 reject_bad_reg (Rn
);
11538 reject_bad_reg (Rm
);
11540 inst
.instruction
|= Rd
<< 8;
11541 inst
.instruction
|= Rn
<< 16;
11542 inst
.instruction
|= Rm
;
11548 if (unified_syntax
&& inst
.size_req
== 4)
11549 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11551 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11557 unsigned int cond
= inst
.operands
[0].imm
;
11559 set_it_insn_type (IT_INSN
);
11560 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11562 now_it
.warn_deprecated
= FALSE
;
11564 /* If the condition is a negative condition, invert the mask. */
11565 if ((cond
& 0x1) == 0x0)
11567 unsigned int mask
= inst
.instruction
& 0x000f;
11569 if ((mask
& 0x7) == 0)
11571 /* No conversion needed. */
11572 now_it
.block_length
= 1;
11574 else if ((mask
& 0x3) == 0)
11577 now_it
.block_length
= 2;
11579 else if ((mask
& 0x1) == 0)
11582 now_it
.block_length
= 3;
11587 now_it
.block_length
= 4;
11590 inst
.instruction
&= 0xfff0;
11591 inst
.instruction
|= mask
;
11594 inst
.instruction
|= cond
<< 4;
11597 /* Helper function used for both push/pop and ldm/stm. */
11599 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
11600 bfd_boolean writeback
)
11602 bfd_boolean load
, store
;
11604 gas_assert (base
!= -1 || !do_io
);
11605 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
11606 store
= do_io
&& !load
;
11608 if (mask
& (1 << 13))
11609 inst
.error
= _("SP not allowed in register list");
11611 if (do_io
&& (mask
& (1 << base
)) != 0
11613 inst
.error
= _("having the base register in the register list when "
11614 "using write back is UNPREDICTABLE");
11618 if (mask
& (1 << 15))
11620 if (mask
& (1 << 14))
11621 inst
.error
= _("LR and PC should not both be in register list");
11623 set_it_insn_type_last ();
11628 if (mask
& (1 << 15))
11629 inst
.error
= _("PC not allowed in register list");
11632 if (do_io
&& ((mask
& (mask
- 1)) == 0))
11634 /* Single register transfers implemented as str/ldr. */
11637 if (inst
.instruction
& (1 << 23))
11638 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11640 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11644 if (inst
.instruction
& (1 << 23))
11645 inst
.instruction
= 0x00800000; /* ia -> [base] */
11647 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11650 inst
.instruction
|= 0xf8400000;
11652 inst
.instruction
|= 0x00100000;
11654 mask
= ffs (mask
) - 1;
11657 else if (writeback
)
11658 inst
.instruction
|= WRITE_BACK
;
11660 inst
.instruction
|= mask
;
11662 inst
.instruction
|= base
<< 16;
11668 /* This really doesn't seem worth it. */
11669 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
11670 _("expression too complex"));
11671 constraint (inst
.operands
[1].writeback
,
11672 _("Thumb load/store multiple does not support {reglist}^"));
11674 if (unified_syntax
)
11676 bfd_boolean narrow
;
11680 /* See if we can use a 16-bit instruction. */
11681 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11682 && inst
.size_req
!= 4
11683 && !(inst
.operands
[1].imm
& ~0xff))
11685 mask
= 1 << inst
.operands
[0].reg
;
11687 if (inst
.operands
[0].reg
<= 7)
11689 if (inst
.instruction
== T_MNEM_stmia
11690 ? inst
.operands
[0].writeback
11691 : (inst
.operands
[0].writeback
11692 == !(inst
.operands
[1].imm
& mask
)))
11694 if (inst
.instruction
== T_MNEM_stmia
11695 && (inst
.operands
[1].imm
& mask
)
11696 && (inst
.operands
[1].imm
& (mask
- 1)))
11697 as_warn (_("value stored for r%d is UNKNOWN"),
11698 inst
.operands
[0].reg
);
11700 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11701 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11702 inst
.instruction
|= inst
.operands
[1].imm
;
11705 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11707 /* This means 1 register in reg list one of 3 situations:
11708 1. Instruction is stmia, but without writeback.
11709 2. lmdia without writeback, but with Rn not in
11711 3. ldmia with writeback, but with Rn in reglist.
11712 Case 3 is UNPREDICTABLE behaviour, so we handle
11713 case 1 and 2 which can be converted into a 16-bit
11714 str or ldr. The SP cases are handled below. */
11715 unsigned long opcode
;
11716 /* First, record an error for Case 3. */
11717 if (inst
.operands
[1].imm
& mask
11718 && inst
.operands
[0].writeback
)
11720 _("having the base register in the register list when "
11721 "using write back is UNPREDICTABLE");
11723 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11725 inst
.instruction
= THUMB_OP16 (opcode
);
11726 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11727 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11731 else if (inst
.operands
[0] .reg
== REG_SP
)
11733 if (inst
.operands
[0].writeback
)
11736 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11737 ? T_MNEM_push
: T_MNEM_pop
);
11738 inst
.instruction
|= inst
.operands
[1].imm
;
11741 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11744 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11745 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11746 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11754 if (inst
.instruction
< 0xffff)
11755 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11757 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
11758 inst
.operands
[1].imm
,
11759 inst
.operands
[0].writeback
);
11764 constraint (inst
.operands
[0].reg
> 7
11765 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11766 constraint (inst
.instruction
!= T_MNEM_ldmia
11767 && inst
.instruction
!= T_MNEM_stmia
,
11768 _("Thumb-2 instruction only valid in unified syntax"));
11769 if (inst
.instruction
== T_MNEM_stmia
)
11771 if (!inst
.operands
[0].writeback
)
11772 as_warn (_("this instruction will write back the base register"));
11773 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11774 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11775 as_warn (_("value stored for r%d is UNKNOWN"),
11776 inst
.operands
[0].reg
);
11780 if (!inst
.operands
[0].writeback
11781 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11782 as_warn (_("this instruction will write back the base register"));
11783 else if (inst
.operands
[0].writeback
11784 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11785 as_warn (_("this instruction will not write back the base register"));
11788 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11789 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11790 inst
.instruction
|= inst
.operands
[1].imm
;
11797 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11798 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11799 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11800 || inst
.operands
[1].negative
,
11803 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11805 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11806 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11807 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11813 if (!inst
.operands
[1].present
)
11815 constraint (inst
.operands
[0].reg
== REG_LR
,
11816 _("r14 not allowed as first register "
11817 "when second register is omitted"));
11818 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11820 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11823 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11824 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11825 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11831 unsigned long opcode
;
11834 if (inst
.operands
[0].isreg
11835 && !inst
.operands
[0].preind
11836 && inst
.operands
[0].reg
== REG_PC
)
11837 set_it_insn_type_last ();
11839 opcode
= inst
.instruction
;
11840 if (unified_syntax
)
11842 if (!inst
.operands
[1].isreg
)
11844 if (opcode
<= 0xffff)
11845 inst
.instruction
= THUMB_OP32 (opcode
);
11846 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11849 if (inst
.operands
[1].isreg
11850 && !inst
.operands
[1].writeback
11851 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11852 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11853 && opcode
<= 0xffff
11854 && inst
.size_req
!= 4)
11856 /* Insn may have a 16-bit form. */
11857 Rn
= inst
.operands
[1].reg
;
11858 if (inst
.operands
[1].immisreg
)
11860 inst
.instruction
= THUMB_OP16 (opcode
);
11862 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11864 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11865 reject_bad_reg (inst
.operands
[1].imm
);
11867 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11868 && opcode
!= T_MNEM_ldrsb
)
11869 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11870 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11877 if (inst
.relocs
[0].pc_rel
)
11878 opcode
= T_MNEM_ldr_pc2
;
11880 opcode
= T_MNEM_ldr_pc
;
11884 if (opcode
== T_MNEM_ldr
)
11885 opcode
= T_MNEM_ldr_sp
;
11887 opcode
= T_MNEM_str_sp
;
11889 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11893 inst
.instruction
= inst
.operands
[0].reg
;
11894 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11896 inst
.instruction
|= THUMB_OP16 (opcode
);
11897 if (inst
.size_req
== 2)
11898 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11900 inst
.relax
= opcode
;
11904 /* Definitely a 32-bit variant. */
11906 /* Warning for Erratum 752419. */
11907 if (opcode
== T_MNEM_ldr
11908 && inst
.operands
[0].reg
== REG_SP
11909 && inst
.operands
[1].writeback
== 1
11910 && !inst
.operands
[1].immisreg
)
11912 if (no_cpu_selected ()
11913 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11914 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11915 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11916 as_warn (_("This instruction may be unpredictable "
11917 "if executed on M-profile cores "
11918 "with interrupts enabled."));
11921 /* Do some validations regarding addressing modes. */
11922 if (inst
.operands
[1].immisreg
)
11923 reject_bad_reg (inst
.operands
[1].imm
);
11925 constraint (inst
.operands
[1].writeback
== 1
11926 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11929 inst
.instruction
= THUMB_OP32 (opcode
);
11930 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11931 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11932 check_ldr_r15_aligned ();
11936 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11938 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11940 /* Only [Rn,Rm] is acceptable. */
11941 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11942 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11943 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11944 || inst
.operands
[1].negative
,
11945 _("Thumb does not support this addressing mode"));
11946 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11950 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11951 if (!inst
.operands
[1].isreg
)
11952 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11955 constraint (!inst
.operands
[1].preind
11956 || inst
.operands
[1].shifted
11957 || inst
.operands
[1].writeback
,
11958 _("Thumb does not support this addressing mode"));
11959 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11961 constraint (inst
.instruction
& 0x0600,
11962 _("byte or halfword not valid for base register"));
11963 constraint (inst
.operands
[1].reg
== REG_PC
11964 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11965 _("r15 based store not allowed"));
11966 constraint (inst
.operands
[1].immisreg
,
11967 _("invalid base register for register offset"));
11969 if (inst
.operands
[1].reg
== REG_PC
)
11970 inst
.instruction
= T_OPCODE_LDR_PC
;
11971 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11972 inst
.instruction
= T_OPCODE_LDR_SP
;
11974 inst
.instruction
= T_OPCODE_STR_SP
;
11976 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11977 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11981 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11982 if (!inst
.operands
[1].immisreg
)
11984 /* Immediate offset. */
11985 inst
.instruction
|= inst
.operands
[0].reg
;
11986 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11987 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11991 /* Register offset. */
11992 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11993 constraint (inst
.operands
[1].negative
,
11994 _("Thumb does not support this addressing mode"));
11997 switch (inst
.instruction
)
11999 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12000 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12001 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12002 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12003 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12004 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12005 case 0x5600 /* ldrsb */:
12006 case 0x5e00 /* ldrsh */: break;
12010 inst
.instruction
|= inst
.operands
[0].reg
;
12011 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12012 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12018 if (!inst
.operands
[1].present
)
12020 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12021 constraint (inst
.operands
[0].reg
== REG_LR
,
12022 _("r14 not allowed here"));
12023 constraint (inst
.operands
[0].reg
== REG_R12
,
12024 _("r12 not allowed here"));
12027 if (inst
.operands
[2].writeback
12028 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12029 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12030 as_warn (_("base register written back, and overlaps "
12031 "one of transfer registers"));
12033 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12034 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12035 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12041 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12042 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12048 unsigned Rd
, Rn
, Rm
, Ra
;
12050 Rd
= inst
.operands
[0].reg
;
12051 Rn
= inst
.operands
[1].reg
;
12052 Rm
= inst
.operands
[2].reg
;
12053 Ra
= inst
.operands
[3].reg
;
12055 reject_bad_reg (Rd
);
12056 reject_bad_reg (Rn
);
12057 reject_bad_reg (Rm
);
12058 reject_bad_reg (Ra
);
12060 inst
.instruction
|= Rd
<< 8;
12061 inst
.instruction
|= Rn
<< 16;
12062 inst
.instruction
|= Rm
;
12063 inst
.instruction
|= Ra
<< 12;
12069 unsigned RdLo
, RdHi
, Rn
, Rm
;
12071 RdLo
= inst
.operands
[0].reg
;
12072 RdHi
= inst
.operands
[1].reg
;
12073 Rn
= inst
.operands
[2].reg
;
12074 Rm
= inst
.operands
[3].reg
;
12076 reject_bad_reg (RdLo
);
12077 reject_bad_reg (RdHi
);
12078 reject_bad_reg (Rn
);
12079 reject_bad_reg (Rm
);
12081 inst
.instruction
|= RdLo
<< 12;
12082 inst
.instruction
|= RdHi
<< 8;
12083 inst
.instruction
|= Rn
<< 16;
12084 inst
.instruction
|= Rm
;
12088 do_t_mov_cmp (void)
12092 Rn
= inst
.operands
[0].reg
;
12093 Rm
= inst
.operands
[1].reg
;
12096 set_it_insn_type_last ();
12098 if (unified_syntax
)
12100 int r0off
= (inst
.instruction
== T_MNEM_mov
12101 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12102 unsigned long opcode
;
12103 bfd_boolean narrow
;
12104 bfd_boolean low_regs
;
12106 low_regs
= (Rn
<= 7 && Rm
<= 7);
12107 opcode
= inst
.instruction
;
12108 if (in_it_block ())
12109 narrow
= opcode
!= T_MNEM_movs
;
12111 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12112 if (inst
.size_req
== 4
12113 || inst
.operands
[1].shifted
)
12116 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12117 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12118 && !inst
.operands
[1].shifted
12122 inst
.instruction
= T2_SUBS_PC_LR
;
12126 if (opcode
== T_MNEM_cmp
)
12128 constraint (Rn
== REG_PC
, BAD_PC
);
12131 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12133 warn_deprecated_sp (Rm
);
12134 /* R15 was documented as a valid choice for Rm in ARMv6,
12135 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12136 tools reject R15, so we do too. */
12137 constraint (Rm
== REG_PC
, BAD_PC
);
12140 reject_bad_reg (Rm
);
12142 else if (opcode
== T_MNEM_mov
12143 || opcode
== T_MNEM_movs
)
12145 if (inst
.operands
[1].isreg
)
12147 if (opcode
== T_MNEM_movs
)
12149 reject_bad_reg (Rn
);
12150 reject_bad_reg (Rm
);
12154 /* This is mov.n. */
12155 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12156 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12158 as_tsktsk (_("Use of r%u as a source register is "
12159 "deprecated when r%u is the destination "
12160 "register."), Rm
, Rn
);
12165 /* This is mov.w. */
12166 constraint (Rn
== REG_PC
, BAD_PC
);
12167 constraint (Rm
== REG_PC
, BAD_PC
);
12168 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12169 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12173 reject_bad_reg (Rn
);
12176 if (!inst
.operands
[1].isreg
)
12178 /* Immediate operand. */
12179 if (!in_it_block () && opcode
== T_MNEM_mov
)
12181 if (low_regs
&& narrow
)
12183 inst
.instruction
= THUMB_OP16 (opcode
);
12184 inst
.instruction
|= Rn
<< 8;
12185 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12186 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12188 if (inst
.size_req
== 2)
12189 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12191 inst
.relax
= opcode
;
12196 constraint ((inst
.relocs
[0].type
12197 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12198 && (inst
.relocs
[0].type
12199 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12200 THUMB1_RELOC_ONLY
);
12202 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12203 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12204 inst
.instruction
|= Rn
<< r0off
;
12205 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12208 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12209 && (inst
.instruction
== T_MNEM_mov
12210 || inst
.instruction
== T_MNEM_movs
))
12212 /* Register shifts are encoded as separate shift instructions. */
12213 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12215 if (in_it_block ())
12220 if (inst
.size_req
== 4)
12223 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12229 switch (inst
.operands
[1].shift_kind
)
12232 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12235 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12238 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12241 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12247 inst
.instruction
= opcode
;
12250 inst
.instruction
|= Rn
;
12251 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12256 inst
.instruction
|= CONDS_BIT
;
12258 inst
.instruction
|= Rn
<< 8;
12259 inst
.instruction
|= Rm
<< 16;
12260 inst
.instruction
|= inst
.operands
[1].imm
;
12265 /* Some mov with immediate shift have narrow variants.
12266 Register shifts are handled above. */
12267 if (low_regs
&& inst
.operands
[1].shifted
12268 && (inst
.instruction
== T_MNEM_mov
12269 || inst
.instruction
== T_MNEM_movs
))
12271 if (in_it_block ())
12272 narrow
= (inst
.instruction
== T_MNEM_mov
);
12274 narrow
= (inst
.instruction
== T_MNEM_movs
);
12279 switch (inst
.operands
[1].shift_kind
)
12281 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12282 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12283 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12284 default: narrow
= FALSE
; break;
12290 inst
.instruction
|= Rn
;
12291 inst
.instruction
|= Rm
<< 3;
12292 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12296 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12297 inst
.instruction
|= Rn
<< r0off
;
12298 encode_thumb32_shifted_operand (1);
12302 switch (inst
.instruction
)
12305 /* In v4t or v5t a move of two lowregs produces unpredictable
12306 results. Don't allow this. */
12309 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12310 "MOV Rd, Rs with two low registers is not "
12311 "permitted on this architecture");
12312 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12316 inst
.instruction
= T_OPCODE_MOV_HR
;
12317 inst
.instruction
|= (Rn
& 0x8) << 4;
12318 inst
.instruction
|= (Rn
& 0x7);
12319 inst
.instruction
|= Rm
<< 3;
12323 /* We know we have low registers at this point.
12324 Generate LSLS Rd, Rs, #0. */
12325 inst
.instruction
= T_OPCODE_LSL_I
;
12326 inst
.instruction
|= Rn
;
12327 inst
.instruction
|= Rm
<< 3;
12333 inst
.instruction
= T_OPCODE_CMP_LR
;
12334 inst
.instruction
|= Rn
;
12335 inst
.instruction
|= Rm
<< 3;
12339 inst
.instruction
= T_OPCODE_CMP_HR
;
12340 inst
.instruction
|= (Rn
& 0x8) << 4;
12341 inst
.instruction
|= (Rn
& 0x7);
12342 inst
.instruction
|= Rm
<< 3;
12349 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12351 /* PR 10443: Do not silently ignore shifted operands. */
12352 constraint (inst
.operands
[1].shifted
,
12353 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12355 if (inst
.operands
[1].isreg
)
12357 if (Rn
< 8 && Rm
< 8)
12359 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12360 since a MOV instruction produces unpredictable results. */
12361 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12362 inst
.instruction
= T_OPCODE_ADD_I3
;
12364 inst
.instruction
= T_OPCODE_CMP_LR
;
12366 inst
.instruction
|= Rn
;
12367 inst
.instruction
|= Rm
<< 3;
12371 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12372 inst
.instruction
= T_OPCODE_MOV_HR
;
12374 inst
.instruction
= T_OPCODE_CMP_HR
;
12380 constraint (Rn
> 7,
12381 _("only lo regs allowed with immediate"));
12382 inst
.instruction
|= Rn
<< 8;
12383 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12394 top
= (inst
.instruction
& 0x00800000) != 0;
12395 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12397 constraint (top
, _(":lower16: not allowed in this instruction"));
12398 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12400 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12402 constraint (!top
, _(":upper16: not allowed in this instruction"));
12403 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12406 Rd
= inst
.operands
[0].reg
;
12407 reject_bad_reg (Rd
);
12409 inst
.instruction
|= Rd
<< 8;
12410 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12412 imm
= inst
.relocs
[0].exp
.X_add_number
;
12413 inst
.instruction
|= (imm
& 0xf000) << 4;
12414 inst
.instruction
|= (imm
& 0x0800) << 15;
12415 inst
.instruction
|= (imm
& 0x0700) << 4;
12416 inst
.instruction
|= (imm
& 0x00ff);
12421 do_t_mvn_tst (void)
12425 Rn
= inst
.operands
[0].reg
;
12426 Rm
= inst
.operands
[1].reg
;
12428 if (inst
.instruction
== T_MNEM_cmp
12429 || inst
.instruction
== T_MNEM_cmn
)
12430 constraint (Rn
== REG_PC
, BAD_PC
);
12432 reject_bad_reg (Rn
);
12433 reject_bad_reg (Rm
);
12435 if (unified_syntax
)
12437 int r0off
= (inst
.instruction
== T_MNEM_mvn
12438 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12439 bfd_boolean narrow
;
12441 if (inst
.size_req
== 4
12442 || inst
.instruction
> 0xffff
12443 || inst
.operands
[1].shifted
12444 || Rn
> 7 || Rm
> 7)
12446 else if (inst
.instruction
== T_MNEM_cmn
12447 || inst
.instruction
== T_MNEM_tst
)
12449 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12450 narrow
= !in_it_block ();
12452 narrow
= in_it_block ();
12454 if (!inst
.operands
[1].isreg
)
12456 /* For an immediate, we always generate a 32-bit opcode;
12457 section relaxation will shrink it later if possible. */
12458 if (inst
.instruction
< 0xffff)
12459 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12460 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12461 inst
.instruction
|= Rn
<< r0off
;
12462 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12466 /* See if we can do this with a 16-bit instruction. */
12469 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12470 inst
.instruction
|= Rn
;
12471 inst
.instruction
|= Rm
<< 3;
12475 constraint (inst
.operands
[1].shifted
12476 && inst
.operands
[1].immisreg
,
12477 _("shift must be constant"));
12478 if (inst
.instruction
< 0xffff)
12479 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12480 inst
.instruction
|= Rn
<< r0off
;
12481 encode_thumb32_shifted_operand (1);
12487 constraint (inst
.instruction
> 0xffff
12488 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12489 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12490 _("unshifted register required"));
12491 constraint (Rn
> 7 || Rm
> 7,
12494 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12495 inst
.instruction
|= Rn
;
12496 inst
.instruction
|= Rm
<< 3;
12505 if (do_vfp_nsyn_mrs () == SUCCESS
)
12508 Rd
= inst
.operands
[0].reg
;
12509 reject_bad_reg (Rd
);
12510 inst
.instruction
|= Rd
<< 8;
12512 if (inst
.operands
[1].isreg
)
12514 unsigned br
= inst
.operands
[1].reg
;
12515 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12516 as_bad (_("bad register for mrs"));
12518 inst
.instruction
|= br
& (0xf << 16);
12519 inst
.instruction
|= (br
& 0x300) >> 4;
12520 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12524 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12526 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12528 /* PR gas/12698: The constraint is only applied for m_profile.
12529 If the user has specified -march=all, we want to ignore it as
12530 we are building for any CPU type, including non-m variants. */
12531 bfd_boolean m_profile
=
12532 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12533 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12534 "not support requested special purpose register"));
12537 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12539 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12540 _("'APSR', 'CPSR' or 'SPSR' expected"));
12542 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12543 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12544 inst
.instruction
|= 0xf0000;
12554 if (do_vfp_nsyn_msr () == SUCCESS
)
12557 constraint (!inst
.operands
[1].isreg
,
12558 _("Thumb encoding does not support an immediate here"));
12560 if (inst
.operands
[0].isreg
)
12561 flags
= (int)(inst
.operands
[0].reg
);
12563 flags
= inst
.operands
[0].imm
;
12565 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12567 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12569 /* PR gas/12698: The constraint is only applied for m_profile.
12570 If the user has specified -march=all, we want to ignore it as
12571 we are building for any CPU type, including non-m variants. */
12572 bfd_boolean m_profile
=
12573 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12574 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12575 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12576 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12577 && bits
!= PSR_f
)) && m_profile
,
12578 _("selected processor does not support requested special "
12579 "purpose register"));
12582 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12583 "requested special purpose register"));
12585 Rn
= inst
.operands
[1].reg
;
12586 reject_bad_reg (Rn
);
12588 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12589 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12590 inst
.instruction
|= (flags
& 0x300) >> 4;
12591 inst
.instruction
|= (flags
& 0xff);
12592 inst
.instruction
|= Rn
<< 16;
12598 bfd_boolean narrow
;
12599 unsigned Rd
, Rn
, Rm
;
12601 if (!inst
.operands
[2].present
)
12602 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12604 Rd
= inst
.operands
[0].reg
;
12605 Rn
= inst
.operands
[1].reg
;
12606 Rm
= inst
.operands
[2].reg
;
12608 if (unified_syntax
)
12610 if (inst
.size_req
== 4
12616 else if (inst
.instruction
== T_MNEM_muls
)
12617 narrow
= !in_it_block ();
12619 narrow
= in_it_block ();
12623 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12624 constraint (Rn
> 7 || Rm
> 7,
12631 /* 16-bit MULS/Conditional MUL. */
12632 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12633 inst
.instruction
|= Rd
;
12636 inst
.instruction
|= Rm
<< 3;
12638 inst
.instruction
|= Rn
<< 3;
12640 constraint (1, _("dest must overlap one source register"));
12644 constraint (inst
.instruction
!= T_MNEM_mul
,
12645 _("Thumb-2 MUL must not set flags"));
12647 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12648 inst
.instruction
|= Rd
<< 8;
12649 inst
.instruction
|= Rn
<< 16;
12650 inst
.instruction
|= Rm
<< 0;
12652 reject_bad_reg (Rd
);
12653 reject_bad_reg (Rn
);
12654 reject_bad_reg (Rm
);
12661 unsigned RdLo
, RdHi
, Rn
, Rm
;
12663 RdLo
= inst
.operands
[0].reg
;
12664 RdHi
= inst
.operands
[1].reg
;
12665 Rn
= inst
.operands
[2].reg
;
12666 Rm
= inst
.operands
[3].reg
;
12668 reject_bad_reg (RdLo
);
12669 reject_bad_reg (RdHi
);
12670 reject_bad_reg (Rn
);
12671 reject_bad_reg (Rm
);
12673 inst
.instruction
|= RdLo
<< 12;
12674 inst
.instruction
|= RdHi
<< 8;
12675 inst
.instruction
|= Rn
<< 16;
12676 inst
.instruction
|= Rm
;
12679 as_tsktsk (_("rdhi and rdlo must be different"));
12685 set_it_insn_type (NEUTRAL_IT_INSN
);
12687 if (unified_syntax
)
12689 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12691 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12692 inst
.instruction
|= inst
.operands
[0].imm
;
12696 /* PR9722: Check for Thumb2 availability before
12697 generating a thumb2 nop instruction. */
12698 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12700 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12701 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12704 inst
.instruction
= 0x46c0;
12709 constraint (inst
.operands
[0].present
,
12710 _("Thumb does not support NOP with hints"));
12711 inst
.instruction
= 0x46c0;
12718 if (unified_syntax
)
12720 bfd_boolean narrow
;
12722 if (THUMB_SETS_FLAGS (inst
.instruction
))
12723 narrow
= !in_it_block ();
12725 narrow
= in_it_block ();
12726 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12728 if (inst
.size_req
== 4)
12733 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12734 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12735 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12739 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12740 inst
.instruction
|= inst
.operands
[0].reg
;
12741 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12746 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12748 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12750 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12751 inst
.instruction
|= inst
.operands
[0].reg
;
12752 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12761 Rd
= inst
.operands
[0].reg
;
12762 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12764 reject_bad_reg (Rd
);
12765 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12766 reject_bad_reg (Rn
);
12768 inst
.instruction
|= Rd
<< 8;
12769 inst
.instruction
|= Rn
<< 16;
12771 if (!inst
.operands
[2].isreg
)
12773 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12774 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12780 Rm
= inst
.operands
[2].reg
;
12781 reject_bad_reg (Rm
);
12783 constraint (inst
.operands
[2].shifted
12784 && inst
.operands
[2].immisreg
,
12785 _("shift must be constant"));
12786 encode_thumb32_shifted_operand (2);
12793 unsigned Rd
, Rn
, Rm
;
12795 Rd
= inst
.operands
[0].reg
;
12796 Rn
= inst
.operands
[1].reg
;
12797 Rm
= inst
.operands
[2].reg
;
12799 reject_bad_reg (Rd
);
12800 reject_bad_reg (Rn
);
12801 reject_bad_reg (Rm
);
12803 inst
.instruction
|= Rd
<< 8;
12804 inst
.instruction
|= Rn
<< 16;
12805 inst
.instruction
|= Rm
;
12806 if (inst
.operands
[3].present
)
12808 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
12809 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
12810 _("expression too complex"));
12811 inst
.instruction
|= (val
& 0x1c) << 10;
12812 inst
.instruction
|= (val
& 0x03) << 6;
12819 if (!inst
.operands
[3].present
)
12823 inst
.instruction
&= ~0x00000020;
12825 /* PR 10168. Swap the Rm and Rn registers. */
12826 Rtmp
= inst
.operands
[1].reg
;
12827 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12828 inst
.operands
[2].reg
= Rtmp
;
12836 if (inst
.operands
[0].immisreg
)
12837 reject_bad_reg (inst
.operands
[0].imm
);
12839 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12843 do_t_push_pop (void)
12847 constraint (inst
.operands
[0].writeback
,
12848 _("push/pop do not support {reglist}^"));
12849 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12850 _("expression too complex"));
12852 mask
= inst
.operands
[0].imm
;
12853 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12854 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12855 else if (inst
.size_req
!= 4
12856 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12857 ? REG_LR
: REG_PC
)))
12859 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12860 inst
.instruction
|= THUMB_PP_PC_LR
;
12861 inst
.instruction
|= mask
& 0xff;
12863 else if (unified_syntax
)
12865 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12866 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
12870 inst
.error
= _("invalid register list to push/pop instruction");
12878 if (unified_syntax
)
12879 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
12882 inst
.error
= _("invalid register list to push/pop instruction");
12888 do_t_vscclrm (void)
12890 if (inst
.operands
[0].issingle
)
12892 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
12893 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
12894 inst
.instruction
|= inst
.operands
[0].imm
;
12898 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
12899 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
12900 inst
.instruction
|= 1 << 8;
12901 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
12910 Rd
= inst
.operands
[0].reg
;
12911 Rm
= inst
.operands
[1].reg
;
12913 reject_bad_reg (Rd
);
12914 reject_bad_reg (Rm
);
12916 inst
.instruction
|= Rd
<< 8;
12917 inst
.instruction
|= Rm
<< 16;
12918 inst
.instruction
|= Rm
;
12926 Rd
= inst
.operands
[0].reg
;
12927 Rm
= inst
.operands
[1].reg
;
12929 reject_bad_reg (Rd
);
12930 reject_bad_reg (Rm
);
12932 if (Rd
<= 7 && Rm
<= 7
12933 && inst
.size_req
!= 4)
12935 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12936 inst
.instruction
|= Rd
;
12937 inst
.instruction
|= Rm
<< 3;
12939 else if (unified_syntax
)
12941 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12942 inst
.instruction
|= Rd
<< 8;
12943 inst
.instruction
|= Rm
<< 16;
12944 inst
.instruction
|= Rm
;
12947 inst
.error
= BAD_HIREG
;
12955 Rd
= inst
.operands
[0].reg
;
12956 Rm
= inst
.operands
[1].reg
;
12958 reject_bad_reg (Rd
);
12959 reject_bad_reg (Rm
);
12961 inst
.instruction
|= Rd
<< 8;
12962 inst
.instruction
|= Rm
;
12970 Rd
= inst
.operands
[0].reg
;
12971 Rs
= (inst
.operands
[1].present
12972 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12973 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12975 reject_bad_reg (Rd
);
12976 reject_bad_reg (Rs
);
12977 if (inst
.operands
[2].isreg
)
12978 reject_bad_reg (inst
.operands
[2].reg
);
12980 inst
.instruction
|= Rd
<< 8;
12981 inst
.instruction
|= Rs
<< 16;
12982 if (!inst
.operands
[2].isreg
)
12984 bfd_boolean narrow
;
12986 if ((inst
.instruction
& 0x00100000) != 0)
12987 narrow
= !in_it_block ();
12989 narrow
= in_it_block ();
12991 if (Rd
> 7 || Rs
> 7)
12994 if (inst
.size_req
== 4 || !unified_syntax
)
12997 if (inst
.relocs
[0].exp
.X_op
!= O_constant
12998 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13001 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13002 relaxation, but it doesn't seem worth the hassle. */
13005 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13006 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13007 inst
.instruction
|= Rs
<< 3;
13008 inst
.instruction
|= Rd
;
13012 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13013 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13017 encode_thumb32_shifted_operand (2);
13023 if (warn_on_deprecated
13024 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13025 as_tsktsk (_("setend use is deprecated for ARMv8"));
13027 set_it_insn_type (OUTSIDE_IT_INSN
);
13028 if (inst
.operands
[0].imm
)
13029 inst
.instruction
|= 0x8;
13035 if (!inst
.operands
[1].present
)
13036 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13038 if (unified_syntax
)
13040 bfd_boolean narrow
;
13043 switch (inst
.instruction
)
13046 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13048 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13050 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13052 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13056 if (THUMB_SETS_FLAGS (inst
.instruction
))
13057 narrow
= !in_it_block ();
13059 narrow
= in_it_block ();
13060 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13062 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13064 if (inst
.operands
[2].isreg
13065 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13066 || inst
.operands
[2].reg
> 7))
13068 if (inst
.size_req
== 4)
13071 reject_bad_reg (inst
.operands
[0].reg
);
13072 reject_bad_reg (inst
.operands
[1].reg
);
13076 if (inst
.operands
[2].isreg
)
13078 reject_bad_reg (inst
.operands
[2].reg
);
13079 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13080 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13081 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13082 inst
.instruction
|= inst
.operands
[2].reg
;
13084 /* PR 12854: Error on extraneous shifts. */
13085 constraint (inst
.operands
[2].shifted
,
13086 _("extraneous shift as part of operand to shift insn"));
13090 inst
.operands
[1].shifted
= 1;
13091 inst
.operands
[1].shift_kind
= shift_kind
;
13092 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13093 ? T_MNEM_movs
: T_MNEM_mov
);
13094 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13095 encode_thumb32_shifted_operand (1);
13096 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13097 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13102 if (inst
.operands
[2].isreg
)
13104 switch (shift_kind
)
13106 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13107 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13108 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13109 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13113 inst
.instruction
|= inst
.operands
[0].reg
;
13114 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13116 /* PR 12854: Error on extraneous shifts. */
13117 constraint (inst
.operands
[2].shifted
,
13118 _("extraneous shift as part of operand to shift insn"));
13122 switch (shift_kind
)
13124 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13125 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13126 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13129 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13130 inst
.instruction
|= inst
.operands
[0].reg
;
13131 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13137 constraint (inst
.operands
[0].reg
> 7
13138 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13139 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13141 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13143 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13144 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13145 _("source1 and dest must be same register"));
13147 switch (inst
.instruction
)
13149 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13150 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13151 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13152 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13156 inst
.instruction
|= inst
.operands
[0].reg
;
13157 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13159 /* PR 12854: Error on extraneous shifts. */
13160 constraint (inst
.operands
[2].shifted
,
13161 _("extraneous shift as part of operand to shift insn"));
13165 switch (inst
.instruction
)
13167 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13168 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13169 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13170 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13173 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13174 inst
.instruction
|= inst
.operands
[0].reg
;
13175 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13183 unsigned Rd
, Rn
, Rm
;
13185 Rd
= inst
.operands
[0].reg
;
13186 Rn
= inst
.operands
[1].reg
;
13187 Rm
= inst
.operands
[2].reg
;
13189 reject_bad_reg (Rd
);
13190 reject_bad_reg (Rn
);
13191 reject_bad_reg (Rm
);
13193 inst
.instruction
|= Rd
<< 8;
13194 inst
.instruction
|= Rn
<< 16;
13195 inst
.instruction
|= Rm
;
13201 unsigned Rd
, Rn
, Rm
;
13203 Rd
= inst
.operands
[0].reg
;
13204 Rm
= inst
.operands
[1].reg
;
13205 Rn
= inst
.operands
[2].reg
;
13207 reject_bad_reg (Rd
);
13208 reject_bad_reg (Rn
);
13209 reject_bad_reg (Rm
);
13211 inst
.instruction
|= Rd
<< 8;
13212 inst
.instruction
|= Rn
<< 16;
13213 inst
.instruction
|= Rm
;
13219 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13220 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13221 _("SMC is not permitted on this architecture"));
13222 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13223 _("expression too complex"));
13224 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13225 inst
.instruction
|= (value
& 0xf000) >> 12;
13226 inst
.instruction
|= (value
& 0x0ff0);
13227 inst
.instruction
|= (value
& 0x000f) << 16;
13228 /* PR gas/15623: SMC instructions must be last in an IT block. */
13229 set_it_insn_type_last ();
13235 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13237 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13238 inst
.instruction
|= (value
& 0x0fff);
13239 inst
.instruction
|= (value
& 0xf000) << 4;
13243 do_t_ssat_usat (int bias
)
13247 Rd
= inst
.operands
[0].reg
;
13248 Rn
= inst
.operands
[2].reg
;
13250 reject_bad_reg (Rd
);
13251 reject_bad_reg (Rn
);
13253 inst
.instruction
|= Rd
<< 8;
13254 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13255 inst
.instruction
|= Rn
<< 16;
13257 if (inst
.operands
[3].present
)
13259 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13261 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13263 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13264 _("expression too complex"));
13266 if (shift_amount
!= 0)
13268 constraint (shift_amount
> 31,
13269 _("shift expression is too large"));
13271 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13272 inst
.instruction
|= 0x00200000; /* sh bit. */
13274 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13275 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13283 do_t_ssat_usat (1);
13291 Rd
= inst
.operands
[0].reg
;
13292 Rn
= inst
.operands
[2].reg
;
13294 reject_bad_reg (Rd
);
13295 reject_bad_reg (Rn
);
13297 inst
.instruction
|= Rd
<< 8;
13298 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13299 inst
.instruction
|= Rn
<< 16;
13305 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13306 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13307 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13308 || inst
.operands
[2].negative
,
13311 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13313 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13314 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13315 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13316 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13322 if (!inst
.operands
[2].present
)
13323 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13325 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13326 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13327 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13330 inst
.instruction
|= inst
.operands
[0].reg
;
13331 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13332 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13333 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13339 unsigned Rd
, Rn
, Rm
;
13341 Rd
= inst
.operands
[0].reg
;
13342 Rn
= inst
.operands
[1].reg
;
13343 Rm
= inst
.operands
[2].reg
;
13345 reject_bad_reg (Rd
);
13346 reject_bad_reg (Rn
);
13347 reject_bad_reg (Rm
);
13349 inst
.instruction
|= Rd
<< 8;
13350 inst
.instruction
|= Rn
<< 16;
13351 inst
.instruction
|= Rm
;
13352 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13360 Rd
= inst
.operands
[0].reg
;
13361 Rm
= inst
.operands
[1].reg
;
13363 reject_bad_reg (Rd
);
13364 reject_bad_reg (Rm
);
13366 if (inst
.instruction
<= 0xffff
13367 && inst
.size_req
!= 4
13368 && Rd
<= 7 && Rm
<= 7
13369 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13371 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13372 inst
.instruction
|= Rd
;
13373 inst
.instruction
|= Rm
<< 3;
13375 else if (unified_syntax
)
13377 if (inst
.instruction
<= 0xffff)
13378 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13379 inst
.instruction
|= Rd
<< 8;
13380 inst
.instruction
|= Rm
;
13381 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13385 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13386 _("Thumb encoding does not support rotation"));
13387 constraint (1, BAD_HIREG
);
13394 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13403 half
= (inst
.instruction
& 0x10) != 0;
13404 set_it_insn_type_last ();
13405 constraint (inst
.operands
[0].immisreg
,
13406 _("instruction requires register index"));
13408 Rn
= inst
.operands
[0].reg
;
13409 Rm
= inst
.operands
[0].imm
;
13411 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13412 constraint (Rn
== REG_SP
, BAD_SP
);
13413 reject_bad_reg (Rm
);
13415 constraint (!half
&& inst
.operands
[0].shifted
,
13416 _("instruction does not allow shifted index"));
13417 inst
.instruction
|= (Rn
<< 16) | Rm
;
13423 if (!inst
.operands
[0].present
)
13424 inst
.operands
[0].imm
= 0;
13426 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13428 constraint (inst
.size_req
== 2,
13429 _("immediate value out of range"));
13430 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13431 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13432 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13436 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13437 inst
.instruction
|= inst
.operands
[0].imm
;
13440 set_it_insn_type (NEUTRAL_IT_INSN
);
13447 do_t_ssat_usat (0);
13455 Rd
= inst
.operands
[0].reg
;
13456 Rn
= inst
.operands
[2].reg
;
13458 reject_bad_reg (Rd
);
13459 reject_bad_reg (Rn
);
13461 inst
.instruction
|= Rd
<< 8;
13462 inst
.instruction
|= inst
.operands
[1].imm
;
13463 inst
.instruction
|= Rn
<< 16;
13466 /* Checking the range of the branch offset (VAL) with NBITS bits
13467 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13469 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13471 gas_assert (nbits
> 0 && nbits
<= 32);
13474 int cmp
= (1 << (nbits
- 1));
13475 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13480 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13486 /* For branches in Armv8.1-M Mainline. */
13488 do_t_branch_future (void)
13490 unsigned long insn
= inst
.instruction
;
13492 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13493 if (inst
.operands
[0].hasreloc
== 0)
13495 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13496 as_bad (BAD_BRANCH_OFF
);
13498 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
13502 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
13503 inst
.relocs
[0].pc_rel
= 1;
13509 if (inst
.operands
[1].hasreloc
== 0)
13511 int val
= inst
.operands
[1].imm
;
13512 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
13513 as_bad (BAD_BRANCH_OFF
);
13515 int immA
= (val
& 0x0001f000) >> 12;
13516 int immB
= (val
& 0x00000ffc) >> 2;
13517 int immC
= (val
& 0x00000002) >> 1;
13518 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13522 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
13523 inst
.relocs
[1].pc_rel
= 1;
13528 if (inst
.operands
[1].hasreloc
== 0)
13530 int val
= inst
.operands
[1].imm
;
13531 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
13532 as_bad (BAD_BRANCH_OFF
);
13534 int immA
= (val
& 0x0007f000) >> 12;
13535 int immB
= (val
& 0x00000ffc) >> 2;
13536 int immC
= (val
& 0x00000002) >> 1;
13537 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13541 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
13542 inst
.relocs
[1].pc_rel
= 1;
13546 case T_MNEM_bfcsel
:
13548 if (inst
.operands
[1].hasreloc
== 0)
13550 int val
= inst
.operands
[1].imm
;
13551 int immA
= (val
& 0x00001000) >> 12;
13552 int immB
= (val
& 0x00000ffc) >> 2;
13553 int immC
= (val
& 0x00000002) >> 1;
13554 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13558 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
13559 inst
.relocs
[1].pc_rel
= 1;
13563 if (inst
.operands
[2].hasreloc
== 0)
13565 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
13566 int val2
= inst
.operands
[2].imm
;
13567 int val0
= inst
.operands
[0].imm
& 0x1f;
13568 int diff
= val2
- val0
;
13570 inst
.instruction
|= 1 << 17; /* T bit. */
13571 else if (diff
!= 2)
13572 as_bad (_("out of range label-relative fixup value"));
13576 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
13577 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
13578 inst
.relocs
[2].pc_rel
= 1;
13582 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
13583 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
13588 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13595 /* Helper function for do_t_loloop to handle relocations. */
13597 v8_1_loop_reloc (int is_le
)
13599 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
13601 int value
= inst
.relocs
[0].exp
.X_add_number
;
13602 value
= (is_le
) ? -value
: value
;
13604 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
13605 as_bad (BAD_BRANCH_OFF
);
13609 immh
= (value
& 0x00000ffc) >> 2;
13610 imml
= (value
& 0x00000002) >> 1;
13612 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
13616 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
13617 inst
.relocs
[0].pc_rel
= 1;
13621 /* To handle the Scalar Low Overhead Loop instructions
13622 in Armv8.1-M Mainline. */
13626 unsigned long insn
= inst
.instruction
;
13628 set_it_insn_type (OUTSIDE_IT_INSN
);
13629 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13635 if (!inst
.operands
[0].present
)
13636 inst
.instruction
|= 1 << 21;
13638 v8_1_loop_reloc (TRUE
);
13642 v8_1_loop_reloc (FALSE
);
13643 /* Fall through. */
13645 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
13646 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
13653 /* Neon instruction encoder helpers. */
13655 /* Encodings for the different types for various Neon opcodes. */
13657 /* An "invalid" code for the following tables. */
13660 struct neon_tab_entry
13663 unsigned float_or_poly
;
13664 unsigned scalar_or_imm
;
13667 /* Map overloaded Neon opcodes to their respective encodings. */
13668 #define NEON_ENC_TAB \
13669 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13670 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13671 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13672 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13673 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13674 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13675 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13676 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13677 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13678 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13679 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13680 /* Register variants of the following two instructions are encoded as
13681 vcge / vcgt with the operands reversed. */ \
13682 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13683 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13684 X(vfma, N_INV, 0x0000c10, N_INV), \
13685 X(vfms, N_INV, 0x0200c10, N_INV), \
13686 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13687 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13688 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13689 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13690 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13691 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13692 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13693 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13694 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13695 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13696 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13697 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13698 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13699 X(vshl, 0x0000400, N_INV, 0x0800510), \
13700 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13701 X(vand, 0x0000110, N_INV, 0x0800030), \
13702 X(vbic, 0x0100110, N_INV, 0x0800030), \
13703 X(veor, 0x1000110, N_INV, N_INV), \
13704 X(vorn, 0x0300110, N_INV, 0x0800010), \
13705 X(vorr, 0x0200110, N_INV, 0x0800010), \
13706 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13707 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13708 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13709 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13710 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13711 X(vst1, 0x0000000, 0x0800000, N_INV), \
13712 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13713 X(vst2, 0x0000100, 0x0800100, N_INV), \
13714 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13715 X(vst3, 0x0000200, 0x0800200, N_INV), \
13716 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13717 X(vst4, 0x0000300, 0x0800300, N_INV), \
13718 X(vmovn, 0x1b20200, N_INV, N_INV), \
13719 X(vtrn, 0x1b20080, N_INV, N_INV), \
13720 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13721 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13722 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13723 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13724 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13725 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13726 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13727 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13728 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13729 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13730 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13731 X(vseleq, 0xe000a00, N_INV, N_INV), \
13732 X(vselvs, 0xe100a00, N_INV, N_INV), \
13733 X(vselge, 0xe200a00, N_INV, N_INV), \
13734 X(vselgt, 0xe300a00, N_INV, N_INV), \
13735 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13736 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13737 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13738 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13739 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13740 X(aes, 0x3b00300, N_INV, N_INV), \
13741 X(sha3op, 0x2000c00, N_INV, N_INV), \
13742 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13743 X(sha2op, 0x3ba0380, N_INV, N_INV)
13747 #define X(OPC,I,F,S) N_MNEM_##OPC
13752 static const struct neon_tab_entry neon_enc_tab
[] =
13754 #define X(OPC,I,F,S) { (I), (F), (S) }
13759 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13760 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13761 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13762 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13763 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13764 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13765 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13766 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13767 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13768 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13769 #define NEON_ENC_SINGLE_(X) \
13770 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13771 #define NEON_ENC_DOUBLE_(X) \
13772 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13773 #define NEON_ENC_FPV8_(X) \
13774 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13776 #define NEON_ENCODE(type, inst) \
13779 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13780 inst.is_neon = 1; \
13784 #define check_neon_suffixes \
13787 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13789 as_bad (_("invalid neon suffix for non neon instruction")); \
13795 /* Define shapes for instruction operands. The following mnemonic characters
13796 are used in this table:
13798 F - VFP S<n> register
13799 D - Neon D<n> register
13800 Q - Neon Q<n> register
13804 L - D<n> register list
13806 This table is used to generate various data:
13807 - enumerations of the form NS_DDR to be used as arguments to
13809 - a table classifying shapes into single, double, quad, mixed.
13810 - a table used to drive neon_select_shape. */
13812 #define NEON_SHAPE_DEF \
13813 X(3, (D, D, D), DOUBLE), \
13814 X(3, (Q, Q, Q), QUAD), \
13815 X(3, (D, D, I), DOUBLE), \
13816 X(3, (Q, Q, I), QUAD), \
13817 X(3, (D, D, S), DOUBLE), \
13818 X(3, (Q, Q, S), QUAD), \
13819 X(2, (D, D), DOUBLE), \
13820 X(2, (Q, Q), QUAD), \
13821 X(2, (D, S), DOUBLE), \
13822 X(2, (Q, S), QUAD), \
13823 X(2, (D, R), DOUBLE), \
13824 X(2, (Q, R), QUAD), \
13825 X(2, (D, I), DOUBLE), \
13826 X(2, (Q, I), QUAD), \
13827 X(3, (D, L, D), DOUBLE), \
13828 X(2, (D, Q), MIXED), \
13829 X(2, (Q, D), MIXED), \
13830 X(3, (D, Q, I), MIXED), \
13831 X(3, (Q, D, I), MIXED), \
13832 X(3, (Q, D, D), MIXED), \
13833 X(3, (D, Q, Q), MIXED), \
13834 X(3, (Q, Q, D), MIXED), \
13835 X(3, (Q, D, S), MIXED), \
13836 X(3, (D, Q, S), MIXED), \
13837 X(4, (D, D, D, I), DOUBLE), \
13838 X(4, (Q, Q, Q, I), QUAD), \
13839 X(4, (D, D, S, I), DOUBLE), \
13840 X(4, (Q, Q, S, I), QUAD), \
13841 X(2, (F, F), SINGLE), \
13842 X(3, (F, F, F), SINGLE), \
13843 X(2, (F, I), SINGLE), \
13844 X(2, (F, D), MIXED), \
13845 X(2, (D, F), MIXED), \
13846 X(3, (F, F, I), MIXED), \
13847 X(4, (R, R, F, F), SINGLE), \
13848 X(4, (F, F, R, R), SINGLE), \
13849 X(3, (D, R, R), DOUBLE), \
13850 X(3, (R, R, D), DOUBLE), \
13851 X(2, (S, R), SINGLE), \
13852 X(2, (R, S), SINGLE), \
13853 X(2, (F, R), SINGLE), \
13854 X(2, (R, F), SINGLE), \
13855 /* Half float shape supported so far. */\
13856 X (2, (H, D), MIXED), \
13857 X (2, (D, H), MIXED), \
13858 X (2, (H, F), MIXED), \
13859 X (2, (F, H), MIXED), \
13860 X (2, (H, H), HALF), \
13861 X (2, (H, R), HALF), \
13862 X (2, (R, H), HALF), \
13863 X (2, (H, I), HALF), \
13864 X (3, (H, H, H), HALF), \
13865 X (3, (H, F, I), MIXED), \
13866 X (3, (F, H, I), MIXED), \
13867 X (3, (D, H, H), MIXED), \
13868 X (3, (D, H, S), MIXED)
13870 #define S2(A,B) NS_##A##B
13871 #define S3(A,B,C) NS_##A##B##C
13872 #define S4(A,B,C,D) NS_##A##B##C##D
13874 #define X(N, L, C) S##N L
13887 enum neon_shape_class
13896 #define X(N, L, C) SC_##C
13898 static enum neon_shape_class neon_shape_class
[] =
13917 /* Register widths of above. */
13918 static unsigned neon_shape_el_size
[] =
13930 struct neon_shape_info
13933 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13936 #define S2(A,B) { SE_##A, SE_##B }
13937 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13938 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13940 #define X(N, L, C) { N, S##N L }
13942 static struct neon_shape_info neon_shape_tab
[] =
13952 /* Bit masks used in type checking given instructions.
13953 'N_EQK' means the type must be the same as (or based on in some way) the key
13954 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13955 set, various other bits can be set as well in order to modify the meaning of
13956 the type constraint. */
13958 enum neon_type_mask
13982 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13983 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13984 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13985 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13986 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13987 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13988 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13989 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13990 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13991 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13992 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13994 N_MAX_NONSPECIAL
= N_P64
13997 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13999 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14000 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14001 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14002 #define N_S_32 (N_S8 | N_S16 | N_S32)
14003 #define N_F_16_32 (N_F16 | N_F32)
14004 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14005 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14006 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14007 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14009 /* Pass this as the first type argument to neon_check_type to ignore types
14011 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14013 /* Select a "shape" for the current instruction (describing register types or
14014 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14015 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14016 function of operand parsing, so this function doesn't need to be called.
14017 Shapes should be listed in order of decreasing length. */
14019 static enum neon_shape
14020 neon_select_shape (enum neon_shape shape
, ...)
14023 enum neon_shape first_shape
= shape
;
14025 /* Fix missing optional operands. FIXME: we don't know at this point how
14026 many arguments we should have, so this makes the assumption that we have
14027 > 1. This is true of all current Neon opcodes, I think, but may not be
14028 true in the future. */
14029 if (!inst
.operands
[1].present
)
14030 inst
.operands
[1] = inst
.operands
[0];
14032 va_start (ap
, shape
);
14034 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14039 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14041 if (!inst
.operands
[j
].present
)
14047 switch (neon_shape_tab
[shape
].el
[j
])
14049 /* If a .f16, .16, .u16, .s16 type specifier is given over
14050 a VFP single precision register operand, it's essentially
14051 means only half of the register is used.
14053 If the type specifier is given after the mnemonics, the
14054 information is stored in inst.vectype. If the type specifier
14055 is given after register operand, the information is stored
14056 in inst.operands[].vectype.
14058 When there is only one type specifier, and all the register
14059 operands are the same type of hardware register, the type
14060 specifier applies to all register operands.
14062 If no type specifier is given, the shape is inferred from
14063 operand information.
14066 vadd.f16 s0, s1, s2: NS_HHH
14067 vabs.f16 s0, s1: NS_HH
14068 vmov.f16 s0, r1: NS_HR
14069 vmov.f16 r0, s1: NS_RH
14070 vcvt.f16 r0, s1: NS_RH
14071 vcvt.f16.s32 s2, s2, #29: NS_HFI
14072 vcvt.f16.s32 s2, s2: NS_HF
14075 if (!(inst
.operands
[j
].isreg
14076 && inst
.operands
[j
].isvec
14077 && inst
.operands
[j
].issingle
14078 && !inst
.operands
[j
].isquad
14079 && ((inst
.vectype
.elems
== 1
14080 && inst
.vectype
.el
[0].size
== 16)
14081 || (inst
.vectype
.elems
> 1
14082 && inst
.vectype
.el
[j
].size
== 16)
14083 || (inst
.vectype
.elems
== 0
14084 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14085 && inst
.operands
[j
].vectype
.size
== 16))))
14090 if (!(inst
.operands
[j
].isreg
14091 && inst
.operands
[j
].isvec
14092 && inst
.operands
[j
].issingle
14093 && !inst
.operands
[j
].isquad
14094 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14095 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14096 || (inst
.vectype
.elems
== 0
14097 && (inst
.operands
[j
].vectype
.size
== 32
14098 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14103 if (!(inst
.operands
[j
].isreg
14104 && inst
.operands
[j
].isvec
14105 && !inst
.operands
[j
].isquad
14106 && !inst
.operands
[j
].issingle
))
14111 if (!(inst
.operands
[j
].isreg
14112 && !inst
.operands
[j
].isvec
))
14117 if (!(inst
.operands
[j
].isreg
14118 && inst
.operands
[j
].isvec
14119 && inst
.operands
[j
].isquad
14120 && !inst
.operands
[j
].issingle
))
14125 if (!(!inst
.operands
[j
].isreg
14126 && !inst
.operands
[j
].isscalar
))
14131 if (!(!inst
.operands
[j
].isreg
14132 && inst
.operands
[j
].isscalar
))
14142 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14143 /* We've matched all the entries in the shape table, and we don't
14144 have any left over operands which have not been matched. */
14150 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14151 first_error (_("invalid instruction shape"));
14156 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14157 means the Q bit should be set). */
14160 neon_quad (enum neon_shape shape
)
14162 return neon_shape_class
[shape
] == SC_QUAD
;
14166 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14169 /* Allow modification to be made to types which are constrained to be
14170 based on the key element, based on bits set alongside N_EQK. */
14171 if ((typebits
& N_EQK
) != 0)
14173 if ((typebits
& N_HLF
) != 0)
14175 else if ((typebits
& N_DBL
) != 0)
14177 if ((typebits
& N_SGN
) != 0)
14178 *g_type
= NT_signed
;
14179 else if ((typebits
& N_UNS
) != 0)
14180 *g_type
= NT_unsigned
;
14181 else if ((typebits
& N_INT
) != 0)
14182 *g_type
= NT_integer
;
14183 else if ((typebits
& N_FLT
) != 0)
14184 *g_type
= NT_float
;
14185 else if ((typebits
& N_SIZ
) != 0)
14186 *g_type
= NT_untyped
;
14190 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14191 operand type, i.e. the single type specified in a Neon instruction when it
14192 is the only one given. */
14194 static struct neon_type_el
14195 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14197 struct neon_type_el dest
= *key
;
14199 gas_assert ((thisarg
& N_EQK
) != 0);
14201 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14206 /* Convert Neon type and size into compact bitmask representation. */
14208 static enum neon_type_mask
14209 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14216 case 8: return N_8
;
14217 case 16: return N_16
;
14218 case 32: return N_32
;
14219 case 64: return N_64
;
14227 case 8: return N_I8
;
14228 case 16: return N_I16
;
14229 case 32: return N_I32
;
14230 case 64: return N_I64
;
14238 case 16: return N_F16
;
14239 case 32: return N_F32
;
14240 case 64: return N_F64
;
14248 case 8: return N_P8
;
14249 case 16: return N_P16
;
14250 case 64: return N_P64
;
14258 case 8: return N_S8
;
14259 case 16: return N_S16
;
14260 case 32: return N_S32
;
14261 case 64: return N_S64
;
14269 case 8: return N_U8
;
14270 case 16: return N_U16
;
14271 case 32: return N_U32
;
14272 case 64: return N_U64
;
14283 /* Convert compact Neon bitmask type representation to a type and size. Only
14284 handles the case where a single bit is set in the mask. */
14287 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14288 enum neon_type_mask mask
)
14290 if ((mask
& N_EQK
) != 0)
14293 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14295 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14297 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14299 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14304 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14306 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14307 *type
= NT_unsigned
;
14308 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14309 *type
= NT_integer
;
14310 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14311 *type
= NT_untyped
;
14312 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14314 else if ((mask
& (N_F_ALL
)) != 0)
14322 /* Modify a bitmask of allowed types. This is only needed for type
14326 modify_types_allowed (unsigned allowed
, unsigned mods
)
14329 enum neon_el_type type
;
14335 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14337 if (el_type_of_type_chk (&type
, &size
,
14338 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14340 neon_modify_type_size (mods
, &type
, &size
);
14341 destmask
|= type_chk_of_el_type (type
, size
);
14348 /* Check type and return type classification.
14349 The manual states (paraphrase): If one datatype is given, it indicates the
14351 - the second operand, if there is one
14352 - the operand, if there is no second operand
14353 - the result, if there are no operands.
14354 This isn't quite good enough though, so we use a concept of a "key" datatype
14355 which is set on a per-instruction basis, which is the one which matters when
14356 only one data type is written.
14357 Note: this function has side-effects (e.g. filling in missing operands). All
14358 Neon instructions should call it before performing bit encoding. */
14360 static struct neon_type_el
14361 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14364 unsigned i
, pass
, key_el
= 0;
14365 unsigned types
[NEON_MAX_TYPE_ELS
];
14366 enum neon_el_type k_type
= NT_invtype
;
14367 unsigned k_size
= -1u;
14368 struct neon_type_el badtype
= {NT_invtype
, -1};
14369 unsigned key_allowed
= 0;
14371 /* Optional registers in Neon instructions are always (not) in operand 1.
14372 Fill in the missing operand here, if it was omitted. */
14373 if (els
> 1 && !inst
.operands
[1].present
)
14374 inst
.operands
[1] = inst
.operands
[0];
14376 /* Suck up all the varargs. */
14378 for (i
= 0; i
< els
; i
++)
14380 unsigned thisarg
= va_arg (ap
, unsigned);
14381 if (thisarg
== N_IGNORE_TYPE
)
14386 types
[i
] = thisarg
;
14387 if ((thisarg
& N_KEY
) != 0)
14392 if (inst
.vectype
.elems
> 0)
14393 for (i
= 0; i
< els
; i
++)
14394 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14396 first_error (_("types specified in both the mnemonic and operands"));
14400 /* Duplicate inst.vectype elements here as necessary.
14401 FIXME: No idea if this is exactly the same as the ARM assembler,
14402 particularly when an insn takes one register and one non-register
14404 if (inst
.vectype
.elems
== 1 && els
> 1)
14407 inst
.vectype
.elems
= els
;
14408 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14409 for (j
= 0; j
< els
; j
++)
14411 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14414 else if (inst
.vectype
.elems
== 0 && els
> 0)
14417 /* No types were given after the mnemonic, so look for types specified
14418 after each operand. We allow some flexibility here; as long as the
14419 "key" operand has a type, we can infer the others. */
14420 for (j
= 0; j
< els
; j
++)
14421 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14422 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14424 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14426 for (j
= 0; j
< els
; j
++)
14427 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14428 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14433 first_error (_("operand types can't be inferred"));
14437 else if (inst
.vectype
.elems
!= els
)
14439 first_error (_("type specifier has the wrong number of parts"));
14443 for (pass
= 0; pass
< 2; pass
++)
14445 for (i
= 0; i
< els
; i
++)
14447 unsigned thisarg
= types
[i
];
14448 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14449 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14450 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14451 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14453 /* Decay more-specific signed & unsigned types to sign-insensitive
14454 integer types if sign-specific variants are unavailable. */
14455 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14456 && (types_allowed
& N_SU_ALL
) == 0)
14457 g_type
= NT_integer
;
14459 /* If only untyped args are allowed, decay any more specific types to
14460 them. Some instructions only care about signs for some element
14461 sizes, so handle that properly. */
14462 if (((types_allowed
& N_UNT
) == 0)
14463 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14464 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14465 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14466 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14467 g_type
= NT_untyped
;
14471 if ((thisarg
& N_KEY
) != 0)
14475 key_allowed
= thisarg
& ~N_KEY
;
14477 /* Check architecture constraint on FP16 extension. */
14479 && k_type
== NT_float
14480 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14482 inst
.error
= _(BAD_FP16
);
14489 if ((thisarg
& N_VFP
) != 0)
14491 enum neon_shape_el regshape
;
14492 unsigned regwidth
, match
;
14494 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14497 first_error (_("invalid instruction shape"));
14500 regshape
= neon_shape_tab
[ns
].el
[i
];
14501 regwidth
= neon_shape_el_size
[regshape
];
14503 /* In VFP mode, operands must match register widths. If we
14504 have a key operand, use its width, else use the width of
14505 the current operand. */
14511 /* FP16 will use a single precision register. */
14512 if (regwidth
== 32 && match
== 16)
14514 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14518 inst
.error
= _(BAD_FP16
);
14523 if (regwidth
!= match
)
14525 first_error (_("operand size must match register width"));
14530 if ((thisarg
& N_EQK
) == 0)
14532 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14534 if ((given_type
& types_allowed
) == 0)
14536 first_error (_("bad type in Neon instruction"));
14542 enum neon_el_type mod_k_type
= k_type
;
14543 unsigned mod_k_size
= k_size
;
14544 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14545 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14547 first_error (_("inconsistent types in Neon instruction"));
14555 return inst
.vectype
.el
[key_el
];
14558 /* Neon-style VFP instruction forwarding. */
14560 /* Thumb VFP instructions have 0xE in the condition field. */
14563 do_vfp_cond_or_thumb (void)
14568 inst
.instruction
|= 0xe0000000;
14570 inst
.instruction
|= inst
.cond
<< 28;
14573 /* Look up and encode a simple mnemonic, for use as a helper function for the
14574 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14575 etc. It is assumed that operand parsing has already been done, and that the
14576 operands are in the form expected by the given opcode (this isn't necessarily
14577 the same as the form in which they were parsed, hence some massaging must
14578 take place before this function is called).
14579 Checks current arch version against that in the looked-up opcode. */
14582 do_vfp_nsyn_opcode (const char *opname
)
14584 const struct asm_opcode
*opcode
;
14586 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14591 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14592 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14599 inst
.instruction
= opcode
->tvalue
;
14600 opcode
->tencode ();
14604 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14605 opcode
->aencode ();
14610 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14612 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14614 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14617 do_vfp_nsyn_opcode ("fadds");
14619 do_vfp_nsyn_opcode ("fsubs");
14621 /* ARMv8.2 fp16 instruction. */
14623 do_scalar_fp16_v82_encode ();
14628 do_vfp_nsyn_opcode ("faddd");
14630 do_vfp_nsyn_opcode ("fsubd");
14634 /* Check operand types to see if this is a VFP instruction, and if so call
14638 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14640 enum neon_shape rs
;
14641 struct neon_type_el et
;
14646 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14647 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14651 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14652 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14653 N_F_ALL
| N_KEY
| N_VFP
);
14660 if (et
.type
!= NT_invtype
)
14671 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14673 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14675 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14678 do_vfp_nsyn_opcode ("fmacs");
14680 do_vfp_nsyn_opcode ("fnmacs");
14682 /* ARMv8.2 fp16 instruction. */
14684 do_scalar_fp16_v82_encode ();
14689 do_vfp_nsyn_opcode ("fmacd");
14691 do_vfp_nsyn_opcode ("fnmacd");
14696 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14698 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14700 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14703 do_vfp_nsyn_opcode ("ffmas");
14705 do_vfp_nsyn_opcode ("ffnmas");
14707 /* ARMv8.2 fp16 instruction. */
14709 do_scalar_fp16_v82_encode ();
14714 do_vfp_nsyn_opcode ("ffmad");
14716 do_vfp_nsyn_opcode ("ffnmad");
14721 do_vfp_nsyn_mul (enum neon_shape rs
)
14723 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14725 do_vfp_nsyn_opcode ("fmuls");
14727 /* ARMv8.2 fp16 instruction. */
14729 do_scalar_fp16_v82_encode ();
14732 do_vfp_nsyn_opcode ("fmuld");
14736 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14738 int is_neg
= (inst
.instruction
& 0x80) != 0;
14739 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14741 if (rs
== NS_FF
|| rs
== NS_HH
)
14744 do_vfp_nsyn_opcode ("fnegs");
14746 do_vfp_nsyn_opcode ("fabss");
14748 /* ARMv8.2 fp16 instruction. */
14750 do_scalar_fp16_v82_encode ();
14755 do_vfp_nsyn_opcode ("fnegd");
14757 do_vfp_nsyn_opcode ("fabsd");
14761 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14762 insns belong to Neon, and are handled elsewhere. */
14765 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14767 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14771 do_vfp_nsyn_opcode ("fldmdbs");
14773 do_vfp_nsyn_opcode ("fldmias");
14778 do_vfp_nsyn_opcode ("fstmdbs");
14780 do_vfp_nsyn_opcode ("fstmias");
14785 do_vfp_nsyn_sqrt (void)
14787 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14788 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14790 if (rs
== NS_FF
|| rs
== NS_HH
)
14792 do_vfp_nsyn_opcode ("fsqrts");
14794 /* ARMv8.2 fp16 instruction. */
14796 do_scalar_fp16_v82_encode ();
14799 do_vfp_nsyn_opcode ("fsqrtd");
14803 do_vfp_nsyn_div (void)
14805 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14806 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14807 N_F_ALL
| N_KEY
| N_VFP
);
14809 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14811 do_vfp_nsyn_opcode ("fdivs");
14813 /* ARMv8.2 fp16 instruction. */
14815 do_scalar_fp16_v82_encode ();
14818 do_vfp_nsyn_opcode ("fdivd");
14822 do_vfp_nsyn_nmul (void)
14824 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14825 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14826 N_F_ALL
| N_KEY
| N_VFP
);
14828 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14830 NEON_ENCODE (SINGLE
, inst
);
14831 do_vfp_sp_dyadic ();
14833 /* ARMv8.2 fp16 instruction. */
14835 do_scalar_fp16_v82_encode ();
14839 NEON_ENCODE (DOUBLE
, inst
);
14840 do_vfp_dp_rd_rn_rm ();
14842 do_vfp_cond_or_thumb ();
14847 do_vfp_nsyn_cmp (void)
14849 enum neon_shape rs
;
14850 if (inst
.operands
[1].isreg
)
14852 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14853 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14855 if (rs
== NS_FF
|| rs
== NS_HH
)
14857 NEON_ENCODE (SINGLE
, inst
);
14858 do_vfp_sp_monadic ();
14862 NEON_ENCODE (DOUBLE
, inst
);
14863 do_vfp_dp_rd_rm ();
14868 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14869 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14871 switch (inst
.instruction
& 0x0fffffff)
14874 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14877 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14883 if (rs
== NS_FI
|| rs
== NS_HI
)
14885 NEON_ENCODE (SINGLE
, inst
);
14886 do_vfp_sp_compare_z ();
14890 NEON_ENCODE (DOUBLE
, inst
);
14894 do_vfp_cond_or_thumb ();
14896 /* ARMv8.2 fp16 instruction. */
14897 if (rs
== NS_HI
|| rs
== NS_HH
)
14898 do_scalar_fp16_v82_encode ();
14902 nsyn_insert_sp (void)
14904 inst
.operands
[1] = inst
.operands
[0];
14905 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14906 inst
.operands
[0].reg
= REG_SP
;
14907 inst
.operands
[0].isreg
= 1;
14908 inst
.operands
[0].writeback
= 1;
14909 inst
.operands
[0].present
= 1;
14913 do_vfp_nsyn_push (void)
14917 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14918 _("register list must contain at least 1 and at most 16 "
14921 if (inst
.operands
[1].issingle
)
14922 do_vfp_nsyn_opcode ("fstmdbs");
14924 do_vfp_nsyn_opcode ("fstmdbd");
14928 do_vfp_nsyn_pop (void)
14932 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14933 _("register list must contain at least 1 and at most 16 "
14936 if (inst
.operands
[1].issingle
)
14937 do_vfp_nsyn_opcode ("fldmias");
14939 do_vfp_nsyn_opcode ("fldmiad");
14942 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14943 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14946 neon_dp_fixup (struct arm_it
* insn
)
14948 unsigned int i
= insn
->instruction
;
14953 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14964 insn
->instruction
= i
;
14967 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14971 neon_logbits (unsigned x
)
14973 return ffs (x
) - 4;
14976 #define LOW4(R) ((R) & 0xf)
14977 #define HI1(R) (((R) >> 4) & 1)
14979 /* Encode insns with bit pattern:
14981 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14982 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14984 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14985 different meaning for some instruction. */
14988 neon_three_same (int isquad
, int ubit
, int size
)
14990 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14991 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14992 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14993 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14994 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14995 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14996 inst
.instruction
|= (isquad
!= 0) << 6;
14997 inst
.instruction
|= (ubit
!= 0) << 24;
14999 inst
.instruction
|= neon_logbits (size
) << 20;
15001 neon_dp_fixup (&inst
);
15004 /* Encode instructions of the form:
15006 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
15007 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
15009 Don't write size if SIZE == -1. */
15012 neon_two_same (int qbit
, int ubit
, int size
)
15014 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15015 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15016 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15017 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15018 inst
.instruction
|= (qbit
!= 0) << 6;
15019 inst
.instruction
|= (ubit
!= 0) << 24;
15022 inst
.instruction
|= neon_logbits (size
) << 18;
15024 neon_dp_fixup (&inst
);
15027 /* Neon instruction encoders, in approximate order of appearance. */
15030 do_neon_dyadic_i_su (void)
15032 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15033 struct neon_type_el et
= neon_check_type (3, rs
,
15034 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
15035 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15039 do_neon_dyadic_i64_su (void)
15041 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15042 struct neon_type_el et
= neon_check_type (3, rs
,
15043 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
15044 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15048 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
15051 unsigned size
= et
.size
>> 3;
15052 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15053 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15054 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15055 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15056 inst
.instruction
|= (isquad
!= 0) << 6;
15057 inst
.instruction
|= immbits
<< 16;
15058 inst
.instruction
|= (size
>> 3) << 7;
15059 inst
.instruction
|= (size
& 0x7) << 19;
15061 inst
.instruction
|= (uval
!= 0) << 24;
15063 neon_dp_fixup (&inst
);
15067 do_neon_shl_imm (void)
15069 if (!inst
.operands
[2].isreg
)
15071 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15072 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
15073 int imm
= inst
.operands
[2].imm
;
15075 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15076 _("immediate out of range for shift"));
15077 NEON_ENCODE (IMMED
, inst
);
15078 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15082 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15083 struct neon_type_el et
= neon_check_type (3, rs
,
15084 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
15087 /* VSHL/VQSHL 3-register variants have syntax such as:
15089 whereas other 3-register operations encoded by neon_three_same have
15092 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
15094 tmp
= inst
.operands
[2].reg
;
15095 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15096 inst
.operands
[1].reg
= tmp
;
15097 NEON_ENCODE (INTEGER
, inst
);
15098 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15103 do_neon_qshl_imm (void)
15105 if (!inst
.operands
[2].isreg
)
15107 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15108 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15109 int imm
= inst
.operands
[2].imm
;
15111 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15112 _("immediate out of range for shift"));
15113 NEON_ENCODE (IMMED
, inst
);
15114 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
15118 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15119 struct neon_type_el et
= neon_check_type (3, rs
,
15120 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
15123 /* See note in do_neon_shl_imm. */
15124 tmp
= inst
.operands
[2].reg
;
15125 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15126 inst
.operands
[1].reg
= tmp
;
15127 NEON_ENCODE (INTEGER
, inst
);
15128 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15133 do_neon_rshl (void)
15135 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15136 struct neon_type_el et
= neon_check_type (3, rs
,
15137 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
15140 tmp
= inst
.operands
[2].reg
;
15141 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15142 inst
.operands
[1].reg
= tmp
;
15143 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15147 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
15149 /* Handle .I8 pseudo-instructions. */
15152 /* Unfortunately, this will make everything apart from zero out-of-range.
15153 FIXME is this the intended semantics? There doesn't seem much point in
15154 accepting .I8 if so. */
15155 immediate
|= immediate
<< 8;
15161 if (immediate
== (immediate
& 0x000000ff))
15163 *immbits
= immediate
;
15166 else if (immediate
== (immediate
& 0x0000ff00))
15168 *immbits
= immediate
>> 8;
15171 else if (immediate
== (immediate
& 0x00ff0000))
15173 *immbits
= immediate
>> 16;
15176 else if (immediate
== (immediate
& 0xff000000))
15178 *immbits
= immediate
>> 24;
15181 if ((immediate
& 0xffff) != (immediate
>> 16))
15182 goto bad_immediate
;
15183 immediate
&= 0xffff;
15186 if (immediate
== (immediate
& 0x000000ff))
15188 *immbits
= immediate
;
15191 else if (immediate
== (immediate
& 0x0000ff00))
15193 *immbits
= immediate
>> 8;
15198 first_error (_("immediate value out of range"));
15203 do_neon_logic (void)
15205 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
15207 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15208 neon_check_type (3, rs
, N_IGNORE_TYPE
);
15209 /* U bit and size field were set as part of the bitmask. */
15210 NEON_ENCODE (INTEGER
, inst
);
15211 neon_three_same (neon_quad (rs
), 0, -1);
15215 const int three_ops_form
= (inst
.operands
[2].present
15216 && !inst
.operands
[2].isreg
);
15217 const int immoperand
= (three_ops_form
? 2 : 1);
15218 enum neon_shape rs
= (three_ops_form
15219 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
15220 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
15221 struct neon_type_el et
= neon_check_type (2, rs
,
15222 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15223 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
15227 if (et
.type
== NT_invtype
)
15230 if (three_ops_form
)
15231 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15232 _("first and second operands shall be the same register"));
15234 NEON_ENCODE (IMMED
, inst
);
15236 immbits
= inst
.operands
[immoperand
].imm
;
15239 /* .i64 is a pseudo-op, so the immediate must be a repeating
15241 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
15242 inst
.operands
[immoperand
].reg
: 0))
15244 /* Set immbits to an invalid constant. */
15245 immbits
= 0xdeadbeef;
15252 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15256 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15260 /* Pseudo-instruction for VBIC. */
15261 neon_invert_size (&immbits
, 0, et
.size
);
15262 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15266 /* Pseudo-instruction for VORR. */
15267 neon_invert_size (&immbits
, 0, et
.size
);
15268 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15278 inst
.instruction
|= neon_quad (rs
) << 6;
15279 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15280 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15281 inst
.instruction
|= cmode
<< 8;
15282 neon_write_immbits (immbits
);
15284 neon_dp_fixup (&inst
);
15289 do_neon_bitfield (void)
15291 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15292 neon_check_type (3, rs
, N_IGNORE_TYPE
);
15293 neon_three_same (neon_quad (rs
), 0, -1);
15297 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
15300 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15301 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
15303 if (et
.type
== NT_float
)
15305 NEON_ENCODE (FLOAT
, inst
);
15306 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15310 NEON_ENCODE (INTEGER
, inst
);
15311 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
15316 do_neon_dyadic_if_su (void)
15318 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
15322 do_neon_dyadic_if_su_d (void)
15324 /* This version only allow D registers, but that constraint is enforced during
15325 operand parsing so we don't need to do anything extra here. */
15326 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
15330 do_neon_dyadic_if_i_d (void)
15332 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15333 affected if we specify unsigned args. */
15334 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15337 enum vfp_or_neon_is_neon_bits
15340 NEON_CHECK_ARCH
= 2,
15341 NEON_CHECK_ARCH8
= 4
15344 /* Call this function if an instruction which may have belonged to the VFP or
15345 Neon instruction sets, but turned out to be a Neon instruction (due to the
15346 operand types involved, etc.). We have to check and/or fix-up a couple of
15349 - Make sure the user hasn't attempted to make a Neon instruction
15351 - Alter the value in the condition code field if necessary.
15352 - Make sure that the arch supports Neon instructions.
15354 Which of these operations take place depends on bits from enum
15355 vfp_or_neon_is_neon_bits.
15357 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
15358 current instruction's condition is COND_ALWAYS, the condition field is
15359 changed to inst.uncond_value. This is necessary because instructions shared
15360 between VFP and Neon may be conditional for the VFP variants only, and the
15361 unconditional Neon version must have, e.g., 0xF in the condition field. */
15364 vfp_or_neon_is_neon (unsigned check
)
15366 /* Conditions are always legal in Thumb mode (IT blocks). */
15367 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
15369 if (inst
.cond
!= COND_ALWAYS
)
15371 first_error (_(BAD_COND
));
15374 if (inst
.uncond_value
!= -1)
15375 inst
.instruction
|= inst
.uncond_value
<< 28;
15378 if ((check
& NEON_CHECK_ARCH
)
15379 && !mark_feature_used (&fpu_neon_ext_v1
))
15381 first_error (_(BAD_FPU
));
15385 if ((check
& NEON_CHECK_ARCH8
)
15386 && !mark_feature_used (&fpu_neon_ext_armv8
))
15388 first_error (_(BAD_FPU
));
15396 do_neon_addsub_if_i (void)
15398 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
15401 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15404 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15405 affected if we specify unsigned args. */
15406 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
15409 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
15411 V<op> A,B (A is operand 0, B is operand 2)
15416 so handle that case specially. */
15419 neon_exchange_operands (void)
15421 if (inst
.operands
[1].present
)
15423 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
15425 /* Swap operands[1] and operands[2]. */
15426 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
15427 inst
.operands
[1] = inst
.operands
[2];
15428 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
15433 inst
.operands
[1] = inst
.operands
[2];
15434 inst
.operands
[2] = inst
.operands
[0];
15439 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
15441 if (inst
.operands
[2].isreg
)
15444 neon_exchange_operands ();
15445 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15449 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15450 struct neon_type_el et
= neon_check_type (2, rs
,
15451 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15453 NEON_ENCODE (IMMED
, inst
);
15454 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15455 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15456 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15457 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15458 inst
.instruction
|= neon_quad (rs
) << 6;
15459 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15460 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15462 neon_dp_fixup (&inst
);
15469 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15473 do_neon_cmp_inv (void)
15475 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15481 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15484 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15485 scalars, which are encoded in 5 bits, M : Rm.
15486 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15487 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15490 Dot Product instructions are similar to multiply instructions except elsize
15491 should always be 32.
15493 This function translates SCALAR, which is GAS's internal encoding of indexed
15494 scalar register, to raw encoding. There is also register and index range
15495 check based on ELSIZE. */
15498 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15500 unsigned regno
= NEON_SCALAR_REG (scalar
);
15501 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15506 if (regno
> 7 || elno
> 3)
15508 return regno
| (elno
<< 3);
15511 if (regno
> 15 || elno
> 1)
15513 return regno
| (elno
<< 4);
15517 first_error (_("scalar out of range for multiply instruction"));
15523 /* Encode multiply / multiply-accumulate scalar instructions. */
15526 neon_mul_mac (struct neon_type_el et
, int ubit
)
15530 /* Give a more helpful error message if we have an invalid type. */
15531 if (et
.type
== NT_invtype
)
15534 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15535 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15536 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15537 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15538 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15539 inst
.instruction
|= LOW4 (scalar
);
15540 inst
.instruction
|= HI1 (scalar
) << 5;
15541 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15542 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15543 inst
.instruction
|= (ubit
!= 0) << 24;
15545 neon_dp_fixup (&inst
);
15549 do_neon_mac_maybe_scalar (void)
15551 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15554 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15557 if (inst
.operands
[2].isscalar
)
15559 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15560 struct neon_type_el et
= neon_check_type (3, rs
,
15561 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15562 NEON_ENCODE (SCALAR
, inst
);
15563 neon_mul_mac (et
, neon_quad (rs
));
15567 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15568 affected if we specify unsigned args. */
15569 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15574 do_neon_fmac (void)
15576 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15579 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15582 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15588 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15589 struct neon_type_el et
= neon_check_type (3, rs
,
15590 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15591 neon_three_same (neon_quad (rs
), 0, et
.size
);
15594 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15595 same types as the MAC equivalents. The polynomial type for this instruction
15596 is encoded the same as the integer type. */
15601 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15604 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15607 if (inst
.operands
[2].isscalar
)
15608 do_neon_mac_maybe_scalar ();
15610 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15614 do_neon_qdmulh (void)
15616 if (inst
.operands
[2].isscalar
)
15618 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15619 struct neon_type_el et
= neon_check_type (3, rs
,
15620 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15621 NEON_ENCODE (SCALAR
, inst
);
15622 neon_mul_mac (et
, neon_quad (rs
));
15626 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15627 struct neon_type_el et
= neon_check_type (3, rs
,
15628 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15629 NEON_ENCODE (INTEGER
, inst
);
15630 /* The U bit (rounding) comes from bit mask. */
15631 neon_three_same (neon_quad (rs
), 0, et
.size
);
15636 do_neon_qrdmlah (void)
15638 /* Check we're on the correct architecture. */
15639 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15641 _("instruction form not available on this architecture.");
15642 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15644 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15645 record_feature_use (&fpu_neon_ext_v8_1
);
15648 if (inst
.operands
[2].isscalar
)
15650 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15651 struct neon_type_el et
= neon_check_type (3, rs
,
15652 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15653 NEON_ENCODE (SCALAR
, inst
);
15654 neon_mul_mac (et
, neon_quad (rs
));
15658 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15659 struct neon_type_el et
= neon_check_type (3, rs
,
15660 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15661 NEON_ENCODE (INTEGER
, inst
);
15662 /* The U bit (rounding) comes from bit mask. */
15663 neon_three_same (neon_quad (rs
), 0, et
.size
);
15668 do_neon_fcmp_absolute (void)
15670 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15671 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15672 N_F_16_32
| N_KEY
);
15673 /* Size field comes from bit mask. */
15674 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15678 do_neon_fcmp_absolute_inv (void)
15680 neon_exchange_operands ();
15681 do_neon_fcmp_absolute ();
15685 do_neon_step (void)
15687 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15688 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15689 N_F_16_32
| N_KEY
);
15690 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15694 do_neon_abs_neg (void)
15696 enum neon_shape rs
;
15697 struct neon_type_el et
;
15699 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15702 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15705 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15706 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15708 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15709 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15710 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15711 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15712 inst
.instruction
|= neon_quad (rs
) << 6;
15713 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15714 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15716 neon_dp_fixup (&inst
);
15722 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15723 struct neon_type_el et
= neon_check_type (2, rs
,
15724 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15725 int imm
= inst
.operands
[2].imm
;
15726 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15727 _("immediate out of range for insert"));
15728 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15734 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15735 struct neon_type_el et
= neon_check_type (2, rs
,
15736 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15737 int imm
= inst
.operands
[2].imm
;
15738 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15739 _("immediate out of range for insert"));
15740 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15744 do_neon_qshlu_imm (void)
15746 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15747 struct neon_type_el et
= neon_check_type (2, rs
,
15748 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15749 int imm
= inst
.operands
[2].imm
;
15750 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15751 _("immediate out of range for shift"));
15752 /* Only encodes the 'U present' variant of the instruction.
15753 In this case, signed types have OP (bit 8) set to 0.
15754 Unsigned types have OP set to 1. */
15755 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15756 /* The rest of the bits are the same as other immediate shifts. */
15757 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15761 do_neon_qmovn (void)
15763 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15764 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15765 /* Saturating move where operands can be signed or unsigned, and the
15766 destination has the same signedness. */
15767 NEON_ENCODE (INTEGER
, inst
);
15768 if (et
.type
== NT_unsigned
)
15769 inst
.instruction
|= 0xc0;
15771 inst
.instruction
|= 0x80;
15772 neon_two_same (0, 1, et
.size
/ 2);
15776 do_neon_qmovun (void)
15778 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15779 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15780 /* Saturating move with unsigned results. Operands must be signed. */
15781 NEON_ENCODE (INTEGER
, inst
);
15782 neon_two_same (0, 1, et
.size
/ 2);
15786 do_neon_rshift_sat_narrow (void)
15788 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15789 or unsigned. If operands are unsigned, results must also be unsigned. */
15790 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15791 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15792 int imm
= inst
.operands
[2].imm
;
15793 /* This gets the bounds check, size encoding and immediate bits calculation
15797 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15798 VQMOVN.I<size> <Dd>, <Qm>. */
15801 inst
.operands
[2].present
= 0;
15802 inst
.instruction
= N_MNEM_vqmovn
;
15807 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15808 _("immediate out of range"));
15809 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15813 do_neon_rshift_sat_narrow_u (void)
15815 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15816 or unsigned. If operands are unsigned, results must also be unsigned. */
15817 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15818 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15819 int imm
= inst
.operands
[2].imm
;
15820 /* This gets the bounds check, size encoding and immediate bits calculation
15824 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15825 VQMOVUN.I<size> <Dd>, <Qm>. */
15828 inst
.operands
[2].present
= 0;
15829 inst
.instruction
= N_MNEM_vqmovun
;
15834 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15835 _("immediate out of range"));
15836 /* FIXME: The manual is kind of unclear about what value U should have in
15837 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15839 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15843 do_neon_movn (void)
15845 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15846 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15847 NEON_ENCODE (INTEGER
, inst
);
15848 neon_two_same (0, 1, et
.size
/ 2);
15852 do_neon_rshift_narrow (void)
15854 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15855 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15856 int imm
= inst
.operands
[2].imm
;
15857 /* This gets the bounds check, size encoding and immediate bits calculation
15861 /* If immediate is zero then we are a pseudo-instruction for
15862 VMOVN.I<size> <Dd>, <Qm> */
15865 inst
.operands
[2].present
= 0;
15866 inst
.instruction
= N_MNEM_vmovn
;
15871 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15872 _("immediate out of range for narrowing operation"));
15873 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15877 do_neon_shll (void)
15879 /* FIXME: Type checking when lengthening. */
15880 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15881 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15882 unsigned imm
= inst
.operands
[2].imm
;
15884 if (imm
== et
.size
)
15886 /* Maximum shift variant. */
15887 NEON_ENCODE (INTEGER
, inst
);
15888 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15889 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15890 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15891 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15892 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15894 neon_dp_fixup (&inst
);
15898 /* A more-specific type check for non-max versions. */
15899 et
= neon_check_type (2, NS_QDI
,
15900 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15901 NEON_ENCODE (IMMED
, inst
);
15902 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15906 /* Check the various types for the VCVT instruction, and return which version
15907 the current instruction is. */
15909 #define CVT_FLAVOUR_VAR \
15910 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15911 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15912 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15913 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15914 /* Half-precision conversions. */ \
15915 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15916 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15917 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15918 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15919 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15920 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15921 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15922 Compared with single/double precision variants, only the co-processor \
15923 field is different, so the encoding flow is reused here. */ \
15924 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15925 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15926 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15927 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15928 /* VFP instructions. */ \
15929 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15930 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15931 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15932 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15933 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15934 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15935 /* VFP instructions with bitshift. */ \
15936 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15937 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15938 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15939 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15940 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15941 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15942 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15943 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15945 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15946 neon_cvt_flavour_##C,
15948 /* The different types of conversions we can do. */
15949 enum neon_cvt_flavour
15952 neon_cvt_flavour_invalid
,
15953 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15958 static enum neon_cvt_flavour
15959 get_neon_cvt_flavour (enum neon_shape rs
)
15961 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15962 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15963 if (et.type != NT_invtype) \
15965 inst.error = NULL; \
15966 return (neon_cvt_flavour_##C); \
15969 struct neon_type_el et
;
15970 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15971 || rs
== NS_FF
) ? N_VFP
: 0;
15972 /* The instruction versions which take an immediate take one register
15973 argument, which is extended to the width of the full register. Thus the
15974 "source" and "destination" registers must have the same width. Hack that
15975 here by making the size equal to the key (wider, in this case) operand. */
15976 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15980 return neon_cvt_flavour_invalid
;
15995 /* Neon-syntax VFP conversions. */
15998 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
16000 const char *opname
= 0;
16002 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
16003 || rs
== NS_FHI
|| rs
== NS_HFI
)
16005 /* Conversions with immediate bitshift. */
16006 const char *enc
[] =
16008 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
16014 if (flavour
< (int) ARRAY_SIZE (enc
))
16016 opname
= enc
[flavour
];
16017 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16018 _("operands 0 and 1 must be the same register"));
16019 inst
.operands
[1] = inst
.operands
[2];
16020 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
16025 /* Conversions without bitshift. */
16026 const char *enc
[] =
16028 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
16034 if (flavour
< (int) ARRAY_SIZE (enc
))
16035 opname
= enc
[flavour
];
16039 do_vfp_nsyn_opcode (opname
);
16041 /* ARMv8.2 fp16 VCVT instruction. */
16042 if (flavour
== neon_cvt_flavour_s32_f16
16043 || flavour
== neon_cvt_flavour_u32_f16
16044 || flavour
== neon_cvt_flavour_f16_u32
16045 || flavour
== neon_cvt_flavour_f16_s32
)
16046 do_scalar_fp16_v82_encode ();
16050 do_vfp_nsyn_cvtz (void)
16052 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
16053 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
16054 const char *enc
[] =
16056 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
16062 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
16063 do_vfp_nsyn_opcode (enc
[flavour
]);
16067 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
16068 enum neon_cvt_mode mode
)
16073 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16074 D register operands. */
16075 if (flavour
== neon_cvt_flavour_s32_f64
16076 || flavour
== neon_cvt_flavour_u32_f64
)
16077 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16080 if (flavour
== neon_cvt_flavour_s32_f16
16081 || flavour
== neon_cvt_flavour_u32_f16
)
16082 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
16085 set_it_insn_type (OUTSIDE_IT_INSN
);
16089 case neon_cvt_flavour_s32_f64
:
16093 case neon_cvt_flavour_s32_f32
:
16097 case neon_cvt_flavour_s32_f16
:
16101 case neon_cvt_flavour_u32_f64
:
16105 case neon_cvt_flavour_u32_f32
:
16109 case neon_cvt_flavour_u32_f16
:
16114 first_error (_("invalid instruction shape"));
16120 case neon_cvt_mode_a
: rm
= 0; break;
16121 case neon_cvt_mode_n
: rm
= 1; break;
16122 case neon_cvt_mode_p
: rm
= 2; break;
16123 case neon_cvt_mode_m
: rm
= 3; break;
16124 default: first_error (_("invalid rounding mode")); return;
16127 NEON_ENCODE (FPV8
, inst
);
16128 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
16129 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
16130 inst
.instruction
|= sz
<< 8;
16132 /* ARMv8.2 fp16 VCVT instruction. */
16133 if (flavour
== neon_cvt_flavour_s32_f16
16134 ||flavour
== neon_cvt_flavour_u32_f16
)
16135 do_scalar_fp16_v82_encode ();
16136 inst
.instruction
|= op
<< 7;
16137 inst
.instruction
|= rm
<< 16;
16138 inst
.instruction
|= 0xf0000000;
16139 inst
.is_neon
= TRUE
;
16143 do_neon_cvt_1 (enum neon_cvt_mode mode
)
16145 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
16146 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
16147 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
16149 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
16151 if (flavour
== neon_cvt_flavour_invalid
)
16154 /* PR11109: Handle round-to-zero for VCVT conversions. */
16155 if (mode
== neon_cvt_mode_z
16156 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
16157 && (flavour
== neon_cvt_flavour_s16_f16
16158 || flavour
== neon_cvt_flavour_u16_f16
16159 || flavour
== neon_cvt_flavour_s32_f32
16160 || flavour
== neon_cvt_flavour_u32_f32
16161 || flavour
== neon_cvt_flavour_s32_f64
16162 || flavour
== neon_cvt_flavour_u32_f64
)
16163 && (rs
== NS_FD
|| rs
== NS_FF
))
16165 do_vfp_nsyn_cvtz ();
16169 /* ARMv8.2 fp16 VCVT conversions. */
16170 if (mode
== neon_cvt_mode_z
16171 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
16172 && (flavour
== neon_cvt_flavour_s32_f16
16173 || flavour
== neon_cvt_flavour_u32_f16
)
16176 do_vfp_nsyn_cvtz ();
16177 do_scalar_fp16_v82_encode ();
16181 /* VFP rather than Neon conversions. */
16182 if (flavour
>= neon_cvt_flavour_first_fp
)
16184 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
16185 do_vfp_nsyn_cvt (rs
, flavour
);
16187 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
16198 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
16199 0x0000100, 0x1000100, 0x0, 0x1000000};
16201 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16204 /* Fixed-point conversion with #0 immediate is encoded as an
16205 integer conversion. */
16206 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
16208 NEON_ENCODE (IMMED
, inst
);
16209 if (flavour
!= neon_cvt_flavour_invalid
)
16210 inst
.instruction
|= enctab
[flavour
];
16211 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16212 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16213 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16214 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16215 inst
.instruction
|= neon_quad (rs
) << 6;
16216 inst
.instruction
|= 1 << 21;
16217 if (flavour
< neon_cvt_flavour_s16_f16
)
16219 inst
.instruction
|= 1 << 21;
16220 immbits
= 32 - inst
.operands
[2].imm
;
16221 inst
.instruction
|= immbits
<< 16;
16225 inst
.instruction
|= 3 << 20;
16226 immbits
= 16 - inst
.operands
[2].imm
;
16227 inst
.instruction
|= immbits
<< 16;
16228 inst
.instruction
&= ~(1 << 9);
16231 neon_dp_fixup (&inst
);
16237 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
16239 NEON_ENCODE (FLOAT
, inst
);
16240 set_it_insn_type (OUTSIDE_IT_INSN
);
16242 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16245 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16246 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16247 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16248 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16249 inst
.instruction
|= neon_quad (rs
) << 6;
16250 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
16251 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
16252 inst
.instruction
|= mode
<< 8;
16253 if (flavour
== neon_cvt_flavour_u16_f16
16254 || flavour
== neon_cvt_flavour_s16_f16
)
16255 /* Mask off the original size bits and reencode them. */
16256 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
16259 inst
.instruction
|= 0xfc000000;
16261 inst
.instruction
|= 0xf0000000;
16267 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
16268 0x100, 0x180, 0x0, 0x080};
16270 NEON_ENCODE (INTEGER
, inst
);
16272 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16275 if (flavour
!= neon_cvt_flavour_invalid
)
16276 inst
.instruction
|= enctab
[flavour
];
16278 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16279 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16280 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16281 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16282 inst
.instruction
|= neon_quad (rs
) << 6;
16283 if (flavour
>= neon_cvt_flavour_s16_f16
16284 && flavour
<= neon_cvt_flavour_f16_u16
)
16285 /* Half precision. */
16286 inst
.instruction
|= 1 << 18;
16288 inst
.instruction
|= 2 << 18;
16290 neon_dp_fixup (&inst
);
16295 /* Half-precision conversions for Advanced SIMD -- neon. */
16298 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16302 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
16304 as_bad (_("operand size must match register width"));
16309 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
16311 as_bad (_("operand size must match register width"));
16316 inst
.instruction
= 0x3b60600;
16318 inst
.instruction
= 0x3b60700;
16320 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16321 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16322 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16323 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16324 neon_dp_fixup (&inst
);
16328 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
16329 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
16330 do_vfp_nsyn_cvt (rs
, flavour
);
16332 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
16337 do_neon_cvtr (void)
16339 do_neon_cvt_1 (neon_cvt_mode_x
);
16345 do_neon_cvt_1 (neon_cvt_mode_z
);
16349 do_neon_cvta (void)
16351 do_neon_cvt_1 (neon_cvt_mode_a
);
16355 do_neon_cvtn (void)
16357 do_neon_cvt_1 (neon_cvt_mode_n
);
16361 do_neon_cvtp (void)
16363 do_neon_cvt_1 (neon_cvt_mode_p
);
16367 do_neon_cvtm (void)
16369 do_neon_cvt_1 (neon_cvt_mode_m
);
16373 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
16376 mark_feature_used (&fpu_vfp_ext_armv8
);
16378 encode_arm_vfp_reg (inst
.operands
[0].reg
,
16379 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
16380 encode_arm_vfp_reg (inst
.operands
[1].reg
,
16381 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
16382 inst
.instruction
|= to
? 0x10000 : 0;
16383 inst
.instruction
|= t
? 0x80 : 0;
16384 inst
.instruction
|= is_double
? 0x100 : 0;
16385 do_vfp_cond_or_thumb ();
16389 do_neon_cvttb_1 (bfd_boolean t
)
16391 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
16392 NS_DF
, NS_DH
, NS_NULL
);
16396 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
16399 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
16401 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
16404 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
16406 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
16408 /* The VCVTB and VCVTT instructions with D-register operands
16409 don't work for SP only targets. */
16410 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16414 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
16416 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
16418 /* The VCVTB and VCVTT instructions with D-register operands
16419 don't work for SP only targets. */
16420 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16424 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
16431 do_neon_cvtb (void)
16433 do_neon_cvttb_1 (FALSE
);
16438 do_neon_cvtt (void)
16440 do_neon_cvttb_1 (TRUE
);
16444 neon_move_immediate (void)
16446 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
16447 struct neon_type_el et
= neon_check_type (2, rs
,
16448 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16449 unsigned immlo
, immhi
= 0, immbits
;
16450 int op
, cmode
, float_p
;
16452 constraint (et
.type
== NT_invtype
,
16453 _("operand size must be specified for immediate VMOV"));
16455 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16456 op
= (inst
.instruction
& (1 << 5)) != 0;
16458 immlo
= inst
.operands
[1].imm
;
16459 if (inst
.operands
[1].regisimm
)
16460 immhi
= inst
.operands
[1].reg
;
16462 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16463 _("immediate has bits set outside the operand size"));
16465 float_p
= inst
.operands
[1].immisfloat
;
16467 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16468 et
.size
, et
.type
)) == FAIL
)
16470 /* Invert relevant bits only. */
16471 neon_invert_size (&immlo
, &immhi
, et
.size
);
16472 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16473 with one or the other; those cases are caught by
16474 neon_cmode_for_move_imm. */
16476 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16477 &op
, et
.size
, et
.type
)) == FAIL
)
16479 first_error (_("immediate out of range"));
16484 inst
.instruction
&= ~(1 << 5);
16485 inst
.instruction
|= op
<< 5;
16487 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16488 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16489 inst
.instruction
|= neon_quad (rs
) << 6;
16490 inst
.instruction
|= cmode
<< 8;
16492 neon_write_immbits (immbits
);
16498 if (inst
.operands
[1].isreg
)
16500 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16502 NEON_ENCODE (INTEGER
, inst
);
16503 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16504 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16505 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16506 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16507 inst
.instruction
|= neon_quad (rs
) << 6;
16511 NEON_ENCODE (IMMED
, inst
);
16512 neon_move_immediate ();
16515 neon_dp_fixup (&inst
);
16518 /* Encode instructions of form:
16520 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16521 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16524 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16526 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16527 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16528 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16529 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16530 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16531 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16532 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16533 inst
.instruction
|= neon_logbits (size
) << 20;
16535 neon_dp_fixup (&inst
);
16539 do_neon_dyadic_long (void)
16541 /* FIXME: Type checking for lengthening op. */
16542 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16543 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16544 neon_mixed_length (et
, et
.size
);
16548 do_neon_abal (void)
16550 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16551 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16552 neon_mixed_length (et
, et
.size
);
16556 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16558 if (inst
.operands
[2].isscalar
)
16560 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16561 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16562 NEON_ENCODE (SCALAR
, inst
);
16563 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16567 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16568 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16569 NEON_ENCODE (INTEGER
, inst
);
16570 neon_mixed_length (et
, et
.size
);
16575 do_neon_mac_maybe_scalar_long (void)
16577 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16580 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16581 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16584 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
16586 unsigned regno
= NEON_SCALAR_REG (scalar
);
16587 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16591 if (regno
> 7 || elno
> 3)
16594 return ((regno
& 0x7)
16595 | ((elno
& 0x1) << 3)
16596 | (((elno
>> 1) & 0x1) << 5));
16600 if (regno
> 15 || elno
> 1)
16603 return (((regno
& 0x1) << 5)
16604 | ((regno
>> 1) & 0x7)
16605 | ((elno
& 0x1) << 3));
16609 first_error (_("scalar out of range for multiply instruction"));
16614 do_neon_fmac_maybe_scalar_long (int subtype
)
16616 enum neon_shape rs
;
16618 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16619 field (bits[21:20]) has different meaning. For scalar index variant, it's
16620 used to differentiate add and subtract, otherwise it's with fixed value
16624 if (inst
.cond
!= COND_ALWAYS
)
16625 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16626 "behaviour is UNPREDICTABLE"));
16628 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
16631 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
16634 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16635 be a scalar index register. */
16636 if (inst
.operands
[2].isscalar
)
16638 high8
= 0xfe000000;
16641 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
16645 high8
= 0xfc000000;
16648 inst
.instruction
|= (0x1 << 23);
16649 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
16652 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
16654 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16655 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16656 so we simply pass -1 as size. */
16657 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
16658 neon_three_same (quad_p
, 0, size
);
16660 /* Undo neon_dp_fixup. Redo the high eight bits. */
16661 inst
.instruction
&= 0x00ffffff;
16662 inst
.instruction
|= high8
;
16664 #define LOW1(R) ((R) & 0x1)
16665 #define HI4(R) (((R) >> 1) & 0xf)
16666 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16667 whether the instruction is in Q form and whether Vm is a scalar indexed
16669 if (inst
.operands
[2].isscalar
)
16672 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
16673 inst
.instruction
&= 0xffffffd0;
16674 inst
.instruction
|= rm
;
16678 /* Redo Rn as well. */
16679 inst
.instruction
&= 0xfff0ff7f;
16680 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16681 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16686 /* Redo Rn and Rm. */
16687 inst
.instruction
&= 0xfff0ff50;
16688 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16689 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16690 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
16691 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
16696 do_neon_vfmal (void)
16698 return do_neon_fmac_maybe_scalar_long (0);
16702 do_neon_vfmsl (void)
16704 return do_neon_fmac_maybe_scalar_long (1);
16708 do_neon_dyadic_wide (void)
16710 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16711 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16712 neon_mixed_length (et
, et
.size
);
16716 do_neon_dyadic_narrow (void)
16718 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16719 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16720 /* Operand sign is unimportant, and the U bit is part of the opcode,
16721 so force the operand type to integer. */
16722 et
.type
= NT_integer
;
16723 neon_mixed_length (et
, et
.size
/ 2);
16727 do_neon_mul_sat_scalar_long (void)
16729 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16733 do_neon_vmull (void)
16735 if (inst
.operands
[2].isscalar
)
16736 do_neon_mac_maybe_scalar_long ();
16739 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16740 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16742 if (et
.type
== NT_poly
)
16743 NEON_ENCODE (POLY
, inst
);
16745 NEON_ENCODE (INTEGER
, inst
);
16747 /* For polynomial encoding the U bit must be zero, and the size must
16748 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16749 obviously, as 0b10). */
16752 /* Check we're on the correct architecture. */
16753 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16755 _("Instruction form not available on this architecture.");
16760 neon_mixed_length (et
, et
.size
);
16767 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16768 struct neon_type_el et
= neon_check_type (3, rs
,
16769 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16770 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16772 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16773 _("shift out of range"));
16774 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16775 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16776 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16777 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16778 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16779 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16780 inst
.instruction
|= neon_quad (rs
) << 6;
16781 inst
.instruction
|= imm
<< 8;
16783 neon_dp_fixup (&inst
);
16789 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16790 struct neon_type_el et
= neon_check_type (2, rs
,
16791 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16792 unsigned op
= (inst
.instruction
>> 7) & 3;
16793 /* N (width of reversed regions) is encoded as part of the bitmask. We
16794 extract it here to check the elements to be reversed are smaller.
16795 Otherwise we'd get a reserved instruction. */
16796 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16797 gas_assert (elsize
!= 0);
16798 constraint (et
.size
>= elsize
,
16799 _("elements must be smaller than reversal region"));
16800 neon_two_same (neon_quad (rs
), 1, et
.size
);
16806 if (inst
.operands
[1].isscalar
)
16808 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16809 struct neon_type_el et
= neon_check_type (2, rs
,
16810 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16811 unsigned sizebits
= et
.size
>> 3;
16812 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16813 int logsize
= neon_logbits (et
.size
);
16814 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16816 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16819 NEON_ENCODE (SCALAR
, inst
);
16820 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16821 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16822 inst
.instruction
|= LOW4 (dm
);
16823 inst
.instruction
|= HI1 (dm
) << 5;
16824 inst
.instruction
|= neon_quad (rs
) << 6;
16825 inst
.instruction
|= x
<< 17;
16826 inst
.instruction
|= sizebits
<< 16;
16828 neon_dp_fixup (&inst
);
16832 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16833 struct neon_type_el et
= neon_check_type (2, rs
,
16834 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16835 /* Duplicate ARM register to lanes of vector. */
16836 NEON_ENCODE (ARMREG
, inst
);
16839 case 8: inst
.instruction
|= 0x400000; break;
16840 case 16: inst
.instruction
|= 0x000020; break;
16841 case 32: inst
.instruction
|= 0x000000; break;
16844 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16845 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16846 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16847 inst
.instruction
|= neon_quad (rs
) << 21;
16848 /* The encoding for this instruction is identical for the ARM and Thumb
16849 variants, except for the condition field. */
16850 do_vfp_cond_or_thumb ();
16854 /* VMOV has particularly many variations. It can be one of:
16855 0. VMOV<c><q> <Qd>, <Qm>
16856 1. VMOV<c><q> <Dd>, <Dm>
16857 (Register operations, which are VORR with Rm = Rn.)
16858 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16859 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16861 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16862 (ARM register to scalar.)
16863 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16864 (Two ARM registers to vector.)
16865 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16866 (Scalar to ARM register.)
16867 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16868 (Vector to two ARM registers.)
16869 8. VMOV.F32 <Sd>, <Sm>
16870 9. VMOV.F64 <Dd>, <Dm>
16871 (VFP register moves.)
16872 10. VMOV.F32 <Sd>, #imm
16873 11. VMOV.F64 <Dd>, #imm
16874 (VFP float immediate load.)
16875 12. VMOV <Rd>, <Sm>
16876 (VFP single to ARM reg.)
16877 13. VMOV <Sd>, <Rm>
16878 (ARM reg to VFP single.)
16879 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16880 (Two ARM regs to two VFP singles.)
16881 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16882 (Two VFP singles to two ARM regs.)
16884 These cases can be disambiguated using neon_select_shape, except cases 1/9
16885 and 3/11 which depend on the operand type too.
16887 All the encoded bits are hardcoded by this function.
16889 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16890 Cases 5, 7 may be used with VFPv2 and above.
16892 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16893 can specify a type where it doesn't make sense to, and is ignored). */
16898 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16899 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16900 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16901 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16902 struct neon_type_el et
;
16903 const char *ldconst
= 0;
16907 case NS_DD
: /* case 1/9. */
16908 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16909 /* It is not an error here if no type is given. */
16911 if (et
.type
== NT_float
&& et
.size
== 64)
16913 do_vfp_nsyn_opcode ("fcpyd");
16916 /* fall through. */
16918 case NS_QQ
: /* case 0/1. */
16920 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16922 /* The architecture manual I have doesn't explicitly state which
16923 value the U bit should have for register->register moves, but
16924 the equivalent VORR instruction has U = 0, so do that. */
16925 inst
.instruction
= 0x0200110;
16926 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16927 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16928 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16929 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16930 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16931 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16932 inst
.instruction
|= neon_quad (rs
) << 6;
16934 neon_dp_fixup (&inst
);
16938 case NS_DI
: /* case 3/11. */
16939 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16941 if (et
.type
== NT_float
&& et
.size
== 64)
16943 /* case 11 (fconstd). */
16944 ldconst
= "fconstd";
16945 goto encode_fconstd
;
16947 /* fall through. */
16949 case NS_QI
: /* case 2/3. */
16950 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16952 inst
.instruction
= 0x0800010;
16953 neon_move_immediate ();
16954 neon_dp_fixup (&inst
);
16957 case NS_SR
: /* case 4. */
16959 unsigned bcdebits
= 0;
16961 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16962 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16964 /* .<size> is optional here, defaulting to .32. */
16965 if (inst
.vectype
.elems
== 0
16966 && inst
.operands
[0].vectype
.type
== NT_invtype
16967 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16969 inst
.vectype
.el
[0].type
= NT_untyped
;
16970 inst
.vectype
.el
[0].size
= 32;
16971 inst
.vectype
.elems
= 1;
16974 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16975 logsize
= neon_logbits (et
.size
);
16977 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16979 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16980 && et
.size
!= 32, _(BAD_FPU
));
16981 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16982 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16986 case 8: bcdebits
= 0x8; break;
16987 case 16: bcdebits
= 0x1; break;
16988 case 32: bcdebits
= 0x0; break;
16992 bcdebits
|= x
<< logsize
;
16994 inst
.instruction
= 0xe000b10;
16995 do_vfp_cond_or_thumb ();
16996 inst
.instruction
|= LOW4 (dn
) << 16;
16997 inst
.instruction
|= HI1 (dn
) << 7;
16998 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16999 inst
.instruction
|= (bcdebits
& 3) << 5;
17000 inst
.instruction
|= (bcdebits
>> 2) << 21;
17004 case NS_DRR
: /* case 5 (fmdrr). */
17005 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
17008 inst
.instruction
= 0xc400b10;
17009 do_vfp_cond_or_thumb ();
17010 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
17011 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
17012 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
17013 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
17016 case NS_RS
: /* case 6. */
17019 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
17020 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
17021 unsigned abcdebits
= 0;
17023 /* .<dt> is optional here, defaulting to .32. */
17024 if (inst
.vectype
.elems
== 0
17025 && inst
.operands
[0].vectype
.type
== NT_invtype
17026 && inst
.operands
[1].vectype
.type
== NT_invtype
)
17028 inst
.vectype
.el
[0].type
= NT_untyped
;
17029 inst
.vectype
.el
[0].size
= 32;
17030 inst
.vectype
.elems
= 1;
17033 et
= neon_check_type (2, NS_NULL
,
17034 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
17035 logsize
= neon_logbits (et
.size
);
17037 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
17039 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
17040 && et
.size
!= 32, _(BAD_FPU
));
17041 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
17042 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
17046 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
17047 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
17048 case 32: abcdebits
= 0x00; break;
17052 abcdebits
|= x
<< logsize
;
17053 inst
.instruction
= 0xe100b10;
17054 do_vfp_cond_or_thumb ();
17055 inst
.instruction
|= LOW4 (dn
) << 16;
17056 inst
.instruction
|= HI1 (dn
) << 7;
17057 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17058 inst
.instruction
|= (abcdebits
& 3) << 5;
17059 inst
.instruction
|= (abcdebits
>> 2) << 21;
17063 case NS_RRD
: /* case 7 (fmrrd). */
17064 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
17067 inst
.instruction
= 0xc500b10;
17068 do_vfp_cond_or_thumb ();
17069 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17070 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17071 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
17072 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
17075 case NS_FF
: /* case 8 (fcpys). */
17076 do_vfp_nsyn_opcode ("fcpys");
17080 case NS_FI
: /* case 10 (fconsts). */
17081 ldconst
= "fconsts";
17083 if (!inst
.operands
[1].immisfloat
)
17086 /* Immediate has to fit in 8 bits so float is enough. */
17087 float imm
= (float) inst
.operands
[1].imm
;
17088 memcpy (&new_imm
, &imm
, sizeof (float));
17089 /* But the assembly may have been written to provide an integer
17090 bit pattern that equates to a float, so check that the
17091 conversion has worked. */
17092 if (is_quarter_float (new_imm
))
17094 if (is_quarter_float (inst
.operands
[1].imm
))
17095 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
17097 inst
.operands
[1].imm
= new_imm
;
17098 inst
.operands
[1].immisfloat
= 1;
17102 if (is_quarter_float (inst
.operands
[1].imm
))
17104 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
17105 do_vfp_nsyn_opcode (ldconst
);
17107 /* ARMv8.2 fp16 vmov.f16 instruction. */
17109 do_scalar_fp16_v82_encode ();
17112 first_error (_("immediate out of range"));
17116 case NS_RF
: /* case 12 (fmrs). */
17117 do_vfp_nsyn_opcode ("fmrs");
17118 /* ARMv8.2 fp16 vmov.f16 instruction. */
17120 do_scalar_fp16_v82_encode ();
17124 case NS_FR
: /* case 13 (fmsr). */
17125 do_vfp_nsyn_opcode ("fmsr");
17126 /* ARMv8.2 fp16 vmov.f16 instruction. */
17128 do_scalar_fp16_v82_encode ();
17131 /* The encoders for the fmrrs and fmsrr instructions expect three operands
17132 (one of which is a list), but we have parsed four. Do some fiddling to
17133 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
17135 case NS_RRFF
: /* case 14 (fmrrs). */
17136 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
17137 _("VFP registers must be adjacent"));
17138 inst
.operands
[2].imm
= 2;
17139 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
17140 do_vfp_nsyn_opcode ("fmrrs");
17143 case NS_FFRR
: /* case 15 (fmsrr). */
17144 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
17145 _("VFP registers must be adjacent"));
17146 inst
.operands
[1] = inst
.operands
[2];
17147 inst
.operands
[2] = inst
.operands
[3];
17148 inst
.operands
[0].imm
= 2;
17149 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
17150 do_vfp_nsyn_opcode ("fmsrr");
17154 /* neon_select_shape has determined that the instruction
17155 shape is wrong and has already set the error message. */
17164 do_neon_rshift_round_imm (void)
17166 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17167 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
17168 int imm
= inst
.operands
[2].imm
;
17170 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
17173 inst
.operands
[2].present
= 0;
17178 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17179 _("immediate out of range for shift"));
17180 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
17185 do_neon_movhf (void)
17187 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
17188 constraint (rs
!= NS_HH
, _("invalid suffix"));
17190 if (inst
.cond
!= COND_ALWAYS
)
17194 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
17195 " the behaviour is UNPREDICTABLE"));
17199 inst
.error
= BAD_COND
;
17204 do_vfp_sp_monadic ();
17207 inst
.instruction
|= 0xf0000000;
17211 do_neon_movl (void)
17213 struct neon_type_el et
= neon_check_type (2, NS_QD
,
17214 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
17215 unsigned sizebits
= et
.size
>> 3;
17216 inst
.instruction
|= sizebits
<< 19;
17217 neon_two_same (0, et
.type
== NT_unsigned
, -1);
17223 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17224 struct neon_type_el et
= neon_check_type (2, rs
,
17225 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17226 NEON_ENCODE (INTEGER
, inst
);
17227 neon_two_same (neon_quad (rs
), 1, et
.size
);
17231 do_neon_zip_uzp (void)
17233 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17234 struct neon_type_el et
= neon_check_type (2, rs
,
17235 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17236 if (rs
== NS_DD
&& et
.size
== 32)
17238 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
17239 inst
.instruction
= N_MNEM_vtrn
;
17243 neon_two_same (neon_quad (rs
), 1, et
.size
);
17247 do_neon_sat_abs_neg (void)
17249 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17250 struct neon_type_el et
= neon_check_type (2, rs
,
17251 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17252 neon_two_same (neon_quad (rs
), 1, et
.size
);
17256 do_neon_pair_long (void)
17258 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17259 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17260 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
17261 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
17262 neon_two_same (neon_quad (rs
), 1, et
.size
);
17266 do_neon_recip_est (void)
17268 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17269 struct neon_type_el et
= neon_check_type (2, rs
,
17270 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
17271 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17272 neon_two_same (neon_quad (rs
), 1, et
.size
);
17278 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17279 struct neon_type_el et
= neon_check_type (2, rs
,
17280 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17281 neon_two_same (neon_quad (rs
), 1, et
.size
);
17287 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17288 struct neon_type_el et
= neon_check_type (2, rs
,
17289 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
17290 neon_two_same (neon_quad (rs
), 1, et
.size
);
17296 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17297 struct neon_type_el et
= neon_check_type (2, rs
,
17298 N_EQK
| N_INT
, N_8
| N_KEY
);
17299 neon_two_same (neon_quad (rs
), 1, et
.size
);
17305 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17306 neon_two_same (neon_quad (rs
), 1, -1);
17310 do_neon_tbl_tbx (void)
17312 unsigned listlenbits
;
17313 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
17315 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
17317 first_error (_("bad list length for table lookup"));
17321 listlenbits
= inst
.operands
[1].imm
- 1;
17322 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17323 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17324 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17325 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17326 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
17327 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
17328 inst
.instruction
|= listlenbits
<< 8;
17330 neon_dp_fixup (&inst
);
17334 do_neon_ldm_stm (void)
17336 /* P, U and L bits are part of bitmask. */
17337 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
17338 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
17340 if (inst
.operands
[1].issingle
)
17342 do_vfp_nsyn_ldm_stm (is_dbmode
);
17346 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
17347 _("writeback (!) must be used for VLDMDB and VSTMDB"));
17349 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
17350 _("register list must contain at least 1 and at most 16 "
17353 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
17354 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
17355 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
17356 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
17358 inst
.instruction
|= offsetbits
;
17360 do_vfp_cond_or_thumb ();
17364 do_neon_ldr_str (void)
17366 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
17368 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
17369 And is UNPREDICTABLE in thumb mode. */
17371 && inst
.operands
[1].reg
== REG_PC
17372 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
17375 inst
.error
= _("Use of PC here is UNPREDICTABLE");
17376 else if (warn_on_deprecated
)
17377 as_tsktsk (_("Use of PC here is deprecated"));
17380 if (inst
.operands
[0].issingle
)
17383 do_vfp_nsyn_opcode ("flds");
17385 do_vfp_nsyn_opcode ("fsts");
17387 /* ARMv8.2 vldr.16/vstr.16 instruction. */
17388 if (inst
.vectype
.el
[0].size
== 16)
17389 do_scalar_fp16_v82_encode ();
17394 do_vfp_nsyn_opcode ("fldd");
17396 do_vfp_nsyn_opcode ("fstd");
17400 /* "interleave" version also handles non-interleaving register VLD1/VST1
17404 do_neon_ld_st_interleave (void)
17406 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
17407 N_8
| N_16
| N_32
| N_64
);
17408 unsigned alignbits
= 0;
17410 /* The bits in this table go:
17411 0: register stride of one (0) or two (1)
17412 1,2: register list length, minus one (1, 2, 3, 4).
17413 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
17414 We use -1 for invalid entries. */
17415 const int typetable
[] =
17417 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
17418 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
17419 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
17420 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
17424 if (et
.type
== NT_invtype
)
17427 if (inst
.operands
[1].immisalign
)
17428 switch (inst
.operands
[1].imm
>> 8)
17430 case 64: alignbits
= 1; break;
17432 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
17433 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17434 goto bad_alignment
;
17438 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17439 goto bad_alignment
;
17444 first_error (_("bad alignment"));
17448 inst
.instruction
|= alignbits
<< 4;
17449 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17451 /* Bits [4:6] of the immediate in a list specifier encode register stride
17452 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17453 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17454 up the right value for "type" in a table based on this value and the given
17455 list style, then stick it back. */
17456 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
17457 | (((inst
.instruction
>> 8) & 3) << 3);
17459 typebits
= typetable
[idx
];
17461 constraint (typebits
== -1, _("bad list type for instruction"));
17462 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
17463 _("bad element type for instruction"));
17465 inst
.instruction
&= ~0xf00;
17466 inst
.instruction
|= typebits
<< 8;
17469 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17470 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17471 otherwise. The variable arguments are a list of pairs of legal (size, align)
17472 values, terminated with -1. */
17475 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
17478 int result
= FAIL
, thissize
, thisalign
;
17480 if (!inst
.operands
[1].immisalign
)
17486 va_start (ap
, do_alignment
);
17490 thissize
= va_arg (ap
, int);
17491 if (thissize
== -1)
17493 thisalign
= va_arg (ap
, int);
17495 if (size
== thissize
&& align
== thisalign
)
17498 while (result
!= SUCCESS
);
17502 if (result
== SUCCESS
)
17505 first_error (_("unsupported alignment for instruction"));
17511 do_neon_ld_st_lane (void)
17513 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17514 int align_good
, do_alignment
= 0;
17515 int logsize
= neon_logbits (et
.size
);
17516 int align
= inst
.operands
[1].imm
>> 8;
17517 int n
= (inst
.instruction
>> 8) & 3;
17518 int max_el
= 64 / et
.size
;
17520 if (et
.type
== NT_invtype
)
17523 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
17524 _("bad list length"));
17525 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
17526 _("scalar index out of range"));
17527 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
17529 _("stride of 2 unavailable when element size is 8"));
17533 case 0: /* VLD1 / VST1. */
17534 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
17536 if (align_good
== FAIL
)
17540 unsigned alignbits
= 0;
17543 case 16: alignbits
= 0x1; break;
17544 case 32: alignbits
= 0x3; break;
17547 inst
.instruction
|= alignbits
<< 4;
17551 case 1: /* VLD2 / VST2. */
17552 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
17553 16, 32, 32, 64, -1);
17554 if (align_good
== FAIL
)
17557 inst
.instruction
|= 1 << 4;
17560 case 2: /* VLD3 / VST3. */
17561 constraint (inst
.operands
[1].immisalign
,
17562 _("can't use alignment with this instruction"));
17565 case 3: /* VLD4 / VST4. */
17566 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17567 16, 64, 32, 64, 32, 128, -1);
17568 if (align_good
== FAIL
)
17572 unsigned alignbits
= 0;
17575 case 8: alignbits
= 0x1; break;
17576 case 16: alignbits
= 0x1; break;
17577 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
17580 inst
.instruction
|= alignbits
<< 4;
17587 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17588 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17589 inst
.instruction
|= 1 << (4 + logsize
);
17591 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
17592 inst
.instruction
|= logsize
<< 10;
17595 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17598 do_neon_ld_dup (void)
17600 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17601 int align_good
, do_alignment
= 0;
17603 if (et
.type
== NT_invtype
)
17606 switch ((inst
.instruction
>> 8) & 3)
17608 case 0: /* VLD1. */
17609 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17610 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17611 &do_alignment
, 16, 16, 32, 32, -1);
17612 if (align_good
== FAIL
)
17614 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17617 case 2: inst
.instruction
|= 1 << 5; break;
17618 default: first_error (_("bad list length")); return;
17620 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17623 case 1: /* VLD2. */
17624 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17625 &do_alignment
, 8, 16, 16, 32, 32, 64,
17627 if (align_good
== FAIL
)
17629 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17630 _("bad list length"));
17631 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17632 inst
.instruction
|= 1 << 5;
17633 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17636 case 2: /* VLD3. */
17637 constraint (inst
.operands
[1].immisalign
,
17638 _("can't use alignment with this instruction"));
17639 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17640 _("bad list length"));
17641 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17642 inst
.instruction
|= 1 << 5;
17643 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17646 case 3: /* VLD4. */
17648 int align
= inst
.operands
[1].imm
>> 8;
17649 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17650 16, 64, 32, 64, 32, 128, -1);
17651 if (align_good
== FAIL
)
17653 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17654 _("bad list length"));
17655 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17656 inst
.instruction
|= 1 << 5;
17657 if (et
.size
== 32 && align
== 128)
17658 inst
.instruction
|= 0x3 << 6;
17660 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17667 inst
.instruction
|= do_alignment
<< 4;
17670 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17671 apart from bits [11:4]. */
17674 do_neon_ldx_stx (void)
17676 if (inst
.operands
[1].isreg
)
17677 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17679 switch (NEON_LANE (inst
.operands
[0].imm
))
17681 case NEON_INTERLEAVE_LANES
:
17682 NEON_ENCODE (INTERLV
, inst
);
17683 do_neon_ld_st_interleave ();
17686 case NEON_ALL_LANES
:
17687 NEON_ENCODE (DUP
, inst
);
17688 if (inst
.instruction
== N_INV
)
17690 first_error ("only loads support such operands");
17697 NEON_ENCODE (LANE
, inst
);
17698 do_neon_ld_st_lane ();
17701 /* L bit comes from bit mask. */
17702 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17703 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17704 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17706 if (inst
.operands
[1].postind
)
17708 int postreg
= inst
.operands
[1].imm
& 0xf;
17709 constraint (!inst
.operands
[1].immisreg
,
17710 _("post-index must be a register"));
17711 constraint (postreg
== 0xd || postreg
== 0xf,
17712 _("bad register for post-index"));
17713 inst
.instruction
|= postreg
;
17717 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17718 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
17719 || inst
.relocs
[0].exp
.X_add_number
!= 0,
17722 if (inst
.operands
[1].writeback
)
17724 inst
.instruction
|= 0xd;
17727 inst
.instruction
|= 0xf;
17731 inst
.instruction
|= 0xf9000000;
17733 inst
.instruction
|= 0xf4000000;
17738 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17740 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17741 D register operands. */
17742 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17743 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17746 NEON_ENCODE (FPV8
, inst
);
17748 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17750 do_vfp_sp_dyadic ();
17752 /* ARMv8.2 fp16 instruction. */
17754 do_scalar_fp16_v82_encode ();
17757 do_vfp_dp_rd_rn_rm ();
17760 inst
.instruction
|= 0x100;
17762 inst
.instruction
|= 0xf0000000;
17768 set_it_insn_type (OUTSIDE_IT_INSN
);
17770 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17771 first_error (_("invalid instruction shape"));
17777 set_it_insn_type (OUTSIDE_IT_INSN
);
17779 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17782 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17785 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17789 do_vrint_1 (enum neon_cvt_mode mode
)
17791 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17792 struct neon_type_el et
;
17797 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17798 D register operands. */
17799 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17800 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17803 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17805 if (et
.type
!= NT_invtype
)
17807 /* VFP encodings. */
17808 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17809 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17810 set_it_insn_type (OUTSIDE_IT_INSN
);
17812 NEON_ENCODE (FPV8
, inst
);
17813 if (rs
== NS_FF
|| rs
== NS_HH
)
17814 do_vfp_sp_monadic ();
17816 do_vfp_dp_rd_rm ();
17820 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17821 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17822 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17823 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17824 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17825 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17826 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17830 inst
.instruction
|= (rs
== NS_DD
) << 8;
17831 do_vfp_cond_or_thumb ();
17833 /* ARMv8.2 fp16 vrint instruction. */
17835 do_scalar_fp16_v82_encode ();
17839 /* Neon encodings (or something broken...). */
17841 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17843 if (et
.type
== NT_invtype
)
17846 set_it_insn_type (OUTSIDE_IT_INSN
);
17847 NEON_ENCODE (FLOAT
, inst
);
17849 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17852 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17853 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17854 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17855 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17856 inst
.instruction
|= neon_quad (rs
) << 6;
17857 /* Mask off the original size bits and reencode them. */
17858 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17859 | neon_logbits (et
.size
) << 18);
17863 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17864 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17865 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17866 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17867 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17868 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17869 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17874 inst
.instruction
|= 0xfc000000;
17876 inst
.instruction
|= 0xf0000000;
17883 do_vrint_1 (neon_cvt_mode_x
);
17889 do_vrint_1 (neon_cvt_mode_z
);
17895 do_vrint_1 (neon_cvt_mode_r
);
17901 do_vrint_1 (neon_cvt_mode_a
);
17907 do_vrint_1 (neon_cvt_mode_n
);
17913 do_vrint_1 (neon_cvt_mode_p
);
17919 do_vrint_1 (neon_cvt_mode_m
);
17923 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17925 unsigned regno
= NEON_SCALAR_REG (opnd
);
17926 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17928 if (elsize
== 16 && elno
< 2 && regno
< 16)
17929 return regno
| (elno
<< 4);
17930 else if (elsize
== 32 && elno
== 0)
17933 first_error (_("scalar out of range"));
17940 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17942 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
17943 _("expression too complex"));
17944 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17945 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17946 _("immediate out of range"));
17948 if (inst
.operands
[2].isscalar
)
17950 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17951 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17952 N_KEY
| N_F16
| N_F32
).size
;
17953 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17955 inst
.instruction
= 0xfe000800;
17956 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17957 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17958 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17959 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17960 inst
.instruction
|= LOW4 (m
);
17961 inst
.instruction
|= HI1 (m
) << 5;
17962 inst
.instruction
|= neon_quad (rs
) << 6;
17963 inst
.instruction
|= rot
<< 20;
17964 inst
.instruction
|= (size
== 32) << 23;
17968 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17969 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17970 N_KEY
| N_F16
| N_F32
).size
;
17971 neon_three_same (neon_quad (rs
), 0, -1);
17972 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17973 inst
.instruction
|= 0xfc200800;
17974 inst
.instruction
|= rot
<< 23;
17975 inst
.instruction
|= (size
== 32) << 20;
17982 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17984 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
17985 _("expression too complex"));
17986 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17987 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17988 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17989 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17990 N_KEY
| N_F16
| N_F32
).size
;
17991 neon_three_same (neon_quad (rs
), 0, -1);
17992 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17993 inst
.instruction
|= 0xfc800800;
17994 inst
.instruction
|= (rot
== 270) << 24;
17995 inst
.instruction
|= (size
== 32) << 20;
17998 /* Dot Product instructions encoding support. */
18001 do_neon_dotproduct (int unsigned_p
)
18003 enum neon_shape rs
;
18004 unsigned scalar_oprd2
= 0;
18007 if (inst
.cond
!= COND_ALWAYS
)
18008 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
18009 "is UNPREDICTABLE"));
18011 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
18014 /* Dot Product instructions are in three-same D/Q register format or the third
18015 operand can be a scalar index register. */
18016 if (inst
.operands
[2].isscalar
)
18018 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
18019 high8
= 0xfe000000;
18020 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18024 high8
= 0xfc000000;
18025 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18029 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
18031 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
18033 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
18034 Product instruction, so we pass 0 as the "ubit" parameter. And the
18035 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
18036 neon_three_same (neon_quad (rs
), 0, 32);
18038 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
18039 different NEON three-same encoding. */
18040 inst
.instruction
&= 0x00ffffff;
18041 inst
.instruction
|= high8
;
18042 /* Encode 'U' bit which indicates signedness. */
18043 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
18044 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
18045 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
18046 the instruction encoding. */
18047 if (inst
.operands
[2].isscalar
)
18049 inst
.instruction
&= 0xffffffd0;
18050 inst
.instruction
|= LOW4 (scalar_oprd2
);
18051 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
18055 /* Dot Product instructions for signed integer. */
18058 do_neon_dotproduct_s (void)
18060 return do_neon_dotproduct (0);
18063 /* Dot Product instructions for unsigned integer. */
18066 do_neon_dotproduct_u (void)
18068 return do_neon_dotproduct (1);
18071 /* Crypto v1 instructions. */
18073 do_crypto_2op_1 (unsigned elttype
, int op
)
18075 set_it_insn_type (OUTSIDE_IT_INSN
);
18077 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
18083 NEON_ENCODE (INTEGER
, inst
);
18084 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18085 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18086 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18087 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18089 inst
.instruction
|= op
<< 6;
18092 inst
.instruction
|= 0xfc000000;
18094 inst
.instruction
|= 0xf0000000;
18098 do_crypto_3op_1 (int u
, int op
)
18100 set_it_insn_type (OUTSIDE_IT_INSN
);
18102 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
18103 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
18108 NEON_ENCODE (INTEGER
, inst
);
18109 neon_three_same (1, u
, 8 << op
);
18115 do_crypto_2op_1 (N_8
, 0);
18121 do_crypto_2op_1 (N_8
, 1);
18127 do_crypto_2op_1 (N_8
, 2);
18133 do_crypto_2op_1 (N_8
, 3);
18139 do_crypto_3op_1 (0, 0);
18145 do_crypto_3op_1 (0, 1);
18151 do_crypto_3op_1 (0, 2);
18157 do_crypto_3op_1 (0, 3);
18163 do_crypto_3op_1 (1, 0);
18169 do_crypto_3op_1 (1, 1);
18173 do_sha256su1 (void)
18175 do_crypto_3op_1 (1, 2);
18181 do_crypto_2op_1 (N_32
, -1);
18187 do_crypto_2op_1 (N_32
, 0);
18191 do_sha256su0 (void)
18193 do_crypto_2op_1 (N_32
, 1);
18197 do_crc32_1 (unsigned int poly
, unsigned int sz
)
18199 unsigned int Rd
= inst
.operands
[0].reg
;
18200 unsigned int Rn
= inst
.operands
[1].reg
;
18201 unsigned int Rm
= inst
.operands
[2].reg
;
18203 set_it_insn_type (OUTSIDE_IT_INSN
);
18204 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
18205 inst
.instruction
|= LOW4 (Rn
) << 16;
18206 inst
.instruction
|= LOW4 (Rm
);
18207 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
18208 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
18210 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
18211 as_warn (UNPRED_REG ("r15"));
18253 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18255 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
18256 do_vfp_sp_dp_cvt ();
18257 do_vfp_cond_or_thumb ();
18261 /* Overall per-instruction processing. */
18263 /* We need to be able to fix up arbitrary expressions in some statements.
18264 This is so that we can handle symbols that are an arbitrary distance from
18265 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
18266 which returns part of an address in a form which will be valid for
18267 a data instruction. We do this by pushing the expression into a symbol
18268 in the expr_section, and creating a fix for that. */
18271 fix_new_arm (fragS
* frag
,
18285 /* Create an absolute valued symbol, so we have something to
18286 refer to in the object file. Unfortunately for us, gas's
18287 generic expression parsing will already have folded out
18288 any use of .set foo/.type foo %function that may have
18289 been used to set type information of the target location,
18290 that's being specified symbolically. We have to presume
18291 the user knows what they are doing. */
18295 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
18297 symbol
= symbol_find_or_make (name
);
18298 S_SET_SEGMENT (symbol
, absolute_section
);
18299 symbol_set_frag (symbol
, &zero_address_frag
);
18300 S_SET_VALUE (symbol
, exp
->X_add_number
);
18301 exp
->X_op
= O_symbol
;
18302 exp
->X_add_symbol
= symbol
;
18303 exp
->X_add_number
= 0;
18309 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
18310 (enum bfd_reloc_code_real
) reloc
);
18314 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
18315 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
18319 /* Mark whether the fix is to a THUMB instruction, or an ARM
18321 new_fix
->tc_fix_data
= thumb_mode
;
18324 /* Create a frg for an instruction requiring relaxation. */
18326 output_relax_insn (void)
18332 /* The size of the instruction is unknown, so tie the debug info to the
18333 start of the instruction. */
18334 dwarf2_emit_insn (0);
18336 switch (inst
.relocs
[0].exp
.X_op
)
18339 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
18340 offset
= inst
.relocs
[0].exp
.X_add_number
;
18344 offset
= inst
.relocs
[0].exp
.X_add_number
;
18347 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
18351 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
18352 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
18353 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
18356 /* Write a 32-bit thumb instruction to buf. */
18358 put_thumb32_insn (char * buf
, unsigned long insn
)
18360 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
18361 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
18365 output_inst (const char * str
)
18371 as_bad ("%s -- `%s'", inst
.error
, str
);
18376 output_relax_insn ();
18379 if (inst
.size
== 0)
18382 to
= frag_more (inst
.size
);
18383 /* PR 9814: Record the thumb mode into the current frag so that we know
18384 what type of NOP padding to use, if necessary. We override any previous
18385 setting so that if the mode has changed then the NOPS that we use will
18386 match the encoding of the last instruction in the frag. */
18387 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18389 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
18391 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
18392 put_thumb32_insn (to
, inst
.instruction
);
18394 else if (inst
.size
> INSN_SIZE
)
18396 gas_assert (inst
.size
== (2 * INSN_SIZE
));
18397 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
18398 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
18401 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
18404 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
18406 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
18407 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
18408 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
18409 inst
.relocs
[r
].type
);
18412 dwarf2_emit_insn (inst
.size
);
18416 output_it_inst (int cond
, int mask
, char * to
)
18418 unsigned long instruction
= 0xbf00;
18421 instruction
|= mask
;
18422 instruction
|= cond
<< 4;
18426 to
= frag_more (2);
18428 dwarf2_emit_insn (2);
18432 md_number_to_chars (to
, instruction
, 2);
18437 /* Tag values used in struct asm_opcode's tag field. */
18440 OT_unconditional
, /* Instruction cannot be conditionalized.
18441 The ARM condition field is still 0xE. */
18442 OT_unconditionalF
, /* Instruction cannot be conditionalized
18443 and carries 0xF in its ARM condition field. */
18444 OT_csuffix
, /* Instruction takes a conditional suffix. */
18445 OT_csuffixF
, /* Some forms of the instruction take a conditional
18446 suffix, others place 0xF where the condition field
18448 OT_cinfix3
, /* Instruction takes a conditional infix,
18449 beginning at character index 3. (In
18450 unified mode, it becomes a suffix.) */
18451 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
18452 tsts, cmps, cmns, and teqs. */
18453 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
18454 character index 3, even in unified mode. Used for
18455 legacy instructions where suffix and infix forms
18456 may be ambiguous. */
18457 OT_csuf_or_in3
, /* Instruction takes either a conditional
18458 suffix or an infix at character index 3. */
18459 OT_odd_infix_unc
, /* This is the unconditional variant of an
18460 instruction that takes a conditional infix
18461 at an unusual position. In unified mode,
18462 this variant will accept a suffix. */
18463 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
18464 are the conditional variants of instructions that
18465 take conditional infixes in unusual positions.
18466 The infix appears at character index
18467 (tag - OT_odd_infix_0). These are not accepted
18468 in unified mode. */
18471 /* Subroutine of md_assemble, responsible for looking up the primary
18472 opcode from the mnemonic the user wrote. STR points to the
18473 beginning of the mnemonic.
18475 This is not simply a hash table lookup, because of conditional
18476 variants. Most instructions have conditional variants, which are
18477 expressed with a _conditional affix_ to the mnemonic. If we were
18478 to encode each conditional variant as a literal string in the opcode
18479 table, it would have approximately 20,000 entries.
18481 Most mnemonics take this affix as a suffix, and in unified syntax,
18482 'most' is upgraded to 'all'. However, in the divided syntax, some
18483 instructions take the affix as an infix, notably the s-variants of
18484 the arithmetic instructions. Of those instructions, all but six
18485 have the infix appear after the third character of the mnemonic.
18487 Accordingly, the algorithm for looking up primary opcodes given
18490 1. Look up the identifier in the opcode table.
18491 If we find a match, go to step U.
18493 2. Look up the last two characters of the identifier in the
18494 conditions table. If we find a match, look up the first N-2
18495 characters of the identifier in the opcode table. If we
18496 find a match, go to step CE.
18498 3. Look up the fourth and fifth characters of the identifier in
18499 the conditions table. If we find a match, extract those
18500 characters from the identifier, and look up the remaining
18501 characters in the opcode table. If we find a match, go
18506 U. Examine the tag field of the opcode structure, in case this is
18507 one of the six instructions with its conditional infix in an
18508 unusual place. If it is, the tag tells us where to find the
18509 infix; look it up in the conditions table and set inst.cond
18510 accordingly. Otherwise, this is an unconditional instruction.
18511 Again set inst.cond accordingly. Return the opcode structure.
18513 CE. Examine the tag field to make sure this is an instruction that
18514 should receive a conditional suffix. If it is not, fail.
18515 Otherwise, set inst.cond from the suffix we already looked up,
18516 and return the opcode structure.
18518 CM. Examine the tag field to make sure this is an instruction that
18519 should receive a conditional infix after the third character.
18520 If it is not, fail. Otherwise, undo the edits to the current
18521 line of input and proceed as for case CE. */
18523 static const struct asm_opcode
*
18524 opcode_lookup (char **str
)
18528 const struct asm_opcode
*opcode
;
18529 const struct asm_cond
*cond
;
18532 /* Scan up to the end of the mnemonic, which must end in white space,
18533 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18534 for (base
= end
= *str
; *end
!= '\0'; end
++)
18535 if (*end
== ' ' || *end
== '.')
18541 /* Handle a possible width suffix and/or Neon type suffix. */
18546 /* The .w and .n suffixes are only valid if the unified syntax is in
18548 if (unified_syntax
&& end
[1] == 'w')
18550 else if (unified_syntax
&& end
[1] == 'n')
18555 inst
.vectype
.elems
= 0;
18557 *str
= end
+ offset
;
18559 if (end
[offset
] == '.')
18561 /* See if we have a Neon type suffix (possible in either unified or
18562 non-unified ARM syntax mode). */
18563 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
18566 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
18572 /* Look for unaffixed or special-case affixed mnemonic. */
18573 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18578 if (opcode
->tag
< OT_odd_infix_0
)
18580 inst
.cond
= COND_ALWAYS
;
18584 if (warn_on_deprecated
&& unified_syntax
)
18585 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18586 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
18587 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18590 inst
.cond
= cond
->value
;
18594 /* Cannot have a conditional suffix on a mnemonic of less than two
18596 if (end
- base
< 3)
18599 /* Look for suffixed mnemonic. */
18601 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18602 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18604 if (opcode
&& cond
)
18607 switch (opcode
->tag
)
18609 case OT_cinfix3_legacy
:
18610 /* Ignore conditional suffixes matched on infix only mnemonics. */
18614 case OT_cinfix3_deprecated
:
18615 case OT_odd_infix_unc
:
18616 if (!unified_syntax
)
18618 /* Fall through. */
18622 case OT_csuf_or_in3
:
18623 inst
.cond
= cond
->value
;
18626 case OT_unconditional
:
18627 case OT_unconditionalF
:
18629 inst
.cond
= cond
->value
;
18632 /* Delayed diagnostic. */
18633 inst
.error
= BAD_COND
;
18634 inst
.cond
= COND_ALWAYS
;
18643 /* Cannot have a usual-position infix on a mnemonic of less than
18644 six characters (five would be a suffix). */
18645 if (end
- base
< 6)
18648 /* Look for infixed mnemonic in the usual position. */
18650 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18654 memcpy (save
, affix
, 2);
18655 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18656 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18658 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18659 memcpy (affix
, save
, 2);
18662 && (opcode
->tag
== OT_cinfix3
18663 || opcode
->tag
== OT_cinfix3_deprecated
18664 || opcode
->tag
== OT_csuf_or_in3
18665 || opcode
->tag
== OT_cinfix3_legacy
))
18668 if (warn_on_deprecated
&& unified_syntax
18669 && (opcode
->tag
== OT_cinfix3
18670 || opcode
->tag
== OT_cinfix3_deprecated
))
18671 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18673 inst
.cond
= cond
->value
;
18680 /* This function generates an initial IT instruction, leaving its block
18681 virtually open for the new instructions. Eventually,
18682 the mask will be updated by now_it_add_mask () each time
18683 a new instruction needs to be included in the IT block.
18684 Finally, the block is closed with close_automatic_it_block ().
18685 The block closure can be requested either from md_assemble (),
18686 a tencode (), or due to a label hook. */
18689 new_automatic_it_block (int cond
)
18691 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18692 now_it
.mask
= 0x18;
18694 now_it
.block_length
= 1;
18695 mapping_state (MAP_THUMB
);
18696 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18697 now_it
.warn_deprecated
= FALSE
;
18698 now_it
.insn_cond
= TRUE
;
18701 /* Close an automatic IT block.
18702 See comments in new_automatic_it_block (). */
18705 close_automatic_it_block (void)
18707 now_it
.mask
= 0x10;
18708 now_it
.block_length
= 0;
18711 /* Update the mask of the current automatically-generated IT
18712 instruction. See comments in new_automatic_it_block (). */
18715 now_it_add_mask (int cond
)
18717 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18718 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18719 | ((bitvalue) << (nbit)))
18720 const int resulting_bit
= (cond
& 1);
18722 now_it
.mask
&= 0xf;
18723 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18725 (5 - now_it
.block_length
));
18726 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18728 ((5 - now_it
.block_length
) - 1) );
18729 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18732 #undef SET_BIT_VALUE
18735 /* The IT blocks handling machinery is accessed through the these functions:
18736 it_fsm_pre_encode () from md_assemble ()
18737 set_it_insn_type () optional, from the tencode functions
18738 set_it_insn_type_last () ditto
18739 in_it_block () ditto
18740 it_fsm_post_encode () from md_assemble ()
18741 force_automatic_it_block_close () from label handling functions
18744 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18745 initializing the IT insn type with a generic initial value depending
18746 on the inst.condition.
18747 2) During the tencode function, two things may happen:
18748 a) The tencode function overrides the IT insn type by
18749 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18750 b) The tencode function queries the IT block state by
18751 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18753 Both set_it_insn_type and in_it_block run the internal FSM state
18754 handling function (handle_it_state), because: a) setting the IT insn
18755 type may incur in an invalid state (exiting the function),
18756 and b) querying the state requires the FSM to be updated.
18757 Specifically we want to avoid creating an IT block for conditional
18758 branches, so it_fsm_pre_encode is actually a guess and we can't
18759 determine whether an IT block is required until the tencode () routine
18760 has decided what type of instruction this actually it.
18761 Because of this, if set_it_insn_type and in_it_block have to be used,
18762 set_it_insn_type has to be called first.
18764 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18765 determines the insn IT type depending on the inst.cond code.
18766 When a tencode () routine encodes an instruction that can be
18767 either outside an IT block, or, in the case of being inside, has to be
18768 the last one, set_it_insn_type_last () will determine the proper
18769 IT instruction type based on the inst.cond code. Otherwise,
18770 set_it_insn_type can be called for overriding that logic or
18771 for covering other cases.
18773 Calling handle_it_state () may not transition the IT block state to
18774 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18775 still queried. Instead, if the FSM determines that the state should
18776 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18777 after the tencode () function: that's what it_fsm_post_encode () does.
18779 Since in_it_block () calls the state handling function to get an
18780 updated state, an error may occur (due to invalid insns combination).
18781 In that case, inst.error is set.
18782 Therefore, inst.error has to be checked after the execution of
18783 the tencode () routine.
18785 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18786 any pending state change (if any) that didn't take place in
18787 handle_it_state () as explained above. */
18790 it_fsm_pre_encode (void)
18792 if (inst
.cond
!= COND_ALWAYS
)
18793 inst
.it_insn_type
= INSIDE_IT_INSN
;
18795 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18797 now_it
.state_handled
= 0;
18800 /* IT state FSM handling function. */
18803 handle_it_state (void)
18805 now_it
.state_handled
= 1;
18806 now_it
.insn_cond
= FALSE
;
18808 switch (now_it
.state
)
18810 case OUTSIDE_IT_BLOCK
:
18811 switch (inst
.it_insn_type
)
18813 case OUTSIDE_IT_INSN
:
18816 case INSIDE_IT_INSN
:
18817 case INSIDE_IT_LAST_INSN
:
18818 if (thumb_mode
== 0)
18821 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18822 as_tsktsk (_("Warning: conditional outside an IT block"\
18827 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18828 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18830 /* Automatically generate the IT instruction. */
18831 new_automatic_it_block (inst
.cond
);
18832 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18833 close_automatic_it_block ();
18837 inst
.error
= BAD_OUT_IT
;
18843 case IF_INSIDE_IT_LAST_INSN
:
18844 case NEUTRAL_IT_INSN
:
18848 now_it
.state
= MANUAL_IT_BLOCK
;
18849 now_it
.block_length
= 0;
18854 case AUTOMATIC_IT_BLOCK
:
18855 /* Three things may happen now:
18856 a) We should increment current it block size;
18857 b) We should close current it block (closing insn or 4 insns);
18858 c) We should close current it block and start a new one (due
18859 to incompatible conditions or
18860 4 insns-length block reached). */
18862 switch (inst
.it_insn_type
)
18864 case OUTSIDE_IT_INSN
:
18865 /* The closure of the block shall happen immediately,
18866 so any in_it_block () call reports the block as closed. */
18867 force_automatic_it_block_close ();
18870 case INSIDE_IT_INSN
:
18871 case INSIDE_IT_LAST_INSN
:
18872 case IF_INSIDE_IT_LAST_INSN
:
18873 now_it
.block_length
++;
18875 if (now_it
.block_length
> 4
18876 || !now_it_compatible (inst
.cond
))
18878 force_automatic_it_block_close ();
18879 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18880 new_automatic_it_block (inst
.cond
);
18884 now_it
.insn_cond
= TRUE
;
18885 now_it_add_mask (inst
.cond
);
18888 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18889 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18890 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18891 close_automatic_it_block ();
18894 case NEUTRAL_IT_INSN
:
18895 now_it
.block_length
++;
18896 now_it
.insn_cond
= TRUE
;
18898 if (now_it
.block_length
> 4)
18899 force_automatic_it_block_close ();
18901 now_it_add_mask (now_it
.cc
& 1);
18905 close_automatic_it_block ();
18906 now_it
.state
= MANUAL_IT_BLOCK
;
18911 case MANUAL_IT_BLOCK
:
18913 /* Check conditional suffixes. */
18914 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18917 now_it
.mask
&= 0x1f;
18918 is_last
= (now_it
.mask
== 0x10);
18919 now_it
.insn_cond
= TRUE
;
18921 switch (inst
.it_insn_type
)
18923 case OUTSIDE_IT_INSN
:
18924 inst
.error
= BAD_NOT_IT
;
18927 case INSIDE_IT_INSN
:
18928 if (cond
!= inst
.cond
)
18930 inst
.error
= BAD_IT_COND
;
18935 case INSIDE_IT_LAST_INSN
:
18936 case IF_INSIDE_IT_LAST_INSN
:
18937 if (cond
!= inst
.cond
)
18939 inst
.error
= BAD_IT_COND
;
18944 inst
.error
= BAD_BRANCH
;
18949 case NEUTRAL_IT_INSN
:
18950 /* The BKPT instruction is unconditional even in an IT block. */
18954 inst
.error
= BAD_IT_IT
;
18964 struct depr_insn_mask
18966 unsigned long pattern
;
18967 unsigned long mask
;
18968 const char* description
;
18971 /* List of 16-bit instruction patterns deprecated in an IT block in
18973 static const struct depr_insn_mask depr_it_insns
[] = {
18974 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18975 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18976 { 0xa000, 0xb800, N_("ADR") },
18977 { 0x4800, 0xf800, N_("Literal loads") },
18978 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18979 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18980 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18981 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18982 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18987 it_fsm_post_encode (void)
18991 if (!now_it
.state_handled
)
18992 handle_it_state ();
18994 if (now_it
.insn_cond
18995 && !now_it
.warn_deprecated
18996 && warn_on_deprecated
18997 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
18998 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
19000 if (inst
.instruction
>= 0x10000)
19002 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
19003 "performance deprecated in ARMv8-A and ARMv8-R"));
19004 now_it
.warn_deprecated
= TRUE
;
19008 const struct depr_insn_mask
*p
= depr_it_insns
;
19010 while (p
->mask
!= 0)
19012 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
19014 as_tsktsk (_("IT blocks containing 16-bit Thumb "
19015 "instructions of the following class are "
19016 "performance deprecated in ARMv8-A and "
19017 "ARMv8-R: %s"), p
->description
);
19018 now_it
.warn_deprecated
= TRUE
;
19026 if (now_it
.block_length
> 1)
19028 as_tsktsk (_("IT blocks containing more than one conditional "
19029 "instruction are performance deprecated in ARMv8-A and "
19031 now_it
.warn_deprecated
= TRUE
;
19035 is_last
= (now_it
.mask
== 0x10);
19038 now_it
.state
= OUTSIDE_IT_BLOCK
;
19044 force_automatic_it_block_close (void)
19046 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
19048 close_automatic_it_block ();
19049 now_it
.state
= OUTSIDE_IT_BLOCK
;
19057 if (!now_it
.state_handled
)
19058 handle_it_state ();
19060 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
19063 /* Whether OPCODE only has T32 encoding. Since this function is only used by
19064 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
19065 here, hence the "known" in the function name. */
19068 known_t32_only_insn (const struct asm_opcode
*opcode
)
19070 /* Original Thumb-1 wide instruction. */
19071 if (opcode
->tencode
== do_t_blx
19072 || opcode
->tencode
== do_t_branch23
19073 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
19074 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
19077 /* Wide-only instruction added to ARMv8-M Baseline. */
19078 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
19079 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
19080 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
19081 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
19087 /* Whether wide instruction variant can be used if available for a valid OPCODE
19091 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
19093 if (known_t32_only_insn (opcode
))
19096 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
19097 of variant T3 of B.W is checked in do_t_branch. */
19098 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
19099 && opcode
->tencode
== do_t_branch
)
19102 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
19103 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
19104 && opcode
->tencode
== do_t_mov_cmp
19105 /* Make sure CMP instruction is not affected. */
19106 && opcode
->aencode
== do_mov
)
19109 /* Wide instruction variants of all instructions with narrow *and* wide
19110 variants become available with ARMv6t2. Other opcodes are either
19111 narrow-only or wide-only and are thus available if OPCODE is valid. */
19112 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
19115 /* OPCODE with narrow only instruction variant or wide variant not
19121 md_assemble (char *str
)
19124 const struct asm_opcode
* opcode
;
19126 /* Align the previous label if needed. */
19127 if (last_label_seen
!= NULL
)
19129 symbol_set_frag (last_label_seen
, frag_now
);
19130 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
19131 S_SET_SEGMENT (last_label_seen
, now_seg
);
19134 memset (&inst
, '\0', sizeof (inst
));
19136 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
19137 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
19139 opcode
= opcode_lookup (&p
);
19142 /* It wasn't an instruction, but it might be a register alias of
19143 the form alias .req reg, or a Neon .dn/.qn directive. */
19144 if (! create_register_alias (str
, p
)
19145 && ! create_neon_reg_alias (str
, p
))
19146 as_bad (_("bad instruction `%s'"), str
);
19151 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
19152 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
19154 /* The value which unconditional instructions should have in place of the
19155 condition field. */
19156 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
19160 arm_feature_set variant
;
19162 variant
= cpu_variant
;
19163 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
19164 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
19165 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
19166 /* Check that this instruction is supported for this CPU. */
19167 if (!opcode
->tvariant
19168 || (thumb_mode
== 1
19169 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
19171 if (opcode
->tencode
== do_t_swi
)
19172 as_bad (_("SVC is not permitted on this architecture"));
19174 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
19177 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
19178 && opcode
->tencode
!= do_t_branch
)
19180 as_bad (_("Thumb does not support conditional execution"));
19184 /* Two things are addressed here:
19185 1) Implicit require narrow instructions on Thumb-1.
19186 This avoids relaxation accidentally introducing Thumb-2
19188 2) Reject wide instructions in non Thumb-2 cores.
19190 Only instructions with narrow and wide variants need to be handled
19191 but selecting all non wide-only instructions is easier. */
19192 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
19193 && !t32_insn_ok (variant
, opcode
))
19195 if (inst
.size_req
== 0)
19197 else if (inst
.size_req
== 4)
19199 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
19200 as_bad (_("selected processor does not support 32bit wide "
19201 "variant of instruction `%s'"), str
);
19203 as_bad (_("selected processor does not support `%s' in "
19204 "Thumb-2 mode"), str
);
19209 inst
.instruction
= opcode
->tvalue
;
19211 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
19213 /* Prepare the it_insn_type for those encodings that don't set
19215 it_fsm_pre_encode ();
19217 opcode
->tencode ();
19219 it_fsm_post_encode ();
19222 if (!(inst
.error
|| inst
.relax
))
19224 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
19225 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
19226 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
19228 as_bad (_("cannot honor width suffix -- `%s'"), str
);
19233 /* Something has gone badly wrong if we try to relax a fixed size
19235 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
19237 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
19238 *opcode
->tvariant
);
19239 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
19240 set those bits when Thumb-2 32-bit instructions are seen. The impact
19241 of relaxable instructions will be considered later after we finish all
19243 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
19244 variant
= arm_arch_none
;
19246 variant
= cpu_variant
;
19247 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
19248 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
19251 check_neon_suffixes
;
19255 mapping_state (MAP_THUMB
);
19258 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19262 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
19263 is_bx
= (opcode
->aencode
== do_bx
);
19265 /* Check that this instruction is supported for this CPU. */
19266 if (!(is_bx
&& fix_v4bx
)
19267 && !(opcode
->avariant
&&
19268 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
19270 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
19275 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
19279 inst
.instruction
= opcode
->avalue
;
19280 if (opcode
->tag
== OT_unconditionalF
)
19281 inst
.instruction
|= 0xFU
<< 28;
19283 inst
.instruction
|= inst
.cond
<< 28;
19284 inst
.size
= INSN_SIZE
;
19285 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
19287 it_fsm_pre_encode ();
19288 opcode
->aencode ();
19289 it_fsm_post_encode ();
19291 /* Arm mode bx is marked as both v4T and v5 because it's still required
19292 on a hypothetical non-thumb v5 core. */
19294 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
19296 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
19297 *opcode
->avariant
);
19299 check_neon_suffixes
;
19303 mapping_state (MAP_ARM
);
19308 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
19316 check_it_blocks_finished (void)
19321 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
19322 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
19323 == MANUAL_IT_BLOCK
)
19325 as_warn (_("section '%s' finished with an open IT block."),
19329 if (now_it
.state
== MANUAL_IT_BLOCK
)
19330 as_warn (_("file finished with an open IT block."));
19334 /* Various frobbings of labels and their addresses. */
19337 arm_start_line_hook (void)
19339 last_label_seen
= NULL
;
19343 arm_frob_label (symbolS
* sym
)
19345 last_label_seen
= sym
;
19347 ARM_SET_THUMB (sym
, thumb_mode
);
19349 #if defined OBJ_COFF || defined OBJ_ELF
19350 ARM_SET_INTERWORK (sym
, support_interwork
);
19353 force_automatic_it_block_close ();
19355 /* Note - do not allow local symbols (.Lxxx) to be labelled
19356 as Thumb functions. This is because these labels, whilst
19357 they exist inside Thumb code, are not the entry points for
19358 possible ARM->Thumb calls. Also, these labels can be used
19359 as part of a computed goto or switch statement. eg gcc
19360 can generate code that looks like this:
19362 ldr r2, [pc, .Laaa]
19372 The first instruction loads the address of the jump table.
19373 The second instruction converts a table index into a byte offset.
19374 The third instruction gets the jump address out of the table.
19375 The fourth instruction performs the jump.
19377 If the address stored at .Laaa is that of a symbol which has the
19378 Thumb_Func bit set, then the linker will arrange for this address
19379 to have the bottom bit set, which in turn would mean that the
19380 address computation performed by the third instruction would end
19381 up with the bottom bit set. Since the ARM is capable of unaligned
19382 word loads, the instruction would then load the incorrect address
19383 out of the jump table, and chaos would ensue. */
19384 if (label_is_thumb_function_name
19385 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
19386 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
19388 /* When the address of a Thumb function is taken the bottom
19389 bit of that address should be set. This will allow
19390 interworking between Arm and Thumb functions to work
19393 THUMB_SET_FUNC (sym
, 1);
19395 label_is_thumb_function_name
= FALSE
;
19398 dwarf2_emit_label (sym
);
19402 arm_data_in_code (void)
19404 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
19406 *input_line_pointer
= '/';
19407 input_line_pointer
+= 5;
19408 *input_line_pointer
= 0;
19416 arm_canonicalize_symbol_name (char * name
)
19420 if (thumb_mode
&& (len
= strlen (name
)) > 5
19421 && streq (name
+ len
- 5, "/data"))
19422 *(name
+ len
- 5) = 0;
19427 /* Table of all register names defined by default. The user can
19428 define additional names with .req. Note that all register names
19429 should appear in both upper and lowercase variants. Some registers
19430 also have mixed-case names. */
19432 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
19433 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
19434 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
19435 #define REGSET(p,t) \
19436 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
19437 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
19438 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
19439 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
19440 #define REGSETH(p,t) \
19441 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
19442 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
19443 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
19444 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
19445 #define REGSET2(p,t) \
19446 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
19447 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
19448 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
19449 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
19450 #define SPLRBANK(base,bank,t) \
19451 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
19452 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
19453 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
19454 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
19455 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
19456 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
19458 static const struct reg_entry reg_names
[] =
19460 /* ARM integer registers. */
19461 REGSET(r
, RN
), REGSET(R
, RN
),
19463 /* ATPCS synonyms. */
19464 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
19465 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
19466 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
19468 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
19469 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
19470 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
19472 /* Well-known aliases. */
19473 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
19474 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
19476 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
19477 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
19479 /* Coprocessor numbers. */
19480 REGSET(p
, CP
), REGSET(P
, CP
),
19482 /* Coprocessor register numbers. The "cr" variants are for backward
19484 REGSET(c
, CN
), REGSET(C
, CN
),
19485 REGSET(cr
, CN
), REGSET(CR
, CN
),
19487 /* ARM banked registers. */
19488 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
19489 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
19490 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
19491 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
19492 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
19493 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
19494 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
19496 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
19497 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
19498 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
19499 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
19500 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
19501 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
19502 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
19503 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
19505 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
19506 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
19507 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
19508 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
19509 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
19510 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
19511 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
19512 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19513 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19515 /* FPA registers. */
19516 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
19517 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
19519 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
19520 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
19522 /* VFP SP registers. */
19523 REGSET(s
,VFS
), REGSET(S
,VFS
),
19524 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
19526 /* VFP DP Registers. */
19527 REGSET(d
,VFD
), REGSET(D
,VFD
),
19528 /* Extra Neon DP registers. */
19529 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
19531 /* Neon QP registers. */
19532 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
19534 /* VFP control registers. */
19535 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
19536 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
19537 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
19538 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
19539 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
19540 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
19541 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
19543 /* Maverick DSP coprocessor registers. */
19544 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
19545 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
19547 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
19548 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
19549 REGDEF(dspsc
,0,DSPSC
),
19551 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
19552 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
19553 REGDEF(DSPSC
,0,DSPSC
),
19555 /* iWMMXt data registers - p0, c0-15. */
19556 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
19558 /* iWMMXt control registers - p1, c0-3. */
19559 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
19560 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
19561 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
19562 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
19564 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
19565 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
19566 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
19567 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
19568 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
19570 /* XScale accumulator registers. */
19571 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
19577 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
19578 within psr_required_here. */
19579 static const struct asm_psr psrs
[] =
19581 /* Backward compatibility notation. Note that "all" is no longer
19582 truly all possible PSR bits. */
19583 {"all", PSR_c
| PSR_f
},
19587 /* Individual flags. */
19593 /* Combinations of flags. */
19594 {"fs", PSR_f
| PSR_s
},
19595 {"fx", PSR_f
| PSR_x
},
19596 {"fc", PSR_f
| PSR_c
},
19597 {"sf", PSR_s
| PSR_f
},
19598 {"sx", PSR_s
| PSR_x
},
19599 {"sc", PSR_s
| PSR_c
},
19600 {"xf", PSR_x
| PSR_f
},
19601 {"xs", PSR_x
| PSR_s
},
19602 {"xc", PSR_x
| PSR_c
},
19603 {"cf", PSR_c
| PSR_f
},
19604 {"cs", PSR_c
| PSR_s
},
19605 {"cx", PSR_c
| PSR_x
},
19606 {"fsx", PSR_f
| PSR_s
| PSR_x
},
19607 {"fsc", PSR_f
| PSR_s
| PSR_c
},
19608 {"fxs", PSR_f
| PSR_x
| PSR_s
},
19609 {"fxc", PSR_f
| PSR_x
| PSR_c
},
19610 {"fcs", PSR_f
| PSR_c
| PSR_s
},
19611 {"fcx", PSR_f
| PSR_c
| PSR_x
},
19612 {"sfx", PSR_s
| PSR_f
| PSR_x
},
19613 {"sfc", PSR_s
| PSR_f
| PSR_c
},
19614 {"sxf", PSR_s
| PSR_x
| PSR_f
},
19615 {"sxc", PSR_s
| PSR_x
| PSR_c
},
19616 {"scf", PSR_s
| PSR_c
| PSR_f
},
19617 {"scx", PSR_s
| PSR_c
| PSR_x
},
19618 {"xfs", PSR_x
| PSR_f
| PSR_s
},
19619 {"xfc", PSR_x
| PSR_f
| PSR_c
},
19620 {"xsf", PSR_x
| PSR_s
| PSR_f
},
19621 {"xsc", PSR_x
| PSR_s
| PSR_c
},
19622 {"xcf", PSR_x
| PSR_c
| PSR_f
},
19623 {"xcs", PSR_x
| PSR_c
| PSR_s
},
19624 {"cfs", PSR_c
| PSR_f
| PSR_s
},
19625 {"cfx", PSR_c
| PSR_f
| PSR_x
},
19626 {"csf", PSR_c
| PSR_s
| PSR_f
},
19627 {"csx", PSR_c
| PSR_s
| PSR_x
},
19628 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19629 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19630 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19631 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19632 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19633 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19634 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19635 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19636 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19637 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19638 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19639 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19640 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19641 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19642 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19643 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19644 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19645 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19646 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19647 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19648 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19649 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19650 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19651 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19652 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19653 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19656 /* Table of V7M psr names. */
19657 static const struct asm_psr v7m_psrs
[] =
19659 {"apsr", 0x0 }, {"APSR", 0x0 },
19660 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19661 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19662 {"psr", 0x3 }, {"PSR", 0x3 },
19663 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19664 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19665 {"epsr", 0x6 }, {"EPSR", 0x6 },
19666 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19667 {"msp", 0x8 }, {"MSP", 0x8 },
19668 {"psp", 0x9 }, {"PSP", 0x9 },
19669 {"msplim", 0xa }, {"MSPLIM", 0xa },
19670 {"psplim", 0xb }, {"PSPLIM", 0xb },
19671 {"primask", 0x10}, {"PRIMASK", 0x10},
19672 {"basepri", 0x11}, {"BASEPRI", 0x11},
19673 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19674 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19675 {"control", 0x14}, {"CONTROL", 0x14},
19676 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19677 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19678 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19679 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19680 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19681 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19682 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19683 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19684 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19687 /* Table of all shift-in-operand names. */
19688 static const struct asm_shift_name shift_names
[] =
19690 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19691 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19692 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19693 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19694 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19695 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19698 /* Table of all explicit relocation names. */
19700 static struct reloc_entry reloc_names
[] =
19702 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19703 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19704 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19705 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19706 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19707 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19708 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19709 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19710 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19711 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19712 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19713 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19714 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19715 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19716 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19717 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19718 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19719 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
19720 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
19721 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
19722 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19723 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19724 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
19725 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
19726 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
19727 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
19728 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
19732 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19733 static const struct asm_cond conds
[] =
19737 {"cs", 0x2}, {"hs", 0x2},
19738 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19752 #define UL_BARRIER(L,U,CODE,FEAT) \
19753 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19754 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19756 static struct asm_barrier_opt barrier_opt_names
[] =
19758 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19759 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19760 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19761 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19762 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19763 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19764 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19765 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19766 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19767 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19768 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19769 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19770 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19771 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19772 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19773 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19778 /* Table of ARM-format instructions. */
19780 /* Macros for gluing together operand strings. N.B. In all cases
19781 other than OPS0, the trailing OP_stop comes from default
19782 zero-initialization of the unspecified elements of the array. */
19783 #define OPS0() { OP_stop, }
19784 #define OPS1(a) { OP_##a, }
19785 #define OPS2(a,b) { OP_##a,OP_##b, }
19786 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19787 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19788 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19789 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19791 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19792 This is useful when mixing operands for ARM and THUMB, i.e. using the
19793 MIX_ARM_THUMB_OPERANDS macro.
19794 In order to use these macros, prefix the number of operands with _
19796 #define OPS_1(a) { a, }
19797 #define OPS_2(a,b) { a,b, }
19798 #define OPS_3(a,b,c) { a,b,c, }
19799 #define OPS_4(a,b,c,d) { a,b,c,d, }
19800 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19801 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19803 /* These macros abstract out the exact format of the mnemonic table and
19804 save some repeated characters. */
19806 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19807 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19808 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19809 THUMB_VARIANT, do_##ae, do_##te }
19811 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19812 a T_MNEM_xyz enumerator. */
19813 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19814 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19815 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19816 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19818 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19819 infix after the third character. */
19820 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19821 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19822 THUMB_VARIANT, do_##ae, do_##te }
19823 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19824 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19825 THUMB_VARIANT, do_##ae, do_##te }
19826 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19827 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19828 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19829 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19830 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19831 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19832 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19833 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19835 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19836 field is still 0xE. Many of the Thumb variants can be executed
19837 conditionally, so this is checked separately. */
19838 #define TUE(mnem, op, top, nops, ops, ae, te) \
19839 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19840 THUMB_VARIANT, do_##ae, do_##te }
19842 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19843 Used by mnemonics that have very minimal differences in the encoding for
19844 ARM and Thumb variants and can be handled in a common function. */
19845 #define TUEc(mnem, op, top, nops, ops, en) \
19846 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19847 THUMB_VARIANT, do_##en, do_##en }
19849 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19850 condition code field. */
19851 #define TUF(mnem, op, top, nops, ops, ae, te) \
19852 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19853 THUMB_VARIANT, do_##ae, do_##te }
19855 /* ARM-only variants of all the above. */
19856 #define CE(mnem, op, nops, ops, ae) \
19857 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19859 #define C3(mnem, op, nops, ops, ae) \
19860 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19862 /* Thumb-only variants of TCE and TUE. */
19863 #define ToC(mnem, top, nops, ops, te) \
19864 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
19867 #define ToU(mnem, top, nops, ops, te) \
19868 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
19871 /* T_MNEM_xyz enumerator variants of ToC. */
19872 #define toC(mnem, top, nops, ops, te) \
19873 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
19876 /* T_MNEM_xyz enumerator variants of ToU. */
19877 #define toU(mnem, top, nops, ops, te) \
19878 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
19881 /* Legacy mnemonics that always have conditional infix after the third
19883 #define CL(mnem, op, nops, ops, ae) \
19884 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19885 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19887 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19888 #define cCE(mnem, op, nops, ops, ae) \
19889 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19891 /* Legacy coprocessor instructions where conditional infix and conditional
19892 suffix are ambiguous. For consistency this includes all FPA instructions,
19893 not just the potentially ambiguous ones. */
19894 #define cCL(mnem, op, nops, ops, ae) \
19895 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19896 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19898 /* Coprocessor, takes either a suffix or a position-3 infix
19899 (for an FPA corner case). */
19900 #define C3E(mnem, op, nops, ops, ae) \
19901 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19902 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19904 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19905 { m1 #m2 m3, OPS##nops ops, \
19906 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19907 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19909 #define CM(m1, m2, op, nops, ops, ae) \
19910 xCM_ (m1, , m2, op, nops, ops, ae), \
19911 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19912 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19913 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19914 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19915 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19916 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19917 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19918 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19919 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19920 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19921 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19922 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19923 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19924 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19925 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19926 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19927 xCM_ (m1, le, m2, op, nops, ops, ae), \
19928 xCM_ (m1, al, m2, op, nops, ops, ae)
19930 #define UE(mnem, op, nops, ops, ae) \
19931 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19933 #define UF(mnem, op, nops, ops, ae) \
19934 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19936 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19937 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19938 use the same encoding function for each. */
19939 #define NUF(mnem, op, nops, ops, enc) \
19940 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19941 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19943 /* Neon data processing, version which indirects through neon_enc_tab for
19944 the various overloaded versions of opcodes. */
19945 #define nUF(mnem, op, nops, ops, enc) \
19946 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19947 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19949 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19951 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19952 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19953 THUMB_VARIANT, do_##enc, do_##enc }
19955 #define NCE(mnem, op, nops, ops, enc) \
19956 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19958 #define NCEF(mnem, op, nops, ops, enc) \
19959 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19961 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19962 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19963 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19964 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19966 #define nCE(mnem, op, nops, ops, enc) \
19967 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19969 #define nCEF(mnem, op, nops, ops, enc) \
19970 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19974 static const struct asm_opcode insns
[] =
19976 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19977 #define THUMB_VARIANT & arm_ext_v4t
19978 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19979 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19980 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19981 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19982 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19983 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19984 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19985 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19986 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19987 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19988 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19989 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19990 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19991 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19992 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19993 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19995 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19996 for setting PSR flag bits. They are obsolete in V6 and do not
19997 have Thumb equivalents. */
19998 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19999 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
20000 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
20001 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
20002 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
20003 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
20004 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
20005 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
20006 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
20008 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
20009 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
20010 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
20011 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
20013 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
20014 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
20015 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
20017 OP_ADDRGLDR
),ldst
, t_ldst
),
20018 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
20020 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20021 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20022 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20023 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20024 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20025 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20027 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
20028 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
20031 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
20032 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
20033 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
20034 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
20036 /* Thumb-compatibility pseudo ops. */
20037 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20038 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20039 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20040 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20041 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20042 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20043 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20044 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20045 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
20046 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
20047 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
20048 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
20050 /* These may simplify to neg. */
20051 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
20052 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
20054 #undef THUMB_VARIANT
20055 #define THUMB_VARIANT & arm_ext_os
20057 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
20058 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
20060 #undef THUMB_VARIANT
20061 #define THUMB_VARIANT & arm_ext_v6
20063 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
20065 /* V1 instructions with no Thumb analogue prior to V6T2. */
20066 #undef THUMB_VARIANT
20067 #define THUMB_VARIANT & arm_ext_v6t2
20069 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
20070 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
20071 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
20073 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
20074 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
20075 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
20076 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
20078 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20079 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20081 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20082 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20084 /* V1 instructions with no Thumb analogue at all. */
20085 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
20086 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
20088 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
20089 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
20090 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
20091 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
20092 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
20093 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
20094 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
20095 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
20098 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
20099 #undef THUMB_VARIANT
20100 #define THUMB_VARIANT & arm_ext_v4t
20102 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
20103 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
20105 #undef THUMB_VARIANT
20106 #define THUMB_VARIANT & arm_ext_v6t2
20108 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
20109 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
20111 /* Generic coprocessor instructions. */
20112 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
20113 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20114 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20115 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20116 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20117 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
20118 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
20121 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
20123 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
20124 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
20127 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
20128 #undef THUMB_VARIANT
20129 #define THUMB_VARIANT & arm_ext_msr
20131 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
20132 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
20135 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
20136 #undef THUMB_VARIANT
20137 #define THUMB_VARIANT & arm_ext_v6t2
20139 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
20140 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
20141 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
20142 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
20143 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
20144 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
20145 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
20146 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
20149 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
20150 #undef THUMB_VARIANT
20151 #define THUMB_VARIANT & arm_ext_v4t
20153 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20154 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20155 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20156 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20157 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20158 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20161 #define ARM_VARIANT & arm_ext_v4t_5
20163 /* ARM Architecture 4T. */
20164 /* Note: bx (and blx) are required on V5, even if the processor does
20165 not support Thumb. */
20166 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
20169 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
20170 #undef THUMB_VARIANT
20171 #define THUMB_VARIANT & arm_ext_v5t
20173 /* Note: blx has 2 variants; the .value coded here is for
20174 BLX(2). Only this variant has conditional execution. */
20175 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
20176 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
20178 #undef THUMB_VARIANT
20179 #define THUMB_VARIANT & arm_ext_v6t2
20181 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
20182 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20183 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20184 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20185 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20186 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
20187 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
20188 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
20191 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
20192 #undef THUMB_VARIANT
20193 #define THUMB_VARIANT & arm_ext_v5exp
20195 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20196 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20197 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20198 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20200 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20201 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20203 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
20204 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
20205 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
20206 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
20208 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20209 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20210 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20211 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20213 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20214 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20216 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20217 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20218 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20219 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20222 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
20223 #undef THUMB_VARIANT
20224 #define THUMB_VARIANT & arm_ext_v6t2
20226 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
20227 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
20229 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
20230 ADDRGLDRS
), ldrd
, t_ldstd
),
20232 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20233 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20236 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
20238 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
20241 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
20242 #undef THUMB_VARIANT
20243 #define THUMB_VARIANT & arm_ext_v6
20245 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
20246 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
20247 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
20248 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
20249 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
20250 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20251 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20252 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20253 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20254 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
20256 #undef THUMB_VARIANT
20257 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20259 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
20260 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20262 #undef THUMB_VARIANT
20263 #define THUMB_VARIANT & arm_ext_v6t2
20265 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20266 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20268 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
20269 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
20271 /* ARM V6 not included in V7M. */
20272 #undef THUMB_VARIANT
20273 #define THUMB_VARIANT & arm_ext_v6_notm
20274 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20275 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20276 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
20277 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
20278 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
20279 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20280 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
20281 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
20282 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
20283 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20284 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20285 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20286 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
20287 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
20288 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
20289 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
20290 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
20291 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
20292 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
20294 /* ARM V6 not included in V7M (eg. integer SIMD). */
20295 #undef THUMB_VARIANT
20296 #define THUMB_VARIANT & arm_ext_v6_dsp
20297 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
20298 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
20299 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20300 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20301 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20302 /* Old name for QASX. */
20303 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20304 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20305 /* Old name for QSAX. */
20306 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20307 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20308 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20309 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20310 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20311 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20312 /* Old name for SASX. */
20313 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20314 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20315 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20316 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20317 /* Old name for SHASX. */
20318 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20319 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20320 /* Old name for SHSAX. */
20321 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20322 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20323 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20324 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20325 /* Old name for SSAX. */
20326 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20327 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20328 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20329 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20330 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20331 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20332 /* Old name for UASX. */
20333 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20334 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20335 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20336 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20337 /* Old name for UHASX. */
20338 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20339 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20340 /* Old name for UHSAX. */
20341 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20342 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20343 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20344 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20345 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20346 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20347 /* Old name for UQASX. */
20348 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20349 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20350 /* Old name for UQSAX. */
20351 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20352 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20353 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20354 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20355 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20356 /* Old name for USAX. */
20357 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20358 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20359 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20360 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20361 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20362 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20363 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20364 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20365 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20366 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20367 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20368 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20369 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20370 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20371 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20372 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20373 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20374 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20375 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20376 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20377 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20378 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20379 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20380 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20381 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20382 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20383 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20384 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20385 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20386 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
20387 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
20388 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20389 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20390 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
20393 #define ARM_VARIANT & arm_ext_v6k_v6t2
20394 #undef THUMB_VARIANT
20395 #define THUMB_VARIANT & arm_ext_v6k_v6t2
20397 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
20398 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
20399 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
20400 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
20402 #undef THUMB_VARIANT
20403 #define THUMB_VARIANT & arm_ext_v6_notm
20404 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
20406 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
20407 RRnpcb
), strexd
, t_strexd
),
20409 #undef THUMB_VARIANT
20410 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20411 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
20413 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
20415 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20417 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20419 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
20422 #define ARM_VARIANT & arm_ext_sec
20423 #undef THUMB_VARIANT
20424 #define THUMB_VARIANT & arm_ext_sec
20426 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
20429 #define ARM_VARIANT & arm_ext_virt
20430 #undef THUMB_VARIANT
20431 #define THUMB_VARIANT & arm_ext_virt
20433 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
20434 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
20437 #define ARM_VARIANT & arm_ext_pan
20438 #undef THUMB_VARIANT
20439 #define THUMB_VARIANT & arm_ext_pan
20441 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
20444 #define ARM_VARIANT & arm_ext_v6t2
20445 #undef THUMB_VARIANT
20446 #define THUMB_VARIANT & arm_ext_v6t2
20448 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
20449 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
20450 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20451 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20453 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
20454 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
20456 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20457 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20458 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20459 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20462 #define ARM_VARIANT & arm_ext_v3
20463 #undef THUMB_VARIANT
20464 #define THUMB_VARIANT & arm_ext_v6t2
20466 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
20467 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
20468 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
20471 #define ARM_VARIANT & arm_ext_v6t2
20472 #undef THUMB_VARIANT
20473 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20474 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20475 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20477 /* Thumb-only instructions. */
20479 #define ARM_VARIANT NULL
20480 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
20481 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
20483 /* ARM does not really have an IT instruction, so always allow it.
20484 The opcode is copied from Thumb in order to allow warnings in
20485 -mimplicit-it=[never | arm] modes. */
20487 #define ARM_VARIANT & arm_ext_v1
20488 #undef THUMB_VARIANT
20489 #define THUMB_VARIANT & arm_ext_v6t2
20491 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
20492 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
20493 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
20494 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
20495 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
20496 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
20497 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
20498 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
20499 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
20500 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
20501 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
20502 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
20503 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
20504 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
20505 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
20506 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
20507 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20508 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20510 /* Thumb2 only instructions. */
20512 #define ARM_VARIANT NULL
20514 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20515 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20516 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20517 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20518 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
20519 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
20521 /* Hardware division instructions. */
20523 #define ARM_VARIANT & arm_ext_adiv
20524 #undef THUMB_VARIANT
20525 #define THUMB_VARIANT & arm_ext_div
20527 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20528 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20530 /* ARM V6M/V7 instructions. */
20532 #define ARM_VARIANT & arm_ext_barrier
20533 #undef THUMB_VARIANT
20534 #define THUMB_VARIANT & arm_ext_barrier
20536 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
20537 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
20538 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
20540 /* ARM V7 instructions. */
20542 #define ARM_VARIANT & arm_ext_v7
20543 #undef THUMB_VARIANT
20544 #define THUMB_VARIANT & arm_ext_v7
20546 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
20547 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
20550 #define ARM_VARIANT & arm_ext_mp
20551 #undef THUMB_VARIANT
20552 #define THUMB_VARIANT & arm_ext_mp
20554 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
20556 /* AArchv8 instructions. */
20558 #define ARM_VARIANT & arm_ext_v8
20560 /* Instructions shared between armv8-a and armv8-m. */
20561 #undef THUMB_VARIANT
20562 #define THUMB_VARIANT & arm_ext_atomics
20564 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20565 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20566 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20567 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20568 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20569 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20570 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20571 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
20572 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20573 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20575 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20577 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20579 #undef THUMB_VARIANT
20580 #define THUMB_VARIANT & arm_ext_v8
20582 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
20583 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
20585 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
20588 /* Defined in V8 but is in undefined encoding space for earlier
20589 architectures. However earlier architectures are required to treat
20590 this instuction as a semihosting trap as well. Hence while not explicitly
20591 defined as such, it is in fact correct to define the instruction for all
20593 #undef THUMB_VARIANT
20594 #define THUMB_VARIANT & arm_ext_v1
20596 #define ARM_VARIANT & arm_ext_v1
20597 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
20599 /* ARMv8 T32 only. */
20601 #define ARM_VARIANT NULL
20602 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
20603 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
20604 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
20606 /* FP for ARMv8. */
20608 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
20609 #undef THUMB_VARIANT
20610 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
20612 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20613 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20614 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20615 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20616 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20617 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20618 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
20619 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
20620 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
20621 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
20622 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
20623 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
20624 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
20625 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
20626 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
20627 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
20628 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
20630 /* Crypto v1 extensions. */
20632 #define ARM_VARIANT & fpu_crypto_ext_armv8
20633 #undef THUMB_VARIANT
20634 #define THUMB_VARIANT & fpu_crypto_ext_armv8
20636 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
20637 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
20638 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
20639 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
20640 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
20641 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
20642 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
20643 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
20644 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
20645 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
20646 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
20647 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
20648 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
20649 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
20652 #define ARM_VARIANT & crc_ext_armv8
20653 #undef THUMB_VARIANT
20654 #define THUMB_VARIANT & crc_ext_armv8
20655 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
20656 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
20657 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
20658 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
20659 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
20660 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
20662 /* ARMv8.2 RAS extension. */
20664 #define ARM_VARIANT & arm_ext_ras
20665 #undef THUMB_VARIANT
20666 #define THUMB_VARIANT & arm_ext_ras
20667 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
20670 #define ARM_VARIANT & arm_ext_v8_3
20671 #undef THUMB_VARIANT
20672 #define THUMB_VARIANT & arm_ext_v8_3
20673 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
20674 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
20675 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
20678 #define ARM_VARIANT & fpu_neon_ext_dotprod
20679 #undef THUMB_VARIANT
20680 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20681 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20682 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20685 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20686 #undef THUMB_VARIANT
20687 #define THUMB_VARIANT NULL
20689 cCE("wfs", e200110
, 1, (RR
), rd
),
20690 cCE("rfs", e300110
, 1, (RR
), rd
),
20691 cCE("wfc", e400110
, 1, (RR
), rd
),
20692 cCE("rfc", e500110
, 1, (RR
), rd
),
20694 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20695 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20696 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20697 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20699 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20700 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20701 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20702 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20704 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20705 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20706 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20707 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20708 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20709 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20710 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20711 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20712 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20713 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20714 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20715 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20717 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20718 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20719 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20720 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20721 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20722 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20723 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20724 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20725 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20726 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20727 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20728 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20730 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20731 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20732 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20733 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20734 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20735 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20736 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20737 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20738 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20739 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20740 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20741 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20743 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20744 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20745 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20746 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20747 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20748 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20749 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20750 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20751 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20752 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20753 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20754 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20756 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20757 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20758 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20759 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20760 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20761 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20762 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20763 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20764 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20765 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20766 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20767 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20769 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20770 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20771 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20772 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20773 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20774 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20775 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20776 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20777 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20778 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20779 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20780 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20782 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20783 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20784 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20785 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20786 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20787 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20788 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20789 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20790 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20791 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20792 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20793 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20795 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20796 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20797 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20798 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20799 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20800 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20801 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20802 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20803 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20804 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20805 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20806 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20808 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20809 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20810 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20811 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20812 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20813 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20814 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20815 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20816 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20817 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20818 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20819 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20821 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20822 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20823 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20824 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20825 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20826 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20827 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20828 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20829 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20830 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20831 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20832 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20834 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20835 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20836 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20837 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20838 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20839 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20840 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20841 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20842 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20843 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20844 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20845 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20847 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20848 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20849 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20850 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20851 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20852 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20853 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20854 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20855 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20856 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20857 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20858 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20860 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20861 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20862 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20863 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20864 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20865 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20866 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20867 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20868 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20869 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20870 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20871 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20873 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20874 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20875 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20876 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20877 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20878 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20879 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20880 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20881 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20882 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20883 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20884 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20886 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20887 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20888 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20889 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20890 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20891 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20892 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20893 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20894 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20895 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20896 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20897 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20899 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20900 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20901 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20902 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20903 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20904 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20905 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20906 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20907 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20908 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20909 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20910 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20912 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20913 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20914 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20915 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20916 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20917 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20918 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20919 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20920 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20921 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20922 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20923 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20925 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20926 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20927 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20928 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20929 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20930 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20931 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20932 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20933 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20934 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20935 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20936 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20938 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20939 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20940 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20941 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20942 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20943 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20944 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20945 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20946 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20947 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20948 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20949 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20951 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20952 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20953 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20954 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20955 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20956 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20957 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20958 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20959 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20960 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20961 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20962 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20964 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20965 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20966 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20967 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20968 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20969 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20970 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20971 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20972 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20973 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20974 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20975 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20977 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20978 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20979 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20980 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20981 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20982 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20983 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20984 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20985 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20986 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20987 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20988 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20990 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20991 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20992 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20993 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20994 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20995 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20996 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20997 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20998 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20999 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21000 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21001 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21003 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21004 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21005 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21006 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21007 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21008 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21009 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21010 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21011 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21012 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21013 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21014 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21016 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21017 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21018 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21019 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21020 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21021 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21022 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21023 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21024 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21025 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21026 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21027 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21029 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21030 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21031 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21032 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21033 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21034 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21035 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21036 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21037 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21038 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21039 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21040 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21042 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21043 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21044 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21045 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21046 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21047 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21048 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21049 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21050 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21051 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21052 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21053 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21055 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21056 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21057 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21058 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21059 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21060 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21061 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21062 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21063 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21064 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21065 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21066 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21068 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21069 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21070 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21071 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21072 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21073 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21074 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21075 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21076 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21077 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21078 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21079 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21081 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
21082 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
21083 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
21084 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
21086 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
21087 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
21088 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
21089 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
21090 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
21091 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
21092 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
21093 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
21094 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
21095 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
21096 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
21097 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
21099 /* The implementation of the FIX instruction is broken on some
21100 assemblers, in that it accepts a precision specifier as well as a
21101 rounding specifier, despite the fact that this is meaningless.
21102 To be more compatible, we accept it as well, though of course it
21103 does not set any bits. */
21104 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
21105 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
21106 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
21107 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
21108 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
21109 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
21110 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
21111 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
21112 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
21113 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
21114 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
21115 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
21116 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
21118 /* Instructions that were new with the real FPA, call them V2. */
21120 #define ARM_VARIANT & fpu_fpa_ext_v2
21122 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
21123 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
21124 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
21125 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
21126 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
21127 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
21130 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
21132 /* Moves and type conversions. */
21133 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21134 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
21135 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
21136 cCE("fmstat", ef1fa10
, 0, (), noargs
),
21137 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
21138 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
21139 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21140 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21141 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21142 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21143 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21144 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21145 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
21146 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
21148 /* Memory operations. */
21149 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
21150 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
21151 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
21152 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
21153 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
21154 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
21155 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
21156 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
21157 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
21158 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
21159 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
21160 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
21161 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
21162 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
21163 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
21164 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
21165 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
21166 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
21168 /* Monadic operations. */
21169 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21170 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21171 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21173 /* Dyadic operations. */
21174 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21175 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21176 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21177 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21178 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21179 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21180 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21181 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21182 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21185 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21186 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
21187 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21188 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
21190 /* Double precision load/store are still present on single precision
21191 implementations. */
21192 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
21193 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
21194 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
21195 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
21196 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
21197 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
21198 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
21199 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
21200 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
21201 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
21204 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
21206 /* Moves and type conversions. */
21207 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21208 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
21209 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21210 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
21211 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
21212 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
21213 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
21214 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
21215 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
21216 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21217 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21218 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21219 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21221 /* Monadic operations. */
21222 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21223 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21224 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21226 /* Dyadic operations. */
21227 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21228 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21229 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21230 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21231 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21232 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21233 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21234 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21235 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21238 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21239 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
21240 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21241 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
21244 #define ARM_VARIANT & fpu_vfp_ext_v2
21246 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
21247 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
21248 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
21249 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
21251 /* Instructions which may belong to either the Neon or VFP instruction sets.
21252 Individual encoder functions perform additional architecture checks. */
21254 #define ARM_VARIANT & fpu_vfp_ext_v1xd
21255 #undef THUMB_VARIANT
21256 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
21258 /* These mnemonics are unique to VFP. */
21259 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
21260 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
21261 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21262 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21263 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21264 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
21265 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
21266 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
21267 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
21268 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
21270 /* Mnemonics shared by Neon and VFP. */
21271 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
21272 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
21273 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
21275 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
21276 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
21278 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
21279 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
21281 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21282 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21283 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21284 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21285 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21286 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21287 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
21288 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
21290 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
21291 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
21292 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
21293 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
21296 /* NOTE: All VMOV encoding is special-cased! */
21297 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
21298 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
21301 #define ARM_VARIANT & arm_ext_fp16
21302 #undef THUMB_VARIANT
21303 #define THUMB_VARIANT & arm_ext_fp16
21304 /* New instructions added from v8.2, allowing the extraction and insertion of
21305 the upper 16 bits of a 32-bit vector register. */
21306 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
21307 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
21309 /* New backported fma/fms instructions optional in v8.2. */
21310 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
21311 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
21313 #undef THUMB_VARIANT
21314 #define THUMB_VARIANT & fpu_neon_ext_v1
21316 #define ARM_VARIANT & fpu_neon_ext_v1
21318 /* Data processing with three registers of the same length. */
21319 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
21320 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
21321 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
21322 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21323 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21324 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21325 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21326 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21327 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21328 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
21329 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
21330 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
21331 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
21332 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
21333 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
21334 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
21335 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
21336 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
21337 /* If not immediate, fall back to neon_dyadic_i64_su.
21338 shl_imm should accept I8 I16 I32 I64,
21339 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
21340 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
21341 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
21342 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
21343 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
21344 /* Logic ops, types optional & ignored. */
21345 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21346 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21347 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21348 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21349 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21350 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21351 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21352 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21353 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
21354 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
21355 /* Bitfield ops, untyped. */
21356 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21357 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21358 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21359 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21360 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21361 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21362 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
21363 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
21364 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
21365 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
21366 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
21367 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
21368 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
21369 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
21370 back to neon_dyadic_if_su. */
21371 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
21372 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
21373 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
21374 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
21375 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
21376 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
21377 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
21378 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
21379 /* Comparison. Type I8 I16 I32 F32. */
21380 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
21381 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
21382 /* As above, D registers only. */
21383 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
21384 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
21385 /* Int and float variants, signedness unimportant. */
21386 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
21387 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
21388 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
21389 /* Add/sub take types I8 I16 I32 I64 F32. */
21390 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
21391 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
21392 /* vtst takes sizes 8, 16, 32. */
21393 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
21394 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
21395 /* VMUL takes I8 I16 I32 F32 P8. */
21396 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
21397 /* VQD{R}MULH takes S16 S32. */
21398 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
21399 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
21400 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
21401 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
21402 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
21403 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
21404 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
21405 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
21406 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
21407 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
21408 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
21409 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
21410 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
21411 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
21412 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
21413 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
21414 /* ARM v8.1 extension. */
21415 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21416 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21417 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21418 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21420 /* Two address, int/float. Types S8 S16 S32 F32. */
21421 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21422 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21424 /* Data processing with two registers and a shift amount. */
21425 /* Right shifts, and variants with rounding.
21426 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
21427 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21428 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21429 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21430 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21431 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21432 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21433 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21434 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21435 /* Shift and insert. Sizes accepted 8 16 32 64. */
21436 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
21437 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
21438 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
21439 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
21440 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
21441 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
21442 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
21443 /* Right shift immediate, saturating & narrowing, with rounding variants.
21444 Types accepted S16 S32 S64 U16 U32 U64. */
21445 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21446 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21447 /* As above, unsigned. Types accepted S16 S32 S64. */
21448 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21449 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21450 /* Right shift narrowing. Types accepted I16 I32 I64. */
21451 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21452 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21453 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21454 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
21455 /* CVT with optional immediate for fixed-point variant. */
21456 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
21458 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
21459 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
21461 /* Data processing, three registers of different lengths. */
21462 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
21463 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
21464 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21465 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21466 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21467 /* If not scalar, fall back to neon_dyadic_long.
21468 Vector types as above, scalar types S16 S32 U16 U32. */
21469 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21470 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21471 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
21472 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21473 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21474 /* Dyadic, narrowing insns. Types I16 I32 I64. */
21475 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21476 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21477 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21478 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21479 /* Saturating doubling multiplies. Types S16 S32. */
21480 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21481 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21482 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21483 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
21484 S16 S32 U16 U32. */
21485 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
21487 /* Extract. Size 8. */
21488 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
21489 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
21491 /* Two registers, miscellaneous. */
21492 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
21493 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
21494 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
21495 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
21496 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
21497 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
21498 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
21499 /* Vector replicate. Sizes 8 16 32. */
21500 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
21501 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
21502 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
21503 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
21504 /* VMOVN. Types I16 I32 I64. */
21505 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
21506 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21507 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
21508 /* VQMOVUN. Types S16 S32 S64. */
21509 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
21510 /* VZIP / VUZP. Sizes 8 16 32. */
21511 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21512 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21513 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21514 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21515 /* VQABS / VQNEG. Types S8 S16 S32. */
21516 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21517 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21518 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21519 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21520 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
21521 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21522 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
21523 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21524 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
21525 /* Reciprocal estimates. Types U32 F16 F32. */
21526 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21527 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
21528 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21529 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
21530 /* VCLS. Types S8 S16 S32. */
21531 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
21532 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
21533 /* VCLZ. Types I8 I16 I32. */
21534 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
21535 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
21536 /* VCNT. Size 8. */
21537 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
21538 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
21539 /* Two address, untyped. */
21540 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
21541 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
21542 /* VTRN. Sizes 8 16 32. */
21543 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
21544 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
21546 /* Table lookup. Size 8. */
21547 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21548 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21550 #undef THUMB_VARIANT
21551 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
21553 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
21555 /* Neon element/structure load/store. */
21556 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21557 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21558 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21559 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21560 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21561 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21562 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21563 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21565 #undef THUMB_VARIANT
21566 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
21568 #define ARM_VARIANT & fpu_vfp_ext_v3xd
21569 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
21570 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21571 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21572 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21573 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21574 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21575 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21576 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21577 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21579 #undef THUMB_VARIANT
21580 #define THUMB_VARIANT & fpu_vfp_ext_v3
21582 #define ARM_VARIANT & fpu_vfp_ext_v3
21584 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
21585 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21586 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21587 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21588 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21589 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21590 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21591 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21592 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21595 #define ARM_VARIANT & fpu_vfp_ext_fma
21596 #undef THUMB_VARIANT
21597 #define THUMB_VARIANT & fpu_vfp_ext_fma
21598 /* Mnemonics shared by Neon and VFP. These are included in the
21599 VFP FMA variant; NEON and VFP FMA always includes the NEON
21600 FMA instructions. */
21601 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21602 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21603 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
21604 the v form should always be used. */
21605 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21606 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21607 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21608 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21609 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21610 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21612 #undef THUMB_VARIANT
21614 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
21616 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21617 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21618 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21619 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21620 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21621 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21622 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
21623 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
21626 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
21628 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
21629 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
21630 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
21631 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
21632 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
21633 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
21634 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
21635 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
21636 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
21637 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21638 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21639 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21640 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21641 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21642 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21643 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21644 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21645 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21646 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
21647 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
21648 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21649 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21650 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21651 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21652 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21653 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21654 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
21655 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
21656 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
21657 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
21658 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
21659 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
21660 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
21661 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
21662 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21663 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21664 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21665 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21666 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21667 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21668 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21669 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21670 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21671 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21672 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21673 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21674 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
21675 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21676 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21677 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21678 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21679 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21680 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21681 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21682 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21683 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21684 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21685 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21686 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21687 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21688 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21689 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21690 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21691 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21692 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21693 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21694 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21695 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21696 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21697 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21698 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21699 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21700 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21701 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21702 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21703 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21704 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21705 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21706 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21707 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21708 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21709 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21710 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21711 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21712 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21713 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21714 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21715 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21716 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21717 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21718 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21719 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21720 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21721 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21722 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21723 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21724 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21725 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21726 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21727 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21728 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21729 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21730 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21731 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21732 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21733 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21734 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21735 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21736 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21737 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21738 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21739 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21740 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21741 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21742 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21743 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21744 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21745 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21746 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21747 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21748 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21749 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21750 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21751 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21752 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21753 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21754 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21755 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21756 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21757 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21758 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21759 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21760 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21761 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21762 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21763 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21764 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21765 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21766 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21767 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21768 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21769 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21770 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21771 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21772 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21773 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21774 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21775 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21776 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21777 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21778 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21779 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21780 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21781 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21782 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21783 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21784 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21785 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21786 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21787 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21788 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21789 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21792 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21794 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21795 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21796 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21797 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21798 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21799 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21800 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21801 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21802 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21803 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21804 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21805 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21806 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21807 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21808 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21809 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21810 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21811 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21812 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21813 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21814 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21815 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21816 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21817 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21818 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21819 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21820 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21821 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21822 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21823 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21824 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21825 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21826 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21827 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21828 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21829 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21830 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21831 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21832 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21833 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21834 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21835 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21836 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21837 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21838 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21839 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21840 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21841 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21842 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21843 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21844 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21845 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21846 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21847 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21848 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21849 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21850 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21853 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21855 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21856 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21857 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21858 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21859 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21860 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21861 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21862 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21863 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21864 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21865 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21866 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21867 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21868 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21869 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21870 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21871 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21872 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21873 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21874 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21875 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21876 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21877 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21878 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21879 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21880 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21881 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21882 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21883 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21884 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21885 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21886 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21887 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21888 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21889 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21890 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21891 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21892 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21893 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21894 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21895 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21896 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21897 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21898 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21899 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21900 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21901 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21902 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21903 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21904 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21905 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21906 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21907 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21908 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21909 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21910 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21911 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21912 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21913 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21914 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21915 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21916 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21917 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21918 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21919 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21920 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21921 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21922 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21923 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21924 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21925 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21926 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21927 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21928 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21929 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21930 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21932 /* ARMv8.5-A instructions. */
21934 #define ARM_VARIANT & arm_ext_sb
21935 #undef THUMB_VARIANT
21936 #define THUMB_VARIANT & arm_ext_sb
21937 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
21940 #define ARM_VARIANT & arm_ext_predres
21941 #undef THUMB_VARIANT
21942 #define THUMB_VARIANT & arm_ext_predres
21943 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
21944 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
21945 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
21947 /* ARMv8-M instructions. */
21949 #define ARM_VARIANT NULL
21950 #undef THUMB_VARIANT
21951 #define THUMB_VARIANT & arm_ext_v8m
21952 ToU("sg", e97fe97f
, 0, (), noargs
),
21953 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
21954 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
21955 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
21956 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
21957 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
21958 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
21960 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21961 instructions behave as nop if no VFP is present. */
21962 #undef THUMB_VARIANT
21963 #define THUMB_VARIANT & arm_ext_v8m_main
21964 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
21965 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
21967 /* Armv8.1-M Mainline instructions. */
21968 #undef THUMB_VARIANT
21969 #define THUMB_VARIANT & arm_ext_v8_1m_main
21970 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
21971 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
21972 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
21973 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
21974 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
21976 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
21977 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
21978 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
21980 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
21981 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
)
21984 #undef THUMB_VARIANT
22016 /* MD interface: bits in the object file. */
22018 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
22019 for use in the a.out file, and stores them in the array pointed to by buf.
22020 This knows about the endian-ness of the target machine and does
22021 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
22022 2 (short) and 4 (long) Floating numbers are put out as a series of
22023 LITTLENUMS (shorts, here at least). */
22026 md_number_to_chars (char * buf
, valueT val
, int n
)
22028 if (target_big_endian
)
22029 number_to_chars_bigendian (buf
, val
, n
);
22031 number_to_chars_littleendian (buf
, val
, n
);
22035 md_chars_to_number (char * buf
, int n
)
22038 unsigned char * where
= (unsigned char *) buf
;
22040 if (target_big_endian
)
22045 result
|= (*where
++ & 255);
22053 result
|= (where
[n
] & 255);
22060 /* MD interface: Sections. */
22062 /* Calculate the maximum variable size (i.e., excluding fr_fix)
22063 that an rs_machine_dependent frag may reach. */
22066 arm_frag_max_var (fragS
*fragp
)
22068 /* We only use rs_machine_dependent for variable-size Thumb instructions,
22069 which are either THUMB_SIZE (2) or INSN_SIZE (4).
22071 Note that we generate relaxable instructions even for cases that don't
22072 really need it, like an immediate that's a trivial constant. So we're
22073 overestimating the instruction size for some of those cases. Rather
22074 than putting more intelligence here, it would probably be better to
22075 avoid generating a relaxation frag in the first place when it can be
22076 determined up front that a short instruction will suffice. */
22078 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
22082 /* Estimate the size of a frag before relaxing. Assume everything fits in
22086 md_estimate_size_before_relax (fragS
* fragp
,
22087 segT segtype ATTRIBUTE_UNUSED
)
22093 /* Convert a machine dependent frag. */
22096 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
22098 unsigned long insn
;
22099 unsigned long old_op
;
22107 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
22109 old_op
= bfd_get_16(abfd
, buf
);
22110 if (fragp
->fr_symbol
)
22112 exp
.X_op
= O_symbol
;
22113 exp
.X_add_symbol
= fragp
->fr_symbol
;
22117 exp
.X_op
= O_constant
;
22119 exp
.X_add_number
= fragp
->fr_offset
;
22120 opcode
= fragp
->fr_subtype
;
22123 case T_MNEM_ldr_pc
:
22124 case T_MNEM_ldr_pc2
:
22125 case T_MNEM_ldr_sp
:
22126 case T_MNEM_str_sp
:
22133 if (fragp
->fr_var
== 4)
22135 insn
= THUMB_OP32 (opcode
);
22136 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
22138 insn
|= (old_op
& 0x700) << 4;
22142 insn
|= (old_op
& 7) << 12;
22143 insn
|= (old_op
& 0x38) << 13;
22145 insn
|= 0x00000c00;
22146 put_thumb32_insn (buf
, insn
);
22147 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
22151 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
22153 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
22156 if (fragp
->fr_var
== 4)
22158 insn
= THUMB_OP32 (opcode
);
22159 insn
|= (old_op
& 0xf0) << 4;
22160 put_thumb32_insn (buf
, insn
);
22161 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
22165 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
22166 exp
.X_add_number
-= 4;
22174 if (fragp
->fr_var
== 4)
22176 int r0off
= (opcode
== T_MNEM_mov
22177 || opcode
== T_MNEM_movs
) ? 0 : 8;
22178 insn
= THUMB_OP32 (opcode
);
22179 insn
= (insn
& 0xe1ffffff) | 0x10000000;
22180 insn
|= (old_op
& 0x700) << r0off
;
22181 put_thumb32_insn (buf
, insn
);
22182 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
22186 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
22191 if (fragp
->fr_var
== 4)
22193 insn
= THUMB_OP32(opcode
);
22194 put_thumb32_insn (buf
, insn
);
22195 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
22198 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
22202 if (fragp
->fr_var
== 4)
22204 insn
= THUMB_OP32(opcode
);
22205 insn
|= (old_op
& 0xf00) << 14;
22206 put_thumb32_insn (buf
, insn
);
22207 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
22210 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
22213 case T_MNEM_add_sp
:
22214 case T_MNEM_add_pc
:
22215 case T_MNEM_inc_sp
:
22216 case T_MNEM_dec_sp
:
22217 if (fragp
->fr_var
== 4)
22219 /* ??? Choose between add and addw. */
22220 insn
= THUMB_OP32 (opcode
);
22221 insn
|= (old_op
& 0xf0) << 4;
22222 put_thumb32_insn (buf
, insn
);
22223 if (opcode
== T_MNEM_add_pc
)
22224 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
22226 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
22229 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
22237 if (fragp
->fr_var
== 4)
22239 insn
= THUMB_OP32 (opcode
);
22240 insn
|= (old_op
& 0xf0) << 4;
22241 insn
|= (old_op
& 0xf) << 16;
22242 put_thumb32_insn (buf
, insn
);
22243 if (insn
& (1 << 20))
22244 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
22246 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
22249 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
22255 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
22256 (enum bfd_reloc_code_real
) reloc_type
);
22257 fixp
->fx_file
= fragp
->fr_file
;
22258 fixp
->fx_line
= fragp
->fr_line
;
22259 fragp
->fr_fix
+= fragp
->fr_var
;
22261 /* Set whether we use thumb-2 ISA based on final relaxation results. */
22262 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
22263 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
22264 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
22267 /* Return the size of a relaxable immediate operand instruction.
22268 SHIFT and SIZE specify the form of the allowable immediate. */
22270 relax_immediate (fragS
*fragp
, int size
, int shift
)
22276 /* ??? Should be able to do better than this. */
22277 if (fragp
->fr_symbol
)
22280 low
= (1 << shift
) - 1;
22281 mask
= (1 << (shift
+ size
)) - (1 << shift
);
22282 offset
= fragp
->fr_offset
;
22283 /* Force misaligned offsets to 32-bit variant. */
22286 if (offset
& ~mask
)
22291 /* Get the address of a symbol during relaxation. */
22293 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
22299 sym
= fragp
->fr_symbol
;
22300 sym_frag
= symbol_get_frag (sym
);
22301 know (S_GET_SEGMENT (sym
) != absolute_section
22302 || sym_frag
== &zero_address_frag
);
22303 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
22305 /* If frag has yet to be reached on this pass, assume it will
22306 move by STRETCH just as we did. If this is not so, it will
22307 be because some frag between grows, and that will force
22311 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
22315 /* Adjust stretch for any alignment frag. Note that if have
22316 been expanding the earlier code, the symbol may be
22317 defined in what appears to be an earlier frag. FIXME:
22318 This doesn't handle the fr_subtype field, which specifies
22319 a maximum number of bytes to skip when doing an
22321 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
22323 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
22326 stretch
= - ((- stretch
)
22327 & ~ ((1 << (int) f
->fr_offset
) - 1));
22329 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
22341 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
22344 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
22349 /* Assume worst case for symbols not known to be in the same section. */
22350 if (fragp
->fr_symbol
== NULL
22351 || !S_IS_DEFINED (fragp
->fr_symbol
)
22352 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
22353 || S_IS_WEAK (fragp
->fr_symbol
))
22356 val
= relaxed_symbol_addr (fragp
, stretch
);
22357 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
22358 addr
= (addr
+ 4) & ~3;
22359 /* Force misaligned targets to 32-bit variant. */
22363 if (val
< 0 || val
> 1020)
22368 /* Return the size of a relaxable add/sub immediate instruction. */
22370 relax_addsub (fragS
*fragp
, asection
*sec
)
22375 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
22376 op
= bfd_get_16(sec
->owner
, buf
);
22377 if ((op
& 0xf) == ((op
>> 4) & 0xf))
22378 return relax_immediate (fragp
, 8, 0);
22380 return relax_immediate (fragp
, 3, 0);
22383 /* Return TRUE iff the definition of symbol S could be pre-empted
22384 (overridden) at link or load time. */
22386 symbol_preemptible (symbolS
*s
)
22388 /* Weak symbols can always be pre-empted. */
22392 /* Non-global symbols cannot be pre-empted. */
22393 if (! S_IS_EXTERNAL (s
))
22397 /* In ELF, a global symbol can be marked protected, or private. In that
22398 case it can't be pre-empted (other definitions in the same link unit
22399 would violate the ODR). */
22400 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
22404 /* Other global symbols might be pre-empted. */
22408 /* Return the size of a relaxable branch instruction. BITS is the
22409 size of the offset field in the narrow instruction. */
22412 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
22418 /* Assume worst case for symbols not known to be in the same section. */
22419 if (!S_IS_DEFINED (fragp
->fr_symbol
)
22420 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
22421 || S_IS_WEAK (fragp
->fr_symbol
))
22425 /* A branch to a function in ARM state will require interworking. */
22426 if (S_IS_DEFINED (fragp
->fr_symbol
)
22427 && ARM_IS_FUNC (fragp
->fr_symbol
))
22431 if (symbol_preemptible (fragp
->fr_symbol
))
22434 val
= relaxed_symbol_addr (fragp
, stretch
);
22435 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
22438 /* Offset is a signed value *2 */
22440 if (val
>= limit
|| val
< -limit
)
22446 /* Relax a machine dependent frag. This returns the amount by which
22447 the current size of the frag should change. */
22450 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
22455 oldsize
= fragp
->fr_var
;
22456 switch (fragp
->fr_subtype
)
22458 case T_MNEM_ldr_pc2
:
22459 newsize
= relax_adr (fragp
, sec
, stretch
);
22461 case T_MNEM_ldr_pc
:
22462 case T_MNEM_ldr_sp
:
22463 case T_MNEM_str_sp
:
22464 newsize
= relax_immediate (fragp
, 8, 2);
22468 newsize
= relax_immediate (fragp
, 5, 2);
22472 newsize
= relax_immediate (fragp
, 5, 1);
22476 newsize
= relax_immediate (fragp
, 5, 0);
22479 newsize
= relax_adr (fragp
, sec
, stretch
);
22485 newsize
= relax_immediate (fragp
, 8, 0);
22488 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
22491 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
22493 case T_MNEM_add_sp
:
22494 case T_MNEM_add_pc
:
22495 newsize
= relax_immediate (fragp
, 8, 2);
22497 case T_MNEM_inc_sp
:
22498 case T_MNEM_dec_sp
:
22499 newsize
= relax_immediate (fragp
, 7, 2);
22505 newsize
= relax_addsub (fragp
, sec
);
22511 fragp
->fr_var
= newsize
;
22512 /* Freeze wide instructions that are at or before the same location as
22513 in the previous pass. This avoids infinite loops.
22514 Don't freeze them unconditionally because targets may be artificially
22515 misaligned by the expansion of preceding frags. */
22516 if (stretch
<= 0 && newsize
> 2)
22518 md_convert_frag (sec
->owner
, sec
, fragp
);
22522 return newsize
- oldsize
;
22525 /* Round up a section size to the appropriate boundary. */
22528 md_section_align (segT segment ATTRIBUTE_UNUSED
,
22534 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
22535 of an rs_align_code fragment. */
22538 arm_handle_align (fragS
* fragP
)
22540 static unsigned char const arm_noop
[2][2][4] =
22543 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
22544 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
22547 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
22548 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
22551 static unsigned char const thumb_noop
[2][2][2] =
22554 {0xc0, 0x46}, /* LE */
22555 {0x46, 0xc0}, /* BE */
22558 {0x00, 0xbf}, /* LE */
22559 {0xbf, 0x00} /* BE */
22562 static unsigned char const wide_thumb_noop
[2][4] =
22563 { /* Wide Thumb-2 */
22564 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
22565 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
22568 unsigned bytes
, fix
, noop_size
;
22570 const unsigned char * noop
;
22571 const unsigned char *narrow_noop
= NULL
;
22576 if (fragP
->fr_type
!= rs_align_code
)
22579 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
22580 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
22583 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22584 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
22586 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
22588 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
22590 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22591 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
22593 narrow_noop
= thumb_noop
[1][target_big_endian
];
22594 noop
= wide_thumb_noop
[target_big_endian
];
22597 noop
= thumb_noop
[0][target_big_endian
];
22605 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22606 ? selected_cpu
: arm_arch_none
,
22608 [target_big_endian
];
22615 fragP
->fr_var
= noop_size
;
22617 if (bytes
& (noop_size
- 1))
22619 fix
= bytes
& (noop_size
- 1);
22621 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
22623 memset (p
, 0, fix
);
22630 if (bytes
& noop_size
)
22632 /* Insert a narrow noop. */
22633 memcpy (p
, narrow_noop
, noop_size
);
22635 bytes
-= noop_size
;
22639 /* Use wide noops for the remainder */
22643 while (bytes
>= noop_size
)
22645 memcpy (p
, noop
, noop_size
);
22647 bytes
-= noop_size
;
22651 fragP
->fr_fix
+= fix
;
22654 /* Called from md_do_align. Used to create an alignment
22655 frag in a code section. */
22658 arm_frag_align_code (int n
, int max
)
22662 /* We assume that there will never be a requirement
22663 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
22664 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22669 _("alignments greater than %d bytes not supported in .text sections."),
22670 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
22671 as_fatal ("%s", err_msg
);
22674 p
= frag_var (rs_align_code
,
22675 MAX_MEM_FOR_RS_ALIGN_CODE
,
22677 (relax_substateT
) max
,
22684 /* Perform target specific initialisation of a frag.
22685 Note - despite the name this initialisation is not done when the frag
22686 is created, but only when its type is assigned. A frag can be created
22687 and used a long time before its type is set, so beware of assuming that
22688 this initialisation is performed first. */
22692 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
22694 /* Record whether this frag is in an ARM or a THUMB area. */
22695 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22698 #else /* OBJ_ELF is defined. */
22700 arm_init_frag (fragS
* fragP
, int max_chars
)
22702 bfd_boolean frag_thumb_mode
;
22704 /* If the current ARM vs THUMB mode has not already
22705 been recorded into this frag then do so now. */
22706 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22707 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22709 /* PR 21809: Do not set a mapping state for debug sections
22710 - it just confuses other tools. */
22711 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
22714 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22716 /* Record a mapping symbol for alignment frags. We will delete this
22717 later if the alignment ends up empty. */
22718 switch (fragP
->fr_type
)
22721 case rs_align_test
:
22723 mapping_state_2 (MAP_DATA
, max_chars
);
22725 case rs_align_code
:
22726 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22733 /* When we change sections we need to issue a new mapping symbol. */
22736 arm_elf_change_section (void)
22738 /* Link an unlinked unwind index table section to the .text section. */
22739 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22740 && elf_linked_to_section (now_seg
) == NULL
)
22741 elf_linked_to_section (now_seg
) = text_section
;
22745 arm_elf_section_type (const char * str
, size_t len
)
22747 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22748 return SHT_ARM_EXIDX
;
22753 /* Code to deal with unwinding tables. */
22755 static void add_unwind_adjustsp (offsetT
);
22757 /* Generate any deferred unwind frame offset. */
22760 flush_pending_unwind (void)
22764 offset
= unwind
.pending_offset
;
22765 unwind
.pending_offset
= 0;
22767 add_unwind_adjustsp (offset
);
22770 /* Add an opcode to this list for this function. Two-byte opcodes should
22771 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22775 add_unwind_opcode (valueT op
, int length
)
22777 /* Add any deferred stack adjustment. */
22778 if (unwind
.pending_offset
)
22779 flush_pending_unwind ();
22781 unwind
.sp_restored
= 0;
22783 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22785 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22786 if (unwind
.opcodes
)
22787 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22788 unwind
.opcode_alloc
);
22790 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22795 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22797 unwind
.opcode_count
++;
22801 /* Add unwind opcodes to adjust the stack pointer. */
22804 add_unwind_adjustsp (offsetT offset
)
22808 if (offset
> 0x200)
22810 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22815 /* Long form: 0xb2, uleb128. */
22816 /* This might not fit in a word so add the individual bytes,
22817 remembering the list is built in reverse order. */
22818 o
= (valueT
) ((offset
- 0x204) >> 2);
22820 add_unwind_opcode (0, 1);
22822 /* Calculate the uleb128 encoding of the offset. */
22826 bytes
[n
] = o
& 0x7f;
22832 /* Add the insn. */
22834 add_unwind_opcode (bytes
[n
- 1], 1);
22835 add_unwind_opcode (0xb2, 1);
22837 else if (offset
> 0x100)
22839 /* Two short opcodes. */
22840 add_unwind_opcode (0x3f, 1);
22841 op
= (offset
- 0x104) >> 2;
22842 add_unwind_opcode (op
, 1);
22844 else if (offset
> 0)
22846 /* Short opcode. */
22847 op
= (offset
- 4) >> 2;
22848 add_unwind_opcode (op
, 1);
22850 else if (offset
< 0)
22853 while (offset
> 0x100)
22855 add_unwind_opcode (0x7f, 1);
22858 op
= ((offset
- 4) >> 2) | 0x40;
22859 add_unwind_opcode (op
, 1);
22863 /* Finish the list of unwind opcodes for this function. */
22866 finish_unwind_opcodes (void)
22870 if (unwind
.fp_used
)
22872 /* Adjust sp as necessary. */
22873 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22874 flush_pending_unwind ();
22876 /* After restoring sp from the frame pointer. */
22877 op
= 0x90 | unwind
.fp_reg
;
22878 add_unwind_opcode (op
, 1);
22881 flush_pending_unwind ();
22885 /* Start an exception table entry. If idx is nonzero this is an index table
22889 start_unwind_section (const segT text_seg
, int idx
)
22891 const char * text_name
;
22892 const char * prefix
;
22893 const char * prefix_once
;
22894 const char * group_name
;
22902 prefix
= ELF_STRING_ARM_unwind
;
22903 prefix_once
= ELF_STRING_ARM_unwind_once
;
22904 type
= SHT_ARM_EXIDX
;
22908 prefix
= ELF_STRING_ARM_unwind_info
;
22909 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22910 type
= SHT_PROGBITS
;
22913 text_name
= segment_name (text_seg
);
22914 if (streq (text_name
, ".text"))
22917 if (strncmp (text_name
, ".gnu.linkonce.t.",
22918 strlen (".gnu.linkonce.t.")) == 0)
22920 prefix
= prefix_once
;
22921 text_name
+= strlen (".gnu.linkonce.t.");
22924 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22930 /* Handle COMDAT group. */
22931 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22933 group_name
= elf_group_name (text_seg
);
22934 if (group_name
== NULL
)
22936 as_bad (_("Group section `%s' has no group signature"),
22937 segment_name (text_seg
));
22938 ignore_rest_of_line ();
22941 flags
|= SHF_GROUP
;
22945 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22948 /* Set the section link for index tables. */
22950 elf_linked_to_section (now_seg
) = text_seg
;
22954 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22955 personality routine data. Returns zero, or the index table value for
22956 an inline entry. */
22959 create_unwind_entry (int have_data
)
22964 /* The current word of data. */
22966 /* The number of bytes left in this word. */
22969 finish_unwind_opcodes ();
22971 /* Remember the current text section. */
22972 unwind
.saved_seg
= now_seg
;
22973 unwind
.saved_subseg
= now_subseg
;
22975 start_unwind_section (now_seg
, 0);
22977 if (unwind
.personality_routine
== NULL
)
22979 if (unwind
.personality_index
== -2)
22982 as_bad (_("handlerdata in cantunwind frame"));
22983 return 1; /* EXIDX_CANTUNWIND. */
22986 /* Use a default personality routine if none is specified. */
22987 if (unwind
.personality_index
== -1)
22989 if (unwind
.opcode_count
> 3)
22990 unwind
.personality_index
= 1;
22992 unwind
.personality_index
= 0;
22995 /* Space for the personality routine entry. */
22996 if (unwind
.personality_index
== 0)
22998 if (unwind
.opcode_count
> 3)
22999 as_bad (_("too many unwind opcodes for personality routine 0"));
23003 /* All the data is inline in the index table. */
23006 while (unwind
.opcode_count
> 0)
23008 unwind
.opcode_count
--;
23009 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
23013 /* Pad with "finish" opcodes. */
23015 data
= (data
<< 8) | 0xb0;
23022 /* We get two opcodes "free" in the first word. */
23023 size
= unwind
.opcode_count
- 2;
23027 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
23028 if (unwind
.personality_index
!= -1)
23030 as_bad (_("attempt to recreate an unwind entry"));
23034 /* An extra byte is required for the opcode count. */
23035 size
= unwind
.opcode_count
+ 1;
23038 size
= (size
+ 3) >> 2;
23040 as_bad (_("too many unwind opcodes"));
23042 frag_align (2, 0, 0);
23043 record_alignment (now_seg
, 2);
23044 unwind
.table_entry
= expr_build_dot ();
23046 /* Allocate the table entry. */
23047 ptr
= frag_more ((size
<< 2) + 4);
23048 /* PR 13449: Zero the table entries in case some of them are not used. */
23049 memset (ptr
, 0, (size
<< 2) + 4);
23050 where
= frag_now_fix () - ((size
<< 2) + 4);
23052 switch (unwind
.personality_index
)
23055 /* ??? Should this be a PLT generating relocation? */
23056 /* Custom personality routine. */
23057 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
23058 BFD_RELOC_ARM_PREL31
);
23063 /* Set the first byte to the number of additional words. */
23064 data
= size
> 0 ? size
- 1 : 0;
23068 /* ABI defined personality routines. */
23070 /* Three opcodes bytes are packed into the first word. */
23077 /* The size and first two opcode bytes go in the first word. */
23078 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
23083 /* Should never happen. */
23087 /* Pack the opcodes into words (MSB first), reversing the list at the same
23089 while (unwind
.opcode_count
> 0)
23093 md_number_to_chars (ptr
, data
, 4);
23098 unwind
.opcode_count
--;
23100 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
23103 /* Finish off the last word. */
23106 /* Pad with "finish" opcodes. */
23108 data
= (data
<< 8) | 0xb0;
23110 md_number_to_chars (ptr
, data
, 4);
23115 /* Add an empty descriptor if there is no user-specified data. */
23116 ptr
= frag_more (4);
23117 md_number_to_chars (ptr
, 0, 4);
23124 /* Initialize the DWARF-2 unwind information for this procedure. */
23127 tc_arm_frame_initial_instructions (void)
23129 cfi_add_CFA_def_cfa (REG_SP
, 0);
23131 #endif /* OBJ_ELF */
23133 /* Convert REGNAME to a DWARF-2 register number. */
23136 tc_arm_regname_to_dw2regnum (char *regname
)
23138 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
23142 /* PR 16694: Allow VFP registers as well. */
23143 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
23147 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
23156 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
23160 exp
.X_op
= O_secrel
;
23161 exp
.X_add_symbol
= symbol
;
23162 exp
.X_add_number
= 0;
23163 emit_expr (&exp
, size
);
23167 /* MD interface: Symbol and relocation handling. */
23169 /* Return the address within the segment that a PC-relative fixup is
23170 relative to. For ARM, PC-relative fixups applied to instructions
23171 are generally relative to the location of the fixup plus 8 bytes.
23172 Thumb branches are offset by 4, and Thumb loads relative to PC
23173 require special handling. */
23176 md_pcrel_from_section (fixS
* fixP
, segT seg
)
23178 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23180 /* If this is pc-relative and we are going to emit a relocation
23181 then we just want to put out any pipeline compensation that the linker
23182 will need. Otherwise we want to use the calculated base.
23183 For WinCE we skip the bias for externals as well, since this
23184 is how the MS ARM-CE assembler behaves and we want to be compatible. */
23186 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23187 || (arm_force_relocation (fixP
)
23189 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
23195 switch (fixP
->fx_r_type
)
23197 /* PC relative addressing on the Thumb is slightly odd as the
23198 bottom two bits of the PC are forced to zero for the
23199 calculation. This happens *after* application of the
23200 pipeline offset. However, Thumb adrl already adjusts for
23201 this, so we need not do it again. */
23202 case BFD_RELOC_ARM_THUMB_ADD
:
23205 case BFD_RELOC_ARM_THUMB_OFFSET
:
23206 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23207 case BFD_RELOC_ARM_T32_ADD_PC12
:
23208 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23209 return (base
+ 4) & ~3;
23211 /* Thumb branches are simply offset by +4. */
23212 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
23213 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23214 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23215 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23216 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23217 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23218 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
23219 case BFD_RELOC_ARM_THUMB_BF17
:
23220 case BFD_RELOC_ARM_THUMB_BF19
:
23221 case BFD_RELOC_ARM_THUMB_BF13
:
23222 case BFD_RELOC_ARM_THUMB_LOOP12
:
23225 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23227 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23228 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23229 && ARM_IS_FUNC (fixP
->fx_addsy
)
23230 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23231 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23234 /* BLX is like branches above, but forces the low two bits of PC to
23236 case BFD_RELOC_THUMB_PCREL_BLX
:
23238 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23239 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23240 && THUMB_IS_FUNC (fixP
->fx_addsy
)
23241 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23242 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23243 return (base
+ 4) & ~3;
23245 /* ARM mode branches are offset by +8. However, the Windows CE
23246 loader expects the relocation not to take this into account. */
23247 case BFD_RELOC_ARM_PCREL_BLX
:
23249 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23250 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23251 && ARM_IS_FUNC (fixP
->fx_addsy
)
23252 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23253 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23256 case BFD_RELOC_ARM_PCREL_CALL
:
23258 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23259 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23260 && THUMB_IS_FUNC (fixP
->fx_addsy
)
23261 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23262 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23265 case BFD_RELOC_ARM_PCREL_BRANCH
:
23266 case BFD_RELOC_ARM_PCREL_JUMP
:
23267 case BFD_RELOC_ARM_PLT32
:
23269 /* When handling fixups immediately, because we have already
23270 discovered the value of a symbol, or the address of the frag involved
23271 we must account for the offset by +8, as the OS loader will never see the reloc.
23272 see fixup_segment() in write.c
23273 The S_IS_EXTERNAL test handles the case of global symbols.
23274 Those need the calculated base, not just the pipe compensation the linker will need. */
23276 && fixP
->fx_addsy
!= NULL
23277 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23278 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
23286 /* ARM mode loads relative to PC are also offset by +8. Unlike
23287 branches, the Windows CE loader *does* expect the relocation
23288 to take this into account. */
23289 case BFD_RELOC_ARM_OFFSET_IMM
:
23290 case BFD_RELOC_ARM_OFFSET_IMM8
:
23291 case BFD_RELOC_ARM_HWLITERAL
:
23292 case BFD_RELOC_ARM_LITERAL
:
23293 case BFD_RELOC_ARM_CP_OFF_IMM
:
23297 /* Other PC-relative relocations are un-offset. */
23303 static bfd_boolean flag_warn_syms
= TRUE
;
23306 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
23308 /* PR 18347 - Warn if the user attempts to create a symbol with the same
23309 name as an ARM instruction. Whilst strictly speaking it is allowed, it
23310 does mean that the resulting code might be very confusing to the reader.
23311 Also this warning can be triggered if the user omits an operand before
23312 an immediate address, eg:
23316 GAS treats this as an assignment of the value of the symbol foo to a
23317 symbol LDR, and so (without this code) it will not issue any kind of
23318 warning or error message.
23320 Note - ARM instructions are case-insensitive but the strings in the hash
23321 table are all stored in lower case, so we must first ensure that name is
23323 if (flag_warn_syms
&& arm_ops_hsh
)
23325 char * nbuf
= strdup (name
);
23328 for (p
= nbuf
; *p
; p
++)
23330 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
23332 static struct hash_control
* already_warned
= NULL
;
23334 if (already_warned
== NULL
)
23335 already_warned
= hash_new ();
23336 /* Only warn about the symbol once. To keep the code
23337 simple we let hash_insert do the lookup for us. */
23338 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
23339 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
23348 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
23349 Otherwise we have no need to default values of symbols. */
23352 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
23355 if (name
[0] == '_' && name
[1] == 'G'
23356 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
23360 if (symbol_find (name
))
23361 as_bad (_("GOT already in the symbol table"));
23363 GOT_symbol
= symbol_new (name
, undefined_section
,
23364 (valueT
) 0, & zero_address_frag
);
23374 /* Subroutine of md_apply_fix. Check to see if an immediate can be
23375 computed as two separate immediate values, added together. We
23376 already know that this value cannot be computed by just one ARM
23379 static unsigned int
23380 validate_immediate_twopart (unsigned int val
,
23381 unsigned int * highpart
)
23386 for (i
= 0; i
< 32; i
+= 2)
23387 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
23393 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
23395 else if (a
& 0xff0000)
23397 if (a
& 0xff000000)
23399 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
23403 gas_assert (a
& 0xff000000);
23404 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
23407 return (a
& 0xff) | (i
<< 7);
23414 validate_offset_imm (unsigned int val
, int hwse
)
23416 if ((hwse
&& val
> 255) || val
> 4095)
23421 /* Subroutine of md_apply_fix. Do those data_ops which can take a
23422 negative immediate constant by altering the instruction. A bit of
23427 by inverting the second operand, and
23430 by negating the second operand. */
23433 negate_data_op (unsigned long * instruction
,
23434 unsigned long value
)
23437 unsigned long negated
, inverted
;
23439 negated
= encode_arm_immediate (-value
);
23440 inverted
= encode_arm_immediate (~value
);
23442 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
23445 /* First negates. */
23446 case OPCODE_SUB
: /* ADD <-> SUB */
23447 new_inst
= OPCODE_ADD
;
23452 new_inst
= OPCODE_SUB
;
23456 case OPCODE_CMP
: /* CMP <-> CMN */
23457 new_inst
= OPCODE_CMN
;
23462 new_inst
= OPCODE_CMP
;
23466 /* Now Inverted ops. */
23467 case OPCODE_MOV
: /* MOV <-> MVN */
23468 new_inst
= OPCODE_MVN
;
23473 new_inst
= OPCODE_MOV
;
23477 case OPCODE_AND
: /* AND <-> BIC */
23478 new_inst
= OPCODE_BIC
;
23483 new_inst
= OPCODE_AND
;
23487 case OPCODE_ADC
: /* ADC <-> SBC */
23488 new_inst
= OPCODE_SBC
;
23493 new_inst
= OPCODE_ADC
;
23497 /* We cannot do anything. */
23502 if (value
== (unsigned) FAIL
)
23505 *instruction
&= OPCODE_MASK
;
23506 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
23510 /* Like negate_data_op, but for Thumb-2. */
23512 static unsigned int
23513 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
23517 unsigned int negated
, inverted
;
23519 negated
= encode_thumb32_immediate (-value
);
23520 inverted
= encode_thumb32_immediate (~value
);
23522 rd
= (*instruction
>> 8) & 0xf;
23523 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
23526 /* ADD <-> SUB. Includes CMP <-> CMN. */
23527 case T2_OPCODE_SUB
:
23528 new_inst
= T2_OPCODE_ADD
;
23532 case T2_OPCODE_ADD
:
23533 new_inst
= T2_OPCODE_SUB
;
23537 /* ORR <-> ORN. Includes MOV <-> MVN. */
23538 case T2_OPCODE_ORR
:
23539 new_inst
= T2_OPCODE_ORN
;
23543 case T2_OPCODE_ORN
:
23544 new_inst
= T2_OPCODE_ORR
;
23548 /* AND <-> BIC. TST has no inverted equivalent. */
23549 case T2_OPCODE_AND
:
23550 new_inst
= T2_OPCODE_BIC
;
23557 case T2_OPCODE_BIC
:
23558 new_inst
= T2_OPCODE_AND
;
23563 case T2_OPCODE_ADC
:
23564 new_inst
= T2_OPCODE_SBC
;
23568 case T2_OPCODE_SBC
:
23569 new_inst
= T2_OPCODE_ADC
;
23573 /* We cannot do anything. */
23578 if (value
== (unsigned int)FAIL
)
23581 *instruction
&= T2_OPCODE_MASK
;
23582 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
23586 /* Read a 32-bit thumb instruction from buf. */
23588 static unsigned long
23589 get_thumb32_insn (char * buf
)
23591 unsigned long insn
;
23592 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
23593 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23598 /* We usually want to set the low bit on the address of thumb function
23599 symbols. In particular .word foo - . should have the low bit set.
23600 Generic code tries to fold the difference of two symbols to
23601 a constant. Prevent this and force a relocation when the first symbols
23602 is a thumb function. */
23605 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
23607 if (op
== O_subtract
23608 && l
->X_op
== O_symbol
23609 && r
->X_op
== O_symbol
23610 && THUMB_IS_FUNC (l
->X_add_symbol
))
23612 l
->X_op
= O_subtract
;
23613 l
->X_op_symbol
= r
->X_add_symbol
;
23614 l
->X_add_number
-= r
->X_add_number
;
23618 /* Process as normal. */
23622 /* Encode Thumb2 unconditional branches and calls. The encoding
23623 for the 2 are identical for the immediate values. */
23626 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
23628 #define T2I1I2MASK ((1 << 13) | (1 << 11))
23631 addressT S
, I1
, I2
, lo
, hi
;
23633 S
= (value
>> 24) & 0x01;
23634 I1
= (value
>> 23) & 0x01;
23635 I2
= (value
>> 22) & 0x01;
23636 hi
= (value
>> 12) & 0x3ff;
23637 lo
= (value
>> 1) & 0x7ff;
23638 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23639 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23640 newval
|= (S
<< 10) | hi
;
23641 newval2
&= ~T2I1I2MASK
;
23642 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
23643 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23644 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23648 md_apply_fix (fixS
* fixP
,
23652 offsetT value
= * valP
;
23654 unsigned int newimm
;
23655 unsigned long temp
;
23657 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
23659 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
23661 /* Note whether this will delete the relocation. */
23663 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
23666 /* On a 64-bit host, silently truncate 'value' to 32 bits for
23667 consistency with the behaviour on 32-bit hosts. Remember value
23669 value
&= 0xffffffff;
23670 value
^= 0x80000000;
23671 value
-= 0x80000000;
23674 fixP
->fx_addnumber
= value
;
23676 /* Same treatment for fixP->fx_offset. */
23677 fixP
->fx_offset
&= 0xffffffff;
23678 fixP
->fx_offset
^= 0x80000000;
23679 fixP
->fx_offset
-= 0x80000000;
23681 switch (fixP
->fx_r_type
)
23683 case BFD_RELOC_NONE
:
23684 /* This will need to go in the object file. */
23688 case BFD_RELOC_ARM_IMMEDIATE
:
23689 /* We claim that this fixup has been processed here,
23690 even if in fact we generate an error because we do
23691 not have a reloc for it, so tc_gen_reloc will reject it. */
23694 if (fixP
->fx_addsy
)
23696 const char *msg
= 0;
23698 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23699 msg
= _("undefined symbol %s used as an immediate value");
23700 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23701 msg
= _("symbol %s is in a different section");
23702 else if (S_IS_WEAK (fixP
->fx_addsy
))
23703 msg
= _("symbol %s is weak and may be overridden later");
23707 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23708 msg
, S_GET_NAME (fixP
->fx_addsy
));
23713 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23715 /* If the offset is negative, we should use encoding A2 for ADR. */
23716 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23717 newimm
= negate_data_op (&temp
, value
);
23720 newimm
= encode_arm_immediate (value
);
23722 /* If the instruction will fail, see if we can fix things up by
23723 changing the opcode. */
23724 if (newimm
== (unsigned int) FAIL
)
23725 newimm
= negate_data_op (&temp
, value
);
23726 /* MOV accepts both ARM modified immediate (A1 encoding) and
23727 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23728 When disassembling, MOV is preferred when there is no encoding
23730 if (newimm
== (unsigned int) FAIL
23731 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23732 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23733 && !((temp
>> SBIT_SHIFT
) & 0x1)
23734 && value
>= 0 && value
<= 0xffff)
23736 /* Clear bits[23:20] to change encoding from A1 to A2. */
23737 temp
&= 0xff0fffff;
23738 /* Encoding high 4bits imm. Code below will encode the remaining
23740 temp
|= (value
& 0x0000f000) << 4;
23741 newimm
= value
& 0x00000fff;
23745 if (newimm
== (unsigned int) FAIL
)
23747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23748 _("invalid constant (%lx) after fixup"),
23749 (unsigned long) value
);
23753 newimm
|= (temp
& 0xfffff000);
23754 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23757 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23759 unsigned int highpart
= 0;
23760 unsigned int newinsn
= 0xe1a00000; /* nop. */
23762 if (fixP
->fx_addsy
)
23764 const char *msg
= 0;
23766 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23767 msg
= _("undefined symbol %s used as an immediate value");
23768 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23769 msg
= _("symbol %s is in a different section");
23770 else if (S_IS_WEAK (fixP
->fx_addsy
))
23771 msg
= _("symbol %s is weak and may be overridden later");
23775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23776 msg
, S_GET_NAME (fixP
->fx_addsy
));
23781 newimm
= encode_arm_immediate (value
);
23782 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23784 /* If the instruction will fail, see if we can fix things up by
23785 changing the opcode. */
23786 if (newimm
== (unsigned int) FAIL
23787 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23789 /* No ? OK - try using two ADD instructions to generate
23791 newimm
= validate_immediate_twopart (value
, & highpart
);
23793 /* Yes - then make sure that the second instruction is
23795 if (newimm
!= (unsigned int) FAIL
)
23797 /* Still No ? Try using a negated value. */
23798 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23799 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23800 /* Otherwise - give up. */
23803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23804 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23809 /* Replace the first operand in the 2nd instruction (which
23810 is the PC) with the destination register. We have
23811 already added in the PC in the first instruction and we
23812 do not want to do it again. */
23813 newinsn
&= ~ 0xf0000;
23814 newinsn
|= ((newinsn
& 0x0f000) << 4);
23817 newimm
|= (temp
& 0xfffff000);
23818 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23820 highpart
|= (newinsn
& 0xfffff000);
23821 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23825 case BFD_RELOC_ARM_OFFSET_IMM
:
23826 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23828 /* Fall through. */
23830 case BFD_RELOC_ARM_LITERAL
:
23836 if (validate_offset_imm (value
, 0) == FAIL
)
23838 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23839 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23840 _("invalid literal constant: pool needs to be closer"));
23842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23843 _("bad immediate value for offset (%ld)"),
23848 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23850 newval
&= 0xfffff000;
23853 newval
&= 0xff7ff000;
23854 newval
|= value
| (sign
? INDEX_UP
: 0);
23856 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23859 case BFD_RELOC_ARM_OFFSET_IMM8
:
23860 case BFD_RELOC_ARM_HWLITERAL
:
23866 if (validate_offset_imm (value
, 1) == FAIL
)
23868 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23869 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23870 _("invalid literal constant: pool needs to be closer"));
23872 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23873 _("bad immediate value for 8-bit offset (%ld)"),
23878 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23880 newval
&= 0xfffff0f0;
23883 newval
&= 0xff7ff0f0;
23884 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23886 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23889 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23890 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23891 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23892 _("bad immediate value for offset (%ld)"), (long) value
);
23895 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23897 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23900 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23901 /* This is a complicated relocation used for all varieties of Thumb32
23902 load/store instruction with immediate offset:
23904 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23905 *4, optional writeback(W)
23906 (doubleword load/store)
23908 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23909 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23910 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23911 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23912 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23914 Uppercase letters indicate bits that are already encoded at
23915 this point. Lowercase letters are our problem. For the
23916 second block of instructions, the secondary opcode nybble
23917 (bits 8..11) is present, and bit 23 is zero, even if this is
23918 a PC-relative operation. */
23919 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23921 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23923 if ((newval
& 0xf0000000) == 0xe0000000)
23925 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23927 newval
|= (1 << 23);
23930 if (value
% 4 != 0)
23932 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23933 _("offset not a multiple of 4"));
23939 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23940 _("offset out of range"));
23945 else if ((newval
& 0x000f0000) == 0x000f0000)
23947 /* PC-relative, 12-bit offset. */
23949 newval
|= (1 << 23);
23954 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23955 _("offset out of range"));
23960 else if ((newval
& 0x00000100) == 0x00000100)
23962 /* Writeback: 8-bit, +/- offset. */
23964 newval
|= (1 << 9);
23969 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23970 _("offset out of range"));
23975 else if ((newval
& 0x00000f00) == 0x00000e00)
23977 /* T-instruction: positive 8-bit offset. */
23978 if (value
< 0 || value
> 0xff)
23980 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23981 _("offset out of range"));
23989 /* Positive 12-bit or negative 8-bit offset. */
23993 newval
|= (1 << 23);
24003 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24004 _("offset out of range"));
24011 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
24012 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
24015 case BFD_RELOC_ARM_SHIFT_IMM
:
24016 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24017 if (((unsigned long) value
) > 32
24019 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
24021 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24022 _("shift expression is too large"));
24027 /* Shifts of zero must be done as lsl. */
24029 else if (value
== 32)
24031 newval
&= 0xfffff07f;
24032 newval
|= (value
& 0x1f) << 7;
24033 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24036 case BFD_RELOC_ARM_T32_IMMEDIATE
:
24037 case BFD_RELOC_ARM_T32_ADD_IMM
:
24038 case BFD_RELOC_ARM_T32_IMM12
:
24039 case BFD_RELOC_ARM_T32_ADD_PC12
:
24040 /* We claim that this fixup has been processed here,
24041 even if in fact we generate an error because we do
24042 not have a reloc for it, so tc_gen_reloc will reject it. */
24046 && ! S_IS_DEFINED (fixP
->fx_addsy
))
24048 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24049 _("undefined symbol %s used as an immediate value"),
24050 S_GET_NAME (fixP
->fx_addsy
));
24054 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24056 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
24059 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24060 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
24061 Thumb2 modified immediate encoding (T2). */
24062 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
24063 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
24065 newimm
= encode_thumb32_immediate (value
);
24066 if (newimm
== (unsigned int) FAIL
)
24067 newimm
= thumb32_negate_data_op (&newval
, value
);
24069 if (newimm
== (unsigned int) FAIL
)
24071 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
24073 /* Turn add/sum into addw/subw. */
24074 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
24075 newval
= (newval
& 0xfeffffff) | 0x02000000;
24076 /* No flat 12-bit imm encoding for addsw/subsw. */
24077 if ((newval
& 0x00100000) == 0)
24079 /* 12 bit immediate for addw/subw. */
24083 newval
^= 0x00a00000;
24086 newimm
= (unsigned int) FAIL
;
24093 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
24094 UINT16 (T3 encoding), MOVW only accepts UINT16. When
24095 disassembling, MOV is preferred when there is no encoding
24097 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
24098 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
24099 but with the Rn field [19:16] set to 1111. */
24100 && (((newval
>> 16) & 0xf) == 0xf)
24101 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
24102 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
24103 && value
>= 0 && value
<= 0xffff)
24105 /* Toggle bit[25] to change encoding from T2 to T3. */
24107 /* Clear bits[19:16]. */
24108 newval
&= 0xfff0ffff;
24109 /* Encoding high 4bits imm. Code below will encode the
24110 remaining low 12bits. */
24111 newval
|= (value
& 0x0000f000) << 4;
24112 newimm
= value
& 0x00000fff;
24117 if (newimm
== (unsigned int)FAIL
)
24119 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24120 _("invalid constant (%lx) after fixup"),
24121 (unsigned long) value
);
24125 newval
|= (newimm
& 0x800) << 15;
24126 newval
|= (newimm
& 0x700) << 4;
24127 newval
|= (newimm
& 0x0ff);
24129 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
24130 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
24133 case BFD_RELOC_ARM_SMC
:
24134 if (((unsigned long) value
) > 0xffff)
24135 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24136 _("invalid smc expression"));
24137 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24138 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
24139 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24142 case BFD_RELOC_ARM_HVC
:
24143 if (((unsigned long) value
) > 0xffff)
24144 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24145 _("invalid hvc expression"));
24146 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24147 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
24148 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24151 case BFD_RELOC_ARM_SWI
:
24152 if (fixP
->tc_fix_data
!= 0)
24154 if (((unsigned long) value
) > 0xff)
24155 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24156 _("invalid swi expression"));
24157 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24159 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24163 if (((unsigned long) value
) > 0x00ffffff)
24164 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24165 _("invalid swi expression"));
24166 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24168 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24172 case BFD_RELOC_ARM_MULTI
:
24173 if (((unsigned long) value
) > 0xffff)
24174 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24175 _("invalid expression in load/store multiple"));
24176 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
24177 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24181 case BFD_RELOC_ARM_PCREL_CALL
:
24183 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24185 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24186 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24187 && THUMB_IS_FUNC (fixP
->fx_addsy
))
24188 /* Flip the bl to blx. This is a simple flip
24189 bit here because we generate PCREL_CALL for
24190 unconditional bls. */
24192 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24193 newval
= newval
| 0x10000000;
24194 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24200 goto arm_branch_common
;
24202 case BFD_RELOC_ARM_PCREL_JUMP
:
24203 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24205 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24206 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24207 && THUMB_IS_FUNC (fixP
->fx_addsy
))
24209 /* This would map to a bl<cond>, b<cond>,
24210 b<always> to a Thumb function. We
24211 need to force a relocation for this particular
24213 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24216 /* Fall through. */
24218 case BFD_RELOC_ARM_PLT32
:
24220 case BFD_RELOC_ARM_PCREL_BRANCH
:
24222 goto arm_branch_common
;
24224 case BFD_RELOC_ARM_PCREL_BLX
:
24227 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24229 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24230 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24231 && ARM_IS_FUNC (fixP
->fx_addsy
))
24233 /* Flip the blx to a bl and warn. */
24234 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
24235 newval
= 0xeb000000;
24236 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
24237 _("blx to '%s' an ARM ISA state function changed to bl"),
24239 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24245 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24246 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
24250 /* We are going to store value (shifted right by two) in the
24251 instruction, in a 24 bit, signed field. Bits 26 through 32 either
24252 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
24255 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24256 _("misaligned branch destination"));
24257 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
24258 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
24259 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24261 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24263 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24264 newval
|= (value
>> 2) & 0x00ffffff;
24265 /* Set the H bit on BLX instructions. */
24269 newval
|= 0x01000000;
24271 newval
&= ~0x01000000;
24273 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24277 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
24278 /* CBZ can only branch forward. */
24280 /* Attempts to use CBZ to branch to the next instruction
24281 (which, strictly speaking, are prohibited) will be turned into
24284 FIXME: It may be better to remove the instruction completely and
24285 perform relaxation. */
24288 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24289 newval
= 0xbf00; /* NOP encoding T1 */
24290 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24295 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24297 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24299 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24300 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
24301 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24306 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
24307 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
24308 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24310 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24312 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24313 newval
|= (value
& 0x1ff) >> 1;
24314 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24318 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
24319 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
24320 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24322 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24324 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24325 newval
|= (value
& 0xfff) >> 1;
24326 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24330 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24332 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24333 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24334 && ARM_IS_FUNC (fixP
->fx_addsy
)
24335 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
24337 /* Force a relocation for a branch 20 bits wide. */
24340 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
24341 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24342 _("conditional branch out of range"));
24344 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24347 addressT S
, J1
, J2
, lo
, hi
;
24349 S
= (value
& 0x00100000) >> 20;
24350 J2
= (value
& 0x00080000) >> 19;
24351 J1
= (value
& 0x00040000) >> 18;
24352 hi
= (value
& 0x0003f000) >> 12;
24353 lo
= (value
& 0x00000ffe) >> 1;
24355 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24356 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24357 newval
|= (S
<< 10) | hi
;
24358 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
24359 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24360 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
24364 case BFD_RELOC_THUMB_PCREL_BLX
:
24365 /* If there is a blx from a thumb state function to
24366 another thumb function flip this to a bl and warn
24370 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24371 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24372 && THUMB_IS_FUNC (fixP
->fx_addsy
))
24374 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
24375 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
24376 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
24378 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24379 newval
= newval
| 0x1000;
24380 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
24381 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24386 goto thumb_bl_common
;
24388 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24389 /* A bl from Thumb state ISA to an internal ARM state function
24390 is converted to a blx. */
24392 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24393 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24394 && ARM_IS_FUNC (fixP
->fx_addsy
)
24395 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
24397 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24398 newval
= newval
& ~0x1000;
24399 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
24400 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
24406 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
24407 /* For a BLX instruction, make sure that the relocation is rounded up
24408 to a word boundary. This follows the semantics of the instruction
24409 which specifies that bit 1 of the target address will come from bit
24410 1 of the base address. */
24411 value
= (value
+ 3) & ~ 3;
24414 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
24415 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
24416 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24419 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
24421 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
24422 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24423 else if ((value
& ~0x1ffffff)
24424 && ((value
& ~0x1ffffff) != ~0x1ffffff))
24425 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24426 _("Thumb2 branch out of range"));
24429 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24430 encode_thumb2_b_bl_offset (buf
, value
);
24434 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24435 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
24436 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24438 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24439 encode_thumb2_b_bl_offset (buf
, value
);
24444 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24449 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24450 md_number_to_chars (buf
, value
, 2);
24454 case BFD_RELOC_ARM_TLS_CALL
:
24455 case BFD_RELOC_ARM_THM_TLS_CALL
:
24456 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24457 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24458 case BFD_RELOC_ARM_TLS_GOTDESC
:
24459 case BFD_RELOC_ARM_TLS_GD32
:
24460 case BFD_RELOC_ARM_TLS_LE32
:
24461 case BFD_RELOC_ARM_TLS_IE32
:
24462 case BFD_RELOC_ARM_TLS_LDM32
:
24463 case BFD_RELOC_ARM_TLS_LDO32
:
24464 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24467 /* Same handling as above, but with the arm_fdpic guard. */
24468 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
24469 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
24470 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
24473 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24477 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24478 _("Relocation supported only in FDPIC mode"));
24482 case BFD_RELOC_ARM_GOT32
:
24483 case BFD_RELOC_ARM_GOTOFF
:
24486 case BFD_RELOC_ARM_GOT_PREL
:
24487 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24488 md_number_to_chars (buf
, value
, 4);
24491 case BFD_RELOC_ARM_TARGET2
:
24492 /* TARGET2 is not partial-inplace, so we need to write the
24493 addend here for REL targets, because it won't be written out
24494 during reloc processing later. */
24495 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24496 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
24499 /* Relocations for FDPIC. */
24500 case BFD_RELOC_ARM_GOTFUNCDESC
:
24501 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
24502 case BFD_RELOC_ARM_FUNCDESC
:
24505 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24506 md_number_to_chars (buf
, 0, 4);
24510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24511 _("Relocation supported only in FDPIC mode"));
24516 case BFD_RELOC_RVA
:
24518 case BFD_RELOC_ARM_TARGET1
:
24519 case BFD_RELOC_ARM_ROSEGREL32
:
24520 case BFD_RELOC_ARM_SBREL32
:
24521 case BFD_RELOC_32_PCREL
:
24523 case BFD_RELOC_32_SECREL
:
24525 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24527 /* For WinCE we only do this for pcrel fixups. */
24528 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
24530 md_number_to_chars (buf
, value
, 4);
24534 case BFD_RELOC_ARM_PREL31
:
24535 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24537 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
24538 if ((value
^ (value
>> 1)) & 0x40000000)
24540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24541 _("rel31 relocation overflow"));
24543 newval
|= value
& 0x7fffffff;
24544 md_number_to_chars (buf
, newval
, 4);
24549 case BFD_RELOC_ARM_CP_OFF_IMM
:
24550 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
24551 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
24552 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24554 newval
= get_thumb32_insn (buf
);
24555 if ((newval
& 0x0f200f00) == 0x0d000900)
24557 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
24558 has permitted values that are multiples of 2, in the range 0
24560 if (value
< -510 || value
> 510 || (value
& 1))
24561 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24562 _("co-processor offset out of range"));
24564 else if (value
< -1023 || value
> 1023 || (value
& 3))
24565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24566 _("co-processor offset out of range"));
24571 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24572 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24573 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24575 newval
= get_thumb32_insn (buf
);
24577 newval
&= 0xffffff00;
24580 newval
&= 0xff7fff00;
24581 if ((newval
& 0x0f200f00) == 0x0d000900)
24583 /* This is a fp16 vstr/vldr.
24585 It requires the immediate offset in the instruction is shifted
24586 left by 1 to be a half-word offset.
24588 Here, left shift by 1 first, and later right shift by 2
24589 should get the right offset. */
24592 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
24594 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24595 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24596 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24598 put_thumb32_insn (buf
, newval
);
24601 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
24602 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
24603 if (value
< -255 || value
> 255)
24604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24605 _("co-processor offset out of range"));
24607 goto cp_off_common
;
24609 case BFD_RELOC_ARM_THUMB_OFFSET
:
24610 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24611 /* Exactly what ranges, and where the offset is inserted depends
24612 on the type of instruction, we can establish this from the
24614 switch (newval
>> 12)
24616 case 4: /* PC load. */
24617 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
24618 forced to zero for these loads; md_pcrel_from has already
24619 compensated for this. */
24621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24622 _("invalid offset, target not word aligned (0x%08lX)"),
24623 (((unsigned long) fixP
->fx_frag
->fr_address
24624 + (unsigned long) fixP
->fx_where
) & ~3)
24625 + (unsigned long) value
);
24627 if (value
& ~0x3fc)
24628 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24629 _("invalid offset, value too big (0x%08lX)"),
24632 newval
|= value
>> 2;
24635 case 9: /* SP load/store. */
24636 if (value
& ~0x3fc)
24637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24638 _("invalid offset, value too big (0x%08lX)"),
24640 newval
|= value
>> 2;
24643 case 6: /* Word load/store. */
24645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24646 _("invalid offset, value too big (0x%08lX)"),
24648 newval
|= value
<< 4; /* 6 - 2. */
24651 case 7: /* Byte load/store. */
24653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24654 _("invalid offset, value too big (0x%08lX)"),
24656 newval
|= value
<< 6;
24659 case 8: /* Halfword load/store. */
24661 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24662 _("invalid offset, value too big (0x%08lX)"),
24664 newval
|= value
<< 5; /* 6 - 1. */
24668 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24669 "Unable to process relocation for thumb opcode: %lx",
24670 (unsigned long) newval
);
24673 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24676 case BFD_RELOC_ARM_THUMB_ADD
:
24677 /* This is a complicated relocation, since we use it for all of
24678 the following immediate relocations:
24682 9bit ADD/SUB SP word-aligned
24683 10bit ADD PC/SP word-aligned
24685 The type of instruction being processed is encoded in the
24692 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24694 int rd
= (newval
>> 4) & 0xf;
24695 int rs
= newval
& 0xf;
24696 int subtract
= !!(newval
& 0x8000);
24698 /* Check for HI regs, only very restricted cases allowed:
24699 Adjusting SP, and using PC or SP to get an address. */
24700 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
24701 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
24702 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24703 _("invalid Hi register with immediate"));
24705 /* If value is negative, choose the opposite instruction. */
24709 subtract
= !subtract
;
24711 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24712 _("immediate value out of range"));
24717 if (value
& ~0x1fc)
24718 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24719 _("invalid immediate for stack address calculation"));
24720 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
24721 newval
|= value
>> 2;
24723 else if (rs
== REG_PC
|| rs
== REG_SP
)
24725 /* PR gas/18541. If the addition is for a defined symbol
24726 within range of an ADR instruction then accept it. */
24729 && fixP
->fx_addsy
!= NULL
)
24733 if (! S_IS_DEFINED (fixP
->fx_addsy
)
24734 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
24735 || S_IS_WEAK (fixP
->fx_addsy
))
24737 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24738 _("address calculation needs a strongly defined nearby symbol"));
24742 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24744 /* Round up to the next 4-byte boundary. */
24749 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24754 _("symbol too far away"));
24764 if (subtract
|| value
& ~0x3fc)
24765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24766 _("invalid immediate for address calculation (value = 0x%08lX)"),
24767 (unsigned long) (subtract
? - value
: value
));
24768 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24770 newval
|= value
>> 2;
24775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24776 _("immediate value out of range"));
24777 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24778 newval
|= (rd
<< 8) | value
;
24783 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24784 _("immediate value out of range"));
24785 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24786 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24789 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24792 case BFD_RELOC_ARM_THUMB_IMM
:
24793 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24794 if (value
< 0 || value
> 255)
24795 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24796 _("invalid immediate: %ld is out of range"),
24799 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24802 case BFD_RELOC_ARM_THUMB_SHIFT
:
24803 /* 5bit shift value (0..32). LSL cannot take 32. */
24804 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24805 temp
= newval
& 0xf800;
24806 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24807 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24808 _("invalid shift value: %ld"), (long) value
);
24809 /* Shifts of zero must be encoded as LSL. */
24811 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24812 /* Shifts of 32 are encoded as zero. */
24813 else if (value
== 32)
24815 newval
|= value
<< 6;
24816 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24819 case BFD_RELOC_VTABLE_INHERIT
:
24820 case BFD_RELOC_VTABLE_ENTRY
:
24824 case BFD_RELOC_ARM_MOVW
:
24825 case BFD_RELOC_ARM_MOVT
:
24826 case BFD_RELOC_ARM_THUMB_MOVW
:
24827 case BFD_RELOC_ARM_THUMB_MOVT
:
24828 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24830 /* REL format relocations are limited to a 16-bit addend. */
24831 if (!fixP
->fx_done
)
24833 if (value
< -0x8000 || value
> 0x7fff)
24834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24835 _("offset out of range"));
24837 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24838 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24843 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24844 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24846 newval
= get_thumb32_insn (buf
);
24847 newval
&= 0xfbf08f00;
24848 newval
|= (value
& 0xf000) << 4;
24849 newval
|= (value
& 0x0800) << 15;
24850 newval
|= (value
& 0x0700) << 4;
24851 newval
|= (value
& 0x00ff);
24852 put_thumb32_insn (buf
, newval
);
24856 newval
= md_chars_to_number (buf
, 4);
24857 newval
&= 0xfff0f000;
24858 newval
|= value
& 0x0fff;
24859 newval
|= (value
& 0xf000) << 4;
24860 md_number_to_chars (buf
, newval
, 4);
24865 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24866 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24867 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24868 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24869 gas_assert (!fixP
->fx_done
);
24872 bfd_boolean is_mov
;
24873 bfd_vma encoded_addend
= value
;
24875 /* Check that addend can be encoded in instruction. */
24876 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24877 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24878 _("the offset 0x%08lX is not representable"),
24879 (unsigned long) encoded_addend
);
24881 /* Extract the instruction. */
24882 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24883 is_mov
= (insn
& 0xf800) == 0x2000;
24888 if (!seg
->use_rela_p
)
24889 insn
|= encoded_addend
;
24895 /* Extract the instruction. */
24896 /* Encoding is the following
24901 /* The following conditions must be true :
24906 rd
= (insn
>> 4) & 0xf;
24908 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24909 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24910 _("Unable to process relocation for thumb opcode: %lx"),
24911 (unsigned long) insn
);
24913 /* Encode as ADD immediate8 thumb 1 code. */
24914 insn
= 0x3000 | (rd
<< 8);
24916 /* Place the encoded addend into the first 8 bits of the
24918 if (!seg
->use_rela_p
)
24919 insn
|= encoded_addend
;
24922 /* Update the instruction. */
24923 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24927 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24928 case BFD_RELOC_ARM_ALU_PC_G0
:
24929 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24930 case BFD_RELOC_ARM_ALU_PC_G1
:
24931 case BFD_RELOC_ARM_ALU_PC_G2
:
24932 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24933 case BFD_RELOC_ARM_ALU_SB_G0
:
24934 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24935 case BFD_RELOC_ARM_ALU_SB_G1
:
24936 case BFD_RELOC_ARM_ALU_SB_G2
:
24937 gas_assert (!fixP
->fx_done
);
24938 if (!seg
->use_rela_p
)
24941 bfd_vma encoded_addend
;
24942 bfd_vma addend_abs
= llabs (value
);
24944 /* Check that the absolute value of the addend can be
24945 expressed as an 8-bit constant plus a rotation. */
24946 encoded_addend
= encode_arm_immediate (addend_abs
);
24947 if (encoded_addend
== (unsigned int) FAIL
)
24948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24949 _("the offset 0x%08lX is not representable"),
24950 (unsigned long) addend_abs
);
24952 /* Extract the instruction. */
24953 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24955 /* If the addend is positive, use an ADD instruction.
24956 Otherwise use a SUB. Take care not to destroy the S bit. */
24957 insn
&= 0xff1fffff;
24963 /* Place the encoded addend into the first 12 bits of the
24965 insn
&= 0xfffff000;
24966 insn
|= encoded_addend
;
24968 /* Update the instruction. */
24969 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24973 case BFD_RELOC_ARM_LDR_PC_G0
:
24974 case BFD_RELOC_ARM_LDR_PC_G1
:
24975 case BFD_RELOC_ARM_LDR_PC_G2
:
24976 case BFD_RELOC_ARM_LDR_SB_G0
:
24977 case BFD_RELOC_ARM_LDR_SB_G1
:
24978 case BFD_RELOC_ARM_LDR_SB_G2
:
24979 gas_assert (!fixP
->fx_done
);
24980 if (!seg
->use_rela_p
)
24983 bfd_vma addend_abs
= llabs (value
);
24985 /* Check that the absolute value of the addend can be
24986 encoded in 12 bits. */
24987 if (addend_abs
>= 0x1000)
24988 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24989 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24990 (unsigned long) addend_abs
);
24992 /* Extract the instruction. */
24993 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24995 /* If the addend is negative, clear bit 23 of the instruction.
24996 Otherwise set it. */
24998 insn
&= ~(1 << 23);
25002 /* Place the absolute value of the addend into the first 12 bits
25003 of the instruction. */
25004 insn
&= 0xfffff000;
25005 insn
|= addend_abs
;
25007 /* Update the instruction. */
25008 md_number_to_chars (buf
, insn
, INSN_SIZE
);
25012 case BFD_RELOC_ARM_LDRS_PC_G0
:
25013 case BFD_RELOC_ARM_LDRS_PC_G1
:
25014 case BFD_RELOC_ARM_LDRS_PC_G2
:
25015 case BFD_RELOC_ARM_LDRS_SB_G0
:
25016 case BFD_RELOC_ARM_LDRS_SB_G1
:
25017 case BFD_RELOC_ARM_LDRS_SB_G2
:
25018 gas_assert (!fixP
->fx_done
);
25019 if (!seg
->use_rela_p
)
25022 bfd_vma addend_abs
= llabs (value
);
25024 /* Check that the absolute value of the addend can be
25025 encoded in 8 bits. */
25026 if (addend_abs
>= 0x100)
25027 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25028 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
25029 (unsigned long) addend_abs
);
25031 /* Extract the instruction. */
25032 insn
= md_chars_to_number (buf
, INSN_SIZE
);
25034 /* If the addend is negative, clear bit 23 of the instruction.
25035 Otherwise set it. */
25037 insn
&= ~(1 << 23);
25041 /* Place the first four bits of the absolute value of the addend
25042 into the first 4 bits of the instruction, and the remaining
25043 four into bits 8 .. 11. */
25044 insn
&= 0xfffff0f0;
25045 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
25047 /* Update the instruction. */
25048 md_number_to_chars (buf
, insn
, INSN_SIZE
);
25052 case BFD_RELOC_ARM_LDC_PC_G0
:
25053 case BFD_RELOC_ARM_LDC_PC_G1
:
25054 case BFD_RELOC_ARM_LDC_PC_G2
:
25055 case BFD_RELOC_ARM_LDC_SB_G0
:
25056 case BFD_RELOC_ARM_LDC_SB_G1
:
25057 case BFD_RELOC_ARM_LDC_SB_G2
:
25058 gas_assert (!fixP
->fx_done
);
25059 if (!seg
->use_rela_p
)
25062 bfd_vma addend_abs
= llabs (value
);
25064 /* Check that the absolute value of the addend is a multiple of
25065 four and, when divided by four, fits in 8 bits. */
25066 if (addend_abs
& 0x3)
25067 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25068 _("bad offset 0x%08lX (must be word-aligned)"),
25069 (unsigned long) addend_abs
);
25071 if ((addend_abs
>> 2) > 0xff)
25072 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25073 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
25074 (unsigned long) addend_abs
);
25076 /* Extract the instruction. */
25077 insn
= md_chars_to_number (buf
, INSN_SIZE
);
25079 /* If the addend is negative, clear bit 23 of the instruction.
25080 Otherwise set it. */
25082 insn
&= ~(1 << 23);
25086 /* Place the addend (divided by four) into the first eight
25087 bits of the instruction. */
25088 insn
&= 0xfffffff0;
25089 insn
|= addend_abs
>> 2;
25091 /* Update the instruction. */
25092 md_number_to_chars (buf
, insn
, INSN_SIZE
);
25096 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
25098 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25099 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25100 && ARM_IS_FUNC (fixP
->fx_addsy
)
25101 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25103 /* Force a relocation for a branch 5 bits wide. */
25106 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
25107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25110 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25112 addressT boff
= value
>> 1;
25114 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25115 newval
|= (boff
<< 7);
25116 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25120 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
25122 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25123 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25124 && ARM_IS_FUNC (fixP
->fx_addsy
)
25125 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25129 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
25130 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25131 _("branch out of range"));
25133 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25135 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25137 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
25138 addressT diff
= value
- boff
;
25142 newval
|= 1 << 1; /* T bit. */
25144 else if (diff
!= 2)
25146 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25147 _("out of range label-relative fixup value"));
25149 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25153 case BFD_RELOC_ARM_THUMB_BF17
:
25155 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25156 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25157 && ARM_IS_FUNC (fixP
->fx_addsy
)
25158 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25160 /* Force a relocation for a branch 17 bits wide. */
25164 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
25165 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25168 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25171 addressT immA
, immB
, immC
;
25173 immA
= (value
& 0x0001f000) >> 12;
25174 immB
= (value
& 0x00000ffc) >> 2;
25175 immC
= (value
& 0x00000002) >> 1;
25177 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25178 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25180 newval2
|= (immC
<< 11) | (immB
<< 1);
25181 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25182 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25186 case BFD_RELOC_ARM_THUMB_BF19
:
25188 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25189 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25190 && ARM_IS_FUNC (fixP
->fx_addsy
)
25191 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25193 /* Force a relocation for a branch 19 bits wide. */
25197 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
25198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25201 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25204 addressT immA
, immB
, immC
;
25206 immA
= (value
& 0x0007f000) >> 12;
25207 immB
= (value
& 0x00000ffc) >> 2;
25208 immC
= (value
& 0x00000002) >> 1;
25210 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25211 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25213 newval2
|= (immC
<< 11) | (immB
<< 1);
25214 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25215 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25219 case BFD_RELOC_ARM_THUMB_BF13
:
25221 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25222 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25223 && ARM_IS_FUNC (fixP
->fx_addsy
)
25224 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25226 /* Force a relocation for a branch 13 bits wide. */
25230 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
25231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25234 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25237 addressT immA
, immB
, immC
;
25239 immA
= (value
& 0x00001000) >> 12;
25240 immB
= (value
& 0x00000ffc) >> 2;
25241 immC
= (value
& 0x00000002) >> 1;
25243 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25244 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25246 newval2
|= (immC
<< 11) | (immB
<< 1);
25247 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25248 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25252 case BFD_RELOC_ARM_THUMB_LOOP12
:
25254 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25255 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25256 && ARM_IS_FUNC (fixP
->fx_addsy
)
25257 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25259 /* Force a relocation for a branch 12 bits wide. */
25263 bfd_vma insn
= get_thumb32_insn (buf
);
25264 /* le lr, <label> or le <label> */
25265 if (((insn
& 0xffffffff) == 0xf00fc001)
25266 || ((insn
& 0xffffffff) == 0xf02fc001))
25269 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
25270 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25272 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25274 addressT imml
, immh
;
25276 immh
= (value
& 0x00000ffc) >> 2;
25277 imml
= (value
& 0x00000002) >> 1;
25279 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25280 newval
|= (imml
<< 11) | (immh
<< 1);
25281 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
25285 case BFD_RELOC_ARM_V4BX
:
25286 /* This will need to go in the object file. */
25290 case BFD_RELOC_UNUSED
:
25292 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25293 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
25297 /* Translate internal representation of relocation info to BFD target
25301 tc_gen_reloc (asection
*section
, fixS
*fixp
)
25304 bfd_reloc_code_real_type code
;
25306 reloc
= XNEW (arelent
);
25308 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
25309 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
25310 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
25312 if (fixp
->fx_pcrel
)
25314 if (section
->use_rela_p
)
25315 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
25317 fixp
->fx_offset
= reloc
->address
;
25319 reloc
->addend
= fixp
->fx_offset
;
25321 switch (fixp
->fx_r_type
)
25324 if (fixp
->fx_pcrel
)
25326 code
= BFD_RELOC_8_PCREL
;
25329 /* Fall through. */
25332 if (fixp
->fx_pcrel
)
25334 code
= BFD_RELOC_16_PCREL
;
25337 /* Fall through. */
25340 if (fixp
->fx_pcrel
)
25342 code
= BFD_RELOC_32_PCREL
;
25345 /* Fall through. */
25347 case BFD_RELOC_ARM_MOVW
:
25348 if (fixp
->fx_pcrel
)
25350 code
= BFD_RELOC_ARM_MOVW_PCREL
;
25353 /* Fall through. */
25355 case BFD_RELOC_ARM_MOVT
:
25356 if (fixp
->fx_pcrel
)
25358 code
= BFD_RELOC_ARM_MOVT_PCREL
;
25361 /* Fall through. */
25363 case BFD_RELOC_ARM_THUMB_MOVW
:
25364 if (fixp
->fx_pcrel
)
25366 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
25369 /* Fall through. */
25371 case BFD_RELOC_ARM_THUMB_MOVT
:
25372 if (fixp
->fx_pcrel
)
25374 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
25377 /* Fall through. */
25379 case BFD_RELOC_NONE
:
25380 case BFD_RELOC_ARM_PCREL_BRANCH
:
25381 case BFD_RELOC_ARM_PCREL_BLX
:
25382 case BFD_RELOC_RVA
:
25383 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
25384 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
25385 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
25386 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25387 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25388 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25389 case BFD_RELOC_VTABLE_ENTRY
:
25390 case BFD_RELOC_VTABLE_INHERIT
:
25392 case BFD_RELOC_32_SECREL
:
25394 code
= fixp
->fx_r_type
;
25397 case BFD_RELOC_THUMB_PCREL_BLX
:
25399 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
25400 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
25403 code
= BFD_RELOC_THUMB_PCREL_BLX
;
25406 case BFD_RELOC_ARM_LITERAL
:
25407 case BFD_RELOC_ARM_HWLITERAL
:
25408 /* If this is called then the a literal has
25409 been referenced across a section boundary. */
25410 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25411 _("literal referenced across section boundary"));
25415 case BFD_RELOC_ARM_TLS_CALL
:
25416 case BFD_RELOC_ARM_THM_TLS_CALL
:
25417 case BFD_RELOC_ARM_TLS_DESCSEQ
:
25418 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
25419 case BFD_RELOC_ARM_GOT32
:
25420 case BFD_RELOC_ARM_GOTOFF
:
25421 case BFD_RELOC_ARM_GOT_PREL
:
25422 case BFD_RELOC_ARM_PLT32
:
25423 case BFD_RELOC_ARM_TARGET1
:
25424 case BFD_RELOC_ARM_ROSEGREL32
:
25425 case BFD_RELOC_ARM_SBREL32
:
25426 case BFD_RELOC_ARM_PREL31
:
25427 case BFD_RELOC_ARM_TARGET2
:
25428 case BFD_RELOC_ARM_TLS_LDO32
:
25429 case BFD_RELOC_ARM_PCREL_CALL
:
25430 case BFD_RELOC_ARM_PCREL_JUMP
:
25431 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
25432 case BFD_RELOC_ARM_ALU_PC_G0
:
25433 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
25434 case BFD_RELOC_ARM_ALU_PC_G1
:
25435 case BFD_RELOC_ARM_ALU_PC_G2
:
25436 case BFD_RELOC_ARM_LDR_PC_G0
:
25437 case BFD_RELOC_ARM_LDR_PC_G1
:
25438 case BFD_RELOC_ARM_LDR_PC_G2
:
25439 case BFD_RELOC_ARM_LDRS_PC_G0
:
25440 case BFD_RELOC_ARM_LDRS_PC_G1
:
25441 case BFD_RELOC_ARM_LDRS_PC_G2
:
25442 case BFD_RELOC_ARM_LDC_PC_G0
:
25443 case BFD_RELOC_ARM_LDC_PC_G1
:
25444 case BFD_RELOC_ARM_LDC_PC_G2
:
25445 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
25446 case BFD_RELOC_ARM_ALU_SB_G0
:
25447 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
25448 case BFD_RELOC_ARM_ALU_SB_G1
:
25449 case BFD_RELOC_ARM_ALU_SB_G2
:
25450 case BFD_RELOC_ARM_LDR_SB_G0
:
25451 case BFD_RELOC_ARM_LDR_SB_G1
:
25452 case BFD_RELOC_ARM_LDR_SB_G2
:
25453 case BFD_RELOC_ARM_LDRS_SB_G0
:
25454 case BFD_RELOC_ARM_LDRS_SB_G1
:
25455 case BFD_RELOC_ARM_LDRS_SB_G2
:
25456 case BFD_RELOC_ARM_LDC_SB_G0
:
25457 case BFD_RELOC_ARM_LDC_SB_G1
:
25458 case BFD_RELOC_ARM_LDC_SB_G2
:
25459 case BFD_RELOC_ARM_V4BX
:
25460 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
25461 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
25462 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
25463 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
25464 case BFD_RELOC_ARM_GOTFUNCDESC
:
25465 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
25466 case BFD_RELOC_ARM_FUNCDESC
:
25467 case BFD_RELOC_ARM_THUMB_BF17
:
25468 case BFD_RELOC_ARM_THUMB_BF19
:
25469 case BFD_RELOC_ARM_THUMB_BF13
:
25470 code
= fixp
->fx_r_type
;
25473 case BFD_RELOC_ARM_TLS_GOTDESC
:
25474 case BFD_RELOC_ARM_TLS_GD32
:
25475 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
25476 case BFD_RELOC_ARM_TLS_LE32
:
25477 case BFD_RELOC_ARM_TLS_IE32
:
25478 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
25479 case BFD_RELOC_ARM_TLS_LDM32
:
25480 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
25481 /* BFD will include the symbol's address in the addend.
25482 But we don't want that, so subtract it out again here. */
25483 if (!S_IS_COMMON (fixp
->fx_addsy
))
25484 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
25485 code
= fixp
->fx_r_type
;
25489 case BFD_RELOC_ARM_IMMEDIATE
:
25490 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25491 _("internal relocation (type: IMMEDIATE) not fixed up"));
25494 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
25495 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25496 _("ADRL used for a symbol not defined in the same file"));
25499 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
25500 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
25501 case BFD_RELOC_ARM_THUMB_LOOP12
:
25502 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25503 _("%s used for a symbol not defined in the same file"),
25504 bfd_get_reloc_code_name (fixp
->fx_r_type
));
25507 case BFD_RELOC_ARM_OFFSET_IMM
:
25508 if (section
->use_rela_p
)
25510 code
= fixp
->fx_r_type
;
25514 if (fixp
->fx_addsy
!= NULL
25515 && !S_IS_DEFINED (fixp
->fx_addsy
)
25516 && S_IS_LOCAL (fixp
->fx_addsy
))
25518 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25519 _("undefined local label `%s'"),
25520 S_GET_NAME (fixp
->fx_addsy
));
25524 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25525 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
25532 switch (fixp
->fx_r_type
)
25534 case BFD_RELOC_NONE
: type
= "NONE"; break;
25535 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
25536 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
25537 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
25538 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
25539 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
25540 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
25541 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
25542 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
25543 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
25544 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
25545 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
25546 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
25547 default: type
= _("<unknown>"); break;
25549 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25550 _("cannot represent %s relocation in this object file format"),
25557 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
25559 && fixp
->fx_addsy
== GOT_symbol
)
25561 code
= BFD_RELOC_ARM_GOTPC
;
25562 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
25566 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
25568 if (reloc
->howto
== NULL
)
25570 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25571 _("cannot represent %s relocation in this object file format"),
25572 bfd_get_reloc_code_name (code
));
25576 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
25577 vtable entry to be used in the relocation's section offset. */
25578 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25579 reloc
->address
= fixp
->fx_offset
;
25584 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
25587 cons_fix_new_arm (fragS
* frag
,
25591 bfd_reloc_code_real_type reloc
)
25596 FIXME: @@ Should look at CPU word size. */
25600 reloc
= BFD_RELOC_8
;
25603 reloc
= BFD_RELOC_16
;
25607 reloc
= BFD_RELOC_32
;
25610 reloc
= BFD_RELOC_64
;
25615 if (exp
->X_op
== O_secrel
)
25617 exp
->X_op
= O_symbol
;
25618 reloc
= BFD_RELOC_32_SECREL
;
25622 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
25625 #if defined (OBJ_COFF)
25627 arm_validate_fix (fixS
* fixP
)
25629 /* If the destination of the branch is a defined symbol which does not have
25630 the THUMB_FUNC attribute, then we must be calling a function which has
25631 the (interfacearm) attribute. We look for the Thumb entry point to that
25632 function and change the branch to refer to that function instead. */
25633 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
25634 && fixP
->fx_addsy
!= NULL
25635 && S_IS_DEFINED (fixP
->fx_addsy
)
25636 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
25638 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
25645 arm_force_relocation (struct fix
* fixp
)
25647 #if defined (OBJ_COFF) && defined (TE_PE)
25648 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
25652 /* In case we have a call or a branch to a function in ARM ISA mode from
25653 a thumb function or vice-versa force the relocation. These relocations
25654 are cleared off for some cores that might have blx and simple transformations
25658 switch (fixp
->fx_r_type
)
25660 case BFD_RELOC_ARM_PCREL_JUMP
:
25661 case BFD_RELOC_ARM_PCREL_CALL
:
25662 case BFD_RELOC_THUMB_PCREL_BLX
:
25663 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
25667 case BFD_RELOC_ARM_PCREL_BLX
:
25668 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25669 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25670 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25671 if (ARM_IS_FUNC (fixp
->fx_addsy
))
25680 /* Resolve these relocations even if the symbol is extern or weak.
25681 Technically this is probably wrong due to symbol preemption.
25682 In practice these relocations do not have enough range to be useful
25683 at dynamic link time, and some code (e.g. in the Linux kernel)
25684 expects these references to be resolved. */
25685 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
25686 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
25687 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
25688 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
25689 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
25690 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
25691 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
25692 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
25693 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
25694 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
25695 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
25696 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
25697 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
25698 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
25701 /* Always leave these relocations for the linker. */
25702 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25703 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25704 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25707 /* Always generate relocations against function symbols. */
25708 if (fixp
->fx_r_type
== BFD_RELOC_32
25710 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
25713 return generic_force_reloc (fixp
);
25716 #if defined (OBJ_ELF) || defined (OBJ_COFF)
25717 /* Relocations against function names must be left unadjusted,
25718 so that the linker can use this information to generate interworking
25719 stubs. The MIPS version of this function
25720 also prevents relocations that are mips-16 specific, but I do not
25721 know why it does this.
25724 There is one other problem that ought to be addressed here, but
25725 which currently is not: Taking the address of a label (rather
25726 than a function) and then later jumping to that address. Such
25727 addresses also ought to have their bottom bit set (assuming that
25728 they reside in Thumb code), but at the moment they will not. */
25731 arm_fix_adjustable (fixS
* fixP
)
25733 if (fixP
->fx_addsy
== NULL
)
25736 /* Preserve relocations against symbols with function type. */
25737 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
25740 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
25741 && fixP
->fx_subsy
== NULL
)
25744 /* We need the symbol name for the VTABLE entries. */
25745 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
25746 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25749 /* Don't allow symbols to be discarded on GOT related relocs. */
25750 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
25751 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
25752 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
25753 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
25754 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
25755 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
25756 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
25757 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
25758 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
25759 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
25760 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
25761 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
25762 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
25763 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
25764 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
25765 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
25766 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
25769 /* Similarly for group relocations. */
25770 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25771 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25772 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25775 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
25776 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
25777 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
25778 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
25779 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
25780 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
25781 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
25782 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
25783 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
25786 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
25787 offsets, so keep these symbols. */
25788 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
25789 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
25794 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
25798 elf32_arm_target_format (void)
25801 return (target_big_endian
25802 ? "elf32-bigarm-symbian"
25803 : "elf32-littlearm-symbian");
25804 #elif defined (TE_VXWORKS)
25805 return (target_big_endian
25806 ? "elf32-bigarm-vxworks"
25807 : "elf32-littlearm-vxworks");
25808 #elif defined (TE_NACL)
25809 return (target_big_endian
25810 ? "elf32-bigarm-nacl"
25811 : "elf32-littlearm-nacl");
25815 if (target_big_endian
)
25816 return "elf32-bigarm-fdpic";
25818 return "elf32-littlearm-fdpic";
25822 if (target_big_endian
)
25823 return "elf32-bigarm";
25825 return "elf32-littlearm";
25831 armelf_frob_symbol (symbolS
* symp
,
25834 elf_frob_symbol (symp
, puntp
);
25838 /* MD interface: Finalization. */
25843 literal_pool
* pool
;
25845 /* Ensure that all the IT blocks are properly closed. */
25846 check_it_blocks_finished ();
25848 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
25850 /* Put it at the end of the relevant section. */
25851 subseg_set (pool
->section
, pool
->sub_section
);
25853 arm_elf_change_section ();
25860 /* Remove any excess mapping symbols generated for alignment frags in
25861 SEC. We may have created a mapping symbol before a zero byte
25862 alignment; remove it if there's a mapping symbol after the
25865 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
25866 void *dummy ATTRIBUTE_UNUSED
)
25868 segment_info_type
*seginfo
= seg_info (sec
);
25871 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
25874 for (fragp
= seginfo
->frchainP
->frch_root
;
25876 fragp
= fragp
->fr_next
)
25878 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
25879 fragS
*next
= fragp
->fr_next
;
25881 /* Variable-sized frags have been converted to fixed size by
25882 this point. But if this was variable-sized to start with,
25883 there will be a fixed-size frag after it. So don't handle
25885 if (sym
== NULL
|| next
== NULL
)
25888 if (S_GET_VALUE (sym
) < next
->fr_address
)
25889 /* Not at the end of this frag. */
25891 know (S_GET_VALUE (sym
) == next
->fr_address
);
25895 if (next
->tc_frag_data
.first_map
!= NULL
)
25897 /* Next frag starts with a mapping symbol. Discard this
25899 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25903 if (next
->fr_next
== NULL
)
25905 /* This mapping symbol is at the end of the section. Discard
25907 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
25908 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25912 /* As long as we have empty frags without any mapping symbols,
25914 /* If the next frag is non-empty and does not start with a
25915 mapping symbol, then this mapping symbol is required. */
25916 if (next
->fr_address
!= next
->fr_next
->fr_address
)
25919 next
= next
->fr_next
;
25921 while (next
!= NULL
);
25926 /* Adjust the symbol table. This marks Thumb symbols as distinct from
25930 arm_adjust_symtab (void)
25935 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25937 if (ARM_IS_THUMB (sym
))
25939 if (THUMB_IS_FUNC (sym
))
25941 /* Mark the symbol as a Thumb function. */
25942 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
25943 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
25944 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
25946 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
25947 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
25949 as_bad (_("%s: unexpected function type: %d"),
25950 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
25952 else switch (S_GET_STORAGE_CLASS (sym
))
25955 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
25958 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
25961 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25969 if (ARM_IS_INTERWORK (sym
))
25970 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25977 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25979 if (ARM_IS_THUMB (sym
))
25981 elf_symbol_type
* elf_sym
;
25983 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25984 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25986 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25987 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25989 /* If it's a .thumb_func, declare it as so,
25990 otherwise tag label as .code 16. */
25991 if (THUMB_IS_FUNC (sym
))
25992 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25993 ST_BRANCH_TO_THUMB
);
25994 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25995 elf_sym
->internal_elf_sym
.st_info
=
25996 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
26001 /* Remove any overlapping mapping symbols generated by alignment frags. */
26002 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
26003 /* Now do generic ELF adjustments. */
26004 elf_adjust_symtab ();
26008 /* MD interface: Initialization. */
26011 set_constant_flonums (void)
26015 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
26016 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
26020 /* Auto-select Thumb mode if it's the only available instruction set for the
26021 given architecture. */
26024 autoselect_thumb_from_cpu_variant (void)
26026 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
26027 opcode_select (16);
26036 if ( (arm_ops_hsh
= hash_new ()) == NULL
26037 || (arm_cond_hsh
= hash_new ()) == NULL
26038 || (arm_shift_hsh
= hash_new ()) == NULL
26039 || (arm_psr_hsh
= hash_new ()) == NULL
26040 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
26041 || (arm_reg_hsh
= hash_new ()) == NULL
26042 || (arm_reloc_hsh
= hash_new ()) == NULL
26043 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
26044 as_fatal (_("virtual memory exhausted"));
26046 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
26047 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
26048 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
26049 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
26050 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
26051 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
26052 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
26053 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
26054 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
26055 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
26056 (void *) (v7m_psrs
+ i
));
26057 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
26058 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
26060 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
26062 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
26063 (void *) (barrier_opt_names
+ i
));
26065 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
26067 struct reloc_entry
* entry
= reloc_names
+ i
;
26069 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
26070 /* This makes encode_branch() use the EABI versions of this relocation. */
26071 entry
->reloc
= BFD_RELOC_UNUSED
;
26073 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
26077 set_constant_flonums ();
26079 /* Set the cpu variant based on the command-line options. We prefer
26080 -mcpu= over -march= if both are set (as for GCC); and we prefer
26081 -mfpu= over any other way of setting the floating point unit.
26082 Use of legacy options with new options are faulted. */
26085 if (mcpu_cpu_opt
|| march_cpu_opt
)
26086 as_bad (_("use of old and new-style options to set CPU type"));
26088 selected_arch
= *legacy_cpu
;
26090 else if (mcpu_cpu_opt
)
26092 selected_arch
= *mcpu_cpu_opt
;
26093 selected_ext
= *mcpu_ext_opt
;
26095 else if (march_cpu_opt
)
26097 selected_arch
= *march_cpu_opt
;
26098 selected_ext
= *march_ext_opt
;
26100 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
26105 as_bad (_("use of old and new-style options to set FPU type"));
26107 selected_fpu
= *legacy_fpu
;
26110 selected_fpu
= *mfpu_opt
;
26113 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
26114 || defined (TE_NetBSD) || defined (TE_VXWORKS))
26115 /* Some environments specify a default FPU. If they don't, infer it
26116 from the processor. */
26118 selected_fpu
= *mcpu_fpu_opt
;
26119 else if (march_fpu_opt
)
26120 selected_fpu
= *march_fpu_opt
;
26122 selected_fpu
= fpu_default
;
26126 if (ARM_FEATURE_ZERO (selected_fpu
))
26128 if (!no_cpu_selected ())
26129 selected_fpu
= fpu_default
;
26131 selected_fpu
= fpu_arch_fpa
;
26135 if (ARM_FEATURE_ZERO (selected_arch
))
26137 selected_arch
= cpu_default
;
26138 selected_cpu
= selected_arch
;
26140 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
26142 /* Autodection of feature mode: allow all features in cpu_variant but leave
26143 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
26144 after all instruction have been processed and we can decide what CPU
26145 should be selected. */
26146 if (ARM_FEATURE_ZERO (selected_arch
))
26147 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
26149 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
26152 autoselect_thumb_from_cpu_variant ();
26154 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
26156 #if defined OBJ_COFF || defined OBJ_ELF
26158 unsigned int flags
= 0;
26160 #if defined OBJ_ELF
26161 flags
= meabi_flags
;
26163 switch (meabi_flags
)
26165 case EF_ARM_EABI_UNKNOWN
:
26167 /* Set the flags in the private structure. */
26168 if (uses_apcs_26
) flags
|= F_APCS26
;
26169 if (support_interwork
) flags
|= F_INTERWORK
;
26170 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
26171 if (pic_code
) flags
|= F_PIC
;
26172 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
26173 flags
|= F_SOFT_FLOAT
;
26175 switch (mfloat_abi_opt
)
26177 case ARM_FLOAT_ABI_SOFT
:
26178 case ARM_FLOAT_ABI_SOFTFP
:
26179 flags
|= F_SOFT_FLOAT
;
26182 case ARM_FLOAT_ABI_HARD
:
26183 if (flags
& F_SOFT_FLOAT
)
26184 as_bad (_("hard-float conflicts with specified fpu"));
26188 /* Using pure-endian doubles (even if soft-float). */
26189 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
26190 flags
|= F_VFP_FLOAT
;
26192 #if defined OBJ_ELF
26193 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
26194 flags
|= EF_ARM_MAVERICK_FLOAT
;
26197 case EF_ARM_EABI_VER4
:
26198 case EF_ARM_EABI_VER5
:
26199 /* No additional flags to set. */
26206 bfd_set_private_flags (stdoutput
, flags
);
26208 /* We have run out flags in the COFF header to encode the
26209 status of ATPCS support, so instead we create a dummy,
26210 empty, debug section called .arm.atpcs. */
26215 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
26219 bfd_set_section_flags
26220 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
26221 bfd_set_section_size (stdoutput
, sec
, 0);
26222 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
26228 /* Record the CPU type as well. */
26229 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
26230 mach
= bfd_mach_arm_iWMMXt2
;
26231 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
26232 mach
= bfd_mach_arm_iWMMXt
;
26233 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
26234 mach
= bfd_mach_arm_XScale
;
26235 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
26236 mach
= bfd_mach_arm_ep9312
;
26237 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
26238 mach
= bfd_mach_arm_5TE
;
26239 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
26241 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
26242 mach
= bfd_mach_arm_5T
;
26244 mach
= bfd_mach_arm_5
;
26246 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
26248 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
26249 mach
= bfd_mach_arm_4T
;
26251 mach
= bfd_mach_arm_4
;
26253 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
26254 mach
= bfd_mach_arm_3M
;
26255 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
26256 mach
= bfd_mach_arm_3
;
26257 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
26258 mach
= bfd_mach_arm_2a
;
26259 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
26260 mach
= bfd_mach_arm_2
;
26262 mach
= bfd_mach_arm_unknown
;
26264 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
26267 /* Command line processing. */
26270 Invocation line includes a switch not recognized by the base assembler.
26271 See if it's a processor-specific option.
26273 This routine is somewhat complicated by the need for backwards
26274 compatibility (since older releases of gcc can't be changed).
26275 The new options try to make the interface as compatible as
26278 New options (supported) are:
26280 -mcpu=<cpu name> Assemble for selected processor
26281 -march=<architecture name> Assemble for selected architecture
26282 -mfpu=<fpu architecture> Assemble for selected FPU.
26283 -EB/-mbig-endian Big-endian
26284 -EL/-mlittle-endian Little-endian
26285 -k Generate PIC code
26286 -mthumb Start in Thumb mode
26287 -mthumb-interwork Code supports ARM/Thumb interworking
26289 -m[no-]warn-deprecated Warn about deprecated features
26290 -m[no-]warn-syms Warn when symbols match instructions
26292 For now we will also provide support for:
26294 -mapcs-32 32-bit Program counter
26295 -mapcs-26 26-bit Program counter
26296 -macps-float Floats passed in FP registers
26297 -mapcs-reentrant Reentrant code
26299 (sometime these will probably be replaced with -mapcs=<list of options>
26300 and -matpcs=<list of options>)
26302 The remaining options are only supported for back-wards compatibility.
26303 Cpu variants, the arm part is optional:
26304 -m[arm]1 Currently not supported.
26305 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
26306 -m[arm]3 Arm 3 processor
26307 -m[arm]6[xx], Arm 6 processors
26308 -m[arm]7[xx][t][[d]m] Arm 7 processors
26309 -m[arm]8[10] Arm 8 processors
26310 -m[arm]9[20][tdmi] Arm 9 processors
26311 -mstrongarm[110[0]] StrongARM processors
26312 -mxscale XScale processors
26313 -m[arm]v[2345[t[e]]] Arm architectures
26314 -mall All (except the ARM1)
26316 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
26317 -mfpe-old (No float load/store multiples)
26318 -mvfpxd VFP Single precision
26320 -mno-fpu Disable all floating point instructions
26322 The following CPU names are recognized:
26323 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
26324 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
26325 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
26326 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
26327 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
26328 arm10t arm10e, arm1020t, arm1020e, arm10200e,
26329 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
26333 const char * md_shortopts
= "m:k";
26335 #ifdef ARM_BI_ENDIAN
26336 #define OPTION_EB (OPTION_MD_BASE + 0)
26337 #define OPTION_EL (OPTION_MD_BASE + 1)
26339 #if TARGET_BYTES_BIG_ENDIAN
26340 #define OPTION_EB (OPTION_MD_BASE + 0)
26342 #define OPTION_EL (OPTION_MD_BASE + 1)
26345 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
26346 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
26348 struct option md_longopts
[] =
26351 {"EB", no_argument
, NULL
, OPTION_EB
},
26354 {"EL", no_argument
, NULL
, OPTION_EL
},
26356 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
26358 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
26360 {NULL
, no_argument
, NULL
, 0}
26363 size_t md_longopts_size
= sizeof (md_longopts
);
26365 struct arm_option_table
26367 const char * option
; /* Option name to match. */
26368 const char * help
; /* Help information. */
26369 int * var
; /* Variable to change. */
26370 int value
; /* What to change it to. */
26371 const char * deprecated
; /* If non-null, print this message. */
26374 struct arm_option_table arm_opts
[] =
26376 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
26377 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
26378 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
26379 &support_interwork
, 1, NULL
},
26380 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
26381 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
26382 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
26384 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
26385 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
26386 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
26387 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
26390 /* These are recognized by the assembler, but have no affect on code. */
26391 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
26392 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
26394 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
26395 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
26396 &warn_on_deprecated
, 0, NULL
},
26397 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
26398 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
26399 {NULL
, NULL
, NULL
, 0, NULL
}
26402 struct arm_legacy_option_table
26404 const char * option
; /* Option name to match. */
26405 const arm_feature_set
** var
; /* Variable to change. */
26406 const arm_feature_set value
; /* What to change it to. */
26407 const char * deprecated
; /* If non-null, print this message. */
26410 const struct arm_legacy_option_table arm_legacy_opts
[] =
26412 /* DON'T add any new processors to this list -- we want the whole list
26413 to go away... Add them to the processors table instead. */
26414 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
26415 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
26416 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
26417 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
26418 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
26419 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
26420 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
26421 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
26422 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
26423 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
26424 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
26425 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
26426 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
26427 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
26428 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
26429 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
26430 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
26431 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
26432 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
26433 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
26434 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
26435 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
26436 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
26437 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
26438 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
26439 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
26440 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
26441 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
26442 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
26443 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
26444 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
26445 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
26446 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
26447 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
26448 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
26449 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
26450 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
26451 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
26452 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
26453 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
26454 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
26455 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
26456 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
26457 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
26458 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
26459 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
26460 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26461 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26462 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26463 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26464 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
26465 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
26466 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
26467 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
26468 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
26469 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
26470 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
26471 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
26472 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
26473 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
26474 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
26475 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
26476 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
26477 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
26478 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
26479 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
26480 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
26481 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
26482 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
26483 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
26484 N_("use -mcpu=strongarm110")},
26485 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
26486 N_("use -mcpu=strongarm1100")},
26487 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
26488 N_("use -mcpu=strongarm1110")},
26489 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
26490 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
26491 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
26493 /* Architecture variants -- don't add any more to this list either. */
26494 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
26495 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
26496 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
26497 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
26498 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
26499 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
26500 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
26501 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
26502 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
26503 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
26504 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
26505 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
26506 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
26507 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
26508 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
26509 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
26510 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
26511 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
26513 /* Floating point variants -- don't add any more to this list either. */
26514 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
26515 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
26516 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
26517 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
26518 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
26520 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
26523 struct arm_cpu_option_table
26527 const arm_feature_set value
;
26528 const arm_feature_set ext
;
26529 /* For some CPUs we assume an FPU unless the user explicitly sets
26531 const arm_feature_set default_fpu
;
26532 /* The canonical name of the CPU, or NULL to use NAME converted to upper
26534 const char * canonical_name
;
26537 /* This list should, at a minimum, contain all the cpu names
26538 recognized by GCC. */
26539 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
26541 static const struct arm_cpu_option_table arm_cpus
[] =
26543 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
26546 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
26549 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
26552 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
26555 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
26558 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
26561 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
26564 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
26567 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
26570 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
26573 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
26576 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
26579 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
26582 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
26585 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
26588 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
26591 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
26594 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
26597 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
26600 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
26603 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
26606 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
26609 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
26612 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
26615 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
26618 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
26621 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
26624 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
26627 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
26630 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
26633 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
26636 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
26639 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
26642 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
26645 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
26648 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
26651 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
26654 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
26657 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
26660 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
26663 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
26666 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
26669 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
26672 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
26675 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
26678 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
26682 /* For V5 or later processors we default to using VFP; but the user
26683 should really set the FPU type explicitly. */
26684 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
26687 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
26690 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26693 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26696 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
26699 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
26702 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
26705 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
26708 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
26711 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
26714 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
26717 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
26720 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
26723 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
26726 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
26729 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
26732 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
26735 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
26738 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
26741 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
26744 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
26747 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
26750 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
26753 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
26756 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
26759 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
26762 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
26765 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
26768 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
26771 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
26774 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
26777 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
26780 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
26783 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
26786 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
26789 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
26792 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
26793 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26795 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
26797 FPU_ARCH_NEON_VFP_V4
),
26798 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
26799 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26800 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26801 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
26802 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26803 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26804 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
26806 FPU_ARCH_NEON_VFP_V4
),
26807 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
26809 FPU_ARCH_NEON_VFP_V4
),
26810 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
26812 FPU_ARCH_NEON_VFP_V4
),
26813 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
26814 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26815 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26816 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
26817 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26818 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26819 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
26820 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26821 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26822 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
26823 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26824 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26825 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
26826 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26827 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26828 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
26829 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26830 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26831 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
26832 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26833 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26834 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
26835 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26836 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26837 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
26838 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26839 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26840 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
26841 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26842 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26843 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
26846 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
26848 FPU_ARCH_VFP_V3D16
),
26849 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
26850 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26852 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
26853 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26854 FPU_ARCH_VFP_V3D16
),
26855 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
26856 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26857 FPU_ARCH_VFP_V3D16
),
26858 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
26859 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26860 FPU_ARCH_NEON_VFP_ARMV8
),
26861 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
26862 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26864 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
26867 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
26870 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
26873 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
26876 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
26879 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
26882 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
26885 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
26886 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26887 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26888 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
26889 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26890 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26891 /* ??? XSCALE is really an architecture. */
26892 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
26896 /* ??? iwmmxt is not a processor. */
26897 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
26900 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
26903 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
26908 ARM_CPU_OPT ("ep9312", "ARM920T",
26909 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
26910 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
26912 /* Marvell processors. */
26913 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
26914 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26915 FPU_ARCH_VFP_V3D16
),
26916 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
26917 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26918 FPU_ARCH_NEON_VFP_V4
),
26920 /* APM X-Gene family. */
26921 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
26923 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26924 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
26925 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26926 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26928 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26932 struct arm_ext_table
26936 const arm_feature_set merge
;
26937 const arm_feature_set clear
;
26940 struct arm_arch_option_table
26944 const arm_feature_set value
;
26945 const arm_feature_set default_fpu
;
26946 const struct arm_ext_table
* ext_table
;
26949 /* Used to add support for +E and +noE extension. */
26950 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
26951 /* Used to add support for a +E extension. */
26952 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
26953 /* Used to add support for a +noE extension. */
26954 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
26956 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
26957 ~0 & ~FPU_ENDIAN_PURE)
26959 static const struct arm_ext_table armv5te_ext_table
[] =
26961 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
26962 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26965 static const struct arm_ext_table armv7_ext_table
[] =
26967 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26968 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26971 static const struct arm_ext_table armv7ve_ext_table
[] =
26973 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
26974 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
26975 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
26976 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26977 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
26978 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
26979 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
26981 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
26982 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
26984 /* Aliases for +simd. */
26985 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
26987 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26988 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26989 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
26991 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26994 static const struct arm_ext_table armv7a_ext_table
[] =
26996 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26997 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
26998 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
26999 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
27000 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
27001 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
27002 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
27004 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
27005 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
27007 /* Aliases for +simd. */
27008 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
27009 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
27011 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
27012 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
27014 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
27015 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
27016 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27019 static const struct arm_ext_table armv7r_ext_table
[] =
27021 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
27022 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
27023 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
27024 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
27025 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
27026 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
27027 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
27028 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
27029 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27032 static const struct arm_ext_table armv7em_ext_table
[] =
27034 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
27035 /* Alias for +fp, used to be known as fpv4-sp-d16. */
27036 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
27037 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
27038 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
27039 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
27040 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27043 static const struct arm_ext_table armv8a_ext_table
[] =
27045 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
27046 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
27047 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
27048 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
27050 /* Armv8-a does not allow an FP implementation without SIMD, so the user
27051 should use the +simd option to turn on FP. */
27052 ARM_REMOVE ("fp", ALL_FP
),
27053 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
27054 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
27055 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27059 static const struct arm_ext_table armv81a_ext_table
[] =
27061 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
27062 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
27063 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
27065 /* Armv8-a does not allow an FP implementation without SIMD, so the user
27066 should use the +simd option to turn on FP. */
27067 ARM_REMOVE ("fp", ALL_FP
),
27068 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
27069 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
27070 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27073 static const struct arm_ext_table armv82a_ext_table
[] =
27075 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
27076 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
27077 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
27078 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
27079 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
27080 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
27082 /* Armv8-a does not allow an FP implementation without SIMD, so the user
27083 should use the +simd option to turn on FP. */
27084 ARM_REMOVE ("fp", ALL_FP
),
27085 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
27086 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
27087 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27090 static const struct arm_ext_table armv84a_ext_table
[] =
27092 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
27093 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
27094 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
27095 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
27097 /* Armv8-a does not allow an FP implementation without SIMD, so the user
27098 should use the +simd option to turn on FP. */
27099 ARM_REMOVE ("fp", ALL_FP
),
27100 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
27101 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
27102 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27105 static const struct arm_ext_table armv85a_ext_table
[] =
27107 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
27108 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
27109 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
27110 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
27112 /* Armv8-a does not allow an FP implementation without SIMD, so the user
27113 should use the +simd option to turn on FP. */
27114 ARM_REMOVE ("fp", ALL_FP
),
27115 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27118 static const struct arm_ext_table armv8m_main_ext_table
[] =
27120 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
27121 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
27122 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
27123 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
27124 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27127 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
27129 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
27130 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
27132 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
27133 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
27136 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
27137 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
27138 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27141 static const struct arm_ext_table armv8r_ext_table
[] =
27143 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
27144 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
27145 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
27146 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
27147 ARM_REMOVE ("fp", ALL_FP
),
27148 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
27149 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27152 /* This list should, at a minimum, contain all the architecture names
27153 recognized by GCC. */
27154 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
27155 #define ARM_ARCH_OPT2(N, V, DF, ext) \
27156 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
27158 static const struct arm_arch_option_table arm_archs
[] =
27160 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
27161 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
27162 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
27163 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
27164 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
27165 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
27166 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
27167 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
27168 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
27169 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
27170 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
27171 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
27172 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
27173 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
27174 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
27175 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
27176 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
27177 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
27178 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
27179 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
27180 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
27181 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
27182 kept to preserve existing behaviour. */
27183 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
27184 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
27185 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
27186 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
27187 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
27188 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
27189 kept to preserve existing behaviour. */
27190 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
27191 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
27192 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
27193 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
27194 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
27195 /* The official spelling of the ARMv7 profile variants is the dashed form.
27196 Accept the non-dashed form for compatibility with old toolchains. */
27197 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
27198 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
27199 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
27200 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
27201 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
27202 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
27203 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
27204 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
27205 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
27206 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
27208 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
27210 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
27211 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
27212 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
27213 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
27214 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
27215 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
27216 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
27217 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
27218 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
27219 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
27220 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
27222 #undef ARM_ARCH_OPT
27224 /* ISA extensions in the co-processor and main instruction set space. */
27226 struct arm_option_extension_value_table
27230 const arm_feature_set merge_value
;
27231 const arm_feature_set clear_value
;
27232 /* List of architectures for which an extension is available. ARM_ARCH_NONE
27233 indicates that an extension is available for all architectures while
27234 ARM_ANY marks an empty entry. */
27235 const arm_feature_set allowed_archs
[2];
27238 /* The following table must be in alphabetical order with a NULL last entry. */
27240 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
27241 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
27243 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
27244 use the context sensitive approach using arm_ext_table's. */
27245 static const struct arm_option_extension_value_table arm_extensions
[] =
27247 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
27248 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
27249 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
27250 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
27251 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
27252 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
27253 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
27255 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
27256 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
27257 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
27258 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
27259 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
27260 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
27261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
27263 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
27264 | ARM_EXT2_FP16_FML
),
27265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
27266 | ARM_EXT2_FP16_FML
),
27268 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
27269 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
27270 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
27271 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
27272 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
27273 Thumb divide instruction. Due to this having the same name as the
27274 previous entry, this will be ignored when doing command-line parsing and
27275 only considered by build attribute selection code. */
27276 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
27277 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
27278 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
27279 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
27280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
27281 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
27282 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
27283 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
27284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
27285 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
27286 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
27287 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
27288 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
27289 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
27290 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
27291 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
27292 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
27293 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
27294 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
27295 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
27296 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
27298 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
27299 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
27300 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
27301 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
27302 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
27303 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
27304 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
27305 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
27307 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
27308 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
27309 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
27310 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
27311 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
27312 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
27313 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
27314 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
27316 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
27317 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
27318 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
27319 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
27320 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
27324 /* ISA floating-point and Advanced SIMD extensions. */
27325 struct arm_option_fpu_value_table
27328 const arm_feature_set value
;
27331 /* This list should, at a minimum, contain all the fpu names
27332 recognized by GCC. */
27333 static const struct arm_option_fpu_value_table arm_fpus
[] =
27335 {"softfpa", FPU_NONE
},
27336 {"fpe", FPU_ARCH_FPE
},
27337 {"fpe2", FPU_ARCH_FPE
},
27338 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
27339 {"fpa", FPU_ARCH_FPA
},
27340 {"fpa10", FPU_ARCH_FPA
},
27341 {"fpa11", FPU_ARCH_FPA
},
27342 {"arm7500fe", FPU_ARCH_FPA
},
27343 {"softvfp", FPU_ARCH_VFP
},
27344 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
27345 {"vfp", FPU_ARCH_VFP_V2
},
27346 {"vfp9", FPU_ARCH_VFP_V2
},
27347 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
27348 {"vfp10", FPU_ARCH_VFP_V2
},
27349 {"vfp10-r0", FPU_ARCH_VFP_V1
},
27350 {"vfpxd", FPU_ARCH_VFP_V1xD
},
27351 {"vfpv2", FPU_ARCH_VFP_V2
},
27352 {"vfpv3", FPU_ARCH_VFP_V3
},
27353 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
27354 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
27355 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
27356 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
27357 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
27358 {"arm1020t", FPU_ARCH_VFP_V1
},
27359 {"arm1020e", FPU_ARCH_VFP_V2
},
27360 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
27361 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
27362 {"maverick", FPU_ARCH_MAVERICK
},
27363 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
27364 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
27365 {"neon-fp16", FPU_ARCH_NEON_FP16
},
27366 {"vfpv4", FPU_ARCH_VFP_V4
},
27367 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
27368 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
27369 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
27370 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
27371 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
27372 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
27373 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
27374 {"crypto-neon-fp-armv8",
27375 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
27376 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
27377 {"crypto-neon-fp-armv8.1",
27378 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
27379 {NULL
, ARM_ARCH_NONE
}
27382 struct arm_option_value_table
27388 static const struct arm_option_value_table arm_float_abis
[] =
27390 {"hard", ARM_FLOAT_ABI_HARD
},
27391 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
27392 {"soft", ARM_FLOAT_ABI_SOFT
},
27397 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
27398 static const struct arm_option_value_table arm_eabis
[] =
27400 {"gnu", EF_ARM_EABI_UNKNOWN
},
27401 {"4", EF_ARM_EABI_VER4
},
27402 {"5", EF_ARM_EABI_VER5
},
27407 struct arm_long_option_table
27409 const char * option
; /* Substring to match. */
27410 const char * help
; /* Help information. */
27411 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
27412 const char * deprecated
; /* If non-null, print this message. */
27416 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
27417 arm_feature_set
*ext_set
,
27418 const struct arm_ext_table
*ext_table
)
27420 /* We insist on extensions being specified in alphabetical order, and with
27421 extensions being added before being removed. We achieve this by having
27422 the global ARM_EXTENSIONS table in alphabetical order, and using the
27423 ADDING_VALUE variable to indicate whether we are adding an extension (1)
27424 or removing it (0) and only allowing it to change in the order
27426 const struct arm_option_extension_value_table
* opt
= NULL
;
27427 const arm_feature_set arm_any
= ARM_ANY
;
27428 int adding_value
= -1;
27430 while (str
!= NULL
&& *str
!= 0)
27437 as_bad (_("invalid architectural extension"));
27442 ext
= strchr (str
, '+');
27447 len
= strlen (str
);
27449 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
27451 if (adding_value
!= 0)
27454 opt
= arm_extensions
;
27462 if (adding_value
== -1)
27465 opt
= arm_extensions
;
27467 else if (adding_value
!= 1)
27469 as_bad (_("must specify extensions to add before specifying "
27470 "those to remove"));
27477 as_bad (_("missing architectural extension"));
27481 gas_assert (adding_value
!= -1);
27482 gas_assert (opt
!= NULL
);
27484 if (ext_table
!= NULL
)
27486 const struct arm_ext_table
* ext_opt
= ext_table
;
27487 bfd_boolean found
= FALSE
;
27488 for (; ext_opt
->name
!= NULL
; ext_opt
++)
27489 if (ext_opt
->name_len
== len
27490 && strncmp (ext_opt
->name
, str
, len
) == 0)
27494 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
27495 /* TODO: Option not supported. When we remove the
27496 legacy table this case should error out. */
27499 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
27503 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
27504 /* TODO: Option not supported. When we remove the
27505 legacy table this case should error out. */
27507 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
27519 /* Scan over the options table trying to find an exact match. */
27520 for (; opt
->name
!= NULL
; opt
++)
27521 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27523 int i
, nb_allowed_archs
=
27524 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
27525 /* Check we can apply the extension to this architecture. */
27526 for (i
= 0; i
< nb_allowed_archs
; i
++)
27529 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
27531 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
27534 if (i
== nb_allowed_archs
)
27536 as_bad (_("extension does not apply to the base architecture"));
27540 /* Add or remove the extension. */
27542 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
27544 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
27546 /* Allowing Thumb division instructions for ARMv7 in autodetection
27547 rely on this break so that duplicate extensions (extensions
27548 with the same name as a previous extension in the list) are not
27549 considered for command-line parsing. */
27553 if (opt
->name
== NULL
)
27555 /* Did we fail to find an extension because it wasn't specified in
27556 alphabetical order, or because it does not exist? */
27558 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27559 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27562 if (opt
->name
== NULL
)
27563 as_bad (_("unknown architectural extension `%s'"), str
);
27565 as_bad (_("architectural extensions must be specified in "
27566 "alphabetical order"));
27572 /* We should skip the extension we've just matched the next time
27584 arm_parse_cpu (const char *str
)
27586 const struct arm_cpu_option_table
*opt
;
27587 const char *ext
= strchr (str
, '+');
27593 len
= strlen (str
);
27597 as_bad (_("missing cpu name `%s'"), str
);
27601 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
27602 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27604 mcpu_cpu_opt
= &opt
->value
;
27605 if (mcpu_ext_opt
== NULL
)
27606 mcpu_ext_opt
= XNEW (arm_feature_set
);
27607 *mcpu_ext_opt
= opt
->ext
;
27608 mcpu_fpu_opt
= &opt
->default_fpu
;
27609 if (opt
->canonical_name
)
27611 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
27612 strcpy (selected_cpu_name
, opt
->canonical_name
);
27618 if (len
>= sizeof selected_cpu_name
)
27619 len
= (sizeof selected_cpu_name
) - 1;
27621 for (i
= 0; i
< len
; i
++)
27622 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27623 selected_cpu_name
[i
] = 0;
27627 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
27632 as_bad (_("unknown cpu `%s'"), str
);
27637 arm_parse_arch (const char *str
)
27639 const struct arm_arch_option_table
*opt
;
27640 const char *ext
= strchr (str
, '+');
27646 len
= strlen (str
);
27650 as_bad (_("missing architecture name `%s'"), str
);
27654 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
27655 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27657 march_cpu_opt
= &opt
->value
;
27658 if (march_ext_opt
== NULL
)
27659 march_ext_opt
= XNEW (arm_feature_set
);
27660 *march_ext_opt
= arm_arch_none
;
27661 march_fpu_opt
= &opt
->default_fpu
;
27662 strcpy (selected_cpu_name
, opt
->name
);
27665 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
27671 as_bad (_("unknown architecture `%s'\n"), str
);
27676 arm_parse_fpu (const char * str
)
27678 const struct arm_option_fpu_value_table
* opt
;
27680 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27681 if (streq (opt
->name
, str
))
27683 mfpu_opt
= &opt
->value
;
27687 as_bad (_("unknown floating point format `%s'\n"), str
);
27692 arm_parse_float_abi (const char * str
)
27694 const struct arm_option_value_table
* opt
;
27696 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
27697 if (streq (opt
->name
, str
))
27699 mfloat_abi_opt
= opt
->value
;
27703 as_bad (_("unknown floating point abi `%s'\n"), str
);
27709 arm_parse_eabi (const char * str
)
27711 const struct arm_option_value_table
*opt
;
27713 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
27714 if (streq (opt
->name
, str
))
27716 meabi_flags
= opt
->value
;
27719 as_bad (_("unknown EABI `%s'\n"), str
);
27725 arm_parse_it_mode (const char * str
)
27727 bfd_boolean ret
= TRUE
;
27729 if (streq ("arm", str
))
27730 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
27731 else if (streq ("thumb", str
))
27732 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
27733 else if (streq ("always", str
))
27734 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
27735 else if (streq ("never", str
))
27736 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
27739 as_bad (_("unknown implicit IT mode `%s', should be "\
27740 "arm, thumb, always, or never."), str
);
27748 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
27750 codecomposer_syntax
= TRUE
;
27751 arm_comment_chars
[0] = ';';
27752 arm_line_separator_chars
[0] = 0;
27756 struct arm_long_option_table arm_long_opts
[] =
27758 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
27759 arm_parse_cpu
, NULL
},
27760 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
27761 arm_parse_arch
, NULL
},
27762 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
27763 arm_parse_fpu
, NULL
},
27764 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
27765 arm_parse_float_abi
, NULL
},
27767 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
27768 arm_parse_eabi
, NULL
},
27770 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
27771 arm_parse_it_mode
, NULL
},
27772 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
27773 arm_ccs_mode
, NULL
},
27774 {NULL
, NULL
, 0, NULL
}
27778 md_parse_option (int c
, const char * arg
)
27780 struct arm_option_table
*opt
;
27781 const struct arm_legacy_option_table
*fopt
;
27782 struct arm_long_option_table
*lopt
;
27788 target_big_endian
= 1;
27794 target_big_endian
= 0;
27798 case OPTION_FIX_V4BX
:
27806 #endif /* OBJ_ELF */
27809 /* Listing option. Just ignore these, we don't support additional
27814 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
27816 if (c
== opt
->option
[0]
27817 && ((arg
== NULL
&& opt
->option
[1] == 0)
27818 || streq (arg
, opt
->option
+ 1)))
27820 /* If the option is deprecated, tell the user. */
27821 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
27822 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
27823 arg
? arg
: "", _(opt
->deprecated
));
27825 if (opt
->var
!= NULL
)
27826 *opt
->var
= opt
->value
;
27832 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
27834 if (c
== fopt
->option
[0]
27835 && ((arg
== NULL
&& fopt
->option
[1] == 0)
27836 || streq (arg
, fopt
->option
+ 1)))
27838 /* If the option is deprecated, tell the user. */
27839 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
27840 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
27841 arg
? arg
: "", _(fopt
->deprecated
));
27843 if (fopt
->var
!= NULL
)
27844 *fopt
->var
= &fopt
->value
;
27850 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
27852 /* These options are expected to have an argument. */
27853 if (c
== lopt
->option
[0]
27855 && strncmp (arg
, lopt
->option
+ 1,
27856 strlen (lopt
->option
+ 1)) == 0)
27858 /* If the option is deprecated, tell the user. */
27859 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
27860 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
27861 _(lopt
->deprecated
));
27863 /* Call the sup-option parser. */
27864 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
27875 md_show_usage (FILE * fp
)
27877 struct arm_option_table
*opt
;
27878 struct arm_long_option_table
*lopt
;
27880 fprintf (fp
, _(" ARM-specific assembler options:\n"));
27882 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
27883 if (opt
->help
!= NULL
)
27884 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
27886 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
27887 if (lopt
->help
!= NULL
)
27888 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
27892 -EB assemble code for a big-endian cpu\n"));
27897 -EL assemble code for a little-endian cpu\n"));
27901 --fix-v4bx Allow BX in ARMv4 code\n"));
27905 --fdpic generate an FDPIC object file\n"));
27906 #endif /* OBJ_ELF */
27914 arm_feature_set flags
;
27915 } cpu_arch_ver_table
;
27917 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
27918 chronologically for architectures, with an exception for ARMv6-M and
27919 ARMv6S-M due to legacy reasons. No new architecture should have a
27920 special case. This allows for build attribute selection results to be
27921 stable when new architectures are added. */
27922 static const cpu_arch_ver_table cpu_arch_ver
[] =
27924 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
27925 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
27926 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
27927 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
27928 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
27929 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
27930 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
27931 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
27932 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
27933 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
27934 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
27935 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
27936 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
27937 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
27938 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
27939 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
27940 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
27941 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
27942 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
27943 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
27944 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
27945 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
27946 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
27947 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
27949 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
27950 always selected build attributes to match those of ARMv6-M
27951 (resp. ARMv6S-M). However, due to these architectures being a strict
27952 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
27953 would be selected when fully respecting chronology of architectures.
27954 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
27955 move them before ARMv7 architectures. */
27956 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
27957 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
27959 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
27960 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
27961 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
27962 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
27963 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
27964 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
27965 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
27966 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
27967 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
27968 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
27969 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
27970 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
27971 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
27972 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
27973 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
27974 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
27975 {-1, ARM_ARCH_NONE
}
27978 /* Set an attribute if it has not already been set by the user. */
27981 aeabi_set_attribute_int (int tag
, int value
)
27984 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27985 || !attributes_set_explicitly
[tag
])
27986 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
27990 aeabi_set_attribute_string (int tag
, const char *value
)
27993 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27994 || !attributes_set_explicitly
[tag
])
27995 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
27998 /* Return whether features in the *NEEDED feature set are available via
27999 extensions for the architecture whose feature set is *ARCH_FSET. */
28002 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
28003 const arm_feature_set
*needed
)
28005 int i
, nb_allowed_archs
;
28006 arm_feature_set ext_fset
;
28007 const struct arm_option_extension_value_table
*opt
;
28009 ext_fset
= arm_arch_none
;
28010 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
28012 /* Extension does not provide any feature we need. */
28013 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
28017 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
28018 for (i
= 0; i
< nb_allowed_archs
; i
++)
28021 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
28024 /* Extension is available, add it. */
28025 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
28026 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
28030 /* Can we enable all features in *needed? */
28031 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
28034 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
28035 a given architecture feature set *ARCH_EXT_FSET including extension feature
28036 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
28037 - if true, check for an exact match of the architecture modulo extensions;
28038 - otherwise, select build attribute value of the first superset
28039 architecture released so that results remains stable when new architectures
28041 For -march/-mcpu=all the build attribute value of the most featureful
28042 architecture is returned. Tag_CPU_arch_profile result is returned in
28046 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
28047 const arm_feature_set
*ext_fset
,
28048 char *profile
, int exact_match
)
28050 arm_feature_set arch_fset
;
28051 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
28053 /* Select most featureful architecture with all its extensions if building
28054 for -march=all as the feature sets used to set build attributes. */
28055 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
28057 /* Force revisiting of decision for each new architecture. */
28058 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
28060 return TAG_CPU_ARCH_V8
;
28063 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
28065 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
28067 arm_feature_set known_arch_fset
;
28069 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
28072 /* Base architecture match user-specified architecture and
28073 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
28074 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
28079 /* Base architecture match user-specified architecture only
28080 (eg. ARMv6-M in the same case as above). Record it in case we
28081 find a match with above condition. */
28082 else if (p_ver_ret
== NULL
28083 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
28089 /* Architecture has all features wanted. */
28090 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
28092 arm_feature_set added_fset
;
28094 /* Compute features added by this architecture over the one
28095 recorded in p_ver_ret. */
28096 if (p_ver_ret
!= NULL
)
28097 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
28099 /* First architecture that match incl. with extensions, or the
28100 only difference in features over the recorded match is
28101 features that were optional and are now mandatory. */
28102 if (p_ver_ret
== NULL
28103 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
28109 else if (p_ver_ret
== NULL
)
28111 arm_feature_set needed_ext_fset
;
28113 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
28115 /* Architecture has all features needed when using some
28116 extensions. Record it and continue searching in case there
28117 exist an architecture providing all needed features without
28118 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
28120 if (have_ext_for_needed_feat_p (&known_arch_fset
,
28127 if (p_ver_ret
== NULL
)
28131 /* Tag_CPU_arch_profile. */
28132 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
28133 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
28134 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
28135 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
28137 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
28139 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
28143 return p_ver_ret
->val
;
28146 /* Set the public EABI object attributes. */
28149 aeabi_set_public_attributes (void)
28151 char profile
= '\0';
28154 int fp16_optional
= 0;
28155 int skip_exact_match
= 0;
28156 arm_feature_set flags
, flags_arch
, flags_ext
;
28158 /* Autodetection mode, choose the architecture based the instructions
28160 if (no_cpu_selected ())
28162 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
28164 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
28165 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
28167 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
28168 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
28170 /* Code run during relaxation relies on selected_cpu being set. */
28171 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
28172 flags_ext
= arm_arch_none
;
28173 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
28174 selected_ext
= flags_ext
;
28175 selected_cpu
= flags
;
28177 /* Otherwise, choose the architecture based on the capabilities of the
28181 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
28182 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
28183 flags_ext
= selected_ext
;
28184 flags
= selected_cpu
;
28186 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
28188 /* Allow the user to override the reported architecture. */
28189 if (!ARM_FEATURE_ZERO (selected_object_arch
))
28191 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
28192 flags_ext
= arm_arch_none
;
28195 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
28197 /* When this function is run again after relaxation has happened there is no
28198 way to determine whether an architecture or CPU was specified by the user:
28199 - selected_cpu is set above for relaxation to work;
28200 - march_cpu_opt is not set if only -mcpu or .cpu is used;
28201 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
28202 Therefore, if not in -march=all case we first try an exact match and fall
28203 back to autodetection. */
28204 if (!skip_exact_match
)
28205 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
28207 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
28209 as_bad (_("no architecture contains all the instructions used\n"));
28211 /* Tag_CPU_name. */
28212 if (selected_cpu_name
[0])
28216 q
= selected_cpu_name
;
28217 if (strncmp (q
, "armv", 4) == 0)
28222 for (i
= 0; q
[i
]; i
++)
28223 q
[i
] = TOUPPER (q
[i
]);
28225 aeabi_set_attribute_string (Tag_CPU_name
, q
);
28228 /* Tag_CPU_arch. */
28229 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
28231 /* Tag_CPU_arch_profile. */
28232 if (profile
!= '\0')
28233 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
28235 /* Tag_DSP_extension. */
28236 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
28237 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
28239 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
28240 /* Tag_ARM_ISA_use. */
28241 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
28242 || ARM_FEATURE_ZERO (flags_arch
))
28243 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
28245 /* Tag_THUMB_ISA_use. */
28246 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
28247 || ARM_FEATURE_ZERO (flags_arch
))
28251 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
28252 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
28254 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
28258 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
28261 /* Tag_VFP_arch. */
28262 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
28263 aeabi_set_attribute_int (Tag_VFP_arch
,
28264 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
28266 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
28267 aeabi_set_attribute_int (Tag_VFP_arch
,
28268 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
28270 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
28273 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
28275 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
28277 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
28280 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
28281 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
28282 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
28283 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
28284 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
28286 /* Tag_ABI_HardFP_use. */
28287 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
28288 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
28289 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
28291 /* Tag_WMMX_arch. */
28292 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
28293 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
28294 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
28295 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
28297 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
28298 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
28299 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
28300 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
28301 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
28302 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
28304 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
28306 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
28310 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
28315 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
28316 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
28317 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
28321 We set Tag_DIV_use to two when integer divide instructions have been used
28322 in ARM state, or when Thumb integer divide instructions have been used,
28323 but we have no architecture profile set, nor have we any ARM instructions.
28325 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
28326 by the base architecture.
28328 For new architectures we will have to check these tests. */
28329 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
28330 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
28331 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
28332 aeabi_set_attribute_int (Tag_DIV_use
, 0);
28333 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
28334 || (profile
== '\0'
28335 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
28336 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
28337 aeabi_set_attribute_int (Tag_DIV_use
, 2);
28339 /* Tag_MP_extension_use. */
28340 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
28341 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
28343 /* Tag Virtualization_use. */
28344 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
28346 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
28349 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
28352 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
28353 finished and free extension feature bits which will not be used anymore. */
28356 arm_md_post_relax (void)
28358 aeabi_set_public_attributes ();
28359 XDELETE (mcpu_ext_opt
);
28360 mcpu_ext_opt
= NULL
;
28361 XDELETE (march_ext_opt
);
28362 march_ext_opt
= NULL
;
28365 /* Add the default contents for the .ARM.attributes section. */
28370 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
28373 aeabi_set_public_attributes ();
28375 #endif /* OBJ_ELF */
28377 /* Parse a .cpu directive. */
28380 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
28382 const struct arm_cpu_option_table
*opt
;
28386 name
= input_line_pointer
;
28387 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28388 input_line_pointer
++;
28389 saved_char
= *input_line_pointer
;
28390 *input_line_pointer
= 0;
28392 /* Skip the first "all" entry. */
28393 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
28394 if (streq (opt
->name
, name
))
28396 selected_arch
= opt
->value
;
28397 selected_ext
= opt
->ext
;
28398 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
28399 if (opt
->canonical_name
)
28400 strcpy (selected_cpu_name
, opt
->canonical_name
);
28404 for (i
= 0; opt
->name
[i
]; i
++)
28405 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
28407 selected_cpu_name
[i
] = 0;
28409 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28411 *input_line_pointer
= saved_char
;
28412 demand_empty_rest_of_line ();
28415 as_bad (_("unknown cpu `%s'"), name
);
28416 *input_line_pointer
= saved_char
;
28417 ignore_rest_of_line ();
28420 /* Parse a .arch directive. */
28423 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
28425 const struct arm_arch_option_table
*opt
;
28429 name
= input_line_pointer
;
28430 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28431 input_line_pointer
++;
28432 saved_char
= *input_line_pointer
;
28433 *input_line_pointer
= 0;
28435 /* Skip the first "all" entry. */
28436 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
28437 if (streq (opt
->name
, name
))
28439 selected_arch
= opt
->value
;
28440 selected_ext
= arm_arch_none
;
28441 selected_cpu
= selected_arch
;
28442 strcpy (selected_cpu_name
, opt
->name
);
28443 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28444 *input_line_pointer
= saved_char
;
28445 demand_empty_rest_of_line ();
28449 as_bad (_("unknown architecture `%s'\n"), name
);
28450 *input_line_pointer
= saved_char
;
28451 ignore_rest_of_line ();
28454 /* Parse a .object_arch directive. */
28457 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
28459 const struct arm_arch_option_table
*opt
;
28463 name
= input_line_pointer
;
28464 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28465 input_line_pointer
++;
28466 saved_char
= *input_line_pointer
;
28467 *input_line_pointer
= 0;
28469 /* Skip the first "all" entry. */
28470 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
28471 if (streq (opt
->name
, name
))
28473 selected_object_arch
= opt
->value
;
28474 *input_line_pointer
= saved_char
;
28475 demand_empty_rest_of_line ();
28479 as_bad (_("unknown architecture `%s'\n"), name
);
28480 *input_line_pointer
= saved_char
;
28481 ignore_rest_of_line ();
28484 /* Parse a .arch_extension directive. */
28487 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
28489 const struct arm_option_extension_value_table
*opt
;
28492 int adding_value
= 1;
28494 name
= input_line_pointer
;
28495 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28496 input_line_pointer
++;
28497 saved_char
= *input_line_pointer
;
28498 *input_line_pointer
= 0;
28500 if (strlen (name
) >= 2
28501 && strncmp (name
, "no", 2) == 0)
28507 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
28508 if (streq (opt
->name
, name
))
28510 int i
, nb_allowed_archs
=
28511 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
28512 for (i
= 0; i
< nb_allowed_archs
; i
++)
28515 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
28517 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
28521 if (i
== nb_allowed_archs
)
28523 as_bad (_("architectural extension `%s' is not allowed for the "
28524 "current base architecture"), name
);
28529 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
28532 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
28534 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
28535 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28536 *input_line_pointer
= saved_char
;
28537 demand_empty_rest_of_line ();
28538 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
28539 on this return so that duplicate extensions (extensions with the
28540 same name as a previous extension in the list) are not considered
28541 for command-line parsing. */
28545 if (opt
->name
== NULL
)
28546 as_bad (_("unknown architecture extension `%s'\n"), name
);
28548 *input_line_pointer
= saved_char
;
28549 ignore_rest_of_line ();
28552 /* Parse a .fpu directive. */
28555 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
28557 const struct arm_option_fpu_value_table
*opt
;
28561 name
= input_line_pointer
;
28562 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28563 input_line_pointer
++;
28564 saved_char
= *input_line_pointer
;
28565 *input_line_pointer
= 0;
28567 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
28568 if (streq (opt
->name
, name
))
28570 selected_fpu
= opt
->value
;
28571 #ifndef CPU_DEFAULT
28572 if (no_cpu_selected ())
28573 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
28576 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28577 *input_line_pointer
= saved_char
;
28578 demand_empty_rest_of_line ();
28582 as_bad (_("unknown floating point format `%s'\n"), name
);
28583 *input_line_pointer
= saved_char
;
28584 ignore_rest_of_line ();
28587 /* Copy symbol information. */
28590 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
28592 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
28596 /* Given a symbolic attribute NAME, return the proper integer value.
28597 Returns -1 if the attribute is not known. */
28600 arm_convert_symbolic_attribute (const char *name
)
28602 static const struct
28607 attribute_table
[] =
28609 /* When you modify this table you should
28610 also modify the list in doc/c-arm.texi. */
28611 #define T(tag) {#tag, tag}
28612 T (Tag_CPU_raw_name
),
28615 T (Tag_CPU_arch_profile
),
28616 T (Tag_ARM_ISA_use
),
28617 T (Tag_THUMB_ISA_use
),
28621 T (Tag_Advanced_SIMD_arch
),
28622 T (Tag_PCS_config
),
28623 T (Tag_ABI_PCS_R9_use
),
28624 T (Tag_ABI_PCS_RW_data
),
28625 T (Tag_ABI_PCS_RO_data
),
28626 T (Tag_ABI_PCS_GOT_use
),
28627 T (Tag_ABI_PCS_wchar_t
),
28628 T (Tag_ABI_FP_rounding
),
28629 T (Tag_ABI_FP_denormal
),
28630 T (Tag_ABI_FP_exceptions
),
28631 T (Tag_ABI_FP_user_exceptions
),
28632 T (Tag_ABI_FP_number_model
),
28633 T (Tag_ABI_align_needed
),
28634 T (Tag_ABI_align8_needed
),
28635 T (Tag_ABI_align_preserved
),
28636 T (Tag_ABI_align8_preserved
),
28637 T (Tag_ABI_enum_size
),
28638 T (Tag_ABI_HardFP_use
),
28639 T (Tag_ABI_VFP_args
),
28640 T (Tag_ABI_WMMX_args
),
28641 T (Tag_ABI_optimization_goals
),
28642 T (Tag_ABI_FP_optimization_goals
),
28643 T (Tag_compatibility
),
28644 T (Tag_CPU_unaligned_access
),
28645 T (Tag_FP_HP_extension
),
28646 T (Tag_VFP_HP_extension
),
28647 T (Tag_ABI_FP_16bit_format
),
28648 T (Tag_MPextension_use
),
28650 T (Tag_nodefaults
),
28651 T (Tag_also_compatible_with
),
28652 T (Tag_conformance
),
28654 T (Tag_Virtualization_use
),
28655 T (Tag_DSP_extension
),
28656 /* We deliberately do not include Tag_MPextension_use_legacy. */
28664 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
28665 if (streq (name
, attribute_table
[i
].name
))
28666 return attribute_table
[i
].tag
;
28671 /* Apply sym value for relocations only in the case that they are for
28672 local symbols in the same segment as the fixup and you have the
28673 respective architectural feature for blx and simple switches. */
28676 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
28679 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28680 /* PR 17444: If the local symbol is in a different section then a reloc
28681 will always be generated for it, so applying the symbol value now
28682 will result in a double offset being stored in the relocation. */
28683 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
28684 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
28686 switch (fixP
->fx_r_type
)
28688 case BFD_RELOC_ARM_PCREL_BLX
:
28689 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28690 if (ARM_IS_FUNC (fixP
->fx_addsy
))
28694 case BFD_RELOC_ARM_PCREL_CALL
:
28695 case BFD_RELOC_THUMB_PCREL_BLX
:
28696 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
28707 #endif /* OBJ_ELF */