1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 #if defined __XSCALE__
101 #define CPU_DEFAULT ARM_ARCH_XSCALE
103 #if defined __thumb__
104 #define CPU_DEFAULT ARM_ARCH_V5T
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 static arm_feature_set cpu_variant
;
130 static arm_feature_set arm_arch_used
;
131 static arm_feature_set thumb_arch_used
;
133 /* Flags stored in private area of BFD structure. */
134 static int uses_apcs_26
= FALSE
;
135 static int atpcs
= FALSE
;
136 static int support_interwork
= FALSE
;
137 static int uses_apcs_float
= FALSE
;
138 static int pic_code
= FALSE
;
139 static int fix_v4bx
= FALSE
;
140 /* Warn on using deprecated features. */
141 static int warn_on_deprecated
= TRUE
;
144 /* Variables that we set while parsing command-line options. Once all
145 options have been read we re-process these values to set the real
147 static const arm_feature_set
*legacy_cpu
= NULL
;
148 static const arm_feature_set
*legacy_fpu
= NULL
;
150 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
151 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
152 static const arm_feature_set
*march_cpu_opt
= NULL
;
153 static const arm_feature_set
*march_fpu_opt
= NULL
;
154 static const arm_feature_set
*mfpu_opt
= NULL
;
155 static const arm_feature_set
*object_arch
= NULL
;
157 /* Constants for known architecture features. */
158 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
159 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
160 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
161 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
162 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
163 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
164 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
166 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
169 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
172 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
174 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
175 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
176 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
177 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
178 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
179 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
180 static const arm_feature_set arm_ext_v4t_5
=
181 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
182 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
183 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
184 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
185 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
186 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
187 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
188 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
190 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
191 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
192 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
193 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
194 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
195 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
196 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
197 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
198 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
199 static const arm_feature_set arm_ext_m
=
200 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
202 static const arm_feature_set arm_arch_any
= ARM_ANY
;
203 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
204 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
205 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
207 static const arm_feature_set arm_cext_iwmmxt2
=
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
209 static const arm_feature_set arm_cext_iwmmxt
=
210 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
211 static const arm_feature_set arm_cext_xscale
=
212 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
213 static const arm_feature_set arm_cext_maverick
=
214 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
215 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
216 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
217 static const arm_feature_set fpu_vfp_ext_v1xd
=
218 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
219 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
220 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
221 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
222 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
223 static const arm_feature_set fpu_vfp_ext_d32
=
224 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
225 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
226 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
227 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
228 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
229 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
230 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
232 static int mfloat_abi_opt
= -1;
233 /* Record user cpu selection for object attributes. */
234 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
235 /* Must be long enough to hold any of the names in arm_cpus. */
236 static char selected_cpu_name
[16];
239 static int meabi_flags
= EABI_DEFAULT
;
241 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
244 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
249 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
254 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
255 symbolS
* GOT_symbol
;
258 /* 0: assemble for ARM,
259 1: assemble for Thumb,
260 2: assemble for Thumb even though target CPU does not support thumb
262 static int thumb_mode
= 0;
263 /* A value distinct from the possible values for thumb_mode that we
264 can use to record whether thumb_mode has been copied into the
265 tc_frag_data field of a frag. */
266 #define MODE_RECORDED (1 << 4)
268 /* Specifies the intrinsic IT insn behavior mode. */
269 enum implicit_it_mode
271 IMPLICIT_IT_MODE_NEVER
= 0x00,
272 IMPLICIT_IT_MODE_ARM
= 0x01,
273 IMPLICIT_IT_MODE_THUMB
= 0x02,
274 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
276 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
278 /* If unified_syntax is true, we are processing the new unified
279 ARM/Thumb syntax. Important differences from the old ARM mode:
281 - Immediate operands do not require a # prefix.
282 - Conditional affixes always appear at the end of the
283 instruction. (For backward compatibility, those instructions
284 that formerly had them in the middle, continue to accept them
286 - The IT instruction may appear, and if it does is validated
287 against subsequent conditional affixes. It does not generate
290 Important differences from the old Thumb mode:
292 - Immediate operands do not require a # prefix.
293 - Most of the V6T2 instructions are only available in unified mode.
294 - The .N and .W suffixes are recognized and honored (it is an error
295 if they cannot be honored).
296 - All instructions set the flags if and only if they have an 's' affix.
297 - Conditional affixes may be used. They are validated against
298 preceding IT instructions. Unlike ARM mode, you cannot use a
299 conditional affix except in the scope of an IT instruction. */
301 static bfd_boolean unified_syntax
= FALSE
;
316 enum neon_el_type type
;
320 #define NEON_MAX_TYPE_ELS 4
324 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
328 enum it_instruction_type
333 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
334 if inside, should be the last one. */
335 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
336 i.e. BKPT and NOP. */
337 IT_INSN
/* The IT insn has been parsed. */
343 unsigned long instruction
;
347 /* "uncond_value" is set to the value in place of the conditional field in
348 unconditional versions of the instruction, or -1 if nothing is
351 struct neon_type vectype
;
352 /* This does not indicate an actual NEON instruction, only that
353 the mnemonic accepts neon-style type suffixes. */
355 /* Set to the opcode if the instruction needs relaxation.
356 Zero if the instruction is not relaxed. */
360 bfd_reloc_code_real_type type
;
365 enum it_instruction_type it_insn_type
;
371 struct neon_type_el vectype
;
372 unsigned present
: 1; /* Operand present. */
373 unsigned isreg
: 1; /* Operand was a register. */
374 unsigned immisreg
: 1; /* .imm field is a second register. */
375 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
376 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
377 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
378 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
379 instructions. This allows us to disambiguate ARM <-> vector insns. */
380 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
381 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
382 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
383 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
384 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
385 unsigned writeback
: 1; /* Operand has trailing ! */
386 unsigned preind
: 1; /* Preindexed address. */
387 unsigned postind
: 1; /* Postindexed address. */
388 unsigned negative
: 1; /* Index register was negated. */
389 unsigned shifted
: 1; /* Shift applied to operation. */
390 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
394 static struct arm_it inst
;
396 #define NUM_FLOAT_VALS 8
398 const char * fp_const
[] =
400 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
403 /* Number of littlenums required to hold an extended precision number. */
404 #define MAX_LITTLENUMS 6
406 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
416 #define CP_T_X 0x00008000
417 #define CP_T_Y 0x00400000
419 #define CONDS_BIT 0x00100000
420 #define LOAD_BIT 0x00100000
422 #define DOUBLE_LOAD_FLAG 0x00000001
426 const char * template_name
;
430 #define COND_ALWAYS 0xE
434 const char * template_name
;
438 struct asm_barrier_opt
440 const char * template_name
;
444 /* The bit that distinguishes CPSR and SPSR. */
445 #define SPSR_BIT (1 << 22)
447 /* The individual PSR flag bits. */
448 #define PSR_c (1 << 16)
449 #define PSR_x (1 << 17)
450 #define PSR_s (1 << 18)
451 #define PSR_f (1 << 19)
456 bfd_reloc_code_real_type reloc
;
461 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
462 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
467 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
470 /* Bits for DEFINED field in neon_typed_alias. */
471 #define NTA_HASTYPE 1
472 #define NTA_HASINDEX 2
474 struct neon_typed_alias
476 unsigned char defined
;
478 struct neon_type_el eltype
;
481 /* ARM register categories. This includes coprocessor numbers and various
482 architecture extensions' registers. */
508 /* Structure for a hash table entry for a register.
509 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
510 information which states whether a vector type or index is specified (for a
511 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
515 unsigned char number
;
517 unsigned char builtin
;
518 struct neon_typed_alias
* neon
;
521 /* Diagnostics used when we don't get a register of the expected type. */
522 const char * const reg_expected_msgs
[] =
524 N_("ARM register expected"),
525 N_("bad or missing co-processor number"),
526 N_("co-processor register expected"),
527 N_("FPA register expected"),
528 N_("VFP single precision register expected"),
529 N_("VFP/Neon double precision register expected"),
530 N_("Neon quad precision register expected"),
531 N_("VFP single or double precision register expected"),
532 N_("Neon double or quad precision register expected"),
533 N_("VFP single, double or Neon quad precision register expected"),
534 N_("VFP system register expected"),
535 N_("Maverick MVF register expected"),
536 N_("Maverick MVD register expected"),
537 N_("Maverick MVFX register expected"),
538 N_("Maverick MVDX register expected"),
539 N_("Maverick MVAX register expected"),
540 N_("Maverick DSPSC register expected"),
541 N_("iWMMXt data register expected"),
542 N_("iWMMXt control register expected"),
543 N_("iWMMXt scalar register expected"),
544 N_("XScale accumulator register expected"),
547 /* Some well known registers that we refer to directly elsewhere. */
552 /* ARM instructions take 4bytes in the object file, Thumb instructions
558 /* Basic string to match. */
559 const char * template_name
;
561 /* Parameters to instruction. */
562 unsigned char operands
[8];
564 /* Conditional tag - see opcode_lookup. */
565 unsigned int tag
: 4;
567 /* Basic instruction code. */
568 unsigned int avalue
: 28;
570 /* Thumb-format instruction code. */
573 /* Which architecture variant provides this instruction. */
574 const arm_feature_set
* avariant
;
575 const arm_feature_set
* tvariant
;
577 /* Function to call to encode instruction in ARM format. */
578 void (* aencode
) (void);
580 /* Function to call to encode instruction in Thumb format. */
581 void (* tencode
) (void);
584 /* Defines for various bits that we will want to toggle. */
585 #define INST_IMMEDIATE 0x02000000
586 #define OFFSET_REG 0x02000000
587 #define HWOFFSET_IMM 0x00400000
588 #define SHIFT_BY_REG 0x00000010
589 #define PRE_INDEX 0x01000000
590 #define INDEX_UP 0x00800000
591 #define WRITE_BACK 0x00200000
592 #define LDM_TYPE_2_OR_3 0x00400000
593 #define CPSI_MMOD 0x00020000
595 #define LITERAL_MASK 0xf000f000
596 #define OPCODE_MASK 0xfe1fffff
597 #define V4_STR_BIT 0x00000020
599 #define T2_SUBS_PC_LR 0xf3de8f00
601 #define DATA_OP_SHIFT 21
603 #define T2_OPCODE_MASK 0xfe1fffff
604 #define T2_DATA_OP_SHIFT 21
606 /* Codes to distinguish the arithmetic instructions. */
617 #define OPCODE_CMP 10
618 #define OPCODE_CMN 11
619 #define OPCODE_ORR 12
620 #define OPCODE_MOV 13
621 #define OPCODE_BIC 14
622 #define OPCODE_MVN 15
624 #define T2_OPCODE_AND 0
625 #define T2_OPCODE_BIC 1
626 #define T2_OPCODE_ORR 2
627 #define T2_OPCODE_ORN 3
628 #define T2_OPCODE_EOR 4
629 #define T2_OPCODE_ADD 8
630 #define T2_OPCODE_ADC 10
631 #define T2_OPCODE_SBC 11
632 #define T2_OPCODE_SUB 13
633 #define T2_OPCODE_RSB 14
635 #define T_OPCODE_MUL 0x4340
636 #define T_OPCODE_TST 0x4200
637 #define T_OPCODE_CMN 0x42c0
638 #define T_OPCODE_NEG 0x4240
639 #define T_OPCODE_MVN 0x43c0
641 #define T_OPCODE_ADD_R3 0x1800
642 #define T_OPCODE_SUB_R3 0x1a00
643 #define T_OPCODE_ADD_HI 0x4400
644 #define T_OPCODE_ADD_ST 0xb000
645 #define T_OPCODE_SUB_ST 0xb080
646 #define T_OPCODE_ADD_SP 0xa800
647 #define T_OPCODE_ADD_PC 0xa000
648 #define T_OPCODE_ADD_I8 0x3000
649 #define T_OPCODE_SUB_I8 0x3800
650 #define T_OPCODE_ADD_I3 0x1c00
651 #define T_OPCODE_SUB_I3 0x1e00
653 #define T_OPCODE_ASR_R 0x4100
654 #define T_OPCODE_LSL_R 0x4080
655 #define T_OPCODE_LSR_R 0x40c0
656 #define T_OPCODE_ROR_R 0x41c0
657 #define T_OPCODE_ASR_I 0x1000
658 #define T_OPCODE_LSL_I 0x0000
659 #define T_OPCODE_LSR_I 0x0800
661 #define T_OPCODE_MOV_I8 0x2000
662 #define T_OPCODE_CMP_I8 0x2800
663 #define T_OPCODE_CMP_LR 0x4280
664 #define T_OPCODE_MOV_HR 0x4600
665 #define T_OPCODE_CMP_HR 0x4500
667 #define T_OPCODE_LDR_PC 0x4800
668 #define T_OPCODE_LDR_SP 0x9800
669 #define T_OPCODE_STR_SP 0x9000
670 #define T_OPCODE_LDR_IW 0x6800
671 #define T_OPCODE_STR_IW 0x6000
672 #define T_OPCODE_LDR_IH 0x8800
673 #define T_OPCODE_STR_IH 0x8000
674 #define T_OPCODE_LDR_IB 0x7800
675 #define T_OPCODE_STR_IB 0x7000
676 #define T_OPCODE_LDR_RW 0x5800
677 #define T_OPCODE_STR_RW 0x5000
678 #define T_OPCODE_LDR_RH 0x5a00
679 #define T_OPCODE_STR_RH 0x5200
680 #define T_OPCODE_LDR_RB 0x5c00
681 #define T_OPCODE_STR_RB 0x5400
683 #define T_OPCODE_PUSH 0xb400
684 #define T_OPCODE_POP 0xbc00
686 #define T_OPCODE_BRANCH 0xe000
688 #define THUMB_SIZE 2 /* Size of thumb instruction. */
689 #define THUMB_PP_PC_LR 0x0100
690 #define THUMB_LOAD_BIT 0x0800
691 #define THUMB2_LOAD_BIT 0x00100000
693 #define BAD_ARGS _("bad arguments to instruction")
694 #define BAD_SP _("r13 not allowed here")
695 #define BAD_PC _("r15 not allowed here")
696 #define BAD_COND _("instruction cannot be conditional")
697 #define BAD_OVERLAP _("registers may not be the same")
698 #define BAD_HIREG _("lo register required")
699 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
700 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
701 #define BAD_BRANCH _("branch must be last instruction in IT block")
702 #define BAD_NOT_IT _("instruction not allowed in IT block")
703 #define BAD_FPU _("selected FPU does not support instruction")
704 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
705 #define BAD_IT_COND _("incorrect condition in IT block")
706 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
707 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
709 static struct hash_control
* arm_ops_hsh
;
710 static struct hash_control
* arm_cond_hsh
;
711 static struct hash_control
* arm_shift_hsh
;
712 static struct hash_control
* arm_psr_hsh
;
713 static struct hash_control
* arm_v7m_psr_hsh
;
714 static struct hash_control
* arm_reg_hsh
;
715 static struct hash_control
* arm_reloc_hsh
;
716 static struct hash_control
* arm_barrier_opt_hsh
;
718 /* Stuff needed to resolve the label ambiguity
727 symbolS
* last_label_seen
;
728 static int label_is_thumb_function_name
= FALSE
;
730 /* Literal pool structure. Held on a per-section
731 and per-sub-section basis. */
733 #define MAX_LITERAL_POOL_SIZE 1024
734 typedef struct literal_pool
736 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
737 unsigned int next_free_entry
;
742 struct literal_pool
* next
;
745 /* Pointer to a linked list of literal pools. */
746 literal_pool
* list_of_pools
= NULL
;
749 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
751 static struct current_it now_it
;
755 now_it_compatible (int cond
)
757 return (cond
& ~1) == (now_it
.cc
& ~1);
761 conditional_insn (void)
763 return inst
.cond
!= COND_ALWAYS
;
766 static int in_it_block (void);
768 static int handle_it_state (void);
770 static void force_automatic_it_block_close (void);
772 static void it_fsm_post_encode (void);
774 #define set_it_insn_type(type) \
777 inst.it_insn_type = type; \
778 if (handle_it_state () == FAIL) \
783 #define set_it_insn_type_nonvoid(type, failret) \
786 inst.it_insn_type = type; \
787 if (handle_it_state () == FAIL) \
792 #define set_it_insn_type_last() \
795 if (inst.cond == COND_ALWAYS) \
796 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
798 set_it_insn_type (INSIDE_IT_LAST_INSN); \
804 /* This array holds the chars that always start a comment. If the
805 pre-processor is disabled, these aren't very useful. */
806 const char comment_chars
[] = "@";
808 /* This array holds the chars that only start a comment at the beginning of
809 a line. If the line seems to have the form '# 123 filename'
810 .line and .file directives will appear in the pre-processed output. */
811 /* Note that input_file.c hand checks for '#' at the beginning of the
812 first line of the input file. This is because the compiler outputs
813 #NO_APP at the beginning of its output. */
814 /* Also note that comments like this one will always work. */
815 const char line_comment_chars
[] = "#";
817 const char line_separator_chars
[] = ";";
819 /* Chars that can be used to separate mant
820 from exp in floating point numbers. */
821 const char EXP_CHARS
[] = "eE";
823 /* Chars that mean this number is a floating point constant. */
827 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
829 /* Prefix characters that indicate the start of an immediate
831 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
833 /* Separator character handling. */
835 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
838 skip_past_char (char ** str
, char c
)
849 #define skip_past_comma(str) skip_past_char (str, ',')
851 /* Arithmetic expressions (possibly involving symbols). */
853 /* Return TRUE if anything in the expression is a bignum. */
856 walk_no_bignums (symbolS
* sp
)
858 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
861 if (symbol_get_value_expression (sp
)->X_add_symbol
)
863 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
864 || (symbol_get_value_expression (sp
)->X_op_symbol
865 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
871 static int in_my_get_expression
= 0;
873 /* Third argument to my_get_expression. */
874 #define GE_NO_PREFIX 0
875 #define GE_IMM_PREFIX 1
876 #define GE_OPT_PREFIX 2
877 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
878 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
879 #define GE_OPT_PREFIX_BIG 3
882 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
887 /* In unified syntax, all prefixes are optional. */
889 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
894 case GE_NO_PREFIX
: break;
896 if (!is_immediate_prefix (**str
))
898 inst
.error
= _("immediate expression requires a # prefix");
904 case GE_OPT_PREFIX_BIG
:
905 if (is_immediate_prefix (**str
))
911 memset (ep
, 0, sizeof (expressionS
));
913 save_in
= input_line_pointer
;
914 input_line_pointer
= *str
;
915 in_my_get_expression
= 1;
916 seg
= expression (ep
);
917 in_my_get_expression
= 0;
919 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
921 /* We found a bad or missing expression in md_operand(). */
922 *str
= input_line_pointer
;
923 input_line_pointer
= save_in
;
924 if (inst
.error
== NULL
)
925 inst
.error
= (ep
->X_op
== O_absent
926 ? _("missing expression") :_("bad expression"));
931 if (seg
!= absolute_section
932 && seg
!= text_section
933 && seg
!= data_section
934 && seg
!= bss_section
935 && seg
!= undefined_section
)
937 inst
.error
= _("bad segment");
938 *str
= input_line_pointer
;
939 input_line_pointer
= save_in
;
944 /* Get rid of any bignums now, so that we don't generate an error for which
945 we can't establish a line number later on. Big numbers are never valid
946 in instructions, which is where this routine is always called. */
947 if (prefix_mode
!= GE_OPT_PREFIX_BIG
948 && (ep
->X_op
== O_big
950 && (walk_no_bignums (ep
->X_add_symbol
)
952 && walk_no_bignums (ep
->X_op_symbol
))))))
954 inst
.error
= _("invalid constant");
955 *str
= input_line_pointer
;
956 input_line_pointer
= save_in
;
960 *str
= input_line_pointer
;
961 input_line_pointer
= save_in
;
965 /* Turn a string in input_line_pointer into a floating point constant
966 of type TYPE, and store the appropriate bytes in *LITP. The number
967 of LITTLENUMS emitted is stored in *SIZEP. An error message is
968 returned, or NULL on OK.
970 Note that fp constants aren't represent in the normal way on the ARM.
971 In big endian mode, things are as expected. However, in little endian
972 mode fp constants are big-endian word-wise, and little-endian byte-wise
973 within the words. For example, (double) 1.1 in big endian mode is
974 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
975 the byte sequence 99 99 f1 3f 9a 99 99 99.
977 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
980 md_atof (int type
, char * litP
, int * sizeP
)
983 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1015 return _("Unrecognized or unsupported floating point constant");
1018 t
= atof_ieee (input_line_pointer
, type
, words
);
1020 input_line_pointer
= t
;
1021 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1023 if (target_big_endian
)
1025 for (i
= 0; i
< prec
; i
++)
1027 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1028 litP
+= sizeof (LITTLENUM_TYPE
);
1033 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1034 for (i
= prec
- 1; i
>= 0; i
--)
1036 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1037 litP
+= sizeof (LITTLENUM_TYPE
);
1040 /* For a 4 byte float the order of elements in `words' is 1 0.
1041 For an 8 byte float the order is 1 0 3 2. */
1042 for (i
= 0; i
< prec
; i
+= 2)
1044 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1045 sizeof (LITTLENUM_TYPE
));
1046 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1047 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1048 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1055 /* We handle all bad expressions here, so that we can report the faulty
1056 instruction in the error message. */
1058 md_operand (expressionS
* exp
)
1060 if (in_my_get_expression
)
1061 exp
->X_op
= O_illegal
;
1064 /* Immediate values. */
1066 /* Generic immediate-value read function for use in directives.
1067 Accepts anything that 'expression' can fold to a constant.
1068 *val receives the number. */
1071 immediate_for_directive (int *val
)
1074 exp
.X_op
= O_illegal
;
1076 if (is_immediate_prefix (*input_line_pointer
))
1078 input_line_pointer
++;
1082 if (exp
.X_op
!= O_constant
)
1084 as_bad (_("expected #constant"));
1085 ignore_rest_of_line ();
1088 *val
= exp
.X_add_number
;
1093 /* Register parsing. */
1095 /* Generic register parser. CCP points to what should be the
1096 beginning of a register name. If it is indeed a valid register
1097 name, advance CCP over it and return the reg_entry structure;
1098 otherwise return NULL. Does not issue diagnostics. */
1100 static struct reg_entry
*
1101 arm_reg_parse_multi (char **ccp
)
1105 struct reg_entry
*reg
;
1107 #ifdef REGISTER_PREFIX
1108 if (*start
!= REGISTER_PREFIX
)
1112 #ifdef OPTIONAL_REGISTER_PREFIX
1113 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1118 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1123 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1125 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1135 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1136 enum arm_reg_type type
)
1138 /* Alternative syntaxes are accepted for a few register classes. */
1145 /* Generic coprocessor register names are allowed for these. */
1146 if (reg
&& reg
->type
== REG_TYPE_CN
)
1151 /* For backward compatibility, a bare number is valid here. */
1153 unsigned long processor
= strtoul (start
, ccp
, 10);
1154 if (*ccp
!= start
&& processor
<= 15)
1158 case REG_TYPE_MMXWC
:
1159 /* WC includes WCG. ??? I'm not sure this is true for all
1160 instructions that take WC registers. */
1161 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1172 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1173 return value is the register number or FAIL. */
1176 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1179 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1182 /* Do not allow a scalar (reg+index) to parse as a register. */
1183 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1186 if (reg
&& reg
->type
== type
)
1189 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1196 /* Parse a Neon type specifier. *STR should point at the leading '.'
1197 character. Does no verification at this stage that the type fits the opcode
1204 Can all be legally parsed by this function.
1206 Fills in neon_type struct pointer with parsed information, and updates STR
1207 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1208 type, FAIL if not. */
1211 parse_neon_type (struct neon_type
*type
, char **str
)
1218 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1220 enum neon_el_type thistype
= NT_untyped
;
1221 unsigned thissize
= -1u;
1228 /* Just a size without an explicit type. */
1232 switch (TOLOWER (*ptr
))
1234 case 'i': thistype
= NT_integer
; break;
1235 case 'f': thistype
= NT_float
; break;
1236 case 'p': thistype
= NT_poly
; break;
1237 case 's': thistype
= NT_signed
; break;
1238 case 'u': thistype
= NT_unsigned
; break;
1240 thistype
= NT_float
;
1245 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1251 /* .f is an abbreviation for .f32. */
1252 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1257 thissize
= strtoul (ptr
, &ptr
, 10);
1259 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1262 as_bad (_("bad size %d in type specifier"), thissize
);
1270 type
->el
[type
->elems
].type
= thistype
;
1271 type
->el
[type
->elems
].size
= thissize
;
1276 /* Empty/missing type is not a successful parse. */
1277 if (type
->elems
== 0)
1285 /* Errors may be set multiple times during parsing or bit encoding
1286 (particularly in the Neon bits), but usually the earliest error which is set
1287 will be the most meaningful. Avoid overwriting it with later (cascading)
1288 errors by calling this function. */
1291 first_error (const char *err
)
1297 /* Parse a single type, e.g. ".s32", leading period included. */
1299 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1302 struct neon_type optype
;
1306 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1308 if (optype
.elems
== 1)
1309 *vectype
= optype
.el
[0];
1312 first_error (_("only one type should be specified for operand"));
1318 first_error (_("vector type expected"));
1330 /* Special meanings for indices (which have a range of 0-7), which will fit into
1333 #define NEON_ALL_LANES 15
1334 #define NEON_INTERLEAVE_LANES 14
1336 /* Parse either a register or a scalar, with an optional type. Return the
1337 register number, and optionally fill in the actual type of the register
1338 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1339 type/index information in *TYPEINFO. */
1342 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1343 enum arm_reg_type
*rtype
,
1344 struct neon_typed_alias
*typeinfo
)
1347 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1348 struct neon_typed_alias atype
;
1349 struct neon_type_el parsetype
;
1353 atype
.eltype
.type
= NT_invtype
;
1354 atype
.eltype
.size
= -1;
1356 /* Try alternate syntax for some types of register. Note these are mutually
1357 exclusive with the Neon syntax extensions. */
1360 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1368 /* Undo polymorphism when a set of register types may be accepted. */
1369 if ((type
== REG_TYPE_NDQ
1370 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1371 || (type
== REG_TYPE_VFSD
1372 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1373 || (type
== REG_TYPE_NSDQ
1374 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1375 || reg
->type
== REG_TYPE_NQ
))
1376 || (type
== REG_TYPE_MMXWC
1377 && (reg
->type
== REG_TYPE_MMXWCG
)))
1378 type
= (enum arm_reg_type
) reg
->type
;
1380 if (type
!= reg
->type
)
1386 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1388 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1390 first_error (_("can't redefine type for operand"));
1393 atype
.defined
|= NTA_HASTYPE
;
1394 atype
.eltype
= parsetype
;
1397 if (skip_past_char (&str
, '[') == SUCCESS
)
1399 if (type
!= REG_TYPE_VFD
)
1401 first_error (_("only D registers may be indexed"));
1405 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1407 first_error (_("can't change index for operand"));
1411 atype
.defined
|= NTA_HASINDEX
;
1413 if (skip_past_char (&str
, ']') == SUCCESS
)
1414 atype
.index
= NEON_ALL_LANES
;
1419 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1421 if (exp
.X_op
!= O_constant
)
1423 first_error (_("constant expression required"));
1427 if (skip_past_char (&str
, ']') == FAIL
)
1430 atype
.index
= exp
.X_add_number
;
1445 /* Like arm_reg_parse, but allow allow the following extra features:
1446 - If RTYPE is non-zero, return the (possibly restricted) type of the
1447 register (e.g. Neon double or quad reg when either has been requested).
1448 - If this is a Neon vector type with additional type information, fill
1449 in the struct pointed to by VECTYPE (if non-NULL).
1450 This function will fault on encountering a scalar. */
1453 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1454 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1456 struct neon_typed_alias atype
;
1458 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1463 /* Do not allow a scalar (reg+index) to parse as a register. */
1464 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1466 first_error (_("register operand expected, but got scalar"));
1471 *vectype
= atype
.eltype
;
1478 #define NEON_SCALAR_REG(X) ((X) >> 4)
1479 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1481 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1482 have enough information to be able to do a good job bounds-checking. So, we
1483 just do easy checks here, and do further checks later. */
1486 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1490 struct neon_typed_alias atype
;
1492 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1494 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1497 if (atype
.index
== NEON_ALL_LANES
)
1499 first_error (_("scalar must have an index"));
1502 else if (atype
.index
>= 64 / elsize
)
1504 first_error (_("scalar index out of range"));
1509 *type
= atype
.eltype
;
1513 return reg
* 16 + atype
.index
;
1516 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1519 parse_reg_list (char ** strp
)
1521 char * str
= * strp
;
1525 /* We come back here if we get ranges concatenated by '+' or '|'. */
1540 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1542 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1552 first_error (_("bad range in register list"));
1556 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1558 if (range
& (1 << i
))
1560 (_("Warning: duplicated register (r%d) in register list"),
1568 if (range
& (1 << reg
))
1569 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1571 else if (reg
<= cur_reg
)
1572 as_tsktsk (_("Warning: register range not in ascending order"));
1577 while (skip_past_comma (&str
) != FAIL
1578 || (in_range
= 1, *str
++ == '-'));
1583 first_error (_("missing `}'"));
1591 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1594 if (exp
.X_op
== O_constant
)
1596 if (exp
.X_add_number
1597 != (exp
.X_add_number
& 0x0000ffff))
1599 inst
.error
= _("invalid register mask");
1603 if ((range
& exp
.X_add_number
) != 0)
1605 int regno
= range
& exp
.X_add_number
;
1608 regno
= (1 << regno
) - 1;
1610 (_("Warning: duplicated register (r%d) in register list"),
1614 range
|= exp
.X_add_number
;
1618 if (inst
.reloc
.type
!= 0)
1620 inst
.error
= _("expression too complex");
1624 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1625 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1626 inst
.reloc
.pc_rel
= 0;
1630 if (*str
== '|' || *str
== '+')
1636 while (another_range
);
1642 /* Types of registers in a list. */
1651 /* Parse a VFP register list. If the string is invalid return FAIL.
1652 Otherwise return the number of registers, and set PBASE to the first
1653 register. Parses registers of type ETYPE.
1654 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1655 - Q registers can be used to specify pairs of D registers
1656 - { } can be omitted from around a singleton register list
1657 FIXME: This is not implemented, as it would require backtracking in
1660 This could be done (the meaning isn't really ambiguous), but doesn't
1661 fit in well with the current parsing framework.
1662 - 32 D registers may be used (also true for VFPv3).
1663 FIXME: Types are ignored in these register lists, which is probably a
1667 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1672 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1676 unsigned long mask
= 0;
1681 inst
.error
= _("expecting {");
1690 regtype
= REG_TYPE_VFS
;
1695 regtype
= REG_TYPE_VFD
;
1698 case REGLIST_NEON_D
:
1699 regtype
= REG_TYPE_NDQ
;
1703 if (etype
!= REGLIST_VFP_S
)
1705 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1706 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1710 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1713 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1720 base_reg
= max_regs
;
1724 int setmask
= 1, addregs
= 1;
1726 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1728 if (new_base
== FAIL
)
1730 first_error (_(reg_expected_msgs
[regtype
]));
1734 if (new_base
>= max_regs
)
1736 first_error (_("register out of range in list"));
1740 /* Note: a value of 2 * n is returned for the register Q<n>. */
1741 if (regtype
== REG_TYPE_NQ
)
1747 if (new_base
< base_reg
)
1748 base_reg
= new_base
;
1750 if (mask
& (setmask
<< new_base
))
1752 first_error (_("invalid register list"));
1756 if ((mask
>> new_base
) != 0 && ! warned
)
1758 as_tsktsk (_("register list not in ascending order"));
1762 mask
|= setmask
<< new_base
;
1765 if (*str
== '-') /* We have the start of a range expression */
1771 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1774 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1778 if (high_range
>= max_regs
)
1780 first_error (_("register out of range in list"));
1784 if (regtype
== REG_TYPE_NQ
)
1785 high_range
= high_range
+ 1;
1787 if (high_range
<= new_base
)
1789 inst
.error
= _("register range not in ascending order");
1793 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1795 if (mask
& (setmask
<< new_base
))
1797 inst
.error
= _("invalid register list");
1801 mask
|= setmask
<< new_base
;
1806 while (skip_past_comma (&str
) != FAIL
);
1810 /* Sanity check -- should have raised a parse error above. */
1811 if (count
== 0 || count
> max_regs
)
1816 /* Final test -- the registers must be consecutive. */
1818 for (i
= 0; i
< count
; i
++)
1820 if ((mask
& (1u << i
)) == 0)
1822 inst
.error
= _("non-contiguous register range");
1832 /* True if two alias types are the same. */
1835 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1843 if (a
->defined
!= b
->defined
)
1846 if ((a
->defined
& NTA_HASTYPE
) != 0
1847 && (a
->eltype
.type
!= b
->eltype
.type
1848 || a
->eltype
.size
!= b
->eltype
.size
))
1851 if ((a
->defined
& NTA_HASINDEX
) != 0
1852 && (a
->index
!= b
->index
))
1858 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1859 The base register is put in *PBASE.
1860 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1862 The register stride (minus one) is put in bit 4 of the return value.
1863 Bits [6:5] encode the list length (minus one).
1864 The type of the list elements is put in *ELTYPE, if non-NULL. */
1866 #define NEON_LANE(X) ((X) & 0xf)
1867 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1868 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1871 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1872 struct neon_type_el
*eltype
)
1879 int leading_brace
= 0;
1880 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1882 const char *const incr_error
= _("register stride must be 1 or 2");
1883 const char *const type_error
= _("mismatched element/structure types in list");
1884 struct neon_typed_alias firsttype
;
1886 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1891 struct neon_typed_alias atype
;
1892 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1896 first_error (_(reg_expected_msgs
[rtype
]));
1903 if (rtype
== REG_TYPE_NQ
)
1910 else if (reg_incr
== -1)
1912 reg_incr
= getreg
- base_reg
;
1913 if (reg_incr
< 1 || reg_incr
> 2)
1915 first_error (_(incr_error
));
1919 else if (getreg
!= base_reg
+ reg_incr
* count
)
1921 first_error (_(incr_error
));
1925 if (! neon_alias_types_same (&atype
, &firsttype
))
1927 first_error (_(type_error
));
1931 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1935 struct neon_typed_alias htype
;
1936 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1938 lane
= NEON_INTERLEAVE_LANES
;
1939 else if (lane
!= NEON_INTERLEAVE_LANES
)
1941 first_error (_(type_error
));
1946 else if (reg_incr
!= 1)
1948 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1952 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1955 first_error (_(reg_expected_msgs
[rtype
]));
1958 if (! neon_alias_types_same (&htype
, &firsttype
))
1960 first_error (_(type_error
));
1963 count
+= hireg
+ dregs
- getreg
;
1967 /* If we're using Q registers, we can't use [] or [n] syntax. */
1968 if (rtype
== REG_TYPE_NQ
)
1974 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1978 else if (lane
!= atype
.index
)
1980 first_error (_(type_error
));
1984 else if (lane
== -1)
1985 lane
= NEON_INTERLEAVE_LANES
;
1986 else if (lane
!= NEON_INTERLEAVE_LANES
)
1988 first_error (_(type_error
));
1993 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1995 /* No lane set by [x]. We must be interleaving structures. */
1997 lane
= NEON_INTERLEAVE_LANES
;
2000 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2001 || (count
> 1 && reg_incr
== -1))
2003 first_error (_("error parsing element/structure list"));
2007 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2009 first_error (_("expected }"));
2017 *eltype
= firsttype
.eltype
;
2022 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2025 /* Parse an explicit relocation suffix on an expression. This is
2026 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2027 arm_reloc_hsh contains no entries, so this function can only
2028 succeed if there is no () after the word. Returns -1 on error,
2029 BFD_RELOC_UNUSED if there wasn't any suffix. */
2031 parse_reloc (char **str
)
2033 struct reloc_entry
*r
;
2037 return BFD_RELOC_UNUSED
;
2042 while (*q
&& *q
!= ')' && *q
!= ',')
2047 if ((r
= (struct reloc_entry
*)
2048 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2055 /* Directives: register aliases. */
2057 static struct reg_entry
*
2058 insert_reg_alias (char *str
, int number
, int type
)
2060 struct reg_entry
*new_reg
;
2063 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2065 if (new_reg
->builtin
)
2066 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2068 /* Only warn about a redefinition if it's not defined as the
2070 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2071 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2076 name
= xstrdup (str
);
2077 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2079 new_reg
->name
= name
;
2080 new_reg
->number
= number
;
2081 new_reg
->type
= type
;
2082 new_reg
->builtin
= FALSE
;
2083 new_reg
->neon
= NULL
;
2085 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2092 insert_neon_reg_alias (char *str
, int number
, int type
,
2093 struct neon_typed_alias
*atype
)
2095 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2099 first_error (_("attempt to redefine typed alias"));
2105 reg
->neon
= (struct neon_typed_alias
*)
2106 xmalloc (sizeof (struct neon_typed_alias
));
2107 *reg
->neon
= *atype
;
2111 /* Look for the .req directive. This is of the form:
2113 new_register_name .req existing_register_name
2115 If we find one, or if it looks sufficiently like one that we want to
2116 handle any error here, return TRUE. Otherwise return FALSE. */
2119 create_register_alias (char * newname
, char *p
)
2121 struct reg_entry
*old
;
2122 char *oldname
, *nbuf
;
2125 /* The input scrubber ensures that whitespace after the mnemonic is
2126 collapsed to single spaces. */
2128 if (strncmp (oldname
, " .req ", 6) != 0)
2132 if (*oldname
== '\0')
2135 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2138 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2142 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2143 the desired alias name, and p points to its end. If not, then
2144 the desired alias name is in the global original_case_string. */
2145 #ifdef TC_CASE_SENSITIVE
2148 newname
= original_case_string
;
2149 nlen
= strlen (newname
);
2152 nbuf
= (char *) alloca (nlen
+ 1);
2153 memcpy (nbuf
, newname
, nlen
);
2156 /* Create aliases under the new name as stated; an all-lowercase
2157 version of the new name; and an all-uppercase version of the new
2159 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2161 for (p
= nbuf
; *p
; p
++)
2164 if (strncmp (nbuf
, newname
, nlen
))
2166 /* If this attempt to create an additional alias fails, do not bother
2167 trying to create the all-lower case alias. We will fail and issue
2168 a second, duplicate error message. This situation arises when the
2169 programmer does something like:
2172 The second .req creates the "Foo" alias but then fails to create
2173 the artificial FOO alias because it has already been created by the
2175 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2179 for (p
= nbuf
; *p
; p
++)
2182 if (strncmp (nbuf
, newname
, nlen
))
2183 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2189 /* Create a Neon typed/indexed register alias using directives, e.g.:
2194 These typed registers can be used instead of the types specified after the
2195 Neon mnemonic, so long as all operands given have types. Types can also be
2196 specified directly, e.g.:
2197 vadd d0.s32, d1.s32, d2.s32 */
2200 create_neon_reg_alias (char *newname
, char *p
)
2202 enum arm_reg_type basetype
;
2203 struct reg_entry
*basereg
;
2204 struct reg_entry mybasereg
;
2205 struct neon_type ntype
;
2206 struct neon_typed_alias typeinfo
;
2207 char *namebuf
, *nameend
;
2210 typeinfo
.defined
= 0;
2211 typeinfo
.eltype
.type
= NT_invtype
;
2212 typeinfo
.eltype
.size
= -1;
2213 typeinfo
.index
= -1;
2217 if (strncmp (p
, " .dn ", 5) == 0)
2218 basetype
= REG_TYPE_VFD
;
2219 else if (strncmp (p
, " .qn ", 5) == 0)
2220 basetype
= REG_TYPE_NQ
;
2229 basereg
= arm_reg_parse_multi (&p
);
2231 if (basereg
&& basereg
->type
!= basetype
)
2233 as_bad (_("bad type for register"));
2237 if (basereg
== NULL
)
2240 /* Try parsing as an integer. */
2241 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2242 if (exp
.X_op
!= O_constant
)
2244 as_bad (_("expression must be constant"));
2247 basereg
= &mybasereg
;
2248 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2254 typeinfo
= *basereg
->neon
;
2256 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2258 /* We got a type. */
2259 if (typeinfo
.defined
& NTA_HASTYPE
)
2261 as_bad (_("can't redefine the type of a register alias"));
2265 typeinfo
.defined
|= NTA_HASTYPE
;
2266 if (ntype
.elems
!= 1)
2268 as_bad (_("you must specify a single type only"));
2271 typeinfo
.eltype
= ntype
.el
[0];
2274 if (skip_past_char (&p
, '[') == SUCCESS
)
2277 /* We got a scalar index. */
2279 if (typeinfo
.defined
& NTA_HASINDEX
)
2281 as_bad (_("can't redefine the index of a scalar alias"));
2285 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2287 if (exp
.X_op
!= O_constant
)
2289 as_bad (_("scalar index must be constant"));
2293 typeinfo
.defined
|= NTA_HASINDEX
;
2294 typeinfo
.index
= exp
.X_add_number
;
2296 if (skip_past_char (&p
, ']') == FAIL
)
2298 as_bad (_("expecting ]"));
2303 namelen
= nameend
- newname
;
2304 namebuf
= (char *) alloca (namelen
+ 1);
2305 strncpy (namebuf
, newname
, namelen
);
2306 namebuf
[namelen
] = '\0';
2308 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2309 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2311 /* Insert name in all uppercase. */
2312 for (p
= namebuf
; *p
; p
++)
2315 if (strncmp (namebuf
, newname
, namelen
))
2316 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2317 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2319 /* Insert name in all lowercase. */
2320 for (p
= namebuf
; *p
; p
++)
2323 if (strncmp (namebuf
, newname
, namelen
))
2324 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2325 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2330 /* Should never be called, as .req goes between the alias and the
2331 register name, not at the beginning of the line. */
2334 s_req (int a ATTRIBUTE_UNUSED
)
2336 as_bad (_("invalid syntax for .req directive"));
2340 s_dn (int a ATTRIBUTE_UNUSED
)
2342 as_bad (_("invalid syntax for .dn directive"));
2346 s_qn (int a ATTRIBUTE_UNUSED
)
2348 as_bad (_("invalid syntax for .qn directive"));
2351 /* The .unreq directive deletes an alias which was previously defined
2352 by .req. For example:
2358 s_unreq (int a ATTRIBUTE_UNUSED
)
2363 name
= input_line_pointer
;
2365 while (*input_line_pointer
!= 0
2366 && *input_line_pointer
!= ' '
2367 && *input_line_pointer
!= '\n')
2368 ++input_line_pointer
;
2370 saved_char
= *input_line_pointer
;
2371 *input_line_pointer
= 0;
2374 as_bad (_("invalid syntax for .unreq directive"));
2377 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2381 as_bad (_("unknown register alias '%s'"), name
);
2382 else if (reg
->builtin
)
2383 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2390 hash_delete (arm_reg_hsh
, name
, FALSE
);
2391 free ((char *) reg
->name
);
2396 /* Also locate the all upper case and all lower case versions.
2397 Do not complain if we cannot find one or the other as it
2398 was probably deleted above. */
2400 nbuf
= strdup (name
);
2401 for (p
= nbuf
; *p
; p
++)
2403 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2406 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2407 free ((char *) reg
->name
);
2413 for (p
= nbuf
; *p
; p
++)
2415 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2418 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2419 free ((char *) reg
->name
);
2429 *input_line_pointer
= saved_char
;
2430 demand_empty_rest_of_line ();
2433 /* Directives: Instruction set selection. */
2436 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2437 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2438 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2439 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2441 /* Create a new mapping symbol for the transition to STATE. */
2444 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2447 const char * symname
;
2454 type
= BSF_NO_FLAGS
;
2458 type
= BSF_NO_FLAGS
;
2462 type
= BSF_NO_FLAGS
;
2468 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2469 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2474 THUMB_SET_FUNC (symbolP
, 0);
2475 ARM_SET_THUMB (symbolP
, 0);
2476 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2480 THUMB_SET_FUNC (symbolP
, 1);
2481 ARM_SET_THUMB (symbolP
, 1);
2482 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2490 /* Save the mapping symbols for future reference. Also check that
2491 we do not place two mapping symbols at the same offset within a
2492 frag. We'll handle overlap between frags in
2493 check_mapping_symbols. */
2496 know (frag
->tc_frag_data
.first_map
== NULL
);
2497 frag
->tc_frag_data
.first_map
= symbolP
;
2499 if (frag
->tc_frag_data
.last_map
!= NULL
)
2500 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) < S_GET_VALUE (symbolP
));
2501 frag
->tc_frag_data
.last_map
= symbolP
;
2504 /* We must sometimes convert a region marked as code to data during
2505 code alignment, if an odd number of bytes have to be padded. The
2506 code mapping symbol is pushed to an aligned address. */
2509 insert_data_mapping_symbol (enum mstate state
,
2510 valueT value
, fragS
*frag
, offsetT bytes
)
2512 /* If there was already a mapping symbol, remove it. */
2513 if (frag
->tc_frag_data
.last_map
!= NULL
2514 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2516 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2520 know (frag
->tc_frag_data
.first_map
== symp
);
2521 frag
->tc_frag_data
.first_map
= NULL
;
2523 frag
->tc_frag_data
.last_map
= NULL
;
2524 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2527 make_mapping_symbol (MAP_DATA
, value
, frag
);
2528 make_mapping_symbol (state
, value
+ bytes
, frag
);
2531 static void mapping_state_2 (enum mstate state
, int max_chars
);
2533 /* Set the mapping state to STATE. Only call this when about to
2534 emit some STATE bytes to the file. */
2537 mapping_state (enum mstate state
)
2539 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2541 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2543 if (mapstate
== state
)
2544 /* The mapping symbol has already been emitted.
2545 There is nothing else to do. */
2547 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2548 /* This case will be evaluated later in the next else. */
2550 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2551 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2553 /* Only add the symbol if the offset is > 0:
2554 if we're at the first frag, check it's size > 0;
2555 if we're not at the first frag, then for sure
2556 the offset is > 0. */
2557 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2558 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2561 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2564 mapping_state_2 (state
, 0);
2568 /* Same as mapping_state, but MAX_CHARS bytes have already been
2569 allocated. Put the mapping symbol that far back. */
2572 mapping_state_2 (enum mstate state
, int max_chars
)
2574 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2576 if (!SEG_NORMAL (now_seg
))
2579 if (mapstate
== state
)
2580 /* The mapping symbol has already been emitted.
2581 There is nothing else to do. */
2584 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2585 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2588 #define mapping_state(x) ((void)0)
2589 #define mapping_state_2(x, y) ((void)0)
2592 /* Find the real, Thumb encoded start of a Thumb function. */
2596 find_real_start (symbolS
* symbolP
)
2599 const char * name
= S_GET_NAME (symbolP
);
2600 symbolS
* new_target
;
2602 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2603 #define STUB_NAME ".real_start_of"
2608 /* The compiler may generate BL instructions to local labels because
2609 it needs to perform a branch to a far away location. These labels
2610 do not have a corresponding ".real_start_of" label. We check
2611 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2612 the ".real_start_of" convention for nonlocal branches. */
2613 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2616 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2617 new_target
= symbol_find (real_start
);
2619 if (new_target
== NULL
)
2621 as_warn (_("Failed to find real start of function: %s\n"), name
);
2622 new_target
= symbolP
;
2630 opcode_select (int width
)
2637 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2638 as_bad (_("selected processor does not support THUMB opcodes"));
2641 /* No need to force the alignment, since we will have been
2642 coming from ARM mode, which is word-aligned. */
2643 record_alignment (now_seg
, 1);
2650 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2651 as_bad (_("selected processor does not support ARM opcodes"));
2656 frag_align (2, 0, 0);
2658 record_alignment (now_seg
, 1);
2663 as_bad (_("invalid instruction size selected (%d)"), width
);
2668 s_arm (int ignore ATTRIBUTE_UNUSED
)
2671 demand_empty_rest_of_line ();
2675 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2678 demand_empty_rest_of_line ();
2682 s_code (int unused ATTRIBUTE_UNUSED
)
2686 temp
= get_absolute_expression ();
2691 opcode_select (temp
);
2695 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2700 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2702 /* If we are not already in thumb mode go into it, EVEN if
2703 the target processor does not support thumb instructions.
2704 This is used by gcc/config/arm/lib1funcs.asm for example
2705 to compile interworking support functions even if the
2706 target processor should not support interworking. */
2710 record_alignment (now_seg
, 1);
2713 demand_empty_rest_of_line ();
2717 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2721 /* The following label is the name/address of the start of a Thumb function.
2722 We need to know this for the interworking support. */
2723 label_is_thumb_function_name
= TRUE
;
2726 /* Perform a .set directive, but also mark the alias as
2727 being a thumb function. */
2730 s_thumb_set (int equiv
)
2732 /* XXX the following is a duplicate of the code for s_set() in read.c
2733 We cannot just call that code as we need to get at the symbol that
2740 /* Especial apologies for the random logic:
2741 This just grew, and could be parsed much more simply!
2743 name
= input_line_pointer
;
2744 delim
= get_symbol_end ();
2745 end_name
= input_line_pointer
;
2748 if (*input_line_pointer
!= ',')
2751 as_bad (_("expected comma after name \"%s\""), name
);
2753 ignore_rest_of_line ();
2757 input_line_pointer
++;
2760 if (name
[0] == '.' && name
[1] == '\0')
2762 /* XXX - this should not happen to .thumb_set. */
2766 if ((symbolP
= symbol_find (name
)) == NULL
2767 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2770 /* When doing symbol listings, play games with dummy fragments living
2771 outside the normal fragment chain to record the file and line info
2773 if (listing
& LISTING_SYMBOLS
)
2775 extern struct list_info_struct
* listing_tail
;
2776 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2778 memset (dummy_frag
, 0, sizeof (fragS
));
2779 dummy_frag
->fr_type
= rs_fill
;
2780 dummy_frag
->line
= listing_tail
;
2781 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2782 dummy_frag
->fr_symbol
= symbolP
;
2786 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2789 /* "set" symbols are local unless otherwise specified. */
2790 SF_SET_LOCAL (symbolP
);
2791 #endif /* OBJ_COFF */
2792 } /* Make a new symbol. */
2794 symbol_table_insert (symbolP
);
2799 && S_IS_DEFINED (symbolP
)
2800 && S_GET_SEGMENT (symbolP
) != reg_section
)
2801 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2803 pseudo_set (symbolP
);
2805 demand_empty_rest_of_line ();
2807 /* XXX Now we come to the Thumb specific bit of code. */
2809 THUMB_SET_FUNC (symbolP
, 1);
2810 ARM_SET_THUMB (symbolP
, 1);
2811 #if defined OBJ_ELF || defined OBJ_COFF
2812 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2816 /* Directives: Mode selection. */
2818 /* .syntax [unified|divided] - choose the new unified syntax
2819 (same for Arm and Thumb encoding, modulo slight differences in what
2820 can be represented) or the old divergent syntax for each mode. */
2822 s_syntax (int unused ATTRIBUTE_UNUSED
)
2826 name
= input_line_pointer
;
2827 delim
= get_symbol_end ();
2829 if (!strcasecmp (name
, "unified"))
2830 unified_syntax
= TRUE
;
2831 else if (!strcasecmp (name
, "divided"))
2832 unified_syntax
= FALSE
;
2835 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2838 *input_line_pointer
= delim
;
2839 demand_empty_rest_of_line ();
2842 /* Directives: sectioning and alignment. */
2844 /* Same as s_align_ptwo but align 0 => align 2. */
2847 s_align (int unused ATTRIBUTE_UNUSED
)
2852 long max_alignment
= 15;
2854 temp
= get_absolute_expression ();
2855 if (temp
> max_alignment
)
2856 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2859 as_bad (_("alignment negative. 0 assumed."));
2863 if (*input_line_pointer
== ',')
2865 input_line_pointer
++;
2866 temp_fill
= get_absolute_expression ();
2878 /* Only make a frag if we HAVE to. */
2879 if (temp
&& !need_pass_2
)
2881 if (!fill_p
&& subseg_text_p (now_seg
))
2882 frag_align_code (temp
, 0);
2884 frag_align (temp
, (int) temp_fill
, 0);
2886 demand_empty_rest_of_line ();
2888 record_alignment (now_seg
, temp
);
2892 s_bss (int ignore ATTRIBUTE_UNUSED
)
2894 /* We don't support putting frags in the BSS segment, we fake it by
2895 marking in_bss, then looking at s_skip for clues. */
2896 subseg_set (bss_section
, 0);
2897 demand_empty_rest_of_line ();
2899 #ifdef md_elf_section_change_hook
2900 md_elf_section_change_hook ();
2905 s_even (int ignore ATTRIBUTE_UNUSED
)
2907 /* Never make frag if expect extra pass. */
2909 frag_align (1, 0, 0);
2911 record_alignment (now_seg
, 1);
2913 demand_empty_rest_of_line ();
2916 /* Directives: Literal pools. */
2918 static literal_pool
*
2919 find_literal_pool (void)
2921 literal_pool
* pool
;
2923 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2925 if (pool
->section
== now_seg
2926 && pool
->sub_section
== now_subseg
)
2933 static literal_pool
*
2934 find_or_make_literal_pool (void)
2936 /* Next literal pool ID number. */
2937 static unsigned int latest_pool_num
= 1;
2938 literal_pool
* pool
;
2940 pool
= find_literal_pool ();
2944 /* Create a new pool. */
2945 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2949 pool
->next_free_entry
= 0;
2950 pool
->section
= now_seg
;
2951 pool
->sub_section
= now_subseg
;
2952 pool
->next
= list_of_pools
;
2953 pool
->symbol
= NULL
;
2955 /* Add it to the list. */
2956 list_of_pools
= pool
;
2959 /* New pools, and emptied pools, will have a NULL symbol. */
2960 if (pool
->symbol
== NULL
)
2962 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2963 (valueT
) 0, &zero_address_frag
);
2964 pool
->id
= latest_pool_num
++;
2971 /* Add the literal in the global 'inst'
2972 structure to the relevant literal pool. */
2975 add_to_lit_pool (void)
2977 literal_pool
* pool
;
2980 pool
= find_or_make_literal_pool ();
2982 /* Check if this literal value is already in the pool. */
2983 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2985 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2986 && (inst
.reloc
.exp
.X_op
== O_constant
)
2987 && (pool
->literals
[entry
].X_add_number
2988 == inst
.reloc
.exp
.X_add_number
)
2989 && (pool
->literals
[entry
].X_unsigned
2990 == inst
.reloc
.exp
.X_unsigned
))
2993 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2994 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2995 && (pool
->literals
[entry
].X_add_number
2996 == inst
.reloc
.exp
.X_add_number
)
2997 && (pool
->literals
[entry
].X_add_symbol
2998 == inst
.reloc
.exp
.X_add_symbol
)
2999 && (pool
->literals
[entry
].X_op_symbol
3000 == inst
.reloc
.exp
.X_op_symbol
))
3004 /* Do we need to create a new entry? */
3005 if (entry
== pool
->next_free_entry
)
3007 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3009 inst
.error
= _("literal pool overflow");
3013 pool
->literals
[entry
] = inst
.reloc
.exp
;
3014 pool
->next_free_entry
+= 1;
3017 inst
.reloc
.exp
.X_op
= O_symbol
;
3018 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3019 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3024 /* Can't use symbol_new here, so have to create a symbol and then at
3025 a later date assign it a value. Thats what these functions do. */
3028 symbol_locate (symbolS
* symbolP
,
3029 const char * name
, /* It is copied, the caller can modify. */
3030 segT segment
, /* Segment identifier (SEG_<something>). */
3031 valueT valu
, /* Symbol value. */
3032 fragS
* frag
) /* Associated fragment. */
3034 unsigned int name_length
;
3035 char * preserved_copy_of_name
;
3037 name_length
= strlen (name
) + 1; /* +1 for \0. */
3038 obstack_grow (¬es
, name
, name_length
);
3039 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3041 #ifdef tc_canonicalize_symbol_name
3042 preserved_copy_of_name
=
3043 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3046 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3048 S_SET_SEGMENT (symbolP
, segment
);
3049 S_SET_VALUE (symbolP
, valu
);
3050 symbol_clear_list_pointers (symbolP
);
3052 symbol_set_frag (symbolP
, frag
);
3054 /* Link to end of symbol chain. */
3056 extern int symbol_table_frozen
;
3058 if (symbol_table_frozen
)
3062 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3064 obj_symbol_new_hook (symbolP
);
3066 #ifdef tc_symbol_new_hook
3067 tc_symbol_new_hook (symbolP
);
3071 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3072 #endif /* DEBUG_SYMS */
3077 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3080 literal_pool
* pool
;
3083 pool
= find_literal_pool ();
3085 || pool
->symbol
== NULL
3086 || pool
->next_free_entry
== 0)
3089 mapping_state (MAP_DATA
);
3091 /* Align pool as you have word accesses.
3092 Only make a frag if we have to. */
3094 frag_align (2, 0, 0);
3096 record_alignment (now_seg
, 2);
3098 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3100 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3101 (valueT
) frag_now_fix (), frag_now
);
3102 symbol_table_insert (pool
->symbol
);
3104 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3106 #if defined OBJ_COFF || defined OBJ_ELF
3107 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3110 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3111 /* First output the expression in the instruction to the pool. */
3112 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3114 /* Mark the pool as empty. */
3115 pool
->next_free_entry
= 0;
3116 pool
->symbol
= NULL
;
3120 /* Forward declarations for functions below, in the MD interface
3122 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3123 static valueT
create_unwind_entry (int);
3124 static void start_unwind_section (const segT
, int);
3125 static void add_unwind_opcode (valueT
, int);
3126 static void flush_pending_unwind (void);
3128 /* Directives: Data. */
3131 s_arm_elf_cons (int nbytes
)
3135 #ifdef md_flush_pending_output
3136 md_flush_pending_output ();
3139 if (is_it_end_of_statement ())
3141 demand_empty_rest_of_line ();
3145 #ifdef md_cons_align
3146 md_cons_align (nbytes
);
3149 mapping_state (MAP_DATA
);
3153 char *base
= input_line_pointer
;
3157 if (exp
.X_op
!= O_symbol
)
3158 emit_expr (&exp
, (unsigned int) nbytes
);
3161 char *before_reloc
= input_line_pointer
;
3162 reloc
= parse_reloc (&input_line_pointer
);
3165 as_bad (_("unrecognized relocation suffix"));
3166 ignore_rest_of_line ();
3169 else if (reloc
== BFD_RELOC_UNUSED
)
3170 emit_expr (&exp
, (unsigned int) nbytes
);
3173 reloc_howto_type
*howto
= (reloc_howto_type
*)
3174 bfd_reloc_type_lookup (stdoutput
,
3175 (bfd_reloc_code_real_type
) reloc
);
3176 int size
= bfd_get_reloc_size (howto
);
3178 if (reloc
== BFD_RELOC_ARM_PLT32
)
3180 as_bad (_("(plt) is only valid on branch targets"));
3181 reloc
= BFD_RELOC_UNUSED
;
3186 as_bad (_("%s relocations do not fit in %d bytes"),
3187 howto
->name
, nbytes
);
3190 /* We've parsed an expression stopping at O_symbol.
3191 But there may be more expression left now that we
3192 have parsed the relocation marker. Parse it again.
3193 XXX Surely there is a cleaner way to do this. */
3194 char *p
= input_line_pointer
;
3196 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3197 memcpy (save_buf
, base
, input_line_pointer
- base
);
3198 memmove (base
+ (input_line_pointer
- before_reloc
),
3199 base
, before_reloc
- base
);
3201 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3203 memcpy (base
, save_buf
, p
- base
);
3205 offset
= nbytes
- size
;
3206 p
= frag_more ((int) nbytes
);
3207 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3208 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3213 while (*input_line_pointer
++ == ',');
3215 /* Put terminator back into stream. */
3216 input_line_pointer
--;
3217 demand_empty_rest_of_line ();
3220 /* Emit an expression containing a 32-bit thumb instruction.
3221 Implementation based on put_thumb32_insn. */
3224 emit_thumb32_expr (expressionS
* exp
)
3226 expressionS exp_high
= *exp
;
3228 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3229 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3230 exp
->X_add_number
&= 0xffff;
3231 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3234 /* Guess the instruction size based on the opcode. */
3237 thumb_insn_size (int opcode
)
3239 if ((unsigned int) opcode
< 0xe800u
)
3241 else if ((unsigned int) opcode
>= 0xe8000000u
)
3248 emit_insn (expressionS
*exp
, int nbytes
)
3252 if (exp
->X_op
== O_constant
)
3257 size
= thumb_insn_size (exp
->X_add_number
);
3261 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3263 as_bad (_(".inst.n operand too big. "\
3264 "Use .inst.w instead"));
3269 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3270 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3272 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3274 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3275 emit_thumb32_expr (exp
);
3277 emit_expr (exp
, (unsigned int) size
);
3279 it_fsm_post_encode ();
3283 as_bad (_("cannot determine Thumb instruction size. " \
3284 "Use .inst.n/.inst.w instead"));
3287 as_bad (_("constant expression required"));
3292 /* Like s_arm_elf_cons but do not use md_cons_align and
3293 set the mapping state to MAP_ARM/MAP_THUMB. */
3296 s_arm_elf_inst (int nbytes
)
3298 if (is_it_end_of_statement ())
3300 demand_empty_rest_of_line ();
3304 /* Calling mapping_state () here will not change ARM/THUMB,
3305 but will ensure not to be in DATA state. */
3308 mapping_state (MAP_THUMB
);
3313 as_bad (_("width suffixes are invalid in ARM mode"));
3314 ignore_rest_of_line ();
3320 mapping_state (MAP_ARM
);
3329 if (! emit_insn (& exp
, nbytes
))
3331 ignore_rest_of_line ();
3335 while (*input_line_pointer
++ == ',');
3337 /* Put terminator back into stream. */
3338 input_line_pointer
--;
3339 demand_empty_rest_of_line ();
3342 /* Parse a .rel31 directive. */
3345 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3352 if (*input_line_pointer
== '1')
3353 highbit
= 0x80000000;
3354 else if (*input_line_pointer
!= '0')
3355 as_bad (_("expected 0 or 1"));
3357 input_line_pointer
++;
3358 if (*input_line_pointer
!= ',')
3359 as_bad (_("missing comma"));
3360 input_line_pointer
++;
3362 #ifdef md_flush_pending_output
3363 md_flush_pending_output ();
3366 #ifdef md_cons_align
3370 mapping_state (MAP_DATA
);
3375 md_number_to_chars (p
, highbit
, 4);
3376 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3377 BFD_RELOC_ARM_PREL31
);
3379 demand_empty_rest_of_line ();
3382 /* Directives: AEABI stack-unwind tables. */
3384 /* Parse an unwind_fnstart directive. Simply records the current location. */
3387 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3389 demand_empty_rest_of_line ();
3390 if (unwind
.proc_start
)
3392 as_bad (_("duplicate .fnstart directive"));
3396 /* Mark the start of the function. */
3397 unwind
.proc_start
= expr_build_dot ();
3399 /* Reset the rest of the unwind info. */
3400 unwind
.opcode_count
= 0;
3401 unwind
.table_entry
= NULL
;
3402 unwind
.personality_routine
= NULL
;
3403 unwind
.personality_index
= -1;
3404 unwind
.frame_size
= 0;
3405 unwind
.fp_offset
= 0;
3406 unwind
.fp_reg
= REG_SP
;
3408 unwind
.sp_restored
= 0;
3412 /* Parse a handlerdata directive. Creates the exception handling table entry
3413 for the function. */
3416 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3418 demand_empty_rest_of_line ();
3419 if (!unwind
.proc_start
)
3420 as_bad (MISSING_FNSTART
);
3422 if (unwind
.table_entry
)
3423 as_bad (_("duplicate .handlerdata directive"));
3425 create_unwind_entry (1);
3428 /* Parse an unwind_fnend directive. Generates the index table entry. */
3431 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3436 unsigned int marked_pr_dependency
;
3438 demand_empty_rest_of_line ();
3440 if (!unwind
.proc_start
)
3442 as_bad (_(".fnend directive without .fnstart"));
3446 /* Add eh table entry. */
3447 if (unwind
.table_entry
== NULL
)
3448 val
= create_unwind_entry (0);
3452 /* Add index table entry. This is two words. */
3453 start_unwind_section (unwind
.saved_seg
, 1);
3454 frag_align (2, 0, 0);
3455 record_alignment (now_seg
, 2);
3457 ptr
= frag_more (8);
3458 where
= frag_now_fix () - 8;
3460 /* Self relative offset of the function start. */
3461 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3462 BFD_RELOC_ARM_PREL31
);
3464 /* Indicate dependency on EHABI-defined personality routines to the
3465 linker, if it hasn't been done already. */
3466 marked_pr_dependency
3467 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3468 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3469 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3471 static const char *const name
[] =
3473 "__aeabi_unwind_cpp_pr0",
3474 "__aeabi_unwind_cpp_pr1",
3475 "__aeabi_unwind_cpp_pr2"
3477 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3478 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3479 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3480 |= 1 << unwind
.personality_index
;
3484 /* Inline exception table entry. */
3485 md_number_to_chars (ptr
+ 4, val
, 4);
3487 /* Self relative offset of the table entry. */
3488 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3489 BFD_RELOC_ARM_PREL31
);
3491 /* Restore the original section. */
3492 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3494 unwind
.proc_start
= NULL
;
3498 /* Parse an unwind_cantunwind directive. */
3501 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3503 demand_empty_rest_of_line ();
3504 if (!unwind
.proc_start
)
3505 as_bad (MISSING_FNSTART
);
3507 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3508 as_bad (_("personality routine specified for cantunwind frame"));
3510 unwind
.personality_index
= -2;
3514 /* Parse a personalityindex directive. */
3517 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3521 if (!unwind
.proc_start
)
3522 as_bad (MISSING_FNSTART
);
3524 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3525 as_bad (_("duplicate .personalityindex directive"));
3529 if (exp
.X_op
!= O_constant
3530 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3532 as_bad (_("bad personality routine number"));
3533 ignore_rest_of_line ();
3537 unwind
.personality_index
= exp
.X_add_number
;
3539 demand_empty_rest_of_line ();
3543 /* Parse a personality directive. */
3546 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3550 if (!unwind
.proc_start
)
3551 as_bad (MISSING_FNSTART
);
3553 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3554 as_bad (_("duplicate .personality directive"));
3556 name
= input_line_pointer
;
3557 c
= get_symbol_end ();
3558 p
= input_line_pointer
;
3559 unwind
.personality_routine
= symbol_find_or_make (name
);
3561 demand_empty_rest_of_line ();
3565 /* Parse a directive saving core registers. */
3568 s_arm_unwind_save_core (void)
3574 range
= parse_reg_list (&input_line_pointer
);
3577 as_bad (_("expected register list"));
3578 ignore_rest_of_line ();
3582 demand_empty_rest_of_line ();
3584 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3585 into .unwind_save {..., sp...}. We aren't bothered about the value of
3586 ip because it is clobbered by calls. */
3587 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3588 && (range
& 0x3000) == 0x1000)
3590 unwind
.opcode_count
--;
3591 unwind
.sp_restored
= 0;
3592 range
= (range
| 0x2000) & ~0x1000;
3593 unwind
.pending_offset
= 0;
3599 /* See if we can use the short opcodes. These pop a block of up to 8
3600 registers starting with r4, plus maybe r14. */
3601 for (n
= 0; n
< 8; n
++)
3603 /* Break at the first non-saved register. */
3604 if ((range
& (1 << (n
+ 4))) == 0)
3607 /* See if there are any other bits set. */
3608 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3610 /* Use the long form. */
3611 op
= 0x8000 | ((range
>> 4) & 0xfff);
3612 add_unwind_opcode (op
, 2);
3616 /* Use the short form. */
3618 op
= 0xa8; /* Pop r14. */
3620 op
= 0xa0; /* Do not pop r14. */
3622 add_unwind_opcode (op
, 1);
3629 op
= 0xb100 | (range
& 0xf);
3630 add_unwind_opcode (op
, 2);
3633 /* Record the number of bytes pushed. */
3634 for (n
= 0; n
< 16; n
++)
3636 if (range
& (1 << n
))
3637 unwind
.frame_size
+= 4;
3642 /* Parse a directive saving FPA registers. */
3645 s_arm_unwind_save_fpa (int reg
)
3651 /* Get Number of registers to transfer. */
3652 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3655 exp
.X_op
= O_illegal
;
3657 if (exp
.X_op
!= O_constant
)
3659 as_bad (_("expected , <constant>"));
3660 ignore_rest_of_line ();
3664 num_regs
= exp
.X_add_number
;
3666 if (num_regs
< 1 || num_regs
> 4)
3668 as_bad (_("number of registers must be in the range [1:4]"));
3669 ignore_rest_of_line ();
3673 demand_empty_rest_of_line ();
3678 op
= 0xb4 | (num_regs
- 1);
3679 add_unwind_opcode (op
, 1);
3684 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3685 add_unwind_opcode (op
, 2);
3687 unwind
.frame_size
+= num_regs
* 12;
3691 /* Parse a directive saving VFP registers for ARMv6 and above. */
3694 s_arm_unwind_save_vfp_armv6 (void)
3699 int num_vfpv3_regs
= 0;
3700 int num_regs_below_16
;
3702 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3705 as_bad (_("expected register list"));
3706 ignore_rest_of_line ();
3710 demand_empty_rest_of_line ();
3712 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3713 than FSTMX/FLDMX-style ones). */
3715 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3717 num_vfpv3_regs
= count
;
3718 else if (start
+ count
> 16)
3719 num_vfpv3_regs
= start
+ count
- 16;
3721 if (num_vfpv3_regs
> 0)
3723 int start_offset
= start
> 16 ? start
- 16 : 0;
3724 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3725 add_unwind_opcode (op
, 2);
3728 /* Generate opcode for registers numbered in the range 0 .. 15. */
3729 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3730 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3731 if (num_regs_below_16
> 0)
3733 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3734 add_unwind_opcode (op
, 2);
3737 unwind
.frame_size
+= count
* 8;
3741 /* Parse a directive saving VFP registers for pre-ARMv6. */
3744 s_arm_unwind_save_vfp (void)
3750 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3753 as_bad (_("expected register list"));
3754 ignore_rest_of_line ();
3758 demand_empty_rest_of_line ();
3763 op
= 0xb8 | (count
- 1);
3764 add_unwind_opcode (op
, 1);
3769 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3770 add_unwind_opcode (op
, 2);
3772 unwind
.frame_size
+= count
* 8 + 4;
3776 /* Parse a directive saving iWMMXt data registers. */
3779 s_arm_unwind_save_mmxwr (void)
3787 if (*input_line_pointer
== '{')
3788 input_line_pointer
++;
3792 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3796 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3801 as_tsktsk (_("register list not in ascending order"));
3804 if (*input_line_pointer
== '-')
3806 input_line_pointer
++;
3807 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3810 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3813 else if (reg
>= hi_reg
)
3815 as_bad (_("bad register range"));
3818 for (; reg
< hi_reg
; reg
++)
3822 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3824 if (*input_line_pointer
== '}')
3825 input_line_pointer
++;
3827 demand_empty_rest_of_line ();
3829 /* Generate any deferred opcodes because we're going to be looking at
3831 flush_pending_unwind ();
3833 for (i
= 0; i
< 16; i
++)
3835 if (mask
& (1 << i
))
3836 unwind
.frame_size
+= 8;
3839 /* Attempt to combine with a previous opcode. We do this because gcc
3840 likes to output separate unwind directives for a single block of
3842 if (unwind
.opcode_count
> 0)
3844 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3845 if ((i
& 0xf8) == 0xc0)
3848 /* Only merge if the blocks are contiguous. */
3851 if ((mask
& 0xfe00) == (1 << 9))
3853 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3854 unwind
.opcode_count
--;
3857 else if (i
== 6 && unwind
.opcode_count
>= 2)
3859 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3863 op
= 0xffff << (reg
- 1);
3865 && ((mask
& op
) == (1u << (reg
- 1))))
3867 op
= (1 << (reg
+ i
+ 1)) - 1;
3868 op
&= ~((1 << reg
) - 1);
3870 unwind
.opcode_count
-= 2;
3877 /* We want to generate opcodes in the order the registers have been
3878 saved, ie. descending order. */
3879 for (reg
= 15; reg
>= -1; reg
--)
3881 /* Save registers in blocks. */
3883 || !(mask
& (1 << reg
)))
3885 /* We found an unsaved reg. Generate opcodes to save the
3892 op
= 0xc0 | (hi_reg
- 10);
3893 add_unwind_opcode (op
, 1);
3898 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3899 add_unwind_opcode (op
, 2);
3908 ignore_rest_of_line ();
3912 s_arm_unwind_save_mmxwcg (void)
3919 if (*input_line_pointer
== '{')
3920 input_line_pointer
++;
3924 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3928 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3934 as_tsktsk (_("register list not in ascending order"));
3937 if (*input_line_pointer
== '-')
3939 input_line_pointer
++;
3940 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3943 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3946 else if (reg
>= hi_reg
)
3948 as_bad (_("bad register range"));
3951 for (; reg
< hi_reg
; reg
++)
3955 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3957 if (*input_line_pointer
== '}')
3958 input_line_pointer
++;
3960 demand_empty_rest_of_line ();
3962 /* Generate any deferred opcodes because we're going to be looking at
3964 flush_pending_unwind ();
3966 for (reg
= 0; reg
< 16; reg
++)
3968 if (mask
& (1 << reg
))
3969 unwind
.frame_size
+= 4;
3972 add_unwind_opcode (op
, 2);
3975 ignore_rest_of_line ();
3979 /* Parse an unwind_save directive.
3980 If the argument is non-zero, this is a .vsave directive. */
3983 s_arm_unwind_save (int arch_v6
)
3986 struct reg_entry
*reg
;
3987 bfd_boolean had_brace
= FALSE
;
3989 if (!unwind
.proc_start
)
3990 as_bad (MISSING_FNSTART
);
3992 /* Figure out what sort of save we have. */
3993 peek
= input_line_pointer
;
4001 reg
= arm_reg_parse_multi (&peek
);
4005 as_bad (_("register expected"));
4006 ignore_rest_of_line ();
4015 as_bad (_("FPA .unwind_save does not take a register list"));
4016 ignore_rest_of_line ();
4019 input_line_pointer
= peek
;
4020 s_arm_unwind_save_fpa (reg
->number
);
4023 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4026 s_arm_unwind_save_vfp_armv6 ();
4028 s_arm_unwind_save_vfp ();
4030 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4031 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4034 as_bad (_(".unwind_save does not support this kind of register"));
4035 ignore_rest_of_line ();
4040 /* Parse an unwind_movsp directive. */
4043 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4049 if (!unwind
.proc_start
)
4050 as_bad (MISSING_FNSTART
);
4052 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4055 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4056 ignore_rest_of_line ();
4060 /* Optional constant. */
4061 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4063 if (immediate_for_directive (&offset
) == FAIL
)
4069 demand_empty_rest_of_line ();
4071 if (reg
== REG_SP
|| reg
== REG_PC
)
4073 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4077 if (unwind
.fp_reg
!= REG_SP
)
4078 as_bad (_("unexpected .unwind_movsp directive"));
4080 /* Generate opcode to restore the value. */
4082 add_unwind_opcode (op
, 1);
4084 /* Record the information for later. */
4085 unwind
.fp_reg
= reg
;
4086 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4087 unwind
.sp_restored
= 1;
4090 /* Parse an unwind_pad directive. */
4093 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4097 if (!unwind
.proc_start
)
4098 as_bad (MISSING_FNSTART
);
4100 if (immediate_for_directive (&offset
) == FAIL
)
4105 as_bad (_("stack increment must be multiple of 4"));
4106 ignore_rest_of_line ();
4110 /* Don't generate any opcodes, just record the details for later. */
4111 unwind
.frame_size
+= offset
;
4112 unwind
.pending_offset
+= offset
;
4114 demand_empty_rest_of_line ();
4117 /* Parse an unwind_setfp directive. */
4120 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4126 if (!unwind
.proc_start
)
4127 as_bad (MISSING_FNSTART
);
4129 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4130 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4133 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4135 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4137 as_bad (_("expected <reg>, <reg>"));
4138 ignore_rest_of_line ();
4142 /* Optional constant. */
4143 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4145 if (immediate_for_directive (&offset
) == FAIL
)
4151 demand_empty_rest_of_line ();
4153 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4155 as_bad (_("register must be either sp or set by a previous"
4156 "unwind_movsp directive"));
4160 /* Don't generate any opcodes, just record the information for later. */
4161 unwind
.fp_reg
= fp_reg
;
4163 if (sp_reg
== REG_SP
)
4164 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4166 unwind
.fp_offset
-= offset
;
4169 /* Parse an unwind_raw directive. */
4172 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4175 /* This is an arbitrary limit. */
4176 unsigned char op
[16];
4179 if (!unwind
.proc_start
)
4180 as_bad (MISSING_FNSTART
);
4183 if (exp
.X_op
== O_constant
4184 && skip_past_comma (&input_line_pointer
) != FAIL
)
4186 unwind
.frame_size
+= exp
.X_add_number
;
4190 exp
.X_op
= O_illegal
;
4192 if (exp
.X_op
!= O_constant
)
4194 as_bad (_("expected <offset>, <opcode>"));
4195 ignore_rest_of_line ();
4201 /* Parse the opcode. */
4206 as_bad (_("unwind opcode too long"));
4207 ignore_rest_of_line ();
4209 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4211 as_bad (_("invalid unwind opcode"));
4212 ignore_rest_of_line ();
4215 op
[count
++] = exp
.X_add_number
;
4217 /* Parse the next byte. */
4218 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4224 /* Add the opcode bytes in reverse order. */
4226 add_unwind_opcode (op
[count
], 1);
4228 demand_empty_rest_of_line ();
4232 /* Parse a .eabi_attribute directive. */
4235 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4237 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4239 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4240 attributes_set_explicitly
[tag
] = 1;
4242 #endif /* OBJ_ELF */
4244 static void s_arm_arch (int);
4245 static void s_arm_object_arch (int);
4246 static void s_arm_cpu (int);
4247 static void s_arm_fpu (int);
4252 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4259 if (exp
.X_op
== O_symbol
)
4260 exp
.X_op
= O_secrel
;
4262 emit_expr (&exp
, 4);
4264 while (*input_line_pointer
++ == ',');
4266 input_line_pointer
--;
4267 demand_empty_rest_of_line ();
4271 /* This table describes all the machine specific pseudo-ops the assembler
4272 has to support. The fields are:
4273 pseudo-op name without dot
4274 function to call to execute this pseudo-op
4275 Integer arg to pass to the function. */
4277 const pseudo_typeS md_pseudo_table
[] =
4279 /* Never called because '.req' does not start a line. */
4280 { "req", s_req
, 0 },
4281 /* Following two are likewise never called. */
4284 { "unreq", s_unreq
, 0 },
4285 { "bss", s_bss
, 0 },
4286 { "align", s_align
, 0 },
4287 { "arm", s_arm
, 0 },
4288 { "thumb", s_thumb
, 0 },
4289 { "code", s_code
, 0 },
4290 { "force_thumb", s_force_thumb
, 0 },
4291 { "thumb_func", s_thumb_func
, 0 },
4292 { "thumb_set", s_thumb_set
, 0 },
4293 { "even", s_even
, 0 },
4294 { "ltorg", s_ltorg
, 0 },
4295 { "pool", s_ltorg
, 0 },
4296 { "syntax", s_syntax
, 0 },
4297 { "cpu", s_arm_cpu
, 0 },
4298 { "arch", s_arm_arch
, 0 },
4299 { "object_arch", s_arm_object_arch
, 0 },
4300 { "fpu", s_arm_fpu
, 0 },
4302 { "word", s_arm_elf_cons
, 4 },
4303 { "long", s_arm_elf_cons
, 4 },
4304 { "inst.n", s_arm_elf_inst
, 2 },
4305 { "inst.w", s_arm_elf_inst
, 4 },
4306 { "inst", s_arm_elf_inst
, 0 },
4307 { "rel31", s_arm_rel31
, 0 },
4308 { "fnstart", s_arm_unwind_fnstart
, 0 },
4309 { "fnend", s_arm_unwind_fnend
, 0 },
4310 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4311 { "personality", s_arm_unwind_personality
, 0 },
4312 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4313 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4314 { "save", s_arm_unwind_save
, 0 },
4315 { "vsave", s_arm_unwind_save
, 1 },
4316 { "movsp", s_arm_unwind_movsp
, 0 },
4317 { "pad", s_arm_unwind_pad
, 0 },
4318 { "setfp", s_arm_unwind_setfp
, 0 },
4319 { "unwind_raw", s_arm_unwind_raw
, 0 },
4320 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4324 /* These are used for dwarf. */
4328 /* These are used for dwarf2. */
4329 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4330 { "loc", dwarf2_directive_loc
, 0 },
4331 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4333 { "extend", float_cons
, 'x' },
4334 { "ldouble", float_cons
, 'x' },
4335 { "packed", float_cons
, 'p' },
4337 {"secrel32", pe_directive_secrel
, 0},
4342 /* Parser functions used exclusively in instruction operands. */
4344 /* Generic immediate-value read function for use in insn parsing.
4345 STR points to the beginning of the immediate (the leading #);
4346 VAL receives the value; if the value is outside [MIN, MAX]
4347 issue an error. PREFIX_OPT is true if the immediate prefix is
4351 parse_immediate (char **str
, int *val
, int min
, int max
,
4352 bfd_boolean prefix_opt
)
4355 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4356 if (exp
.X_op
!= O_constant
)
4358 inst
.error
= _("constant expression required");
4362 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4364 inst
.error
= _("immediate value out of range");
4368 *val
= exp
.X_add_number
;
4372 /* Less-generic immediate-value read function with the possibility of loading a
4373 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4374 instructions. Puts the result directly in inst.operands[i]. */
4377 parse_big_immediate (char **str
, int i
)
4382 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4384 if (exp
.X_op
== O_constant
)
4386 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4387 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4388 O_constant. We have to be careful not to break compilation for
4389 32-bit X_add_number, though. */
4390 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4392 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4393 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4394 inst
.operands
[i
].regisimm
= 1;
4397 else if (exp
.X_op
== O_big
4398 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4399 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4401 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4402 /* Bignums have their least significant bits in
4403 generic_bignum[0]. Make sure we put 32 bits in imm and
4404 32 bits in reg, in a (hopefully) portable way. */
4405 gas_assert (parts
!= 0);
4406 inst
.operands
[i
].imm
= 0;
4407 for (j
= 0; j
< parts
; j
++, idx
++)
4408 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4409 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4410 inst
.operands
[i
].reg
= 0;
4411 for (j
= 0; j
< parts
; j
++, idx
++)
4412 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4413 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4414 inst
.operands
[i
].regisimm
= 1;
4424 /* Returns the pseudo-register number of an FPA immediate constant,
4425 or FAIL if there isn't a valid constant here. */
4428 parse_fpa_immediate (char ** str
)
4430 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4436 /* First try and match exact strings, this is to guarantee
4437 that some formats will work even for cross assembly. */
4439 for (i
= 0; fp_const
[i
]; i
++)
4441 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4445 *str
+= strlen (fp_const
[i
]);
4446 if (is_end_of_line
[(unsigned char) **str
])
4452 /* Just because we didn't get a match doesn't mean that the constant
4453 isn't valid, just that it is in a format that we don't
4454 automatically recognize. Try parsing it with the standard
4455 expression routines. */
4457 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4459 /* Look for a raw floating point number. */
4460 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4461 && is_end_of_line
[(unsigned char) *save_in
])
4463 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4465 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4467 if (words
[j
] != fp_values
[i
][j
])
4471 if (j
== MAX_LITTLENUMS
)
4479 /* Try and parse a more complex expression, this will probably fail
4480 unless the code uses a floating point prefix (eg "0f"). */
4481 save_in
= input_line_pointer
;
4482 input_line_pointer
= *str
;
4483 if (expression (&exp
) == absolute_section
4484 && exp
.X_op
== O_big
4485 && exp
.X_add_number
< 0)
4487 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4489 if (gen_to_words (words
, 5, (long) 15) == 0)
4491 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4493 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4495 if (words
[j
] != fp_values
[i
][j
])
4499 if (j
== MAX_LITTLENUMS
)
4501 *str
= input_line_pointer
;
4502 input_line_pointer
= save_in
;
4509 *str
= input_line_pointer
;
4510 input_line_pointer
= save_in
;
4511 inst
.error
= _("invalid FPA immediate expression");
4515 /* Returns 1 if a number has "quarter-precision" float format
4516 0baBbbbbbc defgh000 00000000 00000000. */
4519 is_quarter_float (unsigned imm
)
4521 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4522 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4525 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4526 0baBbbbbbc defgh000 00000000 00000000.
4527 The zero and minus-zero cases need special handling, since they can't be
4528 encoded in the "quarter-precision" float format, but can nonetheless be
4529 loaded as integer constants. */
4532 parse_qfloat_immediate (char **ccp
, int *immed
)
4536 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4537 int found_fpchar
= 0;
4539 skip_past_char (&str
, '#');
4541 /* We must not accidentally parse an integer as a floating-point number. Make
4542 sure that the value we parse is not an integer by checking for special
4543 characters '.' or 'e'.
4544 FIXME: This is a horrible hack, but doing better is tricky because type
4545 information isn't in a very usable state at parse time. */
4547 skip_whitespace (fpnum
);
4549 if (strncmp (fpnum
, "0x", 2) == 0)
4553 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4554 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4564 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4566 unsigned fpword
= 0;
4569 /* Our FP word must be 32 bits (single-precision FP). */
4570 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4572 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4576 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4589 /* Shift operands. */
4592 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4595 struct asm_shift_name
4598 enum shift_kind kind
;
4601 /* Third argument to parse_shift. */
4602 enum parse_shift_mode
4604 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4605 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4606 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4607 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4608 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4611 /* Parse a <shift> specifier on an ARM data processing instruction.
4612 This has three forms:
4614 (LSL|LSR|ASL|ASR|ROR) Rs
4615 (LSL|LSR|ASL|ASR|ROR) #imm
4618 Note that ASL is assimilated to LSL in the instruction encoding, and
4619 RRX to ROR #0 (which cannot be written as such). */
4622 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4624 const struct asm_shift_name
*shift_name
;
4625 enum shift_kind shift
;
4630 for (p
= *str
; ISALPHA (*p
); p
++)
4635 inst
.error
= _("shift expression expected");
4639 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4642 if (shift_name
== NULL
)
4644 inst
.error
= _("shift expression expected");
4648 shift
= shift_name
->kind
;
4652 case NO_SHIFT_RESTRICT
:
4653 case SHIFT_IMMEDIATE
: break;
4655 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4656 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4658 inst
.error
= _("'LSL' or 'ASR' required");
4663 case SHIFT_LSL_IMMEDIATE
:
4664 if (shift
!= SHIFT_LSL
)
4666 inst
.error
= _("'LSL' required");
4671 case SHIFT_ASR_IMMEDIATE
:
4672 if (shift
!= SHIFT_ASR
)
4674 inst
.error
= _("'ASR' required");
4682 if (shift
!= SHIFT_RRX
)
4684 /* Whitespace can appear here if the next thing is a bare digit. */
4685 skip_whitespace (p
);
4687 if (mode
== NO_SHIFT_RESTRICT
4688 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4690 inst
.operands
[i
].imm
= reg
;
4691 inst
.operands
[i
].immisreg
= 1;
4693 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4696 inst
.operands
[i
].shift_kind
= shift
;
4697 inst
.operands
[i
].shifted
= 1;
4702 /* Parse a <shifter_operand> for an ARM data processing instruction:
4705 #<immediate>, <rotate>
4709 where <shift> is defined by parse_shift above, and <rotate> is a
4710 multiple of 2 between 0 and 30. Validation of immediate operands
4711 is deferred to md_apply_fix. */
4714 parse_shifter_operand (char **str
, int i
)
4719 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4721 inst
.operands
[i
].reg
= value
;
4722 inst
.operands
[i
].isreg
= 1;
4724 /* parse_shift will override this if appropriate */
4725 inst
.reloc
.exp
.X_op
= O_constant
;
4726 inst
.reloc
.exp
.X_add_number
= 0;
4728 if (skip_past_comma (str
) == FAIL
)
4731 /* Shift operation on register. */
4732 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4735 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4738 if (skip_past_comma (str
) == SUCCESS
)
4740 /* #x, y -- ie explicit rotation by Y. */
4741 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4744 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4746 inst
.error
= _("constant expression expected");
4750 value
= exp
.X_add_number
;
4751 if (value
< 0 || value
> 30 || value
% 2 != 0)
4753 inst
.error
= _("invalid rotation");
4756 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4758 inst
.error
= _("invalid constant");
4762 /* Convert to decoded value. md_apply_fix will put it back. */
4763 inst
.reloc
.exp
.X_add_number
4764 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4765 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4768 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4769 inst
.reloc
.pc_rel
= 0;
4773 /* Group relocation information. Each entry in the table contains the
4774 textual name of the relocation as may appear in assembler source
4775 and must end with a colon.
4776 Along with this textual name are the relocation codes to be used if
4777 the corresponding instruction is an ALU instruction (ADD or SUB only),
4778 an LDR, an LDRS, or an LDC. */
4780 struct group_reloc_table_entry
4791 /* Varieties of non-ALU group relocation. */
4798 static struct group_reloc_table_entry group_reloc_table
[] =
4799 { /* Program counter relative: */
4801 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4806 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4807 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4808 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4809 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4811 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4816 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4817 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4818 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4819 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4821 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4822 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4823 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4824 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4825 /* Section base relative */
4827 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4832 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4833 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4834 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4835 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4837 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4842 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4843 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4844 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4845 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4847 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4848 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4849 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4850 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4852 /* Given the address of a pointer pointing to the textual name of a group
4853 relocation as may appear in assembler source, attempt to find its details
4854 in group_reloc_table. The pointer will be updated to the character after
4855 the trailing colon. On failure, FAIL will be returned; SUCCESS
4856 otherwise. On success, *entry will be updated to point at the relevant
4857 group_reloc_table entry. */
4860 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4863 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4865 int length
= strlen (group_reloc_table
[i
].name
);
4867 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4868 && (*str
)[length
] == ':')
4870 *out
= &group_reloc_table
[i
];
4871 *str
+= (length
+ 1);
4879 /* Parse a <shifter_operand> for an ARM data processing instruction
4880 (as for parse_shifter_operand) where group relocations are allowed:
4883 #<immediate>, <rotate>
4884 #:<group_reloc>:<expression>
4888 where <group_reloc> is one of the strings defined in group_reloc_table.
4889 The hashes are optional.
4891 Everything else is as for parse_shifter_operand. */
4893 static parse_operand_result
4894 parse_shifter_operand_group_reloc (char **str
, int i
)
4896 /* Determine if we have the sequence of characters #: or just :
4897 coming next. If we do, then we check for a group relocation.
4898 If we don't, punt the whole lot to parse_shifter_operand. */
4900 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4901 || (*str
)[0] == ':')
4903 struct group_reloc_table_entry
*entry
;
4905 if ((*str
)[0] == '#')
4910 /* Try to parse a group relocation. Anything else is an error. */
4911 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4913 inst
.error
= _("unknown group relocation");
4914 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4917 /* We now have the group relocation table entry corresponding to
4918 the name in the assembler source. Next, we parse the expression. */
4919 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4920 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4922 /* Record the relocation type (always the ALU variant here). */
4923 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4924 gas_assert (inst
.reloc
.type
!= 0);
4926 return PARSE_OPERAND_SUCCESS
;
4929 return parse_shifter_operand (str
, i
) == SUCCESS
4930 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4932 /* Never reached. */
4935 /* Parse all forms of an ARM address expression. Information is written
4936 to inst.operands[i] and/or inst.reloc.
4938 Preindexed addressing (.preind=1):
4940 [Rn, #offset] .reg=Rn .reloc.exp=offset
4941 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4942 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4943 .shift_kind=shift .reloc.exp=shift_imm
4945 These three may have a trailing ! which causes .writeback to be set also.
4947 Postindexed addressing (.postind=1, .writeback=1):
4949 [Rn], #offset .reg=Rn .reloc.exp=offset
4950 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4951 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4952 .shift_kind=shift .reloc.exp=shift_imm
4954 Unindexed addressing (.preind=0, .postind=0):
4956 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4960 [Rn]{!} shorthand for [Rn,#0]{!}
4961 =immediate .isreg=0 .reloc.exp=immediate
4962 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4964 It is the caller's responsibility to check for addressing modes not
4965 supported by the instruction, and to set inst.reloc.type. */
4967 static parse_operand_result
4968 parse_address_main (char **str
, int i
, int group_relocations
,
4969 group_reloc_type group_type
)
4974 if (skip_past_char (&p
, '[') == FAIL
)
4976 if (skip_past_char (&p
, '=') == FAIL
)
4978 /* Bare address - translate to PC-relative offset. */
4979 inst
.reloc
.pc_rel
= 1;
4980 inst
.operands
[i
].reg
= REG_PC
;
4981 inst
.operands
[i
].isreg
= 1;
4982 inst
.operands
[i
].preind
= 1;
4984 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
4986 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4987 return PARSE_OPERAND_FAIL
;
4990 return PARSE_OPERAND_SUCCESS
;
4993 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4995 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4996 return PARSE_OPERAND_FAIL
;
4998 inst
.operands
[i
].reg
= reg
;
4999 inst
.operands
[i
].isreg
= 1;
5001 if (skip_past_comma (&p
) == SUCCESS
)
5003 inst
.operands
[i
].preind
= 1;
5006 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5008 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5010 inst
.operands
[i
].imm
= reg
;
5011 inst
.operands
[i
].immisreg
= 1;
5013 if (skip_past_comma (&p
) == SUCCESS
)
5014 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5015 return PARSE_OPERAND_FAIL
;
5017 else if (skip_past_char (&p
, ':') == SUCCESS
)
5019 /* FIXME: '@' should be used here, but it's filtered out by generic
5020 code before we get to see it here. This may be subject to
5023 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5024 if (exp
.X_op
!= O_constant
)
5026 inst
.error
= _("alignment must be constant");
5027 return PARSE_OPERAND_FAIL
;
5029 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5030 inst
.operands
[i
].immisalign
= 1;
5031 /* Alignments are not pre-indexes. */
5032 inst
.operands
[i
].preind
= 0;
5036 if (inst
.operands
[i
].negative
)
5038 inst
.operands
[i
].negative
= 0;
5042 if (group_relocations
5043 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5045 struct group_reloc_table_entry
*entry
;
5047 /* Skip over the #: or : sequence. */
5053 /* Try to parse a group relocation. Anything else is an
5055 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5057 inst
.error
= _("unknown group relocation");
5058 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5061 /* We now have the group relocation table entry corresponding to
5062 the name in the assembler source. Next, we parse the
5064 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5065 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5067 /* Record the relocation type. */
5071 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5075 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5079 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5086 if (inst
.reloc
.type
== 0)
5088 inst
.error
= _("this group relocation is not allowed on this instruction");
5089 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5093 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5094 return PARSE_OPERAND_FAIL
;
5098 if (skip_past_char (&p
, ']') == FAIL
)
5100 inst
.error
= _("']' expected");
5101 return PARSE_OPERAND_FAIL
;
5104 if (skip_past_char (&p
, '!') == SUCCESS
)
5105 inst
.operands
[i
].writeback
= 1;
5107 else if (skip_past_comma (&p
) == SUCCESS
)
5109 if (skip_past_char (&p
, '{') == SUCCESS
)
5111 /* [Rn], {expr} - unindexed, with option */
5112 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5113 0, 255, TRUE
) == FAIL
)
5114 return PARSE_OPERAND_FAIL
;
5116 if (skip_past_char (&p
, '}') == FAIL
)
5118 inst
.error
= _("'}' expected at end of 'option' field");
5119 return PARSE_OPERAND_FAIL
;
5121 if (inst
.operands
[i
].preind
)
5123 inst
.error
= _("cannot combine index with option");
5124 return PARSE_OPERAND_FAIL
;
5127 return PARSE_OPERAND_SUCCESS
;
5131 inst
.operands
[i
].postind
= 1;
5132 inst
.operands
[i
].writeback
= 1;
5134 if (inst
.operands
[i
].preind
)
5136 inst
.error
= _("cannot combine pre- and post-indexing");
5137 return PARSE_OPERAND_FAIL
;
5141 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5143 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5145 /* We might be using the immediate for alignment already. If we
5146 are, OR the register number into the low-order bits. */
5147 if (inst
.operands
[i
].immisalign
)
5148 inst
.operands
[i
].imm
|= reg
;
5150 inst
.operands
[i
].imm
= reg
;
5151 inst
.operands
[i
].immisreg
= 1;
5153 if (skip_past_comma (&p
) == SUCCESS
)
5154 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5155 return PARSE_OPERAND_FAIL
;
5159 if (inst
.operands
[i
].negative
)
5161 inst
.operands
[i
].negative
= 0;
5164 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5165 return PARSE_OPERAND_FAIL
;
5170 /* If at this point neither .preind nor .postind is set, we have a
5171 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5172 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5174 inst
.operands
[i
].preind
= 1;
5175 inst
.reloc
.exp
.X_op
= O_constant
;
5176 inst
.reloc
.exp
.X_add_number
= 0;
5179 return PARSE_OPERAND_SUCCESS
;
5183 parse_address (char **str
, int i
)
5185 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5189 static parse_operand_result
5190 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5192 return parse_address_main (str
, i
, 1, type
);
5195 /* Parse an operand for a MOVW or MOVT instruction. */
5197 parse_half (char **str
)
5202 skip_past_char (&p
, '#');
5203 if (strncasecmp (p
, ":lower16:", 9) == 0)
5204 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5205 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5206 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5208 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5211 skip_whitespace (p
);
5214 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5217 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5219 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5221 inst
.error
= _("constant expression expected");
5224 if (inst
.reloc
.exp
.X_add_number
< 0
5225 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5227 inst
.error
= _("immediate value out of range");
5235 /* Miscellaneous. */
5237 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5238 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5240 parse_psr (char **str
)
5243 unsigned long psr_field
;
5244 const struct asm_psr
*psr
;
5247 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5248 feature for ease of use and backwards compatibility. */
5250 if (strncasecmp (p
, "SPSR", 4) == 0)
5251 psr_field
= SPSR_BIT
;
5252 else if (strncasecmp (p
, "CPSR", 4) == 0)
5259 while (ISALNUM (*p
) || *p
== '_');
5261 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5273 /* A suffix follows. */
5279 while (ISALNUM (*p
) || *p
== '_');
5281 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5286 psr_field
|= psr
->field
;
5291 goto error
; /* Garbage after "[CS]PSR". */
5293 psr_field
|= (PSR_c
| PSR_f
);
5299 inst
.error
= _("flag for {c}psr instruction expected");
5303 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5304 value suitable for splatting into the AIF field of the instruction. */
5307 parse_cps_flags (char **str
)
5316 case '\0': case ',':
5319 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5320 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5321 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5324 inst
.error
= _("unrecognized CPS flag");
5329 if (saw_a_flag
== 0)
5331 inst
.error
= _("missing CPS flags");
5339 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5340 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5343 parse_endian_specifier (char **str
)
5348 if (strncasecmp (s
, "BE", 2))
5350 else if (strncasecmp (s
, "LE", 2))
5354 inst
.error
= _("valid endian specifiers are be or le");
5358 if (ISALNUM (s
[2]) || s
[2] == '_')
5360 inst
.error
= _("valid endian specifiers are be or le");
5365 return little_endian
;
5368 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5369 value suitable for poking into the rotate field of an sxt or sxta
5370 instruction, or FAIL on error. */
5373 parse_ror (char **str
)
5378 if (strncasecmp (s
, "ROR", 3) == 0)
5382 inst
.error
= _("missing rotation field after comma");
5386 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5391 case 0: *str
= s
; return 0x0;
5392 case 8: *str
= s
; return 0x1;
5393 case 16: *str
= s
; return 0x2;
5394 case 24: *str
= s
; return 0x3;
5397 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5402 /* Parse a conditional code (from conds[] below). The value returned is in the
5403 range 0 .. 14, or FAIL. */
5405 parse_cond (char **str
)
5408 const struct asm_cond
*c
;
5410 /* Condition codes are always 2 characters, so matching up to
5411 3 characters is sufficient. */
5416 while (ISALPHA (*q
) && n
< 3)
5418 cond
[n
] = TOLOWER (*q
);
5423 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5426 inst
.error
= _("condition required");
5434 /* Parse an option for a barrier instruction. Returns the encoding for the
5437 parse_barrier (char **str
)
5440 const struct asm_barrier_opt
*o
;
5443 while (ISALPHA (*q
))
5446 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5455 /* Parse the operands of a table branch instruction. Similar to a memory
5458 parse_tb (char **str
)
5463 if (skip_past_char (&p
, '[') == FAIL
)
5465 inst
.error
= _("'[' expected");
5469 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5471 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5474 inst
.operands
[0].reg
= reg
;
5476 if (skip_past_comma (&p
) == FAIL
)
5478 inst
.error
= _("',' expected");
5482 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5484 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5487 inst
.operands
[0].imm
= reg
;
5489 if (skip_past_comma (&p
) == SUCCESS
)
5491 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5493 if (inst
.reloc
.exp
.X_add_number
!= 1)
5495 inst
.error
= _("invalid shift");
5498 inst
.operands
[0].shifted
= 1;
5501 if (skip_past_char (&p
, ']') == FAIL
)
5503 inst
.error
= _("']' expected");
5510 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5511 information on the types the operands can take and how they are encoded.
5512 Up to four operands may be read; this function handles setting the
5513 ".present" field for each read operand itself.
5514 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5515 else returns FAIL. */
5518 parse_neon_mov (char **str
, int *which_operand
)
5520 int i
= *which_operand
, val
;
5521 enum arm_reg_type rtype
;
5523 struct neon_type_el optype
;
5525 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5527 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5528 inst
.operands
[i
].reg
= val
;
5529 inst
.operands
[i
].isscalar
= 1;
5530 inst
.operands
[i
].vectype
= optype
;
5531 inst
.operands
[i
++].present
= 1;
5533 if (skip_past_comma (&ptr
) == FAIL
)
5536 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5539 inst
.operands
[i
].reg
= val
;
5540 inst
.operands
[i
].isreg
= 1;
5541 inst
.operands
[i
].present
= 1;
5543 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5546 /* Cases 0, 1, 2, 3, 5 (D only). */
5547 if (skip_past_comma (&ptr
) == FAIL
)
5550 inst
.operands
[i
].reg
= val
;
5551 inst
.operands
[i
].isreg
= 1;
5552 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5553 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5554 inst
.operands
[i
].isvec
= 1;
5555 inst
.operands
[i
].vectype
= optype
;
5556 inst
.operands
[i
++].present
= 1;
5558 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5560 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5561 Case 13: VMOV <Sd>, <Rm> */
5562 inst
.operands
[i
].reg
= val
;
5563 inst
.operands
[i
].isreg
= 1;
5564 inst
.operands
[i
].present
= 1;
5566 if (rtype
== REG_TYPE_NQ
)
5568 first_error (_("can't use Neon quad register here"));
5571 else if (rtype
!= REG_TYPE_VFS
)
5574 if (skip_past_comma (&ptr
) == FAIL
)
5576 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5578 inst
.operands
[i
].reg
= val
;
5579 inst
.operands
[i
].isreg
= 1;
5580 inst
.operands
[i
].present
= 1;
5583 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5586 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5587 Case 1: VMOV<c><q> <Dd>, <Dm>
5588 Case 8: VMOV.F32 <Sd>, <Sm>
5589 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5591 inst
.operands
[i
].reg
= val
;
5592 inst
.operands
[i
].isreg
= 1;
5593 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5594 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5595 inst
.operands
[i
].isvec
= 1;
5596 inst
.operands
[i
].vectype
= optype
;
5597 inst
.operands
[i
].present
= 1;
5599 if (skip_past_comma (&ptr
) == SUCCESS
)
5604 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5607 inst
.operands
[i
].reg
= val
;
5608 inst
.operands
[i
].isreg
= 1;
5609 inst
.operands
[i
++].present
= 1;
5611 if (skip_past_comma (&ptr
) == FAIL
)
5614 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5617 inst
.operands
[i
].reg
= val
;
5618 inst
.operands
[i
].isreg
= 1;
5619 inst
.operands
[i
++].present
= 1;
5622 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5623 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5624 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5625 Case 10: VMOV.F32 <Sd>, #<imm>
5626 Case 11: VMOV.F64 <Dd>, #<imm> */
5627 inst
.operands
[i
].immisfloat
= 1;
5628 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5629 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5630 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5634 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5638 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5641 inst
.operands
[i
].reg
= val
;
5642 inst
.operands
[i
].isreg
= 1;
5643 inst
.operands
[i
++].present
= 1;
5645 if (skip_past_comma (&ptr
) == FAIL
)
5648 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5650 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5651 inst
.operands
[i
].reg
= val
;
5652 inst
.operands
[i
].isscalar
= 1;
5653 inst
.operands
[i
].present
= 1;
5654 inst
.operands
[i
].vectype
= optype
;
5656 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5658 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5659 inst
.operands
[i
].reg
= val
;
5660 inst
.operands
[i
].isreg
= 1;
5661 inst
.operands
[i
++].present
= 1;
5663 if (skip_past_comma (&ptr
) == FAIL
)
5666 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5669 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5673 inst
.operands
[i
].reg
= val
;
5674 inst
.operands
[i
].isreg
= 1;
5675 inst
.operands
[i
].isvec
= 1;
5676 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5677 inst
.operands
[i
].vectype
= optype
;
5678 inst
.operands
[i
].present
= 1;
5680 if (rtype
== REG_TYPE_VFS
)
5684 if (skip_past_comma (&ptr
) == FAIL
)
5686 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5689 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5692 inst
.operands
[i
].reg
= val
;
5693 inst
.operands
[i
].isreg
= 1;
5694 inst
.operands
[i
].isvec
= 1;
5695 inst
.operands
[i
].issingle
= 1;
5696 inst
.operands
[i
].vectype
= optype
;
5697 inst
.operands
[i
].present
= 1;
5700 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5704 inst
.operands
[i
].reg
= val
;
5705 inst
.operands
[i
].isreg
= 1;
5706 inst
.operands
[i
].isvec
= 1;
5707 inst
.operands
[i
].issingle
= 1;
5708 inst
.operands
[i
].vectype
= optype
;
5709 inst
.operands
[i
++].present
= 1;
5714 first_error (_("parse error"));
5718 /* Successfully parsed the operands. Update args. */
5724 first_error (_("expected comma"));
5728 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5732 /* Matcher codes for parse_operands. */
5733 enum operand_parse_code
5735 OP_stop
, /* end of line */
5737 OP_RR
, /* ARM register */
5738 OP_RRnpc
, /* ARM register, not r15 */
5739 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5740 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5741 OP_RCP
, /* Coprocessor number */
5742 OP_RCN
, /* Coprocessor register */
5743 OP_RF
, /* FPA register */
5744 OP_RVS
, /* VFP single precision register */
5745 OP_RVD
, /* VFP double precision register (0..15) */
5746 OP_RND
, /* Neon double precision register (0..31) */
5747 OP_RNQ
, /* Neon quad precision register */
5748 OP_RVSD
, /* VFP single or double precision register */
5749 OP_RNDQ
, /* Neon double or quad precision register */
5750 OP_RNSDQ
, /* Neon single, double or quad precision register */
5751 OP_RNSC
, /* Neon scalar D[X] */
5752 OP_RVC
, /* VFP control register */
5753 OP_RMF
, /* Maverick F register */
5754 OP_RMD
, /* Maverick D register */
5755 OP_RMFX
, /* Maverick FX register */
5756 OP_RMDX
, /* Maverick DX register */
5757 OP_RMAX
, /* Maverick AX register */
5758 OP_RMDS
, /* Maverick DSPSC register */
5759 OP_RIWR
, /* iWMMXt wR register */
5760 OP_RIWC
, /* iWMMXt wC register */
5761 OP_RIWG
, /* iWMMXt wCG register */
5762 OP_RXA
, /* XScale accumulator register */
5764 OP_REGLST
, /* ARM register list */
5765 OP_VRSLST
, /* VFP single-precision register list */
5766 OP_VRDLST
, /* VFP double-precision register list */
5767 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5768 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5769 OP_NSTRLST
, /* Neon element/structure list */
5771 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5772 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5773 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5774 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5775 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5776 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5777 OP_VMOV
, /* Neon VMOV operands. */
5778 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5779 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5780 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5782 OP_I0
, /* immediate zero */
5783 OP_I7
, /* immediate value 0 .. 7 */
5784 OP_I15
, /* 0 .. 15 */
5785 OP_I16
, /* 1 .. 16 */
5786 OP_I16z
, /* 0 .. 16 */
5787 OP_I31
, /* 0 .. 31 */
5788 OP_I31w
, /* 0 .. 31, optional trailing ! */
5789 OP_I32
, /* 1 .. 32 */
5790 OP_I32z
, /* 0 .. 32 */
5791 OP_I63
, /* 0 .. 63 */
5792 OP_I63s
, /* -64 .. 63 */
5793 OP_I64
, /* 1 .. 64 */
5794 OP_I64z
, /* 0 .. 64 */
5795 OP_I255
, /* 0 .. 255 */
5797 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5798 OP_I7b
, /* 0 .. 7 */
5799 OP_I15b
, /* 0 .. 15 */
5800 OP_I31b
, /* 0 .. 31 */
5802 OP_SH
, /* shifter operand */
5803 OP_SHG
, /* shifter operand with possible group relocation */
5804 OP_ADDR
, /* Memory address expression (any mode) */
5805 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5806 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5807 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5808 OP_EXP
, /* arbitrary expression */
5809 OP_EXPi
, /* same, with optional immediate prefix */
5810 OP_EXPr
, /* same, with optional relocation suffix */
5811 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5813 OP_CPSF
, /* CPS flags */
5814 OP_ENDI
, /* Endianness specifier */
5815 OP_PSR
, /* CPSR/SPSR mask for msr */
5816 OP_COND
, /* conditional code */
5817 OP_TB
, /* Table branch. */
5819 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5820 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5822 OP_RRnpc_I0
, /* ARM register or literal 0 */
5823 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5824 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5825 OP_RF_IF
, /* FPA register or immediate */
5826 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5827 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5829 /* Optional operands. */
5830 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5831 OP_oI31b
, /* 0 .. 31 */
5832 OP_oI32b
, /* 1 .. 32 */
5833 OP_oIffffb
, /* 0 .. 65535 */
5834 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5836 OP_oRR
, /* ARM register */
5837 OP_oRRnpc
, /* ARM register, not the PC */
5838 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5839 OP_oRND
, /* Optional Neon double precision register */
5840 OP_oRNQ
, /* Optional Neon quad precision register */
5841 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5842 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5843 OP_oSHll
, /* LSL immediate */
5844 OP_oSHar
, /* ASR immediate */
5845 OP_oSHllar
, /* LSL or ASR immediate */
5846 OP_oROR
, /* ROR 0/8/16/24 */
5847 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5849 OP_FIRST_OPTIONAL
= OP_oI7b
5852 /* Generic instruction operand parser. This does no encoding and no
5853 semantic validation; it merely squirrels values away in the inst
5854 structure. Returns SUCCESS or FAIL depending on whether the
5855 specified grammar matched. */
5857 parse_operands (char *str
, const unsigned char *pattern
)
5859 unsigned const char *upat
= pattern
;
5860 char *backtrack_pos
= 0;
5861 const char *backtrack_error
= 0;
5862 int i
, val
, backtrack_index
= 0;
5863 enum arm_reg_type rtype
;
5864 parse_operand_result result
;
5866 #define po_char_or_fail(chr) \
5869 if (skip_past_char (&str, chr) == FAIL) \
5874 #define po_reg_or_fail(regtype) \
5877 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5878 & inst.operands[i].vectype); \
5881 first_error (_(reg_expected_msgs[regtype])); \
5884 inst.operands[i].reg = val; \
5885 inst.operands[i].isreg = 1; \
5886 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5887 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5888 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5889 || rtype == REG_TYPE_VFD \
5890 || rtype == REG_TYPE_NQ); \
5894 #define po_reg_or_goto(regtype, label) \
5897 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5898 & inst.operands[i].vectype); \
5902 inst.operands[i].reg = val; \
5903 inst.operands[i].isreg = 1; \
5904 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5905 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5906 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5907 || rtype == REG_TYPE_VFD \
5908 || rtype == REG_TYPE_NQ); \
5912 #define po_imm_or_fail(min, max, popt) \
5915 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5917 inst.operands[i].imm = val; \
5921 #define po_scalar_or_goto(elsz, label) \
5924 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5927 inst.operands[i].reg = val; \
5928 inst.operands[i].isscalar = 1; \
5932 #define po_misc_or_fail(expr) \
5940 #define po_misc_or_fail_no_backtrack(expr) \
5944 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
5945 backtrack_pos = 0; \
5946 if (result != PARSE_OPERAND_SUCCESS) \
5951 skip_whitespace (str
);
5953 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5955 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5957 /* Remember where we are in case we need to backtrack. */
5958 gas_assert (!backtrack_pos
);
5959 backtrack_pos
= str
;
5960 backtrack_error
= inst
.error
;
5961 backtrack_index
= i
;
5964 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5965 po_char_or_fail (',');
5973 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5974 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5975 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5976 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5977 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5978 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5980 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5982 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5984 /* Also accept generic coprocessor regs for unknown registers. */
5986 po_reg_or_fail (REG_TYPE_CN
);
5988 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5989 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5990 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5991 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5992 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5993 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5994 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5995 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5996 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5997 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5999 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6001 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6002 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6004 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6006 /* Neon scalar. Using an element size of 8 means that some invalid
6007 scalars are accepted here, so deal with those in later code. */
6008 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6012 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6015 po_imm_or_fail (0, 0, TRUE
);
6020 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6025 po_scalar_or_goto (8, try_rr
);
6028 po_reg_or_fail (REG_TYPE_RN
);
6034 po_scalar_or_goto (8, try_nsdq
);
6037 po_reg_or_fail (REG_TYPE_NSDQ
);
6043 po_scalar_or_goto (8, try_ndq
);
6046 po_reg_or_fail (REG_TYPE_NDQ
);
6052 po_scalar_or_goto (8, try_vfd
);
6055 po_reg_or_fail (REG_TYPE_VFD
);
6060 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6061 not careful then bad things might happen. */
6062 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6067 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6070 /* There's a possibility of getting a 64-bit immediate here, so
6071 we need special handling. */
6072 if (parse_big_immediate (&str
, i
) == FAIL
)
6074 inst
.error
= _("immediate value is out of range");
6082 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6085 po_imm_or_fail (0, 63, TRUE
);
6090 po_char_or_fail ('[');
6091 po_reg_or_fail (REG_TYPE_RN
);
6092 po_char_or_fail (']');
6097 po_reg_or_fail (REG_TYPE_RN
);
6098 if (skip_past_char (&str
, '!') == SUCCESS
)
6099 inst
.operands
[i
].writeback
= 1;
6103 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6104 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6105 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6106 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6107 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6108 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6109 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6110 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6111 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6112 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6113 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6114 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6116 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6118 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6119 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6121 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6122 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6123 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6125 /* Immediate variants */
6127 po_char_or_fail ('{');
6128 po_imm_or_fail (0, 255, TRUE
);
6129 po_char_or_fail ('}');
6133 /* The expression parser chokes on a trailing !, so we have
6134 to find it first and zap it. */
6137 while (*s
&& *s
!= ',')
6142 inst
.operands
[i
].writeback
= 1;
6144 po_imm_or_fail (0, 31, TRUE
);
6152 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6157 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6162 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6164 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6166 val
= parse_reloc (&str
);
6169 inst
.error
= _("unrecognized relocation suffix");
6172 else if (val
!= BFD_RELOC_UNUSED
)
6174 inst
.operands
[i
].imm
= val
;
6175 inst
.operands
[i
].hasreloc
= 1;
6180 /* Operand for MOVW or MOVT. */
6182 po_misc_or_fail (parse_half (&str
));
6185 /* Register or expression. */
6186 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6187 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6189 /* Register or immediate. */
6190 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6191 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6193 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6195 if (!is_immediate_prefix (*str
))
6198 val
= parse_fpa_immediate (&str
);
6201 /* FPA immediates are encoded as registers 8-15.
6202 parse_fpa_immediate has already applied the offset. */
6203 inst
.operands
[i
].reg
= val
;
6204 inst
.operands
[i
].isreg
= 1;
6207 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6208 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6210 /* Two kinds of register. */
6213 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6215 || (rege
->type
!= REG_TYPE_MMXWR
6216 && rege
->type
!= REG_TYPE_MMXWC
6217 && rege
->type
!= REG_TYPE_MMXWCG
))
6219 inst
.error
= _("iWMMXt data or control register expected");
6222 inst
.operands
[i
].reg
= rege
->number
;
6223 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6229 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6231 || (rege
->type
!= REG_TYPE_MMXWC
6232 && rege
->type
!= REG_TYPE_MMXWCG
))
6234 inst
.error
= _("iWMMXt control register expected");
6237 inst
.operands
[i
].reg
= rege
->number
;
6238 inst
.operands
[i
].isreg
= 1;
6243 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6244 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6245 case OP_oROR
: val
= parse_ror (&str
); break;
6246 case OP_PSR
: val
= parse_psr (&str
); break;
6247 case OP_COND
: val
= parse_cond (&str
); break;
6248 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
6251 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6252 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6255 val
= parse_psr (&str
);
6259 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6262 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6264 if (strncasecmp (str
, "APSR_", 5) == 0)
6271 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6272 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6273 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6274 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6275 default: found
= 16;
6279 inst
.operands
[i
].isvec
= 1;
6280 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6281 inst
.operands
[i
].reg
= REG_PC
;
6288 po_misc_or_fail (parse_tb (&str
));
6291 /* Register lists. */
6293 val
= parse_reg_list (&str
);
6296 inst
.operands
[1].writeback
= 1;
6302 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6306 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6310 /* Allow Q registers too. */
6311 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6316 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6318 inst
.operands
[i
].issingle
= 1;
6323 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6328 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6329 &inst
.operands
[i
].vectype
);
6332 /* Addressing modes */
6334 po_misc_or_fail (parse_address (&str
, i
));
6338 po_misc_or_fail_no_backtrack (
6339 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6343 po_misc_or_fail_no_backtrack (
6344 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6348 po_misc_or_fail_no_backtrack (
6349 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6353 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6357 po_misc_or_fail_no_backtrack (
6358 parse_shifter_operand_group_reloc (&str
, i
));
6362 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6366 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6370 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6374 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6377 /* Various value-based sanity checks and shared operations. We
6378 do not signal immediate failures for the register constraints;
6379 this allows a syntax error to take precedence. */
6388 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6389 inst
.error
= BAD_PC
;
6407 inst
.operands
[i
].imm
= val
;
6414 /* If we get here, this operand was successfully parsed. */
6415 inst
.operands
[i
].present
= 1;
6419 inst
.error
= BAD_ARGS
;
6424 /* The parse routine should already have set inst.error, but set a
6425 default here just in case. */
6427 inst
.error
= _("syntax error");
6431 /* Do not backtrack over a trailing optional argument that
6432 absorbed some text. We will only fail again, with the
6433 'garbage following instruction' error message, which is
6434 probably less helpful than the current one. */
6435 if (backtrack_index
== i
&& backtrack_pos
!= str
6436 && upat
[i
+1] == OP_stop
)
6439 inst
.error
= _("syntax error");
6443 /* Try again, skipping the optional argument at backtrack_pos. */
6444 str
= backtrack_pos
;
6445 inst
.error
= backtrack_error
;
6446 inst
.operands
[backtrack_index
].present
= 0;
6447 i
= backtrack_index
;
6451 /* Check that we have parsed all the arguments. */
6452 if (*str
!= '\0' && !inst
.error
)
6453 inst
.error
= _("garbage following instruction");
6455 return inst
.error
? FAIL
: SUCCESS
;
6458 #undef po_char_or_fail
6459 #undef po_reg_or_fail
6460 #undef po_reg_or_goto
6461 #undef po_imm_or_fail
6462 #undef po_scalar_or_fail
6464 /* Shorthand macro for instruction encoding functions issuing errors. */
6465 #define constraint(expr, err) \
6476 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6477 instructions are unpredictable if these registers are used. This
6478 is the BadReg predicate in ARM's Thumb-2 documentation. */
6479 #define reject_bad_reg(reg) \
6481 if (reg == REG_SP || reg == REG_PC) \
6483 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6488 /* If REG is R13 (the stack pointer), warn that its use is
6490 #define warn_deprecated_sp(reg) \
6492 if (warn_on_deprecated && reg == REG_SP) \
6493 as_warn (_("use of r13 is deprecated")); \
6496 /* Functions for operand encoding. ARM, then Thumb. */
6498 #define rotate_left(v, n) (v << n | v >> (32 - n))
6500 /* If VAL can be encoded in the immediate field of an ARM instruction,
6501 return the encoded form. Otherwise, return FAIL. */
6504 encode_arm_immediate (unsigned int val
)
6508 for (i
= 0; i
< 32; i
+= 2)
6509 if ((a
= rotate_left (val
, i
)) <= 0xff)
6510 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6515 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6516 return the encoded form. Otherwise, return FAIL. */
6518 encode_thumb32_immediate (unsigned int val
)
6525 for (i
= 1; i
<= 24; i
++)
6528 if ((val
& ~(0xff << i
)) == 0)
6529 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6533 if (val
== ((a
<< 16) | a
))
6535 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6539 if (val
== ((a
<< 16) | a
))
6540 return 0x200 | (a
>> 8);
6544 /* Encode a VFP SP or DP register number into inst.instruction. */
6547 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6549 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6552 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6555 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6558 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6563 first_error (_("D register out of range for selected VFP version"));
6571 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6575 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6579 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6583 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6587 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6591 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6599 /* Encode a <shift> in an ARM-format instruction. The immediate,
6600 if any, is handled by md_apply_fix. */
6602 encode_arm_shift (int i
)
6604 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6605 inst
.instruction
|= SHIFT_ROR
<< 5;
6608 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6609 if (inst
.operands
[i
].immisreg
)
6611 inst
.instruction
|= SHIFT_BY_REG
;
6612 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6615 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6620 encode_arm_shifter_operand (int i
)
6622 if (inst
.operands
[i
].isreg
)
6624 inst
.instruction
|= inst
.operands
[i
].reg
;
6625 encode_arm_shift (i
);
6628 inst
.instruction
|= INST_IMMEDIATE
;
6631 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6633 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6635 gas_assert (inst
.operands
[i
].isreg
);
6636 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6638 if (inst
.operands
[i
].preind
)
6642 inst
.error
= _("instruction does not accept preindexed addressing");
6645 inst
.instruction
|= PRE_INDEX
;
6646 if (inst
.operands
[i
].writeback
)
6647 inst
.instruction
|= WRITE_BACK
;
6650 else if (inst
.operands
[i
].postind
)
6652 gas_assert (inst
.operands
[i
].writeback
);
6654 inst
.instruction
|= WRITE_BACK
;
6656 else /* unindexed - only for coprocessor */
6658 inst
.error
= _("instruction does not accept unindexed addressing");
6662 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6663 && (((inst
.instruction
& 0x000f0000) >> 16)
6664 == ((inst
.instruction
& 0x0000f000) >> 12)))
6665 as_warn ((inst
.instruction
& LOAD_BIT
)
6666 ? _("destination register same as write-back base")
6667 : _("source register same as write-back base"));
6670 /* inst.operands[i] was set up by parse_address. Encode it into an
6671 ARM-format mode 2 load or store instruction. If is_t is true,
6672 reject forms that cannot be used with a T instruction (i.e. not
6675 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6677 encode_arm_addr_mode_common (i
, is_t
);
6679 if (inst
.operands
[i
].immisreg
)
6681 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6682 inst
.instruction
|= inst
.operands
[i
].imm
;
6683 if (!inst
.operands
[i
].negative
)
6684 inst
.instruction
|= INDEX_UP
;
6685 if (inst
.operands
[i
].shifted
)
6687 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6688 inst
.instruction
|= SHIFT_ROR
<< 5;
6691 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6692 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6696 else /* immediate offset in inst.reloc */
6698 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6699 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6703 /* inst.operands[i] was set up by parse_address. Encode it into an
6704 ARM-format mode 3 load or store instruction. Reject forms that
6705 cannot be used with such instructions. If is_t is true, reject
6706 forms that cannot be used with a T instruction (i.e. not
6709 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6711 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6713 inst
.error
= _("instruction does not accept scaled register index");
6717 encode_arm_addr_mode_common (i
, is_t
);
6719 if (inst
.operands
[i
].immisreg
)
6721 inst
.instruction
|= inst
.operands
[i
].imm
;
6722 if (!inst
.operands
[i
].negative
)
6723 inst
.instruction
|= INDEX_UP
;
6725 else /* immediate offset in inst.reloc */
6727 inst
.instruction
|= HWOFFSET_IMM
;
6728 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6729 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6733 /* inst.operands[i] was set up by parse_address. Encode it into an
6734 ARM-format instruction. Reject all forms which cannot be encoded
6735 into a coprocessor load/store instruction. If wb_ok is false,
6736 reject use of writeback; if unind_ok is false, reject use of
6737 unindexed addressing. If reloc_override is not 0, use it instead
6738 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6739 (in which case it is preserved). */
6742 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6744 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6746 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6748 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6750 gas_assert (!inst
.operands
[i
].writeback
);
6753 inst
.error
= _("instruction does not support unindexed addressing");
6756 inst
.instruction
|= inst
.operands
[i
].imm
;
6757 inst
.instruction
|= INDEX_UP
;
6761 if (inst
.operands
[i
].preind
)
6762 inst
.instruction
|= PRE_INDEX
;
6764 if (inst
.operands
[i
].writeback
)
6766 if (inst
.operands
[i
].reg
== REG_PC
)
6768 inst
.error
= _("pc may not be used with write-back");
6773 inst
.error
= _("instruction does not support writeback");
6776 inst
.instruction
|= WRITE_BACK
;
6780 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6781 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6782 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6783 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6786 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6788 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6794 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6795 Determine whether it can be performed with a move instruction; if
6796 it can, convert inst.instruction to that move instruction and
6797 return TRUE; if it can't, convert inst.instruction to a literal-pool
6798 load and return FALSE. If this is not a valid thing to do in the
6799 current context, set inst.error and return TRUE.
6801 inst.operands[i] describes the destination register. */
6804 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6809 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6813 if ((inst
.instruction
& tbit
) == 0)
6815 inst
.error
= _("invalid pseudo operation");
6818 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6820 inst
.error
= _("constant expression expected");
6823 if (inst
.reloc
.exp
.X_op
== O_constant
)
6827 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6829 /* This can be done with a mov(1) instruction. */
6830 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6831 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6837 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6840 /* This can be done with a mov instruction. */
6841 inst
.instruction
&= LITERAL_MASK
;
6842 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6843 inst
.instruction
|= value
& 0xfff;
6847 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6850 /* This can be done with a mvn instruction. */
6851 inst
.instruction
&= LITERAL_MASK
;
6852 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6853 inst
.instruction
|= value
& 0xfff;
6859 if (add_to_lit_pool () == FAIL
)
6861 inst
.error
= _("literal pool insertion failed");
6864 inst
.operands
[1].reg
= REG_PC
;
6865 inst
.operands
[1].isreg
= 1;
6866 inst
.operands
[1].preind
= 1;
6867 inst
.reloc
.pc_rel
= 1;
6868 inst
.reloc
.type
= (thumb_p
6869 ? BFD_RELOC_ARM_THUMB_OFFSET
6871 ? BFD_RELOC_ARM_HWLITERAL
6872 : BFD_RELOC_ARM_LITERAL
));
6876 /* Functions for instruction encoding, sorted by sub-architecture.
6877 First some generics; their names are taken from the conventional
6878 bit positions for register arguments in ARM format instructions. */
6888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6894 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6895 inst
.instruction
|= inst
.operands
[1].reg
;
6901 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6902 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6908 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6909 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6915 unsigned Rn
= inst
.operands
[2].reg
;
6916 /* Enforce restrictions on SWP instruction. */
6917 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6918 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6919 _("Rn must not overlap other operands"));
6920 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6921 inst
.instruction
|= inst
.operands
[1].reg
;
6922 inst
.instruction
|= Rn
<< 16;
6928 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6929 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6930 inst
.instruction
|= inst
.operands
[2].reg
;
6936 inst
.instruction
|= inst
.operands
[0].reg
;
6937 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6938 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6944 inst
.instruction
|= inst
.operands
[0].imm
;
6950 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6951 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6954 /* ARM instructions, in alphabetical order by function name (except
6955 that wrapper functions appear immediately after the function they
6958 /* This is a pseudo-op of the form "adr rd, label" to be converted
6959 into a relative address of the form "add rd, pc, #label-.-8". */
6964 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6966 /* Frag hacking will turn this into a sub instruction if the offset turns
6967 out to be negative. */
6968 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6969 inst
.reloc
.pc_rel
= 1;
6970 inst
.reloc
.exp
.X_add_number
-= 8;
6973 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6974 into a relative address of the form:
6975 add rd, pc, #low(label-.-8)"
6976 add rd, rd, #high(label-.-8)" */
6981 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6983 /* Frag hacking will turn this into a sub instruction if the offset turns
6984 out to be negative. */
6985 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6986 inst
.reloc
.pc_rel
= 1;
6987 inst
.size
= INSN_SIZE
* 2;
6988 inst
.reloc
.exp
.X_add_number
-= 8;
6994 if (!inst
.operands
[1].present
)
6995 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6996 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6997 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6998 encode_arm_shifter_operand (2);
7004 if (inst
.operands
[0].present
)
7006 constraint ((inst
.instruction
& 0xf0) != 0x40
7007 && inst
.operands
[0].imm
!= 0xf,
7008 _("bad barrier type"));
7009 inst
.instruction
|= inst
.operands
[0].imm
;
7012 inst
.instruction
|= 0xf;
7018 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7019 constraint (msb
> 32, _("bit-field extends past end of register"));
7020 /* The instruction encoding stores the LSB and MSB,
7021 not the LSB and width. */
7022 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7023 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7024 inst
.instruction
|= (msb
- 1) << 16;
7032 /* #0 in second position is alternative syntax for bfc, which is
7033 the same instruction but with REG_PC in the Rm field. */
7034 if (!inst
.operands
[1].isreg
)
7035 inst
.operands
[1].reg
= REG_PC
;
7037 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7038 constraint (msb
> 32, _("bit-field extends past end of register"));
7039 /* The instruction encoding stores the LSB and MSB,
7040 not the LSB and width. */
7041 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7042 inst
.instruction
|= inst
.operands
[1].reg
;
7043 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7044 inst
.instruction
|= (msb
- 1) << 16;
7050 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7051 _("bit-field extends past end of register"));
7052 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7053 inst
.instruction
|= inst
.operands
[1].reg
;
7054 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7055 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7058 /* ARM V5 breakpoint instruction (argument parse)
7059 BKPT <16 bit unsigned immediate>
7060 Instruction is not conditional.
7061 The bit pattern given in insns[] has the COND_ALWAYS condition,
7062 and it is an error if the caller tried to override that. */
7067 /* Top 12 of 16 bits to bits 19:8. */
7068 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7070 /* Bottom 4 of 16 bits to bits 3:0. */
7071 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7075 encode_branch (int default_reloc
)
7077 if (inst
.operands
[0].hasreloc
)
7079 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7080 _("the only suffix valid here is '(plt)'"));
7081 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7085 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7087 inst
.reloc
.pc_rel
= 1;
7094 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7095 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7098 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7105 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7107 if (inst
.cond
== COND_ALWAYS
)
7108 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7110 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7114 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7117 /* ARM V5 branch-link-exchange instruction (argument parse)
7118 BLX <target_addr> ie BLX(1)
7119 BLX{<condition>} <Rm> ie BLX(2)
7120 Unfortunately, there are two different opcodes for this mnemonic.
7121 So, the insns[].value is not used, and the code here zaps values
7122 into inst.instruction.
7123 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7128 if (inst
.operands
[0].isreg
)
7130 /* Arg is a register; the opcode provided by insns[] is correct.
7131 It is not illegal to do "blx pc", just useless. */
7132 if (inst
.operands
[0].reg
== REG_PC
)
7133 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7135 inst
.instruction
|= inst
.operands
[0].reg
;
7139 /* Arg is an address; this instruction cannot be executed
7140 conditionally, and the opcode must be adjusted.
7141 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7142 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7143 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7144 inst
.instruction
= 0xfa000000;
7145 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7152 bfd_boolean want_reloc
;
7154 if (inst
.operands
[0].reg
== REG_PC
)
7155 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7157 inst
.instruction
|= inst
.operands
[0].reg
;
7158 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7159 it is for ARMv4t or earlier. */
7160 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7161 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7165 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7170 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7174 /* ARM v5TEJ. Jump to Jazelle code. */
7179 if (inst
.operands
[0].reg
== REG_PC
)
7180 as_tsktsk (_("use of r15 in bxj is not really useful"));
7182 inst
.instruction
|= inst
.operands
[0].reg
;
7185 /* Co-processor data operation:
7186 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7187 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7191 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7192 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7193 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7194 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7195 inst
.instruction
|= inst
.operands
[4].reg
;
7196 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7202 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7203 encode_arm_shifter_operand (1);
7206 /* Transfer between coprocessor and ARM registers.
7207 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7212 No special properties. */
7219 Rd
= inst
.operands
[2].reg
;
7222 if (inst
.instruction
== 0xee000010
7223 || inst
.instruction
== 0xfe000010)
7225 reject_bad_reg (Rd
);
7228 constraint (Rd
== REG_SP
, BAD_SP
);
7233 if (inst
.instruction
== 0xe000010)
7234 constraint (Rd
== REG_PC
, BAD_PC
);
7238 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7239 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7240 inst
.instruction
|= Rd
<< 12;
7241 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7242 inst
.instruction
|= inst
.operands
[4].reg
;
7243 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7246 /* Transfer between coprocessor register and pair of ARM registers.
7247 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7252 Two XScale instructions are special cases of these:
7254 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7255 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7257 Result unpredictable if Rd or Rn is R15. */
7264 Rd
= inst
.operands
[2].reg
;
7265 Rn
= inst
.operands
[3].reg
;
7269 reject_bad_reg (Rd
);
7270 reject_bad_reg (Rn
);
7274 constraint (Rd
== REG_PC
, BAD_PC
);
7275 constraint (Rn
== REG_PC
, BAD_PC
);
7278 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7279 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7280 inst
.instruction
|= Rd
<< 12;
7281 inst
.instruction
|= Rn
<< 16;
7282 inst
.instruction
|= inst
.operands
[4].reg
;
7288 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7289 if (inst
.operands
[1].present
)
7291 inst
.instruction
|= CPSI_MMOD
;
7292 inst
.instruction
|= inst
.operands
[1].imm
;
7299 inst
.instruction
|= inst
.operands
[0].imm
;
7305 /* There is no IT instruction in ARM mode. We
7306 process it to do the validation as if in
7307 thumb mode, just in case the code gets
7308 assembled for thumb using the unified syntax. */
7313 set_it_insn_type (IT_INSN
);
7314 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7315 now_it
.cc
= inst
.operands
[0].imm
;
7322 int base_reg
= inst
.operands
[0].reg
;
7323 int range
= inst
.operands
[1].imm
;
7325 inst
.instruction
|= base_reg
<< 16;
7326 inst
.instruction
|= range
;
7328 if (inst
.operands
[1].writeback
)
7329 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7331 if (inst
.operands
[0].writeback
)
7333 inst
.instruction
|= WRITE_BACK
;
7334 /* Check for unpredictable uses of writeback. */
7335 if (inst
.instruction
& LOAD_BIT
)
7337 /* Not allowed in LDM type 2. */
7338 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7339 && ((range
& (1 << REG_PC
)) == 0))
7340 as_warn (_("writeback of base register is UNPREDICTABLE"));
7341 /* Only allowed if base reg not in list for other types. */
7342 else if (range
& (1 << base_reg
))
7343 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7347 /* Not allowed for type 2. */
7348 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7349 as_warn (_("writeback of base register is UNPREDICTABLE"));
7350 /* Only allowed if base reg not in list, or first in list. */
7351 else if ((range
& (1 << base_reg
))
7352 && (range
& ((1 << base_reg
) - 1)))
7353 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7358 /* ARMv5TE load-consecutive (argument parse)
7367 constraint (inst
.operands
[0].reg
% 2 != 0,
7368 _("first destination register must be even"));
7369 constraint (inst
.operands
[1].present
7370 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7371 _("can only load two consecutive registers"));
7372 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7373 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7375 if (!inst
.operands
[1].present
)
7376 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7378 if (inst
.instruction
& LOAD_BIT
)
7380 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7381 register and the first register written; we have to diagnose
7382 overlap between the base and the second register written here. */
7384 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7385 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7386 as_warn (_("base register written back, and overlaps "
7387 "second destination register"));
7389 /* For an index-register load, the index register must not overlap the
7390 destination (even if not write-back). */
7391 else if (inst
.operands
[2].immisreg
7392 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7393 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7394 as_warn (_("index register overlaps destination register"));
7397 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7398 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7404 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7405 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7406 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7407 || inst
.operands
[1].negative
7408 /* This can arise if the programmer has written
7410 or if they have mistakenly used a register name as the last
7413 It is very difficult to distinguish between these two cases
7414 because "rX" might actually be a label. ie the register
7415 name has been occluded by a symbol of the same name. So we
7416 just generate a general 'bad addressing mode' type error
7417 message and leave it up to the programmer to discover the
7418 true cause and fix their mistake. */
7419 || (inst
.operands
[1].reg
== REG_PC
),
7422 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7423 || inst
.reloc
.exp
.X_add_number
!= 0,
7424 _("offset must be zero in ARM encoding"));
7426 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7427 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7428 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7434 constraint (inst
.operands
[0].reg
% 2 != 0,
7435 _("even register required"));
7436 constraint (inst
.operands
[1].present
7437 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7438 _("can only load two consecutive registers"));
7439 /* If op 1 were present and equal to PC, this function wouldn't
7440 have been called in the first place. */
7441 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7443 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7444 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7450 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7451 if (!inst
.operands
[1].isreg
)
7452 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7454 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7460 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7462 if (inst
.operands
[1].preind
)
7464 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7465 || inst
.reloc
.exp
.X_add_number
!= 0,
7466 _("this instruction requires a post-indexed address"));
7468 inst
.operands
[1].preind
= 0;
7469 inst
.operands
[1].postind
= 1;
7470 inst
.operands
[1].writeback
= 1;
7472 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7473 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7476 /* Halfword and signed-byte load/store operations. */
7481 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7482 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7483 if (!inst
.operands
[1].isreg
)
7484 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7486 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7492 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7494 if (inst
.operands
[1].preind
)
7496 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7497 || inst
.reloc
.exp
.X_add_number
!= 0,
7498 _("this instruction requires a post-indexed address"));
7500 inst
.operands
[1].preind
= 0;
7501 inst
.operands
[1].postind
= 1;
7502 inst
.operands
[1].writeback
= 1;
7504 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7505 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7508 /* Co-processor register load/store.
7509 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7513 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7514 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7515 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7521 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7522 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7523 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7524 && !(inst
.instruction
& 0x00400000))
7525 as_tsktsk (_("Rd and Rm should be different in mla"));
7527 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7528 inst
.instruction
|= inst
.operands
[1].reg
;
7529 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7530 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7536 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7537 encode_arm_shifter_operand (1);
7540 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7547 top
= (inst
.instruction
& 0x00400000) != 0;
7548 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7549 _(":lower16: not allowed this instruction"));
7550 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7551 _(":upper16: not allowed instruction"));
7552 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7553 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7555 imm
= inst
.reloc
.exp
.X_add_number
;
7556 /* The value is in two pieces: 0:11, 16:19. */
7557 inst
.instruction
|= (imm
& 0x00000fff);
7558 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7562 static void do_vfp_nsyn_opcode (const char *);
7565 do_vfp_nsyn_mrs (void)
7567 if (inst
.operands
[0].isvec
)
7569 if (inst
.operands
[1].reg
!= 1)
7570 first_error (_("operand 1 must be FPSCR"));
7571 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7572 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7573 do_vfp_nsyn_opcode ("fmstat");
7575 else if (inst
.operands
[1].isvec
)
7576 do_vfp_nsyn_opcode ("fmrx");
7584 do_vfp_nsyn_msr (void)
7586 if (inst
.operands
[0].isvec
)
7587 do_vfp_nsyn_opcode ("fmxr");
7597 unsigned Rt
= inst
.operands
[0].reg
;
7599 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7601 inst
.error
= BAD_SP
;
7605 /* APSR_ sets isvec. All other refs to PC are illegal. */
7606 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7608 inst
.error
= BAD_PC
;
7612 if (inst
.operands
[1].reg
!= 1)
7613 first_error (_("operand 1 must be FPSCR"));
7615 inst
.instruction
|= (Rt
<< 12);
7621 unsigned Rt
= inst
.operands
[1].reg
;
7624 reject_bad_reg (Rt
);
7625 else if (Rt
== REG_PC
)
7627 inst
.error
= BAD_PC
;
7631 if (inst
.operands
[0].reg
!= 1)
7632 first_error (_("operand 0 must be FPSCR"));
7634 inst
.instruction
|= (Rt
<< 12);
7640 if (do_vfp_nsyn_mrs () == SUCCESS
)
7643 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7644 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7646 _("'CPSR' or 'SPSR' expected"));
7647 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7648 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7649 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7652 /* Two possible forms:
7653 "{C|S}PSR_<field>, Rm",
7654 "{C|S}PSR_f, #expression". */
7659 if (do_vfp_nsyn_msr () == SUCCESS
)
7662 inst
.instruction
|= inst
.operands
[0].imm
;
7663 if (inst
.operands
[1].isreg
)
7664 inst
.instruction
|= inst
.operands
[1].reg
;
7667 inst
.instruction
|= INST_IMMEDIATE
;
7668 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7669 inst
.reloc
.pc_rel
= 0;
7676 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7678 if (!inst
.operands
[2].present
)
7679 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7680 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7681 inst
.instruction
|= inst
.operands
[1].reg
;
7682 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7684 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7685 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7686 as_tsktsk (_("Rd and Rm should be different in mul"));
7689 /* Long Multiply Parser
7690 UMULL RdLo, RdHi, Rm, Rs
7691 SMULL RdLo, RdHi, Rm, Rs
7692 UMLAL RdLo, RdHi, Rm, Rs
7693 SMLAL RdLo, RdHi, Rm, Rs. */
7698 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7699 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7700 inst
.instruction
|= inst
.operands
[2].reg
;
7701 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7703 /* rdhi and rdlo must be different. */
7704 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7705 as_tsktsk (_("rdhi and rdlo must be different"));
7707 /* rdhi, rdlo and rm must all be different before armv6. */
7708 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7709 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7710 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7711 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7717 if (inst
.operands
[0].present
7718 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7720 /* Architectural NOP hints are CPSR sets with no bits selected. */
7721 inst
.instruction
&= 0xf0000000;
7722 inst
.instruction
|= 0x0320f000;
7723 if (inst
.operands
[0].present
)
7724 inst
.instruction
|= inst
.operands
[0].imm
;
7728 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7729 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7730 Condition defaults to COND_ALWAYS.
7731 Error if Rd, Rn or Rm are R15. */
7736 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7737 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7738 inst
.instruction
|= inst
.operands
[2].reg
;
7739 if (inst
.operands
[3].present
)
7740 encode_arm_shift (3);
7743 /* ARM V6 PKHTB (Argument Parse). */
7748 if (!inst
.operands
[3].present
)
7750 /* If the shift specifier is omitted, turn the instruction
7751 into pkhbt rd, rm, rn. */
7752 inst
.instruction
&= 0xfff00010;
7753 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7754 inst
.instruction
|= inst
.operands
[1].reg
;
7755 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7759 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7760 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7761 inst
.instruction
|= inst
.operands
[2].reg
;
7762 encode_arm_shift (3);
7766 /* ARMv5TE: Preload-Cache
7770 Syntactically, like LDR with B=1, W=0, L=1. */
7775 constraint (!inst
.operands
[0].isreg
,
7776 _("'[' expected after PLD mnemonic"));
7777 constraint (inst
.operands
[0].postind
,
7778 _("post-indexed expression used in preload instruction"));
7779 constraint (inst
.operands
[0].writeback
,
7780 _("writeback used in preload instruction"));
7781 constraint (!inst
.operands
[0].preind
,
7782 _("unindexed addressing used in preload instruction"));
7783 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7786 /* ARMv7: PLI <addr_mode> */
7790 constraint (!inst
.operands
[0].isreg
,
7791 _("'[' expected after PLI mnemonic"));
7792 constraint (inst
.operands
[0].postind
,
7793 _("post-indexed expression used in preload instruction"));
7794 constraint (inst
.operands
[0].writeback
,
7795 _("writeback used in preload instruction"));
7796 constraint (!inst
.operands
[0].preind
,
7797 _("unindexed addressing used in preload instruction"));
7798 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7799 inst
.instruction
&= ~PRE_INDEX
;
7805 inst
.operands
[1] = inst
.operands
[0];
7806 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7807 inst
.operands
[0].isreg
= 1;
7808 inst
.operands
[0].writeback
= 1;
7809 inst
.operands
[0].reg
= REG_SP
;
7813 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7814 word at the specified address and the following word
7816 Unconditionally executed.
7817 Error if Rn is R15. */
7822 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7823 if (inst
.operands
[0].writeback
)
7824 inst
.instruction
|= WRITE_BACK
;
7827 /* ARM V6 ssat (argument parse). */
7832 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7833 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7834 inst
.instruction
|= inst
.operands
[2].reg
;
7836 if (inst
.operands
[3].present
)
7837 encode_arm_shift (3);
7840 /* ARM V6 usat (argument parse). */
7845 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7846 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7847 inst
.instruction
|= inst
.operands
[2].reg
;
7849 if (inst
.operands
[3].present
)
7850 encode_arm_shift (3);
7853 /* ARM V6 ssat16 (argument parse). */
7858 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7859 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7860 inst
.instruction
|= inst
.operands
[2].reg
;
7866 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7867 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7868 inst
.instruction
|= inst
.operands
[2].reg
;
7871 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7872 preserving the other bits.
7874 setend <endian_specifier>, where <endian_specifier> is either
7880 if (inst
.operands
[0].imm
)
7881 inst
.instruction
|= 0x200;
7887 unsigned int Rm
= (inst
.operands
[1].present
7888 ? inst
.operands
[1].reg
7889 : inst
.operands
[0].reg
);
7891 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7892 inst
.instruction
|= Rm
;
7893 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7895 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7896 inst
.instruction
|= SHIFT_BY_REG
;
7899 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7905 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7906 inst
.reloc
.pc_rel
= 0;
7912 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7913 inst
.reloc
.pc_rel
= 0;
7916 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7917 SMLAxy{cond} Rd,Rm,Rs,Rn
7918 SMLAWy{cond} Rd,Rm,Rs,Rn
7919 Error if any register is R15. */
7924 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7925 inst
.instruction
|= inst
.operands
[1].reg
;
7926 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7927 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7930 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7931 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7932 Error if any register is R15.
7933 Warning if Rdlo == Rdhi. */
7938 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7939 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7940 inst
.instruction
|= inst
.operands
[2].reg
;
7941 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7943 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7944 as_tsktsk (_("rdhi and rdlo must be different"));
7947 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7948 SMULxy{cond} Rd,Rm,Rs
7949 Error if any register is R15. */
7954 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7955 inst
.instruction
|= inst
.operands
[1].reg
;
7956 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7959 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7960 the same for both ARM and Thumb-2. */
7967 if (inst
.operands
[0].present
)
7969 reg
= inst
.operands
[0].reg
;
7970 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
7975 inst
.instruction
|= reg
<< 16;
7976 inst
.instruction
|= inst
.operands
[1].imm
;
7977 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7978 inst
.instruction
|= WRITE_BACK
;
7981 /* ARM V6 strex (argument parse). */
7986 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7987 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7988 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7989 || inst
.operands
[2].negative
7990 /* See comment in do_ldrex(). */
7991 || (inst
.operands
[2].reg
== REG_PC
),
7994 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7995 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7997 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7998 || inst
.reloc
.exp
.X_add_number
!= 0,
7999 _("offset must be zero in ARM encoding"));
8001 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8002 inst
.instruction
|= inst
.operands
[1].reg
;
8003 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8004 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8010 constraint (inst
.operands
[1].reg
% 2 != 0,
8011 _("even register required"));
8012 constraint (inst
.operands
[2].present
8013 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8014 _("can only store two consecutive registers"));
8015 /* If op 2 were present and equal to PC, this function wouldn't
8016 have been called in the first place. */
8017 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8019 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8020 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8021 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8024 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8025 inst
.instruction
|= inst
.operands
[1].reg
;
8026 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8029 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8030 extends it to 32-bits, and adds the result to a value in another
8031 register. You can specify a rotation by 0, 8, 16, or 24 bits
8032 before extracting the 16-bit value.
8033 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8034 Condition defaults to COND_ALWAYS.
8035 Error if any register uses R15. */
8040 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8041 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8042 inst
.instruction
|= inst
.operands
[2].reg
;
8043 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8048 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8049 Condition defaults to COND_ALWAYS.
8050 Error if any register uses R15. */
8055 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8056 inst
.instruction
|= inst
.operands
[1].reg
;
8057 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8060 /* VFP instructions. In a logical order: SP variant first, monad
8061 before dyad, arithmetic then move then load/store. */
8064 do_vfp_sp_monadic (void)
8066 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8067 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8071 do_vfp_sp_dyadic (void)
8073 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8074 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8075 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8079 do_vfp_sp_compare_z (void)
8081 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8085 do_vfp_dp_sp_cvt (void)
8087 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8088 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8092 do_vfp_sp_dp_cvt (void)
8094 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8095 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8099 do_vfp_reg_from_sp (void)
8101 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8102 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8106 do_vfp_reg2_from_sp2 (void)
8108 constraint (inst
.operands
[2].imm
!= 2,
8109 _("only two consecutive VFP SP registers allowed here"));
8110 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8111 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8112 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8116 do_vfp_sp_from_reg (void)
8118 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8119 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8123 do_vfp_sp2_from_reg2 (void)
8125 constraint (inst
.operands
[0].imm
!= 2,
8126 _("only two consecutive VFP SP registers allowed here"));
8127 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8128 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8129 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8133 do_vfp_sp_ldst (void)
8135 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8136 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8140 do_vfp_dp_ldst (void)
8142 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8143 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8148 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8150 if (inst
.operands
[0].writeback
)
8151 inst
.instruction
|= WRITE_BACK
;
8153 constraint (ldstm_type
!= VFP_LDSTMIA
,
8154 _("this addressing mode requires base-register writeback"));
8155 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8156 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8157 inst
.instruction
|= inst
.operands
[1].imm
;
8161 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8165 if (inst
.operands
[0].writeback
)
8166 inst
.instruction
|= WRITE_BACK
;
8168 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8169 _("this addressing mode requires base-register writeback"));
8171 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8172 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8174 count
= inst
.operands
[1].imm
<< 1;
8175 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8178 inst
.instruction
|= count
;
8182 do_vfp_sp_ldstmia (void)
8184 vfp_sp_ldstm (VFP_LDSTMIA
);
8188 do_vfp_sp_ldstmdb (void)
8190 vfp_sp_ldstm (VFP_LDSTMDB
);
8194 do_vfp_dp_ldstmia (void)
8196 vfp_dp_ldstm (VFP_LDSTMIA
);
8200 do_vfp_dp_ldstmdb (void)
8202 vfp_dp_ldstm (VFP_LDSTMDB
);
8206 do_vfp_xp_ldstmia (void)
8208 vfp_dp_ldstm (VFP_LDSTMIAX
);
8212 do_vfp_xp_ldstmdb (void)
8214 vfp_dp_ldstm (VFP_LDSTMDBX
);
8218 do_vfp_dp_rd_rm (void)
8220 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8221 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8225 do_vfp_dp_rn_rd (void)
8227 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8228 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8232 do_vfp_dp_rd_rn (void)
8234 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8235 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8239 do_vfp_dp_rd_rn_rm (void)
8241 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8242 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8243 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8249 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8253 do_vfp_dp_rm_rd_rn (void)
8255 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8256 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8257 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8260 /* VFPv3 instructions. */
8262 do_vfp_sp_const (void)
8264 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8265 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8266 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8270 do_vfp_dp_const (void)
8272 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8273 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8274 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8278 vfp_conv (int srcsize
)
8280 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8281 inst
.instruction
|= (immbits
& 1) << 5;
8282 inst
.instruction
|= (immbits
>> 1);
8286 do_vfp_sp_conv_16 (void)
8288 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8293 do_vfp_dp_conv_16 (void)
8295 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8300 do_vfp_sp_conv_32 (void)
8302 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8307 do_vfp_dp_conv_32 (void)
8309 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8313 /* FPA instructions. Also in a logical order. */
8318 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8319 inst
.instruction
|= inst
.operands
[1].reg
;
8323 do_fpa_ldmstm (void)
8325 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8326 switch (inst
.operands
[1].imm
)
8328 case 1: inst
.instruction
|= CP_T_X
; break;
8329 case 2: inst
.instruction
|= CP_T_Y
; break;
8330 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8335 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8337 /* The instruction specified "ea" or "fd", so we can only accept
8338 [Rn]{!}. The instruction does not really support stacking or
8339 unstacking, so we have to emulate these by setting appropriate
8340 bits and offsets. */
8341 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8342 || inst
.reloc
.exp
.X_add_number
!= 0,
8343 _("this instruction does not support indexing"));
8345 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8346 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8348 if (!(inst
.instruction
& INDEX_UP
))
8349 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8351 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8353 inst
.operands
[2].preind
= 0;
8354 inst
.operands
[2].postind
= 1;
8358 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8361 /* iWMMXt instructions: strictly in alphabetical order. */
8364 do_iwmmxt_tandorc (void)
8366 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8370 do_iwmmxt_textrc (void)
8372 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8373 inst
.instruction
|= inst
.operands
[1].imm
;
8377 do_iwmmxt_textrm (void)
8379 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8380 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8381 inst
.instruction
|= inst
.operands
[2].imm
;
8385 do_iwmmxt_tinsr (void)
8387 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8388 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8389 inst
.instruction
|= inst
.operands
[2].imm
;
8393 do_iwmmxt_tmia (void)
8395 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8396 inst
.instruction
|= inst
.operands
[1].reg
;
8397 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8401 do_iwmmxt_waligni (void)
8403 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8404 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8405 inst
.instruction
|= inst
.operands
[2].reg
;
8406 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8410 do_iwmmxt_wmerge (void)
8412 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8413 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8414 inst
.instruction
|= inst
.operands
[2].reg
;
8415 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8419 do_iwmmxt_wmov (void)
8421 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8422 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8423 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8424 inst
.instruction
|= inst
.operands
[1].reg
;
8428 do_iwmmxt_wldstbh (void)
8431 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8433 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8435 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8436 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8440 do_iwmmxt_wldstw (void)
8442 /* RIWR_RIWC clears .isreg for a control register. */
8443 if (!inst
.operands
[0].isreg
)
8445 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8446 inst
.instruction
|= 0xf0000000;
8449 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8450 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8454 do_iwmmxt_wldstd (void)
8456 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8457 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8458 && inst
.operands
[1].immisreg
)
8460 inst
.instruction
&= ~0x1a000ff;
8461 inst
.instruction
|= (0xf << 28);
8462 if (inst
.operands
[1].preind
)
8463 inst
.instruction
|= PRE_INDEX
;
8464 if (!inst
.operands
[1].negative
)
8465 inst
.instruction
|= INDEX_UP
;
8466 if (inst
.operands
[1].writeback
)
8467 inst
.instruction
|= WRITE_BACK
;
8468 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8469 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8470 inst
.instruction
|= inst
.operands
[1].imm
;
8473 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8477 do_iwmmxt_wshufh (void)
8479 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8480 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8481 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8482 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8486 do_iwmmxt_wzero (void)
8488 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8489 inst
.instruction
|= inst
.operands
[0].reg
;
8490 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8491 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8495 do_iwmmxt_wrwrwr_or_imm5 (void)
8497 if (inst
.operands
[2].isreg
)
8500 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8501 _("immediate operand requires iWMMXt2"));
8503 if (inst
.operands
[2].imm
== 0)
8505 switch ((inst
.instruction
>> 20) & 0xf)
8511 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8512 inst
.operands
[2].imm
= 16;
8513 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8519 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8520 inst
.operands
[2].imm
= 32;
8521 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8528 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8530 wrn
= (inst
.instruction
>> 16) & 0xf;
8531 inst
.instruction
&= 0xff0fff0f;
8532 inst
.instruction
|= wrn
;
8533 /* Bail out here; the instruction is now assembled. */
8538 /* Map 32 -> 0, etc. */
8539 inst
.operands
[2].imm
&= 0x1f;
8540 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8544 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8545 operations first, then control, shift, and load/store. */
8547 /* Insns like "foo X,Y,Z". */
8550 do_mav_triple (void)
8552 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8553 inst
.instruction
|= inst
.operands
[1].reg
;
8554 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8557 /* Insns like "foo W,X,Y,Z".
8558 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8563 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8564 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8565 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8566 inst
.instruction
|= inst
.operands
[3].reg
;
8569 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8573 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8576 /* Maverick shift immediate instructions.
8577 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8578 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8583 int imm
= inst
.operands
[2].imm
;
8585 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8586 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8588 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8589 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8590 Bit 4 should be 0. */
8591 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8593 inst
.instruction
|= imm
;
8596 /* XScale instructions. Also sorted arithmetic before move. */
8598 /* Xscale multiply-accumulate (argument parse)
8601 MIAxycc acc0,Rm,Rs. */
8606 inst
.instruction
|= inst
.operands
[1].reg
;
8607 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8610 /* Xscale move-accumulator-register (argument parse)
8612 MARcc acc0,RdLo,RdHi. */
8617 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8618 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8621 /* Xscale move-register-accumulator (argument parse)
8623 MRAcc RdLo,RdHi,acc0. */
8628 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8629 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8630 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8633 /* Encoding functions relevant only to Thumb. */
8635 /* inst.operands[i] is a shifted-register operand; encode
8636 it into inst.instruction in the format used by Thumb32. */
8639 encode_thumb32_shifted_operand (int i
)
8641 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8642 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8644 constraint (inst
.operands
[i
].immisreg
,
8645 _("shift by register not allowed in thumb mode"));
8646 inst
.instruction
|= inst
.operands
[i
].reg
;
8647 if (shift
== SHIFT_RRX
)
8648 inst
.instruction
|= SHIFT_ROR
<< 4;
8651 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8652 _("expression too complex"));
8654 constraint (value
> 32
8655 || (value
== 32 && (shift
== SHIFT_LSL
8656 || shift
== SHIFT_ROR
)),
8657 _("shift expression is too large"));
8661 else if (value
== 32)
8664 inst
.instruction
|= shift
<< 4;
8665 inst
.instruction
|= (value
& 0x1c) << 10;
8666 inst
.instruction
|= (value
& 0x03) << 6;
8671 /* inst.operands[i] was set up by parse_address. Encode it into a
8672 Thumb32 format load or store instruction. Reject forms that cannot
8673 be used with such instructions. If is_t is true, reject forms that
8674 cannot be used with a T instruction; if is_d is true, reject forms
8675 that cannot be used with a D instruction. */
8678 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8680 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8682 constraint (!inst
.operands
[i
].isreg
,
8683 _("Instruction does not support =N addresses"));
8685 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8686 if (inst
.operands
[i
].immisreg
)
8688 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8689 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8690 constraint (inst
.operands
[i
].negative
,
8691 _("Thumb does not support negative register indexing"));
8692 constraint (inst
.operands
[i
].postind
,
8693 _("Thumb does not support register post-indexing"));
8694 constraint (inst
.operands
[i
].writeback
,
8695 _("Thumb does not support register indexing with writeback"));
8696 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8697 _("Thumb supports only LSL in shifted register indexing"));
8699 inst
.instruction
|= inst
.operands
[i
].imm
;
8700 if (inst
.operands
[i
].shifted
)
8702 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8703 _("expression too complex"));
8704 constraint (inst
.reloc
.exp
.X_add_number
< 0
8705 || inst
.reloc
.exp
.X_add_number
> 3,
8706 _("shift out of range"));
8707 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8709 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8711 else if (inst
.operands
[i
].preind
)
8713 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8714 _("cannot use writeback with PC-relative addressing"));
8715 constraint (is_t
&& inst
.operands
[i
].writeback
,
8716 _("cannot use writeback with this instruction"));
8720 inst
.instruction
|= 0x01000000;
8721 if (inst
.operands
[i
].writeback
)
8722 inst
.instruction
|= 0x00200000;
8726 inst
.instruction
|= 0x00000c00;
8727 if (inst
.operands
[i
].writeback
)
8728 inst
.instruction
|= 0x00000100;
8730 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8732 else if (inst
.operands
[i
].postind
)
8734 gas_assert (inst
.operands
[i
].writeback
);
8735 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8736 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8739 inst
.instruction
|= 0x00200000;
8741 inst
.instruction
|= 0x00000900;
8742 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8744 else /* unindexed - only for coprocessor */
8745 inst
.error
= _("instruction does not accept unindexed addressing");
8748 /* Table of Thumb instructions which exist in both 16- and 32-bit
8749 encodings (the latter only in post-V6T2 cores). The index is the
8750 value used in the insns table below. When there is more than one
8751 possible 16-bit encoding for the instruction, this table always
8753 Also contains several pseudo-instructions used during relaxation. */
8754 #define T16_32_TAB \
8755 X(_adc, 4140, eb400000), \
8756 X(_adcs, 4140, eb500000), \
8757 X(_add, 1c00, eb000000), \
8758 X(_adds, 1c00, eb100000), \
8759 X(_addi, 0000, f1000000), \
8760 X(_addis, 0000, f1100000), \
8761 X(_add_pc,000f, f20f0000), \
8762 X(_add_sp,000d, f10d0000), \
8763 X(_adr, 000f, f20f0000), \
8764 X(_and, 4000, ea000000), \
8765 X(_ands, 4000, ea100000), \
8766 X(_asr, 1000, fa40f000), \
8767 X(_asrs, 1000, fa50f000), \
8768 X(_b, e000, f000b000), \
8769 X(_bcond, d000, f0008000), \
8770 X(_bic, 4380, ea200000), \
8771 X(_bics, 4380, ea300000), \
8772 X(_cmn, 42c0, eb100f00), \
8773 X(_cmp, 2800, ebb00f00), \
8774 X(_cpsie, b660, f3af8400), \
8775 X(_cpsid, b670, f3af8600), \
8776 X(_cpy, 4600, ea4f0000), \
8777 X(_dec_sp,80dd, f1ad0d00), \
8778 X(_eor, 4040, ea800000), \
8779 X(_eors, 4040, ea900000), \
8780 X(_inc_sp,00dd, f10d0d00), \
8781 X(_ldmia, c800, e8900000), \
8782 X(_ldr, 6800, f8500000), \
8783 X(_ldrb, 7800, f8100000), \
8784 X(_ldrh, 8800, f8300000), \
8785 X(_ldrsb, 5600, f9100000), \
8786 X(_ldrsh, 5e00, f9300000), \
8787 X(_ldr_pc,4800, f85f0000), \
8788 X(_ldr_pc2,4800, f85f0000), \
8789 X(_ldr_sp,9800, f85d0000), \
8790 X(_lsl, 0000, fa00f000), \
8791 X(_lsls, 0000, fa10f000), \
8792 X(_lsr, 0800, fa20f000), \
8793 X(_lsrs, 0800, fa30f000), \
8794 X(_mov, 2000, ea4f0000), \
8795 X(_movs, 2000, ea5f0000), \
8796 X(_mul, 4340, fb00f000), \
8797 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8798 X(_mvn, 43c0, ea6f0000), \
8799 X(_mvns, 43c0, ea7f0000), \
8800 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8801 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8802 X(_orr, 4300, ea400000), \
8803 X(_orrs, 4300, ea500000), \
8804 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8805 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8806 X(_rev, ba00, fa90f080), \
8807 X(_rev16, ba40, fa90f090), \
8808 X(_revsh, bac0, fa90f0b0), \
8809 X(_ror, 41c0, fa60f000), \
8810 X(_rors, 41c0, fa70f000), \
8811 X(_sbc, 4180, eb600000), \
8812 X(_sbcs, 4180, eb700000), \
8813 X(_stmia, c000, e8800000), \
8814 X(_str, 6000, f8400000), \
8815 X(_strb, 7000, f8000000), \
8816 X(_strh, 8000, f8200000), \
8817 X(_str_sp,9000, f84d0000), \
8818 X(_sub, 1e00, eba00000), \
8819 X(_subs, 1e00, ebb00000), \
8820 X(_subi, 8000, f1a00000), \
8821 X(_subis, 8000, f1b00000), \
8822 X(_sxtb, b240, fa4ff080), \
8823 X(_sxth, b200, fa0ff080), \
8824 X(_tst, 4200, ea100f00), \
8825 X(_uxtb, b2c0, fa5ff080), \
8826 X(_uxth, b280, fa1ff080), \
8827 X(_nop, bf00, f3af8000), \
8828 X(_yield, bf10, f3af8001), \
8829 X(_wfe, bf20, f3af8002), \
8830 X(_wfi, bf30, f3af8003), \
8831 X(_sev, bf40, f3af8004),
8833 /* To catch errors in encoding functions, the codes are all offset by
8834 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8835 as 16-bit instructions. */
8836 #define X(a,b,c) T_MNEM##a
8837 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8840 #define X(a,b,c) 0x##b
8841 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8842 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8845 #define X(a,b,c) 0x##c
8846 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8847 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8848 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8852 /* Thumb instruction encoders, in alphabetical order. */
8857 do_t_add_sub_w (void)
8861 Rd
= inst
.operands
[0].reg
;
8862 Rn
= inst
.operands
[1].reg
;
8864 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
8865 is the SP-{plus,minus}-immediate form of the instruction. */
8867 constraint (Rd
== REG_PC
, BAD_PC
);
8869 reject_bad_reg (Rd
);
8871 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8872 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8875 /* Parse an add or subtract instruction. We get here with inst.instruction
8876 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8883 Rd
= inst
.operands
[0].reg
;
8884 Rs
= (inst
.operands
[1].present
8885 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8886 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8889 set_it_insn_type_last ();
8897 flags
= (inst
.instruction
== T_MNEM_adds
8898 || inst
.instruction
== T_MNEM_subs
);
8900 narrow
= !in_it_block ();
8902 narrow
= in_it_block ();
8903 if (!inst
.operands
[2].isreg
)
8907 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8909 add
= (inst
.instruction
== T_MNEM_add
8910 || inst
.instruction
== T_MNEM_adds
);
8912 if (inst
.size_req
!= 4)
8914 /* Attempt to use a narrow opcode, with relaxation if
8916 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8917 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8918 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8919 opcode
= T_MNEM_add_sp
;
8920 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8921 opcode
= T_MNEM_add_pc
;
8922 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8925 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8927 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8931 inst
.instruction
= THUMB_OP16(opcode
);
8932 inst
.instruction
|= (Rd
<< 4) | Rs
;
8933 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8934 if (inst
.size_req
!= 2)
8935 inst
.relax
= opcode
;
8938 constraint (inst
.size_req
== 2, BAD_HIREG
);
8940 if (inst
.size_req
== 4
8941 || (inst
.size_req
!= 2 && !opcode
))
8945 constraint (add
, BAD_PC
);
8946 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8947 _("only SUBS PC, LR, #const allowed"));
8948 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8949 _("expression too complex"));
8950 constraint (inst
.reloc
.exp
.X_add_number
< 0
8951 || inst
.reloc
.exp
.X_add_number
> 0xff,
8952 _("immediate value out of range"));
8953 inst
.instruction
= T2_SUBS_PC_LR
8954 | inst
.reloc
.exp
.X_add_number
;
8955 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8958 else if (Rs
== REG_PC
)
8960 /* Always use addw/subw. */
8961 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8962 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8966 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8967 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8970 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8972 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8974 inst
.instruction
|= Rd
<< 8;
8975 inst
.instruction
|= Rs
<< 16;
8980 Rn
= inst
.operands
[2].reg
;
8981 /* See if we can do this with a 16-bit instruction. */
8982 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8984 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8989 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8990 || inst
.instruction
== T_MNEM_add
)
8993 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8997 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
8999 /* Thumb-1 cores (except v6-M) require at least one high
9000 register in a narrow non flag setting add. */
9001 if (Rd
> 7 || Rn
> 7
9002 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9003 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9010 inst
.instruction
= T_OPCODE_ADD_HI
;
9011 inst
.instruction
|= (Rd
& 8) << 4;
9012 inst
.instruction
|= (Rd
& 7);
9013 inst
.instruction
|= Rn
<< 3;
9019 constraint (Rd
== REG_PC
, BAD_PC
);
9020 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9021 constraint (Rs
== REG_PC
, BAD_PC
);
9022 reject_bad_reg (Rn
);
9024 /* If we get here, it can't be done in 16 bits. */
9025 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9026 _("shift must be constant"));
9027 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9028 inst
.instruction
|= Rd
<< 8;
9029 inst
.instruction
|= Rs
<< 16;
9030 encode_thumb32_shifted_operand (2);
9035 constraint (inst
.instruction
== T_MNEM_adds
9036 || inst
.instruction
== T_MNEM_subs
,
9039 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9041 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9042 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9045 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9047 inst
.instruction
|= (Rd
<< 4) | Rs
;
9048 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9052 Rn
= inst
.operands
[2].reg
;
9053 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9055 /* We now have Rd, Rs, and Rn set to registers. */
9056 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9058 /* Can't do this for SUB. */
9059 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9060 inst
.instruction
= T_OPCODE_ADD_HI
;
9061 inst
.instruction
|= (Rd
& 8) << 4;
9062 inst
.instruction
|= (Rd
& 7);
9064 inst
.instruction
|= Rn
<< 3;
9066 inst
.instruction
|= Rs
<< 3;
9068 constraint (1, _("dest must overlap one source register"));
9072 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9073 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9074 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9084 Rd
= inst
.operands
[0].reg
;
9085 reject_bad_reg (Rd
);
9087 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9089 /* Defer to section relaxation. */
9090 inst
.relax
= inst
.instruction
;
9091 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9092 inst
.instruction
|= Rd
<< 4;
9094 else if (unified_syntax
&& inst
.size_req
!= 2)
9096 /* Generate a 32-bit opcode. */
9097 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9098 inst
.instruction
|= Rd
<< 8;
9099 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9100 inst
.reloc
.pc_rel
= 1;
9104 /* Generate a 16-bit opcode. */
9105 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9106 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9107 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9108 inst
.reloc
.pc_rel
= 1;
9110 inst
.instruction
|= Rd
<< 4;
9114 /* Arithmetic instructions for which there is just one 16-bit
9115 instruction encoding, and it allows only two low registers.
9116 For maximal compatibility with ARM syntax, we allow three register
9117 operands even when Thumb-32 instructions are not available, as long
9118 as the first two are identical. For instance, both "sbc r0,r1" and
9119 "sbc r0,r0,r1" are allowed. */
9125 Rd
= inst
.operands
[0].reg
;
9126 Rs
= (inst
.operands
[1].present
9127 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9128 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9129 Rn
= inst
.operands
[2].reg
;
9131 reject_bad_reg (Rd
);
9132 reject_bad_reg (Rs
);
9133 if (inst
.operands
[2].isreg
)
9134 reject_bad_reg (Rn
);
9138 if (!inst
.operands
[2].isreg
)
9140 /* For an immediate, we always generate a 32-bit opcode;
9141 section relaxation will shrink it later if possible. */
9142 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9143 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9144 inst
.instruction
|= Rd
<< 8;
9145 inst
.instruction
|= Rs
<< 16;
9146 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9152 /* See if we can do this with a 16-bit instruction. */
9153 if (THUMB_SETS_FLAGS (inst
.instruction
))
9154 narrow
= !in_it_block ();
9156 narrow
= in_it_block ();
9158 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9160 if (inst
.operands
[2].shifted
)
9162 if (inst
.size_req
== 4)
9168 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9169 inst
.instruction
|= Rd
;
9170 inst
.instruction
|= Rn
<< 3;
9174 /* If we get here, it can't be done in 16 bits. */
9175 constraint (inst
.operands
[2].shifted
9176 && inst
.operands
[2].immisreg
,
9177 _("shift must be constant"));
9178 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9179 inst
.instruction
|= Rd
<< 8;
9180 inst
.instruction
|= Rs
<< 16;
9181 encode_thumb32_shifted_operand (2);
9186 /* On its face this is a lie - the instruction does set the
9187 flags. However, the only supported mnemonic in this mode
9189 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9191 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9192 _("unshifted register required"));
9193 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9194 constraint (Rd
!= Rs
,
9195 _("dest and source1 must be the same register"));
9197 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9198 inst
.instruction
|= Rd
;
9199 inst
.instruction
|= Rn
<< 3;
9203 /* Similarly, but for instructions where the arithmetic operation is
9204 commutative, so we can allow either of them to be different from
9205 the destination operand in a 16-bit instruction. For instance, all
9206 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9213 Rd
= inst
.operands
[0].reg
;
9214 Rs
= (inst
.operands
[1].present
9215 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9216 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9217 Rn
= inst
.operands
[2].reg
;
9219 reject_bad_reg (Rd
);
9220 reject_bad_reg (Rs
);
9221 if (inst
.operands
[2].isreg
)
9222 reject_bad_reg (Rn
);
9226 if (!inst
.operands
[2].isreg
)
9228 /* For an immediate, we always generate a 32-bit opcode;
9229 section relaxation will shrink it later if possible. */
9230 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9231 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9232 inst
.instruction
|= Rd
<< 8;
9233 inst
.instruction
|= Rs
<< 16;
9234 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9240 /* See if we can do this with a 16-bit instruction. */
9241 if (THUMB_SETS_FLAGS (inst
.instruction
))
9242 narrow
= !in_it_block ();
9244 narrow
= in_it_block ();
9246 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9248 if (inst
.operands
[2].shifted
)
9250 if (inst
.size_req
== 4)
9257 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9258 inst
.instruction
|= Rd
;
9259 inst
.instruction
|= Rn
<< 3;
9264 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9265 inst
.instruction
|= Rd
;
9266 inst
.instruction
|= Rs
<< 3;
9271 /* If we get here, it can't be done in 16 bits. */
9272 constraint (inst
.operands
[2].shifted
9273 && inst
.operands
[2].immisreg
,
9274 _("shift must be constant"));
9275 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9276 inst
.instruction
|= Rd
<< 8;
9277 inst
.instruction
|= Rs
<< 16;
9278 encode_thumb32_shifted_operand (2);
9283 /* On its face this is a lie - the instruction does set the
9284 flags. However, the only supported mnemonic in this mode
9286 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9288 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9289 _("unshifted register required"));
9290 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9292 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9293 inst
.instruction
|= Rd
;
9296 inst
.instruction
|= Rn
<< 3;
9298 inst
.instruction
|= Rs
<< 3;
9300 constraint (1, _("dest must overlap one source register"));
9307 if (inst
.operands
[0].present
)
9309 constraint ((inst
.instruction
& 0xf0) != 0x40
9310 && inst
.operands
[0].imm
!= 0xf,
9311 _("bad barrier type"));
9312 inst
.instruction
|= inst
.operands
[0].imm
;
9315 inst
.instruction
|= 0xf;
9322 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9323 constraint (msb
> 32, _("bit-field extends past end of register"));
9324 /* The instruction encoding stores the LSB and MSB,
9325 not the LSB and width. */
9326 Rd
= inst
.operands
[0].reg
;
9327 reject_bad_reg (Rd
);
9328 inst
.instruction
|= Rd
<< 8;
9329 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9330 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9331 inst
.instruction
|= msb
- 1;
9340 Rd
= inst
.operands
[0].reg
;
9341 reject_bad_reg (Rd
);
9343 /* #0 in second position is alternative syntax for bfc, which is
9344 the same instruction but with REG_PC in the Rm field. */
9345 if (!inst
.operands
[1].isreg
)
9349 Rn
= inst
.operands
[1].reg
;
9350 reject_bad_reg (Rn
);
9353 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9354 constraint (msb
> 32, _("bit-field extends past end of register"));
9355 /* The instruction encoding stores the LSB and MSB,
9356 not the LSB and width. */
9357 inst
.instruction
|= Rd
<< 8;
9358 inst
.instruction
|= Rn
<< 16;
9359 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9360 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9361 inst
.instruction
|= msb
- 1;
9369 Rd
= inst
.operands
[0].reg
;
9370 Rn
= inst
.operands
[1].reg
;
9372 reject_bad_reg (Rd
);
9373 reject_bad_reg (Rn
);
9375 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9376 _("bit-field extends past end of register"));
9377 inst
.instruction
|= Rd
<< 8;
9378 inst
.instruction
|= Rn
<< 16;
9379 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9380 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9381 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9384 /* ARM V5 Thumb BLX (argument parse)
9385 BLX <target_addr> which is BLX(1)
9386 BLX <Rm> which is BLX(2)
9387 Unfortunately, there are two different opcodes for this mnemonic.
9388 So, the insns[].value is not used, and the code here zaps values
9389 into inst.instruction.
9391 ??? How to take advantage of the additional two bits of displacement
9392 available in Thumb32 mode? Need new relocation? */
9397 set_it_insn_type_last ();
9399 if (inst
.operands
[0].isreg
)
9401 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9402 /* We have a register, so this is BLX(2). */
9403 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9407 /* No register. This must be BLX(1). */
9408 inst
.instruction
= 0xf000e800;
9409 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9410 inst
.reloc
.pc_rel
= 1;
9421 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9425 /* Conditional branches inside IT blocks are encoded as unconditional
9432 if (cond
!= COND_ALWAYS
)
9433 opcode
= T_MNEM_bcond
;
9435 opcode
= inst
.instruction
;
9437 if (unified_syntax
&& inst
.size_req
== 4)
9439 inst
.instruction
= THUMB_OP32(opcode
);
9440 if (cond
== COND_ALWAYS
)
9441 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9444 gas_assert (cond
!= 0xF);
9445 inst
.instruction
|= cond
<< 22;
9446 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9451 inst
.instruction
= THUMB_OP16(opcode
);
9452 if (cond
== COND_ALWAYS
)
9453 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9456 inst
.instruction
|= cond
<< 8;
9457 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9459 /* Allow section relaxation. */
9460 if (unified_syntax
&& inst
.size_req
!= 2)
9461 inst
.relax
= opcode
;
9464 inst
.reloc
.pc_rel
= 1;
9470 constraint (inst
.cond
!= COND_ALWAYS
,
9471 _("instruction is always unconditional"));
9472 if (inst
.operands
[0].present
)
9474 constraint (inst
.operands
[0].imm
> 255,
9475 _("immediate value out of range"));
9476 inst
.instruction
|= inst
.operands
[0].imm
;
9477 set_it_insn_type (NEUTRAL_IT_INSN
);
9482 do_t_branch23 (void)
9484 set_it_insn_type_last ();
9485 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9486 inst
.reloc
.pc_rel
= 1;
9488 #if defined(OBJ_COFF)
9489 /* If the destination of the branch is a defined symbol which does not have
9490 the THUMB_FUNC attribute, then we must be calling a function which has
9491 the (interfacearm) attribute. We look for the Thumb entry point to that
9492 function and change the branch to refer to that function instead. */
9493 if ( inst
.reloc
.exp
.X_op
== O_symbol
9494 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9495 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9496 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9497 inst
.reloc
.exp
.X_add_symbol
=
9498 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9505 set_it_insn_type_last ();
9506 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9507 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9508 should cause the alignment to be checked once it is known. This is
9509 because BX PC only works if the instruction is word aligned. */
9517 set_it_insn_type_last ();
9518 Rm
= inst
.operands
[0].reg
;
9519 reject_bad_reg (Rm
);
9520 inst
.instruction
|= Rm
<< 16;
9529 Rd
= inst
.operands
[0].reg
;
9530 Rm
= inst
.operands
[1].reg
;
9532 reject_bad_reg (Rd
);
9533 reject_bad_reg (Rm
);
9535 inst
.instruction
|= Rd
<< 8;
9536 inst
.instruction
|= Rm
<< 16;
9537 inst
.instruction
|= Rm
;
9543 set_it_insn_type (OUTSIDE_IT_INSN
);
9544 inst
.instruction
|= inst
.operands
[0].imm
;
9550 set_it_insn_type (OUTSIDE_IT_INSN
);
9552 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9553 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9555 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9556 inst
.instruction
= 0xf3af8000;
9557 inst
.instruction
|= imod
<< 9;
9558 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9559 if (inst
.operands
[1].present
)
9560 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9564 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9565 && (inst
.operands
[0].imm
& 4),
9566 _("selected processor does not support 'A' form "
9567 "of this instruction"));
9568 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9569 _("Thumb does not support the 2-argument "
9570 "form of this instruction"));
9571 inst
.instruction
|= inst
.operands
[0].imm
;
9575 /* THUMB CPY instruction (argument parse). */
9580 if (inst
.size_req
== 4)
9582 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9583 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9584 inst
.instruction
|= inst
.operands
[1].reg
;
9588 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9589 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9590 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9597 set_it_insn_type (OUTSIDE_IT_INSN
);
9598 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9599 inst
.instruction
|= inst
.operands
[0].reg
;
9600 inst
.reloc
.pc_rel
= 1;
9601 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9607 inst
.instruction
|= inst
.operands
[0].imm
;
9613 unsigned Rd
, Rn
, Rm
;
9615 Rd
= inst
.operands
[0].reg
;
9616 Rn
= (inst
.operands
[1].present
9617 ? inst
.operands
[1].reg
: Rd
);
9618 Rm
= inst
.operands
[2].reg
;
9620 reject_bad_reg (Rd
);
9621 reject_bad_reg (Rn
);
9622 reject_bad_reg (Rm
);
9624 inst
.instruction
|= Rd
<< 8;
9625 inst
.instruction
|= Rn
<< 16;
9626 inst
.instruction
|= Rm
;
9632 if (unified_syntax
&& inst
.size_req
== 4)
9633 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9635 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9641 unsigned int cond
= inst
.operands
[0].imm
;
9643 set_it_insn_type (IT_INSN
);
9644 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9647 /* If the condition is a negative condition, invert the mask. */
9648 if ((cond
& 0x1) == 0x0)
9650 unsigned int mask
= inst
.instruction
& 0x000f;
9652 if ((mask
& 0x7) == 0)
9653 /* no conversion needed */;
9654 else if ((mask
& 0x3) == 0)
9656 else if ((mask
& 0x1) == 0)
9661 inst
.instruction
&= 0xfff0;
9662 inst
.instruction
|= mask
;
9665 inst
.instruction
|= cond
<< 4;
9668 /* Helper function used for both push/pop and ldm/stm. */
9670 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9674 load
= (inst
.instruction
& (1 << 20)) != 0;
9676 if (mask
& (1 << 13))
9677 inst
.error
= _("SP not allowed in register list");
9680 if (mask
& (1 << 15))
9682 if (mask
& (1 << 14))
9683 inst
.error
= _("LR and PC should not both be in register list");
9685 set_it_insn_type_last ();
9688 if ((mask
& (1 << base
)) != 0
9690 as_warn (_("base register should not be in register list "
9691 "when written back"));
9695 if (mask
& (1 << 15))
9696 inst
.error
= _("PC not allowed in register list");
9698 if (mask
& (1 << base
))
9699 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9702 if ((mask
& (mask
- 1)) == 0)
9704 /* Single register transfers implemented as str/ldr. */
9707 if (inst
.instruction
& (1 << 23))
9708 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9710 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9714 if (inst
.instruction
& (1 << 23))
9715 inst
.instruction
= 0x00800000; /* ia -> [base] */
9717 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9720 inst
.instruction
|= 0xf8400000;
9722 inst
.instruction
|= 0x00100000;
9724 mask
= ffs (mask
) - 1;
9728 inst
.instruction
|= WRITE_BACK
;
9730 inst
.instruction
|= mask
;
9731 inst
.instruction
|= base
<< 16;
9737 /* This really doesn't seem worth it. */
9738 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9739 _("expression too complex"));
9740 constraint (inst
.operands
[1].writeback
,
9741 _("Thumb load/store multiple does not support {reglist}^"));
9749 /* See if we can use a 16-bit instruction. */
9750 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9751 && inst
.size_req
!= 4
9752 && !(inst
.operands
[1].imm
& ~0xff))
9754 mask
= 1 << inst
.operands
[0].reg
;
9756 if (inst
.operands
[0].reg
<= 7
9757 && (inst
.instruction
== T_MNEM_stmia
9758 ? inst
.operands
[0].writeback
9759 : (inst
.operands
[0].writeback
9760 == !(inst
.operands
[1].imm
& mask
))))
9762 if (inst
.instruction
== T_MNEM_stmia
9763 && (inst
.operands
[1].imm
& mask
)
9764 && (inst
.operands
[1].imm
& (mask
- 1)))
9765 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9766 inst
.operands
[0].reg
);
9768 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9769 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9770 inst
.instruction
|= inst
.operands
[1].imm
;
9773 else if (inst
.operands
[0] .reg
== REG_SP
9774 && inst
.operands
[0].writeback
)
9776 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9777 ? T_MNEM_push
: T_MNEM_pop
);
9778 inst
.instruction
|= inst
.operands
[1].imm
;
9785 if (inst
.instruction
< 0xffff)
9786 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9788 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9789 inst
.operands
[0].writeback
);
9794 constraint (inst
.operands
[0].reg
> 7
9795 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9796 constraint (inst
.instruction
!= T_MNEM_ldmia
9797 && inst
.instruction
!= T_MNEM_stmia
,
9798 _("Thumb-2 instruction only valid in unified syntax"));
9799 if (inst
.instruction
== T_MNEM_stmia
)
9801 if (!inst
.operands
[0].writeback
)
9802 as_warn (_("this instruction will write back the base register"));
9803 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9804 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9805 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9806 inst
.operands
[0].reg
);
9810 if (!inst
.operands
[0].writeback
9811 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9812 as_warn (_("this instruction will write back the base register"));
9813 else if (inst
.operands
[0].writeback
9814 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9815 as_warn (_("this instruction will not write back the base register"));
9818 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9819 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9820 inst
.instruction
|= inst
.operands
[1].imm
;
9827 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9828 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9829 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9830 || inst
.operands
[1].negative
,
9833 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9834 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9835 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9841 if (!inst
.operands
[1].present
)
9843 constraint (inst
.operands
[0].reg
== REG_LR
,
9844 _("r14 not allowed as first register "
9845 "when second register is omitted"));
9846 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9848 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9851 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9852 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9853 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9859 unsigned long opcode
;
9862 if (inst
.operands
[0].isreg
9863 && !inst
.operands
[0].preind
9864 && inst
.operands
[0].reg
== REG_PC
)
9865 set_it_insn_type_last ();
9867 opcode
= inst
.instruction
;
9870 if (!inst
.operands
[1].isreg
)
9872 if (opcode
<= 0xffff)
9873 inst
.instruction
= THUMB_OP32 (opcode
);
9874 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9877 if (inst
.operands
[1].isreg
9878 && !inst
.operands
[1].writeback
9879 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9880 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9882 && inst
.size_req
!= 4)
9884 /* Insn may have a 16-bit form. */
9885 Rn
= inst
.operands
[1].reg
;
9886 if (inst
.operands
[1].immisreg
)
9888 inst
.instruction
= THUMB_OP16 (opcode
);
9890 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9893 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9894 && opcode
!= T_MNEM_ldrsb
)
9895 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9896 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9903 if (inst
.reloc
.pc_rel
)
9904 opcode
= T_MNEM_ldr_pc2
;
9906 opcode
= T_MNEM_ldr_pc
;
9910 if (opcode
== T_MNEM_ldr
)
9911 opcode
= T_MNEM_ldr_sp
;
9913 opcode
= T_MNEM_str_sp
;
9915 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9919 inst
.instruction
= inst
.operands
[0].reg
;
9920 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9922 inst
.instruction
|= THUMB_OP16 (opcode
);
9923 if (inst
.size_req
== 2)
9924 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9926 inst
.relax
= opcode
;
9930 /* Definitely a 32-bit variant. */
9931 inst
.instruction
= THUMB_OP32 (opcode
);
9932 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9933 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9937 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9939 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9941 /* Only [Rn,Rm] is acceptable. */
9942 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9943 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9944 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9945 || inst
.operands
[1].negative
,
9946 _("Thumb does not support this addressing mode"));
9947 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9951 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9952 if (!inst
.operands
[1].isreg
)
9953 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9956 constraint (!inst
.operands
[1].preind
9957 || inst
.operands
[1].shifted
9958 || inst
.operands
[1].writeback
,
9959 _("Thumb does not support this addressing mode"));
9960 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9962 constraint (inst
.instruction
& 0x0600,
9963 _("byte or halfword not valid for base register"));
9964 constraint (inst
.operands
[1].reg
== REG_PC
9965 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9966 _("r15 based store not allowed"));
9967 constraint (inst
.operands
[1].immisreg
,
9968 _("invalid base register for register offset"));
9970 if (inst
.operands
[1].reg
== REG_PC
)
9971 inst
.instruction
= T_OPCODE_LDR_PC
;
9972 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9973 inst
.instruction
= T_OPCODE_LDR_SP
;
9975 inst
.instruction
= T_OPCODE_STR_SP
;
9977 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9978 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9982 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9983 if (!inst
.operands
[1].immisreg
)
9985 /* Immediate offset. */
9986 inst
.instruction
|= inst
.operands
[0].reg
;
9987 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9988 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9992 /* Register offset. */
9993 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9994 constraint (inst
.operands
[1].negative
,
9995 _("Thumb does not support this addressing mode"));
9998 switch (inst
.instruction
)
10000 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10001 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10002 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10003 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10004 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10005 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10006 case 0x5600 /* ldrsb */:
10007 case 0x5e00 /* ldrsh */: break;
10011 inst
.instruction
|= inst
.operands
[0].reg
;
10012 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10013 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10019 if (!inst
.operands
[1].present
)
10021 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10022 constraint (inst
.operands
[0].reg
== REG_LR
,
10023 _("r14 not allowed here"));
10025 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10026 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10027 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10033 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10034 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10040 unsigned Rd
, Rn
, Rm
, Ra
;
10042 Rd
= inst
.operands
[0].reg
;
10043 Rn
= inst
.operands
[1].reg
;
10044 Rm
= inst
.operands
[2].reg
;
10045 Ra
= inst
.operands
[3].reg
;
10047 reject_bad_reg (Rd
);
10048 reject_bad_reg (Rn
);
10049 reject_bad_reg (Rm
);
10050 reject_bad_reg (Ra
);
10052 inst
.instruction
|= Rd
<< 8;
10053 inst
.instruction
|= Rn
<< 16;
10054 inst
.instruction
|= Rm
;
10055 inst
.instruction
|= Ra
<< 12;
10061 unsigned RdLo
, RdHi
, Rn
, Rm
;
10063 RdLo
= inst
.operands
[0].reg
;
10064 RdHi
= inst
.operands
[1].reg
;
10065 Rn
= inst
.operands
[2].reg
;
10066 Rm
= inst
.operands
[3].reg
;
10068 reject_bad_reg (RdLo
);
10069 reject_bad_reg (RdHi
);
10070 reject_bad_reg (Rn
);
10071 reject_bad_reg (Rm
);
10073 inst
.instruction
|= RdLo
<< 12;
10074 inst
.instruction
|= RdHi
<< 8;
10075 inst
.instruction
|= Rn
<< 16;
10076 inst
.instruction
|= Rm
;
10080 do_t_mov_cmp (void)
10084 Rn
= inst
.operands
[0].reg
;
10085 Rm
= inst
.operands
[1].reg
;
10088 set_it_insn_type_last ();
10090 if (unified_syntax
)
10092 int r0off
= (inst
.instruction
== T_MNEM_mov
10093 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10094 unsigned long opcode
;
10095 bfd_boolean narrow
;
10096 bfd_boolean low_regs
;
10098 low_regs
= (Rn
<= 7 && Rm
<= 7);
10099 opcode
= inst
.instruction
;
10100 if (in_it_block ())
10101 narrow
= opcode
!= T_MNEM_movs
;
10103 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10104 if (inst
.size_req
== 4
10105 || inst
.operands
[1].shifted
)
10108 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10109 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10110 && !inst
.operands
[1].shifted
10114 inst
.instruction
= T2_SUBS_PC_LR
;
10118 if (opcode
== T_MNEM_cmp
)
10120 constraint (Rn
== REG_PC
, BAD_PC
);
10123 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10125 warn_deprecated_sp (Rm
);
10126 /* R15 was documented as a valid choice for Rm in ARMv6,
10127 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10128 tools reject R15, so we do too. */
10129 constraint (Rm
== REG_PC
, BAD_PC
);
10132 reject_bad_reg (Rm
);
10134 else if (opcode
== T_MNEM_mov
10135 || opcode
== T_MNEM_movs
)
10137 if (inst
.operands
[1].isreg
)
10139 if (opcode
== T_MNEM_movs
)
10141 reject_bad_reg (Rn
);
10142 reject_bad_reg (Rm
);
10144 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10145 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10146 reject_bad_reg (Rm
);
10149 reject_bad_reg (Rn
);
10152 if (!inst
.operands
[1].isreg
)
10154 /* Immediate operand. */
10155 if (!in_it_block () && opcode
== T_MNEM_mov
)
10157 if (low_regs
&& narrow
)
10159 inst
.instruction
= THUMB_OP16 (opcode
);
10160 inst
.instruction
|= Rn
<< 8;
10161 if (inst
.size_req
== 2)
10162 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10164 inst
.relax
= opcode
;
10168 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10169 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10170 inst
.instruction
|= Rn
<< r0off
;
10171 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10174 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10175 && (inst
.instruction
== T_MNEM_mov
10176 || inst
.instruction
== T_MNEM_movs
))
10178 /* Register shifts are encoded as separate shift instructions. */
10179 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10181 if (in_it_block ())
10186 if (inst
.size_req
== 4)
10189 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10195 switch (inst
.operands
[1].shift_kind
)
10198 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10201 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10204 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10207 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10213 inst
.instruction
= opcode
;
10216 inst
.instruction
|= Rn
;
10217 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10222 inst
.instruction
|= CONDS_BIT
;
10224 inst
.instruction
|= Rn
<< 8;
10225 inst
.instruction
|= Rm
<< 16;
10226 inst
.instruction
|= inst
.operands
[1].imm
;
10231 /* Some mov with immediate shift have narrow variants.
10232 Register shifts are handled above. */
10233 if (low_regs
&& inst
.operands
[1].shifted
10234 && (inst
.instruction
== T_MNEM_mov
10235 || inst
.instruction
== T_MNEM_movs
))
10237 if (in_it_block ())
10238 narrow
= (inst
.instruction
== T_MNEM_mov
);
10240 narrow
= (inst
.instruction
== T_MNEM_movs
);
10245 switch (inst
.operands
[1].shift_kind
)
10247 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10248 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10249 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10250 default: narrow
= FALSE
; break;
10256 inst
.instruction
|= Rn
;
10257 inst
.instruction
|= Rm
<< 3;
10258 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10262 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10263 inst
.instruction
|= Rn
<< r0off
;
10264 encode_thumb32_shifted_operand (1);
10268 switch (inst
.instruction
)
10271 inst
.instruction
= T_OPCODE_MOV_HR
;
10272 inst
.instruction
|= (Rn
& 0x8) << 4;
10273 inst
.instruction
|= (Rn
& 0x7);
10274 inst
.instruction
|= Rm
<< 3;
10278 /* We know we have low registers at this point.
10279 Generate ADD Rd, Rs, #0. */
10280 inst
.instruction
= T_OPCODE_ADD_I3
;
10281 inst
.instruction
|= Rn
;
10282 inst
.instruction
|= Rm
<< 3;
10288 inst
.instruction
= T_OPCODE_CMP_LR
;
10289 inst
.instruction
|= Rn
;
10290 inst
.instruction
|= Rm
<< 3;
10294 inst
.instruction
= T_OPCODE_CMP_HR
;
10295 inst
.instruction
|= (Rn
& 0x8) << 4;
10296 inst
.instruction
|= (Rn
& 0x7);
10297 inst
.instruction
|= Rm
<< 3;
10304 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10306 /* PR 10443: Do not silently ignore shifted operands. */
10307 constraint (inst
.operands
[1].shifted
,
10308 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10310 if (inst
.operands
[1].isreg
)
10312 if (Rn
< 8 && Rm
< 8)
10314 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10315 since a MOV instruction produces unpredictable results. */
10316 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10317 inst
.instruction
= T_OPCODE_ADD_I3
;
10319 inst
.instruction
= T_OPCODE_CMP_LR
;
10321 inst
.instruction
|= Rn
;
10322 inst
.instruction
|= Rm
<< 3;
10326 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10327 inst
.instruction
= T_OPCODE_MOV_HR
;
10329 inst
.instruction
= T_OPCODE_CMP_HR
;
10335 constraint (Rn
> 7,
10336 _("only lo regs allowed with immediate"));
10337 inst
.instruction
|= Rn
<< 8;
10338 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10349 top
= (inst
.instruction
& 0x00800000) != 0;
10350 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10352 constraint (top
, _(":lower16: not allowed this instruction"));
10353 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10355 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10357 constraint (!top
, _(":upper16: not allowed this instruction"));
10358 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10361 Rd
= inst
.operands
[0].reg
;
10362 reject_bad_reg (Rd
);
10364 inst
.instruction
|= Rd
<< 8;
10365 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10367 imm
= inst
.reloc
.exp
.X_add_number
;
10368 inst
.instruction
|= (imm
& 0xf000) << 4;
10369 inst
.instruction
|= (imm
& 0x0800) << 15;
10370 inst
.instruction
|= (imm
& 0x0700) << 4;
10371 inst
.instruction
|= (imm
& 0x00ff);
10376 do_t_mvn_tst (void)
10380 Rn
= inst
.operands
[0].reg
;
10381 Rm
= inst
.operands
[1].reg
;
10383 if (inst
.instruction
== T_MNEM_cmp
10384 || inst
.instruction
== T_MNEM_cmn
)
10385 constraint (Rn
== REG_PC
, BAD_PC
);
10387 reject_bad_reg (Rn
);
10388 reject_bad_reg (Rm
);
10390 if (unified_syntax
)
10392 int r0off
= (inst
.instruction
== T_MNEM_mvn
10393 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10394 bfd_boolean narrow
;
10396 if (inst
.size_req
== 4
10397 || inst
.instruction
> 0xffff
10398 || inst
.operands
[1].shifted
10399 || Rn
> 7 || Rm
> 7)
10401 else if (inst
.instruction
== T_MNEM_cmn
)
10403 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10404 narrow
= !in_it_block ();
10406 narrow
= in_it_block ();
10408 if (!inst
.operands
[1].isreg
)
10410 /* For an immediate, we always generate a 32-bit opcode;
10411 section relaxation will shrink it later if possible. */
10412 if (inst
.instruction
< 0xffff)
10413 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10414 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10415 inst
.instruction
|= Rn
<< r0off
;
10416 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10420 /* See if we can do this with a 16-bit instruction. */
10423 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10424 inst
.instruction
|= Rn
;
10425 inst
.instruction
|= Rm
<< 3;
10429 constraint (inst
.operands
[1].shifted
10430 && inst
.operands
[1].immisreg
,
10431 _("shift must be constant"));
10432 if (inst
.instruction
< 0xffff)
10433 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10434 inst
.instruction
|= Rn
<< r0off
;
10435 encode_thumb32_shifted_operand (1);
10441 constraint (inst
.instruction
> 0xffff
10442 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10443 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10444 _("unshifted register required"));
10445 constraint (Rn
> 7 || Rm
> 7,
10448 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10449 inst
.instruction
|= Rn
;
10450 inst
.instruction
|= Rm
<< 3;
10460 if (do_vfp_nsyn_mrs () == SUCCESS
)
10463 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10466 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10467 _("selected processor does not support "
10468 "requested special purpose register"));
10472 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10473 _("selected processor does not support "
10474 "requested special purpose register"));
10475 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10476 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10477 _("'CPSR' or 'SPSR' expected"));
10480 Rd
= inst
.operands
[0].reg
;
10481 reject_bad_reg (Rd
);
10483 inst
.instruction
|= Rd
<< 8;
10484 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10485 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10494 if (do_vfp_nsyn_msr () == SUCCESS
)
10497 constraint (!inst
.operands
[1].isreg
,
10498 _("Thumb encoding does not support an immediate here"));
10499 flags
= inst
.operands
[0].imm
;
10502 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10503 _("selected processor does not support "
10504 "requested special purpose register"));
10508 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10509 _("selected processor does not support "
10510 "requested special purpose register"));
10514 Rn
= inst
.operands
[1].reg
;
10515 reject_bad_reg (Rn
);
10517 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10518 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10519 inst
.instruction
|= (flags
& 0xff);
10520 inst
.instruction
|= Rn
<< 16;
10526 bfd_boolean narrow
;
10527 unsigned Rd
, Rn
, Rm
;
10529 if (!inst
.operands
[2].present
)
10530 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10532 Rd
= inst
.operands
[0].reg
;
10533 Rn
= inst
.operands
[1].reg
;
10534 Rm
= inst
.operands
[2].reg
;
10536 if (unified_syntax
)
10538 if (inst
.size_req
== 4
10544 else if (inst
.instruction
== T_MNEM_muls
)
10545 narrow
= !in_it_block ();
10547 narrow
= in_it_block ();
10551 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10552 constraint (Rn
> 7 || Rm
> 7,
10559 /* 16-bit MULS/Conditional MUL. */
10560 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10561 inst
.instruction
|= Rd
;
10564 inst
.instruction
|= Rm
<< 3;
10566 inst
.instruction
|= Rn
<< 3;
10568 constraint (1, _("dest must overlap one source register"));
10572 constraint (inst
.instruction
!= T_MNEM_mul
,
10573 _("Thumb-2 MUL must not set flags"));
10575 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10576 inst
.instruction
|= Rd
<< 8;
10577 inst
.instruction
|= Rn
<< 16;
10578 inst
.instruction
|= Rm
<< 0;
10580 reject_bad_reg (Rd
);
10581 reject_bad_reg (Rn
);
10582 reject_bad_reg (Rm
);
10589 unsigned RdLo
, RdHi
, Rn
, Rm
;
10591 RdLo
= inst
.operands
[0].reg
;
10592 RdHi
= inst
.operands
[1].reg
;
10593 Rn
= inst
.operands
[2].reg
;
10594 Rm
= inst
.operands
[3].reg
;
10596 reject_bad_reg (RdLo
);
10597 reject_bad_reg (RdHi
);
10598 reject_bad_reg (Rn
);
10599 reject_bad_reg (Rm
);
10601 inst
.instruction
|= RdLo
<< 12;
10602 inst
.instruction
|= RdHi
<< 8;
10603 inst
.instruction
|= Rn
<< 16;
10604 inst
.instruction
|= Rm
;
10607 as_tsktsk (_("rdhi and rdlo must be different"));
10613 set_it_insn_type (NEUTRAL_IT_INSN
);
10615 if (unified_syntax
)
10617 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10619 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10620 inst
.instruction
|= inst
.operands
[0].imm
;
10624 /* PR9722: Check for Thumb2 availability before
10625 generating a thumb2 nop instruction. */
10626 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10628 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10629 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10632 inst
.instruction
= 0x46c0;
10637 constraint (inst
.operands
[0].present
,
10638 _("Thumb does not support NOP with hints"));
10639 inst
.instruction
= 0x46c0;
10646 if (unified_syntax
)
10648 bfd_boolean narrow
;
10650 if (THUMB_SETS_FLAGS (inst
.instruction
))
10651 narrow
= !in_it_block ();
10653 narrow
= in_it_block ();
10654 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10656 if (inst
.size_req
== 4)
10661 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10662 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10663 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10667 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10668 inst
.instruction
|= inst
.operands
[0].reg
;
10669 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10674 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10676 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10678 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10679 inst
.instruction
|= inst
.operands
[0].reg
;
10680 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10689 Rd
= inst
.operands
[0].reg
;
10690 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10692 reject_bad_reg (Rd
);
10693 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10694 reject_bad_reg (Rn
);
10696 inst
.instruction
|= Rd
<< 8;
10697 inst
.instruction
|= Rn
<< 16;
10699 if (!inst
.operands
[2].isreg
)
10701 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10702 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10708 Rm
= inst
.operands
[2].reg
;
10709 reject_bad_reg (Rm
);
10711 constraint (inst
.operands
[2].shifted
10712 && inst
.operands
[2].immisreg
,
10713 _("shift must be constant"));
10714 encode_thumb32_shifted_operand (2);
10721 unsigned Rd
, Rn
, Rm
;
10723 Rd
= inst
.operands
[0].reg
;
10724 Rn
= inst
.operands
[1].reg
;
10725 Rm
= inst
.operands
[2].reg
;
10727 reject_bad_reg (Rd
);
10728 reject_bad_reg (Rn
);
10729 reject_bad_reg (Rm
);
10731 inst
.instruction
|= Rd
<< 8;
10732 inst
.instruction
|= Rn
<< 16;
10733 inst
.instruction
|= Rm
;
10734 if (inst
.operands
[3].present
)
10736 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10737 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10738 _("expression too complex"));
10739 inst
.instruction
|= (val
& 0x1c) << 10;
10740 inst
.instruction
|= (val
& 0x03) << 6;
10747 if (!inst
.operands
[3].present
)
10751 inst
.instruction
&= ~0x00000020;
10753 /* PR 10168. Swap the Rm and Rn registers. */
10754 Rtmp
= inst
.operands
[1].reg
;
10755 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10756 inst
.operands
[2].reg
= Rtmp
;
10764 if (inst
.operands
[0].immisreg
)
10765 reject_bad_reg (inst
.operands
[0].imm
);
10767 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10771 do_t_push_pop (void)
10775 constraint (inst
.operands
[0].writeback
,
10776 _("push/pop do not support {reglist}^"));
10777 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10778 _("expression too complex"));
10780 mask
= inst
.operands
[0].imm
;
10781 if ((mask
& ~0xff) == 0)
10782 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10783 else if ((inst
.instruction
== T_MNEM_push
10784 && (mask
& ~0xff) == 1 << REG_LR
)
10785 || (inst
.instruction
== T_MNEM_pop
10786 && (mask
& ~0xff) == 1 << REG_PC
))
10788 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10789 inst
.instruction
|= THUMB_PP_PC_LR
;
10790 inst
.instruction
|= mask
& 0xff;
10792 else if (unified_syntax
)
10794 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10795 encode_thumb2_ldmstm (13, mask
, TRUE
);
10799 inst
.error
= _("invalid register list to push/pop instruction");
10809 Rd
= inst
.operands
[0].reg
;
10810 Rm
= inst
.operands
[1].reg
;
10812 reject_bad_reg (Rd
);
10813 reject_bad_reg (Rm
);
10815 inst
.instruction
|= Rd
<< 8;
10816 inst
.instruction
|= Rm
<< 16;
10817 inst
.instruction
|= Rm
;
10825 Rd
= inst
.operands
[0].reg
;
10826 Rm
= inst
.operands
[1].reg
;
10828 reject_bad_reg (Rd
);
10829 reject_bad_reg (Rm
);
10831 if (Rd
<= 7 && Rm
<= 7
10832 && inst
.size_req
!= 4)
10834 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10835 inst
.instruction
|= Rd
;
10836 inst
.instruction
|= Rm
<< 3;
10838 else if (unified_syntax
)
10840 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10841 inst
.instruction
|= Rd
<< 8;
10842 inst
.instruction
|= Rm
<< 16;
10843 inst
.instruction
|= Rm
;
10846 inst
.error
= BAD_HIREG
;
10854 Rd
= inst
.operands
[0].reg
;
10855 Rm
= inst
.operands
[1].reg
;
10857 reject_bad_reg (Rd
);
10858 reject_bad_reg (Rm
);
10860 inst
.instruction
|= Rd
<< 8;
10861 inst
.instruction
|= Rm
;
10869 Rd
= inst
.operands
[0].reg
;
10870 Rs
= (inst
.operands
[1].present
10871 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10872 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10874 reject_bad_reg (Rd
);
10875 reject_bad_reg (Rs
);
10876 if (inst
.operands
[2].isreg
)
10877 reject_bad_reg (inst
.operands
[2].reg
);
10879 inst
.instruction
|= Rd
<< 8;
10880 inst
.instruction
|= Rs
<< 16;
10881 if (!inst
.operands
[2].isreg
)
10883 bfd_boolean narrow
;
10885 if ((inst
.instruction
& 0x00100000) != 0)
10886 narrow
= !in_it_block ();
10888 narrow
= in_it_block ();
10890 if (Rd
> 7 || Rs
> 7)
10893 if (inst
.size_req
== 4 || !unified_syntax
)
10896 if (inst
.reloc
.exp
.X_op
!= O_constant
10897 || inst
.reloc
.exp
.X_add_number
!= 0)
10900 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10901 relaxation, but it doesn't seem worth the hassle. */
10904 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10905 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10906 inst
.instruction
|= Rs
<< 3;
10907 inst
.instruction
|= Rd
;
10911 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10912 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10916 encode_thumb32_shifted_operand (2);
10922 set_it_insn_type (OUTSIDE_IT_INSN
);
10923 if (inst
.operands
[0].imm
)
10924 inst
.instruction
|= 0x8;
10930 if (!inst
.operands
[1].present
)
10931 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10933 if (unified_syntax
)
10935 bfd_boolean narrow
;
10938 switch (inst
.instruction
)
10941 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10943 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10945 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10947 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10951 if (THUMB_SETS_FLAGS (inst
.instruction
))
10952 narrow
= !in_it_block ();
10954 narrow
= in_it_block ();
10955 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10957 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10959 if (inst
.operands
[2].isreg
10960 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10961 || inst
.operands
[2].reg
> 7))
10963 if (inst
.size_req
== 4)
10966 reject_bad_reg (inst
.operands
[0].reg
);
10967 reject_bad_reg (inst
.operands
[1].reg
);
10971 if (inst
.operands
[2].isreg
)
10973 reject_bad_reg (inst
.operands
[2].reg
);
10974 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10975 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10976 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10977 inst
.instruction
|= inst
.operands
[2].reg
;
10981 inst
.operands
[1].shifted
= 1;
10982 inst
.operands
[1].shift_kind
= shift_kind
;
10983 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10984 ? T_MNEM_movs
: T_MNEM_mov
);
10985 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10986 encode_thumb32_shifted_operand (1);
10987 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10988 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10993 if (inst
.operands
[2].isreg
)
10995 switch (shift_kind
)
10997 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10998 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10999 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11000 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11004 inst
.instruction
|= inst
.operands
[0].reg
;
11005 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11009 switch (shift_kind
)
11011 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11012 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11013 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11016 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11017 inst
.instruction
|= inst
.operands
[0].reg
;
11018 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11024 constraint (inst
.operands
[0].reg
> 7
11025 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11026 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11028 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11030 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11031 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11032 _("source1 and dest must be same register"));
11034 switch (inst
.instruction
)
11036 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11037 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11038 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11039 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11043 inst
.instruction
|= inst
.operands
[0].reg
;
11044 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11048 switch (inst
.instruction
)
11050 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11051 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11052 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11053 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11056 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11057 inst
.instruction
|= inst
.operands
[0].reg
;
11058 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11066 unsigned Rd
, Rn
, Rm
;
11068 Rd
= inst
.operands
[0].reg
;
11069 Rn
= inst
.operands
[1].reg
;
11070 Rm
= inst
.operands
[2].reg
;
11072 reject_bad_reg (Rd
);
11073 reject_bad_reg (Rn
);
11074 reject_bad_reg (Rm
);
11076 inst
.instruction
|= Rd
<< 8;
11077 inst
.instruction
|= Rn
<< 16;
11078 inst
.instruction
|= Rm
;
11084 unsigned Rd
, Rn
, Rm
;
11086 Rd
= inst
.operands
[0].reg
;
11087 Rm
= inst
.operands
[1].reg
;
11088 Rn
= inst
.operands
[2].reg
;
11090 reject_bad_reg (Rd
);
11091 reject_bad_reg (Rn
);
11092 reject_bad_reg (Rm
);
11094 inst
.instruction
|= Rd
<< 8;
11095 inst
.instruction
|= Rn
<< 16;
11096 inst
.instruction
|= Rm
;
11102 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11103 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11104 _("expression too complex"));
11105 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11106 inst
.instruction
|= (value
& 0xf000) >> 12;
11107 inst
.instruction
|= (value
& 0x0ff0);
11108 inst
.instruction
|= (value
& 0x000f) << 16;
11112 do_t_ssat_usat (int bias
)
11116 Rd
= inst
.operands
[0].reg
;
11117 Rn
= inst
.operands
[2].reg
;
11119 reject_bad_reg (Rd
);
11120 reject_bad_reg (Rn
);
11122 inst
.instruction
|= Rd
<< 8;
11123 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11124 inst
.instruction
|= Rn
<< 16;
11126 if (inst
.operands
[3].present
)
11128 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11130 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11132 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11133 _("expression too complex"));
11135 if (shift_amount
!= 0)
11137 constraint (shift_amount
> 31,
11138 _("shift expression is too large"));
11140 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11141 inst
.instruction
|= 0x00200000; /* sh bit. */
11143 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11144 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11152 do_t_ssat_usat (1);
11160 Rd
= inst
.operands
[0].reg
;
11161 Rn
= inst
.operands
[2].reg
;
11163 reject_bad_reg (Rd
);
11164 reject_bad_reg (Rn
);
11166 inst
.instruction
|= Rd
<< 8;
11167 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11168 inst
.instruction
|= Rn
<< 16;
11174 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11175 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11176 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11177 || inst
.operands
[2].negative
,
11180 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11181 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11182 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11183 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11189 if (!inst
.operands
[2].present
)
11190 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11192 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11193 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11194 || inst
.operands
[0].reg
== inst
.operands
[3].reg
11195 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
11198 inst
.instruction
|= inst
.operands
[0].reg
;
11199 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11200 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11201 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11207 unsigned Rd
, Rn
, Rm
;
11209 Rd
= inst
.operands
[0].reg
;
11210 Rn
= inst
.operands
[1].reg
;
11211 Rm
= inst
.operands
[2].reg
;
11213 reject_bad_reg (Rd
);
11214 reject_bad_reg (Rn
);
11215 reject_bad_reg (Rm
);
11217 inst
.instruction
|= Rd
<< 8;
11218 inst
.instruction
|= Rn
<< 16;
11219 inst
.instruction
|= Rm
;
11220 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11228 Rd
= inst
.operands
[0].reg
;
11229 Rm
= inst
.operands
[1].reg
;
11231 reject_bad_reg (Rd
);
11232 reject_bad_reg (Rm
);
11234 if (inst
.instruction
<= 0xffff
11235 && inst
.size_req
!= 4
11236 && Rd
<= 7 && Rm
<= 7
11237 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11239 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11240 inst
.instruction
|= Rd
;
11241 inst
.instruction
|= Rm
<< 3;
11243 else if (unified_syntax
)
11245 if (inst
.instruction
<= 0xffff)
11246 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11247 inst
.instruction
|= Rd
<< 8;
11248 inst
.instruction
|= Rm
;
11249 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11253 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11254 _("Thumb encoding does not support rotation"));
11255 constraint (1, BAD_HIREG
);
11262 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11271 half
= (inst
.instruction
& 0x10) != 0;
11272 set_it_insn_type_last ();
11273 constraint (inst
.operands
[0].immisreg
,
11274 _("instruction requires register index"));
11276 Rn
= inst
.operands
[0].reg
;
11277 Rm
= inst
.operands
[0].imm
;
11279 constraint (Rn
== REG_SP
, BAD_SP
);
11280 reject_bad_reg (Rm
);
11282 constraint (!half
&& inst
.operands
[0].shifted
,
11283 _("instruction does not allow shifted index"));
11284 inst
.instruction
|= (Rn
<< 16) | Rm
;
11290 do_t_ssat_usat (0);
11298 Rd
= inst
.operands
[0].reg
;
11299 Rn
= inst
.operands
[2].reg
;
11301 reject_bad_reg (Rd
);
11302 reject_bad_reg (Rn
);
11304 inst
.instruction
|= Rd
<< 8;
11305 inst
.instruction
|= inst
.operands
[1].imm
;
11306 inst
.instruction
|= Rn
<< 16;
11309 /* Neon instruction encoder helpers. */
11311 /* Encodings for the different types for various Neon opcodes. */
11313 /* An "invalid" code for the following tables. */
11316 struct neon_tab_entry
11319 unsigned float_or_poly
;
11320 unsigned scalar_or_imm
;
11323 /* Map overloaded Neon opcodes to their respective encodings. */
11324 #define NEON_ENC_TAB \
11325 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11326 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11327 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11328 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11329 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11330 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11331 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11332 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11333 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11334 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11335 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11336 /* Register variants of the following two instructions are encoded as
11337 vcge / vcgt with the operands reversed. */ \
11338 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11339 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11340 X(vfma, N_INV, 0x0000c10, N_INV), \
11341 X(vfms, N_INV, 0x0200c10, N_INV), \
11342 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11343 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11344 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11345 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11346 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11347 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11348 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11349 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11350 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11351 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11352 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11353 X(vshl, 0x0000400, N_INV, 0x0800510), \
11354 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11355 X(vand, 0x0000110, N_INV, 0x0800030), \
11356 X(vbic, 0x0100110, N_INV, 0x0800030), \
11357 X(veor, 0x1000110, N_INV, N_INV), \
11358 X(vorn, 0x0300110, N_INV, 0x0800010), \
11359 X(vorr, 0x0200110, N_INV, 0x0800010), \
11360 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11361 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11362 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11363 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11364 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11365 X(vst1, 0x0000000, 0x0800000, N_INV), \
11366 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11367 X(vst2, 0x0000100, 0x0800100, N_INV), \
11368 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11369 X(vst3, 0x0000200, 0x0800200, N_INV), \
11370 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11371 X(vst4, 0x0000300, 0x0800300, N_INV), \
11372 X(vmovn, 0x1b20200, N_INV, N_INV), \
11373 X(vtrn, 0x1b20080, N_INV, N_INV), \
11374 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11375 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11376 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11377 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11378 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11379 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11380 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11381 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11382 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11383 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11384 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11388 #define X(OPC,I,F,S) N_MNEM_##OPC
11393 static const struct neon_tab_entry neon_enc_tab
[] =
11395 #define X(OPC,I,F,S) { (I), (F), (S) }
11400 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11401 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11402 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11403 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11404 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11405 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11406 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11407 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11408 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11409 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11410 #define NEON_ENC_SINGLE_(X) \
11411 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11412 #define NEON_ENC_DOUBLE_(X) \
11413 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11415 #define NEON_ENCODE(type, inst) \
11418 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11419 inst.is_neon = 1; \
11423 #define check_neon_suffixes \
11426 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11428 as_bad (_("invalid neon suffix for non neon instruction")); \
11434 /* Define shapes for instruction operands. The following mnemonic characters
11435 are used in this table:
11437 F - VFP S<n> register
11438 D - Neon D<n> register
11439 Q - Neon Q<n> register
11443 L - D<n> register list
11445 This table is used to generate various data:
11446 - enumerations of the form NS_DDR to be used as arguments to
11448 - a table classifying shapes into single, double, quad, mixed.
11449 - a table used to drive neon_select_shape. */
11451 #define NEON_SHAPE_DEF \
11452 X(3, (D, D, D), DOUBLE), \
11453 X(3, (Q, Q, Q), QUAD), \
11454 X(3, (D, D, I), DOUBLE), \
11455 X(3, (Q, Q, I), QUAD), \
11456 X(3, (D, D, S), DOUBLE), \
11457 X(3, (Q, Q, S), QUAD), \
11458 X(2, (D, D), DOUBLE), \
11459 X(2, (Q, Q), QUAD), \
11460 X(2, (D, S), DOUBLE), \
11461 X(2, (Q, S), QUAD), \
11462 X(2, (D, R), DOUBLE), \
11463 X(2, (Q, R), QUAD), \
11464 X(2, (D, I), DOUBLE), \
11465 X(2, (Q, I), QUAD), \
11466 X(3, (D, L, D), DOUBLE), \
11467 X(2, (D, Q), MIXED), \
11468 X(2, (Q, D), MIXED), \
11469 X(3, (D, Q, I), MIXED), \
11470 X(3, (Q, D, I), MIXED), \
11471 X(3, (Q, D, D), MIXED), \
11472 X(3, (D, Q, Q), MIXED), \
11473 X(3, (Q, Q, D), MIXED), \
11474 X(3, (Q, D, S), MIXED), \
11475 X(3, (D, Q, S), MIXED), \
11476 X(4, (D, D, D, I), DOUBLE), \
11477 X(4, (Q, Q, Q, I), QUAD), \
11478 X(2, (F, F), SINGLE), \
11479 X(3, (F, F, F), SINGLE), \
11480 X(2, (F, I), SINGLE), \
11481 X(2, (F, D), MIXED), \
11482 X(2, (D, F), MIXED), \
11483 X(3, (F, F, I), MIXED), \
11484 X(4, (R, R, F, F), SINGLE), \
11485 X(4, (F, F, R, R), SINGLE), \
11486 X(3, (D, R, R), DOUBLE), \
11487 X(3, (R, R, D), DOUBLE), \
11488 X(2, (S, R), SINGLE), \
11489 X(2, (R, S), SINGLE), \
11490 X(2, (F, R), SINGLE), \
11491 X(2, (R, F), SINGLE)
11493 #define S2(A,B) NS_##A##B
11494 #define S3(A,B,C) NS_##A##B##C
11495 #define S4(A,B,C,D) NS_##A##B##C##D
11497 #define X(N, L, C) S##N L
11510 enum neon_shape_class
11518 #define X(N, L, C) SC_##C
11520 static enum neon_shape_class neon_shape_class
[] =
11538 /* Register widths of above. */
11539 static unsigned neon_shape_el_size
[] =
11550 struct neon_shape_info
11553 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11556 #define S2(A,B) { SE_##A, SE_##B }
11557 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11558 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11560 #define X(N, L, C) { N, S##N L }
11562 static struct neon_shape_info neon_shape_tab
[] =
11572 /* Bit masks used in type checking given instructions.
11573 'N_EQK' means the type must be the same as (or based on in some way) the key
11574 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11575 set, various other bits can be set as well in order to modify the meaning of
11576 the type constraint. */
11578 enum neon_type_mask
11601 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11602 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11603 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11604 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11605 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11606 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11607 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11608 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11609 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11610 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11612 N_MAX_NONSPECIAL
= N_F64
11615 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11617 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11618 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11619 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11620 #define N_SUF_32 (N_SU_32 | N_F32)
11621 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11622 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11624 /* Pass this as the first type argument to neon_check_type to ignore types
11626 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11628 /* Select a "shape" for the current instruction (describing register types or
11629 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11630 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11631 function of operand parsing, so this function doesn't need to be called.
11632 Shapes should be listed in order of decreasing length. */
11634 static enum neon_shape
11635 neon_select_shape (enum neon_shape shape
, ...)
11638 enum neon_shape first_shape
= shape
;
11640 /* Fix missing optional operands. FIXME: we don't know at this point how
11641 many arguments we should have, so this makes the assumption that we have
11642 > 1. This is true of all current Neon opcodes, I think, but may not be
11643 true in the future. */
11644 if (!inst
.operands
[1].present
)
11645 inst
.operands
[1] = inst
.operands
[0];
11647 va_start (ap
, shape
);
11649 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11654 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11656 if (!inst
.operands
[j
].present
)
11662 switch (neon_shape_tab
[shape
].el
[j
])
11665 if (!(inst
.operands
[j
].isreg
11666 && inst
.operands
[j
].isvec
11667 && inst
.operands
[j
].issingle
11668 && !inst
.operands
[j
].isquad
))
11673 if (!(inst
.operands
[j
].isreg
11674 && inst
.operands
[j
].isvec
11675 && !inst
.operands
[j
].isquad
11676 && !inst
.operands
[j
].issingle
))
11681 if (!(inst
.operands
[j
].isreg
11682 && !inst
.operands
[j
].isvec
))
11687 if (!(inst
.operands
[j
].isreg
11688 && inst
.operands
[j
].isvec
11689 && inst
.operands
[j
].isquad
11690 && !inst
.operands
[j
].issingle
))
11695 if (!(!inst
.operands
[j
].isreg
11696 && !inst
.operands
[j
].isscalar
))
11701 if (!(!inst
.operands
[j
].isreg
11702 && inst
.operands
[j
].isscalar
))
11716 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11717 first_error (_("invalid instruction shape"));
11722 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11723 means the Q bit should be set). */
11726 neon_quad (enum neon_shape shape
)
11728 return neon_shape_class
[shape
] == SC_QUAD
;
11732 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11735 /* Allow modification to be made to types which are constrained to be
11736 based on the key element, based on bits set alongside N_EQK. */
11737 if ((typebits
& N_EQK
) != 0)
11739 if ((typebits
& N_HLF
) != 0)
11741 else if ((typebits
& N_DBL
) != 0)
11743 if ((typebits
& N_SGN
) != 0)
11744 *g_type
= NT_signed
;
11745 else if ((typebits
& N_UNS
) != 0)
11746 *g_type
= NT_unsigned
;
11747 else if ((typebits
& N_INT
) != 0)
11748 *g_type
= NT_integer
;
11749 else if ((typebits
& N_FLT
) != 0)
11750 *g_type
= NT_float
;
11751 else if ((typebits
& N_SIZ
) != 0)
11752 *g_type
= NT_untyped
;
11756 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11757 operand type, i.e. the single type specified in a Neon instruction when it
11758 is the only one given. */
11760 static struct neon_type_el
11761 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11763 struct neon_type_el dest
= *key
;
11765 gas_assert ((thisarg
& N_EQK
) != 0);
11767 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11772 /* Convert Neon type and size into compact bitmask representation. */
11774 static enum neon_type_mask
11775 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11782 case 8: return N_8
;
11783 case 16: return N_16
;
11784 case 32: return N_32
;
11785 case 64: return N_64
;
11793 case 8: return N_I8
;
11794 case 16: return N_I16
;
11795 case 32: return N_I32
;
11796 case 64: return N_I64
;
11804 case 16: return N_F16
;
11805 case 32: return N_F32
;
11806 case 64: return N_F64
;
11814 case 8: return N_P8
;
11815 case 16: return N_P16
;
11823 case 8: return N_S8
;
11824 case 16: return N_S16
;
11825 case 32: return N_S32
;
11826 case 64: return N_S64
;
11834 case 8: return N_U8
;
11835 case 16: return N_U16
;
11836 case 32: return N_U32
;
11837 case 64: return N_U64
;
11848 /* Convert compact Neon bitmask type representation to a type and size. Only
11849 handles the case where a single bit is set in the mask. */
11852 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11853 enum neon_type_mask mask
)
11855 if ((mask
& N_EQK
) != 0)
11858 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11860 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11862 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11864 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11869 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11871 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11872 *type
= NT_unsigned
;
11873 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11874 *type
= NT_integer
;
11875 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11876 *type
= NT_untyped
;
11877 else if ((mask
& (N_P8
| N_P16
)) != 0)
11879 else if ((mask
& (N_F32
| N_F64
)) != 0)
11887 /* Modify a bitmask of allowed types. This is only needed for type
11891 modify_types_allowed (unsigned allowed
, unsigned mods
)
11894 enum neon_el_type type
;
11900 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11902 if (el_type_of_type_chk (&type
, &size
,
11903 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
11905 neon_modify_type_size (mods
, &type
, &size
);
11906 destmask
|= type_chk_of_el_type (type
, size
);
11913 /* Check type and return type classification.
11914 The manual states (paraphrase): If one datatype is given, it indicates the
11916 - the second operand, if there is one
11917 - the operand, if there is no second operand
11918 - the result, if there are no operands.
11919 This isn't quite good enough though, so we use a concept of a "key" datatype
11920 which is set on a per-instruction basis, which is the one which matters when
11921 only one data type is written.
11922 Note: this function has side-effects (e.g. filling in missing operands). All
11923 Neon instructions should call it before performing bit encoding. */
11925 static struct neon_type_el
11926 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11929 unsigned i
, pass
, key_el
= 0;
11930 unsigned types
[NEON_MAX_TYPE_ELS
];
11931 enum neon_el_type k_type
= NT_invtype
;
11932 unsigned k_size
= -1u;
11933 struct neon_type_el badtype
= {NT_invtype
, -1};
11934 unsigned key_allowed
= 0;
11936 /* Optional registers in Neon instructions are always (not) in operand 1.
11937 Fill in the missing operand here, if it was omitted. */
11938 if (els
> 1 && !inst
.operands
[1].present
)
11939 inst
.operands
[1] = inst
.operands
[0];
11941 /* Suck up all the varargs. */
11943 for (i
= 0; i
< els
; i
++)
11945 unsigned thisarg
= va_arg (ap
, unsigned);
11946 if (thisarg
== N_IGNORE_TYPE
)
11951 types
[i
] = thisarg
;
11952 if ((thisarg
& N_KEY
) != 0)
11957 if (inst
.vectype
.elems
> 0)
11958 for (i
= 0; i
< els
; i
++)
11959 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11961 first_error (_("types specified in both the mnemonic and operands"));
11965 /* Duplicate inst.vectype elements here as necessary.
11966 FIXME: No idea if this is exactly the same as the ARM assembler,
11967 particularly when an insn takes one register and one non-register
11969 if (inst
.vectype
.elems
== 1 && els
> 1)
11972 inst
.vectype
.elems
= els
;
11973 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11974 for (j
= 0; j
< els
; j
++)
11976 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11979 else if (inst
.vectype
.elems
== 0 && els
> 0)
11982 /* No types were given after the mnemonic, so look for types specified
11983 after each operand. We allow some flexibility here; as long as the
11984 "key" operand has a type, we can infer the others. */
11985 for (j
= 0; j
< els
; j
++)
11986 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11987 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11989 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11991 for (j
= 0; j
< els
; j
++)
11992 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11993 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11998 first_error (_("operand types can't be inferred"));
12002 else if (inst
.vectype
.elems
!= els
)
12004 first_error (_("type specifier has the wrong number of parts"));
12008 for (pass
= 0; pass
< 2; pass
++)
12010 for (i
= 0; i
< els
; i
++)
12012 unsigned thisarg
= types
[i
];
12013 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12014 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12015 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12016 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12018 /* Decay more-specific signed & unsigned types to sign-insensitive
12019 integer types if sign-specific variants are unavailable. */
12020 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12021 && (types_allowed
& N_SU_ALL
) == 0)
12022 g_type
= NT_integer
;
12024 /* If only untyped args are allowed, decay any more specific types to
12025 them. Some instructions only care about signs for some element
12026 sizes, so handle that properly. */
12027 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12028 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12029 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12030 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12031 g_type
= NT_untyped
;
12035 if ((thisarg
& N_KEY
) != 0)
12039 key_allowed
= thisarg
& ~N_KEY
;
12044 if ((thisarg
& N_VFP
) != 0)
12046 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
12047 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
12049 /* In VFP mode, operands must match register widths. If we
12050 have a key operand, use its width, else use the width of
12051 the current operand. */
12057 if (regwidth
!= match
)
12059 first_error (_("operand size must match register width"));
12064 if ((thisarg
& N_EQK
) == 0)
12066 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12068 if ((given_type
& types_allowed
) == 0)
12070 first_error (_("bad type in Neon instruction"));
12076 enum neon_el_type mod_k_type
= k_type
;
12077 unsigned mod_k_size
= k_size
;
12078 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12079 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12081 first_error (_("inconsistent types in Neon instruction"));
12089 return inst
.vectype
.el
[key_el
];
12092 /* Neon-style VFP instruction forwarding. */
12094 /* Thumb VFP instructions have 0xE in the condition field. */
12097 do_vfp_cond_or_thumb (void)
12102 inst
.instruction
|= 0xe0000000;
12104 inst
.instruction
|= inst
.cond
<< 28;
12107 /* Look up and encode a simple mnemonic, for use as a helper function for the
12108 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12109 etc. It is assumed that operand parsing has already been done, and that the
12110 operands are in the form expected by the given opcode (this isn't necessarily
12111 the same as the form in which they were parsed, hence some massaging must
12112 take place before this function is called).
12113 Checks current arch version against that in the looked-up opcode. */
12116 do_vfp_nsyn_opcode (const char *opname
)
12118 const struct asm_opcode
*opcode
;
12120 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12125 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12126 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12133 inst
.instruction
= opcode
->tvalue
;
12134 opcode
->tencode ();
12138 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12139 opcode
->aencode ();
12144 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12146 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12151 do_vfp_nsyn_opcode ("fadds");
12153 do_vfp_nsyn_opcode ("fsubs");
12158 do_vfp_nsyn_opcode ("faddd");
12160 do_vfp_nsyn_opcode ("fsubd");
12164 /* Check operand types to see if this is a VFP instruction, and if so call
12168 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12170 enum neon_shape rs
;
12171 struct neon_type_el et
;
12176 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12177 et
= neon_check_type (2, rs
,
12178 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12182 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12183 et
= neon_check_type (3, rs
,
12184 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12191 if (et
.type
!= NT_invtype
)
12203 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12205 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12210 do_vfp_nsyn_opcode ("fmacs");
12212 do_vfp_nsyn_opcode ("fnmacs");
12217 do_vfp_nsyn_opcode ("fmacd");
12219 do_vfp_nsyn_opcode ("fnmacd");
12224 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12226 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12231 do_vfp_nsyn_opcode ("ffmas");
12233 do_vfp_nsyn_opcode ("ffnmas");
12238 do_vfp_nsyn_opcode ("ffmad");
12240 do_vfp_nsyn_opcode ("ffnmad");
12245 do_vfp_nsyn_mul (enum neon_shape rs
)
12248 do_vfp_nsyn_opcode ("fmuls");
12250 do_vfp_nsyn_opcode ("fmuld");
12254 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12256 int is_neg
= (inst
.instruction
& 0x80) != 0;
12257 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12262 do_vfp_nsyn_opcode ("fnegs");
12264 do_vfp_nsyn_opcode ("fabss");
12269 do_vfp_nsyn_opcode ("fnegd");
12271 do_vfp_nsyn_opcode ("fabsd");
12275 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12276 insns belong to Neon, and are handled elsewhere. */
12279 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12281 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12285 do_vfp_nsyn_opcode ("fldmdbs");
12287 do_vfp_nsyn_opcode ("fldmias");
12292 do_vfp_nsyn_opcode ("fstmdbs");
12294 do_vfp_nsyn_opcode ("fstmias");
12299 do_vfp_nsyn_sqrt (void)
12301 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12302 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12305 do_vfp_nsyn_opcode ("fsqrts");
12307 do_vfp_nsyn_opcode ("fsqrtd");
12311 do_vfp_nsyn_div (void)
12313 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12314 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12315 N_F32
| N_F64
| N_KEY
| N_VFP
);
12318 do_vfp_nsyn_opcode ("fdivs");
12320 do_vfp_nsyn_opcode ("fdivd");
12324 do_vfp_nsyn_nmul (void)
12326 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12327 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12328 N_F32
| N_F64
| N_KEY
| N_VFP
);
12332 NEON_ENCODE (SINGLE
, inst
);
12333 do_vfp_sp_dyadic ();
12337 NEON_ENCODE (DOUBLE
, inst
);
12338 do_vfp_dp_rd_rn_rm ();
12340 do_vfp_cond_or_thumb ();
12344 do_vfp_nsyn_cmp (void)
12346 if (inst
.operands
[1].isreg
)
12348 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12349 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12353 NEON_ENCODE (SINGLE
, inst
);
12354 do_vfp_sp_monadic ();
12358 NEON_ENCODE (DOUBLE
, inst
);
12359 do_vfp_dp_rd_rm ();
12364 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12365 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12367 switch (inst
.instruction
& 0x0fffffff)
12370 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12373 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12381 NEON_ENCODE (SINGLE
, inst
);
12382 do_vfp_sp_compare_z ();
12386 NEON_ENCODE (DOUBLE
, inst
);
12390 do_vfp_cond_or_thumb ();
12394 nsyn_insert_sp (void)
12396 inst
.operands
[1] = inst
.operands
[0];
12397 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12398 inst
.operands
[0].reg
= REG_SP
;
12399 inst
.operands
[0].isreg
= 1;
12400 inst
.operands
[0].writeback
= 1;
12401 inst
.operands
[0].present
= 1;
12405 do_vfp_nsyn_push (void)
12408 if (inst
.operands
[1].issingle
)
12409 do_vfp_nsyn_opcode ("fstmdbs");
12411 do_vfp_nsyn_opcode ("fstmdbd");
12415 do_vfp_nsyn_pop (void)
12418 if (inst
.operands
[1].issingle
)
12419 do_vfp_nsyn_opcode ("fldmias");
12421 do_vfp_nsyn_opcode ("fldmiad");
12424 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12425 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12428 neon_dp_fixup (struct arm_it
* insn
)
12430 unsigned int i
= insn
->instruction
;
12435 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12446 insn
->instruction
= i
;
12449 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12453 neon_logbits (unsigned x
)
12455 return ffs (x
) - 4;
12458 #define LOW4(R) ((R) & 0xf)
12459 #define HI1(R) (((R) >> 4) & 1)
12461 /* Encode insns with bit pattern:
12463 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12464 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12466 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12467 different meaning for some instruction. */
12470 neon_three_same (int isquad
, int ubit
, int size
)
12472 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12473 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12474 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12475 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12476 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12477 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12478 inst
.instruction
|= (isquad
!= 0) << 6;
12479 inst
.instruction
|= (ubit
!= 0) << 24;
12481 inst
.instruction
|= neon_logbits (size
) << 20;
12483 neon_dp_fixup (&inst
);
12486 /* Encode instructions of the form:
12488 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12489 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12491 Don't write size if SIZE == -1. */
12494 neon_two_same (int qbit
, int ubit
, int size
)
12496 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12497 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12498 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12499 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12500 inst
.instruction
|= (qbit
!= 0) << 6;
12501 inst
.instruction
|= (ubit
!= 0) << 24;
12504 inst
.instruction
|= neon_logbits (size
) << 18;
12506 neon_dp_fixup (&inst
);
12509 /* Neon instruction encoders, in approximate order of appearance. */
12512 do_neon_dyadic_i_su (void)
12514 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12515 struct neon_type_el et
= neon_check_type (3, rs
,
12516 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12517 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12521 do_neon_dyadic_i64_su (void)
12523 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12524 struct neon_type_el et
= neon_check_type (3, rs
,
12525 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12526 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12530 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12533 unsigned size
= et
.size
>> 3;
12534 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12535 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12536 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12537 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12538 inst
.instruction
|= (isquad
!= 0) << 6;
12539 inst
.instruction
|= immbits
<< 16;
12540 inst
.instruction
|= (size
>> 3) << 7;
12541 inst
.instruction
|= (size
& 0x7) << 19;
12543 inst
.instruction
|= (uval
!= 0) << 24;
12545 neon_dp_fixup (&inst
);
12549 do_neon_shl_imm (void)
12551 if (!inst
.operands
[2].isreg
)
12553 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12554 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12555 NEON_ENCODE (IMMED
, inst
);
12556 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12560 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12561 struct neon_type_el et
= neon_check_type (3, rs
,
12562 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12565 /* VSHL/VQSHL 3-register variants have syntax such as:
12567 whereas other 3-register operations encoded by neon_three_same have
12570 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12572 tmp
= inst
.operands
[2].reg
;
12573 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12574 inst
.operands
[1].reg
= tmp
;
12575 NEON_ENCODE (INTEGER
, inst
);
12576 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12581 do_neon_qshl_imm (void)
12583 if (!inst
.operands
[2].isreg
)
12585 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12586 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12588 NEON_ENCODE (IMMED
, inst
);
12589 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12590 inst
.operands
[2].imm
);
12594 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12595 struct neon_type_el et
= neon_check_type (3, rs
,
12596 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12599 /* See note in do_neon_shl_imm. */
12600 tmp
= inst
.operands
[2].reg
;
12601 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12602 inst
.operands
[1].reg
= tmp
;
12603 NEON_ENCODE (INTEGER
, inst
);
12604 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12609 do_neon_rshl (void)
12611 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12612 struct neon_type_el et
= neon_check_type (3, rs
,
12613 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12616 tmp
= inst
.operands
[2].reg
;
12617 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12618 inst
.operands
[1].reg
= tmp
;
12619 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12623 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12625 /* Handle .I8 pseudo-instructions. */
12628 /* Unfortunately, this will make everything apart from zero out-of-range.
12629 FIXME is this the intended semantics? There doesn't seem much point in
12630 accepting .I8 if so. */
12631 immediate
|= immediate
<< 8;
12637 if (immediate
== (immediate
& 0x000000ff))
12639 *immbits
= immediate
;
12642 else if (immediate
== (immediate
& 0x0000ff00))
12644 *immbits
= immediate
>> 8;
12647 else if (immediate
== (immediate
& 0x00ff0000))
12649 *immbits
= immediate
>> 16;
12652 else if (immediate
== (immediate
& 0xff000000))
12654 *immbits
= immediate
>> 24;
12657 if ((immediate
& 0xffff) != (immediate
>> 16))
12658 goto bad_immediate
;
12659 immediate
&= 0xffff;
12662 if (immediate
== (immediate
& 0x000000ff))
12664 *immbits
= immediate
;
12667 else if (immediate
== (immediate
& 0x0000ff00))
12669 *immbits
= immediate
>> 8;
12674 first_error (_("immediate value out of range"));
12678 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12682 neon_bits_same_in_bytes (unsigned imm
)
12684 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12685 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12686 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12687 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12690 /* For immediate of above form, return 0bABCD. */
12693 neon_squash_bits (unsigned imm
)
12695 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12696 | ((imm
& 0x01000000) >> 21);
12699 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12702 neon_qfloat_bits (unsigned imm
)
12704 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12707 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12708 the instruction. *OP is passed as the initial value of the op field, and
12709 may be set to a different value depending on the constant (i.e.
12710 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12711 MVN). If the immediate looks like a repeated pattern then also
12712 try smaller element sizes. */
12715 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12716 unsigned *immbits
, int *op
, int size
,
12717 enum neon_el_type type
)
12719 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12721 if (type
== NT_float
&& !float_p
)
12724 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12726 if (size
!= 32 || *op
== 1)
12728 *immbits
= neon_qfloat_bits (immlo
);
12734 if (neon_bits_same_in_bytes (immhi
)
12735 && neon_bits_same_in_bytes (immlo
))
12739 *immbits
= (neon_squash_bits (immhi
) << 4)
12740 | neon_squash_bits (immlo
);
12745 if (immhi
!= immlo
)
12751 if (immlo
== (immlo
& 0x000000ff))
12756 else if (immlo
== (immlo
& 0x0000ff00))
12758 *immbits
= immlo
>> 8;
12761 else if (immlo
== (immlo
& 0x00ff0000))
12763 *immbits
= immlo
>> 16;
12766 else if (immlo
== (immlo
& 0xff000000))
12768 *immbits
= immlo
>> 24;
12771 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12773 *immbits
= (immlo
>> 8) & 0xff;
12776 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12778 *immbits
= (immlo
>> 16) & 0xff;
12782 if ((immlo
& 0xffff) != (immlo
>> 16))
12789 if (immlo
== (immlo
& 0x000000ff))
12794 else if (immlo
== (immlo
& 0x0000ff00))
12796 *immbits
= immlo
>> 8;
12800 if ((immlo
& 0xff) != (immlo
>> 8))
12805 if (immlo
== (immlo
& 0x000000ff))
12807 /* Don't allow MVN with 8-bit immediate. */
12817 /* Write immediate bits [7:0] to the following locations:
12819 |28/24|23 19|18 16|15 4|3 0|
12820 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12822 This function is used by VMOV/VMVN/VORR/VBIC. */
12825 neon_write_immbits (unsigned immbits
)
12827 inst
.instruction
|= immbits
& 0xf;
12828 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12829 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12832 /* Invert low-order SIZE bits of XHI:XLO. */
12835 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12837 unsigned immlo
= xlo
? *xlo
: 0;
12838 unsigned immhi
= xhi
? *xhi
: 0;
12843 immlo
= (~immlo
) & 0xff;
12847 immlo
= (~immlo
) & 0xffff;
12851 immhi
= (~immhi
) & 0xffffffff;
12852 /* fall through. */
12855 immlo
= (~immlo
) & 0xffffffff;
12870 do_neon_logic (void)
12872 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12874 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12875 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12876 /* U bit and size field were set as part of the bitmask. */
12877 NEON_ENCODE (INTEGER
, inst
);
12878 neon_three_same (neon_quad (rs
), 0, -1);
12882 const int three_ops_form
= (inst
.operands
[2].present
12883 && !inst
.operands
[2].isreg
);
12884 const int immoperand
= (three_ops_form
? 2 : 1);
12885 enum neon_shape rs
= (three_ops_form
12886 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
12887 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
12888 struct neon_type_el et
= neon_check_type (2, rs
,
12889 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12890 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
12894 if (et
.type
== NT_invtype
)
12897 if (three_ops_form
)
12898 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12899 _("first and second operands shall be the same register"));
12901 NEON_ENCODE (IMMED
, inst
);
12903 immbits
= inst
.operands
[immoperand
].imm
;
12906 /* .i64 is a pseudo-op, so the immediate must be a repeating
12908 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
12909 inst
.operands
[immoperand
].reg
: 0))
12911 /* Set immbits to an invalid constant. */
12912 immbits
= 0xdeadbeef;
12919 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12923 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12927 /* Pseudo-instruction for VBIC. */
12928 neon_invert_size (&immbits
, 0, et
.size
);
12929 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12933 /* Pseudo-instruction for VORR. */
12934 neon_invert_size (&immbits
, 0, et
.size
);
12935 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12945 inst
.instruction
|= neon_quad (rs
) << 6;
12946 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12947 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12948 inst
.instruction
|= cmode
<< 8;
12949 neon_write_immbits (immbits
);
12951 neon_dp_fixup (&inst
);
12956 do_neon_bitfield (void)
12958 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12959 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12960 neon_three_same (neon_quad (rs
), 0, -1);
12964 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12967 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12968 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12970 if (et
.type
== NT_float
)
12972 NEON_ENCODE (FLOAT
, inst
);
12973 neon_three_same (neon_quad (rs
), 0, -1);
12977 NEON_ENCODE (INTEGER
, inst
);
12978 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12983 do_neon_dyadic_if_su (void)
12985 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12989 do_neon_dyadic_if_su_d (void)
12991 /* This version only allow D registers, but that constraint is enforced during
12992 operand parsing so we don't need to do anything extra here. */
12993 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12997 do_neon_dyadic_if_i_d (void)
12999 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13000 affected if we specify unsigned args. */
13001 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13004 enum vfp_or_neon_is_neon_bits
13007 NEON_CHECK_ARCH
= 2
13010 /* Call this function if an instruction which may have belonged to the VFP or
13011 Neon instruction sets, but turned out to be a Neon instruction (due to the
13012 operand types involved, etc.). We have to check and/or fix-up a couple of
13015 - Make sure the user hasn't attempted to make a Neon instruction
13017 - Alter the value in the condition code field if necessary.
13018 - Make sure that the arch supports Neon instructions.
13020 Which of these operations take place depends on bits from enum
13021 vfp_or_neon_is_neon_bits.
13023 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13024 current instruction's condition is COND_ALWAYS, the condition field is
13025 changed to inst.uncond_value. This is necessary because instructions shared
13026 between VFP and Neon may be conditional for the VFP variants only, and the
13027 unconditional Neon version must have, e.g., 0xF in the condition field. */
13030 vfp_or_neon_is_neon (unsigned check
)
13032 /* Conditions are always legal in Thumb mode (IT blocks). */
13033 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13035 if (inst
.cond
!= COND_ALWAYS
)
13037 first_error (_(BAD_COND
));
13040 if (inst
.uncond_value
!= -1)
13041 inst
.instruction
|= inst
.uncond_value
<< 28;
13044 if ((check
& NEON_CHECK_ARCH
)
13045 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13047 first_error (_(BAD_FPU
));
13055 do_neon_addsub_if_i (void)
13057 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13060 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13063 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13064 affected if we specify unsigned args. */
13065 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13068 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13070 V<op> A,B (A is operand 0, B is operand 2)
13075 so handle that case specially. */
13078 neon_exchange_operands (void)
13080 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13081 if (inst
.operands
[1].present
)
13083 /* Swap operands[1] and operands[2]. */
13084 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13085 inst
.operands
[1] = inst
.operands
[2];
13086 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13090 inst
.operands
[1] = inst
.operands
[2];
13091 inst
.operands
[2] = inst
.operands
[0];
13096 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13098 if (inst
.operands
[2].isreg
)
13101 neon_exchange_operands ();
13102 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13106 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13107 struct neon_type_el et
= neon_check_type (2, rs
,
13108 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13110 NEON_ENCODE (IMMED
, inst
);
13111 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13112 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13113 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13114 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13115 inst
.instruction
|= neon_quad (rs
) << 6;
13116 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13117 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13119 neon_dp_fixup (&inst
);
13126 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13130 do_neon_cmp_inv (void)
13132 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13138 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13141 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13142 scalars, which are encoded in 5 bits, M : Rm.
13143 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13144 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13148 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13150 unsigned regno
= NEON_SCALAR_REG (scalar
);
13151 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13156 if (regno
> 7 || elno
> 3)
13158 return regno
| (elno
<< 3);
13161 if (regno
> 15 || elno
> 1)
13163 return regno
| (elno
<< 4);
13167 first_error (_("scalar out of range for multiply instruction"));
13173 /* Encode multiply / multiply-accumulate scalar instructions. */
13176 neon_mul_mac (struct neon_type_el et
, int ubit
)
13180 /* Give a more helpful error message if we have an invalid type. */
13181 if (et
.type
== NT_invtype
)
13184 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13185 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13186 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13187 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13188 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13189 inst
.instruction
|= LOW4 (scalar
);
13190 inst
.instruction
|= HI1 (scalar
) << 5;
13191 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13192 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13193 inst
.instruction
|= (ubit
!= 0) << 24;
13195 neon_dp_fixup (&inst
);
13199 do_neon_mac_maybe_scalar (void)
13201 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13204 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13207 if (inst
.operands
[2].isscalar
)
13209 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13210 struct neon_type_el et
= neon_check_type (3, rs
,
13211 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13212 NEON_ENCODE (SCALAR
, inst
);
13213 neon_mul_mac (et
, neon_quad (rs
));
13217 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13218 affected if we specify unsigned args. */
13219 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13224 do_neon_fmac (void)
13226 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13229 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13232 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13238 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13239 struct neon_type_el et
= neon_check_type (3, rs
,
13240 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13241 neon_three_same (neon_quad (rs
), 0, et
.size
);
13244 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13245 same types as the MAC equivalents. The polynomial type for this instruction
13246 is encoded the same as the integer type. */
13251 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13254 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13257 if (inst
.operands
[2].isscalar
)
13258 do_neon_mac_maybe_scalar ();
13260 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13264 do_neon_qdmulh (void)
13266 if (inst
.operands
[2].isscalar
)
13268 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13269 struct neon_type_el et
= neon_check_type (3, rs
,
13270 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13271 NEON_ENCODE (SCALAR
, inst
);
13272 neon_mul_mac (et
, neon_quad (rs
));
13276 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13277 struct neon_type_el et
= neon_check_type (3, rs
,
13278 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13279 NEON_ENCODE (INTEGER
, inst
);
13280 /* The U bit (rounding) comes from bit mask. */
13281 neon_three_same (neon_quad (rs
), 0, et
.size
);
13286 do_neon_fcmp_absolute (void)
13288 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13289 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13290 /* Size field comes from bit mask. */
13291 neon_three_same (neon_quad (rs
), 1, -1);
13295 do_neon_fcmp_absolute_inv (void)
13297 neon_exchange_operands ();
13298 do_neon_fcmp_absolute ();
13302 do_neon_step (void)
13304 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13305 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13306 neon_three_same (neon_quad (rs
), 0, -1);
13310 do_neon_abs_neg (void)
13312 enum neon_shape rs
;
13313 struct neon_type_el et
;
13315 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13318 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13321 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13322 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13324 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13325 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13326 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13327 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13328 inst
.instruction
|= neon_quad (rs
) << 6;
13329 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13330 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13332 neon_dp_fixup (&inst
);
13338 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13339 struct neon_type_el et
= neon_check_type (2, rs
,
13340 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13341 int imm
= inst
.operands
[2].imm
;
13342 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13343 _("immediate out of range for insert"));
13344 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13350 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13351 struct neon_type_el et
= neon_check_type (2, rs
,
13352 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13353 int imm
= inst
.operands
[2].imm
;
13354 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13355 _("immediate out of range for insert"));
13356 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13360 do_neon_qshlu_imm (void)
13362 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13363 struct neon_type_el et
= neon_check_type (2, rs
,
13364 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13365 int imm
= inst
.operands
[2].imm
;
13366 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13367 _("immediate out of range for shift"));
13368 /* Only encodes the 'U present' variant of the instruction.
13369 In this case, signed types have OP (bit 8) set to 0.
13370 Unsigned types have OP set to 1. */
13371 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13372 /* The rest of the bits are the same as other immediate shifts. */
13373 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13377 do_neon_qmovn (void)
13379 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13380 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13381 /* Saturating move where operands can be signed or unsigned, and the
13382 destination has the same signedness. */
13383 NEON_ENCODE (INTEGER
, inst
);
13384 if (et
.type
== NT_unsigned
)
13385 inst
.instruction
|= 0xc0;
13387 inst
.instruction
|= 0x80;
13388 neon_two_same (0, 1, et
.size
/ 2);
13392 do_neon_qmovun (void)
13394 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13395 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13396 /* Saturating move with unsigned results. Operands must be signed. */
13397 NEON_ENCODE (INTEGER
, inst
);
13398 neon_two_same (0, 1, et
.size
/ 2);
13402 do_neon_rshift_sat_narrow (void)
13404 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13405 or unsigned. If operands are unsigned, results must also be unsigned. */
13406 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13407 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13408 int imm
= inst
.operands
[2].imm
;
13409 /* This gets the bounds check, size encoding and immediate bits calculation
13413 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13414 VQMOVN.I<size> <Dd>, <Qm>. */
13417 inst
.operands
[2].present
= 0;
13418 inst
.instruction
= N_MNEM_vqmovn
;
13423 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13424 _("immediate out of range"));
13425 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13429 do_neon_rshift_sat_narrow_u (void)
13431 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13432 or unsigned. If operands are unsigned, results must also be unsigned. */
13433 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13434 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13435 int imm
= inst
.operands
[2].imm
;
13436 /* This gets the bounds check, size encoding and immediate bits calculation
13440 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13441 VQMOVUN.I<size> <Dd>, <Qm>. */
13444 inst
.operands
[2].present
= 0;
13445 inst
.instruction
= N_MNEM_vqmovun
;
13450 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13451 _("immediate out of range"));
13452 /* FIXME: The manual is kind of unclear about what value U should have in
13453 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13455 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13459 do_neon_movn (void)
13461 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13462 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13463 NEON_ENCODE (INTEGER
, inst
);
13464 neon_two_same (0, 1, et
.size
/ 2);
13468 do_neon_rshift_narrow (void)
13470 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13471 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13472 int imm
= inst
.operands
[2].imm
;
13473 /* This gets the bounds check, size encoding and immediate bits calculation
13477 /* If immediate is zero then we are a pseudo-instruction for
13478 VMOVN.I<size> <Dd>, <Qm> */
13481 inst
.operands
[2].present
= 0;
13482 inst
.instruction
= N_MNEM_vmovn
;
13487 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13488 _("immediate out of range for narrowing operation"));
13489 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13493 do_neon_shll (void)
13495 /* FIXME: Type checking when lengthening. */
13496 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13497 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13498 unsigned imm
= inst
.operands
[2].imm
;
13500 if (imm
== et
.size
)
13502 /* Maximum shift variant. */
13503 NEON_ENCODE (INTEGER
, inst
);
13504 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13505 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13506 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13507 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13508 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13510 neon_dp_fixup (&inst
);
13514 /* A more-specific type check for non-max versions. */
13515 et
= neon_check_type (2, NS_QDI
,
13516 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13517 NEON_ENCODE (IMMED
, inst
);
13518 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13522 /* Check the various types for the VCVT instruction, and return which version
13523 the current instruction is. */
13526 neon_cvt_flavour (enum neon_shape rs
)
13528 #define CVT_VAR(C,X,Y) \
13529 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13530 if (et.type != NT_invtype) \
13532 inst.error = NULL; \
13535 struct neon_type_el et
;
13536 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13537 || rs
== NS_FF
) ? N_VFP
: 0;
13538 /* The instruction versions which take an immediate take one register
13539 argument, which is extended to the width of the full register. Thus the
13540 "source" and "destination" registers must have the same width. Hack that
13541 here by making the size equal to the key (wider, in this case) operand. */
13542 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13544 CVT_VAR (0, N_S32
, N_F32
);
13545 CVT_VAR (1, N_U32
, N_F32
);
13546 CVT_VAR (2, N_F32
, N_S32
);
13547 CVT_VAR (3, N_F32
, N_U32
);
13548 /* Half-precision conversions. */
13549 CVT_VAR (4, N_F32
, N_F16
);
13550 CVT_VAR (5, N_F16
, N_F32
);
13554 /* VFP instructions. */
13555 CVT_VAR (6, N_F32
, N_F64
);
13556 CVT_VAR (7, N_F64
, N_F32
);
13557 CVT_VAR (8, N_S32
, N_F64
| key
);
13558 CVT_VAR (9, N_U32
, N_F64
| key
);
13559 CVT_VAR (10, N_F64
| key
, N_S32
);
13560 CVT_VAR (11, N_F64
| key
, N_U32
);
13561 /* VFP instructions with bitshift. */
13562 CVT_VAR (12, N_F32
| key
, N_S16
);
13563 CVT_VAR (13, N_F32
| key
, N_U16
);
13564 CVT_VAR (14, N_F64
| key
, N_S16
);
13565 CVT_VAR (15, N_F64
| key
, N_U16
);
13566 CVT_VAR (16, N_S16
, N_F32
| key
);
13567 CVT_VAR (17, N_U16
, N_F32
| key
);
13568 CVT_VAR (18, N_S16
, N_F64
| key
);
13569 CVT_VAR (19, N_U16
, N_F64
| key
);
13575 /* Neon-syntax VFP conversions. */
13578 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13580 const char *opname
= 0;
13582 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13584 /* Conversions with immediate bitshift. */
13585 const char *enc
[] =
13609 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13611 opname
= enc
[flavour
];
13612 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13613 _("operands 0 and 1 must be the same register"));
13614 inst
.operands
[1] = inst
.operands
[2];
13615 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13620 /* Conversions without bitshift. */
13621 const char *enc
[] =
13637 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13638 opname
= enc
[flavour
];
13642 do_vfp_nsyn_opcode (opname
);
13646 do_vfp_nsyn_cvtz (void)
13648 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13649 int flavour
= neon_cvt_flavour (rs
);
13650 const char *enc
[] =
13664 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13665 do_vfp_nsyn_opcode (enc
[flavour
]);
13669 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
13671 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13672 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13673 int flavour
= neon_cvt_flavour (rs
);
13675 /* PR11109: Handle round-to-zero for VCVT conversions. */
13677 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
13678 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
13679 && (rs
== NS_FD
|| rs
== NS_FF
))
13681 do_vfp_nsyn_cvtz ();
13685 /* VFP rather than Neon conversions. */
13688 do_vfp_nsyn_cvt (rs
, flavour
);
13698 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13700 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13703 /* Fixed-point conversion with #0 immediate is encoded as an
13704 integer conversion. */
13705 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13707 immbits
= 32 - inst
.operands
[2].imm
;
13708 NEON_ENCODE (IMMED
, inst
);
13710 inst
.instruction
|= enctab
[flavour
];
13711 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13712 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13713 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13714 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13715 inst
.instruction
|= neon_quad (rs
) << 6;
13716 inst
.instruction
|= 1 << 21;
13717 inst
.instruction
|= immbits
<< 16;
13719 neon_dp_fixup (&inst
);
13727 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13729 NEON_ENCODE (INTEGER
, inst
);
13731 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13735 inst
.instruction
|= enctab
[flavour
];
13737 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13738 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13739 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13740 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13741 inst
.instruction
|= neon_quad (rs
) << 6;
13742 inst
.instruction
|= 2 << 18;
13744 neon_dp_fixup (&inst
);
13748 /* Half-precision conversions for Advanced SIMD -- neon. */
13753 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13755 as_bad (_("operand size must match register width"));
13760 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13762 as_bad (_("operand size must match register width"));
13767 inst
.instruction
= 0x3b60600;
13769 inst
.instruction
= 0x3b60700;
13771 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13772 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13773 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13774 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13775 neon_dp_fixup (&inst
);
13779 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13780 do_vfp_nsyn_cvt (rs
, flavour
);
13785 do_neon_cvtr (void)
13787 do_neon_cvt_1 (FALSE
);
13793 do_neon_cvt_1 (TRUE
);
13797 do_neon_cvtb (void)
13799 inst
.instruction
= 0xeb20a40;
13801 /* The sizes are attached to the mnemonic. */
13802 if (inst
.vectype
.el
[0].type
!= NT_invtype
13803 && inst
.vectype
.el
[0].size
== 16)
13804 inst
.instruction
|= 0x00010000;
13806 /* Programmer's syntax: the sizes are attached to the operands. */
13807 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13808 && inst
.operands
[0].vectype
.size
== 16)
13809 inst
.instruction
|= 0x00010000;
13811 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13812 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13813 do_vfp_cond_or_thumb ();
13818 do_neon_cvtt (void)
13821 inst
.instruction
|= 0x80;
13825 neon_move_immediate (void)
13827 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13828 struct neon_type_el et
= neon_check_type (2, rs
,
13829 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13830 unsigned immlo
, immhi
= 0, immbits
;
13831 int op
, cmode
, float_p
;
13833 constraint (et
.type
== NT_invtype
,
13834 _("operand size must be specified for immediate VMOV"));
13836 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13837 op
= (inst
.instruction
& (1 << 5)) != 0;
13839 immlo
= inst
.operands
[1].imm
;
13840 if (inst
.operands
[1].regisimm
)
13841 immhi
= inst
.operands
[1].reg
;
13843 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13844 _("immediate has bits set outside the operand size"));
13846 float_p
= inst
.operands
[1].immisfloat
;
13848 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13849 et
.size
, et
.type
)) == FAIL
)
13851 /* Invert relevant bits only. */
13852 neon_invert_size (&immlo
, &immhi
, et
.size
);
13853 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13854 with one or the other; those cases are caught by
13855 neon_cmode_for_move_imm. */
13857 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
13858 &op
, et
.size
, et
.type
)) == FAIL
)
13860 first_error (_("immediate out of range"));
13865 inst
.instruction
&= ~(1 << 5);
13866 inst
.instruction
|= op
<< 5;
13868 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13869 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13870 inst
.instruction
|= neon_quad (rs
) << 6;
13871 inst
.instruction
|= cmode
<< 8;
13873 neon_write_immbits (immbits
);
13879 if (inst
.operands
[1].isreg
)
13881 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13883 NEON_ENCODE (INTEGER
, inst
);
13884 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13885 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13886 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13887 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13888 inst
.instruction
|= neon_quad (rs
) << 6;
13892 NEON_ENCODE (IMMED
, inst
);
13893 neon_move_immediate ();
13896 neon_dp_fixup (&inst
);
13899 /* Encode instructions of form:
13901 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13902 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
13905 neon_mixed_length (struct neon_type_el et
, unsigned size
)
13907 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13908 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13909 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13910 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13911 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13912 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13913 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
13914 inst
.instruction
|= neon_logbits (size
) << 20;
13916 neon_dp_fixup (&inst
);
13920 do_neon_dyadic_long (void)
13922 /* FIXME: Type checking for lengthening op. */
13923 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13924 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13925 neon_mixed_length (et
, et
.size
);
13929 do_neon_abal (void)
13931 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13932 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13933 neon_mixed_length (et
, et
.size
);
13937 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
13939 if (inst
.operands
[2].isscalar
)
13941 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
13942 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
13943 NEON_ENCODE (SCALAR
, inst
);
13944 neon_mul_mac (et
, et
.type
== NT_unsigned
);
13948 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13949 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
13950 NEON_ENCODE (INTEGER
, inst
);
13951 neon_mixed_length (et
, et
.size
);
13956 do_neon_mac_maybe_scalar_long (void)
13958 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13962 do_neon_dyadic_wide (void)
13964 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13965 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13966 neon_mixed_length (et
, et
.size
);
13970 do_neon_dyadic_narrow (void)
13972 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13973 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13974 /* Operand sign is unimportant, and the U bit is part of the opcode,
13975 so force the operand type to integer. */
13976 et
.type
= NT_integer
;
13977 neon_mixed_length (et
, et
.size
/ 2);
13981 do_neon_mul_sat_scalar_long (void)
13983 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13987 do_neon_vmull (void)
13989 if (inst
.operands
[2].isscalar
)
13990 do_neon_mac_maybe_scalar_long ();
13993 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13994 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13995 if (et
.type
== NT_poly
)
13996 NEON_ENCODE (POLY
, inst
);
13998 NEON_ENCODE (INTEGER
, inst
);
13999 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14000 zero. Should be OK as-is. */
14001 neon_mixed_length (et
, et
.size
);
14008 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14009 struct neon_type_el et
= neon_check_type (3, rs
,
14010 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14011 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14013 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14014 _("shift out of range"));
14015 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14016 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14017 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14018 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14019 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14020 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14021 inst
.instruction
|= neon_quad (rs
) << 6;
14022 inst
.instruction
|= imm
<< 8;
14024 neon_dp_fixup (&inst
);
14030 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14031 struct neon_type_el et
= neon_check_type (2, rs
,
14032 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14033 unsigned op
= (inst
.instruction
>> 7) & 3;
14034 /* N (width of reversed regions) is encoded as part of the bitmask. We
14035 extract it here to check the elements to be reversed are smaller.
14036 Otherwise we'd get a reserved instruction. */
14037 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14038 gas_assert (elsize
!= 0);
14039 constraint (et
.size
>= elsize
,
14040 _("elements must be smaller than reversal region"));
14041 neon_two_same (neon_quad (rs
), 1, et
.size
);
14047 if (inst
.operands
[1].isscalar
)
14049 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14050 struct neon_type_el et
= neon_check_type (2, rs
,
14051 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14052 unsigned sizebits
= et
.size
>> 3;
14053 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14054 int logsize
= neon_logbits (et
.size
);
14055 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14057 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14060 NEON_ENCODE (SCALAR
, inst
);
14061 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14062 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14063 inst
.instruction
|= LOW4 (dm
);
14064 inst
.instruction
|= HI1 (dm
) << 5;
14065 inst
.instruction
|= neon_quad (rs
) << 6;
14066 inst
.instruction
|= x
<< 17;
14067 inst
.instruction
|= sizebits
<< 16;
14069 neon_dp_fixup (&inst
);
14073 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14074 struct neon_type_el et
= neon_check_type (2, rs
,
14075 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14076 /* Duplicate ARM register to lanes of vector. */
14077 NEON_ENCODE (ARMREG
, inst
);
14080 case 8: inst
.instruction
|= 0x400000; break;
14081 case 16: inst
.instruction
|= 0x000020; break;
14082 case 32: inst
.instruction
|= 0x000000; break;
14085 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14086 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14087 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14088 inst
.instruction
|= neon_quad (rs
) << 21;
14089 /* The encoding for this instruction is identical for the ARM and Thumb
14090 variants, except for the condition field. */
14091 do_vfp_cond_or_thumb ();
14095 /* VMOV has particularly many variations. It can be one of:
14096 0. VMOV<c><q> <Qd>, <Qm>
14097 1. VMOV<c><q> <Dd>, <Dm>
14098 (Register operations, which are VORR with Rm = Rn.)
14099 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14100 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14102 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14103 (ARM register to scalar.)
14104 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14105 (Two ARM registers to vector.)
14106 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14107 (Scalar to ARM register.)
14108 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14109 (Vector to two ARM registers.)
14110 8. VMOV.F32 <Sd>, <Sm>
14111 9. VMOV.F64 <Dd>, <Dm>
14112 (VFP register moves.)
14113 10. VMOV.F32 <Sd>, #imm
14114 11. VMOV.F64 <Dd>, #imm
14115 (VFP float immediate load.)
14116 12. VMOV <Rd>, <Sm>
14117 (VFP single to ARM reg.)
14118 13. VMOV <Sd>, <Rm>
14119 (ARM reg to VFP single.)
14120 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14121 (Two ARM regs to two VFP singles.)
14122 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14123 (Two VFP singles to two ARM regs.)
14125 These cases can be disambiguated using neon_select_shape, except cases 1/9
14126 and 3/11 which depend on the operand type too.
14128 All the encoded bits are hardcoded by this function.
14130 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14131 Cases 5, 7 may be used with VFPv2 and above.
14133 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14134 can specify a type where it doesn't make sense to, and is ignored). */
14139 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14140 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14142 struct neon_type_el et
;
14143 const char *ldconst
= 0;
14147 case NS_DD
: /* case 1/9. */
14148 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14149 /* It is not an error here if no type is given. */
14151 if (et
.type
== NT_float
&& et
.size
== 64)
14153 do_vfp_nsyn_opcode ("fcpyd");
14156 /* fall through. */
14158 case NS_QQ
: /* case 0/1. */
14160 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14162 /* The architecture manual I have doesn't explicitly state which
14163 value the U bit should have for register->register moves, but
14164 the equivalent VORR instruction has U = 0, so do that. */
14165 inst
.instruction
= 0x0200110;
14166 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14167 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14168 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14169 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14170 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14171 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14172 inst
.instruction
|= neon_quad (rs
) << 6;
14174 neon_dp_fixup (&inst
);
14178 case NS_DI
: /* case 3/11. */
14179 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14181 if (et
.type
== NT_float
&& et
.size
== 64)
14183 /* case 11 (fconstd). */
14184 ldconst
= "fconstd";
14185 goto encode_fconstd
;
14187 /* fall through. */
14189 case NS_QI
: /* case 2/3. */
14190 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14192 inst
.instruction
= 0x0800010;
14193 neon_move_immediate ();
14194 neon_dp_fixup (&inst
);
14197 case NS_SR
: /* case 4. */
14199 unsigned bcdebits
= 0;
14201 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14202 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14204 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14205 logsize
= neon_logbits (et
.size
);
14207 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14209 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14210 && et
.size
!= 32, _(BAD_FPU
));
14211 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14212 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14216 case 8: bcdebits
= 0x8; break;
14217 case 16: bcdebits
= 0x1; break;
14218 case 32: bcdebits
= 0x0; break;
14222 bcdebits
|= x
<< logsize
;
14224 inst
.instruction
= 0xe000b10;
14225 do_vfp_cond_or_thumb ();
14226 inst
.instruction
|= LOW4 (dn
) << 16;
14227 inst
.instruction
|= HI1 (dn
) << 7;
14228 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14229 inst
.instruction
|= (bcdebits
& 3) << 5;
14230 inst
.instruction
|= (bcdebits
>> 2) << 21;
14234 case NS_DRR
: /* case 5 (fmdrr). */
14235 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14238 inst
.instruction
= 0xc400b10;
14239 do_vfp_cond_or_thumb ();
14240 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14241 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14242 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14243 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14246 case NS_RS
: /* case 6. */
14249 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14250 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14251 unsigned abcdebits
= 0;
14253 et
= neon_check_type (2, NS_NULL
,
14254 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14255 logsize
= neon_logbits (et
.size
);
14257 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14259 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14260 && et
.size
!= 32, _(BAD_FPU
));
14261 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14262 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14266 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14267 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14268 case 32: abcdebits
= 0x00; break;
14272 abcdebits
|= x
<< logsize
;
14273 inst
.instruction
= 0xe100b10;
14274 do_vfp_cond_or_thumb ();
14275 inst
.instruction
|= LOW4 (dn
) << 16;
14276 inst
.instruction
|= HI1 (dn
) << 7;
14277 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14278 inst
.instruction
|= (abcdebits
& 3) << 5;
14279 inst
.instruction
|= (abcdebits
>> 2) << 21;
14283 case NS_RRD
: /* case 7 (fmrrd). */
14284 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14287 inst
.instruction
= 0xc500b10;
14288 do_vfp_cond_or_thumb ();
14289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14290 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14291 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14292 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14295 case NS_FF
: /* case 8 (fcpys). */
14296 do_vfp_nsyn_opcode ("fcpys");
14299 case NS_FI
: /* case 10 (fconsts). */
14300 ldconst
= "fconsts";
14302 if (is_quarter_float (inst
.operands
[1].imm
))
14304 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14305 do_vfp_nsyn_opcode (ldconst
);
14308 first_error (_("immediate out of range"));
14311 case NS_RF
: /* case 12 (fmrs). */
14312 do_vfp_nsyn_opcode ("fmrs");
14315 case NS_FR
: /* case 13 (fmsr). */
14316 do_vfp_nsyn_opcode ("fmsr");
14319 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14320 (one of which is a list), but we have parsed four. Do some fiddling to
14321 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14323 case NS_RRFF
: /* case 14 (fmrrs). */
14324 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14325 _("VFP registers must be adjacent"));
14326 inst
.operands
[2].imm
= 2;
14327 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14328 do_vfp_nsyn_opcode ("fmrrs");
14331 case NS_FFRR
: /* case 15 (fmsrr). */
14332 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14333 _("VFP registers must be adjacent"));
14334 inst
.operands
[1] = inst
.operands
[2];
14335 inst
.operands
[2] = inst
.operands
[3];
14336 inst
.operands
[0].imm
= 2;
14337 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14338 do_vfp_nsyn_opcode ("fmsrr");
14347 do_neon_rshift_round_imm (void)
14349 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14350 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14351 int imm
= inst
.operands
[2].imm
;
14353 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14356 inst
.operands
[2].present
= 0;
14361 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14362 _("immediate out of range for shift"));
14363 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14368 do_neon_movl (void)
14370 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14371 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14372 unsigned sizebits
= et
.size
>> 3;
14373 inst
.instruction
|= sizebits
<< 19;
14374 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14380 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14381 struct neon_type_el et
= neon_check_type (2, rs
,
14382 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14383 NEON_ENCODE (INTEGER
, inst
);
14384 neon_two_same (neon_quad (rs
), 1, et
.size
);
14388 do_neon_zip_uzp (void)
14390 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14391 struct neon_type_el et
= neon_check_type (2, rs
,
14392 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14393 if (rs
== NS_DD
&& et
.size
== 32)
14395 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14396 inst
.instruction
= N_MNEM_vtrn
;
14400 neon_two_same (neon_quad (rs
), 1, et
.size
);
14404 do_neon_sat_abs_neg (void)
14406 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14407 struct neon_type_el et
= neon_check_type (2, rs
,
14408 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14409 neon_two_same (neon_quad (rs
), 1, et
.size
);
14413 do_neon_pair_long (void)
14415 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14416 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14417 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14418 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14419 neon_two_same (neon_quad (rs
), 1, et
.size
);
14423 do_neon_recip_est (void)
14425 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14426 struct neon_type_el et
= neon_check_type (2, rs
,
14427 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14428 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14429 neon_two_same (neon_quad (rs
), 1, et
.size
);
14435 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14436 struct neon_type_el et
= neon_check_type (2, rs
,
14437 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14438 neon_two_same (neon_quad (rs
), 1, et
.size
);
14444 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14445 struct neon_type_el et
= neon_check_type (2, rs
,
14446 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14447 neon_two_same (neon_quad (rs
), 1, et
.size
);
14453 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14454 struct neon_type_el et
= neon_check_type (2, rs
,
14455 N_EQK
| N_INT
, N_8
| N_KEY
);
14456 neon_two_same (neon_quad (rs
), 1, et
.size
);
14462 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14463 neon_two_same (neon_quad (rs
), 1, -1);
14467 do_neon_tbl_tbx (void)
14469 unsigned listlenbits
;
14470 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14472 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14474 first_error (_("bad list length for table lookup"));
14478 listlenbits
= inst
.operands
[1].imm
- 1;
14479 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14480 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14481 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14482 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14483 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14484 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14485 inst
.instruction
|= listlenbits
<< 8;
14487 neon_dp_fixup (&inst
);
14491 do_neon_ldm_stm (void)
14493 /* P, U and L bits are part of bitmask. */
14494 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14495 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14497 if (inst
.operands
[1].issingle
)
14499 do_vfp_nsyn_ldm_stm (is_dbmode
);
14503 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14504 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14506 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14507 _("register list must contain at least 1 and at most 16 "
14510 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14511 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14512 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14513 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14515 inst
.instruction
|= offsetbits
;
14517 do_vfp_cond_or_thumb ();
14521 do_neon_ldr_str (void)
14523 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14525 if (inst
.operands
[0].issingle
)
14528 do_vfp_nsyn_opcode ("flds");
14530 do_vfp_nsyn_opcode ("fsts");
14535 do_vfp_nsyn_opcode ("fldd");
14537 do_vfp_nsyn_opcode ("fstd");
14541 /* "interleave" version also handles non-interleaving register VLD1/VST1
14545 do_neon_ld_st_interleave (void)
14547 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14548 N_8
| N_16
| N_32
| N_64
);
14549 unsigned alignbits
= 0;
14551 /* The bits in this table go:
14552 0: register stride of one (0) or two (1)
14553 1,2: register list length, minus one (1, 2, 3, 4).
14554 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14555 We use -1 for invalid entries. */
14556 const int typetable
[] =
14558 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14559 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14560 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14561 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14565 if (et
.type
== NT_invtype
)
14568 if (inst
.operands
[1].immisalign
)
14569 switch (inst
.operands
[1].imm
>> 8)
14571 case 64: alignbits
= 1; break;
14573 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14574 goto bad_alignment
;
14578 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14579 goto bad_alignment
;
14584 first_error (_("bad alignment"));
14588 inst
.instruction
|= alignbits
<< 4;
14589 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14591 /* Bits [4:6] of the immediate in a list specifier encode register stride
14592 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14593 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14594 up the right value for "type" in a table based on this value and the given
14595 list style, then stick it back. */
14596 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14597 | (((inst
.instruction
>> 8) & 3) << 3);
14599 typebits
= typetable
[idx
];
14601 constraint (typebits
== -1, _("bad list type for instruction"));
14603 inst
.instruction
&= ~0xf00;
14604 inst
.instruction
|= typebits
<< 8;
14607 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14608 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14609 otherwise. The variable arguments are a list of pairs of legal (size, align)
14610 values, terminated with -1. */
14613 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14616 int result
= FAIL
, thissize
, thisalign
;
14618 if (!inst
.operands
[1].immisalign
)
14624 va_start (ap
, do_align
);
14628 thissize
= va_arg (ap
, int);
14629 if (thissize
== -1)
14631 thisalign
= va_arg (ap
, int);
14633 if (size
== thissize
&& align
== thisalign
)
14636 while (result
!= SUCCESS
);
14640 if (result
== SUCCESS
)
14643 first_error (_("unsupported alignment for instruction"));
14649 do_neon_ld_st_lane (void)
14651 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14652 int align_good
, do_align
= 0;
14653 int logsize
= neon_logbits (et
.size
);
14654 int align
= inst
.operands
[1].imm
>> 8;
14655 int n
= (inst
.instruction
>> 8) & 3;
14656 int max_el
= 64 / et
.size
;
14658 if (et
.type
== NT_invtype
)
14661 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14662 _("bad list length"));
14663 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14664 _("scalar index out of range"));
14665 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14667 _("stride of 2 unavailable when element size is 8"));
14671 case 0: /* VLD1 / VST1. */
14672 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14674 if (align_good
== FAIL
)
14678 unsigned alignbits
= 0;
14681 case 16: alignbits
= 0x1; break;
14682 case 32: alignbits
= 0x3; break;
14685 inst
.instruction
|= alignbits
<< 4;
14689 case 1: /* VLD2 / VST2. */
14690 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14692 if (align_good
== FAIL
)
14695 inst
.instruction
|= 1 << 4;
14698 case 2: /* VLD3 / VST3. */
14699 constraint (inst
.operands
[1].immisalign
,
14700 _("can't use alignment with this instruction"));
14703 case 3: /* VLD4 / VST4. */
14704 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14705 16, 64, 32, 64, 32, 128, -1);
14706 if (align_good
== FAIL
)
14710 unsigned alignbits
= 0;
14713 case 8: alignbits
= 0x1; break;
14714 case 16: alignbits
= 0x1; break;
14715 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14718 inst
.instruction
|= alignbits
<< 4;
14725 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14726 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14727 inst
.instruction
|= 1 << (4 + logsize
);
14729 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14730 inst
.instruction
|= logsize
<< 10;
14733 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14736 do_neon_ld_dup (void)
14738 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14739 int align_good
, do_align
= 0;
14741 if (et
.type
== NT_invtype
)
14744 switch ((inst
.instruction
>> 8) & 3)
14746 case 0: /* VLD1. */
14747 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14748 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14749 &do_align
, 16, 16, 32, 32, -1);
14750 if (align_good
== FAIL
)
14752 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14755 case 2: inst
.instruction
|= 1 << 5; break;
14756 default: first_error (_("bad list length")); return;
14758 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14761 case 1: /* VLD2. */
14762 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14763 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14764 if (align_good
== FAIL
)
14766 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14767 _("bad list length"));
14768 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14769 inst
.instruction
|= 1 << 5;
14770 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14773 case 2: /* VLD3. */
14774 constraint (inst
.operands
[1].immisalign
,
14775 _("can't use alignment with this instruction"));
14776 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14777 _("bad list length"));
14778 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14779 inst
.instruction
|= 1 << 5;
14780 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14783 case 3: /* VLD4. */
14785 int align
= inst
.operands
[1].imm
>> 8;
14786 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14787 16, 64, 32, 64, 32, 128, -1);
14788 if (align_good
== FAIL
)
14790 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14791 _("bad list length"));
14792 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14793 inst
.instruction
|= 1 << 5;
14794 if (et
.size
== 32 && align
== 128)
14795 inst
.instruction
|= 0x3 << 6;
14797 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14804 inst
.instruction
|= do_align
<< 4;
14807 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14808 apart from bits [11:4]. */
14811 do_neon_ldx_stx (void)
14813 if (inst
.operands
[1].isreg
)
14814 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
14816 switch (NEON_LANE (inst
.operands
[0].imm
))
14818 case NEON_INTERLEAVE_LANES
:
14819 NEON_ENCODE (INTERLV
, inst
);
14820 do_neon_ld_st_interleave ();
14823 case NEON_ALL_LANES
:
14824 NEON_ENCODE (DUP
, inst
);
14829 NEON_ENCODE (LANE
, inst
);
14830 do_neon_ld_st_lane ();
14833 /* L bit comes from bit mask. */
14834 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14835 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14836 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14838 if (inst
.operands
[1].postind
)
14840 int postreg
= inst
.operands
[1].imm
& 0xf;
14841 constraint (!inst
.operands
[1].immisreg
,
14842 _("post-index must be a register"));
14843 constraint (postreg
== 0xd || postreg
== 0xf,
14844 _("bad register for post-index"));
14845 inst
.instruction
|= postreg
;
14847 else if (inst
.operands
[1].writeback
)
14849 inst
.instruction
|= 0xd;
14852 inst
.instruction
|= 0xf;
14855 inst
.instruction
|= 0xf9000000;
14857 inst
.instruction
|= 0xf4000000;
14860 /* Overall per-instruction processing. */
14862 /* We need to be able to fix up arbitrary expressions in some statements.
14863 This is so that we can handle symbols that are an arbitrary distance from
14864 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
14865 which returns part of an address in a form which will be valid for
14866 a data instruction. We do this by pushing the expression into a symbol
14867 in the expr_section, and creating a fix for that. */
14870 fix_new_arm (fragS
* frag
,
14885 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
14886 (enum bfd_reloc_code_real
) reloc
);
14890 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
14891 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
14895 /* Mark whether the fix is to a THUMB instruction, or an ARM
14897 new_fix
->tc_fix_data
= thumb_mode
;
14900 /* Create a frg for an instruction requiring relaxation. */
14902 output_relax_insn (void)
14908 /* The size of the instruction is unknown, so tie the debug info to the
14909 start of the instruction. */
14910 dwarf2_emit_insn (0);
14912 switch (inst
.reloc
.exp
.X_op
)
14915 sym
= inst
.reloc
.exp
.X_add_symbol
;
14916 offset
= inst
.reloc
.exp
.X_add_number
;
14920 offset
= inst
.reloc
.exp
.X_add_number
;
14923 sym
= make_expr_symbol (&inst
.reloc
.exp
);
14927 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
14928 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
14929 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
14932 /* Write a 32-bit thumb instruction to buf. */
14934 put_thumb32_insn (char * buf
, unsigned long insn
)
14936 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
14937 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
14941 output_inst (const char * str
)
14947 as_bad ("%s -- `%s'", inst
.error
, str
);
14952 output_relax_insn ();
14955 if (inst
.size
== 0)
14958 to
= frag_more (inst
.size
);
14959 /* PR 9814: Record the thumb mode into the current frag so that we know
14960 what type of NOP padding to use, if necessary. We override any previous
14961 setting so that if the mode has changed then the NOPS that we use will
14962 match the encoding of the last instruction in the frag. */
14963 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
14965 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
14967 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
14968 put_thumb32_insn (to
, inst
.instruction
);
14970 else if (inst
.size
> INSN_SIZE
)
14972 gas_assert (inst
.size
== (2 * INSN_SIZE
));
14973 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14974 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14977 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14979 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14980 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14981 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14984 dwarf2_emit_insn (inst
.size
);
14988 output_it_inst (int cond
, int mask
, char * to
)
14990 unsigned long instruction
= 0xbf00;
14993 instruction
|= mask
;
14994 instruction
|= cond
<< 4;
14998 to
= frag_more (2);
15000 dwarf2_emit_insn (2);
15004 md_number_to_chars (to
, instruction
, 2);
15009 /* Tag values used in struct asm_opcode's tag field. */
15012 OT_unconditional
, /* Instruction cannot be conditionalized.
15013 The ARM condition field is still 0xE. */
15014 OT_unconditionalF
, /* Instruction cannot be conditionalized
15015 and carries 0xF in its ARM condition field. */
15016 OT_csuffix
, /* Instruction takes a conditional suffix. */
15017 OT_csuffixF
, /* Some forms of the instruction take a conditional
15018 suffix, others place 0xF where the condition field
15020 OT_cinfix3
, /* Instruction takes a conditional infix,
15021 beginning at character index 3. (In
15022 unified mode, it becomes a suffix.) */
15023 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15024 tsts, cmps, cmns, and teqs. */
15025 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15026 character index 3, even in unified mode. Used for
15027 legacy instructions where suffix and infix forms
15028 may be ambiguous. */
15029 OT_csuf_or_in3
, /* Instruction takes either a conditional
15030 suffix or an infix at character index 3. */
15031 OT_odd_infix_unc
, /* This is the unconditional variant of an
15032 instruction that takes a conditional infix
15033 at an unusual position. In unified mode,
15034 this variant will accept a suffix. */
15035 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15036 are the conditional variants of instructions that
15037 take conditional infixes in unusual positions.
15038 The infix appears at character index
15039 (tag - OT_odd_infix_0). These are not accepted
15040 in unified mode. */
15043 /* Subroutine of md_assemble, responsible for looking up the primary
15044 opcode from the mnemonic the user wrote. STR points to the
15045 beginning of the mnemonic.
15047 This is not simply a hash table lookup, because of conditional
15048 variants. Most instructions have conditional variants, which are
15049 expressed with a _conditional affix_ to the mnemonic. If we were
15050 to encode each conditional variant as a literal string in the opcode
15051 table, it would have approximately 20,000 entries.
15053 Most mnemonics take this affix as a suffix, and in unified syntax,
15054 'most' is upgraded to 'all'. However, in the divided syntax, some
15055 instructions take the affix as an infix, notably the s-variants of
15056 the arithmetic instructions. Of those instructions, all but six
15057 have the infix appear after the third character of the mnemonic.
15059 Accordingly, the algorithm for looking up primary opcodes given
15062 1. Look up the identifier in the opcode table.
15063 If we find a match, go to step U.
15065 2. Look up the last two characters of the identifier in the
15066 conditions table. If we find a match, look up the first N-2
15067 characters of the identifier in the opcode table. If we
15068 find a match, go to step CE.
15070 3. Look up the fourth and fifth characters of the identifier in
15071 the conditions table. If we find a match, extract those
15072 characters from the identifier, and look up the remaining
15073 characters in the opcode table. If we find a match, go
15078 U. Examine the tag field of the opcode structure, in case this is
15079 one of the six instructions with its conditional infix in an
15080 unusual place. If it is, the tag tells us where to find the
15081 infix; look it up in the conditions table and set inst.cond
15082 accordingly. Otherwise, this is an unconditional instruction.
15083 Again set inst.cond accordingly. Return the opcode structure.
15085 CE. Examine the tag field to make sure this is an instruction that
15086 should receive a conditional suffix. If it is not, fail.
15087 Otherwise, set inst.cond from the suffix we already looked up,
15088 and return the opcode structure.
15090 CM. Examine the tag field to make sure this is an instruction that
15091 should receive a conditional infix after the third character.
15092 If it is not, fail. Otherwise, undo the edits to the current
15093 line of input and proceed as for case CE. */
15095 static const struct asm_opcode
*
15096 opcode_lookup (char **str
)
15100 const struct asm_opcode
*opcode
;
15101 const struct asm_cond
*cond
;
15104 /* Scan up to the end of the mnemonic, which must end in white space,
15105 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15106 for (base
= end
= *str
; *end
!= '\0'; end
++)
15107 if (*end
== ' ' || *end
== '.')
15113 /* Handle a possible width suffix and/or Neon type suffix. */
15118 /* The .w and .n suffixes are only valid if the unified syntax is in
15120 if (unified_syntax
&& end
[1] == 'w')
15122 else if (unified_syntax
&& end
[1] == 'n')
15127 inst
.vectype
.elems
= 0;
15129 *str
= end
+ offset
;
15131 if (end
[offset
] == '.')
15133 /* See if we have a Neon type suffix (possible in either unified or
15134 non-unified ARM syntax mode). */
15135 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15138 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15144 /* Look for unaffixed or special-case affixed mnemonic. */
15145 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15150 if (opcode
->tag
< OT_odd_infix_0
)
15152 inst
.cond
= COND_ALWAYS
;
15156 if (warn_on_deprecated
&& unified_syntax
)
15157 as_warn (_("conditional infixes are deprecated in unified syntax"));
15158 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15159 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15162 inst
.cond
= cond
->value
;
15166 /* Cannot have a conditional suffix on a mnemonic of less than two
15168 if (end
- base
< 3)
15171 /* Look for suffixed mnemonic. */
15173 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15174 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15176 if (opcode
&& cond
)
15179 switch (opcode
->tag
)
15181 case OT_cinfix3_legacy
:
15182 /* Ignore conditional suffixes matched on infix only mnemonics. */
15186 case OT_cinfix3_deprecated
:
15187 case OT_odd_infix_unc
:
15188 if (!unified_syntax
)
15190 /* else fall through */
15194 case OT_csuf_or_in3
:
15195 inst
.cond
= cond
->value
;
15198 case OT_unconditional
:
15199 case OT_unconditionalF
:
15201 inst
.cond
= cond
->value
;
15204 /* Delayed diagnostic. */
15205 inst
.error
= BAD_COND
;
15206 inst
.cond
= COND_ALWAYS
;
15215 /* Cannot have a usual-position infix on a mnemonic of less than
15216 six characters (five would be a suffix). */
15217 if (end
- base
< 6)
15220 /* Look for infixed mnemonic in the usual position. */
15222 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15226 memcpy (save
, affix
, 2);
15227 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15228 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15230 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15231 memcpy (affix
, save
, 2);
15234 && (opcode
->tag
== OT_cinfix3
15235 || opcode
->tag
== OT_cinfix3_deprecated
15236 || opcode
->tag
== OT_csuf_or_in3
15237 || opcode
->tag
== OT_cinfix3_legacy
))
15240 if (warn_on_deprecated
&& unified_syntax
15241 && (opcode
->tag
== OT_cinfix3
15242 || opcode
->tag
== OT_cinfix3_deprecated
))
15243 as_warn (_("conditional infixes are deprecated in unified syntax"));
15245 inst
.cond
= cond
->value
;
15252 /* This function generates an initial IT instruction, leaving its block
15253 virtually open for the new instructions. Eventually,
15254 the mask will be updated by now_it_add_mask () each time
15255 a new instruction needs to be included in the IT block.
15256 Finally, the block is closed with close_automatic_it_block ().
15257 The block closure can be requested either from md_assemble (),
15258 a tencode (), or due to a label hook. */
15261 new_automatic_it_block (int cond
)
15263 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15264 now_it
.mask
= 0x18;
15266 now_it
.block_length
= 1;
15267 mapping_state (MAP_THUMB
);
15268 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15271 /* Close an automatic IT block.
15272 See comments in new_automatic_it_block (). */
15275 close_automatic_it_block (void)
15277 now_it
.mask
= 0x10;
15278 now_it
.block_length
= 0;
15281 /* Update the mask of the current automatically-generated IT
15282 instruction. See comments in new_automatic_it_block (). */
15285 now_it_add_mask (int cond
)
15287 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15288 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15289 | ((bitvalue) << (nbit)))
15290 const int resulting_bit
= (cond
& 1);
15292 now_it
.mask
&= 0xf;
15293 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15295 (5 - now_it
.block_length
));
15296 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15298 ((5 - now_it
.block_length
) - 1) );
15299 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15302 #undef SET_BIT_VALUE
15305 /* The IT blocks handling machinery is accessed through the these functions:
15306 it_fsm_pre_encode () from md_assemble ()
15307 set_it_insn_type () optional, from the tencode functions
15308 set_it_insn_type_last () ditto
15309 in_it_block () ditto
15310 it_fsm_post_encode () from md_assemble ()
15311 force_automatic_it_block_close () from label habdling functions
15314 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15315 initializing the IT insn type with a generic initial value depending
15316 on the inst.condition.
15317 2) During the tencode function, two things may happen:
15318 a) The tencode function overrides the IT insn type by
15319 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15320 b) The tencode function queries the IT block state by
15321 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15323 Both set_it_insn_type and in_it_block run the internal FSM state
15324 handling function (handle_it_state), because: a) setting the IT insn
15325 type may incur in an invalid state (exiting the function),
15326 and b) querying the state requires the FSM to be updated.
15327 Specifically we want to avoid creating an IT block for conditional
15328 branches, so it_fsm_pre_encode is actually a guess and we can't
15329 determine whether an IT block is required until the tencode () routine
15330 has decided what type of instruction this actually it.
15331 Because of this, if set_it_insn_type and in_it_block have to be used,
15332 set_it_insn_type has to be called first.
15334 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15335 determines the insn IT type depending on the inst.cond code.
15336 When a tencode () routine encodes an instruction that can be
15337 either outside an IT block, or, in the case of being inside, has to be
15338 the last one, set_it_insn_type_last () will determine the proper
15339 IT instruction type based on the inst.cond code. Otherwise,
15340 set_it_insn_type can be called for overriding that logic or
15341 for covering other cases.
15343 Calling handle_it_state () may not transition the IT block state to
15344 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15345 still queried. Instead, if the FSM determines that the state should
15346 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15347 after the tencode () function: that's what it_fsm_post_encode () does.
15349 Since in_it_block () calls the state handling function to get an
15350 updated state, an error may occur (due to invalid insns combination).
15351 In that case, inst.error is set.
15352 Therefore, inst.error has to be checked after the execution of
15353 the tencode () routine.
15355 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15356 any pending state change (if any) that didn't take place in
15357 handle_it_state () as explained above. */
15360 it_fsm_pre_encode (void)
15362 if (inst
.cond
!= COND_ALWAYS
)
15363 inst
.it_insn_type
= INSIDE_IT_INSN
;
15365 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15367 now_it
.state_handled
= 0;
15370 /* IT state FSM handling function. */
15373 handle_it_state (void)
15375 now_it
.state_handled
= 1;
15377 switch (now_it
.state
)
15379 case OUTSIDE_IT_BLOCK
:
15380 switch (inst
.it_insn_type
)
15382 case OUTSIDE_IT_INSN
:
15385 case INSIDE_IT_INSN
:
15386 case INSIDE_IT_LAST_INSN
:
15387 if (thumb_mode
== 0)
15390 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15391 as_tsktsk (_("Warning: conditional outside an IT block"\
15396 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15397 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15399 /* Automatically generate the IT instruction. */
15400 new_automatic_it_block (inst
.cond
);
15401 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15402 close_automatic_it_block ();
15406 inst
.error
= BAD_OUT_IT
;
15412 case IF_INSIDE_IT_LAST_INSN
:
15413 case NEUTRAL_IT_INSN
:
15417 now_it
.state
= MANUAL_IT_BLOCK
;
15418 now_it
.block_length
= 0;
15423 case AUTOMATIC_IT_BLOCK
:
15424 /* Three things may happen now:
15425 a) We should increment current it block size;
15426 b) We should close current it block (closing insn or 4 insns);
15427 c) We should close current it block and start a new one (due
15428 to incompatible conditions or
15429 4 insns-length block reached). */
15431 switch (inst
.it_insn_type
)
15433 case OUTSIDE_IT_INSN
:
15434 /* The closure of the block shall happen immediatelly,
15435 so any in_it_block () call reports the block as closed. */
15436 force_automatic_it_block_close ();
15439 case INSIDE_IT_INSN
:
15440 case INSIDE_IT_LAST_INSN
:
15441 case IF_INSIDE_IT_LAST_INSN
:
15442 now_it
.block_length
++;
15444 if (now_it
.block_length
> 4
15445 || !now_it_compatible (inst
.cond
))
15447 force_automatic_it_block_close ();
15448 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15449 new_automatic_it_block (inst
.cond
);
15453 now_it_add_mask (inst
.cond
);
15456 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15457 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15458 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15459 close_automatic_it_block ();
15462 case NEUTRAL_IT_INSN
:
15463 now_it
.block_length
++;
15465 if (now_it
.block_length
> 4)
15466 force_automatic_it_block_close ();
15468 now_it_add_mask (now_it
.cc
& 1);
15472 close_automatic_it_block ();
15473 now_it
.state
= MANUAL_IT_BLOCK
;
15478 case MANUAL_IT_BLOCK
:
15480 /* Check conditional suffixes. */
15481 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15484 now_it
.mask
&= 0x1f;
15485 is_last
= (now_it
.mask
== 0x10);
15487 switch (inst
.it_insn_type
)
15489 case OUTSIDE_IT_INSN
:
15490 inst
.error
= BAD_NOT_IT
;
15493 case INSIDE_IT_INSN
:
15494 if (cond
!= inst
.cond
)
15496 inst
.error
= BAD_IT_COND
;
15501 case INSIDE_IT_LAST_INSN
:
15502 case IF_INSIDE_IT_LAST_INSN
:
15503 if (cond
!= inst
.cond
)
15505 inst
.error
= BAD_IT_COND
;
15510 inst
.error
= BAD_BRANCH
;
15515 case NEUTRAL_IT_INSN
:
15516 /* The BKPT instruction is unconditional even in an IT block. */
15520 inst
.error
= BAD_IT_IT
;
15531 it_fsm_post_encode (void)
15535 if (!now_it
.state_handled
)
15536 handle_it_state ();
15538 is_last
= (now_it
.mask
== 0x10);
15541 now_it
.state
= OUTSIDE_IT_BLOCK
;
15547 force_automatic_it_block_close (void)
15549 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15551 close_automatic_it_block ();
15552 now_it
.state
= OUTSIDE_IT_BLOCK
;
15560 if (!now_it
.state_handled
)
15561 handle_it_state ();
15563 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15567 md_assemble (char *str
)
15570 const struct asm_opcode
* opcode
;
15572 /* Align the previous label if needed. */
15573 if (last_label_seen
!= NULL
)
15575 symbol_set_frag (last_label_seen
, frag_now
);
15576 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15577 S_SET_SEGMENT (last_label_seen
, now_seg
);
15580 memset (&inst
, '\0', sizeof (inst
));
15581 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15583 opcode
= opcode_lookup (&p
);
15586 /* It wasn't an instruction, but it might be a register alias of
15587 the form alias .req reg, or a Neon .dn/.qn directive. */
15588 if (! create_register_alias (str
, p
)
15589 && ! create_neon_reg_alias (str
, p
))
15590 as_bad (_("bad instruction `%s'"), str
);
15595 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15596 as_warn (_("s suffix on comparison instruction is deprecated"));
15598 /* The value which unconditional instructions should have in place of the
15599 condition field. */
15600 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15604 arm_feature_set variant
;
15606 variant
= cpu_variant
;
15607 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15608 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15609 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15610 /* Check that this instruction is supported for this CPU. */
15611 if (!opcode
->tvariant
15612 || (thumb_mode
== 1
15613 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15615 as_bad (_("selected processor does not support `%s'"), str
);
15618 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15619 && opcode
->tencode
!= do_t_branch
)
15621 as_bad (_("Thumb does not support conditional execution"));
15625 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15627 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15628 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15629 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15631 /* Two things are addressed here.
15632 1) Implicit require narrow instructions on Thumb-1.
15633 This avoids relaxation accidentally introducing Thumb-2
15635 2) Reject wide instructions in non Thumb-2 cores. */
15636 if (inst
.size_req
== 0)
15638 else if (inst
.size_req
== 4)
15640 as_bad (_("selected processor does not support `%s'"), str
);
15646 inst
.instruction
= opcode
->tvalue
;
15648 if (!parse_operands (p
, opcode
->operands
))
15650 /* Prepare the it_insn_type for those encodings that don't set
15652 it_fsm_pre_encode ();
15654 opcode
->tencode ();
15656 it_fsm_post_encode ();
15659 if (!(inst
.error
|| inst
.relax
))
15661 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15662 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15663 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15665 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15670 /* Something has gone badly wrong if we try to relax a fixed size
15672 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15674 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15675 *opcode
->tvariant
);
15676 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15677 set those bits when Thumb-2 32-bit instructions are seen. ie.
15678 anything other than bl/blx and v6-M instructions.
15679 This is overly pessimistic for relaxable instructions. */
15680 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15682 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15683 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15684 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15687 check_neon_suffixes
;
15691 mapping_state (MAP_THUMB
);
15694 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15698 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15699 is_bx
= (opcode
->aencode
== do_bx
);
15701 /* Check that this instruction is supported for this CPU. */
15702 if (!(is_bx
&& fix_v4bx
)
15703 && !(opcode
->avariant
&&
15704 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15706 as_bad (_("selected processor does not support `%s'"), str
);
15711 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15715 inst
.instruction
= opcode
->avalue
;
15716 if (opcode
->tag
== OT_unconditionalF
)
15717 inst
.instruction
|= 0xF << 28;
15719 inst
.instruction
|= inst
.cond
<< 28;
15720 inst
.size
= INSN_SIZE
;
15721 if (!parse_operands (p
, opcode
->operands
))
15723 it_fsm_pre_encode ();
15724 opcode
->aencode ();
15725 it_fsm_post_encode ();
15727 /* Arm mode bx is marked as both v4T and v5 because it's still required
15728 on a hypothetical non-thumb v5 core. */
15730 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15732 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15733 *opcode
->avariant
);
15735 check_neon_suffixes
;
15739 mapping_state (MAP_ARM
);
15744 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15752 check_it_blocks_finished (void)
15757 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15758 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15759 == MANUAL_IT_BLOCK
)
15761 as_warn (_("section '%s' finished with an open IT block."),
15765 if (now_it
.state
== MANUAL_IT_BLOCK
)
15766 as_warn (_("file finished with an open IT block."));
15770 /* Various frobbings of labels and their addresses. */
15773 arm_start_line_hook (void)
15775 last_label_seen
= NULL
;
15779 arm_frob_label (symbolS
* sym
)
15781 last_label_seen
= sym
;
15783 ARM_SET_THUMB (sym
, thumb_mode
);
15785 #if defined OBJ_COFF || defined OBJ_ELF
15786 ARM_SET_INTERWORK (sym
, support_interwork
);
15789 force_automatic_it_block_close ();
15791 /* Note - do not allow local symbols (.Lxxx) to be labelled
15792 as Thumb functions. This is because these labels, whilst
15793 they exist inside Thumb code, are not the entry points for
15794 possible ARM->Thumb calls. Also, these labels can be used
15795 as part of a computed goto or switch statement. eg gcc
15796 can generate code that looks like this:
15798 ldr r2, [pc, .Laaa]
15808 The first instruction loads the address of the jump table.
15809 The second instruction converts a table index into a byte offset.
15810 The third instruction gets the jump address out of the table.
15811 The fourth instruction performs the jump.
15813 If the address stored at .Laaa is that of a symbol which has the
15814 Thumb_Func bit set, then the linker will arrange for this address
15815 to have the bottom bit set, which in turn would mean that the
15816 address computation performed by the third instruction would end
15817 up with the bottom bit set. Since the ARM is capable of unaligned
15818 word loads, the instruction would then load the incorrect address
15819 out of the jump table, and chaos would ensue. */
15820 if (label_is_thumb_function_name
15821 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
15822 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
15824 /* When the address of a Thumb function is taken the bottom
15825 bit of that address should be set. This will allow
15826 interworking between Arm and Thumb functions to work
15829 THUMB_SET_FUNC (sym
, 1);
15831 label_is_thumb_function_name
= FALSE
;
15834 dwarf2_emit_label (sym
);
15838 arm_data_in_code (void)
15840 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
15842 *input_line_pointer
= '/';
15843 input_line_pointer
+= 5;
15844 *input_line_pointer
= 0;
15852 arm_canonicalize_symbol_name (char * name
)
15856 if (thumb_mode
&& (len
= strlen (name
)) > 5
15857 && streq (name
+ len
- 5, "/data"))
15858 *(name
+ len
- 5) = 0;
15863 /* Table of all register names defined by default. The user can
15864 define additional names with .req. Note that all register names
15865 should appear in both upper and lowercase variants. Some registers
15866 also have mixed-case names. */
15868 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
15869 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
15870 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
15871 #define REGSET(p,t) \
15872 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
15873 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
15874 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
15875 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
15876 #define REGSETH(p,t) \
15877 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
15878 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
15879 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
15880 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
15881 #define REGSET2(p,t) \
15882 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
15883 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
15884 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
15885 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
15887 static const struct reg_entry reg_names
[] =
15889 /* ARM integer registers. */
15890 REGSET(r
, RN
), REGSET(R
, RN
),
15892 /* ATPCS synonyms. */
15893 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
15894 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
15895 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
15897 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
15898 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
15899 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
15901 /* Well-known aliases. */
15902 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
15903 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
15905 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
15906 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
15908 /* Coprocessor numbers. */
15909 REGSET(p
, CP
), REGSET(P
, CP
),
15911 /* Coprocessor register numbers. The "cr" variants are for backward
15913 REGSET(c
, CN
), REGSET(C
, CN
),
15914 REGSET(cr
, CN
), REGSET(CR
, CN
),
15916 /* FPA registers. */
15917 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
15918 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
15920 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
15921 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
15923 /* VFP SP registers. */
15924 REGSET(s
,VFS
), REGSET(S
,VFS
),
15925 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
15927 /* VFP DP Registers. */
15928 REGSET(d
,VFD
), REGSET(D
,VFD
),
15929 /* Extra Neon DP registers. */
15930 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
15932 /* Neon QP registers. */
15933 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
15935 /* VFP control registers. */
15936 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
15937 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
15938 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
15939 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
15940 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
15941 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
15943 /* Maverick DSP coprocessor registers. */
15944 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
15945 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
15947 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
15948 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
15949 REGDEF(dspsc
,0,DSPSC
),
15951 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
15952 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
15953 REGDEF(DSPSC
,0,DSPSC
),
15955 /* iWMMXt data registers - p0, c0-15. */
15956 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
15958 /* iWMMXt control registers - p1, c0-3. */
15959 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
15960 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
15961 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
15962 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
15964 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
15965 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
15966 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
15967 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
15968 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
15970 /* XScale accumulator registers. */
15971 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
15977 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
15978 within psr_required_here. */
15979 static const struct asm_psr psrs
[] =
15981 /* Backward compatibility notation. Note that "all" is no longer
15982 truly all possible PSR bits. */
15983 {"all", PSR_c
| PSR_f
},
15987 /* Individual flags. */
15992 /* Combinations of flags. */
15993 {"fs", PSR_f
| PSR_s
},
15994 {"fx", PSR_f
| PSR_x
},
15995 {"fc", PSR_f
| PSR_c
},
15996 {"sf", PSR_s
| PSR_f
},
15997 {"sx", PSR_s
| PSR_x
},
15998 {"sc", PSR_s
| PSR_c
},
15999 {"xf", PSR_x
| PSR_f
},
16000 {"xs", PSR_x
| PSR_s
},
16001 {"xc", PSR_x
| PSR_c
},
16002 {"cf", PSR_c
| PSR_f
},
16003 {"cs", PSR_c
| PSR_s
},
16004 {"cx", PSR_c
| PSR_x
},
16005 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16006 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16007 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16008 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16009 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16010 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16011 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16012 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16013 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16014 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16015 {"scf", PSR_s
| PSR_c
| PSR_f
},
16016 {"scx", PSR_s
| PSR_c
| PSR_x
},
16017 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16018 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16019 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16020 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16021 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16022 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16023 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16024 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16025 {"csf", PSR_c
| PSR_s
| PSR_f
},
16026 {"csx", PSR_c
| PSR_s
| PSR_x
},
16027 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16028 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16029 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16030 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16031 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16032 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16033 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16034 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16035 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16036 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16037 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16038 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16039 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16040 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16041 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16042 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16043 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16044 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16045 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16046 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16047 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16048 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16049 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16050 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16051 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16052 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16055 /* Table of V7M psr names. */
16056 static const struct asm_psr v7m_psrs
[] =
16058 {"apsr", 0 }, {"APSR", 0 },
16059 {"iapsr", 1 }, {"IAPSR", 1 },
16060 {"eapsr", 2 }, {"EAPSR", 2 },
16061 {"psr", 3 }, {"PSR", 3 },
16062 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16063 {"ipsr", 5 }, {"IPSR", 5 },
16064 {"epsr", 6 }, {"EPSR", 6 },
16065 {"iepsr", 7 }, {"IEPSR", 7 },
16066 {"msp", 8 }, {"MSP", 8 },
16067 {"psp", 9 }, {"PSP", 9 },
16068 {"primask", 16}, {"PRIMASK", 16},
16069 {"basepri", 17}, {"BASEPRI", 17},
16070 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16071 {"faultmask", 19}, {"FAULTMASK", 19},
16072 {"control", 20}, {"CONTROL", 20}
16075 /* Table of all shift-in-operand names. */
16076 static const struct asm_shift_name shift_names
[] =
16078 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16079 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16080 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16081 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16082 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16083 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16086 /* Table of all explicit relocation names. */
16088 static struct reloc_entry reloc_names
[] =
16090 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16091 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16092 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16093 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16094 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16095 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16096 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16097 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16098 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16099 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16100 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
16104 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16105 static const struct asm_cond conds
[] =
16109 {"cs", 0x2}, {"hs", 0x2},
16110 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16124 static struct asm_barrier_opt barrier_opt_names
[] =
16132 /* Table of ARM-format instructions. */
16134 /* Macros for gluing together operand strings. N.B. In all cases
16135 other than OPS0, the trailing OP_stop comes from default
16136 zero-initialization of the unspecified elements of the array. */
16137 #define OPS0() { OP_stop, }
16138 #define OPS1(a) { OP_##a, }
16139 #define OPS2(a,b) { OP_##a,OP_##b, }
16140 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16141 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16142 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16143 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16145 /* These macros abstract out the exact format of the mnemonic table and
16146 save some repeated characters. */
16148 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16149 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16150 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16151 THUMB_VARIANT, do_##ae, do_##te }
16153 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16154 a T_MNEM_xyz enumerator. */
16155 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16156 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16157 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16158 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16160 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16161 infix after the third character. */
16162 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16163 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16164 THUMB_VARIANT, do_##ae, do_##te }
16165 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16166 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16167 THUMB_VARIANT, do_##ae, do_##te }
16168 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16169 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16170 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16171 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16172 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16173 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16174 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16175 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16177 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16178 appear in the condition table. */
16179 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16180 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16181 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16183 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16184 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16185 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16186 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16187 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16188 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16189 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16190 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16191 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16192 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16193 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16194 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16195 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16196 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16197 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16198 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16199 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16200 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16201 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16202 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16204 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16205 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16206 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16207 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16209 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16210 field is still 0xE. Many of the Thumb variants can be executed
16211 conditionally, so this is checked separately. */
16212 #define TUE(mnem, op, top, nops, ops, ae, te) \
16213 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16214 THUMB_VARIANT, do_##ae, do_##te }
16216 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16217 condition code field. */
16218 #define TUF(mnem, op, top, nops, ops, ae, te) \
16219 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16220 THUMB_VARIANT, do_##ae, do_##te }
16222 /* ARM-only variants of all the above. */
16223 #define CE(mnem, op, nops, ops, ae) \
16224 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16226 #define C3(mnem, op, nops, ops, ae) \
16227 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16229 /* Legacy mnemonics that always have conditional infix after the third
16231 #define CL(mnem, op, nops, ops, ae) \
16232 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16233 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16235 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16236 #define cCE(mnem, op, nops, ops, ae) \
16237 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16239 /* Legacy coprocessor instructions where conditional infix and conditional
16240 suffix are ambiguous. For consistency this includes all FPA instructions,
16241 not just the potentially ambiguous ones. */
16242 #define cCL(mnem, op, nops, ops, ae) \
16243 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16244 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16246 /* Coprocessor, takes either a suffix or a position-3 infix
16247 (for an FPA corner case). */
16248 #define C3E(mnem, op, nops, ops, ae) \
16249 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16250 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16252 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16253 { m1 #m2 m3, OPS##nops ops, \
16254 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16255 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16257 #define CM(m1, m2, op, nops, ops, ae) \
16258 xCM_ (m1, , m2, op, nops, ops, ae), \
16259 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16260 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16261 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16262 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16263 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16264 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16265 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16266 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16267 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16268 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16269 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16270 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16271 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16272 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16273 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16274 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16275 xCM_ (m1, le, m2, op, nops, ops, ae), \
16276 xCM_ (m1, al, m2, op, nops, ops, ae)
16278 #define UE(mnem, op, nops, ops, ae) \
16279 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16281 #define UF(mnem, op, nops, ops, ae) \
16282 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16284 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16285 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16286 use the same encoding function for each. */
16287 #define NUF(mnem, op, nops, ops, enc) \
16288 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16289 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16291 /* Neon data processing, version which indirects through neon_enc_tab for
16292 the various overloaded versions of opcodes. */
16293 #define nUF(mnem, op, nops, ops, enc) \
16294 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16295 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16297 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16299 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16300 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16301 THUMB_VARIANT, do_##enc, do_##enc }
16303 #define NCE(mnem, op, nops, ops, enc) \
16304 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16306 #define NCEF(mnem, op, nops, ops, enc) \
16307 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16309 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16310 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16311 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16312 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16314 #define nCE(mnem, op, nops, ops, enc) \
16315 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16317 #define nCEF(mnem, op, nops, ops, enc) \
16318 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16322 /* Thumb-only, unconditional. */
16323 #define UT(mnem, op, nops, ops, te) TUE (mnem, 0, op, nops, ops, 0, te)
16325 static const struct asm_opcode insns
[] =
16327 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16328 #define THUMB_VARIANT &arm_ext_v4t
16329 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16330 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16331 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16332 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16333 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16334 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16335 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16336 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16337 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16338 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16339 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16340 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16341 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16342 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16343 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16344 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16346 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16347 for setting PSR flag bits. They are obsolete in V6 and do not
16348 have Thumb equivalents. */
16349 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16350 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16351 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16352 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16353 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16354 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16355 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16356 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16357 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16359 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16360 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16361 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16362 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16364 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16365 tC3("ldrb", 4500000, _ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16366 tCE("str", 4000000, _str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16367 tC3("strb", 4400000, _strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16369 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16370 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16371 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16372 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16373 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16374 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16376 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16377 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16378 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16379 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16382 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16383 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16384 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16386 /* Thumb-compatibility pseudo ops. */
16387 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16388 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16389 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16390 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16391 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16392 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16393 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16394 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16395 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16396 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16397 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16398 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16400 /* These may simplify to neg. */
16401 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16402 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16404 #undef THUMB_VARIANT
16405 #define THUMB_VARIANT & arm_ext_v6
16407 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16409 /* V1 instructions with no Thumb analogue prior to V6T2. */
16410 #undef THUMB_VARIANT
16411 #define THUMB_VARIANT & arm_ext_v6t2
16413 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16414 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16415 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16417 TC3("ldrt", 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16418 TC3("ldrbt", 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16419 TC3("strt", 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16420 TC3("strbt", 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16422 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16423 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16425 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16426 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16428 /* V1 instructions with no Thumb analogue at all. */
16429 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16430 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16432 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16433 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16434 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16435 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16436 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16437 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16438 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16439 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16442 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16443 #undef THUMB_VARIANT
16444 #define THUMB_VARIANT & arm_ext_v4t
16446 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16447 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16449 #undef THUMB_VARIANT
16450 #define THUMB_VARIANT & arm_ext_v6t2
16452 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16453 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16455 /* Generic coprocessor instructions. */
16456 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16457 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16458 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16459 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16460 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16461 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16462 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16465 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16467 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16468 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16471 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16472 #undef THUMB_VARIANT
16473 #define THUMB_VARIANT & arm_ext_msr
16475 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16476 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16479 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16480 #undef THUMB_VARIANT
16481 #define THUMB_VARIANT & arm_ext_v6t2
16483 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16484 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16485 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16486 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16487 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16488 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16489 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16490 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16493 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16494 #undef THUMB_VARIANT
16495 #define THUMB_VARIANT & arm_ext_v4t
16497 tC3("ldrh", 01000b0
, _ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16498 tC3("strh", 00000b0
, _strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16499 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16500 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16501 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16502 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16505 #define ARM_VARIANT & arm_ext_v4t_5
16507 /* ARM Architecture 4T. */
16508 /* Note: bx (and blx) are required on V5, even if the processor does
16509 not support Thumb. */
16510 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16513 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16514 #undef THUMB_VARIANT
16515 #define THUMB_VARIANT & arm_ext_v5t
16517 /* Note: blx has 2 variants; the .value coded here is for
16518 BLX(2). Only this variant has conditional execution. */
16519 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16520 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16522 #undef THUMB_VARIANT
16523 #define THUMB_VARIANT & arm_ext_v6t2
16525 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16526 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16527 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16528 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16529 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16530 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16531 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16532 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16535 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16536 #undef THUMB_VARIANT
16537 #define THUMB_VARIANT &arm_ext_v5exp
16539 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16540 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16541 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16542 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16544 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16545 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16547 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16548 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16549 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16550 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16552 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16553 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16554 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16555 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16557 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16558 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16560 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16561 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16562 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16563 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16566 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16567 #undef THUMB_VARIANT
16568 #define THUMB_VARIANT &arm_ext_v6t2
16570 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16571 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16572 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16574 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16575 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16578 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16580 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16583 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16584 #undef THUMB_VARIANT
16585 #define THUMB_VARIANT & arm_ext_v6
16587 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16588 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16589 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16590 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16591 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16592 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16593 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16594 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16595 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16596 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16598 #undef THUMB_VARIANT
16599 #define THUMB_VARIANT & arm_ext_v6t2
16601 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
16602 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
16603 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16604 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16606 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16607 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16609 /* ARM V6 not included in V7M. */
16610 #undef THUMB_VARIANT
16611 #define THUMB_VARIANT & arm_ext_v6_notm
16612 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16613 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16614 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16615 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16616 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16617 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16618 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16619 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16620 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16621 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16622 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16623 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16625 /* ARM V6 not included in V7M (eg. integer SIMD). */
16626 #undef THUMB_VARIANT
16627 #define THUMB_VARIANT & arm_ext_v6_dsp
16628 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16629 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16630 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16631 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16632 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16633 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16634 /* Old name for QASX. */
16635 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16636 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16637 /* Old name for QSAX. */
16638 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16639 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16640 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16641 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16642 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16643 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16644 /* Old name for SASX. */
16645 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16646 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16647 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16648 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16649 /* Old name for SHASX. */
16650 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16651 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16652 /* Old name for SHSAX. */
16653 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16654 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16655 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16656 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16657 /* Old name for SSAX. */
16658 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16659 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16660 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16661 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16662 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16663 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16664 /* Old name for UASX. */
16665 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16666 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16667 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16668 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16669 /* Old name for UHASX. */
16670 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16671 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16672 /* Old name for UHSAX. */
16673 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16674 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16675 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16676 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16677 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16678 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16679 /* Old name for UQASX. */
16680 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16681 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16682 /* Old name for UQSAX. */
16683 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16684 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16685 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16686 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16687 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16688 /* Old name for USAX. */
16689 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16690 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16691 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16692 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16693 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16694 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16695 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16696 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16697 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16698 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16699 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16700 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16701 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16702 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16703 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16704 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16705 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16706 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16707 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16708 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16709 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16710 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16711 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16712 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16713 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16714 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16715 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16716 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16717 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16718 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16719 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16720 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16721 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16722 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16725 #define ARM_VARIANT & arm_ext_v6k
16726 #undef THUMB_VARIANT
16727 #define THUMB_VARIANT & arm_ext_v6k
16729 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
16730 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
16731 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
16732 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
16734 #undef THUMB_VARIANT
16735 #define THUMB_VARIANT & arm_ext_v6_notm
16737 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
16738 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
16740 #undef THUMB_VARIANT
16741 #define THUMB_VARIANT & arm_ext_v6t2
16743 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16744 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16745 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16746 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16747 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16750 #define ARM_VARIANT & arm_ext_v6z
16752 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16755 #define ARM_VARIANT & arm_ext_v6t2
16757 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16758 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16759 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16760 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16762 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16763 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16764 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16765 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
16767 TC3("ldrht", 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16768 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16769 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16770 TC3("strht", 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16772 UT("cbnz", b900
, 2, (RR
, EXP
), t_cbz
),
16773 UT("cbz", b100
, 2, (RR
, EXP
), t_cbz
),
16775 /* ARM does not really have an IT instruction, so always allow it.
16776 The opcode is copied from Thumb in order to allow warnings in
16777 -mimplicit-it=[never | arm] modes. */
16779 #define ARM_VARIANT & arm_ext_v1
16781 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
16782 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
16783 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
16784 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
16785 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
16786 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
16787 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
16788 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
16789 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
16790 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
16791 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
16792 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
16793 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
16794 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
16795 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
16796 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
16797 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16798 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16800 /* Thumb2 only instructions. */
16802 #define ARM_VARIANT NULL
16804 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16805 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16806 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16807 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16808 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
16809 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
16811 /* Thumb-2 hardware division instructions (R and M profiles only). */
16812 #undef THUMB_VARIANT
16813 #define THUMB_VARIANT & arm_ext_div
16815 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16816 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16818 /* ARM V6M/V7 instructions. */
16820 #define ARM_VARIANT & arm_ext_barrier
16821 #undef THUMB_VARIANT
16822 #define THUMB_VARIANT & arm_ext_barrier
16824 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
16825 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
16826 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
16828 /* ARM V7 instructions. */
16830 #define ARM_VARIANT & arm_ext_v7
16831 #undef THUMB_VARIANT
16832 #define THUMB_VARIANT & arm_ext_v7
16834 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
16835 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
16838 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
16840 cCE("wfs", e200110
, 1, (RR
), rd
),
16841 cCE("rfs", e300110
, 1, (RR
), rd
),
16842 cCE("wfc", e400110
, 1, (RR
), rd
),
16843 cCE("rfc", e500110
, 1, (RR
), rd
),
16845 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16846 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16847 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16848 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16850 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16851 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16852 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16853 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16855 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
16856 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
16857 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
16858 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
16859 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
16860 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
16861 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
16862 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
16863 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
16864 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
16865 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
16866 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
16868 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
16869 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
16870 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
16871 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
16872 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
16873 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
16874 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
16875 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
16876 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
16877 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
16878 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
16879 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
16881 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
16882 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
16883 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
16884 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
16885 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
16886 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
16887 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
16888 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
16889 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
16890 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
16891 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
16892 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
16894 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
16895 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
16896 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
16897 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
16898 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
16899 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
16900 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
16901 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
16902 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
16903 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
16904 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
16905 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
16907 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
16908 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
16909 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
16910 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
16911 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
16912 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
16913 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
16914 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
16915 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
16916 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
16917 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
16918 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
16920 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
16921 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
16922 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
16923 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
16924 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
16925 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
16926 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
16927 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
16928 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
16929 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
16930 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
16931 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
16933 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
16934 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
16935 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
16936 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
16937 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
16938 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
16939 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
16940 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
16941 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
16942 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
16943 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
16944 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
16946 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
16947 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
16948 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
16949 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
16950 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
16951 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
16952 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
16953 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
16954 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
16955 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
16956 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
16957 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
16959 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
16960 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
16961 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
16962 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
16963 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
16964 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
16965 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
16966 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
16967 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
16968 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
16969 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
16970 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
16972 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
16973 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
16974 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
16975 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
16976 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
16977 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
16978 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
16979 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
16980 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
16981 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
16982 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
16983 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
16985 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
16986 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
16987 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
16988 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
16989 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
16990 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
16991 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
16992 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
16993 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
16994 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
16995 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
16996 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
16998 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
16999 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17000 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17001 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17002 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17003 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17004 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17005 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17006 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17007 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17008 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17009 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17011 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17012 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17013 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17014 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17015 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17016 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17017 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17018 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17019 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17020 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17021 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17022 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17024 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17025 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17026 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17027 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17028 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17029 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17030 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17031 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17032 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17033 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17034 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17035 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17037 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17038 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17039 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17040 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17041 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17042 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17043 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17044 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17045 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17046 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17047 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17048 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17050 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17051 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17052 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17053 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17054 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17055 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17056 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17057 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17058 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17059 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17060 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17061 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17063 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17064 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17065 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17066 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17067 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17068 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17069 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17070 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17071 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17072 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17073 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17074 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17076 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17077 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17078 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17079 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17080 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17081 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17082 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17083 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17084 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17085 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17086 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17087 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17089 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17090 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17091 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17092 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17093 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17094 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17095 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17096 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17097 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17098 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17099 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17100 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17102 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17103 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17104 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17105 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17106 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17107 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17108 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17109 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17110 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17111 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17112 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17113 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17115 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17116 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17117 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17118 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17119 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17120 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17121 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17122 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17123 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17124 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17125 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17126 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17128 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17129 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17130 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17131 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17132 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17133 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17134 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17135 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17136 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17137 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17138 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17139 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17141 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17142 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17143 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17144 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17145 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17146 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17147 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17148 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17149 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17150 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17151 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17152 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17154 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17155 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17156 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17157 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17158 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17159 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17160 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17161 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17162 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17163 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17164 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17165 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17167 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17168 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17169 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17170 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17171 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17172 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17173 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17174 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17175 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17176 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17177 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17178 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17180 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17181 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17182 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17183 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17184 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17185 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17186 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17187 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17188 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17189 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17190 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17191 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17193 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17194 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17195 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17196 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17197 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17198 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17199 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17200 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17201 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17202 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17203 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17204 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17206 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17207 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17208 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17209 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17210 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17211 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17212 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17213 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17214 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17215 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17216 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17217 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17219 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17220 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17221 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17222 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17223 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17224 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17225 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17226 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17227 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17228 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17229 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17230 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17232 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17233 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17234 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17235 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17237 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17238 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17239 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17240 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17241 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17242 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17243 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17244 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17245 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17246 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17247 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17248 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17250 /* The implementation of the FIX instruction is broken on some
17251 assemblers, in that it accepts a precision specifier as well as a
17252 rounding specifier, despite the fact that this is meaningless.
17253 To be more compatible, we accept it as well, though of course it
17254 does not set any bits. */
17255 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17256 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17257 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17258 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17259 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17260 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17261 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17262 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17263 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17264 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17265 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17266 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17267 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17269 /* Instructions that were new with the real FPA, call them V2. */
17271 #define ARM_VARIANT & fpu_fpa_ext_v2
17273 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17274 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17275 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17276 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17277 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17278 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17281 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17283 /* Moves and type conversions. */
17284 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17285 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17286 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17287 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17288 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17289 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17290 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17291 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17292 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17293 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17294 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17295 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17296 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17297 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17299 /* Memory operations. */
17300 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17301 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17302 cCE("fldmias", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17303 cCE("fldmfds", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17304 cCE("fldmdbs", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17305 cCE("fldmeas", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17306 cCE("fldmiax", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17307 cCE("fldmfdx", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17308 cCE("fldmdbx", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17309 cCE("fldmeax", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17310 cCE("fstmias", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17311 cCE("fstmeas", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17312 cCE("fstmdbs", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17313 cCE("fstmfds", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17314 cCE("fstmiax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17315 cCE("fstmeax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17316 cCE("fstmdbx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17317 cCE("fstmfdx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17319 /* Monadic operations. */
17320 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17321 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17322 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17324 /* Dyadic operations. */
17325 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17326 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17327 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17328 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17329 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17330 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17331 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17332 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17333 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17336 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17337 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17338 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17339 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17341 /* Double precision load/store are still present on single precision
17342 implementations. */
17343 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17344 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17345 cCE("fldmiad", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17346 cCE("fldmfdd", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17347 cCE("fldmdbd", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17348 cCE("fldmead", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17349 cCE("fstmiad", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17350 cCE("fstmead", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17351 cCE("fstmdbd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17352 cCE("fstmfdd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17355 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17357 /* Moves and type conversions. */
17358 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17359 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17360 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17361 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17362 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17363 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17364 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17365 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17366 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17367 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17368 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17369 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17370 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17372 /* Monadic operations. */
17373 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17374 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17375 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17377 /* Dyadic operations. */
17378 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17379 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17380 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17381 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17382 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17383 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17384 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17385 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17386 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17389 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17390 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17391 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17392 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17395 #define ARM_VARIANT & fpu_vfp_ext_v2
17397 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17398 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17399 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17400 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17402 /* Instructions which may belong to either the Neon or VFP instruction sets.
17403 Individual encoder functions perform additional architecture checks. */
17405 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17406 #undef THUMB_VARIANT
17407 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17409 /* These mnemonics are unique to VFP. */
17410 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17411 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17412 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17413 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17414 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17415 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17416 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17417 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17418 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17419 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17421 /* Mnemonics shared by Neon and VFP. */
17422 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17423 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17424 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17426 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17427 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17429 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17430 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17432 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17433 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17434 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17435 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17436 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17437 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17438 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17439 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17441 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17442 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17443 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17444 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17447 /* NOTE: All VMOV encoding is special-cased! */
17448 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17449 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17451 #undef THUMB_VARIANT
17452 #define THUMB_VARIANT & fpu_neon_ext_v1
17454 #define ARM_VARIANT & fpu_neon_ext_v1
17456 /* Data processing with three registers of the same length. */
17457 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17458 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17459 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17460 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17461 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17462 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17463 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17464 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17465 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17466 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17467 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17468 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17469 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17470 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17471 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17472 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17473 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17474 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17475 /* If not immediate, fall back to neon_dyadic_i64_su.
17476 shl_imm should accept I8 I16 I32 I64,
17477 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17478 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17479 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17480 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17481 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17482 /* Logic ops, types optional & ignored. */
17483 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17484 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17485 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17486 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17487 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17488 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17489 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17490 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17491 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17492 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17493 /* Bitfield ops, untyped. */
17494 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17495 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17496 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17497 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17498 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17499 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17500 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17501 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17502 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17503 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17504 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17505 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17506 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17507 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17508 back to neon_dyadic_if_su. */
17509 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17510 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17511 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17512 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17513 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17514 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17515 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17516 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17517 /* Comparison. Type I8 I16 I32 F32. */
17518 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17519 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17520 /* As above, D registers only. */
17521 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17522 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17523 /* Int and float variants, signedness unimportant. */
17524 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17525 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17526 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17527 /* Add/sub take types I8 I16 I32 I64 F32. */
17528 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17529 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17530 /* vtst takes sizes 8, 16, 32. */
17531 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17532 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17533 /* VMUL takes I8 I16 I32 F32 P8. */
17534 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17535 /* VQD{R}MULH takes S16 S32. */
17536 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17537 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17538 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17539 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17540 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17541 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17542 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17543 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17544 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17545 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17546 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17547 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17548 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17549 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17550 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17551 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17553 /* Two address, int/float. Types S8 S16 S32 F32. */
17554 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17555 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17557 /* Data processing with two registers and a shift amount. */
17558 /* Right shifts, and variants with rounding.
17559 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17560 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17561 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17562 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17563 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17564 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17565 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17566 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17567 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17568 /* Shift and insert. Sizes accepted 8 16 32 64. */
17569 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17570 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17571 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17572 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17573 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17574 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17575 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17576 /* Right shift immediate, saturating & narrowing, with rounding variants.
17577 Types accepted S16 S32 S64 U16 U32 U64. */
17578 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17579 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17580 /* As above, unsigned. Types accepted S16 S32 S64. */
17581 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17582 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17583 /* Right shift narrowing. Types accepted I16 I32 I64. */
17584 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17585 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17586 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17587 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17588 /* CVT with optional immediate for fixed-point variant. */
17589 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17591 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
17592 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
17594 /* Data processing, three registers of different lengths. */
17595 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17596 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17597 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17598 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17599 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17600 /* If not scalar, fall back to neon_dyadic_long.
17601 Vector types as above, scalar types S16 S32 U16 U32. */
17602 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17603 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17604 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17605 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17606 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17607 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17608 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17609 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17610 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17611 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17612 /* Saturating doubling multiplies. Types S16 S32. */
17613 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17614 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17615 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17616 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17617 S16 S32 U16 U32. */
17618 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17620 /* Extract. Size 8. */
17621 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17622 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17624 /* Two registers, miscellaneous. */
17625 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17626 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17627 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17628 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17629 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17630 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17631 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17632 /* Vector replicate. Sizes 8 16 32. */
17633 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17634 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17635 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17636 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17637 /* VMOVN. Types I16 I32 I64. */
17638 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17639 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17640 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17641 /* VQMOVUN. Types S16 S32 S64. */
17642 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17643 /* VZIP / VUZP. Sizes 8 16 32. */
17644 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17645 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17646 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17647 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17648 /* VQABS / VQNEG. Types S8 S16 S32. */
17649 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17650 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17651 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17652 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17653 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17654 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17655 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17656 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17657 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17658 /* Reciprocal estimates. Types U32 F32. */
17659 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17660 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17661 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17662 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17663 /* VCLS. Types S8 S16 S32. */
17664 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17665 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17666 /* VCLZ. Types I8 I16 I32. */
17667 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17668 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17669 /* VCNT. Size 8. */
17670 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17671 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17672 /* Two address, untyped. */
17673 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17674 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17675 /* VTRN. Sizes 8 16 32. */
17676 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17677 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17679 /* Table lookup. Size 8. */
17680 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17681 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17683 #undef THUMB_VARIANT
17684 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17686 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17688 /* Neon element/structure load/store. */
17689 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17690 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17691 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17692 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17693 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17694 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17695 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17696 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17698 #undef THUMB_VARIANT
17699 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
17701 #define ARM_VARIANT &fpu_vfp_ext_v3xd
17702 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17703 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17704 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17705 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17706 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17707 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17708 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17709 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17710 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17712 #undef THUMB_VARIANT
17713 #define THUMB_VARIANT & fpu_vfp_ext_v3
17715 #define ARM_VARIANT & fpu_vfp_ext_v3
17717 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17718 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17719 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17720 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17721 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17722 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17723 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17724 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17725 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17728 #define ARM_VARIANT &fpu_vfp_ext_fma
17729 #undef THUMB_VARIANT
17730 #define THUMB_VARIANT &fpu_vfp_ext_fma
17731 /* Mnemonics shared by Neon and VFP. These are included in the
17732 VFP FMA variant; NEON and VFP FMA always includes the NEON
17733 FMA instructions. */
17734 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17735 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17736 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
17737 the v form should always be used. */
17738 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17739 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17740 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17741 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17742 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17743 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17745 #undef THUMB_VARIANT
17747 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17749 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17750 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17751 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17752 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17753 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17754 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17755 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17756 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17759 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17761 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
17762 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
17763 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
17764 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
17765 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
17766 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
17767 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
17768 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
17769 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
17770 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17771 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17772 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17773 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17774 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17775 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17776 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17777 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17778 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17779 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
17780 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
17781 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17782 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17783 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17784 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17785 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17786 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17787 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
17788 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
17789 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
17790 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
17791 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
17792 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
17793 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
17794 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
17795 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17796 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17797 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17798 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17799 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17800 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17801 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17802 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17803 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17804 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17805 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17806 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17807 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
17808 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17809 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17810 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17811 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17812 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17813 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17814 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17815 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17816 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17817 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17818 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17819 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17820 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17821 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17822 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17823 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17824 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17825 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17826 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17827 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17828 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17829 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17830 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17831 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17832 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17833 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17834 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17835 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17836 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17837 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17838 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17839 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17840 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17841 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17842 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17843 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17844 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17845 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17846 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17847 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17848 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17849 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
17850 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17851 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17852 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17853 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17854 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17855 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17856 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17857 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17858 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17859 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17860 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17861 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17862 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17863 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17864 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17865 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17866 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17867 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17868 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17869 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17870 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17871 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
17872 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17873 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17874 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17875 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17876 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17877 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17878 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17879 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17880 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17881 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17882 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17883 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17884 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17885 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17886 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17887 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17888 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17889 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17890 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17891 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17892 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17893 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17894 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17895 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17896 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17897 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17898 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17899 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17900 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17901 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17902 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17903 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17904 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17905 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17906 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17907 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17908 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17909 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17910 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17911 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17912 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17913 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17914 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17915 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17916 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17917 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17918 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17919 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17920 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17921 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17922 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
17925 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
17927 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
17928 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
17929 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
17930 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17931 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17932 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17933 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17934 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17935 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17936 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17937 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17938 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17939 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17940 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17941 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17942 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17943 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17944 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17945 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17946 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17947 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
17948 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17949 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17950 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17951 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17952 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17953 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17954 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17955 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17956 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17957 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17958 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17959 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17960 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17961 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17962 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17963 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17964 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17965 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17966 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17967 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17968 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17969 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17970 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17971 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17972 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17973 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17974 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17975 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17976 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17977 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17978 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17979 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17980 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17981 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17982 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17983 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17986 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
17988 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17989 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17990 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17991 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17992 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17993 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17994 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17995 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17996 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
17997 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
17998 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
17999 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18000 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18001 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18002 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18003 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18004 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18005 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18006 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18007 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18008 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18009 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18010 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18011 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18012 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18013 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18014 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18015 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18016 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18017 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18018 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18019 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18020 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18021 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18022 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18023 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18024 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18025 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18026 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18027 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18028 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18029 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18030 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18031 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18032 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18033 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18034 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18035 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18036 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18037 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18038 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18039 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18040 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18041 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18042 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18043 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18044 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18045 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18046 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18047 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18048 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18049 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18050 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18051 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18052 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18053 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18054 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18055 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18056 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18057 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18058 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18059 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18060 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18061 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18062 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18063 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18066 #undef THUMB_VARIANT
18093 /* MD interface: bits in the object file. */
18095 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18096 for use in the a.out file, and stores them in the array pointed to by buf.
18097 This knows about the endian-ness of the target machine and does
18098 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18099 2 (short) and 4 (long) Floating numbers are put out as a series of
18100 LITTLENUMS (shorts, here at least). */
18103 md_number_to_chars (char * buf
, valueT val
, int n
)
18105 if (target_big_endian
)
18106 number_to_chars_bigendian (buf
, val
, n
);
18108 number_to_chars_littleendian (buf
, val
, n
);
18112 md_chars_to_number (char * buf
, int n
)
18115 unsigned char * where
= (unsigned char *) buf
;
18117 if (target_big_endian
)
18122 result
|= (*where
++ & 255);
18130 result
|= (where
[n
] & 255);
18137 /* MD interface: Sections. */
18139 /* Estimate the size of a frag before relaxing. Assume everything fits in
18143 md_estimate_size_before_relax (fragS
* fragp
,
18144 segT segtype ATTRIBUTE_UNUSED
)
18150 /* Convert a machine dependent frag. */
18153 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18155 unsigned long insn
;
18156 unsigned long old_op
;
18164 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18166 old_op
= bfd_get_16(abfd
, buf
);
18167 if (fragp
->fr_symbol
)
18169 exp
.X_op
= O_symbol
;
18170 exp
.X_add_symbol
= fragp
->fr_symbol
;
18174 exp
.X_op
= O_constant
;
18176 exp
.X_add_number
= fragp
->fr_offset
;
18177 opcode
= fragp
->fr_subtype
;
18180 case T_MNEM_ldr_pc
:
18181 case T_MNEM_ldr_pc2
:
18182 case T_MNEM_ldr_sp
:
18183 case T_MNEM_str_sp
:
18190 if (fragp
->fr_var
== 4)
18192 insn
= THUMB_OP32 (opcode
);
18193 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18195 insn
|= (old_op
& 0x700) << 4;
18199 insn
|= (old_op
& 7) << 12;
18200 insn
|= (old_op
& 0x38) << 13;
18202 insn
|= 0x00000c00;
18203 put_thumb32_insn (buf
, insn
);
18204 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18208 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18210 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18213 if (fragp
->fr_var
== 4)
18215 insn
= THUMB_OP32 (opcode
);
18216 insn
|= (old_op
& 0xf0) << 4;
18217 put_thumb32_insn (buf
, insn
);
18218 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18222 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18223 exp
.X_add_number
-= 4;
18231 if (fragp
->fr_var
== 4)
18233 int r0off
= (opcode
== T_MNEM_mov
18234 || opcode
== T_MNEM_movs
) ? 0 : 8;
18235 insn
= THUMB_OP32 (opcode
);
18236 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18237 insn
|= (old_op
& 0x700) << r0off
;
18238 put_thumb32_insn (buf
, insn
);
18239 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18243 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18248 if (fragp
->fr_var
== 4)
18250 insn
= THUMB_OP32(opcode
);
18251 put_thumb32_insn (buf
, insn
);
18252 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18255 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18259 if (fragp
->fr_var
== 4)
18261 insn
= THUMB_OP32(opcode
);
18262 insn
|= (old_op
& 0xf00) << 14;
18263 put_thumb32_insn (buf
, insn
);
18264 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18267 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18270 case T_MNEM_add_sp
:
18271 case T_MNEM_add_pc
:
18272 case T_MNEM_inc_sp
:
18273 case T_MNEM_dec_sp
:
18274 if (fragp
->fr_var
== 4)
18276 /* ??? Choose between add and addw. */
18277 insn
= THUMB_OP32 (opcode
);
18278 insn
|= (old_op
& 0xf0) << 4;
18279 put_thumb32_insn (buf
, insn
);
18280 if (opcode
== T_MNEM_add_pc
)
18281 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18283 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18286 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18294 if (fragp
->fr_var
== 4)
18296 insn
= THUMB_OP32 (opcode
);
18297 insn
|= (old_op
& 0xf0) << 4;
18298 insn
|= (old_op
& 0xf) << 16;
18299 put_thumb32_insn (buf
, insn
);
18300 if (insn
& (1 << 20))
18301 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18303 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18306 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18312 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18313 (enum bfd_reloc_code_real
) reloc_type
);
18314 fixp
->fx_file
= fragp
->fr_file
;
18315 fixp
->fx_line
= fragp
->fr_line
;
18316 fragp
->fr_fix
+= fragp
->fr_var
;
18319 /* Return the size of a relaxable immediate operand instruction.
18320 SHIFT and SIZE specify the form of the allowable immediate. */
18322 relax_immediate (fragS
*fragp
, int size
, int shift
)
18328 /* ??? Should be able to do better than this. */
18329 if (fragp
->fr_symbol
)
18332 low
= (1 << shift
) - 1;
18333 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18334 offset
= fragp
->fr_offset
;
18335 /* Force misaligned offsets to 32-bit variant. */
18338 if (offset
& ~mask
)
18343 /* Get the address of a symbol during relaxation. */
18345 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18351 sym
= fragp
->fr_symbol
;
18352 sym_frag
= symbol_get_frag (sym
);
18353 know (S_GET_SEGMENT (sym
) != absolute_section
18354 || sym_frag
== &zero_address_frag
);
18355 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18357 /* If frag has yet to be reached on this pass, assume it will
18358 move by STRETCH just as we did. If this is not so, it will
18359 be because some frag between grows, and that will force
18363 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18367 /* Adjust stretch for any alignment frag. Note that if have
18368 been expanding the earlier code, the symbol may be
18369 defined in what appears to be an earlier frag. FIXME:
18370 This doesn't handle the fr_subtype field, which specifies
18371 a maximum number of bytes to skip when doing an
18373 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18375 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18378 stretch
= - ((- stretch
)
18379 & ~ ((1 << (int) f
->fr_offset
) - 1));
18381 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18393 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18396 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18401 /* Assume worst case for symbols not known to be in the same section. */
18402 if (fragp
->fr_symbol
== NULL
18403 || !S_IS_DEFINED (fragp
->fr_symbol
)
18404 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18407 val
= relaxed_symbol_addr (fragp
, stretch
);
18408 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18409 addr
= (addr
+ 4) & ~3;
18410 /* Force misaligned targets to 32-bit variant. */
18414 if (val
< 0 || val
> 1020)
18419 /* Return the size of a relaxable add/sub immediate instruction. */
18421 relax_addsub (fragS
*fragp
, asection
*sec
)
18426 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18427 op
= bfd_get_16(sec
->owner
, buf
);
18428 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18429 return relax_immediate (fragp
, 8, 0);
18431 return relax_immediate (fragp
, 3, 0);
18435 /* Return the size of a relaxable branch instruction. BITS is the
18436 size of the offset field in the narrow instruction. */
18439 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18445 /* Assume worst case for symbols not known to be in the same section. */
18446 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18447 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18451 if (S_IS_DEFINED (fragp
->fr_symbol
)
18452 && ARM_IS_FUNC (fragp
->fr_symbol
))
18456 val
= relaxed_symbol_addr (fragp
, stretch
);
18457 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18460 /* Offset is a signed value *2 */
18462 if (val
>= limit
|| val
< -limit
)
18468 /* Relax a machine dependent frag. This returns the amount by which
18469 the current size of the frag should change. */
18472 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18477 oldsize
= fragp
->fr_var
;
18478 switch (fragp
->fr_subtype
)
18480 case T_MNEM_ldr_pc2
:
18481 newsize
= relax_adr (fragp
, sec
, stretch
);
18483 case T_MNEM_ldr_pc
:
18484 case T_MNEM_ldr_sp
:
18485 case T_MNEM_str_sp
:
18486 newsize
= relax_immediate (fragp
, 8, 2);
18490 newsize
= relax_immediate (fragp
, 5, 2);
18494 newsize
= relax_immediate (fragp
, 5, 1);
18498 newsize
= relax_immediate (fragp
, 5, 0);
18501 newsize
= relax_adr (fragp
, sec
, stretch
);
18507 newsize
= relax_immediate (fragp
, 8, 0);
18510 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18513 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18515 case T_MNEM_add_sp
:
18516 case T_MNEM_add_pc
:
18517 newsize
= relax_immediate (fragp
, 8, 2);
18519 case T_MNEM_inc_sp
:
18520 case T_MNEM_dec_sp
:
18521 newsize
= relax_immediate (fragp
, 7, 2);
18527 newsize
= relax_addsub (fragp
, sec
);
18533 fragp
->fr_var
= newsize
;
18534 /* Freeze wide instructions that are at or before the same location as
18535 in the previous pass. This avoids infinite loops.
18536 Don't freeze them unconditionally because targets may be artificially
18537 misaligned by the expansion of preceding frags. */
18538 if (stretch
<= 0 && newsize
> 2)
18540 md_convert_frag (sec
->owner
, sec
, fragp
);
18544 return newsize
- oldsize
;
18547 /* Round up a section size to the appropriate boundary. */
18550 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18553 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18554 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18556 /* For a.out, force the section size to be aligned. If we don't do
18557 this, BFD will align it for us, but it will not write out the
18558 final bytes of the section. This may be a bug in BFD, but it is
18559 easier to fix it here since that is how the other a.out targets
18563 align
= bfd_get_section_alignment (stdoutput
, segment
);
18564 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18571 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18572 of an rs_align_code fragment. */
18575 arm_handle_align (fragS
* fragP
)
18577 static char const arm_noop
[2][2][4] =
18580 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18581 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18584 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18585 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18588 static char const thumb_noop
[2][2][2] =
18591 {0xc0, 0x46}, /* LE */
18592 {0x46, 0xc0}, /* BE */
18595 {0x00, 0xbf}, /* LE */
18596 {0xbf, 0x00} /* BE */
18599 static char const wide_thumb_noop
[2][4] =
18600 { /* Wide Thumb-2 */
18601 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18602 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18605 unsigned bytes
, fix
, noop_size
;
18608 const char *narrow_noop
= NULL
;
18613 if (fragP
->fr_type
!= rs_align_code
)
18616 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18617 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18620 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18621 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18623 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18625 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18627 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18629 narrow_noop
= thumb_noop
[1][target_big_endian
];
18630 noop
= wide_thumb_noop
[target_big_endian
];
18633 noop
= thumb_noop
[0][target_big_endian
];
18641 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18642 [target_big_endian
];
18649 fragP
->fr_var
= noop_size
;
18651 if (bytes
& (noop_size
- 1))
18653 fix
= bytes
& (noop_size
- 1);
18655 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18657 memset (p
, 0, fix
);
18664 if (bytes
& noop_size
)
18666 /* Insert a narrow noop. */
18667 memcpy (p
, narrow_noop
, noop_size
);
18669 bytes
-= noop_size
;
18673 /* Use wide noops for the remainder */
18677 while (bytes
>= noop_size
)
18679 memcpy (p
, noop
, noop_size
);
18681 bytes
-= noop_size
;
18685 fragP
->fr_fix
+= fix
;
18688 /* Called from md_do_align. Used to create an alignment
18689 frag in a code section. */
18692 arm_frag_align_code (int n
, int max
)
18696 /* We assume that there will never be a requirement
18697 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18698 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18703 _("alignments greater than %d bytes not supported in .text sections."),
18704 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18705 as_fatal ("%s", err_msg
);
18708 p
= frag_var (rs_align_code
,
18709 MAX_MEM_FOR_RS_ALIGN_CODE
,
18711 (relax_substateT
) max
,
18718 /* Perform target specific initialisation of a frag.
18719 Note - despite the name this initialisation is not done when the frag
18720 is created, but only when its type is assigned. A frag can be created
18721 and used a long time before its type is set, so beware of assuming that
18722 this initialisationis performed first. */
18726 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18728 /* Record whether this frag is in an ARM or a THUMB area. */
18729 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18732 #else /* OBJ_ELF is defined. */
18734 arm_init_frag (fragS
* fragP
, int max_chars
)
18736 /* If the current ARM vs THUMB mode has not already
18737 been recorded into this frag then do so now. */
18738 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18740 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18742 /* Record a mapping symbol for alignment frags. We will delete this
18743 later if the alignment ends up empty. */
18744 switch (fragP
->fr_type
)
18747 case rs_align_test
:
18749 mapping_state_2 (MAP_DATA
, max_chars
);
18751 case rs_align_code
:
18752 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
18760 /* When we change sections we need to issue a new mapping symbol. */
18763 arm_elf_change_section (void)
18765 /* Link an unlinked unwind index table section to the .text section. */
18766 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
18767 && elf_linked_to_section (now_seg
) == NULL
)
18768 elf_linked_to_section (now_seg
) = text_section
;
18772 arm_elf_section_type (const char * str
, size_t len
)
18774 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
18775 return SHT_ARM_EXIDX
;
18780 /* Code to deal with unwinding tables. */
18782 static void add_unwind_adjustsp (offsetT
);
18784 /* Generate any deferred unwind frame offset. */
18787 flush_pending_unwind (void)
18791 offset
= unwind
.pending_offset
;
18792 unwind
.pending_offset
= 0;
18794 add_unwind_adjustsp (offset
);
18797 /* Add an opcode to this list for this function. Two-byte opcodes should
18798 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
18802 add_unwind_opcode (valueT op
, int length
)
18804 /* Add any deferred stack adjustment. */
18805 if (unwind
.pending_offset
)
18806 flush_pending_unwind ();
18808 unwind
.sp_restored
= 0;
18810 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
18812 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
18813 if (unwind
.opcodes
)
18814 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
18815 unwind
.opcode_alloc
);
18817 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
18822 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
18824 unwind
.opcode_count
++;
18828 /* Add unwind opcodes to adjust the stack pointer. */
18831 add_unwind_adjustsp (offsetT offset
)
18835 if (offset
> 0x200)
18837 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
18842 /* Long form: 0xb2, uleb128. */
18843 /* This might not fit in a word so add the individual bytes,
18844 remembering the list is built in reverse order. */
18845 o
= (valueT
) ((offset
- 0x204) >> 2);
18847 add_unwind_opcode (0, 1);
18849 /* Calculate the uleb128 encoding of the offset. */
18853 bytes
[n
] = o
& 0x7f;
18859 /* Add the insn. */
18861 add_unwind_opcode (bytes
[n
- 1], 1);
18862 add_unwind_opcode (0xb2, 1);
18864 else if (offset
> 0x100)
18866 /* Two short opcodes. */
18867 add_unwind_opcode (0x3f, 1);
18868 op
= (offset
- 0x104) >> 2;
18869 add_unwind_opcode (op
, 1);
18871 else if (offset
> 0)
18873 /* Short opcode. */
18874 op
= (offset
- 4) >> 2;
18875 add_unwind_opcode (op
, 1);
18877 else if (offset
< 0)
18880 while (offset
> 0x100)
18882 add_unwind_opcode (0x7f, 1);
18885 op
= ((offset
- 4) >> 2) | 0x40;
18886 add_unwind_opcode (op
, 1);
18890 /* Finish the list of unwind opcodes for this function. */
18892 finish_unwind_opcodes (void)
18896 if (unwind
.fp_used
)
18898 /* Adjust sp as necessary. */
18899 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
18900 flush_pending_unwind ();
18902 /* After restoring sp from the frame pointer. */
18903 op
= 0x90 | unwind
.fp_reg
;
18904 add_unwind_opcode (op
, 1);
18907 flush_pending_unwind ();
18911 /* Start an exception table entry. If idx is nonzero this is an index table
18915 start_unwind_section (const segT text_seg
, int idx
)
18917 const char * text_name
;
18918 const char * prefix
;
18919 const char * prefix_once
;
18920 const char * group_name
;
18924 size_t sec_name_len
;
18931 prefix
= ELF_STRING_ARM_unwind
;
18932 prefix_once
= ELF_STRING_ARM_unwind_once
;
18933 type
= SHT_ARM_EXIDX
;
18937 prefix
= ELF_STRING_ARM_unwind_info
;
18938 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
18939 type
= SHT_PROGBITS
;
18942 text_name
= segment_name (text_seg
);
18943 if (streq (text_name
, ".text"))
18946 if (strncmp (text_name
, ".gnu.linkonce.t.",
18947 strlen (".gnu.linkonce.t.")) == 0)
18949 prefix
= prefix_once
;
18950 text_name
+= strlen (".gnu.linkonce.t.");
18953 prefix_len
= strlen (prefix
);
18954 text_len
= strlen (text_name
);
18955 sec_name_len
= prefix_len
+ text_len
;
18956 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
18957 memcpy (sec_name
, prefix
, prefix_len
);
18958 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
18959 sec_name
[prefix_len
+ text_len
] = '\0';
18965 /* Handle COMDAT group. */
18966 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
18968 group_name
= elf_group_name (text_seg
);
18969 if (group_name
== NULL
)
18971 as_bad (_("Group section `%s' has no group signature"),
18972 segment_name (text_seg
));
18973 ignore_rest_of_line ();
18976 flags
|= SHF_GROUP
;
18980 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
18982 /* Set the section link for index tables. */
18984 elf_linked_to_section (now_seg
) = text_seg
;
18988 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
18989 personality routine data. Returns zero, or the index table value for
18990 and inline entry. */
18993 create_unwind_entry (int have_data
)
18998 /* The current word of data. */
19000 /* The number of bytes left in this word. */
19003 finish_unwind_opcodes ();
19005 /* Remember the current text section. */
19006 unwind
.saved_seg
= now_seg
;
19007 unwind
.saved_subseg
= now_subseg
;
19009 start_unwind_section (now_seg
, 0);
19011 if (unwind
.personality_routine
== NULL
)
19013 if (unwind
.personality_index
== -2)
19016 as_bad (_("handlerdata in cantunwind frame"));
19017 return 1; /* EXIDX_CANTUNWIND. */
19020 /* Use a default personality routine if none is specified. */
19021 if (unwind
.personality_index
== -1)
19023 if (unwind
.opcode_count
> 3)
19024 unwind
.personality_index
= 1;
19026 unwind
.personality_index
= 0;
19029 /* Space for the personality routine entry. */
19030 if (unwind
.personality_index
== 0)
19032 if (unwind
.opcode_count
> 3)
19033 as_bad (_("too many unwind opcodes for personality routine 0"));
19037 /* All the data is inline in the index table. */
19040 while (unwind
.opcode_count
> 0)
19042 unwind
.opcode_count
--;
19043 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19047 /* Pad with "finish" opcodes. */
19049 data
= (data
<< 8) | 0xb0;
19056 /* We get two opcodes "free" in the first word. */
19057 size
= unwind
.opcode_count
- 2;
19060 /* An extra byte is required for the opcode count. */
19061 size
= unwind
.opcode_count
+ 1;
19063 size
= (size
+ 3) >> 2;
19065 as_bad (_("too many unwind opcodes"));
19067 frag_align (2, 0, 0);
19068 record_alignment (now_seg
, 2);
19069 unwind
.table_entry
= expr_build_dot ();
19071 /* Allocate the table entry. */
19072 ptr
= frag_more ((size
<< 2) + 4);
19073 where
= frag_now_fix () - ((size
<< 2) + 4);
19075 switch (unwind
.personality_index
)
19078 /* ??? Should this be a PLT generating relocation? */
19079 /* Custom personality routine. */
19080 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19081 BFD_RELOC_ARM_PREL31
);
19086 /* Set the first byte to the number of additional words. */
19091 /* ABI defined personality routines. */
19093 /* Three opcodes bytes are packed into the first word. */
19100 /* The size and first two opcode bytes go in the first word. */
19101 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19106 /* Should never happen. */
19110 /* Pack the opcodes into words (MSB first), reversing the list at the same
19112 while (unwind
.opcode_count
> 0)
19116 md_number_to_chars (ptr
, data
, 4);
19121 unwind
.opcode_count
--;
19123 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19126 /* Finish off the last word. */
19129 /* Pad with "finish" opcodes. */
19131 data
= (data
<< 8) | 0xb0;
19133 md_number_to_chars (ptr
, data
, 4);
19138 /* Add an empty descriptor if there is no user-specified data. */
19139 ptr
= frag_more (4);
19140 md_number_to_chars (ptr
, 0, 4);
19147 /* Initialize the DWARF-2 unwind information for this procedure. */
19150 tc_arm_frame_initial_instructions (void)
19152 cfi_add_CFA_def_cfa (REG_SP
, 0);
19154 #endif /* OBJ_ELF */
19156 /* Convert REGNAME to a DWARF-2 register number. */
19159 tc_arm_regname_to_dw2regnum (char *regname
)
19161 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19171 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19175 exp
.X_op
= O_secrel
;
19176 exp
.X_add_symbol
= symbol
;
19177 exp
.X_add_number
= 0;
19178 emit_expr (&exp
, size
);
19182 /* MD interface: Symbol and relocation handling. */
19184 /* Return the address within the segment that a PC-relative fixup is
19185 relative to. For ARM, PC-relative fixups applied to instructions
19186 are generally relative to the location of the fixup plus 8 bytes.
19187 Thumb branches are offset by 4, and Thumb loads relative to PC
19188 require special handling. */
19191 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19193 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19195 /* If this is pc-relative and we are going to emit a relocation
19196 then we just want to put out any pipeline compensation that the linker
19197 will need. Otherwise we want to use the calculated base.
19198 For WinCE we skip the bias for externals as well, since this
19199 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19201 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19202 || (arm_force_relocation (fixP
)
19204 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19210 switch (fixP
->fx_r_type
)
19212 /* PC relative addressing on the Thumb is slightly odd as the
19213 bottom two bits of the PC are forced to zero for the
19214 calculation. This happens *after* application of the
19215 pipeline offset. However, Thumb adrl already adjusts for
19216 this, so we need not do it again. */
19217 case BFD_RELOC_ARM_THUMB_ADD
:
19220 case BFD_RELOC_ARM_THUMB_OFFSET
:
19221 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19222 case BFD_RELOC_ARM_T32_ADD_PC12
:
19223 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19224 return (base
+ 4) & ~3;
19226 /* Thumb branches are simply offset by +4. */
19227 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19228 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19229 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19230 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19231 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19234 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19236 && ARM_IS_FUNC (fixP
->fx_addsy
)
19237 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19238 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19241 /* BLX is like branches above, but forces the low two bits of PC to
19243 case BFD_RELOC_THUMB_PCREL_BLX
:
19245 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19246 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19247 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19248 return (base
+ 4) & ~3;
19250 /* ARM mode branches are offset by +8. However, the Windows CE
19251 loader expects the relocation not to take this into account. */
19252 case BFD_RELOC_ARM_PCREL_BLX
:
19254 && ARM_IS_FUNC (fixP
->fx_addsy
)
19255 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19256 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19259 case BFD_RELOC_ARM_PCREL_CALL
:
19261 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19262 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19263 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19266 case BFD_RELOC_ARM_PCREL_BRANCH
:
19267 case BFD_RELOC_ARM_PCREL_JUMP
:
19268 case BFD_RELOC_ARM_PLT32
:
19270 /* When handling fixups immediately, because we have already
19271 discovered the value of a symbol, or the address of the frag involved
19272 we must account for the offset by +8, as the OS loader will never see the reloc.
19273 see fixup_segment() in write.c
19274 The S_IS_EXTERNAL test handles the case of global symbols.
19275 Those need the calculated base, not just the pipe compensation the linker will need. */
19277 && fixP
->fx_addsy
!= NULL
19278 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19279 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19287 /* ARM mode loads relative to PC are also offset by +8. Unlike
19288 branches, the Windows CE loader *does* expect the relocation
19289 to take this into account. */
19290 case BFD_RELOC_ARM_OFFSET_IMM
:
19291 case BFD_RELOC_ARM_OFFSET_IMM8
:
19292 case BFD_RELOC_ARM_HWLITERAL
:
19293 case BFD_RELOC_ARM_LITERAL
:
19294 case BFD_RELOC_ARM_CP_OFF_IMM
:
19298 /* Other PC-relative relocations are un-offset. */
19304 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19305 Otherwise we have no need to default values of symbols. */
19308 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19311 if (name
[0] == '_' && name
[1] == 'G'
19312 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19316 if (symbol_find (name
))
19317 as_bad (_("GOT already in the symbol table"));
19319 GOT_symbol
= symbol_new (name
, undefined_section
,
19320 (valueT
) 0, & zero_address_frag
);
19330 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19331 computed as two separate immediate values, added together. We
19332 already know that this value cannot be computed by just one ARM
19335 static unsigned int
19336 validate_immediate_twopart (unsigned int val
,
19337 unsigned int * highpart
)
19342 for (i
= 0; i
< 32; i
+= 2)
19343 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19349 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19351 else if (a
& 0xff0000)
19353 if (a
& 0xff000000)
19355 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19359 gas_assert (a
& 0xff000000);
19360 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19363 return (a
& 0xff) | (i
<< 7);
19370 validate_offset_imm (unsigned int val
, int hwse
)
19372 if ((hwse
&& val
> 255) || val
> 4095)
19377 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19378 negative immediate constant by altering the instruction. A bit of
19383 by inverting the second operand, and
19386 by negating the second operand. */
19389 negate_data_op (unsigned long * instruction
,
19390 unsigned long value
)
19393 unsigned long negated
, inverted
;
19395 negated
= encode_arm_immediate (-value
);
19396 inverted
= encode_arm_immediate (~value
);
19398 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19401 /* First negates. */
19402 case OPCODE_SUB
: /* ADD <-> SUB */
19403 new_inst
= OPCODE_ADD
;
19408 new_inst
= OPCODE_SUB
;
19412 case OPCODE_CMP
: /* CMP <-> CMN */
19413 new_inst
= OPCODE_CMN
;
19418 new_inst
= OPCODE_CMP
;
19422 /* Now Inverted ops. */
19423 case OPCODE_MOV
: /* MOV <-> MVN */
19424 new_inst
= OPCODE_MVN
;
19429 new_inst
= OPCODE_MOV
;
19433 case OPCODE_AND
: /* AND <-> BIC */
19434 new_inst
= OPCODE_BIC
;
19439 new_inst
= OPCODE_AND
;
19443 case OPCODE_ADC
: /* ADC <-> SBC */
19444 new_inst
= OPCODE_SBC
;
19449 new_inst
= OPCODE_ADC
;
19453 /* We cannot do anything. */
19458 if (value
== (unsigned) FAIL
)
19461 *instruction
&= OPCODE_MASK
;
19462 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19466 /* Like negate_data_op, but for Thumb-2. */
19468 static unsigned int
19469 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19473 unsigned int negated
, inverted
;
19475 negated
= encode_thumb32_immediate (-value
);
19476 inverted
= encode_thumb32_immediate (~value
);
19478 rd
= (*instruction
>> 8) & 0xf;
19479 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19482 /* ADD <-> SUB. Includes CMP <-> CMN. */
19483 case T2_OPCODE_SUB
:
19484 new_inst
= T2_OPCODE_ADD
;
19488 case T2_OPCODE_ADD
:
19489 new_inst
= T2_OPCODE_SUB
;
19493 /* ORR <-> ORN. Includes MOV <-> MVN. */
19494 case T2_OPCODE_ORR
:
19495 new_inst
= T2_OPCODE_ORN
;
19499 case T2_OPCODE_ORN
:
19500 new_inst
= T2_OPCODE_ORR
;
19504 /* AND <-> BIC. TST has no inverted equivalent. */
19505 case T2_OPCODE_AND
:
19506 new_inst
= T2_OPCODE_BIC
;
19513 case T2_OPCODE_BIC
:
19514 new_inst
= T2_OPCODE_AND
;
19519 case T2_OPCODE_ADC
:
19520 new_inst
= T2_OPCODE_SBC
;
19524 case T2_OPCODE_SBC
:
19525 new_inst
= T2_OPCODE_ADC
;
19529 /* We cannot do anything. */
19534 if (value
== (unsigned int)FAIL
)
19537 *instruction
&= T2_OPCODE_MASK
;
19538 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19542 /* Read a 32-bit thumb instruction from buf. */
19543 static unsigned long
19544 get_thumb32_insn (char * buf
)
19546 unsigned long insn
;
19547 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19548 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19554 /* We usually want to set the low bit on the address of thumb function
19555 symbols. In particular .word foo - . should have the low bit set.
19556 Generic code tries to fold the difference of two symbols to
19557 a constant. Prevent this and force a relocation when the first symbols
19558 is a thumb function. */
19561 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19563 if (op
== O_subtract
19564 && l
->X_op
== O_symbol
19565 && r
->X_op
== O_symbol
19566 && THUMB_IS_FUNC (l
->X_add_symbol
))
19568 l
->X_op
= O_subtract
;
19569 l
->X_op_symbol
= r
->X_add_symbol
;
19570 l
->X_add_number
-= r
->X_add_number
;
19574 /* Process as normal. */
19578 /* Encode Thumb2 unconditional branches and calls. The encoding
19579 for the 2 are identical for the immediate values. */
19582 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
19584 #define T2I1I2MASK ((1 << 13) | (1 << 11))
19587 addressT S
, I1
, I2
, lo
, hi
;
19589 S
= (value
>> 24) & 0x01;
19590 I1
= (value
>> 23) & 0x01;
19591 I2
= (value
>> 22) & 0x01;
19592 hi
= (value
>> 12) & 0x3ff;
19593 lo
= (value
>> 1) & 0x7ff;
19594 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19595 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19596 newval
|= (S
<< 10) | hi
;
19597 newval2
&= ~T2I1I2MASK
;
19598 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
19599 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19600 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19604 md_apply_fix (fixS
* fixP
,
19608 offsetT value
= * valP
;
19610 unsigned int newimm
;
19611 unsigned long temp
;
19613 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19615 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19617 /* Note whether this will delete the relocation. */
19619 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19622 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19623 consistency with the behaviour on 32-bit hosts. Remember value
19625 value
&= 0xffffffff;
19626 value
^= 0x80000000;
19627 value
-= 0x80000000;
19630 fixP
->fx_addnumber
= value
;
19632 /* Same treatment for fixP->fx_offset. */
19633 fixP
->fx_offset
&= 0xffffffff;
19634 fixP
->fx_offset
^= 0x80000000;
19635 fixP
->fx_offset
-= 0x80000000;
19637 switch (fixP
->fx_r_type
)
19639 case BFD_RELOC_NONE
:
19640 /* This will need to go in the object file. */
19644 case BFD_RELOC_ARM_IMMEDIATE
:
19645 /* We claim that this fixup has been processed here,
19646 even if in fact we generate an error because we do
19647 not have a reloc for it, so tc_gen_reloc will reject it. */
19651 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19654 _("undefined symbol %s used as an immediate value"),
19655 S_GET_NAME (fixP
->fx_addsy
));
19660 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19663 _("symbol %s is in a different section"),
19664 S_GET_NAME (fixP
->fx_addsy
));
19668 newimm
= encode_arm_immediate (value
);
19669 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19671 /* If the instruction will fail, see if we can fix things up by
19672 changing the opcode. */
19673 if (newimm
== (unsigned int) FAIL
19674 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19677 _("invalid constant (%lx) after fixup"),
19678 (unsigned long) value
);
19682 newimm
|= (temp
& 0xfffff000);
19683 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19686 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19688 unsigned int highpart
= 0;
19689 unsigned int newinsn
= 0xe1a00000; /* nop. */
19692 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19695 _("undefined symbol %s used as an immediate value"),
19696 S_GET_NAME (fixP
->fx_addsy
));
19701 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19703 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19704 _("symbol %s is in a different section"),
19705 S_GET_NAME (fixP
->fx_addsy
));
19709 newimm
= encode_arm_immediate (value
);
19710 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19712 /* If the instruction will fail, see if we can fix things up by
19713 changing the opcode. */
19714 if (newimm
== (unsigned int) FAIL
19715 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19717 /* No ? OK - try using two ADD instructions to generate
19719 newimm
= validate_immediate_twopart (value
, & highpart
);
19721 /* Yes - then make sure that the second instruction is
19723 if (newimm
!= (unsigned int) FAIL
)
19725 /* Still No ? Try using a negated value. */
19726 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19727 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19728 /* Otherwise - give up. */
19731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19732 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19737 /* Replace the first operand in the 2nd instruction (which
19738 is the PC) with the destination register. We have
19739 already added in the PC in the first instruction and we
19740 do not want to do it again. */
19741 newinsn
&= ~ 0xf0000;
19742 newinsn
|= ((newinsn
& 0x0f000) << 4);
19745 newimm
|= (temp
& 0xfffff000);
19746 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19748 highpart
|= (newinsn
& 0xfffff000);
19749 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
19753 case BFD_RELOC_ARM_OFFSET_IMM
:
19754 if (!fixP
->fx_done
&& seg
->use_rela_p
)
19757 case BFD_RELOC_ARM_LITERAL
:
19763 if (validate_offset_imm (value
, 0) == FAIL
)
19765 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
19766 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19767 _("invalid literal constant: pool needs to be closer"));
19769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19770 _("bad immediate value for offset (%ld)"),
19775 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19776 newval
&= 0xff7ff000;
19777 newval
|= value
| (sign
? INDEX_UP
: 0);
19778 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19781 case BFD_RELOC_ARM_OFFSET_IMM8
:
19782 case BFD_RELOC_ARM_HWLITERAL
:
19788 if (validate_offset_imm (value
, 1) == FAIL
)
19790 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
19791 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19792 _("invalid literal constant: pool needs to be closer"));
19794 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
19799 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19800 newval
&= 0xff7ff0f0;
19801 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
19802 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19805 case BFD_RELOC_ARM_T32_OFFSET_U8
:
19806 if (value
< 0 || value
> 1020 || value
% 4 != 0)
19807 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19808 _("bad immediate value for offset (%ld)"), (long) value
);
19811 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
19813 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
19816 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19817 /* This is a complicated relocation used for all varieties of Thumb32
19818 load/store instruction with immediate offset:
19820 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
19821 *4, optional writeback(W)
19822 (doubleword load/store)
19824 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
19825 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
19826 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
19827 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
19828 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
19830 Uppercase letters indicate bits that are already encoded at
19831 this point. Lowercase letters are our problem. For the
19832 second block of instructions, the secondary opcode nybble
19833 (bits 8..11) is present, and bit 23 is zero, even if this is
19834 a PC-relative operation. */
19835 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19837 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
19839 if ((newval
& 0xf0000000) == 0xe0000000)
19841 /* Doubleword load/store: 8-bit offset, scaled by 4. */
19843 newval
|= (1 << 23);
19846 if (value
% 4 != 0)
19848 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19849 _("offset not a multiple of 4"));
19855 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19856 _("offset out of range"));
19861 else if ((newval
& 0x000f0000) == 0x000f0000)
19863 /* PC-relative, 12-bit offset. */
19865 newval
|= (1 << 23);
19870 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19871 _("offset out of range"));
19876 else if ((newval
& 0x00000100) == 0x00000100)
19878 /* Writeback: 8-bit, +/- offset. */
19880 newval
|= (1 << 9);
19885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19886 _("offset out of range"));
19891 else if ((newval
& 0x00000f00) == 0x00000e00)
19893 /* T-instruction: positive 8-bit offset. */
19894 if (value
< 0 || value
> 0xff)
19896 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19897 _("offset out of range"));
19905 /* Positive 12-bit or negative 8-bit offset. */
19909 newval
|= (1 << 23);
19919 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19920 _("offset out of range"));
19927 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
19928 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
19931 case BFD_RELOC_ARM_SHIFT_IMM
:
19932 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19933 if (((unsigned long) value
) > 32
19935 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
19937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19938 _("shift expression is too large"));
19943 /* Shifts of zero must be done as lsl. */
19945 else if (value
== 32)
19947 newval
&= 0xfffff07f;
19948 newval
|= (value
& 0x1f) << 7;
19949 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19952 case BFD_RELOC_ARM_T32_IMMEDIATE
:
19953 case BFD_RELOC_ARM_T32_ADD_IMM
:
19954 case BFD_RELOC_ARM_T32_IMM12
:
19955 case BFD_RELOC_ARM_T32_ADD_PC12
:
19956 /* We claim that this fixup has been processed here,
19957 even if in fact we generate an error because we do
19958 not have a reloc for it, so tc_gen_reloc will reject it. */
19962 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19965 _("undefined symbol %s used as an immediate value"),
19966 S_GET_NAME (fixP
->fx_addsy
));
19970 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19972 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
19975 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19976 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19978 newimm
= encode_thumb32_immediate (value
);
19979 if (newimm
== (unsigned int) FAIL
)
19980 newimm
= thumb32_negate_data_op (&newval
, value
);
19982 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
19983 && newimm
== (unsigned int) FAIL
)
19985 /* Turn add/sum into addw/subw. */
19986 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19987 newval
= (newval
& 0xfeffffff) | 0x02000000;
19989 /* 12 bit immediate for addw/subw. */
19993 newval
^= 0x00a00000;
19996 newimm
= (unsigned int) FAIL
;
20001 if (newimm
== (unsigned int)FAIL
)
20003 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20004 _("invalid constant (%lx) after fixup"),
20005 (unsigned long) value
);
20009 newval
|= (newimm
& 0x800) << 15;
20010 newval
|= (newimm
& 0x700) << 4;
20011 newval
|= (newimm
& 0x0ff);
20013 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20014 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20017 case BFD_RELOC_ARM_SMC
:
20018 if (((unsigned long) value
) > 0xffff)
20019 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20020 _("invalid smc expression"));
20021 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20022 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20023 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20026 case BFD_RELOC_ARM_SWI
:
20027 if (fixP
->tc_fix_data
!= 0)
20029 if (((unsigned long) value
) > 0xff)
20030 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20031 _("invalid swi expression"));
20032 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20034 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20038 if (((unsigned long) value
) > 0x00ffffff)
20039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20040 _("invalid swi expression"));
20041 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20043 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20047 case BFD_RELOC_ARM_MULTI
:
20048 if (((unsigned long) value
) > 0xffff)
20049 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20050 _("invalid expression in load/store multiple"));
20051 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20052 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20056 case BFD_RELOC_ARM_PCREL_CALL
:
20058 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20060 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20061 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20062 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20063 /* Flip the bl to blx. This is a simple flip
20064 bit here because we generate PCREL_CALL for
20065 unconditional bls. */
20067 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20068 newval
= newval
| 0x10000000;
20069 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20075 goto arm_branch_common
;
20077 case BFD_RELOC_ARM_PCREL_JUMP
:
20078 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20080 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20081 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20082 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20084 /* This would map to a bl<cond>, b<cond>,
20085 b<always> to a Thumb function. We
20086 need to force a relocation for this particular
20088 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20092 case BFD_RELOC_ARM_PLT32
:
20094 case BFD_RELOC_ARM_PCREL_BRANCH
:
20096 goto arm_branch_common
;
20098 case BFD_RELOC_ARM_PCREL_BLX
:
20101 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20103 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20104 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20105 && ARM_IS_FUNC (fixP
->fx_addsy
))
20107 /* Flip the blx to a bl and warn. */
20108 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20109 newval
= 0xeb000000;
20110 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20111 _("blx to '%s' an ARM ISA state function changed to bl"),
20113 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20119 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20120 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20124 /* We are going to store value (shifted right by two) in the
20125 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20126 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20127 also be be clear. */
20129 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20130 _("misaligned branch destination"));
20131 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20132 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20133 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20134 _("branch out of range"));
20136 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20138 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20139 newval
|= (value
>> 2) & 0x00ffffff;
20140 /* Set the H bit on BLX instructions. */
20144 newval
|= 0x01000000;
20146 newval
&= ~0x01000000;
20148 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20152 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20153 /* CBZ can only branch forward. */
20155 /* Attempts to use CBZ to branch to the next instruction
20156 (which, strictly speaking, are prohibited) will be turned into
20159 FIXME: It may be better to remove the instruction completely and
20160 perform relaxation. */
20163 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20164 newval
= 0xbf00; /* NOP encoding T1 */
20165 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20170 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20171 _("branch out of range"));
20173 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20175 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20176 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20177 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20182 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20183 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20184 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20185 _("branch out of range"));
20187 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20189 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20190 newval
|= (value
& 0x1ff) >> 1;
20191 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20195 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20196 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20197 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20198 _("branch out of range"));
20200 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20202 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20203 newval
|= (value
& 0xfff) >> 1;
20204 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20208 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20210 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20211 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20212 && S_IS_DEFINED (fixP
->fx_addsy
)
20213 && ARM_IS_FUNC (fixP
->fx_addsy
)
20214 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20216 /* Force a relocation for a branch 20 bits wide. */
20219 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20220 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20221 _("conditional branch out of range"));
20223 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20226 addressT S
, J1
, J2
, lo
, hi
;
20228 S
= (value
& 0x00100000) >> 20;
20229 J2
= (value
& 0x00080000) >> 19;
20230 J1
= (value
& 0x00040000) >> 18;
20231 hi
= (value
& 0x0003f000) >> 12;
20232 lo
= (value
& 0x00000ffe) >> 1;
20234 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20235 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20236 newval
|= (S
<< 10) | hi
;
20237 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20238 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20239 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20243 case BFD_RELOC_THUMB_PCREL_BLX
:
20245 /* If there is a blx from a thumb state function to
20246 another thumb function flip this to a bl and warn
20250 && S_IS_DEFINED (fixP
->fx_addsy
)
20251 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20252 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20253 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20255 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20256 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20257 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20259 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20260 newval
= newval
| 0x1000;
20261 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20262 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20267 goto thumb_bl_common
;
20269 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20271 /* A bl from Thumb state ISA to an internal ARM state function
20272 is converted to a blx. */
20274 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20275 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20276 && S_IS_DEFINED (fixP
->fx_addsy
)
20277 && ARM_IS_FUNC (fixP
->fx_addsy
)
20278 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20280 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20281 newval
= newval
& ~0x1000;
20282 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20283 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20290 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20291 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20292 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20295 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20296 /* For a BLX instruction, make sure that the relocation is rounded up
20297 to a word boundary. This follows the semantics of the instruction
20298 which specifies that bit 1 of the target address will come from bit
20299 1 of the base address. */
20300 value
= (value
+ 1) & ~ 1;
20303 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20305 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20308 _("branch out of range"));
20310 else if ((value
& ~0x1ffffff)
20311 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20313 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20314 _("Thumb2 branch out of range"));
20318 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20319 encode_thumb2_b_bl_offset (buf
, value
);
20323 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20324 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20325 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20326 _("branch out of range"));
20328 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20329 encode_thumb2_b_bl_offset (buf
, value
);
20334 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20335 md_number_to_chars (buf
, value
, 1);
20339 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20340 md_number_to_chars (buf
, value
, 2);
20344 case BFD_RELOC_ARM_TLS_GD32
:
20345 case BFD_RELOC_ARM_TLS_LE32
:
20346 case BFD_RELOC_ARM_TLS_IE32
:
20347 case BFD_RELOC_ARM_TLS_LDM32
:
20348 case BFD_RELOC_ARM_TLS_LDO32
:
20349 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20352 case BFD_RELOC_ARM_GOT32
:
20353 case BFD_RELOC_ARM_GOTOFF
:
20354 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20355 md_number_to_chars (buf
, 0, 4);
20358 case BFD_RELOC_ARM_TARGET2
:
20359 /* TARGET2 is not partial-inplace, so we need to write the
20360 addend here for REL targets, because it won't be written out
20361 during reloc processing later. */
20362 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20363 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20367 case BFD_RELOC_RVA
:
20369 case BFD_RELOC_ARM_TARGET1
:
20370 case BFD_RELOC_ARM_ROSEGREL32
:
20371 case BFD_RELOC_ARM_SBREL32
:
20372 case BFD_RELOC_32_PCREL
:
20374 case BFD_RELOC_32_SECREL
:
20376 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20378 /* For WinCE we only do this for pcrel fixups. */
20379 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20381 md_number_to_chars (buf
, value
, 4);
20385 case BFD_RELOC_ARM_PREL31
:
20386 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20388 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20389 if ((value
^ (value
>> 1)) & 0x40000000)
20391 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20392 _("rel31 relocation overflow"));
20394 newval
|= value
& 0x7fffffff;
20395 md_number_to_chars (buf
, newval
, 4);
20400 case BFD_RELOC_ARM_CP_OFF_IMM
:
20401 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20402 if (value
< -1023 || value
> 1023 || (value
& 3))
20403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20404 _("co-processor offset out of range"));
20409 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20410 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20411 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20413 newval
= get_thumb32_insn (buf
);
20414 newval
&= 0xff7fff00;
20415 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20416 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20417 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20418 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20420 put_thumb32_insn (buf
, newval
);
20423 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20424 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20425 if (value
< -255 || value
> 255)
20426 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20427 _("co-processor offset out of range"));
20429 goto cp_off_common
;
20431 case BFD_RELOC_ARM_THUMB_OFFSET
:
20432 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20433 /* Exactly what ranges, and where the offset is inserted depends
20434 on the type of instruction, we can establish this from the
20436 switch (newval
>> 12)
20438 case 4: /* PC load. */
20439 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20440 forced to zero for these loads; md_pcrel_from has already
20441 compensated for this. */
20443 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20444 _("invalid offset, target not word aligned (0x%08lX)"),
20445 (((unsigned long) fixP
->fx_frag
->fr_address
20446 + (unsigned long) fixP
->fx_where
) & ~3)
20447 + (unsigned long) value
);
20449 if (value
& ~0x3fc)
20450 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20451 _("invalid offset, value too big (0x%08lX)"),
20454 newval
|= value
>> 2;
20457 case 9: /* SP load/store. */
20458 if (value
& ~0x3fc)
20459 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20460 _("invalid offset, value too big (0x%08lX)"),
20462 newval
|= value
>> 2;
20465 case 6: /* Word load/store. */
20467 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20468 _("invalid offset, value too big (0x%08lX)"),
20470 newval
|= value
<< 4; /* 6 - 2. */
20473 case 7: /* Byte load/store. */
20475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20476 _("invalid offset, value too big (0x%08lX)"),
20478 newval
|= value
<< 6;
20481 case 8: /* Halfword load/store. */
20483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20484 _("invalid offset, value too big (0x%08lX)"),
20486 newval
|= value
<< 5; /* 6 - 1. */
20490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20491 "Unable to process relocation for thumb opcode: %lx",
20492 (unsigned long) newval
);
20495 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20498 case BFD_RELOC_ARM_THUMB_ADD
:
20499 /* This is a complicated relocation, since we use it for all of
20500 the following immediate relocations:
20504 9bit ADD/SUB SP word-aligned
20505 10bit ADD PC/SP word-aligned
20507 The type of instruction being processed is encoded in the
20514 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20516 int rd
= (newval
>> 4) & 0xf;
20517 int rs
= newval
& 0xf;
20518 int subtract
= !!(newval
& 0x8000);
20520 /* Check for HI regs, only very restricted cases allowed:
20521 Adjusting SP, and using PC or SP to get an address. */
20522 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20523 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20524 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20525 _("invalid Hi register with immediate"));
20527 /* If value is negative, choose the opposite instruction. */
20531 subtract
= !subtract
;
20533 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20534 _("immediate value out of range"));
20539 if (value
& ~0x1fc)
20540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20541 _("invalid immediate for stack address calculation"));
20542 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20543 newval
|= value
>> 2;
20545 else if (rs
== REG_PC
|| rs
== REG_SP
)
20547 if (subtract
|| value
& ~0x3fc)
20548 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20549 _("invalid immediate for address calculation (value = 0x%08lX)"),
20550 (unsigned long) value
);
20551 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20553 newval
|= value
>> 2;
20558 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20559 _("immediate value out of range"));
20560 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20561 newval
|= (rd
<< 8) | value
;
20566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20567 _("immediate value out of range"));
20568 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20569 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20572 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20575 case BFD_RELOC_ARM_THUMB_IMM
:
20576 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20577 if (value
< 0 || value
> 255)
20578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20579 _("invalid immediate: %ld is out of range"),
20582 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20585 case BFD_RELOC_ARM_THUMB_SHIFT
:
20586 /* 5bit shift value (0..32). LSL cannot take 32. */
20587 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20588 temp
= newval
& 0xf800;
20589 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20590 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20591 _("invalid shift value: %ld"), (long) value
);
20592 /* Shifts of zero must be encoded as LSL. */
20594 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20595 /* Shifts of 32 are encoded as zero. */
20596 else if (value
== 32)
20598 newval
|= value
<< 6;
20599 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20602 case BFD_RELOC_VTABLE_INHERIT
:
20603 case BFD_RELOC_VTABLE_ENTRY
:
20607 case BFD_RELOC_ARM_MOVW
:
20608 case BFD_RELOC_ARM_MOVT
:
20609 case BFD_RELOC_ARM_THUMB_MOVW
:
20610 case BFD_RELOC_ARM_THUMB_MOVT
:
20611 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20613 /* REL format relocations are limited to a 16-bit addend. */
20614 if (!fixP
->fx_done
)
20616 if (value
< -0x8000 || value
> 0x7fff)
20617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20618 _("offset out of range"));
20620 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20621 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20626 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20627 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20629 newval
= get_thumb32_insn (buf
);
20630 newval
&= 0xfbf08f00;
20631 newval
|= (value
& 0xf000) << 4;
20632 newval
|= (value
& 0x0800) << 15;
20633 newval
|= (value
& 0x0700) << 4;
20634 newval
|= (value
& 0x00ff);
20635 put_thumb32_insn (buf
, newval
);
20639 newval
= md_chars_to_number (buf
, 4);
20640 newval
&= 0xfff0f000;
20641 newval
|= value
& 0x0fff;
20642 newval
|= (value
& 0xf000) << 4;
20643 md_number_to_chars (buf
, newval
, 4);
20648 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20649 case BFD_RELOC_ARM_ALU_PC_G0
:
20650 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20651 case BFD_RELOC_ARM_ALU_PC_G1
:
20652 case BFD_RELOC_ARM_ALU_PC_G2
:
20653 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20654 case BFD_RELOC_ARM_ALU_SB_G0
:
20655 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20656 case BFD_RELOC_ARM_ALU_SB_G1
:
20657 case BFD_RELOC_ARM_ALU_SB_G2
:
20658 gas_assert (!fixP
->fx_done
);
20659 if (!seg
->use_rela_p
)
20662 bfd_vma encoded_addend
;
20663 bfd_vma addend_abs
= abs (value
);
20665 /* Check that the absolute value of the addend can be
20666 expressed as an 8-bit constant plus a rotation. */
20667 encoded_addend
= encode_arm_immediate (addend_abs
);
20668 if (encoded_addend
== (unsigned int) FAIL
)
20669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20670 _("the offset 0x%08lX is not representable"),
20671 (unsigned long) addend_abs
);
20673 /* Extract the instruction. */
20674 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20676 /* If the addend is positive, use an ADD instruction.
20677 Otherwise use a SUB. Take care not to destroy the S bit. */
20678 insn
&= 0xff1fffff;
20684 /* Place the encoded addend into the first 12 bits of the
20686 insn
&= 0xfffff000;
20687 insn
|= encoded_addend
;
20689 /* Update the instruction. */
20690 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20694 case BFD_RELOC_ARM_LDR_PC_G0
:
20695 case BFD_RELOC_ARM_LDR_PC_G1
:
20696 case BFD_RELOC_ARM_LDR_PC_G2
:
20697 case BFD_RELOC_ARM_LDR_SB_G0
:
20698 case BFD_RELOC_ARM_LDR_SB_G1
:
20699 case BFD_RELOC_ARM_LDR_SB_G2
:
20700 gas_assert (!fixP
->fx_done
);
20701 if (!seg
->use_rela_p
)
20704 bfd_vma addend_abs
= abs (value
);
20706 /* Check that the absolute value of the addend can be
20707 encoded in 12 bits. */
20708 if (addend_abs
>= 0x1000)
20709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20710 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20711 (unsigned long) addend_abs
);
20713 /* Extract the instruction. */
20714 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20716 /* If the addend is negative, clear bit 23 of the instruction.
20717 Otherwise set it. */
20719 insn
&= ~(1 << 23);
20723 /* Place the absolute value of the addend into the first 12 bits
20724 of the instruction. */
20725 insn
&= 0xfffff000;
20726 insn
|= addend_abs
;
20728 /* Update the instruction. */
20729 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20733 case BFD_RELOC_ARM_LDRS_PC_G0
:
20734 case BFD_RELOC_ARM_LDRS_PC_G1
:
20735 case BFD_RELOC_ARM_LDRS_PC_G2
:
20736 case BFD_RELOC_ARM_LDRS_SB_G0
:
20737 case BFD_RELOC_ARM_LDRS_SB_G1
:
20738 case BFD_RELOC_ARM_LDRS_SB_G2
:
20739 gas_assert (!fixP
->fx_done
);
20740 if (!seg
->use_rela_p
)
20743 bfd_vma addend_abs
= abs (value
);
20745 /* Check that the absolute value of the addend can be
20746 encoded in 8 bits. */
20747 if (addend_abs
>= 0x100)
20748 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20749 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
20750 (unsigned long) addend_abs
);
20752 /* Extract the instruction. */
20753 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20755 /* If the addend is negative, clear bit 23 of the instruction.
20756 Otherwise set it. */
20758 insn
&= ~(1 << 23);
20762 /* Place the first four bits of the absolute value of the addend
20763 into the first 4 bits of the instruction, and the remaining
20764 four into bits 8 .. 11. */
20765 insn
&= 0xfffff0f0;
20766 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
20768 /* Update the instruction. */
20769 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20773 case BFD_RELOC_ARM_LDC_PC_G0
:
20774 case BFD_RELOC_ARM_LDC_PC_G1
:
20775 case BFD_RELOC_ARM_LDC_PC_G2
:
20776 case BFD_RELOC_ARM_LDC_SB_G0
:
20777 case BFD_RELOC_ARM_LDC_SB_G1
:
20778 case BFD_RELOC_ARM_LDC_SB_G2
:
20779 gas_assert (!fixP
->fx_done
);
20780 if (!seg
->use_rela_p
)
20783 bfd_vma addend_abs
= abs (value
);
20785 /* Check that the absolute value of the addend is a multiple of
20786 four and, when divided by four, fits in 8 bits. */
20787 if (addend_abs
& 0x3)
20788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20789 _("bad offset 0x%08lX (must be word-aligned)"),
20790 (unsigned long) addend_abs
);
20792 if ((addend_abs
>> 2) > 0xff)
20793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20794 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
20795 (unsigned long) addend_abs
);
20797 /* Extract the instruction. */
20798 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20800 /* If the addend is negative, clear bit 23 of the instruction.
20801 Otherwise set it. */
20803 insn
&= ~(1 << 23);
20807 /* Place the addend (divided by four) into the first eight
20808 bits of the instruction. */
20809 insn
&= 0xfffffff0;
20810 insn
|= addend_abs
>> 2;
20812 /* Update the instruction. */
20813 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20817 case BFD_RELOC_ARM_V4BX
:
20818 /* This will need to go in the object file. */
20822 case BFD_RELOC_UNUSED
:
20824 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20825 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
20829 /* Translate internal representation of relocation info to BFD target
20833 tc_gen_reloc (asection
*section
, fixS
*fixp
)
20836 bfd_reloc_code_real_type code
;
20838 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
20840 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
20841 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
20842 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
20844 if (fixp
->fx_pcrel
)
20846 if (section
->use_rela_p
)
20847 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
20849 fixp
->fx_offset
= reloc
->address
;
20851 reloc
->addend
= fixp
->fx_offset
;
20853 switch (fixp
->fx_r_type
)
20856 if (fixp
->fx_pcrel
)
20858 code
= BFD_RELOC_8_PCREL
;
20863 if (fixp
->fx_pcrel
)
20865 code
= BFD_RELOC_16_PCREL
;
20870 if (fixp
->fx_pcrel
)
20872 code
= BFD_RELOC_32_PCREL
;
20876 case BFD_RELOC_ARM_MOVW
:
20877 if (fixp
->fx_pcrel
)
20879 code
= BFD_RELOC_ARM_MOVW_PCREL
;
20883 case BFD_RELOC_ARM_MOVT
:
20884 if (fixp
->fx_pcrel
)
20886 code
= BFD_RELOC_ARM_MOVT_PCREL
;
20890 case BFD_RELOC_ARM_THUMB_MOVW
:
20891 if (fixp
->fx_pcrel
)
20893 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
20897 case BFD_RELOC_ARM_THUMB_MOVT
:
20898 if (fixp
->fx_pcrel
)
20900 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
20904 case BFD_RELOC_NONE
:
20905 case BFD_RELOC_ARM_PCREL_BRANCH
:
20906 case BFD_RELOC_ARM_PCREL_BLX
:
20907 case BFD_RELOC_RVA
:
20908 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
20909 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
20910 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
20911 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20912 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20913 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20914 case BFD_RELOC_VTABLE_ENTRY
:
20915 case BFD_RELOC_VTABLE_INHERIT
:
20917 case BFD_RELOC_32_SECREL
:
20919 code
= fixp
->fx_r_type
;
20922 case BFD_RELOC_THUMB_PCREL_BLX
:
20924 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20925 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20928 code
= BFD_RELOC_THUMB_PCREL_BLX
;
20931 case BFD_RELOC_ARM_LITERAL
:
20932 case BFD_RELOC_ARM_HWLITERAL
:
20933 /* If this is called then the a literal has
20934 been referenced across a section boundary. */
20935 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20936 _("literal referenced across section boundary"));
20940 case BFD_RELOC_ARM_GOT32
:
20941 case BFD_RELOC_ARM_GOTOFF
:
20942 case BFD_RELOC_ARM_PLT32
:
20943 case BFD_RELOC_ARM_TARGET1
:
20944 case BFD_RELOC_ARM_ROSEGREL32
:
20945 case BFD_RELOC_ARM_SBREL32
:
20946 case BFD_RELOC_ARM_PREL31
:
20947 case BFD_RELOC_ARM_TARGET2
:
20948 case BFD_RELOC_ARM_TLS_LE32
:
20949 case BFD_RELOC_ARM_TLS_LDO32
:
20950 case BFD_RELOC_ARM_PCREL_CALL
:
20951 case BFD_RELOC_ARM_PCREL_JUMP
:
20952 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20953 case BFD_RELOC_ARM_ALU_PC_G0
:
20954 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20955 case BFD_RELOC_ARM_ALU_PC_G1
:
20956 case BFD_RELOC_ARM_ALU_PC_G2
:
20957 case BFD_RELOC_ARM_LDR_PC_G0
:
20958 case BFD_RELOC_ARM_LDR_PC_G1
:
20959 case BFD_RELOC_ARM_LDR_PC_G2
:
20960 case BFD_RELOC_ARM_LDRS_PC_G0
:
20961 case BFD_RELOC_ARM_LDRS_PC_G1
:
20962 case BFD_RELOC_ARM_LDRS_PC_G2
:
20963 case BFD_RELOC_ARM_LDC_PC_G0
:
20964 case BFD_RELOC_ARM_LDC_PC_G1
:
20965 case BFD_RELOC_ARM_LDC_PC_G2
:
20966 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20967 case BFD_RELOC_ARM_ALU_SB_G0
:
20968 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20969 case BFD_RELOC_ARM_ALU_SB_G1
:
20970 case BFD_RELOC_ARM_ALU_SB_G2
:
20971 case BFD_RELOC_ARM_LDR_SB_G0
:
20972 case BFD_RELOC_ARM_LDR_SB_G1
:
20973 case BFD_RELOC_ARM_LDR_SB_G2
:
20974 case BFD_RELOC_ARM_LDRS_SB_G0
:
20975 case BFD_RELOC_ARM_LDRS_SB_G1
:
20976 case BFD_RELOC_ARM_LDRS_SB_G2
:
20977 case BFD_RELOC_ARM_LDC_SB_G0
:
20978 case BFD_RELOC_ARM_LDC_SB_G1
:
20979 case BFD_RELOC_ARM_LDC_SB_G2
:
20980 case BFD_RELOC_ARM_V4BX
:
20981 code
= fixp
->fx_r_type
;
20984 case BFD_RELOC_ARM_TLS_GD32
:
20985 case BFD_RELOC_ARM_TLS_IE32
:
20986 case BFD_RELOC_ARM_TLS_LDM32
:
20987 /* BFD will include the symbol's address in the addend.
20988 But we don't want that, so subtract it out again here. */
20989 if (!S_IS_COMMON (fixp
->fx_addsy
))
20990 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
20991 code
= fixp
->fx_r_type
;
20995 case BFD_RELOC_ARM_IMMEDIATE
:
20996 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20997 _("internal relocation (type: IMMEDIATE) not fixed up"));
21000 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21001 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21002 _("ADRL used for a symbol not defined in the same file"));
21005 case BFD_RELOC_ARM_OFFSET_IMM
:
21006 if (section
->use_rela_p
)
21008 code
= fixp
->fx_r_type
;
21012 if (fixp
->fx_addsy
!= NULL
21013 && !S_IS_DEFINED (fixp
->fx_addsy
)
21014 && S_IS_LOCAL (fixp
->fx_addsy
))
21016 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21017 _("undefined local label `%s'"),
21018 S_GET_NAME (fixp
->fx_addsy
));
21022 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21023 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21030 switch (fixp
->fx_r_type
)
21032 case BFD_RELOC_NONE
: type
= "NONE"; break;
21033 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21034 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21035 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21036 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21037 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21038 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21039 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21040 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21041 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21042 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21043 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21044 default: type
= _("<unknown>"); break;
21046 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21047 _("cannot represent %s relocation in this object file format"),
21054 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21056 && fixp
->fx_addsy
== GOT_symbol
)
21058 code
= BFD_RELOC_ARM_GOTPC
;
21059 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21063 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21065 if (reloc
->howto
== NULL
)
21067 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21068 _("cannot represent %s relocation in this object file format"),
21069 bfd_get_reloc_code_name (code
));
21073 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21074 vtable entry to be used in the relocation's section offset. */
21075 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21076 reloc
->address
= fixp
->fx_offset
;
21081 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21084 cons_fix_new_arm (fragS
* frag
,
21089 bfd_reloc_code_real_type type
;
21093 FIXME: @@ Should look at CPU word size. */
21097 type
= BFD_RELOC_8
;
21100 type
= BFD_RELOC_16
;
21104 type
= BFD_RELOC_32
;
21107 type
= BFD_RELOC_64
;
21112 if (exp
->X_op
== O_secrel
)
21114 exp
->X_op
= O_symbol
;
21115 type
= BFD_RELOC_32_SECREL
;
21119 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21122 #if defined (OBJ_COFF)
21124 arm_validate_fix (fixS
* fixP
)
21126 /* If the destination of the branch is a defined symbol which does not have
21127 the THUMB_FUNC attribute, then we must be calling a function which has
21128 the (interfacearm) attribute. We look for the Thumb entry point to that
21129 function and change the branch to refer to that function instead. */
21130 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21131 && fixP
->fx_addsy
!= NULL
21132 && S_IS_DEFINED (fixP
->fx_addsy
)
21133 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21135 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21142 arm_force_relocation (struct fix
* fixp
)
21144 #if defined (OBJ_COFF) && defined (TE_PE)
21145 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21149 /* In case we have a call or a branch to a function in ARM ISA mode from
21150 a thumb function or vice-versa force the relocation. These relocations
21151 are cleared off for some cores that might have blx and simple transformations
21155 switch (fixp
->fx_r_type
)
21157 case BFD_RELOC_ARM_PCREL_JUMP
:
21158 case BFD_RELOC_ARM_PCREL_CALL
:
21159 case BFD_RELOC_THUMB_PCREL_BLX
:
21160 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21164 case BFD_RELOC_ARM_PCREL_BLX
:
21165 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21166 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21167 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21168 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21177 /* Resolve these relocations even if the symbol is extern or weak. */
21178 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21179 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21180 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21181 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21182 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21183 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21184 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21187 /* Always leave these relocations for the linker. */
21188 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21189 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21190 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21193 /* Always generate relocations against function symbols. */
21194 if (fixp
->fx_r_type
== BFD_RELOC_32
21196 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21199 return generic_force_reloc (fixp
);
21202 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21203 /* Relocations against function names must be left unadjusted,
21204 so that the linker can use this information to generate interworking
21205 stubs. The MIPS version of this function
21206 also prevents relocations that are mips-16 specific, but I do not
21207 know why it does this.
21210 There is one other problem that ought to be addressed here, but
21211 which currently is not: Taking the address of a label (rather
21212 than a function) and then later jumping to that address. Such
21213 addresses also ought to have their bottom bit set (assuming that
21214 they reside in Thumb code), but at the moment they will not. */
21217 arm_fix_adjustable (fixS
* fixP
)
21219 if (fixP
->fx_addsy
== NULL
)
21222 /* Preserve relocations against symbols with function type. */
21223 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21226 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21227 && fixP
->fx_subsy
== NULL
)
21230 /* We need the symbol name for the VTABLE entries. */
21231 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21232 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21235 /* Don't allow symbols to be discarded on GOT related relocs. */
21236 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21237 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21238 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21239 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21240 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21241 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21242 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21243 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21244 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21247 /* Similarly for group relocations. */
21248 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21249 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21250 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21253 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21254 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21255 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21256 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21257 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21258 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21259 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21260 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21261 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21266 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21271 elf32_arm_target_format (void)
21274 return (target_big_endian
21275 ? "elf32-bigarm-symbian"
21276 : "elf32-littlearm-symbian");
21277 #elif defined (TE_VXWORKS)
21278 return (target_big_endian
21279 ? "elf32-bigarm-vxworks"
21280 : "elf32-littlearm-vxworks");
21282 if (target_big_endian
)
21283 return "elf32-bigarm";
21285 return "elf32-littlearm";
21290 armelf_frob_symbol (symbolS
* symp
,
21293 elf_frob_symbol (symp
, puntp
);
21297 /* MD interface: Finalization. */
21302 literal_pool
* pool
;
21304 /* Ensure that all the IT blocks are properly closed. */
21305 check_it_blocks_finished ();
21307 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21309 /* Put it at the end of the relevant section. */
21310 subseg_set (pool
->section
, pool
->sub_section
);
21312 arm_elf_change_section ();
21319 /* Remove any excess mapping symbols generated for alignment frags in
21320 SEC. We may have created a mapping symbol before a zero byte
21321 alignment; remove it if there's a mapping symbol after the
21324 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21325 void *dummy ATTRIBUTE_UNUSED
)
21327 segment_info_type
*seginfo
= seg_info (sec
);
21330 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21333 for (fragp
= seginfo
->frchainP
->frch_root
;
21335 fragp
= fragp
->fr_next
)
21337 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21338 fragS
*next
= fragp
->fr_next
;
21340 /* Variable-sized frags have been converted to fixed size by
21341 this point. But if this was variable-sized to start with,
21342 there will be a fixed-size frag after it. So don't handle
21344 if (sym
== NULL
|| next
== NULL
)
21347 if (S_GET_VALUE (sym
) < next
->fr_address
)
21348 /* Not at the end of this frag. */
21350 know (S_GET_VALUE (sym
) == next
->fr_address
);
21354 if (next
->tc_frag_data
.first_map
!= NULL
)
21356 /* Next frag starts with a mapping symbol. Discard this
21358 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21362 if (next
->fr_next
== NULL
)
21364 /* This mapping symbol is at the end of the section. Discard
21366 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21367 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21371 /* As long as we have empty frags without any mapping symbols,
21373 /* If the next frag is non-empty and does not start with a
21374 mapping symbol, then this mapping symbol is required. */
21375 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21378 next
= next
->fr_next
;
21380 while (next
!= NULL
);
21385 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21389 arm_adjust_symtab (void)
21394 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21396 if (ARM_IS_THUMB (sym
))
21398 if (THUMB_IS_FUNC (sym
))
21400 /* Mark the symbol as a Thumb function. */
21401 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21402 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21403 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21405 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21406 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21408 as_bad (_("%s: unexpected function type: %d"),
21409 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21411 else switch (S_GET_STORAGE_CLASS (sym
))
21414 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21417 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21420 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21428 if (ARM_IS_INTERWORK (sym
))
21429 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21436 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21438 if (ARM_IS_THUMB (sym
))
21440 elf_symbol_type
* elf_sym
;
21442 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21443 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21445 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21446 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21448 /* If it's a .thumb_func, declare it as so,
21449 otherwise tag label as .code 16. */
21450 if (THUMB_IS_FUNC (sym
))
21451 elf_sym
->internal_elf_sym
.st_info
=
21452 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21453 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21454 elf_sym
->internal_elf_sym
.st_info
=
21455 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21460 /* Remove any overlapping mapping symbols generated by alignment frags. */
21461 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21465 /* MD interface: Initialization. */
21468 set_constant_flonums (void)
21472 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21473 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21477 /* Auto-select Thumb mode if it's the only available instruction set for the
21478 given architecture. */
21481 autoselect_thumb_from_cpu_variant (void)
21483 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21484 opcode_select (16);
21493 if ( (arm_ops_hsh
= hash_new ()) == NULL
21494 || (arm_cond_hsh
= hash_new ()) == NULL
21495 || (arm_shift_hsh
= hash_new ()) == NULL
21496 || (arm_psr_hsh
= hash_new ()) == NULL
21497 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21498 || (arm_reg_hsh
= hash_new ()) == NULL
21499 || (arm_reloc_hsh
= hash_new ()) == NULL
21500 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21501 as_fatal (_("virtual memory exhausted"));
21503 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21504 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21505 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21506 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21507 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21508 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21509 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21510 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21511 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21512 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21513 (void *) (v7m_psrs
+ i
));
21514 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21515 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21517 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21519 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21520 (void *) (barrier_opt_names
+ i
));
21522 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21523 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21526 set_constant_flonums ();
21528 /* Set the cpu variant based on the command-line options. We prefer
21529 -mcpu= over -march= if both are set (as for GCC); and we prefer
21530 -mfpu= over any other way of setting the floating point unit.
21531 Use of legacy options with new options are faulted. */
21534 if (mcpu_cpu_opt
|| march_cpu_opt
)
21535 as_bad (_("use of old and new-style options to set CPU type"));
21537 mcpu_cpu_opt
= legacy_cpu
;
21539 else if (!mcpu_cpu_opt
)
21540 mcpu_cpu_opt
= march_cpu_opt
;
21545 as_bad (_("use of old and new-style options to set FPU type"));
21547 mfpu_opt
= legacy_fpu
;
21549 else if (!mfpu_opt
)
21551 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21552 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21553 /* Some environments specify a default FPU. If they don't, infer it
21554 from the processor. */
21556 mfpu_opt
= mcpu_fpu_opt
;
21558 mfpu_opt
= march_fpu_opt
;
21560 mfpu_opt
= &fpu_default
;
21566 if (mcpu_cpu_opt
!= NULL
)
21567 mfpu_opt
= &fpu_default
;
21568 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21569 mfpu_opt
= &fpu_arch_vfp_v2
;
21571 mfpu_opt
= &fpu_arch_fpa
;
21577 mcpu_cpu_opt
= &cpu_default
;
21578 selected_cpu
= cpu_default
;
21582 selected_cpu
= *mcpu_cpu_opt
;
21584 mcpu_cpu_opt
= &arm_arch_any
;
21587 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21589 autoselect_thumb_from_cpu_variant ();
21591 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21593 #if defined OBJ_COFF || defined OBJ_ELF
21595 unsigned int flags
= 0;
21597 #if defined OBJ_ELF
21598 flags
= meabi_flags
;
21600 switch (meabi_flags
)
21602 case EF_ARM_EABI_UNKNOWN
:
21604 /* Set the flags in the private structure. */
21605 if (uses_apcs_26
) flags
|= F_APCS26
;
21606 if (support_interwork
) flags
|= F_INTERWORK
;
21607 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21608 if (pic_code
) flags
|= F_PIC
;
21609 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21610 flags
|= F_SOFT_FLOAT
;
21612 switch (mfloat_abi_opt
)
21614 case ARM_FLOAT_ABI_SOFT
:
21615 case ARM_FLOAT_ABI_SOFTFP
:
21616 flags
|= F_SOFT_FLOAT
;
21619 case ARM_FLOAT_ABI_HARD
:
21620 if (flags
& F_SOFT_FLOAT
)
21621 as_bad (_("hard-float conflicts with specified fpu"));
21625 /* Using pure-endian doubles (even if soft-float). */
21626 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21627 flags
|= F_VFP_FLOAT
;
21629 #if defined OBJ_ELF
21630 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21631 flags
|= EF_ARM_MAVERICK_FLOAT
;
21634 case EF_ARM_EABI_VER4
:
21635 case EF_ARM_EABI_VER5
:
21636 /* No additional flags to set. */
21643 bfd_set_private_flags (stdoutput
, flags
);
21645 /* We have run out flags in the COFF header to encode the
21646 status of ATPCS support, so instead we create a dummy,
21647 empty, debug section called .arm.atpcs. */
21652 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21656 bfd_set_section_flags
21657 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21658 bfd_set_section_size (stdoutput
, sec
, 0);
21659 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21665 /* Record the CPU type as well. */
21666 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21667 mach
= bfd_mach_arm_iWMMXt2
;
21668 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21669 mach
= bfd_mach_arm_iWMMXt
;
21670 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21671 mach
= bfd_mach_arm_XScale
;
21672 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21673 mach
= bfd_mach_arm_ep9312
;
21674 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21675 mach
= bfd_mach_arm_5TE
;
21676 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21678 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21679 mach
= bfd_mach_arm_5T
;
21681 mach
= bfd_mach_arm_5
;
21683 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21685 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21686 mach
= bfd_mach_arm_4T
;
21688 mach
= bfd_mach_arm_4
;
21690 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21691 mach
= bfd_mach_arm_3M
;
21692 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21693 mach
= bfd_mach_arm_3
;
21694 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21695 mach
= bfd_mach_arm_2a
;
21696 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21697 mach
= bfd_mach_arm_2
;
21699 mach
= bfd_mach_arm_unknown
;
21701 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21704 /* Command line processing. */
21707 Invocation line includes a switch not recognized by the base assembler.
21708 See if it's a processor-specific option.
21710 This routine is somewhat complicated by the need for backwards
21711 compatibility (since older releases of gcc can't be changed).
21712 The new options try to make the interface as compatible as
21715 New options (supported) are:
21717 -mcpu=<cpu name> Assemble for selected processor
21718 -march=<architecture name> Assemble for selected architecture
21719 -mfpu=<fpu architecture> Assemble for selected FPU.
21720 -EB/-mbig-endian Big-endian
21721 -EL/-mlittle-endian Little-endian
21722 -k Generate PIC code
21723 -mthumb Start in Thumb mode
21724 -mthumb-interwork Code supports ARM/Thumb interworking
21726 -m[no-]warn-deprecated Warn about deprecated features
21728 For now we will also provide support for:
21730 -mapcs-32 32-bit Program counter
21731 -mapcs-26 26-bit Program counter
21732 -macps-float Floats passed in FP registers
21733 -mapcs-reentrant Reentrant code
21735 (sometime these will probably be replaced with -mapcs=<list of options>
21736 and -matpcs=<list of options>)
21738 The remaining options are only supported for back-wards compatibility.
21739 Cpu variants, the arm part is optional:
21740 -m[arm]1 Currently not supported.
21741 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21742 -m[arm]3 Arm 3 processor
21743 -m[arm]6[xx], Arm 6 processors
21744 -m[arm]7[xx][t][[d]m] Arm 7 processors
21745 -m[arm]8[10] Arm 8 processors
21746 -m[arm]9[20][tdmi] Arm 9 processors
21747 -mstrongarm[110[0]] StrongARM processors
21748 -mxscale XScale processors
21749 -m[arm]v[2345[t[e]]] Arm architectures
21750 -mall All (except the ARM1)
21752 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
21753 -mfpe-old (No float load/store multiples)
21754 -mvfpxd VFP Single precision
21756 -mno-fpu Disable all floating point instructions
21758 The following CPU names are recognized:
21759 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
21760 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
21761 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
21762 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
21763 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
21764 arm10t arm10e, arm1020t, arm1020e, arm10200e,
21765 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
21769 const char * md_shortopts
= "m:k";
21771 #ifdef ARM_BI_ENDIAN
21772 #define OPTION_EB (OPTION_MD_BASE + 0)
21773 #define OPTION_EL (OPTION_MD_BASE + 1)
21775 #if TARGET_BYTES_BIG_ENDIAN
21776 #define OPTION_EB (OPTION_MD_BASE + 0)
21778 #define OPTION_EL (OPTION_MD_BASE + 1)
21781 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
21783 struct option md_longopts
[] =
21786 {"EB", no_argument
, NULL
, OPTION_EB
},
21789 {"EL", no_argument
, NULL
, OPTION_EL
},
21791 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
21792 {NULL
, no_argument
, NULL
, 0}
21795 size_t md_longopts_size
= sizeof (md_longopts
);
21797 struct arm_option_table
21799 char *option
; /* Option name to match. */
21800 char *help
; /* Help information. */
21801 int *var
; /* Variable to change. */
21802 int value
; /* What to change it to. */
21803 char *deprecated
; /* If non-null, print this message. */
21806 struct arm_option_table arm_opts
[] =
21808 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
21809 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
21810 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
21811 &support_interwork
, 1, NULL
},
21812 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
21813 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
21814 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
21816 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
21817 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
21818 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
21819 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
21822 /* These are recognized by the assembler, but have no affect on code. */
21823 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
21824 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
21826 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
21827 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
21828 &warn_on_deprecated
, 0, NULL
},
21829 {NULL
, NULL
, NULL
, 0, NULL
}
21832 struct arm_legacy_option_table
21834 char *option
; /* Option name to match. */
21835 const arm_feature_set
**var
; /* Variable to change. */
21836 const arm_feature_set value
; /* What to change it to. */
21837 char *deprecated
; /* If non-null, print this message. */
21840 const struct arm_legacy_option_table arm_legacy_opts
[] =
21842 /* DON'T add any new processors to this list -- we want the whole list
21843 to go away... Add them to the processors table instead. */
21844 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21845 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21846 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21847 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21848 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21849 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21850 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21851 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21852 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21853 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21854 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21855 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21856 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21857 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21858 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21859 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21860 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21861 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21862 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21863 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21864 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21865 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21866 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21867 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21868 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21869 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21870 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21871 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21872 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21873 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21874 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21875 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21876 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21877 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21878 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21879 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21880 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21881 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21882 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21883 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21884 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21885 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21886 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21887 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21888 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21889 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21890 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21891 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21892 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21893 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21894 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21895 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21896 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21897 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21898 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21899 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21900 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21901 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21902 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21903 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21904 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21905 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21906 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21907 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21908 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21909 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21910 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21911 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21912 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
21913 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
21914 N_("use -mcpu=strongarm110")},
21915 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
21916 N_("use -mcpu=strongarm1100")},
21917 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
21918 N_("use -mcpu=strongarm1110")},
21919 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
21920 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
21921 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
21923 /* Architecture variants -- don't add any more to this list either. */
21924 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21925 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21926 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21927 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21928 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21929 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21930 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21931 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21932 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21933 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21934 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21935 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21936 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21937 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21938 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21939 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21940 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21941 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21943 /* Floating point variants -- don't add any more to this list either. */
21944 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
21945 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
21946 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
21947 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
21948 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
21950 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
21953 struct arm_cpu_option_table
21956 const arm_feature_set value
;
21957 /* For some CPUs we assume an FPU unless the user explicitly sets
21959 const arm_feature_set default_fpu
;
21960 /* The canonical name of the CPU, or NULL to use NAME converted to upper
21962 const char *canonical_name
;
21965 /* This list should, at a minimum, contain all the cpu names
21966 recognized by GCC. */
21967 static const struct arm_cpu_option_table arm_cpus
[] =
21969 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
21970 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
21971 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
21972 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21973 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21974 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21975 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21976 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21977 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21978 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21979 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21980 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21981 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21982 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21983 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21984 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21985 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21986 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21987 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21988 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21989 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21990 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21991 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21992 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21993 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21994 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21995 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21996 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21997 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21998 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21999 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22000 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22001 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22002 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22003 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22004 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22005 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22006 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22007 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22008 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22009 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22010 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22011 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22012 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22013 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22014 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22015 /* For V5 or later processors we default to using VFP; but the user
22016 should really set the FPU type explicitly. */
22017 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22018 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22019 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22020 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22021 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22022 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22023 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22024 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22025 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22026 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22027 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22028 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22029 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22030 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22031 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22032 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22033 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22034 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22035 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22036 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22037 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22038 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22039 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22040 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22041 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22042 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22043 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22044 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
22045 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
22046 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22047 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22048 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22049 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22050 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, NULL
},
22051 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22052 | FPU_NEON_EXT_V1
),
22054 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22055 | FPU_NEON_EXT_V1
),
22057 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
22058 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
, NULL
},
22059 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
22060 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22061 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22062 /* ??? XSCALE is really an architecture. */
22063 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22064 /* ??? iwmmxt is not a processor. */
22065 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22066 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22067 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22069 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22070 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22073 struct arm_arch_option_table
22076 const arm_feature_set value
;
22077 const arm_feature_set default_fpu
;
22080 /* This list should, at a minimum, contain all the architecture names
22081 recognized by GCC. */
22082 static const struct arm_arch_option_table arm_archs
[] =
22084 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22085 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22086 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22087 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22088 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22089 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22090 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22091 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22092 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22093 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22094 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22095 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22096 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22097 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22098 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22099 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22100 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22101 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22102 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22103 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22104 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22105 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22106 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22107 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22108 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22109 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22110 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22111 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22112 /* The official spelling of the ARMv7 profile variants is the dashed form.
22113 Accept the non-dashed form for compatibility with old toolchains. */
22114 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22115 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22116 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22117 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22118 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22119 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22120 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22121 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22122 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22123 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22124 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22127 /* ISA extensions in the co-processor space. */
22128 struct arm_option_cpu_value_table
22131 const arm_feature_set value
;
22134 static const struct arm_option_cpu_value_table arm_extensions
[] =
22136 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
22137 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
22138 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
22139 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
22140 {NULL
, ARM_ARCH_NONE
}
22143 /* This list should, at a minimum, contain all the fpu names
22144 recognized by GCC. */
22145 static const struct arm_option_cpu_value_table arm_fpus
[] =
22147 {"softfpa", FPU_NONE
},
22148 {"fpe", FPU_ARCH_FPE
},
22149 {"fpe2", FPU_ARCH_FPE
},
22150 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22151 {"fpa", FPU_ARCH_FPA
},
22152 {"fpa10", FPU_ARCH_FPA
},
22153 {"fpa11", FPU_ARCH_FPA
},
22154 {"arm7500fe", FPU_ARCH_FPA
},
22155 {"softvfp", FPU_ARCH_VFP
},
22156 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22157 {"vfp", FPU_ARCH_VFP_V2
},
22158 {"vfp9", FPU_ARCH_VFP_V2
},
22159 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22160 {"vfp10", FPU_ARCH_VFP_V2
},
22161 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22162 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22163 {"vfpv2", FPU_ARCH_VFP_V2
},
22164 {"vfpv3", FPU_ARCH_VFP_V3
},
22165 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22166 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22167 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22168 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22169 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22170 {"arm1020t", FPU_ARCH_VFP_V1
},
22171 {"arm1020e", FPU_ARCH_VFP_V2
},
22172 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22173 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22174 {"maverick", FPU_ARCH_MAVERICK
},
22175 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22176 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22177 {"vfpv4", FPU_ARCH_VFP_V4
},
22178 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22179 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22180 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22181 {NULL
, ARM_ARCH_NONE
}
22184 struct arm_option_value_table
22190 static const struct arm_option_value_table arm_float_abis
[] =
22192 {"hard", ARM_FLOAT_ABI_HARD
},
22193 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22194 {"soft", ARM_FLOAT_ABI_SOFT
},
22199 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22200 static const struct arm_option_value_table arm_eabis
[] =
22202 {"gnu", EF_ARM_EABI_UNKNOWN
},
22203 {"4", EF_ARM_EABI_VER4
},
22204 {"5", EF_ARM_EABI_VER5
},
22209 struct arm_long_option_table
22211 char * option
; /* Substring to match. */
22212 char * help
; /* Help information. */
22213 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22214 char * deprecated
; /* If non-null, print this message. */
22218 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22220 arm_feature_set
*ext_set
= (arm_feature_set
*)
22221 xmalloc (sizeof (arm_feature_set
));
22223 /* Copy the feature set, so that we can modify it. */
22224 *ext_set
= **opt_p
;
22227 while (str
!= NULL
&& *str
!= 0)
22229 const struct arm_option_cpu_value_table
* opt
;
22235 as_bad (_("invalid architectural extension"));
22240 ext
= strchr (str
, '+');
22243 optlen
= ext
- str
;
22245 optlen
= strlen (str
);
22249 as_bad (_("missing architectural extension"));
22253 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22254 if (strncmp (opt
->name
, str
, optlen
) == 0)
22256 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22260 if (opt
->name
== NULL
)
22262 as_bad (_("unknown architectural extension `%s'"), str
);
22273 arm_parse_cpu (char * str
)
22275 const struct arm_cpu_option_table
* opt
;
22276 char * ext
= strchr (str
, '+');
22280 optlen
= ext
- str
;
22282 optlen
= strlen (str
);
22286 as_bad (_("missing cpu name `%s'"), str
);
22290 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22291 if (strncmp (opt
->name
, str
, optlen
) == 0)
22293 mcpu_cpu_opt
= &opt
->value
;
22294 mcpu_fpu_opt
= &opt
->default_fpu
;
22295 if (opt
->canonical_name
)
22296 strcpy (selected_cpu_name
, opt
->canonical_name
);
22301 for (i
= 0; i
< optlen
; i
++)
22302 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22303 selected_cpu_name
[i
] = 0;
22307 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22312 as_bad (_("unknown cpu `%s'"), str
);
22317 arm_parse_arch (char * str
)
22319 const struct arm_arch_option_table
*opt
;
22320 char *ext
= strchr (str
, '+');
22324 optlen
= ext
- str
;
22326 optlen
= strlen (str
);
22330 as_bad (_("missing architecture name `%s'"), str
);
22334 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22335 if (streq (opt
->name
, str
))
22337 march_cpu_opt
= &opt
->value
;
22338 march_fpu_opt
= &opt
->default_fpu
;
22339 strcpy (selected_cpu_name
, opt
->name
);
22342 return arm_parse_extension (ext
, &march_cpu_opt
);
22347 as_bad (_("unknown architecture `%s'\n"), str
);
22352 arm_parse_fpu (char * str
)
22354 const struct arm_option_cpu_value_table
* opt
;
22356 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22357 if (streq (opt
->name
, str
))
22359 mfpu_opt
= &opt
->value
;
22363 as_bad (_("unknown floating point format `%s'\n"), str
);
22368 arm_parse_float_abi (char * str
)
22370 const struct arm_option_value_table
* opt
;
22372 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22373 if (streq (opt
->name
, str
))
22375 mfloat_abi_opt
= opt
->value
;
22379 as_bad (_("unknown floating point abi `%s'\n"), str
);
22385 arm_parse_eabi (char * str
)
22387 const struct arm_option_value_table
*opt
;
22389 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22390 if (streq (opt
->name
, str
))
22392 meabi_flags
= opt
->value
;
22395 as_bad (_("unknown EABI `%s'\n"), str
);
22401 arm_parse_it_mode (char * str
)
22403 bfd_boolean ret
= TRUE
;
22405 if (streq ("arm", str
))
22406 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22407 else if (streq ("thumb", str
))
22408 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22409 else if (streq ("always", str
))
22410 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22411 else if (streq ("never", str
))
22412 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22415 as_bad (_("unknown implicit IT mode `%s', should be "\
22416 "arm, thumb, always, or never."), str
);
22423 struct arm_long_option_table arm_long_opts
[] =
22425 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22426 arm_parse_cpu
, NULL
},
22427 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22428 arm_parse_arch
, NULL
},
22429 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22430 arm_parse_fpu
, NULL
},
22431 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22432 arm_parse_float_abi
, NULL
},
22434 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22435 arm_parse_eabi
, NULL
},
22437 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22438 arm_parse_it_mode
, NULL
},
22439 {NULL
, NULL
, 0, NULL
}
22443 md_parse_option (int c
, char * arg
)
22445 struct arm_option_table
*opt
;
22446 const struct arm_legacy_option_table
*fopt
;
22447 struct arm_long_option_table
*lopt
;
22453 target_big_endian
= 1;
22459 target_big_endian
= 0;
22463 case OPTION_FIX_V4BX
:
22468 /* Listing option. Just ignore these, we don't support additional
22473 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22475 if (c
== opt
->option
[0]
22476 && ((arg
== NULL
&& opt
->option
[1] == 0)
22477 || streq (arg
, opt
->option
+ 1)))
22479 /* If the option is deprecated, tell the user. */
22480 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22481 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22482 arg
? arg
: "", _(opt
->deprecated
));
22484 if (opt
->var
!= NULL
)
22485 *opt
->var
= opt
->value
;
22491 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22493 if (c
== fopt
->option
[0]
22494 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22495 || streq (arg
, fopt
->option
+ 1)))
22497 /* If the option is deprecated, tell the user. */
22498 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22499 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22500 arg
? arg
: "", _(fopt
->deprecated
));
22502 if (fopt
->var
!= NULL
)
22503 *fopt
->var
= &fopt
->value
;
22509 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22511 /* These options are expected to have an argument. */
22512 if (c
== lopt
->option
[0]
22514 && strncmp (arg
, lopt
->option
+ 1,
22515 strlen (lopt
->option
+ 1)) == 0)
22517 /* If the option is deprecated, tell the user. */
22518 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22519 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22520 _(lopt
->deprecated
));
22522 /* Call the sup-option parser. */
22523 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22534 md_show_usage (FILE * fp
)
22536 struct arm_option_table
*opt
;
22537 struct arm_long_option_table
*lopt
;
22539 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22541 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22542 if (opt
->help
!= NULL
)
22543 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22545 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22546 if (lopt
->help
!= NULL
)
22547 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22551 -EB assemble code for a big-endian cpu\n"));
22556 -EL assemble code for a little-endian cpu\n"));
22560 --fix-v4bx Allow BX in ARMv4 code\n"));
22568 arm_feature_set flags
;
22569 } cpu_arch_ver_table
;
22571 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22572 least features first. */
22573 static const cpu_arch_ver_table cpu_arch_ver
[] =
22579 {4, ARM_ARCH_V5TE
},
22580 {5, ARM_ARCH_V5TEJ
},
22584 {11, ARM_ARCH_V6M
},
22585 {8, ARM_ARCH_V6T2
},
22586 {10, ARM_ARCH_V7A
},
22587 {10, ARM_ARCH_V7R
},
22588 {10, ARM_ARCH_V7M
},
22592 /* Set an attribute if it has not already been set by the user. */
22594 aeabi_set_attribute_int (int tag
, int value
)
22597 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22598 || !attributes_set_explicitly
[tag
])
22599 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22603 aeabi_set_attribute_string (int tag
, const char *value
)
22606 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22607 || !attributes_set_explicitly
[tag
])
22608 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22611 /* Set the public EABI object attributes. */
22613 aeabi_set_public_attributes (void)
22616 arm_feature_set flags
;
22617 arm_feature_set tmp
;
22618 const cpu_arch_ver_table
*p
;
22620 /* Choose the architecture based on the capabilities of the requested cpu
22621 (if any) and/or the instructions actually used. */
22622 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22623 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22624 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22625 /*Allow the user to override the reported architecture. */
22628 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22629 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22634 for (p
= cpu_arch_ver
; p
->val
; p
++)
22636 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22639 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22643 /* The table lookup above finds the last architecture to contribute
22644 a new feature. Unfortunately, Tag13 is a subset of the union of
22645 v6T2 and v7-M, so it is never seen as contributing a new feature.
22646 We can not search for the last entry which is entirely used,
22647 because if no CPU is specified we build up only those flags
22648 actually used. Perhaps we should separate out the specified
22649 and implicit cases. Avoid taking this path for -march=all by
22650 checking for contradictory v7-A / v7-M features. */
22652 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
22653 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
22654 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
22657 /* Tag_CPU_name. */
22658 if (selected_cpu_name
[0])
22662 q
= selected_cpu_name
;
22663 if (strncmp (q
, "armv", 4) == 0)
22668 for (i
= 0; q
[i
]; i
++)
22669 q
[i
] = TOUPPER (q
[i
]);
22671 aeabi_set_attribute_string (Tag_CPU_name
, q
);
22674 /* Tag_CPU_arch. */
22675 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22677 /* Tag_CPU_arch_profile. */
22678 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22679 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22680 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22681 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22682 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22683 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22685 /* Tag_ARM_ISA_use. */
22686 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22688 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22690 /* Tag_THUMB_ISA_use. */
22691 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22693 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22694 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22696 /* Tag_VFP_arch. */
22697 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
22698 aeabi_set_attribute_int (Tag_VFP_arch
,
22699 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
22701 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22702 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22703 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
22704 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22705 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22706 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22707 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22708 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22709 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22711 /* Tag_WMMX_arch. */
22712 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22713 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22714 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22715 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22717 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22718 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22719 aeabi_set_attribute_int
22720 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
22723 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22724 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
22725 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22728 /* Add the default contents for the .ARM.attributes section. */
22732 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22735 aeabi_set_public_attributes ();
22737 #endif /* OBJ_ELF */
22740 /* Parse a .cpu directive. */
22743 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
22745 const struct arm_cpu_option_table
*opt
;
22749 name
= input_line_pointer
;
22750 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22751 input_line_pointer
++;
22752 saved_char
= *input_line_pointer
;
22753 *input_line_pointer
= 0;
22755 /* Skip the first "all" entry. */
22756 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
22757 if (streq (opt
->name
, name
))
22759 mcpu_cpu_opt
= &opt
->value
;
22760 selected_cpu
= opt
->value
;
22761 if (opt
->canonical_name
)
22762 strcpy (selected_cpu_name
, opt
->canonical_name
);
22766 for (i
= 0; opt
->name
[i
]; i
++)
22767 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22768 selected_cpu_name
[i
] = 0;
22770 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22771 *input_line_pointer
= saved_char
;
22772 demand_empty_rest_of_line ();
22775 as_bad (_("unknown cpu `%s'"), name
);
22776 *input_line_pointer
= saved_char
;
22777 ignore_rest_of_line ();
22781 /* Parse a .arch directive. */
22784 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
22786 const struct arm_arch_option_table
*opt
;
22790 name
= input_line_pointer
;
22791 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22792 input_line_pointer
++;
22793 saved_char
= *input_line_pointer
;
22794 *input_line_pointer
= 0;
22796 /* Skip the first "all" entry. */
22797 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22798 if (streq (opt
->name
, name
))
22800 mcpu_cpu_opt
= &opt
->value
;
22801 selected_cpu
= opt
->value
;
22802 strcpy (selected_cpu_name
, opt
->name
);
22803 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22804 *input_line_pointer
= saved_char
;
22805 demand_empty_rest_of_line ();
22809 as_bad (_("unknown architecture `%s'\n"), name
);
22810 *input_line_pointer
= saved_char
;
22811 ignore_rest_of_line ();
22815 /* Parse a .object_arch directive. */
22818 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
22820 const struct arm_arch_option_table
*opt
;
22824 name
= input_line_pointer
;
22825 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22826 input_line_pointer
++;
22827 saved_char
= *input_line_pointer
;
22828 *input_line_pointer
= 0;
22830 /* Skip the first "all" entry. */
22831 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22832 if (streq (opt
->name
, name
))
22834 object_arch
= &opt
->value
;
22835 *input_line_pointer
= saved_char
;
22836 demand_empty_rest_of_line ();
22840 as_bad (_("unknown architecture `%s'\n"), name
);
22841 *input_line_pointer
= saved_char
;
22842 ignore_rest_of_line ();
22845 /* Parse a .fpu directive. */
22848 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
22850 const struct arm_option_cpu_value_table
*opt
;
22854 name
= input_line_pointer
;
22855 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22856 input_line_pointer
++;
22857 saved_char
= *input_line_pointer
;
22858 *input_line_pointer
= 0;
22860 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22861 if (streq (opt
->name
, name
))
22863 mfpu_opt
= &opt
->value
;
22864 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22865 *input_line_pointer
= saved_char
;
22866 demand_empty_rest_of_line ();
22870 as_bad (_("unknown floating point format `%s'\n"), name
);
22871 *input_line_pointer
= saved_char
;
22872 ignore_rest_of_line ();
22875 /* Copy symbol information. */
22878 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
22880 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
22884 /* Given a symbolic attribute NAME, return the proper integer value.
22885 Returns -1 if the attribute is not known. */
22888 arm_convert_symbolic_attribute (const char *name
)
22890 static const struct
22895 attribute_table
[] =
22897 /* When you modify this table you should
22898 also modify the list in doc/c-arm.texi. */
22899 #define T(tag) {#tag, tag}
22900 T (Tag_CPU_raw_name
),
22903 T (Tag_CPU_arch_profile
),
22904 T (Tag_ARM_ISA_use
),
22905 T (Tag_THUMB_ISA_use
),
22908 T (Tag_Advanced_SIMD_arch
),
22909 T (Tag_PCS_config
),
22910 T (Tag_ABI_PCS_R9_use
),
22911 T (Tag_ABI_PCS_RW_data
),
22912 T (Tag_ABI_PCS_RO_data
),
22913 T (Tag_ABI_PCS_GOT_use
),
22914 T (Tag_ABI_PCS_wchar_t
),
22915 T (Tag_ABI_FP_rounding
),
22916 T (Tag_ABI_FP_denormal
),
22917 T (Tag_ABI_FP_exceptions
),
22918 T (Tag_ABI_FP_user_exceptions
),
22919 T (Tag_ABI_FP_number_model
),
22920 T (Tag_ABI_align8_needed
),
22921 T (Tag_ABI_align8_preserved
),
22922 T (Tag_ABI_enum_size
),
22923 T (Tag_ABI_HardFP_use
),
22924 T (Tag_ABI_VFP_args
),
22925 T (Tag_ABI_WMMX_args
),
22926 T (Tag_ABI_optimization_goals
),
22927 T (Tag_ABI_FP_optimization_goals
),
22928 T (Tag_compatibility
),
22929 T (Tag_CPU_unaligned_access
),
22930 T (Tag_VFP_HP_extension
),
22931 T (Tag_ABI_FP_16bit_format
),
22932 T (Tag_nodefaults
),
22933 T (Tag_also_compatible_with
),
22934 T (Tag_conformance
),
22936 T (Tag_Virtualization_use
),
22937 T (Tag_MPextension_use
)
22945 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
22946 if (streq (name
, attribute_table
[i
].name
))
22947 return attribute_table
[i
].tag
;
22953 /* Apply sym value for relocations only in the case that
22954 they are for local symbols and you have the respective
22955 architectural feature for blx and simple switches. */
22957 arm_apply_sym_value (struct fix
* fixP
)
22960 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22961 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
22963 switch (fixP
->fx_r_type
)
22965 case BFD_RELOC_ARM_PCREL_BLX
:
22966 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22967 if (ARM_IS_FUNC (fixP
->fx_addsy
))
22971 case BFD_RELOC_ARM_PCREL_CALL
:
22972 case BFD_RELOC_THUMB_PCREL_BLX
:
22973 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
22984 #endif /* OBJ_ELF */