1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
80 /* Bit N indicates that an R_ARM_NONE relocation has been output for
81 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
82 emitted only once per section, to save unnecessary bloat. */
83 static unsigned int marked_pr_dependency
= 0;
87 /* Results from operand parsing worker functions. */
91 PARSE_OPERAND_SUCCESS
,
93 PARSE_OPERAND_FAIL_NO_BACKTRACK
94 } parse_operand_result
;
103 /* Types of processor to assemble for. */
105 #if defined __XSCALE__
106 #define CPU_DEFAULT ARM_ARCH_XSCALE
108 #if defined __thumb__
109 #define CPU_DEFAULT ARM_ARCH_V5T
116 # define FPU_DEFAULT FPU_ARCH_FPA
117 # elif defined (TE_NetBSD)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
121 /* Legacy a.out format. */
122 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
124 # elif defined (TE_VXWORKS)
125 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
127 /* For backwards compatibility, default to FPA. */
128 # define FPU_DEFAULT FPU_ARCH_FPA
130 #endif /* ifndef FPU_DEFAULT */
132 #define streq(a, b) (strcmp (a, b) == 0)
134 static arm_feature_set cpu_variant
;
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
149 /* Variables that we set while parsing command-line options. Once all
150 options have been read we re-process these values to set the real
152 static const arm_feature_set
*legacy_cpu
= NULL
;
153 static const arm_feature_set
*legacy_fpu
= NULL
;
155 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
156 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
157 static const arm_feature_set
*march_cpu_opt
= NULL
;
158 static const arm_feature_set
*march_fpu_opt
= NULL
;
159 static const arm_feature_set
*mfpu_opt
= NULL
;
160 static const arm_feature_set
*object_arch
= NULL
;
162 /* Constants for known architecture features. */
163 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
164 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
165 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
166 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
167 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
168 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
169 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
170 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
171 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
174 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
177 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
178 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
179 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
180 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
181 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
182 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
183 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
184 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
185 static const arm_feature_set arm_ext_v4t_5
=
186 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
187 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
188 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
189 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
190 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
191 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
192 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
193 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
194 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
195 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
196 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
197 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
198 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
199 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
200 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
201 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
202 static const arm_feature_set arm_ext_m
=
203 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
205 static const arm_feature_set arm_arch_any
= ARM_ANY
;
206 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
207 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
208 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_cext_iwmmxt2
=
211 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
212 static const arm_feature_set arm_cext_iwmmxt
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
214 static const arm_feature_set arm_cext_xscale
=
215 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
216 static const arm_feature_set arm_cext_maverick
=
217 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
218 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
219 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v1xd
=
221 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
222 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
223 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
224 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
225 static const arm_feature_set fpu_vfp_ext_d32
=
226 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
227 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
228 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
229 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
230 static const arm_feature_set fpu_neon_fp16
= ARM_FEATURE (0, FPU_NEON_FP16
);
232 static int mfloat_abi_opt
= -1;
233 /* Record user cpu selection for object attributes. */
234 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
235 /* Must be long enough to hold any of the names in arm_cpus. */
236 static char selected_cpu_name
[16];
239 static int meabi_flags
= EABI_DEFAULT
;
241 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
244 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
249 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
254 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
255 symbolS
* GOT_symbol
;
258 /* 0: assemble for ARM,
259 1: assemble for Thumb,
260 2: assemble for Thumb even though target CPU does not support thumb
262 static int thumb_mode
= 0;
263 /* A value distinct from the possible values for thumb_mode that we
264 can use to record whether thumb_mode has been copied into the
265 tc_frag_data field of a frag. */
266 #define MODE_RECORDED (1 << 4)
268 /* If unified_syntax is true, we are processing the new unified
269 ARM/Thumb syntax. Important differences from the old ARM mode:
271 - Immediate operands do not require a # prefix.
272 - Conditional affixes always appear at the end of the
273 instruction. (For backward compatibility, those instructions
274 that formerly had them in the middle, continue to accept them
276 - The IT instruction may appear, and if it does is validated
277 against subsequent conditional affixes. It does not generate
280 Important differences from the old Thumb mode:
282 - Immediate operands do not require a # prefix.
283 - Most of the V6T2 instructions are only available in unified mode.
284 - The .N and .W suffixes are recognized and honored (it is an error
285 if they cannot be honored).
286 - All instructions set the flags if and only if they have an 's' affix.
287 - Conditional affixes may be used. They are validated against
288 preceding IT instructions. Unlike ARM mode, you cannot use a
289 conditional affix except in the scope of an IT instruction. */
291 static bfd_boolean unified_syntax
= FALSE
;
306 enum neon_el_type type
;
310 #define NEON_MAX_TYPE_ELS 4
314 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
321 unsigned long instruction
;
325 /* "uncond_value" is set to the value in place of the conditional field in
326 unconditional versions of the instruction, or -1 if nothing is
329 struct neon_type vectype
;
330 /* Set to the opcode if the instruction needs relaxation.
331 Zero if the instruction is not relaxed. */
335 bfd_reloc_code_real_type type
;
344 struct neon_type_el vectype
;
345 unsigned present
: 1; /* Operand present. */
346 unsigned isreg
: 1; /* Operand was a register. */
347 unsigned immisreg
: 1; /* .imm field is a second register. */
348 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
349 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
350 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
351 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
352 instructions. This allows us to disambiguate ARM <-> vector insns. */
353 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
354 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
355 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
356 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
357 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
358 unsigned writeback
: 1; /* Operand has trailing ! */
359 unsigned preind
: 1; /* Preindexed address. */
360 unsigned postind
: 1; /* Postindexed address. */
361 unsigned negative
: 1; /* Index register was negated. */
362 unsigned shifted
: 1; /* Shift applied to operation. */
363 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
367 static struct arm_it inst
;
369 #define NUM_FLOAT_VALS 8
371 const char * fp_const
[] =
373 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
376 /* Number of littlenums required to hold an extended precision number. */
377 #define MAX_LITTLENUMS 6
379 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
389 #define CP_T_X 0x00008000
390 #define CP_T_Y 0x00400000
392 #define CONDS_BIT 0x00100000
393 #define LOAD_BIT 0x00100000
395 #define DOUBLE_LOAD_FLAG 0x00000001
399 const char * template;
403 #define COND_ALWAYS 0xE
407 const char *template;
411 struct asm_barrier_opt
413 const char *template;
417 /* The bit that distinguishes CPSR and SPSR. */
418 #define SPSR_BIT (1 << 22)
420 /* The individual PSR flag bits. */
421 #define PSR_c (1 << 16)
422 #define PSR_x (1 << 17)
423 #define PSR_s (1 << 18)
424 #define PSR_f (1 << 19)
429 bfd_reloc_code_real_type reloc
;
434 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
435 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
440 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
443 /* Bits for DEFINED field in neon_typed_alias. */
444 #define NTA_HASTYPE 1
445 #define NTA_HASINDEX 2
447 struct neon_typed_alias
449 unsigned char defined
;
451 struct neon_type_el eltype
;
454 /* ARM register categories. This includes coprocessor numbers and various
455 architecture extensions' registers. */
481 /* Structure for a hash table entry for a register.
482 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
483 information which states whether a vector type or index is specified (for a
484 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
488 unsigned char number
;
490 unsigned char builtin
;
491 struct neon_typed_alias
*neon
;
494 /* Diagnostics used when we don't get a register of the expected type. */
495 const char *const reg_expected_msgs
[] =
497 N_("ARM register expected"),
498 N_("bad or missing co-processor number"),
499 N_("co-processor register expected"),
500 N_("FPA register expected"),
501 N_("VFP single precision register expected"),
502 N_("VFP/Neon double precision register expected"),
503 N_("Neon quad precision register expected"),
504 N_("VFP single or double precision register expected"),
505 N_("Neon double or quad precision register expected"),
506 N_("VFP single, double or Neon quad precision register expected"),
507 N_("VFP system register expected"),
508 N_("Maverick MVF register expected"),
509 N_("Maverick MVD register expected"),
510 N_("Maverick MVFX register expected"),
511 N_("Maverick MVDX register expected"),
512 N_("Maverick MVAX register expected"),
513 N_("Maverick DSPSC register expected"),
514 N_("iWMMXt data register expected"),
515 N_("iWMMXt control register expected"),
516 N_("iWMMXt scalar register expected"),
517 N_("XScale accumulator register expected"),
520 /* Some well known registers that we refer to directly elsewhere. */
525 /* ARM instructions take 4bytes in the object file, Thumb instructions
531 /* Basic string to match. */
532 const char *template;
534 /* Parameters to instruction. */
535 unsigned char operands
[8];
537 /* Conditional tag - see opcode_lookup. */
538 unsigned int tag
: 4;
540 /* Basic instruction code. */
541 unsigned int avalue
: 28;
543 /* Thumb-format instruction code. */
546 /* Which architecture variant provides this instruction. */
547 const arm_feature_set
*avariant
;
548 const arm_feature_set
*tvariant
;
550 /* Function to call to encode instruction in ARM format. */
551 void (* aencode
) (void);
553 /* Function to call to encode instruction in Thumb format. */
554 void (* tencode
) (void);
557 /* Defines for various bits that we will want to toggle. */
558 #define INST_IMMEDIATE 0x02000000
559 #define OFFSET_REG 0x02000000
560 #define HWOFFSET_IMM 0x00400000
561 #define SHIFT_BY_REG 0x00000010
562 #define PRE_INDEX 0x01000000
563 #define INDEX_UP 0x00800000
564 #define WRITE_BACK 0x00200000
565 #define LDM_TYPE_2_OR_3 0x00400000
566 #define CPSI_MMOD 0x00020000
568 #define LITERAL_MASK 0xf000f000
569 #define OPCODE_MASK 0xfe1fffff
570 #define V4_STR_BIT 0x00000020
572 #define T2_SUBS_PC_LR 0xf3de8f00
574 #define DATA_OP_SHIFT 21
576 #define T2_OPCODE_MASK 0xfe1fffff
577 #define T2_DATA_OP_SHIFT 21
579 /* Codes to distinguish the arithmetic instructions. */
590 #define OPCODE_CMP 10
591 #define OPCODE_CMN 11
592 #define OPCODE_ORR 12
593 #define OPCODE_MOV 13
594 #define OPCODE_BIC 14
595 #define OPCODE_MVN 15
597 #define T2_OPCODE_AND 0
598 #define T2_OPCODE_BIC 1
599 #define T2_OPCODE_ORR 2
600 #define T2_OPCODE_ORN 3
601 #define T2_OPCODE_EOR 4
602 #define T2_OPCODE_ADD 8
603 #define T2_OPCODE_ADC 10
604 #define T2_OPCODE_SBC 11
605 #define T2_OPCODE_SUB 13
606 #define T2_OPCODE_RSB 14
608 #define T_OPCODE_MUL 0x4340
609 #define T_OPCODE_TST 0x4200
610 #define T_OPCODE_CMN 0x42c0
611 #define T_OPCODE_NEG 0x4240
612 #define T_OPCODE_MVN 0x43c0
614 #define T_OPCODE_ADD_R3 0x1800
615 #define T_OPCODE_SUB_R3 0x1a00
616 #define T_OPCODE_ADD_HI 0x4400
617 #define T_OPCODE_ADD_ST 0xb000
618 #define T_OPCODE_SUB_ST 0xb080
619 #define T_OPCODE_ADD_SP 0xa800
620 #define T_OPCODE_ADD_PC 0xa000
621 #define T_OPCODE_ADD_I8 0x3000
622 #define T_OPCODE_SUB_I8 0x3800
623 #define T_OPCODE_ADD_I3 0x1c00
624 #define T_OPCODE_SUB_I3 0x1e00
626 #define T_OPCODE_ASR_R 0x4100
627 #define T_OPCODE_LSL_R 0x4080
628 #define T_OPCODE_LSR_R 0x40c0
629 #define T_OPCODE_ROR_R 0x41c0
630 #define T_OPCODE_ASR_I 0x1000
631 #define T_OPCODE_LSL_I 0x0000
632 #define T_OPCODE_LSR_I 0x0800
634 #define T_OPCODE_MOV_I8 0x2000
635 #define T_OPCODE_CMP_I8 0x2800
636 #define T_OPCODE_CMP_LR 0x4280
637 #define T_OPCODE_MOV_HR 0x4600
638 #define T_OPCODE_CMP_HR 0x4500
640 #define T_OPCODE_LDR_PC 0x4800
641 #define T_OPCODE_LDR_SP 0x9800
642 #define T_OPCODE_STR_SP 0x9000
643 #define T_OPCODE_LDR_IW 0x6800
644 #define T_OPCODE_STR_IW 0x6000
645 #define T_OPCODE_LDR_IH 0x8800
646 #define T_OPCODE_STR_IH 0x8000
647 #define T_OPCODE_LDR_IB 0x7800
648 #define T_OPCODE_STR_IB 0x7000
649 #define T_OPCODE_LDR_RW 0x5800
650 #define T_OPCODE_STR_RW 0x5000
651 #define T_OPCODE_LDR_RH 0x5a00
652 #define T_OPCODE_STR_RH 0x5200
653 #define T_OPCODE_LDR_RB 0x5c00
654 #define T_OPCODE_STR_RB 0x5400
656 #define T_OPCODE_PUSH 0xb400
657 #define T_OPCODE_POP 0xbc00
659 #define T_OPCODE_BRANCH 0xe000
661 #define THUMB_SIZE 2 /* Size of thumb instruction. */
662 #define THUMB_PP_PC_LR 0x0100
663 #define THUMB_LOAD_BIT 0x0800
664 #define THUMB2_LOAD_BIT 0x00100000
666 #define BAD_ARGS _("bad arguments to instruction")
667 #define BAD_SP _("r13 not allowed here")
668 #define BAD_PC _("r15 not allowed here")
669 #define BAD_COND _("instruction cannot be conditional")
670 #define BAD_OVERLAP _("registers may not be the same")
671 #define BAD_HIREG _("lo register required")
672 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
673 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
674 #define BAD_BRANCH _("branch must be last instruction in IT block")
675 #define BAD_NOT_IT _("instruction not allowed in IT block")
676 #define BAD_FPU _("selected FPU does not support instruction")
678 static struct hash_control
*arm_ops_hsh
;
679 static struct hash_control
*arm_cond_hsh
;
680 static struct hash_control
*arm_shift_hsh
;
681 static struct hash_control
*arm_psr_hsh
;
682 static struct hash_control
*arm_v7m_psr_hsh
;
683 static struct hash_control
*arm_reg_hsh
;
684 static struct hash_control
*arm_reloc_hsh
;
685 static struct hash_control
*arm_barrier_opt_hsh
;
687 /* Stuff needed to resolve the label ambiguity
696 symbolS
* last_label_seen
;
697 static int label_is_thumb_function_name
= FALSE
;
699 /* Literal pool structure. Held on a per-section
700 and per-sub-section basis. */
702 #define MAX_LITERAL_POOL_SIZE 1024
703 typedef struct literal_pool
705 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
706 unsigned int next_free_entry
;
711 struct literal_pool
* next
;
714 /* Pointer to a linked list of literal pools. */
715 literal_pool
* list_of_pools
= NULL
;
717 /* State variables for IT block handling. */
718 static bfd_boolean current_it_mask
= 0;
719 static int current_cc
;
723 /* This array holds the chars that always start a comment. If the
724 pre-processor is disabled, these aren't very useful. */
725 const char comment_chars
[] = "@";
727 /* This array holds the chars that only start a comment at the beginning of
728 a line. If the line seems to have the form '# 123 filename'
729 .line and .file directives will appear in the pre-processed output. */
730 /* Note that input_file.c hand checks for '#' at the beginning of the
731 first line of the input file. This is because the compiler outputs
732 #NO_APP at the beginning of its output. */
733 /* Also note that comments like this one will always work. */
734 const char line_comment_chars
[] = "#";
736 const char line_separator_chars
[] = ";";
738 /* Chars that can be used to separate mant
739 from exp in floating point numbers. */
740 const char EXP_CHARS
[] = "eE";
742 /* Chars that mean this number is a floating point constant. */
746 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
748 /* Prefix characters that indicate the start of an immediate
750 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
752 /* Separator character handling. */
754 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
757 skip_past_char (char ** str
, char c
)
767 #define skip_past_comma(str) skip_past_char (str, ',')
769 /* Arithmetic expressions (possibly involving symbols). */
771 /* Return TRUE if anything in the expression is a bignum. */
774 walk_no_bignums (symbolS
* sp
)
776 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
779 if (symbol_get_value_expression (sp
)->X_add_symbol
)
781 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
782 || (symbol_get_value_expression (sp
)->X_op_symbol
783 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
789 static int in_my_get_expression
= 0;
791 /* Third argument to my_get_expression. */
792 #define GE_NO_PREFIX 0
793 #define GE_IMM_PREFIX 1
794 #define GE_OPT_PREFIX 2
795 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
796 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
797 #define GE_OPT_PREFIX_BIG 3
800 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
805 /* In unified syntax, all prefixes are optional. */
807 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
812 case GE_NO_PREFIX
: break;
814 if (!is_immediate_prefix (**str
))
816 inst
.error
= _("immediate expression requires a # prefix");
822 case GE_OPT_PREFIX_BIG
:
823 if (is_immediate_prefix (**str
))
829 memset (ep
, 0, sizeof (expressionS
));
831 save_in
= input_line_pointer
;
832 input_line_pointer
= *str
;
833 in_my_get_expression
= 1;
834 seg
= expression (ep
);
835 in_my_get_expression
= 0;
837 if (ep
->X_op
== O_illegal
)
839 /* We found a bad expression in md_operand(). */
840 *str
= input_line_pointer
;
841 input_line_pointer
= save_in
;
842 if (inst
.error
== NULL
)
843 inst
.error
= _("bad expression");
848 if (seg
!= absolute_section
849 && seg
!= text_section
850 && seg
!= data_section
851 && seg
!= bss_section
852 && seg
!= undefined_section
)
854 inst
.error
= _("bad segment");
855 *str
= input_line_pointer
;
856 input_line_pointer
= save_in
;
861 /* Get rid of any bignums now, so that we don't generate an error for which
862 we can't establish a line number later on. Big numbers are never valid
863 in instructions, which is where this routine is always called. */
864 if (prefix_mode
!= GE_OPT_PREFIX_BIG
865 && (ep
->X_op
== O_big
867 && (walk_no_bignums (ep
->X_add_symbol
)
869 && walk_no_bignums (ep
->X_op_symbol
))))))
871 inst
.error
= _("invalid constant");
872 *str
= input_line_pointer
;
873 input_line_pointer
= save_in
;
877 *str
= input_line_pointer
;
878 input_line_pointer
= save_in
;
882 /* Turn a string in input_line_pointer into a floating point constant
883 of type TYPE, and store the appropriate bytes in *LITP. The number
884 of LITTLENUMS emitted is stored in *SIZEP. An error message is
885 returned, or NULL on OK.
887 Note that fp constants aren't represent in the normal way on the ARM.
888 In big endian mode, things are as expected. However, in little endian
889 mode fp constants are big-endian word-wise, and little-endian byte-wise
890 within the words. For example, (double) 1.1 in big endian mode is
891 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
892 the byte sequence 99 99 f1 3f 9a 99 99 99.
894 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
897 md_atof (int type
, char * litP
, int * sizeP
)
900 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
932 return _("Unrecognized or unsupported floating point constant");
935 t
= atof_ieee (input_line_pointer
, type
, words
);
937 input_line_pointer
= t
;
938 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
940 if (target_big_endian
)
942 for (i
= 0; i
< prec
; i
++)
944 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
945 litP
+= sizeof (LITTLENUM_TYPE
);
950 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
951 for (i
= prec
- 1; i
>= 0; i
--)
953 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
954 litP
+= sizeof (LITTLENUM_TYPE
);
957 /* For a 4 byte float the order of elements in `words' is 1 0.
958 For an 8 byte float the order is 1 0 3 2. */
959 for (i
= 0; i
< prec
; i
+= 2)
961 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
962 sizeof (LITTLENUM_TYPE
));
963 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
964 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
965 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
972 /* We handle all bad expressions here, so that we can report the faulty
973 instruction in the error message. */
975 md_operand (expressionS
* expr
)
977 if (in_my_get_expression
)
978 expr
->X_op
= O_illegal
;
981 /* Immediate values. */
983 /* Generic immediate-value read function for use in directives.
984 Accepts anything that 'expression' can fold to a constant.
985 *val receives the number. */
988 immediate_for_directive (int *val
)
991 exp
.X_op
= O_illegal
;
993 if (is_immediate_prefix (*input_line_pointer
))
995 input_line_pointer
++;
999 if (exp
.X_op
!= O_constant
)
1001 as_bad (_("expected #constant"));
1002 ignore_rest_of_line ();
1005 *val
= exp
.X_add_number
;
1010 /* Register parsing. */
1012 /* Generic register parser. CCP points to what should be the
1013 beginning of a register name. If it is indeed a valid register
1014 name, advance CCP over it and return the reg_entry structure;
1015 otherwise return NULL. Does not issue diagnostics. */
1017 static struct reg_entry
*
1018 arm_reg_parse_multi (char **ccp
)
1022 struct reg_entry
*reg
;
1024 #ifdef REGISTER_PREFIX
1025 if (*start
!= REGISTER_PREFIX
)
1029 #ifdef OPTIONAL_REGISTER_PREFIX
1030 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1035 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1040 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1042 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1052 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1053 enum arm_reg_type type
)
1055 /* Alternative syntaxes are accepted for a few register classes. */
1062 /* Generic coprocessor register names are allowed for these. */
1063 if (reg
&& reg
->type
== REG_TYPE_CN
)
1068 /* For backward compatibility, a bare number is valid here. */
1070 unsigned long processor
= strtoul (start
, ccp
, 10);
1071 if (*ccp
!= start
&& processor
<= 15)
1075 case REG_TYPE_MMXWC
:
1076 /* WC includes WCG. ??? I'm not sure this is true for all
1077 instructions that take WC registers. */
1078 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1089 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1090 return value is the register number or FAIL. */
1093 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1096 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1099 /* Do not allow a scalar (reg+index) to parse as a register. */
1100 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1103 if (reg
&& reg
->type
== type
)
1106 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1113 /* Parse a Neon type specifier. *STR should point at the leading '.'
1114 character. Does no verification at this stage that the type fits the opcode
1121 Can all be legally parsed by this function.
1123 Fills in neon_type struct pointer with parsed information, and updates STR
1124 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1125 type, FAIL if not. */
1128 parse_neon_type (struct neon_type
*type
, char **str
)
1135 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1137 enum neon_el_type thistype
= NT_untyped
;
1138 unsigned thissize
= -1u;
1145 /* Just a size without an explicit type. */
1149 switch (TOLOWER (*ptr
))
1151 case 'i': thistype
= NT_integer
; break;
1152 case 'f': thistype
= NT_float
; break;
1153 case 'p': thistype
= NT_poly
; break;
1154 case 's': thistype
= NT_signed
; break;
1155 case 'u': thistype
= NT_unsigned
; break;
1157 thistype
= NT_float
;
1162 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1168 /* .f is an abbreviation for .f32. */
1169 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1174 thissize
= strtoul (ptr
, &ptr
, 10);
1176 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1179 as_bad (_("bad size %d in type specifier"), thissize
);
1187 type
->el
[type
->elems
].type
= thistype
;
1188 type
->el
[type
->elems
].size
= thissize
;
1193 /* Empty/missing type is not a successful parse. */
1194 if (type
->elems
== 0)
1202 /* Errors may be set multiple times during parsing or bit encoding
1203 (particularly in the Neon bits), but usually the earliest error which is set
1204 will be the most meaningful. Avoid overwriting it with later (cascading)
1205 errors by calling this function. */
1208 first_error (const char *err
)
1214 /* Parse a single type, e.g. ".s32", leading period included. */
1216 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1219 struct neon_type optype
;
1223 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1225 if (optype
.elems
== 1)
1226 *vectype
= optype
.el
[0];
1229 first_error (_("only one type should be specified for operand"));
1235 first_error (_("vector type expected"));
1247 /* Special meanings for indices (which have a range of 0-7), which will fit into
1250 #define NEON_ALL_LANES 15
1251 #define NEON_INTERLEAVE_LANES 14
1253 /* Parse either a register or a scalar, with an optional type. Return the
1254 register number, and optionally fill in the actual type of the register
1255 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1256 type/index information in *TYPEINFO. */
1259 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1260 enum arm_reg_type
*rtype
,
1261 struct neon_typed_alias
*typeinfo
)
1264 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1265 struct neon_typed_alias atype
;
1266 struct neon_type_el parsetype
;
1270 atype
.eltype
.type
= NT_invtype
;
1271 atype
.eltype
.size
= -1;
1273 /* Try alternate syntax for some types of register. Note these are mutually
1274 exclusive with the Neon syntax extensions. */
1277 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1285 /* Undo polymorphism when a set of register types may be accepted. */
1286 if ((type
== REG_TYPE_NDQ
1287 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1288 || (type
== REG_TYPE_VFSD
1289 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1290 || (type
== REG_TYPE_NSDQ
1291 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1292 || reg
->type
== REG_TYPE_NQ
))
1293 || (type
== REG_TYPE_MMXWC
1294 && (reg
->type
== REG_TYPE_MMXWCG
)))
1297 if (type
!= reg
->type
)
1303 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1305 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1307 first_error (_("can't redefine type for operand"));
1310 atype
.defined
|= NTA_HASTYPE
;
1311 atype
.eltype
= parsetype
;
1314 if (skip_past_char (&str
, '[') == SUCCESS
)
1316 if (type
!= REG_TYPE_VFD
)
1318 first_error (_("only D registers may be indexed"));
1322 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1324 first_error (_("can't change index for operand"));
1328 atype
.defined
|= NTA_HASINDEX
;
1330 if (skip_past_char (&str
, ']') == SUCCESS
)
1331 atype
.index
= NEON_ALL_LANES
;
1336 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1338 if (exp
.X_op
!= O_constant
)
1340 first_error (_("constant expression required"));
1344 if (skip_past_char (&str
, ']') == FAIL
)
1347 atype
.index
= exp
.X_add_number
;
1362 /* Like arm_reg_parse, but allow allow the following extra features:
1363 - If RTYPE is non-zero, return the (possibly restricted) type of the
1364 register (e.g. Neon double or quad reg when either has been requested).
1365 - If this is a Neon vector type with additional type information, fill
1366 in the struct pointed to by VECTYPE (if non-NULL).
1367 This function will fault on encountering a scalar. */
1370 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1371 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1373 struct neon_typed_alias atype
;
1375 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1380 /* Do not allow a scalar (reg+index) to parse as a register. */
1381 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1383 first_error (_("register operand expected, but got scalar"));
1388 *vectype
= atype
.eltype
;
1395 #define NEON_SCALAR_REG(X) ((X) >> 4)
1396 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1398 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1399 have enough information to be able to do a good job bounds-checking. So, we
1400 just do easy checks here, and do further checks later. */
1403 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1407 struct neon_typed_alias atype
;
1409 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1411 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1414 if (atype
.index
== NEON_ALL_LANES
)
1416 first_error (_("scalar must have an index"));
1419 else if (atype
.index
>= 64 / elsize
)
1421 first_error (_("scalar index out of range"));
1426 *type
= atype
.eltype
;
1430 return reg
* 16 + atype
.index
;
1433 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1435 parse_reg_list (char ** strp
)
1437 char * str
= * strp
;
1441 /* We come back here if we get ranges concatenated by '+' or '|'. */
1456 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1458 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1468 first_error (_("bad range in register list"));
1472 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1474 if (range
& (1 << i
))
1476 (_("Warning: duplicated register (r%d) in register list"),
1484 if (range
& (1 << reg
))
1485 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1487 else if (reg
<= cur_reg
)
1488 as_tsktsk (_("Warning: register range not in ascending order"));
1493 while (skip_past_comma (&str
) != FAIL
1494 || (in_range
= 1, *str
++ == '-'));
1499 first_error (_("missing `}'"));
1507 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1510 if (expr
.X_op
== O_constant
)
1512 if (expr
.X_add_number
1513 != (expr
.X_add_number
& 0x0000ffff))
1515 inst
.error
= _("invalid register mask");
1519 if ((range
& expr
.X_add_number
) != 0)
1521 int regno
= range
& expr
.X_add_number
;
1524 regno
= (1 << regno
) - 1;
1526 (_("Warning: duplicated register (r%d) in register list"),
1530 range
|= expr
.X_add_number
;
1534 if (inst
.reloc
.type
!= 0)
1536 inst
.error
= _("expression too complex");
1540 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1541 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1542 inst
.reloc
.pc_rel
= 0;
1546 if (*str
== '|' || *str
== '+')
1552 while (another_range
);
1558 /* Types of registers in a list. */
1567 /* Parse a VFP register list. If the string is invalid return FAIL.
1568 Otherwise return the number of registers, and set PBASE to the first
1569 register. Parses registers of type ETYPE.
1570 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1571 - Q registers can be used to specify pairs of D registers
1572 - { } can be omitted from around a singleton register list
1573 FIXME: This is not implemented, as it would require backtracking in
1576 This could be done (the meaning isn't really ambiguous), but doesn't
1577 fit in well with the current parsing framework.
1578 - 32 D registers may be used (also true for VFPv3).
1579 FIXME: Types are ignored in these register lists, which is probably a
1583 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1588 enum arm_reg_type regtype
= 0;
1592 unsigned long mask
= 0;
1597 inst
.error
= _("expecting {");
1606 regtype
= REG_TYPE_VFS
;
1611 regtype
= REG_TYPE_VFD
;
1614 case REGLIST_NEON_D
:
1615 regtype
= REG_TYPE_NDQ
;
1619 if (etype
!= REGLIST_VFP_S
)
1621 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1622 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1626 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1629 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1636 base_reg
= max_regs
;
1640 int setmask
= 1, addregs
= 1;
1642 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1644 if (new_base
== FAIL
)
1646 first_error (_(reg_expected_msgs
[regtype
]));
1650 if (new_base
>= max_regs
)
1652 first_error (_("register out of range in list"));
1656 /* Note: a value of 2 * n is returned for the register Q<n>. */
1657 if (regtype
== REG_TYPE_NQ
)
1663 if (new_base
< base_reg
)
1664 base_reg
= new_base
;
1666 if (mask
& (setmask
<< new_base
))
1668 first_error (_("invalid register list"));
1672 if ((mask
>> new_base
) != 0 && ! warned
)
1674 as_tsktsk (_("register list not in ascending order"));
1678 mask
|= setmask
<< new_base
;
1681 if (*str
== '-') /* We have the start of a range expression */
1687 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1690 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1694 if (high_range
>= max_regs
)
1696 first_error (_("register out of range in list"));
1700 if (regtype
== REG_TYPE_NQ
)
1701 high_range
= high_range
+ 1;
1703 if (high_range
<= new_base
)
1705 inst
.error
= _("register range not in ascending order");
1709 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1711 if (mask
& (setmask
<< new_base
))
1713 inst
.error
= _("invalid register list");
1717 mask
|= setmask
<< new_base
;
1722 while (skip_past_comma (&str
) != FAIL
);
1726 /* Sanity check -- should have raised a parse error above. */
1727 if (count
== 0 || count
> max_regs
)
1732 /* Final test -- the registers must be consecutive. */
1734 for (i
= 0; i
< count
; i
++)
1736 if ((mask
& (1u << i
)) == 0)
1738 inst
.error
= _("non-contiguous register range");
1748 /* True if two alias types are the same. */
1751 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1759 if (a
->defined
!= b
->defined
)
1762 if ((a
->defined
& NTA_HASTYPE
) != 0
1763 && (a
->eltype
.type
!= b
->eltype
.type
1764 || a
->eltype
.size
!= b
->eltype
.size
))
1767 if ((a
->defined
& NTA_HASINDEX
) != 0
1768 && (a
->index
!= b
->index
))
1774 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1775 The base register is put in *PBASE.
1776 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1778 The register stride (minus one) is put in bit 4 of the return value.
1779 Bits [6:5] encode the list length (minus one).
1780 The type of the list elements is put in *ELTYPE, if non-NULL. */
1782 #define NEON_LANE(X) ((X) & 0xf)
1783 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1784 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1787 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1788 struct neon_type_el
*eltype
)
1795 int leading_brace
= 0;
1796 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1798 const char *const incr_error
= "register stride must be 1 or 2";
1799 const char *const type_error
= "mismatched element/structure types in list";
1800 struct neon_typed_alias firsttype
;
1802 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1807 struct neon_typed_alias atype
;
1808 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1812 first_error (_(reg_expected_msgs
[rtype
]));
1819 if (rtype
== REG_TYPE_NQ
)
1826 else if (reg_incr
== -1)
1828 reg_incr
= getreg
- base_reg
;
1829 if (reg_incr
< 1 || reg_incr
> 2)
1831 first_error (_(incr_error
));
1835 else if (getreg
!= base_reg
+ reg_incr
* count
)
1837 first_error (_(incr_error
));
1841 if (!neon_alias_types_same (&atype
, &firsttype
))
1843 first_error (_(type_error
));
1847 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1851 struct neon_typed_alias htype
;
1852 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1854 lane
= NEON_INTERLEAVE_LANES
;
1855 else if (lane
!= NEON_INTERLEAVE_LANES
)
1857 first_error (_(type_error
));
1862 else if (reg_incr
!= 1)
1864 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1868 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1871 first_error (_(reg_expected_msgs
[rtype
]));
1874 if (!neon_alias_types_same (&htype
, &firsttype
))
1876 first_error (_(type_error
));
1879 count
+= hireg
+ dregs
- getreg
;
1883 /* If we're using Q registers, we can't use [] or [n] syntax. */
1884 if (rtype
== REG_TYPE_NQ
)
1890 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1894 else if (lane
!= atype
.index
)
1896 first_error (_(type_error
));
1900 else if (lane
== -1)
1901 lane
= NEON_INTERLEAVE_LANES
;
1902 else if (lane
!= NEON_INTERLEAVE_LANES
)
1904 first_error (_(type_error
));
1909 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1911 /* No lane set by [x]. We must be interleaving structures. */
1913 lane
= NEON_INTERLEAVE_LANES
;
1916 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1917 || (count
> 1 && reg_incr
== -1))
1919 first_error (_("error parsing element/structure list"));
1923 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1925 first_error (_("expected }"));
1933 *eltype
= firsttype
.eltype
;
1938 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1941 /* Parse an explicit relocation suffix on an expression. This is
1942 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1943 arm_reloc_hsh contains no entries, so this function can only
1944 succeed if there is no () after the word. Returns -1 on error,
1945 BFD_RELOC_UNUSED if there wasn't any suffix. */
1947 parse_reloc (char **str
)
1949 struct reloc_entry
*r
;
1953 return BFD_RELOC_UNUSED
;
1958 while (*q
&& *q
!= ')' && *q
!= ',')
1963 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1970 /* Directives: register aliases. */
1972 static struct reg_entry
*
1973 insert_reg_alias (char *str
, int number
, int type
)
1975 struct reg_entry
*new;
1978 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1981 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1983 /* Only warn about a redefinition if it's not defined as the
1985 else if (new->number
!= number
|| new->type
!= type
)
1986 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1991 name
= xstrdup (str
);
1992 new = xmalloc (sizeof (struct reg_entry
));
1995 new->number
= number
;
1997 new->builtin
= FALSE
;
2000 if (hash_insert (arm_reg_hsh
, name
, (void *) new))
2007 insert_neon_reg_alias (char *str
, int number
, int type
,
2008 struct neon_typed_alias
*atype
)
2010 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2014 first_error (_("attempt to redefine typed alias"));
2020 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2021 *reg
->neon
= *atype
;
2025 /* Look for the .req directive. This is of the form:
2027 new_register_name .req existing_register_name
2029 If we find one, or if it looks sufficiently like one that we want to
2030 handle any error here, return TRUE. Otherwise return FALSE. */
2033 create_register_alias (char * newname
, char *p
)
2035 struct reg_entry
*old
;
2036 char *oldname
, *nbuf
;
2039 /* The input scrubber ensures that whitespace after the mnemonic is
2040 collapsed to single spaces. */
2042 if (strncmp (oldname
, " .req ", 6) != 0)
2046 if (*oldname
== '\0')
2049 old
= hash_find (arm_reg_hsh
, oldname
);
2052 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2056 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2057 the desired alias name, and p points to its end. If not, then
2058 the desired alias name is in the global original_case_string. */
2059 #ifdef TC_CASE_SENSITIVE
2062 newname
= original_case_string
;
2063 nlen
= strlen (newname
);
2066 nbuf
= alloca (nlen
+ 1);
2067 memcpy (nbuf
, newname
, nlen
);
2070 /* Create aliases under the new name as stated; an all-lowercase
2071 version of the new name; and an all-uppercase version of the new
2073 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2075 for (p
= nbuf
; *p
; p
++)
2078 if (strncmp (nbuf
, newname
, nlen
))
2080 /* If this attempt to create an additional alias fails, do not bother
2081 trying to create the all-lower case alias. We will fail and issue
2082 a second, duplicate error message. This situation arises when the
2083 programmer does something like:
2086 The second .req creates the "Foo" alias but then fails to create
2087 the artificial FOO alias because it has already been created by the
2089 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2093 for (p
= nbuf
; *p
; p
++)
2096 if (strncmp (nbuf
, newname
, nlen
))
2097 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2103 /* Create a Neon typed/indexed register alias using directives, e.g.:
2108 These typed registers can be used instead of the types specified after the
2109 Neon mnemonic, so long as all operands given have types. Types can also be
2110 specified directly, e.g.:
2111 vadd d0.s32, d1.s32, d2.s32 */
2114 create_neon_reg_alias (char *newname
, char *p
)
2116 enum arm_reg_type basetype
;
2117 struct reg_entry
*basereg
;
2118 struct reg_entry mybasereg
;
2119 struct neon_type ntype
;
2120 struct neon_typed_alias typeinfo
;
2121 char *namebuf
, *nameend
;
2124 typeinfo
.defined
= 0;
2125 typeinfo
.eltype
.type
= NT_invtype
;
2126 typeinfo
.eltype
.size
= -1;
2127 typeinfo
.index
= -1;
2131 if (strncmp (p
, " .dn ", 5) == 0)
2132 basetype
= REG_TYPE_VFD
;
2133 else if (strncmp (p
, " .qn ", 5) == 0)
2134 basetype
= REG_TYPE_NQ
;
2143 basereg
= arm_reg_parse_multi (&p
);
2145 if (basereg
&& basereg
->type
!= basetype
)
2147 as_bad (_("bad type for register"));
2151 if (basereg
== NULL
)
2154 /* Try parsing as an integer. */
2155 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2156 if (exp
.X_op
!= O_constant
)
2158 as_bad (_("expression must be constant"));
2161 basereg
= &mybasereg
;
2162 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2168 typeinfo
= *basereg
->neon
;
2170 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2172 /* We got a type. */
2173 if (typeinfo
.defined
& NTA_HASTYPE
)
2175 as_bad (_("can't redefine the type of a register alias"));
2179 typeinfo
.defined
|= NTA_HASTYPE
;
2180 if (ntype
.elems
!= 1)
2182 as_bad (_("you must specify a single type only"));
2185 typeinfo
.eltype
= ntype
.el
[0];
2188 if (skip_past_char (&p
, '[') == SUCCESS
)
2191 /* We got a scalar index. */
2193 if (typeinfo
.defined
& NTA_HASINDEX
)
2195 as_bad (_("can't redefine the index of a scalar alias"));
2199 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2201 if (exp
.X_op
!= O_constant
)
2203 as_bad (_("scalar index must be constant"));
2207 typeinfo
.defined
|= NTA_HASINDEX
;
2208 typeinfo
.index
= exp
.X_add_number
;
2210 if (skip_past_char (&p
, ']') == FAIL
)
2212 as_bad (_("expecting ]"));
2217 namelen
= nameend
- newname
;
2218 namebuf
= alloca (namelen
+ 1);
2219 strncpy (namebuf
, newname
, namelen
);
2220 namebuf
[namelen
] = '\0';
2222 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2223 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2225 /* Insert name in all uppercase. */
2226 for (p
= namebuf
; *p
; p
++)
2229 if (strncmp (namebuf
, newname
, namelen
))
2230 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2231 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2233 /* Insert name in all lowercase. */
2234 for (p
= namebuf
; *p
; p
++)
2237 if (strncmp (namebuf
, newname
, namelen
))
2238 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2239 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2244 /* Should never be called, as .req goes between the alias and the
2245 register name, not at the beginning of the line. */
2247 s_req (int a ATTRIBUTE_UNUSED
)
2249 as_bad (_("invalid syntax for .req directive"));
2253 s_dn (int a ATTRIBUTE_UNUSED
)
2255 as_bad (_("invalid syntax for .dn directive"));
2259 s_qn (int a ATTRIBUTE_UNUSED
)
2261 as_bad (_("invalid syntax for .qn directive"));
2264 /* The .unreq directive deletes an alias which was previously defined
2265 by .req. For example:
2271 s_unreq (int a ATTRIBUTE_UNUSED
)
2276 name
= input_line_pointer
;
2278 while (*input_line_pointer
!= 0
2279 && *input_line_pointer
!= ' '
2280 && *input_line_pointer
!= '\n')
2281 ++input_line_pointer
;
2283 saved_char
= *input_line_pointer
;
2284 *input_line_pointer
= 0;
2287 as_bad (_("invalid syntax for .unreq directive"));
2290 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2293 as_bad (_("unknown register alias '%s'"), name
);
2294 else if (reg
->builtin
)
2295 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2302 hash_delete (arm_reg_hsh
, name
, FALSE
);
2303 free ((char *) reg
->name
);
2308 /* Also locate the all upper case and all lower case versions.
2309 Do not complain if we cannot find one or the other as it
2310 was probably deleted above. */
2312 nbuf
= strdup (name
);
2313 for (p
= nbuf
; *p
; p
++)
2315 reg
= hash_find (arm_reg_hsh
, nbuf
);
2318 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2319 free ((char *) reg
->name
);
2325 for (p
= nbuf
; *p
; p
++)
2327 reg
= hash_find (arm_reg_hsh
, nbuf
);
2330 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2331 free ((char *) reg
->name
);
2341 *input_line_pointer
= saved_char
;
2342 demand_empty_rest_of_line ();
2345 /* Directives: Instruction set selection. */
2348 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2349 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2350 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2351 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2353 static enum mstate mapstate
= MAP_UNDEFINED
;
2356 mapping_state (enum mstate state
)
2359 const char * symname
;
2362 if (mapstate
== state
)
2363 /* The mapping symbol has already been emitted.
2364 There is nothing else to do. */
2373 type
= BSF_NO_FLAGS
;
2377 type
= BSF_NO_FLAGS
;
2381 type
= BSF_NO_FLAGS
;
2389 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2391 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2392 symbol_table_insert (symbolP
);
2393 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2398 THUMB_SET_FUNC (symbolP
, 0);
2399 ARM_SET_THUMB (symbolP
, 0);
2400 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2404 THUMB_SET_FUNC (symbolP
, 1);
2405 ARM_SET_THUMB (symbolP
, 1);
2406 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2415 #define mapping_state(x) /* nothing */
2418 /* Find the real, Thumb encoded start of a Thumb function. */
2422 find_real_start (symbolS
* symbolP
)
2425 const char * name
= S_GET_NAME (symbolP
);
2426 symbolS
* new_target
;
2428 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2429 #define STUB_NAME ".real_start_of"
2434 /* The compiler may generate BL instructions to local labels because
2435 it needs to perform a branch to a far away location. These labels
2436 do not have a corresponding ".real_start_of" label. We check
2437 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2438 the ".real_start_of" convention for nonlocal branches. */
2439 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2442 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2443 new_target
= symbol_find (real_start
);
2445 if (new_target
== NULL
)
2447 as_warn (_("Failed to find real start of function: %s\n"), name
);
2448 new_target
= symbolP
;
2456 opcode_select (int width
)
2463 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2464 as_bad (_("selected processor does not support THUMB opcodes"));
2467 /* No need to force the alignment, since we will have been
2468 coming from ARM mode, which is word-aligned. */
2469 record_alignment (now_seg
, 1);
2471 mapping_state (MAP_THUMB
);
2477 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2478 as_bad (_("selected processor does not support ARM opcodes"));
2483 frag_align (2, 0, 0);
2485 record_alignment (now_seg
, 1);
2487 mapping_state (MAP_ARM
);
2491 as_bad (_("invalid instruction size selected (%d)"), width
);
2496 s_arm (int ignore ATTRIBUTE_UNUSED
)
2499 demand_empty_rest_of_line ();
2503 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2506 demand_empty_rest_of_line ();
2510 s_code (int unused ATTRIBUTE_UNUSED
)
2514 temp
= get_absolute_expression ();
2519 opcode_select (temp
);
2523 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2528 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2530 /* If we are not already in thumb mode go into it, EVEN if
2531 the target processor does not support thumb instructions.
2532 This is used by gcc/config/arm/lib1funcs.asm for example
2533 to compile interworking support functions even if the
2534 target processor should not support interworking. */
2538 record_alignment (now_seg
, 1);
2541 demand_empty_rest_of_line ();
2545 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2549 /* The following label is the name/address of the start of a Thumb function.
2550 We need to know this for the interworking support. */
2551 label_is_thumb_function_name
= TRUE
;
2554 /* Perform a .set directive, but also mark the alias as
2555 being a thumb function. */
2558 s_thumb_set (int equiv
)
2560 /* XXX the following is a duplicate of the code for s_set() in read.c
2561 We cannot just call that code as we need to get at the symbol that
2568 /* Especial apologies for the random logic:
2569 This just grew, and could be parsed much more simply!
2571 name
= input_line_pointer
;
2572 delim
= get_symbol_end ();
2573 end_name
= input_line_pointer
;
2576 if (*input_line_pointer
!= ',')
2579 as_bad (_("expected comma after name \"%s\""), name
);
2581 ignore_rest_of_line ();
2585 input_line_pointer
++;
2588 if (name
[0] == '.' && name
[1] == '\0')
2590 /* XXX - this should not happen to .thumb_set. */
2594 if ((symbolP
= symbol_find (name
)) == NULL
2595 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2598 /* When doing symbol listings, play games with dummy fragments living
2599 outside the normal fragment chain to record the file and line info
2601 if (listing
& LISTING_SYMBOLS
)
2603 extern struct list_info_struct
* listing_tail
;
2604 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2606 memset (dummy_frag
, 0, sizeof (fragS
));
2607 dummy_frag
->fr_type
= rs_fill
;
2608 dummy_frag
->line
= listing_tail
;
2609 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2610 dummy_frag
->fr_symbol
= symbolP
;
2614 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2617 /* "set" symbols are local unless otherwise specified. */
2618 SF_SET_LOCAL (symbolP
);
2619 #endif /* OBJ_COFF */
2620 } /* Make a new symbol. */
2622 symbol_table_insert (symbolP
);
2627 && S_IS_DEFINED (symbolP
)
2628 && S_GET_SEGMENT (symbolP
) != reg_section
)
2629 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2631 pseudo_set (symbolP
);
2633 demand_empty_rest_of_line ();
2635 /* XXX Now we come to the Thumb specific bit of code. */
2637 THUMB_SET_FUNC (symbolP
, 1);
2638 ARM_SET_THUMB (symbolP
, 1);
2639 #if defined OBJ_ELF || defined OBJ_COFF
2640 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2644 /* Directives: Mode selection. */
2646 /* .syntax [unified|divided] - choose the new unified syntax
2647 (same for Arm and Thumb encoding, modulo slight differences in what
2648 can be represented) or the old divergent syntax for each mode. */
2650 s_syntax (int unused ATTRIBUTE_UNUSED
)
2654 name
= input_line_pointer
;
2655 delim
= get_symbol_end ();
2657 if (!strcasecmp (name
, "unified"))
2658 unified_syntax
= TRUE
;
2659 else if (!strcasecmp (name
, "divided"))
2660 unified_syntax
= FALSE
;
2663 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2666 *input_line_pointer
= delim
;
2667 demand_empty_rest_of_line ();
2670 /* Directives: sectioning and alignment. */
2672 /* Same as s_align_ptwo but align 0 => align 2. */
2675 s_align (int unused ATTRIBUTE_UNUSED
)
2680 long max_alignment
= 15;
2682 temp
= get_absolute_expression ();
2683 if (temp
> max_alignment
)
2684 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2687 as_bad (_("alignment negative. 0 assumed."));
2691 if (*input_line_pointer
== ',')
2693 input_line_pointer
++;
2694 temp_fill
= get_absolute_expression ();
2706 /* Only make a frag if we HAVE to. */
2707 if (temp
&& !need_pass_2
)
2709 if (!fill_p
&& subseg_text_p (now_seg
))
2710 frag_align_code (temp
, 0);
2712 frag_align (temp
, (int) temp_fill
, 0);
2714 demand_empty_rest_of_line ();
2716 record_alignment (now_seg
, temp
);
2720 s_bss (int ignore ATTRIBUTE_UNUSED
)
2722 /* We don't support putting frags in the BSS segment, we fake it by
2723 marking in_bss, then looking at s_skip for clues. */
2724 subseg_set (bss_section
, 0);
2725 demand_empty_rest_of_line ();
2726 mapping_state (MAP_DATA
);
2730 s_even (int ignore ATTRIBUTE_UNUSED
)
2732 /* Never make frag if expect extra pass. */
2734 frag_align (1, 0, 0);
2736 record_alignment (now_seg
, 1);
2738 demand_empty_rest_of_line ();
2741 /* Directives: Literal pools. */
2743 static literal_pool
*
2744 find_literal_pool (void)
2746 literal_pool
* pool
;
2748 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2750 if (pool
->section
== now_seg
2751 && pool
->sub_section
== now_subseg
)
2758 static literal_pool
*
2759 find_or_make_literal_pool (void)
2761 /* Next literal pool ID number. */
2762 static unsigned int latest_pool_num
= 1;
2763 literal_pool
* pool
;
2765 pool
= find_literal_pool ();
2769 /* Create a new pool. */
2770 pool
= xmalloc (sizeof (* pool
));
2774 pool
->next_free_entry
= 0;
2775 pool
->section
= now_seg
;
2776 pool
->sub_section
= now_subseg
;
2777 pool
->next
= list_of_pools
;
2778 pool
->symbol
= NULL
;
2780 /* Add it to the list. */
2781 list_of_pools
= pool
;
2784 /* New pools, and emptied pools, will have a NULL symbol. */
2785 if (pool
->symbol
== NULL
)
2787 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2788 (valueT
) 0, &zero_address_frag
);
2789 pool
->id
= latest_pool_num
++;
2796 /* Add the literal in the global 'inst'
2797 structure to the relevant literal pool. */
2800 add_to_lit_pool (void)
2802 literal_pool
* pool
;
2805 pool
= find_or_make_literal_pool ();
2807 /* Check if this literal value is already in the pool. */
2808 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2810 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2811 && (inst
.reloc
.exp
.X_op
== O_constant
)
2812 && (pool
->literals
[entry
].X_add_number
2813 == inst
.reloc
.exp
.X_add_number
)
2814 && (pool
->literals
[entry
].X_unsigned
2815 == inst
.reloc
.exp
.X_unsigned
))
2818 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2819 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2820 && (pool
->literals
[entry
].X_add_number
2821 == inst
.reloc
.exp
.X_add_number
)
2822 && (pool
->literals
[entry
].X_add_symbol
2823 == inst
.reloc
.exp
.X_add_symbol
)
2824 && (pool
->literals
[entry
].X_op_symbol
2825 == inst
.reloc
.exp
.X_op_symbol
))
2829 /* Do we need to create a new entry? */
2830 if (entry
== pool
->next_free_entry
)
2832 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2834 inst
.error
= _("literal pool overflow");
2838 pool
->literals
[entry
] = inst
.reloc
.exp
;
2839 pool
->next_free_entry
+= 1;
2842 inst
.reloc
.exp
.X_op
= O_symbol
;
2843 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2844 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2849 /* Can't use symbol_new here, so have to create a symbol and then at
2850 a later date assign it a value. Thats what these functions do. */
2853 symbol_locate (symbolS
* symbolP
,
2854 const char * name
, /* It is copied, the caller can modify. */
2855 segT segment
, /* Segment identifier (SEG_<something>). */
2856 valueT valu
, /* Symbol value. */
2857 fragS
* frag
) /* Associated fragment. */
2859 unsigned int name_length
;
2860 char * preserved_copy_of_name
;
2862 name_length
= strlen (name
) + 1; /* +1 for \0. */
2863 obstack_grow (¬es
, name
, name_length
);
2864 preserved_copy_of_name
= obstack_finish (¬es
);
2866 #ifdef tc_canonicalize_symbol_name
2867 preserved_copy_of_name
=
2868 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2871 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2873 S_SET_SEGMENT (symbolP
, segment
);
2874 S_SET_VALUE (symbolP
, valu
);
2875 symbol_clear_list_pointers (symbolP
);
2877 symbol_set_frag (symbolP
, frag
);
2879 /* Link to end of symbol chain. */
2881 extern int symbol_table_frozen
;
2883 if (symbol_table_frozen
)
2887 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2889 obj_symbol_new_hook (symbolP
);
2891 #ifdef tc_symbol_new_hook
2892 tc_symbol_new_hook (symbolP
);
2896 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2897 #endif /* DEBUG_SYMS */
2902 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2905 literal_pool
* pool
;
2908 pool
= find_literal_pool ();
2910 || pool
->symbol
== NULL
2911 || pool
->next_free_entry
== 0)
2914 mapping_state (MAP_DATA
);
2916 /* Align pool as you have word accesses.
2917 Only make a frag if we have to. */
2919 frag_align (2, 0, 0);
2921 record_alignment (now_seg
, 2);
2923 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2925 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2926 (valueT
) frag_now_fix (), frag_now
);
2927 symbol_table_insert (pool
->symbol
);
2929 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2931 #if defined OBJ_COFF || defined OBJ_ELF
2932 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2935 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2936 /* First output the expression in the instruction to the pool. */
2937 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2939 /* Mark the pool as empty. */
2940 pool
->next_free_entry
= 0;
2941 pool
->symbol
= NULL
;
2945 /* Forward declarations for functions below, in the MD interface
2947 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2948 static valueT
create_unwind_entry (int);
2949 static void start_unwind_section (const segT
, int);
2950 static void add_unwind_opcode (valueT
, int);
2951 static void flush_pending_unwind (void);
2953 /* Directives: Data. */
2956 s_arm_elf_cons (int nbytes
)
2960 #ifdef md_flush_pending_output
2961 md_flush_pending_output ();
2964 if (is_it_end_of_statement ())
2966 demand_empty_rest_of_line ();
2970 #ifdef md_cons_align
2971 md_cons_align (nbytes
);
2974 mapping_state (MAP_DATA
);
2978 char *base
= input_line_pointer
;
2982 if (exp
.X_op
!= O_symbol
)
2983 emit_expr (&exp
, (unsigned int) nbytes
);
2986 char *before_reloc
= input_line_pointer
;
2987 reloc
= parse_reloc (&input_line_pointer
);
2990 as_bad (_("unrecognized relocation suffix"));
2991 ignore_rest_of_line ();
2994 else if (reloc
== BFD_RELOC_UNUSED
)
2995 emit_expr (&exp
, (unsigned int) nbytes
);
2998 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2999 int size
= bfd_get_reloc_size (howto
);
3001 if (reloc
== BFD_RELOC_ARM_PLT32
)
3003 as_bad (_("(plt) is only valid on branch targets"));
3004 reloc
= BFD_RELOC_UNUSED
;
3009 as_bad (_("%s relocations do not fit in %d bytes"),
3010 howto
->name
, nbytes
);
3013 /* We've parsed an expression stopping at O_symbol.
3014 But there may be more expression left now that we
3015 have parsed the relocation marker. Parse it again.
3016 XXX Surely there is a cleaner way to do this. */
3017 char *p
= input_line_pointer
;
3019 char *save_buf
= alloca (input_line_pointer
- base
);
3020 memcpy (save_buf
, base
, input_line_pointer
- base
);
3021 memmove (base
+ (input_line_pointer
- before_reloc
),
3022 base
, before_reloc
- base
);
3024 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3026 memcpy (base
, save_buf
, p
- base
);
3028 offset
= nbytes
- size
;
3029 p
= frag_more ((int) nbytes
);
3030 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3031 size
, &exp
, 0, reloc
);
3036 while (*input_line_pointer
++ == ',');
3038 /* Put terminator back into stream. */
3039 input_line_pointer
--;
3040 demand_empty_rest_of_line ();
3044 /* Parse a .rel31 directive. */
3047 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3054 if (*input_line_pointer
== '1')
3055 highbit
= 0x80000000;
3056 else if (*input_line_pointer
!= '0')
3057 as_bad (_("expected 0 or 1"));
3059 input_line_pointer
++;
3060 if (*input_line_pointer
!= ',')
3061 as_bad (_("missing comma"));
3062 input_line_pointer
++;
3064 #ifdef md_flush_pending_output
3065 md_flush_pending_output ();
3068 #ifdef md_cons_align
3072 mapping_state (MAP_DATA
);
3077 md_number_to_chars (p
, highbit
, 4);
3078 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3079 BFD_RELOC_ARM_PREL31
);
3081 demand_empty_rest_of_line ();
3084 /* Directives: AEABI stack-unwind tables. */
3086 /* Parse an unwind_fnstart directive. Simply records the current location. */
3089 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3091 demand_empty_rest_of_line ();
3092 /* Mark the start of the function. */
3093 unwind
.proc_start
= expr_build_dot ();
3095 /* Reset the rest of the unwind info. */
3096 unwind
.opcode_count
= 0;
3097 unwind
.table_entry
= NULL
;
3098 unwind
.personality_routine
= NULL
;
3099 unwind
.personality_index
= -1;
3100 unwind
.frame_size
= 0;
3101 unwind
.fp_offset
= 0;
3102 unwind
.fp_reg
= REG_SP
;
3104 unwind
.sp_restored
= 0;
3108 /* Parse a handlerdata directive. Creates the exception handling table entry
3109 for the function. */
3112 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3114 demand_empty_rest_of_line ();
3115 if (unwind
.table_entry
)
3116 as_bad (_("duplicate .handlerdata directive"));
3118 create_unwind_entry (1);
3121 /* Parse an unwind_fnend directive. Generates the index table entry. */
3124 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3130 demand_empty_rest_of_line ();
3132 /* Add eh table entry. */
3133 if (unwind
.table_entry
== NULL
)
3134 val
= create_unwind_entry (0);
3138 /* Add index table entry. This is two words. */
3139 start_unwind_section (unwind
.saved_seg
, 1);
3140 frag_align (2, 0, 0);
3141 record_alignment (now_seg
, 2);
3143 ptr
= frag_more (8);
3144 where
= frag_now_fix () - 8;
3146 /* Self relative offset of the function start. */
3147 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3148 BFD_RELOC_ARM_PREL31
);
3150 /* Indicate dependency on EHABI-defined personality routines to the
3151 linker, if it hasn't been done already. */
3152 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3153 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3155 static const char *const name
[] =
3157 "__aeabi_unwind_cpp_pr0",
3158 "__aeabi_unwind_cpp_pr1",
3159 "__aeabi_unwind_cpp_pr2"
3161 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3162 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3163 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3164 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3165 = marked_pr_dependency
;
3169 /* Inline exception table entry. */
3170 md_number_to_chars (ptr
+ 4, val
, 4);
3172 /* Self relative offset of the table entry. */
3173 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3174 BFD_RELOC_ARM_PREL31
);
3176 /* Restore the original section. */
3177 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3181 /* Parse an unwind_cantunwind directive. */
3184 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3186 demand_empty_rest_of_line ();
3187 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3188 as_bad (_("personality routine specified for cantunwind frame"));
3190 unwind
.personality_index
= -2;
3194 /* Parse a personalityindex directive. */
3197 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3201 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3202 as_bad (_("duplicate .personalityindex directive"));
3206 if (exp
.X_op
!= O_constant
3207 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3209 as_bad (_("bad personality routine number"));
3210 ignore_rest_of_line ();
3214 unwind
.personality_index
= exp
.X_add_number
;
3216 demand_empty_rest_of_line ();
3220 /* Parse a personality directive. */
3223 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3227 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3228 as_bad (_("duplicate .personality directive"));
3230 name
= input_line_pointer
;
3231 c
= get_symbol_end ();
3232 p
= input_line_pointer
;
3233 unwind
.personality_routine
= symbol_find_or_make (name
);
3235 demand_empty_rest_of_line ();
3239 /* Parse a directive saving core registers. */
3242 s_arm_unwind_save_core (void)
3248 range
= parse_reg_list (&input_line_pointer
);
3251 as_bad (_("expected register list"));
3252 ignore_rest_of_line ();
3256 demand_empty_rest_of_line ();
3258 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3259 into .unwind_save {..., sp...}. We aren't bothered about the value of
3260 ip because it is clobbered by calls. */
3261 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3262 && (range
& 0x3000) == 0x1000)
3264 unwind
.opcode_count
--;
3265 unwind
.sp_restored
= 0;
3266 range
= (range
| 0x2000) & ~0x1000;
3267 unwind
.pending_offset
= 0;
3273 /* See if we can use the short opcodes. These pop a block of up to 8
3274 registers starting with r4, plus maybe r14. */
3275 for (n
= 0; n
< 8; n
++)
3277 /* Break at the first non-saved register. */
3278 if ((range
& (1 << (n
+ 4))) == 0)
3281 /* See if there are any other bits set. */
3282 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3284 /* Use the long form. */
3285 op
= 0x8000 | ((range
>> 4) & 0xfff);
3286 add_unwind_opcode (op
, 2);
3290 /* Use the short form. */
3292 op
= 0xa8; /* Pop r14. */
3294 op
= 0xa0; /* Do not pop r14. */
3296 add_unwind_opcode (op
, 1);
3303 op
= 0xb100 | (range
& 0xf);
3304 add_unwind_opcode (op
, 2);
3307 /* Record the number of bytes pushed. */
3308 for (n
= 0; n
< 16; n
++)
3310 if (range
& (1 << n
))
3311 unwind
.frame_size
+= 4;
3316 /* Parse a directive saving FPA registers. */
3319 s_arm_unwind_save_fpa (int reg
)
3325 /* Get Number of registers to transfer. */
3326 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3329 exp
.X_op
= O_illegal
;
3331 if (exp
.X_op
!= O_constant
)
3333 as_bad (_("expected , <constant>"));
3334 ignore_rest_of_line ();
3338 num_regs
= exp
.X_add_number
;
3340 if (num_regs
< 1 || num_regs
> 4)
3342 as_bad (_("number of registers must be in the range [1:4]"));
3343 ignore_rest_of_line ();
3347 demand_empty_rest_of_line ();
3352 op
= 0xb4 | (num_regs
- 1);
3353 add_unwind_opcode (op
, 1);
3358 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3359 add_unwind_opcode (op
, 2);
3361 unwind
.frame_size
+= num_regs
* 12;
3365 /* Parse a directive saving VFP registers for ARMv6 and above. */
3368 s_arm_unwind_save_vfp_armv6 (void)
3373 int num_vfpv3_regs
= 0;
3374 int num_regs_below_16
;
3376 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3379 as_bad (_("expected register list"));
3380 ignore_rest_of_line ();
3384 demand_empty_rest_of_line ();
3386 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3387 than FSTMX/FLDMX-style ones). */
3389 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3391 num_vfpv3_regs
= count
;
3392 else if (start
+ count
> 16)
3393 num_vfpv3_regs
= start
+ count
- 16;
3395 if (num_vfpv3_regs
> 0)
3397 int start_offset
= start
> 16 ? start
- 16 : 0;
3398 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3399 add_unwind_opcode (op
, 2);
3402 /* Generate opcode for registers numbered in the range 0 .. 15. */
3403 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3404 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3405 if (num_regs_below_16
> 0)
3407 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3408 add_unwind_opcode (op
, 2);
3411 unwind
.frame_size
+= count
* 8;
3415 /* Parse a directive saving VFP registers for pre-ARMv6. */
3418 s_arm_unwind_save_vfp (void)
3424 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3427 as_bad (_("expected register list"));
3428 ignore_rest_of_line ();
3432 demand_empty_rest_of_line ();
3437 op
= 0xb8 | (count
- 1);
3438 add_unwind_opcode (op
, 1);
3443 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3444 add_unwind_opcode (op
, 2);
3446 unwind
.frame_size
+= count
* 8 + 4;
3450 /* Parse a directive saving iWMMXt data registers. */
3453 s_arm_unwind_save_mmxwr (void)
3461 if (*input_line_pointer
== '{')
3462 input_line_pointer
++;
3466 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3470 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3475 as_tsktsk (_("register list not in ascending order"));
3478 if (*input_line_pointer
== '-')
3480 input_line_pointer
++;
3481 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3484 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3487 else if (reg
>= hi_reg
)
3489 as_bad (_("bad register range"));
3492 for (; reg
< hi_reg
; reg
++)
3496 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3498 if (*input_line_pointer
== '}')
3499 input_line_pointer
++;
3501 demand_empty_rest_of_line ();
3503 /* Generate any deferred opcodes because we're going to be looking at
3505 flush_pending_unwind ();
3507 for (i
= 0; i
< 16; i
++)
3509 if (mask
& (1 << i
))
3510 unwind
.frame_size
+= 8;
3513 /* Attempt to combine with a previous opcode. We do this because gcc
3514 likes to output separate unwind directives for a single block of
3516 if (unwind
.opcode_count
> 0)
3518 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3519 if ((i
& 0xf8) == 0xc0)
3522 /* Only merge if the blocks are contiguous. */
3525 if ((mask
& 0xfe00) == (1 << 9))
3527 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3528 unwind
.opcode_count
--;
3531 else if (i
== 6 && unwind
.opcode_count
>= 2)
3533 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3537 op
= 0xffff << (reg
- 1);
3539 && ((mask
& op
) == (1u << (reg
- 1))))
3541 op
= (1 << (reg
+ i
+ 1)) - 1;
3542 op
&= ~((1 << reg
) - 1);
3544 unwind
.opcode_count
-= 2;
3551 /* We want to generate opcodes in the order the registers have been
3552 saved, ie. descending order. */
3553 for (reg
= 15; reg
>= -1; reg
--)
3555 /* Save registers in blocks. */
3557 || !(mask
& (1 << reg
)))
3559 /* We found an unsaved reg. Generate opcodes to save the
3566 op
= 0xc0 | (hi_reg
- 10);
3567 add_unwind_opcode (op
, 1);
3572 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3573 add_unwind_opcode (op
, 2);
3582 ignore_rest_of_line ();
3586 s_arm_unwind_save_mmxwcg (void)
3593 if (*input_line_pointer
== '{')
3594 input_line_pointer
++;
3598 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3602 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3608 as_tsktsk (_("register list not in ascending order"));
3611 if (*input_line_pointer
== '-')
3613 input_line_pointer
++;
3614 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3617 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3620 else if (reg
>= hi_reg
)
3622 as_bad (_("bad register range"));
3625 for (; reg
< hi_reg
; reg
++)
3629 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3631 if (*input_line_pointer
== '}')
3632 input_line_pointer
++;
3634 demand_empty_rest_of_line ();
3636 /* Generate any deferred opcodes because we're going to be looking at
3638 flush_pending_unwind ();
3640 for (reg
= 0; reg
< 16; reg
++)
3642 if (mask
& (1 << reg
))
3643 unwind
.frame_size
+= 4;
3646 add_unwind_opcode (op
, 2);
3649 ignore_rest_of_line ();
3653 /* Parse an unwind_save directive.
3654 If the argument is non-zero, this is a .vsave directive. */
3657 s_arm_unwind_save (int arch_v6
)
3660 struct reg_entry
*reg
;
3661 bfd_boolean had_brace
= FALSE
;
3663 /* Figure out what sort of save we have. */
3664 peek
= input_line_pointer
;
3672 reg
= arm_reg_parse_multi (&peek
);
3676 as_bad (_("register expected"));
3677 ignore_rest_of_line ();
3686 as_bad (_("FPA .unwind_save does not take a register list"));
3687 ignore_rest_of_line ();
3690 input_line_pointer
= peek
;
3691 s_arm_unwind_save_fpa (reg
->number
);
3694 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3697 s_arm_unwind_save_vfp_armv6 ();
3699 s_arm_unwind_save_vfp ();
3701 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3702 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3705 as_bad (_(".unwind_save does not support this kind of register"));
3706 ignore_rest_of_line ();
3711 /* Parse an unwind_movsp directive. */
3714 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3720 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3723 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
3724 ignore_rest_of_line ();
3728 /* Optional constant. */
3729 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3731 if (immediate_for_directive (&offset
) == FAIL
)
3737 demand_empty_rest_of_line ();
3739 if (reg
== REG_SP
|| reg
== REG_PC
)
3741 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3745 if (unwind
.fp_reg
!= REG_SP
)
3746 as_bad (_("unexpected .unwind_movsp directive"));
3748 /* Generate opcode to restore the value. */
3750 add_unwind_opcode (op
, 1);
3752 /* Record the information for later. */
3753 unwind
.fp_reg
= reg
;
3754 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3755 unwind
.sp_restored
= 1;
3758 /* Parse an unwind_pad directive. */
3761 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3765 if (immediate_for_directive (&offset
) == FAIL
)
3770 as_bad (_("stack increment must be multiple of 4"));
3771 ignore_rest_of_line ();
3775 /* Don't generate any opcodes, just record the details for later. */
3776 unwind
.frame_size
+= offset
;
3777 unwind
.pending_offset
+= offset
;
3779 demand_empty_rest_of_line ();
3782 /* Parse an unwind_setfp directive. */
3785 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3791 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3792 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3795 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3797 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3799 as_bad (_("expected <reg>, <reg>"));
3800 ignore_rest_of_line ();
3804 /* Optional constant. */
3805 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3807 if (immediate_for_directive (&offset
) == FAIL
)
3813 demand_empty_rest_of_line ();
3815 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
3817 as_bad (_("register must be either sp or set by a previous"
3818 "unwind_movsp directive"));
3822 /* Don't generate any opcodes, just record the information for later. */
3823 unwind
.fp_reg
= fp_reg
;
3825 if (sp_reg
== REG_SP
)
3826 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3828 unwind
.fp_offset
-= offset
;
3831 /* Parse an unwind_raw directive. */
3834 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3837 /* This is an arbitrary limit. */
3838 unsigned char op
[16];
3842 if (exp
.X_op
== O_constant
3843 && skip_past_comma (&input_line_pointer
) != FAIL
)
3845 unwind
.frame_size
+= exp
.X_add_number
;
3849 exp
.X_op
= O_illegal
;
3851 if (exp
.X_op
!= O_constant
)
3853 as_bad (_("expected <offset>, <opcode>"));
3854 ignore_rest_of_line ();
3860 /* Parse the opcode. */
3865 as_bad (_("unwind opcode too long"));
3866 ignore_rest_of_line ();
3868 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3870 as_bad (_("invalid unwind opcode"));
3871 ignore_rest_of_line ();
3874 op
[count
++] = exp
.X_add_number
;
3876 /* Parse the next byte. */
3877 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3883 /* Add the opcode bytes in reverse order. */
3885 add_unwind_opcode (op
[count
], 1);
3887 demand_empty_rest_of_line ();
3891 /* Parse a .eabi_attribute directive. */
3894 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3896 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
3898 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
3899 attributes_set_explicitly
[tag
] = 1;
3901 #endif /* OBJ_ELF */
3903 static void s_arm_arch (int);
3904 static void s_arm_object_arch (int);
3905 static void s_arm_cpu (int);
3906 static void s_arm_fpu (int);
3911 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3918 if (exp
.X_op
== O_symbol
)
3919 exp
.X_op
= O_secrel
;
3921 emit_expr (&exp
, 4);
3923 while (*input_line_pointer
++ == ',');
3925 input_line_pointer
--;
3926 demand_empty_rest_of_line ();
3930 /* This table describes all the machine specific pseudo-ops the assembler
3931 has to support. The fields are:
3932 pseudo-op name without dot
3933 function to call to execute this pseudo-op
3934 Integer arg to pass to the function. */
3936 const pseudo_typeS md_pseudo_table
[] =
3938 /* Never called because '.req' does not start a line. */
3939 { "req", s_req
, 0 },
3940 /* Following two are likewise never called. */
3943 { "unreq", s_unreq
, 0 },
3944 { "bss", s_bss
, 0 },
3945 { "align", s_align
, 0 },
3946 { "arm", s_arm
, 0 },
3947 { "thumb", s_thumb
, 0 },
3948 { "code", s_code
, 0 },
3949 { "force_thumb", s_force_thumb
, 0 },
3950 { "thumb_func", s_thumb_func
, 0 },
3951 { "thumb_set", s_thumb_set
, 0 },
3952 { "even", s_even
, 0 },
3953 { "ltorg", s_ltorg
, 0 },
3954 { "pool", s_ltorg
, 0 },
3955 { "syntax", s_syntax
, 0 },
3956 { "cpu", s_arm_cpu
, 0 },
3957 { "arch", s_arm_arch
, 0 },
3958 { "object_arch", s_arm_object_arch
, 0 },
3959 { "fpu", s_arm_fpu
, 0 },
3961 { "word", s_arm_elf_cons
, 4 },
3962 { "long", s_arm_elf_cons
, 4 },
3963 { "rel31", s_arm_rel31
, 0 },
3964 { "fnstart", s_arm_unwind_fnstart
, 0 },
3965 { "fnend", s_arm_unwind_fnend
, 0 },
3966 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3967 { "personality", s_arm_unwind_personality
, 0 },
3968 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3969 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3970 { "save", s_arm_unwind_save
, 0 },
3971 { "vsave", s_arm_unwind_save
, 1 },
3972 { "movsp", s_arm_unwind_movsp
, 0 },
3973 { "pad", s_arm_unwind_pad
, 0 },
3974 { "setfp", s_arm_unwind_setfp
, 0 },
3975 { "unwind_raw", s_arm_unwind_raw
, 0 },
3976 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3980 /* These are used for dwarf. */
3984 /* These are used for dwarf2. */
3985 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3986 { "loc", dwarf2_directive_loc
, 0 },
3987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3989 { "extend", float_cons
, 'x' },
3990 { "ldouble", float_cons
, 'x' },
3991 { "packed", float_cons
, 'p' },
3993 {"secrel32", pe_directive_secrel
, 0},
3998 /* Parser functions used exclusively in instruction operands. */
4000 /* Generic immediate-value read function for use in insn parsing.
4001 STR points to the beginning of the immediate (the leading #);
4002 VAL receives the value; if the value is outside [MIN, MAX]
4003 issue an error. PREFIX_OPT is true if the immediate prefix is
4007 parse_immediate (char **str
, int *val
, int min
, int max
,
4008 bfd_boolean prefix_opt
)
4011 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4012 if (exp
.X_op
!= O_constant
)
4014 inst
.error
= _("constant expression required");
4018 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4020 inst
.error
= _("immediate value out of range");
4024 *val
= exp
.X_add_number
;
4028 /* Less-generic immediate-value read function with the possibility of loading a
4029 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4030 instructions. Puts the result directly in inst.operands[i]. */
4033 parse_big_immediate (char **str
, int i
)
4038 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4040 if (exp
.X_op
== O_constant
)
4042 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4043 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4044 O_constant. We have to be careful not to break compilation for
4045 32-bit X_add_number, though. */
4046 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4048 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4049 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4050 inst
.operands
[i
].regisimm
= 1;
4053 else if (exp
.X_op
== O_big
4054 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4055 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4057 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4058 /* Bignums have their least significant bits in
4059 generic_bignum[0]. Make sure we put 32 bits in imm and
4060 32 bits in reg, in a (hopefully) portable way. */
4061 assert (parts
!= 0);
4062 inst
.operands
[i
].imm
= 0;
4063 for (j
= 0; j
< parts
; j
++, idx
++)
4064 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4065 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4066 inst
.operands
[i
].reg
= 0;
4067 for (j
= 0; j
< parts
; j
++, idx
++)
4068 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4069 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4070 inst
.operands
[i
].regisimm
= 1;
4080 /* Returns the pseudo-register number of an FPA immediate constant,
4081 or FAIL if there isn't a valid constant here. */
4084 parse_fpa_immediate (char ** str
)
4086 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4092 /* First try and match exact strings, this is to guarantee
4093 that some formats will work even for cross assembly. */
4095 for (i
= 0; fp_const
[i
]; i
++)
4097 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4101 *str
+= strlen (fp_const
[i
]);
4102 if (is_end_of_line
[(unsigned char) **str
])
4108 /* Just because we didn't get a match doesn't mean that the constant
4109 isn't valid, just that it is in a format that we don't
4110 automatically recognize. Try parsing it with the standard
4111 expression routines. */
4113 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4115 /* Look for a raw floating point number. */
4116 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4117 && is_end_of_line
[(unsigned char) *save_in
])
4119 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4121 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4123 if (words
[j
] != fp_values
[i
][j
])
4127 if (j
== MAX_LITTLENUMS
)
4135 /* Try and parse a more complex expression, this will probably fail
4136 unless the code uses a floating point prefix (eg "0f"). */
4137 save_in
= input_line_pointer
;
4138 input_line_pointer
= *str
;
4139 if (expression (&exp
) == absolute_section
4140 && exp
.X_op
== O_big
4141 && exp
.X_add_number
< 0)
4143 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4145 if (gen_to_words (words
, 5, (long) 15) == 0)
4147 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4149 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4151 if (words
[j
] != fp_values
[i
][j
])
4155 if (j
== MAX_LITTLENUMS
)
4157 *str
= input_line_pointer
;
4158 input_line_pointer
= save_in
;
4165 *str
= input_line_pointer
;
4166 input_line_pointer
= save_in
;
4167 inst
.error
= _("invalid FPA immediate expression");
4171 /* Returns 1 if a number has "quarter-precision" float format
4172 0baBbbbbbc defgh000 00000000 00000000. */
4175 is_quarter_float (unsigned imm
)
4177 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4178 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4181 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4182 0baBbbbbbc defgh000 00000000 00000000.
4183 The zero and minus-zero cases need special handling, since they can't be
4184 encoded in the "quarter-precision" float format, but can nonetheless be
4185 loaded as integer constants. */
4188 parse_qfloat_immediate (char **ccp
, int *immed
)
4192 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4193 int found_fpchar
= 0;
4195 skip_past_char (&str
, '#');
4197 /* We must not accidentally parse an integer as a floating-point number. Make
4198 sure that the value we parse is not an integer by checking for special
4199 characters '.' or 'e'.
4200 FIXME: This is a horrible hack, but doing better is tricky because type
4201 information isn't in a very usable state at parse time. */
4203 skip_whitespace (fpnum
);
4205 if (strncmp (fpnum
, "0x", 2) == 0)
4209 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4210 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4220 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4222 unsigned fpword
= 0;
4225 /* Our FP word must be 32 bits (single-precision FP). */
4226 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4228 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4232 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4245 /* Shift operands. */
4248 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4251 struct asm_shift_name
4254 enum shift_kind kind
;
4257 /* Third argument to parse_shift. */
4258 enum parse_shift_mode
4260 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4261 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4262 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4263 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4264 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4267 /* Parse a <shift> specifier on an ARM data processing instruction.
4268 This has three forms:
4270 (LSL|LSR|ASL|ASR|ROR) Rs
4271 (LSL|LSR|ASL|ASR|ROR) #imm
4274 Note that ASL is assimilated to LSL in the instruction encoding, and
4275 RRX to ROR #0 (which cannot be written as such). */
4278 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4280 const struct asm_shift_name
*shift_name
;
4281 enum shift_kind shift
;
4286 for (p
= *str
; ISALPHA (*p
); p
++)
4291 inst
.error
= _("shift expression expected");
4295 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4297 if (shift_name
== NULL
)
4299 inst
.error
= _("shift expression expected");
4303 shift
= shift_name
->kind
;
4307 case NO_SHIFT_RESTRICT
:
4308 case SHIFT_IMMEDIATE
: break;
4310 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4311 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4313 inst
.error
= _("'LSL' or 'ASR' required");
4318 case SHIFT_LSL_IMMEDIATE
:
4319 if (shift
!= SHIFT_LSL
)
4321 inst
.error
= _("'LSL' required");
4326 case SHIFT_ASR_IMMEDIATE
:
4327 if (shift
!= SHIFT_ASR
)
4329 inst
.error
= _("'ASR' required");
4337 if (shift
!= SHIFT_RRX
)
4339 /* Whitespace can appear here if the next thing is a bare digit. */
4340 skip_whitespace (p
);
4342 if (mode
== NO_SHIFT_RESTRICT
4343 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4345 inst
.operands
[i
].imm
= reg
;
4346 inst
.operands
[i
].immisreg
= 1;
4348 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4351 inst
.operands
[i
].shift_kind
= shift
;
4352 inst
.operands
[i
].shifted
= 1;
4357 /* Parse a <shifter_operand> for an ARM data processing instruction:
4360 #<immediate>, <rotate>
4364 where <shift> is defined by parse_shift above, and <rotate> is a
4365 multiple of 2 between 0 and 30. Validation of immediate operands
4366 is deferred to md_apply_fix. */
4369 parse_shifter_operand (char **str
, int i
)
4374 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4376 inst
.operands
[i
].reg
= value
;
4377 inst
.operands
[i
].isreg
= 1;
4379 /* parse_shift will override this if appropriate */
4380 inst
.reloc
.exp
.X_op
= O_constant
;
4381 inst
.reloc
.exp
.X_add_number
= 0;
4383 if (skip_past_comma (str
) == FAIL
)
4386 /* Shift operation on register. */
4387 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4390 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4393 if (skip_past_comma (str
) == SUCCESS
)
4395 /* #x, y -- ie explicit rotation by Y. */
4396 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4399 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4401 inst
.error
= _("constant expression expected");
4405 value
= expr
.X_add_number
;
4406 if (value
< 0 || value
> 30 || value
% 2 != 0)
4408 inst
.error
= _("invalid rotation");
4411 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4413 inst
.error
= _("invalid constant");
4417 /* Convert to decoded value. md_apply_fix will put it back. */
4418 inst
.reloc
.exp
.X_add_number
4419 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4420 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4423 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4424 inst
.reloc
.pc_rel
= 0;
4428 /* Group relocation information. Each entry in the table contains the
4429 textual name of the relocation as may appear in assembler source
4430 and must end with a colon.
4431 Along with this textual name are the relocation codes to be used if
4432 the corresponding instruction is an ALU instruction (ADD or SUB only),
4433 an LDR, an LDRS, or an LDC. */
4435 struct group_reloc_table_entry
4446 /* Varieties of non-ALU group relocation. */
4453 static struct group_reloc_table_entry group_reloc_table
[] =
4454 { /* Program counter relative: */
4456 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4461 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4462 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4463 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4464 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4466 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4471 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4472 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4473 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4474 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4476 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4477 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4478 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4479 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4480 /* Section base relative */
4482 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4487 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4488 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4489 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4490 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4492 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4497 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4498 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4499 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4500 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4502 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4503 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4504 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4505 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4507 /* Given the address of a pointer pointing to the textual name of a group
4508 relocation as may appear in assembler source, attempt to find its details
4509 in group_reloc_table. The pointer will be updated to the character after
4510 the trailing colon. On failure, FAIL will be returned; SUCCESS
4511 otherwise. On success, *entry will be updated to point at the relevant
4512 group_reloc_table entry. */
4515 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4518 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4520 int length
= strlen (group_reloc_table
[i
].name
);
4522 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4523 && (*str
)[length
] == ':')
4525 *out
= &group_reloc_table
[i
];
4526 *str
+= (length
+ 1);
4534 /* Parse a <shifter_operand> for an ARM data processing instruction
4535 (as for parse_shifter_operand) where group relocations are allowed:
4538 #<immediate>, <rotate>
4539 #:<group_reloc>:<expression>
4543 where <group_reloc> is one of the strings defined in group_reloc_table.
4544 The hashes are optional.
4546 Everything else is as for parse_shifter_operand. */
4548 static parse_operand_result
4549 parse_shifter_operand_group_reloc (char **str
, int i
)
4551 /* Determine if we have the sequence of characters #: or just :
4552 coming next. If we do, then we check for a group relocation.
4553 If we don't, punt the whole lot to parse_shifter_operand. */
4555 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4556 || (*str
)[0] == ':')
4558 struct group_reloc_table_entry
*entry
;
4560 if ((*str
)[0] == '#')
4565 /* Try to parse a group relocation. Anything else is an error. */
4566 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4568 inst
.error
= _("unknown group relocation");
4569 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4572 /* We now have the group relocation table entry corresponding to
4573 the name in the assembler source. Next, we parse the expression. */
4574 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4575 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4577 /* Record the relocation type (always the ALU variant here). */
4578 inst
.reloc
.type
= entry
->alu_code
;
4579 assert (inst
.reloc
.type
!= 0);
4581 return PARSE_OPERAND_SUCCESS
;
4584 return parse_shifter_operand (str
, i
) == SUCCESS
4585 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4587 /* Never reached. */
4590 /* Parse all forms of an ARM address expression. Information is written
4591 to inst.operands[i] and/or inst.reloc.
4593 Preindexed addressing (.preind=1):
4595 [Rn, #offset] .reg=Rn .reloc.exp=offset
4596 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4597 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4598 .shift_kind=shift .reloc.exp=shift_imm
4600 These three may have a trailing ! which causes .writeback to be set also.
4602 Postindexed addressing (.postind=1, .writeback=1):
4604 [Rn], #offset .reg=Rn .reloc.exp=offset
4605 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4606 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4607 .shift_kind=shift .reloc.exp=shift_imm
4609 Unindexed addressing (.preind=0, .postind=0):
4611 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4615 [Rn]{!} shorthand for [Rn,#0]{!}
4616 =immediate .isreg=0 .reloc.exp=immediate
4617 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4619 It is the caller's responsibility to check for addressing modes not
4620 supported by the instruction, and to set inst.reloc.type. */
4622 static parse_operand_result
4623 parse_address_main (char **str
, int i
, int group_relocations
,
4624 group_reloc_type group_type
)
4629 if (skip_past_char (&p
, '[') == FAIL
)
4631 if (skip_past_char (&p
, '=') == FAIL
)
4633 /* bare address - translate to PC-relative offset */
4634 inst
.reloc
.pc_rel
= 1;
4635 inst
.operands
[i
].reg
= REG_PC
;
4636 inst
.operands
[i
].isreg
= 1;
4637 inst
.operands
[i
].preind
= 1;
4639 /* else a load-constant pseudo op, no special treatment needed here */
4641 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4642 return PARSE_OPERAND_FAIL
;
4645 return PARSE_OPERAND_SUCCESS
;
4648 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4650 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4651 return PARSE_OPERAND_FAIL
;
4653 inst
.operands
[i
].reg
= reg
;
4654 inst
.operands
[i
].isreg
= 1;
4656 if (skip_past_comma (&p
) == SUCCESS
)
4658 inst
.operands
[i
].preind
= 1;
4661 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4663 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4665 inst
.operands
[i
].imm
= reg
;
4666 inst
.operands
[i
].immisreg
= 1;
4668 if (skip_past_comma (&p
) == SUCCESS
)
4669 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4670 return PARSE_OPERAND_FAIL
;
4672 else if (skip_past_char (&p
, ':') == SUCCESS
)
4674 /* FIXME: '@' should be used here, but it's filtered out by generic
4675 code before we get to see it here. This may be subject to
4678 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4679 if (exp
.X_op
!= O_constant
)
4681 inst
.error
= _("alignment must be constant");
4682 return PARSE_OPERAND_FAIL
;
4684 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4685 inst
.operands
[i
].immisalign
= 1;
4686 /* Alignments are not pre-indexes. */
4687 inst
.operands
[i
].preind
= 0;
4691 if (inst
.operands
[i
].negative
)
4693 inst
.operands
[i
].negative
= 0;
4697 if (group_relocations
4698 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4700 struct group_reloc_table_entry
*entry
;
4702 /* Skip over the #: or : sequence. */
4708 /* Try to parse a group relocation. Anything else is an
4710 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4712 inst
.error
= _("unknown group relocation");
4713 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4716 /* We now have the group relocation table entry corresponding to
4717 the name in the assembler source. Next, we parse the
4719 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4720 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4722 /* Record the relocation type. */
4726 inst
.reloc
.type
= entry
->ldr_code
;
4730 inst
.reloc
.type
= entry
->ldrs_code
;
4734 inst
.reloc
.type
= entry
->ldc_code
;
4741 if (inst
.reloc
.type
== 0)
4743 inst
.error
= _("this group relocation is not allowed on this instruction");
4744 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4748 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4749 return PARSE_OPERAND_FAIL
;
4753 if (skip_past_char (&p
, ']') == FAIL
)
4755 inst
.error
= _("']' expected");
4756 return PARSE_OPERAND_FAIL
;
4759 if (skip_past_char (&p
, '!') == SUCCESS
)
4760 inst
.operands
[i
].writeback
= 1;
4762 else if (skip_past_comma (&p
) == SUCCESS
)
4764 if (skip_past_char (&p
, '{') == SUCCESS
)
4766 /* [Rn], {expr} - unindexed, with option */
4767 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4768 0, 255, TRUE
) == FAIL
)
4769 return PARSE_OPERAND_FAIL
;
4771 if (skip_past_char (&p
, '}') == FAIL
)
4773 inst
.error
= _("'}' expected at end of 'option' field");
4774 return PARSE_OPERAND_FAIL
;
4776 if (inst
.operands
[i
].preind
)
4778 inst
.error
= _("cannot combine index with option");
4779 return PARSE_OPERAND_FAIL
;
4782 return PARSE_OPERAND_SUCCESS
;
4786 inst
.operands
[i
].postind
= 1;
4787 inst
.operands
[i
].writeback
= 1;
4789 if (inst
.operands
[i
].preind
)
4791 inst
.error
= _("cannot combine pre- and post-indexing");
4792 return PARSE_OPERAND_FAIL
;
4796 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4798 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4800 /* We might be using the immediate for alignment already. If we
4801 are, OR the register number into the low-order bits. */
4802 if (inst
.operands
[i
].immisalign
)
4803 inst
.operands
[i
].imm
|= reg
;
4805 inst
.operands
[i
].imm
= reg
;
4806 inst
.operands
[i
].immisreg
= 1;
4808 if (skip_past_comma (&p
) == SUCCESS
)
4809 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4810 return PARSE_OPERAND_FAIL
;
4814 if (inst
.operands
[i
].negative
)
4816 inst
.operands
[i
].negative
= 0;
4819 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4820 return PARSE_OPERAND_FAIL
;
4825 /* If at this point neither .preind nor .postind is set, we have a
4826 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4827 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4829 inst
.operands
[i
].preind
= 1;
4830 inst
.reloc
.exp
.X_op
= O_constant
;
4831 inst
.reloc
.exp
.X_add_number
= 0;
4834 return PARSE_OPERAND_SUCCESS
;
4838 parse_address (char **str
, int i
)
4840 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4844 static parse_operand_result
4845 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4847 return parse_address_main (str
, i
, 1, type
);
4850 /* Parse an operand for a MOVW or MOVT instruction. */
4852 parse_half (char **str
)
4857 skip_past_char (&p
, '#');
4858 if (strncasecmp (p
, ":lower16:", 9) == 0)
4859 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4860 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4861 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4863 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4866 skip_whitespace (p
);
4869 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4872 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4874 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4876 inst
.error
= _("constant expression expected");
4879 if (inst
.reloc
.exp
.X_add_number
< 0
4880 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4882 inst
.error
= _("immediate value out of range");
4890 /* Miscellaneous. */
4892 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4893 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4895 parse_psr (char **str
)
4898 unsigned long psr_field
;
4899 const struct asm_psr
*psr
;
4902 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4903 feature for ease of use and backwards compatibility. */
4905 if (strncasecmp (p
, "SPSR", 4) == 0)
4906 psr_field
= SPSR_BIT
;
4907 else if (strncasecmp (p
, "CPSR", 4) == 0)
4914 while (ISALNUM (*p
) || *p
== '_');
4916 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4927 /* A suffix follows. */
4933 while (ISALNUM (*p
) || *p
== '_');
4935 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4939 psr_field
|= psr
->field
;
4944 goto error
; /* Garbage after "[CS]PSR". */
4946 psr_field
|= (PSR_c
| PSR_f
);
4952 inst
.error
= _("flag for {c}psr instruction expected");
4956 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4957 value suitable for splatting into the AIF field of the instruction. */
4960 parse_cps_flags (char **str
)
4969 case '\0': case ',':
4972 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4973 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4974 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4977 inst
.error
= _("unrecognized CPS flag");
4982 if (saw_a_flag
== 0)
4984 inst
.error
= _("missing CPS flags");
4992 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4993 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4996 parse_endian_specifier (char **str
)
5001 if (strncasecmp (s
, "BE", 2))
5003 else if (strncasecmp (s
, "LE", 2))
5007 inst
.error
= _("valid endian specifiers are be or le");
5011 if (ISALNUM (s
[2]) || s
[2] == '_')
5013 inst
.error
= _("valid endian specifiers are be or le");
5018 return little_endian
;
5021 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5022 value suitable for poking into the rotate field of an sxt or sxta
5023 instruction, or FAIL on error. */
5026 parse_ror (char **str
)
5031 if (strncasecmp (s
, "ROR", 3) == 0)
5035 inst
.error
= _("missing rotation field after comma");
5039 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5044 case 0: *str
= s
; return 0x0;
5045 case 8: *str
= s
; return 0x1;
5046 case 16: *str
= s
; return 0x2;
5047 case 24: *str
= s
; return 0x3;
5050 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5055 /* Parse a conditional code (from conds[] below). The value returned is in the
5056 range 0 .. 14, or FAIL. */
5058 parse_cond (char **str
)
5061 const struct asm_cond
*c
;
5063 /* Condition codes are always 2 characters, so matching up to
5064 3 characters is sufficient. */
5069 while (ISALPHA (*q
) && n
< 3)
5071 cond
[n
] = TOLOWER(*q
);
5076 c
= hash_find_n (arm_cond_hsh
, cond
, n
);
5079 inst
.error
= _("condition required");
5087 /* Parse an option for a barrier instruction. Returns the encoding for the
5090 parse_barrier (char **str
)
5093 const struct asm_barrier_opt
*o
;
5096 while (ISALPHA (*q
))
5099 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5107 /* Parse the operands of a table branch instruction. Similar to a memory
5110 parse_tb (char **str
)
5115 if (skip_past_char (&p
, '[') == FAIL
)
5117 inst
.error
= _("'[' expected");
5121 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5123 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5126 inst
.operands
[0].reg
= reg
;
5128 if (skip_past_comma (&p
) == FAIL
)
5130 inst
.error
= _("',' expected");
5134 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5136 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5139 inst
.operands
[0].imm
= reg
;
5141 if (skip_past_comma (&p
) == SUCCESS
)
5143 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5145 if (inst
.reloc
.exp
.X_add_number
!= 1)
5147 inst
.error
= _("invalid shift");
5150 inst
.operands
[0].shifted
= 1;
5153 if (skip_past_char (&p
, ']') == FAIL
)
5155 inst
.error
= _("']' expected");
5162 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5163 information on the types the operands can take and how they are encoded.
5164 Up to four operands may be read; this function handles setting the
5165 ".present" field for each read operand itself.
5166 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5167 else returns FAIL. */
5170 parse_neon_mov (char **str
, int *which_operand
)
5172 int i
= *which_operand
, val
;
5173 enum arm_reg_type rtype
;
5175 struct neon_type_el optype
;
5177 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5179 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5180 inst
.operands
[i
].reg
= val
;
5181 inst
.operands
[i
].isscalar
= 1;
5182 inst
.operands
[i
].vectype
= optype
;
5183 inst
.operands
[i
++].present
= 1;
5185 if (skip_past_comma (&ptr
) == FAIL
)
5188 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5191 inst
.operands
[i
].reg
= val
;
5192 inst
.operands
[i
].isreg
= 1;
5193 inst
.operands
[i
].present
= 1;
5195 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5198 /* Cases 0, 1, 2, 3, 5 (D only). */
5199 if (skip_past_comma (&ptr
) == FAIL
)
5202 inst
.operands
[i
].reg
= val
;
5203 inst
.operands
[i
].isreg
= 1;
5204 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5205 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5206 inst
.operands
[i
].isvec
= 1;
5207 inst
.operands
[i
].vectype
= optype
;
5208 inst
.operands
[i
++].present
= 1;
5210 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5212 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5213 Case 13: VMOV <Sd>, <Rm> */
5214 inst
.operands
[i
].reg
= val
;
5215 inst
.operands
[i
].isreg
= 1;
5216 inst
.operands
[i
].present
= 1;
5218 if (rtype
== REG_TYPE_NQ
)
5220 first_error (_("can't use Neon quad register here"));
5223 else if (rtype
!= REG_TYPE_VFS
)
5226 if (skip_past_comma (&ptr
) == FAIL
)
5228 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5230 inst
.operands
[i
].reg
= val
;
5231 inst
.operands
[i
].isreg
= 1;
5232 inst
.operands
[i
].present
= 1;
5235 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5238 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5239 Case 1: VMOV<c><q> <Dd>, <Dm>
5240 Case 8: VMOV.F32 <Sd>, <Sm>
5241 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5243 inst
.operands
[i
].reg
= val
;
5244 inst
.operands
[i
].isreg
= 1;
5245 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5246 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5247 inst
.operands
[i
].isvec
= 1;
5248 inst
.operands
[i
].vectype
= optype
;
5249 inst
.operands
[i
].present
= 1;
5251 if (skip_past_comma (&ptr
) == SUCCESS
)
5256 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5259 inst
.operands
[i
].reg
= val
;
5260 inst
.operands
[i
].isreg
= 1;
5261 inst
.operands
[i
++].present
= 1;
5263 if (skip_past_comma (&ptr
) == FAIL
)
5266 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5269 inst
.operands
[i
].reg
= val
;
5270 inst
.operands
[i
].isreg
= 1;
5271 inst
.operands
[i
++].present
= 1;
5274 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5275 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5276 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5277 Case 10: VMOV.F32 <Sd>, #<imm>
5278 Case 11: VMOV.F64 <Dd>, #<imm> */
5279 inst
.operands
[i
].immisfloat
= 1;
5280 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5281 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5282 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5286 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5290 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5293 inst
.operands
[i
].reg
= val
;
5294 inst
.operands
[i
].isreg
= 1;
5295 inst
.operands
[i
++].present
= 1;
5297 if (skip_past_comma (&ptr
) == FAIL
)
5300 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5302 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5303 inst
.operands
[i
].reg
= val
;
5304 inst
.operands
[i
].isscalar
= 1;
5305 inst
.operands
[i
].present
= 1;
5306 inst
.operands
[i
].vectype
= optype
;
5308 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5310 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5311 inst
.operands
[i
].reg
= val
;
5312 inst
.operands
[i
].isreg
= 1;
5313 inst
.operands
[i
++].present
= 1;
5315 if (skip_past_comma (&ptr
) == FAIL
)
5318 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5321 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5325 inst
.operands
[i
].reg
= val
;
5326 inst
.operands
[i
].isreg
= 1;
5327 inst
.operands
[i
].isvec
= 1;
5328 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5329 inst
.operands
[i
].vectype
= optype
;
5330 inst
.operands
[i
].present
= 1;
5332 if (rtype
== REG_TYPE_VFS
)
5336 if (skip_past_comma (&ptr
) == FAIL
)
5338 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5341 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5344 inst
.operands
[i
].reg
= val
;
5345 inst
.operands
[i
].isreg
= 1;
5346 inst
.operands
[i
].isvec
= 1;
5347 inst
.operands
[i
].issingle
= 1;
5348 inst
.operands
[i
].vectype
= optype
;
5349 inst
.operands
[i
].present
= 1;
5352 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5356 inst
.operands
[i
].reg
= val
;
5357 inst
.operands
[i
].isreg
= 1;
5358 inst
.operands
[i
].isvec
= 1;
5359 inst
.operands
[i
].issingle
= 1;
5360 inst
.operands
[i
].vectype
= optype
;
5361 inst
.operands
[i
++].present
= 1;
5366 first_error (_("parse error"));
5370 /* Successfully parsed the operands. Update args. */
5376 first_error (_("expected comma"));
5380 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5384 /* Matcher codes for parse_operands. */
5385 enum operand_parse_code
5387 OP_stop
, /* end of line */
5389 OP_RR
, /* ARM register */
5390 OP_RRnpc
, /* ARM register, not r15 */
5391 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5392 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5393 OP_RCP
, /* Coprocessor number */
5394 OP_RCN
, /* Coprocessor register */
5395 OP_RF
, /* FPA register */
5396 OP_RVS
, /* VFP single precision register */
5397 OP_RVD
, /* VFP double precision register (0..15) */
5398 OP_RND
, /* Neon double precision register (0..31) */
5399 OP_RNQ
, /* Neon quad precision register */
5400 OP_RVSD
, /* VFP single or double precision register */
5401 OP_RNDQ
, /* Neon double or quad precision register */
5402 OP_RNSDQ
, /* Neon single, double or quad precision register */
5403 OP_RNSC
, /* Neon scalar D[X] */
5404 OP_RVC
, /* VFP control register */
5405 OP_RMF
, /* Maverick F register */
5406 OP_RMD
, /* Maverick D register */
5407 OP_RMFX
, /* Maverick FX register */
5408 OP_RMDX
, /* Maverick DX register */
5409 OP_RMAX
, /* Maverick AX register */
5410 OP_RMDS
, /* Maverick DSPSC register */
5411 OP_RIWR
, /* iWMMXt wR register */
5412 OP_RIWC
, /* iWMMXt wC register */
5413 OP_RIWG
, /* iWMMXt wCG register */
5414 OP_RXA
, /* XScale accumulator register */
5416 OP_REGLST
, /* ARM register list */
5417 OP_VRSLST
, /* VFP single-precision register list */
5418 OP_VRDLST
, /* VFP double-precision register list */
5419 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5420 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5421 OP_NSTRLST
, /* Neon element/structure list */
5423 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5424 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5425 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5426 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5427 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5428 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5429 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5430 OP_VMOV
, /* Neon VMOV operands. */
5431 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5432 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5433 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5435 OP_I0
, /* immediate zero */
5436 OP_I7
, /* immediate value 0 .. 7 */
5437 OP_I15
, /* 0 .. 15 */
5438 OP_I16
, /* 1 .. 16 */
5439 OP_I16z
, /* 0 .. 16 */
5440 OP_I31
, /* 0 .. 31 */
5441 OP_I31w
, /* 0 .. 31, optional trailing ! */
5442 OP_I32
, /* 1 .. 32 */
5443 OP_I32z
, /* 0 .. 32 */
5444 OP_I63
, /* 0 .. 63 */
5445 OP_I63s
, /* -64 .. 63 */
5446 OP_I64
, /* 1 .. 64 */
5447 OP_I64z
, /* 0 .. 64 */
5448 OP_I255
, /* 0 .. 255 */
5450 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5451 OP_I7b
, /* 0 .. 7 */
5452 OP_I15b
, /* 0 .. 15 */
5453 OP_I31b
, /* 0 .. 31 */
5455 OP_SH
, /* shifter operand */
5456 OP_SHG
, /* shifter operand with possible group relocation */
5457 OP_ADDR
, /* Memory address expression (any mode) */
5458 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5459 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5460 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5461 OP_EXP
, /* arbitrary expression */
5462 OP_EXPi
, /* same, with optional immediate prefix */
5463 OP_EXPr
, /* same, with optional relocation suffix */
5464 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5466 OP_CPSF
, /* CPS flags */
5467 OP_ENDI
, /* Endianness specifier */
5468 OP_PSR
, /* CPSR/SPSR mask for msr */
5469 OP_COND
, /* conditional code */
5470 OP_TB
, /* Table branch. */
5472 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5473 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5475 OP_RRnpc_I0
, /* ARM register or literal 0 */
5476 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5477 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5478 OP_RF_IF
, /* FPA register or immediate */
5479 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5480 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5482 /* Optional operands. */
5483 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5484 OP_oI31b
, /* 0 .. 31 */
5485 OP_oI32b
, /* 1 .. 32 */
5486 OP_oIffffb
, /* 0 .. 65535 */
5487 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5489 OP_oRR
, /* ARM register */
5490 OP_oRRnpc
, /* ARM register, not the PC */
5491 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5492 OP_oRND
, /* Optional Neon double precision register */
5493 OP_oRNQ
, /* Optional Neon quad precision register */
5494 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5495 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5496 OP_oSHll
, /* LSL immediate */
5497 OP_oSHar
, /* ASR immediate */
5498 OP_oSHllar
, /* LSL or ASR immediate */
5499 OP_oROR
, /* ROR 0/8/16/24 */
5500 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5502 OP_FIRST_OPTIONAL
= OP_oI7b
5505 /* Generic instruction operand parser. This does no encoding and no
5506 semantic validation; it merely squirrels values away in the inst
5507 structure. Returns SUCCESS or FAIL depending on whether the
5508 specified grammar matched. */
5510 parse_operands (char *str
, const unsigned char *pattern
)
5512 unsigned const char *upat
= pattern
;
5513 char *backtrack_pos
= 0;
5514 const char *backtrack_error
= 0;
5515 int i
, val
, backtrack_index
= 0;
5516 enum arm_reg_type rtype
;
5517 parse_operand_result result
;
5519 #define po_char_or_fail(chr) do { \
5520 if (skip_past_char (&str, chr) == FAIL) \
5524 #define po_reg_or_fail(regtype) do { \
5525 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5526 &inst.operands[i].vectype); \
5529 first_error (_(reg_expected_msgs[regtype])); \
5532 inst.operands[i].reg = val; \
5533 inst.operands[i].isreg = 1; \
5534 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5535 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5536 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5537 || rtype == REG_TYPE_VFD \
5538 || rtype == REG_TYPE_NQ); \
5541 #define po_reg_or_goto(regtype, label) do { \
5542 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5543 &inst.operands[i].vectype); \
5547 inst.operands[i].reg = val; \
5548 inst.operands[i].isreg = 1; \
5549 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5550 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5551 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5552 || rtype == REG_TYPE_VFD \
5553 || rtype == REG_TYPE_NQ); \
5556 #define po_imm_or_fail(min, max, popt) do { \
5557 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5559 inst.operands[i].imm = val; \
5562 #define po_scalar_or_goto(elsz, label) do { \
5563 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5566 inst.operands[i].reg = val; \
5567 inst.operands[i].isscalar = 1; \
5570 #define po_misc_or_fail(expr) do { \
5575 #define po_misc_or_fail_no_backtrack(expr) do { \
5577 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5578 backtrack_pos = 0; \
5579 if (result != PARSE_OPERAND_SUCCESS) \
5583 skip_whitespace (str
);
5585 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5587 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5589 /* Remember where we are in case we need to backtrack. */
5590 assert (!backtrack_pos
);
5591 backtrack_pos
= str
;
5592 backtrack_error
= inst
.error
;
5593 backtrack_index
= i
;
5596 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5597 po_char_or_fail (',');
5605 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5606 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5607 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5608 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5609 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5610 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5612 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5614 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5616 /* Also accept generic coprocessor regs for unknown registers. */
5618 po_reg_or_fail (REG_TYPE_CN
);
5620 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5621 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5622 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5623 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5624 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5625 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5626 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5627 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5628 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5629 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5631 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5633 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5634 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5636 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5638 /* Neon scalar. Using an element size of 8 means that some invalid
5639 scalars are accepted here, so deal with those in later code. */
5640 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5642 /* WARNING: We can expand to two operands here. This has the potential
5643 to totally confuse the backtracking mechanism! It will be OK at
5644 least as long as we don't try to use optional args as well,
5648 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5649 inst
.operands
[i
].present
= 1;
5651 skip_past_comma (&str
);
5652 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5655 /* Optional register operand was omitted. Unfortunately, it's in
5656 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5657 here (this is a bit grotty). */
5658 inst
.operands
[i
] = inst
.operands
[i
-1];
5659 inst
.operands
[i
-1].present
= 0;
5662 /* There's a possibility of getting a 64-bit immediate here, so
5663 we need special handling. */
5664 if (parse_big_immediate (&str
, i
) == FAIL
)
5666 inst
.error
= _("immediate value is out of range");
5674 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5677 po_imm_or_fail (0, 0, TRUE
);
5682 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5687 po_scalar_or_goto (8, try_rr
);
5690 po_reg_or_fail (REG_TYPE_RN
);
5696 po_scalar_or_goto (8, try_nsdq
);
5699 po_reg_or_fail (REG_TYPE_NSDQ
);
5705 po_scalar_or_goto (8, try_ndq
);
5708 po_reg_or_fail (REG_TYPE_NDQ
);
5714 po_scalar_or_goto (8, try_vfd
);
5717 po_reg_or_fail (REG_TYPE_VFD
);
5722 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5723 not careful then bad things might happen. */
5724 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5729 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5732 /* There's a possibility of getting a 64-bit immediate here, so
5733 we need special handling. */
5734 if (parse_big_immediate (&str
, i
) == FAIL
)
5736 inst
.error
= _("immediate value is out of range");
5744 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5747 po_imm_or_fail (0, 63, TRUE
);
5752 po_char_or_fail ('[');
5753 po_reg_or_fail (REG_TYPE_RN
);
5754 po_char_or_fail (']');
5759 po_reg_or_fail (REG_TYPE_RN
);
5760 if (skip_past_char (&str
, '!') == SUCCESS
)
5761 inst
.operands
[i
].writeback
= 1;
5765 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5766 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5767 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5768 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5769 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5770 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5771 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5772 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5773 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5774 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5775 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5776 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5778 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5780 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5781 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5783 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5784 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5785 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5787 /* Immediate variants */
5789 po_char_or_fail ('{');
5790 po_imm_or_fail (0, 255, TRUE
);
5791 po_char_or_fail ('}');
5795 /* The expression parser chokes on a trailing !, so we have
5796 to find it first and zap it. */
5799 while (*s
&& *s
!= ',')
5804 inst
.operands
[i
].writeback
= 1;
5806 po_imm_or_fail (0, 31, TRUE
);
5814 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5819 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5824 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5826 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5828 val
= parse_reloc (&str
);
5831 inst
.error
= _("unrecognized relocation suffix");
5834 else if (val
!= BFD_RELOC_UNUSED
)
5836 inst
.operands
[i
].imm
= val
;
5837 inst
.operands
[i
].hasreloc
= 1;
5842 /* Operand for MOVW or MOVT. */
5844 po_misc_or_fail (parse_half (&str
));
5847 /* Register or expression */
5848 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5849 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5851 /* Register or immediate */
5852 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5853 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5855 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5857 if (!is_immediate_prefix (*str
))
5860 val
= parse_fpa_immediate (&str
);
5863 /* FPA immediates are encoded as registers 8-15.
5864 parse_fpa_immediate has already applied the offset. */
5865 inst
.operands
[i
].reg
= val
;
5866 inst
.operands
[i
].isreg
= 1;
5869 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5870 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5872 /* Two kinds of register */
5875 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5877 || (rege
->type
!= REG_TYPE_MMXWR
5878 && rege
->type
!= REG_TYPE_MMXWC
5879 && rege
->type
!= REG_TYPE_MMXWCG
))
5881 inst
.error
= _("iWMMXt data or control register expected");
5884 inst
.operands
[i
].reg
= rege
->number
;
5885 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5891 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5893 || (rege
->type
!= REG_TYPE_MMXWC
5894 && rege
->type
!= REG_TYPE_MMXWCG
))
5896 inst
.error
= _("iWMMXt control register expected");
5899 inst
.operands
[i
].reg
= rege
->number
;
5900 inst
.operands
[i
].isreg
= 1;
5905 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5906 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5907 case OP_oROR
: val
= parse_ror (&str
); break;
5908 case OP_PSR
: val
= parse_psr (&str
); break;
5909 case OP_COND
: val
= parse_cond (&str
); break;
5910 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5913 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5914 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5917 val
= parse_psr (&str
);
5921 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5924 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5926 if (strncasecmp (str
, "APSR_", 5) == 0)
5933 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5934 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5935 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5936 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5937 default: found
= 16;
5941 inst
.operands
[i
].isvec
= 1;
5948 po_misc_or_fail (parse_tb (&str
));
5951 /* Register lists */
5953 val
= parse_reg_list (&str
);
5956 inst
.operands
[1].writeback
= 1;
5962 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5966 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5970 /* Allow Q registers too. */
5971 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5976 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5978 inst
.operands
[i
].issingle
= 1;
5983 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5988 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5989 &inst
.operands
[i
].vectype
);
5992 /* Addressing modes */
5994 po_misc_or_fail (parse_address (&str
, i
));
5998 po_misc_or_fail_no_backtrack (
5999 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6003 po_misc_or_fail_no_backtrack (
6004 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6008 po_misc_or_fail_no_backtrack (
6009 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6013 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6017 po_misc_or_fail_no_backtrack (
6018 parse_shifter_operand_group_reloc (&str
, i
));
6022 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6026 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6030 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6034 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6037 /* Various value-based sanity checks and shared operations. We
6038 do not signal immediate failures for the register constraints;
6039 this allows a syntax error to take precedence. */
6048 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6049 inst
.error
= BAD_PC
;
6067 inst
.operands
[i
].imm
= val
;
6074 /* If we get here, this operand was successfully parsed. */
6075 inst
.operands
[i
].present
= 1;
6079 inst
.error
= BAD_ARGS
;
6084 /* The parse routine should already have set inst.error, but set a
6085 default here just in case. */
6087 inst
.error
= _("syntax error");
6091 /* Do not backtrack over a trailing optional argument that
6092 absorbed some text. We will only fail again, with the
6093 'garbage following instruction' error message, which is
6094 probably less helpful than the current one. */
6095 if (backtrack_index
== i
&& backtrack_pos
!= str
6096 && upat
[i
+1] == OP_stop
)
6099 inst
.error
= _("syntax error");
6103 /* Try again, skipping the optional argument at backtrack_pos. */
6104 str
= backtrack_pos
;
6105 inst
.error
= backtrack_error
;
6106 inst
.operands
[backtrack_index
].present
= 0;
6107 i
= backtrack_index
;
6111 /* Check that we have parsed all the arguments. */
6112 if (*str
!= '\0' && !inst
.error
)
6113 inst
.error
= _("garbage following instruction");
6115 return inst
.error
? FAIL
: SUCCESS
;
6118 #undef po_char_or_fail
6119 #undef po_reg_or_fail
6120 #undef po_reg_or_goto
6121 #undef po_imm_or_fail
6122 #undef po_scalar_or_fail
6124 /* Shorthand macro for instruction encoding functions issuing errors. */
6125 #define constraint(expr, err) do { \
6133 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6134 instructions are unpredictable if these registers are used. This
6135 is the BadReg predicate in ARM's Thumb-2 documentation. */
6136 #define reject_bad_reg(reg) \
6138 if (reg == REG_SP || reg == REG_PC) \
6140 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6145 /* If REG is R13 (the stack pointer), warn that its use is
6147 #define warn_deprecated_sp(reg) \
6149 if (warn_on_deprecated && reg == REG_SP) \
6150 as_warn (_("use of r13 is deprecated")); \
6153 /* Functions for operand encoding. ARM, then Thumb. */
6155 #define rotate_left(v, n) (v << n | v >> (32 - n))
6157 /* If VAL can be encoded in the immediate field of an ARM instruction,
6158 return the encoded form. Otherwise, return FAIL. */
6161 encode_arm_immediate (unsigned int val
)
6165 for (i
= 0; i
< 32; i
+= 2)
6166 if ((a
= rotate_left (val
, i
)) <= 0xff)
6167 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6172 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6173 return the encoded form. Otherwise, return FAIL. */
6175 encode_thumb32_immediate (unsigned int val
)
6182 for (i
= 1; i
<= 24; i
++)
6185 if ((val
& ~(0xff << i
)) == 0)
6186 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6190 if (val
== ((a
<< 16) | a
))
6192 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6196 if (val
== ((a
<< 16) | a
))
6197 return 0x200 | (a
>> 8);
6201 /* Encode a VFP SP or DP register number into inst.instruction. */
6204 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6206 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6209 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6212 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6215 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6220 first_error (_("D register out of range for selected VFP version"));
6228 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6232 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6236 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6240 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6244 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6248 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6256 /* Encode a <shift> in an ARM-format instruction. The immediate,
6257 if any, is handled by md_apply_fix. */
6259 encode_arm_shift (int i
)
6261 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6262 inst
.instruction
|= SHIFT_ROR
<< 5;
6265 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6266 if (inst
.operands
[i
].immisreg
)
6268 inst
.instruction
|= SHIFT_BY_REG
;
6269 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6272 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6277 encode_arm_shifter_operand (int i
)
6279 if (inst
.operands
[i
].isreg
)
6281 inst
.instruction
|= inst
.operands
[i
].reg
;
6282 encode_arm_shift (i
);
6285 inst
.instruction
|= INST_IMMEDIATE
;
6288 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6290 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6292 assert (inst
.operands
[i
].isreg
);
6293 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6295 if (inst
.operands
[i
].preind
)
6299 inst
.error
= _("instruction does not accept preindexed addressing");
6302 inst
.instruction
|= PRE_INDEX
;
6303 if (inst
.operands
[i
].writeback
)
6304 inst
.instruction
|= WRITE_BACK
;
6307 else if (inst
.operands
[i
].postind
)
6309 assert (inst
.operands
[i
].writeback
);
6311 inst
.instruction
|= WRITE_BACK
;
6313 else /* unindexed - only for coprocessor */
6315 inst
.error
= _("instruction does not accept unindexed addressing");
6319 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6320 && (((inst
.instruction
& 0x000f0000) >> 16)
6321 == ((inst
.instruction
& 0x0000f000) >> 12)))
6322 as_warn ((inst
.instruction
& LOAD_BIT
)
6323 ? _("destination register same as write-back base")
6324 : _("source register same as write-back base"));
6327 /* inst.operands[i] was set up by parse_address. Encode it into an
6328 ARM-format mode 2 load or store instruction. If is_t is true,
6329 reject forms that cannot be used with a T instruction (i.e. not
6332 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6334 encode_arm_addr_mode_common (i
, is_t
);
6336 if (inst
.operands
[i
].immisreg
)
6338 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6339 inst
.instruction
|= inst
.operands
[i
].imm
;
6340 if (!inst
.operands
[i
].negative
)
6341 inst
.instruction
|= INDEX_UP
;
6342 if (inst
.operands
[i
].shifted
)
6344 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6345 inst
.instruction
|= SHIFT_ROR
<< 5;
6348 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6349 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6353 else /* immediate offset in inst.reloc */
6355 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6356 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6360 /* inst.operands[i] was set up by parse_address. Encode it into an
6361 ARM-format mode 3 load or store instruction. Reject forms that
6362 cannot be used with such instructions. If is_t is true, reject
6363 forms that cannot be used with a T instruction (i.e. not
6366 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6368 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6370 inst
.error
= _("instruction does not accept scaled register index");
6374 encode_arm_addr_mode_common (i
, is_t
);
6376 if (inst
.operands
[i
].immisreg
)
6378 inst
.instruction
|= inst
.operands
[i
].imm
;
6379 if (!inst
.operands
[i
].negative
)
6380 inst
.instruction
|= INDEX_UP
;
6382 else /* immediate offset in inst.reloc */
6384 inst
.instruction
|= HWOFFSET_IMM
;
6385 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6386 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6390 /* inst.operands[i] was set up by parse_address. Encode it into an
6391 ARM-format instruction. Reject all forms which cannot be encoded
6392 into a coprocessor load/store instruction. If wb_ok is false,
6393 reject use of writeback; if unind_ok is false, reject use of
6394 unindexed addressing. If reloc_override is not 0, use it instead
6395 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6396 (in which case it is preserved). */
6399 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6401 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6403 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6405 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6407 assert (!inst
.operands
[i
].writeback
);
6410 inst
.error
= _("instruction does not support unindexed addressing");
6413 inst
.instruction
|= inst
.operands
[i
].imm
;
6414 inst
.instruction
|= INDEX_UP
;
6418 if (inst
.operands
[i
].preind
)
6419 inst
.instruction
|= PRE_INDEX
;
6421 if (inst
.operands
[i
].writeback
)
6423 if (inst
.operands
[i
].reg
== REG_PC
)
6425 inst
.error
= _("pc may not be used with write-back");
6430 inst
.error
= _("instruction does not support writeback");
6433 inst
.instruction
|= WRITE_BACK
;
6437 inst
.reloc
.type
= reloc_override
;
6438 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6439 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6440 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6443 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6445 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6451 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6452 Determine whether it can be performed with a move instruction; if
6453 it can, convert inst.instruction to that move instruction and
6454 return 1; if it can't, convert inst.instruction to a literal-pool
6455 load and return 0. If this is not a valid thing to do in the
6456 current context, set inst.error and return 1.
6458 inst.operands[i] describes the destination register. */
6461 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6466 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6470 if ((inst
.instruction
& tbit
) == 0)
6472 inst
.error
= _("invalid pseudo operation");
6475 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6477 inst
.error
= _("constant expression expected");
6480 if (inst
.reloc
.exp
.X_op
== O_constant
)
6484 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6486 /* This can be done with a mov(1) instruction. */
6487 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6488 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6494 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6497 /* This can be done with a mov instruction. */
6498 inst
.instruction
&= LITERAL_MASK
;
6499 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6500 inst
.instruction
|= value
& 0xfff;
6504 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6507 /* This can be done with a mvn instruction. */
6508 inst
.instruction
&= LITERAL_MASK
;
6509 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6510 inst
.instruction
|= value
& 0xfff;
6516 if (add_to_lit_pool () == FAIL
)
6518 inst
.error
= _("literal pool insertion failed");
6521 inst
.operands
[1].reg
= REG_PC
;
6522 inst
.operands
[1].isreg
= 1;
6523 inst
.operands
[1].preind
= 1;
6524 inst
.reloc
.pc_rel
= 1;
6525 inst
.reloc
.type
= (thumb_p
6526 ? BFD_RELOC_ARM_THUMB_OFFSET
6528 ? BFD_RELOC_ARM_HWLITERAL
6529 : BFD_RELOC_ARM_LITERAL
));
6533 /* Functions for instruction encoding, sorted by sub-architecture.
6534 First some generics; their names are taken from the conventional
6535 bit positions for register arguments in ARM format instructions. */
6545 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6551 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6552 inst
.instruction
|= inst
.operands
[1].reg
;
6558 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6559 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6565 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6566 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6572 unsigned Rn
= inst
.operands
[2].reg
;
6573 /* Enforce restrictions on SWP instruction. */
6574 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6575 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6576 _("Rn must not overlap other operands"));
6577 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6578 inst
.instruction
|= inst
.operands
[1].reg
;
6579 inst
.instruction
|= Rn
<< 16;
6585 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6586 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6587 inst
.instruction
|= inst
.operands
[2].reg
;
6593 inst
.instruction
|= inst
.operands
[0].reg
;
6594 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6595 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6601 inst
.instruction
|= inst
.operands
[0].imm
;
6607 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6608 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6611 /* ARM instructions, in alphabetical order by function name (except
6612 that wrapper functions appear immediately after the function they
6615 /* This is a pseudo-op of the form "adr rd, label" to be converted
6616 into a relative address of the form "add rd, pc, #label-.-8". */
6621 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6623 /* Frag hacking will turn this into a sub instruction if the offset turns
6624 out to be negative. */
6625 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6626 inst
.reloc
.pc_rel
= 1;
6627 inst
.reloc
.exp
.X_add_number
-= 8;
6630 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6631 into a relative address of the form:
6632 add rd, pc, #low(label-.-8)"
6633 add rd, rd, #high(label-.-8)" */
6638 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6640 /* Frag hacking will turn this into a sub instruction if the offset turns
6641 out to be negative. */
6642 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6643 inst
.reloc
.pc_rel
= 1;
6644 inst
.size
= INSN_SIZE
* 2;
6645 inst
.reloc
.exp
.X_add_number
-= 8;
6651 if (!inst
.operands
[1].present
)
6652 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6653 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6654 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6655 encode_arm_shifter_operand (2);
6661 if (inst
.operands
[0].present
)
6663 constraint ((inst
.instruction
& 0xf0) != 0x40
6664 && inst
.operands
[0].imm
!= 0xf,
6665 _("bad barrier type"));
6666 inst
.instruction
|= inst
.operands
[0].imm
;
6669 inst
.instruction
|= 0xf;
6675 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6676 constraint (msb
> 32, _("bit-field extends past end of register"));
6677 /* The instruction encoding stores the LSB and MSB,
6678 not the LSB and width. */
6679 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6680 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6681 inst
.instruction
|= (msb
- 1) << 16;
6689 /* #0 in second position is alternative syntax for bfc, which is
6690 the same instruction but with REG_PC in the Rm field. */
6691 if (!inst
.operands
[1].isreg
)
6692 inst
.operands
[1].reg
= REG_PC
;
6694 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6695 constraint (msb
> 32, _("bit-field extends past end of register"));
6696 /* The instruction encoding stores the LSB and MSB,
6697 not the LSB and width. */
6698 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6699 inst
.instruction
|= inst
.operands
[1].reg
;
6700 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6701 inst
.instruction
|= (msb
- 1) << 16;
6707 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6708 _("bit-field extends past end of register"));
6709 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6710 inst
.instruction
|= inst
.operands
[1].reg
;
6711 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6712 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6715 /* ARM V5 breakpoint instruction (argument parse)
6716 BKPT <16 bit unsigned immediate>
6717 Instruction is not conditional.
6718 The bit pattern given in insns[] has the COND_ALWAYS condition,
6719 and it is an error if the caller tried to override that. */
6724 /* Top 12 of 16 bits to bits 19:8. */
6725 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6727 /* Bottom 4 of 16 bits to bits 3:0. */
6728 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6732 encode_branch (int default_reloc
)
6734 if (inst
.operands
[0].hasreloc
)
6736 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6737 _("the only suffix valid here is '(plt)'"));
6738 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6742 inst
.reloc
.type
= default_reloc
;
6744 inst
.reloc
.pc_rel
= 1;
6751 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6752 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6755 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6762 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6764 if (inst
.cond
== COND_ALWAYS
)
6765 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6767 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6771 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6774 /* ARM V5 branch-link-exchange instruction (argument parse)
6775 BLX <target_addr> ie BLX(1)
6776 BLX{<condition>} <Rm> ie BLX(2)
6777 Unfortunately, there are two different opcodes for this mnemonic.
6778 So, the insns[].value is not used, and the code here zaps values
6779 into inst.instruction.
6780 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6785 if (inst
.operands
[0].isreg
)
6787 /* Arg is a register; the opcode provided by insns[] is correct.
6788 It is not illegal to do "blx pc", just useless. */
6789 if (inst
.operands
[0].reg
== REG_PC
)
6790 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6792 inst
.instruction
|= inst
.operands
[0].reg
;
6796 /* Arg is an address; this instruction cannot be executed
6797 conditionally, and the opcode must be adjusted. */
6798 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6799 inst
.instruction
= 0xfa000000;
6801 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6802 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6805 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6812 bfd_boolean want_reloc
;
6814 if (inst
.operands
[0].reg
== REG_PC
)
6815 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6817 inst
.instruction
|= inst
.operands
[0].reg
;
6818 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
6819 it is for ARMv4t or earlier. */
6820 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
6821 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
6825 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
6830 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
6834 /* ARM v5TEJ. Jump to Jazelle code. */
6839 if (inst
.operands
[0].reg
== REG_PC
)
6840 as_tsktsk (_("use of r15 in bxj is not really useful"));
6842 inst
.instruction
|= inst
.operands
[0].reg
;
6845 /* Co-processor data operation:
6846 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6847 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6851 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6852 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6853 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6854 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6855 inst
.instruction
|= inst
.operands
[4].reg
;
6856 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6862 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6863 encode_arm_shifter_operand (1);
6866 /* Transfer between coprocessor and ARM registers.
6867 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6872 No special properties. */
6879 Rd
= inst
.operands
[2].reg
;
6882 if (inst
.instruction
== 0xee000010
6883 || inst
.instruction
== 0xfe000010)
6885 reject_bad_reg (Rd
);
6888 constraint (Rd
== REG_SP
, BAD_SP
);
6893 if (inst
.instruction
== 0xe000010)
6894 constraint (Rd
== REG_PC
, BAD_PC
);
6898 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6899 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6900 inst
.instruction
|= Rd
<< 12;
6901 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6902 inst
.instruction
|= inst
.operands
[4].reg
;
6903 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6906 /* Transfer between coprocessor register and pair of ARM registers.
6907 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6912 Two XScale instructions are special cases of these:
6914 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6915 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6917 Result unpredictable if Rd or Rn is R15. */
6924 Rd
= inst
.operands
[2].reg
;
6925 Rn
= inst
.operands
[3].reg
;
6929 reject_bad_reg (Rd
);
6930 reject_bad_reg (Rn
);
6934 constraint (Rd
== REG_PC
, BAD_PC
);
6935 constraint (Rn
== REG_PC
, BAD_PC
);
6938 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6939 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6940 inst
.instruction
|= Rd
<< 12;
6941 inst
.instruction
|= Rn
<< 16;
6942 inst
.instruction
|= inst
.operands
[4].reg
;
6948 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6949 if (inst
.operands
[1].present
)
6951 inst
.instruction
|= CPSI_MMOD
;
6952 inst
.instruction
|= inst
.operands
[1].imm
;
6959 inst
.instruction
|= inst
.operands
[0].imm
;
6965 /* There is no IT instruction in ARM mode. We
6966 process it but do not generate code for it. */
6973 int base_reg
= inst
.operands
[0].reg
;
6974 int range
= inst
.operands
[1].imm
;
6976 inst
.instruction
|= base_reg
<< 16;
6977 inst
.instruction
|= range
;
6979 if (inst
.operands
[1].writeback
)
6980 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6982 if (inst
.operands
[0].writeback
)
6984 inst
.instruction
|= WRITE_BACK
;
6985 /* Check for unpredictable uses of writeback. */
6986 if (inst
.instruction
& LOAD_BIT
)
6988 /* Not allowed in LDM type 2. */
6989 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6990 && ((range
& (1 << REG_PC
)) == 0))
6991 as_warn (_("writeback of base register is UNPREDICTABLE"));
6992 /* Only allowed if base reg not in list for other types. */
6993 else if (range
& (1 << base_reg
))
6994 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6998 /* Not allowed for type 2. */
6999 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7000 as_warn (_("writeback of base register is UNPREDICTABLE"));
7001 /* Only allowed if base reg not in list, or first in list. */
7002 else if ((range
& (1 << base_reg
))
7003 && (range
& ((1 << base_reg
) - 1)))
7004 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7009 /* ARMv5TE load-consecutive (argument parse)
7018 constraint (inst
.operands
[0].reg
% 2 != 0,
7019 _("first destination register must be even"));
7020 constraint (inst
.operands
[1].present
7021 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7022 _("can only load two consecutive registers"));
7023 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7024 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7026 if (!inst
.operands
[1].present
)
7027 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7029 if (inst
.instruction
& LOAD_BIT
)
7031 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7032 register and the first register written; we have to diagnose
7033 overlap between the base and the second register written here. */
7035 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7036 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7037 as_warn (_("base register written back, and overlaps "
7038 "second destination register"));
7040 /* For an index-register load, the index register must not overlap the
7041 destination (even if not write-back). */
7042 else if (inst
.operands
[2].immisreg
7043 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7044 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7045 as_warn (_("index register overlaps destination register"));
7048 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7049 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7055 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7056 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7057 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7058 || inst
.operands
[1].negative
7059 /* This can arise if the programmer has written
7061 or if they have mistakenly used a register name as the last
7064 It is very difficult to distinguish between these two cases
7065 because "rX" might actually be a label. ie the register
7066 name has been occluded by a symbol of the same name. So we
7067 just generate a general 'bad addressing mode' type error
7068 message and leave it up to the programmer to discover the
7069 true cause and fix their mistake. */
7070 || (inst
.operands
[1].reg
== REG_PC
),
7073 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7074 || inst
.reloc
.exp
.X_add_number
!= 0,
7075 _("offset must be zero in ARM encoding"));
7077 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7078 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7079 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7085 constraint (inst
.operands
[0].reg
% 2 != 0,
7086 _("even register required"));
7087 constraint (inst
.operands
[1].present
7088 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7089 _("can only load two consecutive registers"));
7090 /* If op 1 were present and equal to PC, this function wouldn't
7091 have been called in the first place. */
7092 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7094 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7095 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7101 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7102 if (!inst
.operands
[1].isreg
)
7103 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7105 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7111 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7113 if (inst
.operands
[1].preind
)
7115 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7116 || inst
.reloc
.exp
.X_add_number
!= 0,
7117 _("this instruction requires a post-indexed address"));
7119 inst
.operands
[1].preind
= 0;
7120 inst
.operands
[1].postind
= 1;
7121 inst
.operands
[1].writeback
= 1;
7123 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7124 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7127 /* Halfword and signed-byte load/store operations. */
7132 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7133 if (!inst
.operands
[1].isreg
)
7134 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7136 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7142 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7144 if (inst
.operands
[1].preind
)
7146 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7147 || inst
.reloc
.exp
.X_add_number
!= 0,
7148 _("this instruction requires a post-indexed address"));
7150 inst
.operands
[1].preind
= 0;
7151 inst
.operands
[1].postind
= 1;
7152 inst
.operands
[1].writeback
= 1;
7154 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7155 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7158 /* Co-processor register load/store.
7159 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7163 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7164 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7165 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7171 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7172 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7173 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7174 && !(inst
.instruction
& 0x00400000))
7175 as_tsktsk (_("Rd and Rm should be different in mla"));
7177 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7178 inst
.instruction
|= inst
.operands
[1].reg
;
7179 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7180 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7186 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7187 encode_arm_shifter_operand (1);
7190 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7197 top
= (inst
.instruction
& 0x00400000) != 0;
7198 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7199 _(":lower16: not allowed this instruction"));
7200 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7201 _(":upper16: not allowed instruction"));
7202 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7203 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7205 imm
= inst
.reloc
.exp
.X_add_number
;
7206 /* The value is in two pieces: 0:11, 16:19. */
7207 inst
.instruction
|= (imm
& 0x00000fff);
7208 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7212 static void do_vfp_nsyn_opcode (const char *);
7215 do_vfp_nsyn_mrs (void)
7217 if (inst
.operands
[0].isvec
)
7219 if (inst
.operands
[1].reg
!= 1)
7220 first_error (_("operand 1 must be FPSCR"));
7221 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7222 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7223 do_vfp_nsyn_opcode ("fmstat");
7225 else if (inst
.operands
[1].isvec
)
7226 do_vfp_nsyn_opcode ("fmrx");
7234 do_vfp_nsyn_msr (void)
7236 if (inst
.operands
[0].isvec
)
7237 do_vfp_nsyn_opcode ("fmxr");
7247 if (do_vfp_nsyn_mrs () == SUCCESS
)
7250 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7251 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7253 _("'CPSR' or 'SPSR' expected"));
7254 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7255 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7258 /* Two possible forms:
7259 "{C|S}PSR_<field>, Rm",
7260 "{C|S}PSR_f, #expression". */
7265 if (do_vfp_nsyn_msr () == SUCCESS
)
7268 inst
.instruction
|= inst
.operands
[0].imm
;
7269 if (inst
.operands
[1].isreg
)
7270 inst
.instruction
|= inst
.operands
[1].reg
;
7273 inst
.instruction
|= INST_IMMEDIATE
;
7274 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7275 inst
.reloc
.pc_rel
= 0;
7282 if (!inst
.operands
[2].present
)
7283 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7284 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7285 inst
.instruction
|= inst
.operands
[1].reg
;
7286 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7288 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7289 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7290 as_tsktsk (_("Rd and Rm should be different in mul"));
7293 /* Long Multiply Parser
7294 UMULL RdLo, RdHi, Rm, Rs
7295 SMULL RdLo, RdHi, Rm, Rs
7296 UMLAL RdLo, RdHi, Rm, Rs
7297 SMLAL RdLo, RdHi, Rm, Rs. */
7302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7303 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7304 inst
.instruction
|= inst
.operands
[2].reg
;
7305 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7307 /* rdhi and rdlo must be different. */
7308 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7309 as_tsktsk (_("rdhi and rdlo must be different"));
7311 /* rdhi, rdlo and rm must all be different before armv6. */
7312 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7313 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7314 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7315 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7321 if (inst
.operands
[0].present
7322 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7324 /* Architectural NOP hints are CPSR sets with no bits selected. */
7325 inst
.instruction
&= 0xf0000000;
7326 inst
.instruction
|= 0x0320f000;
7327 if (inst
.operands
[0].present
)
7328 inst
.instruction
|= inst
.operands
[0].imm
;
7332 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7333 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7334 Condition defaults to COND_ALWAYS.
7335 Error if Rd, Rn or Rm are R15. */
7340 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7341 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7342 inst
.instruction
|= inst
.operands
[2].reg
;
7343 if (inst
.operands
[3].present
)
7344 encode_arm_shift (3);
7347 /* ARM V6 PKHTB (Argument Parse). */
7352 if (!inst
.operands
[3].present
)
7354 /* If the shift specifier is omitted, turn the instruction
7355 into pkhbt rd, rm, rn. */
7356 inst
.instruction
&= 0xfff00010;
7357 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7358 inst
.instruction
|= inst
.operands
[1].reg
;
7359 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7363 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7364 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7365 inst
.instruction
|= inst
.operands
[2].reg
;
7366 encode_arm_shift (3);
7370 /* ARMv5TE: Preload-Cache
7374 Syntactically, like LDR with B=1, W=0, L=1. */
7379 constraint (!inst
.operands
[0].isreg
,
7380 _("'[' expected after PLD mnemonic"));
7381 constraint (inst
.operands
[0].postind
,
7382 _("post-indexed expression used in preload instruction"));
7383 constraint (inst
.operands
[0].writeback
,
7384 _("writeback used in preload instruction"));
7385 constraint (!inst
.operands
[0].preind
,
7386 _("unindexed addressing used in preload instruction"));
7387 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7390 /* ARMv7: PLI <addr_mode> */
7394 constraint (!inst
.operands
[0].isreg
,
7395 _("'[' expected after PLI mnemonic"));
7396 constraint (inst
.operands
[0].postind
,
7397 _("post-indexed expression used in preload instruction"));
7398 constraint (inst
.operands
[0].writeback
,
7399 _("writeback used in preload instruction"));
7400 constraint (!inst
.operands
[0].preind
,
7401 _("unindexed addressing used in preload instruction"));
7402 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7403 inst
.instruction
&= ~PRE_INDEX
;
7409 inst
.operands
[1] = inst
.operands
[0];
7410 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7411 inst
.operands
[0].isreg
= 1;
7412 inst
.operands
[0].writeback
= 1;
7413 inst
.operands
[0].reg
= REG_SP
;
7417 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7418 word at the specified address and the following word
7420 Unconditionally executed.
7421 Error if Rn is R15. */
7426 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7427 if (inst
.operands
[0].writeback
)
7428 inst
.instruction
|= WRITE_BACK
;
7431 /* ARM V6 ssat (argument parse). */
7436 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7437 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7438 inst
.instruction
|= inst
.operands
[2].reg
;
7440 if (inst
.operands
[3].present
)
7441 encode_arm_shift (3);
7444 /* ARM V6 usat (argument parse). */
7449 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7450 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7451 inst
.instruction
|= inst
.operands
[2].reg
;
7453 if (inst
.operands
[3].present
)
7454 encode_arm_shift (3);
7457 /* ARM V6 ssat16 (argument parse). */
7462 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7463 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7464 inst
.instruction
|= inst
.operands
[2].reg
;
7470 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7471 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7472 inst
.instruction
|= inst
.operands
[2].reg
;
7475 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7476 preserving the other bits.
7478 setend <endian_specifier>, where <endian_specifier> is either
7484 if (inst
.operands
[0].imm
)
7485 inst
.instruction
|= 0x200;
7491 unsigned int Rm
= (inst
.operands
[1].present
7492 ? inst
.operands
[1].reg
7493 : inst
.operands
[0].reg
);
7495 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7496 inst
.instruction
|= Rm
;
7497 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7499 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7500 inst
.instruction
|= SHIFT_BY_REG
;
7503 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7509 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7510 inst
.reloc
.pc_rel
= 0;
7516 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7517 inst
.reloc
.pc_rel
= 0;
7520 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7521 SMLAxy{cond} Rd,Rm,Rs,Rn
7522 SMLAWy{cond} Rd,Rm,Rs,Rn
7523 Error if any register is R15. */
7528 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7529 inst
.instruction
|= inst
.operands
[1].reg
;
7530 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7531 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7534 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7535 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7536 Error if any register is R15.
7537 Warning if Rdlo == Rdhi. */
7542 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7543 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7544 inst
.instruction
|= inst
.operands
[2].reg
;
7545 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7547 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7548 as_tsktsk (_("rdhi and rdlo must be different"));
7551 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7552 SMULxy{cond} Rd,Rm,Rs
7553 Error if any register is R15. */
7558 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7559 inst
.instruction
|= inst
.operands
[1].reg
;
7560 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7563 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7564 the same for both ARM and Thumb-2. */
7571 if (inst
.operands
[0].present
)
7573 reg
= inst
.operands
[0].reg
;
7574 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
7579 inst
.instruction
|= reg
<< 16;
7580 inst
.instruction
|= inst
.operands
[1].imm
;
7581 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7582 inst
.instruction
|= WRITE_BACK
;
7585 /* ARM V6 strex (argument parse). */
7590 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7591 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7592 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7593 || inst
.operands
[2].negative
7594 /* See comment in do_ldrex(). */
7595 || (inst
.operands
[2].reg
== REG_PC
),
7598 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7599 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7601 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7602 || inst
.reloc
.exp
.X_add_number
!= 0,
7603 _("offset must be zero in ARM encoding"));
7605 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7606 inst
.instruction
|= inst
.operands
[1].reg
;
7607 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7608 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7614 constraint (inst
.operands
[1].reg
% 2 != 0,
7615 _("even register required"));
7616 constraint (inst
.operands
[2].present
7617 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7618 _("can only store two consecutive registers"));
7619 /* If op 2 were present and equal to PC, this function wouldn't
7620 have been called in the first place. */
7621 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7623 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7624 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7625 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7628 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7629 inst
.instruction
|= inst
.operands
[1].reg
;
7630 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7633 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7634 extends it to 32-bits, and adds the result to a value in another
7635 register. You can specify a rotation by 0, 8, 16, or 24 bits
7636 before extracting the 16-bit value.
7637 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7638 Condition defaults to COND_ALWAYS.
7639 Error if any register uses R15. */
7644 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7645 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7646 inst
.instruction
|= inst
.operands
[2].reg
;
7647 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7652 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7653 Condition defaults to COND_ALWAYS.
7654 Error if any register uses R15. */
7659 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7660 inst
.instruction
|= inst
.operands
[1].reg
;
7661 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7664 /* VFP instructions. In a logical order: SP variant first, monad
7665 before dyad, arithmetic then move then load/store. */
7668 do_vfp_sp_monadic (void)
7670 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7671 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7675 do_vfp_sp_dyadic (void)
7677 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7678 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7679 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7683 do_vfp_sp_compare_z (void)
7685 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7689 do_vfp_dp_sp_cvt (void)
7691 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7692 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7696 do_vfp_sp_dp_cvt (void)
7698 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7699 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7703 do_vfp_reg_from_sp (void)
7705 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7706 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7710 do_vfp_reg2_from_sp2 (void)
7712 constraint (inst
.operands
[2].imm
!= 2,
7713 _("only two consecutive VFP SP registers allowed here"));
7714 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7715 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7716 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7720 do_vfp_sp_from_reg (void)
7722 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7723 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7727 do_vfp_sp2_from_reg2 (void)
7729 constraint (inst
.operands
[0].imm
!= 2,
7730 _("only two consecutive VFP SP registers allowed here"));
7731 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7732 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7733 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7737 do_vfp_sp_ldst (void)
7739 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7740 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7744 do_vfp_dp_ldst (void)
7746 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7747 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7752 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7754 if (inst
.operands
[0].writeback
)
7755 inst
.instruction
|= WRITE_BACK
;
7757 constraint (ldstm_type
!= VFP_LDSTMIA
,
7758 _("this addressing mode requires base-register writeback"));
7759 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7760 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7761 inst
.instruction
|= inst
.operands
[1].imm
;
7765 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7769 if (inst
.operands
[0].writeback
)
7770 inst
.instruction
|= WRITE_BACK
;
7772 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7773 _("this addressing mode requires base-register writeback"));
7775 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7776 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7778 count
= inst
.operands
[1].imm
<< 1;
7779 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7782 inst
.instruction
|= count
;
7786 do_vfp_sp_ldstmia (void)
7788 vfp_sp_ldstm (VFP_LDSTMIA
);
7792 do_vfp_sp_ldstmdb (void)
7794 vfp_sp_ldstm (VFP_LDSTMDB
);
7798 do_vfp_dp_ldstmia (void)
7800 vfp_dp_ldstm (VFP_LDSTMIA
);
7804 do_vfp_dp_ldstmdb (void)
7806 vfp_dp_ldstm (VFP_LDSTMDB
);
7810 do_vfp_xp_ldstmia (void)
7812 vfp_dp_ldstm (VFP_LDSTMIAX
);
7816 do_vfp_xp_ldstmdb (void)
7818 vfp_dp_ldstm (VFP_LDSTMDBX
);
7822 do_vfp_dp_rd_rm (void)
7824 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7825 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7829 do_vfp_dp_rn_rd (void)
7831 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7832 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7836 do_vfp_dp_rd_rn (void)
7838 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7839 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7843 do_vfp_dp_rd_rn_rm (void)
7845 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7846 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7847 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7853 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7857 do_vfp_dp_rm_rd_rn (void)
7859 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7860 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7861 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7864 /* VFPv3 instructions. */
7866 do_vfp_sp_const (void)
7868 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7869 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7870 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7874 do_vfp_dp_const (void)
7876 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7877 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7878 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7882 vfp_conv (int srcsize
)
7884 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7885 inst
.instruction
|= (immbits
& 1) << 5;
7886 inst
.instruction
|= (immbits
>> 1);
7890 do_vfp_sp_conv_16 (void)
7892 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7897 do_vfp_dp_conv_16 (void)
7899 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7904 do_vfp_sp_conv_32 (void)
7906 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7911 do_vfp_dp_conv_32 (void)
7913 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7917 /* FPA instructions. Also in a logical order. */
7922 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7923 inst
.instruction
|= inst
.operands
[1].reg
;
7927 do_fpa_ldmstm (void)
7929 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7930 switch (inst
.operands
[1].imm
)
7932 case 1: inst
.instruction
|= CP_T_X
; break;
7933 case 2: inst
.instruction
|= CP_T_Y
; break;
7934 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7939 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7941 /* The instruction specified "ea" or "fd", so we can only accept
7942 [Rn]{!}. The instruction does not really support stacking or
7943 unstacking, so we have to emulate these by setting appropriate
7944 bits and offsets. */
7945 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7946 || inst
.reloc
.exp
.X_add_number
!= 0,
7947 _("this instruction does not support indexing"));
7949 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7950 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7952 if (!(inst
.instruction
& INDEX_UP
))
7953 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7955 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7957 inst
.operands
[2].preind
= 0;
7958 inst
.operands
[2].postind
= 1;
7962 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7965 /* iWMMXt instructions: strictly in alphabetical order. */
7968 do_iwmmxt_tandorc (void)
7970 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7974 do_iwmmxt_textrc (void)
7976 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7977 inst
.instruction
|= inst
.operands
[1].imm
;
7981 do_iwmmxt_textrm (void)
7983 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7984 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7985 inst
.instruction
|= inst
.operands
[2].imm
;
7989 do_iwmmxt_tinsr (void)
7991 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7992 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7993 inst
.instruction
|= inst
.operands
[2].imm
;
7997 do_iwmmxt_tmia (void)
7999 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8000 inst
.instruction
|= inst
.operands
[1].reg
;
8001 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8005 do_iwmmxt_waligni (void)
8007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8008 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8009 inst
.instruction
|= inst
.operands
[2].reg
;
8010 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8014 do_iwmmxt_wmerge (void)
8016 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8017 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8018 inst
.instruction
|= inst
.operands
[2].reg
;
8019 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8023 do_iwmmxt_wmov (void)
8025 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8026 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8027 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8028 inst
.instruction
|= inst
.operands
[1].reg
;
8032 do_iwmmxt_wldstbh (void)
8035 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8037 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8039 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8040 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8044 do_iwmmxt_wldstw (void)
8046 /* RIWR_RIWC clears .isreg for a control register. */
8047 if (!inst
.operands
[0].isreg
)
8049 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8050 inst
.instruction
|= 0xf0000000;
8053 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8054 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8058 do_iwmmxt_wldstd (void)
8060 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8061 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8062 && inst
.operands
[1].immisreg
)
8064 inst
.instruction
&= ~0x1a000ff;
8065 inst
.instruction
|= (0xf << 28);
8066 if (inst
.operands
[1].preind
)
8067 inst
.instruction
|= PRE_INDEX
;
8068 if (!inst
.operands
[1].negative
)
8069 inst
.instruction
|= INDEX_UP
;
8070 if (inst
.operands
[1].writeback
)
8071 inst
.instruction
|= WRITE_BACK
;
8072 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8073 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8074 inst
.instruction
|= inst
.operands
[1].imm
;
8077 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8081 do_iwmmxt_wshufh (void)
8083 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8084 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8085 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8086 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8090 do_iwmmxt_wzero (void)
8092 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8093 inst
.instruction
|= inst
.operands
[0].reg
;
8094 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8095 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8099 do_iwmmxt_wrwrwr_or_imm5 (void)
8101 if (inst
.operands
[2].isreg
)
8104 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8105 _("immediate operand requires iWMMXt2"));
8107 if (inst
.operands
[2].imm
== 0)
8109 switch ((inst
.instruction
>> 20) & 0xf)
8115 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8116 inst
.operands
[2].imm
= 16;
8117 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8123 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8124 inst
.operands
[2].imm
= 32;
8125 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8132 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8134 wrn
= (inst
.instruction
>> 16) & 0xf;
8135 inst
.instruction
&= 0xff0fff0f;
8136 inst
.instruction
|= wrn
;
8137 /* Bail out here; the instruction is now assembled. */
8142 /* Map 32 -> 0, etc. */
8143 inst
.operands
[2].imm
&= 0x1f;
8144 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8148 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8149 operations first, then control, shift, and load/store. */
8151 /* Insns like "foo X,Y,Z". */
8154 do_mav_triple (void)
8156 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8157 inst
.instruction
|= inst
.operands
[1].reg
;
8158 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8161 /* Insns like "foo W,X,Y,Z".
8162 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8167 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8168 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8169 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8170 inst
.instruction
|= inst
.operands
[3].reg
;
8173 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8177 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8180 /* Maverick shift immediate instructions.
8181 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8182 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8187 int imm
= inst
.operands
[2].imm
;
8189 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8190 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8192 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8193 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8194 Bit 4 should be 0. */
8195 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8197 inst
.instruction
|= imm
;
8200 /* XScale instructions. Also sorted arithmetic before move. */
8202 /* Xscale multiply-accumulate (argument parse)
8205 MIAxycc acc0,Rm,Rs. */
8210 inst
.instruction
|= inst
.operands
[1].reg
;
8211 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8214 /* Xscale move-accumulator-register (argument parse)
8216 MARcc acc0,RdLo,RdHi. */
8221 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8222 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8225 /* Xscale move-register-accumulator (argument parse)
8227 MRAcc RdLo,RdHi,acc0. */
8232 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8233 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8234 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8237 /* Encoding functions relevant only to Thumb. */
8239 /* inst.operands[i] is a shifted-register operand; encode
8240 it into inst.instruction in the format used by Thumb32. */
8243 encode_thumb32_shifted_operand (int i
)
8245 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8246 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8248 constraint (inst
.operands
[i
].immisreg
,
8249 _("shift by register not allowed in thumb mode"));
8250 inst
.instruction
|= inst
.operands
[i
].reg
;
8251 if (shift
== SHIFT_RRX
)
8252 inst
.instruction
|= SHIFT_ROR
<< 4;
8255 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8256 _("expression too complex"));
8258 constraint (value
> 32
8259 || (value
== 32 && (shift
== SHIFT_LSL
8260 || shift
== SHIFT_ROR
)),
8261 _("shift expression is too large"));
8265 else if (value
== 32)
8268 inst
.instruction
|= shift
<< 4;
8269 inst
.instruction
|= (value
& 0x1c) << 10;
8270 inst
.instruction
|= (value
& 0x03) << 6;
8275 /* inst.operands[i] was set up by parse_address. Encode it into a
8276 Thumb32 format load or store instruction. Reject forms that cannot
8277 be used with such instructions. If is_t is true, reject forms that
8278 cannot be used with a T instruction; if is_d is true, reject forms
8279 that cannot be used with a D instruction. */
8282 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8284 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8286 constraint (!inst
.operands
[i
].isreg
,
8287 _("Instruction does not support =N addresses"));
8289 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8290 if (inst
.operands
[i
].immisreg
)
8292 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8293 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8294 constraint (inst
.operands
[i
].negative
,
8295 _("Thumb does not support negative register indexing"));
8296 constraint (inst
.operands
[i
].postind
,
8297 _("Thumb does not support register post-indexing"));
8298 constraint (inst
.operands
[i
].writeback
,
8299 _("Thumb does not support register indexing with writeback"));
8300 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8301 _("Thumb supports only LSL in shifted register indexing"));
8303 inst
.instruction
|= inst
.operands
[i
].imm
;
8304 if (inst
.operands
[i
].shifted
)
8306 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8307 _("expression too complex"));
8308 constraint (inst
.reloc
.exp
.X_add_number
< 0
8309 || inst
.reloc
.exp
.X_add_number
> 3,
8310 _("shift out of range"));
8311 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8313 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8315 else if (inst
.operands
[i
].preind
)
8317 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8318 _("cannot use writeback with PC-relative addressing"));
8319 constraint (is_t
&& inst
.operands
[i
].writeback
,
8320 _("cannot use writeback with this instruction"));
8324 inst
.instruction
|= 0x01000000;
8325 if (inst
.operands
[i
].writeback
)
8326 inst
.instruction
|= 0x00200000;
8330 inst
.instruction
|= 0x00000c00;
8331 if (inst
.operands
[i
].writeback
)
8332 inst
.instruction
|= 0x00000100;
8334 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8336 else if (inst
.operands
[i
].postind
)
8338 assert (inst
.operands
[i
].writeback
);
8339 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8340 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8343 inst
.instruction
|= 0x00200000;
8345 inst
.instruction
|= 0x00000900;
8346 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8348 else /* unindexed - only for coprocessor */
8349 inst
.error
= _("instruction does not accept unindexed addressing");
8352 /* Table of Thumb instructions which exist in both 16- and 32-bit
8353 encodings (the latter only in post-V6T2 cores). The index is the
8354 value used in the insns table below. When there is more than one
8355 possible 16-bit encoding for the instruction, this table always
8357 Also contains several pseudo-instructions used during relaxation. */
8358 #define T16_32_TAB \
8359 X(adc, 4140, eb400000), \
8360 X(adcs, 4140, eb500000), \
8361 X(add, 1c00, eb000000), \
8362 X(adds, 1c00, eb100000), \
8363 X(addi, 0000, f1000000), \
8364 X(addis, 0000, f1100000), \
8365 X(add_pc,000f, f20f0000), \
8366 X(add_sp,000d, f10d0000), \
8367 X(adr, 000f, f20f0000), \
8368 X(and, 4000, ea000000), \
8369 X(ands, 4000, ea100000), \
8370 X(asr, 1000, fa40f000), \
8371 X(asrs, 1000, fa50f000), \
8372 X(b, e000, f000b000), \
8373 X(bcond, d000, f0008000), \
8374 X(bic, 4380, ea200000), \
8375 X(bics, 4380, ea300000), \
8376 X(cmn, 42c0, eb100f00), \
8377 X(cmp, 2800, ebb00f00), \
8378 X(cpsie, b660, f3af8400), \
8379 X(cpsid, b670, f3af8600), \
8380 X(cpy, 4600, ea4f0000), \
8381 X(dec_sp,80dd, f1ad0d00), \
8382 X(eor, 4040, ea800000), \
8383 X(eors, 4040, ea900000), \
8384 X(inc_sp,00dd, f10d0d00), \
8385 X(ldmia, c800, e8900000), \
8386 X(ldr, 6800, f8500000), \
8387 X(ldrb, 7800, f8100000), \
8388 X(ldrh, 8800, f8300000), \
8389 X(ldrsb, 5600, f9100000), \
8390 X(ldrsh, 5e00, f9300000), \
8391 X(ldr_pc,4800, f85f0000), \
8392 X(ldr_pc2,4800, f85f0000), \
8393 X(ldr_sp,9800, f85d0000), \
8394 X(lsl, 0000, fa00f000), \
8395 X(lsls, 0000, fa10f000), \
8396 X(lsr, 0800, fa20f000), \
8397 X(lsrs, 0800, fa30f000), \
8398 X(mov, 2000, ea4f0000), \
8399 X(movs, 2000, ea5f0000), \
8400 X(mul, 4340, fb00f000), \
8401 X(muls, 4340, ffffffff), /* no 32b muls */ \
8402 X(mvn, 43c0, ea6f0000), \
8403 X(mvns, 43c0, ea7f0000), \
8404 X(neg, 4240, f1c00000), /* rsb #0 */ \
8405 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8406 X(orr, 4300, ea400000), \
8407 X(orrs, 4300, ea500000), \
8408 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8409 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8410 X(rev, ba00, fa90f080), \
8411 X(rev16, ba40, fa90f090), \
8412 X(revsh, bac0, fa90f0b0), \
8413 X(ror, 41c0, fa60f000), \
8414 X(rors, 41c0, fa70f000), \
8415 X(sbc, 4180, eb600000), \
8416 X(sbcs, 4180, eb700000), \
8417 X(stmia, c000, e8800000), \
8418 X(str, 6000, f8400000), \
8419 X(strb, 7000, f8000000), \
8420 X(strh, 8000, f8200000), \
8421 X(str_sp,9000, f84d0000), \
8422 X(sub, 1e00, eba00000), \
8423 X(subs, 1e00, ebb00000), \
8424 X(subi, 8000, f1a00000), \
8425 X(subis, 8000, f1b00000), \
8426 X(sxtb, b240, fa4ff080), \
8427 X(sxth, b200, fa0ff080), \
8428 X(tst, 4200, ea100f00), \
8429 X(uxtb, b2c0, fa5ff080), \
8430 X(uxth, b280, fa1ff080), \
8431 X(nop, bf00, f3af8000), \
8432 X(yield, bf10, f3af8001), \
8433 X(wfe, bf20, f3af8002), \
8434 X(wfi, bf30, f3af8003), \
8435 X(sev, bf40, f3af9004), /* typo, 8004? */
8437 /* To catch errors in encoding functions, the codes are all offset by
8438 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8439 as 16-bit instructions. */
8440 #define X(a,b,c) T_MNEM_##a
8441 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8444 #define X(a,b,c) 0x##b
8445 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8446 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8449 #define X(a,b,c) 0x##c
8450 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8451 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8452 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8456 /* Thumb instruction encoders, in alphabetical order. */
8460 do_t_add_sub_w (void)
8464 Rd
= inst
.operands
[0].reg
;
8465 Rn
= inst
.operands
[1].reg
;
8467 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this is the
8468 SP-{plus,minute}-immediate form of the instruction. */
8469 reject_bad_reg (Rd
);
8471 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8472 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8475 /* Parse an add or subtract instruction. We get here with inst.instruction
8476 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8483 Rd
= inst
.operands
[0].reg
;
8484 Rs
= (inst
.operands
[1].present
8485 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8486 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8494 flags
= (inst
.instruction
== T_MNEM_adds
8495 || inst
.instruction
== T_MNEM_subs
);
8497 narrow
= (current_it_mask
== 0);
8499 narrow
= (current_it_mask
!= 0);
8500 if (!inst
.operands
[2].isreg
)
8504 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8506 add
= (inst
.instruction
== T_MNEM_add
8507 || inst
.instruction
== T_MNEM_adds
);
8509 if (inst
.size_req
!= 4)
8511 /* Attempt to use a narrow opcode, with relaxation if
8513 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8514 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8515 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8516 opcode
= T_MNEM_add_sp
;
8517 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8518 opcode
= T_MNEM_add_pc
;
8519 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8522 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8524 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8528 inst
.instruction
= THUMB_OP16(opcode
);
8529 inst
.instruction
|= (Rd
<< 4) | Rs
;
8530 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8531 if (inst
.size_req
!= 2)
8532 inst
.relax
= opcode
;
8535 constraint (inst
.size_req
== 2, BAD_HIREG
);
8537 if (inst
.size_req
== 4
8538 || (inst
.size_req
!= 2 && !opcode
))
8542 constraint (add
, BAD_PC
);
8543 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8544 _("only SUBS PC, LR, #const allowed"));
8545 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8546 _("expression too complex"));
8547 constraint (inst
.reloc
.exp
.X_add_number
< 0
8548 || inst
.reloc
.exp
.X_add_number
> 0xff,
8549 _("immediate value out of range"));
8550 inst
.instruction
= T2_SUBS_PC_LR
8551 | inst
.reloc
.exp
.X_add_number
;
8552 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8555 else if (Rs
== REG_PC
)
8557 /* Always use addw/subw. */
8558 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8559 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8563 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8564 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8567 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8569 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8571 inst
.instruction
|= Rd
<< 8;
8572 inst
.instruction
|= Rs
<< 16;
8577 Rn
= inst
.operands
[2].reg
;
8578 /* See if we can do this with a 16-bit instruction. */
8579 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8581 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8586 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8587 || inst
.instruction
== T_MNEM_add
)
8590 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8594 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
8596 /* Thumb-1 cores (except v6-M) require at least one high
8597 register in a narrow non flag setting add. */
8598 if (Rd
> 7 || Rn
> 7
8599 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
8600 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
8607 inst
.instruction
= T_OPCODE_ADD_HI
;
8608 inst
.instruction
|= (Rd
& 8) << 4;
8609 inst
.instruction
|= (Rd
& 7);
8610 inst
.instruction
|= Rn
<< 3;
8616 constraint (Rd
== REG_PC
, BAD_PC
);
8617 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8618 constraint (Rs
== REG_PC
, BAD_PC
);
8619 reject_bad_reg (Rn
);
8621 /* If we get here, it can't be done in 16 bits. */
8622 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8623 _("shift must be constant"));
8624 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8625 inst
.instruction
|= Rd
<< 8;
8626 inst
.instruction
|= Rs
<< 16;
8627 encode_thumb32_shifted_operand (2);
8632 constraint (inst
.instruction
== T_MNEM_adds
8633 || inst
.instruction
== T_MNEM_subs
,
8636 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8638 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8639 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8642 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8644 inst
.instruction
|= (Rd
<< 4) | Rs
;
8645 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8649 Rn
= inst
.operands
[2].reg
;
8650 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8652 /* We now have Rd, Rs, and Rn set to registers. */
8653 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8655 /* Can't do this for SUB. */
8656 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8657 inst
.instruction
= T_OPCODE_ADD_HI
;
8658 inst
.instruction
|= (Rd
& 8) << 4;
8659 inst
.instruction
|= (Rd
& 7);
8661 inst
.instruction
|= Rn
<< 3;
8663 inst
.instruction
|= Rs
<< 3;
8665 constraint (1, _("dest must overlap one source register"));
8669 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8670 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8671 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8681 Rd
= inst
.operands
[0].reg
;
8682 reject_bad_reg (Rd
);
8684 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
8686 /* Defer to section relaxation. */
8687 inst
.relax
= inst
.instruction
;
8688 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8689 inst
.instruction
|= Rd
<< 4;
8691 else if (unified_syntax
&& inst
.size_req
!= 2)
8693 /* Generate a 32-bit opcode. */
8694 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8695 inst
.instruction
|= Rd
<< 8;
8696 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8697 inst
.reloc
.pc_rel
= 1;
8701 /* Generate a 16-bit opcode. */
8702 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8703 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8704 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8705 inst
.reloc
.pc_rel
= 1;
8707 inst
.instruction
|= Rd
<< 4;
8711 /* Arithmetic instructions for which there is just one 16-bit
8712 instruction encoding, and it allows only two low registers.
8713 For maximal compatibility with ARM syntax, we allow three register
8714 operands even when Thumb-32 instructions are not available, as long
8715 as the first two are identical. For instance, both "sbc r0,r1" and
8716 "sbc r0,r0,r1" are allowed. */
8722 Rd
= inst
.operands
[0].reg
;
8723 Rs
= (inst
.operands
[1].present
8724 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8725 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8726 Rn
= inst
.operands
[2].reg
;
8728 reject_bad_reg (Rd
);
8729 reject_bad_reg (Rs
);
8730 if (inst
.operands
[2].isreg
)
8731 reject_bad_reg (Rn
);
8735 if (!inst
.operands
[2].isreg
)
8737 /* For an immediate, we always generate a 32-bit opcode;
8738 section relaxation will shrink it later if possible. */
8739 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8740 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8741 inst
.instruction
|= Rd
<< 8;
8742 inst
.instruction
|= Rs
<< 16;
8743 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8749 /* See if we can do this with a 16-bit instruction. */
8750 if (THUMB_SETS_FLAGS (inst
.instruction
))
8751 narrow
= current_it_mask
== 0;
8753 narrow
= current_it_mask
!= 0;
8755 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8757 if (inst
.operands
[2].shifted
)
8759 if (inst
.size_req
== 4)
8765 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8766 inst
.instruction
|= Rd
;
8767 inst
.instruction
|= Rn
<< 3;
8771 /* If we get here, it can't be done in 16 bits. */
8772 constraint (inst
.operands
[2].shifted
8773 && inst
.operands
[2].immisreg
,
8774 _("shift must be constant"));
8775 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8776 inst
.instruction
|= Rd
<< 8;
8777 inst
.instruction
|= Rs
<< 16;
8778 encode_thumb32_shifted_operand (2);
8783 /* On its face this is a lie - the instruction does set the
8784 flags. However, the only supported mnemonic in this mode
8786 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8788 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8789 _("unshifted register required"));
8790 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8791 constraint (Rd
!= Rs
,
8792 _("dest and source1 must be the same register"));
8794 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8795 inst
.instruction
|= Rd
;
8796 inst
.instruction
|= Rn
<< 3;
8800 /* Similarly, but for instructions where the arithmetic operation is
8801 commutative, so we can allow either of them to be different from
8802 the destination operand in a 16-bit instruction. For instance, all
8803 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8810 Rd
= inst
.operands
[0].reg
;
8811 Rs
= (inst
.operands
[1].present
8812 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8813 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8814 Rn
= inst
.operands
[2].reg
;
8816 reject_bad_reg (Rd
);
8817 reject_bad_reg (Rs
);
8818 if (inst
.operands
[2].isreg
)
8819 reject_bad_reg (Rn
);
8823 if (!inst
.operands
[2].isreg
)
8825 /* For an immediate, we always generate a 32-bit opcode;
8826 section relaxation will shrink it later if possible. */
8827 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8828 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8829 inst
.instruction
|= Rd
<< 8;
8830 inst
.instruction
|= Rs
<< 16;
8831 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8837 /* See if we can do this with a 16-bit instruction. */
8838 if (THUMB_SETS_FLAGS (inst
.instruction
))
8839 narrow
= current_it_mask
== 0;
8841 narrow
= current_it_mask
!= 0;
8843 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8845 if (inst
.operands
[2].shifted
)
8847 if (inst
.size_req
== 4)
8854 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8855 inst
.instruction
|= Rd
;
8856 inst
.instruction
|= Rn
<< 3;
8861 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8862 inst
.instruction
|= Rd
;
8863 inst
.instruction
|= Rs
<< 3;
8868 /* If we get here, it can't be done in 16 bits. */
8869 constraint (inst
.operands
[2].shifted
8870 && inst
.operands
[2].immisreg
,
8871 _("shift must be constant"));
8872 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8873 inst
.instruction
|= Rd
<< 8;
8874 inst
.instruction
|= Rs
<< 16;
8875 encode_thumb32_shifted_operand (2);
8880 /* On its face this is a lie - the instruction does set the
8881 flags. However, the only supported mnemonic in this mode
8883 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8885 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8886 _("unshifted register required"));
8887 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8889 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8890 inst
.instruction
|= Rd
;
8893 inst
.instruction
|= Rn
<< 3;
8895 inst
.instruction
|= Rs
<< 3;
8897 constraint (1, _("dest must overlap one source register"));
8904 if (inst
.operands
[0].present
)
8906 constraint ((inst
.instruction
& 0xf0) != 0x40
8907 && inst
.operands
[0].imm
!= 0xf,
8908 _("bad barrier type"));
8909 inst
.instruction
|= inst
.operands
[0].imm
;
8912 inst
.instruction
|= 0xf;
8919 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8920 constraint (msb
> 32, _("bit-field extends past end of register"));
8921 /* The instruction encoding stores the LSB and MSB,
8922 not the LSB and width. */
8923 Rd
= inst
.operands
[0].reg
;
8924 reject_bad_reg (Rd
);
8925 inst
.instruction
|= Rd
<< 8;
8926 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8927 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8928 inst
.instruction
|= msb
- 1;
8937 Rd
= inst
.operands
[0].reg
;
8938 reject_bad_reg (Rd
);
8940 /* #0 in second position is alternative syntax for bfc, which is
8941 the same instruction but with REG_PC in the Rm field. */
8942 if (!inst
.operands
[1].isreg
)
8946 Rn
= inst
.operands
[1].reg
;
8947 reject_bad_reg (Rn
);
8950 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8951 constraint (msb
> 32, _("bit-field extends past end of register"));
8952 /* The instruction encoding stores the LSB and MSB,
8953 not the LSB and width. */
8954 inst
.instruction
|= Rd
<< 8;
8955 inst
.instruction
|= Rn
<< 16;
8956 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8957 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8958 inst
.instruction
|= msb
- 1;
8966 Rd
= inst
.operands
[0].reg
;
8967 Rn
= inst
.operands
[1].reg
;
8969 reject_bad_reg (Rd
);
8970 reject_bad_reg (Rn
);
8972 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8973 _("bit-field extends past end of register"));
8974 inst
.instruction
|= Rd
<< 8;
8975 inst
.instruction
|= Rn
<< 16;
8976 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8977 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8978 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8981 /* ARM V5 Thumb BLX (argument parse)
8982 BLX <target_addr> which is BLX(1)
8983 BLX <Rm> which is BLX(2)
8984 Unfortunately, there are two different opcodes for this mnemonic.
8985 So, the insns[].value is not used, and the code here zaps values
8986 into inst.instruction.
8988 ??? How to take advantage of the additional two bits of displacement
8989 available in Thumb32 mode? Need new relocation? */
8994 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8995 if (inst
.operands
[0].isreg
)
8997 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8998 /* We have a register, so this is BLX(2). */
8999 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9003 /* No register. This must be BLX(1). */
9004 inst
.instruction
= 0xf000e800;
9005 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9006 inst
.reloc
.pc_rel
= 1;
9016 if (current_it_mask
)
9018 /* Conditional branches inside IT blocks are encoded as unconditional
9021 /* A branch must be the last instruction in an IT block. */
9022 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
9027 if (cond
!= COND_ALWAYS
)
9028 opcode
= T_MNEM_bcond
;
9030 opcode
= inst
.instruction
;
9032 if (unified_syntax
&& inst
.size_req
== 4)
9034 inst
.instruction
= THUMB_OP32(opcode
);
9035 if (cond
== COND_ALWAYS
)
9036 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9039 assert (cond
!= 0xF);
9040 inst
.instruction
|= cond
<< 22;
9041 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9046 inst
.instruction
= THUMB_OP16(opcode
);
9047 if (cond
== COND_ALWAYS
)
9048 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9051 inst
.instruction
|= cond
<< 8;
9052 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9054 /* Allow section relaxation. */
9055 if (unified_syntax
&& inst
.size_req
!= 2)
9056 inst
.relax
= opcode
;
9059 inst
.reloc
.pc_rel
= 1;
9065 constraint (inst
.cond
!= COND_ALWAYS
,
9066 _("instruction is always unconditional"));
9067 if (inst
.operands
[0].present
)
9069 constraint (inst
.operands
[0].imm
> 255,
9070 _("immediate value out of range"));
9071 inst
.instruction
|= inst
.operands
[0].imm
;
9076 do_t_branch23 (void)
9078 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
9079 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9080 inst
.reloc
.pc_rel
= 1;
9082 #if defined(OBJ_COFF)
9083 /* If the destination of the branch is a defined symbol which does not have
9084 the THUMB_FUNC attribute, then we must be calling a function which has
9085 the (interfacearm) attribute. We look for the Thumb entry point to that
9086 function and change the branch to refer to that function instead. */
9087 if ( inst
.reloc
.exp
.X_op
== O_symbol
9088 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9089 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9090 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9091 inst
.reloc
.exp
.X_add_symbol
=
9092 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9099 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
9100 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9101 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9102 should cause the alignment to be checked once it is known. This is
9103 because BX PC only works if the instruction is word aligned. */
9111 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
9112 Rm
= inst
.operands
[0].reg
;
9113 reject_bad_reg (Rm
);
9114 inst
.instruction
|= Rm
<< 16;
9123 Rd
= inst
.operands
[0].reg
;
9124 Rm
= inst
.operands
[1].reg
;
9126 reject_bad_reg (Rd
);
9127 reject_bad_reg (Rm
);
9129 inst
.instruction
|= Rd
<< 8;
9130 inst
.instruction
|= Rm
<< 16;
9131 inst
.instruction
|= Rm
;
9137 constraint (current_it_mask
, BAD_NOT_IT
);
9138 inst
.instruction
|= inst
.operands
[0].imm
;
9144 constraint (current_it_mask
, BAD_NOT_IT
);
9146 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9147 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9149 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9150 inst
.instruction
= 0xf3af8000;
9151 inst
.instruction
|= imod
<< 9;
9152 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9153 if (inst
.operands
[1].present
)
9154 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9158 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9159 && (inst
.operands
[0].imm
& 4),
9160 _("selected processor does not support 'A' form "
9161 "of this instruction"));
9162 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9163 _("Thumb does not support the 2-argument "
9164 "form of this instruction"));
9165 inst
.instruction
|= inst
.operands
[0].imm
;
9169 /* THUMB CPY instruction (argument parse). */
9174 if (inst
.size_req
== 4)
9176 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9177 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9178 inst
.instruction
|= inst
.operands
[1].reg
;
9182 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9183 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9184 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9191 constraint (current_it_mask
, BAD_NOT_IT
);
9192 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9193 inst
.instruction
|= inst
.operands
[0].reg
;
9194 inst
.reloc
.pc_rel
= 1;
9195 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9201 inst
.instruction
|= inst
.operands
[0].imm
;
9207 unsigned Rd
, Rn
, Rm
;
9209 Rd
= inst
.operands
[0].reg
;
9210 Rn
= (inst
.operands
[1].present
9211 ? inst
.operands
[1].reg
: Rd
);
9212 Rm
= inst
.operands
[2].reg
;
9214 reject_bad_reg (Rd
);
9215 reject_bad_reg (Rn
);
9216 reject_bad_reg (Rm
);
9218 inst
.instruction
|= Rd
<< 8;
9219 inst
.instruction
|= Rn
<< 16;
9220 inst
.instruction
|= Rm
;
9226 if (unified_syntax
&& inst
.size_req
== 4)
9227 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9229 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9235 unsigned int cond
= inst
.operands
[0].imm
;
9237 constraint (current_it_mask
, BAD_NOT_IT
);
9238 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9241 /* If the condition is a negative condition, invert the mask. */
9242 if ((cond
& 0x1) == 0x0)
9244 unsigned int mask
= inst
.instruction
& 0x000f;
9246 if ((mask
& 0x7) == 0)
9247 /* no conversion needed */;
9248 else if ((mask
& 0x3) == 0)
9250 else if ((mask
& 0x1) == 0)
9255 inst
.instruction
&= 0xfff0;
9256 inst
.instruction
|= mask
;
9259 inst
.instruction
|= cond
<< 4;
9262 /* Helper function used for both push/pop and ldm/stm. */
9264 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9268 load
= (inst
.instruction
& (1 << 20)) != 0;
9270 if (mask
& (1 << 13))
9271 inst
.error
= _("SP not allowed in register list");
9274 if (mask
& (1 << 14)
9275 && mask
& (1 << 15))
9276 inst
.error
= _("LR and PC should not both be in register list");
9278 if ((mask
& (1 << base
)) != 0
9280 as_warn (_("base register should not be in register list "
9281 "when written back"));
9285 if (mask
& (1 << 15))
9286 inst
.error
= _("PC not allowed in register list");
9288 if (mask
& (1 << base
))
9289 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9292 if ((mask
& (mask
- 1)) == 0)
9294 /* Single register transfers implemented as str/ldr. */
9297 if (inst
.instruction
& (1 << 23))
9298 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9300 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9304 if (inst
.instruction
& (1 << 23))
9305 inst
.instruction
= 0x00800000; /* ia -> [base] */
9307 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9310 inst
.instruction
|= 0xf8400000;
9312 inst
.instruction
|= 0x00100000;
9314 mask
= ffs (mask
) - 1;
9318 inst
.instruction
|= WRITE_BACK
;
9320 inst
.instruction
|= mask
;
9321 inst
.instruction
|= base
<< 16;
9327 /* This really doesn't seem worth it. */
9328 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9329 _("expression too complex"));
9330 constraint (inst
.operands
[1].writeback
,
9331 _("Thumb load/store multiple does not support {reglist}^"));
9339 /* See if we can use a 16-bit instruction. */
9340 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9341 && inst
.size_req
!= 4
9342 && !(inst
.operands
[1].imm
& ~0xff))
9344 mask
= 1 << inst
.operands
[0].reg
;
9346 if (inst
.operands
[0].reg
<= 7
9347 && (inst
.instruction
== T_MNEM_stmia
9348 ? inst
.operands
[0].writeback
9349 : (inst
.operands
[0].writeback
9350 == !(inst
.operands
[1].imm
& mask
))))
9352 if (inst
.instruction
== T_MNEM_stmia
9353 && (inst
.operands
[1].imm
& mask
)
9354 && (inst
.operands
[1].imm
& (mask
- 1)))
9355 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9356 inst
.operands
[0].reg
);
9358 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9359 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9360 inst
.instruction
|= inst
.operands
[1].imm
;
9363 else if (inst
.operands
[0] .reg
== REG_SP
9364 && inst
.operands
[0].writeback
)
9366 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9367 ? T_MNEM_push
: T_MNEM_pop
);
9368 inst
.instruction
|= inst
.operands
[1].imm
;
9375 if (inst
.instruction
< 0xffff)
9376 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9378 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9379 inst
.operands
[0].writeback
);
9384 constraint (inst
.operands
[0].reg
> 7
9385 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9386 constraint (inst
.instruction
!= T_MNEM_ldmia
9387 && inst
.instruction
!= T_MNEM_stmia
,
9388 _("Thumb-2 instruction only valid in unified syntax"));
9389 if (inst
.instruction
== T_MNEM_stmia
)
9391 if (!inst
.operands
[0].writeback
)
9392 as_warn (_("this instruction will write back the base register"));
9393 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9394 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9395 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9396 inst
.operands
[0].reg
);
9400 if (!inst
.operands
[0].writeback
9401 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9402 as_warn (_("this instruction will write back the base register"));
9403 else if (inst
.operands
[0].writeback
9404 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9405 as_warn (_("this instruction will not write back the base register"));
9408 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9409 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9410 inst
.instruction
|= inst
.operands
[1].imm
;
9417 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9418 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9419 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9420 || inst
.operands
[1].negative
,
9423 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9424 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9425 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9431 if (!inst
.operands
[1].present
)
9433 constraint (inst
.operands
[0].reg
== REG_LR
,
9434 _("r14 not allowed as first register "
9435 "when second register is omitted"));
9436 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9438 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9441 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9442 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9443 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9449 unsigned long opcode
;
9452 opcode
= inst
.instruction
;
9455 if (!inst
.operands
[1].isreg
)
9457 if (opcode
<= 0xffff)
9458 inst
.instruction
= THUMB_OP32 (opcode
);
9459 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9462 if (inst
.operands
[1].isreg
9463 && !inst
.operands
[1].writeback
9464 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9465 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9467 && inst
.size_req
!= 4)
9469 /* Insn may have a 16-bit form. */
9470 Rn
= inst
.operands
[1].reg
;
9471 if (inst
.operands
[1].immisreg
)
9473 inst
.instruction
= THUMB_OP16 (opcode
);
9475 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9478 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9479 && opcode
!= T_MNEM_ldrsb
)
9480 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9481 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9488 if (inst
.reloc
.pc_rel
)
9489 opcode
= T_MNEM_ldr_pc2
;
9491 opcode
= T_MNEM_ldr_pc
;
9495 if (opcode
== T_MNEM_ldr
)
9496 opcode
= T_MNEM_ldr_sp
;
9498 opcode
= T_MNEM_str_sp
;
9500 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9504 inst
.instruction
= inst
.operands
[0].reg
;
9505 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9507 inst
.instruction
|= THUMB_OP16 (opcode
);
9508 if (inst
.size_req
== 2)
9509 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9511 inst
.relax
= opcode
;
9515 /* Definitely a 32-bit variant. */
9516 inst
.instruction
= THUMB_OP32 (opcode
);
9517 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9518 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9522 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9524 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9526 /* Only [Rn,Rm] is acceptable. */
9527 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9528 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9529 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9530 || inst
.operands
[1].negative
,
9531 _("Thumb does not support this addressing mode"));
9532 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9536 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9537 if (!inst
.operands
[1].isreg
)
9538 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9541 constraint (!inst
.operands
[1].preind
9542 || inst
.operands
[1].shifted
9543 || inst
.operands
[1].writeback
,
9544 _("Thumb does not support this addressing mode"));
9545 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9547 constraint (inst
.instruction
& 0x0600,
9548 _("byte or halfword not valid for base register"));
9549 constraint (inst
.operands
[1].reg
== REG_PC
9550 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9551 _("r15 based store not allowed"));
9552 constraint (inst
.operands
[1].immisreg
,
9553 _("invalid base register for register offset"));
9555 if (inst
.operands
[1].reg
== REG_PC
)
9556 inst
.instruction
= T_OPCODE_LDR_PC
;
9557 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9558 inst
.instruction
= T_OPCODE_LDR_SP
;
9560 inst
.instruction
= T_OPCODE_STR_SP
;
9562 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9563 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9567 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9568 if (!inst
.operands
[1].immisreg
)
9570 /* Immediate offset. */
9571 inst
.instruction
|= inst
.operands
[0].reg
;
9572 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9573 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9577 /* Register offset. */
9578 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9579 constraint (inst
.operands
[1].negative
,
9580 _("Thumb does not support this addressing mode"));
9583 switch (inst
.instruction
)
9585 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9586 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9587 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9588 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9589 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9590 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9591 case 0x5600 /* ldrsb */:
9592 case 0x5e00 /* ldrsh */: break;
9596 inst
.instruction
|= inst
.operands
[0].reg
;
9597 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9598 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9604 if (!inst
.operands
[1].present
)
9606 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9607 constraint (inst
.operands
[0].reg
== REG_LR
,
9608 _("r14 not allowed here"));
9610 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9611 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9612 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9618 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9619 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9625 unsigned Rd
, Rn
, Rm
, Ra
;
9627 Rd
= inst
.operands
[0].reg
;
9628 Rn
= inst
.operands
[1].reg
;
9629 Rm
= inst
.operands
[2].reg
;
9630 Ra
= inst
.operands
[3].reg
;
9632 reject_bad_reg (Rd
);
9633 reject_bad_reg (Rn
);
9634 reject_bad_reg (Rm
);
9635 reject_bad_reg (Ra
);
9637 inst
.instruction
|= Rd
<< 8;
9638 inst
.instruction
|= Rn
<< 16;
9639 inst
.instruction
|= Rm
;
9640 inst
.instruction
|= Ra
<< 12;
9646 unsigned RdLo
, RdHi
, Rn
, Rm
;
9648 RdLo
= inst
.operands
[0].reg
;
9649 RdHi
= inst
.operands
[1].reg
;
9650 Rn
= inst
.operands
[2].reg
;
9651 Rm
= inst
.operands
[3].reg
;
9653 reject_bad_reg (RdLo
);
9654 reject_bad_reg (RdHi
);
9655 reject_bad_reg (Rn
);
9656 reject_bad_reg (Rm
);
9658 inst
.instruction
|= RdLo
<< 12;
9659 inst
.instruction
|= RdHi
<< 8;
9660 inst
.instruction
|= Rn
<< 16;
9661 inst
.instruction
|= Rm
;
9669 Rn
= inst
.operands
[0].reg
;
9670 Rm
= inst
.operands
[1].reg
;
9674 int r0off
= (inst
.instruction
== T_MNEM_mov
9675 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9676 unsigned long opcode
;
9678 bfd_boolean low_regs
;
9680 low_regs
= (Rn
<= 7 && Rm
<= 7);
9681 opcode
= inst
.instruction
;
9682 if (current_it_mask
)
9683 narrow
= opcode
!= T_MNEM_movs
;
9685 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9686 if (inst
.size_req
== 4
9687 || inst
.operands
[1].shifted
)
9690 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9691 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
9692 && !inst
.operands
[1].shifted
9696 inst
.instruction
= T2_SUBS_PC_LR
;
9700 if (opcode
== T_MNEM_cmp
)
9702 constraint (Rn
== REG_PC
, BAD_PC
);
9705 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
9707 warn_deprecated_sp (Rm
);
9708 /* R15 was documented as a valid choice for Rm in ARMv6,
9709 but as UNPREDICTABLE in ARMv7. ARM's proprietary
9710 tools reject R15, so we do too. */
9711 constraint (Rm
== REG_PC
, BAD_PC
);
9714 reject_bad_reg (Rm
);
9716 else if (opcode
== T_MNEM_mov
9717 || opcode
== T_MNEM_movs
)
9719 if (inst
.operands
[1].isreg
)
9721 if (opcode
== T_MNEM_movs
)
9723 reject_bad_reg (Rn
);
9724 reject_bad_reg (Rm
);
9726 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
9727 && (Rm
== REG_SP
|| Rm
== REG_PC
))
9728 reject_bad_reg (Rm
);
9731 reject_bad_reg (Rn
);
9734 if (!inst
.operands
[1].isreg
)
9736 /* Immediate operand. */
9737 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9739 if (low_regs
&& narrow
)
9741 inst
.instruction
= THUMB_OP16 (opcode
);
9742 inst
.instruction
|= Rn
<< 8;
9743 if (inst
.size_req
== 2)
9744 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9746 inst
.relax
= opcode
;
9750 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9751 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9752 inst
.instruction
|= Rn
<< r0off
;
9753 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9756 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
9757 && (inst
.instruction
== T_MNEM_mov
9758 || inst
.instruction
== T_MNEM_movs
))
9760 /* Register shifts are encoded as separate shift instructions. */
9761 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
9763 if (current_it_mask
)
9768 if (inst
.size_req
== 4)
9771 if (!low_regs
|| inst
.operands
[1].imm
> 7)
9777 switch (inst
.operands
[1].shift_kind
)
9780 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
9783 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
9786 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
9789 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
9795 inst
.instruction
= opcode
;
9798 inst
.instruction
|= Rn
;
9799 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
9804 inst
.instruction
|= CONDS_BIT
;
9806 inst
.instruction
|= Rn
<< 8;
9807 inst
.instruction
|= Rm
<< 16;
9808 inst
.instruction
|= inst
.operands
[1].imm
;
9813 /* Some mov with immediate shift have narrow variants.
9814 Register shifts are handled above. */
9815 if (low_regs
&& inst
.operands
[1].shifted
9816 && (inst
.instruction
== T_MNEM_mov
9817 || inst
.instruction
== T_MNEM_movs
))
9819 if (current_it_mask
)
9820 narrow
= (inst
.instruction
== T_MNEM_mov
);
9822 narrow
= (inst
.instruction
== T_MNEM_movs
);
9827 switch (inst
.operands
[1].shift_kind
)
9829 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9830 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9831 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9832 default: narrow
= FALSE
; break;
9838 inst
.instruction
|= Rn
;
9839 inst
.instruction
|= Rm
<< 3;
9840 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9844 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9845 inst
.instruction
|= Rn
<< r0off
;
9846 encode_thumb32_shifted_operand (1);
9850 switch (inst
.instruction
)
9853 inst
.instruction
= T_OPCODE_MOV_HR
;
9854 inst
.instruction
|= (Rn
& 0x8) << 4;
9855 inst
.instruction
|= (Rn
& 0x7);
9856 inst
.instruction
|= Rm
<< 3;
9860 /* We know we have low registers at this point.
9861 Generate ADD Rd, Rs, #0. */
9862 inst
.instruction
= T_OPCODE_ADD_I3
;
9863 inst
.instruction
|= Rn
;
9864 inst
.instruction
|= Rm
<< 3;
9870 inst
.instruction
= T_OPCODE_CMP_LR
;
9871 inst
.instruction
|= Rn
;
9872 inst
.instruction
|= Rm
<< 3;
9876 inst
.instruction
= T_OPCODE_CMP_HR
;
9877 inst
.instruction
|= (Rn
& 0x8) << 4;
9878 inst
.instruction
|= (Rn
& 0x7);
9879 inst
.instruction
|= Rm
<< 3;
9886 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9887 if (inst
.operands
[1].isreg
)
9889 if (Rn
< 8 && Rm
< 8)
9891 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9892 since a MOV instruction produces unpredictable results. */
9893 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9894 inst
.instruction
= T_OPCODE_ADD_I3
;
9896 inst
.instruction
= T_OPCODE_CMP_LR
;
9898 inst
.instruction
|= Rn
;
9899 inst
.instruction
|= Rm
<< 3;
9903 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9904 inst
.instruction
= T_OPCODE_MOV_HR
;
9906 inst
.instruction
= T_OPCODE_CMP_HR
;
9913 _("only lo regs allowed with immediate"));
9914 inst
.instruction
|= Rn
<< 8;
9915 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9926 top
= (inst
.instruction
& 0x00800000) != 0;
9927 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9929 constraint (top
, _(":lower16: not allowed this instruction"));
9930 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9932 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9934 constraint (!top
, _(":upper16: not allowed this instruction"));
9935 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9938 Rd
= inst
.operands
[0].reg
;
9939 reject_bad_reg (Rd
);
9941 inst
.instruction
|= Rd
<< 8;
9942 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9944 imm
= inst
.reloc
.exp
.X_add_number
;
9945 inst
.instruction
|= (imm
& 0xf000) << 4;
9946 inst
.instruction
|= (imm
& 0x0800) << 15;
9947 inst
.instruction
|= (imm
& 0x0700) << 4;
9948 inst
.instruction
|= (imm
& 0x00ff);
9957 Rn
= inst
.operands
[0].reg
;
9958 Rm
= inst
.operands
[1].reg
;
9960 if (inst
.instruction
== T_MNEM_cmp
9961 || inst
.instruction
== T_MNEM_cmn
)
9962 constraint (Rn
== REG_PC
, BAD_PC
);
9964 reject_bad_reg (Rn
);
9965 reject_bad_reg (Rm
);
9969 int r0off
= (inst
.instruction
== T_MNEM_mvn
9970 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9973 if (inst
.size_req
== 4
9974 || inst
.instruction
> 0xffff
9975 || inst
.operands
[1].shifted
9976 || Rn
> 7 || Rm
> 7)
9978 else if (inst
.instruction
== T_MNEM_cmn
)
9980 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9981 narrow
= (current_it_mask
== 0);
9983 narrow
= (current_it_mask
!= 0);
9985 if (!inst
.operands
[1].isreg
)
9987 /* For an immediate, we always generate a 32-bit opcode;
9988 section relaxation will shrink it later if possible. */
9989 if (inst
.instruction
< 0xffff)
9990 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9991 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9992 inst
.instruction
|= Rn
<< r0off
;
9993 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9997 /* See if we can do this with a 16-bit instruction. */
10000 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10001 inst
.instruction
|= Rn
;
10002 inst
.instruction
|= Rm
<< 3;
10006 constraint (inst
.operands
[1].shifted
10007 && inst
.operands
[1].immisreg
,
10008 _("shift must be constant"));
10009 if (inst
.instruction
< 0xffff)
10010 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10011 inst
.instruction
|= Rn
<< r0off
;
10012 encode_thumb32_shifted_operand (1);
10018 constraint (inst
.instruction
> 0xffff
10019 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10020 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10021 _("unshifted register required"));
10022 constraint (Rn
> 7 || Rm
> 7,
10025 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10026 inst
.instruction
|= Rn
;
10027 inst
.instruction
|= Rm
<< 3;
10037 if (do_vfp_nsyn_mrs () == SUCCESS
)
10040 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10043 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10044 _("selected processor does not support "
10045 "requested special purpose register"));
10049 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10050 _("selected processor does not support "
10051 "requested special purpose register"));
10052 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10053 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10054 _("'CPSR' or 'SPSR' expected"));
10057 Rd
= inst
.operands
[0].reg
;
10058 reject_bad_reg (Rd
);
10060 inst
.instruction
|= Rd
<< 8;
10061 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10062 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10071 if (do_vfp_nsyn_msr () == SUCCESS
)
10074 constraint (!inst
.operands
[1].isreg
,
10075 _("Thumb encoding does not support an immediate here"));
10076 flags
= inst
.operands
[0].imm
;
10079 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10080 _("selected processor does not support "
10081 "requested special purpose register"));
10085 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10086 _("selected processor does not support "
10087 "requested special purpose register"));
10091 Rn
= inst
.operands
[1].reg
;
10092 reject_bad_reg (Rn
);
10094 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10095 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10096 inst
.instruction
|= (flags
& 0xff);
10097 inst
.instruction
|= Rn
<< 16;
10103 bfd_boolean narrow
;
10104 unsigned Rd
, Rn
, Rm
;
10106 if (!inst
.operands
[2].present
)
10107 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10109 Rd
= inst
.operands
[0].reg
;
10110 Rn
= inst
.operands
[1].reg
;
10111 Rm
= inst
.operands
[2].reg
;
10113 if (unified_syntax
)
10115 if (inst
.size_req
== 4
10121 else if (inst
.instruction
== T_MNEM_muls
)
10122 narrow
= (current_it_mask
== 0);
10124 narrow
= (current_it_mask
!= 0);
10128 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10129 constraint (Rn
> 7 || Rm
> 7,
10136 /* 16-bit MULS/Conditional MUL. */
10137 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10138 inst
.instruction
|= Rd
;
10141 inst
.instruction
|= Rm
<< 3;
10143 inst
.instruction
|= Rn
<< 3;
10145 constraint (1, _("dest must overlap one source register"));
10149 constraint(inst
.instruction
!= T_MNEM_mul
,
10150 _("Thumb-2 MUL must not set flags"));
10152 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10153 inst
.instruction
|= Rd
<< 8;
10154 inst
.instruction
|= Rn
<< 16;
10155 inst
.instruction
|= Rm
<< 0;
10157 reject_bad_reg (Rd
);
10158 reject_bad_reg (Rn
);
10159 reject_bad_reg (Rm
);
10166 unsigned RdLo
, RdHi
, Rn
, Rm
;
10168 RdLo
= inst
.operands
[0].reg
;
10169 RdHi
= inst
.operands
[1].reg
;
10170 Rn
= inst
.operands
[2].reg
;
10171 Rm
= inst
.operands
[3].reg
;
10173 reject_bad_reg (RdLo
);
10174 reject_bad_reg (RdHi
);
10175 reject_bad_reg (Rn
);
10176 reject_bad_reg (Rm
);
10178 inst
.instruction
|= RdLo
<< 12;
10179 inst
.instruction
|= RdHi
<< 8;
10180 inst
.instruction
|= Rn
<< 16;
10181 inst
.instruction
|= Rm
;
10184 as_tsktsk (_("rdhi and rdlo must be different"));
10190 if (unified_syntax
)
10192 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10194 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10195 inst
.instruction
|= inst
.operands
[0].imm
;
10199 /* PR9722: Check for Thumb2 availability before
10200 generating a thumb2 nop instruction. */
10201 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
10203 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10204 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10207 inst
.instruction
= 0x46c0;
10212 constraint (inst
.operands
[0].present
,
10213 _("Thumb does not support NOP with hints"));
10214 inst
.instruction
= 0x46c0;
10221 if (unified_syntax
)
10223 bfd_boolean narrow
;
10225 if (THUMB_SETS_FLAGS (inst
.instruction
))
10226 narrow
= (current_it_mask
== 0);
10228 narrow
= (current_it_mask
!= 0);
10229 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10231 if (inst
.size_req
== 4)
10236 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10237 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10238 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10242 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10243 inst
.instruction
|= inst
.operands
[0].reg
;
10244 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10249 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10251 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10253 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10254 inst
.instruction
|= inst
.operands
[0].reg
;
10255 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10264 Rd
= inst
.operands
[0].reg
;
10265 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10267 reject_bad_reg (Rd
);
10268 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10269 reject_bad_reg (Rn
);
10271 inst
.instruction
|= Rd
<< 8;
10272 inst
.instruction
|= Rn
<< 16;
10274 if (!inst
.operands
[2].isreg
)
10276 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10277 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10283 Rm
= inst
.operands
[2].reg
;
10284 reject_bad_reg (Rm
);
10286 constraint (inst
.operands
[2].shifted
10287 && inst
.operands
[2].immisreg
,
10288 _("shift must be constant"));
10289 encode_thumb32_shifted_operand (2);
10296 unsigned Rd
, Rn
, Rm
;
10298 Rd
= inst
.operands
[0].reg
;
10299 Rn
= inst
.operands
[1].reg
;
10300 Rm
= inst
.operands
[2].reg
;
10302 reject_bad_reg (Rd
);
10303 reject_bad_reg (Rn
);
10304 reject_bad_reg (Rm
);
10306 inst
.instruction
|= Rd
<< 8;
10307 inst
.instruction
|= Rn
<< 16;
10308 inst
.instruction
|= Rm
;
10309 if (inst
.operands
[3].present
)
10311 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10312 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10313 _("expression too complex"));
10314 inst
.instruction
|= (val
& 0x1c) << 10;
10315 inst
.instruction
|= (val
& 0x03) << 6;
10322 if (!inst
.operands
[3].present
)
10323 inst
.instruction
&= ~0x00000020;
10330 if (inst
.operands
[0].immisreg
)
10331 reject_bad_reg (inst
.operands
[0].imm
);
10333 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10337 do_t_push_pop (void)
10341 constraint (inst
.operands
[0].writeback
,
10342 _("push/pop do not support {reglist}^"));
10343 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10344 _("expression too complex"));
10346 mask
= inst
.operands
[0].imm
;
10347 if ((mask
& ~0xff) == 0)
10348 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10349 else if ((inst
.instruction
== T_MNEM_push
10350 && (mask
& ~0xff) == 1 << REG_LR
)
10351 || (inst
.instruction
== T_MNEM_pop
10352 && (mask
& ~0xff) == 1 << REG_PC
))
10354 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10355 inst
.instruction
|= THUMB_PP_PC_LR
;
10356 inst
.instruction
|= mask
& 0xff;
10358 else if (unified_syntax
)
10360 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10361 encode_thumb2_ldmstm (13, mask
, TRUE
);
10365 inst
.error
= _("invalid register list to push/pop instruction");
10375 Rd
= inst
.operands
[0].reg
;
10376 Rm
= inst
.operands
[1].reg
;
10378 reject_bad_reg (Rd
);
10379 reject_bad_reg (Rm
);
10381 inst
.instruction
|= Rd
<< 8;
10382 inst
.instruction
|= Rm
<< 16;
10383 inst
.instruction
|= Rm
;
10391 Rd
= inst
.operands
[0].reg
;
10392 Rm
= inst
.operands
[1].reg
;
10394 reject_bad_reg (Rd
);
10395 reject_bad_reg (Rm
);
10397 if (Rd
<= 7 && Rm
<= 7
10398 && inst
.size_req
!= 4)
10400 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10401 inst
.instruction
|= Rd
;
10402 inst
.instruction
|= Rm
<< 3;
10404 else if (unified_syntax
)
10406 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10407 inst
.instruction
|= Rd
<< 8;
10408 inst
.instruction
|= Rm
<< 16;
10409 inst
.instruction
|= Rm
;
10412 inst
.error
= BAD_HIREG
;
10420 Rd
= inst
.operands
[0].reg
;
10421 Rm
= inst
.operands
[1].reg
;
10423 reject_bad_reg (Rd
);
10424 reject_bad_reg (Rm
);
10426 inst
.instruction
|= Rd
<< 8;
10427 inst
.instruction
|= Rm
;
10435 Rd
= inst
.operands
[0].reg
;
10436 Rs
= (inst
.operands
[1].present
10437 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10438 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10440 reject_bad_reg (Rd
);
10441 reject_bad_reg (Rs
);
10442 if (inst
.operands
[2].isreg
)
10443 reject_bad_reg (inst
.operands
[2].reg
);
10445 inst
.instruction
|= Rd
<< 8;
10446 inst
.instruction
|= Rs
<< 16;
10447 if (!inst
.operands
[2].isreg
)
10449 bfd_boolean narrow
;
10451 if ((inst
.instruction
& 0x00100000) != 0)
10452 narrow
= (current_it_mask
== 0);
10454 narrow
= (current_it_mask
!= 0);
10456 if (Rd
> 7 || Rs
> 7)
10459 if (inst
.size_req
== 4 || !unified_syntax
)
10462 if (inst
.reloc
.exp
.X_op
!= O_constant
10463 || inst
.reloc
.exp
.X_add_number
!= 0)
10466 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10467 relaxation, but it doesn't seem worth the hassle. */
10470 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10471 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10472 inst
.instruction
|= Rs
<< 3;
10473 inst
.instruction
|= Rd
;
10477 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10478 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10482 encode_thumb32_shifted_operand (2);
10488 constraint (current_it_mask
, BAD_NOT_IT
);
10489 if (inst
.operands
[0].imm
)
10490 inst
.instruction
|= 0x8;
10496 if (!inst
.operands
[1].present
)
10497 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10499 if (unified_syntax
)
10501 bfd_boolean narrow
;
10504 switch (inst
.instruction
)
10507 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10509 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10511 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10513 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10517 if (THUMB_SETS_FLAGS (inst
.instruction
))
10518 narrow
= (current_it_mask
== 0);
10520 narrow
= (current_it_mask
!= 0);
10521 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10523 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10525 if (inst
.operands
[2].isreg
10526 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10527 || inst
.operands
[2].reg
> 7))
10529 if (inst
.size_req
== 4)
10532 reject_bad_reg (inst
.operands
[0].reg
);
10533 reject_bad_reg (inst
.operands
[1].reg
);
10537 if (inst
.operands
[2].isreg
)
10539 reject_bad_reg (inst
.operands
[2].reg
);
10540 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10541 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10542 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10543 inst
.instruction
|= inst
.operands
[2].reg
;
10547 inst
.operands
[1].shifted
= 1;
10548 inst
.operands
[1].shift_kind
= shift_kind
;
10549 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10550 ? T_MNEM_movs
: T_MNEM_mov
);
10551 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10552 encode_thumb32_shifted_operand (1);
10553 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10554 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10559 if (inst
.operands
[2].isreg
)
10561 switch (shift_kind
)
10563 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10564 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10565 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10566 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10570 inst
.instruction
|= inst
.operands
[0].reg
;
10571 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10575 switch (shift_kind
)
10577 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10578 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10579 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10582 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10583 inst
.instruction
|= inst
.operands
[0].reg
;
10584 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10590 constraint (inst
.operands
[0].reg
> 7
10591 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10592 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10594 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10596 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10597 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10598 _("source1 and dest must be same register"));
10600 switch (inst
.instruction
)
10602 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10603 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10604 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10605 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10609 inst
.instruction
|= inst
.operands
[0].reg
;
10610 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10614 switch (inst
.instruction
)
10616 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10617 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10618 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10619 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10622 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10623 inst
.instruction
|= inst
.operands
[0].reg
;
10624 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10632 unsigned Rd
, Rn
, Rm
;
10634 Rd
= inst
.operands
[0].reg
;
10635 Rn
= inst
.operands
[1].reg
;
10636 Rm
= inst
.operands
[2].reg
;
10638 reject_bad_reg (Rd
);
10639 reject_bad_reg (Rn
);
10640 reject_bad_reg (Rm
);
10642 inst
.instruction
|= Rd
<< 8;
10643 inst
.instruction
|= Rn
<< 16;
10644 inst
.instruction
|= Rm
;
10650 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10651 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10652 _("expression too complex"));
10653 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10654 inst
.instruction
|= (value
& 0xf000) >> 12;
10655 inst
.instruction
|= (value
& 0x0ff0);
10656 inst
.instruction
|= (value
& 0x000f) << 16;
10664 Rd
= inst
.operands
[0].reg
;
10665 Rn
= inst
.operands
[2].reg
;
10667 reject_bad_reg (Rd
);
10668 reject_bad_reg (Rn
);
10670 inst
.instruction
|= Rd
<< 8;
10671 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10672 inst
.instruction
|= Rn
<< 16;
10674 if (inst
.operands
[3].present
)
10676 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10677 _("expression too complex"));
10679 if (inst
.reloc
.exp
.X_add_number
!= 0)
10681 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10682 inst
.instruction
|= 0x00200000; /* sh bit */
10683 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10684 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10686 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10695 Rd
= inst
.operands
[0].reg
;
10696 Rn
= inst
.operands
[2].reg
;
10698 reject_bad_reg (Rd
);
10699 reject_bad_reg (Rn
);
10701 inst
.instruction
|= Rd
<< 8;
10702 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10703 inst
.instruction
|= Rn
<< 16;
10709 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10710 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10711 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10712 || inst
.operands
[2].negative
,
10715 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10716 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10717 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10718 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10724 if (!inst
.operands
[2].present
)
10725 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10727 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10728 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10729 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10730 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10733 inst
.instruction
|= inst
.operands
[0].reg
;
10734 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10735 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10736 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10742 unsigned Rd
, Rn
, Rm
;
10744 Rd
= inst
.operands
[0].reg
;
10745 Rn
= inst
.operands
[1].reg
;
10746 Rm
= inst
.operands
[2].reg
;
10748 reject_bad_reg (Rd
);
10749 reject_bad_reg (Rn
);
10750 reject_bad_reg (Rm
);
10752 inst
.instruction
|= Rd
<< 8;
10753 inst
.instruction
|= Rn
<< 16;
10754 inst
.instruction
|= Rm
;
10755 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10763 Rd
= inst
.operands
[0].reg
;
10764 Rm
= inst
.operands
[1].reg
;
10766 reject_bad_reg (Rd
);
10767 reject_bad_reg (Rm
);
10769 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10770 && Rd
<= 7 && Rm
<= 7
10771 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10773 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10774 inst
.instruction
|= Rd
;
10775 inst
.instruction
|= Rm
<< 3;
10777 else if (unified_syntax
)
10779 if (inst
.instruction
<= 0xffff)
10780 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10781 inst
.instruction
|= Rd
<< 8;
10782 inst
.instruction
|= Rm
;
10783 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10787 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10788 _("Thumb encoding does not support rotation"));
10789 constraint (1, BAD_HIREG
);
10796 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10805 half
= (inst
.instruction
& 0x10) != 0;
10806 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10807 constraint (inst
.operands
[0].immisreg
,
10808 _("instruction requires register index"));
10810 Rn
= inst
.operands
[0].reg
;
10811 Rm
= inst
.operands
[0].imm
;
10813 constraint (Rn
== REG_SP
, BAD_SP
);
10814 reject_bad_reg (Rm
);
10816 constraint (!half
&& inst
.operands
[0].shifted
,
10817 _("instruction does not allow shifted index"));
10818 inst
.instruction
|= (Rn
<< 16) | Rm
;
10826 Rd
= inst
.operands
[0].reg
;
10827 Rn
= inst
.operands
[2].reg
;
10829 reject_bad_reg (Rd
);
10830 reject_bad_reg (Rn
);
10832 inst
.instruction
|= Rd
<< 8;
10833 inst
.instruction
|= inst
.operands
[1].imm
;
10834 inst
.instruction
|= Rn
<< 16;
10836 if (inst
.operands
[3].present
)
10838 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10839 _("expression too complex"));
10840 if (inst
.reloc
.exp
.X_add_number
!= 0)
10842 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10843 inst
.instruction
|= 0x00200000; /* sh bit */
10845 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10846 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10848 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10857 Rd
= inst
.operands
[0].reg
;
10858 Rn
= inst
.operands
[2].reg
;
10860 reject_bad_reg (Rd
);
10861 reject_bad_reg (Rn
);
10863 inst
.instruction
|= Rd
<< 8;
10864 inst
.instruction
|= inst
.operands
[1].imm
;
10865 inst
.instruction
|= Rn
<< 16;
10868 /* Neon instruction encoder helpers. */
10870 /* Encodings for the different types for various Neon opcodes. */
10872 /* An "invalid" code for the following tables. */
10875 struct neon_tab_entry
10878 unsigned float_or_poly
;
10879 unsigned scalar_or_imm
;
10882 /* Map overloaded Neon opcodes to their respective encodings. */
10883 #define NEON_ENC_TAB \
10884 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10885 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10886 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10887 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10888 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10889 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10890 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10891 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10892 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10893 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10894 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10895 /* Register variants of the following two instructions are encoded as
10896 vcge / vcgt with the operands reversed. */ \
10897 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10898 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10899 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10900 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10901 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10902 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10903 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10904 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10905 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10906 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10907 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10908 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10909 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10910 X(vshl, 0x0000400, N_INV, 0x0800510), \
10911 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10912 X(vand, 0x0000110, N_INV, 0x0800030), \
10913 X(vbic, 0x0100110, N_INV, 0x0800030), \
10914 X(veor, 0x1000110, N_INV, N_INV), \
10915 X(vorn, 0x0300110, N_INV, 0x0800010), \
10916 X(vorr, 0x0200110, N_INV, 0x0800010), \
10917 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10918 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10919 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10920 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10921 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10922 X(vst1, 0x0000000, 0x0800000, N_INV), \
10923 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10924 X(vst2, 0x0000100, 0x0800100, N_INV), \
10925 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10926 X(vst3, 0x0000200, 0x0800200, N_INV), \
10927 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10928 X(vst4, 0x0000300, 0x0800300, N_INV), \
10929 X(vmovn, 0x1b20200, N_INV, N_INV), \
10930 X(vtrn, 0x1b20080, N_INV, N_INV), \
10931 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10932 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10933 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10934 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10935 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10936 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10937 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10938 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10939 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10943 #define X(OPC,I,F,S) N_MNEM_##OPC
10948 static const struct neon_tab_entry neon_enc_tab
[] =
10950 #define X(OPC,I,F,S) { (I), (F), (S) }
10955 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10956 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10957 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10958 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10959 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10960 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10961 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10962 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10963 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10964 #define NEON_ENC_SINGLE(X) \
10965 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10966 #define NEON_ENC_DOUBLE(X) \
10967 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10969 /* Define shapes for instruction operands. The following mnemonic characters
10970 are used in this table:
10972 F - VFP S<n> register
10973 D - Neon D<n> register
10974 Q - Neon Q<n> register
10978 L - D<n> register list
10980 This table is used to generate various data:
10981 - enumerations of the form NS_DDR to be used as arguments to
10983 - a table classifying shapes into single, double, quad, mixed.
10984 - a table used to drive neon_select_shape. */
10986 #define NEON_SHAPE_DEF \
10987 X(3, (D, D, D), DOUBLE), \
10988 X(3, (Q, Q, Q), QUAD), \
10989 X(3, (D, D, I), DOUBLE), \
10990 X(3, (Q, Q, I), QUAD), \
10991 X(3, (D, D, S), DOUBLE), \
10992 X(3, (Q, Q, S), QUAD), \
10993 X(2, (D, D), DOUBLE), \
10994 X(2, (Q, Q), QUAD), \
10995 X(2, (D, S), DOUBLE), \
10996 X(2, (Q, S), QUAD), \
10997 X(2, (D, R), DOUBLE), \
10998 X(2, (Q, R), QUAD), \
10999 X(2, (D, I), DOUBLE), \
11000 X(2, (Q, I), QUAD), \
11001 X(3, (D, L, D), DOUBLE), \
11002 X(2, (D, Q), MIXED), \
11003 X(2, (Q, D), MIXED), \
11004 X(3, (D, Q, I), MIXED), \
11005 X(3, (Q, D, I), MIXED), \
11006 X(3, (Q, D, D), MIXED), \
11007 X(3, (D, Q, Q), MIXED), \
11008 X(3, (Q, Q, D), MIXED), \
11009 X(3, (Q, D, S), MIXED), \
11010 X(3, (D, Q, S), MIXED), \
11011 X(4, (D, D, D, I), DOUBLE), \
11012 X(4, (Q, Q, Q, I), QUAD), \
11013 X(2, (F, F), SINGLE), \
11014 X(3, (F, F, F), SINGLE), \
11015 X(2, (F, I), SINGLE), \
11016 X(2, (F, D), MIXED), \
11017 X(2, (D, F), MIXED), \
11018 X(3, (F, F, I), MIXED), \
11019 X(4, (R, R, F, F), SINGLE), \
11020 X(4, (F, F, R, R), SINGLE), \
11021 X(3, (D, R, R), DOUBLE), \
11022 X(3, (R, R, D), DOUBLE), \
11023 X(2, (S, R), SINGLE), \
11024 X(2, (R, S), SINGLE), \
11025 X(2, (F, R), SINGLE), \
11026 X(2, (R, F), SINGLE)
11028 #define S2(A,B) NS_##A##B
11029 #define S3(A,B,C) NS_##A##B##C
11030 #define S4(A,B,C,D) NS_##A##B##C##D
11032 #define X(N, L, C) S##N L
11045 enum neon_shape_class
11053 #define X(N, L, C) SC_##C
11055 static enum neon_shape_class neon_shape_class
[] =
11073 /* Register widths of above. */
11074 static unsigned neon_shape_el_size
[] =
11085 struct neon_shape_info
11088 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11091 #define S2(A,B) { SE_##A, SE_##B }
11092 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11093 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11095 #define X(N, L, C) { N, S##N L }
11097 static struct neon_shape_info neon_shape_tab
[] =
11107 /* Bit masks used in type checking given instructions.
11108 'N_EQK' means the type must be the same as (or based on in some way) the key
11109 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11110 set, various other bits can be set as well in order to modify the meaning of
11111 the type constraint. */
11113 enum neon_type_mask
11136 N_KEY
= 0x1000000, /* key element (main type specifier). */
11137 N_EQK
= 0x2000000, /* given operand has the same type & size as the key. */
11138 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11139 N_DBL
= 0x0000001, /* if N_EQK, this operand is twice the size. */
11140 N_HLF
= 0x0000002, /* if N_EQK, this operand is half the size. */
11141 N_SGN
= 0x0000004, /* if N_EQK, this operand is forced to be signed. */
11142 N_UNS
= 0x0000008, /* if N_EQK, this operand is forced to be unsigned. */
11143 N_INT
= 0x0000010, /* if N_EQK, this operand is forced to be integer. */
11144 N_FLT
= 0x0000020, /* if N_EQK, this operand is forced to be float. */
11145 N_SIZ
= 0x0000040, /* if N_EQK, this operand is forced to be size-only. */
11147 N_MAX_NONSPECIAL
= N_F64
11150 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11152 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11153 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11154 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11155 #define N_SUF_32 (N_SU_32 | N_F32)
11156 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11157 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11159 /* Pass this as the first type argument to neon_check_type to ignore types
11161 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11163 /* Select a "shape" for the current instruction (describing register types or
11164 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11165 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11166 function of operand parsing, so this function doesn't need to be called.
11167 Shapes should be listed in order of decreasing length. */
11169 static enum neon_shape
11170 neon_select_shape (enum neon_shape shape
, ...)
11173 enum neon_shape first_shape
= shape
;
11175 /* Fix missing optional operands. FIXME: we don't know at this point how
11176 many arguments we should have, so this makes the assumption that we have
11177 > 1. This is true of all current Neon opcodes, I think, but may not be
11178 true in the future. */
11179 if (!inst
.operands
[1].present
)
11180 inst
.operands
[1] = inst
.operands
[0];
11182 va_start (ap
, shape
);
11184 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
11189 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11191 if (!inst
.operands
[j
].present
)
11197 switch (neon_shape_tab
[shape
].el
[j
])
11200 if (!(inst
.operands
[j
].isreg
11201 && inst
.operands
[j
].isvec
11202 && inst
.operands
[j
].issingle
11203 && !inst
.operands
[j
].isquad
))
11208 if (!(inst
.operands
[j
].isreg
11209 && inst
.operands
[j
].isvec
11210 && !inst
.operands
[j
].isquad
11211 && !inst
.operands
[j
].issingle
))
11216 if (!(inst
.operands
[j
].isreg
11217 && !inst
.operands
[j
].isvec
))
11222 if (!(inst
.operands
[j
].isreg
11223 && inst
.operands
[j
].isvec
11224 && inst
.operands
[j
].isquad
11225 && !inst
.operands
[j
].issingle
))
11230 if (!(!inst
.operands
[j
].isreg
11231 && !inst
.operands
[j
].isscalar
))
11236 if (!(!inst
.operands
[j
].isreg
11237 && inst
.operands
[j
].isscalar
))
11251 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11252 first_error (_("invalid instruction shape"));
11257 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11258 means the Q bit should be set). */
11261 neon_quad (enum neon_shape shape
)
11263 return neon_shape_class
[shape
] == SC_QUAD
;
11267 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11270 /* Allow modification to be made to types which are constrained to be
11271 based on the key element, based on bits set alongside N_EQK. */
11272 if ((typebits
& N_EQK
) != 0)
11274 if ((typebits
& N_HLF
) != 0)
11276 else if ((typebits
& N_DBL
) != 0)
11278 if ((typebits
& N_SGN
) != 0)
11279 *g_type
= NT_signed
;
11280 else if ((typebits
& N_UNS
) != 0)
11281 *g_type
= NT_unsigned
;
11282 else if ((typebits
& N_INT
) != 0)
11283 *g_type
= NT_integer
;
11284 else if ((typebits
& N_FLT
) != 0)
11285 *g_type
= NT_float
;
11286 else if ((typebits
& N_SIZ
) != 0)
11287 *g_type
= NT_untyped
;
11291 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11292 operand type, i.e. the single type specified in a Neon instruction when it
11293 is the only one given. */
11295 static struct neon_type_el
11296 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11298 struct neon_type_el dest
= *key
;
11300 assert ((thisarg
& N_EQK
) != 0);
11302 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11307 /* Convert Neon type and size into compact bitmask representation. */
11309 static enum neon_type_mask
11310 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11317 case 8: return N_8
;
11318 case 16: return N_16
;
11319 case 32: return N_32
;
11320 case 64: return N_64
;
11328 case 8: return N_I8
;
11329 case 16: return N_I16
;
11330 case 32: return N_I32
;
11331 case 64: return N_I64
;
11339 case 16: return N_F16
;
11340 case 32: return N_F32
;
11341 case 64: return N_F64
;
11349 case 8: return N_P8
;
11350 case 16: return N_P16
;
11358 case 8: return N_S8
;
11359 case 16: return N_S16
;
11360 case 32: return N_S32
;
11361 case 64: return N_S64
;
11369 case 8: return N_U8
;
11370 case 16: return N_U16
;
11371 case 32: return N_U32
;
11372 case 64: return N_U64
;
11383 /* Convert compact Neon bitmask type representation to a type and size. Only
11384 handles the case where a single bit is set in the mask. */
11387 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11388 enum neon_type_mask mask
)
11390 if ((mask
& N_EQK
) != 0)
11393 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11395 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11397 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11399 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11404 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11406 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11407 *type
= NT_unsigned
;
11408 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11409 *type
= NT_integer
;
11410 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11411 *type
= NT_untyped
;
11412 else if ((mask
& (N_P8
| N_P16
)) != 0)
11414 else if ((mask
& (N_F32
| N_F64
)) != 0)
11422 /* Modify a bitmask of allowed types. This is only needed for type
11426 modify_types_allowed (unsigned allowed
, unsigned mods
)
11429 enum neon_el_type type
;
11435 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11437 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
11439 neon_modify_type_size (mods
, &type
, &size
);
11440 destmask
|= type_chk_of_el_type (type
, size
);
11447 /* Check type and return type classification.
11448 The manual states (paraphrase): If one datatype is given, it indicates the
11450 - the second operand, if there is one
11451 - the operand, if there is no second operand
11452 - the result, if there are no operands.
11453 This isn't quite good enough though, so we use a concept of a "key" datatype
11454 which is set on a per-instruction basis, which is the one which matters when
11455 only one data type is written.
11456 Note: this function has side-effects (e.g. filling in missing operands). All
11457 Neon instructions should call it before performing bit encoding. */
11459 static struct neon_type_el
11460 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11463 unsigned i
, pass
, key_el
= 0;
11464 unsigned types
[NEON_MAX_TYPE_ELS
];
11465 enum neon_el_type k_type
= NT_invtype
;
11466 unsigned k_size
= -1u;
11467 struct neon_type_el badtype
= {NT_invtype
, -1};
11468 unsigned key_allowed
= 0;
11470 /* Optional registers in Neon instructions are always (not) in operand 1.
11471 Fill in the missing operand here, if it was omitted. */
11472 if (els
> 1 && !inst
.operands
[1].present
)
11473 inst
.operands
[1] = inst
.operands
[0];
11475 /* Suck up all the varargs. */
11477 for (i
= 0; i
< els
; i
++)
11479 unsigned thisarg
= va_arg (ap
, unsigned);
11480 if (thisarg
== N_IGNORE_TYPE
)
11485 types
[i
] = thisarg
;
11486 if ((thisarg
& N_KEY
) != 0)
11491 if (inst
.vectype
.elems
> 0)
11492 for (i
= 0; i
< els
; i
++)
11493 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11495 first_error (_("types specified in both the mnemonic and operands"));
11499 /* Duplicate inst.vectype elements here as necessary.
11500 FIXME: No idea if this is exactly the same as the ARM assembler,
11501 particularly when an insn takes one register and one non-register
11503 if (inst
.vectype
.elems
== 1 && els
> 1)
11506 inst
.vectype
.elems
= els
;
11507 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11508 for (j
= 0; j
< els
; j
++)
11510 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11513 else if (inst
.vectype
.elems
== 0 && els
> 0)
11516 /* No types were given after the mnemonic, so look for types specified
11517 after each operand. We allow some flexibility here; as long as the
11518 "key" operand has a type, we can infer the others. */
11519 for (j
= 0; j
< els
; j
++)
11520 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11521 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11523 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11525 for (j
= 0; j
< els
; j
++)
11526 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11527 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11532 first_error (_("operand types can't be inferred"));
11536 else if (inst
.vectype
.elems
!= els
)
11538 first_error (_("type specifier has the wrong number of parts"));
11542 for (pass
= 0; pass
< 2; pass
++)
11544 for (i
= 0; i
< els
; i
++)
11546 unsigned thisarg
= types
[i
];
11547 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11548 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11549 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11550 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11552 /* Decay more-specific signed & unsigned types to sign-insensitive
11553 integer types if sign-specific variants are unavailable. */
11554 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11555 && (types_allowed
& N_SU_ALL
) == 0)
11556 g_type
= NT_integer
;
11558 /* If only untyped args are allowed, decay any more specific types to
11559 them. Some instructions only care about signs for some element
11560 sizes, so handle that properly. */
11561 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11562 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11563 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11564 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11565 g_type
= NT_untyped
;
11569 if ((thisarg
& N_KEY
) != 0)
11573 key_allowed
= thisarg
& ~N_KEY
;
11578 if ((thisarg
& N_VFP
) != 0)
11580 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11581 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11583 /* In VFP mode, operands must match register widths. If we
11584 have a key operand, use its width, else use the width of
11585 the current operand. */
11591 if (regwidth
!= match
)
11593 first_error (_("operand size must match register width"));
11598 if ((thisarg
& N_EQK
) == 0)
11600 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11602 if ((given_type
& types_allowed
) == 0)
11604 first_error (_("bad type in Neon instruction"));
11610 enum neon_el_type mod_k_type
= k_type
;
11611 unsigned mod_k_size
= k_size
;
11612 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11613 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11615 first_error (_("inconsistent types in Neon instruction"));
11623 return inst
.vectype
.el
[key_el
];
11626 /* Neon-style VFP instruction forwarding. */
11628 /* Thumb VFP instructions have 0xE in the condition field. */
11631 do_vfp_cond_or_thumb (void)
11634 inst
.instruction
|= 0xe0000000;
11636 inst
.instruction
|= inst
.cond
<< 28;
11639 /* Look up and encode a simple mnemonic, for use as a helper function for the
11640 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11641 etc. It is assumed that operand parsing has already been done, and that the
11642 operands are in the form expected by the given opcode (this isn't necessarily
11643 the same as the form in which they were parsed, hence some massaging must
11644 take place before this function is called).
11645 Checks current arch version against that in the looked-up opcode. */
11648 do_vfp_nsyn_opcode (const char *opname
)
11650 const struct asm_opcode
*opcode
;
11652 opcode
= hash_find (arm_ops_hsh
, opname
);
11657 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11658 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11663 inst
.instruction
= opcode
->tvalue
;
11664 opcode
->tencode ();
11668 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11669 opcode
->aencode ();
11674 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11676 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11681 do_vfp_nsyn_opcode ("fadds");
11683 do_vfp_nsyn_opcode ("fsubs");
11688 do_vfp_nsyn_opcode ("faddd");
11690 do_vfp_nsyn_opcode ("fsubd");
11694 /* Check operand types to see if this is a VFP instruction, and if so call
11698 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11700 enum neon_shape rs
;
11701 struct neon_type_el et
;
11706 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11707 et
= neon_check_type (2, rs
,
11708 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11712 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11713 et
= neon_check_type (3, rs
,
11714 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11721 if (et
.type
!= NT_invtype
)
11733 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11735 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11740 do_vfp_nsyn_opcode ("fmacs");
11742 do_vfp_nsyn_opcode ("fmscs");
11747 do_vfp_nsyn_opcode ("fmacd");
11749 do_vfp_nsyn_opcode ("fmscd");
11754 do_vfp_nsyn_mul (enum neon_shape rs
)
11757 do_vfp_nsyn_opcode ("fmuls");
11759 do_vfp_nsyn_opcode ("fmuld");
11763 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11765 int is_neg
= (inst
.instruction
& 0x80) != 0;
11766 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11771 do_vfp_nsyn_opcode ("fnegs");
11773 do_vfp_nsyn_opcode ("fabss");
11778 do_vfp_nsyn_opcode ("fnegd");
11780 do_vfp_nsyn_opcode ("fabsd");
11784 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11785 insns belong to Neon, and are handled elsewhere. */
11788 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11790 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11794 do_vfp_nsyn_opcode ("fldmdbs");
11796 do_vfp_nsyn_opcode ("fldmias");
11801 do_vfp_nsyn_opcode ("fstmdbs");
11803 do_vfp_nsyn_opcode ("fstmias");
11808 do_vfp_nsyn_sqrt (void)
11810 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11811 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11814 do_vfp_nsyn_opcode ("fsqrts");
11816 do_vfp_nsyn_opcode ("fsqrtd");
11820 do_vfp_nsyn_div (void)
11822 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11823 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11824 N_F32
| N_F64
| N_KEY
| N_VFP
);
11827 do_vfp_nsyn_opcode ("fdivs");
11829 do_vfp_nsyn_opcode ("fdivd");
11833 do_vfp_nsyn_nmul (void)
11835 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11836 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11837 N_F32
| N_F64
| N_KEY
| N_VFP
);
11841 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11842 do_vfp_sp_dyadic ();
11846 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11847 do_vfp_dp_rd_rn_rm ();
11849 do_vfp_cond_or_thumb ();
11853 do_vfp_nsyn_cmp (void)
11855 if (inst
.operands
[1].isreg
)
11857 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11858 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11862 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11863 do_vfp_sp_monadic ();
11867 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11868 do_vfp_dp_rd_rm ();
11873 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11874 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11876 switch (inst
.instruction
& 0x0fffffff)
11879 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11882 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11890 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11891 do_vfp_sp_compare_z ();
11895 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11899 do_vfp_cond_or_thumb ();
11903 nsyn_insert_sp (void)
11905 inst
.operands
[1] = inst
.operands
[0];
11906 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11907 inst
.operands
[0].reg
= REG_SP
;
11908 inst
.operands
[0].isreg
= 1;
11909 inst
.operands
[0].writeback
= 1;
11910 inst
.operands
[0].present
= 1;
11914 do_vfp_nsyn_push (void)
11917 if (inst
.operands
[1].issingle
)
11918 do_vfp_nsyn_opcode ("fstmdbs");
11920 do_vfp_nsyn_opcode ("fstmdbd");
11924 do_vfp_nsyn_pop (void)
11927 if (inst
.operands
[1].issingle
)
11928 do_vfp_nsyn_opcode ("fldmias");
11930 do_vfp_nsyn_opcode ("fldmiad");
11933 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11934 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11937 neon_dp_fixup (unsigned i
)
11941 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11955 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11959 neon_logbits (unsigned x
)
11961 return ffs (x
) - 4;
11964 #define LOW4(R) ((R) & 0xf)
11965 #define HI1(R) (((R) >> 4) & 1)
11967 /* Encode insns with bit pattern:
11969 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11970 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11972 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11973 different meaning for some instruction. */
11976 neon_three_same (int isquad
, int ubit
, int size
)
11978 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11979 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11980 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11981 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11982 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11983 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11984 inst
.instruction
|= (isquad
!= 0) << 6;
11985 inst
.instruction
|= (ubit
!= 0) << 24;
11987 inst
.instruction
|= neon_logbits (size
) << 20;
11989 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11992 /* Encode instructions of the form:
11994 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11995 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11997 Don't write size if SIZE == -1. */
12000 neon_two_same (int qbit
, int ubit
, int size
)
12002 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12003 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12004 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12005 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12006 inst
.instruction
|= (qbit
!= 0) << 6;
12007 inst
.instruction
|= (ubit
!= 0) << 24;
12010 inst
.instruction
|= neon_logbits (size
) << 18;
12012 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12015 /* Neon instruction encoders, in approximate order of appearance. */
12018 do_neon_dyadic_i_su (void)
12020 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12021 struct neon_type_el et
= neon_check_type (3, rs
,
12022 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12023 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12027 do_neon_dyadic_i64_su (void)
12029 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12030 struct neon_type_el et
= neon_check_type (3, rs
,
12031 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12032 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12036 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12039 unsigned size
= et
.size
>> 3;
12040 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12041 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12042 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12043 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12044 inst
.instruction
|= (isquad
!= 0) << 6;
12045 inst
.instruction
|= immbits
<< 16;
12046 inst
.instruction
|= (size
>> 3) << 7;
12047 inst
.instruction
|= (size
& 0x7) << 19;
12049 inst
.instruction
|= (uval
!= 0) << 24;
12051 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12055 do_neon_shl_imm (void)
12057 if (!inst
.operands
[2].isreg
)
12059 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12060 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12061 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12062 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12066 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12067 struct neon_type_el et
= neon_check_type (3, rs
,
12068 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12071 /* VSHL/VQSHL 3-register variants have syntax such as:
12073 whereas other 3-register operations encoded by neon_three_same have
12076 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12078 tmp
= inst
.operands
[2].reg
;
12079 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12080 inst
.operands
[1].reg
= tmp
;
12081 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12082 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12087 do_neon_qshl_imm (void)
12089 if (!inst
.operands
[2].isreg
)
12091 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12092 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12094 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12095 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12096 inst
.operands
[2].imm
);
12100 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12101 struct neon_type_el et
= neon_check_type (3, rs
,
12102 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12105 /* See note in do_neon_shl_imm. */
12106 tmp
= inst
.operands
[2].reg
;
12107 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12108 inst
.operands
[1].reg
= tmp
;
12109 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12110 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12115 do_neon_rshl (void)
12117 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12118 struct neon_type_el et
= neon_check_type (3, rs
,
12119 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12122 tmp
= inst
.operands
[2].reg
;
12123 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12124 inst
.operands
[1].reg
= tmp
;
12125 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12129 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12131 /* Handle .I8 pseudo-instructions. */
12134 /* Unfortunately, this will make everything apart from zero out-of-range.
12135 FIXME is this the intended semantics? There doesn't seem much point in
12136 accepting .I8 if so. */
12137 immediate
|= immediate
<< 8;
12143 if (immediate
== (immediate
& 0x000000ff))
12145 *immbits
= immediate
;
12148 else if (immediate
== (immediate
& 0x0000ff00))
12150 *immbits
= immediate
>> 8;
12153 else if (immediate
== (immediate
& 0x00ff0000))
12155 *immbits
= immediate
>> 16;
12158 else if (immediate
== (immediate
& 0xff000000))
12160 *immbits
= immediate
>> 24;
12163 if ((immediate
& 0xffff) != (immediate
>> 16))
12164 goto bad_immediate
;
12165 immediate
&= 0xffff;
12168 if (immediate
== (immediate
& 0x000000ff))
12170 *immbits
= immediate
;
12173 else if (immediate
== (immediate
& 0x0000ff00))
12175 *immbits
= immediate
>> 8;
12180 first_error (_("immediate value out of range"));
12184 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12188 neon_bits_same_in_bytes (unsigned imm
)
12190 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12191 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12192 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12193 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12196 /* For immediate of above form, return 0bABCD. */
12199 neon_squash_bits (unsigned imm
)
12201 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12202 | ((imm
& 0x01000000) >> 21);
12205 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12208 neon_qfloat_bits (unsigned imm
)
12210 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12213 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12214 the instruction. *OP is passed as the initial value of the op field, and
12215 may be set to a different value depending on the constant (i.e.
12216 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12217 MVN). If the immediate looks like a repeated pattern then also
12218 try smaller element sizes. */
12221 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12222 unsigned *immbits
, int *op
, int size
,
12223 enum neon_el_type type
)
12225 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12227 if (type
== NT_float
&& !float_p
)
12230 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12232 if (size
!= 32 || *op
== 1)
12234 *immbits
= neon_qfloat_bits (immlo
);
12240 if (neon_bits_same_in_bytes (immhi
)
12241 && neon_bits_same_in_bytes (immlo
))
12245 *immbits
= (neon_squash_bits (immhi
) << 4)
12246 | neon_squash_bits (immlo
);
12251 if (immhi
!= immlo
)
12257 if (immlo
== (immlo
& 0x000000ff))
12262 else if (immlo
== (immlo
& 0x0000ff00))
12264 *immbits
= immlo
>> 8;
12267 else if (immlo
== (immlo
& 0x00ff0000))
12269 *immbits
= immlo
>> 16;
12272 else if (immlo
== (immlo
& 0xff000000))
12274 *immbits
= immlo
>> 24;
12277 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12279 *immbits
= (immlo
>> 8) & 0xff;
12282 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12284 *immbits
= (immlo
>> 16) & 0xff;
12288 if ((immlo
& 0xffff) != (immlo
>> 16))
12295 if (immlo
== (immlo
& 0x000000ff))
12300 else if (immlo
== (immlo
& 0x0000ff00))
12302 *immbits
= immlo
>> 8;
12306 if ((immlo
& 0xff) != (immlo
>> 8))
12311 if (immlo
== (immlo
& 0x000000ff))
12313 /* Don't allow MVN with 8-bit immediate. */
12323 /* Write immediate bits [7:0] to the following locations:
12325 |28/24|23 19|18 16|15 4|3 0|
12326 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12328 This function is used by VMOV/VMVN/VORR/VBIC. */
12331 neon_write_immbits (unsigned immbits
)
12333 inst
.instruction
|= immbits
& 0xf;
12334 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12335 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12338 /* Invert low-order SIZE bits of XHI:XLO. */
12341 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12343 unsigned immlo
= xlo
? *xlo
: 0;
12344 unsigned immhi
= xhi
? *xhi
: 0;
12349 immlo
= (~immlo
) & 0xff;
12353 immlo
= (~immlo
) & 0xffff;
12357 immhi
= (~immhi
) & 0xffffffff;
12358 /* fall through. */
12361 immlo
= (~immlo
) & 0xffffffff;
12376 do_neon_logic (void)
12378 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12380 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12381 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12382 /* U bit and size field were set as part of the bitmask. */
12383 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12384 neon_three_same (neon_quad (rs
), 0, -1);
12388 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12389 struct neon_type_el et
= neon_check_type (2, rs
,
12390 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12391 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
12395 if (et
.type
== NT_invtype
)
12398 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12400 immbits
= inst
.operands
[1].imm
;
12403 /* .i64 is a pseudo-op, so the immediate must be a repeating
12405 if (immbits
!= (inst
.operands
[1].regisimm
?
12406 inst
.operands
[1].reg
: 0))
12408 /* Set immbits to an invalid constant. */
12409 immbits
= 0xdeadbeef;
12416 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12420 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12424 /* Pseudo-instruction for VBIC. */
12425 neon_invert_size (&immbits
, 0, et
.size
);
12426 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12430 /* Pseudo-instruction for VORR. */
12431 neon_invert_size (&immbits
, 0, et
.size
);
12432 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12442 inst
.instruction
|= neon_quad (rs
) << 6;
12443 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12444 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12445 inst
.instruction
|= cmode
<< 8;
12446 neon_write_immbits (immbits
);
12448 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12453 do_neon_bitfield (void)
12455 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12456 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12457 neon_three_same (neon_quad (rs
), 0, -1);
12461 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12464 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12465 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12467 if (et
.type
== NT_float
)
12469 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12470 neon_three_same (neon_quad (rs
), 0, -1);
12474 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12475 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12480 do_neon_dyadic_if_su (void)
12482 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12486 do_neon_dyadic_if_su_d (void)
12488 /* This version only allow D registers, but that constraint is enforced during
12489 operand parsing so we don't need to do anything extra here. */
12490 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12494 do_neon_dyadic_if_i_d (void)
12496 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12497 affected if we specify unsigned args. */
12498 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12501 enum vfp_or_neon_is_neon_bits
12504 NEON_CHECK_ARCH
= 2
12507 /* Call this function if an instruction which may have belonged to the VFP or
12508 Neon instruction sets, but turned out to be a Neon instruction (due to the
12509 operand types involved, etc.). We have to check and/or fix-up a couple of
12512 - Make sure the user hasn't attempted to make a Neon instruction
12514 - Alter the value in the condition code field if necessary.
12515 - Make sure that the arch supports Neon instructions.
12517 Which of these operations take place depends on bits from enum
12518 vfp_or_neon_is_neon_bits.
12520 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12521 current instruction's condition is COND_ALWAYS, the condition field is
12522 changed to inst.uncond_value. This is necessary because instructions shared
12523 between VFP and Neon may be conditional for the VFP variants only, and the
12524 unconditional Neon version must have, e.g., 0xF in the condition field. */
12527 vfp_or_neon_is_neon (unsigned check
)
12529 /* Conditions are always legal in Thumb mode (IT blocks). */
12530 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12532 if (inst
.cond
!= COND_ALWAYS
)
12534 first_error (_(BAD_COND
));
12537 if (inst
.uncond_value
!= -1)
12538 inst
.instruction
|= inst
.uncond_value
<< 28;
12541 if ((check
& NEON_CHECK_ARCH
)
12542 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12544 first_error (_(BAD_FPU
));
12552 do_neon_addsub_if_i (void)
12554 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12557 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12560 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12561 affected if we specify unsigned args. */
12562 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12565 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12567 V<op> A,B (A is operand 0, B is operand 2)
12572 so handle that case specially. */
12575 neon_exchange_operands (void)
12577 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12578 if (inst
.operands
[1].present
)
12580 /* Swap operands[1] and operands[2]. */
12581 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12582 inst
.operands
[1] = inst
.operands
[2];
12583 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12587 inst
.operands
[1] = inst
.operands
[2];
12588 inst
.operands
[2] = inst
.operands
[0];
12593 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12595 if (inst
.operands
[2].isreg
)
12598 neon_exchange_operands ();
12599 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12603 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12604 struct neon_type_el et
= neon_check_type (2, rs
,
12605 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12607 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12608 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12609 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12610 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12611 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12612 inst
.instruction
|= neon_quad (rs
) << 6;
12613 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12614 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12616 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12623 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12627 do_neon_cmp_inv (void)
12629 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12635 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12638 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12639 scalars, which are encoded in 5 bits, M : Rm.
12640 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12641 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12645 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12647 unsigned regno
= NEON_SCALAR_REG (scalar
);
12648 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12653 if (regno
> 7 || elno
> 3)
12655 return regno
| (elno
<< 3);
12658 if (regno
> 15 || elno
> 1)
12660 return regno
| (elno
<< 4);
12664 first_error (_("scalar out of range for multiply instruction"));
12670 /* Encode multiply / multiply-accumulate scalar instructions. */
12673 neon_mul_mac (struct neon_type_el et
, int ubit
)
12677 /* Give a more helpful error message if we have an invalid type. */
12678 if (et
.type
== NT_invtype
)
12681 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12682 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12683 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12684 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12685 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12686 inst
.instruction
|= LOW4 (scalar
);
12687 inst
.instruction
|= HI1 (scalar
) << 5;
12688 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12689 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12690 inst
.instruction
|= (ubit
!= 0) << 24;
12692 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12696 do_neon_mac_maybe_scalar (void)
12698 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12701 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12704 if (inst
.operands
[2].isscalar
)
12706 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12707 struct neon_type_el et
= neon_check_type (3, rs
,
12708 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12709 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12710 neon_mul_mac (et
, neon_quad (rs
));
12714 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12715 affected if we specify unsigned args. */
12716 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12723 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12724 struct neon_type_el et
= neon_check_type (3, rs
,
12725 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12726 neon_three_same (neon_quad (rs
), 0, et
.size
);
12729 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12730 same types as the MAC equivalents. The polynomial type for this instruction
12731 is encoded the same as the integer type. */
12736 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12739 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12742 if (inst
.operands
[2].isscalar
)
12743 do_neon_mac_maybe_scalar ();
12745 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12749 do_neon_qdmulh (void)
12751 if (inst
.operands
[2].isscalar
)
12753 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12754 struct neon_type_el et
= neon_check_type (3, rs
,
12755 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12756 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12757 neon_mul_mac (et
, neon_quad (rs
));
12761 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12762 struct neon_type_el et
= neon_check_type (3, rs
,
12763 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12764 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12765 /* The U bit (rounding) comes from bit mask. */
12766 neon_three_same (neon_quad (rs
), 0, et
.size
);
12771 do_neon_fcmp_absolute (void)
12773 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12774 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12775 /* Size field comes from bit mask. */
12776 neon_three_same (neon_quad (rs
), 1, -1);
12780 do_neon_fcmp_absolute_inv (void)
12782 neon_exchange_operands ();
12783 do_neon_fcmp_absolute ();
12787 do_neon_step (void)
12789 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12790 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12791 neon_three_same (neon_quad (rs
), 0, -1);
12795 do_neon_abs_neg (void)
12797 enum neon_shape rs
;
12798 struct neon_type_el et
;
12800 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12803 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12806 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12807 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12809 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12810 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12811 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12812 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12813 inst
.instruction
|= neon_quad (rs
) << 6;
12814 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12815 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12817 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12823 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12824 struct neon_type_el et
= neon_check_type (2, rs
,
12825 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12826 int imm
= inst
.operands
[2].imm
;
12827 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12828 _("immediate out of range for insert"));
12829 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12835 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12836 struct neon_type_el et
= neon_check_type (2, rs
,
12837 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12838 int imm
= inst
.operands
[2].imm
;
12839 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12840 _("immediate out of range for insert"));
12841 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12845 do_neon_qshlu_imm (void)
12847 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12848 struct neon_type_el et
= neon_check_type (2, rs
,
12849 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12850 int imm
= inst
.operands
[2].imm
;
12851 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12852 _("immediate out of range for shift"));
12853 /* Only encodes the 'U present' variant of the instruction.
12854 In this case, signed types have OP (bit 8) set to 0.
12855 Unsigned types have OP set to 1. */
12856 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12857 /* The rest of the bits are the same as other immediate shifts. */
12858 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12862 do_neon_qmovn (void)
12864 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12865 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12866 /* Saturating move where operands can be signed or unsigned, and the
12867 destination has the same signedness. */
12868 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12869 if (et
.type
== NT_unsigned
)
12870 inst
.instruction
|= 0xc0;
12872 inst
.instruction
|= 0x80;
12873 neon_two_same (0, 1, et
.size
/ 2);
12877 do_neon_qmovun (void)
12879 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12880 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12881 /* Saturating move with unsigned results. Operands must be signed. */
12882 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12883 neon_two_same (0, 1, et
.size
/ 2);
12887 do_neon_rshift_sat_narrow (void)
12889 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12890 or unsigned. If operands are unsigned, results must also be unsigned. */
12891 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12892 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12893 int imm
= inst
.operands
[2].imm
;
12894 /* This gets the bounds check, size encoding and immediate bits calculation
12898 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12899 VQMOVN.I<size> <Dd>, <Qm>. */
12902 inst
.operands
[2].present
= 0;
12903 inst
.instruction
= N_MNEM_vqmovn
;
12908 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12909 _("immediate out of range"));
12910 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12914 do_neon_rshift_sat_narrow_u (void)
12916 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12917 or unsigned. If operands are unsigned, results must also be unsigned. */
12918 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12919 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12920 int imm
= inst
.operands
[2].imm
;
12921 /* This gets the bounds check, size encoding and immediate bits calculation
12925 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12926 VQMOVUN.I<size> <Dd>, <Qm>. */
12929 inst
.operands
[2].present
= 0;
12930 inst
.instruction
= N_MNEM_vqmovun
;
12935 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12936 _("immediate out of range"));
12937 /* FIXME: The manual is kind of unclear about what value U should have in
12938 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12940 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12944 do_neon_movn (void)
12946 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12947 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12948 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12949 neon_two_same (0, 1, et
.size
/ 2);
12953 do_neon_rshift_narrow (void)
12955 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12956 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12957 int imm
= inst
.operands
[2].imm
;
12958 /* This gets the bounds check, size encoding and immediate bits calculation
12962 /* If immediate is zero then we are a pseudo-instruction for
12963 VMOVN.I<size> <Dd>, <Qm> */
12966 inst
.operands
[2].present
= 0;
12967 inst
.instruction
= N_MNEM_vmovn
;
12972 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12973 _("immediate out of range for narrowing operation"));
12974 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12978 do_neon_shll (void)
12980 /* FIXME: Type checking when lengthening. */
12981 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12982 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12983 unsigned imm
= inst
.operands
[2].imm
;
12985 if (imm
== et
.size
)
12987 /* Maximum shift variant. */
12988 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12989 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12990 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12991 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12992 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12993 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12995 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12999 /* A more-specific type check for non-max versions. */
13000 et
= neon_check_type (2, NS_QDI
,
13001 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13002 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13003 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13007 /* Check the various types for the VCVT instruction, and return which version
13008 the current instruction is. */
13011 neon_cvt_flavour (enum neon_shape rs
)
13013 #define CVT_VAR(C,X,Y) \
13014 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13015 if (et.type != NT_invtype) \
13017 inst.error = NULL; \
13020 struct neon_type_el et
;
13021 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13022 || rs
== NS_FF
) ? N_VFP
: 0;
13023 /* The instruction versions which take an immediate take one register
13024 argument, which is extended to the width of the full register. Thus the
13025 "source" and "destination" registers must have the same width. Hack that
13026 here by making the size equal to the key (wider, in this case) operand. */
13027 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13029 CVT_VAR (0, N_S32
, N_F32
);
13030 CVT_VAR (1, N_U32
, N_F32
);
13031 CVT_VAR (2, N_F32
, N_S32
);
13032 CVT_VAR (3, N_F32
, N_U32
);
13033 /* Half-precision conversions. */
13034 CVT_VAR (4, N_F32
, N_F16
);
13035 CVT_VAR (5, N_F16
, N_F32
);
13039 /* VFP instructions. */
13040 CVT_VAR (6, N_F32
, N_F64
);
13041 CVT_VAR (7, N_F64
, N_F32
);
13042 CVT_VAR (8, N_S32
, N_F64
| key
);
13043 CVT_VAR (9, N_U32
, N_F64
| key
);
13044 CVT_VAR (10, N_F64
| key
, N_S32
);
13045 CVT_VAR (11, N_F64
| key
, N_U32
);
13046 /* VFP instructions with bitshift. */
13047 CVT_VAR (12, N_F32
| key
, N_S16
);
13048 CVT_VAR (13, N_F32
| key
, N_U16
);
13049 CVT_VAR (14, N_F64
| key
, N_S16
);
13050 CVT_VAR (15, N_F64
| key
, N_U16
);
13051 CVT_VAR (16, N_S16
, N_F32
| key
);
13052 CVT_VAR (17, N_U16
, N_F32
| key
);
13053 CVT_VAR (18, N_S16
, N_F64
| key
);
13054 CVT_VAR (19, N_U16
, N_F64
| key
);
13060 /* Neon-syntax VFP conversions. */
13063 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13065 const char *opname
= 0;
13067 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13069 /* Conversions with immediate bitshift. */
13070 const char *enc
[] =
13094 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13096 opname
= enc
[flavour
];
13097 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13098 _("operands 0 and 1 must be the same register"));
13099 inst
.operands
[1] = inst
.operands
[2];
13100 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13105 /* Conversions without bitshift. */
13106 const char *enc
[] =
13122 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13123 opname
= enc
[flavour
];
13127 do_vfp_nsyn_opcode (opname
);
13131 do_vfp_nsyn_cvtz (void)
13133 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13134 int flavour
= neon_cvt_flavour (rs
);
13135 const char *enc
[] =
13149 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13150 do_vfp_nsyn_opcode (enc
[flavour
]);
13156 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13157 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13158 int flavour
= neon_cvt_flavour (rs
);
13160 /* VFP rather than Neon conversions. */
13163 do_vfp_nsyn_cvt (rs
, flavour
);
13173 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13175 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13178 /* Fixed-point conversion with #0 immediate is encoded as an
13179 integer conversion. */
13180 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13182 immbits
= 32 - inst
.operands
[2].imm
;
13183 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13185 inst
.instruction
|= enctab
[flavour
];
13186 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13187 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13188 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13189 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13190 inst
.instruction
|= neon_quad (rs
) << 6;
13191 inst
.instruction
|= 1 << 21;
13192 inst
.instruction
|= immbits
<< 16;
13194 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13202 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13204 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13206 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13210 inst
.instruction
|= enctab
[flavour
];
13212 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13213 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13214 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13215 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13216 inst
.instruction
|= neon_quad (rs
) << 6;
13217 inst
.instruction
|= 2 << 18;
13219 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13223 /* Half-precision conversions for Advanced SIMD -- neon. */
13228 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13230 as_bad (_("operand size must match register width"));
13235 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13237 as_bad (_("operand size must match register width"));
13242 inst
.instruction
= 0x3b60600;
13244 inst
.instruction
= 0x3b60700;
13246 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13247 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13248 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13249 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13250 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13254 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13255 do_vfp_nsyn_cvt (rs
, flavour
);
13260 do_neon_cvtb (void)
13262 inst
.instruction
= 0xeb20a40;
13264 /* The sizes are attached to the mnemonic. */
13265 if (inst
.vectype
.el
[0].type
!= NT_invtype
13266 && inst
.vectype
.el
[0].size
== 16)
13267 inst
.instruction
|= 0x00010000;
13269 /* Programmer's syntax: the sizes are attached to the operands. */
13270 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13271 && inst
.operands
[0].vectype
.size
== 16)
13272 inst
.instruction
|= 0x00010000;
13274 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13275 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13276 do_vfp_cond_or_thumb ();
13281 do_neon_cvtt (void)
13284 inst
.instruction
|= 0x80;
13288 neon_move_immediate (void)
13290 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13291 struct neon_type_el et
= neon_check_type (2, rs
,
13292 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13293 unsigned immlo
, immhi
= 0, immbits
;
13294 int op
, cmode
, float_p
;
13296 constraint (et
.type
== NT_invtype
,
13297 _("operand size must be specified for immediate VMOV"));
13299 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13300 op
= (inst
.instruction
& (1 << 5)) != 0;
13302 immlo
= inst
.operands
[1].imm
;
13303 if (inst
.operands
[1].regisimm
)
13304 immhi
= inst
.operands
[1].reg
;
13306 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13307 _("immediate has bits set outside the operand size"));
13309 float_p
= inst
.operands
[1].immisfloat
;
13311 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13312 et
.size
, et
.type
)) == FAIL
)
13314 /* Invert relevant bits only. */
13315 neon_invert_size (&immlo
, &immhi
, et
.size
);
13316 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13317 with one or the other; those cases are caught by
13318 neon_cmode_for_move_imm. */
13320 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
13321 &op
, et
.size
, et
.type
)) == FAIL
)
13323 first_error (_("immediate out of range"));
13328 inst
.instruction
&= ~(1 << 5);
13329 inst
.instruction
|= op
<< 5;
13331 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13332 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13333 inst
.instruction
|= neon_quad (rs
) << 6;
13334 inst
.instruction
|= cmode
<< 8;
13336 neon_write_immbits (immbits
);
13342 if (inst
.operands
[1].isreg
)
13344 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13346 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13347 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13348 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13349 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13350 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13351 inst
.instruction
|= neon_quad (rs
) << 6;
13355 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13356 neon_move_immediate ();
13359 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13362 /* Encode instructions of form:
13364 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13365 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
13368 neon_mixed_length (struct neon_type_el et
, unsigned size
)
13370 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13371 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13372 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13373 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13374 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13375 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13376 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
13377 inst
.instruction
|= neon_logbits (size
) << 20;
13379 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13383 do_neon_dyadic_long (void)
13385 /* FIXME: Type checking for lengthening op. */
13386 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13387 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13388 neon_mixed_length (et
, et
.size
);
13392 do_neon_abal (void)
13394 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13395 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13396 neon_mixed_length (et
, et
.size
);
13400 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
13402 if (inst
.operands
[2].isscalar
)
13404 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
13405 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
13406 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13407 neon_mul_mac (et
, et
.type
== NT_unsigned
);
13411 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13412 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
13413 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13414 neon_mixed_length (et
, et
.size
);
13419 do_neon_mac_maybe_scalar_long (void)
13421 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13425 do_neon_dyadic_wide (void)
13427 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13428 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13429 neon_mixed_length (et
, et
.size
);
13433 do_neon_dyadic_narrow (void)
13435 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13436 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13437 /* Operand sign is unimportant, and the U bit is part of the opcode,
13438 so force the operand type to integer. */
13439 et
.type
= NT_integer
;
13440 neon_mixed_length (et
, et
.size
/ 2);
13444 do_neon_mul_sat_scalar_long (void)
13446 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13450 do_neon_vmull (void)
13452 if (inst
.operands
[2].isscalar
)
13453 do_neon_mac_maybe_scalar_long ();
13456 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13457 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13458 if (et
.type
== NT_poly
)
13459 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
13461 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13462 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13463 zero. Should be OK as-is. */
13464 neon_mixed_length (et
, et
.size
);
13471 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
13472 struct neon_type_el et
= neon_check_type (3, rs
,
13473 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13474 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
13476 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
13477 _("shift out of range"));
13478 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13479 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13480 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13481 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13482 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13483 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13484 inst
.instruction
|= neon_quad (rs
) << 6;
13485 inst
.instruction
|= imm
<< 8;
13487 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13493 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13494 struct neon_type_el et
= neon_check_type (2, rs
,
13495 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13496 unsigned op
= (inst
.instruction
>> 7) & 3;
13497 /* N (width of reversed regions) is encoded as part of the bitmask. We
13498 extract it here to check the elements to be reversed are smaller.
13499 Otherwise we'd get a reserved instruction. */
13500 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
13501 assert (elsize
!= 0);
13502 constraint (et
.size
>= elsize
,
13503 _("elements must be smaller than reversal region"));
13504 neon_two_same (neon_quad (rs
), 1, et
.size
);
13510 if (inst
.operands
[1].isscalar
)
13512 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
13513 struct neon_type_el et
= neon_check_type (2, rs
,
13514 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13515 unsigned sizebits
= et
.size
>> 3;
13516 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13517 int logsize
= neon_logbits (et
.size
);
13518 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13520 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13523 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13524 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13525 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13526 inst
.instruction
|= LOW4 (dm
);
13527 inst
.instruction
|= HI1 (dm
) << 5;
13528 inst
.instruction
|= neon_quad (rs
) << 6;
13529 inst
.instruction
|= x
<< 17;
13530 inst
.instruction
|= sizebits
<< 16;
13532 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13536 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13537 struct neon_type_el et
= neon_check_type (2, rs
,
13538 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13539 /* Duplicate ARM register to lanes of vector. */
13540 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13543 case 8: inst
.instruction
|= 0x400000; break;
13544 case 16: inst
.instruction
|= 0x000020; break;
13545 case 32: inst
.instruction
|= 0x000000; break;
13548 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13549 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13550 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13551 inst
.instruction
|= neon_quad (rs
) << 21;
13552 /* The encoding for this instruction is identical for the ARM and Thumb
13553 variants, except for the condition field. */
13554 do_vfp_cond_or_thumb ();
13558 /* VMOV has particularly many variations. It can be one of:
13559 0. VMOV<c><q> <Qd>, <Qm>
13560 1. VMOV<c><q> <Dd>, <Dm>
13561 (Register operations, which are VORR with Rm = Rn.)
13562 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13563 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13565 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13566 (ARM register to scalar.)
13567 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13568 (Two ARM registers to vector.)
13569 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13570 (Scalar to ARM register.)
13571 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13572 (Vector to two ARM registers.)
13573 8. VMOV.F32 <Sd>, <Sm>
13574 9. VMOV.F64 <Dd>, <Dm>
13575 (VFP register moves.)
13576 10. VMOV.F32 <Sd>, #imm
13577 11. VMOV.F64 <Dd>, #imm
13578 (VFP float immediate load.)
13579 12. VMOV <Rd>, <Sm>
13580 (VFP single to ARM reg.)
13581 13. VMOV <Sd>, <Rm>
13582 (ARM reg to VFP single.)
13583 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13584 (Two ARM regs to two VFP singles.)
13585 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13586 (Two VFP singles to two ARM regs.)
13588 These cases can be disambiguated using neon_select_shape, except cases 1/9
13589 and 3/11 which depend on the operand type too.
13591 All the encoded bits are hardcoded by this function.
13593 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13594 Cases 5, 7 may be used with VFPv2 and above.
13596 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13597 can specify a type where it doesn't make sense to, and is ignored). */
13602 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13603 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13605 struct neon_type_el et
;
13606 const char *ldconst
= 0;
13610 case NS_DD
: /* case 1/9. */
13611 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13612 /* It is not an error here if no type is given. */
13614 if (et
.type
== NT_float
&& et
.size
== 64)
13616 do_vfp_nsyn_opcode ("fcpyd");
13619 /* fall through. */
13621 case NS_QQ
: /* case 0/1. */
13623 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13625 /* The architecture manual I have doesn't explicitly state which
13626 value the U bit should have for register->register moves, but
13627 the equivalent VORR instruction has U = 0, so do that. */
13628 inst
.instruction
= 0x0200110;
13629 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13630 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13631 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13632 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13633 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13634 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13635 inst
.instruction
|= neon_quad (rs
) << 6;
13637 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13641 case NS_DI
: /* case 3/11. */
13642 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13644 if (et
.type
== NT_float
&& et
.size
== 64)
13646 /* case 11 (fconstd). */
13647 ldconst
= "fconstd";
13648 goto encode_fconstd
;
13650 /* fall through. */
13652 case NS_QI
: /* case 2/3. */
13653 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13655 inst
.instruction
= 0x0800010;
13656 neon_move_immediate ();
13657 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13660 case NS_SR
: /* case 4. */
13662 unsigned bcdebits
= 0;
13663 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13664 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13665 int logsize
= neon_logbits (et
.size
);
13666 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13667 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13669 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13671 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13672 && et
.size
!= 32, _(BAD_FPU
));
13673 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13674 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13678 case 8: bcdebits
= 0x8; break;
13679 case 16: bcdebits
= 0x1; break;
13680 case 32: bcdebits
= 0x0; break;
13684 bcdebits
|= x
<< logsize
;
13686 inst
.instruction
= 0xe000b10;
13687 do_vfp_cond_or_thumb ();
13688 inst
.instruction
|= LOW4 (dn
) << 16;
13689 inst
.instruction
|= HI1 (dn
) << 7;
13690 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13691 inst
.instruction
|= (bcdebits
& 3) << 5;
13692 inst
.instruction
|= (bcdebits
>> 2) << 21;
13696 case NS_DRR
: /* case 5 (fmdrr). */
13697 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13700 inst
.instruction
= 0xc400b10;
13701 do_vfp_cond_or_thumb ();
13702 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13703 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13704 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13705 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13708 case NS_RS
: /* case 6. */
13710 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13711 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
13712 unsigned logsize
= neon_logbits (et
.size
);
13713 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13714 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
13715 unsigned abcdebits
= 0;
13717 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13719 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13720 && et
.size
!= 32, _(BAD_FPU
));
13721 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13722 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13726 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
13727 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
13728 case 32: abcdebits
= 0x00; break;
13732 abcdebits
|= x
<< logsize
;
13733 inst
.instruction
= 0xe100b10;
13734 do_vfp_cond_or_thumb ();
13735 inst
.instruction
|= LOW4 (dn
) << 16;
13736 inst
.instruction
|= HI1 (dn
) << 7;
13737 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13738 inst
.instruction
|= (abcdebits
& 3) << 5;
13739 inst
.instruction
|= (abcdebits
>> 2) << 21;
13743 case NS_RRD
: /* case 7 (fmrrd). */
13744 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13747 inst
.instruction
= 0xc500b10;
13748 do_vfp_cond_or_thumb ();
13749 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13750 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13751 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13752 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13755 case NS_FF
: /* case 8 (fcpys). */
13756 do_vfp_nsyn_opcode ("fcpys");
13759 case NS_FI
: /* case 10 (fconsts). */
13760 ldconst
= "fconsts";
13762 if (is_quarter_float (inst
.operands
[1].imm
))
13764 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13765 do_vfp_nsyn_opcode (ldconst
);
13768 first_error (_("immediate out of range"));
13771 case NS_RF
: /* case 12 (fmrs). */
13772 do_vfp_nsyn_opcode ("fmrs");
13775 case NS_FR
: /* case 13 (fmsr). */
13776 do_vfp_nsyn_opcode ("fmsr");
13779 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13780 (one of which is a list), but we have parsed four. Do some fiddling to
13781 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13783 case NS_RRFF
: /* case 14 (fmrrs). */
13784 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13785 _("VFP registers must be adjacent"));
13786 inst
.operands
[2].imm
= 2;
13787 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13788 do_vfp_nsyn_opcode ("fmrrs");
13791 case NS_FFRR
: /* case 15 (fmsrr). */
13792 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13793 _("VFP registers must be adjacent"));
13794 inst
.operands
[1] = inst
.operands
[2];
13795 inst
.operands
[2] = inst
.operands
[3];
13796 inst
.operands
[0].imm
= 2;
13797 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13798 do_vfp_nsyn_opcode ("fmsrr");
13807 do_neon_rshift_round_imm (void)
13809 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13810 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13811 int imm
= inst
.operands
[2].imm
;
13813 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13816 inst
.operands
[2].present
= 0;
13821 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13822 _("immediate out of range for shift"));
13823 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13828 do_neon_movl (void)
13830 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13831 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13832 unsigned sizebits
= et
.size
>> 3;
13833 inst
.instruction
|= sizebits
<< 19;
13834 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13840 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13841 struct neon_type_el et
= neon_check_type (2, rs
,
13842 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13843 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13844 neon_two_same (neon_quad (rs
), 1, et
.size
);
13848 do_neon_zip_uzp (void)
13850 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13851 struct neon_type_el et
= neon_check_type (2, rs
,
13852 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13853 if (rs
== NS_DD
&& et
.size
== 32)
13855 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13856 inst
.instruction
= N_MNEM_vtrn
;
13860 neon_two_same (neon_quad (rs
), 1, et
.size
);
13864 do_neon_sat_abs_neg (void)
13866 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13867 struct neon_type_el et
= neon_check_type (2, rs
,
13868 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13869 neon_two_same (neon_quad (rs
), 1, et
.size
);
13873 do_neon_pair_long (void)
13875 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13876 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13877 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13878 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13879 neon_two_same (neon_quad (rs
), 1, et
.size
);
13883 do_neon_recip_est (void)
13885 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13886 struct neon_type_el et
= neon_check_type (2, rs
,
13887 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13888 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13889 neon_two_same (neon_quad (rs
), 1, et
.size
);
13895 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13896 struct neon_type_el et
= neon_check_type (2, rs
,
13897 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13898 neon_two_same (neon_quad (rs
), 1, et
.size
);
13904 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13905 struct neon_type_el et
= neon_check_type (2, rs
,
13906 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13907 neon_two_same (neon_quad (rs
), 1, et
.size
);
13913 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13914 struct neon_type_el et
= neon_check_type (2, rs
,
13915 N_EQK
| N_INT
, N_8
| N_KEY
);
13916 neon_two_same (neon_quad (rs
), 1, et
.size
);
13922 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13923 neon_two_same (neon_quad (rs
), 1, -1);
13927 do_neon_tbl_tbx (void)
13929 unsigned listlenbits
;
13930 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13932 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13934 first_error (_("bad list length for table lookup"));
13938 listlenbits
= inst
.operands
[1].imm
- 1;
13939 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13940 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13941 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13942 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13943 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13944 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13945 inst
.instruction
|= listlenbits
<< 8;
13947 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13951 do_neon_ldm_stm (void)
13953 /* P, U and L bits are part of bitmask. */
13954 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13955 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13957 if (inst
.operands
[1].issingle
)
13959 do_vfp_nsyn_ldm_stm (is_dbmode
);
13963 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13964 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13966 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13967 _("register list must contain at least 1 and at most 16 "
13970 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13971 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13972 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13973 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13975 inst
.instruction
|= offsetbits
;
13977 do_vfp_cond_or_thumb ();
13981 do_neon_ldr_str (void)
13983 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13985 if (inst
.operands
[0].issingle
)
13988 do_vfp_nsyn_opcode ("flds");
13990 do_vfp_nsyn_opcode ("fsts");
13995 do_vfp_nsyn_opcode ("fldd");
13997 do_vfp_nsyn_opcode ("fstd");
14001 /* "interleave" version also handles non-interleaving register VLD1/VST1
14005 do_neon_ld_st_interleave (void)
14007 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14008 N_8
| N_16
| N_32
| N_64
);
14009 unsigned alignbits
= 0;
14011 /* The bits in this table go:
14012 0: register stride of one (0) or two (1)
14013 1,2: register list length, minus one (1, 2, 3, 4).
14014 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14015 We use -1 for invalid entries. */
14016 const int typetable
[] =
14018 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14019 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14020 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14021 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14025 if (et
.type
== NT_invtype
)
14028 if (inst
.operands
[1].immisalign
)
14029 switch (inst
.operands
[1].imm
>> 8)
14031 case 64: alignbits
= 1; break;
14033 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14034 goto bad_alignment
;
14038 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14039 goto bad_alignment
;
14044 first_error (_("bad alignment"));
14048 inst
.instruction
|= alignbits
<< 4;
14049 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14051 /* Bits [4:6] of the immediate in a list specifier encode register stride
14052 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14053 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14054 up the right value for "type" in a table based on this value and the given
14055 list style, then stick it back. */
14056 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14057 | (((inst
.instruction
>> 8) & 3) << 3);
14059 typebits
= typetable
[idx
];
14061 constraint (typebits
== -1, _("bad list type for instruction"));
14063 inst
.instruction
&= ~0xf00;
14064 inst
.instruction
|= typebits
<< 8;
14067 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14068 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14069 otherwise. The variable arguments are a list of pairs of legal (size, align)
14070 values, terminated with -1. */
14073 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14076 int result
= FAIL
, thissize
, thisalign
;
14078 if (!inst
.operands
[1].immisalign
)
14084 va_start (ap
, do_align
);
14088 thissize
= va_arg (ap
, int);
14089 if (thissize
== -1)
14091 thisalign
= va_arg (ap
, int);
14093 if (size
== thissize
&& align
== thisalign
)
14096 while (result
!= SUCCESS
);
14100 if (result
== SUCCESS
)
14103 first_error (_("unsupported alignment for instruction"));
14109 do_neon_ld_st_lane (void)
14111 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14112 int align_good
, do_align
= 0;
14113 int logsize
= neon_logbits (et
.size
);
14114 int align
= inst
.operands
[1].imm
>> 8;
14115 int n
= (inst
.instruction
>> 8) & 3;
14116 int max_el
= 64 / et
.size
;
14118 if (et
.type
== NT_invtype
)
14121 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14122 _("bad list length"));
14123 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14124 _("scalar index out of range"));
14125 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14127 _("stride of 2 unavailable when element size is 8"));
14131 case 0: /* VLD1 / VST1. */
14132 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14134 if (align_good
== FAIL
)
14138 unsigned alignbits
= 0;
14141 case 16: alignbits
= 0x1; break;
14142 case 32: alignbits
= 0x3; break;
14145 inst
.instruction
|= alignbits
<< 4;
14149 case 1: /* VLD2 / VST2. */
14150 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14152 if (align_good
== FAIL
)
14155 inst
.instruction
|= 1 << 4;
14158 case 2: /* VLD3 / VST3. */
14159 constraint (inst
.operands
[1].immisalign
,
14160 _("can't use alignment with this instruction"));
14163 case 3: /* VLD4 / VST4. */
14164 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14165 16, 64, 32, 64, 32, 128, -1);
14166 if (align_good
== FAIL
)
14170 unsigned alignbits
= 0;
14173 case 8: alignbits
= 0x1; break;
14174 case 16: alignbits
= 0x1; break;
14175 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14178 inst
.instruction
|= alignbits
<< 4;
14185 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14186 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14187 inst
.instruction
|= 1 << (4 + logsize
);
14189 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14190 inst
.instruction
|= logsize
<< 10;
14193 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14196 do_neon_ld_dup (void)
14198 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14199 int align_good
, do_align
= 0;
14201 if (et
.type
== NT_invtype
)
14204 switch ((inst
.instruction
>> 8) & 3)
14206 case 0: /* VLD1. */
14207 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14208 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14209 &do_align
, 16, 16, 32, 32, -1);
14210 if (align_good
== FAIL
)
14212 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14215 case 2: inst
.instruction
|= 1 << 5; break;
14216 default: first_error (_("bad list length")); return;
14218 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14221 case 1: /* VLD2. */
14222 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14223 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14224 if (align_good
== FAIL
)
14226 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14227 _("bad list length"));
14228 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14229 inst
.instruction
|= 1 << 5;
14230 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14233 case 2: /* VLD3. */
14234 constraint (inst
.operands
[1].immisalign
,
14235 _("can't use alignment with this instruction"));
14236 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14237 _("bad list length"));
14238 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14239 inst
.instruction
|= 1 << 5;
14240 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14243 case 3: /* VLD4. */
14245 int align
= inst
.operands
[1].imm
>> 8;
14246 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14247 16, 64, 32, 64, 32, 128, -1);
14248 if (align_good
== FAIL
)
14250 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14251 _("bad list length"));
14252 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14253 inst
.instruction
|= 1 << 5;
14254 if (et
.size
== 32 && align
== 128)
14255 inst
.instruction
|= 0x3 << 6;
14257 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14264 inst
.instruction
|= do_align
<< 4;
14267 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14268 apart from bits [11:4]. */
14271 do_neon_ldx_stx (void)
14273 switch (NEON_LANE (inst
.operands
[0].imm
))
14275 case NEON_INTERLEAVE_LANES
:
14276 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
14277 do_neon_ld_st_interleave ();
14280 case NEON_ALL_LANES
:
14281 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
14286 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
14287 do_neon_ld_st_lane ();
14290 /* L bit comes from bit mask. */
14291 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14292 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14293 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14295 if (inst
.operands
[1].postind
)
14297 int postreg
= inst
.operands
[1].imm
& 0xf;
14298 constraint (!inst
.operands
[1].immisreg
,
14299 _("post-index must be a register"));
14300 constraint (postreg
== 0xd || postreg
== 0xf,
14301 _("bad register for post-index"));
14302 inst
.instruction
|= postreg
;
14304 else if (inst
.operands
[1].writeback
)
14306 inst
.instruction
|= 0xd;
14309 inst
.instruction
|= 0xf;
14312 inst
.instruction
|= 0xf9000000;
14314 inst
.instruction
|= 0xf4000000;
14317 /* Overall per-instruction processing. */
14319 /* We need to be able to fix up arbitrary expressions in some statements.
14320 This is so that we can handle symbols that are an arbitrary distance from
14321 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
14322 which returns part of an address in a form which will be valid for
14323 a data instruction. We do this by pushing the expression into a symbol
14324 in the expr_section, and creating a fix for that. */
14327 fix_new_arm (fragS
* frag
,
14342 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
14346 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
14351 /* Mark whether the fix is to a THUMB instruction, or an ARM
14353 new_fix
->tc_fix_data
= thumb_mode
;
14356 /* Create a frg for an instruction requiring relaxation. */
14358 output_relax_insn (void)
14364 /* The size of the instruction is unknown, so tie the debug info to the
14365 start of the instruction. */
14366 dwarf2_emit_insn (0);
14368 switch (inst
.reloc
.exp
.X_op
)
14371 sym
= inst
.reloc
.exp
.X_add_symbol
;
14372 offset
= inst
.reloc
.exp
.X_add_number
;
14376 offset
= inst
.reloc
.exp
.X_add_number
;
14379 sym
= make_expr_symbol (&inst
.reloc
.exp
);
14383 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
14384 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
14385 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
14388 /* Write a 32-bit thumb instruction to buf. */
14390 put_thumb32_insn (char * buf
, unsigned long insn
)
14392 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
14393 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
14397 output_inst (const char * str
)
14403 as_bad ("%s -- `%s'", inst
.error
, str
);
14408 output_relax_insn ();
14411 if (inst
.size
== 0)
14414 to
= frag_more (inst
.size
);
14415 /* PR 9814: Record the thumb mode into the current frag so that we know
14416 what type of NOP padding to use, if necessary. We override any previous
14417 setting so that if the mode has changed then the NOPS that we use will
14418 match the encoding of the last instruction in the frag. */
14419 frag_now
->tc_frag_data
= thumb_mode
| MODE_RECORDED
;
14421 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
14423 assert (inst
.size
== (2 * THUMB_SIZE
));
14424 put_thumb32_insn (to
, inst
.instruction
);
14426 else if (inst
.size
> INSN_SIZE
)
14428 assert (inst
.size
== (2 * INSN_SIZE
));
14429 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14430 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14433 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14435 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14436 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14437 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14440 dwarf2_emit_insn (inst
.size
);
14443 /* Tag values used in struct asm_opcode's tag field. */
14446 OT_unconditional
, /* Instruction cannot be conditionalized.
14447 The ARM condition field is still 0xE. */
14448 OT_unconditionalF
, /* Instruction cannot be conditionalized
14449 and carries 0xF in its ARM condition field. */
14450 OT_csuffix
, /* Instruction takes a conditional suffix. */
14451 OT_csuffixF
, /* Some forms of the instruction take a conditional
14452 suffix, others place 0xF where the condition field
14454 OT_cinfix3
, /* Instruction takes a conditional infix,
14455 beginning at character index 3. (In
14456 unified mode, it becomes a suffix.) */
14457 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
14458 tsts, cmps, cmns, and teqs. */
14459 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
14460 character index 3, even in unified mode. Used for
14461 legacy instructions where suffix and infix forms
14462 may be ambiguous. */
14463 OT_csuf_or_in3
, /* Instruction takes either a conditional
14464 suffix or an infix at character index 3. */
14465 OT_odd_infix_unc
, /* This is the unconditional variant of an
14466 instruction that takes a conditional infix
14467 at an unusual position. In unified mode,
14468 this variant will accept a suffix. */
14469 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
14470 are the conditional variants of instructions that
14471 take conditional infixes in unusual positions.
14472 The infix appears at character index
14473 (tag - OT_odd_infix_0). These are not accepted
14474 in unified mode. */
14477 /* Subroutine of md_assemble, responsible for looking up the primary
14478 opcode from the mnemonic the user wrote. STR points to the
14479 beginning of the mnemonic.
14481 This is not simply a hash table lookup, because of conditional
14482 variants. Most instructions have conditional variants, which are
14483 expressed with a _conditional affix_ to the mnemonic. If we were
14484 to encode each conditional variant as a literal string in the opcode
14485 table, it would have approximately 20,000 entries.
14487 Most mnemonics take this affix as a suffix, and in unified syntax,
14488 'most' is upgraded to 'all'. However, in the divided syntax, some
14489 instructions take the affix as an infix, notably the s-variants of
14490 the arithmetic instructions. Of those instructions, all but six
14491 have the infix appear after the third character of the mnemonic.
14493 Accordingly, the algorithm for looking up primary opcodes given
14496 1. Look up the identifier in the opcode table.
14497 If we find a match, go to step U.
14499 2. Look up the last two characters of the identifier in the
14500 conditions table. If we find a match, look up the first N-2
14501 characters of the identifier in the opcode table. If we
14502 find a match, go to step CE.
14504 3. Look up the fourth and fifth characters of the identifier in
14505 the conditions table. If we find a match, extract those
14506 characters from the identifier, and look up the remaining
14507 characters in the opcode table. If we find a match, go
14512 U. Examine the tag field of the opcode structure, in case this is
14513 one of the six instructions with its conditional infix in an
14514 unusual place. If it is, the tag tells us where to find the
14515 infix; look it up in the conditions table and set inst.cond
14516 accordingly. Otherwise, this is an unconditional instruction.
14517 Again set inst.cond accordingly. Return the opcode structure.
14519 CE. Examine the tag field to make sure this is an instruction that
14520 should receive a conditional suffix. If it is not, fail.
14521 Otherwise, set inst.cond from the suffix we already looked up,
14522 and return the opcode structure.
14524 CM. Examine the tag field to make sure this is an instruction that
14525 should receive a conditional infix after the third character.
14526 If it is not, fail. Otherwise, undo the edits to the current
14527 line of input and proceed as for case CE. */
14529 static const struct asm_opcode
*
14530 opcode_lookup (char **str
)
14534 const struct asm_opcode
*opcode
;
14535 const struct asm_cond
*cond
;
14537 bfd_boolean neon_supported
;
14539 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
14541 /* Scan up to the end of the mnemonic, which must end in white space,
14542 '.' (in unified mode, or for Neon instructions), or end of string. */
14543 for (base
= end
= *str
; *end
!= '\0'; end
++)
14544 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14550 /* Handle a possible width suffix and/or Neon type suffix. */
14555 /* The .w and .n suffixes are only valid if the unified syntax is in
14557 if (unified_syntax
&& end
[1] == 'w')
14559 else if (unified_syntax
&& end
[1] == 'n')
14564 inst
.vectype
.elems
= 0;
14566 *str
= end
+ offset
;
14568 if (end
[offset
] == '.')
14570 /* See if we have a Neon type suffix (possible in either unified or
14571 non-unified ARM syntax mode). */
14572 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14575 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14581 /* Look for unaffixed or special-case affixed mnemonic. */
14582 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14586 if (opcode
->tag
< OT_odd_infix_0
)
14588 inst
.cond
= COND_ALWAYS
;
14592 if (warn_on_deprecated
&& unified_syntax
)
14593 as_warn (_("conditional infixes are deprecated in unified syntax"));
14594 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14595 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14598 inst
.cond
= cond
->value
;
14602 /* Cannot have a conditional suffix on a mnemonic of less than two
14604 if (end
- base
< 3)
14607 /* Look for suffixed mnemonic. */
14609 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14610 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
14611 if (opcode
&& cond
)
14614 switch (opcode
->tag
)
14616 case OT_cinfix3_legacy
:
14617 /* Ignore conditional suffixes matched on infix only mnemonics. */
14621 case OT_cinfix3_deprecated
:
14622 case OT_odd_infix_unc
:
14623 if (!unified_syntax
)
14625 /* else fall through */
14629 case OT_csuf_or_in3
:
14630 inst
.cond
= cond
->value
;
14633 case OT_unconditional
:
14634 case OT_unconditionalF
:
14637 inst
.cond
= cond
->value
;
14641 /* delayed diagnostic */
14642 inst
.error
= BAD_COND
;
14643 inst
.cond
= COND_ALWAYS
;
14652 /* Cannot have a usual-position infix on a mnemonic of less than
14653 six characters (five would be a suffix). */
14654 if (end
- base
< 6)
14657 /* Look for infixed mnemonic in the usual position. */
14659 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14663 memcpy (save
, affix
, 2);
14664 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14665 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14666 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14667 memcpy (affix
, save
, 2);
14670 && (opcode
->tag
== OT_cinfix3
14671 || opcode
->tag
== OT_cinfix3_deprecated
14672 || opcode
->tag
== OT_csuf_or_in3
14673 || opcode
->tag
== OT_cinfix3_legacy
))
14676 if (warn_on_deprecated
&& unified_syntax
14677 && (opcode
->tag
== OT_cinfix3
14678 || opcode
->tag
== OT_cinfix3_deprecated
))
14679 as_warn (_("conditional infixes are deprecated in unified syntax"));
14681 inst
.cond
= cond
->value
;
14689 md_assemble (char *str
)
14692 const struct asm_opcode
* opcode
;
14694 /* Align the previous label if needed. */
14695 if (last_label_seen
!= NULL
)
14697 symbol_set_frag (last_label_seen
, frag_now
);
14698 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
14699 S_SET_SEGMENT (last_label_seen
, now_seg
);
14702 memset (&inst
, '\0', sizeof (inst
));
14703 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
14705 opcode
= opcode_lookup (&p
);
14708 /* It wasn't an instruction, but it might be a register alias of
14709 the form alias .req reg, or a Neon .dn/.qn directive. */
14710 if (!create_register_alias (str
, p
)
14711 && !create_neon_reg_alias (str
, p
))
14712 as_bad (_("bad instruction `%s'"), str
);
14717 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
14718 as_warn (_("s suffix on comparison instruction is deprecated"));
14720 /* The value which unconditional instructions should have in place of the
14721 condition field. */
14722 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
14726 arm_feature_set variant
;
14728 variant
= cpu_variant
;
14729 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14730 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
14731 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
14732 /* Check that this instruction is supported for this CPU. */
14733 if (!opcode
->tvariant
14734 || (thumb_mode
== 1
14735 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14737 as_bad (_("selected processor does not support `%s'"), str
);
14740 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14741 && opcode
->tencode
!= do_t_branch
)
14743 as_bad (_("Thumb does not support conditional execution"));
14747 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
) && !inst
.size_req
)
14749 /* Implicit require narrow instructions on Thumb-1. This avoids
14750 relaxation accidentally introducing Thumb-2 instructions. */
14751 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
14752 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
14753 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
14757 /* Check conditional suffixes. */
14758 if (current_it_mask
)
14761 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14762 current_it_mask
<<= 1;
14763 current_it_mask
&= 0x1f;
14764 /* The BKPT instruction is unconditional even in an IT block. */
14766 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14768 as_bad (_("incorrect condition in IT block"));
14772 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14774 as_bad (_("thumb conditional instruction not in IT block"));
14778 mapping_state (MAP_THUMB
);
14779 inst
.instruction
= opcode
->tvalue
;
14781 if (!parse_operands (p
, opcode
->operands
))
14782 opcode
->tencode ();
14784 /* Clear current_it_mask at the end of an IT block. */
14785 if (current_it_mask
== 0x10)
14786 current_it_mask
= 0;
14788 if (!(inst
.error
|| inst
.relax
))
14790 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14791 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14792 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14794 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14799 /* Something has gone badly wrong if we try to relax a fixed size
14801 assert (inst
.size_req
== 0 || !inst
.relax
);
14803 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14804 *opcode
->tvariant
);
14805 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14806 set those bits when Thumb-2 32-bit instructions are seen. ie.
14807 anything other than bl/blx and v6-M instructions.
14808 This is overly pessimistic for relaxable instructions. */
14809 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14811 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
14812 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
14813 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14816 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14820 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
14821 is_bx
= (opcode
->aencode
== do_bx
);
14823 /* Check that this instruction is supported for this CPU. */
14824 if (!(is_bx
&& fix_v4bx
)
14825 && !(opcode
->avariant
&&
14826 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
14828 as_bad (_("selected processor does not support `%s'"), str
);
14833 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14837 mapping_state (MAP_ARM
);
14838 inst
.instruction
= opcode
->avalue
;
14839 if (opcode
->tag
== OT_unconditionalF
)
14840 inst
.instruction
|= 0xF << 28;
14842 inst
.instruction
|= inst
.cond
<< 28;
14843 inst
.size
= INSN_SIZE
;
14844 if (!parse_operands (p
, opcode
->operands
))
14845 opcode
->aencode ();
14846 /* Arm mode bx is marked as both v4T and v5 because it's still required
14847 on a hypothetical non-thumb v5 core. */
14849 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14851 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14852 *opcode
->avariant
);
14856 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14863 /* Various frobbings of labels and their addresses. */
14866 arm_start_line_hook (void)
14868 last_label_seen
= NULL
;
14872 arm_frob_label (symbolS
* sym
)
14874 last_label_seen
= sym
;
14876 ARM_SET_THUMB (sym
, thumb_mode
);
14878 #if defined OBJ_COFF || defined OBJ_ELF
14879 ARM_SET_INTERWORK (sym
, support_interwork
);
14882 /* Note - do not allow local symbols (.Lxxx) to be labelled
14883 as Thumb functions. This is because these labels, whilst
14884 they exist inside Thumb code, are not the entry points for
14885 possible ARM->Thumb calls. Also, these labels can be used
14886 as part of a computed goto or switch statement. eg gcc
14887 can generate code that looks like this:
14889 ldr r2, [pc, .Laaa]
14899 The first instruction loads the address of the jump table.
14900 The second instruction converts a table index into a byte offset.
14901 The third instruction gets the jump address out of the table.
14902 The fourth instruction performs the jump.
14904 If the address stored at .Laaa is that of a symbol which has the
14905 Thumb_Func bit set, then the linker will arrange for this address
14906 to have the bottom bit set, which in turn would mean that the
14907 address computation performed by the third instruction would end
14908 up with the bottom bit set. Since the ARM is capable of unaligned
14909 word loads, the instruction would then load the incorrect address
14910 out of the jump table, and chaos would ensue. */
14911 if (label_is_thumb_function_name
14912 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14913 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14915 /* When the address of a Thumb function is taken the bottom
14916 bit of that address should be set. This will allow
14917 interworking between Arm and Thumb functions to work
14920 THUMB_SET_FUNC (sym
, 1);
14922 label_is_thumb_function_name
= FALSE
;
14925 dwarf2_emit_label (sym
);
14929 arm_data_in_code (void)
14931 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14933 *input_line_pointer
= '/';
14934 input_line_pointer
+= 5;
14935 *input_line_pointer
= 0;
14943 arm_canonicalize_symbol_name (char * name
)
14947 if (thumb_mode
&& (len
= strlen (name
)) > 5
14948 && streq (name
+ len
- 5, "/data"))
14949 *(name
+ len
- 5) = 0;
14954 /* Table of all register names defined by default. The user can
14955 define additional names with .req. Note that all register names
14956 should appear in both upper and lowercase variants. Some registers
14957 also have mixed-case names. */
14959 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14960 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14961 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14962 #define REGSET(p,t) \
14963 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14964 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14965 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14966 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14967 #define REGSETH(p,t) \
14968 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14969 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14970 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14971 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14972 #define REGSET2(p,t) \
14973 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14974 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14975 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14976 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14978 static const struct reg_entry reg_names
[] =
14980 /* ARM integer registers. */
14981 REGSET(r
, RN
), REGSET(R
, RN
),
14983 /* ATPCS synonyms. */
14984 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14985 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14986 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14988 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14989 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14990 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14992 /* Well-known aliases. */
14993 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14994 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14996 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14997 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14999 /* Coprocessor numbers. */
15000 REGSET(p
, CP
), REGSET(P
, CP
),
15002 /* Coprocessor register numbers. The "cr" variants are for backward
15004 REGSET(c
, CN
), REGSET(C
, CN
),
15005 REGSET(cr
, CN
), REGSET(CR
, CN
),
15007 /* FPA registers. */
15008 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
15009 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
15011 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
15012 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
15014 /* VFP SP registers. */
15015 REGSET(s
,VFS
), REGSET(S
,VFS
),
15016 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
15018 /* VFP DP Registers. */
15019 REGSET(d
,VFD
), REGSET(D
,VFD
),
15020 /* Extra Neon DP registers. */
15021 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
15023 /* Neon QP registers. */
15024 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
15026 /* VFP control registers. */
15027 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
15028 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
15029 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
15030 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
15031 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
15032 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
15034 /* Maverick DSP coprocessor registers. */
15035 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
15036 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
15038 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
15039 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
15040 REGDEF(dspsc
,0,DSPSC
),
15042 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
15043 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
15044 REGDEF(DSPSC
,0,DSPSC
),
15046 /* iWMMXt data registers - p0, c0-15. */
15047 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
15049 /* iWMMXt control registers - p1, c0-3. */
15050 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
15051 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
15052 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
15053 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
15055 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
15056 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
15057 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
15058 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
15059 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
15061 /* XScale accumulator registers. */
15062 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
15068 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
15069 within psr_required_here. */
15070 static const struct asm_psr psrs
[] =
15072 /* Backward compatibility notation. Note that "all" is no longer
15073 truly all possible PSR bits. */
15074 {"all", PSR_c
| PSR_f
},
15078 /* Individual flags. */
15083 /* Combinations of flags. */
15084 {"fs", PSR_f
| PSR_s
},
15085 {"fx", PSR_f
| PSR_x
},
15086 {"fc", PSR_f
| PSR_c
},
15087 {"sf", PSR_s
| PSR_f
},
15088 {"sx", PSR_s
| PSR_x
},
15089 {"sc", PSR_s
| PSR_c
},
15090 {"xf", PSR_x
| PSR_f
},
15091 {"xs", PSR_x
| PSR_s
},
15092 {"xc", PSR_x
| PSR_c
},
15093 {"cf", PSR_c
| PSR_f
},
15094 {"cs", PSR_c
| PSR_s
},
15095 {"cx", PSR_c
| PSR_x
},
15096 {"fsx", PSR_f
| PSR_s
| PSR_x
},
15097 {"fsc", PSR_f
| PSR_s
| PSR_c
},
15098 {"fxs", PSR_f
| PSR_x
| PSR_s
},
15099 {"fxc", PSR_f
| PSR_x
| PSR_c
},
15100 {"fcs", PSR_f
| PSR_c
| PSR_s
},
15101 {"fcx", PSR_f
| PSR_c
| PSR_x
},
15102 {"sfx", PSR_s
| PSR_f
| PSR_x
},
15103 {"sfc", PSR_s
| PSR_f
| PSR_c
},
15104 {"sxf", PSR_s
| PSR_x
| PSR_f
},
15105 {"sxc", PSR_s
| PSR_x
| PSR_c
},
15106 {"scf", PSR_s
| PSR_c
| PSR_f
},
15107 {"scx", PSR_s
| PSR_c
| PSR_x
},
15108 {"xfs", PSR_x
| PSR_f
| PSR_s
},
15109 {"xfc", PSR_x
| PSR_f
| PSR_c
},
15110 {"xsf", PSR_x
| PSR_s
| PSR_f
},
15111 {"xsc", PSR_x
| PSR_s
| PSR_c
},
15112 {"xcf", PSR_x
| PSR_c
| PSR_f
},
15113 {"xcs", PSR_x
| PSR_c
| PSR_s
},
15114 {"cfs", PSR_c
| PSR_f
| PSR_s
},
15115 {"cfx", PSR_c
| PSR_f
| PSR_x
},
15116 {"csf", PSR_c
| PSR_s
| PSR_f
},
15117 {"csx", PSR_c
| PSR_s
| PSR_x
},
15118 {"cxf", PSR_c
| PSR_x
| PSR_f
},
15119 {"cxs", PSR_c
| PSR_x
| PSR_s
},
15120 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
15121 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
15122 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
15123 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
15124 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
15125 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
15126 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
15127 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
15128 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
15129 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
15130 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
15131 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
15132 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
15133 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
15134 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
15135 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
15136 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
15137 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
15138 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
15139 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
15140 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
15141 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
15142 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
15143 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
15146 /* Table of V7M psr names. */
15147 static const struct asm_psr v7m_psrs
[] =
15149 {"apsr", 0 }, {"APSR", 0 },
15150 {"iapsr", 1 }, {"IAPSR", 1 },
15151 {"eapsr", 2 }, {"EAPSR", 2 },
15152 {"psr", 3 }, {"PSR", 3 },
15153 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
15154 {"ipsr", 5 }, {"IPSR", 5 },
15155 {"epsr", 6 }, {"EPSR", 6 },
15156 {"iepsr", 7 }, {"IEPSR", 7 },
15157 {"msp", 8 }, {"MSP", 8 },
15158 {"psp", 9 }, {"PSP", 9 },
15159 {"primask", 16}, {"PRIMASK", 16},
15160 {"basepri", 17}, {"BASEPRI", 17},
15161 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
15162 {"faultmask", 19}, {"FAULTMASK", 19},
15163 {"control", 20}, {"CONTROL", 20}
15166 /* Table of all shift-in-operand names. */
15167 static const struct asm_shift_name shift_names
[] =
15169 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
15170 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
15171 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
15172 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
15173 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
15174 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
15177 /* Table of all explicit relocation names. */
15179 static struct reloc_entry reloc_names
[] =
15181 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
15182 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
15183 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
15184 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
15185 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
15186 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
15187 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
15188 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
15189 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
15190 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
15191 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
15195 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
15196 static const struct asm_cond conds
[] =
15200 {"cs", 0x2}, {"hs", 0x2},
15201 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
15215 static struct asm_barrier_opt barrier_opt_names
[] =
15223 /* Table of ARM-format instructions. */
15225 /* Macros for gluing together operand strings. N.B. In all cases
15226 other than OPS0, the trailing OP_stop comes from default
15227 zero-initialization of the unspecified elements of the array. */
15228 #define OPS0() { OP_stop, }
15229 #define OPS1(a) { OP_##a, }
15230 #define OPS2(a,b) { OP_##a,OP_##b, }
15231 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
15232 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
15233 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
15234 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
15236 /* These macros abstract out the exact format of the mnemonic table and
15237 save some repeated characters. */
15239 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
15240 #define TxCE(mnem, op, top, nops, ops, ae, te) \
15241 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
15242 THUMB_VARIANT, do_##ae, do_##te }
15244 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
15245 a T_MNEM_xyz enumerator. */
15246 #define TCE(mnem, aop, top, nops, ops, ae, te) \
15247 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
15248 #define tCE(mnem, aop, top, nops, ops, ae, te) \
15249 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
15251 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
15252 infix after the third character. */
15253 #define TxC3(mnem, op, top, nops, ops, ae, te) \
15254 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
15255 THUMB_VARIANT, do_##ae, do_##te }
15256 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
15257 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
15258 THUMB_VARIANT, do_##ae, do_##te }
15259 #define TC3(mnem, aop, top, nops, ops, ae, te) \
15260 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
15261 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
15262 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
15263 #define tC3(mnem, aop, top, nops, ops, ae, te) \
15264 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
15265 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
15266 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
15268 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
15269 appear in the condition table. */
15270 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
15271 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
15272 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
15274 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
15275 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
15276 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
15277 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
15278 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
15279 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
15280 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
15281 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
15282 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
15283 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
15284 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
15285 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
15286 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
15287 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
15288 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
15289 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
15290 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
15291 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
15292 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
15293 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
15295 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
15296 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
15297 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
15298 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
15300 /* Mnemonic that cannot be conditionalized. The ARM condition-code
15301 field is still 0xE. Many of the Thumb variants can be executed
15302 conditionally, so this is checked separately. */
15303 #define TUE(mnem, op, top, nops, ops, ae, te) \
15304 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
15305 THUMB_VARIANT, do_##ae, do_##te }
15307 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
15308 condition code field. */
15309 #define TUF(mnem, op, top, nops, ops, ae, te) \
15310 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
15311 THUMB_VARIANT, do_##ae, do_##te }
15313 /* ARM-only variants of all the above. */
15314 #define CE(mnem, op, nops, ops, ae) \
15315 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15317 #define C3(mnem, op, nops, ops, ae) \
15318 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15320 /* Legacy mnemonics that always have conditional infix after the third
15322 #define CL(mnem, op, nops, ops, ae) \
15323 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
15324 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15326 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
15327 #define cCE(mnem, op, nops, ops, ae) \
15328 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
15330 /* Legacy coprocessor instructions where conditional infix and conditional
15331 suffix are ambiguous. For consistency this includes all FPA instructions,
15332 not just the potentially ambiguous ones. */
15333 #define cCL(mnem, op, nops, ops, ae) \
15334 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
15335 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
15337 /* Coprocessor, takes either a suffix or a position-3 infix
15338 (for an FPA corner case). */
15339 #define C3E(mnem, op, nops, ops, ae) \
15340 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
15341 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
15343 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
15344 { #m1 #m2 #m3, OPS##nops ops, \
15345 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
15346 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15348 #define CM(m1, m2, op, nops, ops, ae) \
15349 xCM_(m1, , m2, op, nops, ops, ae), \
15350 xCM_(m1, eq, m2, op, nops, ops, ae), \
15351 xCM_(m1, ne, m2, op, nops, ops, ae), \
15352 xCM_(m1, cs, m2, op, nops, ops, ae), \
15353 xCM_(m1, hs, m2, op, nops, ops, ae), \
15354 xCM_(m1, cc, m2, op, nops, ops, ae), \
15355 xCM_(m1, ul, m2, op, nops, ops, ae), \
15356 xCM_(m1, lo, m2, op, nops, ops, ae), \
15357 xCM_(m1, mi, m2, op, nops, ops, ae), \
15358 xCM_(m1, pl, m2, op, nops, ops, ae), \
15359 xCM_(m1, vs, m2, op, nops, ops, ae), \
15360 xCM_(m1, vc, m2, op, nops, ops, ae), \
15361 xCM_(m1, hi, m2, op, nops, ops, ae), \
15362 xCM_(m1, ls, m2, op, nops, ops, ae), \
15363 xCM_(m1, ge, m2, op, nops, ops, ae), \
15364 xCM_(m1, lt, m2, op, nops, ops, ae), \
15365 xCM_(m1, gt, m2, op, nops, ops, ae), \
15366 xCM_(m1, le, m2, op, nops, ops, ae), \
15367 xCM_(m1, al, m2, op, nops, ops, ae)
15369 #define UE(mnem, op, nops, ops, ae) \
15370 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
15372 #define UF(mnem, op, nops, ops, ae) \
15373 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
15375 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
15376 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
15377 use the same encoding function for each. */
15378 #define NUF(mnem, op, nops, ops, enc) \
15379 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
15380 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
15382 /* Neon data processing, version which indirects through neon_enc_tab for
15383 the various overloaded versions of opcodes. */
15384 #define nUF(mnem, op, nops, ops, enc) \
15385 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
15386 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
15388 /* Neon insn with conditional suffix for the ARM version, non-overloaded
15390 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
15391 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
15392 THUMB_VARIANT, do_##enc, do_##enc }
15394 #define NCE(mnem, op, nops, ops, enc) \
15395 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
15397 #define NCEF(mnem, op, nops, ops, enc) \
15398 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
15400 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
15401 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
15402 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
15403 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
15405 #define nCE(mnem, op, nops, ops, enc) \
15406 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
15408 #define nCEF(mnem, op, nops, ops, enc) \
15409 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
15413 /* Thumb-only, unconditional. */
15414 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
15416 static const struct asm_opcode insns
[] =
15418 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
15419 #define THUMB_VARIANT &arm_ext_v4t
15420 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15421 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15422 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15423 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15424 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
15425 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
15426 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
15427 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
15428 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15429 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15430 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15431 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15432 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15433 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15434 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15435 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15437 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
15438 for setting PSR flag bits. They are obsolete in V6 and do not
15439 have Thumb equivalents. */
15440 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15441 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15442 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
15443 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
15444 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
15445 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
15446 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15447 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15448 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
15450 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
15451 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
15452 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
15453 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
15455 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15456 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15457 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15458 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15460 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15461 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15462 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15463 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15464 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15465 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15467 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
15468 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
15469 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
15470 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
15473 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
15474 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
15475 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
15477 /* Thumb-compatibility pseudo ops. */
15478 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15479 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15480 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15481 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15482 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15483 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15484 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15485 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15486 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
15487 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
15488 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
15489 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
15491 /* These may simplify to neg. */
15492 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
15493 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
15495 #undef THUMB_VARIANT
15496 #define THUMB_VARIANT &arm_ext_v6
15497 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
15499 /* V1 instructions with no Thumb analogue prior to V6T2. */
15500 #undef THUMB_VARIANT
15501 #define THUMB_VARIANT &arm_ext_v6t2
15502 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15503 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15504 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
15506 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15507 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15508 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15509 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15511 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15512 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15514 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15515 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15517 /* V1 instructions with no Thumb analogue at all. */
15518 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
15519 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
15521 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15522 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15523 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15524 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15525 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15526 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15527 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15528 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15531 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
15532 #undef THUMB_VARIANT
15533 #define THUMB_VARIANT &arm_ext_v4t
15534 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15535 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15537 #undef THUMB_VARIANT
15538 #define THUMB_VARIANT &arm_ext_v6t2
15539 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15540 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
15542 /* Generic coprocessor instructions. */
15543 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15544 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15545 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15546 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15547 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15548 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15549 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15552 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15553 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15554 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15557 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15558 #undef THUMB_VARIANT
15559 #define THUMB_VARIANT &arm_ext_msr
15560 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
15561 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
15564 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15565 #undef THUMB_VARIANT
15566 #define THUMB_VARIANT &arm_ext_v6t2
15567 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15568 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15569 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15570 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15571 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15572 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15573 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15574 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15577 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15578 #undef THUMB_VARIANT
15579 #define THUMB_VARIANT &arm_ext_v4t
15580 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15581 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15582 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15583 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15584 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15585 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15588 #define ARM_VARIANT &arm_ext_v4t_5
15589 /* ARM Architecture 4T. */
15590 /* Note: bx (and blx) are required on V5, even if the processor does
15591 not support Thumb. */
15592 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
15595 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15596 #undef THUMB_VARIANT
15597 #define THUMB_VARIANT &arm_ext_v5t
15598 /* Note: blx has 2 variants; the .value coded here is for
15599 BLX(2). Only this variant has conditional execution. */
15600 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
15601 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
15603 #undef THUMB_VARIANT
15604 #define THUMB_VARIANT &arm_ext_v6t2
15605 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
15606 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15607 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15608 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15609 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15610 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15611 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15612 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15615 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15616 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15617 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15618 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15619 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15621 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15622 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15624 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15625 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15626 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15627 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15629 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15630 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15631 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15632 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15634 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15635 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15637 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15638 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15639 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15640 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15643 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15644 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
15645 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15646 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15648 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15649 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15652 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15653 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
15656 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15657 #undef THUMB_VARIANT
15658 #define THUMB_VARIANT &arm_ext_v6
15659 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15660 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15661 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15662 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15663 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15664 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15665 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15666 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15667 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15668 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
15670 #undef THUMB_VARIANT
15671 #define THUMB_VARIANT &arm_ext_v6t2
15672 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
15673 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
15674 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15675 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15677 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
15678 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
15680 /* ARM V6 not included in V7M (eg. integer SIMD). */
15681 #undef THUMB_VARIANT
15682 #define THUMB_VARIANT &arm_ext_v6_notm
15683 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
15684 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
15685 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
15686 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15687 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15688 TCE(qasx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15689 /* Old name for QASX. */
15690 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15691 TCE(qsax
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15692 /* Old name for QSAX. */
15693 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15694 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15695 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15696 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15697 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15698 TCE(sasx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15699 /* Old name for SASX. */
15700 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15701 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15702 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15703 TCE(shasx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15704 /* Old name for SHASX. */
15705 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15706 TCE(shsax
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15707 /* Old name for SHSAX. */
15708 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15709 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15710 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15711 TCE(ssax
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15712 /* Old name for SSAX. */
15713 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15714 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15715 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15716 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15717 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15718 TCE(uasx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15719 /* Old name for UASX. */
15720 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15721 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15722 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15723 TCE(uhasx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15724 /* Old name for UHASX. */
15725 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15726 TCE(uhsax
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15727 /* Old name for UHSAX. */
15728 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15729 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15730 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15731 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15732 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15733 TCE(uqasx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15734 /* Old name for UQASX. */
15735 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15736 TCE(uqsax
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15737 /* Old name for UQSAX. */
15738 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15739 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15740 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15741 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15742 TCE(usax
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15743 /* Old name for USAX. */
15744 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15745 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15746 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15747 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
15748 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
15749 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15750 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15751 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
15752 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
15753 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15754 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15755 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15756 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15757 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15758 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15759 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15760 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15761 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15762 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15763 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15764 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15765 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15766 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15767 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15768 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15769 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15770 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15771 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15772 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15773 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15774 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15775 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15776 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15777 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15778 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15779 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15780 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15781 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
15782 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
15783 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
15784 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
15785 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
15786 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
15787 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15788 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15789 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15792 #define ARM_VARIANT &arm_ext_v6k
15793 #undef THUMB_VARIANT
15794 #define THUMB_VARIANT &arm_ext_v6k
15795 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15796 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15797 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15798 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15800 #undef THUMB_VARIANT
15801 #define THUMB_VARIANT &arm_ext_v6_notm
15802 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15803 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15805 #undef THUMB_VARIANT
15806 #define THUMB_VARIANT &arm_ext_v6t2
15807 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15808 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15809 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15810 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15811 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15814 #define ARM_VARIANT &arm_ext_v6z
15815 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15818 #define ARM_VARIANT &arm_ext_v6t2
15819 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15820 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15821 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15822 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15824 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15825 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15826 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15827 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15829 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15830 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15831 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15832 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15834 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15835 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15836 /* ARM does not really have an IT instruction, so always allow it. */
15838 #define ARM_VARIANT &arm_ext_v1
15839 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15840 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15841 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15842 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15843 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15844 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15845 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15846 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15847 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15848 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15849 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15850 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15851 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15852 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15853 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15854 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
15855 TC3(rrx
, 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
15856 TC3(rrxs
, 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
15858 /* Thumb2 only instructions. */
15860 #define ARM_VARIANT NULL
15862 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15863 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15864 TCE(orn
, 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
15865 TCE(orns
, 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
15866 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15867 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15869 /* Thumb-2 hardware division instructions (R and M profiles only). */
15870 #undef THUMB_VARIANT
15871 #define THUMB_VARIANT &arm_ext_div
15872 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15873 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15875 /* ARM V6M/V7 instructions. */
15877 #define ARM_VARIANT &arm_ext_barrier
15878 #undef THUMB_VARIANT
15879 #define THUMB_VARIANT &arm_ext_barrier
15880 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15881 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15882 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15884 /* ARM V7 instructions. */
15886 #define ARM_VARIANT &arm_ext_v7
15887 #undef THUMB_VARIANT
15888 #define THUMB_VARIANT &arm_ext_v7
15889 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15890 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15893 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15894 cCE(wfs
, e200110
, 1, (RR
), rd
),
15895 cCE(rfs
, e300110
, 1, (RR
), rd
),
15896 cCE(wfc
, e400110
, 1, (RR
), rd
),
15897 cCE(rfc
, e500110
, 1, (RR
), rd
),
15899 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15900 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15901 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15902 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15904 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15905 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15906 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15907 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15909 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15910 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15911 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15912 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15913 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15914 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15915 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15916 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15917 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15918 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15919 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15920 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15922 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15923 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15924 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15925 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15926 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15927 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15928 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15929 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15930 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15931 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15932 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15933 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15935 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15936 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15937 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15938 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15939 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15940 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15941 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15942 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15943 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15944 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15945 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15946 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15948 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15949 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15950 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15951 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15952 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15953 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15954 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15955 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15956 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15957 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15958 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15959 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15961 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15962 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15963 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15964 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15965 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15966 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15967 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15968 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15969 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15970 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15971 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15972 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15974 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15975 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15976 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15977 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15978 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15979 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15980 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15981 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15982 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15983 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15984 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15985 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15987 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15988 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15989 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15990 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15991 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15992 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15993 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15994 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15995 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15996 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15997 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15998 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
16000 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
16001 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
16002 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
16003 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
16004 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
16005 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
16006 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
16007 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
16008 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
16009 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
16010 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
16011 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
16013 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
16014 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
16015 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
16016 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
16017 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
16018 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
16019 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
16020 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
16021 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
16022 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
16023 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
16024 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
16026 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
16027 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
16028 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
16029 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
16030 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
16031 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
16032 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
16033 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
16034 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
16035 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
16036 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
16037 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
16039 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
16040 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
16041 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
16042 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
16043 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
16044 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
16045 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
16046 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
16047 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
16048 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
16049 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
16050 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
16052 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
16053 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
16054 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
16055 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
16056 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
16057 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
16058 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
16059 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
16060 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
16061 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
16062 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
16063 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
16065 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
16066 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
16067 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
16068 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
16069 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
16070 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
16071 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
16072 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
16073 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
16074 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
16075 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
16076 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
16078 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
16079 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
16080 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
16081 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
16082 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
16083 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
16084 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
16085 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
16086 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
16087 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
16088 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
16089 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
16091 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
16092 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
16093 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
16094 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
16095 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
16096 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
16097 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
16098 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
16099 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
16100 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
16101 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
16102 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
16104 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
16105 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
16106 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
16107 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
16108 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
16109 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
16110 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
16111 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
16112 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
16113 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
16114 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
16115 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
16117 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16118 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16119 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16120 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16121 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16122 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16123 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16124 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16125 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16126 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16127 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16128 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16130 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16131 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16132 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16133 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16134 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16135 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16136 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16137 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16138 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16139 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16140 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16141 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16143 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16144 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16145 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16146 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16147 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16148 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16149 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16150 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16151 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16152 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16153 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16154 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16156 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16157 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16158 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16159 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16160 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16161 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16162 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16163 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16164 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16165 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16166 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16167 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16169 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16170 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16171 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16172 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16173 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16174 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16175 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16176 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16177 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16178 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16179 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16180 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16182 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16183 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16184 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16185 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16186 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16187 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16188 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16189 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16190 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16191 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16192 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16193 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16195 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16196 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16197 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16198 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16199 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16200 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16201 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16202 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16203 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16204 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16205 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16206 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16208 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16209 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16210 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16211 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16212 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16213 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16214 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16215 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16216 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16217 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16218 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16219 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16221 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16222 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16223 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16224 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16225 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16226 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16227 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16228 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16229 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16230 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16231 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16232 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16234 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16235 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16236 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16237 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16238 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16239 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16240 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16241 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16242 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16243 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16244 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16245 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16247 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16248 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16249 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16250 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16251 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16252 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16253 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16254 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16255 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16256 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16257 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16258 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16260 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16261 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16262 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16263 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16264 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16265 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16266 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16267 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16268 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16269 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16270 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16271 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16273 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16274 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16275 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16276 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16277 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16278 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16279 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16280 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16281 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16282 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16283 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16284 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16286 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16287 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16288 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16289 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16291 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
16292 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
16293 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
16294 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
16295 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
16296 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
16297 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
16298 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
16299 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
16300 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
16301 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
16302 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
16304 /* The implementation of the FIX instruction is broken on some
16305 assemblers, in that it accepts a precision specifier as well as a
16306 rounding specifier, despite the fact that this is meaningless.
16307 To be more compatible, we accept it as well, though of course it
16308 does not set any bits. */
16309 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
16310 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
16311 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
16312 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
16313 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
16314 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
16315 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
16316 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
16317 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
16318 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
16319 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
16320 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
16321 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
16323 /* Instructions that were new with the real FPA, call them V2. */
16325 #define ARM_VARIANT &fpu_fpa_ext_v2
16326 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16327 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16328 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16329 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16330 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16331 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16334 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
16335 /* Moves and type conversions. */
16336 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16337 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
16338 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
16339 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
16340 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16341 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16342 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16343 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16344 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16345 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16346 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
16347 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
16349 /* Memory operations. */
16350 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
16351 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
16352 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16353 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16354 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16355 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16356 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16357 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16358 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16359 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16360 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16361 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16362 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16363 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16364 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16365 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16366 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16367 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16369 /* Monadic operations. */
16370 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16371 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16372 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16374 /* Dyadic operations. */
16375 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16376 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16377 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16378 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16379 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16380 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16381 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16382 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16383 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16386 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16387 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
16388 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16389 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
16392 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
16393 /* Moves and type conversions. */
16394 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16395 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
16396 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16397 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
16398 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
16399 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
16400 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
16401 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
16402 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
16403 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16404 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16405 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16406 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16408 /* Memory operations. */
16409 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
16410 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
16411 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16412 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16413 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16414 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16415 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16416 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16417 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16418 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16420 /* Monadic operations. */
16421 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16422 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16423 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16425 /* Dyadic operations. */
16426 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16427 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16428 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16429 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16430 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16431 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16432 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16433 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16434 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16437 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16438 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
16439 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16440 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
16443 #define ARM_VARIANT &fpu_vfp_ext_v2
16444 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
16445 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
16446 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
16447 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
16449 /* Instructions which may belong to either the Neon or VFP instruction sets.
16450 Individual encoder functions perform additional architecture checks. */
16452 #define ARM_VARIANT &fpu_vfp_ext_v1xd
16453 #undef THUMB_VARIANT
16454 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
16455 /* These mnemonics are unique to VFP. */
16456 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
16457 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
16458 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16459 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16460 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16461 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
16462 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
16463 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
16464 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
16465 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
16467 /* Mnemonics shared by Neon and VFP. */
16468 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
16469 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
16470 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
16472 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
16473 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
16475 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
16476 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
16478 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16479 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16480 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16481 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16482 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16483 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16484 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
16485 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
16487 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
16488 nCEF(vcvtb
, vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
16489 nCEF(vcvtt
, vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
16492 /* NOTE: All VMOV encoding is special-cased! */
16493 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
16494 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
16496 #undef THUMB_VARIANT
16497 #define THUMB_VARIANT &fpu_neon_ext_v1
16499 #define ARM_VARIANT &fpu_neon_ext_v1
16500 /* Data processing with three registers of the same length. */
16501 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
16502 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
16503 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
16504 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16505 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16506 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16507 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16508 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16509 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16510 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
16511 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
16512 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
16513 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
16514 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
16515 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
16516 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
16517 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
16518 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
16519 /* If not immediate, fall back to neon_dyadic_i64_su.
16520 shl_imm should accept I8 I16 I32 I64,
16521 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
16522 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
16523 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
16524 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
16525 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
16526 /* Logic ops, types optional & ignored. */
16527 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
16528 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
16529 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
16530 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
16531 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
16532 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
16533 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
16534 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
16535 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
16536 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
16537 /* Bitfield ops, untyped. */
16538 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16539 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16540 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16541 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16542 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16543 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16544 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
16545 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16546 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16547 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16548 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16549 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16550 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16551 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
16552 back to neon_dyadic_if_su. */
16553 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16554 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16555 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16556 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16557 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16558 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16559 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16560 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16561 /* Comparison. Type I8 I16 I32 F32. */
16562 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
16563 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
16564 /* As above, D registers only. */
16565 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16566 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16567 /* Int and float variants, signedness unimportant. */
16568 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16569 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16570 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
16571 /* Add/sub take types I8 I16 I32 I64 F32. */
16572 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16573 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16574 /* vtst takes sizes 8, 16, 32. */
16575 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
16576 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
16577 /* VMUL takes I8 I16 I32 F32 P8. */
16578 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
16579 /* VQD{R}MULH takes S16 S32. */
16580 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16581 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16582 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16583 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16584 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16585 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16586 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16587 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16588 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16589 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16590 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16591 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16592 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16593 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16594 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16595 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16597 /* Two address, int/float. Types S8 S16 S32 F32. */
16598 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16599 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16601 /* Data processing with two registers and a shift amount. */
16602 /* Right shifts, and variants with rounding.
16603 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16604 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16605 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16606 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16607 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16608 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16609 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16610 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16611 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16612 /* Shift and insert. Sizes accepted 8 16 32 64. */
16613 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
16614 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
16615 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
16616 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
16617 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16618 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
16619 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
16620 /* Right shift immediate, saturating & narrowing, with rounding variants.
16621 Types accepted S16 S32 S64 U16 U32 U64. */
16622 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16623 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16624 /* As above, unsigned. Types accepted S16 S32 S64. */
16625 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16626 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16627 /* Right shift narrowing. Types accepted I16 I32 I64. */
16628 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16629 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16630 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16631 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
16632 /* CVT with optional immediate for fixed-point variant. */
16633 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
16635 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
16636 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
16638 /* Data processing, three registers of different lengths. */
16639 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16640 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
16641 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16642 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16643 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16644 /* If not scalar, fall back to neon_dyadic_long.
16645 Vector types as above, scalar types S16 S32 U16 U32. */
16646 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16647 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16648 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16649 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16650 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16651 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16652 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16653 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16654 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16655 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16656 /* Saturating doubling multiplies. Types S16 S32. */
16657 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16658 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16659 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16660 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16661 S16 S32 U16 U32. */
16662 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
16664 /* Extract. Size 8. */
16665 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
16666 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
16668 /* Two registers, miscellaneous. */
16669 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16670 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
16671 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
16672 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
16673 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
16674 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
16675 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
16676 /* Vector replicate. Sizes 8 16 32. */
16677 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
16678 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
16679 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16680 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
16681 /* VMOVN. Types I16 I32 I64. */
16682 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
16683 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16684 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
16685 /* VQMOVUN. Types S16 S32 S64. */
16686 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
16687 /* VZIP / VUZP. Sizes 8 16 32. */
16688 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16689 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16690 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16691 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16692 /* VQABS / VQNEG. Types S8 S16 S32. */
16693 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16694 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16695 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16696 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16697 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16698 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16699 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
16700 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16701 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
16702 /* Reciprocal estimates. Types U32 F32. */
16703 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16704 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
16705 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16706 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
16707 /* VCLS. Types S8 S16 S32. */
16708 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
16709 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
16710 /* VCLZ. Types I8 I16 I32. */
16711 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
16712 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
16713 /* VCNT. Size 8. */
16714 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
16715 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
16716 /* Two address, untyped. */
16717 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
16718 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
16719 /* VTRN. Sizes 8 16 32. */
16720 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
16721 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
16723 /* Table lookup. Size 8. */
16724 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16725 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16727 #undef THUMB_VARIANT
16728 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16730 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16731 /* Neon element/structure load/store. */
16732 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16733 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16734 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16735 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16736 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16737 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16738 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16739 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16741 #undef THUMB_VARIANT
16742 #define THUMB_VARIANT &fpu_vfp_ext_v3
16744 #define ARM_VARIANT &fpu_vfp_ext_v3
16745 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
16746 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
16747 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16748 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16749 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16750 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16751 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16752 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16753 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16754 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16755 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16756 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16757 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16758 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16759 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16760 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16761 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16762 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16764 #undef THUMB_VARIANT
16766 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16767 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16768 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16769 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16770 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16771 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16772 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16773 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
16774 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
16777 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16778 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
16779 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
16780 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
16781 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
16782 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
16783 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
16784 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
16785 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
16786 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
16787 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16788 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16789 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16790 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16791 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16792 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16793 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16794 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16795 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16796 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
16797 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
16798 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16799 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16800 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16801 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16802 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16803 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16804 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
16805 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16806 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16807 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16808 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16809 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16810 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16811 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16812 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16813 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16814 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16815 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16816 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16817 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16818 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16819 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16820 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16821 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16822 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16823 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16824 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16825 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16826 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16827 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16828 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16829 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16830 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16831 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16832 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16833 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16834 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16835 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16836 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16837 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16838 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16839 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16840 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16841 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16842 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16843 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16844 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16845 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16846 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16847 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16848 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16849 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16850 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16851 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16852 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16853 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16854 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16855 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16856 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16857 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16858 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16859 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16860 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16861 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16862 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16863 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16864 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16865 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16866 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16867 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16868 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16869 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16870 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16871 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16872 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16873 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16874 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16875 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16876 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16877 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16878 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16879 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16880 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16881 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16882 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16883 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16884 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16885 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16886 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16887 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16888 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16889 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16890 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16891 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16892 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16893 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16894 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16895 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16896 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16897 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16898 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16899 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16900 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16901 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16902 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16903 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16904 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16905 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16906 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16907 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16908 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16909 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16910 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16911 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16912 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16913 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16914 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16915 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16916 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16917 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16918 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16919 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16920 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16921 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16922 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16923 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16924 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16925 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16926 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16927 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16928 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16929 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16930 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16931 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16932 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16933 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16934 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16935 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16936 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16937 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16938 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16939 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16942 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16943 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16944 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16945 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16946 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16947 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16948 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16949 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16950 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16951 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16952 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16953 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16954 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16955 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16956 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16957 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16958 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16959 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16960 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16961 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16962 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16963 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16964 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16965 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16966 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16967 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16968 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16969 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16970 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16971 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16972 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16973 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16974 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16975 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16976 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16977 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16978 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16979 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16980 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16981 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16982 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16983 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16984 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16985 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16986 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16987 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16988 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16989 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16990 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16991 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16992 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16993 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16994 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16995 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16996 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16997 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16998 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16999 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17002 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
17003 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17004 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17005 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17006 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17007 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17008 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17009 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17010 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17011 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
17012 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
17013 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
17014 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
17015 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
17016 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
17017 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
17018 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
17019 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
17020 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
17021 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
17022 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
17023 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
17024 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
17025 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
17026 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
17027 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
17028 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
17029 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
17030 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
17031 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
17032 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
17033 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
17034 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
17035 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
17036 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
17037 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
17038 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
17039 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
17040 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
17041 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
17042 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
17043 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
17044 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
17045 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
17046 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
17047 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
17048 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
17049 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
17050 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
17051 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
17052 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
17053 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
17054 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
17055 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
17056 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
17057 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17058 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17059 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17060 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17061 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17062 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17063 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
17064 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
17065 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
17066 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
17067 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17068 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17069 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17070 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17071 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17072 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17073 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17074 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17075 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17076 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17077 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17078 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17081 #undef THUMB_VARIANT
17108 /* MD interface: bits in the object file. */
17110 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
17111 for use in the a.out file, and stores them in the array pointed to by buf.
17112 This knows about the endian-ness of the target machine and does
17113 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
17114 2 (short) and 4 (long) Floating numbers are put out as a series of
17115 LITTLENUMS (shorts, here at least). */
17118 md_number_to_chars (char * buf
, valueT val
, int n
)
17120 if (target_big_endian
)
17121 number_to_chars_bigendian (buf
, val
, n
);
17123 number_to_chars_littleendian (buf
, val
, n
);
17127 md_chars_to_number (char * buf
, int n
)
17130 unsigned char * where
= (unsigned char *) buf
;
17132 if (target_big_endian
)
17137 result
|= (*where
++ & 255);
17145 result
|= (where
[n
] & 255);
17152 /* MD interface: Sections. */
17154 /* Estimate the size of a frag before relaxing. Assume everything fits in
17158 md_estimate_size_before_relax (fragS
* fragp
,
17159 segT segtype ATTRIBUTE_UNUSED
)
17165 /* Convert a machine dependent frag. */
17168 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
17170 unsigned long insn
;
17171 unsigned long old_op
;
17179 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17181 old_op
= bfd_get_16(abfd
, buf
);
17182 if (fragp
->fr_symbol
)
17184 exp
.X_op
= O_symbol
;
17185 exp
.X_add_symbol
= fragp
->fr_symbol
;
17189 exp
.X_op
= O_constant
;
17191 exp
.X_add_number
= fragp
->fr_offset
;
17192 opcode
= fragp
->fr_subtype
;
17195 case T_MNEM_ldr_pc
:
17196 case T_MNEM_ldr_pc2
:
17197 case T_MNEM_ldr_sp
:
17198 case T_MNEM_str_sp
:
17205 if (fragp
->fr_var
== 4)
17207 insn
= THUMB_OP32 (opcode
);
17208 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
17210 insn
|= (old_op
& 0x700) << 4;
17214 insn
|= (old_op
& 7) << 12;
17215 insn
|= (old_op
& 0x38) << 13;
17217 insn
|= 0x00000c00;
17218 put_thumb32_insn (buf
, insn
);
17219 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
17223 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
17225 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
17228 if (fragp
->fr_var
== 4)
17230 insn
= THUMB_OP32 (opcode
);
17231 insn
|= (old_op
& 0xf0) << 4;
17232 put_thumb32_insn (buf
, insn
);
17233 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
17237 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
17238 exp
.X_add_number
-= 4;
17246 if (fragp
->fr_var
== 4)
17248 int r0off
= (opcode
== T_MNEM_mov
17249 || opcode
== T_MNEM_movs
) ? 0 : 8;
17250 insn
= THUMB_OP32 (opcode
);
17251 insn
= (insn
& 0xe1ffffff) | 0x10000000;
17252 insn
|= (old_op
& 0x700) << r0off
;
17253 put_thumb32_insn (buf
, insn
);
17254 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
17258 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
17263 if (fragp
->fr_var
== 4)
17265 insn
= THUMB_OP32(opcode
);
17266 put_thumb32_insn (buf
, insn
);
17267 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
17270 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
17274 if (fragp
->fr_var
== 4)
17276 insn
= THUMB_OP32(opcode
);
17277 insn
|= (old_op
& 0xf00) << 14;
17278 put_thumb32_insn (buf
, insn
);
17279 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
17282 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
17285 case T_MNEM_add_sp
:
17286 case T_MNEM_add_pc
:
17287 case T_MNEM_inc_sp
:
17288 case T_MNEM_dec_sp
:
17289 if (fragp
->fr_var
== 4)
17291 /* ??? Choose between add and addw. */
17292 insn
= THUMB_OP32 (opcode
);
17293 insn
|= (old_op
& 0xf0) << 4;
17294 put_thumb32_insn (buf
, insn
);
17295 if (opcode
== T_MNEM_add_pc
)
17296 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
17298 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
17301 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
17309 if (fragp
->fr_var
== 4)
17311 insn
= THUMB_OP32 (opcode
);
17312 insn
|= (old_op
& 0xf0) << 4;
17313 insn
|= (old_op
& 0xf) << 16;
17314 put_thumb32_insn (buf
, insn
);
17315 if (insn
& (1 << 20))
17316 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
17318 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
17321 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
17327 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
17329 fixp
->fx_file
= fragp
->fr_file
;
17330 fixp
->fx_line
= fragp
->fr_line
;
17331 fragp
->fr_fix
+= fragp
->fr_var
;
17334 /* Return the size of a relaxable immediate operand instruction.
17335 SHIFT and SIZE specify the form of the allowable immediate. */
17337 relax_immediate (fragS
*fragp
, int size
, int shift
)
17343 /* ??? Should be able to do better than this. */
17344 if (fragp
->fr_symbol
)
17347 low
= (1 << shift
) - 1;
17348 mask
= (1 << (shift
+ size
)) - (1 << shift
);
17349 offset
= fragp
->fr_offset
;
17350 /* Force misaligned offsets to 32-bit variant. */
17353 if (offset
& ~mask
)
17358 /* Get the address of a symbol during relaxation. */
17360 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
17366 sym
= fragp
->fr_symbol
;
17367 sym_frag
= symbol_get_frag (sym
);
17368 know (S_GET_SEGMENT (sym
) != absolute_section
17369 || sym_frag
== &zero_address_frag
);
17370 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
17372 /* If frag has yet to be reached on this pass, assume it will
17373 move by STRETCH just as we did. If this is not so, it will
17374 be because some frag between grows, and that will force
17378 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17382 /* Adjust stretch for any alignment frag. Note that if have
17383 been expanding the earlier code, the symbol may be
17384 defined in what appears to be an earlier frag. FIXME:
17385 This doesn't handle the fr_subtype field, which specifies
17386 a maximum number of bytes to skip when doing an
17388 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17390 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17393 stretch
= - ((- stretch
)
17394 & ~ ((1 << (int) f
->fr_offset
) - 1));
17396 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17408 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
17411 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
17416 /* Assume worst case for symbols not known to be in the same section. */
17417 if (!S_IS_DEFINED (fragp
->fr_symbol
)
17418 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
17421 val
= relaxed_symbol_addr (fragp
, stretch
);
17422 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17423 addr
= (addr
+ 4) & ~3;
17424 /* Force misaligned targets to 32-bit variant. */
17428 if (val
< 0 || val
> 1020)
17433 /* Return the size of a relaxable add/sub immediate instruction. */
17435 relax_addsub (fragS
*fragp
, asection
*sec
)
17440 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17441 op
= bfd_get_16(sec
->owner
, buf
);
17442 if ((op
& 0xf) == ((op
>> 4) & 0xf))
17443 return relax_immediate (fragp
, 8, 0);
17445 return relax_immediate (fragp
, 3, 0);
17449 /* Return the size of a relaxable branch instruction. BITS is the
17450 size of the offset field in the narrow instruction. */
17453 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
17459 /* Assume worst case for symbols not known to be in the same section. */
17460 if (!S_IS_DEFINED (fragp
->fr_symbol
)
17461 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
17464 val
= relaxed_symbol_addr (fragp
, stretch
);
17465 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17468 /* Offset is a signed value *2 */
17470 if (val
>= limit
|| val
< -limit
)
17476 /* Relax a machine dependent frag. This returns the amount by which
17477 the current size of the frag should change. */
17480 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17485 oldsize
= fragp
->fr_var
;
17486 switch (fragp
->fr_subtype
)
17488 case T_MNEM_ldr_pc2
:
17489 newsize
= relax_adr (fragp
, sec
, stretch
);
17491 case T_MNEM_ldr_pc
:
17492 case T_MNEM_ldr_sp
:
17493 case T_MNEM_str_sp
:
17494 newsize
= relax_immediate (fragp
, 8, 2);
17498 newsize
= relax_immediate (fragp
, 5, 2);
17502 newsize
= relax_immediate (fragp
, 5, 1);
17506 newsize
= relax_immediate (fragp
, 5, 0);
17509 newsize
= relax_adr (fragp
, sec
, stretch
);
17515 newsize
= relax_immediate (fragp
, 8, 0);
17518 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
17521 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
17523 case T_MNEM_add_sp
:
17524 case T_MNEM_add_pc
:
17525 newsize
= relax_immediate (fragp
, 8, 2);
17527 case T_MNEM_inc_sp
:
17528 case T_MNEM_dec_sp
:
17529 newsize
= relax_immediate (fragp
, 7, 2);
17535 newsize
= relax_addsub (fragp
, sec
);
17541 fragp
->fr_var
= newsize
;
17542 /* Freeze wide instructions that are at or before the same location as
17543 in the previous pass. This avoids infinite loops.
17544 Don't freeze them unconditionally because targets may be artificially
17545 misaligned by the expansion of preceding frags. */
17546 if (stretch
<= 0 && newsize
> 2)
17548 md_convert_frag (sec
->owner
, sec
, fragp
);
17552 return newsize
- oldsize
;
17555 /* Round up a section size to the appropriate boundary. */
17558 md_section_align (segT segment ATTRIBUTE_UNUSED
,
17561 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
17562 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
17564 /* For a.out, force the section size to be aligned. If we don't do
17565 this, BFD will align it for us, but it will not write out the
17566 final bytes of the section. This may be a bug in BFD, but it is
17567 easier to fix it here since that is how the other a.out targets
17571 align
= bfd_get_section_alignment (stdoutput
, segment
);
17572 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
17579 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
17580 of an rs_align_code fragment. */
17583 arm_handle_align (fragS
* fragP
)
17585 static char const arm_noop
[2][2][4] =
17588 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
17589 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
17592 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
17593 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
17596 static char const thumb_noop
[2][2][2] =
17599 {0xc0, 0x46}, /* LE */
17600 {0x46, 0xc0}, /* BE */
17603 {0x00, 0xbf}, /* LE */
17604 {0xbf, 0x00} /* BE */
17607 static char const wide_thumb_noop
[2][4] =
17608 { /* Wide Thumb-2 */
17609 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
17610 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
17613 unsigned bytes
, fix
, noop_size
;
17616 const char *narrow_noop
= NULL
;
17618 if (fragP
->fr_type
!= rs_align_code
)
17621 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
17622 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
17625 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17626 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
17628 assert ((fragP
->tc_frag_data
& MODE_RECORDED
) != 0);
17630 if (fragP
->tc_frag_data
& (~ MODE_RECORDED
))
17632 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
17634 narrow_noop
= thumb_noop
[1][target_big_endian
];
17635 noop
= wide_thumb_noop
[target_big_endian
];
17638 noop
= thumb_noop
[0][target_big_endian
];
17643 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
17644 [target_big_endian
];
17648 fragP
->fr_var
= noop_size
;
17650 if (bytes
& (noop_size
- 1))
17652 fix
= bytes
& (noop_size
- 1);
17653 memset (p
, 0, fix
);
17660 if (bytes
& noop_size
)
17662 /* Insert a narrow noop. */
17663 memcpy (p
, narrow_noop
, noop_size
);
17665 bytes
-= noop_size
;
17669 /* Use wide noops for the remainder */
17673 while (bytes
>= noop_size
)
17675 memcpy (p
, noop
, noop_size
);
17677 bytes
-= noop_size
;
17681 fragP
->fr_fix
+= fix
;
17684 /* Called from md_do_align. Used to create an alignment
17685 frag in a code section. */
17688 arm_frag_align_code (int n
, int max
)
17692 /* We assume that there will never be a requirement
17693 to support alignments greater than 32 bytes. */
17694 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17695 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17697 p
= frag_var (rs_align_code
,
17698 MAX_MEM_FOR_RS_ALIGN_CODE
,
17700 (relax_substateT
) max
,
17707 /* Perform target specific initialisation of a frag.
17708 Note - despite the name this initialisation is not done when the frag
17709 is created, but only when its type is assigned. A frag can be created
17710 and used a long time before its type is set, so beware of assuming that
17711 this initialisationis performed first. */
17714 arm_init_frag (fragS
* fragP
)
17716 /* If the current ARM vs THUMB mode has not already
17717 been recorded into this frag then do so now. */
17718 if ((fragP
->tc_frag_data
& MODE_RECORDED
) == 0)
17719 fragP
->tc_frag_data
= thumb_mode
| MODE_RECORDED
;
17723 /* When we change sections we need to issue a new mapping symbol. */
17726 arm_elf_change_section (void)
17729 segment_info_type
*seginfo
;
17731 /* Link an unlinked unwind index table section to the .text section. */
17732 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
17733 && elf_linked_to_section (now_seg
) == NULL
)
17734 elf_linked_to_section (now_seg
) = text_section
;
17736 if (!SEG_NORMAL (now_seg
))
17739 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
17741 /* We can ignore sections that only contain debug info. */
17742 if ((flags
& SEC_ALLOC
) == 0)
17745 seginfo
= seg_info (now_seg
);
17746 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
17747 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
17751 arm_elf_section_type (const char * str
, size_t len
)
17753 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
17754 return SHT_ARM_EXIDX
;
17759 /* Code to deal with unwinding tables. */
17761 static void add_unwind_adjustsp (offsetT
);
17763 /* Generate any deferred unwind frame offset. */
17766 flush_pending_unwind (void)
17770 offset
= unwind
.pending_offset
;
17771 unwind
.pending_offset
= 0;
17773 add_unwind_adjustsp (offset
);
17776 /* Add an opcode to this list for this function. Two-byte opcodes should
17777 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17781 add_unwind_opcode (valueT op
, int length
)
17783 /* Add any deferred stack adjustment. */
17784 if (unwind
.pending_offset
)
17785 flush_pending_unwind ();
17787 unwind
.sp_restored
= 0;
17789 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
17791 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
17792 if (unwind
.opcodes
)
17793 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
17794 unwind
.opcode_alloc
);
17796 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
17801 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
17803 unwind
.opcode_count
++;
17807 /* Add unwind opcodes to adjust the stack pointer. */
17810 add_unwind_adjustsp (offsetT offset
)
17814 if (offset
> 0x200)
17816 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17821 /* Long form: 0xb2, uleb128. */
17822 /* This might not fit in a word so add the individual bytes,
17823 remembering the list is built in reverse order. */
17824 o
= (valueT
) ((offset
- 0x204) >> 2);
17826 add_unwind_opcode (0, 1);
17828 /* Calculate the uleb128 encoding of the offset. */
17832 bytes
[n
] = o
& 0x7f;
17838 /* Add the insn. */
17840 add_unwind_opcode (bytes
[n
- 1], 1);
17841 add_unwind_opcode (0xb2, 1);
17843 else if (offset
> 0x100)
17845 /* Two short opcodes. */
17846 add_unwind_opcode (0x3f, 1);
17847 op
= (offset
- 0x104) >> 2;
17848 add_unwind_opcode (op
, 1);
17850 else if (offset
> 0)
17852 /* Short opcode. */
17853 op
= (offset
- 4) >> 2;
17854 add_unwind_opcode (op
, 1);
17856 else if (offset
< 0)
17859 while (offset
> 0x100)
17861 add_unwind_opcode (0x7f, 1);
17864 op
= ((offset
- 4) >> 2) | 0x40;
17865 add_unwind_opcode (op
, 1);
17869 /* Finish the list of unwind opcodes for this function. */
17871 finish_unwind_opcodes (void)
17875 if (unwind
.fp_used
)
17877 /* Adjust sp as necessary. */
17878 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
17879 flush_pending_unwind ();
17881 /* After restoring sp from the frame pointer. */
17882 op
= 0x90 | unwind
.fp_reg
;
17883 add_unwind_opcode (op
, 1);
17886 flush_pending_unwind ();
17890 /* Start an exception table entry. If idx is nonzero this is an index table
17894 start_unwind_section (const segT text_seg
, int idx
)
17896 const char * text_name
;
17897 const char * prefix
;
17898 const char * prefix_once
;
17899 const char * group_name
;
17903 size_t sec_name_len
;
17910 prefix
= ELF_STRING_ARM_unwind
;
17911 prefix_once
= ELF_STRING_ARM_unwind_once
;
17912 type
= SHT_ARM_EXIDX
;
17916 prefix
= ELF_STRING_ARM_unwind_info
;
17917 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17918 type
= SHT_PROGBITS
;
17921 text_name
= segment_name (text_seg
);
17922 if (streq (text_name
, ".text"))
17925 if (strncmp (text_name
, ".gnu.linkonce.t.",
17926 strlen (".gnu.linkonce.t.")) == 0)
17928 prefix
= prefix_once
;
17929 text_name
+= strlen (".gnu.linkonce.t.");
17932 prefix_len
= strlen (prefix
);
17933 text_len
= strlen (text_name
);
17934 sec_name_len
= prefix_len
+ text_len
;
17935 sec_name
= xmalloc (sec_name_len
+ 1);
17936 memcpy (sec_name
, prefix
, prefix_len
);
17937 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17938 sec_name
[prefix_len
+ text_len
] = '\0';
17944 /* Handle COMDAT group. */
17945 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17947 group_name
= elf_group_name (text_seg
);
17948 if (group_name
== NULL
)
17950 as_bad (_("Group section `%s' has no group signature"),
17951 segment_name (text_seg
));
17952 ignore_rest_of_line ();
17955 flags
|= SHF_GROUP
;
17959 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17961 /* Set the section link for index tables. */
17963 elf_linked_to_section (now_seg
) = text_seg
;
17967 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17968 personality routine data. Returns zero, or the index table value for
17969 and inline entry. */
17972 create_unwind_entry (int have_data
)
17977 /* The current word of data. */
17979 /* The number of bytes left in this word. */
17982 finish_unwind_opcodes ();
17984 /* Remember the current text section. */
17985 unwind
.saved_seg
= now_seg
;
17986 unwind
.saved_subseg
= now_subseg
;
17988 start_unwind_section (now_seg
, 0);
17990 if (unwind
.personality_routine
== NULL
)
17992 if (unwind
.personality_index
== -2)
17995 as_bad (_("handlerdata in cantunwind frame"));
17996 return 1; /* EXIDX_CANTUNWIND. */
17999 /* Use a default personality routine if none is specified. */
18000 if (unwind
.personality_index
== -1)
18002 if (unwind
.opcode_count
> 3)
18003 unwind
.personality_index
= 1;
18005 unwind
.personality_index
= 0;
18008 /* Space for the personality routine entry. */
18009 if (unwind
.personality_index
== 0)
18011 if (unwind
.opcode_count
> 3)
18012 as_bad (_("too many unwind opcodes for personality routine 0"));
18016 /* All the data is inline in the index table. */
18019 while (unwind
.opcode_count
> 0)
18021 unwind
.opcode_count
--;
18022 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
18026 /* Pad with "finish" opcodes. */
18028 data
= (data
<< 8) | 0xb0;
18035 /* We get two opcodes "free" in the first word. */
18036 size
= unwind
.opcode_count
- 2;
18039 /* An extra byte is required for the opcode count. */
18040 size
= unwind
.opcode_count
+ 1;
18042 size
= (size
+ 3) >> 2;
18044 as_bad (_("too many unwind opcodes"));
18046 frag_align (2, 0, 0);
18047 record_alignment (now_seg
, 2);
18048 unwind
.table_entry
= expr_build_dot ();
18050 /* Allocate the table entry. */
18051 ptr
= frag_more ((size
<< 2) + 4);
18052 where
= frag_now_fix () - ((size
<< 2) + 4);
18054 switch (unwind
.personality_index
)
18057 /* ??? Should this be a PLT generating relocation? */
18058 /* Custom personality routine. */
18059 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
18060 BFD_RELOC_ARM_PREL31
);
18065 /* Set the first byte to the number of additional words. */
18070 /* ABI defined personality routines. */
18072 /* Three opcodes bytes are packed into the first word. */
18079 /* The size and first two opcode bytes go in the first word. */
18080 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
18085 /* Should never happen. */
18089 /* Pack the opcodes into words (MSB first), reversing the list at the same
18091 while (unwind
.opcode_count
> 0)
18095 md_number_to_chars (ptr
, data
, 4);
18100 unwind
.opcode_count
--;
18102 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
18105 /* Finish off the last word. */
18108 /* Pad with "finish" opcodes. */
18110 data
= (data
<< 8) | 0xb0;
18112 md_number_to_chars (ptr
, data
, 4);
18117 /* Add an empty descriptor if there is no user-specified data. */
18118 ptr
= frag_more (4);
18119 md_number_to_chars (ptr
, 0, 4);
18126 /* Initialize the DWARF-2 unwind information for this procedure. */
18129 tc_arm_frame_initial_instructions (void)
18131 cfi_add_CFA_def_cfa (REG_SP
, 0);
18133 #endif /* OBJ_ELF */
18135 /* Convert REGNAME to a DWARF-2 register number. */
18138 tc_arm_regname_to_dw2regnum (char *regname
)
18140 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
18150 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
18154 expr
.X_op
= O_secrel
;
18155 expr
.X_add_symbol
= symbol
;
18156 expr
.X_add_number
= 0;
18157 emit_expr (&expr
, size
);
18161 /* MD interface: Symbol and relocation handling. */
18163 /* Return the address within the segment that a PC-relative fixup is
18164 relative to. For ARM, PC-relative fixups applied to instructions
18165 are generally relative to the location of the fixup plus 8 bytes.
18166 Thumb branches are offset by 4, and Thumb loads relative to PC
18167 require special handling. */
18170 md_pcrel_from_section (fixS
* fixP
, segT seg
)
18172 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
18174 /* If this is pc-relative and we are going to emit a relocation
18175 then we just want to put out any pipeline compensation that the linker
18176 will need. Otherwise we want to use the calculated base.
18177 For WinCE we skip the bias for externals as well, since this
18178 is how the MS ARM-CE assembler behaves and we want to be compatible. */
18180 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
18181 || (arm_force_relocation (fixP
)
18183 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
18188 switch (fixP
->fx_r_type
)
18190 /* PC relative addressing on the Thumb is slightly odd as the
18191 bottom two bits of the PC are forced to zero for the
18192 calculation. This happens *after* application of the
18193 pipeline offset. However, Thumb adrl already adjusts for
18194 this, so we need not do it again. */
18195 case BFD_RELOC_ARM_THUMB_ADD
:
18198 case BFD_RELOC_ARM_THUMB_OFFSET
:
18199 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18200 case BFD_RELOC_ARM_T32_ADD_PC12
:
18201 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18202 return (base
+ 4) & ~3;
18204 /* Thumb branches are simply offset by +4. */
18205 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
18206 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
18207 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
18208 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18209 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18210 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18213 /* BLX is like branches above, but forces the low two bits of PC to
18215 case BFD_RELOC_THUMB_PCREL_BLX
:
18216 return (base
+ 4) & ~3;
18218 /* ARM mode branches are offset by +8. However, the Windows CE
18219 loader expects the relocation not to take this into account. */
18220 case BFD_RELOC_ARM_PCREL_BRANCH
:
18221 case BFD_RELOC_ARM_PCREL_CALL
:
18222 case BFD_RELOC_ARM_PCREL_JUMP
:
18223 case BFD_RELOC_ARM_PCREL_BLX
:
18224 case BFD_RELOC_ARM_PLT32
:
18226 /* When handling fixups immediately, because we have already
18227 discovered the value of a symbol, or the address of the frag involved
18228 we must account for the offset by +8, as the OS loader will never see the reloc.
18229 see fixup_segment() in write.c
18230 The S_IS_EXTERNAL test handles the case of global symbols.
18231 Those need the calculated base, not just the pipe compensation the linker will need. */
18233 && fixP
->fx_addsy
!= NULL
18234 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
18235 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
18242 /* ARM mode loads relative to PC are also offset by +8. Unlike
18243 branches, the Windows CE loader *does* expect the relocation
18244 to take this into account. */
18245 case BFD_RELOC_ARM_OFFSET_IMM
:
18246 case BFD_RELOC_ARM_OFFSET_IMM8
:
18247 case BFD_RELOC_ARM_HWLITERAL
:
18248 case BFD_RELOC_ARM_LITERAL
:
18249 case BFD_RELOC_ARM_CP_OFF_IMM
:
18253 /* Other PC-relative relocations are un-offset. */
18259 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
18260 Otherwise we have no need to default values of symbols. */
18263 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
18266 if (name
[0] == '_' && name
[1] == 'G'
18267 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
18271 if (symbol_find (name
))
18272 as_bad (_("GOT already in the symbol table"));
18274 GOT_symbol
= symbol_new (name
, undefined_section
,
18275 (valueT
) 0, & zero_address_frag
);
18285 /* Subroutine of md_apply_fix. Check to see if an immediate can be
18286 computed as two separate immediate values, added together. We
18287 already know that this value cannot be computed by just one ARM
18290 static unsigned int
18291 validate_immediate_twopart (unsigned int val
,
18292 unsigned int * highpart
)
18297 for (i
= 0; i
< 32; i
+= 2)
18298 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
18304 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
18306 else if (a
& 0xff0000)
18308 if (a
& 0xff000000)
18310 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
18314 assert (a
& 0xff000000);
18315 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
18318 return (a
& 0xff) | (i
<< 7);
18325 validate_offset_imm (unsigned int val
, int hwse
)
18327 if ((hwse
&& val
> 255) || val
> 4095)
18332 /* Subroutine of md_apply_fix. Do those data_ops which can take a
18333 negative immediate constant by altering the instruction. A bit of
18338 by inverting the second operand, and
18341 by negating the second operand. */
18344 negate_data_op (unsigned long * instruction
,
18345 unsigned long value
)
18348 unsigned long negated
, inverted
;
18350 negated
= encode_arm_immediate (-value
);
18351 inverted
= encode_arm_immediate (~value
);
18353 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
18356 /* First negates. */
18357 case OPCODE_SUB
: /* ADD <-> SUB */
18358 new_inst
= OPCODE_ADD
;
18363 new_inst
= OPCODE_SUB
;
18367 case OPCODE_CMP
: /* CMP <-> CMN */
18368 new_inst
= OPCODE_CMN
;
18373 new_inst
= OPCODE_CMP
;
18377 /* Now Inverted ops. */
18378 case OPCODE_MOV
: /* MOV <-> MVN */
18379 new_inst
= OPCODE_MVN
;
18384 new_inst
= OPCODE_MOV
;
18388 case OPCODE_AND
: /* AND <-> BIC */
18389 new_inst
= OPCODE_BIC
;
18394 new_inst
= OPCODE_AND
;
18398 case OPCODE_ADC
: /* ADC <-> SBC */
18399 new_inst
= OPCODE_SBC
;
18404 new_inst
= OPCODE_ADC
;
18408 /* We cannot do anything. */
18413 if (value
== (unsigned) FAIL
)
18416 *instruction
&= OPCODE_MASK
;
18417 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
18421 /* Like negate_data_op, but for Thumb-2. */
18423 static unsigned int
18424 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
18428 unsigned int negated
, inverted
;
18430 negated
= encode_thumb32_immediate (-value
);
18431 inverted
= encode_thumb32_immediate (~value
);
18433 rd
= (*instruction
>> 8) & 0xf;
18434 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
18437 /* ADD <-> SUB. Includes CMP <-> CMN. */
18438 case T2_OPCODE_SUB
:
18439 new_inst
= T2_OPCODE_ADD
;
18443 case T2_OPCODE_ADD
:
18444 new_inst
= T2_OPCODE_SUB
;
18448 /* ORR <-> ORN. Includes MOV <-> MVN. */
18449 case T2_OPCODE_ORR
:
18450 new_inst
= T2_OPCODE_ORN
;
18454 case T2_OPCODE_ORN
:
18455 new_inst
= T2_OPCODE_ORR
;
18459 /* AND <-> BIC. TST has no inverted equivalent. */
18460 case T2_OPCODE_AND
:
18461 new_inst
= T2_OPCODE_BIC
;
18468 case T2_OPCODE_BIC
:
18469 new_inst
= T2_OPCODE_AND
;
18474 case T2_OPCODE_ADC
:
18475 new_inst
= T2_OPCODE_SBC
;
18479 case T2_OPCODE_SBC
:
18480 new_inst
= T2_OPCODE_ADC
;
18484 /* We cannot do anything. */
18489 if (value
== (unsigned int)FAIL
)
18492 *instruction
&= T2_OPCODE_MASK
;
18493 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
18497 /* Read a 32-bit thumb instruction from buf. */
18498 static unsigned long
18499 get_thumb32_insn (char * buf
)
18501 unsigned long insn
;
18502 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
18503 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18509 /* We usually want to set the low bit on the address of thumb function
18510 symbols. In particular .word foo - . should have the low bit set.
18511 Generic code tries to fold the difference of two symbols to
18512 a constant. Prevent this and force a relocation when the first symbols
18513 is a thumb function. */
18515 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
18517 if (op
== O_subtract
18518 && l
->X_op
== O_symbol
18519 && r
->X_op
== O_symbol
18520 && THUMB_IS_FUNC (l
->X_add_symbol
))
18522 l
->X_op
= O_subtract
;
18523 l
->X_op_symbol
= r
->X_add_symbol
;
18524 l
->X_add_number
-= r
->X_add_number
;
18527 /* Process as normal. */
18532 md_apply_fix (fixS
* fixP
,
18536 offsetT value
= * valP
;
18538 unsigned int newimm
;
18539 unsigned long temp
;
18541 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
18543 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
18545 /* Note whether this will delete the relocation. */
18547 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
18550 /* On a 64-bit host, silently truncate 'value' to 32 bits for
18551 consistency with the behaviour on 32-bit hosts. Remember value
18553 value
&= 0xffffffff;
18554 value
^= 0x80000000;
18555 value
-= 0x80000000;
18558 fixP
->fx_addnumber
= value
;
18560 /* Same treatment for fixP->fx_offset. */
18561 fixP
->fx_offset
&= 0xffffffff;
18562 fixP
->fx_offset
^= 0x80000000;
18563 fixP
->fx_offset
-= 0x80000000;
18565 switch (fixP
->fx_r_type
)
18567 case BFD_RELOC_NONE
:
18568 /* This will need to go in the object file. */
18572 case BFD_RELOC_ARM_IMMEDIATE
:
18573 /* We claim that this fixup has been processed here,
18574 even if in fact we generate an error because we do
18575 not have a reloc for it, so tc_gen_reloc will reject it. */
18579 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18581 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18582 _("undefined symbol %s used as an immediate value"),
18583 S_GET_NAME (fixP
->fx_addsy
));
18588 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
18590 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18591 _("symbol %s is in a different section"),
18592 S_GET_NAME (fixP
->fx_addsy
));
18596 newimm
= encode_arm_immediate (value
);
18597 temp
= md_chars_to_number (buf
, INSN_SIZE
);
18599 /* If the instruction will fail, see if we can fix things up by
18600 changing the opcode. */
18601 if (newimm
== (unsigned int) FAIL
18602 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
18604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18605 _("invalid constant (%lx) after fixup"),
18606 (unsigned long) value
);
18610 newimm
|= (temp
& 0xfffff000);
18611 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18614 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18616 unsigned int highpart
= 0;
18617 unsigned int newinsn
= 0xe1a00000; /* nop. */
18620 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18622 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18623 _("undefined symbol %s used as an immediate value"),
18624 S_GET_NAME (fixP
->fx_addsy
));
18629 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
18631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18632 _("symbol %s is in a different section"),
18633 S_GET_NAME (fixP
->fx_addsy
));
18637 newimm
= encode_arm_immediate (value
);
18638 temp
= md_chars_to_number (buf
, INSN_SIZE
);
18640 /* If the instruction will fail, see if we can fix things up by
18641 changing the opcode. */
18642 if (newimm
== (unsigned int) FAIL
18643 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
18645 /* No ? OK - try using two ADD instructions to generate
18647 newimm
= validate_immediate_twopart (value
, & highpart
);
18649 /* Yes - then make sure that the second instruction is
18651 if (newimm
!= (unsigned int) FAIL
)
18653 /* Still No ? Try using a negated value. */
18654 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
18655 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
18656 /* Otherwise - give up. */
18659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18660 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18665 /* Replace the first operand in the 2nd instruction (which
18666 is the PC) with the destination register. We have
18667 already added in the PC in the first instruction and we
18668 do not want to do it again. */
18669 newinsn
&= ~ 0xf0000;
18670 newinsn
|= ((newinsn
& 0x0f000) << 4);
18673 newimm
|= (temp
& 0xfffff000);
18674 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18676 highpart
|= (newinsn
& 0xfffff000);
18677 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
18681 case BFD_RELOC_ARM_OFFSET_IMM
:
18682 if (!fixP
->fx_done
&& seg
->use_rela_p
)
18685 case BFD_RELOC_ARM_LITERAL
:
18691 if (validate_offset_imm (value
, 0) == FAIL
)
18693 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
18694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18695 _("invalid literal constant: pool needs to be closer"));
18697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18698 _("bad immediate value for offset (%ld)"),
18703 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18704 newval
&= 0xff7ff000;
18705 newval
|= value
| (sign
? INDEX_UP
: 0);
18706 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18709 case BFD_RELOC_ARM_OFFSET_IMM8
:
18710 case BFD_RELOC_ARM_HWLITERAL
:
18716 if (validate_offset_imm (value
, 1) == FAIL
)
18718 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
18719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18720 _("invalid literal constant: pool needs to be closer"));
18722 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18727 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18728 newval
&= 0xff7ff0f0;
18729 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
18730 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18733 case BFD_RELOC_ARM_T32_OFFSET_U8
:
18734 if (value
< 0 || value
> 1020 || value
% 4 != 0)
18735 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18736 _("bad immediate value for offset (%ld)"), (long) value
);
18739 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
18741 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
18744 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18745 /* This is a complicated relocation used for all varieties of Thumb32
18746 load/store instruction with immediate offset:
18748 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18749 *4, optional writeback(W)
18750 (doubleword load/store)
18752 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18753 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18754 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18755 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18756 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18758 Uppercase letters indicate bits that are already encoded at
18759 this point. Lowercase letters are our problem. For the
18760 second block of instructions, the secondary opcode nybble
18761 (bits 8..11) is present, and bit 23 is zero, even if this is
18762 a PC-relative operation. */
18763 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18765 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
18767 if ((newval
& 0xf0000000) == 0xe0000000)
18769 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18771 newval
|= (1 << 23);
18774 if (value
% 4 != 0)
18776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18777 _("offset not a multiple of 4"));
18783 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18784 _("offset out of range"));
18789 else if ((newval
& 0x000f0000) == 0x000f0000)
18791 /* PC-relative, 12-bit offset. */
18793 newval
|= (1 << 23);
18798 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18799 _("offset out of range"));
18804 else if ((newval
& 0x00000100) == 0x00000100)
18806 /* Writeback: 8-bit, +/- offset. */
18808 newval
|= (1 << 9);
18813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18814 _("offset out of range"));
18819 else if ((newval
& 0x00000f00) == 0x00000e00)
18821 /* T-instruction: positive 8-bit offset. */
18822 if (value
< 0 || value
> 0xff)
18824 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18825 _("offset out of range"));
18833 /* Positive 12-bit or negative 8-bit offset. */
18837 newval
|= (1 << 23);
18847 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18848 _("offset out of range"));
18855 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
18856 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
18859 case BFD_RELOC_ARM_SHIFT_IMM
:
18860 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18861 if (((unsigned long) value
) > 32
18863 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
18865 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18866 _("shift expression is too large"));
18871 /* Shifts of zero must be done as lsl. */
18873 else if (value
== 32)
18875 newval
&= 0xfffff07f;
18876 newval
|= (value
& 0x1f) << 7;
18877 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18880 case BFD_RELOC_ARM_T32_IMMEDIATE
:
18881 case BFD_RELOC_ARM_T32_ADD_IMM
:
18882 case BFD_RELOC_ARM_T32_IMM12
:
18883 case BFD_RELOC_ARM_T32_ADD_PC12
:
18884 /* We claim that this fixup has been processed here,
18885 even if in fact we generate an error because we do
18886 not have a reloc for it, so tc_gen_reloc will reject it. */
18890 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18893 _("undefined symbol %s used as an immediate value"),
18894 S_GET_NAME (fixP
->fx_addsy
));
18898 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18900 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
18903 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18904 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18906 newimm
= encode_thumb32_immediate (value
);
18907 if (newimm
== (unsigned int) FAIL
)
18908 newimm
= thumb32_negate_data_op (&newval
, value
);
18910 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
18911 && newimm
== (unsigned int) FAIL
)
18913 /* Turn add/sum into addw/subw. */
18914 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18915 newval
= (newval
& 0xfeffffff) | 0x02000000;
18917 /* 12 bit immediate for addw/subw. */
18921 newval
^= 0x00a00000;
18924 newimm
= (unsigned int) FAIL
;
18929 if (newimm
== (unsigned int)FAIL
)
18931 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18932 _("invalid constant (%lx) after fixup"),
18933 (unsigned long) value
);
18937 newval
|= (newimm
& 0x800) << 15;
18938 newval
|= (newimm
& 0x700) << 4;
18939 newval
|= (newimm
& 0x0ff);
18941 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18942 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18945 case BFD_RELOC_ARM_SMC
:
18946 if (((unsigned long) value
) > 0xffff)
18947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18948 _("invalid smc expression"));
18949 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18950 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18951 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18954 case BFD_RELOC_ARM_SWI
:
18955 if (fixP
->tc_fix_data
!= 0)
18957 if (((unsigned long) value
) > 0xff)
18958 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18959 _("invalid swi expression"));
18960 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18962 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18966 if (((unsigned long) value
) > 0x00ffffff)
18967 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18968 _("invalid swi expression"));
18969 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18971 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18975 case BFD_RELOC_ARM_MULTI
:
18976 if (((unsigned long) value
) > 0xffff)
18977 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18978 _("invalid expression in load/store multiple"));
18979 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
18980 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18984 case BFD_RELOC_ARM_PCREL_CALL
:
18985 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18986 if ((newval
& 0xf0000000) == 0xf0000000)
18990 goto arm_branch_common
;
18992 case BFD_RELOC_ARM_PCREL_JUMP
:
18993 case BFD_RELOC_ARM_PLT32
:
18995 case BFD_RELOC_ARM_PCREL_BRANCH
:
18997 goto arm_branch_common
;
18999 case BFD_RELOC_ARM_PCREL_BLX
:
19002 /* We are going to store value (shifted right by two) in the
19003 instruction, in a 24 bit, signed field. Bits 26 through 32 either
19004 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
19005 also be be clear. */
19007 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19008 _("misaligned branch destination"));
19009 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
19010 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
19011 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19012 _("branch out of range"));
19014 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19016 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19017 newval
|= (value
>> 2) & 0x00ffffff;
19018 /* Set the H bit on BLX instructions. */
19022 newval
|= 0x01000000;
19024 newval
&= ~0x01000000;
19026 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19030 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
19031 /* CBZ can only branch forward. */
19033 /* Attempts to use CBZ to branch to the next instruction
19034 (which, strictly speaking, are prohibited) will be turned into
19037 FIXME: It may be better to remove the instruction completely and
19038 perform relaxation. */
19041 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19042 newval
= 0xbf00; /* NOP encoding T1 */
19043 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19048 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19049 _("branch out of range"));
19051 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19053 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19054 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
19055 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19060 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
19061 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
19062 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19063 _("branch out of range"));
19065 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19067 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19068 newval
|= (value
& 0x1ff) >> 1;
19069 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19073 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
19074 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
19075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19076 _("branch out of range"));
19078 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19080 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19081 newval
|= (value
& 0xfff) >> 1;
19082 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19086 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19087 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
19088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19089 _("conditional branch out of range"));
19091 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19094 addressT S
, J1
, J2
, lo
, hi
;
19096 S
= (value
& 0x00100000) >> 20;
19097 J2
= (value
& 0x00080000) >> 19;
19098 J1
= (value
& 0x00040000) >> 18;
19099 hi
= (value
& 0x0003f000) >> 12;
19100 lo
= (value
& 0x00000ffe) >> 1;
19102 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19103 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19104 newval
|= (S
<< 10) | hi
;
19105 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
19106 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19107 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19111 case BFD_RELOC_THUMB_PCREL_BLX
:
19112 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19113 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
19114 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19115 _("branch out of range"));
19117 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
19118 /* For a BLX instruction, make sure that the relocation is rounded up
19119 to a word boundary. This follows the semantics of the instruction
19120 which specifies that bit 1 of the target address will come from bit
19121 1 of the base address. */
19122 value
= (value
+ 1) & ~ 1;
19124 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19128 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19129 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19130 newval
|= (value
& 0x7fffff) >> 12;
19131 newval2
|= (value
& 0xfff) >> 1;
19132 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19133 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19137 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19138 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
19139 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19140 _("branch out of range"));
19142 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19145 addressT S
, I1
, I2
, lo
, hi
;
19147 S
= (value
& 0x01000000) >> 24;
19148 I1
= (value
& 0x00800000) >> 23;
19149 I2
= (value
& 0x00400000) >> 22;
19150 hi
= (value
& 0x003ff000) >> 12;
19151 lo
= (value
& 0x00000ffe) >> 1;
19156 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19157 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19158 newval
|= (S
<< 10) | hi
;
19159 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
19160 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19161 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19166 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19167 md_number_to_chars (buf
, value
, 1);
19171 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19172 md_number_to_chars (buf
, value
, 2);
19176 case BFD_RELOC_ARM_TLS_GD32
:
19177 case BFD_RELOC_ARM_TLS_LE32
:
19178 case BFD_RELOC_ARM_TLS_IE32
:
19179 case BFD_RELOC_ARM_TLS_LDM32
:
19180 case BFD_RELOC_ARM_TLS_LDO32
:
19181 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
19184 case BFD_RELOC_ARM_GOT32
:
19185 case BFD_RELOC_ARM_GOTOFF
:
19186 case BFD_RELOC_ARM_TARGET2
:
19187 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19188 md_number_to_chars (buf
, 0, 4);
19192 case BFD_RELOC_RVA
:
19194 case BFD_RELOC_ARM_TARGET1
:
19195 case BFD_RELOC_ARM_ROSEGREL32
:
19196 case BFD_RELOC_ARM_SBREL32
:
19197 case BFD_RELOC_32_PCREL
:
19199 case BFD_RELOC_32_SECREL
:
19201 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19203 /* For WinCE we only do this for pcrel fixups. */
19204 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
19206 md_number_to_chars (buf
, value
, 4);
19210 case BFD_RELOC_ARM_PREL31
:
19211 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19213 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
19214 if ((value
^ (value
>> 1)) & 0x40000000)
19216 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19217 _("rel31 relocation overflow"));
19219 newval
|= value
& 0x7fffffff;
19220 md_number_to_chars (buf
, newval
, 4);
19225 case BFD_RELOC_ARM_CP_OFF_IMM
:
19226 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19227 if (value
< -1023 || value
> 1023 || (value
& 3))
19228 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19229 _("co-processor offset out of range"));
19234 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
19235 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
19236 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19238 newval
= get_thumb32_insn (buf
);
19239 newval
&= 0xff7fff00;
19240 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
19241 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
19242 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
19243 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19245 put_thumb32_insn (buf
, newval
);
19248 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
19249 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
19250 if (value
< -255 || value
> 255)
19251 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19252 _("co-processor offset out of range"));
19254 goto cp_off_common
;
19256 case BFD_RELOC_ARM_THUMB_OFFSET
:
19257 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19258 /* Exactly what ranges, and where the offset is inserted depends
19259 on the type of instruction, we can establish this from the
19261 switch (newval
>> 12)
19263 case 4: /* PC load. */
19264 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
19265 forced to zero for these loads; md_pcrel_from has already
19266 compensated for this. */
19268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19269 _("invalid offset, target not word aligned (0x%08lX)"),
19270 (((unsigned long) fixP
->fx_frag
->fr_address
19271 + (unsigned long) fixP
->fx_where
) & ~3)
19272 + (unsigned long) value
);
19274 if (value
& ~0x3fc)
19275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19276 _("invalid offset, value too big (0x%08lX)"),
19279 newval
|= value
>> 2;
19282 case 9: /* SP load/store. */
19283 if (value
& ~0x3fc)
19284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19285 _("invalid offset, value too big (0x%08lX)"),
19287 newval
|= value
>> 2;
19290 case 6: /* Word load/store. */
19292 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19293 _("invalid offset, value too big (0x%08lX)"),
19295 newval
|= value
<< 4; /* 6 - 2. */
19298 case 7: /* Byte load/store. */
19300 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19301 _("invalid offset, value too big (0x%08lX)"),
19303 newval
|= value
<< 6;
19306 case 8: /* Halfword load/store. */
19308 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19309 _("invalid offset, value too big (0x%08lX)"),
19311 newval
|= value
<< 5; /* 6 - 1. */
19315 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19316 "Unable to process relocation for thumb opcode: %lx",
19317 (unsigned long) newval
);
19320 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19323 case BFD_RELOC_ARM_THUMB_ADD
:
19324 /* This is a complicated relocation, since we use it for all of
19325 the following immediate relocations:
19329 9bit ADD/SUB SP word-aligned
19330 10bit ADD PC/SP word-aligned
19332 The type of instruction being processed is encoded in the
19339 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19341 int rd
= (newval
>> 4) & 0xf;
19342 int rs
= newval
& 0xf;
19343 int subtract
= !!(newval
& 0x8000);
19345 /* Check for HI regs, only very restricted cases allowed:
19346 Adjusting SP, and using PC or SP to get an address. */
19347 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
19348 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
19349 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19350 _("invalid Hi register with immediate"));
19352 /* If value is negative, choose the opposite instruction. */
19356 subtract
= !subtract
;
19358 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19359 _("immediate value out of range"));
19364 if (value
& ~0x1fc)
19365 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19366 _("invalid immediate for stack address calculation"));
19367 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
19368 newval
|= value
>> 2;
19370 else if (rs
== REG_PC
|| rs
== REG_SP
)
19372 if (subtract
|| value
& ~0x3fc)
19373 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19374 _("invalid immediate for address calculation (value = 0x%08lX)"),
19375 (unsigned long) value
);
19376 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
19378 newval
|= value
>> 2;
19383 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19384 _("immediate value out of range"));
19385 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
19386 newval
|= (rd
<< 8) | value
;
19391 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19392 _("immediate value out of range"));
19393 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
19394 newval
|= rd
| (rs
<< 3) | (value
<< 6);
19397 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19400 case BFD_RELOC_ARM_THUMB_IMM
:
19401 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19402 if (value
< 0 || value
> 255)
19403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19404 _("invalid immediate: %ld is out of range"),
19407 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19410 case BFD_RELOC_ARM_THUMB_SHIFT
:
19411 /* 5bit shift value (0..32). LSL cannot take 32. */
19412 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
19413 temp
= newval
& 0xf800;
19414 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
19415 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19416 _("invalid shift value: %ld"), (long) value
);
19417 /* Shifts of zero must be encoded as LSL. */
19419 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
19420 /* Shifts of 32 are encoded as zero. */
19421 else if (value
== 32)
19423 newval
|= value
<< 6;
19424 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19427 case BFD_RELOC_VTABLE_INHERIT
:
19428 case BFD_RELOC_VTABLE_ENTRY
:
19432 case BFD_RELOC_ARM_MOVW
:
19433 case BFD_RELOC_ARM_MOVT
:
19434 case BFD_RELOC_ARM_THUMB_MOVW
:
19435 case BFD_RELOC_ARM_THUMB_MOVT
:
19436 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19438 /* REL format relocations are limited to a 16-bit addend. */
19439 if (!fixP
->fx_done
)
19441 if (value
< -0x8000 || value
> 0x7fff)
19442 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19443 _("offset out of range"));
19445 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
19446 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
19451 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
19452 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
19454 newval
= get_thumb32_insn (buf
);
19455 newval
&= 0xfbf08f00;
19456 newval
|= (value
& 0xf000) << 4;
19457 newval
|= (value
& 0x0800) << 15;
19458 newval
|= (value
& 0x0700) << 4;
19459 newval
|= (value
& 0x00ff);
19460 put_thumb32_insn (buf
, newval
);
19464 newval
= md_chars_to_number (buf
, 4);
19465 newval
&= 0xfff0f000;
19466 newval
|= value
& 0x0fff;
19467 newval
|= (value
& 0xf000) << 4;
19468 md_number_to_chars (buf
, newval
, 4);
19473 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19474 case BFD_RELOC_ARM_ALU_PC_G0
:
19475 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19476 case BFD_RELOC_ARM_ALU_PC_G1
:
19477 case BFD_RELOC_ARM_ALU_PC_G2
:
19478 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19479 case BFD_RELOC_ARM_ALU_SB_G0
:
19480 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19481 case BFD_RELOC_ARM_ALU_SB_G1
:
19482 case BFD_RELOC_ARM_ALU_SB_G2
:
19483 assert (!fixP
->fx_done
);
19484 if (!seg
->use_rela_p
)
19487 bfd_vma encoded_addend
;
19488 bfd_vma addend_abs
= abs (value
);
19490 /* Check that the absolute value of the addend can be
19491 expressed as an 8-bit constant plus a rotation. */
19492 encoded_addend
= encode_arm_immediate (addend_abs
);
19493 if (encoded_addend
== (unsigned int) FAIL
)
19494 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19495 _("the offset 0x%08lX is not representable"),
19496 (unsigned long) addend_abs
);
19498 /* Extract the instruction. */
19499 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19501 /* If the addend is positive, use an ADD instruction.
19502 Otherwise use a SUB. Take care not to destroy the S bit. */
19503 insn
&= 0xff1fffff;
19509 /* Place the encoded addend into the first 12 bits of the
19511 insn
&= 0xfffff000;
19512 insn
|= encoded_addend
;
19514 /* Update the instruction. */
19515 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19519 case BFD_RELOC_ARM_LDR_PC_G0
:
19520 case BFD_RELOC_ARM_LDR_PC_G1
:
19521 case BFD_RELOC_ARM_LDR_PC_G2
:
19522 case BFD_RELOC_ARM_LDR_SB_G0
:
19523 case BFD_RELOC_ARM_LDR_SB_G1
:
19524 case BFD_RELOC_ARM_LDR_SB_G2
:
19525 assert (!fixP
->fx_done
);
19526 if (!seg
->use_rela_p
)
19529 bfd_vma addend_abs
= abs (value
);
19531 /* Check that the absolute value of the addend can be
19532 encoded in 12 bits. */
19533 if (addend_abs
>= 0x1000)
19534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19535 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
19536 (unsigned long) addend_abs
);
19538 /* Extract the instruction. */
19539 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19541 /* If the addend is negative, clear bit 23 of the instruction.
19542 Otherwise set it. */
19544 insn
&= ~(1 << 23);
19548 /* Place the absolute value of the addend into the first 12 bits
19549 of the instruction. */
19550 insn
&= 0xfffff000;
19551 insn
|= addend_abs
;
19553 /* Update the instruction. */
19554 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19558 case BFD_RELOC_ARM_LDRS_PC_G0
:
19559 case BFD_RELOC_ARM_LDRS_PC_G1
:
19560 case BFD_RELOC_ARM_LDRS_PC_G2
:
19561 case BFD_RELOC_ARM_LDRS_SB_G0
:
19562 case BFD_RELOC_ARM_LDRS_SB_G1
:
19563 case BFD_RELOC_ARM_LDRS_SB_G2
:
19564 assert (!fixP
->fx_done
);
19565 if (!seg
->use_rela_p
)
19568 bfd_vma addend_abs
= abs (value
);
19570 /* Check that the absolute value of the addend can be
19571 encoded in 8 bits. */
19572 if (addend_abs
>= 0x100)
19573 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19574 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
19575 (unsigned long) addend_abs
);
19577 /* Extract the instruction. */
19578 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19580 /* If the addend is negative, clear bit 23 of the instruction.
19581 Otherwise set it. */
19583 insn
&= ~(1 << 23);
19587 /* Place the first four bits of the absolute value of the addend
19588 into the first 4 bits of the instruction, and the remaining
19589 four into bits 8 .. 11. */
19590 insn
&= 0xfffff0f0;
19591 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
19593 /* Update the instruction. */
19594 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19598 case BFD_RELOC_ARM_LDC_PC_G0
:
19599 case BFD_RELOC_ARM_LDC_PC_G1
:
19600 case BFD_RELOC_ARM_LDC_PC_G2
:
19601 case BFD_RELOC_ARM_LDC_SB_G0
:
19602 case BFD_RELOC_ARM_LDC_SB_G1
:
19603 case BFD_RELOC_ARM_LDC_SB_G2
:
19604 assert (!fixP
->fx_done
);
19605 if (!seg
->use_rela_p
)
19608 bfd_vma addend_abs
= abs (value
);
19610 /* Check that the absolute value of the addend is a multiple of
19611 four and, when divided by four, fits in 8 bits. */
19612 if (addend_abs
& 0x3)
19613 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19614 _("bad offset 0x%08lX (must be word-aligned)"),
19615 (unsigned long) addend_abs
);
19617 if ((addend_abs
>> 2) > 0xff)
19618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19619 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
19620 (unsigned long) addend_abs
);
19622 /* Extract the instruction. */
19623 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19625 /* If the addend is negative, clear bit 23 of the instruction.
19626 Otherwise set it. */
19628 insn
&= ~(1 << 23);
19632 /* Place the addend (divided by four) into the first eight
19633 bits of the instruction. */
19634 insn
&= 0xfffffff0;
19635 insn
|= addend_abs
>> 2;
19637 /* Update the instruction. */
19638 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19642 case BFD_RELOC_ARM_V4BX
:
19643 /* This will need to go in the object file. */
19647 case BFD_RELOC_UNUSED
:
19649 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19650 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
19654 /* Translate internal representation of relocation info to BFD target
19658 tc_gen_reloc (asection
*section
, fixS
*fixp
)
19661 bfd_reloc_code_real_type code
;
19663 reloc
= xmalloc (sizeof (arelent
));
19665 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
19666 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
19667 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
19669 if (fixp
->fx_pcrel
)
19671 if (section
->use_rela_p
)
19672 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
19674 fixp
->fx_offset
= reloc
->address
;
19676 reloc
->addend
= fixp
->fx_offset
;
19678 switch (fixp
->fx_r_type
)
19681 if (fixp
->fx_pcrel
)
19683 code
= BFD_RELOC_8_PCREL
;
19688 if (fixp
->fx_pcrel
)
19690 code
= BFD_RELOC_16_PCREL
;
19695 if (fixp
->fx_pcrel
)
19697 code
= BFD_RELOC_32_PCREL
;
19701 case BFD_RELOC_ARM_MOVW
:
19702 if (fixp
->fx_pcrel
)
19704 code
= BFD_RELOC_ARM_MOVW_PCREL
;
19708 case BFD_RELOC_ARM_MOVT
:
19709 if (fixp
->fx_pcrel
)
19711 code
= BFD_RELOC_ARM_MOVT_PCREL
;
19715 case BFD_RELOC_ARM_THUMB_MOVW
:
19716 if (fixp
->fx_pcrel
)
19718 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
19722 case BFD_RELOC_ARM_THUMB_MOVT
:
19723 if (fixp
->fx_pcrel
)
19725 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
19729 case BFD_RELOC_NONE
:
19730 case BFD_RELOC_ARM_PCREL_BRANCH
:
19731 case BFD_RELOC_ARM_PCREL_BLX
:
19732 case BFD_RELOC_RVA
:
19733 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19734 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19735 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19736 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19737 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19738 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19739 case BFD_RELOC_VTABLE_ENTRY
:
19740 case BFD_RELOC_VTABLE_INHERIT
:
19742 case BFD_RELOC_32_SECREL
:
19744 code
= fixp
->fx_r_type
;
19747 case BFD_RELOC_THUMB_PCREL_BLX
:
19749 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
19750 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
19753 code
= BFD_RELOC_THUMB_PCREL_BLX
;
19756 case BFD_RELOC_ARM_LITERAL
:
19757 case BFD_RELOC_ARM_HWLITERAL
:
19758 /* If this is called then the a literal has
19759 been referenced across a section boundary. */
19760 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19761 _("literal referenced across section boundary"));
19765 case BFD_RELOC_ARM_GOT32
:
19766 case BFD_RELOC_ARM_GOTOFF
:
19767 case BFD_RELOC_ARM_PLT32
:
19768 case BFD_RELOC_ARM_TARGET1
:
19769 case BFD_RELOC_ARM_ROSEGREL32
:
19770 case BFD_RELOC_ARM_SBREL32
:
19771 case BFD_RELOC_ARM_PREL31
:
19772 case BFD_RELOC_ARM_TARGET2
:
19773 case BFD_RELOC_ARM_TLS_LE32
:
19774 case BFD_RELOC_ARM_TLS_LDO32
:
19775 case BFD_RELOC_ARM_PCREL_CALL
:
19776 case BFD_RELOC_ARM_PCREL_JUMP
:
19777 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19778 case BFD_RELOC_ARM_ALU_PC_G0
:
19779 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19780 case BFD_RELOC_ARM_ALU_PC_G1
:
19781 case BFD_RELOC_ARM_ALU_PC_G2
:
19782 case BFD_RELOC_ARM_LDR_PC_G0
:
19783 case BFD_RELOC_ARM_LDR_PC_G1
:
19784 case BFD_RELOC_ARM_LDR_PC_G2
:
19785 case BFD_RELOC_ARM_LDRS_PC_G0
:
19786 case BFD_RELOC_ARM_LDRS_PC_G1
:
19787 case BFD_RELOC_ARM_LDRS_PC_G2
:
19788 case BFD_RELOC_ARM_LDC_PC_G0
:
19789 case BFD_RELOC_ARM_LDC_PC_G1
:
19790 case BFD_RELOC_ARM_LDC_PC_G2
:
19791 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19792 case BFD_RELOC_ARM_ALU_SB_G0
:
19793 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19794 case BFD_RELOC_ARM_ALU_SB_G1
:
19795 case BFD_RELOC_ARM_ALU_SB_G2
:
19796 case BFD_RELOC_ARM_LDR_SB_G0
:
19797 case BFD_RELOC_ARM_LDR_SB_G1
:
19798 case BFD_RELOC_ARM_LDR_SB_G2
:
19799 case BFD_RELOC_ARM_LDRS_SB_G0
:
19800 case BFD_RELOC_ARM_LDRS_SB_G1
:
19801 case BFD_RELOC_ARM_LDRS_SB_G2
:
19802 case BFD_RELOC_ARM_LDC_SB_G0
:
19803 case BFD_RELOC_ARM_LDC_SB_G1
:
19804 case BFD_RELOC_ARM_LDC_SB_G2
:
19805 case BFD_RELOC_ARM_V4BX
:
19806 code
= fixp
->fx_r_type
;
19809 case BFD_RELOC_ARM_TLS_GD32
:
19810 case BFD_RELOC_ARM_TLS_IE32
:
19811 case BFD_RELOC_ARM_TLS_LDM32
:
19812 /* BFD will include the symbol's address in the addend.
19813 But we don't want that, so subtract it out again here. */
19814 if (!S_IS_COMMON (fixp
->fx_addsy
))
19815 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
19816 code
= fixp
->fx_r_type
;
19820 case BFD_RELOC_ARM_IMMEDIATE
:
19821 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19822 _("internal relocation (type: IMMEDIATE) not fixed up"));
19825 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19826 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19827 _("ADRL used for a symbol not defined in the same file"));
19830 case BFD_RELOC_ARM_OFFSET_IMM
:
19831 if (section
->use_rela_p
)
19833 code
= fixp
->fx_r_type
;
19837 if (fixp
->fx_addsy
!= NULL
19838 && !S_IS_DEFINED (fixp
->fx_addsy
)
19839 && S_IS_LOCAL (fixp
->fx_addsy
))
19841 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19842 _("undefined local label `%s'"),
19843 S_GET_NAME (fixp
->fx_addsy
));
19847 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19848 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19855 switch (fixp
->fx_r_type
)
19857 case BFD_RELOC_NONE
: type
= "NONE"; break;
19858 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
19859 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
19860 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
19861 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
19862 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
19863 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
19864 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
19865 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
19866 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
19867 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
19868 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
19869 default: type
= _("<unknown>"); break;
19871 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19872 _("cannot represent %s relocation in this object file format"),
19879 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
19881 && fixp
->fx_addsy
== GOT_symbol
)
19883 code
= BFD_RELOC_ARM_GOTPC
;
19884 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
19888 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
19890 if (reloc
->howto
== NULL
)
19892 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19893 _("cannot represent %s relocation in this object file format"),
19894 bfd_get_reloc_code_name (code
));
19898 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19899 vtable entry to be used in the relocation's section offset. */
19900 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19901 reloc
->address
= fixp
->fx_offset
;
19906 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19909 cons_fix_new_arm (fragS
* frag
,
19914 bfd_reloc_code_real_type type
;
19918 FIXME: @@ Should look at CPU word size. */
19922 type
= BFD_RELOC_8
;
19925 type
= BFD_RELOC_16
;
19929 type
= BFD_RELOC_32
;
19932 type
= BFD_RELOC_64
;
19937 if (exp
->X_op
== O_secrel
)
19939 exp
->X_op
= O_symbol
;
19940 type
= BFD_RELOC_32_SECREL
;
19944 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
19947 #if defined (OBJ_COFF)
19949 arm_validate_fix (fixS
* fixP
)
19951 /* If the destination of the branch is a defined symbol which does not have
19952 the THUMB_FUNC attribute, then we must be calling a function which has
19953 the (interfacearm) attribute. We look for the Thumb entry point to that
19954 function and change the branch to refer to that function instead. */
19955 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
19956 && fixP
->fx_addsy
!= NULL
19957 && S_IS_DEFINED (fixP
->fx_addsy
)
19958 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
19960 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
19966 arm_force_relocation (struct fix
* fixp
)
19968 #if defined (OBJ_COFF) && defined (TE_PE)
19969 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
19973 /* Resolve these relocations even if the symbol is extern or weak. */
19974 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
19975 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
19976 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
19977 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
19978 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19979 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
19980 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
19983 /* Always leave these relocations for the linker. */
19984 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19985 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19986 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19989 /* Always generate relocations against function symbols. */
19990 if (fixp
->fx_r_type
== BFD_RELOC_32
19992 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
19995 return generic_force_reloc (fixp
);
19998 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19999 /* Relocations against function names must be left unadjusted,
20000 so that the linker can use this information to generate interworking
20001 stubs. The MIPS version of this function
20002 also prevents relocations that are mips-16 specific, but I do not
20003 know why it does this.
20006 There is one other problem that ought to be addressed here, but
20007 which currently is not: Taking the address of a label (rather
20008 than a function) and then later jumping to that address. Such
20009 addresses also ought to have their bottom bit set (assuming that
20010 they reside in Thumb code), but at the moment they will not. */
20013 arm_fix_adjustable (fixS
* fixP
)
20015 if (fixP
->fx_addsy
== NULL
)
20018 /* Preserve relocations against symbols with function type. */
20019 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
20022 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
20023 && fixP
->fx_subsy
== NULL
)
20026 /* We need the symbol name for the VTABLE entries. */
20027 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
20028 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
20031 /* Don't allow symbols to be discarded on GOT related relocs. */
20032 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
20033 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
20034 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
20035 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
20036 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
20037 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
20038 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
20039 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
20040 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
20043 /* Similarly for group relocations. */
20044 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
20045 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
20046 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
20049 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
20050 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
20051 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20052 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
20053 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
20054 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20055 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
20056 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
20057 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
20062 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
20067 elf32_arm_target_format (void)
20070 return (target_big_endian
20071 ? "elf32-bigarm-symbian"
20072 : "elf32-littlearm-symbian");
20073 #elif defined (TE_VXWORKS)
20074 return (target_big_endian
20075 ? "elf32-bigarm-vxworks"
20076 : "elf32-littlearm-vxworks");
20078 if (target_big_endian
)
20079 return "elf32-bigarm";
20081 return "elf32-littlearm";
20086 armelf_frob_symbol (symbolS
* symp
,
20089 elf_frob_symbol (symp
, puntp
);
20093 /* MD interface: Finalization. */
20095 /* A good place to do this, although this was probably not intended
20096 for this kind of use. We need to dump the literal pool before
20097 references are made to a null symbol pointer. */
20102 literal_pool
* pool
;
20104 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
20106 /* Put it at the end of the relevant section. */
20107 subseg_set (pool
->section
, pool
->sub_section
);
20109 arm_elf_change_section ();
20115 /* Adjust the symbol table. This marks Thumb symbols as distinct from
20119 arm_adjust_symtab (void)
20124 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
20126 if (ARM_IS_THUMB (sym
))
20128 if (THUMB_IS_FUNC (sym
))
20130 /* Mark the symbol as a Thumb function. */
20131 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
20132 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
20133 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
20135 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
20136 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
20138 as_bad (_("%s: unexpected function type: %d"),
20139 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
20141 else switch (S_GET_STORAGE_CLASS (sym
))
20144 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
20147 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
20150 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
20158 if (ARM_IS_INTERWORK (sym
))
20159 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
20166 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
20168 if (ARM_IS_THUMB (sym
))
20170 elf_symbol_type
* elf_sym
;
20172 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
20173 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
20175 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
20176 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
20178 /* If it's a .thumb_func, declare it as so,
20179 otherwise tag label as .code 16. */
20180 if (THUMB_IS_FUNC (sym
))
20181 elf_sym
->internal_elf_sym
.st_info
=
20182 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
20183 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20184 elf_sym
->internal_elf_sym
.st_info
=
20185 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
20192 /* MD interface: Initialization. */
20195 set_constant_flonums (void)
20199 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
20200 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
20204 /* Auto-select Thumb mode if it's the only available instruction set for the
20205 given architecture. */
20208 autoselect_thumb_from_cpu_variant (void)
20210 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
20211 opcode_select (16);
20220 if ( (arm_ops_hsh
= hash_new ()) == NULL
20221 || (arm_cond_hsh
= hash_new ()) == NULL
20222 || (arm_shift_hsh
= hash_new ()) == NULL
20223 || (arm_psr_hsh
= hash_new ()) == NULL
20224 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
20225 || (arm_reg_hsh
= hash_new ()) == NULL
20226 || (arm_reloc_hsh
= hash_new ()) == NULL
20227 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
20228 as_fatal (_("virtual memory exhausted"));
20230 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
20231 hash_insert (arm_ops_hsh
, insns
[i
].template, (void *) (insns
+ i
));
20232 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
20233 hash_insert (arm_cond_hsh
, conds
[i
].template, (void *) (conds
+ i
));
20234 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
20235 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
20236 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
20237 hash_insert (arm_psr_hsh
, psrs
[i
].template, (void *) (psrs
+ i
));
20238 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
20239 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (void *) (v7m_psrs
+ i
));
20240 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
20241 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
20243 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
20245 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
20246 (void *) (barrier_opt_names
+ i
));
20248 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
20249 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
20252 set_constant_flonums ();
20254 /* Set the cpu variant based on the command-line options. We prefer
20255 -mcpu= over -march= if both are set (as for GCC); and we prefer
20256 -mfpu= over any other way of setting the floating point unit.
20257 Use of legacy options with new options are faulted. */
20260 if (mcpu_cpu_opt
|| march_cpu_opt
)
20261 as_bad (_("use of old and new-style options to set CPU type"));
20263 mcpu_cpu_opt
= legacy_cpu
;
20265 else if (!mcpu_cpu_opt
)
20266 mcpu_cpu_opt
= march_cpu_opt
;
20271 as_bad (_("use of old and new-style options to set FPU type"));
20273 mfpu_opt
= legacy_fpu
;
20275 else if (!mfpu_opt
)
20277 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
20278 /* Some environments specify a default FPU. If they don't, infer it
20279 from the processor. */
20281 mfpu_opt
= mcpu_fpu_opt
;
20283 mfpu_opt
= march_fpu_opt
;
20285 mfpu_opt
= &fpu_default
;
20291 if (mcpu_cpu_opt
!= NULL
)
20292 mfpu_opt
= &fpu_default
;
20293 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
20294 mfpu_opt
= &fpu_arch_vfp_v2
;
20296 mfpu_opt
= &fpu_arch_fpa
;
20302 mcpu_cpu_opt
= &cpu_default
;
20303 selected_cpu
= cpu_default
;
20307 selected_cpu
= *mcpu_cpu_opt
;
20309 mcpu_cpu_opt
= &arm_arch_any
;
20312 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20314 autoselect_thumb_from_cpu_variant ();
20316 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
20318 #if defined OBJ_COFF || defined OBJ_ELF
20320 unsigned int flags
= 0;
20322 #if defined OBJ_ELF
20323 flags
= meabi_flags
;
20325 switch (meabi_flags
)
20327 case EF_ARM_EABI_UNKNOWN
:
20329 /* Set the flags in the private structure. */
20330 if (uses_apcs_26
) flags
|= F_APCS26
;
20331 if (support_interwork
) flags
|= F_INTERWORK
;
20332 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
20333 if (pic_code
) flags
|= F_PIC
;
20334 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
20335 flags
|= F_SOFT_FLOAT
;
20337 switch (mfloat_abi_opt
)
20339 case ARM_FLOAT_ABI_SOFT
:
20340 case ARM_FLOAT_ABI_SOFTFP
:
20341 flags
|= F_SOFT_FLOAT
;
20344 case ARM_FLOAT_ABI_HARD
:
20345 if (flags
& F_SOFT_FLOAT
)
20346 as_bad (_("hard-float conflicts with specified fpu"));
20350 /* Using pure-endian doubles (even if soft-float). */
20351 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
20352 flags
|= F_VFP_FLOAT
;
20354 #if defined OBJ_ELF
20355 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
20356 flags
|= EF_ARM_MAVERICK_FLOAT
;
20359 case EF_ARM_EABI_VER4
:
20360 case EF_ARM_EABI_VER5
:
20361 /* No additional flags to set. */
20368 bfd_set_private_flags (stdoutput
, flags
);
20370 /* We have run out flags in the COFF header to encode the
20371 status of ATPCS support, so instead we create a dummy,
20372 empty, debug section called .arm.atpcs. */
20377 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
20381 bfd_set_section_flags
20382 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
20383 bfd_set_section_size (stdoutput
, sec
, 0);
20384 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
20390 /* Record the CPU type as well. */
20391 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
20392 mach
= bfd_mach_arm_iWMMXt2
;
20393 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
20394 mach
= bfd_mach_arm_iWMMXt
;
20395 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
20396 mach
= bfd_mach_arm_XScale
;
20397 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
20398 mach
= bfd_mach_arm_ep9312
;
20399 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
20400 mach
= bfd_mach_arm_5TE
;
20401 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
20403 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
20404 mach
= bfd_mach_arm_5T
;
20406 mach
= bfd_mach_arm_5
;
20408 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
20410 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
20411 mach
= bfd_mach_arm_4T
;
20413 mach
= bfd_mach_arm_4
;
20415 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
20416 mach
= bfd_mach_arm_3M
;
20417 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
20418 mach
= bfd_mach_arm_3
;
20419 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
20420 mach
= bfd_mach_arm_2a
;
20421 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
20422 mach
= bfd_mach_arm_2
;
20424 mach
= bfd_mach_arm_unknown
;
20426 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
20429 /* Command line processing. */
20432 Invocation line includes a switch not recognized by the base assembler.
20433 See if it's a processor-specific option.
20435 This routine is somewhat complicated by the need for backwards
20436 compatibility (since older releases of gcc can't be changed).
20437 The new options try to make the interface as compatible as
20440 New options (supported) are:
20442 -mcpu=<cpu name> Assemble for selected processor
20443 -march=<architecture name> Assemble for selected architecture
20444 -mfpu=<fpu architecture> Assemble for selected FPU.
20445 -EB/-mbig-endian Big-endian
20446 -EL/-mlittle-endian Little-endian
20447 -k Generate PIC code
20448 -mthumb Start in Thumb mode
20449 -mthumb-interwork Code supports ARM/Thumb interworking
20451 -m[no-]warn-deprecated Warn about deprecated features
20453 For now we will also provide support for:
20455 -mapcs-32 32-bit Program counter
20456 -mapcs-26 26-bit Program counter
20457 -macps-float Floats passed in FP registers
20458 -mapcs-reentrant Reentrant code
20460 (sometime these will probably be replaced with -mapcs=<list of options>
20461 and -matpcs=<list of options>)
20463 The remaining options are only supported for back-wards compatibility.
20464 Cpu variants, the arm part is optional:
20465 -m[arm]1 Currently not supported.
20466 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
20467 -m[arm]3 Arm 3 processor
20468 -m[arm]6[xx], Arm 6 processors
20469 -m[arm]7[xx][t][[d]m] Arm 7 processors
20470 -m[arm]8[10] Arm 8 processors
20471 -m[arm]9[20][tdmi] Arm 9 processors
20472 -mstrongarm[110[0]] StrongARM processors
20473 -mxscale XScale processors
20474 -m[arm]v[2345[t[e]]] Arm architectures
20475 -mall All (except the ARM1)
20477 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
20478 -mfpe-old (No float load/store multiples)
20479 -mvfpxd VFP Single precision
20481 -mno-fpu Disable all floating point instructions
20483 The following CPU names are recognized:
20484 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
20485 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
20486 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
20487 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
20488 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
20489 arm10t arm10e, arm1020t, arm1020e, arm10200e,
20490 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
20494 const char * md_shortopts
= "m:k";
20496 #ifdef ARM_BI_ENDIAN
20497 #define OPTION_EB (OPTION_MD_BASE + 0)
20498 #define OPTION_EL (OPTION_MD_BASE + 1)
20500 #if TARGET_BYTES_BIG_ENDIAN
20501 #define OPTION_EB (OPTION_MD_BASE + 0)
20503 #define OPTION_EL (OPTION_MD_BASE + 1)
20506 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
20508 struct option md_longopts
[] =
20511 {"EB", no_argument
, NULL
, OPTION_EB
},
20514 {"EL", no_argument
, NULL
, OPTION_EL
},
20516 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
20517 {NULL
, no_argument
, NULL
, 0}
20520 size_t md_longopts_size
= sizeof (md_longopts
);
20522 struct arm_option_table
20524 char *option
; /* Option name to match. */
20525 char *help
; /* Help information. */
20526 int *var
; /* Variable to change. */
20527 int value
; /* What to change it to. */
20528 char *deprecated
; /* If non-null, print this message. */
20531 struct arm_option_table arm_opts
[] =
20533 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
20534 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
20535 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
20536 &support_interwork
, 1, NULL
},
20537 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
20538 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
20539 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
20541 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
20542 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
20543 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
20544 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
20547 /* These are recognized by the assembler, but have no affect on code. */
20548 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
20549 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
20551 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
20552 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
20553 &warn_on_deprecated
, 0, NULL
},
20554 {NULL
, NULL
, NULL
, 0, NULL
}
20557 struct arm_legacy_option_table
20559 char *option
; /* Option name to match. */
20560 const arm_feature_set
**var
; /* Variable to change. */
20561 const arm_feature_set value
; /* What to change it to. */
20562 char *deprecated
; /* If non-null, print this message. */
20565 const struct arm_legacy_option_table arm_legacy_opts
[] =
20567 /* DON'T add any new processors to this list -- we want the whole list
20568 to go away... Add them to the processors table instead. */
20569 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
20570 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
20571 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
20572 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
20573 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
20574 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
20575 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
20576 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
20577 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
20578 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
20579 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
20580 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
20581 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
20582 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
20583 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
20584 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
20585 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
20586 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
20587 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
20588 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
20589 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
20590 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
20591 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
20592 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
20593 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
20594 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
20595 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
20596 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
20597 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
20598 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
20599 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
20600 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
20601 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
20602 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
20603 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
20604 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
20605 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
20606 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
20607 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
20608 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
20609 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
20610 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
20611 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
20612 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
20613 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
20614 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
20615 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20616 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20617 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20618 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20619 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
20620 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
20621 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
20622 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
20623 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
20624 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
20625 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
20626 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
20627 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
20628 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
20629 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
20630 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
20631 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
20632 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
20633 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
20634 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
20635 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
20636 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
20637 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
20638 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
20639 N_("use -mcpu=strongarm110")},
20640 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
20641 N_("use -mcpu=strongarm1100")},
20642 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
20643 N_("use -mcpu=strongarm1110")},
20644 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
20645 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
20646 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
20648 /* Architecture variants -- don't add any more to this list either. */
20649 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
20650 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
20651 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
20652 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
20653 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
20654 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
20655 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
20656 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
20657 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
20658 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
20659 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20660 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20661 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20662 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20663 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20664 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20665 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20666 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20668 /* Floating point variants -- don't add any more to this list either. */
20669 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
20670 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
20671 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
20672 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
20673 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
20675 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
20678 struct arm_cpu_option_table
20681 const arm_feature_set value
;
20682 /* For some CPUs we assume an FPU unless the user explicitly sets
20684 const arm_feature_set default_fpu
;
20685 /* The canonical name of the CPU, or NULL to use NAME converted to upper
20687 const char *canonical_name
;
20690 /* This list should, at a minimum, contain all the cpu names
20691 recognized by GCC. */
20692 static const struct arm_cpu_option_table arm_cpus
[] =
20694 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
20695 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
20696 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
20697 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20698 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20699 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20700 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20701 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20702 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20703 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20704 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20705 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20706 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20707 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20708 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20709 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20710 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20711 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20712 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20713 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20714 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20715 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20716 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20717 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20718 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20719 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20720 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20721 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20722 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20723 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20724 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20725 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20726 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20727 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20728 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20729 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20730 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20731 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20732 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20733 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
20734 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20735 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20736 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20737 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20738 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20739 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20740 /* For V5 or later processors we default to using VFP; but the user
20741 should really set the FPU type explicitly. */
20742 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20743 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20744 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20745 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20746 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20747 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20748 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
20749 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20750 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20751 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
20752 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20753 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20754 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20755 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20756 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20757 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
20758 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20759 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20760 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20761 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
20762 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20763 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
20764 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20765 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
20766 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
20767 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
20768 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
20769 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
20770 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
20771 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
20772 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
20773 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
20774 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
20775 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20776 | FPU_NEON_EXT_V1
),
20778 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20779 | FPU_NEON_EXT_V1
),
20781 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
20782 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
20783 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
20784 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
20785 /* ??? XSCALE is really an architecture. */
20786 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20787 /* ??? iwmmxt is not a processor. */
20788 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
20789 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
20790 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20792 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
20793 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
20796 struct arm_arch_option_table
20799 const arm_feature_set value
;
20800 const arm_feature_set default_fpu
;
20803 /* This list should, at a minimum, contain all the architecture names
20804 recognized by GCC. */
20805 static const struct arm_arch_option_table arm_archs
[] =
20807 {"all", ARM_ANY
, FPU_ARCH_FPA
},
20808 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
20809 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
20810 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20811 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20812 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
20813 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
20814 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
20815 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
20816 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
20817 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
20818 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
20819 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
20820 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
20821 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
20822 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
20823 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
20824 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20825 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20826 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
20827 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
20828 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
20829 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
20830 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
20831 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
20832 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
20833 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
20834 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
20835 /* The official spelling of the ARMv7 profile variants is the dashed form.
20836 Accept the non-dashed form for compatibility with old toolchains. */
20837 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20838 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20839 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20840 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20841 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20842 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20843 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
20844 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
20845 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
20846 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
20849 /* ISA extensions in the co-processor space. */
20850 struct arm_option_cpu_value_table
20853 const arm_feature_set value
;
20856 static const struct arm_option_cpu_value_table arm_extensions
[] =
20858 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
20859 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
20860 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
20861 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
20862 {NULL
, ARM_ARCH_NONE
}
20865 /* This list should, at a minimum, contain all the fpu names
20866 recognized by GCC. */
20867 static const struct arm_option_cpu_value_table arm_fpus
[] =
20869 {"softfpa", FPU_NONE
},
20870 {"fpe", FPU_ARCH_FPE
},
20871 {"fpe2", FPU_ARCH_FPE
},
20872 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
20873 {"fpa", FPU_ARCH_FPA
},
20874 {"fpa10", FPU_ARCH_FPA
},
20875 {"fpa11", FPU_ARCH_FPA
},
20876 {"arm7500fe", FPU_ARCH_FPA
},
20877 {"softvfp", FPU_ARCH_VFP
},
20878 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
20879 {"vfp", FPU_ARCH_VFP_V2
},
20880 {"vfp9", FPU_ARCH_VFP_V2
},
20881 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
20882 {"vfp10", FPU_ARCH_VFP_V2
},
20883 {"vfp10-r0", FPU_ARCH_VFP_V1
},
20884 {"vfpxd", FPU_ARCH_VFP_V1xD
},
20885 {"vfpv2", FPU_ARCH_VFP_V2
},
20886 {"vfpv3", FPU_ARCH_VFP_V3
},
20887 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
20888 {"arm1020t", FPU_ARCH_VFP_V1
},
20889 {"arm1020e", FPU_ARCH_VFP_V2
},
20890 {"arm1136jfs", FPU_ARCH_VFP_V2
},
20891 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
20892 {"maverick", FPU_ARCH_MAVERICK
},
20893 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
20894 {"neon-fp16", FPU_ARCH_NEON_FP16
},
20895 {NULL
, ARM_ARCH_NONE
}
20898 struct arm_option_value_table
20904 static const struct arm_option_value_table arm_float_abis
[] =
20906 {"hard", ARM_FLOAT_ABI_HARD
},
20907 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
20908 {"soft", ARM_FLOAT_ABI_SOFT
},
20913 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20914 static const struct arm_option_value_table arm_eabis
[] =
20916 {"gnu", EF_ARM_EABI_UNKNOWN
},
20917 {"4", EF_ARM_EABI_VER4
},
20918 {"5", EF_ARM_EABI_VER5
},
20923 struct arm_long_option_table
20925 char * option
; /* Substring to match. */
20926 char * help
; /* Help information. */
20927 int (* func
) (char * subopt
); /* Function to decode sub-option. */
20928 char * deprecated
; /* If non-null, print this message. */
20932 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
20934 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
20936 /* Copy the feature set, so that we can modify it. */
20937 *ext_set
= **opt_p
;
20940 while (str
!= NULL
&& *str
!= 0)
20942 const struct arm_option_cpu_value_table
* opt
;
20948 as_bad (_("invalid architectural extension"));
20953 ext
= strchr (str
, '+');
20956 optlen
= ext
- str
;
20958 optlen
= strlen (str
);
20962 as_bad (_("missing architectural extension"));
20966 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
20967 if (strncmp (opt
->name
, str
, optlen
) == 0)
20969 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
20973 if (opt
->name
== NULL
)
20975 as_bad (_("unknown architectural extension `%s'"), str
);
20986 arm_parse_cpu (char * str
)
20988 const struct arm_cpu_option_table
* opt
;
20989 char * ext
= strchr (str
, '+');
20993 optlen
= ext
- str
;
20995 optlen
= strlen (str
);
20999 as_bad (_("missing cpu name `%s'"), str
);
21003 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
21004 if (strncmp (opt
->name
, str
, optlen
) == 0)
21006 mcpu_cpu_opt
= &opt
->value
;
21007 mcpu_fpu_opt
= &opt
->default_fpu
;
21008 if (opt
->canonical_name
)
21009 strcpy (selected_cpu_name
, opt
->canonical_name
);
21013 for (i
= 0; i
< optlen
; i
++)
21014 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
21015 selected_cpu_name
[i
] = 0;
21019 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
21024 as_bad (_("unknown cpu `%s'"), str
);
21029 arm_parse_arch (char * str
)
21031 const struct arm_arch_option_table
*opt
;
21032 char *ext
= strchr (str
, '+');
21036 optlen
= ext
- str
;
21038 optlen
= strlen (str
);
21042 as_bad (_("missing architecture name `%s'"), str
);
21046 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
21047 if (streq (opt
->name
, str
))
21049 march_cpu_opt
= &opt
->value
;
21050 march_fpu_opt
= &opt
->default_fpu
;
21051 strcpy (selected_cpu_name
, opt
->name
);
21054 return arm_parse_extension (ext
, &march_cpu_opt
);
21059 as_bad (_("unknown architecture `%s'\n"), str
);
21064 arm_parse_fpu (char * str
)
21066 const struct arm_option_cpu_value_table
* opt
;
21068 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
21069 if (streq (opt
->name
, str
))
21071 mfpu_opt
= &opt
->value
;
21075 as_bad (_("unknown floating point format `%s'\n"), str
);
21080 arm_parse_float_abi (char * str
)
21082 const struct arm_option_value_table
* opt
;
21084 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
21085 if (streq (opt
->name
, str
))
21087 mfloat_abi_opt
= opt
->value
;
21091 as_bad (_("unknown floating point abi `%s'\n"), str
);
21097 arm_parse_eabi (char * str
)
21099 const struct arm_option_value_table
*opt
;
21101 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
21102 if (streq (opt
->name
, str
))
21104 meabi_flags
= opt
->value
;
21107 as_bad (_("unknown EABI `%s'\n"), str
);
21112 struct arm_long_option_table arm_long_opts
[] =
21114 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
21115 arm_parse_cpu
, NULL
},
21116 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
21117 arm_parse_arch
, NULL
},
21118 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
21119 arm_parse_fpu
, NULL
},
21120 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
21121 arm_parse_float_abi
, NULL
},
21123 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
21124 arm_parse_eabi
, NULL
},
21126 {NULL
, NULL
, 0, NULL
}
21130 md_parse_option (int c
, char * arg
)
21132 struct arm_option_table
*opt
;
21133 const struct arm_legacy_option_table
*fopt
;
21134 struct arm_long_option_table
*lopt
;
21140 target_big_endian
= 1;
21146 target_big_endian
= 0;
21150 case OPTION_FIX_V4BX
:
21155 /* Listing option. Just ignore these, we don't support additional
21160 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
21162 if (c
== opt
->option
[0]
21163 && ((arg
== NULL
&& opt
->option
[1] == 0)
21164 || streq (arg
, opt
->option
+ 1)))
21166 /* If the option is deprecated, tell the user. */
21167 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
21168 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
21169 arg
? arg
: "", _(opt
->deprecated
));
21171 if (opt
->var
!= NULL
)
21172 *opt
->var
= opt
->value
;
21178 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
21180 if (c
== fopt
->option
[0]
21181 && ((arg
== NULL
&& fopt
->option
[1] == 0)
21182 || streq (arg
, fopt
->option
+ 1)))
21184 /* If the option is deprecated, tell the user. */
21185 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
21186 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
21187 arg
? arg
: "", _(fopt
->deprecated
));
21189 if (fopt
->var
!= NULL
)
21190 *fopt
->var
= &fopt
->value
;
21196 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
21198 /* These options are expected to have an argument. */
21199 if (c
== lopt
->option
[0]
21201 && strncmp (arg
, lopt
->option
+ 1,
21202 strlen (lopt
->option
+ 1)) == 0)
21204 /* If the option is deprecated, tell the user. */
21205 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
21206 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
21207 _(lopt
->deprecated
));
21209 /* Call the sup-option parser. */
21210 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
21221 md_show_usage (FILE * fp
)
21223 struct arm_option_table
*opt
;
21224 struct arm_long_option_table
*lopt
;
21226 fprintf (fp
, _(" ARM-specific assembler options:\n"));
21228 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
21229 if (opt
->help
!= NULL
)
21230 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
21232 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
21233 if (lopt
->help
!= NULL
)
21234 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
21238 -EB assemble code for a big-endian cpu\n"));
21243 -EL assemble code for a little-endian cpu\n"));
21247 --fix-v4bx Allow BX in ARMv4 code\n"));
21255 arm_feature_set flags
;
21256 } cpu_arch_ver_table
;
21258 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
21259 least features first. */
21260 static const cpu_arch_ver_table cpu_arch_ver
[] =
21266 {4, ARM_ARCH_V5TE
},
21267 {5, ARM_ARCH_V5TEJ
},
21271 {11, ARM_ARCH_V6M
},
21272 {8, ARM_ARCH_V6T2
},
21273 {10, ARM_ARCH_V7A
},
21274 {10, ARM_ARCH_V7R
},
21275 {10, ARM_ARCH_V7M
},
21279 /* Set an attribute if it has not already been set by the user. */
21281 aeabi_set_attribute_int (int tag
, int value
)
21284 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
21285 || !attributes_set_explicitly
[tag
])
21286 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
21290 aeabi_set_attribute_string (int tag
, const char *value
)
21293 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
21294 || !attributes_set_explicitly
[tag
])
21295 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
21298 /* Set the public EABI object attributes. */
21300 aeabi_set_public_attributes (void)
21303 arm_feature_set flags
;
21304 arm_feature_set tmp
;
21305 const cpu_arch_ver_table
*p
;
21307 /* Choose the architecture based on the capabilities of the requested cpu
21308 (if any) and/or the instructions actually used. */
21309 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
21310 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
21311 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
21312 /*Allow the user to override the reported architecture. */
21315 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
21316 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
21321 for (p
= cpu_arch_ver
; p
->val
; p
++)
21323 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
21326 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
21330 /* Tag_CPU_name. */
21331 if (selected_cpu_name
[0])
21335 p
= selected_cpu_name
;
21336 if (strncmp (p
, "armv", 4) == 0)
21341 for (i
= 0; p
[i
]; i
++)
21342 p
[i
] = TOUPPER (p
[i
]);
21344 aeabi_set_attribute_string (Tag_CPU_name
, p
);
21346 /* Tag_CPU_arch. */
21347 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
21348 /* Tag_CPU_arch_profile. */
21349 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
21350 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
21351 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
21352 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
21353 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
21354 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
21355 /* Tag_ARM_ISA_use. */
21356 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
21358 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
21359 /* Tag_THUMB_ISA_use. */
21360 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
21362 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
21363 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
21364 /* Tag_VFP_arch. */
21365 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
21366 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
21367 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3
))
21368 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
21369 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
21370 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
21371 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
21372 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
21373 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
21374 /* Tag_WMMX_arch. */
21375 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
21376 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
21377 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
21378 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
21379 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
21380 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
21381 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
21382 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
21383 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_fp16
))
21384 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
21387 /* Add the default contents for the .ARM.attributes section. */
21391 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21394 aeabi_set_public_attributes ();
21396 #endif /* OBJ_ELF */
21399 /* Parse a .cpu directive. */
21402 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
21404 const struct arm_cpu_option_table
*opt
;
21408 name
= input_line_pointer
;
21409 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21410 input_line_pointer
++;
21411 saved_char
= *input_line_pointer
;
21412 *input_line_pointer
= 0;
21414 /* Skip the first "all" entry. */
21415 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
21416 if (streq (opt
->name
, name
))
21418 mcpu_cpu_opt
= &opt
->value
;
21419 selected_cpu
= opt
->value
;
21420 if (opt
->canonical_name
)
21421 strcpy (selected_cpu_name
, opt
->canonical_name
);
21425 for (i
= 0; opt
->name
[i
]; i
++)
21426 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
21427 selected_cpu_name
[i
] = 0;
21429 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21430 *input_line_pointer
= saved_char
;
21431 demand_empty_rest_of_line ();
21434 as_bad (_("unknown cpu `%s'"), name
);
21435 *input_line_pointer
= saved_char
;
21436 ignore_rest_of_line ();
21440 /* Parse a .arch directive. */
21443 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
21445 const struct arm_arch_option_table
*opt
;
21449 name
= input_line_pointer
;
21450 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21451 input_line_pointer
++;
21452 saved_char
= *input_line_pointer
;
21453 *input_line_pointer
= 0;
21455 /* Skip the first "all" entry. */
21456 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
21457 if (streq (opt
->name
, name
))
21459 mcpu_cpu_opt
= &opt
->value
;
21460 selected_cpu
= opt
->value
;
21461 strcpy (selected_cpu_name
, opt
->name
);
21462 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21463 *input_line_pointer
= saved_char
;
21464 demand_empty_rest_of_line ();
21468 as_bad (_("unknown architecture `%s'\n"), name
);
21469 *input_line_pointer
= saved_char
;
21470 ignore_rest_of_line ();
21474 /* Parse a .object_arch directive. */
21477 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
21479 const struct arm_arch_option_table
*opt
;
21483 name
= input_line_pointer
;
21484 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21485 input_line_pointer
++;
21486 saved_char
= *input_line_pointer
;
21487 *input_line_pointer
= 0;
21489 /* Skip the first "all" entry. */
21490 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
21491 if (streq (opt
->name
, name
))
21493 object_arch
= &opt
->value
;
21494 *input_line_pointer
= saved_char
;
21495 demand_empty_rest_of_line ();
21499 as_bad (_("unknown architecture `%s'\n"), name
);
21500 *input_line_pointer
= saved_char
;
21501 ignore_rest_of_line ();
21504 /* Parse a .fpu directive. */
21507 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
21509 const struct arm_option_cpu_value_table
*opt
;
21513 name
= input_line_pointer
;
21514 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21515 input_line_pointer
++;
21516 saved_char
= *input_line_pointer
;
21517 *input_line_pointer
= 0;
21519 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
21520 if (streq (opt
->name
, name
))
21522 mfpu_opt
= &opt
->value
;
21523 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21524 *input_line_pointer
= saved_char
;
21525 demand_empty_rest_of_line ();
21529 as_bad (_("unknown floating point format `%s'\n"), name
);
21530 *input_line_pointer
= saved_char
;
21531 ignore_rest_of_line ();
21534 /* Copy symbol information. */
21537 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
21539 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
21543 /* Given a symbolic attribute NAME, return the proper integer value.
21544 Returns -1 if the attribute is not known. */
21547 arm_convert_symbolic_attribute (const char *name
)
21549 static const struct
21554 attribute_table
[] =
21556 /* When you modify this table you should
21557 also modify the list in doc/c-arm.texi. */
21558 #define T(tag) {#tag, tag}
21559 T (Tag_CPU_raw_name
),
21562 T (Tag_CPU_arch_profile
),
21563 T (Tag_ARM_ISA_use
),
21564 T (Tag_THUMB_ISA_use
),
21567 T (Tag_Advanced_SIMD_arch
),
21568 T (Tag_PCS_config
),
21569 T (Tag_ABI_PCS_R9_use
),
21570 T (Tag_ABI_PCS_RW_data
),
21571 T (Tag_ABI_PCS_RO_data
),
21572 T (Tag_ABI_PCS_GOT_use
),
21573 T (Tag_ABI_PCS_wchar_t
),
21574 T (Tag_ABI_FP_rounding
),
21575 T (Tag_ABI_FP_denormal
),
21576 T (Tag_ABI_FP_exceptions
),
21577 T (Tag_ABI_FP_user_exceptions
),
21578 T (Tag_ABI_FP_number_model
),
21579 T (Tag_ABI_align8_needed
),
21580 T (Tag_ABI_align8_preserved
),
21581 T (Tag_ABI_enum_size
),
21582 T (Tag_ABI_HardFP_use
),
21583 T (Tag_ABI_VFP_args
),
21584 T (Tag_ABI_WMMX_args
),
21585 T (Tag_ABI_optimization_goals
),
21586 T (Tag_ABI_FP_optimization_goals
),
21587 T (Tag_compatibility
),
21588 T (Tag_CPU_unaligned_access
),
21589 T (Tag_VFP_HP_extension
),
21590 T (Tag_ABI_FP_16bit_format
),
21591 T (Tag_nodefaults
),
21592 T (Tag_also_compatible_with
),
21593 T (Tag_conformance
),
21595 T (Tag_Virtualization_use
),
21596 T (Tag_MPextension_use
)
21604 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
21605 if (strcmp (name
, attribute_table
[i
].name
) == 0)
21606 return attribute_table
[i
].tag
;
21610 #endif /* OBJ_ELF */